Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 37
1 12:17:28.048613 lava-dispatcher, installed at version: 2023.10
2 12:17:28.048846 start: 0 validate
3 12:17:28.048984 Start time: 2024-01-31 12:17:28.048976+00:00 (UTC)
4 12:17:28.049126 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:17:28.049257 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:17:28.317092 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:17:28.317824 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:17:28.589717 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:17:28.590493 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:17:28.859228 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:17:28.860047 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:17:29.128699 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:17:29.129462 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:17:29.404698 validate duration: 1.36
16 12:17:29.405931 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:17:29.406481 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:17:29.406988 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:17:29.407602 Not decompressing ramdisk as can be used compressed.
20 12:17:29.408107 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 12:17:29.408490 saving as /var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/ramdisk/initrd.cpio.gz
22 12:17:29.408908 total size: 4665395 (4 MB)
23 12:17:29.414129 progress 0 % (0 MB)
24 12:17:29.422865 progress 5 % (0 MB)
25 12:17:29.428880 progress 10 % (0 MB)
26 12:17:29.433075 progress 15 % (0 MB)
27 12:17:29.436491 progress 20 % (0 MB)
28 12:17:29.439342 progress 25 % (1 MB)
29 12:17:29.442122 progress 30 % (1 MB)
30 12:17:29.444480 progress 35 % (1 MB)
31 12:17:29.446760 progress 40 % (1 MB)
32 12:17:29.449014 progress 45 % (2 MB)
33 12:17:29.450959 progress 50 % (2 MB)
34 12:17:29.452842 progress 55 % (2 MB)
35 12:17:29.454553 progress 60 % (2 MB)
36 12:17:29.456288 progress 65 % (2 MB)
37 12:17:29.457897 progress 70 % (3 MB)
38 12:17:29.459424 progress 75 % (3 MB)
39 12:17:29.461018 progress 80 % (3 MB)
40 12:17:29.462721 progress 85 % (3 MB)
41 12:17:29.464127 progress 90 % (4 MB)
42 12:17:29.465510 progress 95 % (4 MB)
43 12:17:29.466915 progress 100 % (4 MB)
44 12:17:29.467091 4 MB downloaded in 0.06 s (76.44 MB/s)
45 12:17:29.467240 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:17:29.467481 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:17:29.467567 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:17:29.467651 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:17:29.467794 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:17:29.467867 saving as /var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/kernel/Image
52 12:17:29.467928 total size: 51532288 (49 MB)
53 12:17:29.467990 No compression specified
54 12:17:29.469132 progress 0 % (0 MB)
55 12:17:29.482501 progress 5 % (2 MB)
56 12:17:29.496070 progress 10 % (4 MB)
57 12:17:29.509194 progress 15 % (7 MB)
58 12:17:29.522491 progress 20 % (9 MB)
59 12:17:29.535696 progress 25 % (12 MB)
60 12:17:29.548697 progress 30 % (14 MB)
61 12:17:29.562028 progress 35 % (17 MB)
62 12:17:29.575379 progress 40 % (19 MB)
63 12:17:29.588767 progress 45 % (22 MB)
64 12:17:29.602292 progress 50 % (24 MB)
65 12:17:29.615485 progress 55 % (27 MB)
66 12:17:29.628620 progress 60 % (29 MB)
67 12:17:29.641727 progress 65 % (31 MB)
68 12:17:29.654664 progress 70 % (34 MB)
69 12:17:29.668174 progress 75 % (36 MB)
70 12:17:29.681357 progress 80 % (39 MB)
71 12:17:29.694790 progress 85 % (41 MB)
72 12:17:29.708213 progress 90 % (44 MB)
73 12:17:29.721595 progress 95 % (46 MB)
74 12:17:29.734263 progress 100 % (49 MB)
75 12:17:29.734462 49 MB downloaded in 0.27 s (184.39 MB/s)
76 12:17:29.734610 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:17:29.734841 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:17:29.734925 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:17:29.735012 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:17:29.735154 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:17:29.735223 saving as /var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/dtb/mt8192-asurada-spherion-r0.dtb
83 12:17:29.735284 total size: 47278 (0 MB)
84 12:17:29.735343 No compression specified
85 12:17:29.736546 progress 69 % (0 MB)
86 12:17:29.736815 progress 100 % (0 MB)
87 12:17:29.736979 0 MB downloaded in 0.00 s (26.64 MB/s)
88 12:17:29.737101 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:17:29.737391 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:17:29.737475 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:17:29.737555 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:17:29.737667 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 12:17:29.737732 saving as /var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/nfsrootfs/full.rootfs.tar
95 12:17:29.737793 total size: 200813988 (191 MB)
96 12:17:29.737853 Using unxz to decompress xz
97 12:17:29.741911 progress 0 % (0 MB)
98 12:17:30.267198 progress 5 % (9 MB)
99 12:17:30.779090 progress 10 % (19 MB)
100 12:17:31.359778 progress 15 % (28 MB)
101 12:17:31.730006 progress 20 % (38 MB)
102 12:17:32.050451 progress 25 % (47 MB)
103 12:17:32.634613 progress 30 % (57 MB)
104 12:17:33.178696 progress 35 % (67 MB)
105 12:17:33.767644 progress 40 % (76 MB)
106 12:17:34.320280 progress 45 % (86 MB)
107 12:17:34.900766 progress 50 % (95 MB)
108 12:17:35.520881 progress 55 % (105 MB)
109 12:17:36.176851 progress 60 % (114 MB)
110 12:17:36.292871 progress 65 % (124 MB)
111 12:17:36.430708 progress 70 % (134 MB)
112 12:17:36.525977 progress 75 % (143 MB)
113 12:17:36.596014 progress 80 % (153 MB)
114 12:17:36.663951 progress 85 % (162 MB)
115 12:17:36.764217 progress 90 % (172 MB)
116 12:17:37.038674 progress 95 % (181 MB)
117 12:17:37.608724 progress 100 % (191 MB)
118 12:17:37.613950 191 MB downloaded in 7.88 s (24.32 MB/s)
119 12:17:37.614209 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:17:37.614467 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:17:37.614557 start: 1.5 download-retry (timeout 00:09:52) [common]
123 12:17:37.614643 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 12:17:37.614801 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:17:37.614873 saving as /var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/modules/modules.tar
126 12:17:37.614935 total size: 8639916 (8 MB)
127 12:17:37.614998 Using unxz to decompress xz
128 12:17:37.619221 progress 0 % (0 MB)
129 12:17:37.639882 progress 5 % (0 MB)
130 12:17:37.662983 progress 10 % (0 MB)
131 12:17:37.686404 progress 15 % (1 MB)
132 12:17:37.709793 progress 20 % (1 MB)
133 12:17:37.733837 progress 25 % (2 MB)
134 12:17:37.761286 progress 30 % (2 MB)
135 12:17:37.785684 progress 35 % (2 MB)
136 12:17:37.809183 progress 40 % (3 MB)
137 12:17:37.840051 progress 45 % (3 MB)
138 12:17:37.865115 progress 50 % (4 MB)
139 12:17:37.891218 progress 55 % (4 MB)
140 12:17:37.916036 progress 60 % (4 MB)
141 12:17:37.941679 progress 65 % (5 MB)
142 12:17:37.966741 progress 70 % (5 MB)
143 12:17:37.990243 progress 75 % (6 MB)
144 12:17:38.017402 progress 80 % (6 MB)
145 12:17:38.044965 progress 85 % (7 MB)
146 12:17:38.069932 progress 90 % (7 MB)
147 12:17:38.099717 progress 95 % (7 MB)
148 12:17:38.127403 progress 100 % (8 MB)
149 12:17:38.133294 8 MB downloaded in 0.52 s (15.90 MB/s)
150 12:17:38.133564 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:17:38.133825 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:17:38.133919 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:17:38.134016 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:17:41.579893 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12669567/extract-nfsrootfs-2wdmky1e
156 12:17:41.580091 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 12:17:41.580196 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 12:17:41.580362 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc
159 12:17:41.580495 makedir: /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin
160 12:17:41.580597 makedir: /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/tests
161 12:17:41.580695 makedir: /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/results
162 12:17:41.580796 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-add-keys
163 12:17:41.580943 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-add-sources
164 12:17:41.581117 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-background-process-start
165 12:17:41.581288 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-background-process-stop
166 12:17:41.581415 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-common-functions
167 12:17:41.581542 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-echo-ipv4
168 12:17:41.581669 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-install-packages
169 12:17:41.581794 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-installed-packages
170 12:17:41.581918 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-os-build
171 12:17:41.582043 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-probe-channel
172 12:17:41.582169 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-probe-ip
173 12:17:41.582293 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-target-ip
174 12:17:41.582419 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-target-mac
175 12:17:41.582544 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-target-storage
176 12:17:41.582671 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-test-case
177 12:17:41.582798 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-test-event
178 12:17:41.582923 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-test-feedback
179 12:17:41.583048 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-test-raise
180 12:17:41.583173 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-test-reference
181 12:17:41.583299 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-test-runner
182 12:17:41.583424 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-test-set
183 12:17:41.583548 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-test-shell
184 12:17:41.583858 Updating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-add-keys (debian)
185 12:17:41.584017 Updating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-add-sources (debian)
186 12:17:41.584158 Updating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-install-packages (debian)
187 12:17:41.584298 Updating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-installed-packages (debian)
188 12:17:41.584437 Updating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/bin/lava-os-build (debian)
189 12:17:41.584558 Creating /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/environment
190 12:17:41.584655 LAVA metadata
191 12:17:41.584725 - LAVA_JOB_ID=12669567
192 12:17:41.584788 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:17:41.584893 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 12:17:41.584960 skipped lava-vland-overlay
195 12:17:41.585033 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:17:41.585110 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 12:17:41.585169 skipped lava-multinode-overlay
198 12:17:41.585252 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:17:41.585330 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 12:17:41.585402 Loading test definitions
201 12:17:41.585491 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 12:17:41.585561 Using /lava-12669567 at stage 0
203 12:17:41.585844 uuid=12669567_1.6.2.3.1 testdef=None
204 12:17:41.585931 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:17:41.586015 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 12:17:41.586466 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:17:41.586682 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 12:17:41.587234 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:17:41.587461 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 12:17:41.588059 runner path: /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/0/tests/0_timesync-off test_uuid 12669567_1.6.2.3.1
213 12:17:41.588212 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:17:41.588434 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 12:17:41.588505 Using /lava-12669567 at stage 0
217 12:17:41.588598 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:17:41.588675 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/0/tests/1_kselftest-dt'
219 12:17:46.509292 Running '/usr/bin/git checkout kernelci.org
220 12:17:46.657462 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 12:17:46.658210 uuid=12669567_1.6.2.3.5 testdef=None
222 12:17:46.658375 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 12:17:46.658627 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 12:17:46.659405 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:17:46.659635 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 12:17:46.660629 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:17:46.660862 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 12:17:46.661801 runner path: /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/0/tests/1_kselftest-dt test_uuid 12669567_1.6.2.3.5
232 12:17:46.661895 BOARD='mt8192-asurada-spherion-r0'
233 12:17:46.661959 BRANCH='cip-gitlab'
234 12:17:46.662018 SKIPFILE='/dev/null'
235 12:17:46.662075 SKIP_INSTALL='True'
236 12:17:46.662131 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:17:46.662190 TST_CASENAME=''
238 12:17:46.662245 TST_CMDFILES='dt'
239 12:17:46.662383 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:17:46.662587 Creating lava-test-runner.conf files
242 12:17:46.662651 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12669567/lava-overlay-ztwfjkdc/lava-12669567/0 for stage 0
243 12:17:46.662745 - 0_timesync-off
244 12:17:46.662815 - 1_kselftest-dt
245 12:17:46.662916 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 12:17:46.663005 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 12:17:54.109387 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 12:17:54.109539 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 12:17:54.109641 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:17:54.109741 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 12:17:54.109833 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 12:17:54.230323 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:17:54.230749 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 12:17:54.230889 extracting modules file /var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669567/extract-nfsrootfs-2wdmky1e
255 12:17:54.462767 extracting modules file /var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669567/extract-overlay-ramdisk-1eq7jjeb/ramdisk
256 12:17:54.698685 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:17:54.698840 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 12:17:54.698955 [common] Applying overlay to NFS
259 12:17:54.699031 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669567/compress-overlay-wkajb8us/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12669567/extract-nfsrootfs-2wdmky1e
260 12:17:55.632174 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:17:55.632330 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 12:17:55.632429 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:17:55.632522 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 12:17:55.632605 Building ramdisk /var/lib/lava/dispatcher/tmp/12669567/extract-overlay-ramdisk-1eq7jjeb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12669567/extract-overlay-ramdisk-1eq7jjeb/ramdisk
265 12:17:55.971731 >> 119414 blocks
266 12:17:57.994617 rename /var/lib/lava/dispatcher/tmp/12669567/extract-overlay-ramdisk-1eq7jjeb/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/ramdisk/ramdisk.cpio.gz
267 12:17:57.995241 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:17:57.995447 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 12:17:57.995627 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 12:17:57.995854 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/kernel/Image'
271 12:18:10.287485 Returned 0 in 12 seconds
272 12:18:10.388446 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/kernel/image.itb
273 12:18:10.764801 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:18:10.765192 output: Created: Wed Jan 31 12:18:10 2024
275 12:18:10.765271 output: Image 0 (kernel-1)
276 12:18:10.765334 output: Description:
277 12:18:10.765396 output: Created: Wed Jan 31 12:18:10 2024
278 12:18:10.765462 output: Type: Kernel Image
279 12:18:10.765523 output: Compression: lzma compressed
280 12:18:10.765582 output: Data Size: 12047284 Bytes = 11764.93 KiB = 11.49 MiB
281 12:18:10.765638 output: Architecture: AArch64
282 12:18:10.765695 output: OS: Linux
283 12:18:10.765749 output: Load Address: 0x00000000
284 12:18:10.765803 output: Entry Point: 0x00000000
285 12:18:10.765879 output: Hash algo: crc32
286 12:18:10.765937 output: Hash value: 5a47eb78
287 12:18:10.765993 output: Image 1 (fdt-1)
288 12:18:10.766047 output: Description: mt8192-asurada-spherion-r0
289 12:18:10.766100 output: Created: Wed Jan 31 12:18:10 2024
290 12:18:10.766152 output: Type: Flat Device Tree
291 12:18:10.766205 output: Compression: uncompressed
292 12:18:10.766256 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 12:18:10.766338 output: Architecture: AArch64
294 12:18:10.766436 output: Hash algo: crc32
295 12:18:10.766501 output: Hash value: cc4352de
296 12:18:10.766553 output: Image 2 (ramdisk-1)
297 12:18:10.766604 output: Description: unavailable
298 12:18:10.766671 output: Created: Wed Jan 31 12:18:10 2024
299 12:18:10.766736 output: Type: RAMDisk Image
300 12:18:10.766788 output: Compression: Unknown Compression
301 12:18:10.766839 output: Data Size: 17803429 Bytes = 17386.16 KiB = 16.98 MiB
302 12:18:10.766891 output: Architecture: AArch64
303 12:18:10.766943 output: OS: Linux
304 12:18:10.766995 output: Load Address: unavailable
305 12:18:10.767046 output: Entry Point: unavailable
306 12:18:10.767098 output: Hash algo: crc32
307 12:18:10.767149 output: Hash value: dfcc05ba
308 12:18:10.767244 output: Default Configuration: 'conf-1'
309 12:18:10.767296 output: Configuration 0 (conf-1)
310 12:18:10.767347 output: Description: mt8192-asurada-spherion-r0
311 12:18:10.767399 output: Kernel: kernel-1
312 12:18:10.767451 output: Init Ramdisk: ramdisk-1
313 12:18:10.767502 output: FDT: fdt-1
314 12:18:10.767554 output: Loadables: kernel-1
315 12:18:10.767605 output:
316 12:18:10.767861 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 12:18:10.767962 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 12:18:10.768068 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 12:18:10.768165 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 12:18:10.768241 No LXC device requested
321 12:18:10.768319 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:18:10.768402 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 12:18:10.768476 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:18:10.768547 Checking files for TFTP limit of 4294967296 bytes.
325 12:18:10.769045 end: 1 tftp-deploy (duration 00:00:41) [common]
326 12:18:10.769148 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:18:10.769240 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:18:10.769364 substitutions:
329 12:18:10.769429 - {DTB}: 12669567/tftp-deploy-ox3fcnsu/dtb/mt8192-asurada-spherion-r0.dtb
330 12:18:10.769494 - {INITRD}: 12669567/tftp-deploy-ox3fcnsu/ramdisk/ramdisk.cpio.gz
331 12:18:10.769552 - {KERNEL}: 12669567/tftp-deploy-ox3fcnsu/kernel/Image
332 12:18:10.769609 - {LAVA_MAC}: None
333 12:18:10.769664 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12669567/extract-nfsrootfs-2wdmky1e
334 12:18:10.769719 - {NFS_SERVER_IP}: 192.168.201.1
335 12:18:10.769775 - {PRESEED_CONFIG}: None
336 12:18:10.769829 - {PRESEED_LOCAL}: None
337 12:18:10.769883 - {RAMDISK}: 12669567/tftp-deploy-ox3fcnsu/ramdisk/ramdisk.cpio.gz
338 12:18:10.769937 - {ROOT_PART}: None
339 12:18:10.769991 - {ROOT}: None
340 12:18:10.770045 - {SERVER_IP}: 192.168.201.1
341 12:18:10.770098 - {TEE}: None
342 12:18:10.770151 Parsed boot commands:
343 12:18:10.770229 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:18:10.770429 Parsed boot commands: tftpboot 192.168.201.1 12669567/tftp-deploy-ox3fcnsu/kernel/image.itb 12669567/tftp-deploy-ox3fcnsu/kernel/cmdline
345 12:18:10.770517 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:18:10.770599 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:18:10.770690 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:18:10.770778 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:18:10.770854 Not connected, no need to disconnect.
350 12:18:10.770927 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:18:10.771009 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:18:10.771076 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 12:18:10.775107 Setting prompt string to ['lava-test: # ']
354 12:18:10.775476 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:18:10.775577 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:18:10.775681 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:18:10.775821 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:18:10.776056 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 12:18:15.907075 >> Command sent successfully.
360 12:18:15.918580 Returned 0 in 5 seconds
361 12:18:16.019881 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:18:16.021416 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:18:16.021982 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:18:16.022477 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:18:16.022863 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:18:16.023250 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:18:16.024615 [Enter `^Ec?' for help]
369 12:18:16.184526
370 12:18:16.185117
371 12:18:16.185514 F0: 102B 0000
372 12:18:16.185887
373 12:18:16.186226 F3: 1001 0000 [0200]
374 12:18:16.186557
375 12:18:16.187962 F3: 1001 0000
376 12:18:16.188485
377 12:18:16.188888 F7: 102D 0000
378 12:18:16.189211
379 12:18:16.189516 F1: 0000 0000
380 12:18:16.189814
381 12:18:16.191265 V0: 0000 0000 [0001]
382 12:18:16.191730
383 12:18:16.192085 00: 0007 8000
384 12:18:16.192424
385 12:18:16.194672 01: 0000 0000
386 12:18:16.195138
387 12:18:16.195474 BP: 0C00 0209 [0000]
388 12:18:16.195835
389 12:18:16.198575 G0: 1182 0000
390 12:18:16.198999
391 12:18:16.199373 EC: 0000 0021 [4000]
392 12:18:16.199743
393 12:18:16.202138 S7: 0000 0000 [0000]
394 12:18:16.202564
395 12:18:16.202901 CC: 0000 0000 [0001]
396 12:18:16.203215
397 12:18:16.206179 T0: 0000 0040 [010F]
398 12:18:16.206610
399 12:18:16.207012 Jump to BL
400 12:18:16.207367
401 12:18:16.230904
402 12:18:16.231462
403 12:18:16.231843
404 12:18:16.237589 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:18:16.241135 ARM64: Exception handlers installed.
406 12:18:16.244171 ARM64: Testing exception
407 12:18:16.247810 ARM64: Done test exception
408 12:18:16.254911 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:18:16.265737 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:18:16.272852 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:18:16.284061 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:18:16.291043 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:18:16.297589 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:18:16.307223 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:18:16.313956 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:18:16.334140 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:18:16.337044 WDT: Last reset was cold boot
418 12:18:16.340608 SPI1(PAD0) initialized at 2873684 Hz
419 12:18:16.344023 SPI5(PAD0) initialized at 992727 Hz
420 12:18:16.346836 VBOOT: Loading verstage.
421 12:18:16.353433 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:18:16.356622 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:18:16.360373 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:18:16.363731 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:18:16.371561 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:18:16.378584 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:18:16.389269 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 12:18:16.389844
429 12:18:16.390421
430 12:18:16.398879 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:18:16.401823 ARM64: Exception handlers installed.
432 12:18:16.405804 ARM64: Testing exception
433 12:18:16.408517 ARM64: Done test exception
434 12:18:16.411485 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:18:16.415321 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:18:16.429831 Probing TPM: . done!
437 12:18:16.430396 TPM ready after 0 ms
438 12:18:16.436552 Connected to device vid:did:rid of 1ae0:0028:00
439 12:18:16.446060 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 12:18:16.488136 Initialized TPM device CR50 revision 0
441 12:18:16.499398 tlcl_send_startup: Startup return code is 0
442 12:18:16.500030 TPM: setup succeeded
443 12:18:16.510872 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:18:16.518769 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:18:16.529532 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:18:16.537770 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:18:16.541148 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:18:16.544984 in-header: 03 07 00 00 08 00 00 00
449 12:18:16.548034 in-data: aa e4 47 04 13 02 00 00
450 12:18:16.551267 Chrome EC: UHEPI supported
451 12:18:16.558040 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:18:16.560859 in-header: 03 ad 00 00 08 00 00 00
453 12:18:16.564829 in-data: 00 20 20 08 00 00 00 00
454 12:18:16.565400 Phase 1
455 12:18:16.568027 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:18:16.574260 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:18:16.581591 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:18:16.584024 Recovery requested (1009000e)
459 12:18:16.592555 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:18:16.596888 tlcl_extend: response is 0
461 12:18:16.605090 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:18:16.610291 tlcl_extend: response is 0
463 12:18:16.617338 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:18:16.637381 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 12:18:16.644337 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:18:16.644898
467 12:18:16.645467
468 12:18:16.655342 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:18:16.657876 ARM64: Exception handlers installed.
470 12:18:16.658417 ARM64: Testing exception
471 12:18:16.660834 ARM64: Done test exception
472 12:18:16.683574 pmic_efuse_setting: Set efuses in 11 msecs
473 12:18:16.686622 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:18:16.690703 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:18:16.696744 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:18:16.701027 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:18:16.707052 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:18:16.710502 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:18:16.716946 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:18:16.720441 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:18:16.726806 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:18:16.730185 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:18:16.734152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:18:16.740759 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:18:16.743465 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:18:16.747395 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:18:16.754038 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:18:16.760584 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:18:16.767610 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:18:16.770482 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:18:16.777143 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:18:16.784040 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:18:16.790284 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:18:16.794343 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:18:16.801183 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:18:16.804634 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:18:16.812430 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:18:16.814799 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:18:16.821687 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:18:16.829110 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:18:16.832457 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:18:16.835964 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:18:16.842234 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:18:16.845955 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:18:16.852843 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:18:16.855756 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:18:16.862403 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:18:16.866085 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:18:16.873783 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:18:16.875776 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:18:16.883346 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:18:16.886402 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:18:16.890400 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:18:16.894363 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:18:16.897712 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:18:16.904230 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:18:16.907719 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:18:16.910666 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:18:16.917659 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:18:16.920715 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:18:16.924017 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:18:16.930494 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:18:16.934313 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:18:16.937540 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:18:16.944394 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:18:16.955176 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:18:16.957301 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:18:16.967530 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:18:16.975110 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:18:16.980285 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:18:16.984614 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:18:16.987169 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:18:16.995466 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x1e
534 12:18:17.002106 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:18:17.005301 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 12:18:17.012219 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:18:17.020242 [RTC]rtc_get_frequency_meter,154: input=15, output=835
538 12:18:17.029713 [RTC]rtc_get_frequency_meter,154: input=7, output=708
539 12:18:17.039456 [RTC]rtc_get_frequency_meter,154: input=11, output=772
540 12:18:17.048408 [RTC]rtc_get_frequency_meter,154: input=13, output=804
541 12:18:17.058398 [RTC]rtc_get_frequency_meter,154: input=12, output=788
542 12:18:17.068140 [RTC]rtc_get_frequency_meter,154: input=12, output=787
543 12:18:17.076611 [RTC]rtc_get_frequency_meter,154: input=13, output=803
544 12:18:17.080271 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 12:18:17.088067 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 12:18:17.090734 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 12:18:17.094733 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 12:18:17.100792 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 12:18:17.104126 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 12:18:17.107582 ADC[4]: Raw value=905988 ID=7
551 12:18:17.108211 ADC[3]: Raw value=212912 ID=1
552 12:18:17.110491 RAM Code: 0x71
553 12:18:17.114099 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 12:18:17.120503 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 12:18:17.127517 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 12:18:17.134248 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 12:18:17.136894 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 12:18:17.140253 in-header: 03 07 00 00 08 00 00 00
559 12:18:17.144013 in-data: aa e4 47 04 13 02 00 00
560 12:18:17.146904 Chrome EC: UHEPI supported
561 12:18:17.153720 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 12:18:17.156753 in-header: 03 dd 00 00 08 00 00 00
563 12:18:17.160624 in-data: 90 20 60 08 00 00 00 00
564 12:18:17.163276 MRC: failed to locate region type 0.
565 12:18:17.170389 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 12:18:17.173574 DRAM-K: Running full calibration
567 12:18:17.180609 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 12:18:17.181196 header.status = 0x0
569 12:18:17.183545 header.version = 0x6 (expected: 0x6)
570 12:18:17.186539 header.size = 0xd00 (expected: 0xd00)
571 12:18:17.190639 header.flags = 0x0
572 12:18:17.196423 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 12:18:17.213529 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 12:18:17.220496 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 12:18:17.224250 dram_init: ddr_geometry: 2
576 12:18:17.226970 [EMI] MDL number = 2
577 12:18:17.227543 [EMI] Get MDL freq = 0
578 12:18:17.229946 dram_init: ddr_type: 0
579 12:18:17.230418 is_discrete_lpddr4: 1
580 12:18:17.234041 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 12:18:17.234618
582 12:18:17.234998
583 12:18:17.236738 [Bian_co] ETT version 0.0.0.1
584 12:18:17.243522 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 12:18:17.244029
586 12:18:17.246756 dramc_set_vcore_voltage set vcore to 650000
587 12:18:17.250058 Read voltage for 800, 4
588 12:18:17.250631 Vio18 = 0
589 12:18:17.251017 Vcore = 650000
590 12:18:17.253621 Vdram = 0
591 12:18:17.254215 Vddq = 0
592 12:18:17.254598 Vmddr = 0
593 12:18:17.256468 dram_init: config_dvfs: 1
594 12:18:17.259820 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 12:18:17.266602 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 12:18:17.269687 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 12:18:17.273786 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 12:18:17.276453 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 12:18:17.282846 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 12:18:17.283323 MEM_TYPE=3, freq_sel=18
601 12:18:17.286220 sv_algorithm_assistance_LP4_1600
602 12:18:17.289901 ============ PULL DRAM RESETB DOWN ============
603 12:18:17.296295 ========== PULL DRAM RESETB DOWN end =========
604 12:18:17.299821 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 12:18:17.302865 ===================================
606 12:18:17.306485 LPDDR4 DRAM CONFIGURATION
607 12:18:17.310709 ===================================
608 12:18:17.311311 EX_ROW_EN[0] = 0x0
609 12:18:17.312555 EX_ROW_EN[1] = 0x0
610 12:18:17.313030 LP4Y_EN = 0x0
611 12:18:17.316207 WORK_FSP = 0x0
612 12:18:17.316685 WL = 0x2
613 12:18:17.319183 RL = 0x2
614 12:18:17.323937 BL = 0x2
615 12:18:17.324503 RPST = 0x0
616 12:18:17.326490 RD_PRE = 0x0
617 12:18:17.326962 WR_PRE = 0x1
618 12:18:17.329261 WR_PST = 0x0
619 12:18:17.329736 DBI_WR = 0x0
620 12:18:17.332979 DBI_RD = 0x0
621 12:18:17.333548 OTF = 0x1
622 12:18:17.335831 ===================================
623 12:18:17.339089 ===================================
624 12:18:17.343119 ANA top config
625 12:18:17.346267 ===================================
626 12:18:17.346838 DLL_ASYNC_EN = 0
627 12:18:17.348888 ALL_SLAVE_EN = 1
628 12:18:17.352710 NEW_RANK_MODE = 1
629 12:18:17.355999 DLL_IDLE_MODE = 1
630 12:18:17.356567 LP45_APHY_COMB_EN = 1
631 12:18:17.359365 TX_ODT_DIS = 1
632 12:18:17.362451 NEW_8X_MODE = 1
633 12:18:17.365564 ===================================
634 12:18:17.369205 ===================================
635 12:18:17.371999 data_rate = 1600
636 12:18:17.375731 CKR = 1
637 12:18:17.379258 DQ_P2S_RATIO = 8
638 12:18:17.382318 ===================================
639 12:18:17.385115 CA_P2S_RATIO = 8
640 12:18:17.385683 DQ_CA_OPEN = 0
641 12:18:17.388272 DQ_SEMI_OPEN = 0
642 12:18:17.391527 CA_SEMI_OPEN = 0
643 12:18:17.394953 CA_FULL_RATE = 0
644 12:18:17.398275 DQ_CKDIV4_EN = 1
645 12:18:17.401992 CA_CKDIV4_EN = 1
646 12:18:17.402561 CA_PREDIV_EN = 0
647 12:18:17.405094 PH8_DLY = 0
648 12:18:17.408685 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 12:18:17.411367 DQ_AAMCK_DIV = 4
650 12:18:17.415663 CA_AAMCK_DIV = 4
651 12:18:17.418814 CA_ADMCK_DIV = 4
652 12:18:17.419384 DQ_TRACK_CA_EN = 0
653 12:18:17.421560 CA_PICK = 800
654 12:18:17.424847 CA_MCKIO = 800
655 12:18:17.428030 MCKIO_SEMI = 0
656 12:18:17.431626 PLL_FREQ = 3068
657 12:18:17.434445 DQ_UI_PI_RATIO = 32
658 12:18:17.438133 CA_UI_PI_RATIO = 0
659 12:18:17.441464 ===================================
660 12:18:17.444546 ===================================
661 12:18:17.445112 memory_type:LPDDR4
662 12:18:17.448244 GP_NUM : 10
663 12:18:17.452063 SRAM_EN : 1
664 12:18:17.452634 MD32_EN : 0
665 12:18:17.455079 ===================================
666 12:18:17.457705 [ANA_INIT] >>>>>>>>>>>>>>
667 12:18:17.461757 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 12:18:17.464504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 12:18:17.468540 ===================================
670 12:18:17.471156 data_rate = 1600,PCW = 0X7600
671 12:18:17.474364 ===================================
672 12:18:17.477836 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 12:18:17.480667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 12:18:17.488134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 12:18:17.491278 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 12:18:17.494322 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 12:18:17.497789 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 12:18:17.500671 [ANA_INIT] flow start
679 12:18:17.504079 [ANA_INIT] PLL >>>>>>>>
680 12:18:17.504652 [ANA_INIT] PLL <<<<<<<<
681 12:18:17.507650 [ANA_INIT] MIDPI >>>>>>>>
682 12:18:17.511520 [ANA_INIT] MIDPI <<<<<<<<
683 12:18:17.514331 [ANA_INIT] DLL >>>>>>>>
684 12:18:17.514909 [ANA_INIT] flow end
685 12:18:17.517561 ============ LP4 DIFF to SE enter ============
686 12:18:17.524588 ============ LP4 DIFF to SE exit ============
687 12:18:17.525096 [ANA_INIT] <<<<<<<<<<<<<
688 12:18:17.527313 [Flow] Enable top DCM control >>>>>
689 12:18:17.531360 [Flow] Enable top DCM control <<<<<
690 12:18:17.534341 Enable DLL master slave shuffle
691 12:18:17.541095 ==============================================================
692 12:18:17.541663 Gating Mode config
693 12:18:17.547928 ==============================================================
694 12:18:17.550837 Config description:
695 12:18:17.560639 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 12:18:17.567538 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 12:18:17.570902 SELPH_MODE 0: By rank 1: By Phase
698 12:18:17.577388 ==============================================================
699 12:18:17.580135 GAT_TRACK_EN = 1
700 12:18:17.580626 RX_GATING_MODE = 2
701 12:18:17.583450 RX_GATING_TRACK_MODE = 2
702 12:18:17.586976 SELPH_MODE = 1
703 12:18:17.590541 PICG_EARLY_EN = 1
704 12:18:17.593522 VALID_LAT_VALUE = 1
705 12:18:17.600261 ==============================================================
706 12:18:17.604614 Enter into Gating configuration >>>>
707 12:18:17.607559 Exit from Gating configuration <<<<
708 12:18:17.610772 Enter into DVFS_PRE_config >>>>>
709 12:18:17.619998 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 12:18:17.623451 Exit from DVFS_PRE_config <<<<<
711 12:18:17.626537 Enter into PICG configuration >>>>
712 12:18:17.630565 Exit from PICG configuration <<<<
713 12:18:17.633771 [RX_INPUT] configuration >>>>>
714 12:18:17.636181 [RX_INPUT] configuration <<<<<
715 12:18:17.640053 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 12:18:17.646899 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 12:18:17.650211 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 12:18:17.658298 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 12:18:17.665385 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 12:18:17.669749 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 12:18:17.676387 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 12:18:17.680270 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 12:18:17.684570 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 12:18:17.687385 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 12:18:17.691037 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 12:18:17.694956 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 12:18:17.698212 ===================================
728 12:18:17.701600 LPDDR4 DRAM CONFIGURATION
729 12:18:17.705708 ===================================
730 12:18:17.706271 EX_ROW_EN[0] = 0x0
731 12:18:17.709085 EX_ROW_EN[1] = 0x0
732 12:18:17.709558 LP4Y_EN = 0x0
733 12:18:17.712704 WORK_FSP = 0x0
734 12:18:17.713132 WL = 0x2
735 12:18:17.716297 RL = 0x2
736 12:18:17.716747 BL = 0x2
737 12:18:17.720091 RPST = 0x0
738 12:18:17.720572 RD_PRE = 0x0
739 12:18:17.723814 WR_PRE = 0x1
740 12:18:17.724264 WR_PST = 0x0
741 12:18:17.724613 DBI_WR = 0x0
742 12:18:17.727389 DBI_RD = 0x0
743 12:18:17.727864 OTF = 0x1
744 12:18:17.731470 ===================================
745 12:18:17.735591 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 12:18:17.738924 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 12:18:17.745838 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 12:18:17.749957 ===================================
749 12:18:17.750388 LPDDR4 DRAM CONFIGURATION
750 12:18:17.753377 ===================================
751 12:18:17.758179 EX_ROW_EN[0] = 0x10
752 12:18:17.758609 EX_ROW_EN[1] = 0x0
753 12:18:17.761629 LP4Y_EN = 0x0
754 12:18:17.762051 WORK_FSP = 0x0
755 12:18:17.764349 WL = 0x2
756 12:18:17.764877 RL = 0x2
757 12:18:17.768162 BL = 0x2
758 12:18:17.768646 RPST = 0x0
759 12:18:17.771972 RD_PRE = 0x0
760 12:18:17.772509 WR_PRE = 0x1
761 12:18:17.772858 WR_PST = 0x0
762 12:18:17.776185 DBI_WR = 0x0
763 12:18:17.776728 DBI_RD = 0x0
764 12:18:17.779458 OTF = 0x1
765 12:18:17.783030 ===================================
766 12:18:17.786491 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 12:18:17.792096 nWR fixed to 40
768 12:18:17.795129 [ModeRegInit_LP4] CH0 RK0
769 12:18:17.795554 [ModeRegInit_LP4] CH0 RK1
770 12:18:17.798919 [ModeRegInit_LP4] CH1 RK0
771 12:18:17.802287 [ModeRegInit_LP4] CH1 RK1
772 12:18:17.802714 match AC timing 13
773 12:18:17.806142 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 12:18:17.809731 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 12:18:17.816128 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 12:18:17.819420 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 12:18:17.826741 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 12:18:17.827169 [EMI DOE] emi_dcm 0
779 12:18:17.829425 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 12:18:17.833038 ==
781 12:18:17.833465 Dram Type= 6, Freq= 0, CH_0, rank 0
782 12:18:17.841071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 12:18:17.841602 ==
784 12:18:17.844024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 12:18:17.850530 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 12:18:17.859505 [CA 0] Center 37 (6~68) winsize 63
787 12:18:17.863007 [CA 1] Center 36 (6~67) winsize 62
788 12:18:17.867294 [CA 2] Center 34 (4~65) winsize 62
789 12:18:17.869338 [CA 3] Center 34 (4~65) winsize 62
790 12:18:17.872994 [CA 4] Center 33 (3~64) winsize 62
791 12:18:17.877139 [CA 5] Center 33 (3~64) winsize 62
792 12:18:17.877652
793 12:18:17.879791 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 12:18:17.880501
795 12:18:17.882961 [CATrainingPosCal] consider 1 rank data
796 12:18:17.887222 u2DelayCellTimex100 = 270/100 ps
797 12:18:17.889989 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
798 12:18:17.892872 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
799 12:18:17.896574 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 12:18:17.904001 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 12:18:17.906425 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 12:18:17.909511 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 12:18:17.909943
804 12:18:17.913150 CA PerBit enable=1, Macro0, CA PI delay=33
805 12:18:17.913579
806 12:18:17.916246 [CBTSetCACLKResult] CA Dly = 33
807 12:18:17.916671 CS Dly: 6 (0~37)
808 12:18:17.917010 ==
809 12:18:17.919348 Dram Type= 6, Freq= 0, CH_0, rank 1
810 12:18:17.926223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 12:18:17.926749 ==
812 12:18:17.929641 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 12:18:17.936254 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 12:18:17.945904 [CA 0] Center 37 (6~68) winsize 63
815 12:18:17.949181 [CA 1] Center 37 (6~68) winsize 63
816 12:18:17.952493 [CA 2] Center 34 (4~65) winsize 62
817 12:18:17.956356 [CA 3] Center 34 (4~65) winsize 62
818 12:18:17.958722 [CA 4] Center 33 (3~64) winsize 62
819 12:18:17.962627 [CA 5] Center 33 (2~64) winsize 63
820 12:18:17.963196
821 12:18:17.965971 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 12:18:17.966561
823 12:18:17.968893 [CATrainingPosCal] consider 2 rank data
824 12:18:17.972352 u2DelayCellTimex100 = 270/100 ps
825 12:18:17.975714 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
826 12:18:17.981869 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
827 12:18:17.986206 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 12:18:17.989994 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 12:18:17.992887 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 12:18:17.996932 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 12:18:17.997404
832 12:18:18.000040 CA PerBit enable=1, Macro0, CA PI delay=33
833 12:18:18.000512
834 12:18:18.003534 [CBTSetCACLKResult] CA Dly = 33
835 12:18:18.004058 CS Dly: 6 (0~38)
836 12:18:18.004436
837 12:18:18.007491 ----->DramcWriteLeveling(PI) begin...
838 12:18:18.008009 ==
839 12:18:18.011096 Dram Type= 6, Freq= 0, CH_0, rank 0
840 12:18:18.014324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 12:18:18.014754 ==
842 12:18:18.017841 Write leveling (Byte 0): 31 => 31
843 12:18:18.021792 Write leveling (Byte 1): 30 => 30
844 12:18:18.024836 DramcWriteLeveling(PI) end<-----
845 12:18:18.025259
846 12:18:18.025592 ==
847 12:18:18.028248 Dram Type= 6, Freq= 0, CH_0, rank 0
848 12:18:18.031359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 12:18:18.031939 ==
850 12:18:18.035299 [Gating] SW mode calibration
851 12:18:18.042191 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 12:18:18.048353 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 12:18:18.051576 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 12:18:18.054870 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 12:18:18.061104 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 12:18:18.064551 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:18:18.068958 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:18:18.074730 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:18:18.078167 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:18:18.081347 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:18:18.088389 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:18:18.091321 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:18:18.095215 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:18:18.098032 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:18:18.105238 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:18:18.107935 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:18:18.110915 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:18:18.117702 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:18:18.121161 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:18:18.125199 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 12:18:18.131452 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 12:18:18.134864 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:18:18.137990 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:18:18.144184 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:18:18.147779 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:18:18.151409 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:18:18.158008 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:18:18.161317 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:18:18.164578 0 9 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
880 12:18:18.170899 0 9 12 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
881 12:18:18.174848 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:18:18.177766 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 12:18:18.184295 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 12:18:18.187860 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 12:18:18.191732 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 12:18:18.197347 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
887 12:18:18.200453 0 10 8 | B1->B0 | 3333 2525 | 0 0 | (1 0) (1 0)
888 12:18:18.204359 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
889 12:18:18.210995 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:18:18.214378 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:18:18.217722 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 12:18:18.223817 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 12:18:18.227668 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 12:18:18.230323 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
895 12:18:18.237389 0 11 8 | B1->B0 | 2727 3535 | 0 0 | (0 0) (1 1)
896 12:18:18.241905 0 11 12 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
897 12:18:18.244395 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:18:18.248009 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:18:18.251805 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 12:18:18.259188 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 12:18:18.263512 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 12:18:18.266582 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 12:18:18.270320 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 12:18:18.274783 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:18:18.281045 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:18:18.284599 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:18:18.288268 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:18:18.292040 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:18:18.298240 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:18:18.302564 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:18:18.304697 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:18:18.311629 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:18:18.314864 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:18:18.318903 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:18:18.325077 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 12:18:18.328479 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 12:18:18.331967 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 12:18:18.337984 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 12:18:18.342114 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 12:18:18.345056 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
921 12:18:18.348337 Total UI for P1: 0, mck2ui 16
922 12:18:18.352185 best dqsien dly found for B0: ( 0, 14, 8)
923 12:18:18.355617 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 12:18:18.359311 Total UI for P1: 0, mck2ui 16
925 12:18:18.362724 best dqsien dly found for B1: ( 0, 14, 10)
926 12:18:18.368120 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
927 12:18:18.370457 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 12:18:18.371083
929 12:18:18.374043 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 12:18:18.378071 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 12:18:18.381287 [Gating] SW calibration Done
932 12:18:18.381812 ==
933 12:18:18.386793 Dram Type= 6, Freq= 0, CH_0, rank 0
934 12:18:18.388850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 12:18:18.389388 ==
936 12:18:18.389739 RX Vref Scan: 0
937 12:18:18.390056
938 12:18:18.392174 RX Vref 0 -> 0, step: 1
939 12:18:18.392599
940 12:18:18.394924 RX Delay -130 -> 252, step: 16
941 12:18:18.398317 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 12:18:18.402463 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
943 12:18:18.409015 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 12:18:18.411639 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 12:18:18.415665 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
946 12:18:18.418519 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
947 12:18:18.422012 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
948 12:18:18.428414 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
949 12:18:18.432552 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
950 12:18:18.435000 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
951 12:18:18.438000 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
952 12:18:18.441983 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
953 12:18:18.448360 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
954 12:18:18.451718 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
955 12:18:18.454845 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 12:18:18.458626 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
957 12:18:18.459201 ==
958 12:18:18.462383 Dram Type= 6, Freq= 0, CH_0, rank 0
959 12:18:18.468652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 12:18:18.469228 ==
961 12:18:18.469608 DQS Delay:
962 12:18:18.471311 DQS0 = 0, DQS1 = 0
963 12:18:18.471813 DQM Delay:
964 12:18:18.472194 DQM0 = 86, DQM1 = 73
965 12:18:18.475928 DQ Delay:
966 12:18:18.478006 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
967 12:18:18.481216 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
968 12:18:18.484338 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
969 12:18:18.488430 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
970 12:18:18.489009
971 12:18:18.489385
972 12:18:18.489729 ==
973 12:18:18.491149 Dram Type= 6, Freq= 0, CH_0, rank 0
974 12:18:18.495032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 12:18:18.495520 ==
976 12:18:18.495962
977 12:18:18.496317
978 12:18:18.498147 TX Vref Scan disable
979 12:18:18.501228 == TX Byte 0 ==
980 12:18:18.504494 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
981 12:18:18.508042 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
982 12:18:18.511134 == TX Byte 1 ==
983 12:18:18.514408 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
984 12:18:18.517581 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
985 12:18:18.518006 ==
986 12:18:18.521365 Dram Type= 6, Freq= 0, CH_0, rank 0
987 12:18:18.524342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 12:18:18.524799 ==
989 12:18:18.538776 TX Vref=22, minBit 13, minWin=26, winSum=439
990 12:18:18.542364 TX Vref=24, minBit 5, minWin=27, winSum=444
991 12:18:18.545307 TX Vref=26, minBit 8, minWin=27, winSum=446
992 12:18:18.548984 TX Vref=28, minBit 8, minWin=27, winSum=447
993 12:18:18.552101 TX Vref=30, minBit 8, minWin=27, winSum=446
994 12:18:18.558575 TX Vref=32, minBit 9, minWin=26, winSum=441
995 12:18:18.561677 [TxChooseVref] Worse bit 8, Min win 27, Win sum 447, Final Vref 28
996 12:18:18.562152
997 12:18:18.565399 Final TX Range 1 Vref 28
998 12:18:18.565873
999 12:18:18.566239 ==
1000 12:18:18.568146 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 12:18:18.571799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 12:18:18.572273 ==
1003 12:18:18.575431
1004 12:18:18.575955
1005 12:18:18.576331 TX Vref Scan disable
1006 12:18:18.578711 == TX Byte 0 ==
1007 12:18:18.582058 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1008 12:18:18.585384 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1009 12:18:18.588294 == TX Byte 1 ==
1010 12:18:18.591836 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1011 12:18:18.598477 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1012 12:18:18.599046
1013 12:18:18.599412 [DATLAT]
1014 12:18:18.599816 Freq=800, CH0 RK0
1015 12:18:18.600159
1016 12:18:18.601709 DATLAT Default: 0xa
1017 12:18:18.602169 0, 0xFFFF, sum = 0
1018 12:18:18.606798 1, 0xFFFF, sum = 0
1019 12:18:18.607388 2, 0xFFFF, sum = 0
1020 12:18:18.608856 3, 0xFFFF, sum = 0
1021 12:18:18.611809 4, 0xFFFF, sum = 0
1022 12:18:18.612381 5, 0xFFFF, sum = 0
1023 12:18:18.615084 6, 0xFFFF, sum = 0
1024 12:18:18.615728 7, 0xFFFF, sum = 0
1025 12:18:18.618163 8, 0xFFFF, sum = 0
1026 12:18:18.618627 9, 0x0, sum = 1
1027 12:18:18.622703 10, 0x0, sum = 2
1028 12:18:18.623281 11, 0x0, sum = 3
1029 12:18:18.623859 12, 0x0, sum = 4
1030 12:18:18.624754 best_step = 10
1031 12:18:18.625145
1032 12:18:18.625512 ==
1033 12:18:18.627859 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 12:18:18.631949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 12:18:18.632735 ==
1036 12:18:18.634669 RX Vref Scan: 1
1037 12:18:18.635216
1038 12:18:18.638000 Set Vref Range= 32 -> 127
1039 12:18:18.638475
1040 12:18:18.638837 RX Vref 32 -> 127, step: 1
1041 12:18:18.639171
1042 12:18:18.642343 RX Delay -111 -> 252, step: 8
1043 12:18:18.642898
1044 12:18:18.645070 Set Vref, RX VrefLevel [Byte0]: 32
1045 12:18:18.648816 [Byte1]: 32
1046 12:18:18.651189
1047 12:18:18.651644 Set Vref, RX VrefLevel [Byte0]: 33
1048 12:18:18.654923 [Byte1]: 33
1049 12:18:18.659621
1050 12:18:18.660233 Set Vref, RX VrefLevel [Byte0]: 34
1051 12:18:18.662847 [Byte1]: 34
1052 12:18:18.668170
1053 12:18:18.668722 Set Vref, RX VrefLevel [Byte0]: 35
1054 12:18:18.669950 [Byte1]: 35
1055 12:18:18.675464
1056 12:18:18.676074 Set Vref, RX VrefLevel [Byte0]: 36
1057 12:18:18.677992 [Byte1]: 36
1058 12:18:18.682868
1059 12:18:18.683325 Set Vref, RX VrefLevel [Byte0]: 37
1060 12:18:18.684997 [Byte1]: 37
1061 12:18:18.690213
1062 12:18:18.690764 Set Vref, RX VrefLevel [Byte0]: 38
1063 12:18:18.692929 [Byte1]: 38
1064 12:18:18.697888
1065 12:18:18.698439 Set Vref, RX VrefLevel [Byte0]: 39
1066 12:18:18.700791 [Byte1]: 39
1067 12:18:18.705085
1068 12:18:18.705633 Set Vref, RX VrefLevel [Byte0]: 40
1069 12:18:18.711579 [Byte1]: 40
1070 12:18:18.712221
1071 12:18:18.714667 Set Vref, RX VrefLevel [Byte0]: 41
1072 12:18:18.718119 [Byte1]: 41
1073 12:18:18.718680
1074 12:18:18.721266 Set Vref, RX VrefLevel [Byte0]: 42
1075 12:18:18.724807 [Byte1]: 42
1076 12:18:18.728567
1077 12:18:18.729121 Set Vref, RX VrefLevel [Byte0]: 43
1078 12:18:18.731280 [Byte1]: 43
1079 12:18:18.735776
1080 12:18:18.736353 Set Vref, RX VrefLevel [Byte0]: 44
1081 12:18:18.738543 [Byte1]: 44
1082 12:18:18.743061
1083 12:18:18.743516 Set Vref, RX VrefLevel [Byte0]: 45
1084 12:18:18.746791 [Byte1]: 45
1085 12:18:18.750823
1086 12:18:18.751387 Set Vref, RX VrefLevel [Byte0]: 46
1087 12:18:18.754309 [Byte1]: 46
1088 12:18:18.758383
1089 12:18:18.758836 Set Vref, RX VrefLevel [Byte0]: 47
1090 12:18:18.761922 [Byte1]: 47
1091 12:18:18.765754
1092 12:18:18.766365 Set Vref, RX VrefLevel [Byte0]: 48
1093 12:18:18.769142 [Byte1]: 48
1094 12:18:18.773421
1095 12:18:18.773908 Set Vref, RX VrefLevel [Byte0]: 49
1096 12:18:18.777249 [Byte1]: 49
1097 12:18:18.781162
1098 12:18:18.781715 Set Vref, RX VrefLevel [Byte0]: 50
1099 12:18:18.784838 [Byte1]: 50
1100 12:18:18.788810
1101 12:18:18.789265 Set Vref, RX VrefLevel [Byte0]: 51
1102 12:18:18.792278 [Byte1]: 51
1103 12:18:18.796920
1104 12:18:18.797471 Set Vref, RX VrefLevel [Byte0]: 52
1105 12:18:18.799574 [Byte1]: 52
1106 12:18:18.804257
1107 12:18:18.804812 Set Vref, RX VrefLevel [Byte0]: 53
1108 12:18:18.810974 [Byte1]: 53
1109 12:18:18.811531
1110 12:18:18.814236 Set Vref, RX VrefLevel [Byte0]: 54
1111 12:18:18.817849 [Byte1]: 54
1112 12:18:18.818406
1113 12:18:18.821001 Set Vref, RX VrefLevel [Byte0]: 55
1114 12:18:18.823971 [Byte1]: 55
1115 12:18:18.827238
1116 12:18:18.827840 Set Vref, RX VrefLevel [Byte0]: 56
1117 12:18:18.830632 [Byte1]: 56
1118 12:18:18.835175
1119 12:18:18.835783 Set Vref, RX VrefLevel [Byte0]: 57
1120 12:18:18.838332 [Byte1]: 57
1121 12:18:18.843131
1122 12:18:18.843708 Set Vref, RX VrefLevel [Byte0]: 58
1123 12:18:18.846565 [Byte1]: 58
1124 12:18:18.849919
1125 12:18:18.850465 Set Vref, RX VrefLevel [Byte0]: 59
1126 12:18:18.853408 [Byte1]: 59
1127 12:18:18.857860
1128 12:18:18.858412 Set Vref, RX VrefLevel [Byte0]: 60
1129 12:18:18.860837 [Byte1]: 60
1130 12:18:18.865753
1131 12:18:18.866206 Set Vref, RX VrefLevel [Byte0]: 61
1132 12:18:18.868465 [Byte1]: 61
1133 12:18:18.873419
1134 12:18:18.874053 Set Vref, RX VrefLevel [Byte0]: 62
1135 12:18:18.876582 [Byte1]: 62
1136 12:18:18.881120
1137 12:18:18.881576 Set Vref, RX VrefLevel [Byte0]: 63
1138 12:18:18.884423 [Byte1]: 63
1139 12:18:18.889149
1140 12:18:18.889725 Set Vref, RX VrefLevel [Byte0]: 64
1141 12:18:18.892387 [Byte1]: 64
1142 12:18:18.896263
1143 12:18:18.896777 Set Vref, RX VrefLevel [Byte0]: 65
1144 12:18:18.900013 [Byte1]: 65
1145 12:18:18.903556
1146 12:18:18.904145 Set Vref, RX VrefLevel [Byte0]: 66
1147 12:18:18.906845 [Byte1]: 66
1148 12:18:18.911504
1149 12:18:18.912003 Set Vref, RX VrefLevel [Byte0]: 67
1150 12:18:18.915168 [Byte1]: 67
1151 12:18:18.919230
1152 12:18:18.919848 Set Vref, RX VrefLevel [Byte0]: 68
1153 12:18:18.922431 [Byte1]: 68
1154 12:18:18.926773
1155 12:18:18.927234 Set Vref, RX VrefLevel [Byte0]: 69
1156 12:18:18.930060 [Byte1]: 69
1157 12:18:18.934115
1158 12:18:18.934604 Set Vref, RX VrefLevel [Byte0]: 70
1159 12:18:18.937368 [Byte1]: 70
1160 12:18:18.942733
1161 12:18:18.943244 Set Vref, RX VrefLevel [Byte0]: 71
1162 12:18:18.945811 [Byte1]: 71
1163 12:18:18.949307
1164 12:18:18.949723 Set Vref, RX VrefLevel [Byte0]: 72
1165 12:18:18.953276 [Byte1]: 72
1166 12:18:18.957272
1167 12:18:18.957684 Set Vref, RX VrefLevel [Byte0]: 73
1168 12:18:18.960802 [Byte1]: 73
1169 12:18:18.965279
1170 12:18:18.965687 Set Vref, RX VrefLevel [Byte0]: 74
1171 12:18:18.968083 [Byte1]: 74
1172 12:18:18.972984
1173 12:18:18.973536 Set Vref, RX VrefLevel [Byte0]: 75
1174 12:18:18.976277 [Byte1]: 75
1175 12:18:18.980229
1176 12:18:18.980701 Set Vref, RX VrefLevel [Byte0]: 76
1177 12:18:18.983787 [Byte1]: 76
1178 12:18:18.987802
1179 12:18:18.988294 Set Vref, RX VrefLevel [Byte0]: 77
1180 12:18:18.991326 [Byte1]: 77
1181 12:18:18.995432
1182 12:18:18.996032 Set Vref, RX VrefLevel [Byte0]: 78
1183 12:18:18.999352 [Byte1]: 78
1184 12:18:19.003149
1185 12:18:19.003746 Set Vref, RX VrefLevel [Byte0]: 79
1186 12:18:19.006958 [Byte1]: 79
1187 12:18:19.011160
1188 12:18:19.013922 Set Vref, RX VrefLevel [Byte0]: 80
1189 12:18:19.014496 [Byte1]: 80
1190 12:18:19.018703
1191 12:18:19.019114 Final RX Vref Byte 0 = 64 to rank0
1192 12:18:19.021974 Final RX Vref Byte 1 = 58 to rank0
1193 12:18:19.025181 Final RX Vref Byte 0 = 64 to rank1
1194 12:18:19.028733 Final RX Vref Byte 1 = 58 to rank1==
1195 12:18:19.032417 Dram Type= 6, Freq= 0, CH_0, rank 0
1196 12:18:19.035977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1197 12:18:19.036462 ==
1198 12:18:19.039281 DQS Delay:
1199 12:18:19.039857 DQS0 = 0, DQS1 = 0
1200 12:18:19.040202 DQM Delay:
1201 12:18:19.043079 DQM0 = 87, DQM1 = 76
1202 12:18:19.043630 DQ Delay:
1203 12:18:19.047214 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1204 12:18:19.050603 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1205 12:18:19.054084 DQ8 =68, DQ9 =68, DQ10 =76, DQ11 =68
1206 12:18:19.058028 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1207 12:18:19.058711
1208 12:18:19.059061
1209 12:18:19.064344 [DQSOSCAuto] RK0, (LSB)MR18= 0x4526, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1210 12:18:19.068182 CH0 RK0: MR19=606, MR18=4526
1211 12:18:19.075663 CH0_RK0: MR19=0x606, MR18=0x4526, DQSOSC=392, MR23=63, INC=96, DEC=64
1212 12:18:19.076283
1213 12:18:19.076657 ----->DramcWriteLeveling(PI) begin...
1214 12:18:19.079199 ==
1215 12:18:19.079789 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 12:18:19.086146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1217 12:18:19.086746 ==
1218 12:18:19.090084 Write leveling (Byte 0): 34 => 34
1219 12:18:19.090518 Write leveling (Byte 1): 29 => 29
1220 12:18:19.093898 DramcWriteLeveling(PI) end<-----
1221 12:18:19.094506
1222 12:18:19.095023 ==
1223 12:18:19.096988 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 12:18:19.100474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1225 12:18:19.144796 ==
1226 12:18:19.145398 [Gating] SW mode calibration
1227 12:18:19.146261 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1228 12:18:19.146649 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1229 12:18:19.147030 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1230 12:18:19.147435 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1231 12:18:19.147996 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1232 12:18:19.148365 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:18:19.148685 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 12:18:19.148996 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 12:18:19.189429 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:18:19.189979 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:18:19.190344 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 12:18:19.191072 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 12:18:19.191432 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 12:18:19.191912 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 12:18:19.192297 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 12:18:19.192618 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 12:18:19.192993 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:18:19.193315 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 12:18:19.224096 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 12:18:19.224867 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1247 12:18:19.225326 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1248 12:18:19.226026 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 12:18:19.226418 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 12:18:19.226773 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 12:18:19.227200 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 12:18:19.227535 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 12:18:19.229399 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 12:18:19.232979 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 12:18:19.236717 0 9 8 | B1->B0 | 2424 2a2a | 1 0 | (1 1) (0 0)
1256 12:18:19.240329 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 12:18:19.243577 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 12:18:19.251185 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 12:18:19.254633 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 12:18:19.257613 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1261 12:18:19.261617 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1262 12:18:19.266030 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1263 12:18:19.272354 0 10 8 | B1->B0 | 3030 2727 | 0 0 | (0 1) (0 0)
1264 12:18:19.276162 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 12:18:19.280001 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 12:18:19.283344 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 12:18:19.287125 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 12:18:19.294791 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 12:18:19.297546 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1270 12:18:19.301386 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1271 12:18:19.304870 0 11 8 | B1->B0 | 2b2b 3d3d | 0 0 | (0 0) (0 0)
1272 12:18:19.312242 0 11 12 | B1->B0 | 4241 4646 | 1 0 | (0 0) (0 0)
1273 12:18:19.316234 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 12:18:19.319745 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 12:18:19.323420 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 12:18:19.326801 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 12:18:19.334533 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 12:18:19.337913 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 12:18:19.342464 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1280 12:18:19.346090 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 12:18:19.349218 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 12:18:19.356067 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 12:18:19.360105 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 12:18:19.363805 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 12:18:19.367711 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 12:18:19.373863 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 12:18:19.376735 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 12:18:19.380019 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 12:18:19.386597 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 12:18:19.389922 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 12:18:19.393715 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 12:18:19.399815 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 12:18:19.403066 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 12:18:19.407156 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1295 12:18:19.412858 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1296 12:18:19.416031 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1297 12:18:19.420529 Total UI for P1: 0, mck2ui 16
1298 12:18:19.422951 best dqsien dly found for B0: ( 0, 14, 6)
1299 12:18:19.426451 Total UI for P1: 0, mck2ui 16
1300 12:18:19.429417 best dqsien dly found for B1: ( 0, 14, 8)
1301 12:18:19.433438 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1302 12:18:19.436571 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1303 12:18:19.437127
1304 12:18:19.440022 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1305 12:18:19.443354 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1306 12:18:19.446410 [Gating] SW calibration Done
1307 12:18:19.446961 ==
1308 12:18:19.449851 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 12:18:19.453560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 12:18:19.454124 ==
1311 12:18:19.456031 RX Vref Scan: 0
1312 12:18:19.456486
1313 12:18:19.459787 RX Vref 0 -> 0, step: 1
1314 12:18:19.460250
1315 12:18:19.460609 RX Delay -130 -> 252, step: 16
1316 12:18:19.466371 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1317 12:18:19.469642 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1318 12:18:19.472773 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1319 12:18:19.476288 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1320 12:18:19.479208 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1321 12:18:19.486291 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1322 12:18:19.489698 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1323 12:18:19.492508 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1324 12:18:19.496210 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1325 12:18:19.499463 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1326 12:18:19.506034 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1327 12:18:19.509590 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1328 12:18:19.512717 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1329 12:18:19.515915 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1330 12:18:19.522874 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1331 12:18:19.526113 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1332 12:18:19.526575 ==
1333 12:18:19.529197 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 12:18:19.532315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 12:18:19.532948 ==
1336 12:18:19.533341 DQS Delay:
1337 12:18:19.536278 DQS0 = 0, DQS1 = 0
1338 12:18:19.536738 DQM Delay:
1339 12:18:19.539358 DQM0 = 85, DQM1 = 77
1340 12:18:19.539878 DQ Delay:
1341 12:18:19.542009 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1342 12:18:19.545397 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1343 12:18:19.549314 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1344 12:18:19.552261 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1345 12:18:19.552679
1346 12:18:19.553004
1347 12:18:19.553307 ==
1348 12:18:19.555880 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 12:18:19.558729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 12:18:19.562019 ==
1351 12:18:19.562243
1352 12:18:19.562471
1353 12:18:19.562639 TX Vref Scan disable
1354 12:18:19.565690 == TX Byte 0 ==
1355 12:18:19.569232 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1356 12:18:19.572143 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1357 12:18:19.575142 == TX Byte 1 ==
1358 12:18:19.578649 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1359 12:18:19.582166 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1360 12:18:19.584979 ==
1361 12:18:19.589609 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 12:18:19.591448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 12:18:19.591552 ==
1364 12:18:19.604409 TX Vref=22, minBit 4, minWin=27, winSum=442
1365 12:18:19.607693 TX Vref=24, minBit 11, minWin=27, winSum=447
1366 12:18:19.611219 TX Vref=26, minBit 4, minWin=27, winSum=445
1367 12:18:19.614109 TX Vref=28, minBit 9, minWin=27, winSum=448
1368 12:18:19.618021 TX Vref=30, minBit 9, minWin=27, winSum=446
1369 12:18:19.625033 TX Vref=32, minBit 3, minWin=27, winSum=443
1370 12:18:19.628042 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 28
1371 12:18:19.628458
1372 12:18:19.631304 Final TX Range 1 Vref 28
1373 12:18:19.631747
1374 12:18:19.632079 ==
1375 12:18:19.634909 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 12:18:19.638500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 12:18:19.641361 ==
1378 12:18:19.641865
1379 12:18:19.642196
1380 12:18:19.642499 TX Vref Scan disable
1381 12:18:19.645172 == TX Byte 0 ==
1382 12:18:19.648285 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1383 12:18:19.652310 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1384 12:18:19.655182 == TX Byte 1 ==
1385 12:18:19.658295 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1386 12:18:19.665184 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1387 12:18:19.665694
1388 12:18:19.666063 [DATLAT]
1389 12:18:19.666396 Freq=800, CH0 RK1
1390 12:18:19.666714
1391 12:18:19.668558 DATLAT Default: 0xa
1392 12:18:19.669006 0, 0xFFFF, sum = 0
1393 12:18:19.671897 1, 0xFFFF, sum = 0
1394 12:18:19.675877 2, 0xFFFF, sum = 0
1395 12:18:19.676385 3, 0xFFFF, sum = 0
1396 12:18:19.678589 4, 0xFFFF, sum = 0
1397 12:18:19.679099 5, 0xFFFF, sum = 0
1398 12:18:19.681877 6, 0xFFFF, sum = 0
1399 12:18:19.682295 7, 0xFFFF, sum = 0
1400 12:18:19.684747 8, 0xFFFF, sum = 0
1401 12:18:19.685167 9, 0x0, sum = 1
1402 12:18:19.688377 10, 0x0, sum = 2
1403 12:18:19.688891 11, 0x0, sum = 3
1404 12:18:19.689227 12, 0x0, sum = 4
1405 12:18:19.691538 best_step = 10
1406 12:18:19.691986
1407 12:18:19.692312 ==
1408 12:18:19.694862 Dram Type= 6, Freq= 0, CH_0, rank 1
1409 12:18:19.697973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 12:18:19.698387 ==
1411 12:18:19.701127 RX Vref Scan: 0
1412 12:18:19.701534
1413 12:18:19.704334 RX Vref 0 -> 0, step: 1
1414 12:18:19.704743
1415 12:18:19.705103 RX Delay -111 -> 252, step: 8
1416 12:18:19.711950 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1417 12:18:19.715857 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1418 12:18:19.718480 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1419 12:18:19.722021 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1420 12:18:19.725645 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1421 12:18:19.732125 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1422 12:18:19.735368 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1423 12:18:19.738876 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1424 12:18:19.741583 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1425 12:18:19.745311 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1426 12:18:19.751932 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1427 12:18:19.755026 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1428 12:18:19.758474 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1429 12:18:19.761581 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1430 12:18:19.768014 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1431 12:18:19.771955 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1432 12:18:19.772503 ==
1433 12:18:19.775457 Dram Type= 6, Freq= 0, CH_0, rank 1
1434 12:18:19.778281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 12:18:19.778832 ==
1436 12:18:19.781269 DQS Delay:
1437 12:18:19.781720 DQS0 = 0, DQS1 = 0
1438 12:18:19.782076 DQM Delay:
1439 12:18:19.785083 DQM0 = 86, DQM1 = 77
1440 12:18:19.785534 DQ Delay:
1441 12:18:19.788915 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1442 12:18:19.791201 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =96
1443 12:18:19.794915 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1444 12:18:19.798249 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1445 12:18:19.798703
1446 12:18:19.799056
1447 12:18:19.807922 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c02, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1448 12:18:19.808476 CH0 RK1: MR19=606, MR18=3C02
1449 12:18:19.814264 CH0_RK1: MR19=0x606, MR18=0x3C02, DQSOSC=394, MR23=63, INC=95, DEC=63
1450 12:18:19.818053 [RxdqsGatingPostProcess] freq 800
1451 12:18:19.824246 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1452 12:18:19.827590 Pre-setting of DQS Precalculation
1453 12:18:19.831079 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1454 12:18:19.831638 ==
1455 12:18:19.834073 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 12:18:19.840674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 12:18:19.841243 ==
1458 12:18:19.844273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1459 12:18:19.850917 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1460 12:18:19.860310 [CA 0] Center 36 (6~67) winsize 62
1461 12:18:19.863974 [CA 1] Center 36 (6~67) winsize 62
1462 12:18:19.867094 [CA 2] Center 34 (4~65) winsize 62
1463 12:18:19.870361 [CA 3] Center 34 (4~65) winsize 62
1464 12:18:19.873810 [CA 4] Center 34 (4~65) winsize 62
1465 12:18:19.876493 [CA 5] Center 34 (3~65) winsize 63
1466 12:18:19.876947
1467 12:18:19.880367 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1468 12:18:19.880919
1469 12:18:19.883516 [CATrainingPosCal] consider 1 rank data
1470 12:18:19.887243 u2DelayCellTimex100 = 270/100 ps
1471 12:18:19.889932 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1472 12:18:19.896971 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1473 12:18:19.900616 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1474 12:18:19.903153 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1475 12:18:19.906469 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 12:18:19.909893 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1477 12:18:19.910460
1478 12:18:19.913603 CA PerBit enable=1, Macro0, CA PI delay=34
1479 12:18:19.914060
1480 12:18:19.916858 [CBTSetCACLKResult] CA Dly = 34
1481 12:18:19.919466 CS Dly: 5 (0~36)
1482 12:18:19.919964 ==
1483 12:18:19.923218 Dram Type= 6, Freq= 0, CH_1, rank 1
1484 12:18:19.926355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1485 12:18:19.926910 ==
1486 12:18:19.932938 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1487 12:18:19.936556 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1488 12:18:19.946540 [CA 0] Center 36 (6~67) winsize 62
1489 12:18:19.950918 [CA 1] Center 36 (6~67) winsize 62
1490 12:18:19.952575 [CA 2] Center 34 (4~65) winsize 62
1491 12:18:19.956217 [CA 3] Center 34 (3~65) winsize 63
1492 12:18:19.959760 [CA 4] Center 34 (4~65) winsize 62
1493 12:18:19.962859 [CA 5] Center 34 (3~65) winsize 63
1494 12:18:19.963418
1495 12:18:19.966084 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1496 12:18:19.966644
1497 12:18:19.969206 [CATrainingPosCal] consider 2 rank data
1498 12:18:19.972789 u2DelayCellTimex100 = 270/100 ps
1499 12:18:19.975963 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1500 12:18:19.983036 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1501 12:18:19.986188 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1502 12:18:19.989502 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1503 12:18:19.992151 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1504 12:18:19.996358 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1505 12:18:19.996773
1506 12:18:19.999087 CA PerBit enable=1, Macro0, CA PI delay=34
1507 12:18:19.999529
1508 12:18:20.002479 [CBTSetCACLKResult] CA Dly = 34
1509 12:18:20.005582 CS Dly: 6 (0~38)
1510 12:18:20.005995
1511 12:18:20.009566 ----->DramcWriteLeveling(PI) begin...
1512 12:18:20.009987 ==
1513 12:18:20.012992 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 12:18:20.015826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 12:18:20.016259 ==
1516 12:18:20.018793 Write leveling (Byte 0): 25 => 25
1517 12:18:20.021935 Write leveling (Byte 1): 30 => 30
1518 12:18:20.025486 DramcWriteLeveling(PI) end<-----
1519 12:18:20.025901
1520 12:18:20.026224 ==
1521 12:18:20.028553 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 12:18:20.031828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 12:18:20.032248 ==
1524 12:18:20.035543 [Gating] SW mode calibration
1525 12:18:20.041882 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1526 12:18:20.049768 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1527 12:18:20.051808 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1528 12:18:20.055259 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1529 12:18:20.062852 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:18:20.066288 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:18:20.068358 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:18:20.075228 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 12:18:20.078390 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:18:20.082382 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:18:20.088358 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:18:20.091334 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 12:18:20.095585 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 12:18:20.101331 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 12:18:20.104896 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 12:18:20.108315 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 12:18:20.114857 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 12:18:20.118277 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:18:20.121655 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1544 12:18:20.128218 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1545 12:18:20.131863 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1546 12:18:20.135094 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 12:18:20.141167 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 12:18:20.144478 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 12:18:20.147726 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 12:18:20.154431 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 12:18:20.157499 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 12:18:20.161401 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 12:18:20.167492 0 9 8 | B1->B0 | 2a2a 3333 | 0 1 | (0 0) (1 1)
1554 12:18:20.171524 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 12:18:20.174410 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 12:18:20.180714 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 12:18:20.184358 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1558 12:18:20.187925 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1559 12:18:20.194194 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1560 12:18:20.197641 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
1561 12:18:20.200747 0 10 8 | B1->B0 | 2b2b 2626 | 0 0 | (0 0) (0 0)
1562 12:18:20.207597 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 12:18:20.212104 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 12:18:20.213820 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 12:18:20.218712 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 12:18:20.224136 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 12:18:20.227474 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 12:18:20.231191 0 11 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1569 12:18:20.237670 0 11 8 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
1570 12:18:20.240422 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 12:18:20.244211 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 12:18:20.251589 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 12:18:20.254042 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 12:18:20.257576 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 12:18:20.263869 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1576 12:18:20.267024 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1577 12:18:20.270925 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1578 12:18:20.277463 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 12:18:20.281311 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 12:18:20.283501 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 12:18:20.290473 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 12:18:20.293579 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 12:18:20.296632 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 12:18:20.303328 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 12:18:20.307014 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 12:18:20.310139 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 12:18:20.316466 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 12:18:20.320592 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 12:18:20.324203 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 12:18:20.330432 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 12:18:20.333166 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 12:18:20.336638 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1593 12:18:20.344061 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1594 12:18:20.344520 Total UI for P1: 0, mck2ui 16
1595 12:18:20.350174 best dqsien dly found for B0: ( 0, 14, 4)
1596 12:18:20.350724 Total UI for P1: 0, mck2ui 16
1597 12:18:20.356903 best dqsien dly found for B1: ( 0, 14, 4)
1598 12:18:20.361258 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1599 12:18:20.363357 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1600 12:18:20.363965
1601 12:18:20.367592 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1602 12:18:20.369903 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1603 12:18:20.373333 [Gating] SW calibration Done
1604 12:18:20.373887 ==
1605 12:18:20.376948 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 12:18:20.380261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 12:18:20.380820 ==
1608 12:18:20.383222 RX Vref Scan: 0
1609 12:18:20.383722
1610 12:18:20.384097 RX Vref 0 -> 0, step: 1
1611 12:18:20.384436
1612 12:18:20.386314 RX Delay -130 -> 252, step: 16
1613 12:18:20.390145 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1614 12:18:20.396257 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1615 12:18:20.399855 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1616 12:18:20.402621 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1617 12:18:20.406137 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1618 12:18:20.409879 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1619 12:18:20.416125 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1620 12:18:20.419800 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1621 12:18:20.422576 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1622 12:18:20.426391 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1623 12:18:20.432516 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1624 12:18:20.436496 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1625 12:18:20.439842 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1626 12:18:20.442805 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1627 12:18:20.446345 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1628 12:18:20.452497 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1629 12:18:20.453059 ==
1630 12:18:20.456316 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 12:18:20.459930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 12:18:20.460521 ==
1633 12:18:20.460891 DQS Delay:
1634 12:18:20.463066 DQS0 = 0, DQS1 = 0
1635 12:18:20.463620 DQM Delay:
1636 12:18:20.465484 DQM0 = 89, DQM1 = 78
1637 12:18:20.465943 DQ Delay:
1638 12:18:20.469381 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1639 12:18:20.472526 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1640 12:18:20.476587 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1641 12:18:20.479260 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1642 12:18:20.479865
1643 12:18:20.480238
1644 12:18:20.480578 ==
1645 12:18:20.483034 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 12:18:20.486149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 12:18:20.486677 ==
1648 12:18:20.488867
1649 12:18:20.489426
1650 12:18:20.489797 TX Vref Scan disable
1651 12:18:20.492352 == TX Byte 0 ==
1652 12:18:20.495929 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1653 12:18:20.498969 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1654 12:18:20.502001 == TX Byte 1 ==
1655 12:18:20.506282 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1656 12:18:20.508949 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1657 12:18:20.509545 ==
1658 12:18:20.512224 Dram Type= 6, Freq= 0, CH_1, rank 0
1659 12:18:20.519082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1660 12:18:20.519600 ==
1661 12:18:20.531909 TX Vref=22, minBit 10, minWin=26, winSum=437
1662 12:18:20.534483 TX Vref=24, minBit 10, minWin=26, winSum=442
1663 12:18:20.537745 TX Vref=26, minBit 8, minWin=27, winSum=446
1664 12:18:20.541107 TX Vref=28, minBit 0, minWin=27, winSum=447
1665 12:18:20.544688 TX Vref=30, minBit 6, minWin=27, winSum=445
1666 12:18:20.551367 TX Vref=32, minBit 1, minWin=27, winSum=444
1667 12:18:20.554541 [TxChooseVref] Worse bit 0, Min win 27, Win sum 447, Final Vref 28
1668 12:18:20.555157
1669 12:18:20.557750 Final TX Range 1 Vref 28
1670 12:18:20.558498
1671 12:18:20.558895 ==
1672 12:18:20.561403 Dram Type= 6, Freq= 0, CH_1, rank 0
1673 12:18:20.564568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1674 12:18:20.567666 ==
1675 12:18:20.568269
1676 12:18:20.568638
1677 12:18:20.568974 TX Vref Scan disable
1678 12:18:20.571844 == TX Byte 0 ==
1679 12:18:20.574868 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1680 12:18:20.581671 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1681 12:18:20.582232 == TX Byte 1 ==
1682 12:18:20.584373 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1683 12:18:20.591326 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1684 12:18:20.591921
1685 12:18:20.592364 [DATLAT]
1686 12:18:20.592713 Freq=800, CH1 RK0
1687 12:18:20.593040
1688 12:18:20.594396 DATLAT Default: 0xa
1689 12:18:20.594859 0, 0xFFFF, sum = 0
1690 12:18:20.597921 1, 0xFFFF, sum = 0
1691 12:18:20.601332 2, 0xFFFF, sum = 0
1692 12:18:20.601897 3, 0xFFFF, sum = 0
1693 12:18:20.604556 4, 0xFFFF, sum = 0
1694 12:18:20.605022 5, 0xFFFF, sum = 0
1695 12:18:20.607544 6, 0xFFFF, sum = 0
1696 12:18:20.608055 7, 0xFFFF, sum = 0
1697 12:18:20.611662 8, 0xFFFF, sum = 0
1698 12:18:20.612280 9, 0x0, sum = 1
1699 12:18:20.614801 10, 0x0, sum = 2
1700 12:18:20.615541 11, 0x0, sum = 3
1701 12:18:20.617789 12, 0x0, sum = 4
1702 12:18:20.618255 best_step = 10
1703 12:18:20.618616
1704 12:18:20.618949 ==
1705 12:18:20.620630 Dram Type= 6, Freq= 0, CH_1, rank 0
1706 12:18:20.623853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1707 12:18:20.624315 ==
1708 12:18:20.628258 RX Vref Scan: 1
1709 12:18:20.628810
1710 12:18:20.631263 Set Vref Range= 32 -> 127
1711 12:18:20.631889
1712 12:18:20.632267 RX Vref 32 -> 127, step: 1
1713 12:18:20.632607
1714 12:18:20.635249 RX Delay -95 -> 252, step: 8
1715 12:18:20.635844
1716 12:18:20.637791 Set Vref, RX VrefLevel [Byte0]: 32
1717 12:18:20.640521 [Byte1]: 32
1718 12:18:20.643782
1719 12:18:20.644242 Set Vref, RX VrefLevel [Byte0]: 33
1720 12:18:20.647846 [Byte1]: 33
1721 12:18:20.651857
1722 12:18:20.652436 Set Vref, RX VrefLevel [Byte0]: 34
1723 12:18:20.655277 [Byte1]: 34
1724 12:18:20.659366
1725 12:18:20.659999 Set Vref, RX VrefLevel [Byte0]: 35
1726 12:18:20.662764 [Byte1]: 35
1727 12:18:20.667004
1728 12:18:20.667559 Set Vref, RX VrefLevel [Byte0]: 36
1729 12:18:20.670085 [Byte1]: 36
1730 12:18:20.675500
1731 12:18:20.676113 Set Vref, RX VrefLevel [Byte0]: 37
1732 12:18:20.678101 [Byte1]: 37
1733 12:18:20.682930
1734 12:18:20.683490 Set Vref, RX VrefLevel [Byte0]: 38
1735 12:18:20.686006 [Byte1]: 38
1736 12:18:20.690134
1737 12:18:20.690592 Set Vref, RX VrefLevel [Byte0]: 39
1738 12:18:20.692823 [Byte1]: 39
1739 12:18:20.697288
1740 12:18:20.697746 Set Vref, RX VrefLevel [Byte0]: 40
1741 12:18:20.701031 [Byte1]: 40
1742 12:18:20.704918
1743 12:18:20.705673 Set Vref, RX VrefLevel [Byte0]: 41
1744 12:18:20.707844 [Byte1]: 41
1745 12:18:20.712581
1746 12:18:20.715492 Set Vref, RX VrefLevel [Byte0]: 42
1747 12:18:20.718697 [Byte1]: 42
1748 12:18:20.719279
1749 12:18:20.722135 Set Vref, RX VrefLevel [Byte0]: 43
1750 12:18:20.725679 [Byte1]: 43
1751 12:18:20.726237
1752 12:18:20.728924 Set Vref, RX VrefLevel [Byte0]: 44
1753 12:18:20.732273 [Byte1]: 44
1754 12:18:20.735045
1755 12:18:20.735500 Set Vref, RX VrefLevel [Byte0]: 45
1756 12:18:20.738461 [Byte1]: 45
1757 12:18:20.743180
1758 12:18:20.743788 Set Vref, RX VrefLevel [Byte0]: 46
1759 12:18:20.746156 [Byte1]: 46
1760 12:18:20.750350
1761 12:18:20.750806 Set Vref, RX VrefLevel [Byte0]: 47
1762 12:18:20.755174 [Byte1]: 47
1763 12:18:20.757958
1764 12:18:20.758414 Set Vref, RX VrefLevel [Byte0]: 48
1765 12:18:20.761226 [Byte1]: 48
1766 12:18:20.765741
1767 12:18:20.766196 Set Vref, RX VrefLevel [Byte0]: 49
1768 12:18:20.768773 [Byte1]: 49
1769 12:18:20.773522
1770 12:18:20.774037 Set Vref, RX VrefLevel [Byte0]: 50
1771 12:18:20.776583 [Byte1]: 50
1772 12:18:20.781242
1773 12:18:20.781754 Set Vref, RX VrefLevel [Byte0]: 51
1774 12:18:20.784352 [Byte1]: 51
1775 12:18:20.788212
1776 12:18:20.788628 Set Vref, RX VrefLevel [Byte0]: 52
1777 12:18:20.791606 [Byte1]: 52
1778 12:18:20.796279
1779 12:18:20.796934 Set Vref, RX VrefLevel [Byte0]: 53
1780 12:18:20.799257 [Byte1]: 53
1781 12:18:20.803844
1782 12:18:20.804362 Set Vref, RX VrefLevel [Byte0]: 54
1783 12:18:20.806813 [Byte1]: 54
1784 12:18:20.810964
1785 12:18:20.815085 Set Vref, RX VrefLevel [Byte0]: 55
1786 12:18:20.817500 [Byte1]: 55
1787 12:18:20.818008
1788 12:18:20.820884 Set Vref, RX VrefLevel [Byte0]: 56
1789 12:18:20.825023 [Byte1]: 56
1790 12:18:20.825543
1791 12:18:20.827924 Set Vref, RX VrefLevel [Byte0]: 57
1792 12:18:20.830714 [Byte1]: 57
1793 12:18:20.834333
1794 12:18:20.834847 Set Vref, RX VrefLevel [Byte0]: 58
1795 12:18:20.837273 [Byte1]: 58
1796 12:18:20.841346
1797 12:18:20.841759 Set Vref, RX VrefLevel [Byte0]: 59
1798 12:18:20.845472 [Byte1]: 59
1799 12:18:20.849168
1800 12:18:20.849681 Set Vref, RX VrefLevel [Byte0]: 60
1801 12:18:20.853279 [Byte1]: 60
1802 12:18:20.856705
1803 12:18:20.857216 Set Vref, RX VrefLevel [Byte0]: 61
1804 12:18:20.860618 [Byte1]: 61
1805 12:18:20.864478
1806 12:18:20.864998 Set Vref, RX VrefLevel [Byte0]: 62
1807 12:18:20.867484 [Byte1]: 62
1808 12:18:20.872101
1809 12:18:20.872601 Set Vref, RX VrefLevel [Byte0]: 63
1810 12:18:20.875486 [Byte1]: 63
1811 12:18:20.879728
1812 12:18:20.880255 Set Vref, RX VrefLevel [Byte0]: 64
1813 12:18:20.883599 [Byte1]: 64
1814 12:18:20.887413
1815 12:18:20.888041 Set Vref, RX VrefLevel [Byte0]: 65
1816 12:18:20.890412 [Byte1]: 65
1817 12:18:20.894711
1818 12:18:20.895182 Set Vref, RX VrefLevel [Byte0]: 66
1819 12:18:20.898399 [Byte1]: 66
1820 12:18:20.902900
1821 12:18:20.903449 Set Vref, RX VrefLevel [Byte0]: 67
1822 12:18:20.905680 [Byte1]: 67
1823 12:18:20.910374
1824 12:18:20.910948 Set Vref, RX VrefLevel [Byte0]: 68
1825 12:18:20.913398 [Byte1]: 68
1826 12:18:20.919152
1827 12:18:20.919749 Set Vref, RX VrefLevel [Byte0]: 69
1828 12:18:20.920969 [Byte1]: 69
1829 12:18:20.925483
1830 12:18:20.926043 Set Vref, RX VrefLevel [Byte0]: 70
1831 12:18:20.928265 [Byte1]: 70
1832 12:18:20.933080
1833 12:18:20.933637 Set Vref, RX VrefLevel [Byte0]: 71
1834 12:18:20.935821 [Byte1]: 71
1835 12:18:20.940526
1836 12:18:20.940981 Set Vref, RX VrefLevel [Byte0]: 72
1837 12:18:20.943360 [Byte1]: 72
1838 12:18:20.948180
1839 12:18:20.948737 Set Vref, RX VrefLevel [Byte0]: 73
1840 12:18:20.951530 [Byte1]: 73
1841 12:18:20.956217
1842 12:18:20.956770 Set Vref, RX VrefLevel [Byte0]: 74
1843 12:18:20.959803 [Byte1]: 74
1844 12:18:20.963449
1845 12:18:20.964061 Final RX Vref Byte 0 = 54 to rank0
1846 12:18:20.966517 Final RX Vref Byte 1 = 63 to rank0
1847 12:18:20.970211 Final RX Vref Byte 0 = 54 to rank1
1848 12:18:20.973567 Final RX Vref Byte 1 = 63 to rank1==
1849 12:18:20.976387 Dram Type= 6, Freq= 0, CH_1, rank 0
1850 12:18:20.982983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1851 12:18:20.983561 ==
1852 12:18:20.984089 DQS Delay:
1853 12:18:20.986767 DQS0 = 0, DQS1 = 0
1854 12:18:20.987334 DQM Delay:
1855 12:18:20.987876 DQM0 = 87, DQM1 = 79
1856 12:18:20.989658 DQ Delay:
1857 12:18:20.992927 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1858 12:18:20.996431 DQ4 =84, DQ5 =100, DQ6 =96, DQ7 =84
1859 12:18:20.999422 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1860 12:18:21.003167 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1861 12:18:21.003779
1862 12:18:21.004260
1863 12:18:21.009392 [DQSOSCAuto] RK0, (LSB)MR18= 0x3421, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1864 12:18:21.013005 CH1 RK0: MR19=606, MR18=3421
1865 12:18:21.019398 CH1_RK0: MR19=0x606, MR18=0x3421, DQSOSC=396, MR23=63, INC=94, DEC=62
1866 12:18:21.020016
1867 12:18:21.022664 ----->DramcWriteLeveling(PI) begin...
1868 12:18:21.023236 ==
1869 12:18:21.026143 Dram Type= 6, Freq= 0, CH_1, rank 1
1870 12:18:21.029842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1871 12:18:21.030319 ==
1872 12:18:21.032432 Write leveling (Byte 0): 28 => 28
1873 12:18:21.036362 Write leveling (Byte 1): 29 => 29
1874 12:18:21.040514 DramcWriteLeveling(PI) end<-----
1875 12:18:21.041074
1876 12:18:21.041556 ==
1877 12:18:21.043201 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 12:18:21.045931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1879 12:18:21.046408 ==
1880 12:18:21.049106 [Gating] SW mode calibration
1881 12:18:21.056231 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1882 12:18:21.062780 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1883 12:18:21.065930 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1884 12:18:21.072725 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1885 12:18:21.075813 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1886 12:18:21.078879 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:18:21.085268 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 12:18:21.089298 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 12:18:21.092807 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:18:21.098958 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:18:21.102187 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:18:21.105345 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:18:21.109212 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:18:21.115953 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:18:21.119119 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:18:21.122484 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:18:21.128664 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:18:21.133195 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:18:21.135756 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:18:21.142617 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1901 12:18:21.145313 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1902 12:18:21.149265 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 12:18:21.155369 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 12:18:21.158734 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 12:18:21.162166 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 12:18:21.168634 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 12:18:21.172168 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 12:18:21.175722 0 9 4 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1909 12:18:21.183293 0 9 8 | B1->B0 | 2f2f 2727 | 1 0 | (1 1) (0 0)
1910 12:18:21.185140 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 12:18:21.188586 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 12:18:21.194936 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 12:18:21.198331 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 12:18:21.202369 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 12:18:21.208357 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 12:18:21.211326 0 10 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1917 12:18:21.214971 0 10 8 | B1->B0 | 2626 3030 | 0 0 | (0 0) (1 1)
1918 12:18:21.221993 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 12:18:21.224778 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 12:18:21.228904 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 12:18:21.235009 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 12:18:21.238860 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 12:18:21.241438 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 12:18:21.249103 0 11 4 | B1->B0 | 2d2d 2424 | 1 0 | (0 0) (0 0)
1925 12:18:21.251439 0 11 8 | B1->B0 | 3f3f 3a3a | 0 0 | (0 0) (0 0)
1926 12:18:21.254791 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1927 12:18:21.261460 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 12:18:21.264730 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 12:18:21.267990 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 12:18:21.275352 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 12:18:21.278177 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 12:18:21.281207 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1933 12:18:21.284714 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 12:18:21.291344 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 12:18:21.295120 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 12:18:21.297835 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 12:18:21.304338 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 12:18:21.308312 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 12:18:21.311274 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 12:18:21.318443 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 12:18:21.321072 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 12:18:21.324336 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 12:18:21.330884 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 12:18:21.334576 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 12:18:21.338230 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 12:18:21.344640 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 12:18:21.347941 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 12:18:21.351315 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1949 12:18:21.357685 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1950 12:18:21.361350 Total UI for P1: 0, mck2ui 16
1951 12:18:21.364576 best dqsien dly found for B1: ( 0, 14, 4)
1952 12:18:21.367933 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1953 12:18:21.370685 Total UI for P1: 0, mck2ui 16
1954 12:18:21.374654 best dqsien dly found for B0: ( 0, 14, 6)
1955 12:18:21.377763 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1956 12:18:21.380906 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1957 12:18:21.381365
1958 12:18:21.384303 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1959 12:18:21.387169 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1960 12:18:21.390419 [Gating] SW calibration Done
1961 12:18:21.390876 ==
1962 12:18:21.393998 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 12:18:21.397665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 12:18:21.400463 ==
1965 12:18:21.400947 RX Vref Scan: 0
1966 12:18:21.401422
1967 12:18:21.403967 RX Vref 0 -> 0, step: 1
1968 12:18:21.404437
1969 12:18:21.407307 RX Delay -130 -> 252, step: 16
1970 12:18:21.410726 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1971 12:18:21.413976 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1972 12:18:21.416809 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1973 12:18:21.421253 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1974 12:18:21.427608 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1975 12:18:21.430490 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1976 12:18:21.433761 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1977 12:18:21.437587 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1978 12:18:21.440294 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1979 12:18:21.446855 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1980 12:18:21.450539 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1981 12:18:21.454103 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1982 12:18:21.456919 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1983 12:18:21.463618 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1984 12:18:21.467024 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1985 12:18:21.470163 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1986 12:18:21.470713 ==
1987 12:18:21.474003 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 12:18:21.477002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 12:18:21.477468 ==
1990 12:18:21.480160 DQS Delay:
1991 12:18:21.480709 DQS0 = 0, DQS1 = 0
1992 12:18:21.483659 DQM Delay:
1993 12:18:21.484270 DQM0 = 88, DQM1 = 79
1994 12:18:21.484635 DQ Delay:
1995 12:18:21.486999 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1996 12:18:21.490382 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1997 12:18:21.493245 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1998 12:18:21.496374 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1999 12:18:21.496832
2000 12:18:21.497192
2001 12:18:21.500096 ==
2002 12:18:21.503789 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 12:18:21.506669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 12:18:21.507129 ==
2005 12:18:21.507494
2006 12:18:21.507881
2007 12:18:21.509824 TX Vref Scan disable
2008 12:18:21.510325 == TX Byte 0 ==
2009 12:18:21.513306 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2010 12:18:21.519801 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2011 12:18:21.520320 == TX Byte 1 ==
2012 12:18:21.526087 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2013 12:18:21.530235 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2014 12:18:21.530749 ==
2015 12:18:21.532793 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 12:18:21.536374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 12:18:21.536791 ==
2018 12:18:21.549913 TX Vref=22, minBit 8, minWin=27, winSum=447
2019 12:18:21.553383 TX Vref=24, minBit 9, minWin=26, winSum=446
2020 12:18:21.556150 TX Vref=26, minBit 1, minWin=27, winSum=449
2021 12:18:21.559776 TX Vref=28, minBit 8, minWin=27, winSum=451
2022 12:18:21.563095 TX Vref=30, minBit 8, minWin=27, winSum=452
2023 12:18:21.570332 TX Vref=32, minBit 8, minWin=27, winSum=450
2024 12:18:21.572869 [TxChooseVref] Worse bit 8, Min win 27, Win sum 452, Final Vref 30
2025 12:18:21.573428
2026 12:18:21.576658 Final TX Range 1 Vref 30
2027 12:18:21.577119
2028 12:18:21.577479 ==
2029 12:18:21.579842 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 12:18:21.583233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 12:18:21.583836 ==
2032 12:18:21.586469
2033 12:18:21.587020
2034 12:18:21.587380 TX Vref Scan disable
2035 12:18:21.589414 == TX Byte 0 ==
2036 12:18:21.592884 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2037 12:18:21.599895 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2038 12:18:21.600492 == TX Byte 1 ==
2039 12:18:21.603497 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2040 12:18:21.609595 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2041 12:18:21.610150
2042 12:18:21.610514 [DATLAT]
2043 12:18:21.610855 Freq=800, CH1 RK1
2044 12:18:21.611181
2045 12:18:21.612504 DATLAT Default: 0xa
2046 12:18:21.615904 0, 0xFFFF, sum = 0
2047 12:18:21.616372 1, 0xFFFF, sum = 0
2048 12:18:21.619715 2, 0xFFFF, sum = 0
2049 12:18:21.620185 3, 0xFFFF, sum = 0
2050 12:18:21.622702 4, 0xFFFF, sum = 0
2051 12:18:21.623275 5, 0xFFFF, sum = 0
2052 12:18:21.625919 6, 0xFFFF, sum = 0
2053 12:18:21.626383 7, 0xFFFF, sum = 0
2054 12:18:21.629240 8, 0xFFFF, sum = 0
2055 12:18:21.629899 9, 0x0, sum = 1
2056 12:18:21.632441 10, 0x0, sum = 2
2057 12:18:21.632908 11, 0x0, sum = 3
2058 12:18:21.635896 12, 0x0, sum = 4
2059 12:18:21.636360 best_step = 10
2060 12:18:21.636719
2061 12:18:21.637056 ==
2062 12:18:21.639336 Dram Type= 6, Freq= 0, CH_1, rank 1
2063 12:18:21.642643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2064 12:18:21.643141 ==
2065 12:18:21.645731 RX Vref Scan: 0
2066 12:18:21.646145
2067 12:18:21.649281 RX Vref 0 -> 0, step: 1
2068 12:18:21.649975
2069 12:18:21.650386 RX Delay -95 -> 252, step: 8
2070 12:18:21.656224 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2071 12:18:21.660153 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2072 12:18:21.663628 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2073 12:18:21.667111 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2074 12:18:21.670104 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2075 12:18:21.676374 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2076 12:18:21.680508 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2077 12:18:21.683196 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2078 12:18:21.686025 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2079 12:18:21.689258 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2080 12:18:21.696287 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2081 12:18:21.699860 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2082 12:18:21.702896 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2083 12:18:21.706993 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2084 12:18:21.712443 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
2085 12:18:21.716330 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2086 12:18:21.716897 ==
2087 12:18:21.719913 Dram Type= 6, Freq= 0, CH_1, rank 1
2088 12:18:21.723833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2089 12:18:21.724389 ==
2090 12:18:21.726309 DQS Delay:
2091 12:18:21.726765 DQS0 = 0, DQS1 = 0
2092 12:18:21.727124 DQM Delay:
2093 12:18:21.729725 DQM0 = 87, DQM1 = 78
2094 12:18:21.730186 DQ Delay:
2095 12:18:21.732705 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2096 12:18:21.736169 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2097 12:18:21.739590 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2098 12:18:21.742721 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
2099 12:18:21.743336
2100 12:18:21.743747
2101 12:18:21.752905 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2102 12:18:21.755497 CH1 RK1: MR19=606, MR18=1C15
2103 12:18:21.758975 CH1_RK1: MR19=0x606, MR18=0x1C15, DQSOSC=402, MR23=63, INC=91, DEC=60
2104 12:18:21.762676 [RxdqsGatingPostProcess] freq 800
2105 12:18:21.768750 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2106 12:18:21.772215 Pre-setting of DQS Precalculation
2107 12:18:21.775448 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2108 12:18:21.785366 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2109 12:18:21.792315 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2110 12:18:21.792867
2111 12:18:21.793232
2112 12:18:21.796464 [Calibration Summary] 1600 Mbps
2113 12:18:21.797018 CH 0, Rank 0
2114 12:18:21.799765 SW Impedance : PASS
2115 12:18:21.800318 DUTY Scan : NO K
2116 12:18:21.802091 ZQ Calibration : PASS
2117 12:18:21.805508 Jitter Meter : NO K
2118 12:18:21.806063 CBT Training : PASS
2119 12:18:21.809190 Write leveling : PASS
2120 12:18:21.812212 RX DQS gating : PASS
2121 12:18:21.812672 RX DQ/DQS(RDDQC) : PASS
2122 12:18:21.815730 TX DQ/DQS : PASS
2123 12:18:21.819081 RX DATLAT : PASS
2124 12:18:21.819630 RX DQ/DQS(Engine): PASS
2125 12:18:21.822129 TX OE : NO K
2126 12:18:21.822681 All Pass.
2127 12:18:21.823044
2128 12:18:21.825435 CH 0, Rank 1
2129 12:18:21.825896 SW Impedance : PASS
2130 12:18:21.828361 DUTY Scan : NO K
2131 12:18:21.828820 ZQ Calibration : PASS
2132 12:18:21.832302 Jitter Meter : NO K
2133 12:18:21.834942 CBT Training : PASS
2134 12:18:21.835399 Write leveling : PASS
2135 12:18:21.838885 RX DQS gating : PASS
2136 12:18:21.841607 RX DQ/DQS(RDDQC) : PASS
2137 12:18:21.842063 TX DQ/DQS : PASS
2138 12:18:21.844885 RX DATLAT : PASS
2139 12:18:21.848401 RX DQ/DQS(Engine): PASS
2140 12:18:21.848856 TX OE : NO K
2141 12:18:21.852413 All Pass.
2142 12:18:21.852868
2143 12:18:21.853223 CH 1, Rank 0
2144 12:18:21.855229 SW Impedance : PASS
2145 12:18:21.855720 DUTY Scan : NO K
2146 12:18:21.858457 ZQ Calibration : PASS
2147 12:18:21.861619 Jitter Meter : NO K
2148 12:18:21.862075 CBT Training : PASS
2149 12:18:21.865683 Write leveling : PASS
2150 12:18:21.868554 RX DQS gating : PASS
2151 12:18:21.869011 RX DQ/DQS(RDDQC) : PASS
2152 12:18:21.872050 TX DQ/DQS : PASS
2153 12:18:21.872567 RX DATLAT : PASS
2154 12:18:21.876082 RX DQ/DQS(Engine): PASS
2155 12:18:21.878305 TX OE : NO K
2156 12:18:21.878822 All Pass.
2157 12:18:21.879149
2158 12:18:21.879457 CH 1, Rank 1
2159 12:18:21.881947 SW Impedance : PASS
2160 12:18:21.885789 DUTY Scan : NO K
2161 12:18:21.886306 ZQ Calibration : PASS
2162 12:18:21.888366 Jitter Meter : NO K
2163 12:18:21.891930 CBT Training : PASS
2164 12:18:21.892439 Write leveling : PASS
2165 12:18:21.895495 RX DQS gating : PASS
2166 12:18:21.898992 RX DQ/DQS(RDDQC) : PASS
2167 12:18:21.899504 TX DQ/DQS : PASS
2168 12:18:21.902313 RX DATLAT : PASS
2169 12:18:21.905572 RX DQ/DQS(Engine): PASS
2170 12:18:21.906079 TX OE : NO K
2171 12:18:21.909114 All Pass.
2172 12:18:21.909618
2173 12:18:21.909943 DramC Write-DBI off
2174 12:18:21.911817 PER_BANK_REFRESH: Hybrid Mode
2175 12:18:21.912234 TX_TRACKING: ON
2176 12:18:21.915447 [GetDramInforAfterCalByMRR] Vendor 6.
2177 12:18:21.922328 [GetDramInforAfterCalByMRR] Revision 606.
2178 12:18:21.925220 [GetDramInforAfterCalByMRR] Revision 2 0.
2179 12:18:21.925638 MR0 0x3b3b
2180 12:18:21.926000 MR8 0x5151
2181 12:18:21.928172 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2182 12:18:21.928587
2183 12:18:21.931922 MR0 0x3b3b
2184 12:18:21.932449 MR8 0x5151
2185 12:18:21.935303 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2186 12:18:21.935864
2187 12:18:21.944530 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2188 12:18:21.948366 [FAST_K] Save calibration result to emmc
2189 12:18:21.951626 [FAST_K] Save calibration result to emmc
2190 12:18:21.954679 dram_init: config_dvfs: 1
2191 12:18:21.958513 dramc_set_vcore_voltage set vcore to 662500
2192 12:18:21.961201 Read voltage for 1200, 2
2193 12:18:21.961616 Vio18 = 0
2194 12:18:21.961941 Vcore = 662500
2195 12:18:21.964740 Vdram = 0
2196 12:18:21.965245 Vddq = 0
2197 12:18:21.965576 Vmddr = 0
2198 12:18:21.971732 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2199 12:18:21.974761 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2200 12:18:21.977894 MEM_TYPE=3, freq_sel=15
2201 12:18:21.981687 sv_algorithm_assistance_LP4_1600
2202 12:18:21.984683 ============ PULL DRAM RESETB DOWN ============
2203 12:18:21.988067 ========== PULL DRAM RESETB DOWN end =========
2204 12:18:21.994101 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2205 12:18:21.997813 ===================================
2206 12:18:22.001038 LPDDR4 DRAM CONFIGURATION
2207 12:18:22.004370 ===================================
2208 12:18:22.004851 EX_ROW_EN[0] = 0x0
2209 12:18:22.008068 EX_ROW_EN[1] = 0x0
2210 12:18:22.008526 LP4Y_EN = 0x0
2211 12:18:22.011175 WORK_FSP = 0x0
2212 12:18:22.011807 WL = 0x4
2213 12:18:22.014542 RL = 0x4
2214 12:18:22.015086 BL = 0x2
2215 12:18:22.017456 RPST = 0x0
2216 12:18:22.018018 RD_PRE = 0x0
2217 12:18:22.021502 WR_PRE = 0x1
2218 12:18:22.022029 WR_PST = 0x0
2219 12:18:22.024171 DBI_WR = 0x0
2220 12:18:22.024718 DBI_RD = 0x0
2221 12:18:22.027560 OTF = 0x1
2222 12:18:22.030674 ===================================
2223 12:18:22.034387 ===================================
2224 12:18:22.034938 ANA top config
2225 12:18:22.037462 ===================================
2226 12:18:22.041108 DLL_ASYNC_EN = 0
2227 12:18:22.044292 ALL_SLAVE_EN = 0
2228 12:18:22.047755 NEW_RANK_MODE = 1
2229 12:18:22.048217 DLL_IDLE_MODE = 1
2230 12:18:22.050699 LP45_APHY_COMB_EN = 1
2231 12:18:22.054136 TX_ODT_DIS = 1
2232 12:18:22.058262 NEW_8X_MODE = 1
2233 12:18:22.060799 ===================================
2234 12:18:22.064088 ===================================
2235 12:18:22.067648 data_rate = 2400
2236 12:18:22.070895 CKR = 1
2237 12:18:22.071453 DQ_P2S_RATIO = 8
2238 12:18:22.074513 ===================================
2239 12:18:22.077912 CA_P2S_RATIO = 8
2240 12:18:22.080680 DQ_CA_OPEN = 0
2241 12:18:22.084418 DQ_SEMI_OPEN = 0
2242 12:18:22.087055 CA_SEMI_OPEN = 0
2243 12:18:22.089990 CA_FULL_RATE = 0
2244 12:18:22.090445 DQ_CKDIV4_EN = 0
2245 12:18:22.093326 CA_CKDIV4_EN = 0
2246 12:18:22.097056 CA_PREDIV_EN = 0
2247 12:18:22.100641 PH8_DLY = 17
2248 12:18:22.103276 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2249 12:18:22.107146 DQ_AAMCK_DIV = 4
2250 12:18:22.107742 CA_AAMCK_DIV = 4
2251 12:18:22.111150 CA_ADMCK_DIV = 4
2252 12:18:22.113664 DQ_TRACK_CA_EN = 0
2253 12:18:22.116804 CA_PICK = 1200
2254 12:18:22.120212 CA_MCKIO = 1200
2255 12:18:22.123460 MCKIO_SEMI = 0
2256 12:18:22.126390 PLL_FREQ = 2366
2257 12:18:22.129723 DQ_UI_PI_RATIO = 32
2258 12:18:22.130187 CA_UI_PI_RATIO = 0
2259 12:18:22.133512 ===================================
2260 12:18:22.136150 ===================================
2261 12:18:22.140052 memory_type:LPDDR4
2262 12:18:22.143482 GP_NUM : 10
2263 12:18:22.144148 SRAM_EN : 1
2264 12:18:22.146905 MD32_EN : 0
2265 12:18:22.149796 ===================================
2266 12:18:22.153483 [ANA_INIT] >>>>>>>>>>>>>>
2267 12:18:22.154043 <<<<<< [CONFIGURE PHASE]: ANA_TX
2268 12:18:22.156543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2269 12:18:22.160173 ===================================
2270 12:18:22.164117 data_rate = 2400,PCW = 0X5b00
2271 12:18:22.167390 ===================================
2272 12:18:22.170091 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2273 12:18:22.176750 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2274 12:18:22.183200 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2275 12:18:22.186954 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2276 12:18:22.189891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2277 12:18:22.193059 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2278 12:18:22.196977 [ANA_INIT] flow start
2279 12:18:22.197541 [ANA_INIT] PLL >>>>>>>>
2280 12:18:22.200190 [ANA_INIT] PLL <<<<<<<<
2281 12:18:22.203573 [ANA_INIT] MIDPI >>>>>>>>
2282 12:18:22.206525 [ANA_INIT] MIDPI <<<<<<<<
2283 12:18:22.207081 [ANA_INIT] DLL >>>>>>>>
2284 12:18:22.209686 [ANA_INIT] DLL <<<<<<<<
2285 12:18:22.210244 [ANA_INIT] flow end
2286 12:18:22.216869 ============ LP4 DIFF to SE enter ============
2287 12:18:22.219990 ============ LP4 DIFF to SE exit ============
2288 12:18:22.223027 [ANA_INIT] <<<<<<<<<<<<<
2289 12:18:22.226128 [Flow] Enable top DCM control >>>>>
2290 12:18:22.229960 [Flow] Enable top DCM control <<<<<
2291 12:18:22.230528 Enable DLL master slave shuffle
2292 12:18:22.236074 ==============================================================
2293 12:18:22.239750 Gating Mode config
2294 12:18:22.243248 ==============================================================
2295 12:18:22.246041 Config description:
2296 12:18:22.256431 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2297 12:18:22.262626 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2298 12:18:22.267459 SELPH_MODE 0: By rank 1: By Phase
2299 12:18:22.273103 ==============================================================
2300 12:18:22.276366 GAT_TRACK_EN = 1
2301 12:18:22.279779 RX_GATING_MODE = 2
2302 12:18:22.282852 RX_GATING_TRACK_MODE = 2
2303 12:18:22.286162 SELPH_MODE = 1
2304 12:18:22.289326 PICG_EARLY_EN = 1
2305 12:18:22.289745 VALID_LAT_VALUE = 1
2306 12:18:22.295797 ==============================================================
2307 12:18:22.299023 Enter into Gating configuration >>>>
2308 12:18:22.302293 Exit from Gating configuration <<<<
2309 12:18:22.305231 Enter into DVFS_PRE_config >>>>>
2310 12:18:22.315284 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2311 12:18:22.319270 Exit from DVFS_PRE_config <<<<<
2312 12:18:22.321981 Enter into PICG configuration >>>>
2313 12:18:22.325832 Exit from PICG configuration <<<<
2314 12:18:22.329705 [RX_INPUT] configuration >>>>>
2315 12:18:22.332033 [RX_INPUT] configuration <<<<<
2316 12:18:22.338759 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2317 12:18:22.342093 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2318 12:18:22.349349 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2319 12:18:22.355885 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2320 12:18:22.363259 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2321 12:18:22.368940 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2322 12:18:22.372291 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2323 12:18:22.375772 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2324 12:18:22.379103 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2325 12:18:22.385387 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2326 12:18:22.388965 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2327 12:18:22.392011 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2328 12:18:22.394926 ===================================
2329 12:18:22.399242 LPDDR4 DRAM CONFIGURATION
2330 12:18:22.402054 ===================================
2331 12:18:22.402617 EX_ROW_EN[0] = 0x0
2332 12:18:22.405209 EX_ROW_EN[1] = 0x0
2333 12:18:22.408699 LP4Y_EN = 0x0
2334 12:18:22.409157 WORK_FSP = 0x0
2335 12:18:22.412068 WL = 0x4
2336 12:18:22.412637 RL = 0x4
2337 12:18:22.414610 BL = 0x2
2338 12:18:22.415068 RPST = 0x0
2339 12:18:22.418543 RD_PRE = 0x0
2340 12:18:22.419068 WR_PRE = 0x1
2341 12:18:22.421488 WR_PST = 0x0
2342 12:18:22.421950 DBI_WR = 0x0
2343 12:18:22.425301 DBI_RD = 0x0
2344 12:18:22.425853 OTF = 0x1
2345 12:18:22.428166 ===================================
2346 12:18:22.431588 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2347 12:18:22.437977 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2348 12:18:22.442073 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2349 12:18:22.444406 ===================================
2350 12:18:22.447865 LPDDR4 DRAM CONFIGURATION
2351 12:18:22.451409 ===================================
2352 12:18:22.451933 EX_ROW_EN[0] = 0x10
2353 12:18:22.454920 EX_ROW_EN[1] = 0x0
2354 12:18:22.458204 LP4Y_EN = 0x0
2355 12:18:22.458762 WORK_FSP = 0x0
2356 12:18:22.461100 WL = 0x4
2357 12:18:22.461662 RL = 0x4
2358 12:18:22.464637 BL = 0x2
2359 12:18:22.465192 RPST = 0x0
2360 12:18:22.468547 RD_PRE = 0x0
2361 12:18:22.469004 WR_PRE = 0x1
2362 12:18:22.471394 WR_PST = 0x0
2363 12:18:22.471847 DBI_WR = 0x0
2364 12:18:22.474315 DBI_RD = 0x0
2365 12:18:22.474724 OTF = 0x1
2366 12:18:22.478440 ===================================
2367 12:18:22.485208 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2368 12:18:22.485639 ==
2369 12:18:22.488047 Dram Type= 6, Freq= 0, CH_0, rank 0
2370 12:18:22.490770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 12:18:22.491202 ==
2372 12:18:22.495172 [Duty_Offset_Calibration]
2373 12:18:22.497930 B0:1 B1:-1 CA:0
2374 12:18:22.498438
2375 12:18:22.501338 [DutyScan_Calibration_Flow] k_type=0
2376 12:18:22.509780
2377 12:18:22.510302 ==CLK 0==
2378 12:18:22.512998 Final CLK duty delay cell = 0
2379 12:18:22.515463 [0] MAX Duty = 5094%(X100), DQS PI = 16
2380 12:18:22.518982 [0] MIN Duty = 4875%(X100), DQS PI = 8
2381 12:18:22.522703 [0] AVG Duty = 4984%(X100)
2382 12:18:22.523115
2383 12:18:22.525662 CH0 CLK Duty spec in!! Max-Min= 219%
2384 12:18:22.529433 [DutyScan_Calibration_Flow] ====Done====
2385 12:18:22.529943
2386 12:18:22.532723 [DutyScan_Calibration_Flow] k_type=1
2387 12:18:22.547365
2388 12:18:22.547920 ==DQS 0 ==
2389 12:18:22.551219 Final DQS duty delay cell = -4
2390 12:18:22.554070 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2391 12:18:22.557014 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2392 12:18:22.560607 [-4] AVG Duty = 4968%(X100)
2393 12:18:22.561155
2394 12:18:22.561513 ==DQS 1 ==
2395 12:18:22.563793 Final DQS duty delay cell = -4
2396 12:18:22.566837 [-4] MAX Duty = 5000%(X100), DQS PI = 8
2397 12:18:22.570050 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2398 12:18:22.573115 [-4] AVG Duty = 4938%(X100)
2399 12:18:22.573569
2400 12:18:22.576603 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2401 12:18:22.577156
2402 12:18:22.580349 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2403 12:18:22.583807 [DutyScan_Calibration_Flow] ====Done====
2404 12:18:22.584367
2405 12:18:22.587896 [DutyScan_Calibration_Flow] k_type=3
2406 12:18:22.605004
2407 12:18:22.605560 ==DQM 0 ==
2408 12:18:22.608456 Final DQM duty delay cell = 0
2409 12:18:22.612349 [0] MAX Duty = 5062%(X100), DQS PI = 24
2410 12:18:22.615763 [0] MIN Duty = 4907%(X100), DQS PI = 6
2411 12:18:22.616311 [0] AVG Duty = 4984%(X100)
2412 12:18:22.619100
2413 12:18:22.619717 ==DQM 1 ==
2414 12:18:22.622293 Final DQM duty delay cell = 4
2415 12:18:22.626116 [4] MAX Duty = 5187%(X100), DQS PI = 14
2416 12:18:22.628745 [4] MIN Duty = 5000%(X100), DQS PI = 22
2417 12:18:22.631483 [4] AVG Duty = 5093%(X100)
2418 12:18:22.632077
2419 12:18:22.634840 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2420 12:18:22.635296
2421 12:18:22.638127 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2422 12:18:22.642116 [DutyScan_Calibration_Flow] ====Done====
2423 12:18:22.642662
2424 12:18:22.644514 [DutyScan_Calibration_Flow] k_type=2
2425 12:18:22.660763
2426 12:18:22.661294 ==DQ 0 ==
2427 12:18:22.663766 Final DQ duty delay cell = -4
2428 12:18:22.667452 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2429 12:18:22.669530 [-4] MIN Duty = 4907%(X100), DQS PI = 46
2430 12:18:22.672949 [-4] AVG Duty = 4969%(X100)
2431 12:18:22.673408
2432 12:18:22.673770 ==DQ 1 ==
2433 12:18:22.677062 Final DQ duty delay cell = -4
2434 12:18:22.680317 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2435 12:18:22.683492 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2436 12:18:22.687053 [-4] AVG Duty = 4922%(X100)
2437 12:18:22.687624
2438 12:18:22.690307 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2439 12:18:22.690921
2440 12:18:22.692945 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2441 12:18:22.696531 [DutyScan_Calibration_Flow] ====Done====
2442 12:18:22.697118 ==
2443 12:18:22.700121 Dram Type= 6, Freq= 0, CH_1, rank 0
2444 12:18:22.703260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2445 12:18:22.703880 ==
2446 12:18:22.706588 [Duty_Offset_Calibration]
2447 12:18:22.707045 B0:-1 B1:1 CA:2
2448 12:18:22.707409
2449 12:18:22.710330 [DutyScan_Calibration_Flow] k_type=0
2450 12:18:22.720632
2451 12:18:22.721218 ==CLK 0==
2452 12:18:22.724092 Final CLK duty delay cell = 0
2453 12:18:22.727920 [0] MAX Duty = 5187%(X100), DQS PI = 22
2454 12:18:22.731204 [0] MIN Duty = 4969%(X100), DQS PI = 0
2455 12:18:22.731797 [0] AVG Duty = 5078%(X100)
2456 12:18:22.733684
2457 12:18:22.737838 CH1 CLK Duty spec in!! Max-Min= 218%
2458 12:18:22.741012 [DutyScan_Calibration_Flow] ====Done====
2459 12:18:22.741472
2460 12:18:22.744263 [DutyScan_Calibration_Flow] k_type=1
2461 12:18:22.759964
2462 12:18:22.760514 ==DQS 0 ==
2463 12:18:22.762990 Final DQS duty delay cell = 0
2464 12:18:22.766762 [0] MAX Duty = 5156%(X100), DQS PI = 50
2465 12:18:22.769978 [0] MIN Duty = 4938%(X100), DQS PI = 6
2466 12:18:22.773109 [0] AVG Duty = 5047%(X100)
2467 12:18:22.773523
2468 12:18:22.773850 ==DQS 1 ==
2469 12:18:22.777085 Final DQS duty delay cell = 0
2470 12:18:22.780102 [0] MAX Duty = 5094%(X100), DQS PI = 12
2471 12:18:22.783150 [0] MIN Duty = 4969%(X100), DQS PI = 56
2472 12:18:22.786637 [0] AVG Duty = 5031%(X100)
2473 12:18:22.787187
2474 12:18:22.790040 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2475 12:18:22.790603
2476 12:18:22.793581 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2477 12:18:22.796988 [DutyScan_Calibration_Flow] ====Done====
2478 12:18:22.797549
2479 12:18:22.800018 [DutyScan_Calibration_Flow] k_type=3
2480 12:18:22.815503
2481 12:18:22.816124 ==DQM 0 ==
2482 12:18:22.819617 Final DQM duty delay cell = -4
2483 12:18:22.823040 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2484 12:18:22.826040 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2485 12:18:22.828929 [-4] AVG Duty = 4969%(X100)
2486 12:18:22.829390
2487 12:18:22.829754 ==DQM 1 ==
2488 12:18:22.832380 Final DQM duty delay cell = 0
2489 12:18:22.835740 [0] MAX Duty = 5156%(X100), DQS PI = 4
2490 12:18:22.839021 [0] MIN Duty = 5000%(X100), DQS PI = 28
2491 12:18:22.842416 [0] AVG Duty = 5078%(X100)
2492 12:18:22.842979
2493 12:18:22.845845 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2494 12:18:22.846305
2495 12:18:22.848548 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2496 12:18:22.852651 [DutyScan_Calibration_Flow] ====Done====
2497 12:18:22.853204
2498 12:18:22.855280 [DutyScan_Calibration_Flow] k_type=2
2499 12:18:22.872303
2500 12:18:22.872866 ==DQ 0 ==
2501 12:18:22.875946 Final DQ duty delay cell = 0
2502 12:18:22.878740 [0] MAX Duty = 5156%(X100), DQS PI = 28
2503 12:18:22.882307 [0] MIN Duty = 4907%(X100), DQS PI = 6
2504 12:18:22.882869 [0] AVG Duty = 5031%(X100)
2505 12:18:22.885736
2506 12:18:22.886293 ==DQ 1 ==
2507 12:18:22.889653 Final DQ duty delay cell = 0
2508 12:18:22.891962 [0] MAX Duty = 5093%(X100), DQS PI = 8
2509 12:18:22.895451 [0] MIN Duty = 4969%(X100), DQS PI = 0
2510 12:18:22.895949 [0] AVG Duty = 5031%(X100)
2511 12:18:22.896316
2512 12:18:22.899070 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2513 12:18:22.902010
2514 12:18:22.905916 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2515 12:18:22.908471 [DutyScan_Calibration_Flow] ====Done====
2516 12:18:22.911932 nWR fixed to 30
2517 12:18:22.912486 [ModeRegInit_LP4] CH0 RK0
2518 12:18:22.914909 [ModeRegInit_LP4] CH0 RK1
2519 12:18:22.918816 [ModeRegInit_LP4] CH1 RK0
2520 12:18:22.922874 [ModeRegInit_LP4] CH1 RK1
2521 12:18:22.923433 match AC timing 7
2522 12:18:22.924794 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2523 12:18:22.932491 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2524 12:18:22.935266 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2525 12:18:22.941748 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2526 12:18:22.944879 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2527 12:18:22.945338 ==
2528 12:18:22.948277 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 12:18:22.951650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 12:18:22.952253 ==
2531 12:18:22.958897 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2532 12:18:22.965912 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2533 12:18:22.972026 [CA 0] Center 39 (9~70) winsize 62
2534 12:18:22.975389 [CA 1] Center 39 (9~69) winsize 61
2535 12:18:22.978729 [CA 2] Center 35 (5~66) winsize 62
2536 12:18:22.981860 [CA 3] Center 35 (4~66) winsize 63
2537 12:18:22.985508 [CA 4] Center 33 (4~63) winsize 60
2538 12:18:22.988561 [CA 5] Center 33 (3~63) winsize 61
2539 12:18:22.989127
2540 12:18:22.991817 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2541 12:18:22.992375
2542 12:18:22.995400 [CATrainingPosCal] consider 1 rank data
2543 12:18:22.999131 u2DelayCellTimex100 = 270/100 ps
2544 12:18:23.001986 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2545 12:18:23.008599 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2546 12:18:23.011628 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2547 12:18:23.015055 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2548 12:18:23.018102 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2549 12:18:23.021563 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2550 12:18:23.022125
2551 12:18:23.025285 CA PerBit enable=1, Macro0, CA PI delay=33
2552 12:18:23.025851
2553 12:18:23.028316 [CBTSetCACLKResult] CA Dly = 33
2554 12:18:23.028818 CS Dly: 8 (0~39)
2555 12:18:23.031443 ==
2556 12:18:23.034544 Dram Type= 6, Freq= 0, CH_0, rank 1
2557 12:18:23.038607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2558 12:18:23.039172 ==
2559 12:18:23.041695 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2560 12:18:23.048051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2561 12:18:23.058238 [CA 0] Center 39 (9~70) winsize 62
2562 12:18:23.061383 [CA 1] Center 39 (9~70) winsize 62
2563 12:18:23.064570 [CA 2] Center 35 (5~66) winsize 62
2564 12:18:23.067626 [CA 3] Center 34 (4~65) winsize 62
2565 12:18:23.071006 [CA 4] Center 33 (3~64) winsize 62
2566 12:18:23.074788 [CA 5] Center 33 (3~63) winsize 61
2567 12:18:23.075248
2568 12:18:23.078088 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2569 12:18:23.078639
2570 12:18:23.081032 [CATrainingPosCal] consider 2 rank data
2571 12:18:23.084262 u2DelayCellTimex100 = 270/100 ps
2572 12:18:23.088663 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2573 12:18:23.093884 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2574 12:18:23.097775 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2575 12:18:23.100580 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2576 12:18:23.104405 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2577 12:18:23.108111 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2578 12:18:23.108591
2579 12:18:23.111012 CA PerBit enable=1, Macro0, CA PI delay=33
2580 12:18:23.111562
2581 12:18:23.113714 [CBTSetCACLKResult] CA Dly = 33
2582 12:18:23.116955 CS Dly: 8 (0~40)
2583 12:18:23.117431
2584 12:18:23.120610 ----->DramcWriteLeveling(PI) begin...
2585 12:18:23.121175 ==
2586 12:18:23.124127 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 12:18:23.127330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 12:18:23.128007 ==
2589 12:18:23.130601 Write leveling (Byte 0): 34 => 34
2590 12:18:23.134286 Write leveling (Byte 1): 28 => 28
2591 12:18:23.137226 DramcWriteLeveling(PI) end<-----
2592 12:18:23.137750
2593 12:18:23.138279 ==
2594 12:18:23.140187 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 12:18:23.144187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 12:18:23.144650 ==
2597 12:18:23.147373 [Gating] SW mode calibration
2598 12:18:23.153775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2599 12:18:23.160561 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2600 12:18:23.164214 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2601 12:18:23.166868 0 15 4 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2602 12:18:23.173532 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 12:18:23.176879 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 12:18:23.180616 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 12:18:23.187098 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 12:18:23.190209 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2607 12:18:23.193800 0 15 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
2608 12:18:23.200230 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (1 0)
2609 12:18:23.204228 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 12:18:23.207117 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 12:18:23.213606 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 12:18:23.216578 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 12:18:23.220477 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 12:18:23.226658 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 12:18:23.230488 1 0 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
2616 12:18:23.234383 1 1 0 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2617 12:18:23.236708 1 1 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2618 12:18:23.243179 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 12:18:23.247062 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 12:18:23.249864 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 12:18:23.256645 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 12:18:23.259738 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 12:18:23.263368 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2624 12:18:23.269711 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2625 12:18:23.273449 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2626 12:18:23.277284 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 12:18:23.283230 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 12:18:23.286469 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 12:18:23.289640 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 12:18:23.296694 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 12:18:23.299712 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 12:18:23.303152 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 12:18:23.309935 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 12:18:23.313509 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 12:18:23.316025 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 12:18:23.323120 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 12:18:23.326748 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 12:18:23.329288 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2639 12:18:23.336189 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2640 12:18:23.339834 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2641 12:18:23.342868 Total UI for P1: 0, mck2ui 16
2642 12:18:23.345999 best dqsien dly found for B0: ( 1, 3, 26)
2643 12:18:23.349529 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2644 12:18:23.352904 Total UI for P1: 0, mck2ui 16
2645 12:18:23.356081 best dqsien dly found for B1: ( 1, 4, 0)
2646 12:18:23.359607 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2647 12:18:23.363439 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2648 12:18:23.363971
2649 12:18:23.369117 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2650 12:18:23.372394 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2651 12:18:23.372810 [Gating] SW calibration Done
2652 12:18:23.375854 ==
2653 12:18:23.376312 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 12:18:23.382917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 12:18:23.383336 ==
2656 12:18:23.383665 RX Vref Scan: 0
2657 12:18:23.384026
2658 12:18:23.385774 RX Vref 0 -> 0, step: 1
2659 12:18:23.386265
2660 12:18:23.389040 RX Delay -40 -> 252, step: 8
2661 12:18:23.392196 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2662 12:18:23.395511 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2663 12:18:23.399244 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2664 12:18:23.405647 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2665 12:18:23.409805 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2666 12:18:23.412024 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2667 12:18:23.415615 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2668 12:18:23.419282 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2669 12:18:23.425390 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2670 12:18:23.429099 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2671 12:18:23.432467 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2672 12:18:23.435086 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2673 12:18:23.439016 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2674 12:18:23.445389 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2675 12:18:23.449104 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2676 12:18:23.452046 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2677 12:18:23.452588 ==
2678 12:18:23.455456 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 12:18:23.459155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 12:18:23.462756 ==
2681 12:18:23.463271 DQS Delay:
2682 12:18:23.463602 DQS0 = 0, DQS1 = 0
2683 12:18:23.465138 DQM Delay:
2684 12:18:23.465549 DQM0 = 119, DQM1 = 107
2685 12:18:23.468800 DQ Delay:
2686 12:18:23.471835 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2687 12:18:23.474884 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2688 12:18:23.478560 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2689 12:18:23.481848 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2690 12:18:23.482406
2691 12:18:23.482778
2692 12:18:23.483197 ==
2693 12:18:23.484975 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 12:18:23.488150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 12:18:23.488610 ==
2696 12:18:23.491453
2697 12:18:23.491966
2698 12:18:23.492406 TX Vref Scan disable
2699 12:18:23.494930 == TX Byte 0 ==
2700 12:18:23.497951 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2701 12:18:23.502179 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2702 12:18:23.505059 == TX Byte 1 ==
2703 12:18:23.508619 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2704 12:18:23.511588 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2705 12:18:23.512047 ==
2706 12:18:23.514576 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 12:18:23.520867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 12:18:23.521293 ==
2709 12:18:23.533317 TX Vref=22, minBit 5, minWin=25, winSum=416
2710 12:18:23.536041 TX Vref=24, minBit 1, minWin=26, winSum=427
2711 12:18:23.539829 TX Vref=26, minBit 8, minWin=26, winSum=431
2712 12:18:23.542774 TX Vref=28, minBit 13, minWin=25, winSum=430
2713 12:18:23.546098 TX Vref=30, minBit 13, minWin=26, winSum=434
2714 12:18:23.553175 TX Vref=32, minBit 5, minWin=26, winSum=430
2715 12:18:23.556107 [TxChooseVref] Worse bit 13, Min win 26, Win sum 434, Final Vref 30
2716 12:18:23.556665
2717 12:18:23.559180 Final TX Range 1 Vref 30
2718 12:18:23.559788
2719 12:18:23.560168 ==
2720 12:18:23.562680 Dram Type= 6, Freq= 0, CH_0, rank 0
2721 12:18:23.565741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2722 12:18:23.568704 ==
2723 12:18:23.569159
2724 12:18:23.569518
2725 12:18:23.569852 TX Vref Scan disable
2726 12:18:23.572885 == TX Byte 0 ==
2727 12:18:23.575729 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2728 12:18:23.582666 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2729 12:18:23.583224 == TX Byte 1 ==
2730 12:18:23.585780 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2731 12:18:23.589208 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2732 12:18:23.592585
2733 12:18:23.593136 [DATLAT]
2734 12:18:23.593501 Freq=1200, CH0 RK0
2735 12:18:23.593841
2736 12:18:23.595977 DATLAT Default: 0xd
2737 12:18:23.596567 0, 0xFFFF, sum = 0
2738 12:18:23.599245 1, 0xFFFF, sum = 0
2739 12:18:23.599864 2, 0xFFFF, sum = 0
2740 12:18:23.602708 3, 0xFFFF, sum = 0
2741 12:18:23.605814 4, 0xFFFF, sum = 0
2742 12:18:23.606379 5, 0xFFFF, sum = 0
2743 12:18:23.609205 6, 0xFFFF, sum = 0
2744 12:18:23.609669 7, 0xFFFF, sum = 0
2745 12:18:23.612417 8, 0xFFFF, sum = 0
2746 12:18:23.612922 9, 0xFFFF, sum = 0
2747 12:18:23.616054 10, 0xFFFF, sum = 0
2748 12:18:23.616519 11, 0xFFFF, sum = 0
2749 12:18:23.619377 12, 0x0, sum = 1
2750 12:18:23.619996 13, 0x0, sum = 2
2751 12:18:23.622103 14, 0x0, sum = 3
2752 12:18:23.622566 15, 0x0, sum = 4
2753 12:18:23.622935 best_step = 13
2754 12:18:23.626892
2755 12:18:23.627453 ==
2756 12:18:23.628872 Dram Type= 6, Freq= 0, CH_0, rank 0
2757 12:18:23.632647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2758 12:18:23.633213 ==
2759 12:18:23.633582 RX Vref Scan: 1
2760 12:18:23.633919
2761 12:18:23.635785 Set Vref Range= 32 -> 127
2762 12:18:23.636349
2763 12:18:23.639115 RX Vref 32 -> 127, step: 1
2764 12:18:23.639666
2765 12:18:23.642935 RX Delay -21 -> 252, step: 4
2766 12:18:23.643537
2767 12:18:23.646010 Set Vref, RX VrefLevel [Byte0]: 32
2768 12:18:23.649040 [Byte1]: 32
2769 12:18:23.649504
2770 12:18:23.652548 Set Vref, RX VrefLevel [Byte0]: 33
2771 12:18:23.655646 [Byte1]: 33
2772 12:18:23.659038
2773 12:18:23.659492 Set Vref, RX VrefLevel [Byte0]: 34
2774 12:18:23.662669 [Byte1]: 34
2775 12:18:23.667174
2776 12:18:23.667719 Set Vref, RX VrefLevel [Byte0]: 35
2777 12:18:23.669974 [Byte1]: 35
2778 12:18:23.675093
2779 12:18:23.675648 Set Vref, RX VrefLevel [Byte0]: 36
2780 12:18:23.678132 [Byte1]: 36
2781 12:18:23.682504
2782 12:18:23.683056 Set Vref, RX VrefLevel [Byte0]: 37
2783 12:18:23.686663 [Byte1]: 37
2784 12:18:23.691035
2785 12:18:23.691592 Set Vref, RX VrefLevel [Byte0]: 38
2786 12:18:23.694251 [Byte1]: 38
2787 12:18:23.699143
2788 12:18:23.699747 Set Vref, RX VrefLevel [Byte0]: 39
2789 12:18:23.701814 [Byte1]: 39
2790 12:18:23.706608
2791 12:18:23.707158 Set Vref, RX VrefLevel [Byte0]: 40
2792 12:18:23.710035 [Byte1]: 40
2793 12:18:23.715129
2794 12:18:23.715738 Set Vref, RX VrefLevel [Byte0]: 41
2795 12:18:23.717743 [Byte1]: 41
2796 12:18:23.722165
2797 12:18:23.722713 Set Vref, RX VrefLevel [Byte0]: 42
2798 12:18:23.726005 [Byte1]: 42
2799 12:18:23.730219
2800 12:18:23.730779 Set Vref, RX VrefLevel [Byte0]: 43
2801 12:18:23.734097 [Byte1]: 43
2802 12:18:23.738304
2803 12:18:23.738764 Set Vref, RX VrefLevel [Byte0]: 44
2804 12:18:23.742163 [Byte1]: 44
2805 12:18:23.745999
2806 12:18:23.746550 Set Vref, RX VrefLevel [Byte0]: 45
2807 12:18:23.752644 [Byte1]: 45
2808 12:18:23.753203
2809 12:18:23.756856 Set Vref, RX VrefLevel [Byte0]: 46
2810 12:18:23.759419 [Byte1]: 46
2811 12:18:23.760024
2812 12:18:23.762127 Set Vref, RX VrefLevel [Byte0]: 47
2813 12:18:23.765329 [Byte1]: 47
2814 12:18:23.770525
2815 12:18:23.771085 Set Vref, RX VrefLevel [Byte0]: 48
2816 12:18:23.773051 [Byte1]: 48
2817 12:18:23.777957
2818 12:18:23.778539 Set Vref, RX VrefLevel [Byte0]: 49
2819 12:18:23.780976 [Byte1]: 49
2820 12:18:23.785897
2821 12:18:23.786450 Set Vref, RX VrefLevel [Byte0]: 50
2822 12:18:23.789314 [Byte1]: 50
2823 12:18:23.794230
2824 12:18:23.794685 Set Vref, RX VrefLevel [Byte0]: 51
2825 12:18:23.797089 [Byte1]: 51
2826 12:18:23.801662
2827 12:18:23.802231 Set Vref, RX VrefLevel [Byte0]: 52
2828 12:18:23.805493 [Byte1]: 52
2829 12:18:23.809610
2830 12:18:23.810168 Set Vref, RX VrefLevel [Byte0]: 53
2831 12:18:23.813002 [Byte1]: 53
2832 12:18:23.817933
2833 12:18:23.818493 Set Vref, RX VrefLevel [Byte0]: 54
2834 12:18:23.821121 [Byte1]: 54
2835 12:18:23.825627
2836 12:18:23.826183 Set Vref, RX VrefLevel [Byte0]: 55
2837 12:18:23.829136 [Byte1]: 55
2838 12:18:23.833752
2839 12:18:23.834307 Set Vref, RX VrefLevel [Byte0]: 56
2840 12:18:23.836757 [Byte1]: 56
2841 12:18:23.841229
2842 12:18:23.841780 Set Vref, RX VrefLevel [Byte0]: 57
2843 12:18:23.844636 [Byte1]: 57
2844 12:18:23.849432
2845 12:18:23.849889 Set Vref, RX VrefLevel [Byte0]: 58
2846 12:18:23.852558 [Byte1]: 58
2847 12:18:23.858223
2848 12:18:23.858774 Set Vref, RX VrefLevel [Byte0]: 59
2849 12:18:23.860472 [Byte1]: 59
2850 12:18:23.864818
2851 12:18:23.865275 Set Vref, RX VrefLevel [Byte0]: 60
2852 12:18:23.868289 [Byte1]: 60
2853 12:18:23.872857
2854 12:18:23.873430 Set Vref, RX VrefLevel [Byte0]: 61
2855 12:18:23.876246 [Byte1]: 61
2856 12:18:23.880950
2857 12:18:23.881498 Set Vref, RX VrefLevel [Byte0]: 62
2858 12:18:23.884447 [Byte1]: 62
2859 12:18:23.888468
2860 12:18:23.888944 Set Vref, RX VrefLevel [Byte0]: 63
2861 12:18:23.892255 [Byte1]: 63
2862 12:18:23.896696
2863 12:18:23.897259 Set Vref, RX VrefLevel [Byte0]: 64
2864 12:18:23.900130 [Byte1]: 64
2865 12:18:23.904940
2866 12:18:23.905491 Set Vref, RX VrefLevel [Byte0]: 65
2867 12:18:23.908282 [Byte1]: 65
2868 12:18:23.912618
2869 12:18:23.913201 Set Vref, RX VrefLevel [Byte0]: 66
2870 12:18:23.915880 [Byte1]: 66
2871 12:18:23.921223
2872 12:18:23.921794 Set Vref, RX VrefLevel [Byte0]: 67
2873 12:18:23.924279 [Byte1]: 67
2874 12:18:23.928700
2875 12:18:23.929262 Set Vref, RX VrefLevel [Byte0]: 68
2876 12:18:23.931604 [Byte1]: 68
2877 12:18:23.937011
2878 12:18:23.937566 Set Vref, RX VrefLevel [Byte0]: 69
2879 12:18:23.939872 [Byte1]: 69
2880 12:18:23.944667
2881 12:18:23.945226 Set Vref, RX VrefLevel [Byte0]: 70
2882 12:18:23.947842 [Byte1]: 70
2883 12:18:23.952620
2884 12:18:23.953171 Set Vref, RX VrefLevel [Byte0]: 71
2885 12:18:23.955507 [Byte1]: 71
2886 12:18:23.960228
2887 12:18:23.960781 Set Vref, RX VrefLevel [Byte0]: 72
2888 12:18:23.963609 [Byte1]: 72
2889 12:18:23.968137
2890 12:18:23.968685 Set Vref, RX VrefLevel [Byte0]: 73
2891 12:18:23.971502 [Byte1]: 73
2892 12:18:23.976761
2893 12:18:23.977312 Set Vref, RX VrefLevel [Byte0]: 74
2894 12:18:23.979781 [Byte1]: 74
2895 12:18:23.983724
2896 12:18:23.984184 Set Vref, RX VrefLevel [Byte0]: 75
2897 12:18:23.987599 [Byte1]: 75
2898 12:18:23.991945
2899 12:18:23.992502 Set Vref, RX VrefLevel [Byte0]: 76
2900 12:18:23.995140 [Byte1]: 76
2901 12:18:23.999906
2902 12:18:24.000461 Set Vref, RX VrefLevel [Byte0]: 77
2903 12:18:24.003245 [Byte1]: 77
2904 12:18:24.008970
2905 12:18:24.009557 Final RX Vref Byte 0 = 60 to rank0
2906 12:18:24.011149 Final RX Vref Byte 1 = 48 to rank0
2907 12:18:24.014349 Final RX Vref Byte 0 = 60 to rank1
2908 12:18:24.018351 Final RX Vref Byte 1 = 48 to rank1==
2909 12:18:24.020919 Dram Type= 6, Freq= 0, CH_0, rank 0
2910 12:18:24.027696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 12:18:24.028159 ==
2912 12:18:24.028519 DQS Delay:
2913 12:18:24.028853 DQS0 = 0, DQS1 = 0
2914 12:18:24.031203 DQM Delay:
2915 12:18:24.031658 DQM0 = 119, DQM1 = 106
2916 12:18:24.034377 DQ Delay:
2917 12:18:24.037622 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2918 12:18:24.041761 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
2919 12:18:24.044155 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
2920 12:18:24.047936 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =116
2921 12:18:24.048497
2922 12:18:24.048860
2923 12:18:24.057796 [DQSOSCAuto] RK0, (LSB)MR18= 0xefa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps
2924 12:18:24.058361 CH0 RK0: MR19=403, MR18=EFA
2925 12:18:24.064363 CH0_RK0: MR19=0x403, MR18=0xEFA, DQSOSC=404, MR23=63, INC=40, DEC=26
2926 12:18:24.064928
2927 12:18:24.067724 ----->DramcWriteLeveling(PI) begin...
2928 12:18:24.068291 ==
2929 12:18:24.071029 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 12:18:24.074492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 12:18:24.077555 ==
2932 12:18:24.078014 Write leveling (Byte 0): 31 => 31
2933 12:18:24.081697 Write leveling (Byte 1): 31 => 31
2934 12:18:24.084363 DramcWriteLeveling(PI) end<-----
2935 12:18:24.084836
2936 12:18:24.085196 ==
2937 12:18:24.087228 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 12:18:24.094016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 12:18:24.094563 ==
2940 12:18:24.094927 [Gating] SW mode calibration
2941 12:18:24.104386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2942 12:18:24.107219 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2943 12:18:24.114567 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2944 12:18:24.117572 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2945 12:18:24.120368 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2946 12:18:24.127333 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2947 12:18:24.130286 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2948 12:18:24.134572 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2949 12:18:24.137364 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2950 12:18:24.144073 0 15 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2951 12:18:24.146860 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (1 0)
2952 12:18:24.151383 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2953 12:18:24.157172 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2954 12:18:24.160537 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2955 12:18:24.163540 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2956 12:18:24.170979 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2957 12:18:24.173628 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 12:18:24.176843 1 0 28 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
2959 12:18:24.183529 1 1 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
2960 12:18:24.186975 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 12:18:24.190236 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2962 12:18:24.197255 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 12:18:24.201170 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 12:18:24.203787 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2965 12:18:24.210094 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 12:18:24.213337 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2967 12:18:24.216831 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2968 12:18:24.222976 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 12:18:24.226430 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 12:18:24.229611 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 12:18:24.236367 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 12:18:24.239624 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 12:18:24.243148 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 12:18:24.250448 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 12:18:24.252820 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 12:18:24.256009 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 12:18:24.263101 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 12:18:24.265934 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 12:18:24.269444 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 12:18:24.276129 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 12:18:24.280340 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 12:18:24.282387 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2983 12:18:24.289682 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2984 12:18:24.290253 Total UI for P1: 0, mck2ui 16
2985 12:18:24.295780 best dqsien dly found for B0: ( 1, 3, 28)
2986 12:18:24.299722 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2987 12:18:24.302676 Total UI for P1: 0, mck2ui 16
2988 12:18:24.306153 best dqsien dly found for B1: ( 1, 4, 0)
2989 12:18:24.309428 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2990 12:18:24.312753 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2991 12:18:24.313211
2992 12:18:24.315892 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2993 12:18:24.319179 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2994 12:18:24.322546 [Gating] SW calibration Done
2995 12:18:24.323129 ==
2996 12:18:24.325789 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 12:18:24.330019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 12:18:24.330577 ==
2999 12:18:24.332228 RX Vref Scan: 0
3000 12:18:24.332685
3001 12:18:24.335593 RX Vref 0 -> 0, step: 1
3002 12:18:24.336088
3003 12:18:24.336453 RX Delay -40 -> 252, step: 8
3004 12:18:24.342223 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3005 12:18:24.345641 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3006 12:18:24.348917 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3007 12:18:24.352171 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3008 12:18:24.355777 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3009 12:18:24.362410 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3010 12:18:24.366112 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3011 12:18:24.369307 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3012 12:18:24.373361 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3013 12:18:24.376274 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3014 12:18:24.381905 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3015 12:18:24.385225 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3016 12:18:24.388646 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3017 12:18:24.391927 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3018 12:18:24.398537 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3019 12:18:24.402828 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3020 12:18:24.403386 ==
3021 12:18:24.405345 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 12:18:24.408526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 12:18:24.409089 ==
3024 12:18:24.409455 DQS Delay:
3025 12:18:24.412382 DQS0 = 0, DQS1 = 0
3026 12:18:24.412843 DQM Delay:
3027 12:18:24.415359 DQM0 = 116, DQM1 = 108
3028 12:18:24.415966 DQ Delay:
3029 12:18:24.418576 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3030 12:18:24.422053 DQ4 =115, DQ5 =111, DQ6 =127, DQ7 =123
3031 12:18:24.425035 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3032 12:18:24.429260 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3033 12:18:24.431385
3034 12:18:24.431878
3035 12:18:24.432244 ==
3036 12:18:24.435171 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 12:18:24.439140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 12:18:24.439735 ==
3039 12:18:24.440111
3040 12:18:24.440449
3041 12:18:24.441563 TX Vref Scan disable
3042 12:18:24.442022 == TX Byte 0 ==
3043 12:18:24.447820 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3044 12:18:24.451842 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3045 12:18:24.452303 == TX Byte 1 ==
3046 12:18:24.458693 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3047 12:18:24.461428 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3048 12:18:24.462016 ==
3049 12:18:24.465181 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 12:18:24.467789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 12:18:24.468254 ==
3052 12:18:24.481102 TX Vref=22, minBit 1, minWin=25, winSum=414
3053 12:18:24.484439 TX Vref=24, minBit 5, minWin=25, winSum=419
3054 12:18:24.487200 TX Vref=26, minBit 13, minWin=25, winSum=427
3055 12:18:24.490572 TX Vref=28, minBit 0, minWin=27, winSum=432
3056 12:18:24.494027 TX Vref=30, minBit 9, minWin=26, winSum=430
3057 12:18:24.500585 TX Vref=32, minBit 12, minWin=26, winSum=429
3058 12:18:24.504393 [TxChooseVref] Worse bit 0, Min win 27, Win sum 432, Final Vref 28
3059 12:18:24.504811
3060 12:18:24.506935 Final TX Range 1 Vref 28
3061 12:18:24.507350
3062 12:18:24.507705 ==
3063 12:18:24.510825 Dram Type= 6, Freq= 0, CH_0, rank 1
3064 12:18:24.513708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 12:18:24.514126 ==
3066 12:18:24.517125
3067 12:18:24.517539
3068 12:18:24.517863 TX Vref Scan disable
3069 12:18:24.520218 == TX Byte 0 ==
3070 12:18:24.523811 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3071 12:18:24.530317 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3072 12:18:24.530821 == TX Byte 1 ==
3073 12:18:24.534121 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3074 12:18:24.540180 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3075 12:18:24.540685
3076 12:18:24.541015 [DATLAT]
3077 12:18:24.541322 Freq=1200, CH0 RK1
3078 12:18:24.541624
3079 12:18:24.544148 DATLAT Default: 0xd
3080 12:18:24.546727 0, 0xFFFF, sum = 0
3081 12:18:24.547251 1, 0xFFFF, sum = 0
3082 12:18:24.550065 2, 0xFFFF, sum = 0
3083 12:18:24.550489 3, 0xFFFF, sum = 0
3084 12:18:24.553419 4, 0xFFFF, sum = 0
3085 12:18:24.553941 5, 0xFFFF, sum = 0
3086 12:18:24.557592 6, 0xFFFF, sum = 0
3087 12:18:24.558118 7, 0xFFFF, sum = 0
3088 12:18:24.560191 8, 0xFFFF, sum = 0
3089 12:18:24.560616 9, 0xFFFF, sum = 0
3090 12:18:24.563225 10, 0xFFFF, sum = 0
3091 12:18:24.563783 11, 0xFFFF, sum = 0
3092 12:18:24.566506 12, 0x0, sum = 1
3093 12:18:24.566929 13, 0x0, sum = 2
3094 12:18:24.569944 14, 0x0, sum = 3
3095 12:18:24.570464 15, 0x0, sum = 4
3096 12:18:24.573464 best_step = 13
3097 12:18:24.573977
3098 12:18:24.574311 ==
3099 12:18:24.576803 Dram Type= 6, Freq= 0, CH_0, rank 1
3100 12:18:24.579838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 12:18:24.580354 ==
3102 12:18:24.583598 RX Vref Scan: 0
3103 12:18:24.584201
3104 12:18:24.584544 RX Vref 0 -> 0, step: 1
3105 12:18:24.584856
3106 12:18:24.587030 RX Delay -21 -> 252, step: 4
3107 12:18:24.593105 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3108 12:18:24.596350 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3109 12:18:24.599666 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3110 12:18:24.603250 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3111 12:18:24.606356 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3112 12:18:24.613296 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3113 12:18:24.616307 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3114 12:18:24.620051 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3115 12:18:24.623518 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3116 12:18:24.626008 iDelay=199, Bit 9, Center 92 (23 ~ 162) 140
3117 12:18:24.632773 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3118 12:18:24.636288 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3119 12:18:24.639811 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3120 12:18:24.642687 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3121 12:18:24.646326 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3122 12:18:24.654104 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3123 12:18:24.654794 ==
3124 12:18:24.656124 Dram Type= 6, Freq= 0, CH_0, rank 1
3125 12:18:24.659011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 12:18:24.659470 ==
3127 12:18:24.659838 DQS Delay:
3128 12:18:24.662241 DQS0 = 0, DQS1 = 0
3129 12:18:24.662894 DQM Delay:
3130 12:18:24.666150 DQM0 = 116, DQM1 = 107
3131 12:18:24.666637 DQ Delay:
3132 12:18:24.668916 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3133 12:18:24.672678 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3134 12:18:24.675902 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3135 12:18:24.678793 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3136 12:18:24.679048
3137 12:18:24.679277
3138 12:18:24.688956 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3139 12:18:24.692081 CH0 RK1: MR19=403, MR18=BE6
3140 12:18:24.695597 CH0_RK1: MR19=0x403, MR18=0xBE6, DQSOSC=405, MR23=63, INC=39, DEC=26
3141 12:18:24.698476 [RxdqsGatingPostProcess] freq 1200
3142 12:18:24.705015 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3143 12:18:24.708863 best DQS0 dly(2T, 0.5T) = (0, 11)
3144 12:18:24.712050 best DQS1 dly(2T, 0.5T) = (0, 12)
3145 12:18:24.715914 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3146 12:18:24.719454 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3147 12:18:24.721921 best DQS0 dly(2T, 0.5T) = (0, 11)
3148 12:18:24.725676 best DQS1 dly(2T, 0.5T) = (0, 12)
3149 12:18:24.728534 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3150 12:18:24.732193 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3151 12:18:24.736003 Pre-setting of DQS Precalculation
3152 12:18:24.738646 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3153 12:18:24.738807 ==
3154 12:18:24.742535 Dram Type= 6, Freq= 0, CH_1, rank 0
3155 12:18:24.746058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 12:18:24.746218 ==
3157 12:18:24.751888 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3158 12:18:24.758839 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3159 12:18:24.766967 [CA 0] Center 37 (7~67) winsize 61
3160 12:18:24.769892 [CA 1] Center 37 (7~68) winsize 62
3161 12:18:24.772885 [CA 2] Center 34 (4~64) winsize 61
3162 12:18:24.776134 [CA 3] Center 33 (3~64) winsize 62
3163 12:18:24.779455 [CA 4] Center 34 (4~64) winsize 61
3164 12:18:24.783165 [CA 5] Center 33 (3~64) winsize 62
3165 12:18:24.783391
3166 12:18:24.785908 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3167 12:18:24.786115
3168 12:18:24.789265 [CATrainingPosCal] consider 1 rank data
3169 12:18:24.793372 u2DelayCellTimex100 = 270/100 ps
3170 12:18:24.795889 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3171 12:18:24.802862 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3172 12:18:24.806244 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3173 12:18:24.809636 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3174 12:18:24.813226 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3175 12:18:24.815916 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3176 12:18:24.816382
3177 12:18:24.819604 CA PerBit enable=1, Macro0, CA PI delay=33
3178 12:18:24.820093
3179 12:18:24.822879 [CBTSetCACLKResult] CA Dly = 33
3180 12:18:24.827183 CS Dly: 6 (0~37)
3181 12:18:24.827640 ==
3182 12:18:24.829606 Dram Type= 6, Freq= 0, CH_1, rank 1
3183 12:18:24.833169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 12:18:24.833632 ==
3185 12:18:24.840104 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3186 12:18:24.842990 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3187 12:18:24.853393 [CA 0] Center 37 (7~68) winsize 62
3188 12:18:24.855638 [CA 1] Center 38 (8~68) winsize 61
3189 12:18:24.859668 [CA 2] Center 34 (4~65) winsize 62
3190 12:18:24.861880 [CA 3] Center 33 (3~64) winsize 62
3191 12:18:24.865813 [CA 4] Center 34 (4~65) winsize 62
3192 12:18:24.869590 [CA 5] Center 33 (3~64) winsize 62
3193 12:18:24.870151
3194 12:18:24.872254 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3195 12:18:24.872715
3196 12:18:24.875247 [CATrainingPosCal] consider 2 rank data
3197 12:18:24.878675 u2DelayCellTimex100 = 270/100 ps
3198 12:18:24.882035 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3199 12:18:24.885109 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3200 12:18:24.892177 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3201 12:18:24.895222 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3202 12:18:24.898951 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3203 12:18:24.902355 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3204 12:18:24.902874
3205 12:18:24.905690 CA PerBit enable=1, Macro0, CA PI delay=33
3206 12:18:24.906221
3207 12:18:24.908359 [CBTSetCACLKResult] CA Dly = 33
3208 12:18:24.908775 CS Dly: 7 (0~40)
3209 12:18:24.909104
3210 12:18:24.912666 ----->DramcWriteLeveling(PI) begin...
3211 12:18:24.915530 ==
3212 12:18:24.918821 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 12:18:24.921929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 12:18:24.922349 ==
3215 12:18:24.925182 Write leveling (Byte 0): 24 => 24
3216 12:18:24.928299 Write leveling (Byte 1): 27 => 27
3217 12:18:24.931936 DramcWriteLeveling(PI) end<-----
3218 12:18:24.932402
3219 12:18:24.932826 ==
3220 12:18:24.936795 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 12:18:24.939046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 12:18:24.939470 ==
3223 12:18:24.942497 [Gating] SW mode calibration
3224 12:18:24.948761 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3225 12:18:24.955594 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3226 12:18:24.958914 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3227 12:18:24.961814 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3228 12:18:24.968354 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3229 12:18:24.971736 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3230 12:18:24.974791 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3231 12:18:24.981235 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3232 12:18:24.984481 0 15 24 | B1->B0 | 3434 3333 | 0 1 | (0 1) (1 0)
3233 12:18:24.988591 0 15 28 | B1->B0 | 2929 2323 | 1 0 | (1 0) (1 0)
3234 12:18:24.994250 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3235 12:18:24.997912 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3236 12:18:25.001094 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3237 12:18:25.008432 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3238 12:18:25.011415 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3239 12:18:25.014679 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3240 12:18:25.017722 1 0 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
3241 12:18:25.024916 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3242 12:18:25.027782 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3243 12:18:25.031645 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3244 12:18:25.038192 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3245 12:18:25.041157 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 12:18:25.044719 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3247 12:18:25.051505 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3248 12:18:25.054876 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3249 12:18:25.058068 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3250 12:18:25.065031 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 12:18:25.068224 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 12:18:25.071595 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 12:18:25.078731 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 12:18:25.081812 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 12:18:25.084998 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 12:18:25.091833 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 12:18:25.094591 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 12:18:25.098105 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 12:18:25.104313 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 12:18:25.108026 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 12:18:25.111210 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 12:18:25.117659 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 12:18:25.121019 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 12:18:25.124655 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3265 12:18:25.130948 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3266 12:18:25.131505 Total UI for P1: 0, mck2ui 16
3267 12:18:25.137826 best dqsien dly found for B0: ( 1, 3, 24)
3268 12:18:25.138381 Total UI for P1: 0, mck2ui 16
3269 12:18:25.141402 best dqsien dly found for B1: ( 1, 3, 24)
3270 12:18:25.148057 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3271 12:18:25.151272 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3272 12:18:25.151918
3273 12:18:25.154564 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3274 12:18:25.158289 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3275 12:18:25.160748 [Gating] SW calibration Done
3276 12:18:25.161214 ==
3277 12:18:25.164890 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 12:18:25.167561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 12:18:25.168164 ==
3280 12:18:25.171049 RX Vref Scan: 0
3281 12:18:25.171596
3282 12:18:25.172014 RX Vref 0 -> 0, step: 1
3283 12:18:25.172368
3284 12:18:25.174045 RX Delay -40 -> 252, step: 8
3285 12:18:25.177395 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3286 12:18:25.184556 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3287 12:18:25.187779 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3288 12:18:25.190579 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3289 12:18:25.194143 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3290 12:18:25.197373 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3291 12:18:25.200985 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3292 12:18:25.207215 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3293 12:18:25.211734 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3294 12:18:25.213700 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3295 12:18:25.218003 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3296 12:18:25.221045 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3297 12:18:25.227617 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3298 12:18:25.230447 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3299 12:18:25.234266 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3300 12:18:25.237315 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3301 12:18:25.237876 ==
3302 12:18:25.240633 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 12:18:25.247775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 12:18:25.248335 ==
3305 12:18:25.248706 DQS Delay:
3306 12:18:25.250618 DQS0 = 0, DQS1 = 0
3307 12:18:25.251078 DQM Delay:
3308 12:18:25.251447 DQM0 = 117, DQM1 = 110
3309 12:18:25.254450 DQ Delay:
3310 12:18:25.257142 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3311 12:18:25.260399 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3312 12:18:25.264649 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =99
3313 12:18:25.266909 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3314 12:18:25.267452
3315 12:18:25.267852
3316 12:18:25.268195 ==
3317 12:18:25.271180 Dram Type= 6, Freq= 0, CH_1, rank 0
3318 12:18:25.273616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3319 12:18:25.276976 ==
3320 12:18:25.277527
3321 12:18:25.277893
3322 12:18:25.278237 TX Vref Scan disable
3323 12:18:25.280267 == TX Byte 0 ==
3324 12:18:25.283662 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3325 12:18:25.286993 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3326 12:18:25.290423 == TX Byte 1 ==
3327 12:18:25.294278 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3328 12:18:25.297337 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3329 12:18:25.300640 ==
3330 12:18:25.303651 Dram Type= 6, Freq= 0, CH_1, rank 0
3331 12:18:25.306686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3332 12:18:25.307465 ==
3333 12:18:25.318061 TX Vref=22, minBit 8, minWin=25, winSum=415
3334 12:18:25.320892 TX Vref=24, minBit 9, minWin=25, winSum=417
3335 12:18:25.324210 TX Vref=26, minBit 9, minWin=25, winSum=429
3336 12:18:25.328318 TX Vref=28, minBit 8, minWin=25, winSum=428
3337 12:18:25.331132 TX Vref=30, minBit 9, minWin=25, winSum=432
3338 12:18:25.337893 TX Vref=32, minBit 9, minWin=25, winSum=425
3339 12:18:25.340936 [TxChooseVref] Worse bit 9, Min win 25, Win sum 432, Final Vref 30
3340 12:18:25.341402
3341 12:18:25.344077 Final TX Range 1 Vref 30
3342 12:18:25.344542
3343 12:18:25.344906 ==
3344 12:18:25.347820 Dram Type= 6, Freq= 0, CH_1, rank 0
3345 12:18:25.351231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3346 12:18:25.355206 ==
3347 12:18:25.355825
3348 12:18:25.356207
3349 12:18:25.356548 TX Vref Scan disable
3350 12:18:25.357574 == TX Byte 0 ==
3351 12:18:25.361219 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3352 12:18:25.364367 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3353 12:18:25.367523 == TX Byte 1 ==
3354 12:18:25.370724 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3355 12:18:25.377852 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3356 12:18:25.378406
3357 12:18:25.378771 [DATLAT]
3358 12:18:25.379110 Freq=1200, CH1 RK0
3359 12:18:25.379458
3360 12:18:25.380720 DATLAT Default: 0xd
3361 12:18:25.381176 0, 0xFFFF, sum = 0
3362 12:18:25.384315 1, 0xFFFF, sum = 0
3363 12:18:25.384780 2, 0xFFFF, sum = 0
3364 12:18:25.387792 3, 0xFFFF, sum = 0
3365 12:18:25.390831 4, 0xFFFF, sum = 0
3366 12:18:25.391252 5, 0xFFFF, sum = 0
3367 12:18:25.394031 6, 0xFFFF, sum = 0
3368 12:18:25.394453 7, 0xFFFF, sum = 0
3369 12:18:25.397339 8, 0xFFFF, sum = 0
3370 12:18:25.397758 9, 0xFFFF, sum = 0
3371 12:18:25.401039 10, 0xFFFF, sum = 0
3372 12:18:25.401600 11, 0xFFFF, sum = 0
3373 12:18:25.403952 12, 0x0, sum = 1
3374 12:18:25.404374 13, 0x0, sum = 2
3375 12:18:25.407174 14, 0x0, sum = 3
3376 12:18:25.407596 15, 0x0, sum = 4
3377 12:18:25.410568 best_step = 13
3378 12:18:25.410980
3379 12:18:25.411306 ==
3380 12:18:25.414879 Dram Type= 6, Freq= 0, CH_1, rank 0
3381 12:18:25.417113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3382 12:18:25.417539 ==
3383 12:18:25.417870 RX Vref Scan: 1
3384 12:18:25.418175
3385 12:18:25.421210 Set Vref Range= 32 -> 127
3386 12:18:25.421760
3387 12:18:25.423839 RX Vref 32 -> 127, step: 1
3388 12:18:25.424256
3389 12:18:25.426855 RX Delay -21 -> 252, step: 4
3390 12:18:25.427273
3391 12:18:25.430172 Set Vref, RX VrefLevel [Byte0]: 32
3392 12:18:25.433681 [Byte1]: 32
3393 12:18:25.434111
3394 12:18:25.438070 Set Vref, RX VrefLevel [Byte0]: 33
3395 12:18:25.440590 [Byte1]: 33
3396 12:18:25.444347
3397 12:18:25.444867 Set Vref, RX VrefLevel [Byte0]: 34
3398 12:18:25.447458 [Byte1]: 34
3399 12:18:25.451740
3400 12:18:25.452204 Set Vref, RX VrefLevel [Byte0]: 35
3401 12:18:25.455251 [Byte1]: 35
3402 12:18:25.460233
3403 12:18:25.460750 Set Vref, RX VrefLevel [Byte0]: 36
3404 12:18:25.463238 [Byte1]: 36
3405 12:18:25.467572
3406 12:18:25.468120 Set Vref, RX VrefLevel [Byte0]: 37
3407 12:18:25.470858 [Byte1]: 37
3408 12:18:25.475667
3409 12:18:25.476172 Set Vref, RX VrefLevel [Byte0]: 38
3410 12:18:25.478965 [Byte1]: 38
3411 12:18:25.484368
3412 12:18:25.484915 Set Vref, RX VrefLevel [Byte0]: 39
3413 12:18:25.487147 [Byte1]: 39
3414 12:18:25.491415
3415 12:18:25.491940 Set Vref, RX VrefLevel [Byte0]: 40
3416 12:18:25.495425 [Byte1]: 40
3417 12:18:25.499451
3418 12:18:25.499958 Set Vref, RX VrefLevel [Byte0]: 41
3419 12:18:25.502699 [Byte1]: 41
3420 12:18:25.507503
3421 12:18:25.508147 Set Vref, RX VrefLevel [Byte0]: 42
3422 12:18:25.510570 [Byte1]: 42
3423 12:18:25.516188
3424 12:18:25.516734 Set Vref, RX VrefLevel [Byte0]: 43
3425 12:18:25.519142 [Byte1]: 43
3426 12:18:25.523791
3427 12:18:25.524250 Set Vref, RX VrefLevel [Byte0]: 44
3428 12:18:25.527339 [Byte1]: 44
3429 12:18:25.531422
3430 12:18:25.532075 Set Vref, RX VrefLevel [Byte0]: 45
3431 12:18:25.534340 [Byte1]: 45
3432 12:18:25.539432
3433 12:18:25.539945 Set Vref, RX VrefLevel [Byte0]: 46
3434 12:18:25.542100 [Byte1]: 46
3435 12:18:25.546776
3436 12:18:25.547277 Set Vref, RX VrefLevel [Byte0]: 47
3437 12:18:25.551224 [Byte1]: 47
3438 12:18:25.554613
3439 12:18:25.555024 Set Vref, RX VrefLevel [Byte0]: 48
3440 12:18:25.558735 [Byte1]: 48
3441 12:18:25.562538
3442 12:18:25.562948 Set Vref, RX VrefLevel [Byte0]: 49
3443 12:18:25.566033 [Byte1]: 49
3444 12:18:25.570820
3445 12:18:25.571324 Set Vref, RX VrefLevel [Byte0]: 50
3446 12:18:25.574101 [Byte1]: 50
3447 12:18:25.578647
3448 12:18:25.579116 Set Vref, RX VrefLevel [Byte0]: 51
3449 12:18:25.581605 [Byte1]: 51
3450 12:18:25.586611
3451 12:18:25.587021 Set Vref, RX VrefLevel [Byte0]: 52
3452 12:18:25.591003 [Byte1]: 52
3453 12:18:25.594650
3454 12:18:25.595091 Set Vref, RX VrefLevel [Byte0]: 53
3455 12:18:25.597368 [Byte1]: 53
3456 12:18:25.602356
3457 12:18:25.602776 Set Vref, RX VrefLevel [Byte0]: 54
3458 12:18:25.606096 [Byte1]: 54
3459 12:18:25.610984
3460 12:18:25.611399 Set Vref, RX VrefLevel [Byte0]: 55
3461 12:18:25.613334 [Byte1]: 55
3462 12:18:25.618367
3463 12:18:25.618878 Set Vref, RX VrefLevel [Byte0]: 56
3464 12:18:25.621572 [Byte1]: 56
3465 12:18:25.626893
3466 12:18:25.627590 Set Vref, RX VrefLevel [Byte0]: 57
3467 12:18:25.629227 [Byte1]: 57
3468 12:18:25.634085
3469 12:18:25.634532 Set Vref, RX VrefLevel [Byte0]: 58
3470 12:18:25.637397 [Byte1]: 58
3471 12:18:25.641612
3472 12:18:25.642121 Set Vref, RX VrefLevel [Byte0]: 59
3473 12:18:25.645337 [Byte1]: 59
3474 12:18:25.650028
3475 12:18:25.650532 Set Vref, RX VrefLevel [Byte0]: 60
3476 12:18:25.653132 [Byte1]: 60
3477 12:18:25.657568
3478 12:18:25.658098 Set Vref, RX VrefLevel [Byte0]: 61
3479 12:18:25.661949 [Byte1]: 61
3480 12:18:25.665691
3481 12:18:25.666111 Set Vref, RX VrefLevel [Byte0]: 62
3482 12:18:25.669127 [Byte1]: 62
3483 12:18:25.674560
3484 12:18:25.675069 Set Vref, RX VrefLevel [Byte0]: 63
3485 12:18:25.676664 [Byte1]: 63
3486 12:18:25.681597
3487 12:18:25.682105 Set Vref, RX VrefLevel [Byte0]: 64
3488 12:18:25.685918 [Byte1]: 64
3489 12:18:25.689444
3490 12:18:25.689905 Set Vref, RX VrefLevel [Byte0]: 65
3491 12:18:25.692869 [Byte1]: 65
3492 12:18:25.698301
3493 12:18:25.698809 Set Vref, RX VrefLevel [Byte0]: 66
3494 12:18:25.700607 [Byte1]: 66
3495 12:18:25.705630
3496 12:18:25.706141 Set Vref, RX VrefLevel [Byte0]: 67
3497 12:18:25.708938 [Byte1]: 67
3498 12:18:25.713301
3499 12:18:25.713812 Set Vref, RX VrefLevel [Byte0]: 68
3500 12:18:25.716589 [Byte1]: 68
3501 12:18:25.721176
3502 12:18:25.721704 Final RX Vref Byte 0 = 49 to rank0
3503 12:18:25.724298 Final RX Vref Byte 1 = 49 to rank0
3504 12:18:25.728039 Final RX Vref Byte 0 = 49 to rank1
3505 12:18:25.731242 Final RX Vref Byte 1 = 49 to rank1==
3506 12:18:25.734243 Dram Type= 6, Freq= 0, CH_1, rank 0
3507 12:18:25.741025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 12:18:25.741618 ==
3509 12:18:25.741964 DQS Delay:
3510 12:18:25.742275 DQS0 = 0, DQS1 = 0
3511 12:18:25.744420 DQM Delay:
3512 12:18:25.744838 DQM0 = 115, DQM1 = 108
3513 12:18:25.747818 DQ Delay:
3514 12:18:25.750994 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =110
3515 12:18:25.754555 DQ4 =114, DQ5 =126, DQ6 =124, DQ7 =112
3516 12:18:25.757558 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =98
3517 12:18:25.761032 DQ12 =116, DQ13 =116, DQ14 =118, DQ15 =116
3518 12:18:25.761548
3519 12:18:25.761882
3520 12:18:25.770619 [DQSOSCAuto] RK0, (LSB)MR18= 0x6fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps
3521 12:18:25.771126 CH1 RK0: MR19=403, MR18=6FA
3522 12:18:25.777839 CH1_RK0: MR19=0x403, MR18=0x6FA, DQSOSC=407, MR23=63, INC=39, DEC=26
3523 12:18:25.778346
3524 12:18:25.780640 ----->DramcWriteLeveling(PI) begin...
3525 12:18:25.781069 ==
3526 12:18:25.784357 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 12:18:25.787421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 12:18:25.790546 ==
3529 12:18:25.791057 Write leveling (Byte 0): 25 => 25
3530 12:18:25.794468 Write leveling (Byte 1): 28 => 28
3531 12:18:25.797054 DramcWriteLeveling(PI) end<-----
3532 12:18:25.797476
3533 12:18:25.797805 ==
3534 12:18:25.800996 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 12:18:25.807106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 12:18:25.807624 ==
3537 12:18:25.810165 [Gating] SW mode calibration
3538 12:18:25.817438 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3539 12:18:25.820191 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3540 12:18:25.827177 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3541 12:18:25.830570 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3542 12:18:25.834654 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3543 12:18:25.840214 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3544 12:18:25.843260 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3545 12:18:25.846997 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3546 12:18:25.853289 0 15 24 | B1->B0 | 3232 3434 | 0 1 | (0 1) (1 1)
3547 12:18:25.856673 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3548 12:18:25.860694 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3549 12:18:25.866806 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3550 12:18:25.869861 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3551 12:18:25.873019 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3552 12:18:25.879599 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3553 12:18:25.883554 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3554 12:18:25.886613 1 0 24 | B1->B0 | 3838 2828 | 1 0 | (0 0) (0 0)
3555 12:18:25.893663 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3556 12:18:25.896241 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3557 12:18:25.900404 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 12:18:25.906455 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 12:18:25.909640 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3560 12:18:25.912998 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3561 12:18:25.920648 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3562 12:18:25.922478 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3563 12:18:25.925942 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3564 12:18:25.932697 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 12:18:25.935618 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 12:18:25.939542 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 12:18:25.945752 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 12:18:25.948773 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 12:18:25.952547 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 12:18:25.959642 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 12:18:25.962448 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 12:18:25.966312 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 12:18:25.972325 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 12:18:25.975664 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 12:18:25.978964 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 12:18:25.985885 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 12:18:25.988784 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 12:18:25.992168 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3579 12:18:25.998680 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3580 12:18:25.999236 Total UI for P1: 0, mck2ui 16
3581 12:18:26.002760 best dqsien dly found for B1: ( 1, 3, 24)
3582 12:18:26.008382 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3583 12:18:26.011946 Total UI for P1: 0, mck2ui 16
3584 12:18:26.015186 best dqsien dly found for B0: ( 1, 3, 28)
3585 12:18:26.018619 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3586 12:18:26.021908 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3587 12:18:26.022373
3588 12:18:26.025114 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3589 12:18:26.028494 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3590 12:18:26.032174 [Gating] SW calibration Done
3591 12:18:26.032643 ==
3592 12:18:26.034858 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 12:18:26.038341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 12:18:26.038898 ==
3595 12:18:26.041331 RX Vref Scan: 0
3596 12:18:26.041793
3597 12:18:26.044713 RX Vref 0 -> 0, step: 1
3598 12:18:26.045177
3599 12:18:26.045543 RX Delay -40 -> 252, step: 8
3600 12:18:26.051882 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3601 12:18:26.054636 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3602 12:18:26.058421 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3603 12:18:26.061734 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3604 12:18:26.065097 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3605 12:18:26.071448 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3606 12:18:26.074621 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3607 12:18:26.077971 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3608 12:18:26.081705 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3609 12:18:26.084821 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3610 12:18:26.091227 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3611 12:18:26.094553 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3612 12:18:26.097732 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3613 12:18:26.101094 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3614 12:18:26.107483 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3615 12:18:26.110958 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3616 12:18:26.111510 ==
3617 12:18:26.114957 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 12:18:26.118030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 12:18:26.118747 ==
3620 12:18:26.121367 DQS Delay:
3621 12:18:26.121832 DQS0 = 0, DQS1 = 0
3622 12:18:26.122201 DQM Delay:
3623 12:18:26.124268 DQM0 = 116, DQM1 = 108
3624 12:18:26.124728 DQ Delay:
3625 12:18:26.127575 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3626 12:18:26.130592 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3627 12:18:26.134501 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =95
3628 12:18:26.140310 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3629 12:18:26.140874
3630 12:18:26.141244
3631 12:18:26.141580 ==
3632 12:18:26.144341 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 12:18:26.147897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 12:18:26.148457 ==
3635 12:18:26.148827
3636 12:18:26.149168
3637 12:18:26.151994 TX Vref Scan disable
3638 12:18:26.152549 == TX Byte 0 ==
3639 12:18:26.157333 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3640 12:18:26.160659 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3641 12:18:26.161218 == TX Byte 1 ==
3642 12:18:26.167753 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3643 12:18:26.170497 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3644 12:18:26.170961 ==
3645 12:18:26.173393 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 12:18:26.176802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 12:18:26.177356 ==
3648 12:18:26.189971 TX Vref=22, minBit 8, minWin=25, winSum=425
3649 12:18:26.192785 TX Vref=24, minBit 9, minWin=25, winSum=430
3650 12:18:26.196511 TX Vref=26, minBit 9, minWin=26, winSum=431
3651 12:18:26.199348 TX Vref=28, minBit 9, minWin=26, winSum=438
3652 12:18:26.202757 TX Vref=30, minBit 9, minWin=26, winSum=436
3653 12:18:26.209461 TX Vref=32, minBit 9, minWin=26, winSum=431
3654 12:18:26.212727 [TxChooseVref] Worse bit 9, Min win 26, Win sum 438, Final Vref 28
3655 12:18:26.213195
3656 12:18:26.216199 Final TX Range 1 Vref 28
3657 12:18:26.216661
3658 12:18:26.217025 ==
3659 12:18:26.219290 Dram Type= 6, Freq= 0, CH_1, rank 1
3660 12:18:26.222600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3661 12:18:26.225690 ==
3662 12:18:26.226163
3663 12:18:26.226611
3664 12:18:26.226957 TX Vref Scan disable
3665 12:18:26.229280 == TX Byte 0 ==
3666 12:18:26.233286 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3667 12:18:26.239391 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3668 12:18:26.240006 == TX Byte 1 ==
3669 12:18:26.242607 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3670 12:18:26.249096 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3671 12:18:26.249639
3672 12:18:26.250001 [DATLAT]
3673 12:18:26.250337 Freq=1200, CH1 RK1
3674 12:18:26.250734
3675 12:18:26.252593 DATLAT Default: 0xd
3676 12:18:26.255593 0, 0xFFFF, sum = 0
3677 12:18:26.256106 1, 0xFFFF, sum = 0
3678 12:18:26.259333 2, 0xFFFF, sum = 0
3679 12:18:26.259835 3, 0xFFFF, sum = 0
3680 12:18:26.261992 4, 0xFFFF, sum = 0
3681 12:18:26.262412 5, 0xFFFF, sum = 0
3682 12:18:26.266461 6, 0xFFFF, sum = 0
3683 12:18:26.266976 7, 0xFFFF, sum = 0
3684 12:18:26.269264 8, 0xFFFF, sum = 0
3685 12:18:26.269820 9, 0xFFFF, sum = 0
3686 12:18:26.272176 10, 0xFFFF, sum = 0
3687 12:18:26.272643 11, 0xFFFF, sum = 0
3688 12:18:26.276343 12, 0x0, sum = 1
3689 12:18:26.276765 13, 0x0, sum = 2
3690 12:18:26.278512 14, 0x0, sum = 3
3691 12:18:26.278992 15, 0x0, sum = 4
3692 12:18:26.282414 best_step = 13
3693 12:18:26.282932
3694 12:18:26.283458 ==
3695 12:18:26.285274 Dram Type= 6, Freq= 0, CH_1, rank 1
3696 12:18:26.289354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3697 12:18:26.289775 ==
3698 12:18:26.292182 RX Vref Scan: 0
3699 12:18:26.292607
3700 12:18:26.292939 RX Vref 0 -> 0, step: 1
3701 12:18:26.293248
3702 12:18:26.294978 RX Delay -21 -> 252, step: 4
3703 12:18:26.302242 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3704 12:18:26.305135 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3705 12:18:26.308211 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3706 12:18:26.311851 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3707 12:18:26.314660 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3708 12:18:26.321455 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3709 12:18:26.324550 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3710 12:18:26.328000 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3711 12:18:26.331594 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3712 12:18:26.334815 iDelay=199, Bit 9, Center 98 (31 ~ 166) 136
3713 12:18:26.341380 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3714 12:18:26.344504 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3715 12:18:26.348130 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3716 12:18:26.351201 iDelay=199, Bit 13, Center 116 (51 ~ 182) 132
3717 12:18:26.357961 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3718 12:18:26.361454 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3719 12:18:26.361986 ==
3720 12:18:26.364535 Dram Type= 6, Freq= 0, CH_1, rank 1
3721 12:18:26.368464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3722 12:18:26.368980 ==
3723 12:18:26.370806 DQS Delay:
3724 12:18:26.371235 DQS0 = 0, DQS1 = 0
3725 12:18:26.371573 DQM Delay:
3726 12:18:26.374478 DQM0 = 116, DQM1 = 108
3727 12:18:26.374893 DQ Delay:
3728 12:18:26.377764 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3729 12:18:26.381014 DQ4 =114, DQ5 =126, DQ6 =128, DQ7 =114
3730 12:18:26.384272 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =98
3731 12:18:26.391104 DQ12 =118, DQ13 =116, DQ14 =116, DQ15 =118
3732 12:18:26.391614
3733 12:18:26.391989
3734 12:18:26.397830 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0eb, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 416 ps
3735 12:18:26.400900 CH1 RK1: MR19=303, MR18=F0EB
3736 12:18:26.407381 CH1_RK1: MR19=0x303, MR18=0xF0EB, DQSOSC=416, MR23=63, INC=37, DEC=25
3737 12:18:26.410777 [RxdqsGatingPostProcess] freq 1200
3738 12:18:26.414081 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3739 12:18:26.417360 best DQS0 dly(2T, 0.5T) = (0, 11)
3740 12:18:26.420618 best DQS1 dly(2T, 0.5T) = (0, 11)
3741 12:18:26.423871 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3742 12:18:26.426814 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3743 12:18:26.430725 best DQS0 dly(2T, 0.5T) = (0, 11)
3744 12:18:26.433716 best DQS1 dly(2T, 0.5T) = (0, 11)
3745 12:18:26.437712 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3746 12:18:26.440013 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3747 12:18:26.443450 Pre-setting of DQS Precalculation
3748 12:18:26.446708 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3749 12:18:26.456606 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3750 12:18:26.463457 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3751 12:18:26.464085
3752 12:18:26.464457
3753 12:18:26.466285 [Calibration Summary] 2400 Mbps
3754 12:18:26.466747 CH 0, Rank 0
3755 12:18:26.469953 SW Impedance : PASS
3756 12:18:26.470415 DUTY Scan : NO K
3757 12:18:26.473854 ZQ Calibration : PASS
3758 12:18:26.476531 Jitter Meter : NO K
3759 12:18:26.476953 CBT Training : PASS
3760 12:18:26.479771 Write leveling : PASS
3761 12:18:26.483131 RX DQS gating : PASS
3762 12:18:26.483551 RX DQ/DQS(RDDQC) : PASS
3763 12:18:26.486715 TX DQ/DQS : PASS
3764 12:18:26.490387 RX DATLAT : PASS
3765 12:18:26.490912 RX DQ/DQS(Engine): PASS
3766 12:18:26.492577 TX OE : NO K
3767 12:18:26.492993 All Pass.
3768 12:18:26.493322
3769 12:18:26.496912 CH 0, Rank 1
3770 12:18:26.497327 SW Impedance : PASS
3771 12:18:26.499211 DUTY Scan : NO K
3772 12:18:26.502538 ZQ Calibration : PASS
3773 12:18:26.502953 Jitter Meter : NO K
3774 12:18:26.506694 CBT Training : PASS
3775 12:18:26.510346 Write leveling : PASS
3776 12:18:26.510761 RX DQS gating : PASS
3777 12:18:26.512494 RX DQ/DQS(RDDQC) : PASS
3778 12:18:26.516503 TX DQ/DQS : PASS
3779 12:18:26.517013 RX DATLAT : PASS
3780 12:18:26.518965 RX DQ/DQS(Engine): PASS
3781 12:18:26.522489 TX OE : NO K
3782 12:18:26.522910 All Pass.
3783 12:18:26.523234
3784 12:18:26.523538 CH 1, Rank 0
3785 12:18:26.526377 SW Impedance : PASS
3786 12:18:26.529320 DUTY Scan : NO K
3787 12:18:26.529832 ZQ Calibration : PASS
3788 12:18:26.532983 Jitter Meter : NO K
3789 12:18:26.535704 CBT Training : PASS
3790 12:18:26.536159 Write leveling : PASS
3791 12:18:26.539557 RX DQS gating : PASS
3792 12:18:26.542455 RX DQ/DQS(RDDQC) : PASS
3793 12:18:26.542967 TX DQ/DQS : PASS
3794 12:18:26.545889 RX DATLAT : PASS
3795 12:18:26.546303 RX DQ/DQS(Engine): PASS
3796 12:18:26.548781 TX OE : NO K
3797 12:18:26.549197 All Pass.
3798 12:18:26.549526
3799 12:18:26.553092 CH 1, Rank 1
3800 12:18:26.553503 SW Impedance : PASS
3801 12:18:26.555330 DUTY Scan : NO K
3802 12:18:26.558590 ZQ Calibration : PASS
3803 12:18:26.559074 Jitter Meter : NO K
3804 12:18:26.562849 CBT Training : PASS
3805 12:18:26.565754 Write leveling : PASS
3806 12:18:26.566267 RX DQS gating : PASS
3807 12:18:26.569063 RX DQ/DQS(RDDQC) : PASS
3808 12:18:26.572006 TX DQ/DQS : PASS
3809 12:18:26.572425 RX DATLAT : PASS
3810 12:18:26.575089 RX DQ/DQS(Engine): PASS
3811 12:18:26.579229 TX OE : NO K
3812 12:18:26.579783 All Pass.
3813 12:18:26.580120
3814 12:18:26.581695 DramC Write-DBI off
3815 12:18:26.582110 PER_BANK_REFRESH: Hybrid Mode
3816 12:18:26.585445 TX_TRACKING: ON
3817 12:18:26.591833 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3818 12:18:26.598197 [FAST_K] Save calibration result to emmc
3819 12:18:26.601930 dramc_set_vcore_voltage set vcore to 650000
3820 12:18:26.602441 Read voltage for 600, 5
3821 12:18:26.604737 Vio18 = 0
3822 12:18:26.605156 Vcore = 650000
3823 12:18:26.605484 Vdram = 0
3824 12:18:26.608251 Vddq = 0
3825 12:18:26.608665 Vmddr = 0
3826 12:18:26.611255 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3827 12:18:26.618299 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3828 12:18:26.621290 MEM_TYPE=3, freq_sel=19
3829 12:18:26.625157 sv_algorithm_assistance_LP4_1600
3830 12:18:26.627976 ============ PULL DRAM RESETB DOWN ============
3831 12:18:26.631317 ========== PULL DRAM RESETB DOWN end =========
3832 12:18:26.637958 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3833 12:18:26.642242 ===================================
3834 12:18:26.642660 LPDDR4 DRAM CONFIGURATION
3835 12:18:26.644385 ===================================
3836 12:18:26.647582 EX_ROW_EN[0] = 0x0
3837 12:18:26.651215 EX_ROW_EN[1] = 0x0
3838 12:18:26.651631 LP4Y_EN = 0x0
3839 12:18:26.654744 WORK_FSP = 0x0
3840 12:18:26.655186 WL = 0x2
3841 12:18:26.657711 RL = 0x2
3842 12:18:26.658126 BL = 0x2
3843 12:18:26.660792 RPST = 0x0
3844 12:18:26.661206 RD_PRE = 0x0
3845 12:18:26.663874 WR_PRE = 0x1
3846 12:18:26.664288 WR_PST = 0x0
3847 12:18:26.667603 DBI_WR = 0x0
3848 12:18:26.668069 DBI_RD = 0x0
3849 12:18:26.671171 OTF = 0x1
3850 12:18:26.673924 ===================================
3851 12:18:26.677769 ===================================
3852 12:18:26.678211 ANA top config
3853 12:18:26.680816 ===================================
3854 12:18:26.683836 DLL_ASYNC_EN = 0
3855 12:18:26.687248 ALL_SLAVE_EN = 1
3856 12:18:26.690569 NEW_RANK_MODE = 1
3857 12:18:26.690993 DLL_IDLE_MODE = 1
3858 12:18:26.693714 LP45_APHY_COMB_EN = 1
3859 12:18:26.697495 TX_ODT_DIS = 1
3860 12:18:26.700270 NEW_8X_MODE = 1
3861 12:18:26.704261 ===================================
3862 12:18:26.707460 ===================================
3863 12:18:26.710331 data_rate = 1200
3864 12:18:26.710746 CKR = 1
3865 12:18:26.713977 DQ_P2S_RATIO = 8
3866 12:18:26.717415 ===================================
3867 12:18:26.720032 CA_P2S_RATIO = 8
3868 12:18:26.723129 DQ_CA_OPEN = 0
3869 12:18:26.726864 DQ_SEMI_OPEN = 0
3870 12:18:26.730297 CA_SEMI_OPEN = 0
3871 12:18:26.730711 CA_FULL_RATE = 0
3872 12:18:26.733431 DQ_CKDIV4_EN = 1
3873 12:18:26.736566 CA_CKDIV4_EN = 1
3874 12:18:26.739747 CA_PREDIV_EN = 0
3875 12:18:26.743925 PH8_DLY = 0
3876 12:18:26.747075 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3877 12:18:26.749645 DQ_AAMCK_DIV = 4
3878 12:18:26.750104 CA_AAMCK_DIV = 4
3879 12:18:26.753388 CA_ADMCK_DIV = 4
3880 12:18:26.757562 DQ_TRACK_CA_EN = 0
3881 12:18:26.759932 CA_PICK = 600
3882 12:18:26.763592 CA_MCKIO = 600
3883 12:18:26.766899 MCKIO_SEMI = 0
3884 12:18:26.769958 PLL_FREQ = 2288
3885 12:18:26.770508 DQ_UI_PI_RATIO = 32
3886 12:18:26.772994 CA_UI_PI_RATIO = 0
3887 12:18:26.776155 ===================================
3888 12:18:26.779775 ===================================
3889 12:18:26.783475 memory_type:LPDDR4
3890 12:18:26.786102 GP_NUM : 10
3891 12:18:26.786648 SRAM_EN : 1
3892 12:18:26.789891 MD32_EN : 0
3893 12:18:26.792518 ===================================
3894 12:18:26.792978 [ANA_INIT] >>>>>>>>>>>>>>
3895 12:18:26.796433 <<<<<< [CONFIGURE PHASE]: ANA_TX
3896 12:18:26.799799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3897 12:18:26.803221 ===================================
3898 12:18:26.806198 data_rate = 1200,PCW = 0X5800
3899 12:18:26.810145 ===================================
3900 12:18:26.812658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3901 12:18:26.819626 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3902 12:18:26.825753 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3903 12:18:26.829704 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3904 12:18:26.832966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3905 12:18:26.836209 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3906 12:18:26.838992 [ANA_INIT] flow start
3907 12:18:26.839444 [ANA_INIT] PLL >>>>>>>>
3908 12:18:26.842659 [ANA_INIT] PLL <<<<<<<<
3909 12:18:26.845939 [ANA_INIT] MIDPI >>>>>>>>
3910 12:18:26.848727 [ANA_INIT] MIDPI <<<<<<<<
3911 12:18:26.849182 [ANA_INIT] DLL >>>>>>>>
3912 12:18:26.852373 [ANA_INIT] flow end
3913 12:18:26.856042 ============ LP4 DIFF to SE enter ============
3914 12:18:26.858815 ============ LP4 DIFF to SE exit ============
3915 12:18:26.862475 [ANA_INIT] <<<<<<<<<<<<<
3916 12:18:26.865322 [Flow] Enable top DCM control >>>>>
3917 12:18:26.868672 [Flow] Enable top DCM control <<<<<
3918 12:18:26.871799 Enable DLL master slave shuffle
3919 12:18:26.878569 ==============================================================
3920 12:18:26.879122 Gating Mode config
3921 12:18:26.885507 ==============================================================
3922 12:18:26.886078 Config description:
3923 12:18:26.895325 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3924 12:18:26.901497 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3925 12:18:26.908535 SELPH_MODE 0: By rank 1: By Phase
3926 12:18:26.911604 ==============================================================
3927 12:18:26.914803 GAT_TRACK_EN = 1
3928 12:18:26.918289 RX_GATING_MODE = 2
3929 12:18:26.921406 RX_GATING_TRACK_MODE = 2
3930 12:18:26.924691 SELPH_MODE = 1
3931 12:18:26.928052 PICG_EARLY_EN = 1
3932 12:18:26.931300 VALID_LAT_VALUE = 1
3933 12:18:26.938407 ==============================================================
3934 12:18:26.941217 Enter into Gating configuration >>>>
3935 12:18:26.945029 Exit from Gating configuration <<<<
3936 12:18:26.947414 Enter into DVFS_PRE_config >>>>>
3937 12:18:26.957346 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3938 12:18:26.960987 Exit from DVFS_PRE_config <<<<<
3939 12:18:26.964376 Enter into PICG configuration >>>>
3940 12:18:26.967485 Exit from PICG configuration <<<<
3941 12:18:26.970734 [RX_INPUT] configuration >>>>>
3942 12:18:26.971193 [RX_INPUT] configuration <<<<<
3943 12:18:26.977620 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3944 12:18:26.984372 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3945 12:18:26.990627 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3946 12:18:26.993765 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3947 12:18:27.001026 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3948 12:18:27.006982 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3949 12:18:27.010395 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3950 12:18:27.016864 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3951 12:18:27.020645 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3952 12:18:27.023529 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3953 12:18:27.026996 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3954 12:18:27.034364 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3955 12:18:27.036790 ===================================
3956 12:18:27.037320 LPDDR4 DRAM CONFIGURATION
3957 12:18:27.040078 ===================================
3958 12:18:27.043218 EX_ROW_EN[0] = 0x0
3959 12:18:27.046773 EX_ROW_EN[1] = 0x0
3960 12:18:27.047322 LP4Y_EN = 0x0
3961 12:18:27.050162 WORK_FSP = 0x0
3962 12:18:27.050830 WL = 0x2
3963 12:18:27.053302 RL = 0x2
3964 12:18:27.053762 BL = 0x2
3965 12:18:27.056556 RPST = 0x0
3966 12:18:27.057014 RD_PRE = 0x0
3967 12:18:27.060761 WR_PRE = 0x1
3968 12:18:27.061222 WR_PST = 0x0
3969 12:18:27.062950 DBI_WR = 0x0
3970 12:18:27.063408 DBI_RD = 0x0
3971 12:18:27.067186 OTF = 0x1
3972 12:18:27.069690 ===================================
3973 12:18:27.072725 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3974 12:18:27.076376 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3975 12:18:27.082882 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3976 12:18:27.085726 ===================================
3977 12:18:27.089072 LPDDR4 DRAM CONFIGURATION
3978 12:18:27.092543 ===================================
3979 12:18:27.093050 EX_ROW_EN[0] = 0x10
3980 12:18:27.096051 EX_ROW_EN[1] = 0x0
3981 12:18:27.096513 LP4Y_EN = 0x0
3982 12:18:27.099097 WORK_FSP = 0x0
3983 12:18:27.099554 WL = 0x2
3984 12:18:27.102379 RL = 0x2
3985 12:18:27.102838 BL = 0x2
3986 12:18:27.105298 RPST = 0x0
3987 12:18:27.105758 RD_PRE = 0x0
3988 12:18:27.109954 WR_PRE = 0x1
3989 12:18:27.110523 WR_PST = 0x0
3990 12:18:27.112382 DBI_WR = 0x0
3991 12:18:27.116177 DBI_RD = 0x0
3992 12:18:27.116728 OTF = 0x1
3993 12:18:27.118494 ===================================
3994 12:18:27.125067 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3995 12:18:27.129036 nWR fixed to 30
3996 12:18:27.132006 [ModeRegInit_LP4] CH0 RK0
3997 12:18:27.132464 [ModeRegInit_LP4] CH0 RK1
3998 12:18:27.136272 [ModeRegInit_LP4] CH1 RK0
3999 12:18:27.138900 [ModeRegInit_LP4] CH1 RK1
4000 12:18:27.139358 match AC timing 17
4001 12:18:27.145983 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4002 12:18:27.148561 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4003 12:18:27.152392 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4004 12:18:27.158308 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4005 12:18:27.161510 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4006 12:18:27.161968 ==
4007 12:18:27.164845 Dram Type= 6, Freq= 0, CH_0, rank 0
4008 12:18:27.168285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 12:18:27.171493 ==
4010 12:18:27.175164 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4011 12:18:27.181192 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4012 12:18:27.185442 [CA 0] Center 36 (6~66) winsize 61
4013 12:18:27.188412 [CA 1] Center 36 (6~66) winsize 61
4014 12:18:27.191708 [CA 2] Center 34 (4~65) winsize 62
4015 12:18:27.194602 [CA 3] Center 34 (4~65) winsize 62
4016 12:18:27.197648 [CA 4] Center 33 (3~64) winsize 62
4017 12:18:27.201223 [CA 5] Center 33 (2~64) winsize 63
4018 12:18:27.201777
4019 12:18:27.204444 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4020 12:18:27.204904
4021 12:18:27.207784 [CATrainingPosCal] consider 1 rank data
4022 12:18:27.211476 u2DelayCellTimex100 = 270/100 ps
4023 12:18:27.214563 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4024 12:18:27.217931 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4025 12:18:27.224729 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4026 12:18:27.227278 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4027 12:18:27.230701 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4028 12:18:27.233843 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4029 12:18:27.234304
4030 12:18:27.238181 CA PerBit enable=1, Macro0, CA PI delay=33
4031 12:18:27.238641
4032 12:18:27.241040 [CBTSetCACLKResult] CA Dly = 33
4033 12:18:27.241594 CS Dly: 5 (0~36)
4034 12:18:27.244769 ==
4035 12:18:27.245295 Dram Type= 6, Freq= 0, CH_0, rank 1
4036 12:18:27.251393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 12:18:27.252011 ==
4038 12:18:27.253715 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4039 12:18:27.260628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4040 12:18:27.264450 [CA 0] Center 36 (6~66) winsize 61
4041 12:18:27.268145 [CA 1] Center 36 (6~66) winsize 61
4042 12:18:27.270932 [CA 2] Center 33 (3~64) winsize 62
4043 12:18:27.274223 [CA 3] Center 34 (4~64) winsize 61
4044 12:18:27.277474 [CA 4] Center 33 (3~64) winsize 62
4045 12:18:27.281186 [CA 5] Center 33 (2~64) winsize 63
4046 12:18:27.281618
4047 12:18:27.284178 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4048 12:18:27.284594
4049 12:18:27.287993 [CATrainingPosCal] consider 2 rank data
4050 12:18:27.290517 u2DelayCellTimex100 = 270/100 ps
4051 12:18:27.294818 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4052 12:18:27.300346 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4053 12:18:27.303759 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4054 12:18:27.307126 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4055 12:18:27.310577 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4056 12:18:27.313485 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4057 12:18:27.313902
4058 12:18:27.317950 CA PerBit enable=1, Macro0, CA PI delay=33
4059 12:18:27.318461
4060 12:18:27.321143 [CBTSetCACLKResult] CA Dly = 33
4061 12:18:27.323607 CS Dly: 5 (0~37)
4062 12:18:27.324046
4063 12:18:27.327095 ----->DramcWriteLeveling(PI) begin...
4064 12:18:27.327612 ==
4065 12:18:27.330295 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 12:18:27.333552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 12:18:27.334068 ==
4068 12:18:27.336364 Write leveling (Byte 0): 35 => 35
4069 12:18:27.340140 Write leveling (Byte 1): 29 => 29
4070 12:18:27.343500 DramcWriteLeveling(PI) end<-----
4071 12:18:27.343954
4072 12:18:27.344281 ==
4073 12:18:27.346587 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 12:18:27.350344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 12:18:27.350912 ==
4076 12:18:27.353113 [Gating] SW mode calibration
4077 12:18:27.359975 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4078 12:18:27.366438 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4079 12:18:27.370193 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4080 12:18:27.373675 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4081 12:18:27.379316 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4082 12:18:27.383257 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4083 12:18:27.386344 0 9 16 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
4084 12:18:27.392425 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4085 12:18:27.395731 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4086 12:18:27.399772 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4087 12:18:27.406055 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4088 12:18:27.410073 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4089 12:18:27.412728 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4090 12:18:27.419124 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4091 12:18:27.422833 0 10 16 | B1->B0 | 3535 4545 | 0 0 | (0 0) (1 1)
4092 12:18:27.425708 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 12:18:27.432176 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 12:18:27.436282 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4095 12:18:27.439290 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 12:18:27.445608 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4097 12:18:27.449373 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4098 12:18:27.452155 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4099 12:18:27.458409 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4100 12:18:27.461526 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 12:18:27.464922 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 12:18:27.471756 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 12:18:27.475454 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 12:18:27.478762 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 12:18:27.484983 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 12:18:27.488611 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 12:18:27.491902 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 12:18:27.498718 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 12:18:27.501772 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 12:18:27.505068 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 12:18:27.511110 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 12:18:27.515059 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 12:18:27.518094 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 12:18:27.524260 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 12:18:27.528352 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4116 12:18:27.530868 Total UI for P1: 0, mck2ui 16
4117 12:18:27.535622 best dqsien dly found for B0: ( 0, 13, 14)
4118 12:18:27.537676 Total UI for P1: 0, mck2ui 16
4119 12:18:27.540993 best dqsien dly found for B1: ( 0, 13, 14)
4120 12:18:27.544769 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4121 12:18:27.548055 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4122 12:18:27.548573
4123 12:18:27.551295 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4124 12:18:27.557752 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4125 12:18:27.558258 [Gating] SW calibration Done
4126 12:18:27.558590 ==
4127 12:18:27.561157 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 12:18:27.567273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 12:18:27.567742 ==
4130 12:18:27.568085 RX Vref Scan: 0
4131 12:18:27.568392
4132 12:18:27.570860 RX Vref 0 -> 0, step: 1
4133 12:18:27.571272
4134 12:18:27.574411 RX Delay -230 -> 252, step: 16
4135 12:18:27.577848 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4136 12:18:27.580599 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4137 12:18:27.587396 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4138 12:18:27.590486 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4139 12:18:27.593938 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4140 12:18:27.597255 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4141 12:18:27.600216 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4142 12:18:27.607347 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4143 12:18:27.610693 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4144 12:18:27.613582 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4145 12:18:27.617546 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4146 12:18:27.623855 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4147 12:18:27.627019 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4148 12:18:27.630272 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4149 12:18:27.633247 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4150 12:18:27.640873 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4151 12:18:27.641468 ==
4152 12:18:27.643764 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 12:18:27.647110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 12:18:27.647524 ==
4155 12:18:27.647905 DQS Delay:
4156 12:18:27.650040 DQS0 = 0, DQS1 = 0
4157 12:18:27.650565 DQM Delay:
4158 12:18:27.654208 DQM0 = 43, DQM1 = 31
4159 12:18:27.654718 DQ Delay:
4160 12:18:27.656631 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4161 12:18:27.659643 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =49
4162 12:18:27.663357 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4163 12:18:27.666904 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4164 12:18:27.667417
4165 12:18:27.667798
4166 12:18:27.668110 ==
4167 12:18:27.669536 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 12:18:27.674750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 12:18:27.676535 ==
4170 12:18:27.677033
4171 12:18:27.677388
4172 12:18:27.677718 TX Vref Scan disable
4173 12:18:27.679891 == TX Byte 0 ==
4174 12:18:27.683077 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4175 12:18:27.690054 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4176 12:18:27.690616 == TX Byte 1 ==
4177 12:18:27.692926 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4178 12:18:27.699282 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4179 12:18:27.700166 ==
4180 12:18:27.702358 Dram Type= 6, Freq= 0, CH_0, rank 0
4181 12:18:27.707089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 12:18:27.707558 ==
4183 12:18:27.707950
4184 12:18:27.708286
4185 12:18:27.709023 TX Vref Scan disable
4186 12:18:27.712856 == TX Byte 0 ==
4187 12:18:27.716587 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4188 12:18:27.719132 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4189 12:18:27.722850 == TX Byte 1 ==
4190 12:18:27.725615 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4191 12:18:27.728843 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4192 12:18:27.729264
4193 12:18:27.732279 [DATLAT]
4194 12:18:27.732693 Freq=600, CH0 RK0
4195 12:18:27.733022
4196 12:18:27.735520 DATLAT Default: 0x9
4197 12:18:27.735851 0, 0xFFFF, sum = 0
4198 12:18:27.738648 1, 0xFFFF, sum = 0
4199 12:18:27.738963 2, 0xFFFF, sum = 0
4200 12:18:27.742130 3, 0xFFFF, sum = 0
4201 12:18:27.742357 4, 0xFFFF, sum = 0
4202 12:18:27.745354 5, 0xFFFF, sum = 0
4203 12:18:27.745546 6, 0xFFFF, sum = 0
4204 12:18:27.748488 7, 0xFFFF, sum = 0
4205 12:18:27.748671 8, 0x0, sum = 1
4206 12:18:27.751596 9, 0x0, sum = 2
4207 12:18:27.751789 10, 0x0, sum = 3
4208 12:18:27.755226 11, 0x0, sum = 4
4209 12:18:27.755357 best_step = 9
4210 12:18:27.755459
4211 12:18:27.755553 ==
4212 12:18:27.758466 Dram Type= 6, Freq= 0, CH_0, rank 0
4213 12:18:27.761844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 12:18:27.764987 ==
4215 12:18:27.765088 RX Vref Scan: 1
4216 12:18:27.765167
4217 12:18:27.768345 RX Vref 0 -> 0, step: 1
4218 12:18:27.768481
4219 12:18:27.771604 RX Delay -195 -> 252, step: 8
4220 12:18:27.771715
4221 12:18:27.771784 Set Vref, RX VrefLevel [Byte0]: 60
4222 12:18:27.775106 [Byte1]: 48
4223 12:18:27.779838
4224 12:18:27.779925 Final RX Vref Byte 0 = 60 to rank0
4225 12:18:27.782979 Final RX Vref Byte 1 = 48 to rank0
4226 12:18:27.786107 Final RX Vref Byte 0 = 60 to rank1
4227 12:18:27.789502 Final RX Vref Byte 1 = 48 to rank1==
4228 12:18:27.792959 Dram Type= 6, Freq= 0, CH_0, rank 0
4229 12:18:27.799788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 12:18:27.799880 ==
4231 12:18:27.799947 DQS Delay:
4232 12:18:27.803037 DQS0 = 0, DQS1 = 0
4233 12:18:27.803119 DQM Delay:
4234 12:18:27.803182 DQM0 = 43, DQM1 = 32
4235 12:18:27.806544 DQ Delay:
4236 12:18:27.809951 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4237 12:18:27.813897 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4238 12:18:27.816636 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4239 12:18:27.820644 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4240 12:18:27.820726
4241 12:18:27.820790
4242 12:18:27.826030 [DQSOSCAuto] RK0, (LSB)MR18= 0x623a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4243 12:18:27.829361 CH0 RK0: MR19=808, MR18=623A
4244 12:18:27.836626 CH0_RK0: MR19=0x808, MR18=0x623A, DQSOSC=391, MR23=63, INC=171, DEC=114
4245 12:18:27.836741
4246 12:18:27.838934 ----->DramcWriteLeveling(PI) begin...
4247 12:18:27.839019 ==
4248 12:18:27.843167 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 12:18:27.845713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 12:18:27.845804 ==
4251 12:18:27.850012 Write leveling (Byte 0): 34 => 34
4252 12:18:27.852234 Write leveling (Byte 1): 31 => 31
4253 12:18:27.855616 DramcWriteLeveling(PI) end<-----
4254 12:18:27.855737
4255 12:18:27.855801 ==
4256 12:18:27.859240 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 12:18:27.862409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 12:18:27.865449 ==
4259 12:18:27.865535 [Gating] SW mode calibration
4260 12:18:27.875701 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4261 12:18:27.878826 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4262 12:18:27.882362 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4263 12:18:27.888430 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4264 12:18:27.892126 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4265 12:18:27.895829 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
4266 12:18:27.902150 0 9 16 | B1->B0 | 2f2f 2b2b | 0 0 | (1 1) (0 0)
4267 12:18:27.905176 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 12:18:27.908890 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 12:18:27.914880 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 12:18:27.918483 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4271 12:18:27.921582 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4272 12:18:27.928455 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4273 12:18:27.931870 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
4274 12:18:27.934797 0 10 16 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
4275 12:18:27.941288 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 12:18:27.944451 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 12:18:27.948425 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 12:18:27.954447 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 12:18:27.957580 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4280 12:18:27.961293 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 12:18:27.967435 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4282 12:18:27.971482 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 12:18:27.974379 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 12:18:27.980669 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 12:18:27.984322 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 12:18:27.988081 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 12:18:27.994619 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 12:18:27.997721 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 12:18:28.000903 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 12:18:28.007244 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 12:18:28.010210 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 12:18:28.013509 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 12:18:28.020491 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 12:18:28.023538 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 12:18:28.027167 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 12:18:28.033308 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 12:18:28.037408 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 12:18:28.039877 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 12:18:28.043534 Total UI for P1: 0, mck2ui 16
4300 12:18:28.047006 best dqsien dly found for B0: ( 0, 13, 14)
4301 12:18:28.049977 Total UI for P1: 0, mck2ui 16
4302 12:18:28.053911 best dqsien dly found for B1: ( 0, 13, 14)
4303 12:18:28.056822 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4304 12:18:28.063341 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4305 12:18:28.063456
4306 12:18:28.066296 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4307 12:18:28.069805 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4308 12:18:28.073522 [Gating] SW calibration Done
4309 12:18:28.073605 ==
4310 12:18:28.076544 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 12:18:28.079603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 12:18:28.079696 ==
4313 12:18:28.082837 RX Vref Scan: 0
4314 12:18:28.082923
4315 12:18:28.082988 RX Vref 0 -> 0, step: 1
4316 12:18:28.083047
4317 12:18:28.086482 RX Delay -230 -> 252, step: 16
4318 12:18:28.089517 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4319 12:18:28.096902 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4320 12:18:28.099568 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4321 12:18:28.103569 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4322 12:18:28.106014 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4323 12:18:28.112345 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4324 12:18:28.115787 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4325 12:18:28.119245 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4326 12:18:28.122515 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4327 12:18:28.126257 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4328 12:18:28.132749 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4329 12:18:28.136026 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4330 12:18:28.139191 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4331 12:18:28.142655 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4332 12:18:28.149131 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4333 12:18:28.152438 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4334 12:18:28.152596 ==
4335 12:18:28.155912 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 12:18:28.159535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 12:18:28.159716 ==
4338 12:18:28.162779 DQS Delay:
4339 12:18:28.162948 DQS0 = 0, DQS1 = 0
4340 12:18:28.165609 DQM Delay:
4341 12:18:28.165782 DQM0 = 41, DQM1 = 36
4342 12:18:28.165873 DQ Delay:
4343 12:18:28.169316 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4344 12:18:28.172344 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4345 12:18:28.175913 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4346 12:18:28.178833 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4347 12:18:28.179002
4348 12:18:28.179094
4349 12:18:28.182303 ==
4350 12:18:28.185274 Dram Type= 6, Freq= 0, CH_0, rank 1
4351 12:18:28.189018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 12:18:28.189105 ==
4353 12:18:28.189169
4354 12:18:28.189228
4355 12:18:28.192632 TX Vref Scan disable
4356 12:18:28.192715 == TX Byte 0 ==
4357 12:18:28.199118 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4358 12:18:28.202148 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4359 12:18:28.202232 == TX Byte 1 ==
4360 12:18:28.208371 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4361 12:18:28.211807 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4362 12:18:28.211911 ==
4363 12:18:28.214961 Dram Type= 6, Freq= 0, CH_0, rank 1
4364 12:18:28.218542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 12:18:28.218625 ==
4366 12:18:28.218689
4367 12:18:28.218746
4368 12:18:28.221761 TX Vref Scan disable
4369 12:18:28.225307 == TX Byte 0 ==
4370 12:18:28.228194 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4371 12:18:28.232025 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4372 12:18:28.235501 == TX Byte 1 ==
4373 12:18:28.238207 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4374 12:18:28.241756 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4375 12:18:28.244562
4376 12:18:28.244655 [DATLAT]
4377 12:18:28.244719 Freq=600, CH0 RK1
4378 12:18:28.244779
4379 12:18:28.248025 DATLAT Default: 0x9
4380 12:18:28.248106 0, 0xFFFF, sum = 0
4381 12:18:28.251081 1, 0xFFFF, sum = 0
4382 12:18:28.251165 2, 0xFFFF, sum = 0
4383 12:18:28.254193 3, 0xFFFF, sum = 0
4384 12:18:28.258347 4, 0xFFFF, sum = 0
4385 12:18:28.258430 5, 0xFFFF, sum = 0
4386 12:18:28.260970 6, 0xFFFF, sum = 0
4387 12:18:28.261055 7, 0xFFFF, sum = 0
4388 12:18:28.264620 8, 0x0, sum = 1
4389 12:18:28.264706 9, 0x0, sum = 2
4390 12:18:28.264772 10, 0x0, sum = 3
4391 12:18:28.268028 11, 0x0, sum = 4
4392 12:18:28.268110 best_step = 9
4393 12:18:28.268173
4394 12:18:28.268231 ==
4395 12:18:28.271252 Dram Type= 6, Freq= 0, CH_0, rank 1
4396 12:18:28.278798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 12:18:28.278898 ==
4398 12:18:28.278964 RX Vref Scan: 0
4399 12:18:28.279023
4400 12:18:28.281541 RX Vref 0 -> 0, step: 1
4401 12:18:28.281622
4402 12:18:28.284324 RX Delay -179 -> 252, step: 8
4403 12:18:28.287581 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4404 12:18:28.294270 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4405 12:18:28.297561 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4406 12:18:28.300765 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4407 12:18:28.303938 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4408 12:18:28.310628 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4409 12:18:28.314809 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4410 12:18:28.317178 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4411 12:18:28.320790 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4412 12:18:28.324093 iDelay=205, Bit 9, Center 24 (-123 ~ 172) 296
4413 12:18:28.330335 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4414 12:18:28.334288 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4415 12:18:28.337203 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4416 12:18:28.340283 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4417 12:18:28.347511 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4418 12:18:28.351120 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4419 12:18:28.351215 ==
4420 12:18:28.353932 Dram Type= 6, Freq= 0, CH_0, rank 1
4421 12:18:28.357351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 12:18:28.357433 ==
4423 12:18:28.360956 DQS Delay:
4424 12:18:28.361036 DQS0 = 0, DQS1 = 0
4425 12:18:28.363569 DQM Delay:
4426 12:18:28.363649 DQM0 = 40, DQM1 = 37
4427 12:18:28.363753 DQ Delay:
4428 12:18:28.366610 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =40
4429 12:18:28.370125 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4430 12:18:28.373259 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4431 12:18:28.377179 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4432 12:18:28.377265
4433 12:18:28.377328
4434 12:18:28.386684 [DQSOSCAuto] RK1, (LSB)MR18= 0x6012, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4435 12:18:28.390002 CH0 RK1: MR19=808, MR18=6012
4436 12:18:28.397140 CH0_RK1: MR19=0x808, MR18=0x6012, DQSOSC=391, MR23=63, INC=171, DEC=114
4437 12:18:28.397297 [RxdqsGatingPostProcess] freq 600
4438 12:18:28.403466 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4439 12:18:28.406546 Pre-setting of DQS Precalculation
4440 12:18:28.410063 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4441 12:18:28.413293 ==
4442 12:18:28.416529 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 12:18:28.420027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 12:18:28.420203 ==
4445 12:18:28.423852 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4446 12:18:28.430121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4447 12:18:28.434502 [CA 0] Center 35 (5~66) winsize 62
4448 12:18:28.437173 [CA 1] Center 35 (5~66) winsize 62
4449 12:18:28.440468 [CA 2] Center 34 (4~65) winsize 62
4450 12:18:28.444080 [CA 3] Center 33 (3~64) winsize 62
4451 12:18:28.446947 [CA 4] Center 34 (4~64) winsize 61
4452 12:18:28.449870 [CA 5] Center 33 (3~64) winsize 62
4453 12:18:28.450162
4454 12:18:28.453471 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4455 12:18:28.453671
4456 12:18:28.456513 [CATrainingPosCal] consider 1 rank data
4457 12:18:28.460502 u2DelayCellTimex100 = 270/100 ps
4458 12:18:28.466555 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4459 12:18:28.470250 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4460 12:18:28.473197 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4461 12:18:28.476759 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4462 12:18:28.479745 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4463 12:18:28.483263 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4464 12:18:28.483717
4465 12:18:28.487053 CA PerBit enable=1, Macro0, CA PI delay=33
4466 12:18:28.487134
4467 12:18:28.489591 [CBTSetCACLKResult] CA Dly = 33
4468 12:18:28.492533 CS Dly: 4 (0~35)
4469 12:18:28.492697 ==
4470 12:18:28.496133 Dram Type= 6, Freq= 0, CH_1, rank 1
4471 12:18:28.499418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 12:18:28.499596 ==
4473 12:18:28.505638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4474 12:18:28.512677 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4475 12:18:28.515557 [CA 0] Center 35 (5~66) winsize 62
4476 12:18:28.519259 [CA 1] Center 36 (6~66) winsize 61
4477 12:18:28.522246 [CA 2] Center 34 (4~65) winsize 62
4478 12:18:28.525370 [CA 3] Center 34 (3~65) winsize 63
4479 12:18:28.528950 [CA 4] Center 34 (3~65) winsize 63
4480 12:18:28.533059 [CA 5] Center 34 (3~65) winsize 63
4481 12:18:28.533350
4482 12:18:28.535509 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4483 12:18:28.535773
4484 12:18:28.539177 [CATrainingPosCal] consider 2 rank data
4485 12:18:28.542693 u2DelayCellTimex100 = 270/100 ps
4486 12:18:28.545563 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4487 12:18:28.549189 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4488 12:18:28.553963 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4489 12:18:28.555448 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4490 12:18:28.558942 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4491 12:18:28.561959 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4492 12:18:28.562417
4493 12:18:28.568443 CA PerBit enable=1, Macro0, CA PI delay=33
4494 12:18:28.568982
4495 12:18:28.572398 [CBTSetCACLKResult] CA Dly = 33
4496 12:18:28.572971 CS Dly: 5 (0~37)
4497 12:18:28.573342
4498 12:18:28.575716 ----->DramcWriteLeveling(PI) begin...
4499 12:18:28.576276 ==
4500 12:18:28.578404 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 12:18:28.582524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 12:18:28.584857 ==
4503 12:18:28.585316 Write leveling (Byte 0): 29 => 29
4504 12:18:28.589067 Write leveling (Byte 1): 32 => 32
4505 12:18:28.592077 DramcWriteLeveling(PI) end<-----
4506 12:18:28.592630
4507 12:18:28.592993 ==
4508 12:18:28.595726 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 12:18:28.601525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 12:18:28.602088 ==
4511 12:18:28.605224 [Gating] SW mode calibration
4512 12:18:28.611477 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4513 12:18:28.614621 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4514 12:18:28.621417 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4515 12:18:28.624621 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4516 12:18:28.627618 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4517 12:18:28.635142 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 1)
4518 12:18:28.637298 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4519 12:18:28.640611 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4520 12:18:28.647404 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 12:18:28.651628 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4522 12:18:28.654393 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4523 12:18:28.660895 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4524 12:18:28.664463 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4525 12:18:28.667754 0 10 12 | B1->B0 | 2a2a 3939 | 0 0 | (0 0) (0 0)
4526 12:18:28.674326 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4527 12:18:28.677112 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 12:18:28.680272 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 12:18:28.687212 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 12:18:28.690688 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4531 12:18:28.693698 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4532 12:18:28.700112 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4533 12:18:28.703437 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4534 12:18:28.706715 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 12:18:28.713570 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 12:18:28.717525 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 12:18:28.720252 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 12:18:28.726557 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 12:18:28.729681 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 12:18:28.732971 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 12:18:28.740122 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 12:18:28.742842 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 12:18:28.746711 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 12:18:28.753067 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 12:18:28.756356 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 12:18:28.759490 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 12:18:28.766730 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 12:18:28.769292 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 12:18:28.772839 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4550 12:18:28.776525 Total UI for P1: 0, mck2ui 16
4551 12:18:28.779847 best dqsien dly found for B0: ( 0, 13, 10)
4552 12:18:28.782684 Total UI for P1: 0, mck2ui 16
4553 12:18:28.785835 best dqsien dly found for B1: ( 0, 13, 10)
4554 12:18:28.789227 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4555 12:18:28.792222 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4556 12:18:28.792681
4557 12:18:28.799013 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4558 12:18:28.802402 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4559 12:18:28.806178 [Gating] SW calibration Done
4560 12:18:28.806636 ==
4561 12:18:28.808950 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 12:18:28.812649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 12:18:28.813182 ==
4564 12:18:28.813548 RX Vref Scan: 0
4565 12:18:28.814080
4566 12:18:28.815721 RX Vref 0 -> 0, step: 1
4567 12:18:28.816182
4568 12:18:28.819556 RX Delay -230 -> 252, step: 16
4569 12:18:28.822827 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4570 12:18:28.825476 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4571 12:18:28.832173 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4572 12:18:28.835282 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4573 12:18:28.839172 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4574 12:18:28.842361 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4575 12:18:28.848689 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4576 12:18:28.851860 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4577 12:18:28.855733 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4578 12:18:28.858298 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4579 12:18:28.865517 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4580 12:18:28.867720 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4581 12:18:28.871057 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4582 12:18:28.874609 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4583 12:18:28.881351 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4584 12:18:28.884598 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4585 12:18:28.885015 ==
4586 12:18:28.887929 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 12:18:28.892365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 12:18:28.892877 ==
4589 12:18:28.894564 DQS Delay:
4590 12:18:28.894997 DQS0 = 0, DQS1 = 0
4591 12:18:28.895329 DQM Delay:
4592 12:18:28.897592 DQM0 = 44, DQM1 = 38
4593 12:18:28.898007 DQ Delay:
4594 12:18:28.901331 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4595 12:18:28.904537 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4596 12:18:28.908278 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4597 12:18:28.911702 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4598 12:18:28.912226
4599 12:18:28.912558
4600 12:18:28.912863 ==
4601 12:18:28.914599 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 12:18:28.921345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 12:18:28.921842 ==
4604 12:18:28.922174
4605 12:18:28.922545
4606 12:18:28.922844 TX Vref Scan disable
4607 12:18:28.924934 == TX Byte 0 ==
4608 12:18:28.928413 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4609 12:18:28.934930 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4610 12:18:28.935443 == TX Byte 1 ==
4611 12:18:28.937819 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4612 12:18:28.944634 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4613 12:18:28.945051 ==
4614 12:18:28.948508 Dram Type= 6, Freq= 0, CH_1, rank 0
4615 12:18:28.951351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 12:18:28.951795 ==
4617 12:18:28.952121
4618 12:18:28.952473
4619 12:18:28.954991 TX Vref Scan disable
4620 12:18:28.958275 == TX Byte 0 ==
4621 12:18:28.960951 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4622 12:18:28.964940 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4623 12:18:28.968025 == TX Byte 1 ==
4624 12:18:28.971316 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4625 12:18:28.975090 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4626 12:18:28.975601
4627 12:18:28.976065 [DATLAT]
4628 12:18:28.977780 Freq=600, CH1 RK0
4629 12:18:28.978203
4630 12:18:28.980943 DATLAT Default: 0x9
4631 12:18:28.981453 0, 0xFFFF, sum = 0
4632 12:18:28.985347 1, 0xFFFF, sum = 0
4633 12:18:28.985767 2, 0xFFFF, sum = 0
4634 12:18:28.987482 3, 0xFFFF, sum = 0
4635 12:18:28.988032 4, 0xFFFF, sum = 0
4636 12:18:28.991771 5, 0xFFFF, sum = 0
4637 12:18:28.992292 6, 0xFFFF, sum = 0
4638 12:18:28.993831 7, 0xFFFF, sum = 0
4639 12:18:28.994255 8, 0x0, sum = 1
4640 12:18:28.997388 9, 0x0, sum = 2
4641 12:18:28.997809 10, 0x0, sum = 3
4642 12:18:29.000572 11, 0x0, sum = 4
4643 12:18:29.001168 best_step = 9
4644 12:18:29.001509
4645 12:18:29.001817 ==
4646 12:18:29.003903 Dram Type= 6, Freq= 0, CH_1, rank 0
4647 12:18:29.007387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 12:18:29.008074 ==
4649 12:18:29.010348 RX Vref Scan: 1
4650 12:18:29.010969
4651 12:18:29.013541 RX Vref 0 -> 0, step: 1
4652 12:18:29.014012
4653 12:18:29.014487 RX Delay -195 -> 252, step: 8
4654 12:18:29.016733
4655 12:18:29.017236 Set Vref, RX VrefLevel [Byte0]: 49
4656 12:18:29.020876 [Byte1]: 49
4657 12:18:29.025835
4658 12:18:29.026344 Final RX Vref Byte 0 = 49 to rank0
4659 12:18:29.029287 Final RX Vref Byte 1 = 49 to rank0
4660 12:18:29.031857 Final RX Vref Byte 0 = 49 to rank1
4661 12:18:29.035814 Final RX Vref Byte 1 = 49 to rank1==
4662 12:18:29.038972 Dram Type= 6, Freq= 0, CH_1, rank 0
4663 12:18:29.045335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 12:18:29.045755 ==
4665 12:18:29.046083 DQS Delay:
4666 12:18:29.048632 DQS0 = 0, DQS1 = 0
4667 12:18:29.049048 DQM Delay:
4668 12:18:29.049379 DQM0 = 45, DQM1 = 33
4669 12:18:29.051821 DQ Delay:
4670 12:18:29.054790 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4671 12:18:29.058272 DQ4 =40, DQ5 =56, DQ6 =56, DQ7 =40
4672 12:18:29.061599 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4673 12:18:29.065198 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4674 12:18:29.065613
4675 12:18:29.065939
4676 12:18:29.071279 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a2f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4677 12:18:29.075019 CH1 RK0: MR19=808, MR18=4A2F
4678 12:18:29.081120 CH1_RK0: MR19=0x808, MR18=0x4A2F, DQSOSC=395, MR23=63, INC=168, DEC=112
4679 12:18:29.081536
4680 12:18:29.084850 ----->DramcWriteLeveling(PI) begin...
4681 12:18:29.085273 ==
4682 12:18:29.087694 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 12:18:29.091422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 12:18:29.091882 ==
4685 12:18:29.094790 Write leveling (Byte 0): 31 => 31
4686 12:18:29.097674 Write leveling (Byte 1): 29 => 29
4687 12:18:29.100839 DramcWriteLeveling(PI) end<-----
4688 12:18:29.101256
4689 12:18:29.101584 ==
4690 12:18:29.104368 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 12:18:29.111470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 12:18:29.112028 ==
4693 12:18:29.112369 [Gating] SW mode calibration
4694 12:18:29.120875 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4695 12:18:29.123996 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4696 12:18:29.127429 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4697 12:18:29.134141 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4698 12:18:29.137694 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4699 12:18:29.140767 0 9 12 | B1->B0 | 3030 3333 | 0 0 | (1 1) (0 1)
4700 12:18:29.147207 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4701 12:18:29.150751 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4702 12:18:29.153691 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4703 12:18:29.160239 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4704 12:18:29.163266 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4705 12:18:29.166976 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4706 12:18:29.173453 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4707 12:18:29.176747 0 10 12 | B1->B0 | 3535 2f2f | 1 0 | (0 0) (0 0)
4708 12:18:29.179870 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4709 12:18:29.187057 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 12:18:29.189985 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 12:18:29.193618 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 12:18:29.199834 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 12:18:29.203458 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 12:18:29.209866 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4715 12:18:29.213576 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 12:18:29.215991 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 12:18:29.219644 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 12:18:29.226749 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 12:18:29.229229 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 12:18:29.232825 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 12:18:29.239735 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 12:18:29.243043 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 12:18:29.246935 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 12:18:29.252899 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 12:18:29.255970 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 12:18:29.259898 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 12:18:29.266142 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 12:18:29.269118 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 12:18:29.272466 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 12:18:29.278550 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 12:18:29.281598 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4732 12:18:29.285135 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4733 12:18:29.288827 Total UI for P1: 0, mck2ui 16
4734 12:18:29.291586 best dqsien dly found for B0: ( 0, 13, 12)
4735 12:18:29.294772 Total UI for P1: 0, mck2ui 16
4736 12:18:29.298052 best dqsien dly found for B1: ( 0, 13, 12)
4737 12:18:29.305719 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4738 12:18:29.308989 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4739 12:18:29.309138
4740 12:18:29.311336 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4741 12:18:29.314700 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4742 12:18:29.318658 [Gating] SW calibration Done
4743 12:18:29.318869 ==
4744 12:18:29.321295 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 12:18:29.325090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 12:18:29.325321 ==
4747 12:18:29.328009 RX Vref Scan: 0
4748 12:18:29.328223
4749 12:18:29.328370 RX Vref 0 -> 0, step: 1
4750 12:18:29.328513
4751 12:18:29.331430 RX Delay -230 -> 252, step: 16
4752 12:18:29.337645 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4753 12:18:29.341793 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4754 12:18:29.344594 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4755 12:18:29.347796 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4756 12:18:29.351960 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4757 12:18:29.358170 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4758 12:18:29.361284 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4759 12:18:29.364594 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4760 12:18:29.367770 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4761 12:18:29.374059 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4762 12:18:29.378379 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4763 12:18:29.381326 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4764 12:18:29.385145 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4765 12:18:29.391460 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4766 12:18:29.394187 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4767 12:18:29.397498 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4768 12:18:29.397962 ==
4769 12:18:29.400689 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 12:18:29.404162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 12:18:29.407154 ==
4772 12:18:29.407851 DQS Delay:
4773 12:18:29.408433 DQS0 = 0, DQS1 = 0
4774 12:18:29.411589 DQM Delay:
4775 12:18:29.412266 DQM0 = 42, DQM1 = 35
4776 12:18:29.413672 DQ Delay:
4777 12:18:29.414320 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4778 12:18:29.417380 DQ4 =41, DQ5 =49, DQ6 =65, DQ7 =33
4779 12:18:29.420663 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4780 12:18:29.424363 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4781 12:18:29.427328
4782 12:18:29.427772
4783 12:18:29.428106 ==
4784 12:18:29.430474 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 12:18:29.433846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 12:18:29.434362 ==
4787 12:18:29.434694
4788 12:18:29.435058
4789 12:18:29.437277 TX Vref Scan disable
4790 12:18:29.437787 == TX Byte 0 ==
4791 12:18:29.443623 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4792 12:18:29.447035 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4793 12:18:29.447448 == TX Byte 1 ==
4794 12:18:29.453266 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4795 12:18:29.456549 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4796 12:18:29.456969 ==
4797 12:18:29.459873 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 12:18:29.463770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 12:18:29.464281 ==
4800 12:18:29.464613
4801 12:18:29.467214
4802 12:18:29.467765 TX Vref Scan disable
4803 12:18:29.470227 == TX Byte 0 ==
4804 12:18:29.473386 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4805 12:18:29.480590 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4806 12:18:29.481093 == TX Byte 1 ==
4807 12:18:29.483602 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4808 12:18:29.490295 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4809 12:18:29.490799
4810 12:18:29.491134 [DATLAT]
4811 12:18:29.491444 Freq=600, CH1 RK1
4812 12:18:29.491791
4813 12:18:29.493086 DATLAT Default: 0x9
4814 12:18:29.496780 0, 0xFFFF, sum = 0
4815 12:18:29.497200 1, 0xFFFF, sum = 0
4816 12:18:29.499930 2, 0xFFFF, sum = 0
4817 12:18:29.500349 3, 0xFFFF, sum = 0
4818 12:18:29.502841 4, 0xFFFF, sum = 0
4819 12:18:29.503389 5, 0xFFFF, sum = 0
4820 12:18:29.506196 6, 0xFFFF, sum = 0
4821 12:18:29.506618 7, 0xFFFF, sum = 0
4822 12:18:29.509764 8, 0x0, sum = 1
4823 12:18:29.510281 9, 0x0, sum = 2
4824 12:18:29.512625 10, 0x0, sum = 3
4825 12:18:29.513049 11, 0x0, sum = 4
4826 12:18:29.513446 best_step = 9
4827 12:18:29.513762
4828 12:18:29.516278 ==
4829 12:18:29.519886 Dram Type= 6, Freq= 0, CH_1, rank 1
4830 12:18:29.522939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4831 12:18:29.523356 ==
4832 12:18:29.523719 RX Vref Scan: 0
4833 12:18:29.524041
4834 12:18:29.525921 RX Vref 0 -> 0, step: 1
4835 12:18:29.526426
4836 12:18:29.529197 RX Delay -195 -> 252, step: 8
4837 12:18:29.535888 iDelay=213, Bit 0, Center 44 (-107 ~ 196) 304
4838 12:18:29.538950 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4839 12:18:29.542582 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4840 12:18:29.545737 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4841 12:18:29.552322 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4842 12:18:29.555276 iDelay=213, Bit 5, Center 52 (-99 ~ 204) 304
4843 12:18:29.559125 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4844 12:18:29.561834 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4845 12:18:29.565948 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4846 12:18:29.572377 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4847 12:18:29.575467 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4848 12:18:29.578911 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4849 12:18:29.581684 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4850 12:18:29.588524 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4851 12:18:29.592451 iDelay=213, Bit 14, Center 40 (-115 ~ 196) 312
4852 12:18:29.595059 iDelay=213, Bit 15, Center 40 (-115 ~ 196) 312
4853 12:18:29.595519 ==
4854 12:18:29.598500 Dram Type= 6, Freq= 0, CH_1, rank 1
4855 12:18:29.601960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4856 12:18:29.605239 ==
4857 12:18:29.605660 DQS Delay:
4858 12:18:29.605986 DQS0 = 0, DQS1 = 0
4859 12:18:29.608182 DQM Delay:
4860 12:18:29.608597 DQM0 = 42, DQM1 = 34
4861 12:18:29.611604 DQ Delay:
4862 12:18:29.615066 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4863 12:18:29.615575 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4864 12:18:29.618177 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4865 12:18:29.624969 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4866 12:18:29.625473
4867 12:18:29.625806
4868 12:18:29.632117 [DQSOSCAuto] RK1, (LSB)MR18= 0x3025, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
4869 12:18:29.634632 CH1 RK1: MR19=808, MR18=3025
4870 12:18:29.641236 CH1_RK1: MR19=0x808, MR18=0x3025, DQSOSC=400, MR23=63, INC=163, DEC=109
4871 12:18:29.644505 [RxdqsGatingPostProcess] freq 600
4872 12:18:29.648131 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4873 12:18:29.651566 Pre-setting of DQS Precalculation
4874 12:18:29.657507 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4875 12:18:29.664130 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4876 12:18:29.670977 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4877 12:18:29.671539
4878 12:18:29.671970
4879 12:18:29.674078 [Calibration Summary] 1200 Mbps
4880 12:18:29.674539 CH 0, Rank 0
4881 12:18:29.677933 SW Impedance : PASS
4882 12:18:29.680584 DUTY Scan : NO K
4883 12:18:29.681043 ZQ Calibration : PASS
4884 12:18:29.684253 Jitter Meter : NO K
4885 12:18:29.687852 CBT Training : PASS
4886 12:18:29.688314 Write leveling : PASS
4887 12:18:29.691165 RX DQS gating : PASS
4888 12:18:29.694395 RX DQ/DQS(RDDQC) : PASS
4889 12:18:29.694938 TX DQ/DQS : PASS
4890 12:18:29.697163 RX DATLAT : PASS
4891 12:18:29.701078 RX DQ/DQS(Engine): PASS
4892 12:18:29.701539 TX OE : NO K
4893 12:18:29.704029 All Pass.
4894 12:18:29.704485
4895 12:18:29.704845 CH 0, Rank 1
4896 12:18:29.707271 SW Impedance : PASS
4897 12:18:29.708047 DUTY Scan : NO K
4898 12:18:29.710239 ZQ Calibration : PASS
4899 12:18:29.713535 Jitter Meter : NO K
4900 12:18:29.713994 CBT Training : PASS
4901 12:18:29.716970 Write leveling : PASS
4902 12:18:29.720298 RX DQS gating : PASS
4903 12:18:29.720842 RX DQ/DQS(RDDQC) : PASS
4904 12:18:29.723577 TX DQ/DQS : PASS
4905 12:18:29.726666 RX DATLAT : PASS
4906 12:18:29.727122 RX DQ/DQS(Engine): PASS
4907 12:18:29.729904 TX OE : NO K
4908 12:18:29.730321 All Pass.
4909 12:18:29.730648
4910 12:18:29.734934 CH 1, Rank 0
4911 12:18:29.735454 SW Impedance : PASS
4912 12:18:29.736375 DUTY Scan : NO K
4913 12:18:29.736737 ZQ Calibration : PASS
4914 12:18:29.739891 Jitter Meter : NO K
4915 12:18:29.743801 CBT Training : PASS
4916 12:18:29.744216 Write leveling : PASS
4917 12:18:29.746649 RX DQS gating : PASS
4918 12:18:29.749903 RX DQ/DQS(RDDQC) : PASS
4919 12:18:29.750320 TX DQ/DQS : PASS
4920 12:18:29.753035 RX DATLAT : PASS
4921 12:18:29.756278 RX DQ/DQS(Engine): PASS
4922 12:18:29.756694 TX OE : NO K
4923 12:18:29.760303 All Pass.
4924 12:18:29.760815
4925 12:18:29.761187 CH 1, Rank 1
4926 12:18:29.763464 SW Impedance : PASS
4927 12:18:29.764179 DUTY Scan : NO K
4928 12:18:29.766566 ZQ Calibration : PASS
4929 12:18:29.769309 Jitter Meter : NO K
4930 12:18:29.769945 CBT Training : PASS
4931 12:18:29.772887 Write leveling : PASS
4932 12:18:29.776339 RX DQS gating : PASS
4933 12:18:29.776966 RX DQ/DQS(RDDQC) : PASS
4934 12:18:29.779144 TX DQ/DQS : PASS
4935 12:18:29.782678 RX DATLAT : PASS
4936 12:18:29.783127 RX DQ/DQS(Engine): PASS
4937 12:18:29.786006 TX OE : NO K
4938 12:18:29.786464 All Pass.
4939 12:18:29.786872
4940 12:18:29.789219 DramC Write-DBI off
4941 12:18:29.792376 PER_BANK_REFRESH: Hybrid Mode
4942 12:18:29.792673 TX_TRACKING: ON
4943 12:18:29.802086 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4944 12:18:29.805411 [FAST_K] Save calibration result to emmc
4945 12:18:29.808973 dramc_set_vcore_voltage set vcore to 662500
4946 12:18:29.812460 Read voltage for 933, 3
4947 12:18:29.812566 Vio18 = 0
4948 12:18:29.812646 Vcore = 662500
4949 12:18:29.815696 Vdram = 0
4950 12:18:29.815796 Vddq = 0
4951 12:18:29.815875 Vmddr = 0
4952 12:18:29.821649 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4953 12:18:29.825058 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4954 12:18:29.828872 MEM_TYPE=3, freq_sel=17
4955 12:18:29.831780 sv_algorithm_assistance_LP4_1600
4956 12:18:29.835620 ============ PULL DRAM RESETB DOWN ============
4957 12:18:29.841844 ========== PULL DRAM RESETB DOWN end =========
4958 12:18:29.845031 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4959 12:18:29.848345 ===================================
4960 12:18:29.852057 LPDDR4 DRAM CONFIGURATION
4961 12:18:29.854841 ===================================
4962 12:18:29.854921 EX_ROW_EN[0] = 0x0
4963 12:18:29.858328 EX_ROW_EN[1] = 0x0
4964 12:18:29.858493 LP4Y_EN = 0x0
4965 12:18:29.861448 WORK_FSP = 0x0
4966 12:18:29.861576 WL = 0x3
4967 12:18:29.865130 RL = 0x3
4968 12:18:29.865299 BL = 0x2
4969 12:18:29.868095 RPST = 0x0
4970 12:18:29.868246 RD_PRE = 0x0
4971 12:18:29.871444 WR_PRE = 0x1
4972 12:18:29.871620 WR_PST = 0x0
4973 12:18:29.875566 DBI_WR = 0x0
4974 12:18:29.878331 DBI_RD = 0x0
4975 12:18:29.878526 OTF = 0x1
4976 12:18:29.882056 ===================================
4977 12:18:29.884531 ===================================
4978 12:18:29.884700 ANA top config
4979 12:18:29.887813 ===================================
4980 12:18:29.891737 DLL_ASYNC_EN = 0
4981 12:18:29.895021 ALL_SLAVE_EN = 1
4982 12:18:29.898002 NEW_RANK_MODE = 1
4983 12:18:29.901029 DLL_IDLE_MODE = 1
4984 12:18:29.901229 LP45_APHY_COMB_EN = 1
4985 12:18:29.904618 TX_ODT_DIS = 1
4986 12:18:29.909267 NEW_8X_MODE = 1
4987 12:18:29.911448 ===================================
4988 12:18:29.914785 ===================================
4989 12:18:29.918030 data_rate = 1866
4990 12:18:29.921848 CKR = 1
4991 12:18:29.924746 DQ_P2S_RATIO = 8
4992 12:18:29.927798 ===================================
4993 12:18:29.928271 CA_P2S_RATIO = 8
4994 12:18:29.931104 DQ_CA_OPEN = 0
4995 12:18:29.934626 DQ_SEMI_OPEN = 0
4996 12:18:29.937786 CA_SEMI_OPEN = 0
4997 12:18:29.941073 CA_FULL_RATE = 0
4998 12:18:29.944877 DQ_CKDIV4_EN = 1
4999 12:18:29.945385 CA_CKDIV4_EN = 1
5000 12:18:29.948356 CA_PREDIV_EN = 0
5001 12:18:29.950518 PH8_DLY = 0
5002 12:18:29.954026 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5003 12:18:29.957677 DQ_AAMCK_DIV = 4
5004 12:18:29.961373 CA_AAMCK_DIV = 4
5005 12:18:29.961877 CA_ADMCK_DIV = 4
5006 12:18:29.964568 DQ_TRACK_CA_EN = 0
5007 12:18:29.967395 CA_PICK = 933
5008 12:18:29.970543 CA_MCKIO = 933
5009 12:18:29.974533 MCKIO_SEMI = 0
5010 12:18:29.977187 PLL_FREQ = 3732
5011 12:18:29.980341 DQ_UI_PI_RATIO = 32
5012 12:18:29.980758 CA_UI_PI_RATIO = 0
5013 12:18:29.984311 ===================================
5014 12:18:29.987706 ===================================
5015 12:18:29.990524 memory_type:LPDDR4
5016 12:18:29.994558 GP_NUM : 10
5017 12:18:29.995075 SRAM_EN : 1
5018 12:18:29.997570 MD32_EN : 0
5019 12:18:30.000165 ===================================
5020 12:18:30.003996 [ANA_INIT] >>>>>>>>>>>>>>
5021 12:18:30.006844 <<<<<< [CONFIGURE PHASE]: ANA_TX
5022 12:18:30.010963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5023 12:18:30.014056 ===================================
5024 12:18:30.016915 data_rate = 1866,PCW = 0X8f00
5025 12:18:30.020061 ===================================
5026 12:18:30.024534 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5027 12:18:30.026856 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5028 12:18:30.033741 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5029 12:18:30.036938 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5030 12:18:30.040079 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5031 12:18:30.043366 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5032 12:18:30.046879 [ANA_INIT] flow start
5033 12:18:30.049948 [ANA_INIT] PLL >>>>>>>>
5034 12:18:30.050408 [ANA_INIT] PLL <<<<<<<<
5035 12:18:30.053082 [ANA_INIT] MIDPI >>>>>>>>
5036 12:18:30.056698 [ANA_INIT] MIDPI <<<<<<<<
5037 12:18:30.057247 [ANA_INIT] DLL >>>>>>>>
5038 12:18:30.059758 [ANA_INIT] flow end
5039 12:18:30.062694 ============ LP4 DIFF to SE enter ============
5040 12:18:30.069987 ============ LP4 DIFF to SE exit ============
5041 12:18:30.070462 [ANA_INIT] <<<<<<<<<<<<<
5042 12:18:30.073258 [Flow] Enable top DCM control >>>>>
5043 12:18:30.076844 [Flow] Enable top DCM control <<<<<
5044 12:18:30.079740 Enable DLL master slave shuffle
5045 12:18:30.085961 ==============================================================
5046 12:18:30.086428 Gating Mode config
5047 12:18:30.092785 ==============================================================
5048 12:18:30.096161 Config description:
5049 12:18:30.105882 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5050 12:18:30.112368 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5051 12:18:30.116465 SELPH_MODE 0: By rank 1: By Phase
5052 12:18:30.122623 ==============================================================
5053 12:18:30.125791 GAT_TRACK_EN = 1
5054 12:18:30.126376 RX_GATING_MODE = 2
5055 12:18:30.129487 RX_GATING_TRACK_MODE = 2
5056 12:18:30.132378 SELPH_MODE = 1
5057 12:18:30.135722 PICG_EARLY_EN = 1
5058 12:18:30.140051 VALID_LAT_VALUE = 1
5059 12:18:30.146557 ==============================================================
5060 12:18:30.149399 Enter into Gating configuration >>>>
5061 12:18:30.152984 Exit from Gating configuration <<<<
5062 12:18:30.156312 Enter into DVFS_PRE_config >>>>>
5063 12:18:30.166148 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5064 12:18:30.169438 Exit from DVFS_PRE_config <<<<<
5065 12:18:30.172357 Enter into PICG configuration >>>>
5066 12:18:30.175777 Exit from PICG configuration <<<<
5067 12:18:30.180021 [RX_INPUT] configuration >>>>>
5068 12:18:30.181767 [RX_INPUT] configuration <<<<<
5069 12:18:30.185167 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5070 12:18:30.192106 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5071 12:18:30.198289 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5072 12:18:30.205129 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5073 12:18:30.209046 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5074 12:18:30.215047 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5075 12:18:30.221859 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5076 12:18:30.224946 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5077 12:18:30.228384 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5078 12:18:30.231206 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5079 12:18:30.235094 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5080 12:18:30.241139 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5081 12:18:30.245034 ===================================
5082 12:18:30.247860 LPDDR4 DRAM CONFIGURATION
5083 12:18:30.251394 ===================================
5084 12:18:30.252056 EX_ROW_EN[0] = 0x0
5085 12:18:30.254462 EX_ROW_EN[1] = 0x0
5086 12:18:30.254919 LP4Y_EN = 0x0
5087 12:18:30.257702 WORK_FSP = 0x0
5088 12:18:30.258159 WL = 0x3
5089 12:18:30.260992 RL = 0x3
5090 12:18:30.261450 BL = 0x2
5091 12:18:30.264059 RPST = 0x0
5092 12:18:30.264516 RD_PRE = 0x0
5093 12:18:30.268342 WR_PRE = 0x1
5094 12:18:30.271380 WR_PST = 0x0
5095 12:18:30.271984 DBI_WR = 0x0
5096 12:18:30.274980 DBI_RD = 0x0
5097 12:18:30.275531 OTF = 0x1
5098 12:18:30.277818 ===================================
5099 12:18:30.280797 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5100 12:18:30.287819 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5101 12:18:30.290678 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5102 12:18:30.294631 ===================================
5103 12:18:30.297406 LPDDR4 DRAM CONFIGURATION
5104 12:18:30.301208 ===================================
5105 12:18:30.301784 EX_ROW_EN[0] = 0x10
5106 12:18:30.303835 EX_ROW_EN[1] = 0x0
5107 12:18:30.304337 LP4Y_EN = 0x0
5108 12:18:30.307127 WORK_FSP = 0x0
5109 12:18:30.307584 WL = 0x3
5110 12:18:30.310354 RL = 0x3
5111 12:18:30.313853 BL = 0x2
5112 12:18:30.314308 RPST = 0x0
5113 12:18:30.317671 RD_PRE = 0x0
5114 12:18:30.318222 WR_PRE = 0x1
5115 12:18:30.320472 WR_PST = 0x0
5116 12:18:30.320929 DBI_WR = 0x0
5117 12:18:30.323931 DBI_RD = 0x0
5118 12:18:30.324389 OTF = 0x1
5119 12:18:30.327341 ===================================
5120 12:18:30.334084 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5121 12:18:30.337502 nWR fixed to 30
5122 12:18:30.340644 [ModeRegInit_LP4] CH0 RK0
5123 12:18:30.341059 [ModeRegInit_LP4] CH0 RK1
5124 12:18:30.345005 [ModeRegInit_LP4] CH1 RK0
5125 12:18:30.347839 [ModeRegInit_LP4] CH1 RK1
5126 12:18:30.348346 match AC timing 9
5127 12:18:30.353490 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5128 12:18:30.356808 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5129 12:18:30.360974 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5130 12:18:30.367198 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5131 12:18:30.370689 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5132 12:18:30.371248 ==
5133 12:18:30.374081 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 12:18:30.377012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 12:18:30.377473 ==
5136 12:18:30.383908 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5137 12:18:30.390613 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5138 12:18:30.394295 [CA 0] Center 37 (7~68) winsize 62
5139 12:18:30.396856 [CA 1] Center 37 (7~68) winsize 62
5140 12:18:30.400373 [CA 2] Center 34 (4~65) winsize 62
5141 12:18:30.404015 [CA 3] Center 35 (5~65) winsize 61
5142 12:18:30.407127 [CA 4] Center 33 (3~64) winsize 62
5143 12:18:30.410470 [CA 5] Center 33 (3~64) winsize 62
5144 12:18:30.411041
5145 12:18:30.413472 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5146 12:18:30.413932
5147 12:18:30.417231 [CATrainingPosCal] consider 1 rank data
5148 12:18:30.420520 u2DelayCellTimex100 = 270/100 ps
5149 12:18:30.423384 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5150 12:18:30.426562 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5151 12:18:30.430200 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5152 12:18:30.436232 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5153 12:18:30.439531 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5154 12:18:30.443094 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5155 12:18:30.443561
5156 12:18:30.446511 CA PerBit enable=1, Macro0, CA PI delay=33
5157 12:18:30.446970
5158 12:18:30.449444 [CBTSetCACLKResult] CA Dly = 33
5159 12:18:30.449903 CS Dly: 7 (0~38)
5160 12:18:30.450263 ==
5161 12:18:30.452606 Dram Type= 6, Freq= 0, CH_0, rank 1
5162 12:18:30.459326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 12:18:30.459830 ==
5164 12:18:30.462466 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5165 12:18:30.468850 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5166 12:18:30.472946 [CA 0] Center 37 (7~68) winsize 62
5167 12:18:30.475789 [CA 1] Center 37 (7~68) winsize 62
5168 12:18:30.479485 [CA 2] Center 34 (4~65) winsize 62
5169 12:18:30.482324 [CA 3] Center 34 (4~65) winsize 62
5170 12:18:30.485797 [CA 4] Center 33 (3~64) winsize 62
5171 12:18:30.489066 [CA 5] Center 32 (2~63) winsize 62
5172 12:18:30.489524
5173 12:18:30.492581 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5174 12:18:30.493134
5175 12:18:30.495799 [CATrainingPosCal] consider 2 rank data
5176 12:18:30.499285 u2DelayCellTimex100 = 270/100 ps
5177 12:18:30.501824 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5178 12:18:30.509093 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5179 12:18:30.512645 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5180 12:18:30.515798 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5181 12:18:30.518170 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5182 12:18:30.522012 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5183 12:18:30.522568
5184 12:18:30.525192 CA PerBit enable=1, Macro0, CA PI delay=33
5185 12:18:30.525748
5186 12:18:30.528709 [CBTSetCACLKResult] CA Dly = 33
5187 12:18:30.532239 CS Dly: 7 (0~39)
5188 12:18:30.532694
5189 12:18:30.535213 ----->DramcWriteLeveling(PI) begin...
5190 12:18:30.535812 ==
5191 12:18:30.538557 Dram Type= 6, Freq= 0, CH_0, rank 0
5192 12:18:30.541736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 12:18:30.542316 ==
5194 12:18:30.545172 Write leveling (Byte 0): 34 => 34
5195 12:18:30.548400 Write leveling (Byte 1): 28 => 28
5196 12:18:30.551722 DramcWriteLeveling(PI) end<-----
5197 12:18:30.552177
5198 12:18:30.552538 ==
5199 12:18:30.554929 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 12:18:30.558182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 12:18:30.558739 ==
5202 12:18:30.561203 [Gating] SW mode calibration
5203 12:18:30.567977 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5204 12:18:30.574143 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5205 12:18:30.577933 0 14 0 | B1->B0 | 2322 3232 | 1 0 | (0 0) (0 0)
5206 12:18:30.584361 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5207 12:18:30.587420 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5208 12:18:30.591073 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5209 12:18:30.597547 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5210 12:18:30.600634 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5211 12:18:30.603912 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5212 12:18:30.610577 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5213 12:18:30.613919 0 15 0 | B1->B0 | 3232 2626 | 0 0 | (0 0) (1 0)
5214 12:18:30.617398 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5215 12:18:30.623816 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5216 12:18:30.627322 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5217 12:18:30.630100 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5218 12:18:30.637135 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5219 12:18:30.640514 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5220 12:18:30.643985 0 15 28 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5221 12:18:30.649917 1 0 0 | B1->B0 | 2f2f 4242 | 1 0 | (0 0) (0 0)
5222 12:18:30.653649 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 12:18:30.657048 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 12:18:30.663214 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 12:18:30.666929 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 12:18:30.669891 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 12:18:30.676438 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5228 12:18:30.680125 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5229 12:18:30.682837 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5230 12:18:30.689373 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5231 12:18:30.693551 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 12:18:30.696022 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 12:18:30.702725 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 12:18:30.706164 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 12:18:30.709617 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 12:18:30.716351 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 12:18:30.719658 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 12:18:30.722614 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 12:18:30.729316 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 12:18:30.732945 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 12:18:30.735997 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 12:18:30.742027 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 12:18:30.746467 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 12:18:30.749440 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 12:18:30.755518 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5246 12:18:30.756126 Total UI for P1: 0, mck2ui 16
5247 12:18:30.761802 best dqsien dly found for B0: ( 1, 2, 30)
5248 12:18:30.765324 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5249 12:18:30.768944 Total UI for P1: 0, mck2ui 16
5250 12:18:30.771785 best dqsien dly found for B1: ( 1, 3, 0)
5251 12:18:30.775613 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5252 12:18:30.778603 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5253 12:18:30.779014
5254 12:18:30.782044 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5255 12:18:30.785107 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5256 12:18:30.788299 [Gating] SW calibration Done
5257 12:18:30.788763 ==
5258 12:18:30.792142 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 12:18:30.795287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 12:18:30.798305 ==
5261 12:18:30.798772 RX Vref Scan: 0
5262 12:18:30.799138
5263 12:18:30.802607 RX Vref 0 -> 0, step: 1
5264 12:18:30.803165
5265 12:18:30.804668 RX Delay -80 -> 252, step: 8
5266 12:18:30.808625 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5267 12:18:30.812799 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5268 12:18:30.814663 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5269 12:18:30.818324 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5270 12:18:30.822259 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5271 12:18:30.828193 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5272 12:18:30.831521 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5273 12:18:30.834408 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5274 12:18:30.837505 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5275 12:18:30.841431 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5276 12:18:30.847632 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5277 12:18:30.850669 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5278 12:18:30.854378 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5279 12:18:30.857642 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5280 12:18:30.861141 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5281 12:18:30.868256 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5282 12:18:30.868674 ==
5283 12:18:30.870837 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 12:18:30.873984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 12:18:30.874398 ==
5286 12:18:30.874721 DQS Delay:
5287 12:18:30.877502 DQS0 = 0, DQS1 = 0
5288 12:18:30.878014 DQM Delay:
5289 12:18:30.880910 DQM0 = 97, DQM1 = 85
5290 12:18:30.881420 DQ Delay:
5291 12:18:30.884226 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5292 12:18:30.887440 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =103
5293 12:18:30.890928 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =75
5294 12:18:30.894402 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5295 12:18:30.894915
5296 12:18:30.895240
5297 12:18:30.895540 ==
5298 12:18:30.898389 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 12:18:30.900645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 12:18:30.904079 ==
5301 12:18:30.904487
5302 12:18:30.904811
5303 12:18:30.905110 TX Vref Scan disable
5304 12:18:30.907626 == TX Byte 0 ==
5305 12:18:30.910017 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5306 12:18:30.913933 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5307 12:18:30.917132 == TX Byte 1 ==
5308 12:18:30.919964 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5309 12:18:30.923424 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5310 12:18:30.927451 ==
5311 12:18:30.930390 Dram Type= 6, Freq= 0, CH_0, rank 0
5312 12:18:30.933608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 12:18:30.934174 ==
5314 12:18:30.934543
5315 12:18:30.934878
5316 12:18:30.937314 TX Vref Scan disable
5317 12:18:30.937872 == TX Byte 0 ==
5318 12:18:30.943315 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5319 12:18:30.946489 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5320 12:18:30.947199 == TX Byte 1 ==
5321 12:18:30.953387 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5322 12:18:30.956549 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5323 12:18:30.957012
5324 12:18:30.957375 [DATLAT]
5325 12:18:30.959808 Freq=933, CH0 RK0
5326 12:18:30.960271
5327 12:18:30.960642 DATLAT Default: 0xd
5328 12:18:30.963188 0, 0xFFFF, sum = 0
5329 12:18:30.964023 1, 0xFFFF, sum = 0
5330 12:18:30.966325 2, 0xFFFF, sum = 0
5331 12:18:30.970369 3, 0xFFFF, sum = 0
5332 12:18:30.970836 4, 0xFFFF, sum = 0
5333 12:18:30.973972 5, 0xFFFF, sum = 0
5334 12:18:30.974439 6, 0xFFFF, sum = 0
5335 12:18:30.976542 7, 0xFFFF, sum = 0
5336 12:18:30.977251 8, 0xFFFF, sum = 0
5337 12:18:30.979361 9, 0xFFFF, sum = 0
5338 12:18:30.979820 10, 0x0, sum = 1
5339 12:18:30.983362 11, 0x0, sum = 2
5340 12:18:30.983834 12, 0x0, sum = 3
5341 12:18:30.984234 13, 0x0, sum = 4
5342 12:18:30.986169 best_step = 11
5343 12:18:30.986581
5344 12:18:30.986910 ==
5345 12:18:30.989369 Dram Type= 6, Freq= 0, CH_0, rank 0
5346 12:18:30.992654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 12:18:30.993075 ==
5348 12:18:30.996450 RX Vref Scan: 1
5349 12:18:30.996868
5350 12:18:30.999499 RX Vref 0 -> 0, step: 1
5351 12:18:30.999959
5352 12:18:31.000291 RX Delay -69 -> 252, step: 4
5353 12:18:31.000601
5354 12:18:31.003064 Set Vref, RX VrefLevel [Byte0]: 60
5355 12:18:31.005930 [Byte1]: 48
5356 12:18:31.010837
5357 12:18:31.011463 Final RX Vref Byte 0 = 60 to rank0
5358 12:18:31.014157 Final RX Vref Byte 1 = 48 to rank0
5359 12:18:31.017283 Final RX Vref Byte 0 = 60 to rank1
5360 12:18:31.020352 Final RX Vref Byte 1 = 48 to rank1==
5361 12:18:31.023780 Dram Type= 6, Freq= 0, CH_0, rank 0
5362 12:18:31.030613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 12:18:31.031030 ==
5364 12:18:31.031386 DQS Delay:
5365 12:18:31.033417 DQS0 = 0, DQS1 = 0
5366 12:18:31.033830 DQM Delay:
5367 12:18:31.034154 DQM0 = 96, DQM1 = 84
5368 12:18:31.036829 DQ Delay:
5369 12:18:31.041026 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =92
5370 12:18:31.043420 DQ4 =96, DQ5 =88, DQ6 =106, DQ7 =106
5371 12:18:31.046869 DQ8 =76, DQ9 =74, DQ10 =84, DQ11 =78
5372 12:18:31.050324 DQ12 =88, DQ13 =88, DQ14 =96, DQ15 =90
5373 12:18:31.050620
5374 12:18:31.050852
5375 12:18:31.056622 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b12, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5376 12:18:31.059901 CH0 RK0: MR19=505, MR18=2B12
5377 12:18:31.067210 CH0_RK0: MR19=0x505, MR18=0x2B12, DQSOSC=408, MR23=63, INC=65, DEC=43
5378 12:18:31.067507
5379 12:18:31.069973 ----->DramcWriteLeveling(PI) begin...
5380 12:18:31.070271 ==
5381 12:18:31.073553 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 12:18:31.077011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 12:18:31.077396 ==
5384 12:18:31.081870 Write leveling (Byte 0): 34 => 34
5385 12:18:31.083502 Write leveling (Byte 1): 33 => 33
5386 12:18:31.086744 DramcWriteLeveling(PI) end<-----
5387 12:18:31.087123
5388 12:18:31.087421 ==
5389 12:18:31.089950 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 12:18:31.093113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 12:18:31.093533 ==
5392 12:18:31.097217 [Gating] SW mode calibration
5393 12:18:31.103418 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5394 12:18:31.109555 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5395 12:18:31.112932 0 14 0 | B1->B0 | 2e2e 3434 | 1 0 | (0 0) (0 0)
5396 12:18:31.119937 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5397 12:18:31.123443 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5398 12:18:31.126367 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5399 12:18:31.133024 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5400 12:18:31.136174 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5401 12:18:31.139422 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5402 12:18:31.145984 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 0)
5403 12:18:31.149647 0 15 0 | B1->B0 | 2d2d 2b2b | 1 0 | (1 0) (0 0)
5404 12:18:31.152420 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5405 12:18:31.159933 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5406 12:18:31.162670 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 12:18:31.166802 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5408 12:18:31.172738 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5409 12:18:31.175630 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5410 12:18:31.178778 0 15 28 | B1->B0 | 2525 3131 | 0 0 | (0 0) (0 0)
5411 12:18:31.185744 1 0 0 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
5412 12:18:31.188803 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 12:18:31.192415 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 12:18:31.198994 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 12:18:31.202715 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 12:18:31.204830 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 12:18:31.211896 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 12:18:31.214827 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5419 12:18:31.218640 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 12:18:31.225181 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 12:18:31.229065 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 12:18:31.232304 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 12:18:31.238073 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 12:18:31.241841 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 12:18:31.244670 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 12:18:31.251423 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 12:18:31.254660 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 12:18:31.257733 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 12:18:31.264344 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 12:18:31.267655 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 12:18:31.271274 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 12:18:31.278055 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 12:18:31.280989 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 12:18:31.285301 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5435 12:18:31.291293 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5436 12:18:31.294358 Total UI for P1: 0, mck2ui 16
5437 12:18:31.297474 best dqsien dly found for B0: ( 1, 2, 28)
5438 12:18:31.301341 Total UI for P1: 0, mck2ui 16
5439 12:18:31.303798 best dqsien dly found for B1: ( 1, 2, 28)
5440 12:18:31.307573 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5441 12:18:31.310358 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5442 12:18:31.310816
5443 12:18:31.313894 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5444 12:18:31.317160 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5445 12:18:31.320323 [Gating] SW calibration Done
5446 12:18:31.320785 ==
5447 12:18:31.324352 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 12:18:31.327499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 12:18:31.328047 ==
5450 12:18:31.330518 RX Vref Scan: 0
5451 12:18:31.331070
5452 12:18:31.333702 RX Vref 0 -> 0, step: 1
5453 12:18:31.334162
5454 12:18:31.334525 RX Delay -80 -> 252, step: 8
5455 12:18:31.339910 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5456 12:18:31.343744 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5457 12:18:31.347084 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5458 12:18:31.349607 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5459 12:18:31.353358 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5460 12:18:31.359498 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5461 12:18:31.363096 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5462 12:18:31.366777 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5463 12:18:31.370013 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5464 12:18:31.372739 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5465 12:18:31.376690 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5466 12:18:31.383342 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5467 12:18:31.386202 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5468 12:18:31.389290 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5469 12:18:31.392590 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5470 12:18:31.396018 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5471 12:18:31.399773 ==
5472 12:18:31.402939 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 12:18:31.406429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 12:18:31.406973 ==
5475 12:18:31.407337 DQS Delay:
5476 12:18:31.409110 DQS0 = 0, DQS1 = 0
5477 12:18:31.409666 DQM Delay:
5478 12:18:31.412697 DQM0 = 97, DQM1 = 87
5479 12:18:31.413157 DQ Delay:
5480 12:18:31.416418 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5481 12:18:31.419548 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5482 12:18:31.423028 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5483 12:18:31.426796 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5484 12:18:31.427349
5485 12:18:31.427763
5486 12:18:31.428110 ==
5487 12:18:31.429443 Dram Type= 6, Freq= 0, CH_0, rank 1
5488 12:18:31.432219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 12:18:31.432711 ==
5490 12:18:31.433114
5491 12:18:31.436026
5492 12:18:31.436506 TX Vref Scan disable
5493 12:18:31.438998 == TX Byte 0 ==
5494 12:18:31.443611 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5495 12:18:31.445428 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5496 12:18:31.448948 == TX Byte 1 ==
5497 12:18:31.452126 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5498 12:18:31.455762 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5499 12:18:31.456179 ==
5500 12:18:31.459000 Dram Type= 6, Freq= 0, CH_0, rank 1
5501 12:18:31.466009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 12:18:31.466519 ==
5503 12:18:31.466850
5504 12:18:31.467151
5505 12:18:31.467440 TX Vref Scan disable
5506 12:18:31.469502 == TX Byte 0 ==
5507 12:18:31.473357 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5508 12:18:31.479901 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5509 12:18:31.480411 == TX Byte 1 ==
5510 12:18:31.482898 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5511 12:18:31.489354 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5512 12:18:31.489852
5513 12:18:31.490180 [DATLAT]
5514 12:18:31.490498 Freq=933, CH0 RK1
5515 12:18:31.490889
5516 12:18:31.493151 DATLAT Default: 0xb
5517 12:18:31.493658 0, 0xFFFF, sum = 0
5518 12:18:31.495985 1, 0xFFFF, sum = 0
5519 12:18:31.499483 2, 0xFFFF, sum = 0
5520 12:18:31.499930 3, 0xFFFF, sum = 0
5521 12:18:31.503246 4, 0xFFFF, sum = 0
5522 12:18:31.503800 5, 0xFFFF, sum = 0
5523 12:18:31.506494 6, 0xFFFF, sum = 0
5524 12:18:31.507012 7, 0xFFFF, sum = 0
5525 12:18:31.509299 8, 0xFFFF, sum = 0
5526 12:18:31.509721 9, 0xFFFF, sum = 0
5527 12:18:31.512205 10, 0x0, sum = 1
5528 12:18:31.512627 11, 0x0, sum = 2
5529 12:18:31.515965 12, 0x0, sum = 3
5530 12:18:31.516387 13, 0x0, sum = 4
5531 12:18:31.519363 best_step = 11
5532 12:18:31.519814
5533 12:18:31.520144 ==
5534 12:18:31.522255 Dram Type= 6, Freq= 0, CH_0, rank 1
5535 12:18:31.526275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 12:18:31.526790 ==
5537 12:18:31.527121 RX Vref Scan: 0
5538 12:18:31.529328
5539 12:18:31.529835 RX Vref 0 -> 0, step: 1
5540 12:18:31.530168
5541 12:18:31.531865 RX Delay -61 -> 252, step: 4
5542 12:18:31.539131 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5543 12:18:31.542161 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5544 12:18:31.545041 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5545 12:18:31.548299 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5546 12:18:31.552676 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5547 12:18:31.558185 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5548 12:18:31.561948 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5549 12:18:31.564590 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5550 12:18:31.568011 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5551 12:18:31.571255 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5552 12:18:31.578019 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5553 12:18:31.581187 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5554 12:18:31.585160 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5555 12:18:31.587894 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5556 12:18:31.591047 iDelay=203, Bit 14, Center 98 (11 ~ 186) 176
5557 12:18:31.597849 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5558 12:18:31.598399 ==
5559 12:18:31.602200 Dram Type= 6, Freq= 0, CH_0, rank 1
5560 12:18:31.604564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 12:18:31.605031 ==
5562 12:18:31.605396 DQS Delay:
5563 12:18:31.607733 DQS0 = 0, DQS1 = 0
5564 12:18:31.608300 DQM Delay:
5565 12:18:31.611217 DQM0 = 95, DQM1 = 86
5566 12:18:31.611825 DQ Delay:
5567 12:18:31.613985 DQ0 =94, DQ1 =96, DQ2 =90, DQ3 =94
5568 12:18:31.618006 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5569 12:18:31.620601 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5570 12:18:31.624622 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =92
5571 12:18:31.625175
5572 12:18:31.625544
5573 12:18:31.633950 [DQSOSCAuto] RK1, (LSB)MR18= 0x24f4, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 410 ps
5574 12:18:31.634558 CH0 RK1: MR19=504, MR18=24F4
5575 12:18:31.640746 CH0_RK1: MR19=0x504, MR18=0x24F4, DQSOSC=410, MR23=63, INC=64, DEC=42
5576 12:18:31.644194 [RxdqsGatingPostProcess] freq 933
5577 12:18:31.650219 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5578 12:18:31.653813 best DQS0 dly(2T, 0.5T) = (0, 10)
5579 12:18:31.657320 best DQS1 dly(2T, 0.5T) = (0, 11)
5580 12:18:31.660272 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5581 12:18:31.663822 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5582 12:18:31.667344 best DQS0 dly(2T, 0.5T) = (0, 10)
5583 12:18:31.667799 best DQS1 dly(2T, 0.5T) = (0, 10)
5584 12:18:31.670964 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5585 12:18:31.674378 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5586 12:18:31.676892 Pre-setting of DQS Precalculation
5587 12:18:31.683932 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5588 12:18:31.684492 ==
5589 12:18:31.687266 Dram Type= 6, Freq= 0, CH_1, rank 0
5590 12:18:31.690196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 12:18:31.690659 ==
5592 12:18:31.696466 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5593 12:18:31.703160 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5594 12:18:31.707126 [CA 0] Center 36 (6~67) winsize 62
5595 12:18:31.710263 [CA 1] Center 36 (6~67) winsize 62
5596 12:18:31.712653 [CA 2] Center 34 (4~64) winsize 61
5597 12:18:31.716584 [CA 3] Center 33 (3~64) winsize 62
5598 12:18:31.720314 [CA 4] Center 34 (4~64) winsize 61
5599 12:18:31.723298 [CA 5] Center 33 (3~64) winsize 62
5600 12:18:31.723887
5601 12:18:31.726856 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5602 12:18:31.727403
5603 12:18:31.729736 [CATrainingPosCal] consider 1 rank data
5604 12:18:31.733228 u2DelayCellTimex100 = 270/100 ps
5605 12:18:31.736339 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5606 12:18:31.739283 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5607 12:18:31.743467 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5608 12:18:31.746633 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5609 12:18:31.749471 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5610 12:18:31.756070 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5611 12:18:31.756622
5612 12:18:31.759575 CA PerBit enable=1, Macro0, CA PI delay=33
5613 12:18:31.760247
5614 12:18:31.762939 [CBTSetCACLKResult] CA Dly = 33
5615 12:18:31.763490 CS Dly: 5 (0~36)
5616 12:18:31.763921 ==
5617 12:18:31.766952 Dram Type= 6, Freq= 0, CH_1, rank 1
5618 12:18:31.769170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 12:18:31.772899 ==
5620 12:18:31.775812 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5621 12:18:31.782401 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5622 12:18:31.786589 [CA 0] Center 36 (6~67) winsize 62
5623 12:18:31.789403 [CA 1] Center 37 (7~67) winsize 61
5624 12:18:31.792613 [CA 2] Center 34 (4~65) winsize 62
5625 12:18:31.795474 [CA 3] Center 33 (3~64) winsize 62
5626 12:18:31.799300 [CA 4] Center 34 (3~65) winsize 63
5627 12:18:31.801986 [CA 5] Center 33 (3~64) winsize 62
5628 12:18:31.802539
5629 12:18:31.805393 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5630 12:18:31.805873
5631 12:18:31.808968 [CATrainingPosCal] consider 2 rank data
5632 12:18:31.812146 u2DelayCellTimex100 = 270/100 ps
5633 12:18:31.815722 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5634 12:18:31.819295 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5635 12:18:31.822229 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5636 12:18:31.828847 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5637 12:18:31.831971 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5638 12:18:31.835163 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5639 12:18:31.835771
5640 12:18:31.840071 CA PerBit enable=1, Macro0, CA PI delay=33
5641 12:18:31.840728
5642 12:18:31.842436 [CBTSetCACLKResult] CA Dly = 33
5643 12:18:31.842991 CS Dly: 6 (0~39)
5644 12:18:31.843401
5645 12:18:31.845538 ----->DramcWriteLeveling(PI) begin...
5646 12:18:31.849099 ==
5647 12:18:31.849552 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 12:18:31.855566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 12:18:31.856175 ==
5650 12:18:31.858250 Write leveling (Byte 0): 24 => 24
5651 12:18:31.861748 Write leveling (Byte 1): 26 => 26
5652 12:18:31.864815 DramcWriteLeveling(PI) end<-----
5653 12:18:31.865269
5654 12:18:31.865719 ==
5655 12:18:31.868596 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 12:18:31.871221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 12:18:31.871723 ==
5658 12:18:31.874507 [Gating] SW mode calibration
5659 12:18:31.881630 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5660 12:18:31.888198 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5661 12:18:31.891864 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5662 12:18:31.895768 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5663 12:18:31.901072 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5664 12:18:31.904278 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5665 12:18:31.907375 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5666 12:18:31.914450 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5667 12:18:31.917333 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5668 12:18:31.921392 0 14 28 | B1->B0 | 2d2d 2626 | 1 0 | (1 0) (0 0)
5669 12:18:31.927768 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5670 12:18:31.930645 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5671 12:18:31.933660 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 12:18:31.940463 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5673 12:18:31.943906 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5674 12:18:31.946716 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5675 12:18:31.954124 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5676 12:18:31.957445 0 15 28 | B1->B0 | 3a3a 3d3d | 0 0 | (0 0) (0 0)
5677 12:18:31.959944 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5678 12:18:31.967304 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 12:18:31.969840 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 12:18:31.973170 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 12:18:31.980222 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 12:18:31.984006 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5683 12:18:31.986350 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5684 12:18:31.993218 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5685 12:18:31.996366 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 12:18:32.000363 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 12:18:32.007521 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 12:18:32.010596 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 12:18:32.012812 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 12:18:32.020172 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 12:18:32.022467 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 12:18:32.026490 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 12:18:32.032626 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 12:18:32.036204 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 12:18:32.040308 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 12:18:32.045949 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 12:18:32.049412 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 12:18:32.052642 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 12:18:32.059017 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5700 12:18:32.062224 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5701 12:18:32.065582 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5702 12:18:32.069616 Total UI for P1: 0, mck2ui 16
5703 12:18:32.073411 best dqsien dly found for B0: ( 1, 2, 26)
5704 12:18:32.075230 Total UI for P1: 0, mck2ui 16
5705 12:18:32.078400 best dqsien dly found for B1: ( 1, 2, 26)
5706 12:18:32.081900 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5707 12:18:32.085823 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5708 12:18:32.086702
5709 12:18:32.091808 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5710 12:18:32.095344 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5711 12:18:32.098739 [Gating] SW calibration Done
5712 12:18:32.099291 ==
5713 12:18:32.101790 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 12:18:32.105448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 12:18:32.105961 ==
5716 12:18:32.106332 RX Vref Scan: 0
5717 12:18:32.106664
5718 12:18:32.108768 RX Vref 0 -> 0, step: 1
5719 12:18:32.109267
5720 12:18:32.112318 RX Delay -80 -> 252, step: 8
5721 12:18:32.114686 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5722 12:18:32.118214 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5723 12:18:32.125788 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5724 12:18:32.128231 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5725 12:18:32.131366 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5726 12:18:32.134671 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5727 12:18:32.138086 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5728 12:18:32.141682 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5729 12:18:32.148348 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5730 12:18:32.150980 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5731 12:18:32.154141 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5732 12:18:32.157647 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5733 12:18:32.161126 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5734 12:18:32.168019 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5735 12:18:32.170712 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5736 12:18:32.174157 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5737 12:18:32.174569 ==
5738 12:18:32.177400 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 12:18:32.181453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 12:18:32.181970 ==
5741 12:18:32.184686 DQS Delay:
5742 12:18:32.185195 DQS0 = 0, DQS1 = 0
5743 12:18:32.187065 DQM Delay:
5744 12:18:32.187470 DQM0 = 102, DQM1 = 90
5745 12:18:32.187836 DQ Delay:
5746 12:18:32.190511 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5747 12:18:32.194654 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5748 12:18:32.197411 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5749 12:18:32.201158 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5750 12:18:32.201574
5751 12:18:32.204425
5752 12:18:32.204940 ==
5753 12:18:32.207104 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 12:18:32.210333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 12:18:32.210749 ==
5756 12:18:32.211096
5757 12:18:32.211405
5758 12:18:32.213665 TX Vref Scan disable
5759 12:18:32.214315 == TX Byte 0 ==
5760 12:18:32.220575 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5761 12:18:32.223353 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5762 12:18:32.223920 == TX Byte 1 ==
5763 12:18:32.230473 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5764 12:18:32.235420 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5765 12:18:32.236034 ==
5766 12:18:32.236904 Dram Type= 6, Freq= 0, CH_1, rank 0
5767 12:18:32.241517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 12:18:32.241946 ==
5769 12:18:32.242297
5770 12:18:32.242604
5771 12:18:32.243824 TX Vref Scan disable
5772 12:18:32.246768 == TX Byte 0 ==
5773 12:18:32.250486 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5774 12:18:32.253987 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5775 12:18:32.256905 == TX Byte 1 ==
5776 12:18:32.260323 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5777 12:18:32.264146 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5778 12:18:32.264605
5779 12:18:32.266990 [DATLAT]
5780 12:18:32.267497 Freq=933, CH1 RK0
5781 12:18:32.267894
5782 12:18:32.269961 DATLAT Default: 0xd
5783 12:18:32.270371 0, 0xFFFF, sum = 0
5784 12:18:32.273367 1, 0xFFFF, sum = 0
5785 12:18:32.273861 2, 0xFFFF, sum = 0
5786 12:18:32.277226 3, 0xFFFF, sum = 0
5787 12:18:32.277803 4, 0xFFFF, sum = 0
5788 12:18:32.280109 5, 0xFFFF, sum = 0
5789 12:18:32.280659 6, 0xFFFF, sum = 0
5790 12:18:32.283341 7, 0xFFFF, sum = 0
5791 12:18:32.284128 8, 0xFFFF, sum = 0
5792 12:18:32.286560 9, 0xFFFF, sum = 0
5793 12:18:32.287119 10, 0x0, sum = 1
5794 12:18:32.290528 11, 0x0, sum = 2
5795 12:18:32.290990 12, 0x0, sum = 3
5796 12:18:32.293168 13, 0x0, sum = 4
5797 12:18:32.293631 best_step = 11
5798 12:18:32.293990
5799 12:18:32.294325 ==
5800 12:18:32.296230 Dram Type= 6, Freq= 0, CH_1, rank 0
5801 12:18:32.303365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 12:18:32.303958 ==
5803 12:18:32.304324 RX Vref Scan: 1
5804 12:18:32.304659
5805 12:18:32.307084 RX Vref 0 -> 0, step: 1
5806 12:18:32.307630
5807 12:18:32.309577 RX Delay -69 -> 252, step: 4
5808 12:18:32.310034
5809 12:18:32.313864 Set Vref, RX VrefLevel [Byte0]: 49
5810 12:18:32.316367 [Byte1]: 49
5811 12:18:32.316825
5812 12:18:32.319732 Final RX Vref Byte 0 = 49 to rank0
5813 12:18:32.323323 Final RX Vref Byte 1 = 49 to rank0
5814 12:18:32.326646 Final RX Vref Byte 0 = 49 to rank1
5815 12:18:32.329371 Final RX Vref Byte 1 = 49 to rank1==
5816 12:18:32.333054 Dram Type= 6, Freq= 0, CH_1, rank 0
5817 12:18:32.335920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 12:18:32.336385 ==
5819 12:18:32.339484 DQS Delay:
5820 12:18:32.339975 DQS0 = 0, DQS1 = 0
5821 12:18:32.343521 DQM Delay:
5822 12:18:32.344136 DQM0 = 100, DQM1 = 93
5823 12:18:32.344500 DQ Delay:
5824 12:18:32.345959 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5825 12:18:32.349423 DQ4 =98, DQ5 =110, DQ6 =108, DQ7 =98
5826 12:18:32.353255 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =84
5827 12:18:32.359260 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =104
5828 12:18:32.359761
5829 12:18:32.360132
5830 12:18:32.365472 [DQSOSCAuto] RK0, (LSB)MR18= 0x1708, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 414 ps
5831 12:18:32.368996 CH1 RK0: MR19=505, MR18=1708
5832 12:18:32.375412 CH1_RK0: MR19=0x505, MR18=0x1708, DQSOSC=414, MR23=63, INC=63, DEC=42
5833 12:18:32.375854
5834 12:18:32.378868 ----->DramcWriteLeveling(PI) begin...
5835 12:18:32.379284 ==
5836 12:18:32.382527 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 12:18:32.386534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 12:18:32.386947 ==
5839 12:18:32.389280 Write leveling (Byte 0): 28 => 28
5840 12:18:32.392350 Write leveling (Byte 1): 31 => 31
5841 12:18:32.395945 DramcWriteLeveling(PI) end<-----
5842 12:18:32.396612
5843 12:18:32.396953 ==
5844 12:18:32.399115 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 12:18:32.402756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 12:18:32.403274 ==
5847 12:18:32.406139 [Gating] SW mode calibration
5848 12:18:32.412029 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5849 12:18:32.418997 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5850 12:18:32.421991 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5851 12:18:32.428817 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5852 12:18:32.432362 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5853 12:18:32.434776 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5854 12:18:32.442235 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5855 12:18:32.445459 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5856 12:18:32.448229 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
5857 12:18:32.454714 0 14 28 | B1->B0 | 2c2c 2f2f | 0 1 | (1 0) (1 0)
5858 12:18:32.458377 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5859 12:18:32.461319 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5860 12:18:32.468226 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5861 12:18:32.472246 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5862 12:18:32.475184 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5863 12:18:32.481221 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5864 12:18:32.485074 0 15 24 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
5865 12:18:32.487711 0 15 28 | B1->B0 | 3737 3332 | 1 1 | (0 0) (0 0)
5866 12:18:32.494656 1 0 0 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5867 12:18:32.497950 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 12:18:32.501243 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 12:18:32.507567 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 12:18:32.511002 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 12:18:32.513887 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5872 12:18:32.521048 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5873 12:18:32.523954 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 12:18:32.527758 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 12:18:32.534044 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 12:18:32.537464 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 12:18:32.540674 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 12:18:32.547386 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 12:18:32.550688 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 12:18:32.553801 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 12:18:32.560087 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 12:18:32.563747 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 12:18:32.566887 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 12:18:32.573773 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 12:18:32.576891 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 12:18:32.580374 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 12:18:32.586322 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 12:18:32.590310 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5889 12:18:32.593361 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5890 12:18:32.600667 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5891 12:18:32.601223 Total UI for P1: 0, mck2ui 16
5892 12:18:32.606604 best dqsien dly found for B0: ( 1, 2, 26)
5893 12:18:32.607161 Total UI for P1: 0, mck2ui 16
5894 12:18:32.612956 best dqsien dly found for B1: ( 1, 2, 26)
5895 12:18:32.616435 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5896 12:18:32.619990 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5897 12:18:32.620539
5898 12:18:32.622820 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5899 12:18:32.625916 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5900 12:18:32.629656 [Gating] SW calibration Done
5901 12:18:32.630141 ==
5902 12:18:32.632538 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 12:18:32.635657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 12:18:32.636283 ==
5905 12:18:32.639255 RX Vref Scan: 0
5906 12:18:32.639760
5907 12:18:32.642307 RX Vref 0 -> 0, step: 1
5908 12:18:32.642760
5909 12:18:32.643123 RX Delay -80 -> 252, step: 8
5910 12:18:32.649458 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5911 12:18:32.652361 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5912 12:18:32.655616 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5913 12:18:32.659323 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5914 12:18:32.662347 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5915 12:18:32.665539 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5916 12:18:32.672568 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5917 12:18:32.675500 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5918 12:18:32.678834 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5919 12:18:32.682701 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5920 12:18:32.685736 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5921 12:18:32.692749 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5922 12:18:32.695415 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5923 12:18:32.698769 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5924 12:18:32.701867 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5925 12:18:32.705330 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5926 12:18:32.705842 ==
5927 12:18:32.709205 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 12:18:32.715576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 12:18:32.716139 ==
5930 12:18:32.716468 DQS Delay:
5931 12:18:32.718816 DQS0 = 0, DQS1 = 0
5932 12:18:32.719321 DQM Delay:
5933 12:18:32.719652 DQM0 = 100, DQM1 = 90
5934 12:18:32.721723 DQ Delay:
5935 12:18:32.725613 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5936 12:18:32.729163 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5937 12:18:32.732374 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5938 12:18:32.735166 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5939 12:18:32.735725
5940 12:18:32.736075
5941 12:18:32.736378 ==
5942 12:18:32.738511 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 12:18:32.742044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 12:18:32.742462 ==
5945 12:18:32.742836
5946 12:18:32.743197
5947 12:18:32.746080 TX Vref Scan disable
5948 12:18:32.748771 == TX Byte 0 ==
5949 12:18:32.751397 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5950 12:18:32.754495 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5951 12:18:32.758026 == TX Byte 1 ==
5952 12:18:32.761951 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5953 12:18:32.764470 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5954 12:18:32.764884 ==
5955 12:18:32.768422 Dram Type= 6, Freq= 0, CH_1, rank 1
5956 12:18:32.774938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5957 12:18:32.775461 ==
5958 12:18:32.775845
5959 12:18:32.776156
5960 12:18:32.776442 TX Vref Scan disable
5961 12:18:32.778966 == TX Byte 0 ==
5962 12:18:32.782111 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5963 12:18:32.788495 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5964 12:18:32.788991 == TX Byte 1 ==
5965 12:18:32.791667 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5966 12:18:32.798605 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5967 12:18:32.799116
5968 12:18:32.799443 [DATLAT]
5969 12:18:32.799798 Freq=933, CH1 RK1
5970 12:18:32.800098
5971 12:18:32.801831 DATLAT Default: 0xb
5972 12:18:32.802241 0, 0xFFFF, sum = 0
5973 12:18:32.804918 1, 0xFFFF, sum = 0
5974 12:18:32.807905 2, 0xFFFF, sum = 0
5975 12:18:32.808324 3, 0xFFFF, sum = 0
5976 12:18:32.811120 4, 0xFFFF, sum = 0
5977 12:18:32.811537 5, 0xFFFF, sum = 0
5978 12:18:32.814391 6, 0xFFFF, sum = 0
5979 12:18:32.814813 7, 0xFFFF, sum = 0
5980 12:18:32.817692 8, 0xFFFF, sum = 0
5981 12:18:32.818150 9, 0xFFFF, sum = 0
5982 12:18:32.821745 10, 0x0, sum = 1
5983 12:18:32.822300 11, 0x0, sum = 2
5984 12:18:32.824310 12, 0x0, sum = 3
5985 12:18:32.824773 13, 0x0, sum = 4
5986 12:18:32.828500 best_step = 11
5987 12:18:32.828951
5988 12:18:32.829310 ==
5989 12:18:32.830771 Dram Type= 6, Freq= 0, CH_1, rank 1
5990 12:18:32.834233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5991 12:18:32.834814 ==
5992 12:18:32.835182 RX Vref Scan: 0
5993 12:18:32.837312
5994 12:18:32.837861 RX Vref 0 -> 0, step: 1
5995 12:18:32.838225
5996 12:18:32.840426 RX Delay -69 -> 252, step: 4
5997 12:18:32.847423 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5998 12:18:32.850578 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
5999 12:18:32.854172 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6000 12:18:32.857155 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6001 12:18:32.860207 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
6002 12:18:32.867006 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6003 12:18:32.870549 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
6004 12:18:32.874561 iDelay=207, Bit 7, Center 96 (3 ~ 190) 188
6005 12:18:32.877138 iDelay=207, Bit 8, Center 80 (-9 ~ 170) 180
6006 12:18:32.880798 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6007 12:18:32.884477 iDelay=207, Bit 10, Center 92 (3 ~ 182) 180
6008 12:18:32.890461 iDelay=207, Bit 11, Center 82 (-5 ~ 170) 176
6009 12:18:32.893596 iDelay=207, Bit 12, Center 104 (11 ~ 198) 188
6010 12:18:32.896897 iDelay=207, Bit 13, Center 100 (11 ~ 190) 180
6011 12:18:32.899974 iDelay=207, Bit 14, Center 96 (3 ~ 190) 188
6012 12:18:32.906698 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6013 12:18:32.907108 ==
6014 12:18:32.910041 Dram Type= 6, Freq= 0, CH_1, rank 1
6015 12:18:32.914034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6016 12:18:32.914548 ==
6017 12:18:32.914876 DQS Delay:
6018 12:18:32.916760 DQS0 = 0, DQS1 = 0
6019 12:18:32.917175 DQM Delay:
6020 12:18:32.920043 DQM0 = 101, DQM1 = 92
6021 12:18:32.920559 DQ Delay:
6022 12:18:32.923372 DQ0 =104, DQ1 =96, DQ2 =90, DQ3 =98
6023 12:18:32.927555 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =96
6024 12:18:32.930446 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =82
6025 12:18:32.933306 DQ12 =104, DQ13 =100, DQ14 =96, DQ15 =102
6026 12:18:32.933859
6027 12:18:32.934222
6028 12:18:32.943389 [DQSOSCAuto] RK1, (LSB)MR18= 0x700, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 419 ps
6029 12:18:32.943884 CH1 RK1: MR19=505, MR18=700
6030 12:18:32.949714 CH1_RK1: MR19=0x505, MR18=0x700, DQSOSC=419, MR23=63, INC=61, DEC=41
6031 12:18:32.953067 [RxdqsGatingPostProcess] freq 933
6032 12:18:32.959570 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6033 12:18:32.962883 best DQS0 dly(2T, 0.5T) = (0, 10)
6034 12:18:32.966002 best DQS1 dly(2T, 0.5T) = (0, 10)
6035 12:18:32.969598 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6036 12:18:32.972454 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6037 12:18:32.976375 best DQS0 dly(2T, 0.5T) = (0, 10)
6038 12:18:32.979628 best DQS1 dly(2T, 0.5T) = (0, 10)
6039 12:18:32.982340 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6040 12:18:32.985605 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6041 12:18:32.986157 Pre-setting of DQS Precalculation
6042 12:18:32.992598 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6043 12:18:32.998809 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6044 12:18:33.005191 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6045 12:18:33.005648
6046 12:18:33.006007
6047 12:18:33.008794 [Calibration Summary] 1866 Mbps
6048 12:18:33.012107 CH 0, Rank 0
6049 12:18:33.012564 SW Impedance : PASS
6050 12:18:33.015728 DUTY Scan : NO K
6051 12:18:33.018813 ZQ Calibration : PASS
6052 12:18:33.019564 Jitter Meter : NO K
6053 12:18:33.022182 CBT Training : PASS
6054 12:18:33.024774 Write leveling : PASS
6055 12:18:33.025228 RX DQS gating : PASS
6056 12:18:33.028428 RX DQ/DQS(RDDQC) : PASS
6057 12:18:33.031518 TX DQ/DQS : PASS
6058 12:18:33.032134 RX DATLAT : PASS
6059 12:18:33.035078 RX DQ/DQS(Engine): PASS
6060 12:18:33.038388 TX OE : NO K
6061 12:18:33.038847 All Pass.
6062 12:18:33.039207
6063 12:18:33.039538 CH 0, Rank 1
6064 12:18:33.041695 SW Impedance : PASS
6065 12:18:33.044977 DUTY Scan : NO K
6066 12:18:33.045534 ZQ Calibration : PASS
6067 12:18:33.047916 Jitter Meter : NO K
6068 12:18:33.051317 CBT Training : PASS
6069 12:18:33.051804 Write leveling : PASS
6070 12:18:33.054714 RX DQS gating : PASS
6071 12:18:33.058532 RX DQ/DQS(RDDQC) : PASS
6072 12:18:33.059011 TX DQ/DQS : PASS
6073 12:18:33.061073 RX DATLAT : PASS
6074 12:18:33.061528 RX DQ/DQS(Engine): PASS
6075 12:18:33.064975 TX OE : NO K
6076 12:18:33.065531 All Pass.
6077 12:18:33.065894
6078 12:18:33.067789 CH 1, Rank 0
6079 12:18:33.068289 SW Impedance : PASS
6080 12:18:33.071194 DUTY Scan : NO K
6081 12:18:33.074728 ZQ Calibration : PASS
6082 12:18:33.075341 Jitter Meter : NO K
6083 12:18:33.077722 CBT Training : PASS
6084 12:18:33.081119 Write leveling : PASS
6085 12:18:33.081672 RX DQS gating : PASS
6086 12:18:33.084597 RX DQ/DQS(RDDQC) : PASS
6087 12:18:33.088047 TX DQ/DQS : PASS
6088 12:18:33.088604 RX DATLAT : PASS
6089 12:18:33.090793 RX DQ/DQS(Engine): PASS
6090 12:18:33.094376 TX OE : NO K
6091 12:18:33.094940 All Pass.
6092 12:18:33.095302
6093 12:18:33.095635 CH 1, Rank 1
6094 12:18:33.097698 SW Impedance : PASS
6095 12:18:33.100547 DUTY Scan : NO K
6096 12:18:33.101002 ZQ Calibration : PASS
6097 12:18:33.104330 Jitter Meter : NO K
6098 12:18:33.107132 CBT Training : PASS
6099 12:18:33.107589 Write leveling : PASS
6100 12:18:33.110603 RX DQS gating : PASS
6101 12:18:33.113905 RX DQ/DQS(RDDQC) : PASS
6102 12:18:33.114357 TX DQ/DQS : PASS
6103 12:18:33.117837 RX DATLAT : PASS
6104 12:18:33.120538 RX DQ/DQS(Engine): PASS
6105 12:18:33.120995 TX OE : NO K
6106 12:18:33.124371 All Pass.
6107 12:18:33.124928
6108 12:18:33.125335 DramC Write-DBI off
6109 12:18:33.127587 PER_BANK_REFRESH: Hybrid Mode
6110 12:18:33.128093 TX_TRACKING: ON
6111 12:18:33.137571 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6112 12:18:33.140803 [FAST_K] Save calibration result to emmc
6113 12:18:33.144128 dramc_set_vcore_voltage set vcore to 650000
6114 12:18:33.147277 Read voltage for 400, 6
6115 12:18:33.147774 Vio18 = 0
6116 12:18:33.150677 Vcore = 650000
6117 12:18:33.151131 Vdram = 0
6118 12:18:33.151492 Vddq = 0
6119 12:18:33.153500 Vmddr = 0
6120 12:18:33.157577 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6121 12:18:33.163281 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6122 12:18:33.163771 MEM_TYPE=3, freq_sel=20
6123 12:18:33.166420 sv_algorithm_assistance_LP4_800
6124 12:18:33.172897 ============ PULL DRAM RESETB DOWN ============
6125 12:18:33.176276 ========== PULL DRAM RESETB DOWN end =========
6126 12:18:33.180258 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6127 12:18:33.184733 ===================================
6128 12:18:33.186233 LPDDR4 DRAM CONFIGURATION
6129 12:18:33.189798 ===================================
6130 12:18:33.193579 EX_ROW_EN[0] = 0x0
6131 12:18:33.194237 EX_ROW_EN[1] = 0x0
6132 12:18:33.196402 LP4Y_EN = 0x0
6133 12:18:33.196812 WORK_FSP = 0x0
6134 12:18:33.199716 WL = 0x2
6135 12:18:33.200415 RL = 0x2
6136 12:18:33.203377 BL = 0x2
6137 12:18:33.203871 RPST = 0x0
6138 12:18:33.205608 RD_PRE = 0x0
6139 12:18:33.206021 WR_PRE = 0x1
6140 12:18:33.209543 WR_PST = 0x0
6141 12:18:33.209954 DBI_WR = 0x0
6142 12:18:33.212153 DBI_RD = 0x0
6143 12:18:33.212568 OTF = 0x1
6144 12:18:33.216086 ===================================
6145 12:18:33.219456 ===================================
6146 12:18:33.222172 ANA top config
6147 12:18:33.225846 ===================================
6148 12:18:33.229011 DLL_ASYNC_EN = 0
6149 12:18:33.229422 ALL_SLAVE_EN = 1
6150 12:18:33.232178 NEW_RANK_MODE = 1
6151 12:18:33.235596 DLL_IDLE_MODE = 1
6152 12:18:33.239359 LP45_APHY_COMB_EN = 1
6153 12:18:33.242114 TX_ODT_DIS = 1
6154 12:18:33.242605 NEW_8X_MODE = 1
6155 12:18:33.246029 ===================================
6156 12:18:33.248718 ===================================
6157 12:18:33.252110 data_rate = 800
6158 12:18:33.255172 CKR = 1
6159 12:18:33.259074 DQ_P2S_RATIO = 4
6160 12:18:33.261971 ===================================
6161 12:18:33.265533 CA_P2S_RATIO = 4
6162 12:18:33.268747 DQ_CA_OPEN = 0
6163 12:18:33.269225 DQ_SEMI_OPEN = 1
6164 12:18:33.271952 CA_SEMI_OPEN = 1
6165 12:18:33.275426 CA_FULL_RATE = 0
6166 12:18:33.278141 DQ_CKDIV4_EN = 0
6167 12:18:33.281718 CA_CKDIV4_EN = 1
6168 12:18:33.285705 CA_PREDIV_EN = 0
6169 12:18:33.286306 PH8_DLY = 0
6170 12:18:33.288443 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6171 12:18:33.291489 DQ_AAMCK_DIV = 0
6172 12:18:33.294837 CA_AAMCK_DIV = 0
6173 12:18:33.298764 CA_ADMCK_DIV = 4
6174 12:18:33.301423 DQ_TRACK_CA_EN = 0
6175 12:18:33.301938 CA_PICK = 800
6176 12:18:33.304862 CA_MCKIO = 400
6177 12:18:33.308542 MCKIO_SEMI = 400
6178 12:18:33.311992 PLL_FREQ = 3016
6179 12:18:33.315250 DQ_UI_PI_RATIO = 32
6180 12:18:33.317965 CA_UI_PI_RATIO = 32
6181 12:18:33.321515 ===================================
6182 12:18:33.324690 ===================================
6183 12:18:33.327993 memory_type:LPDDR4
6184 12:18:33.328511 GP_NUM : 10
6185 12:18:33.332449 SRAM_EN : 1
6186 12:18:33.332955 MD32_EN : 0
6187 12:18:33.334759 ===================================
6188 12:18:33.338297 [ANA_INIT] >>>>>>>>>>>>>>
6189 12:18:33.342065 <<<<<< [CONFIGURE PHASE]: ANA_TX
6190 12:18:33.345041 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6191 12:18:33.348126 ===================================
6192 12:18:33.351141 data_rate = 800,PCW = 0X7400
6193 12:18:33.354893 ===================================
6194 12:18:33.358207 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6195 12:18:33.364384 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6196 12:18:33.374929 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6197 12:18:33.377647 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6198 12:18:33.380746 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6199 12:18:33.387480 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6200 12:18:33.387933 [ANA_INIT] flow start
6201 12:18:33.390489 [ANA_INIT] PLL >>>>>>>>
6202 12:18:33.390905 [ANA_INIT] PLL <<<<<<<<
6203 12:18:33.394017 [ANA_INIT] MIDPI >>>>>>>>
6204 12:18:33.397254 [ANA_INIT] MIDPI <<<<<<<<
6205 12:18:33.400618 [ANA_INIT] DLL >>>>>>>>
6206 12:18:33.401034 [ANA_INIT] flow end
6207 12:18:33.403908 ============ LP4 DIFF to SE enter ============
6208 12:18:33.410278 ============ LP4 DIFF to SE exit ============
6209 12:18:33.410862 [ANA_INIT] <<<<<<<<<<<<<
6210 12:18:33.413793 [Flow] Enable top DCM control >>>>>
6211 12:18:33.416985 [Flow] Enable top DCM control <<<<<
6212 12:18:33.420442 Enable DLL master slave shuffle
6213 12:18:33.426772 ==============================================================
6214 12:18:33.427105 Gating Mode config
6215 12:18:33.433232 ==============================================================
6216 12:18:33.436619 Config description:
6217 12:18:33.446426 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6218 12:18:33.453591 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6219 12:18:33.457159 SELPH_MODE 0: By rank 1: By Phase
6220 12:18:33.463420 ==============================================================
6221 12:18:33.466912 GAT_TRACK_EN = 0
6222 12:18:33.470418 RX_GATING_MODE = 2
6223 12:18:33.473511 RX_GATING_TRACK_MODE = 2
6224 12:18:33.473658 SELPH_MODE = 1
6225 12:18:33.476662 PICG_EARLY_EN = 1
6226 12:18:33.479862 VALID_LAT_VALUE = 1
6227 12:18:33.486211 ==============================================================
6228 12:18:33.490662 Enter into Gating configuration >>>>
6229 12:18:33.493452 Exit from Gating configuration <<<<
6230 12:18:33.497535 Enter into DVFS_PRE_config >>>>>
6231 12:18:33.506009 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6232 12:18:33.509160 Exit from DVFS_PRE_config <<<<<
6233 12:18:33.512893 Enter into PICG configuration >>>>
6234 12:18:33.517126 Exit from PICG configuration <<<<
6235 12:18:33.519508 [RX_INPUT] configuration >>>>>
6236 12:18:33.522779 [RX_INPUT] configuration <<<<<
6237 12:18:33.526148 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6238 12:18:33.532314 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6239 12:18:33.539415 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6240 12:18:33.545964 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6241 12:18:33.552781 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6242 12:18:33.555829 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6243 12:18:33.562856 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6244 12:18:33.565897 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6245 12:18:33.568995 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6246 12:18:33.573303 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6247 12:18:33.579566 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6248 12:18:33.582008 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6249 12:18:33.585947 ===================================
6250 12:18:33.589206 LPDDR4 DRAM CONFIGURATION
6251 12:18:33.592505 ===================================
6252 12:18:33.592964 EX_ROW_EN[0] = 0x0
6253 12:18:33.595494 EX_ROW_EN[1] = 0x0
6254 12:18:33.595994 LP4Y_EN = 0x0
6255 12:18:33.598929 WORK_FSP = 0x0
6256 12:18:33.599475 WL = 0x2
6257 12:18:33.602421 RL = 0x2
6258 12:18:33.605710 BL = 0x2
6259 12:18:33.606167 RPST = 0x0
6260 12:18:33.609604 RD_PRE = 0x0
6261 12:18:33.610060 WR_PRE = 0x1
6262 12:18:33.612045 WR_PST = 0x0
6263 12:18:33.612498 DBI_WR = 0x0
6264 12:18:33.615860 DBI_RD = 0x0
6265 12:18:33.616406 OTF = 0x1
6266 12:18:33.619055 ===================================
6267 12:18:33.621986 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6268 12:18:33.628767 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6269 12:18:33.632253 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6270 12:18:33.634968 ===================================
6271 12:18:33.638950 LPDDR4 DRAM CONFIGURATION
6272 12:18:33.642157 ===================================
6273 12:18:33.642724 EX_ROW_EN[0] = 0x10
6274 12:18:33.645021 EX_ROW_EN[1] = 0x0
6275 12:18:33.645473 LP4Y_EN = 0x0
6276 12:18:33.649023 WORK_FSP = 0x0
6277 12:18:33.649480 WL = 0x2
6278 12:18:33.651812 RL = 0x2
6279 12:18:33.655156 BL = 0x2
6280 12:18:33.655758 RPST = 0x0
6281 12:18:33.658134 RD_PRE = 0x0
6282 12:18:33.658589 WR_PRE = 0x1
6283 12:18:33.661555 WR_PST = 0x0
6284 12:18:33.662007 DBI_WR = 0x0
6285 12:18:33.664884 DBI_RD = 0x0
6286 12:18:33.665335 OTF = 0x1
6287 12:18:33.668212 ===================================
6288 12:18:33.676301 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6289 12:18:33.678829 nWR fixed to 30
6290 12:18:33.682084 [ModeRegInit_LP4] CH0 RK0
6291 12:18:33.682603 [ModeRegInit_LP4] CH0 RK1
6292 12:18:33.686343 [ModeRegInit_LP4] CH1 RK0
6293 12:18:33.688890 [ModeRegInit_LP4] CH1 RK1
6294 12:18:33.689297 match AC timing 19
6295 12:18:33.695392 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6296 12:18:33.698503 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6297 12:18:33.702395 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6298 12:18:33.708371 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6299 12:18:33.712031 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6300 12:18:33.712443 ==
6301 12:18:33.715176 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 12:18:33.718021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 12:18:33.722784 ==
6304 12:18:33.724939 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6305 12:18:33.731447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6306 12:18:33.734437 [CA 0] Center 36 (8~64) winsize 57
6307 12:18:33.738373 [CA 1] Center 36 (8~64) winsize 57
6308 12:18:33.741569 [CA 2] Center 36 (8~64) winsize 57
6309 12:18:33.744691 [CA 3] Center 36 (8~64) winsize 57
6310 12:18:33.747841 [CA 4] Center 36 (8~64) winsize 57
6311 12:18:33.751414 [CA 5] Center 36 (8~64) winsize 57
6312 12:18:33.751971
6313 12:18:33.754644 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6314 12:18:33.755156
6315 12:18:33.757839 [CATrainingPosCal] consider 1 rank data
6316 12:18:33.760961 u2DelayCellTimex100 = 270/100 ps
6317 12:18:33.764406 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 12:18:33.767621 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 12:18:33.770952 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 12:18:33.774527 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 12:18:33.777367 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 12:18:33.780636 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 12:18:33.781047
6324 12:18:33.787529 CA PerBit enable=1, Macro0, CA PI delay=36
6325 12:18:33.788088
6326 12:18:33.790961 [CBTSetCACLKResult] CA Dly = 36
6327 12:18:33.791473 CS Dly: 1 (0~32)
6328 12:18:33.791859 ==
6329 12:18:33.793605 Dram Type= 6, Freq= 0, CH_0, rank 1
6330 12:18:33.796952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 12:18:33.797380 ==
6332 12:18:33.803874 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6333 12:18:33.810379 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6334 12:18:33.813520 [CA 0] Center 36 (8~64) winsize 57
6335 12:18:33.817057 [CA 1] Center 36 (8~64) winsize 57
6336 12:18:33.820682 [CA 2] Center 36 (8~64) winsize 57
6337 12:18:33.823840 [CA 3] Center 36 (8~64) winsize 57
6338 12:18:33.826971 [CA 4] Center 36 (8~64) winsize 57
6339 12:18:33.830491 [CA 5] Center 36 (8~64) winsize 57
6340 12:18:33.830956
6341 12:18:33.833352 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6342 12:18:33.833809
6343 12:18:33.837159 [CATrainingPosCal] consider 2 rank data
6344 12:18:33.840241 u2DelayCellTimex100 = 270/100 ps
6345 12:18:33.843275 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 12:18:33.846918 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 12:18:33.849927 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 12:18:33.853289 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 12:18:33.856353 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 12:18:33.859849 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6351 12:18:33.860442
6352 12:18:33.866575 CA PerBit enable=1, Macro0, CA PI delay=36
6353 12:18:33.867032
6354 12:18:33.867387 [CBTSetCACLKResult] CA Dly = 36
6355 12:18:33.869223 CS Dly: 1 (0~32)
6356 12:18:33.869680
6357 12:18:33.872891 ----->DramcWriteLeveling(PI) begin...
6358 12:18:33.873351 ==
6359 12:18:33.876207 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 12:18:33.879413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 12:18:33.879904 ==
6362 12:18:33.882685 Write leveling (Byte 0): 40 => 8
6363 12:18:33.886018 Write leveling (Byte 1): 32 => 0
6364 12:18:33.889243 DramcWriteLeveling(PI) end<-----
6365 12:18:33.889650
6366 12:18:33.889968 ==
6367 12:18:33.893506 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 12:18:33.896719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 12:18:33.899510 ==
6370 12:18:33.900080 [Gating] SW mode calibration
6371 12:18:33.910006 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6372 12:18:33.913171 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6373 12:18:33.915696 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6374 12:18:33.922601 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6375 12:18:33.926498 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6376 12:18:33.929134 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6377 12:18:33.935651 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6378 12:18:33.938928 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6379 12:18:33.942411 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6380 12:18:33.948785 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6381 12:18:33.952105 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6382 12:18:33.954944 Total UI for P1: 0, mck2ui 16
6383 12:18:33.958523 best dqsien dly found for B0: ( 0, 14, 24)
6384 12:18:33.962354 Total UI for P1: 0, mck2ui 16
6385 12:18:33.964802 best dqsien dly found for B1: ( 0, 14, 24)
6386 12:18:33.968409 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6387 12:18:33.971531 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6388 12:18:33.971980
6389 12:18:33.975576 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6390 12:18:33.982291 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6391 12:18:33.982846 [Gating] SW calibration Done
6392 12:18:33.983209 ==
6393 12:18:33.985025 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 12:18:33.991891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 12:18:33.992447 ==
6396 12:18:33.992815 RX Vref Scan: 0
6397 12:18:33.993155
6398 12:18:33.995339 RX Vref 0 -> 0, step: 1
6399 12:18:33.995843
6400 12:18:33.998095 RX Delay -410 -> 252, step: 16
6401 12:18:34.001950 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6402 12:18:34.005310 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6403 12:18:34.011077 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6404 12:18:34.015922 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6405 12:18:34.018530 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6406 12:18:34.022115 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6407 12:18:34.028108 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6408 12:18:34.031517 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6409 12:18:34.034323 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6410 12:18:34.038037 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6411 12:18:34.044625 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6412 12:18:34.047417 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6413 12:18:34.051034 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6414 12:18:34.057692 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6415 12:18:34.060689 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6416 12:18:34.064258 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6417 12:18:34.064715 ==
6418 12:18:34.067310 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 12:18:34.070771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 12:18:34.074584 ==
6421 12:18:34.075062 DQS Delay:
6422 12:18:34.075424 DQS0 = 43, DQS1 = 59
6423 12:18:34.077091 DQM Delay:
6424 12:18:34.077549 DQM0 = 9, DQM1 = 12
6425 12:18:34.080260 DQ Delay:
6426 12:18:34.080717 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6427 12:18:34.084332 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6428 12:18:34.087090 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6429 12:18:34.090367 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6430 12:18:34.090832
6431 12:18:34.091193
6432 12:18:34.093526 ==
6433 12:18:34.094078 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 12:18:34.100609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 12:18:34.101027 ==
6436 12:18:34.101356
6437 12:18:34.101660
6438 12:18:34.103407 TX Vref Scan disable
6439 12:18:34.103856 == TX Byte 0 ==
6440 12:18:34.107835 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6441 12:18:34.113913 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6442 12:18:34.114326 == TX Byte 1 ==
6443 12:18:34.116184 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6444 12:18:34.123106 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6445 12:18:34.123557 ==
6446 12:18:34.127849 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 12:18:34.130033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 12:18:34.130604 ==
6449 12:18:34.130976
6450 12:18:34.131310
6451 12:18:34.132914 TX Vref Scan disable
6452 12:18:34.133393 == TX Byte 0 ==
6453 12:18:34.140060 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6454 12:18:34.143288 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6455 12:18:34.143780 == TX Byte 1 ==
6456 12:18:34.149967 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6457 12:18:34.153677 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6458 12:18:34.154231
6459 12:18:34.154591 [DATLAT]
6460 12:18:34.156414 Freq=400, CH0 RK0
6461 12:18:34.156870
6462 12:18:34.157225 DATLAT Default: 0xf
6463 12:18:34.159479 0, 0xFFFF, sum = 0
6464 12:18:34.160143 1, 0xFFFF, sum = 0
6465 12:18:34.162430 2, 0xFFFF, sum = 0
6466 12:18:34.162895 3, 0xFFFF, sum = 0
6467 12:18:34.165741 4, 0xFFFF, sum = 0
6468 12:18:34.166255 5, 0xFFFF, sum = 0
6469 12:18:34.169435 6, 0xFFFF, sum = 0
6470 12:18:34.169895 7, 0xFFFF, sum = 0
6471 12:18:34.173062 8, 0xFFFF, sum = 0
6472 12:18:34.173561 9, 0xFFFF, sum = 0
6473 12:18:34.176860 10, 0xFFFF, sum = 0
6474 12:18:34.179519 11, 0xFFFF, sum = 0
6475 12:18:34.180014 12, 0xFFFF, sum = 0
6476 12:18:34.182715 13, 0x0, sum = 1
6477 12:18:34.183176 14, 0x0, sum = 2
6478 12:18:34.183541 15, 0x0, sum = 3
6479 12:18:34.186385 16, 0x0, sum = 4
6480 12:18:34.186941 best_step = 14
6481 12:18:34.187304
6482 12:18:34.189358 ==
6483 12:18:34.189914 Dram Type= 6, Freq= 0, CH_0, rank 0
6484 12:18:34.195961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 12:18:34.196529 ==
6486 12:18:34.196898 RX Vref Scan: 1
6487 12:18:34.197233
6488 12:18:34.199130 RX Vref 0 -> 0, step: 1
6489 12:18:34.199583
6490 12:18:34.202412 RX Delay -359 -> 252, step: 8
6491 12:18:34.202986
6492 12:18:34.205469 Set Vref, RX VrefLevel [Byte0]: 60
6493 12:18:34.208965 [Byte1]: 48
6494 12:18:34.212543
6495 12:18:34.213002 Final RX Vref Byte 0 = 60 to rank0
6496 12:18:34.215916 Final RX Vref Byte 1 = 48 to rank0
6497 12:18:34.219431 Final RX Vref Byte 0 = 60 to rank1
6498 12:18:34.223227 Final RX Vref Byte 1 = 48 to rank1==
6499 12:18:34.225960 Dram Type= 6, Freq= 0, CH_0, rank 0
6500 12:18:34.232540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 12:18:34.233044 ==
6502 12:18:34.233419 DQS Delay:
6503 12:18:34.236291 DQS0 = 48, DQS1 = 60
6504 12:18:34.236744 DQM Delay:
6505 12:18:34.237164 DQM0 = 11, DQM1 = 12
6506 12:18:34.239479 DQ Delay:
6507 12:18:34.242856 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6508 12:18:34.245931 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6509 12:18:34.246490 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6510 12:18:34.249354 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6511 12:18:34.253880
6512 12:18:34.254606
6513 12:18:34.259052 [DQSOSCAuto] RK0, (LSB)MR18= 0xba7d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 386 ps
6514 12:18:34.262211 CH0 RK0: MR19=C0C, MR18=BA7D
6515 12:18:34.268709 CH0_RK0: MR19=0xC0C, MR18=0xBA7D, DQSOSC=386, MR23=63, INC=396, DEC=264
6516 12:18:34.269169 ==
6517 12:18:34.272342 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 12:18:34.275564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 12:18:34.276167 ==
6520 12:18:34.278486 [Gating] SW mode calibration
6521 12:18:34.285468 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6522 12:18:34.292159 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6523 12:18:34.294993 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6524 12:18:34.298776 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6525 12:18:34.305506 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6526 12:18:34.308051 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6527 12:18:34.311527 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6528 12:18:34.318679 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6529 12:18:34.321562 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6530 12:18:34.324483 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6531 12:18:34.331285 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6532 12:18:34.334788 Total UI for P1: 0, mck2ui 16
6533 12:18:34.338148 best dqsien dly found for B0: ( 0, 14, 24)
6534 12:18:34.338565 Total UI for P1: 0, mck2ui 16
6535 12:18:34.344842 best dqsien dly found for B1: ( 0, 14, 24)
6536 12:18:34.348092 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6537 12:18:34.350765 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6538 12:18:34.351273
6539 12:18:34.354345 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6540 12:18:34.357633 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6541 12:18:34.361632 [Gating] SW calibration Done
6542 12:18:34.362045 ==
6543 12:18:34.364229 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 12:18:34.367976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 12:18:34.368392 ==
6546 12:18:34.370912 RX Vref Scan: 0
6547 12:18:34.371321
6548 12:18:34.374200 RX Vref 0 -> 0, step: 1
6549 12:18:34.374614
6550 12:18:34.374938 RX Delay -410 -> 252, step: 16
6551 12:18:34.381498 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6552 12:18:34.384564 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6553 12:18:34.387420 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6554 12:18:34.394020 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6555 12:18:34.397197 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6556 12:18:34.400500 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6557 12:18:34.403996 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6558 12:18:34.410546 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6559 12:18:34.414011 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6560 12:18:34.417303 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6561 12:18:34.420867 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6562 12:18:34.427051 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6563 12:18:34.430131 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6564 12:18:34.433338 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6565 12:18:34.436763 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6566 12:18:34.443587 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6567 12:18:34.444111 ==
6568 12:18:34.446872 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 12:18:34.450655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 12:18:34.451352 ==
6571 12:18:34.453107 DQS Delay:
6572 12:18:34.453636 DQS0 = 43, DQS1 = 59
6573 12:18:34.453967 DQM Delay:
6574 12:18:34.457416 DQM0 = 10, DQM1 = 16
6575 12:18:34.457965 DQ Delay:
6576 12:18:34.459987 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6577 12:18:34.463372 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6578 12:18:34.466497 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6579 12:18:34.469647 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6580 12:18:34.470127
6581 12:18:34.470549
6582 12:18:34.470906 ==
6583 12:18:34.472560 Dram Type= 6, Freq= 0, CH_0, rank 1
6584 12:18:34.476432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 12:18:34.479953 ==
6586 12:18:34.480363
6587 12:18:34.480685
6588 12:18:34.480987 TX Vref Scan disable
6589 12:18:34.482748 == TX Byte 0 ==
6590 12:18:34.486729 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6591 12:18:34.489475 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6592 12:18:34.492737 == TX Byte 1 ==
6593 12:18:34.496124 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6594 12:18:34.498960 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6595 12:18:34.499372 ==
6596 12:18:34.502694 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 12:18:34.509962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 12:18:34.510489 ==
6599 12:18:34.510823
6600 12:18:34.511125
6601 12:18:34.511415 TX Vref Scan disable
6602 12:18:34.512414 == TX Byte 0 ==
6603 12:18:34.516206 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6604 12:18:34.518946 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6605 12:18:34.522723 == TX Byte 1 ==
6606 12:18:34.525352 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6607 12:18:34.529005 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6608 12:18:34.529522
6609 12:18:34.532044 [DATLAT]
6610 12:18:34.532453 Freq=400, CH0 RK1
6611 12:18:34.532779
6612 12:18:34.536708 DATLAT Default: 0xe
6613 12:18:34.537220 0, 0xFFFF, sum = 0
6614 12:18:34.538836 1, 0xFFFF, sum = 0
6615 12:18:34.539251 2, 0xFFFF, sum = 0
6616 12:18:34.543033 3, 0xFFFF, sum = 0
6617 12:18:34.543556 4, 0xFFFF, sum = 0
6618 12:18:34.545562 5, 0xFFFF, sum = 0
6619 12:18:34.546082 6, 0xFFFF, sum = 0
6620 12:18:34.549148 7, 0xFFFF, sum = 0
6621 12:18:34.549671 8, 0xFFFF, sum = 0
6622 12:18:34.551873 9, 0xFFFF, sum = 0
6623 12:18:34.552296 10, 0xFFFF, sum = 0
6624 12:18:34.555240 11, 0xFFFF, sum = 0
6625 12:18:34.558707 12, 0xFFFF, sum = 0
6626 12:18:34.559149 13, 0x0, sum = 1
6627 12:18:34.559601 14, 0x0, sum = 2
6628 12:18:34.561893 15, 0x0, sum = 3
6629 12:18:34.562335 16, 0x0, sum = 4
6630 12:18:34.565268 best_step = 14
6631 12:18:34.565703
6632 12:18:34.566144 ==
6633 12:18:34.568573 Dram Type= 6, Freq= 0, CH_0, rank 1
6634 12:18:34.571616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 12:18:34.572089 ==
6636 12:18:34.575361 RX Vref Scan: 0
6637 12:18:34.575825
6638 12:18:34.576165 RX Vref 0 -> 0, step: 1
6639 12:18:34.578229
6640 12:18:34.578644 RX Delay -359 -> 252, step: 8
6641 12:18:34.587464 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6642 12:18:34.590772 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6643 12:18:34.593974 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6644 12:18:34.597053 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6645 12:18:34.603759 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6646 12:18:34.607163 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6647 12:18:34.610335 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6648 12:18:34.616510 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6649 12:18:34.619946 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6650 12:18:34.623821 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6651 12:18:34.626370 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6652 12:18:34.633551 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6653 12:18:34.636555 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6654 12:18:34.640374 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6655 12:18:34.643265 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6656 12:18:34.650414 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6657 12:18:34.650972 ==
6658 12:18:34.653220 Dram Type= 6, Freq= 0, CH_0, rank 1
6659 12:18:34.656264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 12:18:34.656726 ==
6661 12:18:34.657085 DQS Delay:
6662 12:18:34.660106 DQS0 = 44, DQS1 = 60
6663 12:18:34.660652 DQM Delay:
6664 12:18:34.662962 DQM0 = 8, DQM1 = 15
6665 12:18:34.663418 DQ Delay:
6666 12:18:34.666244 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6667 12:18:34.669630 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6668 12:18:34.674013 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6669 12:18:34.676355 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6670 12:18:34.676816
6671 12:18:34.677173
6672 12:18:34.683716 [DQSOSCAuto] RK1, (LSB)MR18= 0xb844, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6673 12:18:34.685840 CH0 RK1: MR19=C0C, MR18=B844
6674 12:18:34.692825 CH0_RK1: MR19=0xC0C, MR18=0xB844, DQSOSC=386, MR23=63, INC=396, DEC=264
6675 12:18:34.695812 [RxdqsGatingPostProcess] freq 400
6676 12:18:34.702762 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6677 12:18:34.705566 best DQS0 dly(2T, 0.5T) = (0, 10)
6678 12:18:34.709154 best DQS1 dly(2T, 0.5T) = (0, 10)
6679 12:18:34.712823 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6680 12:18:34.715346 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6681 12:18:34.719186 best DQS0 dly(2T, 0.5T) = (0, 10)
6682 12:18:34.719779 best DQS1 dly(2T, 0.5T) = (0, 10)
6683 12:18:34.722351 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6684 12:18:34.725402 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6685 12:18:34.728718 Pre-setting of DQS Precalculation
6686 12:18:34.735553 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6687 12:18:34.736042 ==
6688 12:18:34.738583 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 12:18:34.742768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 12:18:34.743228 ==
6691 12:18:34.749126 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6692 12:18:34.755257 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6693 12:18:34.758557 [CA 0] Center 36 (8~64) winsize 57
6694 12:18:34.762354 [CA 1] Center 36 (8~64) winsize 57
6695 12:18:34.764904 [CA 2] Center 36 (8~64) winsize 57
6696 12:18:34.765375 [CA 3] Center 36 (8~64) winsize 57
6697 12:18:34.767942 [CA 4] Center 36 (8~64) winsize 57
6698 12:18:34.771589 [CA 5] Center 36 (8~64) winsize 57
6699 12:18:34.772195
6700 12:18:34.778572 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6701 12:18:34.779124
6702 12:18:34.781420 [CATrainingPosCal] consider 1 rank data
6703 12:18:34.784630 u2DelayCellTimex100 = 270/100 ps
6704 12:18:34.788396 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 12:18:34.791195 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 12:18:34.795281 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 12:18:34.797702 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 12:18:34.802001 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 12:18:34.804869 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 12:18:34.805426
6711 12:18:34.807845 CA PerBit enable=1, Macro0, CA PI delay=36
6712 12:18:34.808399
6713 12:18:34.811162 [CBTSetCACLKResult] CA Dly = 36
6714 12:18:34.814977 CS Dly: 1 (0~32)
6715 12:18:34.815432 ==
6716 12:18:34.817702 Dram Type= 6, Freq= 0, CH_1, rank 1
6717 12:18:34.821630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 12:18:34.822188 ==
6719 12:18:34.827874 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6720 12:18:34.834514 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6721 12:18:34.838446 [CA 0] Center 36 (8~64) winsize 57
6722 12:18:34.839002 [CA 1] Center 36 (8~64) winsize 57
6723 12:18:34.840855 [CA 2] Center 36 (8~64) winsize 57
6724 12:18:34.844467 [CA 3] Center 36 (8~64) winsize 57
6725 12:18:34.848035 [CA 4] Center 36 (8~64) winsize 57
6726 12:18:34.851003 [CA 5] Center 36 (8~64) winsize 57
6727 12:18:34.851459
6728 12:18:34.854197 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6729 12:18:34.854651
6730 12:18:34.858026 [CATrainingPosCal] consider 2 rank data
6731 12:18:34.861515 u2DelayCellTimex100 = 270/100 ps
6732 12:18:34.864147 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 12:18:34.870615 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 12:18:34.873674 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 12:18:34.876778 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 12:18:34.881337 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 12:18:34.883442 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6738 12:18:34.883958
6739 12:18:34.886821 CA PerBit enable=1, Macro0, CA PI delay=36
6740 12:18:34.887278
6741 12:18:34.890217 [CBTSetCACLKResult] CA Dly = 36
6742 12:18:34.893818 CS Dly: 1 (0~32)
6743 12:18:34.894228
6744 12:18:34.896904 ----->DramcWriteLeveling(PI) begin...
6745 12:18:34.897322 ==
6746 12:18:34.900235 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 12:18:34.903283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 12:18:34.903838 ==
6749 12:18:34.907029 Write leveling (Byte 0): 40 => 8
6750 12:18:34.910658 Write leveling (Byte 1): 32 => 0
6751 12:18:34.913314 DramcWriteLeveling(PI) end<-----
6752 12:18:34.913767
6753 12:18:34.914125 ==
6754 12:18:34.917209 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 12:18:34.921663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 12:18:34.922177 ==
6757 12:18:34.923213 [Gating] SW mode calibration
6758 12:18:34.930624 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6759 12:18:34.936998 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6760 12:18:34.939701 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6761 12:18:34.943796 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6762 12:18:34.950517 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6763 12:18:34.953373 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6764 12:18:34.957030 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6765 12:18:34.963372 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6766 12:18:34.967176 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6767 12:18:34.969995 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6768 12:18:34.976177 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6769 12:18:34.976645 Total UI for P1: 0, mck2ui 16
6770 12:18:34.982996 best dqsien dly found for B0: ( 0, 14, 24)
6771 12:18:34.983567 Total UI for P1: 0, mck2ui 16
6772 12:18:34.989402 best dqsien dly found for B1: ( 0, 14, 24)
6773 12:18:34.993132 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6774 12:18:34.995669 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6775 12:18:34.996169
6776 12:18:34.999272 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6777 12:18:35.002543 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6778 12:18:35.006568 [Gating] SW calibration Done
6779 12:18:35.007030 ==
6780 12:18:35.009212 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 12:18:35.012758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 12:18:35.013326 ==
6783 12:18:35.015582 RX Vref Scan: 0
6784 12:18:35.016083
6785 12:18:35.019102 RX Vref 0 -> 0, step: 1
6786 12:18:35.019564
6787 12:18:35.019971 RX Delay -410 -> 252, step: 16
6788 12:18:35.025933 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6789 12:18:35.029960 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6790 12:18:35.033549 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6791 12:18:35.038794 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6792 12:18:35.042006 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6793 12:18:35.046541 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6794 12:18:35.048281 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6795 12:18:35.055551 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6796 12:18:35.058402 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6797 12:18:35.061784 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6798 12:18:35.065554 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6799 12:18:35.071896 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6800 12:18:35.075330 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6801 12:18:35.078597 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6802 12:18:35.081866 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6803 12:18:35.088376 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6804 12:18:35.088938 ==
6805 12:18:35.091400 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 12:18:35.095088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 12:18:35.095555 ==
6808 12:18:35.097963 DQS Delay:
6809 12:18:35.098531 DQS0 = 43, DQS1 = 51
6810 12:18:35.098924 DQM Delay:
6811 12:18:35.101671 DQM0 = 12, DQM1 = 14
6812 12:18:35.102235 DQ Delay:
6813 12:18:35.104238 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6814 12:18:35.107775 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6815 12:18:35.111099 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6816 12:18:35.114610 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6817 12:18:35.115092
6818 12:18:35.115471
6819 12:18:35.115850 ==
6820 12:18:35.117919 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 12:18:35.121555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 12:18:35.124528 ==
6823 12:18:35.124987
6824 12:18:35.125345
6825 12:18:35.125778 TX Vref Scan disable
6826 12:18:35.127740 == TX Byte 0 ==
6827 12:18:35.130535 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6828 12:18:35.134911 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6829 12:18:35.137253 == TX Byte 1 ==
6830 12:18:35.140938 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6831 12:18:35.143914 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6832 12:18:35.144373 ==
6833 12:18:35.147580 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 12:18:35.154293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 12:18:35.154753 ==
6836 12:18:35.155112
6837 12:18:35.155413
6838 12:18:35.155740 TX Vref Scan disable
6839 12:18:35.157256 == TX Byte 0 ==
6840 12:18:35.160559 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6841 12:18:35.163370 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6842 12:18:35.166895 == TX Byte 1 ==
6843 12:18:35.170149 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6844 12:18:35.173954 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6845 12:18:35.176934
6846 12:18:35.177396 [DATLAT]
6847 12:18:35.177763 Freq=400, CH1 RK0
6848 12:18:35.178191
6849 12:18:35.180167 DATLAT Default: 0xf
6850 12:18:35.180628 0, 0xFFFF, sum = 0
6851 12:18:35.183559 1, 0xFFFF, sum = 0
6852 12:18:35.184025 2, 0xFFFF, sum = 0
6853 12:18:35.187242 3, 0xFFFF, sum = 0
6854 12:18:35.187864 4, 0xFFFF, sum = 0
6855 12:18:35.190395 5, 0xFFFF, sum = 0
6856 12:18:35.193352 6, 0xFFFF, sum = 0
6857 12:18:35.193824 7, 0xFFFF, sum = 0
6858 12:18:35.196847 8, 0xFFFF, sum = 0
6859 12:18:35.197316 9, 0xFFFF, sum = 0
6860 12:18:35.200496 10, 0xFFFF, sum = 0
6861 12:18:35.200920 11, 0xFFFF, sum = 0
6862 12:18:35.203893 12, 0xFFFF, sum = 0
6863 12:18:35.204312 13, 0x0, sum = 1
6864 12:18:35.206553 14, 0x0, sum = 2
6865 12:18:35.206966 15, 0x0, sum = 3
6866 12:18:35.209779 16, 0x0, sum = 4
6867 12:18:35.210195 best_step = 14
6868 12:18:35.210519
6869 12:18:35.210820 ==
6870 12:18:35.212946 Dram Type= 6, Freq= 0, CH_1, rank 0
6871 12:18:35.216294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 12:18:35.219953 ==
6873 12:18:35.220466 RX Vref Scan: 1
6874 12:18:35.220797
6875 12:18:35.223377 RX Vref 0 -> 0, step: 1
6876 12:18:35.223983
6877 12:18:35.227031 RX Delay -343 -> 252, step: 8
6878 12:18:35.227581
6879 12:18:35.229875 Set Vref, RX VrefLevel [Byte0]: 49
6880 12:18:35.233343 [Byte1]: 49
6881 12:18:35.233896
6882 12:18:35.236574 Final RX Vref Byte 0 = 49 to rank0
6883 12:18:35.239973 Final RX Vref Byte 1 = 49 to rank0
6884 12:18:35.243466 Final RX Vref Byte 0 = 49 to rank1
6885 12:18:35.246679 Final RX Vref Byte 1 = 49 to rank1==
6886 12:18:35.249268 Dram Type= 6, Freq= 0, CH_1, rank 0
6887 12:18:35.252816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 12:18:35.253278 ==
6889 12:18:35.256464 DQS Delay:
6890 12:18:35.257033 DQS0 = 44, DQS1 = 52
6891 12:18:35.260058 DQM Delay:
6892 12:18:35.260671 DQM0 = 8, DQM1 = 8
6893 12:18:35.261213 DQ Delay:
6894 12:18:35.262357 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6895 12:18:35.266150 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =4
6896 12:18:35.269342 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6897 12:18:35.272597 DQ12 =16, DQ13 =12, DQ14 =16, DQ15 =16
6898 12:18:35.273071
6899 12:18:35.273433
6900 12:18:35.282690 [DQSOSCAuto] RK0, (LSB)MR18= 0x966d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6901 12:18:35.286049 CH1 RK0: MR19=C0C, MR18=966D
6902 12:18:35.289631 CH1_RK0: MR19=0xC0C, MR18=0x966D, DQSOSC=391, MR23=63, INC=386, DEC=257
6903 12:18:35.292343 ==
6904 12:18:35.292799 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 12:18:35.298932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 12:18:35.299392 ==
6907 12:18:35.302696 [Gating] SW mode calibration
6908 12:18:35.309191 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6909 12:18:35.312422 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6910 12:18:35.319526 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6911 12:18:35.323047 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6912 12:18:35.325232 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6913 12:18:35.332035 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6914 12:18:35.335644 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6915 12:18:35.338700 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6916 12:18:35.345511 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6917 12:18:35.348626 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6918 12:18:35.352487 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6919 12:18:35.354954 Total UI for P1: 0, mck2ui 16
6920 12:18:35.358326 best dqsien dly found for B0: ( 0, 14, 24)
6921 12:18:35.361562 Total UI for P1: 0, mck2ui 16
6922 12:18:35.364461 best dqsien dly found for B1: ( 0, 14, 24)
6923 12:18:35.368681 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6924 12:18:35.371938 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6925 12:18:35.374700
6926 12:18:35.378021 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6927 12:18:35.381696 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6928 12:18:35.384589 [Gating] SW calibration Done
6929 12:18:35.385047 ==
6930 12:18:35.387819 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 12:18:35.391989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 12:18:35.392449 ==
6933 12:18:35.392806 RX Vref Scan: 0
6934 12:18:35.395130
6935 12:18:35.395600 RX Vref 0 -> 0, step: 1
6936 12:18:35.396078
6937 12:18:35.398337 RX Delay -410 -> 252, step: 16
6938 12:18:35.401056 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6939 12:18:35.407754 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6940 12:18:35.410970 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6941 12:18:35.414001 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6942 12:18:35.417657 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6943 12:18:35.424347 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6944 12:18:35.427381 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6945 12:18:35.430807 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6946 12:18:35.437382 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6947 12:18:35.440950 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6948 12:18:35.443811 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6949 12:18:35.447486 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6950 12:18:35.453436 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6951 12:18:35.457264 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6952 12:18:35.460300 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6953 12:18:35.463541 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6954 12:18:35.467264 ==
6955 12:18:35.467827 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 12:18:35.474067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 12:18:35.474544 ==
6958 12:18:35.474881 DQS Delay:
6959 12:18:35.477031 DQS0 = 51, DQS1 = 51
6960 12:18:35.477544 DQM Delay:
6961 12:18:35.480172 DQM0 = 19, DQM1 = 12
6962 12:18:35.480676 DQ Delay:
6963 12:18:35.483281 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6964 12:18:35.487491 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6965 12:18:35.490754 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6966 12:18:35.493220 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6967 12:18:35.493686
6968 12:18:35.494050
6969 12:18:35.494392 ==
6970 12:18:35.496756 Dram Type= 6, Freq= 0, CH_1, rank 1
6971 12:18:35.499858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6972 12:18:35.500330 ==
6973 12:18:35.500697
6974 12:18:35.501033
6975 12:18:35.503424 TX Vref Scan disable
6976 12:18:35.503923 == TX Byte 0 ==
6977 12:18:35.510078 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6978 12:18:35.513802 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6979 12:18:35.514285 == TX Byte 1 ==
6980 12:18:35.519618 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6981 12:18:35.523176 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6982 12:18:35.523734 ==
6983 12:18:35.526270 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 12:18:35.529655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 12:18:35.530115 ==
6986 12:18:35.530473
6987 12:18:35.530805
6988 12:18:35.533140 TX Vref Scan disable
6989 12:18:35.536620 == TX Byte 0 ==
6990 12:18:35.539854 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6991 12:18:35.543024 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6992 12:18:35.543580 == TX Byte 1 ==
6993 12:18:35.550030 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6994 12:18:35.552696 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6995 12:18:35.553154
6996 12:18:35.553510 [DATLAT]
6997 12:18:35.556667 Freq=400, CH1 RK1
6998 12:18:35.557222
6999 12:18:35.557585 DATLAT Default: 0xe
7000 12:18:35.559564 0, 0xFFFF, sum = 0
7001 12:18:35.560079 1, 0xFFFF, sum = 0
7002 12:18:35.562975 2, 0xFFFF, sum = 0
7003 12:18:35.563434 3, 0xFFFF, sum = 0
7004 12:18:35.566617 4, 0xFFFF, sum = 0
7005 12:18:35.569015 5, 0xFFFF, sum = 0
7006 12:18:35.569569 6, 0xFFFF, sum = 0
7007 12:18:35.572863 7, 0xFFFF, sum = 0
7008 12:18:35.573325 8, 0xFFFF, sum = 0
7009 12:18:35.576682 9, 0xFFFF, sum = 0
7010 12:18:35.577143 10, 0xFFFF, sum = 0
7011 12:18:35.579280 11, 0xFFFF, sum = 0
7012 12:18:35.579775 12, 0xFFFF, sum = 0
7013 12:18:35.582660 13, 0x0, sum = 1
7014 12:18:35.583121 14, 0x0, sum = 2
7015 12:18:35.585978 15, 0x0, sum = 3
7016 12:18:35.586629 16, 0x0, sum = 4
7017 12:18:35.589282 best_step = 14
7018 12:18:35.589837
7019 12:18:35.590202 ==
7020 12:18:35.592480 Dram Type= 6, Freq= 0, CH_1, rank 1
7021 12:18:35.595949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7022 12:18:35.596519 ==
7023 12:18:35.596889 RX Vref Scan: 0
7024 12:18:35.598695
7025 12:18:35.599147 RX Vref 0 -> 0, step: 1
7026 12:18:35.599509
7027 12:18:35.602346 RX Delay -343 -> 252, step: 8
7028 12:18:35.609477 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7029 12:18:35.612820 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7030 12:18:35.616608 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7031 12:18:35.619737 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
7032 12:18:35.626703 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7033 12:18:35.629592 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7034 12:18:35.633770 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7035 12:18:35.639214 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7036 12:18:35.642726 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7037 12:18:35.645905 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7038 12:18:35.649389 iDelay=225, Bit 10, Center -44 (-287 ~ 200) 488
7039 12:18:35.656126 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7040 12:18:35.658962 iDelay=225, Bit 12, Center -32 (-279 ~ 216) 496
7041 12:18:35.662752 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7042 12:18:35.665895 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7043 12:18:35.672955 iDelay=225, Bit 15, Center -36 (-279 ~ 208) 488
7044 12:18:35.673514 ==
7045 12:18:35.675634 Dram Type= 6, Freq= 0, CH_1, rank 1
7046 12:18:35.678892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7047 12:18:35.679466 ==
7048 12:18:35.679913 DQS Delay:
7049 12:18:35.682648 DQS0 = 48, DQS1 = 56
7050 12:18:35.683210 DQM Delay:
7051 12:18:35.685603 DQM0 = 13, DQM1 = 11
7052 12:18:35.686167 DQ Delay:
7053 12:18:35.689059 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7054 12:18:35.691989 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7055 12:18:35.695599 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7056 12:18:35.698667 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =20
7057 12:18:35.699288
7058 12:18:35.699662
7059 12:18:35.708481 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b58, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7060 12:18:35.709035 CH1 RK1: MR19=C0C, MR18=6B58
7061 12:18:35.715535 CH1_RK1: MR19=0xC0C, MR18=0x6B58, DQSOSC=396, MR23=63, INC=376, DEC=251
7062 12:18:35.718494 [RxdqsGatingPostProcess] freq 400
7063 12:18:35.725131 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7064 12:18:35.728522 best DQS0 dly(2T, 0.5T) = (0, 10)
7065 12:18:35.731882 best DQS1 dly(2T, 0.5T) = (0, 10)
7066 12:18:35.735277 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7067 12:18:35.738370 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7068 12:18:35.741519 best DQS0 dly(2T, 0.5T) = (0, 10)
7069 12:18:35.744810 best DQS1 dly(2T, 0.5T) = (0, 10)
7070 12:18:35.745268 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7071 12:18:35.748844 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7072 12:18:35.751485 Pre-setting of DQS Precalculation
7073 12:18:35.757977 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7074 12:18:35.764669 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7075 12:18:35.771704 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7076 12:18:35.772285
7077 12:18:35.772650
7078 12:18:35.775155 [Calibration Summary] 800 Mbps
7079 12:18:35.778398 CH 0, Rank 0
7080 12:18:35.778854 SW Impedance : PASS
7081 12:18:35.781554 DUTY Scan : NO K
7082 12:18:35.784204 ZQ Calibration : PASS
7083 12:18:35.784664 Jitter Meter : NO K
7084 12:18:35.787529 CBT Training : PASS
7085 12:18:35.791307 Write leveling : PASS
7086 12:18:35.791805 RX DQS gating : PASS
7087 12:18:35.794287 RX DQ/DQS(RDDQC) : PASS
7088 12:18:35.794838 TX DQ/DQS : PASS
7089 12:18:35.797477 RX DATLAT : PASS
7090 12:18:35.800636 RX DQ/DQS(Engine): PASS
7091 12:18:35.801092 TX OE : NO K
7092 12:18:35.803967 All Pass.
7093 12:18:35.804417
7094 12:18:35.804772 CH 0, Rank 1
7095 12:18:35.807551 SW Impedance : PASS
7096 12:18:35.808043 DUTY Scan : NO K
7097 12:18:35.811476 ZQ Calibration : PASS
7098 12:18:35.814985 Jitter Meter : NO K
7099 12:18:35.815574 CBT Training : PASS
7100 12:18:35.817711 Write leveling : NO K
7101 12:18:35.821083 RX DQS gating : PASS
7102 12:18:35.821632 RX DQ/DQS(RDDQC) : PASS
7103 12:18:35.823946 TX DQ/DQS : PASS
7104 12:18:35.827051 RX DATLAT : PASS
7105 12:18:35.827504 RX DQ/DQS(Engine): PASS
7106 12:18:35.830709 TX OE : NO K
7107 12:18:35.831249 All Pass.
7108 12:18:35.831613
7109 12:18:35.834343 CH 1, Rank 0
7110 12:18:35.834794 SW Impedance : PASS
7111 12:18:35.837261 DUTY Scan : NO K
7112 12:18:35.840396 ZQ Calibration : PASS
7113 12:18:35.840951 Jitter Meter : NO K
7114 12:18:35.843754 CBT Training : PASS
7115 12:18:35.846864 Write leveling : PASS
7116 12:18:35.847318 RX DQS gating : PASS
7117 12:18:35.850353 RX DQ/DQS(RDDQC) : PASS
7118 12:18:35.853526 TX DQ/DQS : PASS
7119 12:18:35.854100 RX DATLAT : PASS
7120 12:18:35.856452 RX DQ/DQS(Engine): PASS
7121 12:18:35.860004 TX OE : NO K
7122 12:18:35.860557 All Pass.
7123 12:18:35.860918
7124 12:18:35.861250 CH 1, Rank 1
7125 12:18:35.863768 SW Impedance : PASS
7126 12:18:35.867030 DUTY Scan : NO K
7127 12:18:35.867481 ZQ Calibration : PASS
7128 12:18:35.869771 Jitter Meter : NO K
7129 12:18:35.873068 CBT Training : PASS
7130 12:18:35.873524 Write leveling : NO K
7131 12:18:35.876703 RX DQS gating : PASS
7132 12:18:35.879795 RX DQ/DQS(RDDQC) : PASS
7133 12:18:35.880352 TX DQ/DQS : PASS
7134 12:18:35.883011 RX DATLAT : PASS
7135 12:18:35.887286 RX DQ/DQS(Engine): PASS
7136 12:18:35.887898 TX OE : NO K
7137 12:18:35.888280 All Pass.
7138 12:18:35.889838
7139 12:18:35.890373 DramC Write-DBI off
7140 12:18:35.892994 PER_BANK_REFRESH: Hybrid Mode
7141 12:18:35.893544 TX_TRACKING: ON
7142 12:18:35.902645 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7143 12:18:35.906744 [FAST_K] Save calibration result to emmc
7144 12:18:35.909116 dramc_set_vcore_voltage set vcore to 725000
7145 12:18:35.912933 Read voltage for 1600, 0
7146 12:18:35.913390 Vio18 = 0
7147 12:18:35.916422 Vcore = 725000
7148 12:18:35.916874 Vdram = 0
7149 12:18:35.917235 Vddq = 0
7150 12:18:35.917569 Vmddr = 0
7151 12:18:35.922666 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7152 12:18:35.929586 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7153 12:18:35.930138 MEM_TYPE=3, freq_sel=13
7154 12:18:35.932262 sv_algorithm_assistance_LP4_3733
7155 12:18:35.939167 ============ PULL DRAM RESETB DOWN ============
7156 12:18:35.942709 ========== PULL DRAM RESETB DOWN end =========
7157 12:18:35.945408 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7158 12:18:35.949132 ===================================
7159 12:18:35.952400 LPDDR4 DRAM CONFIGURATION
7160 12:18:35.955574 ===================================
7161 12:18:35.958643 EX_ROW_EN[0] = 0x0
7162 12:18:35.959127 EX_ROW_EN[1] = 0x0
7163 12:18:35.962442 LP4Y_EN = 0x0
7164 12:18:35.963219 WORK_FSP = 0x1
7165 12:18:35.965359 WL = 0x5
7166 12:18:35.965815 RL = 0x5
7167 12:18:35.968605 BL = 0x2
7168 12:18:35.969059 RPST = 0x0
7169 12:18:35.971863 RD_PRE = 0x0
7170 12:18:35.972415 WR_PRE = 0x1
7171 12:18:35.975416 WR_PST = 0x1
7172 12:18:35.975909 DBI_WR = 0x0
7173 12:18:35.979151 DBI_RD = 0x0
7174 12:18:35.979603 OTF = 0x1
7175 12:18:35.981690 ===================================
7176 12:18:35.986112 ===================================
7177 12:18:35.989006 ANA top config
7178 12:18:35.992094 ===================================
7179 12:18:35.995791 DLL_ASYNC_EN = 0
7180 12:18:35.996251 ALL_SLAVE_EN = 0
7181 12:18:35.998260 NEW_RANK_MODE = 1
7182 12:18:36.001400 DLL_IDLE_MODE = 1
7183 12:18:36.004742 LP45_APHY_COMB_EN = 1
7184 12:18:36.005293 TX_ODT_DIS = 0
7185 12:18:36.008595 NEW_8X_MODE = 1
7186 12:18:36.011845 ===================================
7187 12:18:36.015103 ===================================
7188 12:18:36.017904 data_rate = 3200
7189 12:18:36.021357 CKR = 1
7190 12:18:36.024557 DQ_P2S_RATIO = 8
7191 12:18:36.028551 ===================================
7192 12:18:36.031492 CA_P2S_RATIO = 8
7193 12:18:36.032099 DQ_CA_OPEN = 0
7194 12:18:36.035026 DQ_SEMI_OPEN = 0
7195 12:18:36.037905 CA_SEMI_OPEN = 0
7196 12:18:36.041279 CA_FULL_RATE = 0
7197 12:18:36.044794 DQ_CKDIV4_EN = 0
7198 12:18:36.047791 CA_CKDIV4_EN = 0
7199 12:18:36.048250 CA_PREDIV_EN = 0
7200 12:18:36.050974 PH8_DLY = 12
7201 12:18:36.055191 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7202 12:18:36.057480 DQ_AAMCK_DIV = 4
7203 12:18:36.062218 CA_AAMCK_DIV = 4
7204 12:18:36.064423 CA_ADMCK_DIV = 4
7205 12:18:36.067912 DQ_TRACK_CA_EN = 0
7206 12:18:36.068461 CA_PICK = 1600
7207 12:18:36.070901 CA_MCKIO = 1600
7208 12:18:36.074255 MCKIO_SEMI = 0
7209 12:18:36.078035 PLL_FREQ = 3068
7210 12:18:36.080803 DQ_UI_PI_RATIO = 32
7211 12:18:36.083830 CA_UI_PI_RATIO = 0
7212 12:18:36.087991 ===================================
7213 12:18:36.091643 ===================================
7214 12:18:36.094184 memory_type:LPDDR4
7215 12:18:36.094736 GP_NUM : 10
7216 12:18:36.097304 SRAM_EN : 1
7217 12:18:36.097856 MD32_EN : 0
7218 12:18:36.101645 ===================================
7219 12:18:36.105120 [ANA_INIT] >>>>>>>>>>>>>>
7220 12:18:36.108223 <<<<<< [CONFIGURE PHASE]: ANA_TX
7221 12:18:36.111275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7222 12:18:36.113938 ===================================
7223 12:18:36.116925 data_rate = 3200,PCW = 0X7600
7224 12:18:36.120784 ===================================
7225 12:18:36.123463 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7226 12:18:36.130298 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7227 12:18:36.134694 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7228 12:18:36.140543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7229 12:18:36.143554 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7230 12:18:36.146956 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7231 12:18:36.147529 [ANA_INIT] flow start
7232 12:18:36.150593 [ANA_INIT] PLL >>>>>>>>
7233 12:18:36.153482 [ANA_INIT] PLL <<<<<<<<
7234 12:18:36.153908 [ANA_INIT] MIDPI >>>>>>>>
7235 12:18:36.156916 [ANA_INIT] MIDPI <<<<<<<<
7236 12:18:36.160444 [ANA_INIT] DLL >>>>>>>>
7237 12:18:36.161006 [ANA_INIT] DLL <<<<<<<<
7238 12:18:36.163701 [ANA_INIT] flow end
7239 12:18:36.166995 ============ LP4 DIFF to SE enter ============
7240 12:18:36.173609 ============ LP4 DIFF to SE exit ============
7241 12:18:36.174077 [ANA_INIT] <<<<<<<<<<<<<
7242 12:18:36.177618 [Flow] Enable top DCM control >>>>>
7243 12:18:36.179972 [Flow] Enable top DCM control <<<<<
7244 12:18:36.183442 Enable DLL master slave shuffle
7245 12:18:36.189717 ==============================================================
7246 12:18:36.190190 Gating Mode config
7247 12:18:36.196220 ==============================================================
7248 12:18:36.199520 Config description:
7249 12:18:36.209587 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7250 12:18:36.216377 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7251 12:18:36.219328 SELPH_MODE 0: By rank 1: By Phase
7252 12:18:36.226393 ==============================================================
7253 12:18:36.229200 GAT_TRACK_EN = 1
7254 12:18:36.233213 RX_GATING_MODE = 2
7255 12:18:36.233769 RX_GATING_TRACK_MODE = 2
7256 12:18:36.239425 SELPH_MODE = 1
7257 12:18:36.240394 PICG_EARLY_EN = 1
7258 12:18:36.242265 VALID_LAT_VALUE = 1
7259 12:18:36.248977 ==============================================================
7260 12:18:36.252248 Enter into Gating configuration >>>>
7261 12:18:36.255845 Exit from Gating configuration <<<<
7262 12:18:36.258929 Enter into DVFS_PRE_config >>>>>
7263 12:18:36.268991 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7264 12:18:36.271728 Exit from DVFS_PRE_config <<<<<
7265 12:18:36.275716 Enter into PICG configuration >>>>
7266 12:18:36.278924 Exit from PICG configuration <<<<
7267 12:18:36.282347 [RX_INPUT] configuration >>>>>
7268 12:18:36.285472 [RX_INPUT] configuration <<<<<
7269 12:18:36.288514 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7270 12:18:36.295647 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7271 12:18:36.301514 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7272 12:18:36.308301 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7273 12:18:36.315073 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7274 12:18:36.318443 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7275 12:18:36.324702 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7276 12:18:36.328291 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7277 12:18:36.331271 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7278 12:18:36.335554 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7279 12:18:36.340937 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7280 12:18:36.344466 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7281 12:18:36.348123 ===================================
7282 12:18:36.351640 LPDDR4 DRAM CONFIGURATION
7283 12:18:36.354898 ===================================
7284 12:18:36.355359 EX_ROW_EN[0] = 0x0
7285 12:18:36.359760 EX_ROW_EN[1] = 0x0
7286 12:18:36.360324 LP4Y_EN = 0x0
7287 12:18:36.361820 WORK_FSP = 0x1
7288 12:18:36.362280 WL = 0x5
7289 12:18:36.365250 RL = 0x5
7290 12:18:36.367789 BL = 0x2
7291 12:18:36.368255 RPST = 0x0
7292 12:18:36.371906 RD_PRE = 0x0
7293 12:18:36.372367 WR_PRE = 0x1
7294 12:18:36.374343 WR_PST = 0x1
7295 12:18:36.374803 DBI_WR = 0x0
7296 12:18:36.377746 DBI_RD = 0x0
7297 12:18:36.378369 OTF = 0x1
7298 12:18:36.380898 ===================================
7299 12:18:36.384956 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7300 12:18:36.390765 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7301 12:18:36.394008 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7302 12:18:36.397430 ===================================
7303 12:18:36.400277 LPDDR4 DRAM CONFIGURATION
7304 12:18:36.403974 ===================================
7305 12:18:36.404438 EX_ROW_EN[0] = 0x10
7306 12:18:36.406788 EX_ROW_EN[1] = 0x0
7307 12:18:36.411150 LP4Y_EN = 0x0
7308 12:18:36.411782 WORK_FSP = 0x1
7309 12:18:36.413347 WL = 0x5
7310 12:18:36.413816 RL = 0x5
7311 12:18:36.416900 BL = 0x2
7312 12:18:36.417420 RPST = 0x0
7313 12:18:36.421007 RD_PRE = 0x0
7314 12:18:36.421460 WR_PRE = 0x1
7315 12:18:36.423440 WR_PST = 0x1
7316 12:18:36.423950 DBI_WR = 0x0
7317 12:18:36.426982 DBI_RD = 0x0
7318 12:18:36.427547 OTF = 0x1
7319 12:18:36.430263 ===================================
7320 12:18:36.436441 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7321 12:18:36.436991 ==
7322 12:18:36.439796 Dram Type= 6, Freq= 0, CH_0, rank 0
7323 12:18:36.443141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7324 12:18:36.446320 ==
7325 12:18:36.446785 [Duty_Offset_Calibration]
7326 12:18:36.450457 B0:1 B1:-1 CA:0
7327 12:18:36.450922
7328 12:18:36.452985 [DutyScan_Calibration_Flow] k_type=0
7329 12:18:36.462160
7330 12:18:36.462577 ==CLK 0==
7331 12:18:36.465545 Final CLK duty delay cell = 0
7332 12:18:36.469638 [0] MAX Duty = 5125%(X100), DQS PI = 20
7333 12:18:36.472217 [0] MIN Duty = 4907%(X100), DQS PI = 6
7334 12:18:36.472634 [0] AVG Duty = 5016%(X100)
7335 12:18:36.475405
7336 12:18:36.479080 CH0 CLK Duty spec in!! Max-Min= 218%
7337 12:18:36.482038 [DutyScan_Calibration_Flow] ====Done====
7338 12:18:36.482461
7339 12:18:36.485264 [DutyScan_Calibration_Flow] k_type=1
7340 12:18:36.501479
7341 12:18:36.501897 ==DQS 0 ==
7342 12:18:36.504502 Final DQS duty delay cell = -4
7343 12:18:36.507464 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7344 12:18:36.511340 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7345 12:18:36.514220 [-4] AVG Duty = 4922%(X100)
7346 12:18:36.514638
7347 12:18:36.514969 ==DQS 1 ==
7348 12:18:36.517803 Final DQS duty delay cell = 0
7349 12:18:36.522082 [0] MAX Duty = 5156%(X100), DQS PI = 2
7350 12:18:36.524588 [0] MIN Duty = 5031%(X100), DQS PI = 16
7351 12:18:36.527495 [0] AVG Duty = 5093%(X100)
7352 12:18:36.527968
7353 12:18:36.532055 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7354 12:18:36.532578
7355 12:18:36.535365 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7356 12:18:36.537642 [DutyScan_Calibration_Flow] ====Done====
7357 12:18:36.538161
7358 12:18:36.540916 [DutyScan_Calibration_Flow] k_type=3
7359 12:18:36.558356
7360 12:18:36.558781 ==DQM 0 ==
7361 12:18:36.562214 Final DQM duty delay cell = 0
7362 12:18:36.566087 [0] MAX Duty = 5124%(X100), DQS PI = 22
7363 12:18:36.568810 [0] MIN Duty = 4907%(X100), DQS PI = 10
7364 12:18:36.571828 [0] AVG Duty = 5015%(X100)
7365 12:18:36.572246
7366 12:18:36.572572 ==DQM 1 ==
7367 12:18:36.575792 Final DQM duty delay cell = 0
7368 12:18:36.578697 [0] MAX Duty = 5000%(X100), DQS PI = 4
7369 12:18:36.582004 [0] MIN Duty = 4813%(X100), DQS PI = 20
7370 12:18:36.585283 [0] AVG Duty = 4906%(X100)
7371 12:18:36.585698
7372 12:18:36.588324 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7373 12:18:36.588741
7374 12:18:36.591921 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7375 12:18:36.595514 [DutyScan_Calibration_Flow] ====Done====
7376 12:18:36.596100
7377 12:18:36.598131 [DutyScan_Calibration_Flow] k_type=2
7378 12:18:36.615306
7379 12:18:36.615958 ==DQ 0 ==
7380 12:18:36.618403 Final DQ duty delay cell = -4
7381 12:18:36.621372 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7382 12:18:36.625167 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7383 12:18:36.628371 [-4] AVG Duty = 4953%(X100)
7384 12:18:36.628929
7385 12:18:36.629294 ==DQ 1 ==
7386 12:18:36.631750 Final DQ duty delay cell = 0
7387 12:18:36.635208 [0] MAX Duty = 5125%(X100), DQS PI = 2
7388 12:18:36.638846 [0] MIN Duty = 5000%(X100), DQS PI = 36
7389 12:18:36.641225 [0] AVG Duty = 5062%(X100)
7390 12:18:36.641685
7391 12:18:36.644941 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7392 12:18:36.645504
7393 12:18:36.648022 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7394 12:18:36.651318 [DutyScan_Calibration_Flow] ====Done====
7395 12:18:36.651932 ==
7396 12:18:36.654718 Dram Type= 6, Freq= 0, CH_1, rank 0
7397 12:18:36.658321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7398 12:18:36.658880 ==
7399 12:18:36.660864 [Duty_Offset_Calibration]
7400 12:18:36.661321 B0:-1 B1:1 CA:2
7401 12:18:36.664352
7402 12:18:36.667490 [DutyScan_Calibration_Flow] k_type=0
7403 12:18:36.675455
7404 12:18:36.675971 ==CLK 0==
7405 12:18:36.678831 Final CLK duty delay cell = 0
7406 12:18:36.681926 [0] MAX Duty = 5187%(X100), DQS PI = 22
7407 12:18:36.685838 [0] MIN Duty = 5031%(X100), DQS PI = 12
7408 12:18:36.688522 [0] AVG Duty = 5109%(X100)
7409 12:18:36.688981
7410 12:18:36.692633 CH1 CLK Duty spec in!! Max-Min= 156%
7411 12:18:36.695463 [DutyScan_Calibration_Flow] ====Done====
7412 12:18:36.696056
7413 12:18:36.698872 [DutyScan_Calibration_Flow] k_type=1
7414 12:18:36.715588
7415 12:18:36.716189 ==DQS 0 ==
7416 12:18:36.719185 Final DQS duty delay cell = 0
7417 12:18:36.721803 [0] MAX Duty = 5156%(X100), DQS PI = 22
7418 12:18:36.725250 [0] MIN Duty = 4907%(X100), DQS PI = 40
7419 12:18:36.728804 [0] AVG Duty = 5031%(X100)
7420 12:18:36.729352
7421 12:18:36.729710 ==DQS 1 ==
7422 12:18:36.731922 Final DQS duty delay cell = 0
7423 12:18:36.736056 [0] MAX Duty = 5093%(X100), DQS PI = 6
7424 12:18:36.738739 [0] MIN Duty = 4969%(X100), DQS PI = 26
7425 12:18:36.742370 [0] AVG Duty = 5031%(X100)
7426 12:18:36.742933
7427 12:18:36.745071 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7428 12:18:36.745633
7429 12:18:36.748652 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7430 12:18:36.752042 [DutyScan_Calibration_Flow] ====Done====
7431 12:18:36.752604
7432 12:18:36.755995 [DutyScan_Calibration_Flow] k_type=3
7433 12:18:36.772634
7434 12:18:36.773185 ==DQM 0 ==
7435 12:18:36.775506 Final DQM duty delay cell = 0
7436 12:18:36.778746 [0] MAX Duty = 5187%(X100), DQS PI = 4
7437 12:18:36.782488 [0] MIN Duty = 5031%(X100), DQS PI = 40
7438 12:18:36.785676 [0] AVG Duty = 5109%(X100)
7439 12:18:36.786139
7440 12:18:36.786499 ==DQM 1 ==
7441 12:18:36.789440 Final DQM duty delay cell = 0
7442 12:18:36.792224 [0] MAX Duty = 5187%(X100), DQS PI = 34
7443 12:18:36.795385 [0] MIN Duty = 5000%(X100), DQS PI = 0
7444 12:18:36.798536 [0] AVG Duty = 5093%(X100)
7445 12:18:36.799100
7446 12:18:36.801812 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7447 12:18:36.802270
7448 12:18:36.805337 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7449 12:18:36.809091 [DutyScan_Calibration_Flow] ====Done====
7450 12:18:36.809550
7451 12:18:36.811859 [DutyScan_Calibration_Flow] k_type=2
7452 12:18:36.829295
7453 12:18:36.829837 ==DQ 0 ==
7454 12:18:36.832512 Final DQ duty delay cell = 0
7455 12:18:36.836274 [0] MAX Duty = 5156%(X100), DQS PI = 0
7456 12:18:36.839261 [0] MIN Duty = 4906%(X100), DQS PI = 40
7457 12:18:36.839839 [0] AVG Duty = 5031%(X100)
7458 12:18:36.842598
7459 12:18:36.843301 ==DQ 1 ==
7460 12:18:36.845334 Final DQ duty delay cell = 0
7461 12:18:36.848686 [0] MAX Duty = 5156%(X100), DQS PI = 42
7462 12:18:36.852500 [0] MIN Duty = 4969%(X100), DQS PI = 26
7463 12:18:36.853047 [0] AVG Duty = 5062%(X100)
7464 12:18:36.853408
7465 12:18:36.859050 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7466 12:18:36.859649
7467 12:18:36.862307 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7468 12:18:36.866355 [DutyScan_Calibration_Flow] ====Done====
7469 12:18:36.869021 nWR fixed to 30
7470 12:18:36.869569 [ModeRegInit_LP4] CH0 RK0
7471 12:18:36.871730 [ModeRegInit_LP4] CH0 RK1
7472 12:18:36.875826 [ModeRegInit_LP4] CH1 RK0
7473 12:18:36.878745 [ModeRegInit_LP4] CH1 RK1
7474 12:18:36.879274 match AC timing 5
7475 12:18:36.885177 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7476 12:18:36.888295 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7477 12:18:36.891704 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7478 12:18:36.898957 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7479 12:18:36.901835 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7480 12:18:36.902413 [MiockJmeterHQA]
7481 12:18:36.902772
7482 12:18:36.904731 [DramcMiockJmeter] u1RxGatingPI = 0
7483 12:18:36.908442 0 : 4363, 4138
7484 12:18:36.908922 4 : 4252, 4027
7485 12:18:36.911389 8 : 4363, 4138
7486 12:18:36.911887 12 : 4366, 4139
7487 12:18:36.914852 16 : 4363, 4137
7488 12:18:36.915404 20 : 4363, 4138
7489 12:18:36.915818 24 : 4253, 4027
7490 12:18:36.918460 28 : 4252, 4027
7491 12:18:36.918978 32 : 4252, 4027
7492 12:18:36.921527 36 : 4255, 4029
7493 12:18:36.922082 40 : 4361, 4137
7494 12:18:36.924940 44 : 4255, 4029
7495 12:18:36.925491 48 : 4250, 4026
7496 12:18:36.925855 52 : 4250, 4027
7497 12:18:36.928460 56 : 4253, 4029
7498 12:18:36.929031 60 : 4250, 4026
7499 12:18:36.931299 64 : 4360, 4138
7500 12:18:36.931792 68 : 4361, 4137
7501 12:18:36.934734 72 : 4250, 4027
7502 12:18:36.935289 76 : 4250, 4027
7503 12:18:36.937863 80 : 4250, 4026
7504 12:18:36.938419 84 : 4252, 4027
7505 12:18:36.938787 88 : 4252, 4029
7506 12:18:36.940874 92 : 4361, 461
7507 12:18:36.941330 96 : 4250, 0
7508 12:18:36.946264 100 : 4360, 0
7509 12:18:36.946823 104 : 4363, 0
7510 12:18:36.947189 108 : 4362, 0
7511 12:18:36.947897 112 : 4250, 0
7512 12:18:36.948261 116 : 4250, 0
7513 12:18:36.951833 120 : 4250, 0
7514 12:18:36.952292 124 : 4250, 0
7515 12:18:36.952654 128 : 4250, 0
7516 12:18:36.954324 132 : 4250, 0
7517 12:18:36.954784 136 : 4252, 0
7518 12:18:36.957871 140 : 4250, 0
7519 12:18:36.958333 144 : 4250, 0
7520 12:18:36.958697 148 : 4363, 0
7521 12:18:36.961416 152 : 4361, 0
7522 12:18:36.961831 156 : 4360, 0
7523 12:18:36.964478 160 : 4363, 0
7524 12:18:36.964895 164 : 4250, 0
7525 12:18:36.965226 168 : 4250, 0
7526 12:18:36.968333 172 : 4250, 0
7527 12:18:36.968750 176 : 4250, 0
7528 12:18:36.969081 180 : 4250, 0
7529 12:18:36.971301 184 : 4250, 0
7530 12:18:36.971930 188 : 4252, 0
7531 12:18:36.974450 192 : 4363, 0
7532 12:18:36.974868 196 : 4250, 0
7533 12:18:36.975199 200 : 4250, 0
7534 12:18:36.977617 204 : 4363, 0
7535 12:18:36.978032 208 : 4360, 0
7536 12:18:36.981326 212 : 4363, 0
7537 12:18:36.981846 216 : 4250, 0
7538 12:18:36.982185 220 : 4250, 0
7539 12:18:36.984005 224 : 4250, 225
7540 12:18:36.984431 228 : 4252, 3355
7541 12:18:36.986967 232 : 4250, 4027
7542 12:18:36.987392 236 : 4361, 4137
7543 12:18:36.991368 240 : 4250, 4027
7544 12:18:36.991927 244 : 4250, 4027
7545 12:18:36.994488 248 : 4250, 4027
7546 12:18:36.995007 252 : 4253, 4029
7547 12:18:36.997502 256 : 4250, 4027
7548 12:18:36.997929 260 : 4250, 4027
7549 12:18:37.000567 264 : 4360, 4137
7550 12:18:37.000994 268 : 4250, 4027
7551 12:18:37.003844 272 : 4250, 4026
7552 12:18:37.004272 276 : 4361, 4137
7553 12:18:37.004610 280 : 4250, 4027
7554 12:18:37.007451 284 : 4250, 4026
7555 12:18:37.008021 288 : 4364, 4140
7556 12:18:37.010355 292 : 4250, 4026
7557 12:18:37.010782 296 : 4250, 4027
7558 12:18:37.014120 300 : 4250, 4026
7559 12:18:37.014637 304 : 4250, 4027
7560 12:18:37.016937 308 : 4250, 4027
7561 12:18:37.017364 312 : 4250, 4027
7562 12:18:37.020361 316 : 4360, 4138
7563 12:18:37.020778 320 : 4249, 4027
7564 12:18:37.023744 324 : 4250, 4026
7565 12:18:37.024267 328 : 4361, 4137
7566 12:18:37.027026 332 : 4250, 4027
7567 12:18:37.027556 336 : 4250, 3893
7568 12:18:37.027958 340 : 4362, 2038
7569 12:18:37.029966
7570 12:18:37.030377 MIOCK jitter meter ch=0
7571 12:18:37.030708
7572 12:18:37.033803 1T = (340-92) = 248 dly cells
7573 12:18:37.040310 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7574 12:18:37.040726 ==
7575 12:18:37.043212 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 12:18:37.046974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 12:18:37.047490 ==
7578 12:18:37.053393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7579 12:18:37.056915 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7580 12:18:37.059985 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7581 12:18:37.066839 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7582 12:18:37.076347 [CA 0] Center 43 (12~74) winsize 63
7583 12:18:37.079618 [CA 1] Center 42 (12~73) winsize 62
7584 12:18:37.083367 [CA 2] Center 38 (9~68) winsize 60
7585 12:18:37.086156 [CA 3] Center 38 (8~68) winsize 61
7586 12:18:37.090105 [CA 4] Center 36 (7~66) winsize 60
7587 12:18:37.092446 [CA 5] Center 35 (6~65) winsize 60
7588 12:18:37.092905
7589 12:18:37.095610 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7590 12:18:37.096126
7591 12:18:37.099207 [CATrainingPosCal] consider 1 rank data
7592 12:18:37.102554 u2DelayCellTimex100 = 262/100 ps
7593 12:18:37.110787 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7594 12:18:37.113090 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7595 12:18:37.116739 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7596 12:18:37.119167 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7597 12:18:37.122574 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7598 12:18:37.125744 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7599 12:18:37.126309
7600 12:18:37.128801 CA PerBit enable=1, Macro0, CA PI delay=35
7601 12:18:37.129283
7602 12:18:37.132140 [CBTSetCACLKResult] CA Dly = 35
7603 12:18:37.135857 CS Dly: 11 (0~42)
7604 12:18:37.138897 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7605 12:18:37.142043 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7606 12:18:37.142601 ==
7607 12:18:37.145566 Dram Type= 6, Freq= 0, CH_0, rank 1
7608 12:18:37.152136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 12:18:37.152685 ==
7610 12:18:37.155560 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7611 12:18:37.162160 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7612 12:18:37.164882 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7613 12:18:37.171871 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7614 12:18:37.179458 [CA 0] Center 42 (12~73) winsize 62
7615 12:18:37.183015 [CA 1] Center 43 (13~73) winsize 61
7616 12:18:37.185880 [CA 2] Center 37 (8~67) winsize 60
7617 12:18:37.189001 [CA 3] Center 37 (7~67) winsize 61
7618 12:18:37.192429 [CA 4] Center 35 (6~65) winsize 60
7619 12:18:37.195565 [CA 5] Center 35 (5~65) winsize 61
7620 12:18:37.195758
7621 12:18:37.198700 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7622 12:18:37.198849
7623 12:18:37.205175 [CATrainingPosCal] consider 2 rank data
7624 12:18:37.205290 u2DelayCellTimex100 = 262/100 ps
7625 12:18:37.212112 CA0 delay=42 (12~73),Diff = 7 PI (26 cell)
7626 12:18:37.215112 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7627 12:18:37.218945 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7628 12:18:37.222036 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7629 12:18:37.224645 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7630 12:18:37.228396 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7631 12:18:37.228482
7632 12:18:37.231229 CA PerBit enable=1, Macro0, CA PI delay=35
7633 12:18:37.231313
7634 12:18:37.234950 [CBTSetCACLKResult] CA Dly = 35
7635 12:18:37.238036 CS Dly: 12 (0~44)
7636 12:18:37.241378 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7637 12:18:37.244895 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7638 12:18:37.244978
7639 12:18:37.251110 ----->DramcWriteLeveling(PI) begin...
7640 12:18:37.251197 ==
7641 12:18:37.254433 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 12:18:37.257677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 12:18:37.257760 ==
7644 12:18:37.260823 Write leveling (Byte 0): 38 => 38
7645 12:18:37.264388 Write leveling (Byte 1): 29 => 29
7646 12:18:37.267383 DramcWriteLeveling(PI) end<-----
7647 12:18:37.267509
7648 12:18:37.267610 ==
7649 12:18:37.270750 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 12:18:37.274098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 12:18:37.274183 ==
7652 12:18:37.277256 [Gating] SW mode calibration
7653 12:18:37.284465 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7654 12:18:37.291810 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7655 12:18:37.293645 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 12:18:37.297245 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 12:18:37.303943 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 12:18:37.307398 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7659 12:18:37.310690 1 4 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7660 12:18:37.317595 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7661 12:18:37.320501 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7662 12:18:37.323902 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7663 12:18:37.330596 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7664 12:18:37.333064 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7665 12:18:37.337144 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7666 12:18:37.342886 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7667 12:18:37.346532 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7668 12:18:37.349853 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7669 12:18:37.356875 1 5 24 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
7670 12:18:37.359892 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7671 12:18:37.362685 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 12:18:37.369302 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7673 12:18:37.372465 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7674 12:18:37.375917 1 6 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7675 12:18:37.383266 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7676 12:18:37.385645 1 6 20 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
7677 12:18:37.389431 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
7678 12:18:37.396211 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7679 12:18:37.399563 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7680 12:18:37.403146 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7681 12:18:37.409788 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7682 12:18:37.412545 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7683 12:18:37.415483 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7684 12:18:37.422666 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7685 12:18:37.425608 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7686 12:18:37.429356 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 12:18:37.435222 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 12:18:37.438586 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 12:18:37.442308 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 12:18:37.448625 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 12:18:37.452099 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 12:18:37.456215 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 12:18:37.461808 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 12:18:37.465443 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 12:18:37.468691 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 12:18:37.475966 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 12:18:37.478567 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 12:18:37.482694 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7699 12:18:37.487894 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7700 12:18:37.491510 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7701 12:18:37.494685 Total UI for P1: 0, mck2ui 16
7702 12:18:37.498176 best dqsien dly found for B0: ( 1, 9, 14)
7703 12:18:37.501407 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7704 12:18:37.507600 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7705 12:18:37.511549 Total UI for P1: 0, mck2ui 16
7706 12:18:37.514582 best dqsien dly found for B1: ( 1, 9, 22)
7707 12:18:37.517654 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7708 12:18:37.521047 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7709 12:18:37.521137
7710 12:18:37.524609 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7711 12:18:37.527425 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7712 12:18:37.532175 [Gating] SW calibration Done
7713 12:18:37.532265 ==
7714 12:18:37.534641 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 12:18:37.537989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 12:18:37.538096 ==
7717 12:18:37.541210 RX Vref Scan: 0
7718 12:18:37.541329
7719 12:18:37.544118 RX Vref 0 -> 0, step: 1
7720 12:18:37.544201
7721 12:18:37.544270 RX Delay 0 -> 252, step: 8
7722 12:18:37.550881 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7723 12:18:37.554009 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7724 12:18:37.557430 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7725 12:18:37.560424 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7726 12:18:37.564553 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7727 12:18:37.571444 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7728 12:18:37.574424 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7729 12:18:37.577416 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7730 12:18:37.580672 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7731 12:18:37.583618 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7732 12:18:37.590346 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7733 12:18:37.593867 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7734 12:18:37.596941 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7735 12:18:37.601152 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7736 12:18:37.607115 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7737 12:18:37.610204 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7738 12:18:37.610296 ==
7739 12:18:37.613948 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 12:18:37.616868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 12:18:37.616956 ==
7742 12:18:37.617021 DQS Delay:
7743 12:18:37.620490 DQS0 = 0, DQS1 = 0
7744 12:18:37.620582 DQM Delay:
7745 12:18:37.623415 DQM0 = 136, DQM1 = 126
7746 12:18:37.623500 DQ Delay:
7747 12:18:37.626428 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7748 12:18:37.630197 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =147
7749 12:18:37.633345 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7750 12:18:37.639536 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7751 12:18:37.639629
7752 12:18:37.639706
7753 12:18:37.639768 ==
7754 12:18:37.642756 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 12:18:37.646365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 12:18:37.646452 ==
7757 12:18:37.646518
7758 12:18:37.646579
7759 12:18:37.649840 TX Vref Scan disable
7760 12:18:37.649925 == TX Byte 0 ==
7761 12:18:37.657503 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7762 12:18:37.659946 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7763 12:18:37.660037 == TX Byte 1 ==
7764 12:18:37.665911 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7765 12:18:37.669527 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7766 12:18:37.669615 ==
7767 12:18:37.672986 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 12:18:37.676032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 12:18:37.676120 ==
7770 12:18:37.690849
7771 12:18:37.694559 TX Vref early break, caculate TX vref
7772 12:18:37.697597 TX Vref=16, minBit 0, minWin=23, winSum=375
7773 12:18:37.700492 TX Vref=18, minBit 0, minWin=23, winSum=384
7774 12:18:37.703853 TX Vref=20, minBit 1, minWin=24, winSum=396
7775 12:18:37.707413 TX Vref=22, minBit 1, minWin=24, winSum=406
7776 12:18:37.711116 TX Vref=24, minBit 0, minWin=25, winSum=415
7777 12:18:37.717199 TX Vref=26, minBit 4, minWin=24, winSum=425
7778 12:18:37.720901 TX Vref=28, minBit 0, minWin=25, winSum=418
7779 12:18:37.723666 TX Vref=30, minBit 4, minWin=24, winSum=413
7780 12:18:37.727360 TX Vref=32, minBit 0, minWin=24, winSum=406
7781 12:18:37.730622 TX Vref=34, minBit 4, minWin=23, winSum=393
7782 12:18:37.737057 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
7783 12:18:37.737143
7784 12:18:37.740268 Final TX Range 0 Vref 28
7785 12:18:37.740344
7786 12:18:37.740405 ==
7787 12:18:37.743338 Dram Type= 6, Freq= 0, CH_0, rank 0
7788 12:18:37.747009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7789 12:18:37.747094 ==
7790 12:18:37.747158
7791 12:18:37.747217
7792 12:18:37.750213 TX Vref Scan disable
7793 12:18:37.757372 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7794 12:18:37.757459 == TX Byte 0 ==
7795 12:18:37.760332 u2DelayCellOfst[0]=14 cells (4 PI)
7796 12:18:37.763086 u2DelayCellOfst[1]=14 cells (4 PI)
7797 12:18:37.766252 u2DelayCellOfst[2]=11 cells (3 PI)
7798 12:18:37.770008 u2DelayCellOfst[3]=11 cells (3 PI)
7799 12:18:37.772970 u2DelayCellOfst[4]=11 cells (3 PI)
7800 12:18:37.776966 u2DelayCellOfst[5]=0 cells (0 PI)
7801 12:18:37.779481 u2DelayCellOfst[6]=18 cells (5 PI)
7802 12:18:37.782790 u2DelayCellOfst[7]=18 cells (5 PI)
7803 12:18:37.786227 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7804 12:18:37.789887 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7805 12:18:37.793142 == TX Byte 1 ==
7806 12:18:37.795990 u2DelayCellOfst[8]=0 cells (0 PI)
7807 12:18:37.799429 u2DelayCellOfst[9]=0 cells (0 PI)
7808 12:18:37.802954 u2DelayCellOfst[10]=7 cells (2 PI)
7809 12:18:37.806301 u2DelayCellOfst[11]=0 cells (0 PI)
7810 12:18:37.809542 u2DelayCellOfst[12]=11 cells (3 PI)
7811 12:18:37.809626 u2DelayCellOfst[13]=11 cells (3 PI)
7812 12:18:37.812598 u2DelayCellOfst[14]=14 cells (4 PI)
7813 12:18:37.816045 u2DelayCellOfst[15]=11 cells (3 PI)
7814 12:18:37.822850 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7815 12:18:37.825902 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7816 12:18:37.829242 DramC Write-DBI on
7817 12:18:37.829334 ==
7818 12:18:37.832213 Dram Type= 6, Freq= 0, CH_0, rank 0
7819 12:18:37.835447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7820 12:18:37.835532 ==
7821 12:18:37.835597
7822 12:18:37.835657
7823 12:18:37.838890 TX Vref Scan disable
7824 12:18:37.838973 == TX Byte 0 ==
7825 12:18:37.845631 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7826 12:18:37.845718 == TX Byte 1 ==
7827 12:18:37.848803 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7828 12:18:37.852192 DramC Write-DBI off
7829 12:18:37.852274
7830 12:18:37.852355 [DATLAT]
7831 12:18:37.855178 Freq=1600, CH0 RK0
7832 12:18:37.855260
7833 12:18:37.855363 DATLAT Default: 0xf
7834 12:18:37.858666 0, 0xFFFF, sum = 0
7835 12:18:37.861795 1, 0xFFFF, sum = 0
7836 12:18:37.861895 2, 0xFFFF, sum = 0
7837 12:18:37.865158 3, 0xFFFF, sum = 0
7838 12:18:37.865243 4, 0xFFFF, sum = 0
7839 12:18:37.868348 5, 0xFFFF, sum = 0
7840 12:18:37.868432 6, 0xFFFF, sum = 0
7841 12:18:37.871996 7, 0xFFFF, sum = 0
7842 12:18:37.872079 8, 0xFFFF, sum = 0
7843 12:18:37.875612 9, 0xFFFF, sum = 0
7844 12:18:37.875762 10, 0xFFFF, sum = 0
7845 12:18:37.878078 11, 0xFFFF, sum = 0
7846 12:18:37.878163 12, 0xFFFF, sum = 0
7847 12:18:37.881859 13, 0xFFFF, sum = 0
7848 12:18:37.881943 14, 0x0, sum = 1
7849 12:18:37.885469 15, 0x0, sum = 2
7850 12:18:37.885553 16, 0x0, sum = 3
7851 12:18:37.888192 17, 0x0, sum = 4
7852 12:18:37.888275 best_step = 15
7853 12:18:37.888338
7854 12:18:37.888414 ==
7855 12:18:37.891263 Dram Type= 6, Freq= 0, CH_0, rank 0
7856 12:18:37.897801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7857 12:18:37.897889 ==
7858 12:18:37.897955 RX Vref Scan: 1
7859 12:18:37.898015
7860 12:18:37.900853 Set Vref Range= 24 -> 127
7861 12:18:37.900935
7862 12:18:37.904729 RX Vref 24 -> 127, step: 1
7863 12:18:37.904840
7864 12:18:37.907956 RX Delay 11 -> 252, step: 4
7865 12:18:37.908038
7866 12:18:37.911131 Set Vref, RX VrefLevel [Byte0]: 24
7867 12:18:37.915221 [Byte1]: 24
7868 12:18:37.915304
7869 12:18:37.917503 Set Vref, RX VrefLevel [Byte0]: 25
7870 12:18:37.920571 [Byte1]: 25
7871 12:18:37.920654
7872 12:18:37.924017 Set Vref, RX VrefLevel [Byte0]: 26
7873 12:18:37.927564 [Byte1]: 26
7874 12:18:37.931069
7875 12:18:37.931154 Set Vref, RX VrefLevel [Byte0]: 27
7876 12:18:37.937346 [Byte1]: 27
7877 12:18:37.937435
7878 12:18:37.940790 Set Vref, RX VrefLevel [Byte0]: 28
7879 12:18:37.944180 [Byte1]: 28
7880 12:18:37.944270
7881 12:18:37.947549 Set Vref, RX VrefLevel [Byte0]: 29
7882 12:18:37.951006 [Byte1]: 29
7883 12:18:37.953781
7884 12:18:37.953866 Set Vref, RX VrefLevel [Byte0]: 30
7885 12:18:37.956927 [Byte1]: 30
7886 12:18:37.961435
7887 12:18:37.961528 Set Vref, RX VrefLevel [Byte0]: 31
7888 12:18:37.965313 [Byte1]: 31
7889 12:18:37.969338
7890 12:18:37.969447 Set Vref, RX VrefLevel [Byte0]: 32
7891 12:18:37.972029 [Byte1]: 32
7892 12:18:37.976633
7893 12:18:37.976736 Set Vref, RX VrefLevel [Byte0]: 33
7894 12:18:37.979634 [Byte1]: 33
7895 12:18:37.984710
7896 12:18:37.984830 Set Vref, RX VrefLevel [Byte0]: 34
7897 12:18:37.987678 [Byte1]: 34
7898 12:18:37.991659
7899 12:18:37.991792 Set Vref, RX VrefLevel [Byte0]: 35
7900 12:18:37.995361 [Byte1]: 35
7901 12:18:37.999564
7902 12:18:37.999713 Set Vref, RX VrefLevel [Byte0]: 36
7903 12:18:38.003012 [Byte1]: 36
7904 12:18:38.006920
7905 12:18:38.007042 Set Vref, RX VrefLevel [Byte0]: 37
7906 12:18:38.010033 [Byte1]: 37
7907 12:18:38.014794
7908 12:18:38.014898 Set Vref, RX VrefLevel [Byte0]: 38
7909 12:18:38.018030 [Byte1]: 38
7910 12:18:38.022234
7911 12:18:38.022319 Set Vref, RX VrefLevel [Byte0]: 39
7912 12:18:38.025635 [Byte1]: 39
7913 12:18:38.029599
7914 12:18:38.029683 Set Vref, RX VrefLevel [Byte0]: 40
7915 12:18:38.036346 [Byte1]: 40
7916 12:18:38.036432
7917 12:18:38.039996 Set Vref, RX VrefLevel [Byte0]: 41
7918 12:18:38.043044 [Byte1]: 41
7919 12:18:38.043127
7920 12:18:38.046277 Set Vref, RX VrefLevel [Byte0]: 42
7921 12:18:38.049795 [Byte1]: 42
7922 12:18:38.053211
7923 12:18:38.053295 Set Vref, RX VrefLevel [Byte0]: 43
7924 12:18:38.056108 [Byte1]: 43
7925 12:18:38.060217
7926 12:18:38.060301 Set Vref, RX VrefLevel [Byte0]: 44
7927 12:18:38.064422 [Byte1]: 44
7928 12:18:38.067811
7929 12:18:38.067895 Set Vref, RX VrefLevel [Byte0]: 45
7930 12:18:38.071375 [Byte1]: 45
7931 12:18:38.075944
7932 12:18:38.076026 Set Vref, RX VrefLevel [Byte0]: 46
7933 12:18:38.078661 [Byte1]: 46
7934 12:18:38.082970
7935 12:18:38.083055 Set Vref, RX VrefLevel [Byte0]: 47
7936 12:18:38.086467 [Byte1]: 47
7937 12:18:38.090688
7938 12:18:38.090841 Set Vref, RX VrefLevel [Byte0]: 48
7939 12:18:38.094713 [Byte1]: 48
7940 12:18:38.098267
7941 12:18:38.098366 Set Vref, RX VrefLevel [Byte0]: 49
7942 12:18:38.101567 [Byte1]: 49
7943 12:18:38.106477
7944 12:18:38.106560 Set Vref, RX VrefLevel [Byte0]: 50
7945 12:18:38.109222 [Byte1]: 50
7946 12:18:38.113678
7947 12:18:38.113760 Set Vref, RX VrefLevel [Byte0]: 51
7948 12:18:38.117132 [Byte1]: 51
7949 12:18:38.120934
7950 12:18:38.121035 Set Vref, RX VrefLevel [Byte0]: 52
7951 12:18:38.125021 [Byte1]: 52
7952 12:18:38.128731
7953 12:18:38.128813 Set Vref, RX VrefLevel [Byte0]: 53
7954 12:18:38.132289 [Byte1]: 53
7955 12:18:38.136118
7956 12:18:38.136202 Set Vref, RX VrefLevel [Byte0]: 54
7957 12:18:38.140046 [Byte1]: 54
7958 12:18:38.143858
7959 12:18:38.143943 Set Vref, RX VrefLevel [Byte0]: 55
7960 12:18:38.148155 [Byte1]: 55
7961 12:18:38.152288
7962 12:18:38.152371 Set Vref, RX VrefLevel [Byte0]: 56
7963 12:18:38.155006 [Byte1]: 56
7964 12:18:38.160399
7965 12:18:38.160484 Set Vref, RX VrefLevel [Byte0]: 57
7966 12:18:38.162643 [Byte1]: 57
7967 12:18:38.167001
7968 12:18:38.167102 Set Vref, RX VrefLevel [Byte0]: 58
7969 12:18:38.169970 [Byte1]: 58
7970 12:18:38.174513
7971 12:18:38.174630 Set Vref, RX VrefLevel [Byte0]: 59
7972 12:18:38.178257 [Byte1]: 59
7973 12:18:38.188631
7974 12:18:38.188723 Set Vref, RX VrefLevel [Byte0]: 60
7975 12:18:38.188789 [Byte1]: 60
7976 12:18:38.189515
7977 12:18:38.189596 Set Vref, RX VrefLevel [Byte0]: 61
7978 12:18:38.193085 [Byte1]: 61
7979 12:18:38.197319
7980 12:18:38.197403 Set Vref, RX VrefLevel [Byte0]: 62
7981 12:18:38.200768 [Byte1]: 62
7982 12:18:38.205243
7983 12:18:38.205346 Set Vref, RX VrefLevel [Byte0]: 63
7984 12:18:38.208490 [Byte1]: 63
7985 12:18:38.212434
7986 12:18:38.212516 Set Vref, RX VrefLevel [Byte0]: 64
7987 12:18:38.215836 [Byte1]: 64
7988 12:18:38.220323
7989 12:18:38.220424 Set Vref, RX VrefLevel [Byte0]: 65
7990 12:18:38.223202 [Byte1]: 65
7991 12:18:38.227521
7992 12:18:38.227628 Set Vref, RX VrefLevel [Byte0]: 66
7993 12:18:38.231278 [Byte1]: 66
7994 12:18:38.235565
7995 12:18:38.235697 Set Vref, RX VrefLevel [Byte0]: 67
7996 12:18:38.238462 [Byte1]: 67
7997 12:18:38.243116
7998 12:18:38.243197 Set Vref, RX VrefLevel [Byte0]: 68
7999 12:18:38.246431 [Byte1]: 68
8000 12:18:38.250537
8001 12:18:38.250619 Set Vref, RX VrefLevel [Byte0]: 69
8002 12:18:38.253614 [Byte1]: 69
8003 12:18:38.258478
8004 12:18:38.258559 Set Vref, RX VrefLevel [Byte0]: 70
8005 12:18:38.261861 [Byte1]: 70
8006 12:18:38.265539
8007 12:18:38.265635 Set Vref, RX VrefLevel [Byte0]: 71
8008 12:18:38.269658 [Byte1]: 71
8009 12:18:38.273751
8010 12:18:38.273833 Set Vref, RX VrefLevel [Byte0]: 72
8011 12:18:38.276492 [Byte1]: 72
8012 12:18:38.280712
8013 12:18:38.280793 Set Vref, RX VrefLevel [Byte0]: 73
8014 12:18:38.284951 [Byte1]: 73
8015 12:18:38.288729
8016 12:18:38.288810 Set Vref, RX VrefLevel [Byte0]: 74
8017 12:18:38.291895 [Byte1]: 74
8018 12:18:38.296164
8019 12:18:38.296245 Set Vref, RX VrefLevel [Byte0]: 75
8020 12:18:38.299266 [Byte1]: 75
8021 12:18:38.303803
8022 12:18:38.303884 Set Vref, RX VrefLevel [Byte0]: 76
8023 12:18:38.307206 [Byte1]: 76
8024 12:18:38.311723
8025 12:18:38.311846 Set Vref, RX VrefLevel [Byte0]: 77
8026 12:18:38.314654 [Byte1]: 77
8027 12:18:38.319003
8028 12:18:38.319084 Set Vref, RX VrefLevel [Byte0]: 78
8029 12:18:38.322357 [Byte1]: 78
8030 12:18:38.327002
8031 12:18:38.327083 Final RX Vref Byte 0 = 68 to rank0
8032 12:18:38.329985 Final RX Vref Byte 1 = 55 to rank0
8033 12:18:38.333259 Final RX Vref Byte 0 = 68 to rank1
8034 12:18:38.337433 Final RX Vref Byte 1 = 55 to rank1==
8035 12:18:38.339901 Dram Type= 6, Freq= 0, CH_0, rank 0
8036 12:18:38.346400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8037 12:18:38.346551 ==
8038 12:18:38.346655 DQS Delay:
8039 12:18:38.346732 DQS0 = 0, DQS1 = 0
8040 12:18:38.350235 DQM Delay:
8041 12:18:38.350332 DQM0 = 134, DQM1 = 123
8042 12:18:38.353241 DQ Delay:
8043 12:18:38.356782 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =134
8044 12:18:38.359880 DQ4 =134, DQ5 =120, DQ6 =142, DQ7 =144
8045 12:18:38.362889 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =118
8046 12:18:38.366874 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =130
8047 12:18:38.366972
8048 12:18:38.367083
8049 12:18:38.367183
8050 12:18:38.369857 [DramC_TX_OE_Calibration] TA2
8051 12:18:38.372932 Original DQ_B0 (3 6) =30, OEN = 27
8052 12:18:38.376163 Original DQ_B1 (3 6) =30, OEN = 27
8053 12:18:38.379416 24, 0x0, End_B0=24 End_B1=24
8054 12:18:38.379515 25, 0x0, End_B0=25 End_B1=25
8055 12:18:38.383169 26, 0x0, End_B0=26 End_B1=26
8056 12:18:38.385896 27, 0x0, End_B0=27 End_B1=27
8057 12:18:38.389288 28, 0x0, End_B0=28 End_B1=28
8058 12:18:38.392674 29, 0x0, End_B0=29 End_B1=29
8059 12:18:38.392756 30, 0x0, End_B0=30 End_B1=30
8060 12:18:38.396050 31, 0x4141, End_B0=30 End_B1=30
8061 12:18:38.399089 Byte0 end_step=30 best_step=27
8062 12:18:38.402532 Byte1 end_step=30 best_step=27
8063 12:18:38.405817 Byte0 TX OE(2T, 0.5T) = (3, 3)
8064 12:18:38.409245 Byte1 TX OE(2T, 0.5T) = (3, 3)
8065 12:18:38.409327
8066 12:18:38.409391
8067 12:18:38.415910 [DQSOSCAuto] RK0, (LSB)MR18= 0x2213, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
8068 12:18:38.418954 CH0 RK0: MR19=303, MR18=2213
8069 12:18:38.426198 CH0_RK0: MR19=0x303, MR18=0x2213, DQSOSC=392, MR23=63, INC=24, DEC=16
8070 12:18:38.426280
8071 12:18:38.429072 ----->DramcWriteLeveling(PI) begin...
8072 12:18:38.429154 ==
8073 12:18:38.432136 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 12:18:38.435281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 12:18:38.435363 ==
8076 12:18:38.439831 Write leveling (Byte 0): 35 => 35
8077 12:18:38.442646 Write leveling (Byte 1): 29 => 29
8078 12:18:38.445417 DramcWriteLeveling(PI) end<-----
8079 12:18:38.445497
8080 12:18:38.445561 ==
8081 12:18:38.448579 Dram Type= 6, Freq= 0, CH_0, rank 1
8082 12:18:38.451785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8083 12:18:38.455269 ==
8084 12:18:38.455350 [Gating] SW mode calibration
8085 12:18:38.464866 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8086 12:18:38.468485 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8087 12:18:38.471694 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8088 12:18:38.478408 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8089 12:18:38.481647 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8090 12:18:38.484920 1 4 12 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
8091 12:18:38.492361 1 4 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8092 12:18:38.495316 1 4 20 | B1->B0 | 3231 3434 | 1 1 | (0 0) (1 1)
8093 12:18:38.498421 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8094 12:18:38.505123 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8095 12:18:38.508261 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8096 12:18:38.511658 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8097 12:18:38.517792 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8098 12:18:38.521314 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8099 12:18:38.524472 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
8100 12:18:38.531491 1 5 20 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
8101 12:18:38.534243 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8102 12:18:38.537528 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8103 12:18:38.545107 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8104 12:18:38.547988 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8105 12:18:38.550912 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8106 12:18:38.557317 1 6 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
8107 12:18:38.560657 1 6 16 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
8108 12:18:38.563954 1 6 20 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8109 12:18:38.570815 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8110 12:18:38.574354 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8111 12:18:38.577379 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8112 12:18:38.583635 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8113 12:18:38.587318 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8114 12:18:38.590385 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8115 12:18:38.597085 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8116 12:18:38.600369 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8117 12:18:38.604376 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 12:18:38.610296 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 12:18:38.613701 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 12:18:38.617373 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 12:18:38.624092 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 12:18:38.627047 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 12:18:38.630363 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 12:18:38.636653 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 12:18:38.639560 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 12:18:38.643866 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 12:18:38.650501 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 12:18:38.653604 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 12:18:38.656480 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 12:18:38.663368 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8131 12:18:38.666396 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8132 12:18:38.669842 Total UI for P1: 0, mck2ui 16
8133 12:18:38.673411 best dqsien dly found for B0: ( 1, 9, 12)
8134 12:18:38.676084 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8135 12:18:38.682565 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8136 12:18:38.687108 Total UI for P1: 0, mck2ui 16
8137 12:18:38.689369 best dqsien dly found for B1: ( 1, 9, 18)
8138 12:18:38.692598 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8139 12:18:38.696445 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8140 12:18:38.696552
8141 12:18:38.699222 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8142 12:18:38.702810 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8143 12:18:38.705694 [Gating] SW calibration Done
8144 12:18:38.705797 ==
8145 12:18:38.709290 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 12:18:38.712693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 12:18:38.712802 ==
8148 12:18:38.715762 RX Vref Scan: 0
8149 12:18:38.715869
8150 12:18:38.719245 RX Vref 0 -> 0, step: 1
8151 12:18:38.719343
8152 12:18:38.719432 RX Delay 0 -> 252, step: 8
8153 12:18:38.725805 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8154 12:18:38.729073 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8155 12:18:38.732205 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8156 12:18:38.735694 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8157 12:18:38.738864 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8158 12:18:38.746854 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8159 12:18:38.749073 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8160 12:18:38.752398 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8161 12:18:38.756331 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8162 12:18:38.758636 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8163 12:18:38.765218 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8164 12:18:38.768607 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8165 12:18:38.772221 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8166 12:18:38.775615 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8167 12:18:38.781821 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8168 12:18:38.785251 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8169 12:18:38.785335 ==
8170 12:18:38.788566 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 12:18:38.791990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 12:18:38.792066 ==
8173 12:18:38.792129 DQS Delay:
8174 12:18:38.795582 DQS0 = 0, DQS1 = 0
8175 12:18:38.795722 DQM Delay:
8176 12:18:38.798104 DQM0 = 133, DQM1 = 127
8177 12:18:38.798203 DQ Delay:
8178 12:18:38.802047 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =127
8179 12:18:38.805593 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8180 12:18:38.808062 DQ8 =115, DQ9 =111, DQ10 =131, DQ11 =123
8181 12:18:38.814617 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8182 12:18:38.814698
8183 12:18:38.814762
8184 12:18:38.814821 ==
8185 12:18:38.817991 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 12:18:38.821512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 12:18:38.821638 ==
8188 12:18:38.821723
8189 12:18:38.821784
8190 12:18:38.825018 TX Vref Scan disable
8191 12:18:38.825099 == TX Byte 0 ==
8192 12:18:38.831086 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8193 12:18:38.834530 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8194 12:18:38.834612 == TX Byte 1 ==
8195 12:18:38.841936 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8196 12:18:38.844768 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8197 12:18:38.844850 ==
8198 12:18:38.847709 Dram Type= 6, Freq= 0, CH_0, rank 1
8199 12:18:38.851556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8200 12:18:38.851639 ==
8201 12:18:38.865304
8202 12:18:38.868943 TX Vref early break, caculate TX vref
8203 12:18:38.871889 TX Vref=16, minBit 2, minWin=21, winSum=376
8204 12:18:38.875830 TX Vref=18, minBit 0, minWin=23, winSum=388
8205 12:18:38.878414 TX Vref=20, minBit 1, minWin=23, winSum=397
8206 12:18:38.881909 TX Vref=22, minBit 1, minWin=24, winSum=407
8207 12:18:38.886047 TX Vref=24, minBit 2, minWin=24, winSum=409
8208 12:18:38.891896 TX Vref=26, minBit 6, minWin=24, winSum=414
8209 12:18:38.895417 TX Vref=28, minBit 1, minWin=24, winSum=416
8210 12:18:38.898743 TX Vref=30, minBit 0, minWin=24, winSum=408
8211 12:18:38.901873 TX Vref=32, minBit 1, minWin=23, winSum=400
8212 12:18:38.905637 TX Vref=34, minBit 0, minWin=23, winSum=392
8213 12:18:38.912020 [TxChooseVref] Worse bit 1, Min win 24, Win sum 416, Final Vref 28
8214 12:18:38.912102
8215 12:18:38.914840 Final TX Range 0 Vref 28
8216 12:18:38.914915
8217 12:18:38.914977 ==
8218 12:18:38.917934 Dram Type= 6, Freq= 0, CH_0, rank 1
8219 12:18:38.921912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8220 12:18:38.922018 ==
8221 12:18:38.922110
8222 12:18:38.922198
8223 12:18:38.924813 TX Vref Scan disable
8224 12:18:38.931377 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8225 12:18:38.931461 == TX Byte 0 ==
8226 12:18:38.934660 u2DelayCellOfst[0]=14 cells (4 PI)
8227 12:18:38.938129 u2DelayCellOfst[1]=18 cells (5 PI)
8228 12:18:38.941406 u2DelayCellOfst[2]=14 cells (4 PI)
8229 12:18:38.944742 u2DelayCellOfst[3]=14 cells (4 PI)
8230 12:18:38.947654 u2DelayCellOfst[4]=11 cells (3 PI)
8231 12:18:38.951171 u2DelayCellOfst[5]=0 cells (0 PI)
8232 12:18:38.954543 u2DelayCellOfst[6]=22 cells (6 PI)
8233 12:18:38.958704 u2DelayCellOfst[7]=22 cells (6 PI)
8234 12:18:38.961887 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8235 12:18:38.964311 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8236 12:18:38.968612 == TX Byte 1 ==
8237 12:18:38.971033 u2DelayCellOfst[8]=0 cells (0 PI)
8238 12:18:38.974119 u2DelayCellOfst[9]=3 cells (1 PI)
8239 12:18:38.977944 u2DelayCellOfst[10]=7 cells (2 PI)
8240 12:18:38.978027 u2DelayCellOfst[11]=3 cells (1 PI)
8241 12:18:38.981998 u2DelayCellOfst[12]=14 cells (4 PI)
8242 12:18:38.984696 u2DelayCellOfst[13]=14 cells (4 PI)
8243 12:18:38.987701 u2DelayCellOfst[14]=18 cells (5 PI)
8244 12:18:38.991107 u2DelayCellOfst[15]=11 cells (3 PI)
8245 12:18:38.997676 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8246 12:18:39.000866 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8247 12:18:39.000954 DramC Write-DBI on
8248 12:18:39.004096 ==
8249 12:18:39.004178 Dram Type= 6, Freq= 0, CH_0, rank 1
8250 12:18:39.010673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8251 12:18:39.010759 ==
8252 12:18:39.010825
8253 12:18:39.010885
8254 12:18:39.013703 TX Vref Scan disable
8255 12:18:39.013785 == TX Byte 0 ==
8256 12:18:39.020580 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8257 12:18:39.020664 == TX Byte 1 ==
8258 12:18:39.023851 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8259 12:18:39.028368 DramC Write-DBI off
8260 12:18:39.028449
8261 12:18:39.028520 [DATLAT]
8262 12:18:39.030922 Freq=1600, CH0 RK1
8263 12:18:39.031004
8264 12:18:39.031068 DATLAT Default: 0xf
8265 12:18:39.034877 0, 0xFFFF, sum = 0
8266 12:18:39.034964 1, 0xFFFF, sum = 0
8267 12:18:39.036985 2, 0xFFFF, sum = 0
8268 12:18:39.037067 3, 0xFFFF, sum = 0
8269 12:18:39.040592 4, 0xFFFF, sum = 0
8270 12:18:39.040675 5, 0xFFFF, sum = 0
8271 12:18:39.043599 6, 0xFFFF, sum = 0
8272 12:18:39.043742 7, 0xFFFF, sum = 0
8273 12:18:39.046767 8, 0xFFFF, sum = 0
8274 12:18:39.050163 9, 0xFFFF, sum = 0
8275 12:18:39.050247 10, 0xFFFF, sum = 0
8276 12:18:39.053529 11, 0xFFFF, sum = 0
8277 12:18:39.053618 12, 0xFFFF, sum = 0
8278 12:18:39.057124 13, 0xFFFF, sum = 0
8279 12:18:39.057220 14, 0x0, sum = 1
8280 12:18:39.060449 15, 0x0, sum = 2
8281 12:18:39.060537 16, 0x0, sum = 3
8282 12:18:39.063770 17, 0x0, sum = 4
8283 12:18:39.063869 best_step = 15
8284 12:18:39.063937
8285 12:18:39.064000 ==
8286 12:18:39.067468 Dram Type= 6, Freq= 0, CH_0, rank 1
8287 12:18:39.070060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8288 12:18:39.073304 ==
8289 12:18:39.073403 RX Vref Scan: 0
8290 12:18:39.073469
8291 12:18:39.077095 RX Vref 0 -> 0, step: 1
8292 12:18:39.077185
8293 12:18:39.077251 RX Delay 11 -> 252, step: 4
8294 12:18:39.084051 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8295 12:18:39.087450 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8296 12:18:39.090306 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8297 12:18:39.094342 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8298 12:18:39.098402 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8299 12:18:39.104698 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8300 12:18:39.107106 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8301 12:18:39.110374 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8302 12:18:39.114208 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8303 12:18:39.120454 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8304 12:18:39.123465 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8305 12:18:39.127114 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8306 12:18:39.130590 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8307 12:18:39.133452 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8308 12:18:39.140480 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8309 12:18:39.143405 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8310 12:18:39.143488 ==
8311 12:18:39.147156 Dram Type= 6, Freq= 0, CH_0, rank 1
8312 12:18:39.150167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 12:18:39.150249 ==
8314 12:18:39.153312 DQS Delay:
8315 12:18:39.153394 DQS0 = 0, DQS1 = 0
8316 12:18:39.153468 DQM Delay:
8317 12:18:39.156816 DQM0 = 130, DQM1 = 125
8318 12:18:39.156899 DQ Delay:
8319 12:18:39.160530 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =126
8320 12:18:39.163180 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =140
8321 12:18:39.170426 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8322 12:18:39.172978 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8323 12:18:39.173062
8324 12:18:39.173126
8325 12:18:39.173185
8326 12:18:39.176481 [DramC_TX_OE_Calibration] TA2
8327 12:18:39.179501 Original DQ_B0 (3 6) =30, OEN = 27
8328 12:18:39.183528 Original DQ_B1 (3 6) =30, OEN = 27
8329 12:18:39.183610 24, 0x0, End_B0=24 End_B1=24
8330 12:18:39.186155 25, 0x0, End_B0=25 End_B1=25
8331 12:18:39.189301 26, 0x0, End_B0=26 End_B1=26
8332 12:18:39.192580 27, 0x0, End_B0=27 End_B1=27
8333 12:18:39.195836 28, 0x0, End_B0=28 End_B1=28
8334 12:18:39.195921 29, 0x0, End_B0=29 End_B1=29
8335 12:18:39.199174 30, 0x0, End_B0=30 End_B1=30
8336 12:18:39.203417 31, 0x4141, End_B0=30 End_B1=30
8337 12:18:39.205780 Byte0 end_step=30 best_step=27
8338 12:18:39.210208 Byte1 end_step=30 best_step=27
8339 12:18:39.210290 Byte0 TX OE(2T, 0.5T) = (3, 3)
8340 12:18:39.212759 Byte1 TX OE(2T, 0.5T) = (3, 3)
8341 12:18:39.212855
8342 12:18:39.212920
8343 12:18:39.222672 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8344 12:18:39.226331 CH0 RK1: MR19=303, MR18=1E01
8345 12:18:39.232421 CH0_RK1: MR19=0x303, MR18=0x1E01, DQSOSC=394, MR23=63, INC=23, DEC=15
8346 12:18:39.232503 [RxdqsGatingPostProcess] freq 1600
8347 12:18:39.238567 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8348 12:18:39.242048 best DQS0 dly(2T, 0.5T) = (1, 1)
8349 12:18:39.245776 best DQS1 dly(2T, 0.5T) = (1, 1)
8350 12:18:39.248868 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8351 12:18:39.251800 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8352 12:18:39.255365 best DQS0 dly(2T, 0.5T) = (1, 1)
8353 12:18:39.259200 best DQS1 dly(2T, 0.5T) = (1, 1)
8354 12:18:39.262024 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8355 12:18:39.265671 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8356 12:18:39.268492 Pre-setting of DQS Precalculation
8357 12:18:39.272446 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8358 12:18:39.272529 ==
8359 12:18:39.275239 Dram Type= 6, Freq= 0, CH_1, rank 0
8360 12:18:39.278445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 12:18:39.278527 ==
8362 12:18:39.285149 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8363 12:18:39.288141 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8364 12:18:39.295347 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8365 12:18:39.298600 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8366 12:18:39.308283 [CA 0] Center 42 (13~72) winsize 60
8367 12:18:39.311472 [CA 1] Center 42 (13~72) winsize 60
8368 12:18:39.314833 [CA 2] Center 37 (8~67) winsize 60
8369 12:18:39.318508 [CA 3] Center 36 (7~66) winsize 60
8370 12:18:39.321665 [CA 4] Center 36 (7~66) winsize 60
8371 12:18:39.324760 [CA 5] Center 37 (7~67) winsize 61
8372 12:18:39.324846
8373 12:18:39.328104 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8374 12:18:39.328186
8375 12:18:39.331303 [CATrainingPosCal] consider 1 rank data
8376 12:18:39.334650 u2DelayCellTimex100 = 262/100 ps
8377 12:18:39.341195 CA0 delay=42 (13~72),Diff = 6 PI (22 cell)
8378 12:18:39.344345 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8379 12:18:39.347931 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8380 12:18:39.351300 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8381 12:18:39.354318 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8382 12:18:39.357707 CA5 delay=37 (7~67),Diff = 1 PI (3 cell)
8383 12:18:39.357806
8384 12:18:39.360959 CA PerBit enable=1, Macro0, CA PI delay=36
8385 12:18:39.361046
8386 12:18:39.364404 [CBTSetCACLKResult] CA Dly = 36
8387 12:18:39.367556 CS Dly: 9 (0~40)
8388 12:18:39.370984 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8389 12:18:39.374728 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8390 12:18:39.374809 ==
8391 12:18:39.377592 Dram Type= 6, Freq= 0, CH_1, rank 1
8392 12:18:39.384200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8393 12:18:39.384283 ==
8394 12:18:39.387361 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8395 12:18:39.394351 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8396 12:18:39.397131 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8397 12:18:39.403940 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8398 12:18:39.411545 [CA 0] Center 42 (12~72) winsize 61
8399 12:18:39.414792 [CA 1] Center 42 (13~72) winsize 60
8400 12:18:39.418091 [CA 2] Center 37 (8~67) winsize 60
8401 12:18:39.421455 [CA 3] Center 36 (7~66) winsize 60
8402 12:18:39.424562 [CA 4] Center 37 (8~67) winsize 60
8403 12:18:39.428012 [CA 5] Center 37 (7~67) winsize 61
8404 12:18:39.428094
8405 12:18:39.430982 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8406 12:18:39.431063
8407 12:18:39.437888 [CATrainingPosCal] consider 2 rank data
8408 12:18:39.437970 u2DelayCellTimex100 = 262/100 ps
8409 12:18:39.444434 CA0 delay=42 (13~72),Diff = 6 PI (22 cell)
8410 12:18:39.448085 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8411 12:18:39.451129 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8412 12:18:39.454599 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8413 12:18:39.458090 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8414 12:18:39.460885 CA5 delay=37 (7~67),Diff = 1 PI (3 cell)
8415 12:18:39.460966
8416 12:18:39.464068 CA PerBit enable=1, Macro0, CA PI delay=36
8417 12:18:39.464149
8418 12:18:39.467378 [CBTSetCACLKResult] CA Dly = 36
8419 12:18:39.470907 CS Dly: 11 (0~44)
8420 12:18:39.474051 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8421 12:18:39.477950 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8422 12:18:39.478032
8423 12:18:39.480392 ----->DramcWriteLeveling(PI) begin...
8424 12:18:39.480474 ==
8425 12:18:39.483976 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 12:18:39.490357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 12:18:39.490439 ==
8428 12:18:39.494455 Write leveling (Byte 0): 23 => 23
8429 12:18:39.496886 Write leveling (Byte 1): 28 => 28
8430 12:18:39.496968 DramcWriteLeveling(PI) end<-----
8431 12:18:39.500606
8432 12:18:39.500689 ==
8433 12:18:39.504259 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 12:18:39.507362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 12:18:39.507443 ==
8436 12:18:39.510102 [Gating] SW mode calibration
8437 12:18:39.516970 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8438 12:18:39.523514 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8439 12:18:39.526831 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 12:18:39.530297 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 12:18:39.533622 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8442 12:18:39.539801 1 4 12 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
8443 12:18:39.543111 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8444 12:18:39.547006 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8445 12:18:39.552926 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8446 12:18:39.556937 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8447 12:18:39.559791 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8448 12:18:39.566794 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8449 12:18:39.569838 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8450 12:18:39.573170 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8451 12:18:39.579520 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8452 12:18:39.583387 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8453 12:18:39.586398 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8454 12:18:39.593694 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8455 12:18:39.596292 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8456 12:18:39.600120 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8457 12:18:39.605876 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8458 12:18:39.609296 1 6 12 | B1->B0 | 2929 4646 | 0 0 | (1 1) (0 0)
8459 12:18:39.612618 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 12:18:39.619513 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 12:18:39.622603 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8462 12:18:39.626036 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8463 12:18:39.632561 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8464 12:18:39.635645 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8465 12:18:39.638975 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8466 12:18:39.645493 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8467 12:18:39.649102 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8468 12:18:39.652115 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 12:18:39.659037 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 12:18:39.661853 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 12:18:39.665411 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 12:18:39.672234 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 12:18:39.675843 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 12:18:39.678748 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 12:18:39.685605 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 12:18:39.688312 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 12:18:39.691667 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 12:18:39.698146 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 12:18:39.701707 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 12:18:39.705210 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 12:18:39.711642 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8482 12:18:39.715128 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8483 12:18:39.718834 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8484 12:18:39.721894 Total UI for P1: 0, mck2ui 16
8485 12:18:39.725225 best dqsien dly found for B0: ( 1, 9, 10)
8486 12:18:39.731297 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8487 12:18:39.731379 Total UI for P1: 0, mck2ui 16
8488 12:18:39.737787 best dqsien dly found for B1: ( 1, 9, 14)
8489 12:18:39.741602 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8490 12:18:39.744660 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8491 12:18:39.744742
8492 12:18:39.747846 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8493 12:18:39.751250 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8494 12:18:39.754582 [Gating] SW calibration Done
8495 12:18:39.754665 ==
8496 12:18:39.757757 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 12:18:39.761204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 12:18:39.761287 ==
8499 12:18:39.764432 RX Vref Scan: 0
8500 12:18:39.764513
8501 12:18:39.767667 RX Vref 0 -> 0, step: 1
8502 12:18:39.767785
8503 12:18:39.767850 RX Delay 0 -> 252, step: 8
8504 12:18:39.774647 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8505 12:18:39.778014 iDelay=208, Bit 1, Center 135 (88 ~ 183) 96
8506 12:18:39.780719 iDelay=208, Bit 2, Center 131 (80 ~ 183) 104
8507 12:18:39.784055 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8508 12:18:39.787473 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8509 12:18:39.794127 iDelay=208, Bit 5, Center 155 (104 ~ 207) 104
8510 12:18:39.797893 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8511 12:18:39.800870 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8512 12:18:39.803878 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8513 12:18:39.807204 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8514 12:18:39.813780 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8515 12:18:39.816986 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8516 12:18:39.820185 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8517 12:18:39.823631 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8518 12:18:39.830506 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8519 12:18:39.833973 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8520 12:18:39.834055 ==
8521 12:18:39.837189 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 12:18:39.840664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 12:18:39.840747 ==
8524 12:18:39.840811 DQS Delay:
8525 12:18:39.844223 DQS0 = 0, DQS1 = 0
8526 12:18:39.844305 DQM Delay:
8527 12:18:39.847032 DQM0 = 140, DQM1 = 129
8528 12:18:39.847113 DQ Delay:
8529 12:18:39.850825 DQ0 =143, DQ1 =135, DQ2 =131, DQ3 =139
8530 12:18:39.853797 DQ4 =135, DQ5 =155, DQ6 =147, DQ7 =135
8531 12:18:39.858309 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8532 12:18:39.863271 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8533 12:18:39.863355
8534 12:18:39.863419
8535 12:18:39.863478 ==
8536 12:18:39.867880 Dram Type= 6, Freq= 0, CH_1, rank 0
8537 12:18:39.870068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8538 12:18:39.870135 ==
8539 12:18:39.870192
8540 12:18:39.870247
8541 12:18:39.873245 TX Vref Scan disable
8542 12:18:39.873326 == TX Byte 0 ==
8543 12:18:39.879793 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8544 12:18:39.883112 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8545 12:18:39.886231 == TX Byte 1 ==
8546 12:18:39.889291 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8547 12:18:39.892979 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8548 12:18:39.893060 ==
8549 12:18:39.896013 Dram Type= 6, Freq= 0, CH_1, rank 0
8550 12:18:39.899842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8551 12:18:39.903064 ==
8552 12:18:39.913906
8553 12:18:39.916900 TX Vref early break, caculate TX vref
8554 12:18:39.920251 TX Vref=16, minBit 0, minWin=21, winSum=372
8555 12:18:39.923589 TX Vref=18, minBit 0, minWin=22, winSum=380
8556 12:18:39.927480 TX Vref=20, minBit 0, minWin=23, winSum=392
8557 12:18:39.930257 TX Vref=22, minBit 0, minWin=23, winSum=400
8558 12:18:39.933439 TX Vref=24, minBit 0, minWin=24, winSum=412
8559 12:18:39.940783 TX Vref=26, minBit 0, minWin=24, winSum=418
8560 12:18:39.943653 TX Vref=28, minBit 0, minWin=24, winSum=423
8561 12:18:39.946740 TX Vref=30, minBit 1, minWin=24, winSum=417
8562 12:18:39.949909 TX Vref=32, minBit 0, minWin=23, winSum=401
8563 12:18:39.953510 TX Vref=34, minBit 0, minWin=23, winSum=393
8564 12:18:39.960024 [TxChooseVref] Worse bit 0, Min win 24, Win sum 423, Final Vref 28
8565 12:18:39.960108
8566 12:18:39.963468 Final TX Range 0 Vref 28
8567 12:18:39.963550
8568 12:18:39.963613 ==
8569 12:18:39.966716 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 12:18:39.970029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 12:18:39.970112 ==
8572 12:18:39.970177
8573 12:18:39.970235
8574 12:18:39.973096 TX Vref Scan disable
8575 12:18:39.979870 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8576 12:18:39.979953 == TX Byte 0 ==
8577 12:18:39.983369 u2DelayCellOfst[0]=18 cells (5 PI)
8578 12:18:39.986703 u2DelayCellOfst[1]=11 cells (3 PI)
8579 12:18:39.989971 u2DelayCellOfst[2]=0 cells (0 PI)
8580 12:18:39.993139 u2DelayCellOfst[3]=3 cells (1 PI)
8581 12:18:39.996244 u2DelayCellOfst[4]=3 cells (1 PI)
8582 12:18:39.999865 u2DelayCellOfst[5]=18 cells (5 PI)
8583 12:18:40.002557 u2DelayCellOfst[6]=18 cells (5 PI)
8584 12:18:40.005959 u2DelayCellOfst[7]=3 cells (1 PI)
8585 12:18:40.009621 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8586 12:18:40.012616 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8587 12:18:40.015793 == TX Byte 1 ==
8588 12:18:40.019508 u2DelayCellOfst[8]=0 cells (0 PI)
8589 12:18:40.022589 u2DelayCellOfst[9]=3 cells (1 PI)
8590 12:18:40.022672 u2DelayCellOfst[10]=11 cells (3 PI)
8591 12:18:40.026304 u2DelayCellOfst[11]=3 cells (1 PI)
8592 12:18:40.029524 u2DelayCellOfst[12]=14 cells (4 PI)
8593 12:18:40.032994 u2DelayCellOfst[13]=18 cells (5 PI)
8594 12:18:40.035539 u2DelayCellOfst[14]=18 cells (5 PI)
8595 12:18:40.038978 u2DelayCellOfst[15]=18 cells (5 PI)
8596 12:18:40.045700 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8597 12:18:40.049559 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8598 12:18:40.049642 DramC Write-DBI on
8599 12:18:40.052672 ==
8600 12:18:40.055310 Dram Type= 6, Freq= 0, CH_1, rank 0
8601 12:18:40.058619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8602 12:18:40.058703 ==
8603 12:18:40.058767
8604 12:18:40.058826
8605 12:18:40.062136 TX Vref Scan disable
8606 12:18:40.062217 == TX Byte 0 ==
8607 12:18:40.068820 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8608 12:18:40.068903 == TX Byte 1 ==
8609 12:18:40.072319 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8610 12:18:40.075133 DramC Write-DBI off
8611 12:18:40.075215
8612 12:18:40.075279 [DATLAT]
8613 12:18:40.078576 Freq=1600, CH1 RK0
8614 12:18:40.078658
8615 12:18:40.078721 DATLAT Default: 0xf
8616 12:18:40.081860 0, 0xFFFF, sum = 0
8617 12:18:40.081943 1, 0xFFFF, sum = 0
8618 12:18:40.085194 2, 0xFFFF, sum = 0
8619 12:18:40.085277 3, 0xFFFF, sum = 0
8620 12:18:40.088471 4, 0xFFFF, sum = 0
8621 12:18:40.088554 5, 0xFFFF, sum = 0
8622 12:18:40.091506 6, 0xFFFF, sum = 0
8623 12:18:40.095037 7, 0xFFFF, sum = 0
8624 12:18:40.095120 8, 0xFFFF, sum = 0
8625 12:18:40.098612 9, 0xFFFF, sum = 0
8626 12:18:40.098695 10, 0xFFFF, sum = 0
8627 12:18:40.102040 11, 0xFFFF, sum = 0
8628 12:18:40.102123 12, 0xFFFF, sum = 0
8629 12:18:40.104700 13, 0xFFFF, sum = 0
8630 12:18:40.104783 14, 0x0, sum = 1
8631 12:18:40.108596 15, 0x0, sum = 2
8632 12:18:40.108679 16, 0x0, sum = 3
8633 12:18:40.111159 17, 0x0, sum = 4
8634 12:18:40.111241 best_step = 15
8635 12:18:40.111305
8636 12:18:40.111366 ==
8637 12:18:40.114431 Dram Type= 6, Freq= 0, CH_1, rank 0
8638 12:18:40.117529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8639 12:18:40.121184 ==
8640 12:18:40.121263 RX Vref Scan: 1
8641 12:18:40.121326
8642 12:18:40.124315 Set Vref Range= 24 -> 127
8643 12:18:40.124395
8644 12:18:40.127593 RX Vref 24 -> 127, step: 1
8645 12:18:40.127682
8646 12:18:40.127762 RX Delay 11 -> 252, step: 4
8647 12:18:40.127822
8648 12:18:40.130881 Set Vref, RX VrefLevel [Byte0]: 24
8649 12:18:40.134515 [Byte1]: 24
8650 12:18:40.139100
8651 12:18:40.139180 Set Vref, RX VrefLevel [Byte0]: 25
8652 12:18:40.141482 [Byte1]: 25
8653 12:18:40.145647
8654 12:18:40.145726 Set Vref, RX VrefLevel [Byte0]: 26
8655 12:18:40.148915 [Byte1]: 26
8656 12:18:40.153736
8657 12:18:40.153816 Set Vref, RX VrefLevel [Byte0]: 27
8658 12:18:40.156868 [Byte1]: 27
8659 12:18:40.161219
8660 12:18:40.161299 Set Vref, RX VrefLevel [Byte0]: 28
8661 12:18:40.164690 [Byte1]: 28
8662 12:18:40.168685
8663 12:18:40.168764 Set Vref, RX VrefLevel [Byte0]: 29
8664 12:18:40.172815 [Byte1]: 29
8665 12:18:40.176948
8666 12:18:40.177028 Set Vref, RX VrefLevel [Byte0]: 30
8667 12:18:40.179591 [Byte1]: 30
8668 12:18:40.183986
8669 12:18:40.184066 Set Vref, RX VrefLevel [Byte0]: 31
8670 12:18:40.187463 [Byte1]: 31
8671 12:18:40.192382
8672 12:18:40.192462 Set Vref, RX VrefLevel [Byte0]: 32
8673 12:18:40.194858 [Byte1]: 32
8674 12:18:40.199176
8675 12:18:40.199260 Set Vref, RX VrefLevel [Byte0]: 33
8676 12:18:40.203061 [Byte1]: 33
8677 12:18:40.206696
8678 12:18:40.206776 Set Vref, RX VrefLevel [Byte0]: 34
8679 12:18:40.209844 [Byte1]: 34
8680 12:18:40.214832
8681 12:18:40.214911 Set Vref, RX VrefLevel [Byte0]: 35
8682 12:18:40.217554 [Byte1]: 35
8683 12:18:40.222228
8684 12:18:40.222308 Set Vref, RX VrefLevel [Byte0]: 36
8685 12:18:40.225198 [Byte1]: 36
8686 12:18:40.229445
8687 12:18:40.229525 Set Vref, RX VrefLevel [Byte0]: 37
8688 12:18:40.232914 [Byte1]: 37
8689 12:18:40.237850
8690 12:18:40.237930 Set Vref, RX VrefLevel [Byte0]: 38
8691 12:18:40.240870 [Byte1]: 38
8692 12:18:40.245312
8693 12:18:40.245391 Set Vref, RX VrefLevel [Byte0]: 39
8694 12:18:40.248038 [Byte1]: 39
8695 12:18:40.252683
8696 12:18:40.252763 Set Vref, RX VrefLevel [Byte0]: 40
8697 12:18:40.255503 [Byte1]: 40
8698 12:18:40.259939
8699 12:18:40.260033 Set Vref, RX VrefLevel [Byte0]: 41
8700 12:18:40.263581 [Byte1]: 41
8701 12:18:40.267956
8702 12:18:40.268036 Set Vref, RX VrefLevel [Byte0]: 42
8703 12:18:40.271099 [Byte1]: 42
8704 12:18:40.275073
8705 12:18:40.275153 Set Vref, RX VrefLevel [Byte0]: 43
8706 12:18:40.278480 [Byte1]: 43
8707 12:18:40.282832
8708 12:18:40.282912 Set Vref, RX VrefLevel [Byte0]: 44
8709 12:18:40.285893 [Byte1]: 44
8710 12:18:40.290694
8711 12:18:40.290773 Set Vref, RX VrefLevel [Byte0]: 45
8712 12:18:40.293716 [Byte1]: 45
8713 12:18:40.297963
8714 12:18:40.298042 Set Vref, RX VrefLevel [Byte0]: 46
8715 12:18:40.301826 [Byte1]: 46
8716 12:18:40.305573
8717 12:18:40.305652 Set Vref, RX VrefLevel [Byte0]: 47
8718 12:18:40.309229 [Byte1]: 47
8719 12:18:40.313542
8720 12:18:40.313621 Set Vref, RX VrefLevel [Byte0]: 48
8721 12:18:40.316852 [Byte1]: 48
8722 12:18:40.320911
8723 12:18:40.321017 Set Vref, RX VrefLevel [Byte0]: 49
8724 12:18:40.324449 [Byte1]: 49
8725 12:18:40.328348
8726 12:18:40.328428 Set Vref, RX VrefLevel [Byte0]: 50
8727 12:18:40.331732 [Byte1]: 50
8728 12:18:40.336465
8729 12:18:40.336546 Set Vref, RX VrefLevel [Byte0]: 51
8730 12:18:40.339385 [Byte1]: 51
8731 12:18:40.344091
8732 12:18:40.344172 Set Vref, RX VrefLevel [Byte0]: 52
8733 12:18:40.347058 [Byte1]: 52
8734 12:18:40.351156
8735 12:18:40.351237 Set Vref, RX VrefLevel [Byte0]: 53
8736 12:18:40.354494 [Byte1]: 53
8737 12:18:40.359422
8738 12:18:40.359507 Set Vref, RX VrefLevel [Byte0]: 54
8739 12:18:40.362474 [Byte1]: 54
8740 12:18:40.366853
8741 12:18:40.366934 Set Vref, RX VrefLevel [Byte0]: 55
8742 12:18:40.370346 [Byte1]: 55
8743 12:18:40.374099
8744 12:18:40.374180 Set Vref, RX VrefLevel [Byte0]: 56
8745 12:18:40.377400 [Byte1]: 56
8746 12:18:40.381884
8747 12:18:40.381966 Set Vref, RX VrefLevel [Byte0]: 57
8748 12:18:40.385412 [Byte1]: 57
8749 12:18:40.390294
8750 12:18:40.390375 Set Vref, RX VrefLevel [Byte0]: 58
8751 12:18:40.393408 [Byte1]: 58
8752 12:18:40.397205
8753 12:18:40.397285 Set Vref, RX VrefLevel [Byte0]: 59
8754 12:18:40.400618 [Byte1]: 59
8755 12:18:40.404488
8756 12:18:40.404568 Set Vref, RX VrefLevel [Byte0]: 60
8757 12:18:40.408163 [Byte1]: 60
8758 12:18:40.412641
8759 12:18:40.412721 Set Vref, RX VrefLevel [Byte0]: 61
8760 12:18:40.415703 [Byte1]: 61
8761 12:18:40.419852
8762 12:18:40.419936 Set Vref, RX VrefLevel [Byte0]: 62
8763 12:18:40.423223 [Byte1]: 62
8764 12:18:40.427326
8765 12:18:40.427406 Set Vref, RX VrefLevel [Byte0]: 63
8766 12:18:40.430894 [Byte1]: 63
8767 12:18:40.435335
8768 12:18:40.435415 Set Vref, RX VrefLevel [Byte0]: 64
8769 12:18:40.438150 [Byte1]: 64
8770 12:18:40.442926
8771 12:18:40.443007 Set Vref, RX VrefLevel [Byte0]: 65
8772 12:18:40.446480 [Byte1]: 65
8773 12:18:40.450293
8774 12:18:40.450374 Set Vref, RX VrefLevel [Byte0]: 66
8775 12:18:40.454020 [Byte1]: 66
8776 12:18:40.457833
8777 12:18:40.457915 Set Vref, RX VrefLevel [Byte0]: 67
8778 12:18:40.461653 [Byte1]: 67
8779 12:18:40.465432
8780 12:18:40.465514 Set Vref, RX VrefLevel [Byte0]: 68
8781 12:18:40.468664 [Byte1]: 68
8782 12:18:40.473227
8783 12:18:40.473309 Set Vref, RX VrefLevel [Byte0]: 69
8784 12:18:40.476730 [Byte1]: 69
8785 12:18:40.480726
8786 12:18:40.480809 Set Vref, RX VrefLevel [Byte0]: 70
8787 12:18:40.484268 [Byte1]: 70
8788 12:18:40.488203
8789 12:18:40.488285 Set Vref, RX VrefLevel [Byte0]: 71
8790 12:18:40.491707 [Byte1]: 71
8791 12:18:40.496039
8792 12:18:40.496120 Set Vref, RX VrefLevel [Byte0]: 72
8793 12:18:40.500053 [Byte1]: 72
8794 12:18:40.503693
8795 12:18:40.503791 Set Vref, RX VrefLevel [Byte0]: 73
8796 12:18:40.506733 [Byte1]: 73
8797 12:18:40.511273
8798 12:18:40.511354 Final RX Vref Byte 0 = 56 to rank0
8799 12:18:40.514223 Final RX Vref Byte 1 = 61 to rank0
8800 12:18:40.517606 Final RX Vref Byte 0 = 56 to rank1
8801 12:18:40.521389 Final RX Vref Byte 1 = 61 to rank1==
8802 12:18:40.524182 Dram Type= 6, Freq= 0, CH_1, rank 0
8803 12:18:40.530885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 12:18:40.530967 ==
8805 12:18:40.531033 DQS Delay:
8806 12:18:40.533972 DQS0 = 0, DQS1 = 0
8807 12:18:40.534053 DQM Delay:
8808 12:18:40.537747 DQM0 = 135, DQM1 = 128
8809 12:18:40.537829 DQ Delay:
8810 12:18:40.541407 DQ0 =142, DQ1 =128, DQ2 =126, DQ3 =132
8811 12:18:40.543870 DQ4 =132, DQ5 =148, DQ6 =146, DQ7 =130
8812 12:18:40.547631 DQ8 =116, DQ9 =114, DQ10 =130, DQ11 =118
8813 12:18:40.550823 DQ12 =136, DQ13 =136, DQ14 =138, DQ15 =138
8814 12:18:40.550904
8815 12:18:40.550968
8816 12:18:40.551027
8817 12:18:40.554222 [DramC_TX_OE_Calibration] TA2
8818 12:18:40.557423 Original DQ_B0 (3 6) =30, OEN = 27
8819 12:18:40.560422 Original DQ_B1 (3 6) =30, OEN = 27
8820 12:18:40.564427 24, 0x0, End_B0=24 End_B1=24
8821 12:18:40.567351 25, 0x0, End_B0=25 End_B1=25
8822 12:18:40.567434 26, 0x0, End_B0=26 End_B1=26
8823 12:18:40.570671 27, 0x0, End_B0=27 End_B1=27
8824 12:18:40.574652 28, 0x0, End_B0=28 End_B1=28
8825 12:18:40.577494 29, 0x0, End_B0=29 End_B1=29
8826 12:18:40.577577 30, 0x0, End_B0=30 End_B1=30
8827 12:18:40.580928 31, 0x4141, End_B0=30 End_B1=30
8828 12:18:40.583963 Byte0 end_step=30 best_step=27
8829 12:18:40.587120 Byte1 end_step=30 best_step=27
8830 12:18:40.590771 Byte0 TX OE(2T, 0.5T) = (3, 3)
8831 12:18:40.593864 Byte1 TX OE(2T, 0.5T) = (3, 3)
8832 12:18:40.593945
8833 12:18:40.594007
8834 12:18:40.600606 [DQSOSCAuto] RK0, (LSB)MR18= 0x180e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8835 12:18:40.603382 CH1 RK0: MR19=303, MR18=180E
8836 12:18:40.609964 CH1_RK0: MR19=0x303, MR18=0x180E, DQSOSC=397, MR23=63, INC=23, DEC=15
8837 12:18:40.610045
8838 12:18:40.613349 ----->DramcWriteLeveling(PI) begin...
8839 12:18:40.613432 ==
8840 12:18:40.616559 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 12:18:40.620674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 12:18:40.620755 ==
8843 12:18:40.623101 Write leveling (Byte 0): 25 => 25
8844 12:18:40.626902 Write leveling (Byte 1): 27 => 27
8845 12:18:40.630181 DramcWriteLeveling(PI) end<-----
8846 12:18:40.630262
8847 12:18:40.630324 ==
8848 12:18:40.633176 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 12:18:40.636861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 12:18:40.640135 ==
8851 12:18:40.640215 [Gating] SW mode calibration
8852 12:18:40.646535 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8853 12:18:40.653221 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8854 12:18:40.656966 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8855 12:18:40.663729 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8856 12:18:40.666413 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 12:18:40.670410 1 4 12 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
8858 12:18:40.677149 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8859 12:18:40.679665 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8860 12:18:40.683277 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8861 12:18:40.690102 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8862 12:18:40.692998 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8863 12:18:40.696033 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8864 12:18:40.702681 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8865 12:18:40.706462 1 5 12 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
8866 12:18:40.709770 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 1)
8867 12:18:40.716067 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8868 12:18:40.719618 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8869 12:18:40.722754 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8870 12:18:40.729023 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8871 12:18:40.732249 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8872 12:18:40.735402 1 6 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8873 12:18:40.742458 1 6 12 | B1->B0 | 4545 3939 | 0 0 | (0 0) (0 0)
8874 12:18:40.745423 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8875 12:18:40.748888 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8876 12:18:40.755909 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8877 12:18:40.758741 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8878 12:18:40.762182 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8879 12:18:40.769074 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8880 12:18:40.771994 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8881 12:18:40.775142 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8882 12:18:40.782009 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8883 12:18:40.785452 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 12:18:40.788895 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 12:18:40.795259 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 12:18:40.798349 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 12:18:40.801738 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8888 12:18:40.808250 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 12:18:40.811865 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 12:18:40.814799 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 12:18:40.822269 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 12:18:40.825171 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 12:18:40.828482 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 12:18:40.835210 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 12:18:40.837833 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 12:18:40.841544 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8897 12:18:40.847771 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8898 12:18:40.851257 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8899 12:18:40.854648 Total UI for P1: 0, mck2ui 16
8900 12:18:40.858484 best dqsien dly found for B0: ( 1, 9, 10)
8901 12:18:40.861231 Total UI for P1: 0, mck2ui 16
8902 12:18:40.864718 best dqsien dly found for B1: ( 1, 9, 10)
8903 12:18:40.868012 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8904 12:18:40.871433 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8905 12:18:40.871514
8906 12:18:40.874433 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8907 12:18:40.878043 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8908 12:18:40.881137 [Gating] SW calibration Done
8909 12:18:40.881218 ==
8910 12:18:40.884432 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 12:18:40.891301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 12:18:40.891383 ==
8913 12:18:40.891446 RX Vref Scan: 0
8914 12:18:40.891505
8915 12:18:40.894109 RX Vref 0 -> 0, step: 1
8916 12:18:40.894189
8917 12:18:40.897492 RX Delay 0 -> 252, step: 8
8918 12:18:40.900913 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8919 12:18:40.904074 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8920 12:18:40.907206 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8921 12:18:40.910463 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8922 12:18:40.916916 iDelay=208, Bit 4, Center 139 (80 ~ 199) 120
8923 12:18:40.920722 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8924 12:18:40.923800 iDelay=208, Bit 6, Center 151 (96 ~ 207) 112
8925 12:18:40.927039 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8926 12:18:40.930600 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8927 12:18:40.937402 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8928 12:18:40.940519 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8929 12:18:40.943407 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8930 12:18:40.946941 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8931 12:18:40.953181 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8932 12:18:40.956753 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8933 12:18:40.960257 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8934 12:18:40.960337 ==
8935 12:18:40.963733 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 12:18:40.967307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 12:18:40.967388 ==
8938 12:18:40.969622 DQS Delay:
8939 12:18:40.969690 DQS0 = 0, DQS1 = 0
8940 12:18:40.973324 DQM Delay:
8941 12:18:40.973405 DQM0 = 138, DQM1 = 130
8942 12:18:40.976096 DQ Delay:
8943 12:18:40.980262 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8944 12:18:40.983001 DQ4 =139, DQ5 =151, DQ6 =151, DQ7 =135
8945 12:18:40.986105 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8946 12:18:40.989345 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8947 12:18:40.989427
8948 12:18:40.989492
8949 12:18:40.989552 ==
8950 12:18:40.992825 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 12:18:40.996238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 12:18:40.996321 ==
8953 12:18:40.996385
8954 12:18:40.999282
8955 12:18:40.999363 TX Vref Scan disable
8956 12:18:41.002765 == TX Byte 0 ==
8957 12:18:41.006439 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8958 12:18:41.009331 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8959 12:18:41.012968 == TX Byte 1 ==
8960 12:18:41.015883 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8961 12:18:41.019417 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8962 12:18:41.019499 ==
8963 12:18:41.022513 Dram Type= 6, Freq= 0, CH_1, rank 1
8964 12:18:41.029271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8965 12:18:41.029353 ==
8966 12:18:41.041403
8967 12:18:41.044083 TX Vref early break, caculate TX vref
8968 12:18:41.047626 TX Vref=16, minBit 1, minWin=23, winSum=391
8969 12:18:41.051241 TX Vref=18, minBit 1, minWin=23, winSum=403
8970 12:18:41.054056 TX Vref=20, minBit 0, minWin=25, winSum=413
8971 12:18:41.057456 TX Vref=22, minBit 8, minWin=25, winSum=419
8972 12:18:41.061224 TX Vref=24, minBit 1, minWin=26, winSum=428
8973 12:18:41.067427 TX Vref=26, minBit 1, minWin=26, winSum=430
8974 12:18:41.071001 TX Vref=28, minBit 3, minWin=26, winSum=434
8975 12:18:41.074011 TX Vref=30, minBit 0, minWin=26, winSum=426
8976 12:18:41.077400 TX Vref=32, minBit 0, minWin=25, winSum=418
8977 12:18:41.080943 TX Vref=34, minBit 1, minWin=24, winSum=408
8978 12:18:41.087201 [TxChooseVref] Worse bit 3, Min win 26, Win sum 434, Final Vref 28
8979 12:18:41.087290
8980 12:18:41.090453 Final TX Range 0 Vref 28
8981 12:18:41.090535
8982 12:18:41.090600 ==
8983 12:18:41.093894 Dram Type= 6, Freq= 0, CH_1, rank 1
8984 12:18:41.097228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8985 12:18:41.097312 ==
8986 12:18:41.097377
8987 12:18:41.097436
8988 12:18:41.101405 TX Vref Scan disable
8989 12:18:41.106956 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8990 12:18:41.107038 == TX Byte 0 ==
8991 12:18:41.110507 u2DelayCellOfst[0]=18 cells (5 PI)
8992 12:18:41.113633 u2DelayCellOfst[1]=14 cells (4 PI)
8993 12:18:41.117278 u2DelayCellOfst[2]=0 cells (0 PI)
8994 12:18:41.121118 u2DelayCellOfst[3]=7 cells (2 PI)
8995 12:18:41.123531 u2DelayCellOfst[4]=11 cells (3 PI)
8996 12:18:41.127097 u2DelayCellOfst[5]=22 cells (6 PI)
8997 12:18:41.129792 u2DelayCellOfst[6]=22 cells (6 PI)
8998 12:18:41.133224 u2DelayCellOfst[7]=11 cells (3 PI)
8999 12:18:41.136469 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9000 12:18:41.139882 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9001 12:18:41.143177 == TX Byte 1 ==
9002 12:18:41.146529 u2DelayCellOfst[8]=0 cells (0 PI)
9003 12:18:41.149931 u2DelayCellOfst[9]=3 cells (1 PI)
9004 12:18:41.153450 u2DelayCellOfst[10]=11 cells (3 PI)
9005 12:18:41.153532 u2DelayCellOfst[11]=3 cells (1 PI)
9006 12:18:41.156051 u2DelayCellOfst[12]=14 cells (4 PI)
9007 12:18:41.159398 u2DelayCellOfst[13]=14 cells (4 PI)
9008 12:18:41.163568 u2DelayCellOfst[14]=18 cells (5 PI)
9009 12:18:41.166699 u2DelayCellOfst[15]=18 cells (5 PI)
9010 12:18:41.172493 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9011 12:18:41.176023 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9012 12:18:41.176105 DramC Write-DBI on
9013 12:18:41.179105 ==
9014 12:18:41.183088 Dram Type= 6, Freq= 0, CH_1, rank 1
9015 12:18:41.186198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9016 12:18:41.186281 ==
9017 12:18:41.186346
9018 12:18:41.186437
9019 12:18:41.189388 TX Vref Scan disable
9020 12:18:41.189469 == TX Byte 0 ==
9021 12:18:41.195994 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9022 12:18:41.196077 == TX Byte 1 ==
9023 12:18:41.199136 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9024 12:18:41.202694 DramC Write-DBI off
9025 12:18:41.202776
9026 12:18:41.202840 [DATLAT]
9027 12:18:41.205937 Freq=1600, CH1 RK1
9028 12:18:41.206018
9029 12:18:41.206082 DATLAT Default: 0xf
9030 12:18:41.209295 0, 0xFFFF, sum = 0
9031 12:18:41.209379 1, 0xFFFF, sum = 0
9032 12:18:41.212367 2, 0xFFFF, sum = 0
9033 12:18:41.212450 3, 0xFFFF, sum = 0
9034 12:18:41.215616 4, 0xFFFF, sum = 0
9035 12:18:41.218791 5, 0xFFFF, sum = 0
9036 12:18:41.218874 6, 0xFFFF, sum = 0
9037 12:18:41.221834 7, 0xFFFF, sum = 0
9038 12:18:41.221916 8, 0xFFFF, sum = 0
9039 12:18:41.225977 9, 0xFFFF, sum = 0
9040 12:18:41.226059 10, 0xFFFF, sum = 0
9041 12:18:41.228954 11, 0xFFFF, sum = 0
9042 12:18:41.229037 12, 0xFFFF, sum = 0
9043 12:18:41.232053 13, 0xFFFF, sum = 0
9044 12:18:41.232137 14, 0x0, sum = 1
9045 12:18:41.235914 15, 0x0, sum = 2
9046 12:18:41.235997 16, 0x0, sum = 3
9047 12:18:41.238911 17, 0x0, sum = 4
9048 12:18:41.238993 best_step = 15
9049 12:18:41.239057
9050 12:18:41.239117 ==
9051 12:18:41.242259 Dram Type= 6, Freq= 0, CH_1, rank 1
9052 12:18:41.245406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9053 12:18:41.248721 ==
9054 12:18:41.248802 RX Vref Scan: 0
9055 12:18:41.248866
9056 12:18:41.252097 RX Vref 0 -> 0, step: 1
9057 12:18:41.252178
9058 12:18:41.255514 RX Delay 11 -> 252, step: 4
9059 12:18:41.258446 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9060 12:18:41.261478 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9061 12:18:41.264719 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9062 12:18:41.271473 iDelay=203, Bit 3, Center 132 (83 ~ 182) 100
9063 12:18:41.275101 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9064 12:18:41.278036 iDelay=203, Bit 5, Center 146 (95 ~ 198) 104
9065 12:18:41.281922 iDelay=203, Bit 6, Center 148 (95 ~ 202) 108
9066 12:18:41.284398 iDelay=203, Bit 7, Center 132 (83 ~ 182) 100
9067 12:18:41.291044 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9068 12:18:41.294271 iDelay=203, Bit 9, Center 114 (59 ~ 170) 112
9069 12:18:41.309549 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9070 12:18:41.309681 iDelay=203, Bit 11, Center 118 (63 ~ 174) 112
9071 12:18:41.309750 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9072 12:18:41.311280 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9073 12:18:41.314654 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9074 12:18:41.318393 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9075 12:18:41.318475 ==
9076 12:18:41.321959 Dram Type= 6, Freq= 0, CH_1, rank 1
9077 12:18:41.324230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9078 12:18:41.327804 ==
9079 12:18:41.327886 DQS Delay:
9080 12:18:41.327952 DQS0 = 0, DQS1 = 0
9081 12:18:41.331414 DQM Delay:
9082 12:18:41.331496 DQM0 = 135, DQM1 = 126
9083 12:18:41.334367 DQ Delay:
9084 12:18:41.337627 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =132
9085 12:18:41.340757 DQ4 =134, DQ5 =146, DQ6 =148, DQ7 =132
9086 12:18:41.344462 DQ8 =112, DQ9 =114, DQ10 =126, DQ11 =118
9087 12:18:41.347530 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
9088 12:18:41.347611
9089 12:18:41.347701
9090 12:18:41.347822
9091 12:18:41.351623 [DramC_TX_OE_Calibration] TA2
9092 12:18:41.353742 Original DQ_B0 (3 6) =30, OEN = 27
9093 12:18:41.357400 Original DQ_B1 (3 6) =30, OEN = 27
9094 12:18:41.360291 24, 0x0, End_B0=24 End_B1=24
9095 12:18:41.360374 25, 0x0, End_B0=25 End_B1=25
9096 12:18:41.364086 26, 0x0, End_B0=26 End_B1=26
9097 12:18:41.366958 27, 0x0, End_B0=27 End_B1=27
9098 12:18:41.370636 28, 0x0, End_B0=28 End_B1=28
9099 12:18:41.373585 29, 0x0, End_B0=29 End_B1=29
9100 12:18:41.373668 30, 0x0, End_B0=30 End_B1=30
9101 12:18:41.377316 31, 0x4141, End_B0=30 End_B1=30
9102 12:18:41.379971 Byte0 end_step=30 best_step=27
9103 12:18:41.383381 Byte1 end_step=30 best_step=27
9104 12:18:41.387098 Byte0 TX OE(2T, 0.5T) = (3, 3)
9105 12:18:41.390033 Byte1 TX OE(2T, 0.5T) = (3, 3)
9106 12:18:41.390118
9107 12:18:41.390184
9108 12:18:41.396827 [DQSOSCAuto] RK1, (LSB)MR18= 0xa06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9109 12:18:41.400264 CH1 RK1: MR19=303, MR18=A06
9110 12:18:41.406597 CH1_RK1: MR19=0x303, MR18=0xA06, DQSOSC=404, MR23=63, INC=22, DEC=15
9111 12:18:41.409873 [RxdqsGatingPostProcess] freq 1600
9112 12:18:41.413906 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9113 12:18:41.416426 best DQS0 dly(2T, 0.5T) = (1, 1)
9114 12:18:41.419779 best DQS1 dly(2T, 0.5T) = (1, 1)
9115 12:18:41.423143 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9116 12:18:41.426513 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9117 12:18:41.429460 best DQS0 dly(2T, 0.5T) = (1, 1)
9118 12:18:41.433009 best DQS1 dly(2T, 0.5T) = (1, 1)
9119 12:18:41.436927 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9120 12:18:41.439615 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9121 12:18:41.442809 Pre-setting of DQS Precalculation
9122 12:18:41.446549 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9123 12:18:41.453516 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9124 12:18:41.463118 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9125 12:18:41.463203
9126 12:18:41.463267
9127 12:18:41.465513 [Calibration Summary] 3200 Mbps
9128 12:18:41.465595 CH 0, Rank 0
9129 12:18:41.469098 SW Impedance : PASS
9130 12:18:41.469180 DUTY Scan : NO K
9131 12:18:41.472425 ZQ Calibration : PASS
9132 12:18:41.475972 Jitter Meter : NO K
9133 12:18:41.476054 CBT Training : PASS
9134 12:18:41.478948 Write leveling : PASS
9135 12:18:41.482574 RX DQS gating : PASS
9136 12:18:41.482656 RX DQ/DQS(RDDQC) : PASS
9137 12:18:41.485425 TX DQ/DQS : PASS
9138 12:18:41.488677 RX DATLAT : PASS
9139 12:18:41.488759 RX DQ/DQS(Engine): PASS
9140 12:18:41.492186 TX OE : PASS
9141 12:18:41.492269 All Pass.
9142 12:18:41.492333
9143 12:18:41.495415 CH 0, Rank 1
9144 12:18:41.495496 SW Impedance : PASS
9145 12:18:41.499691 DUTY Scan : NO K
9146 12:18:41.502680 ZQ Calibration : PASS
9147 12:18:41.502762 Jitter Meter : NO K
9148 12:18:41.505138 CBT Training : PASS
9149 12:18:41.505220 Write leveling : PASS
9150 12:18:41.508849 RX DQS gating : PASS
9151 12:18:41.511574 RX DQ/DQS(RDDQC) : PASS
9152 12:18:41.511655 TX DQ/DQS : PASS
9153 12:18:41.515053 RX DATLAT : PASS
9154 12:18:41.518268 RX DQ/DQS(Engine): PASS
9155 12:18:41.518350 TX OE : PASS
9156 12:18:41.521572 All Pass.
9157 12:18:41.521653
9158 12:18:41.521718 CH 1, Rank 0
9159 12:18:41.524999 SW Impedance : PASS
9160 12:18:41.525081 DUTY Scan : NO K
9161 12:18:41.528713 ZQ Calibration : PASS
9162 12:18:41.531953 Jitter Meter : NO K
9163 12:18:41.532034 CBT Training : PASS
9164 12:18:41.535092 Write leveling : PASS
9165 12:18:41.538039 RX DQS gating : PASS
9166 12:18:41.538120 RX DQ/DQS(RDDQC) : PASS
9167 12:18:41.541836 TX DQ/DQS : PASS
9168 12:18:41.545659 RX DATLAT : PASS
9169 12:18:41.545740 RX DQ/DQS(Engine): PASS
9170 12:18:41.548090 TX OE : PASS
9171 12:18:41.548171 All Pass.
9172 12:18:41.548236
9173 12:18:41.551280 CH 1, Rank 1
9174 12:18:41.551361 SW Impedance : PASS
9175 12:18:41.554646 DUTY Scan : NO K
9176 12:18:41.557700 ZQ Calibration : PASS
9177 12:18:41.557781 Jitter Meter : NO K
9178 12:18:41.561481 CBT Training : PASS
9179 12:18:41.564444 Write leveling : PASS
9180 12:18:41.564525 RX DQS gating : PASS
9181 12:18:41.568288 RX DQ/DQS(RDDQC) : PASS
9182 12:18:41.571051 TX DQ/DQS : PASS
9183 12:18:41.571133 RX DATLAT : PASS
9184 12:18:41.574216 RX DQ/DQS(Engine): PASS
9185 12:18:41.577807 TX OE : PASS
9186 12:18:41.577889 All Pass.
9187 12:18:41.577953
9188 12:18:41.578013 DramC Write-DBI on
9189 12:18:41.581053 PER_BANK_REFRESH: Hybrid Mode
9190 12:18:41.584611 TX_TRACKING: ON
9191 12:18:41.591137 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9192 12:18:41.600741 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9193 12:18:41.607148 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9194 12:18:41.610839 [FAST_K] Save calibration result to emmc
9195 12:18:41.613791 sync common calibartion params.
9196 12:18:41.617019 sync cbt_mode0:1, 1:1
9197 12:18:41.617100 dram_init: ddr_geometry: 2
9198 12:18:41.620497 dram_init: ddr_geometry: 2
9199 12:18:41.623904 dram_init: ddr_geometry: 2
9200 12:18:41.626781 0:dram_rank_size:100000000
9201 12:18:41.626864 1:dram_rank_size:100000000
9202 12:18:41.633833 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9203 12:18:41.636764 DFS_SHUFFLE_HW_MODE: ON
9204 12:18:41.640031 dramc_set_vcore_voltage set vcore to 725000
9205 12:18:41.640114 Read voltage for 1600, 0
9206 12:18:41.643571 Vio18 = 0
9207 12:18:41.643652 Vcore = 725000
9208 12:18:41.643763 Vdram = 0
9209 12:18:41.646732 Vddq = 0
9210 12:18:41.646814 Vmddr = 0
9211 12:18:41.650195 switch to 3200 Mbps bootup
9212 12:18:41.650276 [DramcRunTimeConfig]
9213 12:18:41.653346 PHYPLL
9214 12:18:41.653427 DPM_CONTROL_AFTERK: ON
9215 12:18:41.656623 PER_BANK_REFRESH: ON
9216 12:18:41.659926 REFRESH_OVERHEAD_REDUCTION: ON
9217 12:18:41.660007 CMD_PICG_NEW_MODE: OFF
9218 12:18:41.663621 XRTWTW_NEW_MODE: ON
9219 12:18:41.663745 XRTRTR_NEW_MODE: ON
9220 12:18:41.666502 TX_TRACKING: ON
9221 12:18:41.666584 RDSEL_TRACKING: OFF
9222 12:18:41.669913 DQS Precalculation for DVFS: ON
9223 12:18:41.673655 RX_TRACKING: OFF
9224 12:18:41.673737 HW_GATING DBG: ON
9225 12:18:41.676204 ZQCS_ENABLE_LP4: ON
9226 12:18:41.676285 RX_PICG_NEW_MODE: ON
9227 12:18:41.680015 TX_PICG_NEW_MODE: ON
9228 12:18:41.680097 ENABLE_RX_DCM_DPHY: ON
9229 12:18:41.683254 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9230 12:18:41.686406 DUMMY_READ_FOR_TRACKING: OFF
9231 12:18:41.689830 !!! SPM_CONTROL_AFTERK: OFF
9232 12:18:41.693012 !!! SPM could not control APHY
9233 12:18:41.693096 IMPEDANCE_TRACKING: ON
9234 12:18:41.696097 TEMP_SENSOR: ON
9235 12:18:41.696179 HW_SAVE_FOR_SR: OFF
9236 12:18:41.699922 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9237 12:18:41.703426 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9238 12:18:41.706996 Read ODT Tracking: ON
9239 12:18:41.709562 Refresh Rate DeBounce: ON
9240 12:18:41.709644 DFS_NO_QUEUE_FLUSH: ON
9241 12:18:41.712714 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9242 12:18:41.716573 ENABLE_DFS_RUNTIME_MRW: OFF
9243 12:18:41.719561 DDR_RESERVE_NEW_MODE: ON
9244 12:18:41.719642 MR_CBT_SWITCH_FREQ: ON
9245 12:18:41.722815 =========================
9246 12:18:41.741735 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9247 12:18:41.745241 dram_init: ddr_geometry: 2
9248 12:18:41.763010 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9249 12:18:41.766305 dram_init: dram init end (result: 0)
9250 12:18:41.772907 DRAM-K: Full calibration passed in 24588 msecs
9251 12:18:41.776646 MRC: failed to locate region type 0.
9252 12:18:41.776729 DRAM rank0 size:0x100000000,
9253 12:18:41.779859 DRAM rank1 size=0x100000000
9254 12:18:41.789218 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9255 12:18:41.796127 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9256 12:18:41.803220 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9257 12:18:41.812765 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9258 12:18:41.812855 DRAM rank0 size:0x100000000,
9259 12:18:41.816204 DRAM rank1 size=0x100000000
9260 12:18:41.816290 CBMEM:
9261 12:18:41.819441 IMD: root @ 0xfffff000 254 entries.
9262 12:18:41.822372 IMD: root @ 0xffffec00 62 entries.
9263 12:18:41.826127 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9264 12:18:41.832127 WARNING: RO_VPD is uninitialized or empty.
9265 12:18:41.835835 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9266 12:18:41.843096 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9267 12:18:41.856136 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9268 12:18:41.867540 BS: romstage times (exec / console): total (unknown) / 24083 ms
9269 12:18:41.867639
9270 12:18:41.867757
9271 12:18:41.877444 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9272 12:18:41.881252 ARM64: Exception handlers installed.
9273 12:18:41.883938 ARM64: Testing exception
9274 12:18:41.887090 ARM64: Done test exception
9275 12:18:41.887173 Enumerating buses...
9276 12:18:41.890431 Show all devs... Before device enumeration.
9277 12:18:41.893779 Root Device: enabled 1
9278 12:18:41.896912 CPU_CLUSTER: 0: enabled 1
9279 12:18:41.896994 CPU: 00: enabled 1
9280 12:18:41.900665 Compare with tree...
9281 12:18:41.900747 Root Device: enabled 1
9282 12:18:41.904313 CPU_CLUSTER: 0: enabled 1
9283 12:18:41.907100 CPU: 00: enabled 1
9284 12:18:41.907182 Root Device scanning...
9285 12:18:41.910110 scan_static_bus for Root Device
9286 12:18:41.913571 CPU_CLUSTER: 0 enabled
9287 12:18:41.917063 scan_static_bus for Root Device done
9288 12:18:41.920076 scan_bus: bus Root Device finished in 8 msecs
9289 12:18:41.920158 done
9290 12:18:41.926820 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9291 12:18:41.929848 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9292 12:18:41.936859 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9293 12:18:41.943208 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9294 12:18:41.943292 Allocating resources...
9295 12:18:41.946572 Reading resources...
9296 12:18:41.949787 Root Device read_resources bus 0 link: 0
9297 12:18:41.953023 DRAM rank0 size:0x100000000,
9298 12:18:41.953105 DRAM rank1 size=0x100000000
9299 12:18:41.960682 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9300 12:18:41.960764 CPU: 00 missing read_resources
9301 12:18:41.966335 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9302 12:18:41.969506 Root Device read_resources bus 0 link: 0 done
9303 12:18:41.972463 Done reading resources.
9304 12:18:41.976609 Show resources in subtree (Root Device)...After reading.
9305 12:18:41.979444 Root Device child on link 0 CPU_CLUSTER: 0
9306 12:18:41.982572 CPU_CLUSTER: 0 child on link 0 CPU: 00
9307 12:18:41.992329 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9308 12:18:41.992414 CPU: 00
9309 12:18:41.999215 Root Device assign_resources, bus 0 link: 0
9310 12:18:42.002358 CPU_CLUSTER: 0 missing set_resources
9311 12:18:42.005320 Root Device assign_resources, bus 0 link: 0 done
9312 12:18:42.009459 Done setting resources.
9313 12:18:42.012109 Show resources in subtree (Root Device)...After assigning values.
9314 12:18:42.015623 Root Device child on link 0 CPU_CLUSTER: 0
9315 12:18:42.022129 CPU_CLUSTER: 0 child on link 0 CPU: 00
9316 12:18:42.028657 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9317 12:18:42.032036 CPU: 00
9318 12:18:42.032119 Done allocating resources.
9319 12:18:42.039219 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9320 12:18:42.039310 Enabling resources...
9321 12:18:42.042219 done.
9322 12:18:42.045551 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9323 12:18:42.048398 Initializing devices...
9324 12:18:42.048519 Root Device init
9325 12:18:42.051728 init hardware done!
9326 12:18:42.051810 0x00000018: ctrlr->caps
9327 12:18:42.055501 52.000 MHz: ctrlr->f_max
9328 12:18:42.058319 0.400 MHz: ctrlr->f_min
9329 12:18:42.061817 0x40ff8080: ctrlr->voltages
9330 12:18:42.061900 sclk: 390625
9331 12:18:42.061965 Bus Width = 1
9332 12:18:42.065166 sclk: 390625
9333 12:18:42.065248 Bus Width = 1
9334 12:18:42.068831 Early init status = 3
9335 12:18:42.071986 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9336 12:18:42.075058 in-header: 03 fc 00 00 01 00 00 00
9337 12:18:42.078211 in-data: 00
9338 12:18:42.081605 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9339 12:18:42.086335 in-header: 03 fd 00 00 00 00 00 00
9340 12:18:42.089673 in-data:
9341 12:18:42.092572 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9342 12:18:42.096991 in-header: 03 fc 00 00 01 00 00 00
9343 12:18:42.100056 in-data: 00
9344 12:18:42.103356 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9345 12:18:42.109265 in-header: 03 fd 00 00 00 00 00 00
9346 12:18:42.112195 in-data:
9347 12:18:42.115724 [SSUSB] Setting up USB HOST controller...
9348 12:18:42.118929 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9349 12:18:42.122304 [SSUSB] phy power-on done.
9350 12:18:42.125487 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9351 12:18:42.132163 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9352 12:18:42.135098 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9353 12:18:42.142333 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9354 12:18:42.148214 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9355 12:18:42.154989 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9356 12:18:42.161546 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9357 12:18:42.168195 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9358 12:18:42.171291 SPM: binary array size = 0x9dc
9359 12:18:42.175452 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9360 12:18:42.181337 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9361 12:18:42.188659 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9362 12:18:42.194465 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9363 12:18:42.198751 configure_display: Starting display init
9364 12:18:42.231881 anx7625_power_on_init: Init interface.
9365 12:18:42.235302 anx7625_disable_pd_protocol: Disabled PD feature.
9366 12:18:42.239592 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9367 12:18:42.266459 anx7625_start_dp_work: Secure OCM version=00
9368 12:18:42.270429 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9369 12:18:42.285038 sp_tx_get_edid_block: EDID Block = 1
9370 12:18:42.386975 Extracted contents:
9371 12:18:42.390503 header: 00 ff ff ff ff ff ff 00
9372 12:18:42.394215 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9373 12:18:42.397054 version: 01 04
9374 12:18:42.400283 basic params: 95 1f 11 78 0a
9375 12:18:42.403799 chroma info: 76 90 94 55 54 90 27 21 50 54
9376 12:18:42.407179 established: 00 00 00
9377 12:18:42.413296 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9378 12:18:42.420302 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9379 12:18:42.423312 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9380 12:18:42.430030 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9381 12:18:42.436834 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9382 12:18:42.439804 extensions: 00
9383 12:18:42.439886 checksum: fb
9384 12:18:42.439951
9385 12:18:42.446041 Manufacturer: IVO Model 57d Serial Number 0
9386 12:18:42.446124 Made week 0 of 2020
9387 12:18:42.449386 EDID version: 1.4
9388 12:18:42.449468 Digital display
9389 12:18:42.452889 6 bits per primary color channel
9390 12:18:42.456239 DisplayPort interface
9391 12:18:42.459488 Maximum image size: 31 cm x 17 cm
9392 12:18:42.459571 Gamma: 220%
9393 12:18:42.459636 Check DPMS levels
9394 12:18:42.466005 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9395 12:18:42.469478 First detailed timing is preferred timing
9396 12:18:42.472316 Established timings supported:
9397 12:18:42.472397 Standard timings supported:
9398 12:18:42.475558 Detailed timings
9399 12:18:42.478739 Hex of detail: 383680a07038204018303c0035ae10000019
9400 12:18:42.485520 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9401 12:18:42.488751 0780 0798 07c8 0820 hborder 0
9402 12:18:42.492033 0438 043b 0447 0458 vborder 0
9403 12:18:42.495575 -hsync -vsync
9404 12:18:42.498800 Did detailed timing
9405 12:18:42.502710 Hex of detail: 000000000000000000000000000000000000
9406 12:18:42.504892 Manufacturer-specified data, tag 0
9407 12:18:42.508547 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9408 12:18:42.511660 ASCII string: InfoVision
9409 12:18:42.515251 Hex of detail: 000000fe00523134304e574635205248200a
9410 12:18:42.518155 ASCII string: R140NWF5 RH
9411 12:18:42.518236 Checksum
9412 12:18:42.521983 Checksum: 0xfb (valid)
9413 12:18:42.524899 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9414 12:18:42.528130 DSI data_rate: 832800000 bps
9415 12:18:42.534991 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9416 12:18:42.538276 anx7625_parse_edid: pixelclock(138800).
9417 12:18:42.541707 hactive(1920), hsync(48), hfp(24), hbp(88)
9418 12:18:42.545056 vactive(1080), vsync(12), vfp(3), vbp(17)
9419 12:18:42.548429 anx7625_dsi_config: config dsi.
9420 12:18:42.555020 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9421 12:18:42.569708 anx7625_dsi_config: success to config DSI
9422 12:18:42.572304 anx7625_dp_start: MIPI phy setup OK.
9423 12:18:42.575901 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9424 12:18:42.579034 mtk_ddp_mode_set invalid vrefresh 60
9425 12:18:42.582517 main_disp_path_setup
9426 12:18:42.582599 ovl_layer_smi_id_en
9427 12:18:42.586036 ovl_layer_smi_id_en
9428 12:18:42.586119 ccorr_config
9429 12:18:42.586183 aal_config
9430 12:18:42.588800 gamma_config
9431 12:18:42.588896 postmask_config
9432 12:18:42.592202 dither_config
9433 12:18:42.595668 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9434 12:18:42.602525 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9435 12:18:42.605392 Root Device init finished in 553 msecs
9436 12:18:42.609131 CPU_CLUSTER: 0 init
9437 12:18:42.615431 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9438 12:18:42.622073 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9439 12:18:42.622184 APU_MBOX 0x190000b0 = 0x10001
9440 12:18:42.625254 APU_MBOX 0x190001b0 = 0x10001
9441 12:18:42.628635 APU_MBOX 0x190005b0 = 0x10001
9442 12:18:42.632197 APU_MBOX 0x190006b0 = 0x10001
9443 12:18:42.638470 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9444 12:18:42.648436 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9445 12:18:42.660305 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9446 12:18:42.667317 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9447 12:18:42.678585 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9448 12:18:42.687814 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9449 12:18:42.691400 CPU_CLUSTER: 0 init finished in 81 msecs
9450 12:18:42.694314 Devices initialized
9451 12:18:42.697833 Show all devs... After init.
9452 12:18:42.697938 Root Device: enabled 1
9453 12:18:42.701076 CPU_CLUSTER: 0: enabled 1
9454 12:18:42.704410 CPU: 00: enabled 1
9455 12:18:42.707801 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9456 12:18:42.711616 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9457 12:18:42.714376 ELOG: NV offset 0x57f000 size 0x1000
9458 12:18:42.721050 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9459 12:18:42.727530 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9460 12:18:42.730765 ELOG: Event(17) added with size 13 at 2024-01-31 12:18:42 UTC
9461 12:18:42.737710 out: cmd=0x121: 03 db 21 01 00 00 00 00
9462 12:18:42.741184 in-header: 03 e4 00 00 2c 00 00 00
9463 12:18:42.754291 in-data: 7b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9464 12:18:42.757483 ELOG: Event(A1) added with size 10 at 2024-01-31 12:18:42 UTC
9465 12:18:42.763857 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9466 12:18:42.770197 ELOG: Event(A0) added with size 9 at 2024-01-31 12:18:42 UTC
9467 12:18:42.773579 elog_add_boot_reason: Logged dev mode boot
9468 12:18:42.780373 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9469 12:18:42.780487 Finalize devices...
9470 12:18:42.783205 Devices finalized
9471 12:18:42.786513 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9472 12:18:42.790502 Writing coreboot table at 0xffe64000
9473 12:18:42.796634 0. 000000000010a000-0000000000113fff: RAMSTAGE
9474 12:18:42.800141 1. 0000000040000000-00000000400fffff: RAM
9475 12:18:42.803488 2. 0000000040100000-000000004032afff: RAMSTAGE
9476 12:18:42.806500 3. 000000004032b000-00000000545fffff: RAM
9477 12:18:42.809636 4. 0000000054600000-000000005465ffff: BL31
9478 12:18:42.813393 5. 0000000054660000-00000000ffe63fff: RAM
9479 12:18:42.820172 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9480 12:18:42.823662 7. 0000000100000000-000000023fffffff: RAM
9481 12:18:42.826565 Passing 5 GPIOs to payload:
9482 12:18:42.829630 NAME | PORT | POLARITY | VALUE
9483 12:18:42.836414 EC in RW | 0x000000aa | low | undefined
9484 12:18:42.839555 EC interrupt | 0x00000005 | low | undefined
9485 12:18:42.847082 TPM interrupt | 0x000000ab | high | undefined
9486 12:18:42.849757 SD card detect | 0x00000011 | high | undefined
9487 12:18:42.853194 speaker enable | 0x00000093 | high | undefined
9488 12:18:42.855769 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9489 12:18:42.859590 in-header: 03 f9 00 00 02 00 00 00
9490 12:18:42.862863 in-data: 02 00
9491 12:18:42.866535 ADC[4]: Raw value=904139 ID=7
9492 12:18:42.869950 ADC[3]: Raw value=213282 ID=1
9493 12:18:42.870057 RAM Code: 0x71
9494 12:18:42.873589 ADC[6]: Raw value=75036 ID=0
9495 12:18:42.876289 ADC[5]: Raw value=213652 ID=1
9496 12:18:42.876397 SKU Code: 0x1
9497 12:18:42.882732 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3c95
9498 12:18:42.882870 coreboot table: 964 bytes.
9499 12:18:42.886062 IMD ROOT 0. 0xfffff000 0x00001000
9500 12:18:42.889723 IMD SMALL 1. 0xffffe000 0x00001000
9501 12:18:42.892852 RO MCACHE 2. 0xffffc000 0x00001104
9502 12:18:42.896143 CONSOLE 3. 0xfff7c000 0x00080000
9503 12:18:42.899204 FMAP 4. 0xfff7b000 0x00000452
9504 12:18:42.902882 TIME STAMP 5. 0xfff7a000 0x00000910
9505 12:18:42.906301 VBOOT WORK 6. 0xfff66000 0x00014000
9506 12:18:42.909608 RAMOOPS 7. 0xffe66000 0x00100000
9507 12:18:42.912797 COREBOOT 8. 0xffe64000 0x00002000
9508 12:18:42.916055 IMD small region:
9509 12:18:42.919209 IMD ROOT 0. 0xffffec00 0x00000400
9510 12:18:42.922821 VPD 1. 0xffffeb80 0x0000006c
9511 12:18:42.926048 MMC STATUS 2. 0xffffeb60 0x00000004
9512 12:18:42.932099 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9513 12:18:42.932210 Probing TPM: done!
9514 12:18:42.939567 Connected to device vid:did:rid of 1ae0:0028:00
9515 12:18:42.946202 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9516 12:18:42.949537 Initialized TPM device CR50 revision 0
9517 12:18:42.952374 Checking cr50 for pending updates
9518 12:18:42.957812 Reading cr50 TPM mode
9519 12:18:42.967108 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9520 12:18:42.973353 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9521 12:18:43.013062 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9522 12:18:43.016594 Checking segment from ROM address 0x40100000
9523 12:18:43.020022 Checking segment from ROM address 0x4010001c
9524 12:18:43.026753 Loading segment from ROM address 0x40100000
9525 12:18:43.026866 code (compression=0)
9526 12:18:43.036092 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9527 12:18:43.043081 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9528 12:18:43.043190 it's not compressed!
9529 12:18:43.049663 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9530 12:18:43.056132 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9531 12:18:43.074133 Loading segment from ROM address 0x4010001c
9532 12:18:43.074247 Entry Point 0x80000000
9533 12:18:43.076780 Loaded segments
9534 12:18:43.080383 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9535 12:18:43.086609 Jumping to boot code at 0x80000000(0xffe64000)
9536 12:18:43.093445 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9537 12:18:43.100053 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9538 12:18:43.108676 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9539 12:18:43.111487 Checking segment from ROM address 0x40100000
9540 12:18:43.114719 Checking segment from ROM address 0x4010001c
9541 12:18:43.121241 Loading segment from ROM address 0x40100000
9542 12:18:43.121352 code (compression=1)
9543 12:18:43.128150 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9544 12:18:43.137691 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9545 12:18:43.137803 using LZMA
9546 12:18:43.146466 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9547 12:18:43.152596 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9548 12:18:43.156141 Loading segment from ROM address 0x4010001c
9549 12:18:43.159630 Entry Point 0x54601000
9550 12:18:43.159779 Loaded segments
9551 12:18:43.162873 NOTICE: MT8192 bl31_setup
9552 12:18:43.170424 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9553 12:18:43.173645 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9554 12:18:43.176938 WARNING: region 0:
9555 12:18:43.179868 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9556 12:18:43.179948 WARNING: region 1:
9557 12:18:43.187017 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9558 12:18:43.190127 WARNING: region 2:
9559 12:18:43.193740 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9560 12:18:43.196896 WARNING: region 3:
9561 12:18:43.200105 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9562 12:18:43.203322 WARNING: region 4:
9563 12:18:43.209880 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9564 12:18:43.209963 WARNING: region 5:
9565 12:18:43.212899 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9566 12:18:43.216180 WARNING: region 6:
9567 12:18:43.219927 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9568 12:18:43.222886 WARNING: region 7:
9569 12:18:43.226258 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9570 12:18:43.233161 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9571 12:18:43.236326 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9572 12:18:43.239924 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9573 12:18:43.246894 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9574 12:18:43.249827 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9575 12:18:43.253104 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9576 12:18:43.259850 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9577 12:18:43.263470 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9578 12:18:43.269643 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9579 12:18:43.273479 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9580 12:18:43.276775 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9581 12:18:43.282724 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9582 12:18:43.286321 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9583 12:18:43.289282 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9584 12:18:43.296354 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9585 12:18:43.299488 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9586 12:18:43.305980 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9587 12:18:43.309426 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9588 12:18:43.312719 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9589 12:18:43.319369 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9590 12:18:43.322645 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9591 12:18:43.329392 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9592 12:18:43.332756 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9593 12:18:43.335685 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9594 12:18:43.342779 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9595 12:18:43.345816 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9596 12:18:43.352454 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9597 12:18:43.356235 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9598 12:18:43.359187 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9599 12:18:43.365789 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9600 12:18:43.369320 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9601 12:18:43.376360 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9602 12:18:43.379211 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9603 12:18:43.382307 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9604 12:18:43.386274 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9605 12:18:43.392582 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9606 12:18:43.396026 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9607 12:18:43.398929 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9608 12:18:43.402838 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9609 12:18:43.408972 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9610 12:18:43.412580 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9611 12:18:43.415944 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9612 12:18:43.418948 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9613 12:18:43.425641 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9614 12:18:43.429037 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9615 12:18:43.432670 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9616 12:18:43.435426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9617 12:18:43.442243 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9618 12:18:43.445343 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9619 12:18:43.452249 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9620 12:18:43.455268 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9621 12:18:43.458610 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9622 12:18:43.466047 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9623 12:18:43.468878 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9624 12:18:43.475422 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9625 12:18:43.478516 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9626 12:18:43.485343 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9627 12:18:43.489164 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9628 12:18:43.492003 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9629 12:18:43.499113 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9630 12:18:43.502425 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9631 12:18:43.508870 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9632 12:18:43.511606 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9633 12:18:43.518864 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9634 12:18:43.522230 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9635 12:18:43.528918 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9636 12:18:43.531602 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9637 12:18:43.535061 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9638 12:18:43.541711 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9639 12:18:43.544932 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9640 12:18:43.551664 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9641 12:18:43.554933 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9642 12:18:43.558353 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9643 12:18:43.565101 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9644 12:18:43.568594 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9645 12:18:43.574730 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9646 12:18:43.578426 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9647 12:18:43.585072 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9648 12:18:43.588088 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9649 12:18:43.595310 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9650 12:18:43.598629 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9651 12:18:43.601544 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9652 12:18:43.608184 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9653 12:18:43.612050 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9654 12:18:43.618585 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9655 12:18:43.621738 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9656 12:18:43.628166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9657 12:18:43.631404 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9658 12:18:43.638078 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9659 12:18:43.641493 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9660 12:18:43.644581 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9661 12:18:43.651552 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9662 12:18:43.654185 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9663 12:18:43.660895 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9664 12:18:43.664751 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9665 12:18:43.670793 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9666 12:18:43.674103 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9667 12:18:43.677380 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9668 12:18:43.681138 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9669 12:18:43.687527 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9670 12:18:43.690722 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9671 12:18:43.694244 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9672 12:18:43.700884 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9673 12:18:43.703883 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9674 12:18:43.711193 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9675 12:18:43.714360 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9676 12:18:43.717348 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9677 12:18:43.724505 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9678 12:18:43.727553 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9679 12:18:43.733954 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9680 12:18:43.737552 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9681 12:18:43.740341 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9682 12:18:43.747165 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9683 12:18:43.750687 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9684 12:18:43.756977 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9685 12:18:43.760805 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9686 12:18:43.763615 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9687 12:18:43.770170 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9688 12:18:43.773845 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9689 12:18:43.777236 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9690 12:18:43.781150 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9691 12:18:43.786871 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9692 12:18:43.790553 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9693 12:18:43.793797 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9694 12:18:43.800452 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9695 12:18:43.803881 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9696 12:18:43.807374 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9697 12:18:43.813481 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9698 12:18:43.817002 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9699 12:18:43.823888 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9700 12:18:43.827073 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9701 12:18:43.829932 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9702 12:18:43.836715 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9703 12:18:43.840014 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9704 12:18:43.846697 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9705 12:18:43.850230 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9706 12:18:43.852971 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9707 12:18:43.859691 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9708 12:18:43.862888 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9709 12:18:43.866413 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9710 12:18:43.873655 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9711 12:18:43.876302 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9712 12:18:43.883016 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9713 12:18:43.886292 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9714 12:18:43.889428 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9715 12:18:43.896184 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9716 12:18:43.899867 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9717 12:18:43.906087 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9718 12:18:43.909357 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9719 12:18:43.916062 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9720 12:18:43.919024 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9721 12:18:43.922365 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9722 12:18:43.929513 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9723 12:18:43.932530 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9724 12:18:43.935847 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9725 12:18:43.942211 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9726 12:18:43.946261 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9727 12:18:43.952799 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9728 12:18:43.956219 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9729 12:18:43.958659 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9730 12:18:43.965428 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9731 12:18:43.969151 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9732 12:18:43.975549 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9733 12:18:43.979303 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9734 12:18:43.982135 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9735 12:18:43.988566 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9736 12:18:43.991664 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9737 12:18:43.998794 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9738 12:18:44.001730 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9739 12:18:44.005158 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9740 12:18:44.012037 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9741 12:18:44.015497 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9742 12:18:44.021572 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9743 12:18:44.025010 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9744 12:18:44.028110 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9745 12:18:44.035313 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9746 12:18:44.037950 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9747 12:18:44.044750 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9748 12:18:44.048253 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9749 12:18:44.051859 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9750 12:18:44.058770 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9751 12:18:44.061182 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9752 12:18:44.068166 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9753 12:18:44.071338 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9754 12:18:44.074543 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9755 12:18:44.081648 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9756 12:18:44.084903 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9757 12:18:44.091174 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9758 12:18:44.094704 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9759 12:18:44.097657 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9760 12:18:44.104173 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9761 12:18:44.107578 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9762 12:18:44.114809 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9763 12:18:44.117269 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9764 12:18:44.124281 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9765 12:18:44.127360 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9766 12:18:44.131027 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9767 12:18:44.137881 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9768 12:18:44.140808 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9769 12:18:44.147234 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9770 12:18:44.150836 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9771 12:18:44.153988 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9772 12:18:44.160515 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9773 12:18:44.163595 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9774 12:18:44.170187 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9775 12:18:44.173727 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9776 12:18:44.180805 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9777 12:18:44.183467 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9778 12:18:44.186953 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9779 12:18:44.193358 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9780 12:18:44.196986 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9781 12:18:44.203704 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9782 12:18:44.206757 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9783 12:18:44.213549 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9784 12:18:44.216426 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9785 12:18:44.219997 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9786 12:18:44.226796 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9787 12:18:44.230064 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9788 12:18:44.236711 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9789 12:18:44.240101 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9790 12:18:44.246658 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9791 12:18:44.249940 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9792 12:18:44.253070 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9793 12:18:44.259663 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9794 12:18:44.262973 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9795 12:18:44.269680 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9796 12:18:44.272507 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9797 12:18:44.280283 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9798 12:18:44.282352 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9799 12:18:44.286184 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9800 12:18:44.289234 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9801 12:18:44.295665 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9802 12:18:44.299112 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9803 12:18:44.302287 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9804 12:18:44.309067 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9805 12:18:44.312240 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9806 12:18:44.315465 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9807 12:18:44.322511 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9808 12:18:44.325685 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9809 12:18:44.328676 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9810 12:18:44.335266 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9811 12:18:44.338673 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9812 12:18:44.345764 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9813 12:18:44.348284 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9814 12:18:44.351980 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9815 12:18:44.358217 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9816 12:18:44.361948 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9817 12:18:44.364944 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9818 12:18:44.371596 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9819 12:18:44.375031 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9820 12:18:44.381722 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9821 12:18:44.385236 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9822 12:18:44.388123 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9823 12:18:44.395050 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9824 12:18:44.398087 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9825 12:18:44.401376 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9826 12:18:44.408128 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9827 12:18:44.411618 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9828 12:18:44.414736 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9829 12:18:44.421022 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9830 12:18:44.424704 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9831 12:18:44.431012 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9832 12:18:44.434689 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9833 12:18:44.438059 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9834 12:18:44.444499 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9835 12:18:44.447825 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9836 12:18:44.454514 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9837 12:18:44.457751 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9838 12:18:44.461067 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9839 12:18:44.464346 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9840 12:18:44.470844 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9841 12:18:44.474274 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9842 12:18:44.477243 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9843 12:18:44.480631 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9844 12:18:44.487158 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9845 12:18:44.490574 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9846 12:18:44.494140 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9847 12:18:44.497401 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9848 12:18:44.503982 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9849 12:18:44.508566 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9850 12:18:44.510994 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9851 12:18:44.514176 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9852 12:18:44.520143 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9853 12:18:44.523381 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9854 12:18:44.530533 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9855 12:18:44.533293 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9856 12:18:44.539877 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9857 12:18:44.543588 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9858 12:18:44.549607 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9859 12:18:44.553226 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9860 12:18:44.556978 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9861 12:18:44.563435 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9862 12:18:44.566430 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9863 12:18:44.572680 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9864 12:18:44.575984 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9865 12:18:44.579637 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9866 12:18:44.585975 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9867 12:18:44.589958 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9868 12:18:44.596171 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9869 12:18:44.599668 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9870 12:18:44.605836 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9871 12:18:44.609383 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9872 12:18:44.612507 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9873 12:18:44.618967 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9874 12:18:44.622576 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9875 12:18:44.628799 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9876 12:18:44.632263 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9877 12:18:44.635895 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9878 12:18:44.642292 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9879 12:18:44.645640 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9880 12:18:44.652430 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9881 12:18:44.655306 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9882 12:18:44.661825 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9883 12:18:44.665267 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9884 12:18:44.668191 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9885 12:18:44.675168 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9886 12:18:44.678343 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9887 12:18:44.685062 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9888 12:18:44.688477 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9889 12:18:44.695109 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9890 12:18:44.698378 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9891 12:18:44.701747 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9892 12:18:44.707854 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9893 12:18:44.711700 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9894 12:18:44.718163 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9895 12:18:44.721755 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9896 12:18:44.724635 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9897 12:18:44.731316 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9898 12:18:44.734483 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9899 12:18:44.741454 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9900 12:18:44.744944 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9901 12:18:44.747821 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9902 12:18:44.754371 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9903 12:18:44.757199 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9904 12:18:44.764327 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9905 12:18:44.767433 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9906 12:18:44.773677 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9907 12:18:44.777338 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9908 12:18:44.780404 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9909 12:18:44.787182 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9910 12:18:44.790460 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9911 12:18:44.796834 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9912 12:18:44.800073 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9913 12:18:44.806550 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9914 12:18:44.810179 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9915 12:18:44.813555 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9916 12:18:44.819876 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9917 12:18:44.822939 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9918 12:18:44.829973 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9919 12:18:44.833500 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9920 12:18:44.836256 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9921 12:18:44.842878 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9922 12:18:44.846281 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9923 12:18:44.853437 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9924 12:18:44.856087 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9925 12:18:44.862995 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9926 12:18:44.866065 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9927 12:18:44.869663 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9928 12:18:44.876365 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9929 12:18:44.879225 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9930 12:18:44.885890 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9931 12:18:44.889411 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9932 12:18:44.896121 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9933 12:18:44.899099 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9934 12:18:44.906136 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9935 12:18:44.908778 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9936 12:18:44.915551 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9937 12:18:44.919106 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9938 12:18:44.921959 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9939 12:18:44.929063 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9940 12:18:44.932318 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9941 12:18:44.938565 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9942 12:18:44.941879 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9943 12:18:44.949098 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9944 12:18:44.952127 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9945 12:18:44.955405 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9946 12:18:44.962173 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9947 12:18:44.965318 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9948 12:18:44.972157 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9949 12:18:44.975169 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9950 12:18:44.982138 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9951 12:18:44.985272 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9952 12:18:44.988849 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9953 12:18:44.995588 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9954 12:18:44.998208 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9955 12:18:45.005176 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9956 12:18:45.008380 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9957 12:18:45.014782 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9958 12:18:45.018166 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9959 12:18:45.024536 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9960 12:18:45.028165 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9961 12:18:45.034328 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9962 12:18:45.037592 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9963 12:18:45.041264 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9964 12:18:45.047582 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9965 12:18:45.050904 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9966 12:18:45.057486 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9967 12:18:45.061102 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9968 12:18:45.067239 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9969 12:18:45.070632 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9970 12:18:45.077576 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9971 12:18:45.080987 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9972 12:18:45.083902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9973 12:18:45.090856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9974 12:18:45.093899 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9975 12:18:45.100165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9976 12:18:45.103395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9977 12:18:45.110135 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9978 12:18:45.113355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9979 12:18:45.120434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9980 12:18:45.123356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9981 12:18:45.130580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9982 12:18:45.133588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9983 12:18:45.139687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9984 12:18:45.143084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9985 12:18:45.149532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9986 12:18:45.153080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9987 12:18:45.159606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9988 12:18:45.163135 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9989 12:18:45.169529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9990 12:18:45.172559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9991 12:18:45.179439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9992 12:18:45.182589 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9993 12:18:45.189266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9994 12:18:45.192942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9995 12:18:45.199380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9996 12:18:45.202575 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9997 12:18:45.209245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9998 12:18:45.212902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9999 12:18:45.219235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10000 12:18:45.222339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10001 12:18:45.229134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10002 12:18:45.232673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10003 12:18:45.239151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10004 12:18:45.242370 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10005 12:18:45.242452 INFO: [APUAPC] vio 0
10006 12:18:45.249681 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10007 12:18:45.253466 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10008 12:18:45.256601 INFO: [APUAPC] D0_APC_0: 0x400510
10009 12:18:45.259662 INFO: [APUAPC] D0_APC_1: 0x0
10010 12:18:45.263099 INFO: [APUAPC] D0_APC_2: 0x1540
10011 12:18:45.266646 INFO: [APUAPC] D0_APC_3: 0x0
10012 12:18:45.269921 INFO: [APUAPC] D1_APC_0: 0xffffffff
10013 12:18:45.272791 INFO: [APUAPC] D1_APC_1: 0xffffffff
10014 12:18:45.276271 INFO: [APUAPC] D1_APC_2: 0x3fffff
10015 12:18:45.279996 INFO: [APUAPC] D1_APC_3: 0x0
10016 12:18:45.283597 INFO: [APUAPC] D2_APC_0: 0xffffffff
10017 12:18:45.286202 INFO: [APUAPC] D2_APC_1: 0xffffffff
10018 12:18:45.289229 INFO: [APUAPC] D2_APC_2: 0x3fffff
10019 12:18:45.292749 INFO: [APUAPC] D2_APC_3: 0x0
10020 12:18:45.296628 INFO: [APUAPC] D3_APC_0: 0xffffffff
10021 12:18:45.298962 INFO: [APUAPC] D3_APC_1: 0xffffffff
10022 12:18:45.302188 INFO: [APUAPC] D3_APC_2: 0x3fffff
10023 12:18:45.306616 INFO: [APUAPC] D3_APC_3: 0x0
10024 12:18:45.309034 INFO: [APUAPC] D4_APC_0: 0xffffffff
10025 12:18:45.312169 INFO: [APUAPC] D4_APC_1: 0xffffffff
10026 12:18:45.315552 INFO: [APUAPC] D4_APC_2: 0x3fffff
10027 12:18:45.318582 INFO: [APUAPC] D4_APC_3: 0x0
10028 12:18:45.322309 INFO: [APUAPC] D5_APC_0: 0xffffffff
10029 12:18:45.326029 INFO: [APUAPC] D5_APC_1: 0xffffffff
10030 12:18:45.328881 INFO: [APUAPC] D5_APC_2: 0x3fffff
10031 12:18:45.332837 INFO: [APUAPC] D5_APC_3: 0x0
10032 12:18:45.335144 INFO: [APUAPC] D6_APC_0: 0xffffffff
10033 12:18:45.338446 INFO: [APUAPC] D6_APC_1: 0xffffffff
10034 12:18:45.341976 INFO: [APUAPC] D6_APC_2: 0x3fffff
10035 12:18:45.345074 INFO: [APUAPC] D6_APC_3: 0x0
10036 12:18:45.348536 INFO: [APUAPC] D7_APC_0: 0xffffffff
10037 12:18:45.351810 INFO: [APUAPC] D7_APC_1: 0xffffffff
10038 12:18:45.355136 INFO: [APUAPC] D7_APC_2: 0x3fffff
10039 12:18:45.355217 INFO: [APUAPC] D7_APC_3: 0x0
10040 12:18:45.362330 INFO: [APUAPC] D8_APC_0: 0xffffffff
10041 12:18:45.365053 INFO: [APUAPC] D8_APC_1: 0xffffffff
10042 12:18:45.368331 INFO: [APUAPC] D8_APC_2: 0x3fffff
10043 12:18:45.368412 INFO: [APUAPC] D8_APC_3: 0x0
10044 12:18:45.372173 INFO: [APUAPC] D9_APC_0: 0xffffffff
10045 12:18:45.375295 INFO: [APUAPC] D9_APC_1: 0xffffffff
10046 12:18:45.378895 INFO: [APUAPC] D9_APC_2: 0x3fffff
10047 12:18:45.382077 INFO: [APUAPC] D9_APC_3: 0x0
10048 12:18:45.385380 INFO: [APUAPC] D10_APC_0: 0xffffffff
10049 12:18:45.388955 INFO: [APUAPC] D10_APC_1: 0xffffffff
10050 12:18:45.394636 INFO: [APUAPC] D10_APC_2: 0x3fffff
10051 12:18:45.394719 INFO: [APUAPC] D10_APC_3: 0x0
10052 12:18:45.397995 INFO: [APUAPC] D11_APC_0: 0xffffffff
10053 12:18:45.404635 INFO: [APUAPC] D11_APC_1: 0xffffffff
10054 12:18:45.407814 INFO: [APUAPC] D11_APC_2: 0x3fffff
10055 12:18:45.407895 INFO: [APUAPC] D11_APC_3: 0x0
10056 12:18:45.414600 INFO: [APUAPC] D12_APC_0: 0xffffffff
10057 12:18:45.418355 INFO: [APUAPC] D12_APC_1: 0xffffffff
10058 12:18:45.421601 INFO: [APUAPC] D12_APC_2: 0x3fffff
10059 12:18:45.425024 INFO: [APUAPC] D12_APC_3: 0x0
10060 12:18:45.427883 INFO: [APUAPC] D13_APC_0: 0xffffffff
10061 12:18:45.430950 INFO: [APUAPC] D13_APC_1: 0xffffffff
10062 12:18:45.434408 INFO: [APUAPC] D13_APC_2: 0x3fffff
10063 12:18:45.438020 INFO: [APUAPC] D13_APC_3: 0x0
10064 12:18:45.440754 INFO: [APUAPC] D14_APC_0: 0xffffffff
10065 12:18:45.444123 INFO: [APUAPC] D14_APC_1: 0xffffffff
10066 12:18:45.447935 INFO: [APUAPC] D14_APC_2: 0x3fffff
10067 12:18:45.451408 INFO: [APUAPC] D14_APC_3: 0x0
10068 12:18:45.454104 INFO: [APUAPC] D15_APC_0: 0xffffffff
10069 12:18:45.457267 INFO: [APUAPC] D15_APC_1: 0xffffffff
10070 12:18:45.460816 INFO: [APUAPC] D15_APC_2: 0x3fffff
10071 12:18:45.464077 INFO: [APUAPC] D15_APC_3: 0x0
10072 12:18:45.467425 INFO: [APUAPC] APC_CON: 0x4
10073 12:18:45.467507 INFO: [NOCDAPC] D0_APC_0: 0x0
10074 12:18:45.471237 INFO: [NOCDAPC] D0_APC_1: 0x0
10075 12:18:45.473826 INFO: [NOCDAPC] D1_APC_0: 0x0
10076 12:18:45.477178 INFO: [NOCDAPC] D1_APC_1: 0xfff
10077 12:18:45.480193 INFO: [NOCDAPC] D2_APC_0: 0x0
10078 12:18:45.483576 INFO: [NOCDAPC] D2_APC_1: 0xfff
10079 12:18:45.487237 INFO: [NOCDAPC] D3_APC_0: 0x0
10080 12:18:45.490386 INFO: [NOCDAPC] D3_APC_1: 0xfff
10081 12:18:45.493926 INFO: [NOCDAPC] D4_APC_0: 0x0
10082 12:18:45.496990 INFO: [NOCDAPC] D4_APC_1: 0xfff
10083 12:18:45.500027 INFO: [NOCDAPC] D5_APC_0: 0x0
10084 12:18:45.500108 INFO: [NOCDAPC] D5_APC_1: 0xfff
10085 12:18:45.503978 INFO: [NOCDAPC] D6_APC_0: 0x0
10086 12:18:45.506727 INFO: [NOCDAPC] D6_APC_1: 0xfff
10087 12:18:45.510108 INFO: [NOCDAPC] D7_APC_0: 0x0
10088 12:18:45.513130 INFO: [NOCDAPC] D7_APC_1: 0xfff
10089 12:18:45.516977 INFO: [NOCDAPC] D8_APC_0: 0x0
10090 12:18:45.519616 INFO: [NOCDAPC] D8_APC_1: 0xfff
10091 12:18:45.523111 INFO: [NOCDAPC] D9_APC_0: 0x0
10092 12:18:45.526458 INFO: [NOCDAPC] D9_APC_1: 0xfff
10093 12:18:45.530369 INFO: [NOCDAPC] D10_APC_0: 0x0
10094 12:18:45.533350 INFO: [NOCDAPC] D10_APC_1: 0xfff
10095 12:18:45.536505 INFO: [NOCDAPC] D11_APC_0: 0x0
10096 12:18:45.539621 INFO: [NOCDAPC] D11_APC_1: 0xfff
10097 12:18:45.539741 INFO: [NOCDAPC] D12_APC_0: 0x0
10098 12:18:45.543046 INFO: [NOCDAPC] D12_APC_1: 0xfff
10099 12:18:45.546264 INFO: [NOCDAPC] D13_APC_0: 0x0
10100 12:18:45.549548 INFO: [NOCDAPC] D13_APC_1: 0xfff
10101 12:18:45.552998 INFO: [NOCDAPC] D14_APC_0: 0x0
10102 12:18:45.556354 INFO: [NOCDAPC] D14_APC_1: 0xfff
10103 12:18:45.559272 INFO: [NOCDAPC] D15_APC_0: 0x0
10104 12:18:45.562702 INFO: [NOCDAPC] D15_APC_1: 0xfff
10105 12:18:45.566280 INFO: [NOCDAPC] APC_CON: 0x4
10106 12:18:45.569116 INFO: [APUAPC] set_apusys_apc done
10107 12:18:45.573112 INFO: [DEVAPC] devapc_init done
10108 12:18:45.575542 INFO: GICv3 without legacy support detected.
10109 12:18:45.578780 INFO: ARM GICv3 driver initialized in EL3
10110 12:18:45.586079 INFO: Maximum SPI INTID supported: 639
10111 12:18:45.589149 INFO: BL31: Initializing runtime services
10112 12:18:45.595616 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10113 12:18:45.595740 INFO: SPM: enable CPC mode
10114 12:18:45.602485 INFO: mcdi ready for mcusys-off-idle and system suspend
10115 12:18:45.605859 INFO: BL31: Preparing for EL3 exit to normal world
10116 12:18:45.608753 INFO: Entry point address = 0x80000000
10117 12:18:45.611862 INFO: SPSR = 0x8
10118 12:18:45.618545
10119 12:18:45.618627
10120 12:18:45.618692
10121 12:18:45.621454 Starting depthcharge on Spherion...
10122 12:18:45.621536
10123 12:18:45.621600 Wipe memory regions:
10124 12:18:45.621658
10125 12:18:45.622346 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10126 12:18:45.622448 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10127 12:18:45.622535 Setting prompt string to ['asurada:']
10128 12:18:45.622617 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10129 12:18:45.624582 [0x00000040000000, 0x00000054600000)
10130 12:18:45.746730
10131 12:18:45.746863 [0x00000054660000, 0x00000080000000)
10132 12:18:46.007495
10133 12:18:46.007630 [0x000000821a7280, 0x000000ffe64000)
10134 12:18:46.752098
10135 12:18:46.752335 [0x00000100000000, 0x00000240000000)
10136 12:18:48.643211
10137 12:18:48.645651 Initializing XHCI USB controller at 0x11200000.
10138 12:18:49.627139
10139 12:18:49.627278 R8152: Initializing
10140 12:18:49.627364
10141 12:18:49.630544 Version 9 (ocp_data = 6010)
10142 12:18:49.630627
10143 12:18:49.633742 R8152: Done initializing
10144 12:18:49.633825
10145 12:18:49.633890 Adding net device
10146 12:18:50.032634
10147 12:18:50.036314 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10148 12:18:50.036411
10149 12:18:50.036476
10150 12:18:50.036536
10151 12:18:50.036817 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10153 12:18:50.137155 asurada: tftpboot 192.168.201.1 12669567/tftp-deploy-ox3fcnsu/kernel/image.itb 12669567/tftp-deploy-ox3fcnsu/kernel/cmdline
10154 12:18:50.137311 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10155 12:18:50.137400 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10156 12:18:50.141359 tftpboot 192.168.201.1 12669567/tftp-deploy-ox3fcnsu/kernel/image.itp-deploy-ox3fcnsu/kernel/cmdline
10157 12:18:50.141470
10158 12:18:50.141537 Waiting for link
10159 12:18:50.343343
10160 12:18:50.343474 done.
10161 12:18:50.343542
10162 12:18:50.343602 MAC: f4:f5:e8:50:de:0a
10163 12:18:50.343660
10164 12:18:50.347262 Sending DHCP discover... done.
10165 12:18:50.347345
10166 12:18:50.349760 Waiting for reply... done.
10167 12:18:50.349842
10168 12:18:50.353297 Sending DHCP request... done.
10169 12:18:50.353405
10170 12:18:50.358233 Waiting for reply... done.
10171 12:18:50.358317
10172 12:18:50.358382 My ip is 192.168.201.14
10173 12:18:50.358441
10174 12:18:50.361218 The DHCP server ip is 192.168.201.1
10175 12:18:50.361301
10176 12:18:50.367585 TFTP server IP predefined by user: 192.168.201.1
10177 12:18:50.367693
10178 12:18:50.374050 Bootfile predefined by user: 12669567/tftp-deploy-ox3fcnsu/kernel/image.itb
10179 12:18:50.374206
10180 12:18:50.377334 Sending tftp read request... done.
10181 12:18:50.377443
10182 12:18:50.381332 Waiting for the transfer...
10183 12:18:50.381416
10184 12:18:50.618502 00000000 ################################################################
10185 12:18:50.618634
10186 12:18:50.853005 00080000 ################################################################
10187 12:18:50.853143
10188 12:18:51.091914 00100000 ################################################################
10189 12:18:51.092049
10190 12:18:51.329505 00180000 ################################################################
10191 12:18:51.329696
10192 12:18:51.566287 00200000 ################################################################
10193 12:18:51.566425
10194 12:18:51.804884 00280000 ################################################################
10195 12:18:51.805021
10196 12:18:52.041658 00300000 ################################################################
10197 12:18:52.041799
10198 12:18:52.274605 00380000 ################################################################
10199 12:18:52.274736
10200 12:18:52.513795 00400000 ################################################################
10201 12:18:52.513960
10202 12:18:52.752721 00480000 ################################################################
10203 12:18:52.752856
10204 12:18:52.982998 00500000 ################################################################
10205 12:18:52.983129
10206 12:18:53.217605 00580000 ################################################################
10207 12:18:53.217779
10208 12:18:53.452713 00600000 ################################################################
10209 12:18:53.452843
10210 12:18:53.694598 00680000 ################################################################
10211 12:18:53.694731
10212 12:18:53.927069 00700000 ################################################################
10213 12:18:53.927254
10214 12:18:54.157718 00780000 ################################################################
10215 12:18:54.157852
10216 12:18:54.387921 00800000 ################################################################
10217 12:18:54.388058
10218 12:18:54.615221 00880000 ################################################################
10219 12:18:54.615382
10220 12:18:54.848337 00900000 ################################################################
10221 12:18:54.848467
10222 12:18:55.080021 00980000 ################################################################
10223 12:18:55.080157
10224 12:18:55.310587 00a00000 ################################################################
10225 12:18:55.310744
10226 12:18:55.544493 00a80000 ################################################################
10227 12:18:55.544660
10228 12:18:55.783449 00b00000 ################################################################
10229 12:18:55.783581
10230 12:18:56.013292 00b80000 ################################################################
10231 12:18:56.013453
10232 12:18:56.260993 00c00000 ################################################################
10233 12:18:56.261167
10234 12:18:56.490897 00c80000 ################################################################
10235 12:18:56.491036
10236 12:18:56.717743 00d00000 ################################################################
10237 12:18:56.717905
10238 12:18:56.946743 00d80000 ################################################################
10239 12:18:56.946927
10240 12:18:57.172759 00e00000 ################################################################
10241 12:18:57.172945
10242 12:18:57.397710 00e80000 ################################################################
10243 12:18:57.397899
10244 12:18:57.633159 00f00000 ################################################################
10245 12:18:57.633347
10246 12:18:57.859037 00f80000 ################################################################
10247 12:18:57.859169
10248 12:18:58.088025 01000000 ################################################################
10249 12:18:58.088153
10250 12:18:58.322230 01080000 ################################################################
10251 12:18:58.322387
10252 12:18:58.550956 01100000 ################################################################
10253 12:18:58.551089
10254 12:18:58.782311 01180000 ################################################################
10255 12:18:58.782480
10256 12:18:59.016198 01200000 ################################################################
10257 12:18:59.016336
10258 12:18:59.243190 01280000 ################################################################
10259 12:18:59.243323
10260 12:18:59.474701 01300000 ################################################################
10261 12:18:59.474870
10262 12:18:59.704969 01380000 ################################################################
10263 12:18:59.705115
10264 12:18:59.937538 01400000 ################################################################
10265 12:18:59.937689
10266 12:19:00.174064 01480000 ################################################################
10267 12:19:00.174211
10268 12:19:00.405509 01500000 ################################################################
10269 12:19:00.405640
10270 12:19:00.635681 01580000 ################################################################
10271 12:19:00.635852
10272 12:19:00.852745 01600000 ################################################################
10273 12:19:00.852933
10274 12:19:01.083413 01680000 ################################################################
10275 12:19:01.083569
10276 12:19:01.316886 01700000 ################################################################
10277 12:19:01.317059
10278 12:19:01.534256 01780000 ################################################################
10279 12:19:01.534432
10280 12:19:01.758848 01800000 ################################################################
10281 12:19:01.759023
10282 12:19:01.990384 01880000 ################################################################
10283 12:19:01.990558
10284 12:19:02.222843 01900000 ################################################################
10285 12:19:02.222982
10286 12:19:02.444110 01980000 ################################################################
10287 12:19:02.444261
10288 12:19:02.668848 01a00000 ################################################################
10289 12:19:02.668994
10290 12:19:02.887211 01a80000 ################################################################
10291 12:19:02.887367
10292 12:19:03.113389 01b00000 ################################################################
10293 12:19:03.113532
10294 12:19:03.333184 01b80000 ################################################################
10295 12:19:03.333356
10296 12:19:03.553008 01c00000 ################################################################
10297 12:19:03.553152
10298 12:19:03.561339 01c80000 ## done.
10299 12:19:03.561422
10300 12:19:03.563822 The bootfile was 29900026 bytes long.
10301 12:19:03.563899
10302 12:19:03.567802 Sending tftp read request... done.
10303 12:19:03.567878
10304 12:19:03.567942 Waiting for the transfer...
10305 12:19:03.568002
10306 12:19:03.570610 00000000 # done.
10307 12:19:03.570696
10308 12:19:03.577127 Command line loaded dynamically from TFTP file: 12669567/tftp-deploy-ox3fcnsu/kernel/cmdline
10309 12:19:03.577248
10310 12:19:03.600128 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12669567/extract-nfsrootfs-2wdmky1e,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10311 12:19:03.600223
10312 12:19:03.600290 Loading FIT.
10313 12:19:03.600378
10314 12:19:03.603751 Image ramdisk-1 has 17803429 bytes.
10315 12:19:03.603829
10316 12:19:03.607173 Image fdt-1 has 47278 bytes.
10317 12:19:03.607277
10318 12:19:03.610406 Image kernel-1 has 12047284 bytes.
10319 12:19:03.610514
10320 12:19:03.619970 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10321 12:19:03.620081
10322 12:19:03.636542 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10323 12:19:03.636635
10324 12:19:03.643355 Choosing best match conf-1 for compat google,spherion-rev2.
10325 12:19:03.643460
10326 12:19:03.650325 Connected to device vid:did:rid of 1ae0:0028:00
10327 12:19:03.657629
10328 12:19:03.660642 tpm_get_response: command 0x17b, return code 0x0
10329 12:19:03.660755
10330 12:19:03.667364 ec_init: CrosEC protocol v3 supported (256, 248)
10331 12:19:03.667467
10332 12:19:03.670577 tpm_cleanup: add release locality here.
10333 12:19:03.670676
10334 12:19:03.674420 Shutting down all USB controllers.
10335 12:19:03.674533
10336 12:19:03.677446 Removing current net device
10337 12:19:03.677530
10338 12:19:03.680875 Exiting depthcharge with code 4 at timestamp: 47448471
10339 12:19:03.680971
10340 12:19:03.683869 LZMA decompressing kernel-1 to 0x821a6718
10341 12:19:03.683945
10342 12:19:03.687357 LZMA decompressing kernel-1 to 0x40000000
10343 12:19:05.189002
10344 12:19:05.189208 jumping to kernel
10345 12:19:05.189683 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
10346 12:19:05.189782 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
10347 12:19:05.189858 Setting prompt string to ['Linux version [0-9]']
10348 12:19:05.189925 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10349 12:19:05.189991 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10350 12:19:05.270678
10351 12:19:05.273848 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10352 12:19:05.277486 start: 2.2.5.1 login-action (timeout 00:04:05) [common]
10353 12:19:05.277582 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10354 12:19:05.277687 Setting prompt string to []
10355 12:19:05.277805 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10356 12:19:05.277914 Using line separator: #'\n'#
10357 12:19:05.277999 No login prompt set.
10358 12:19:05.278065 Parsing kernel messages
10359 12:19:05.278121 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10360 12:19:05.278231 [login-action] Waiting for messages, (timeout 00:04:05)
10361 12:19:05.297341 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j93261-arm64-gcc-10-defconfig-arm64-chromebook-cwjwh) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024
10362 12:19:05.300538 [ 0.000000] random: crng init done
10363 12:19:05.307018 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10364 12:19:05.310479 [ 0.000000] efi: UEFI not found.
10365 12:19:05.316515 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10366 12:19:05.323521 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10367 12:19:05.333015 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10368 12:19:05.343266 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10369 12:19:05.350417 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10370 12:19:05.356702 [ 0.000000] printk: bootconsole [mtk8250] enabled
10371 12:19:05.362688 [ 0.000000] NUMA: No NUMA configuration found
10372 12:19:05.369704 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10373 12:19:05.372716 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10374 12:19:05.375874 [ 0.000000] Zone ranges:
10375 12:19:05.382775 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10376 12:19:05.386211 [ 0.000000] DMA32 empty
10377 12:19:05.392533 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10378 12:19:05.396191 [ 0.000000] Movable zone start for each node
10379 12:19:05.399318 [ 0.000000] Early memory node ranges
10380 12:19:05.405499 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10381 12:19:05.412161 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10382 12:19:05.418729 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10383 12:19:05.425121 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10384 12:19:05.431749 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10385 12:19:05.438781 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10386 12:19:05.495231 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10387 12:19:05.501563 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10388 12:19:05.508242 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10389 12:19:05.511485 [ 0.000000] psci: probing for conduit method from DT.
10390 12:19:05.518162 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10391 12:19:05.521598 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10392 12:19:05.527984 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10393 12:19:05.531330 [ 0.000000] psci: SMC Calling Convention v1.2
10394 12:19:05.537944 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10395 12:19:05.540846 [ 0.000000] Detected VIPT I-cache on CPU0
10396 12:19:05.547565 [ 0.000000] CPU features: detected: GIC system register CPU interface
10397 12:19:05.554148 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10398 12:19:05.561005 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10399 12:19:05.567598 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10400 12:19:05.577465 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10401 12:19:05.583972 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10402 12:19:05.587232 [ 0.000000] alternatives: applying boot alternatives
10403 12:19:05.593925 [ 0.000000] Fallback order for Node 0: 0
10404 12:19:05.600710 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10405 12:19:05.603662 [ 0.000000] Policy zone: Normal
10406 12:19:05.627689 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12669567/extract-nfsrootfs-2wdmky1e,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10407 12:19:05.636745 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10408 12:19:05.646917 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10409 12:19:05.656659 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10410 12:19:05.663041 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10411 12:19:05.666753 <6>[ 0.000000] software IO TLB: area num 8.
10412 12:19:05.723229 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10413 12:19:05.872529 <6>[ 0.000000] Memory: 7949868K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 402900K reserved, 32768K cma-reserved)
10414 12:19:05.879213 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10415 12:19:05.885702 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10416 12:19:05.889081 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10417 12:19:05.895576 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10418 12:19:05.902317 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10419 12:19:05.905321 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10420 12:19:05.915573 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10421 12:19:05.921892 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10422 12:19:05.928622 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10423 12:19:05.934757 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10424 12:19:05.938306 <6>[ 0.000000] GICv3: 608 SPIs implemented
10425 12:19:05.941909 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10426 12:19:05.948070 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10427 12:19:05.951204 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10428 12:19:05.958212 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10429 12:19:05.971460 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10430 12:19:05.984373 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10431 12:19:05.991146 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10432 12:19:05.999240 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10433 12:19:06.012184 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10434 12:19:06.018817 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10435 12:19:06.025882 <6>[ 0.009240] Console: colour dummy device 80x25
10436 12:19:06.035384 <6>[ 0.013995] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10437 12:19:06.042037 <6>[ 0.024502] pid_max: default: 32768 minimum: 301
10438 12:19:06.045347 <6>[ 0.029403] LSM: Security Framework initializing
10439 12:19:06.055060 <6>[ 0.034342] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10440 12:19:06.062127 <6>[ 0.042203] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10441 12:19:06.071437 <6>[ 0.051618] cblist_init_generic: Setting adjustable number of callback queues.
10442 12:19:06.077902 <6>[ 0.059106] cblist_init_generic: Setting shift to 3 and lim to 1.
10443 12:19:06.084451 <6>[ 0.065444] cblist_init_generic: Setting adjustable number of callback queues.
10444 12:19:06.090937 <6>[ 0.072917] cblist_init_generic: Setting shift to 3 and lim to 1.
10445 12:19:06.094633 <6>[ 0.079357] rcu: Hierarchical SRCU implementation.
10446 12:19:06.101044 <6>[ 0.084403] rcu: Max phase no-delay instances is 1000.
10447 12:19:06.107953 <6>[ 0.091461] EFI services will not be available.
10448 12:19:06.111075 <6>[ 0.096417] smp: Bringing up secondary CPUs ...
10449 12:19:06.120241 <6>[ 0.101463] Detected VIPT I-cache on CPU1
10450 12:19:06.126831 <6>[ 0.101533] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10451 12:19:06.133200 <6>[ 0.101563] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10452 12:19:06.136424 <6>[ 0.101898] Detected VIPT I-cache on CPU2
10453 12:19:06.143396 <6>[ 0.101945] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10454 12:19:06.150031 <6>[ 0.101961] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10455 12:19:06.156609 <6>[ 0.102215] Detected VIPT I-cache on CPU3
10456 12:19:06.163987 <6>[ 0.102262] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10457 12:19:06.169810 <6>[ 0.102275] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10458 12:19:06.173186 <6>[ 0.102579] CPU features: detected: Spectre-v4
10459 12:19:06.179387 <6>[ 0.102586] CPU features: detected: Spectre-BHB
10460 12:19:06.183308 <6>[ 0.102591] Detected PIPT I-cache on CPU4
10461 12:19:06.189560 <6>[ 0.102649] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10462 12:19:06.196015 <6>[ 0.102665] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10463 12:19:06.202553 <6>[ 0.102957] Detected PIPT I-cache on CPU5
10464 12:19:06.209077 <6>[ 0.103020] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10465 12:19:06.215830 <6>[ 0.103037] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10466 12:19:06.219557 <6>[ 0.103320] Detected PIPT I-cache on CPU6
10467 12:19:06.226098 <6>[ 0.103385] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10468 12:19:06.232566 <6>[ 0.103404] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10469 12:19:06.239406 <6>[ 0.103701] Detected PIPT I-cache on CPU7
10470 12:19:06.246131 <6>[ 0.103766] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10471 12:19:06.252179 <6>[ 0.103783] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10472 12:19:06.255470 <6>[ 0.103831] smp: Brought up 1 node, 8 CPUs
10473 12:19:06.262412 <6>[ 0.245017] SMP: Total of 8 processors activated.
10474 12:19:06.265757 <6>[ 0.249937] CPU features: detected: 32-bit EL0 Support
10475 12:19:06.275375 <6>[ 0.255333] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10476 12:19:06.282383 <6>[ 0.264133] CPU features: detected: Common not Private translations
10477 12:19:06.288513 <6>[ 0.270609] CPU features: detected: CRC32 instructions
10478 12:19:06.292142 <6>[ 0.275961] CPU features: detected: RCpc load-acquire (LDAPR)
10479 12:19:06.298765 <6>[ 0.281921] CPU features: detected: LSE atomic instructions
10480 12:19:06.305298 <6>[ 0.287702] CPU features: detected: Privileged Access Never
10481 12:19:06.311878 <6>[ 0.293518] CPU features: detected: RAS Extension Support
10482 12:19:06.318575 <6>[ 0.299127] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10483 12:19:06.321766 <6>[ 0.306393] CPU: All CPU(s) started at EL2
10484 12:19:06.328276 <6>[ 0.310710] alternatives: applying system-wide alternatives
10485 12:19:06.338013 <6>[ 0.321431] devtmpfs: initialized
10486 12:19:06.353246 <6>[ 0.330283] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10487 12:19:06.359628 <6>[ 0.340243] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10488 12:19:06.366400 <6>[ 0.348467] pinctrl core: initialized pinctrl subsystem
10489 12:19:06.369831 <6>[ 0.355113] DMI not present or invalid.
10490 12:19:06.376306 <6>[ 0.359528] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10491 12:19:06.386128 <6>[ 0.366413] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10492 12:19:06.392653 <6>[ 0.373999] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10493 12:19:06.402614 <6>[ 0.382227] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10494 12:19:06.406053 <6>[ 0.390472] audit: initializing netlink subsys (disabled)
10495 12:19:06.415457 <5>[ 0.396163] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10496 12:19:06.422433 <6>[ 0.396853] thermal_sys: Registered thermal governor 'step_wise'
10497 12:19:06.428802 <6>[ 0.404132] thermal_sys: Registered thermal governor 'power_allocator'
10498 12:19:06.432646 <6>[ 0.410387] cpuidle: using governor menu
10499 12:19:06.438837 <6>[ 0.421348] NET: Registered PF_QIPCRTR protocol family
10500 12:19:06.445386 <6>[ 0.426835] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10501 12:19:06.452075 <6>[ 0.433938] ASID allocator initialised with 32768 entries
10502 12:19:06.454974 <6>[ 0.440500] Serial: AMBA PL011 UART driver
10503 12:19:06.465451 <4>[ 0.449232] Trying to register duplicate clock ID: 134
10504 12:19:06.519759 <6>[ 0.506454] KASLR enabled
10505 12:19:06.533350 <6>[ 0.514229] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10506 12:19:06.540033 <6>[ 0.521245] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10507 12:19:06.546908 <6>[ 0.527736] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10508 12:19:06.553393 <6>[ 0.534743] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10509 12:19:06.559919 <6>[ 0.541231] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10510 12:19:06.566301 <6>[ 0.548233] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10511 12:19:06.573600 <6>[ 0.554721] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10512 12:19:06.579842 <6>[ 0.561724] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10513 12:19:06.583212 <6>[ 0.569235] ACPI: Interpreter disabled.
10514 12:19:06.592084 <6>[ 0.575652] iommu: Default domain type: Translated
10515 12:19:06.598585 <6>[ 0.580763] iommu: DMA domain TLB invalidation policy: strict mode
10516 12:19:06.601566 <5>[ 0.587421] SCSI subsystem initialized
10517 12:19:06.608573 <6>[ 0.591589] usbcore: registered new interface driver usbfs
10518 12:19:06.614817 <6>[ 0.597321] usbcore: registered new interface driver hub
10519 12:19:06.618410 <6>[ 0.602872] usbcore: registered new device driver usb
10520 12:19:06.625315 <6>[ 0.608975] pps_core: LinuxPPS API ver. 1 registered
10521 12:19:06.634845 <6>[ 0.614168] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10522 12:19:06.638242 <6>[ 0.623517] PTP clock support registered
10523 12:19:06.641815 <6>[ 0.627759] EDAC MC: Ver: 3.0.0
10524 12:19:06.649045 <6>[ 0.632922] FPGA manager framework
10525 12:19:06.655470 <6>[ 0.636603] Advanced Linux Sound Architecture Driver Initialized.
10526 12:19:06.659200 <6>[ 0.643381] vgaarb: loaded
10527 12:19:06.665589 <6>[ 0.646533] clocksource: Switched to clocksource arch_sys_counter
10528 12:19:06.668582 <5>[ 0.652974] VFS: Disk quotas dquot_6.6.0
10529 12:19:06.674911 <6>[ 0.657161] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10530 12:19:06.679196 <6>[ 0.664353] pnp: PnP ACPI: disabled
10531 12:19:06.687367 <6>[ 0.671079] NET: Registered PF_INET protocol family
10532 12:19:06.696780 <6>[ 0.676680] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10533 12:19:06.708732 <6>[ 0.689012] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10534 12:19:06.718777 <6>[ 0.697828] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10535 12:19:06.724708 <6>[ 0.705801] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10536 12:19:06.734722 <6>[ 0.714500] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10537 12:19:06.741506 <6>[ 0.724249] TCP: Hash tables configured (established 65536 bind 65536)
10538 12:19:06.747974 <6>[ 0.731117] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10539 12:19:06.757662 <6>[ 0.738317] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10540 12:19:06.764146 <6>[ 0.746024] NET: Registered PF_UNIX/PF_LOCAL protocol family
10541 12:19:06.770781 <6>[ 0.752174] RPC: Registered named UNIX socket transport module.
10542 12:19:06.774226 <6>[ 0.758326] RPC: Registered udp transport module.
10543 12:19:06.781140 <6>[ 0.763259] RPC: Registered tcp transport module.
10544 12:19:06.787553 <6>[ 0.768188] RPC: Registered tcp NFSv4.1 backchannel transport module.
10545 12:19:06.791245 <6>[ 0.774850] PCI: CLS 0 bytes, default 64
10546 12:19:06.793975 <6>[ 0.779171] Unpacking initramfs...
10547 12:19:06.810942 <6>[ 0.791078] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10548 12:19:06.820756 <6>[ 0.799718] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10549 12:19:06.823584 <6>[ 0.808566] kvm [1]: IPA Size Limit: 40 bits
10550 12:19:06.830448 <6>[ 0.813095] kvm [1]: GICv3: no GICV resource entry
10551 12:19:06.833551 <6>[ 0.818117] kvm [1]: disabling GICv2 emulation
10552 12:19:06.840454 <6>[ 0.822802] kvm [1]: GIC system register CPU interface enabled
10553 12:19:06.843313 <6>[ 0.828973] kvm [1]: vgic interrupt IRQ18
10554 12:19:06.850203 <6>[ 0.833338] kvm [1]: VHE mode initialized successfully
10555 12:19:06.856423 <5>[ 0.839819] Initialise system trusted keyrings
10556 12:19:06.863238 <6>[ 0.844611] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10557 12:19:06.870846 <6>[ 0.854730] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10558 12:19:06.877272 <5>[ 0.861131] NFS: Registering the id_resolver key type
10559 12:19:06.881235 <5>[ 0.866427] Key type id_resolver registered
10560 12:19:06.887155 <5>[ 0.870841] Key type id_legacy registered
10561 12:19:06.893838 <6>[ 0.875126] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10562 12:19:06.900512 <6>[ 0.882050] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10563 12:19:06.907156 <6>[ 0.889765] 9p: Installing v9fs 9p2000 file system support
10564 12:19:06.944851 <5>[ 0.927819] Key type asymmetric registered
10565 12:19:06.947300 <5>[ 0.932151] Asymmetric key parser 'x509' registered
10566 12:19:06.957029 <6>[ 0.937294] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10567 12:19:06.961067 <6>[ 0.944908] io scheduler mq-deadline registered
10568 12:19:06.963643 <6>[ 0.949685] io scheduler kyber registered
10569 12:19:06.982690 <6>[ 0.966756] EINJ: ACPI disabled.
10570 12:19:07.015420 <4>[ 0.992603] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10571 12:19:07.025544 <4>[ 1.003264] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10572 12:19:07.040524 <6>[ 1.023997] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10573 12:19:07.047928 <6>[ 1.032043] printk: console [ttyS0] disabled
10574 12:19:07.076508 <6>[ 1.056711] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10575 12:19:07.083023 <6>[ 1.066185] printk: console [ttyS0] enabled
10576 12:19:07.086542 <6>[ 1.066185] printk: console [ttyS0] enabled
10577 12:19:07.092797 <6>[ 1.075080] printk: bootconsole [mtk8250] disabled
10578 12:19:07.096474 <6>[ 1.075080] printk: bootconsole [mtk8250] disabled
10579 12:19:07.102679 <6>[ 1.086421] SuperH (H)SCI(F) driver initialized
10580 12:19:07.105691 <6>[ 1.091702] msm_serial: driver initialized
10581 12:19:07.120184 <6>[ 1.100708] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10582 12:19:07.130295 <6>[ 1.109257] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10583 12:19:07.136680 <6>[ 1.117798] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10584 12:19:07.146543 <6>[ 1.126427] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10585 12:19:07.156599 <6>[ 1.135135] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10586 12:19:07.163257 <6>[ 1.143854] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10587 12:19:07.172660 <6>[ 1.152404] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10588 12:19:07.179357 <6>[ 1.161214] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10589 12:19:07.189443 <6>[ 1.169758] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10590 12:19:07.201738 <6>[ 1.185438] loop: module loaded
10591 12:19:07.208286 <6>[ 1.191428] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10592 12:19:07.231203 <4>[ 1.214871] mtk-pmic-keys: Failed to locate of_node [id: -1]
10593 12:19:07.238259 <6>[ 1.221738] megasas: 07.719.03.00-rc1
10594 12:19:07.247345 <6>[ 1.231452] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10595 12:19:07.257968 <6>[ 1.241901] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10596 12:19:07.274981 <6>[ 1.258210] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10597 12:19:07.334687 <6>[ 1.312205] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10598 12:19:07.541243 <6>[ 1.524558] Freeing initrd memory: 17384K
10599 12:19:07.550979 <6>[ 1.534832] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10600 12:19:07.562329 <6>[ 1.545780] tun: Universal TUN/TAP device driver, 1.6
10601 12:19:07.565132 <6>[ 1.551848] thunder_xcv, ver 1.0
10602 12:19:07.568822 <6>[ 1.555356] thunder_bgx, ver 1.0
10603 12:19:07.571856 <6>[ 1.558849] nicpf, ver 1.0
10604 12:19:07.582693 <6>[ 1.562889] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10605 12:19:07.585626 <6>[ 1.570364] hns3: Copyright (c) 2017 Huawei Corporation.
10606 12:19:07.589101 <6>[ 1.575950] hclge is initializing
10607 12:19:07.595556 <6>[ 1.579527] e1000: Intel(R) PRO/1000 Network Driver
10608 12:19:07.602126 <6>[ 1.584657] e1000: Copyright (c) 1999-2006 Intel Corporation.
10609 12:19:07.605807 <6>[ 1.590670] e1000e: Intel(R) PRO/1000 Network Driver
10610 12:19:07.612461 <6>[ 1.595885] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10611 12:19:07.619204 <6>[ 1.602073] igb: Intel(R) Gigabit Ethernet Network Driver
10612 12:19:07.625584 <6>[ 1.607723] igb: Copyright (c) 2007-2014 Intel Corporation.
10613 12:19:07.632080 <6>[ 1.613559] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10614 12:19:07.639316 <6>[ 1.620077] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10615 12:19:07.641904 <6>[ 1.626547] sky2: driver version 1.30
10616 12:19:07.648793 <6>[ 1.631550] VFIO - User Level meta-driver version: 0.3
10617 12:19:07.655819 <6>[ 1.639776] usbcore: registered new interface driver usb-storage
10618 12:19:07.663142 <6>[ 1.646222] usbcore: registered new device driver onboard-usb-hub
10619 12:19:07.671827 <6>[ 1.655352] mt6397-rtc mt6359-rtc: registered as rtc0
10620 12:19:07.681574 <6>[ 1.660812] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-31T12:19:07 UTC (1706703547)
10621 12:19:07.684587 <6>[ 1.670374] i2c_dev: i2c /dev entries driver
10622 12:19:07.701436 <6>[ 1.682100] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10623 12:19:07.721602 <6>[ 1.705124] cpu cpu0: EM: created perf domain
10624 12:19:07.724732 <6>[ 1.710057] cpu cpu4: EM: created perf domain
10625 12:19:07.731584 <6>[ 1.715651] sdhci: Secure Digital Host Controller Interface driver
10626 12:19:07.738681 <6>[ 1.722084] sdhci: Copyright(c) Pierre Ossman
10627 12:19:07.745178 <6>[ 1.727041] Synopsys Designware Multimedia Card Interface Driver
10628 12:19:07.752044 <6>[ 1.733685] sdhci-pltfm: SDHCI platform and OF driver helper
10629 12:19:07.754905 <6>[ 1.733684] mmc0: CQHCI version 5.10
10630 12:19:07.762341 <6>[ 1.743692] ledtrig-cpu: registered to indicate activity on CPUs
10631 12:19:07.768551 <6>[ 1.750707] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10632 12:19:07.774799 <6>[ 1.757758] usbcore: registered new interface driver usbhid
10633 12:19:07.778279 <6>[ 1.763580] usbhid: USB HID core driver
10634 12:19:07.784901 <6>[ 1.767772] spi_master spi0: will run message pump with realtime priority
10635 12:19:07.833926 <6>[ 1.811256] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10636 12:19:07.853067 <6>[ 1.826861] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10637 12:19:07.856340 <6>[ 1.840449] mmc0: Command Queue Engine enabled
10638 12:19:07.862893 <6>[ 1.845205] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10639 12:19:07.869713 <6>[ 1.852149] cros-ec-spi spi0.0: Chrome EC device registered
10640 12:19:07.873188 <6>[ 1.852491] mmcblk0: mmc0:0001 DA4128 116 GiB
10641 12:19:07.883292 <6>[ 1.867131] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10642 12:19:07.890960 <6>[ 1.874682] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10643 12:19:07.897703 <6>[ 1.880614] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10644 12:19:07.904055 <6>[ 1.886581] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10645 12:19:07.913830 <6>[ 1.893542] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10646 12:19:07.920815 <6>[ 1.904374] NET: Registered PF_PACKET protocol family
10647 12:19:07.923862 <6>[ 1.909782] 9pnet: Installing 9P2000 support
10648 12:19:07.930457 <5>[ 1.914350] Key type dns_resolver registered
10649 12:19:07.934065 <6>[ 1.919369] registered taskstats version 1
10650 12:19:07.940620 <5>[ 1.923757] Loading compiled-in X.509 certificates
10651 12:19:07.972446 <4>[ 1.949459] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10652 12:19:07.982427 <4>[ 1.960390] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10653 12:19:07.988536 <3>[ 1.970969] debugfs: File 'uA_load' in directory '/' already present!
10654 12:19:07.995734 <3>[ 1.977684] debugfs: File 'min_uV' in directory '/' already present!
10655 12:19:08.001747 <3>[ 1.984306] debugfs: File 'max_uV' in directory '/' already present!
10656 12:19:08.008570 <3>[ 1.990919] debugfs: File 'constraint_flags' in directory '/' already present!
10657 12:19:08.020208 <3>[ 2.000933] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10658 12:19:08.034927 <6>[ 2.018821] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10659 12:19:08.042212 <6>[ 2.025715] xhci-mtk 11200000.usb: xHCI Host Controller
10660 12:19:08.048217 <6>[ 2.031218] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10661 12:19:08.058273 <6>[ 2.039090] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10662 12:19:08.065147 <6>[ 2.048531] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10663 12:19:08.072110 <6>[ 2.054636] xhci-mtk 11200000.usb: xHCI Host Controller
10664 12:19:08.079083 <6>[ 2.060123] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10665 12:19:08.085571 <6>[ 2.067790] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10666 12:19:08.091875 <6>[ 2.075619] hub 1-0:1.0: USB hub found
10667 12:19:08.094925 <6>[ 2.079656] hub 1-0:1.0: 1 port detected
10668 12:19:08.104824 <6>[ 2.083980] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10669 12:19:08.108561 <6>[ 2.092799] hub 2-0:1.0: USB hub found
10670 12:19:08.111493 <6>[ 2.096843] hub 2-0:1.0: 1 port detected
10671 12:19:08.121137 <6>[ 2.104892] mtk-msdc 11f70000.mmc: Got CD GPIO
10672 12:19:08.134128 <6>[ 2.114325] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10673 12:19:08.140440 <6>[ 2.122357] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10674 12:19:08.150488 <4>[ 2.130277] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10675 12:19:08.161410 <6>[ 2.139845] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10676 12:19:08.167162 <6>[ 2.147922] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10677 12:19:08.173476 <6>[ 2.155939] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10678 12:19:08.183567 <6>[ 2.163869] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10679 12:19:08.190138 <6>[ 2.171688] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10680 12:19:08.199922 <6>[ 2.179506] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10681 12:19:08.209882 <6>[ 2.189933] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10682 12:19:08.216598 <6>[ 2.198335] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10683 12:19:08.226151 <6>[ 2.206688] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10684 12:19:08.232812 <6>[ 2.215029] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10685 12:19:08.242804 <6>[ 2.223368] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10686 12:19:08.252941 <6>[ 2.231707] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10687 12:19:08.259803 <6>[ 2.240045] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10688 12:19:08.269449 <6>[ 2.248384] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10689 12:19:08.276005 <6>[ 2.256727] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10690 12:19:08.285784 <6>[ 2.265068] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10691 12:19:08.291924 <6>[ 2.273407] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10692 12:19:08.301843 <6>[ 2.281745] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10693 12:19:08.308744 <6>[ 2.290083] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10694 12:19:08.318943 <6>[ 2.298421] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10695 12:19:08.325216 <6>[ 2.306760] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10696 12:19:08.331800 <6>[ 2.315499] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10697 12:19:08.338584 <6>[ 2.322667] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10698 12:19:08.345461 <6>[ 2.329432] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10699 12:19:08.355359 <6>[ 2.336185] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10700 12:19:08.361997 <6>[ 2.343117] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10701 12:19:08.368672 <6>[ 2.349960] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10702 12:19:08.378230 <6>[ 2.359088] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10703 12:19:08.388077 <6>[ 2.368206] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10704 12:19:08.398344 <6>[ 2.377501] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10705 12:19:08.408765 <6>[ 2.386966] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10706 12:19:08.417777 <6>[ 2.396433] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10707 12:19:08.424534 <6>[ 2.405552] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10708 12:19:08.435045 <6>[ 2.415018] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10709 12:19:08.444351 <6>[ 2.424136] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10710 12:19:08.453995 <6>[ 2.433429] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10711 12:19:08.464053 <6>[ 2.443589] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10712 12:19:08.474240 <6>[ 2.455053] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10713 12:19:08.480897 <6>[ 2.464932] Trying to probe devices needed for running init ...
10714 12:19:08.525756 <6>[ 2.506783] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10715 12:19:08.680945 <6>[ 2.664830] hub 1-1:1.0: USB hub found
10716 12:19:08.684015 <6>[ 2.669343] hub 1-1:1.0: 4 ports detected
10717 12:19:08.693674 <6>[ 2.677762] hub 1-1:1.0: USB hub found
10718 12:19:08.696803 <6>[ 2.682093] hub 1-1:1.0: 4 ports detected
10719 12:19:08.806138 <6>[ 2.787137] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10720 12:19:08.833088 <6>[ 2.816973] hub 2-1:1.0: USB hub found
10721 12:19:08.836134 <6>[ 2.821504] hub 2-1:1.0: 3 ports detected
10722 12:19:08.845896 <6>[ 2.829587] hub 2-1:1.0: USB hub found
10723 12:19:08.848994 <6>[ 2.834171] hub 2-1:1.0: 3 ports detected
10724 12:19:09.022428 <6>[ 3.002847] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10725 12:19:09.153461 <6>[ 3.137032] hub 1-1.1:1.0: USB hub found
10726 12:19:09.156060 <6>[ 3.141377] hub 1-1.1:1.0: 4 ports detected
10727 12:19:09.269878 <6>[ 3.250936] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10728 12:19:09.402884 <6>[ 3.386687] hub 1-1.4:1.0: USB hub found
10729 12:19:09.405805 <6>[ 3.391342] hub 1-1.4:1.0: 2 ports detected
10730 12:19:09.415214 <6>[ 3.399499] hub 1-1.4:1.0: USB hub found
10731 12:19:09.418596 <6>[ 3.404105] hub 1-1.4:1.0: 2 ports detected
10732 12:19:09.482050 <6>[ 3.462843] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10733 12:19:09.713953 <6>[ 3.694860] usb 1-1.4.1: new high-speed USB device number 6 using xhci-mtk
10734 12:19:09.905901 <6>[ 3.886844] usb 1-1.4.2: new high-speed USB device number 7 using xhci-mtk
10735 12:19:20.779392 <6>[ 14.767813] ALSA device list:
10736 12:19:20.785974 <6>[ 14.771103] No soundcards found.
10737 12:19:20.794040 <6>[ 14.779110] Freeing unused kernel memory: 8448K
10738 12:19:20.797579 <6>[ 14.784126] Run /init as init process
10739 12:19:20.808311 Loading, please wait...
10740 12:19:20.829093 Starting version 247.3-7+deb11u2
10741 12:19:21.049589 <6>[ 15.031102] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10742 12:19:21.059699 <6>[ 15.039573] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10743 12:19:21.065970 <6>[ 15.048434] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10744 12:19:21.079096 <3>[ 15.060721] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 12:19:21.085603 <3>[ 15.069010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 12:19:21.095193 <6>[ 15.070475] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10747 12:19:21.102332 <3>[ 15.077270] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 12:19:21.108778 <4>[ 15.080997] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10749 12:19:21.118361 <4>[ 15.084819] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10750 12:19:21.125336 <3>[ 15.093576] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 12:19:21.131728 <6>[ 15.100454] remoteproc remoteproc0: scp is available
10752 12:19:21.137949 <3>[ 15.107397] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 12:19:21.145212 <6>[ 15.109612] mc: Linux media interface: v0.10
10754 12:19:21.151732 <6>[ 15.113595] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10755 12:19:21.154722 <6>[ 15.115503] remoteproc remoteproc0: powering up scp
10756 12:19:21.164585 <3>[ 15.120814] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 12:19:21.171423 <6>[ 15.128714] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10758 12:19:21.177551 <6>[ 15.128762] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10759 12:19:21.184934 <6>[ 15.129552] usbcore: registered new device driver r8152-cfgselector
10760 12:19:21.191435 <6>[ 15.129589] videodev: Linux video capture interface: v2.00
10761 12:19:21.197510 <3>[ 15.133568] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10762 12:19:21.207786 <4>[ 15.142884] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10763 12:19:21.211748 <4>[ 15.142884] Fallback method does not support PEC.
10764 12:19:21.221902 <3>[ 15.146037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10765 12:19:21.228083 <3>[ 15.171057] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10766 12:19:21.238548 <3>[ 15.174787] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10767 12:19:21.247900 <6>[ 15.175095] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10768 12:19:21.258268 <6>[ 15.175329] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10769 12:19:21.264323 <6>[ 15.180014] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10770 12:19:21.268009 <6>[ 15.180022] pci_bus 0000:00: root bus resource [bus 00-ff]
10771 12:19:21.274201 <6>[ 15.180029] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10772 12:19:21.284189 <6>[ 15.180033] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10773 12:19:21.291157 <6>[ 15.180072] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10774 12:19:21.300583 <6>[ 15.180092] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10775 12:19:21.304350 <6>[ 15.180169] pci 0000:00:00.0: supports D1 D2
10776 12:19:21.310879 <6>[ 15.180172] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10777 12:19:21.320945 <6>[ 15.181854] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10778 12:19:21.327215 <3>[ 15.188590] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 12:19:21.336976 <3>[ 15.202045] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10780 12:19:21.343960 <6>[ 15.202314] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10781 12:19:21.350341 <3>[ 15.210285] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 12:19:21.360010 <3>[ 15.210287] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 12:19:21.366836 <3>[ 15.210321] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 12:19:21.373358 <6>[ 15.219103] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10785 12:19:21.383578 <6>[ 15.219516] r8152-cfgselector 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10786 12:19:21.393085 <6>[ 15.222446] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10787 12:19:21.399633 <3>[ 15.227164] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10788 12:19:21.409729 <3>[ 15.227167] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10789 12:19:21.416478 <6>[ 15.237378] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10790 12:19:21.422657 <3>[ 15.246284] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 12:19:21.433117 <3>[ 15.246289] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 12:19:21.439542 <6>[ 15.253163] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10793 12:19:21.446247 <3>[ 15.258911] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10794 12:19:21.452723 <6>[ 15.266135] pci 0000:01:00.0: supports D1 D2
10795 12:19:21.459223 <6>[ 15.266736] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10796 12:19:21.462528 <6>[ 15.276398] Bluetooth: Core ver 2.22
10797 12:19:21.472526 <6>[ 15.282214] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10798 12:19:21.479091 <6>[ 15.282792] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10799 12:19:21.485939 <6>[ 15.284076] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10800 12:19:21.492209 <6>[ 15.284245] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10801 12:19:21.505410 <6>[ 15.285489] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10802 12:19:21.511668 <6>[ 15.285643] usbcore: registered new interface driver uvcvideo
10803 12:19:21.518419 <6>[ 15.285912] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10804 12:19:21.525269 <6>[ 15.289727] NET: Registered PF_BLUETOOTH protocol family
10805 12:19:21.531626 <6>[ 15.294195] remoteproc remoteproc0: remote processor scp is now up
10806 12:19:21.538314 <6>[ 15.302598] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10807 12:19:21.545068 <6>[ 15.309368] Bluetooth: HCI device and connection manager initialized
10808 12:19:21.551423 <6>[ 15.309388] Bluetooth: HCI socket layer initialized
10809 12:19:21.558496 <6>[ 15.309909] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10810 12:19:21.564535 <6>[ 15.317482] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10811 12:19:21.571624 <6>[ 15.326232] Bluetooth: L2CAP socket layer initialized
10812 12:19:21.574391 <6>[ 15.326240] Bluetooth: SCO socket layer initialized
10813 12:19:21.584550 <4>[ 15.330200] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10814 12:19:21.594511 <4>[ 15.330206] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10815 12:19:21.600805 <6>[ 15.332490] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10816 12:19:21.604518 <6>[ 15.378870] r8152 1-1.1.1:1.0 eth0: v1.12.13
10817 12:19:21.614243 <6>[ 15.381999] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10818 12:19:21.620608 <6>[ 15.382012] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10819 12:19:21.627478 <6>[ 15.390271] usbcore: registered new interface driver r8152
10820 12:19:21.633838 <6>[ 15.398166] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10821 12:19:21.640501 <6>[ 15.398178] pci 0000:00:00.0: PCI bridge to [bus 01]
10822 12:19:21.646979 <6>[ 15.398699] usbcore: registered new interface driver btusb
10823 12:19:21.657053 <4>[ 15.399482] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10824 12:19:21.664054 <3>[ 15.399488] Bluetooth: hci0: Failed to load firmware file (-2)
10825 12:19:21.667050 <3>[ 15.399491] Bluetooth: hci0: Failed to set up firmware (-2)
10826 12:19:21.680509 <4>[ 15.399495] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10827 12:19:21.683591 <6>[ 15.437584] usbcore: registered new interface driver cdc_ether
10828 12:19:21.693419 <6>[ 15.441863] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10829 12:19:21.700107 <6>[ 15.442072] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10830 12:19:21.706760 <6>[ 15.452988] usbcore: registered new interface driver r8153_ecm
10831 12:19:21.710007 <6>[ 15.461727] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10832 12:19:21.716935 <6>[ 15.497763] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10833 12:19:21.723070 <6>[ 15.502223] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10834 12:19:21.754889 <5>[ 15.737222] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10835 12:19:21.774520 <5>[ 15.756770] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10836 12:19:21.781422 <5>[ 15.764739] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10837 12:19:21.791173 <4>[ 15.773235] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10838 12:19:21.797642 <6>[ 15.782156] cfg80211: failed to load regulatory.db
10839 12:19:21.854844 <6>[ 15.836749] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10840 12:19:21.861133 <6>[ 15.844416] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10841 12:19:21.885946 <6>[ 15.871269] mt7921e 0000:01:00.0: ASIC revision: 79610010
10842 12:19:21.987904 <6>[ 15.970237] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10843 12:19:21.991802 <6>[ 15.970237]
10844 12:19:21.998502 Begin: Loading essential drivers ... done.
10845 12:19:22.001771 Begin: Running /scripts/init-premount ... done.
10846 12:19:22.008414 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10847 12:19:22.018495 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10848 12:19:22.021550 Device /sys/class/net/enxf4f5e850de0a found
10849 12:19:22.021982 done.
10850 12:19:22.076965 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10851 12:19:22.255312 <6>[ 16.236956] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10852 12:19:23.008525 <6>[ 16.993467] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10853 12:19:23.100505 <6>[ 17.085906] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10854 12:19:23.175408 IP-Config: no response after 2 secs - giving up
10855 12:19:23.220812 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10856 12:19:23.233553 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:47 mtu 1500 DHCP
10857 12:19:23.951907 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10858 12:19:23.957986 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10859 12:19:23.968192 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10860 12:19:23.974628 host : mt8192-asurada-spherion-r0-cbg-9
10861 12:19:23.981001 domain : lava-rack
10862 12:19:23.984118 rootserver: 192.168.201.1 rootpath:
10863 12:19:23.984534 filename :
10864 12:19:24.106741 done.
10865 12:19:24.114682 Begin: Running /scripts/nfs-bottom ... done.
10866 12:19:24.135265 Begin: Running /scripts/init-bottom ... done.
10867 12:19:25.295291 <6>[ 19.281187] NET: Registered PF_INET6 protocol family
10868 12:19:25.302822 <6>[ 19.288943] Segment Routing with IPv6
10869 12:19:25.306518 <6>[ 19.292939] In-situ OAM (IOAM) with IPv6
10870 12:19:25.443807 <30>[ 19.409982] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10871 12:19:25.447004 <30>[ 19.434377] systemd[1]: Detected architecture arm64.
10872 12:19:25.467574
10873 12:19:25.471243 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10874 12:19:25.471346
10875 12:19:25.487318 <30>[ 19.472866] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10876 12:19:26.222345 <30>[ 20.204909] systemd[1]: Queued start job for default target Graphical Interface.
10877 12:19:26.255751 <30>[ 20.241204] systemd[1]: Created slice system-getty.slice.
10878 12:19:26.262010 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10879 12:19:26.278748 <30>[ 20.264221] systemd[1]: Created slice system-modprobe.slice.
10880 12:19:26.285157 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10881 12:19:26.302818 <30>[ 20.288039] systemd[1]: Created slice system-serial\x2dgetty.slice.
10882 12:19:26.312556 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10883 12:19:26.326155 <30>[ 20.311870] systemd[1]: Created slice User and Session Slice.
10884 12:19:26.332742 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10885 12:19:26.353272 <30>[ 20.335668] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10886 12:19:26.363076 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10887 12:19:26.381414 <30>[ 20.363589] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10888 12:19:26.388354 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10889 12:19:26.412155 <30>[ 20.390986] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10890 12:19:26.418746 <30>[ 20.403132] systemd[1]: Reached target Local Encrypted Volumes.
10891 12:19:26.425021 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10892 12:19:26.441914 <30>[ 20.427401] systemd[1]: Reached target Paths.
10893 12:19:26.448188 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10894 12:19:26.461203 <30>[ 20.446813] systemd[1]: Reached target Remote File Systems.
10895 12:19:26.467763 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10896 12:19:26.485989 <30>[ 20.471192] systemd[1]: Reached target Slices.
10897 12:19:26.491741 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10898 12:19:26.505220 <30>[ 20.490834] systemd[1]: Reached target Swap.
10899 12:19:26.508317 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10900 12:19:26.529138 <30>[ 20.511320] systemd[1]: Listening on initctl Compatibility Named Pipe.
10901 12:19:26.535600 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10902 12:19:26.542388 <30>[ 20.527455] systemd[1]: Listening on Journal Audit Socket.
10903 12:19:26.548998 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10904 12:19:26.566477 <30>[ 20.552134] systemd[1]: Listening on Journal Socket (/dev/log).
10905 12:19:26.573480 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10906 12:19:26.589694 <30>[ 20.575399] systemd[1]: Listening on Journal Socket.
10907 12:19:26.596170 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10908 12:19:26.613881 <30>[ 20.596283] systemd[1]: Listening on Network Service Netlink Socket.
10909 12:19:26.620782 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10910 12:19:26.636171 <30>[ 20.621515] systemd[1]: Listening on udev Control Socket.
10911 12:19:26.642281 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10912 12:19:26.657554 <30>[ 20.643253] systemd[1]: Listening on udev Kernel Socket.
10913 12:19:26.663851 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10914 12:19:26.704721 <30>[ 20.690882] systemd[1]: Mounting Huge Pages File System...
10915 12:19:26.711572 Mounting [0;1;39mHuge Pages File System[0m...
10916 12:19:26.729237 <30>[ 20.715216] systemd[1]: Mounting POSIX Message Queue File System...
10917 12:19:26.736115 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10918 12:19:26.780791 <30>[ 20.766949] systemd[1]: Mounting Kernel Debug File System...
10919 12:19:26.788001 Mounting [0;1;39mKernel Debug File System[0m...
10920 12:19:26.808783 <30>[ 20.791431] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10921 12:19:26.822003 <30>[ 20.804744] systemd[1]: Starting Create list of static device nodes for the current kernel...
10922 12:19:26.828639 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10923 12:19:26.849935 <30>[ 20.835837] systemd[1]: Starting Load Kernel Module configfs...
10924 12:19:26.856515 Starting [0;1;39mLoad Kernel Module configfs[0m...
10925 12:19:26.877752 <30>[ 20.863507] systemd[1]: Starting Load Kernel Module drm...
10926 12:19:26.883994 Starting [0;1;39mLoad Kernel Module drm[0m...
10927 12:19:26.901429 <30>[ 20.887667] systemd[1]: Starting Load Kernel Module fuse...
10928 12:19:26.908168 Starting [0;1;39mLoad Kernel Module fuse[0m...
10929 12:19:26.937066 <6>[ 20.922845] fuse: init (API version 7.37)
10930 12:19:26.946396 <30>[ 20.923640] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10931 12:19:26.973612 <30>[ 20.959609] systemd[1]: Starting Journal Service...
10932 12:19:26.980276 Starting [0;1;39mJournal Service[0m...
10933 12:19:27.001784 <30>[ 20.987957] systemd[1]: Starting Load Kernel Modules...
10934 12:19:27.008315 Starting [0;1;39mLoad Kernel Modules[0m...
10935 12:19:27.029931 <30>[ 21.012499] systemd[1]: Starting Remount Root and Kernel File Systems...
10936 12:19:27.036933 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10937 12:19:27.054554 <30>[ 21.040633] systemd[1]: Starting Coldplug All udev Devices...
10938 12:19:27.061287 Starting [0;1;39mColdplug All udev Devices[0m...
10939 12:19:27.080499 <30>[ 21.066229] systemd[1]: Mounted Huge Pages File System.
10940 12:19:27.086751 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10941 12:19:27.100362 <3>[ 21.083038] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 12:19:27.107053 <30>[ 21.092450] systemd[1]: Mounted POSIX Message Queue File System.
10943 12:19:27.113468 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10944 12:19:27.129338 <30>[ 21.115026] systemd[1]: Mounted Kernel Debug File System.
10945 12:19:27.139512 <3>[ 21.119077] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 12:19:27.145666 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10947 12:19:27.164610 <30>[ 21.147526] systemd[1]: Finished Create list of static device nodes for the current kernel.
10948 12:19:27.175409 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10949 12:19:27.185222 <3>[ 21.167454] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 12:19:27.191776 <30>[ 21.177301] systemd[1]: modprobe@configfs.service: Succeeded.
10951 12:19:27.198862 <30>[ 21.183820] systemd[1]: Finished Load Kernel Module configfs.
10952 12:19:27.205542 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10953 12:19:27.216378 <3>[ 21.199536] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 12:19:27.223414 <30>[ 21.209459] systemd[1]: modprobe@drm.service: Succeeded.
10955 12:19:27.230545 <30>[ 21.216174] systemd[1]: Finished Load Kernel Module drm.
10956 12:19:27.236643 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10957 12:19:27.243619 <30>[ 21.229593] systemd[1]: modprobe@fuse.service: Succeeded.
10958 12:19:27.253659 <3>[ 21.232056] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 12:19:27.260085 <30>[ 21.236088] systemd[1]: Finished Load Kernel Module fuse.
10960 12:19:27.266547 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10961 12:19:27.286226 <3>[ 21.268810] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 12:19:27.293194 <30>[ 21.268915] systemd[1]: Finished Load Kernel Modules.
10963 12:19:27.298993 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10964 12:19:27.317123 <30>[ 21.299869] systemd[1]: Finished Remount Root and Kernel File Systems.
10965 12:19:27.323521 <3>[ 21.303497] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 12:19:27.330675 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10967 12:19:27.357426 <3>[ 21.340422] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10968 12:19:27.378846 <30>[ 21.364184] systemd[1]: Mounting FUSE Control File System...
10969 12:19:27.393124 Mounting [0;1;39mFUSE <3>[ 21.372657] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 12:19:27.393262 Control File System[0m...
10971 12:19:27.411930 <30>[ 21.397515] systemd[1]: Mounting Kernel Configuration File System...
10972 12:19:27.422272 <3>[ 21.403476] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 12:19:27.428783 Mounting [0;1;39mKernel Configuration File System[0m...
10974 12:19:27.452829 <30>[ 21.435426] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10975 12:19:27.462435 <30>[ 21.444510] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10976 12:19:27.472011 <30>[ 21.457791] systemd[1]: Starting Load/Save Random Seed...
10977 12:19:27.479052 Starting [0;1;39mLoad/Save Random Seed[0m...
10978 12:19:27.496813 <30>[ 21.482570] systemd[1]: Starting Apply Kernel Variables...
10979 12:19:27.503307 Starting [0;1;39mApply Kernel Variables[0m...
10980 12:19:27.521817 <30>[ 21.507133] systemd[1]: Starting Create System Users...
10981 12:19:27.538221 <4>[ 21.511492] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10982 12:19:27.544666 <3>[ 21.528459] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10983 12:19:27.551256 Starting [0;1;39mCreate System Users[0m...
10984 12:19:27.566522 <30>[ 21.552330] systemd[1]: Started Journal Service.
10985 12:19:27.573411 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10986 12:19:27.593367 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10987 12:19:27.608906 See 'systemctl status systemd-udev-trigger.service' for details.
10988 12:19:27.630357 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10989 12:19:27.649297 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10990 12:19:27.666724 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10991 12:19:27.682617 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10992 12:19:27.698503 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10993 12:19:27.741764 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10994 12:19:27.759351 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10995 12:19:27.787277 <46>[ 21.769723] systemd-journald[292]: Received client request to flush runtime journal.
10996 12:19:27.821703 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10997 12:19:27.833459 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10998 12:19:27.848910 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10999 12:19:27.897301 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11000 12:19:29.185469 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11001 12:19:29.225666 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11002 12:19:29.250022 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11003 12:19:29.274669 Starting [0;1;39mNetwork Service[0m...
11004 12:19:29.564145 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11005 12:19:29.581915 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11006 12:19:29.628902 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11007 12:19:29.902460 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11008 12:19:29.920456 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11009 12:19:29.957801 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11010 12:19:29.996262 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11011 12:19:30.016970 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11012 12:19:30.049870 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11013 12:19:30.069644 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11014 12:19:30.118007 Starting [0;1;39mNetwork Name Resolution[0m...
11015 12:19:30.146234 Starting [0;1;39mNetwork Time Synchronization[0m...
11016 12:19:30.171079 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11017 12:19:30.223543 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11018 12:19:30.338158 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11019 12:19:30.353401 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11020 12:19:30.372276 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11021 12:19:30.385288 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11022 12:19:30.401007 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11023 12:19:30.552054 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11024 12:19:30.594662 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11025 12:19:30.617649 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11026 12:19:30.644057 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11027 12:19:30.646944 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11028 12:19:30.669951 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11029 12:19:30.680904 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11030 12:19:30.696327 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11031 12:19:30.733194 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11032 12:19:30.786540 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11033 12:19:30.882522 Starting [0;1;39mUser Login Management[0m...
11034 12:19:30.899315 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11035 12:19:30.917477 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11036 12:19:30.937032 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11037 12:19:30.982272 Starting [0;1;39mPermit User Sessions[0m...
11038 12:19:31.114696 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11039 12:19:31.137183 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11040 12:19:31.174835 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11041 12:19:31.220705 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11042 12:19:31.240083 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11043 12:19:31.258983 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11044 12:19:31.277677 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11045 12:19:31.294886 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11046 12:19:31.346472 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11047 12:19:31.386052 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11048 12:19:31.471468
11049 12:19:31.471977
11050 12:19:31.475003 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11051 12:19:31.475366
11052 12:19:31.478343 debian-bullseye-arm64 login: root (automatic login)
11053 12:19:31.478824
11054 12:19:31.479155
11055 12:19:31.803044 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024 aarch64
11056 12:19:31.803166
11057 12:19:31.809408 The programs included with the Debian GNU/Linux system are free software;
11058 12:19:31.816096 the exact distribution terms for each program are described in the
11059 12:19:31.819541 individual files in /usr/share/doc/*/copyright.
11060 12:19:31.819642
11061 12:19:31.825685 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11062 12:19:31.828901 permitted by applicable law.
11063 12:19:32.792809 Matched prompt #10: / #
11065 12:19:32.793374 Setting prompt string to ['/ #']
11066 12:19:32.793539 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11068 12:19:32.793958 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11069 12:19:32.794117 start: 2.2.6 expect-shell-connection (timeout 00:03:38) [common]
11070 12:19:32.794292 Setting prompt string to ['/ #']
11071 12:19:32.794414 Forcing a shell prompt, looking for ['/ #']
11073 12:19:32.844736 / #
11074 12:19:32.844965 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11075 12:19:32.845113 Waiting using forced prompt support (timeout 00:02:30)
11076 12:19:32.849418
11077 12:19:32.849776 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11078 12:19:32.849936 start: 2.2.7 export-device-env (timeout 00:03:38) [common]
11080 12:19:32.950417 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12669567/extract-nfsrootfs-2wdmky1e'
11081 12:19:32.956283 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12669567/extract-nfsrootfs-2wdmky1e'
11083 12:19:33.057001 / # export NFS_SERVER_IP='192.168.201.1'
11084 12:19:33.062284 export NFS_SERVER_IP='192.168.201.1'
11085 12:19:33.062812 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11086 12:19:33.063080 end: 2.2 depthcharge-retry (duration 00:01:22) [common]
11087 12:19:33.063354 end: 2 depthcharge-action (duration 00:01:22) [common]
11088 12:19:33.063607 start: 3 lava-test-retry (timeout 00:07:56) [common]
11089 12:19:33.063895 start: 3.1 lava-test-shell (timeout 00:07:56) [common]
11090 12:19:33.064106 Using namespace: common
11092 12:19:33.164834 / # #
11093 12:19:33.165503 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11094 12:19:33.171543 #
11095 12:19:33.172315 Using /lava-12669567
11097 12:19:33.273416 / # export SHELL=/bin/bash
11098 12:19:33.279663 export SHELL=/bin/bash
11100 12:19:33.381082 / # . /lava-12669567/environment
11101 12:19:33.386822 . /lava-12669567/environment
11103 12:19:33.493920 / # /lava-12669567/bin/lava-test-runner /lava-12669567/0
11104 12:19:33.494298 Test shell timeout: 10s (minimum of the action and connection timeout)
11105 12:19:33.499772 /lava-12669567/bin/lava-test-runner /lava-12669567/0
11106 12:19:33.742995 + export TESTRUN_ID=0_timesync-off
11107 12:19:33.745855 + TESTRUN_ID=0_timesync-off
11108 12:19:33.749075 + cd /lava-12669567/0/tests/0_timesync-off
11109 12:19:33.752654 ++ cat uuid
11110 12:19:33.752727 + UUID=12669567_1.6.2.3.1
11111 12:19:33.756103 + set +x
11112 12:19:33.759135 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12669567_1.6.2.3.1>
11113 12:19:33.759381 Received signal: <STARTRUN> 0_timesync-off 12669567_1.6.2.3.1
11114 12:19:33.759454 Starting test lava.0_timesync-off (12669567_1.6.2.3.1)
11115 12:19:33.759536 Skipping test definition patterns.
11116 12:19:33.762971 + systemctl stop systemd-timesyncd
11117 12:19:33.820225 + set +x
11118 12:19:33.823835 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12669567_1.6.2.3.1>
11119 12:19:33.824095 Received signal: <ENDRUN> 0_timesync-off 12669567_1.6.2.3.1
11120 12:19:33.824183 Ending use of test pattern.
11121 12:19:33.824249 Ending test lava.0_timesync-off (12669567_1.6.2.3.1), duration 0.06
11123 12:19:33.880627 + export TESTRUN_ID=1_kselftest-dt
11124 12:19:33.884145 + TESTRUN_ID=1_kselftest-dt
11125 12:19:33.887425 + cd /lava-12669567/0/tests/1_kselftest-dt
11126 12:19:33.890625 ++ cat uuid
11127 12:19:33.890700 + UUID=12669567_1.6.2.3.5
11128 12:19:33.893915 + set +x
11129 12:19:33.897122 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 12669567_1.6.2.3.5>
11130 12:19:33.897395 Received signal: <STARTRUN> 1_kselftest-dt 12669567_1.6.2.3.5
11131 12:19:33.897489 Starting test lava.1_kselftest-dt (12669567_1.6.2.3.5)
11132 12:19:33.897603 Skipping test definition patterns.
11133 12:19:33.900239 + cd ./automated/linux/kselftest/
11134 12:19:33.930118 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11135 12:19:33.954312 INFO: install_deps skipped
11136 12:19:34.069929 --2024-01-31 12:19:33-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11137 12:19:34.076349 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11138 12:19:34.203008 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11139 12:19:34.335253 HTTP request sent, awaiting response... 200 OK
11140 12:19:34.338545 Length: 2966336 (2.8M) [application/octet-stream]
11141 12:19:34.341941 Saving to: 'kselftest.tar.xz'
11142 12:19:34.342348
11143 12:19:34.342800
11144 12:19:34.599493 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11145 12:19:34.866731 kselftest.tar.xz 1%[ ] 47.81K 180KB/s
11146 12:19:35.210856 kselftest.tar.xz 7%[> ] 218.91K 408KB/s
11147 12:19:35.528203 kselftest.tar.xz 25%[====> ] 746.35K 843KB/s
11148 12:19:35.615422 kselftest.tar.xz 47%[========> ] 1.34M 1.11MB/s
11149 12:19:35.622145 kselftest.tar.xz 100%[===================>] 2.83M 2.18MB/s in 1.3s
11150 12:19:35.622547
11151 12:19:35.878508 2024-01-31 12:19:35 (2.18 MB/s) - 'kselftest.tar.xz' saved [2966336/2966336]
11152 12:19:35.878634
11153 12:19:41.211882 skiplist:
11154 12:19:41.214690 ========================================
11155 12:19:41.218204 ========================================
11156 12:19:41.268904 ============== Tests to run ===============
11157 12:19:41.271994 ===========End Tests to run ===============
11158 12:19:41.275465 shardfile-dt fail
11159 12:19:41.297669 ./kselftest.sh: 131: cannot open /lava-12669567/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11160 12:19:41.301069 + ../../utils/send-to-lava.sh ./output/result.txt
11161 12:19:41.358139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11162 12:19:41.358273 + set +x
11163 12:19:41.358515 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11165 12:19:41.364688 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 12669567_1.6.2.3.5>
11166 12:19:41.364938 Received signal: <ENDRUN> 1_kselftest-dt 12669567_1.6.2.3.5
11167 12:19:41.365013 Ending use of test pattern.
11168 12:19:41.365073 Ending test lava.1_kselftest-dt (12669567_1.6.2.3.5), duration 7.47
11170 12:19:41.365282 ok: lava_test_shell seems to have completed
11171 12:19:41.365370 shardfile-dt: fail
11172 12:19:41.365453 end: 3.1 lava-test-shell (duration 00:00:08) [common]
11173 12:19:41.365535 end: 3 lava-test-retry (duration 00:00:08) [common]
11174 12:19:41.365619 start: 4 finalize (timeout 00:07:48) [common]
11175 12:19:41.365720 start: 4.1 power-off (timeout 00:00:30) [common]
11176 12:19:41.365874 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11177 12:19:41.443714 >> Command sent successfully.
11178 12:19:41.448758 Returned 0 in 0 seconds
11179 12:19:41.549697 end: 4.1 power-off (duration 00:00:00) [common]
11181 12:19:41.551257 start: 4.2 read-feedback (timeout 00:07:48) [common]
11183 12:19:41.553540 Listened to connection for namespace 'common' for up to 1s
11184 12:19:42.553002 Finalising connection for namespace 'common'
11185 12:19:42.553166 Disconnecting from shell: Finalise
11186 12:19:42.553248 / #
11187 12:19:42.653560 end: 4.2 read-feedback (duration 00:00:01) [common]
11188 12:19:42.653732 end: 4 finalize (duration 00:00:01) [common]
11189 12:19:42.653843 Cleaning after the job
11190 12:19:42.653947 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/ramdisk
11191 12:19:42.656944 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/kernel
11192 12:19:42.669901 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/dtb
11193 12:19:42.670101 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/nfsrootfs
11194 12:19:42.760032 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669567/tftp-deploy-ox3fcnsu/modules
11195 12:19:42.767320 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12669567
11196 12:19:43.412170 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12669567
11197 12:19:43.412363 Job finished correctly