Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 38
1 12:13:58.705291 lava-dispatcher, installed at version: 2023.10
2 12:13:58.705501 start: 0 validate
3 12:13:58.705639 Start time: 2024-01-31 12:13:58.705631+00:00 (UTC)
4 12:13:58.705766 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:13:58.705912 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:13:58.973206 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:13:58.973504 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:13:59.240538 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:13:59.241320 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:13:59.510716 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:13:59.511496 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:13:59.780022 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:13:59.780918 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:14:00.057368 validate duration: 1.35
16 12:14:00.058722 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:14:00.059214 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:14:00.059661 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:14:00.060205 Not decompressing ramdisk as can be used compressed.
20 12:14:00.060624 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/initrd.cpio.gz
21 12:14:00.061015 saving as /var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/ramdisk/initrd.cpio.gz
22 12:14:00.061351 total size: 4665398 (4 MB)
23 12:14:00.066805 progress 0 % (0 MB)
24 12:14:00.074588 progress 5 % (0 MB)
25 12:14:00.080276 progress 10 % (0 MB)
26 12:14:00.084397 progress 15 % (0 MB)
27 12:14:00.087864 progress 20 % (0 MB)
28 12:14:00.090798 progress 25 % (1 MB)
29 12:14:00.093531 progress 30 % (1 MB)
30 12:14:00.095820 progress 35 % (1 MB)
31 12:14:00.098086 progress 40 % (1 MB)
32 12:14:00.100445 progress 45 % (2 MB)
33 12:14:00.102400 progress 50 % (2 MB)
34 12:14:00.104226 progress 55 % (2 MB)
35 12:14:00.106174 progress 60 % (2 MB)
36 12:14:00.107961 progress 65 % (2 MB)
37 12:14:00.109600 progress 70 % (3 MB)
38 12:14:00.111218 progress 75 % (3 MB)
39 12:14:00.112769 progress 80 % (3 MB)
40 12:14:00.114411 progress 85 % (3 MB)
41 12:14:00.115860 progress 90 % (4 MB)
42 12:14:00.117306 progress 95 % (4 MB)
43 12:14:00.118657 progress 100 % (4 MB)
44 12:14:00.118847 4 MB downloaded in 0.06 s (77.36 MB/s)
45 12:14:00.119049 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:14:00.119437 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:14:00.119558 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:14:00.119672 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:14:00.119827 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:14:00.119929 saving as /var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/kernel/Image
52 12:14:00.120019 total size: 51532288 (49 MB)
53 12:14:00.120092 No compression specified
54 12:14:00.121643 progress 0 % (0 MB)
55 12:14:00.135777 progress 5 % (2 MB)
56 12:14:00.150060 progress 10 % (4 MB)
57 12:14:00.163942 progress 15 % (7 MB)
58 12:14:00.178087 progress 20 % (9 MB)
59 12:14:00.191966 progress 25 % (12 MB)
60 12:14:00.205822 progress 30 % (14 MB)
61 12:14:00.219920 progress 35 % (17 MB)
62 12:14:00.234245 progress 40 % (19 MB)
63 12:14:00.248322 progress 45 % (22 MB)
64 12:14:00.262595 progress 50 % (24 MB)
65 12:14:00.276517 progress 55 % (27 MB)
66 12:14:00.290514 progress 60 % (29 MB)
67 12:14:00.304415 progress 65 % (31 MB)
68 12:14:00.318286 progress 70 % (34 MB)
69 12:14:00.332313 progress 75 % (36 MB)
70 12:14:00.345824 progress 80 % (39 MB)
71 12:14:00.359017 progress 85 % (41 MB)
72 12:14:00.372567 progress 90 % (44 MB)
73 12:14:00.385864 progress 95 % (46 MB)
74 12:14:00.398718 progress 100 % (49 MB)
75 12:14:00.398923 49 MB downloaded in 0.28 s (176.21 MB/s)
76 12:14:00.399072 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:14:00.399299 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:14:00.399387 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:14:00.399471 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:14:00.399608 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:14:00.399682 saving as /var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/dtb/mt8192-asurada-spherion-r0.dtb
83 12:14:00.399742 total size: 47278 (0 MB)
84 12:14:00.399801 No compression specified
85 12:14:00.400907 progress 69 % (0 MB)
86 12:14:00.401178 progress 100 % (0 MB)
87 12:14:00.401334 0 MB downloaded in 0.00 s (28.36 MB/s)
88 12:14:00.401453 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:14:00.401671 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:14:00.401762 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:14:00.401843 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:14:00.401952 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/full.rootfs.tar.xz
94 12:14:00.402017 saving as /var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/nfsrootfs/full.rootfs.tar
95 12:14:00.402075 total size: 89451516 (85 MB)
96 12:14:00.402135 Using unxz to decompress xz
97 12:14:00.406315 progress 0 % (0 MB)
98 12:14:00.613814 progress 5 % (4 MB)
99 12:14:00.828304 progress 10 % (8 MB)
100 12:14:01.078680 progress 15 % (12 MB)
101 12:14:01.270051 progress 20 % (17 MB)
102 12:14:01.364535 progress 25 % (21 MB)
103 12:14:01.607183 progress 30 % (25 MB)
104 12:14:01.888093 progress 35 % (29 MB)
105 12:14:02.147541 progress 40 % (34 MB)
106 12:14:02.408939 progress 45 % (38 MB)
107 12:14:02.653203 progress 50 % (42 MB)
108 12:14:02.912847 progress 55 % (46 MB)
109 12:14:03.162212 progress 60 % (51 MB)
110 12:14:03.425779 progress 65 % (55 MB)
111 12:14:03.717021 progress 70 % (59 MB)
112 12:14:04.013494 progress 75 % (64 MB)
113 12:14:04.305669 progress 80 % (68 MB)
114 12:14:04.559983 progress 85 % (72 MB)
115 12:14:04.783360 progress 90 % (76 MB)
116 12:14:05.037666 progress 95 % (81 MB)
117 12:14:05.297859 progress 100 % (85 MB)
118 12:14:05.303947 85 MB downloaded in 4.90 s (17.40 MB/s)
119 12:14:05.304206 end: 1.4.1 http-download (duration 00:00:05) [common]
121 12:14:05.304473 end: 1.4 download-retry (duration 00:00:05) [common]
122 12:14:05.304565 start: 1.5 download-retry (timeout 00:09:55) [common]
123 12:14:05.304671 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 12:14:05.304855 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:14:05.304929 saving as /var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/modules/modules.tar
126 12:14:05.304991 total size: 8639916 (8 MB)
127 12:14:05.305053 Using unxz to decompress xz
128 12:14:05.309489 progress 0 % (0 MB)
129 12:14:05.330531 progress 5 % (0 MB)
130 12:14:05.354047 progress 10 % (0 MB)
131 12:14:05.377554 progress 15 % (1 MB)
132 12:14:05.400678 progress 20 % (1 MB)
133 12:14:05.424470 progress 25 % (2 MB)
134 12:14:05.452025 progress 30 % (2 MB)
135 12:14:05.476216 progress 35 % (2 MB)
136 12:14:05.499347 progress 40 % (3 MB)
137 12:14:05.523362 progress 45 % (3 MB)
138 12:14:05.548655 progress 50 % (4 MB)
139 12:14:05.574689 progress 55 % (4 MB)
140 12:14:05.599370 progress 60 % (4 MB)
141 12:14:05.624628 progress 65 % (5 MB)
142 12:14:05.649644 progress 70 % (5 MB)
143 12:14:05.673003 progress 75 % (6 MB)
144 12:14:05.700095 progress 80 % (6 MB)
145 12:14:05.727405 progress 85 % (7 MB)
146 12:14:05.752299 progress 90 % (7 MB)
147 12:14:05.781762 progress 95 % (7 MB)
148 12:14:05.809616 progress 100 % (8 MB)
149 12:14:05.815445 8 MB downloaded in 0.51 s (16.14 MB/s)
150 12:14:05.815693 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:14:05.815959 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:14:05.816055 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 12:14:05.816148 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 12:14:07.548058 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12669512/extract-nfsrootfs-zak5hcs0
156 12:14:07.548263 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 12:14:07.548370 start: 1.6.2 lava-overlay (timeout 00:09:53) [common]
158 12:14:07.548529 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1
159 12:14:07.548660 makedir: /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin
160 12:14:07.548802 makedir: /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/tests
161 12:14:07.548907 makedir: /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/results
162 12:14:07.549008 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-add-keys
163 12:14:07.549151 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-add-sources
164 12:14:07.549283 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-background-process-start
165 12:14:07.549412 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-background-process-stop
166 12:14:07.549541 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-common-functions
167 12:14:07.549667 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-echo-ipv4
168 12:14:07.549793 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-install-packages
169 12:14:07.549919 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-installed-packages
170 12:14:07.550044 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-os-build
171 12:14:07.550170 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-probe-channel
172 12:14:07.550295 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-probe-ip
173 12:14:07.550421 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-target-ip
174 12:14:07.550546 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-target-mac
175 12:14:07.550673 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-target-storage
176 12:14:07.550802 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-test-case
177 12:14:07.550931 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-test-event
178 12:14:07.551057 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-test-feedback
179 12:14:07.551183 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-test-raise
180 12:14:07.551310 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-test-reference
181 12:14:07.551437 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-test-runner
182 12:14:07.551562 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-test-set
183 12:14:07.551687 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-test-shell
184 12:14:07.551814 Updating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-install-packages (oe)
185 12:14:07.551968 Updating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/bin/lava-installed-packages (oe)
186 12:14:07.552092 Creating /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/environment
187 12:14:07.552188 LAVA metadata
188 12:14:07.552259 - LAVA_JOB_ID=12669512
189 12:14:07.552321 - LAVA_DISPATCHER_IP=192.168.201.1
190 12:14:07.552420 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:53) [common]
191 12:14:07.552487 skipped lava-vland-overlay
192 12:14:07.552561 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 12:14:07.552639 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:53) [common]
194 12:14:07.552699 skipped lava-multinode-overlay
195 12:14:07.552814 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 12:14:07.552893 start: 1.6.2.3 test-definition (timeout 00:09:53) [common]
197 12:14:07.552965 Loading test definitions
198 12:14:07.553053 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:53) [common]
199 12:14:07.553126 Using /lava-12669512 at stage 0
200 12:14:07.553426 uuid=12669512_1.6.2.3.1 testdef=None
201 12:14:07.553515 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 12:14:07.553599 start: 1.6.2.3.2 test-overlay (timeout 00:09:53) [common]
203 12:14:07.554088 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 12:14:07.554308 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:53) [common]
206 12:14:07.554902 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 12:14:07.555129 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:53) [common]
209 12:14:07.556228 runner path: /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/0/tests/0_lc-compliance test_uuid 12669512_1.6.2.3.1
210 12:14:07.556381 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 12:14:07.556587 Creating lava-test-runner.conf files
213 12:14:07.556650 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12669512/lava-overlay-ys8w1aq1/lava-12669512/0 for stage 0
214 12:14:07.556772 - 0_lc-compliance
215 12:14:07.556884 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 12:14:07.556970 start: 1.6.2.4 compress-overlay (timeout 00:09:53) [common]
217 12:14:07.562949 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 12:14:07.563050 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
219 12:14:07.563134 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 12:14:07.563218 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 12:14:07.563302 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
222 12:14:07.683488 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 12:14:07.683892 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 12:14:07.684012 extracting modules file /var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669512/extract-nfsrootfs-zak5hcs0
225 12:14:07.908201 extracting modules file /var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669512/extract-overlay-ramdisk-wkmkea5g/ramdisk
226 12:14:08.135921 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 12:14:08.136097 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 12:14:08.136221 [common] Applying overlay to NFS
229 12:14:08.136297 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669512/compress-overlay-slijwlod/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12669512/extract-nfsrootfs-zak5hcs0
230 12:14:08.142907 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 12:14:08.143021 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 12:14:08.143112 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 12:14:08.143201 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 12:14:08.143277 Building ramdisk /var/lib/lava/dispatcher/tmp/12669512/extract-overlay-ramdisk-wkmkea5g/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12669512/extract-overlay-ramdisk-wkmkea5g/ramdisk
235 12:14:08.481542 >> 119414 blocks
236 12:14:10.446648 rename /var/lib/lava/dispatcher/tmp/12669512/extract-overlay-ramdisk-wkmkea5g/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/ramdisk/ramdisk.cpio.gz
237 12:14:10.447109 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 12:14:10.447233 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 12:14:10.447331 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 12:14:10.447437 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/kernel/Image'
241 12:14:22.707925 Returned 0 in 12 seconds
242 12:14:22.808993 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/kernel/image.itb
243 12:14:23.180574 output: FIT description: Kernel Image image with one or more FDT blobs
244 12:14:23.180998 output: Created: Wed Jan 31 12:14:23 2024
245 12:14:23.181078 output: Image 0 (kernel-1)
246 12:14:23.181143 output: Description:
247 12:14:23.181207 output: Created: Wed Jan 31 12:14:23 2024
248 12:14:23.181271 output: Type: Kernel Image
249 12:14:23.181332 output: Compression: lzma compressed
250 12:14:23.181391 output: Data Size: 12047284 Bytes = 11764.93 KiB = 11.49 MiB
251 12:14:23.181450 output: Architecture: AArch64
252 12:14:23.181507 output: OS: Linux
253 12:14:23.181565 output: Load Address: 0x00000000
254 12:14:23.181621 output: Entry Point: 0x00000000
255 12:14:23.181677 output: Hash algo: crc32
256 12:14:23.181734 output: Hash value: 5a47eb78
257 12:14:23.181789 output: Image 1 (fdt-1)
258 12:14:23.181848 output: Description: mt8192-asurada-spherion-r0
259 12:14:23.181901 output: Created: Wed Jan 31 12:14:23 2024
260 12:14:23.181954 output: Type: Flat Device Tree
261 12:14:23.182007 output: Compression: uncompressed
262 12:14:23.182060 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
263 12:14:23.182113 output: Architecture: AArch64
264 12:14:23.182165 output: Hash algo: crc32
265 12:14:23.182218 output: Hash value: cc4352de
266 12:14:23.182270 output: Image 2 (ramdisk-1)
267 12:14:23.182323 output: Description: unavailable
268 12:14:23.182375 output: Created: Wed Jan 31 12:14:23 2024
269 12:14:23.182428 output: Type: RAMDisk Image
270 12:14:23.182481 output: Compression: Unknown Compression
271 12:14:23.182533 output: Data Size: 17799535 Bytes = 17382.36 KiB = 16.97 MiB
272 12:14:23.182586 output: Architecture: AArch64
273 12:14:23.182639 output: OS: Linux
274 12:14:23.182692 output: Load Address: unavailable
275 12:14:23.182745 output: Entry Point: unavailable
276 12:14:23.182797 output: Hash algo: crc32
277 12:14:23.182849 output: Hash value: ff73b1ab
278 12:14:23.182901 output: Default Configuration: 'conf-1'
279 12:14:23.182953 output: Configuration 0 (conf-1)
280 12:14:23.183006 output: Description: mt8192-asurada-spherion-r0
281 12:14:23.183058 output: Kernel: kernel-1
282 12:14:23.183110 output: Init Ramdisk: ramdisk-1
283 12:14:23.183162 output: FDT: fdt-1
284 12:14:23.183214 output: Loadables: kernel-1
285 12:14:23.183267 output:
286 12:14:23.183473 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 12:14:23.183574 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 12:14:23.183680 end: 1.6 prepare-tftp-overlay (duration 00:00:17) [common]
289 12:14:23.183773 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 12:14:23.183852 No LXC device requested
291 12:14:23.183935 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 12:14:23.184020 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 12:14:23.184098 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 12:14:23.184167 Checking files for TFTP limit of 4294967296 bytes.
295 12:14:23.184654 end: 1 tftp-deploy (duration 00:00:23) [common]
296 12:14:23.184798 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 12:14:23.184891 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 12:14:23.185016 substitutions:
299 12:14:23.185082 - {DTB}: 12669512/tftp-deploy-51zf4tfc/dtb/mt8192-asurada-spherion-r0.dtb
300 12:14:23.185144 - {INITRD}: 12669512/tftp-deploy-51zf4tfc/ramdisk/ramdisk.cpio.gz
301 12:14:23.185203 - {KERNEL}: 12669512/tftp-deploy-51zf4tfc/kernel/Image
302 12:14:23.185260 - {LAVA_MAC}: None
303 12:14:23.185316 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12669512/extract-nfsrootfs-zak5hcs0
304 12:14:23.185371 - {NFS_SERVER_IP}: 192.168.201.1
305 12:14:23.185425 - {PRESEED_CONFIG}: None
306 12:14:23.185479 - {PRESEED_LOCAL}: None
307 12:14:23.185532 - {RAMDISK}: 12669512/tftp-deploy-51zf4tfc/ramdisk/ramdisk.cpio.gz
308 12:14:23.185585 - {ROOT_PART}: None
309 12:14:23.185639 - {ROOT}: None
310 12:14:23.185692 - {SERVER_IP}: 192.168.201.1
311 12:14:23.185745 - {TEE}: None
312 12:14:23.185798 Parsed boot commands:
313 12:14:23.185851 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 12:14:23.186038 Parsed boot commands: tftpboot 192.168.201.1 12669512/tftp-deploy-51zf4tfc/kernel/image.itb 12669512/tftp-deploy-51zf4tfc/kernel/cmdline
315 12:14:23.186125 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 12:14:23.186213 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 12:14:23.186302 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 12:14:23.186386 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 12:14:23.186458 Not connected, no need to disconnect.
320 12:14:23.186530 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 12:14:23.186610 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 12:14:23.186679 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
323 12:14:23.190657 Setting prompt string to ['lava-test: # ']
324 12:14:23.191019 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 12:14:23.191125 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 12:14:23.191224 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 12:14:23.191357 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 12:14:23.191594 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
329 12:14:28.345548 >> Command sent successfully.
330 12:14:28.357013 Returned 0 in 5 seconds
331 12:14:28.458350 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 12:14:28.459914 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 12:14:28.460503 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 12:14:28.461041 Setting prompt string to 'Starting depthcharge on Spherion...'
336 12:14:28.461431 Changing prompt to 'Starting depthcharge on Spherion...'
337 12:14:28.461831 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 12:14:28.463195 [Enter `^Ec?' for help]
339 12:14:28.631758
340 12:14:28.632360
341 12:14:28.632826 F0: 102B 0000
342 12:14:28.633209
343 12:14:28.633552 F3: 1001 0000 [0200]
344 12:14:28.633984
345 12:14:28.634622 F3: 1001 0000
346 12:14:28.634982
347 12:14:28.635312 F7: 102D 0000
348 12:14:28.635638
349 12:14:28.635957 F1: 0000 0000
350 12:14:28.636271
351 12:14:28.638664 V0: 0000 0000 [0001]
352 12:14:28.639149
353 12:14:28.639528 00: 0007 8000
354 12:14:28.639908
355 12:14:28.641662 01: 0000 0000
356 12:14:28.642140
357 12:14:28.642513 BP: 0C00 0209 [0000]
358 12:14:28.642861
359 12:14:28.645920 G0: 1182 0000
360 12:14:28.646538
361 12:14:28.646921 EC: 0000 0021 [4000]
362 12:14:28.647274
363 12:14:28.648752 S7: 0000 0000 [0000]
364 12:14:28.649235
365 12:14:28.649608 CC: 0000 0000 [0001]
366 12:14:28.649958
367 12:14:28.652121 T0: 0000 0040 [010F]
368 12:14:28.652597
369 12:14:28.653013 Jump to BL
370 12:14:28.653365
371 12:14:28.677298
372 12:14:28.677887
373 12:14:28.678271
374 12:14:28.684498 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 12:14:28.687978 ARM64: Exception handlers installed.
376 12:14:28.691903 ARM64: Testing exception
377 12:14:28.694396 ARM64: Done test exception
378 12:14:28.701509 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 12:14:28.711692 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 12:14:28.718995 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 12:14:28.728880 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 12:14:28.735553 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 12:14:28.742266 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 12:14:28.753882 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 12:14:28.760311 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 12:14:28.780649 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 12:14:28.784218 WDT: Last reset was cold boot
388 12:14:28.786727 SPI1(PAD0) initialized at 2873684 Hz
389 12:14:28.789784 SPI5(PAD0) initialized at 992727 Hz
390 12:14:28.793000 VBOOT: Loading verstage.
391 12:14:28.799932 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 12:14:28.803053 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 12:14:28.806844 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 12:14:28.810328 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 12:14:28.817197 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 12:14:28.824769 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 12:14:28.835637 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
398 12:14:28.836207
399 12:14:28.836583
400 12:14:28.844835 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 12:14:28.848477 ARM64: Exception handlers installed.
402 12:14:28.852521 ARM64: Testing exception
403 12:14:28.853135 ARM64: Done test exception
404 12:14:28.858846 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 12:14:28.861812 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 12:14:28.876074 Probing TPM: . done!
407 12:14:28.876640 TPM ready after 0 ms
408 12:14:28.883279 Connected to device vid:did:rid of 1ae0:0028:00
409 12:14:28.889633 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
410 12:14:28.893890 Initialized TPM device CR50 revision 0
411 12:14:28.942434 tlcl_send_startup: Startup return code is 0
412 12:14:28.942994 TPM: setup succeeded
413 12:14:28.954799 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 12:14:28.963719 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 12:14:28.973040 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 12:14:28.982490 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 12:14:28.985516 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 12:14:28.988905 in-header: 03 07 00 00 08 00 00 00
419 12:14:28.992249 in-data: aa e4 47 04 13 02 00 00
420 12:14:28.995026 Chrome EC: UHEPI supported
421 12:14:29.002080 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 12:14:29.005608 in-header: 03 9d 00 00 08 00 00 00
423 12:14:29.008368 in-data: 10 20 20 08 00 00 00 00
424 12:14:29.008876 Phase 1
425 12:14:29.012279 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 12:14:29.018965 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 12:14:29.025344 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 12:14:29.028982 Recovery requested (1009000e)
429 12:14:29.032300 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 12:14:29.041350 tlcl_extend: response is 0
431 12:14:29.048461 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 12:14:29.053875 tlcl_extend: response is 0
433 12:14:29.060547 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 12:14:29.081231 read SPI 0x210d4 0x2173b: 15143 us, 9048 KB/s, 72.384 Mbps
435 12:14:29.088688 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 12:14:29.089302
437 12:14:29.089679
438 12:14:29.098176 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 12:14:29.101384 ARM64: Exception handlers installed.
440 12:14:29.105194 ARM64: Testing exception
441 12:14:29.105687 ARM64: Done test exception
442 12:14:29.128510 pmic_efuse_setting: Set efuses in 11 msecs
443 12:14:29.130222 pmwrap_interface_init: Select PMIF_VLD_RDY
444 12:14:29.137198 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 12:14:29.140376 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 12:14:29.144489 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 12:14:29.152201 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 12:14:29.155453 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 12:14:29.159893 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 12:14:29.166455 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 12:14:29.169590 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 12:14:29.172993 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 12:14:29.179777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 12:14:29.184609 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 12:14:29.189901 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 12:14:29.193794 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 12:14:29.200360 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 12:14:29.206763 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 12:14:29.209609 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 12:14:29.216485 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 12:14:29.223856 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 12:14:29.227388 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 12:14:29.233533 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 12:14:29.237619 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 12:14:29.244449 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 12:14:29.250453 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 12:14:29.254004 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 12:14:29.260574 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 12:14:29.267102 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 12:14:29.270397 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 12:14:29.277319 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 12:14:29.280358 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 12:14:29.287223 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 12:14:29.290715 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 12:14:29.296988 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 12:14:29.300062 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 12:14:29.307467 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 12:14:29.310068 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 12:14:29.316859 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 12:14:29.320208 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 12:14:29.327822 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 12:14:29.329956 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 12:14:29.334024 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 12:14:29.341272 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 12:14:29.344296 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 12:14:29.347587 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 12:14:29.353549 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 12:14:29.356968 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 12:14:29.360294 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 12:14:29.363352 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 12:14:29.370443 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 12:14:29.373067 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 12:14:29.376649 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 12:14:29.383278 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 12:14:29.390375 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 12:14:29.396770 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 12:14:29.403250 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 12:14:29.409969 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 12:14:29.420682 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 12:14:29.423761 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 12:14:29.430662 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 12:14:29.433045 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 12:14:29.439496 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x15
504 12:14:29.446330 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 12:14:29.450245 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 12:14:29.453148 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 12:14:29.464507 [RTC]rtc_get_frequency_meter,154: input=15, output=764
508 12:14:29.474223 [RTC]rtc_get_frequency_meter,154: input=23, output=949
509 12:14:29.483162 [RTC]rtc_get_frequency_meter,154: input=19, output=857
510 12:14:29.492747 [RTC]rtc_get_frequency_meter,154: input=17, output=811
511 12:14:29.502981 [RTC]rtc_get_frequency_meter,154: input=16, output=786
512 12:14:29.512071 [RTC]rtc_get_frequency_meter,154: input=16, output=787
513 12:14:29.522012 [RTC]rtc_get_frequency_meter,154: input=17, output=811
514 12:14:29.524404 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
515 12:14:29.531939 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
516 12:14:29.535469 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 12:14:29.538712 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 12:14:29.544907 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 12:14:29.549229 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 12:14:29.551801 ADC[4]: Raw value=669695 ID=5
521 12:14:29.552294 ADC[3]: Raw value=212917 ID=1
522 12:14:29.554998 RAM Code: 0x51
523 12:14:29.558874 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 12:14:29.565136 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 12:14:29.571623 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
526 12:14:29.578701 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
527 12:14:29.581539 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 12:14:29.584779 in-header: 03 07 00 00 08 00 00 00
529 12:14:29.588255 in-data: aa e4 47 04 13 02 00 00
530 12:14:29.591928 Chrome EC: UHEPI supported
531 12:14:29.599217 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 12:14:29.602057 in-header: 03 d5 00 00 08 00 00 00
533 12:14:29.605303 in-data: 98 20 60 08 00 00 00 00
534 12:14:29.609116 MRC: failed to locate region type 0.
535 12:14:29.615168 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 12:14:29.615743 DRAM-K: Running full calibration
537 12:14:29.621687 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
538 12:14:29.625395 header.status = 0x0
539 12:14:29.628479 header.version = 0x6 (expected: 0x6)
540 12:14:29.632251 header.size = 0xd00 (expected: 0xd00)
541 12:14:29.632862 header.flags = 0x0
542 12:14:29.637974 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 12:14:29.656400 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
544 12:14:29.663237 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 12:14:29.667256 dram_init: ddr_geometry: 0
546 12:14:29.669400 [EMI] MDL number = 0
547 12:14:29.669875 [EMI] Get MDL freq = 0
548 12:14:29.673236 dram_init: ddr_type: 0
549 12:14:29.673800 is_discrete_lpddr4: 1
550 12:14:29.676333 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 12:14:29.676837
552 12:14:29.677216
553 12:14:29.679741 [Bian_co] ETT version 0.0.0.1
554 12:14:29.684539 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
555 12:14:29.685196
556 12:14:29.690553 dramc_set_vcore_voltage set vcore to 650000
557 12:14:29.691136 Read voltage for 800, 4
558 12:14:29.691524 Vio18 = 0
559 12:14:29.695375 Vcore = 650000
560 12:14:29.695950 Vdram = 0
561 12:14:29.696333 Vddq = 0
562 12:14:29.697050 Vmddr = 0
563 12:14:29.697423 dram_init: config_dvfs: 1
564 12:14:29.704282 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 12:14:29.710321 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 12:14:29.713424 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
567 12:14:29.717077 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
568 12:14:29.721986 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
569 12:14:29.723508 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
570 12:14:29.727226 MEM_TYPE=3, freq_sel=18
571 12:14:29.730871 sv_algorithm_assistance_LP4_1600
572 12:14:29.734069 ============ PULL DRAM RESETB DOWN ============
573 12:14:29.737198 ========== PULL DRAM RESETB DOWN end =========
574 12:14:29.743957 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 12:14:29.747585 ===================================
576 12:14:29.748176 LPDDR4 DRAM CONFIGURATION
577 12:14:29.751139 ===================================
578 12:14:29.753960 EX_ROW_EN[0] = 0x0
579 12:14:29.754533 EX_ROW_EN[1] = 0x0
580 12:14:29.757638 LP4Y_EN = 0x0
581 12:14:29.758224 WORK_FSP = 0x0
582 12:14:29.761159 WL = 0x2
583 12:14:29.761730 RL = 0x2
584 12:14:29.763825 BL = 0x2
585 12:14:29.764298 RPST = 0x0
586 12:14:29.767958 RD_PRE = 0x0
587 12:14:29.768542 WR_PRE = 0x1
588 12:14:29.770532 WR_PST = 0x0
589 12:14:29.774157 DBI_WR = 0x0
590 12:14:29.774736 DBI_RD = 0x0
591 12:14:29.777456 OTF = 0x1
592 12:14:29.782103 ===================================
593 12:14:29.783824 ===================================
594 12:14:29.784315 ANA top config
595 12:14:29.787730 ===================================
596 12:14:29.791037 DLL_ASYNC_EN = 0
597 12:14:29.794238 ALL_SLAVE_EN = 1
598 12:14:29.794813 NEW_RANK_MODE = 1
599 12:14:29.797331 DLL_IDLE_MODE = 1
600 12:14:29.800793 LP45_APHY_COMB_EN = 1
601 12:14:29.804147 TX_ODT_DIS = 1
602 12:14:29.804769 NEW_8X_MODE = 1
603 12:14:29.806793 ===================================
604 12:14:29.810612 ===================================
605 12:14:29.813851 data_rate = 1600
606 12:14:29.817308 CKR = 1
607 12:14:29.820795 DQ_P2S_RATIO = 8
608 12:14:29.823937 ===================================
609 12:14:29.826714 CA_P2S_RATIO = 8
610 12:14:29.830415 DQ_CA_OPEN = 0
611 12:14:29.831007 DQ_SEMI_OPEN = 0
612 12:14:29.833901 CA_SEMI_OPEN = 0
613 12:14:29.837413 CA_FULL_RATE = 0
614 12:14:29.840399 DQ_CKDIV4_EN = 1
615 12:14:29.843411 CA_CKDIV4_EN = 1
616 12:14:29.847088 CA_PREDIV_EN = 0
617 12:14:29.847679 PH8_DLY = 0
618 12:14:29.850109 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 12:14:29.854066 DQ_AAMCK_DIV = 4
620 12:14:29.857676 CA_AAMCK_DIV = 4
621 12:14:29.860557 CA_ADMCK_DIV = 4
622 12:14:29.863573 DQ_TRACK_CA_EN = 0
623 12:14:29.864047 CA_PICK = 800
624 12:14:29.866604 CA_MCKIO = 800
625 12:14:29.869758 MCKIO_SEMI = 0
626 12:14:29.873583 PLL_FREQ = 3068
627 12:14:29.877168 DQ_UI_PI_RATIO = 32
628 12:14:29.880508 CA_UI_PI_RATIO = 0
629 12:14:29.884200 ===================================
630 12:14:29.886683 ===================================
631 12:14:29.887158 memory_type:LPDDR4
632 12:14:29.891254 GP_NUM : 10
633 12:14:29.894253 SRAM_EN : 1
634 12:14:29.894823 MD32_EN : 0
635 12:14:29.896927 ===================================
636 12:14:29.900098 [ANA_INIT] >>>>>>>>>>>>>>
637 12:14:29.903220 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 12:14:29.907111 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 12:14:29.909915 ===================================
640 12:14:29.913406 data_rate = 1600,PCW = 0X7600
641 12:14:29.916875 ===================================
642 12:14:29.920270 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 12:14:29.924214 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 12:14:29.929554 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 12:14:29.933192 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 12:14:29.936581 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 12:14:29.940044 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 12:14:29.943553 [ANA_INIT] flow start
649 12:14:29.947858 [ANA_INIT] PLL >>>>>>>>
650 12:14:29.948427 [ANA_INIT] PLL <<<<<<<<
651 12:14:29.949554 [ANA_INIT] MIDPI >>>>>>>>
652 12:14:29.953378 [ANA_INIT] MIDPI <<<<<<<<
653 12:14:29.957116 [ANA_INIT] DLL >>>>>>>>
654 12:14:29.957680 [ANA_INIT] flow end
655 12:14:29.959869 ============ LP4 DIFF to SE enter ============
656 12:14:29.966634 ============ LP4 DIFF to SE exit ============
657 12:14:29.967106 [ANA_INIT] <<<<<<<<<<<<<
658 12:14:29.969565 [Flow] Enable top DCM control >>>>>
659 12:14:29.973200 [Flow] Enable top DCM control <<<<<
660 12:14:29.976646 Enable DLL master slave shuffle
661 12:14:29.983003 ==============================================================
662 12:14:29.983592 Gating Mode config
663 12:14:29.989733 ==============================================================
664 12:14:29.993711 Config description:
665 12:14:30.002874 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 12:14:30.007100 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 12:14:30.013437 SELPH_MODE 0: By rank 1: By Phase
668 12:14:30.020413 ==============================================================
669 12:14:30.023275 GAT_TRACK_EN = 1
670 12:14:30.023849 RX_GATING_MODE = 2
671 12:14:30.027258 RX_GATING_TRACK_MODE = 2
672 12:14:30.030302 SELPH_MODE = 1
673 12:14:30.033477 PICG_EARLY_EN = 1
674 12:14:30.036481 VALID_LAT_VALUE = 1
675 12:14:30.043472 ==============================================================
676 12:14:30.046777 Enter into Gating configuration >>>>
677 12:14:30.049971 Exit from Gating configuration <<<<
678 12:14:30.053511 Enter into DVFS_PRE_config >>>>>
679 12:14:30.063320 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 12:14:30.067154 Exit from DVFS_PRE_config <<<<<
681 12:14:30.069796 Enter into PICG configuration >>>>
682 12:14:30.073316 Exit from PICG configuration <<<<
683 12:14:30.076657 [RX_INPUT] configuration >>>>>
684 12:14:30.077175 [RX_INPUT] configuration <<<<<
685 12:14:30.083578 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 12:14:30.090046 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 12:14:30.093328 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 12:14:30.100100 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 12:14:30.107002 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 12:14:30.113528 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 12:14:30.116857 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 12:14:30.120304 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 12:14:30.126298 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 12:14:30.130247 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 12:14:30.133630 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 12:14:30.136448 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 12:14:30.140203 ===================================
698 12:14:30.143256 LPDDR4 DRAM CONFIGURATION
699 12:14:30.146654 ===================================
700 12:14:30.149783 EX_ROW_EN[0] = 0x0
701 12:14:30.150256 EX_ROW_EN[1] = 0x0
702 12:14:30.153234 LP4Y_EN = 0x0
703 12:14:30.153801 WORK_FSP = 0x0
704 12:14:30.157413 WL = 0x2
705 12:14:30.157882 RL = 0x2
706 12:14:30.159790 BL = 0x2
707 12:14:30.160357 RPST = 0x0
708 12:14:30.163296 RD_PRE = 0x0
709 12:14:30.163868 WR_PRE = 0x1
710 12:14:30.166871 WR_PST = 0x0
711 12:14:30.169680 DBI_WR = 0x0
712 12:14:30.170228 DBI_RD = 0x0
713 12:14:30.172829 OTF = 0x1
714 12:14:30.177272 ===================================
715 12:14:30.179884 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 12:14:30.183582 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 12:14:30.187045 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 12:14:30.190516 ===================================
719 12:14:30.193001 LPDDR4 DRAM CONFIGURATION
720 12:14:30.196604 ===================================
721 12:14:30.202121 EX_ROW_EN[0] = 0x10
722 12:14:30.202628 EX_ROW_EN[1] = 0x0
723 12:14:30.204265 LP4Y_EN = 0x0
724 12:14:30.204858 WORK_FSP = 0x0
725 12:14:30.206429 WL = 0x2
726 12:14:30.206987 RL = 0x2
727 12:14:30.210040 BL = 0x2
728 12:14:30.210513 RPST = 0x0
729 12:14:30.213107 RD_PRE = 0x0
730 12:14:30.213719 WR_PRE = 0x1
731 12:14:30.216621 WR_PST = 0x0
732 12:14:30.217160 DBI_WR = 0x0
733 12:14:30.220587 DBI_RD = 0x0
734 12:14:30.221092 OTF = 0x1
735 12:14:30.223059 ===================================
736 12:14:30.230841 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 12:14:30.234587 nWR fixed to 40
738 12:14:30.239474 [ModeRegInit_LP4] CH0 RK0
739 12:14:30.239949 [ModeRegInit_LP4] CH0 RK1
740 12:14:30.241023 [ModeRegInit_LP4] CH1 RK0
741 12:14:30.244292 [ModeRegInit_LP4] CH1 RK1
742 12:14:30.244804 match AC timing 12
743 12:14:30.251126 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
744 12:14:30.254511 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 12:14:30.257719 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 12:14:30.264773 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 12:14:30.267534 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 12:14:30.271049 [EMI DOE] emi_dcm 0
749 12:14:30.274449 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 12:14:30.275056 ==
751 12:14:30.277307 Dram Type= 6, Freq= 0, CH_0, rank 0
752 12:14:30.281052 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
753 12:14:30.281761 ==
754 12:14:30.289758 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 12:14:30.294222 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 12:14:30.301784 [CA 0] Center 37 (7~68) winsize 62
757 12:14:30.305529 [CA 1] Center 37 (7~68) winsize 62
758 12:14:30.309251 [CA 2] Center 35 (5~66) winsize 62
759 12:14:30.312049 [CA 3] Center 35 (5~66) winsize 62
760 12:14:30.315491 [CA 4] Center 34 (4~65) winsize 62
761 12:14:30.318412 [CA 5] Center 34 (3~65) winsize 63
762 12:14:30.318886
763 12:14:30.321984 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 12:14:30.322729
765 12:14:30.325874 [CATrainingPosCal] consider 1 rank data
766 12:14:30.328432 u2DelayCellTimex100 = 270/100 ps
767 12:14:30.331867 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
768 12:14:30.335710 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
769 12:14:30.338773 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
770 12:14:30.345573 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
771 12:14:30.349029 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
772 12:14:30.352225 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
773 12:14:30.352841
774 12:14:30.355070 CA PerBit enable=1, Macro0, CA PI delay=34
775 12:14:30.355639
776 12:14:30.359126 [CBTSetCACLKResult] CA Dly = 34
777 12:14:30.359699 CS Dly: 6 (0~37)
778 12:14:30.360079 ==
779 12:14:30.361588 Dram Type= 6, Freq= 0, CH_0, rank 1
780 12:14:30.369158 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
781 12:14:30.369735 ==
782 12:14:30.371618 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 12:14:30.379209 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 12:14:30.387930 [CA 0] Center 37 (7~68) winsize 62
785 12:14:30.391512 [CA 1] Center 37 (6~68) winsize 63
786 12:14:30.394503 [CA 2] Center 35 (4~66) winsize 63
787 12:14:30.397709 [CA 3] Center 34 (4~65) winsize 62
788 12:14:30.401290 [CA 4] Center 33 (3~64) winsize 62
789 12:14:30.403904 [CA 5] Center 33 (3~64) winsize 62
790 12:14:30.404445
791 12:14:30.407893 [CmdBusTrainingLP45] Vref(ca) range 1: 34
792 12:14:30.408434
793 12:14:30.411357 [CATrainingPosCal] consider 2 rank data
794 12:14:30.414284 u2DelayCellTimex100 = 270/100 ps
795 12:14:30.417730 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
796 12:14:30.422402 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
797 12:14:30.427723 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
798 12:14:30.431078 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
799 12:14:30.434543 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
800 12:14:30.437494 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 12:14:30.438011
802 12:14:30.441346 CA PerBit enable=1, Macro0, CA PI delay=33
803 12:14:30.441915
804 12:14:30.444170 [CBTSetCACLKResult] CA Dly = 33
805 12:14:30.444769 CS Dly: 6 (0~38)
806 12:14:30.445159
807 12:14:30.450978 ----->DramcWriteLeveling(PI) begin...
808 12:14:30.451572 ==
809 12:14:30.454718 Dram Type= 6, Freq= 0, CH_0, rank 0
810 12:14:30.458234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 12:14:30.458808 ==
812 12:14:30.460848 Write leveling (Byte 0): 29 => 29
813 12:14:30.464188 Write leveling (Byte 1): 29 => 29
814 12:14:30.467641 DramcWriteLeveling(PI) end<-----
815 12:14:30.468209
816 12:14:30.468585 ==
817 12:14:30.470449 Dram Type= 6, Freq= 0, CH_0, rank 0
818 12:14:30.474924 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
819 12:14:30.475500 ==
820 12:14:30.477400 [Gating] SW mode calibration
821 12:14:30.483956 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 12:14:30.491822 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 12:14:30.494317 0 6 0 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
824 12:14:30.497323 0 6 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
825 12:14:30.503410 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:14:30.507217 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:14:30.510190 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:14:30.517127 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 12:14:30.522022 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 12:14:30.524129 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 12:14:30.530308 0 7 0 | B1->B0 | 2828 2e2e | 0 0 | (0 0) (0 0)
832 12:14:30.533604 0 7 4 | B1->B0 | 3d3d 4343 | 0 0 | (0 0) (0 0)
833 12:14:30.537455 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:14:30.544031 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:14:30.547812 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:14:30.549644 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 12:14:30.557162 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 12:14:30.560578 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 12:14:30.563794 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
840 12:14:30.566742 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
841 12:14:30.573895 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:14:30.576840 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:14:30.579632 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:14:30.587103 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:14:30.590518 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:14:30.593731 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:14:30.600037 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:14:30.603597 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:14:30.606433 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:14:30.613002 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:14:30.616761 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:14:30.619722 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 12:14:30.626144 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 12:14:30.629605 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 12:14:30.633293 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
856 12:14:30.639546 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 12:14:30.640157 Total UI for P1: 0, mck2ui 16
858 12:14:30.646841 best dqsien dly found for B0: ( 0, 10, 0)
859 12:14:30.647317 Total UI for P1: 0, mck2ui 16
860 12:14:30.652874 best dqsien dly found for B1: ( 0, 10, 0)
861 12:14:30.656437 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
862 12:14:30.660527 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
863 12:14:30.661227
864 12:14:30.663796 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
865 12:14:30.666205 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
866 12:14:30.669502 [Gating] SW calibration Done
867 12:14:30.670068 ==
868 12:14:30.672843 Dram Type= 6, Freq= 0, CH_0, rank 0
869 12:14:30.676620 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
870 12:14:30.677478 ==
871 12:14:30.679911 RX Vref Scan: 0
872 12:14:30.680384
873 12:14:30.680792 RX Vref 0 -> 0, step: 1
874 12:14:30.681155
875 12:14:30.684039 RX Delay -130 -> 252, step: 16
876 12:14:30.686961 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
877 12:14:30.690569 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
878 12:14:30.696699 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
879 12:14:30.700274 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
880 12:14:30.703531 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
881 12:14:30.706957 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
882 12:14:30.710332 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
883 12:14:30.717340 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
884 12:14:30.720131 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
885 12:14:30.723799 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
886 12:14:30.726578 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
887 12:14:30.729704 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
888 12:14:30.737078 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
889 12:14:30.740262 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
890 12:14:30.743276 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
891 12:14:30.747058 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
892 12:14:30.747627 ==
893 12:14:30.749921 Dram Type= 6, Freq= 0, CH_0, rank 0
894 12:14:30.757040 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
895 12:14:30.757616 ==
896 12:14:30.757997 DQS Delay:
897 12:14:30.759876 DQS0 = 0, DQS1 = 0
898 12:14:30.760348 DQM Delay:
899 12:14:30.760793 DQM0 = 87, DQM1 = 76
900 12:14:30.763041 DQ Delay:
901 12:14:30.766641 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
902 12:14:30.769823 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
903 12:14:30.773002 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
904 12:14:30.776554 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
905 12:14:30.777163
906 12:14:30.777547
907 12:14:30.777903 ==
908 12:14:30.779854 Dram Type= 6, Freq= 0, CH_0, rank 0
909 12:14:30.783577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
910 12:14:30.784054 ==
911 12:14:30.784431
912 12:14:30.784827
913 12:14:30.787177 TX Vref Scan disable
914 12:14:30.790516 == TX Byte 0 ==
915 12:14:30.793296 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 12:14:30.797161 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 12:14:30.800109 == TX Byte 1 ==
918 12:14:30.803536 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
919 12:14:30.807254 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
920 12:14:30.807730 ==
921 12:14:30.811051 Dram Type= 6, Freq= 0, CH_0, rank 0
922 12:14:30.812824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
923 12:14:30.813306 ==
924 12:14:30.827951 TX Vref=22, minBit 2, minWin=27, winSum=445
925 12:14:30.831112 TX Vref=24, minBit 0, minWin=27, winSum=447
926 12:14:30.834530 TX Vref=26, minBit 4, minWin=27, winSum=452
927 12:14:30.837446 TX Vref=28, minBit 2, minWin=28, winSum=457
928 12:14:30.840920 TX Vref=30, minBit 0, minWin=28, winSum=456
929 12:14:30.844025 TX Vref=32, minBit 0, minWin=27, winSum=451
930 12:14:30.850786 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 28
931 12:14:30.851373
932 12:14:30.855215 Final TX Range 1 Vref 28
933 12:14:30.855781
934 12:14:30.856189 ==
935 12:14:30.857054 Dram Type= 6, Freq= 0, CH_0, rank 0
936 12:14:30.861032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
937 12:14:30.861605 ==
938 12:14:30.861981
939 12:14:30.863682
940 12:14:30.864150 TX Vref Scan disable
941 12:14:30.867842 == TX Byte 0 ==
942 12:14:30.870754 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 12:14:30.873548 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 12:14:30.877113 == TX Byte 1 ==
945 12:14:30.880316 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
946 12:14:30.887401 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
947 12:14:30.887972
948 12:14:30.888348 [DATLAT]
949 12:14:30.888700 Freq=800, CH0 RK0
950 12:14:30.889107
951 12:14:30.890237 DATLAT Default: 0xa
952 12:14:30.890703 0, 0xFFFF, sum = 0
953 12:14:30.893798 1, 0xFFFF, sum = 0
954 12:14:30.894345 2, 0xFFFF, sum = 0
955 12:14:30.896856 3, 0xFFFF, sum = 0
956 12:14:30.900329 4, 0xFFFF, sum = 0
957 12:14:30.900976 5, 0xFFFF, sum = 0
958 12:14:30.904365 6, 0xFFFF, sum = 0
959 12:14:30.904907 7, 0xFFFF, sum = 0
960 12:14:30.907084 8, 0x0, sum = 1
961 12:14:30.907569 9, 0x0, sum = 2
962 12:14:30.907949 10, 0x0, sum = 3
963 12:14:30.910545 11, 0x0, sum = 4
964 12:14:30.911126 best_step = 9
965 12:14:30.911504
966 12:14:30.911852 ==
967 12:14:30.914110 Dram Type= 6, Freq= 0, CH_0, rank 0
968 12:14:30.920241 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
969 12:14:30.920837 ==
970 12:14:30.921225 RX Vref Scan: 1
971 12:14:30.921579
972 12:14:30.923590 Set Vref Range= 32 -> 127
973 12:14:30.924156
974 12:14:30.927042 RX Vref 32 -> 127, step: 1
975 12:14:30.927513
976 12:14:30.930525 RX Delay -95 -> 252, step: 8
977 12:14:30.931097
978 12:14:30.931473 Set Vref, RX VrefLevel [Byte0]: 32
979 12:14:30.933332 [Byte1]: 32
980 12:14:30.938316
981 12:14:30.938884 Set Vref, RX VrefLevel [Byte0]: 33
982 12:14:30.941606 [Byte1]: 33
983 12:14:30.945656
984 12:14:30.946223 Set Vref, RX VrefLevel [Byte0]: 34
985 12:14:30.948676 [Byte1]: 34
986 12:14:30.952786
987 12:14:30.953257 Set Vref, RX VrefLevel [Byte0]: 35
988 12:14:30.956302 [Byte1]: 35
989 12:14:30.961259
990 12:14:30.961884 Set Vref, RX VrefLevel [Byte0]: 36
991 12:14:30.963988 [Byte1]: 36
992 12:14:30.968301
993 12:14:30.968921 Set Vref, RX VrefLevel [Byte0]: 37
994 12:14:30.971253 [Byte1]: 37
995 12:14:30.976911
996 12:14:30.977486 Set Vref, RX VrefLevel [Byte0]: 38
997 12:14:30.979670 [Byte1]: 38
998 12:14:30.983486
999 12:14:30.984045 Set Vref, RX VrefLevel [Byte0]: 39
1000 12:14:30.986910 [Byte1]: 39
1001 12:14:30.991668
1002 12:14:30.992234 Set Vref, RX VrefLevel [Byte0]: 40
1003 12:14:30.996353 [Byte1]: 40
1004 12:14:30.998754
1005 12:14:30.999319 Set Vref, RX VrefLevel [Byte0]: 41
1006 12:14:31.001989 [Byte1]: 41
1007 12:14:31.006008
1008 12:14:31.006677 Set Vref, RX VrefLevel [Byte0]: 42
1009 12:14:31.009498 [Byte1]: 42
1010 12:14:31.014213
1011 12:14:31.014695 Set Vref, RX VrefLevel [Byte0]: 43
1012 12:14:31.016928 [Byte1]: 43
1013 12:14:31.021870
1014 12:14:31.022440 Set Vref, RX VrefLevel [Byte0]: 44
1015 12:14:31.025168 [Byte1]: 44
1016 12:14:31.029331
1017 12:14:31.029796 Set Vref, RX VrefLevel [Byte0]: 45
1018 12:14:31.032822 [Byte1]: 45
1019 12:14:31.037073
1020 12:14:31.037637 Set Vref, RX VrefLevel [Byte0]: 46
1021 12:14:31.040023 [Byte1]: 46
1022 12:14:31.044094
1023 12:14:31.044657 Set Vref, RX VrefLevel [Byte0]: 47
1024 12:14:31.048099 [Byte1]: 47
1025 12:14:31.052180
1026 12:14:31.052819 Set Vref, RX VrefLevel [Byte0]: 48
1027 12:14:31.055176 [Byte1]: 48
1028 12:14:31.061093
1029 12:14:31.061653 Set Vref, RX VrefLevel [Byte0]: 49
1030 12:14:31.062629 [Byte1]: 49
1031 12:14:31.066835
1032 12:14:31.067290 Set Vref, RX VrefLevel [Byte0]: 50
1033 12:14:31.070642 [Byte1]: 50
1034 12:14:31.075985
1035 12:14:31.076543 Set Vref, RX VrefLevel [Byte0]: 51
1036 12:14:31.077901 [Byte1]: 51
1037 12:14:31.083639
1038 12:14:31.084195 Set Vref, RX VrefLevel [Byte0]: 52
1039 12:14:31.086688 [Byte1]: 52
1040 12:14:31.090582
1041 12:14:31.091135 Set Vref, RX VrefLevel [Byte0]: 53
1042 12:14:31.093985 [Byte1]: 53
1043 12:14:31.097494
1044 12:14:31.097955 Set Vref, RX VrefLevel [Byte0]: 54
1045 12:14:31.100696 [Byte1]: 54
1046 12:14:31.105117
1047 12:14:31.105868 Set Vref, RX VrefLevel [Byte0]: 55
1048 12:14:31.108652 [Byte1]: 55
1049 12:14:31.112702
1050 12:14:31.113207 Set Vref, RX VrefLevel [Byte0]: 56
1051 12:14:31.115785 [Byte1]: 56
1052 12:14:31.120526
1053 12:14:31.121154 Set Vref, RX VrefLevel [Byte0]: 57
1054 12:14:31.123744 [Byte1]: 57
1055 12:14:31.129057
1056 12:14:31.129689 Set Vref, RX VrefLevel [Byte0]: 58
1057 12:14:31.131042 [Byte1]: 58
1058 12:14:31.136027
1059 12:14:31.136583 Set Vref, RX VrefLevel [Byte0]: 59
1060 12:14:31.139177 [Byte1]: 59
1061 12:14:31.143099
1062 12:14:31.143658 Set Vref, RX VrefLevel [Byte0]: 60
1063 12:14:31.146453 [Byte1]: 60
1064 12:14:31.150767
1065 12:14:31.151326 Set Vref, RX VrefLevel [Byte0]: 61
1066 12:14:31.154751 [Byte1]: 61
1067 12:14:31.159251
1068 12:14:31.159806 Set Vref, RX VrefLevel [Byte0]: 62
1069 12:14:31.161309 [Byte1]: 62
1070 12:14:31.166366
1071 12:14:31.166928 Set Vref, RX VrefLevel [Byte0]: 63
1072 12:14:31.169410 [Byte1]: 63
1073 12:14:31.173314
1074 12:14:31.173778 Set Vref, RX VrefLevel [Byte0]: 64
1075 12:14:31.176540 [Byte1]: 64
1076 12:14:31.181275
1077 12:14:31.181735 Set Vref, RX VrefLevel [Byte0]: 65
1078 12:14:31.184523 [Byte1]: 65
1079 12:14:31.188517
1080 12:14:31.189118 Set Vref, RX VrefLevel [Byte0]: 66
1081 12:14:31.192829 [Byte1]: 66
1082 12:14:31.197158
1083 12:14:31.197712 Set Vref, RX VrefLevel [Byte0]: 67
1084 12:14:31.199716 [Byte1]: 67
1085 12:14:31.204063
1086 12:14:31.204618 Set Vref, RX VrefLevel [Byte0]: 68
1087 12:14:31.207284 [Byte1]: 68
1088 12:14:31.211572
1089 12:14:31.212129 Set Vref, RX VrefLevel [Byte0]: 69
1090 12:14:31.214332 [Byte1]: 69
1091 12:14:31.218877
1092 12:14:31.219427 Set Vref, RX VrefLevel [Byte0]: 70
1093 12:14:31.221928 [Byte1]: 70
1094 12:14:31.226593
1095 12:14:31.227148 Set Vref, RX VrefLevel [Byte0]: 71
1096 12:14:31.229789 [Byte1]: 71
1097 12:14:31.234547
1098 12:14:31.235101 Set Vref, RX VrefLevel [Byte0]: 72
1099 12:14:31.237282 [Byte1]: 72
1100 12:14:31.241888
1101 12:14:31.242435 Set Vref, RX VrefLevel [Byte0]: 73
1102 12:14:31.245664 [Byte1]: 73
1103 12:14:31.249771
1104 12:14:31.250324 Final RX Vref Byte 0 = 53 to rank0
1105 12:14:31.253118 Final RX Vref Byte 1 = 55 to rank0
1106 12:14:31.255936 Final RX Vref Byte 0 = 53 to rank1
1107 12:14:31.259416 Final RX Vref Byte 1 = 55 to rank1==
1108 12:14:31.263450 Dram Type= 6, Freq= 0, CH_0, rank 0
1109 12:14:31.269309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1110 12:14:31.269774 ==
1111 12:14:31.270139 DQS Delay:
1112 12:14:31.270723 DQS0 = 0, DQS1 = 0
1113 12:14:31.272320 DQM Delay:
1114 12:14:31.272832 DQM0 = 83, DQM1 = 73
1115 12:14:31.275992 DQ Delay:
1116 12:14:31.276454 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1117 12:14:31.280079 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1118 12:14:31.282853 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1119 12:14:31.286695 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1120 12:14:31.287254
1121 12:14:31.289325
1122 12:14:31.296330 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1123 12:14:31.299877 CH0 RK0: MR19=606, MR18=3A3A
1124 12:14:31.306898 CH0_RK0: MR19=0x606, MR18=0x3A3A, DQSOSC=395, MR23=63, INC=94, DEC=63
1125 12:14:31.307747
1126 12:14:31.309534 ----->DramcWriteLeveling(PI) begin...
1127 12:14:31.310139 ==
1128 12:14:31.312773 Dram Type= 6, Freq= 0, CH_0, rank 1
1129 12:14:31.316606 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1130 12:14:31.317136 ==
1131 12:14:31.319818 Write leveling (Byte 0): 29 => 29
1132 12:14:31.323178 Write leveling (Byte 1): 27 => 27
1133 12:14:31.325972 DramcWriteLeveling(PI) end<-----
1134 12:14:31.326446
1135 12:14:31.326811 ==
1136 12:14:31.329573 Dram Type= 6, Freq= 0, CH_0, rank 1
1137 12:14:31.332703 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1138 12:14:31.333201 ==
1139 12:14:31.336830 [Gating] SW mode calibration
1140 12:14:31.342744 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1141 12:14:31.349081 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1142 12:14:31.352952 0 6 0 | B1->B0 | 3232 3030 | 1 1 | (1 0) (1 0)
1143 12:14:31.356004 0 6 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1144 12:14:31.362916 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 12:14:31.366348 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 12:14:31.369225 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 12:14:31.376104 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 12:14:31.379458 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 12:14:31.383083 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 12:14:31.389387 0 7 0 | B1->B0 | 2e2e 3636 | 0 0 | (0 0) (0 0)
1151 12:14:31.392898 0 7 4 | B1->B0 | 4343 4141 | 0 0 | (0 0) (0 0)
1152 12:14:31.396444 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1153 12:14:31.403243 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1154 12:14:31.407189 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1155 12:14:31.409548 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1156 12:14:31.412664 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1157 12:14:31.419588 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1158 12:14:31.423350 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1159 12:14:31.425613 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1160 12:14:31.432550 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1161 12:14:31.436189 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1162 12:14:31.439656 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1163 12:14:31.446508 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1164 12:14:31.449710 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1165 12:14:31.452683 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1166 12:14:31.459668 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1167 12:14:31.463149 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1168 12:14:31.465842 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1169 12:14:31.472555 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1170 12:14:31.476416 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1171 12:14:31.479202 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1172 12:14:31.486347 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1173 12:14:31.489920 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1174 12:14:31.493674 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1175 12:14:31.498934 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1176 12:14:31.499478 Total UI for P1: 0, mck2ui 16
1177 12:14:31.502864 best dqsien dly found for B0: ( 0, 10, 0)
1178 12:14:31.506069 Total UI for P1: 0, mck2ui 16
1179 12:14:31.509168 best dqsien dly found for B1: ( 0, 10, 0)
1180 12:14:31.512986 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1181 12:14:31.520429 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1182 12:14:31.521043
1183 12:14:31.523096 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1184 12:14:31.527376 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1185 12:14:31.529323 [Gating] SW calibration Done
1186 12:14:31.529791 ==
1187 12:14:31.532891 Dram Type= 6, Freq= 0, CH_0, rank 1
1188 12:14:31.535595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1189 12:14:31.536121 ==
1190 12:14:31.536492 RX Vref Scan: 0
1191 12:14:31.539080
1192 12:14:31.539580 RX Vref 0 -> 0, step: 1
1193 12:14:31.539961
1194 12:14:31.543509 RX Delay -130 -> 252, step: 16
1195 12:14:31.546486 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1196 12:14:31.549404 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1197 12:14:31.597466 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1198 12:14:31.598053 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1199 12:14:31.598792 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1200 12:14:31.599170 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1201 12:14:31.599511 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1202 12:14:31.599905 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1203 12:14:31.600244 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1204 12:14:31.600625 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1205 12:14:31.600997 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1206 12:14:31.601314 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1207 12:14:31.601686 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1208 12:14:31.620296 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1209 12:14:31.620912 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1210 12:14:31.621293 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1211 12:14:31.621637 ==
1212 12:14:31.621970 Dram Type= 6, Freq= 0, CH_0, rank 1
1213 12:14:31.622299 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1214 12:14:31.622625 ==
1215 12:14:31.623303 DQS Delay:
1216 12:14:31.623662 DQS0 = 0, DQS1 = 0
1217 12:14:31.623987 DQM Delay:
1218 12:14:31.624365 DQM0 = 82, DQM1 = 74
1219 12:14:31.624694 DQ Delay:
1220 12:14:31.625067 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1221 12:14:31.627135 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1222 12:14:31.631287 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1223 12:14:31.633882 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1224 12:14:31.634443
1225 12:14:31.634814
1226 12:14:31.635158 ==
1227 12:14:31.637880 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 12:14:31.643804 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1229 12:14:31.644365 ==
1230 12:14:31.644771
1231 12:14:31.645119
1232 12:14:31.645450 TX Vref Scan disable
1233 12:14:31.647546 == TX Byte 0 ==
1234 12:14:31.651075 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1235 12:14:31.657835 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1236 12:14:31.658397 == TX Byte 1 ==
1237 12:14:31.660789 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1238 12:14:31.666824 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1239 12:14:31.667374 ==
1240 12:14:31.670975 Dram Type= 6, Freq= 0, CH_0, rank 1
1241 12:14:31.673976 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1242 12:14:31.674446 ==
1243 12:14:31.686616 TX Vref=22, minBit 0, minWin=27, winSum=444
1244 12:14:31.689830 TX Vref=24, minBit 11, minWin=27, winSum=448
1245 12:14:31.693809 TX Vref=26, minBit 2, minWin=28, winSum=454
1246 12:14:31.697056 TX Vref=28, minBit 2, minWin=28, winSum=455
1247 12:14:31.699927 TX Vref=30, minBit 2, minWin=28, winSum=457
1248 12:14:31.706685 TX Vref=32, minBit 2, minWin=28, winSum=456
1249 12:14:31.709933 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 30
1250 12:14:31.710527
1251 12:14:31.713892 Final TX Range 1 Vref 30
1252 12:14:31.714453
1253 12:14:31.714821 ==
1254 12:14:31.716102 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 12:14:31.719369 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1256 12:14:31.719837 ==
1257 12:14:31.723311
1258 12:14:31.723768
1259 12:14:31.724137 TX Vref Scan disable
1260 12:14:31.726532 == TX Byte 0 ==
1261 12:14:31.729561 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1262 12:14:31.733272 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1263 12:14:31.736877 == TX Byte 1 ==
1264 12:14:31.739978 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1265 12:14:31.742988 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1266 12:14:31.746645
1267 12:14:31.747105 [DATLAT]
1268 12:14:31.747678 Freq=800, CH0 RK1
1269 12:14:31.748065
1270 12:14:31.750545 DATLAT Default: 0x9
1271 12:14:31.751104 0, 0xFFFF, sum = 0
1272 12:14:31.753859 1, 0xFFFF, sum = 0
1273 12:14:31.754419 2, 0xFFFF, sum = 0
1274 12:14:31.756265 3, 0xFFFF, sum = 0
1275 12:14:31.756853 4, 0xFFFF, sum = 0
1276 12:14:31.759706 5, 0xFFFF, sum = 0
1277 12:14:31.760269 6, 0xFFFF, sum = 0
1278 12:14:31.763355 7, 0xFFFF, sum = 0
1279 12:14:31.763918 8, 0x0, sum = 1
1280 12:14:31.766265 9, 0x0, sum = 2
1281 12:14:31.766736 10, 0x0, sum = 3
1282 12:14:31.770261 11, 0x0, sum = 4
1283 12:14:31.770817 best_step = 9
1284 12:14:31.771180
1285 12:14:31.771524 ==
1286 12:14:31.773307 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 12:14:31.779887 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1288 12:14:31.780356 ==
1289 12:14:31.780771 RX Vref Scan: 0
1290 12:14:31.781132
1291 12:14:31.783588 RX Vref 0 -> 0, step: 1
1292 12:14:31.784144
1293 12:14:31.786611 RX Delay -111 -> 252, step: 8
1294 12:14:31.790011 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1295 12:14:31.792987 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1296 12:14:31.800701 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1297 12:14:31.803947 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1298 12:14:31.806765 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1299 12:14:31.810190 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1300 12:14:31.813520 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1301 12:14:31.819347 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1302 12:14:31.823239 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1303 12:14:31.825991 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1304 12:14:31.829989 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1305 12:14:31.833098 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1306 12:14:31.840049 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1307 12:14:31.842991 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1308 12:14:31.846417 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1309 12:14:31.849558 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1310 12:14:31.850116 ==
1311 12:14:31.852924 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 12:14:31.856887 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1313 12:14:31.859380 ==
1314 12:14:31.859941 DQS Delay:
1315 12:14:31.860311 DQS0 = 0, DQS1 = 0
1316 12:14:31.863315 DQM Delay:
1317 12:14:31.863878 DQM0 = 86, DQM1 = 75
1318 12:14:31.866887 DQ Delay:
1319 12:14:31.867446 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =84
1320 12:14:31.870034 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1321 12:14:31.873467 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1322 12:14:31.877194 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1323 12:14:31.877751
1324 12:14:31.879594
1325 12:14:31.887547 [DQSOSCAuto] RK1, (LSB)MR18= 0x4343, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1326 12:14:31.889862 CH0 RK1: MR19=606, MR18=4343
1327 12:14:31.896376 CH0_RK1: MR19=0x606, MR18=0x4343, DQSOSC=393, MR23=63, INC=95, DEC=63
1328 12:14:31.897024 [RxdqsGatingPostProcess] freq 800
1329 12:14:31.902932 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1330 12:14:31.906742 Pre-setting of DQS Precalculation
1331 12:14:31.909562 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1332 12:14:31.913007 ==
1333 12:14:31.913470 Dram Type= 6, Freq= 0, CH_1, rank 0
1334 12:14:31.919713 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1335 12:14:31.920179 ==
1336 12:14:31.922726 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1337 12:14:31.929401 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1338 12:14:31.938893 [CA 0] Center 37 (6~68) winsize 63
1339 12:14:31.942809 [CA 1] Center 37 (6~68) winsize 63
1340 12:14:31.945702 [CA 2] Center 34 (4~65) winsize 62
1341 12:14:31.950536 [CA 3] Center 34 (4~65) winsize 62
1342 12:14:31.952891 [CA 4] Center 33 (3~64) winsize 62
1343 12:14:31.956109 [CA 5] Center 33 (3~64) winsize 62
1344 12:14:31.956508
1345 12:14:31.960005 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1346 12:14:31.960569
1347 12:14:31.961988 [CATrainingPosCal] consider 1 rank data
1348 12:14:31.965905 u2DelayCellTimex100 = 270/100 ps
1349 12:14:31.969308 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1350 12:14:31.972149 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1351 12:14:31.979451 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1352 12:14:31.982292 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1353 12:14:31.985954 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1354 12:14:31.989077 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1355 12:14:31.989628
1356 12:14:31.992160 CA PerBit enable=1, Macro0, CA PI delay=33
1357 12:14:31.992727
1358 12:14:31.995687 [CBTSetCACLKResult] CA Dly = 33
1359 12:14:31.996240 CS Dly: 5 (0~36)
1360 12:14:31.998823 ==
1361 12:14:32.002529 Dram Type= 6, Freq= 0, CH_1, rank 1
1362 12:14:32.006226 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1363 12:14:32.006780 ==
1364 12:14:32.009550 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1365 12:14:32.015130 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1366 12:14:32.024843 [CA 0] Center 36 (6~67) winsize 62
1367 12:14:32.028170 [CA 1] Center 37 (6~68) winsize 63
1368 12:14:32.032018 [CA 2] Center 34 (4~65) winsize 62
1369 12:14:32.034932 [CA 3] Center 34 (4~65) winsize 62
1370 12:14:32.038575 [CA 4] Center 33 (3~64) winsize 62
1371 12:14:32.042508 [CA 5] Center 33 (3~64) winsize 62
1372 12:14:32.043066
1373 12:14:32.045113 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1374 12:14:32.045565
1375 12:14:32.049601 [CATrainingPosCal] consider 2 rank data
1376 12:14:32.051342 u2DelayCellTimex100 = 270/100 ps
1377 12:14:32.055716 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1378 12:14:32.058096 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1379 12:14:32.065051 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1380 12:14:32.068073 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1381 12:14:32.071751 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1382 12:14:32.075510 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1383 12:14:32.075983
1384 12:14:32.078696 CA PerBit enable=1, Macro0, CA PI delay=33
1385 12:14:32.079256
1386 12:14:32.081337 [CBTSetCACLKResult] CA Dly = 33
1387 12:14:32.081790 CS Dly: 5 (0~36)
1388 12:14:32.082150
1389 12:14:32.085240 ----->DramcWriteLeveling(PI) begin...
1390 12:14:32.088194 ==
1391 12:14:32.091593 Dram Type= 6, Freq= 0, CH_1, rank 0
1392 12:14:32.094876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1393 12:14:32.095432 ==
1394 12:14:32.097989 Write leveling (Byte 0): 24 => 24
1395 12:14:32.101359 Write leveling (Byte 1): 24 => 24
1396 12:14:32.105414 DramcWriteLeveling(PI) end<-----
1397 12:14:32.105969
1398 12:14:32.106323 ==
1399 12:14:32.109103 Dram Type= 6, Freq= 0, CH_1, rank 0
1400 12:14:32.111353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1401 12:14:32.111813 ==
1402 12:14:32.115514 [Gating] SW mode calibration
1403 12:14:32.121491 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1404 12:14:32.125365 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1405 12:14:32.132489 0 6 0 | B1->B0 | 3030 2929 | 0 1 | (0 1) (1 0)
1406 12:14:32.135244 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1407 12:14:32.137989 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1408 12:14:32.145758 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1409 12:14:32.148575 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1410 12:14:32.151880 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1411 12:14:32.158599 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1412 12:14:32.161629 0 6 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1413 12:14:32.165331 0 7 0 | B1->B0 | 2929 4242 | 0 0 | (0 0) (0 0)
1414 12:14:32.171933 0 7 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1415 12:14:32.176374 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1416 12:14:32.178144 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1417 12:14:32.185395 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1418 12:14:32.188452 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1419 12:14:32.191497 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1420 12:14:32.198613 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1421 12:14:32.201920 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1422 12:14:32.204963 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1423 12:14:32.208595 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1424 12:14:32.214810 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1425 12:14:32.218557 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1426 12:14:32.221191 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1427 12:14:32.227881 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1428 12:14:32.231267 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1429 12:14:32.234858 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1430 12:14:32.241670 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1431 12:14:32.244878 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1432 12:14:32.248125 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1433 12:14:32.255106 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1434 12:14:32.258193 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1435 12:14:32.261642 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1436 12:14:32.268704 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1437 12:14:32.271343 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1438 12:14:32.275221 Total UI for P1: 0, mck2ui 16
1439 12:14:32.278610 best dqsien dly found for B0: ( 0, 9, 28)
1440 12:14:32.281400 Total UI for P1: 0, mck2ui 16
1441 12:14:32.285086 best dqsien dly found for B1: ( 0, 9, 30)
1442 12:14:32.288297 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1443 12:14:32.291650 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1444 12:14:32.292204
1445 12:14:32.295070 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1446 12:14:32.298047 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1447 12:14:32.301422 [Gating] SW calibration Done
1448 12:14:32.302079 ==
1449 12:14:32.304703 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 12:14:32.308189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1451 12:14:32.311683 ==
1452 12:14:32.312249 RX Vref Scan: 0
1453 12:14:32.312621
1454 12:14:32.314532 RX Vref 0 -> 0, step: 1
1455 12:14:32.314993
1456 12:14:32.318214 RX Delay -130 -> 252, step: 16
1457 12:14:32.321821 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1458 12:14:32.324840 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1459 12:14:32.328829 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1460 12:14:32.331125 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1461 12:14:32.338341 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1462 12:14:32.341366 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1463 12:14:32.344677 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1464 12:14:32.348069 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1465 12:14:32.351752 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1466 12:14:32.354741 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1467 12:14:32.361179 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1468 12:14:32.364520 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1469 12:14:32.368638 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1470 12:14:32.371190 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1471 12:14:32.378116 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1472 12:14:32.381245 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1473 12:14:32.381708 ==
1474 12:14:32.384789 Dram Type= 6, Freq= 0, CH_1, rank 0
1475 12:14:32.388041 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1476 12:14:32.388506 ==
1477 12:14:32.391720 DQS Delay:
1478 12:14:32.392177 DQS0 = 0, DQS1 = 0
1479 12:14:32.392544 DQM Delay:
1480 12:14:32.394601 DQM0 = 80, DQM1 = 74
1481 12:14:32.395161 DQ Delay:
1482 12:14:32.398557 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1483 12:14:32.401443 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1484 12:14:32.404828 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1485 12:14:32.408021 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =85
1486 12:14:32.408590
1487 12:14:32.409002
1488 12:14:32.409343 ==
1489 12:14:32.411434 Dram Type= 6, Freq= 0, CH_1, rank 0
1490 12:14:32.414922 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1491 12:14:32.417698 ==
1492 12:14:32.418156
1493 12:14:32.418521
1494 12:14:32.418858 TX Vref Scan disable
1495 12:14:32.421651 == TX Byte 0 ==
1496 12:14:32.425695 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1497 12:14:32.428633 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1498 12:14:32.431442 == TX Byte 1 ==
1499 12:14:32.434653 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1500 12:14:32.438484 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1501 12:14:32.439054 ==
1502 12:14:32.442092 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 12:14:32.447565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1504 12:14:32.448111 ==
1505 12:14:32.460500 TX Vref=22, minBit 2, minWin=27, winSum=447
1506 12:14:32.463134 TX Vref=24, minBit 0, minWin=28, winSum=450
1507 12:14:32.466498 TX Vref=26, minBit 0, minWin=28, winSum=456
1508 12:14:32.470295 TX Vref=28, minBit 0, minWin=28, winSum=456
1509 12:14:32.473537 TX Vref=30, minBit 0, minWin=28, winSum=459
1510 12:14:32.476186 TX Vref=32, minBit 0, minWin=28, winSum=458
1511 12:14:32.482854 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
1512 12:14:32.483404
1513 12:14:32.486942 Final TX Range 1 Vref 30
1514 12:14:32.487511
1515 12:14:32.487874 ==
1516 12:14:32.490529 Dram Type= 6, Freq= 0, CH_1, rank 0
1517 12:14:32.493356 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1518 12:14:32.493817 ==
1519 12:14:32.496908
1520 12:14:32.497458
1521 12:14:32.497828 TX Vref Scan disable
1522 12:14:32.499462 == TX Byte 0 ==
1523 12:14:32.504116 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1524 12:14:32.510197 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1525 12:14:32.510782 == TX Byte 1 ==
1526 12:14:32.513502 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1527 12:14:32.516061 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1528 12:14:32.519664
1529 12:14:32.520215 [DATLAT]
1530 12:14:32.520583 Freq=800, CH1 RK0
1531 12:14:32.520992
1532 12:14:32.523071 DATLAT Default: 0xa
1533 12:14:32.523627 0, 0xFFFF, sum = 0
1534 12:14:32.526499 1, 0xFFFF, sum = 0
1535 12:14:32.527065 2, 0xFFFF, sum = 0
1536 12:14:32.529861 3, 0xFFFF, sum = 0
1537 12:14:32.530326 4, 0xFFFF, sum = 0
1538 12:14:32.533289 5, 0xFFFF, sum = 0
1539 12:14:32.533752 6, 0xFFFF, sum = 0
1540 12:14:32.536908 7, 0xFFFF, sum = 0
1541 12:14:32.537470 8, 0x0, sum = 1
1542 12:14:32.539824 9, 0x0, sum = 2
1543 12:14:32.540385 10, 0x0, sum = 3
1544 12:14:32.543342 11, 0x0, sum = 4
1545 12:14:32.543900 best_step = 9
1546 12:14:32.544267
1547 12:14:32.544607 ==
1548 12:14:32.546192 Dram Type= 6, Freq= 0, CH_1, rank 0
1549 12:14:32.553501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1550 12:14:32.554060 ==
1551 12:14:32.554432 RX Vref Scan: 1
1552 12:14:32.554775
1553 12:14:32.556604 Set Vref Range= 32 -> 127
1554 12:14:32.557220
1555 12:14:32.560241 RX Vref 32 -> 127, step: 1
1556 12:14:32.560700
1557 12:14:32.561121 RX Delay -95 -> 252, step: 8
1558 12:14:32.565116
1559 12:14:32.565671 Set Vref, RX VrefLevel [Byte0]: 32
1560 12:14:32.566440 [Byte1]: 32
1561 12:14:32.570480
1562 12:14:32.570938 Set Vref, RX VrefLevel [Byte0]: 33
1563 12:14:32.573769 [Byte1]: 33
1564 12:14:32.578392
1565 12:14:32.578945 Set Vref, RX VrefLevel [Byte0]: 34
1566 12:14:32.581708 [Byte1]: 34
1567 12:14:32.585885
1568 12:14:32.586341 Set Vref, RX VrefLevel [Byte0]: 35
1569 12:14:32.589276 [Byte1]: 35
1570 12:14:32.593987
1571 12:14:32.594545 Set Vref, RX VrefLevel [Byte0]: 36
1572 12:14:32.597301 [Byte1]: 36
1573 12:14:32.601178
1574 12:14:32.601736 Set Vref, RX VrefLevel [Byte0]: 37
1575 12:14:32.604501 [Byte1]: 37
1576 12:14:32.608661
1577 12:14:32.609271 Set Vref, RX VrefLevel [Byte0]: 38
1578 12:14:32.612483 [Byte1]: 38
1579 12:14:32.615991
1580 12:14:32.616450 Set Vref, RX VrefLevel [Byte0]: 39
1581 12:14:32.619788 [Byte1]: 39
1582 12:14:32.624482
1583 12:14:32.624993 Set Vref, RX VrefLevel [Byte0]: 40
1584 12:14:32.627288 [Byte1]: 40
1585 12:14:32.631267
1586 12:14:32.631829 Set Vref, RX VrefLevel [Byte0]: 41
1587 12:14:32.634416 [Byte1]: 41
1588 12:14:32.640195
1589 12:14:32.640780 Set Vref, RX VrefLevel [Byte0]: 42
1590 12:14:32.642184 [Byte1]: 42
1591 12:14:32.646586
1592 12:14:32.647147 Set Vref, RX VrefLevel [Byte0]: 43
1593 12:14:32.649535 [Byte1]: 43
1594 12:14:32.654774
1595 12:14:32.655340 Set Vref, RX VrefLevel [Byte0]: 44
1596 12:14:32.657069 [Byte1]: 44
1597 12:14:32.661680
1598 12:14:32.662253 Set Vref, RX VrefLevel [Byte0]: 45
1599 12:14:32.665304 [Byte1]: 45
1600 12:14:32.669923
1601 12:14:32.670476 Set Vref, RX VrefLevel [Byte0]: 46
1602 12:14:32.673160 [Byte1]: 46
1603 12:14:32.676790
1604 12:14:32.677300 Set Vref, RX VrefLevel [Byte0]: 47
1605 12:14:32.680303 [Byte1]: 47
1606 12:14:32.685267
1607 12:14:32.685724 Set Vref, RX VrefLevel [Byte0]: 48
1608 12:14:32.688075 [Byte1]: 48
1609 12:14:32.692168
1610 12:14:32.692769 Set Vref, RX VrefLevel [Byte0]: 49
1611 12:14:32.696444 [Byte1]: 49
1612 12:14:32.700090
1613 12:14:32.700646 Set Vref, RX VrefLevel [Byte0]: 50
1614 12:14:32.703134 [Byte1]: 50
1615 12:14:32.707718
1616 12:14:32.708272 Set Vref, RX VrefLevel [Byte0]: 51
1617 12:14:32.710560 [Byte1]: 51
1618 12:14:32.715648
1619 12:14:32.716358 Set Vref, RX VrefLevel [Byte0]: 52
1620 12:14:32.718126 [Byte1]: 52
1621 12:14:32.722509
1622 12:14:32.723085 Set Vref, RX VrefLevel [Byte0]: 53
1623 12:14:32.726013 [Byte1]: 53
1624 12:14:32.730140
1625 12:14:32.730693 Set Vref, RX VrefLevel [Byte0]: 54
1626 12:14:32.733621 [Byte1]: 54
1627 12:14:32.738180
1628 12:14:32.738746 Set Vref, RX VrefLevel [Byte0]: 55
1629 12:14:32.741009 [Byte1]: 55
1630 12:14:32.745666
1631 12:14:32.746229 Set Vref, RX VrefLevel [Byte0]: 56
1632 12:14:32.748594 [Byte1]: 56
1633 12:14:32.753081
1634 12:14:32.753644 Set Vref, RX VrefLevel [Byte0]: 57
1635 12:14:32.756685 [Byte1]: 57
1636 12:14:32.760342
1637 12:14:32.760959 Set Vref, RX VrefLevel [Byte0]: 58
1638 12:14:32.763951 [Byte1]: 58
1639 12:14:32.768428
1640 12:14:32.769045 Set Vref, RX VrefLevel [Byte0]: 59
1641 12:14:32.771554 [Byte1]: 59
1642 12:14:32.775707
1643 12:14:32.776171 Set Vref, RX VrefLevel [Byte0]: 60
1644 12:14:32.780441 [Byte1]: 60
1645 12:14:32.783362
1646 12:14:32.783827 Set Vref, RX VrefLevel [Byte0]: 61
1647 12:14:32.786924 [Byte1]: 61
1648 12:14:32.791165
1649 12:14:32.791735 Set Vref, RX VrefLevel [Byte0]: 62
1650 12:14:32.794201 [Byte1]: 62
1651 12:14:32.798718
1652 12:14:32.799283 Set Vref, RX VrefLevel [Byte0]: 63
1653 12:14:32.802228 [Byte1]: 63
1654 12:14:32.806206
1655 12:14:32.806770 Set Vref, RX VrefLevel [Byte0]: 64
1656 12:14:32.809627 [Byte1]: 64
1657 12:14:32.813552
1658 12:14:32.814048 Set Vref, RX VrefLevel [Byte0]: 65
1659 12:14:32.816547 [Byte1]: 65
1660 12:14:32.821174
1661 12:14:32.821754 Set Vref, RX VrefLevel [Byte0]: 66
1662 12:14:32.824514 [Byte1]: 66
1663 12:14:32.828589
1664 12:14:32.829103 Set Vref, RX VrefLevel [Byte0]: 67
1665 12:14:32.832166 [Byte1]: 67
1666 12:14:32.836493
1667 12:14:32.837080 Set Vref, RX VrefLevel [Byte0]: 68
1668 12:14:32.840243 [Byte1]: 68
1669 12:14:32.844082
1670 12:14:32.844643 Set Vref, RX VrefLevel [Byte0]: 69
1671 12:14:32.847765 [Byte1]: 69
1672 12:14:32.852499
1673 12:14:32.853103 Set Vref, RX VrefLevel [Byte0]: 70
1674 12:14:32.855270 [Byte1]: 70
1675 12:14:32.859876
1676 12:14:32.860439 Set Vref, RX VrefLevel [Byte0]: 71
1677 12:14:32.862815 [Byte1]: 71
1678 12:14:32.866810
1679 12:14:32.867366 Set Vref, RX VrefLevel [Byte0]: 72
1680 12:14:32.870913 [Byte1]: 72
1681 12:14:32.874793
1682 12:14:32.875360 Set Vref, RX VrefLevel [Byte0]: 73
1683 12:14:32.878006 [Byte1]: 73
1684 12:14:32.882643
1685 12:14:32.883210 Set Vref, RX VrefLevel [Byte0]: 74
1686 12:14:32.886353 [Byte1]: 74
1687 12:14:32.889431
1688 12:14:32.889892 Set Vref, RX VrefLevel [Byte0]: 75
1689 12:14:32.893187 [Byte1]: 75
1690 12:14:32.897611
1691 12:14:32.898172 Set Vref, RX VrefLevel [Byte0]: 76
1692 12:14:32.900463 [Byte1]: 76
1693 12:14:32.904965
1694 12:14:32.905524 Set Vref, RX VrefLevel [Byte0]: 77
1695 12:14:32.908432 [Byte1]: 77
1696 12:14:32.912379
1697 12:14:32.912983 Set Vref, RX VrefLevel [Byte0]: 78
1698 12:14:32.916315 [Byte1]: 78
1699 12:14:32.920670
1700 12:14:32.921278 Set Vref, RX VrefLevel [Byte0]: 79
1701 12:14:32.923711 [Byte1]: 79
1702 12:14:32.927229
1703 12:14:32.927688 Set Vref, RX VrefLevel [Byte0]: 80
1704 12:14:32.931095 [Byte1]: 80
1705 12:14:32.935083
1706 12:14:32.935645 Set Vref, RX VrefLevel [Byte0]: 81
1707 12:14:32.938540 [Byte1]: 81
1708 12:14:32.943167
1709 12:14:32.943730 Final RX Vref Byte 0 = 62 to rank0
1710 12:14:32.946444 Final RX Vref Byte 1 = 59 to rank0
1711 12:14:32.949533 Final RX Vref Byte 0 = 62 to rank1
1712 12:14:32.953125 Final RX Vref Byte 1 = 59 to rank1==
1713 12:14:32.956699 Dram Type= 6, Freq= 0, CH_1, rank 0
1714 12:14:32.963339 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1715 12:14:32.963904 ==
1716 12:14:32.964277 DQS Delay:
1717 12:14:32.964623 DQS0 = 0, DQS1 = 0
1718 12:14:32.967290 DQM Delay:
1719 12:14:32.967858 DQM0 = 80, DQM1 = 75
1720 12:14:32.969283 DQ Delay:
1721 12:14:32.972804 DQ0 =88, DQ1 =72, DQ2 =72, DQ3 =76
1722 12:14:32.976767 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1723 12:14:32.980031 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1724 12:14:32.982908 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1725 12:14:32.983539
1726 12:14:32.983932
1727 12:14:32.989706 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d4d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1728 12:14:32.993044 CH1 RK0: MR19=606, MR18=4D4D
1729 12:14:32.999094 CH1_RK0: MR19=0x606, MR18=0x4D4D, DQSOSC=390, MR23=63, INC=97, DEC=64
1730 12:14:32.999646
1731 12:14:33.002332 ----->DramcWriteLeveling(PI) begin...
1732 12:14:33.002902 ==
1733 12:14:33.005831 Dram Type= 6, Freq= 0, CH_1, rank 1
1734 12:14:33.009256 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1735 12:14:33.009745 ==
1736 12:14:33.012387 Write leveling (Byte 0): 26 => 26
1737 12:14:33.015804 Write leveling (Byte 1): 24 => 24
1738 12:14:33.018802 DramcWriteLeveling(PI) end<-----
1739 12:14:33.019267
1740 12:14:33.019633 ==
1741 12:14:33.022523 Dram Type= 6, Freq= 0, CH_1, rank 1
1742 12:14:33.026156 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1743 12:14:33.026626 ==
1744 12:14:33.029121 [Gating] SW mode calibration
1745 12:14:33.036280 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1746 12:14:33.043010 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1747 12:14:33.045926 0 6 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1748 12:14:33.049181 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1749 12:14:33.055677 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1750 12:14:33.058708 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1751 12:14:33.062409 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1752 12:14:33.069283 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1753 12:14:33.072388 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1754 12:14:33.075400 0 6 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1755 12:14:33.082648 0 7 0 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
1756 12:14:33.085881 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1757 12:14:33.089845 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1758 12:14:33.095794 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1759 12:14:33.099120 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1760 12:14:33.102809 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1761 12:14:33.108748 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1762 12:14:33.112243 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1763 12:14:33.115701 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1764 12:14:33.122345 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1765 12:14:33.125579 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1766 12:14:33.129882 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1767 12:14:33.135841 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1768 12:14:33.139756 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1769 12:14:33.143107 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1770 12:14:33.149168 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1771 12:14:33.152255 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1772 12:14:33.155669 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1773 12:14:33.161913 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1774 12:14:33.165685 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1775 12:14:33.168949 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1776 12:14:33.171875 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1777 12:14:33.178578 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1778 12:14:33.182197 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1779 12:14:33.185251 Total UI for P1: 0, mck2ui 16
1780 12:14:33.188951 best dqsien dly found for B0: ( 0, 9, 26)
1781 12:14:33.192307 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1782 12:14:33.200220 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1783 12:14:33.202838 Total UI for P1: 0, mck2ui 16
1784 12:14:33.205849 best dqsien dly found for B1: ( 0, 9, 30)
1785 12:14:33.208636 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1786 12:14:33.213619 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1787 12:14:33.214185
1788 12:14:33.215943 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1789 12:14:33.218743 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1790 12:14:33.223050 [Gating] SW calibration Done
1791 12:14:33.223614 ==
1792 12:14:33.225069 Dram Type= 6, Freq= 0, CH_1, rank 1
1793 12:14:33.228557 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1794 12:14:33.229073 ==
1795 12:14:33.231989 RX Vref Scan: 0
1796 12:14:33.232551
1797 12:14:33.233004 RX Vref 0 -> 0, step: 1
1798 12:14:33.235195
1799 12:14:33.235761 RX Delay -130 -> 252, step: 16
1800 12:14:33.242413 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1801 12:14:33.245220 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1802 12:14:33.248617 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1803 12:14:33.252247 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1804 12:14:33.255359 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1805 12:14:33.261747 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1806 12:14:33.265590 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1807 12:14:33.268880 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1808 12:14:33.271887 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1809 12:14:33.275909 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1810 12:14:33.281710 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1811 12:14:33.284894 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1812 12:14:33.288360 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1813 12:14:33.291988 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1814 12:14:33.295301 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1815 12:14:33.302107 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1816 12:14:33.302670 ==
1817 12:14:33.305094 Dram Type= 6, Freq= 0, CH_1, rank 1
1818 12:14:33.308792 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1819 12:14:33.309362 ==
1820 12:14:33.309732 DQS Delay:
1821 12:14:33.311652 DQS0 = 0, DQS1 = 0
1822 12:14:33.312214 DQM Delay:
1823 12:14:33.316116 DQM0 = 85, DQM1 = 73
1824 12:14:33.316687 DQ Delay:
1825 12:14:33.318893 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1826 12:14:33.322364 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1827 12:14:33.325171 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1828 12:14:33.328783 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1829 12:14:33.329243
1830 12:14:33.329604
1831 12:14:33.329942 ==
1832 12:14:33.331496 Dram Type= 6, Freq= 0, CH_1, rank 1
1833 12:14:33.335309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1834 12:14:33.335955 ==
1835 12:14:33.336335
1836 12:14:33.338667
1837 12:14:33.339131 TX Vref Scan disable
1838 12:14:33.342219 == TX Byte 0 ==
1839 12:14:33.345313 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1840 12:14:33.348801 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1841 12:14:33.351577 == TX Byte 1 ==
1842 12:14:33.355163 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1843 12:14:33.358577 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1844 12:14:33.359152 ==
1845 12:14:33.361789 Dram Type= 6, Freq= 0, CH_1, rank 1
1846 12:14:33.368868 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1847 12:14:33.369427 ==
1848 12:14:33.380449 TX Vref=22, minBit 0, minWin=27, winSum=449
1849 12:14:33.383323 TX Vref=24, minBit 8, minWin=27, winSum=453
1850 12:14:33.386545 TX Vref=26, minBit 0, minWin=28, winSum=456
1851 12:14:33.390527 TX Vref=28, minBit 0, minWin=28, winSum=456
1852 12:14:33.393647 TX Vref=30, minBit 3, minWin=28, winSum=456
1853 12:14:33.401334 TX Vref=32, minBit 9, minWin=27, winSum=455
1854 12:14:33.403720 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 26
1855 12:14:33.404282
1856 12:14:33.406694 Final TX Range 1 Vref 26
1857 12:14:33.407254
1858 12:14:33.407629 ==
1859 12:14:33.410038 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 12:14:33.413892 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1861 12:14:33.414458 ==
1862 12:14:33.416901
1863 12:14:33.417466
1864 12:14:33.417836 TX Vref Scan disable
1865 12:14:33.420575 == TX Byte 0 ==
1866 12:14:33.423232 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1867 12:14:33.430192 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1868 12:14:33.430765 == TX Byte 1 ==
1869 12:14:33.433309 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1870 12:14:33.440530 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1871 12:14:33.441062
1872 12:14:33.441434 [DATLAT]
1873 12:14:33.441778 Freq=800, CH1 RK1
1874 12:14:33.442109
1875 12:14:33.443433 DATLAT Default: 0x9
1876 12:14:33.443897 0, 0xFFFF, sum = 0
1877 12:14:33.447021 1, 0xFFFF, sum = 0
1878 12:14:33.447492 2, 0xFFFF, sum = 0
1879 12:14:33.450403 3, 0xFFFF, sum = 0
1880 12:14:33.450881 4, 0xFFFF, sum = 0
1881 12:14:33.453123 5, 0xFFFF, sum = 0
1882 12:14:33.457201 6, 0xFFFF, sum = 0
1883 12:14:33.457775 7, 0xFFFF, sum = 0
1884 12:14:33.458153 8, 0x0, sum = 1
1885 12:14:33.459920 9, 0x0, sum = 2
1886 12:14:33.460389 10, 0x0, sum = 3
1887 12:14:33.463727 11, 0x0, sum = 4
1888 12:14:33.464295 best_step = 9
1889 12:14:33.464666
1890 12:14:33.465097 ==
1891 12:14:33.466957 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 12:14:33.473434 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1893 12:14:33.473906 ==
1894 12:14:33.474277 RX Vref Scan: 0
1895 12:14:33.474620
1896 12:14:33.476578 RX Vref 0 -> 0, step: 1
1897 12:14:33.477083
1898 12:14:33.480337 RX Delay -111 -> 252, step: 8
1899 12:14:33.483249 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1900 12:14:33.486409 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1901 12:14:33.493659 iDelay=209, Bit 2, Center 72 (-47 ~ 192) 240
1902 12:14:33.496304 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1903 12:14:33.500336 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1904 12:14:33.503628 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1905 12:14:33.506992 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1906 12:14:33.513408 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1907 12:14:33.516494 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1908 12:14:33.520990 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1909 12:14:33.523807 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1910 12:14:33.526466 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1911 12:14:33.532895 iDelay=209, Bit 12, Center 88 (-31 ~ 208) 240
1912 12:14:33.537128 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1913 12:14:33.539861 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1914 12:14:33.543563 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1915 12:14:33.544135 ==
1916 12:14:33.546690 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 12:14:33.553089 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1918 12:14:33.553661 ==
1919 12:14:33.554034 DQS Delay:
1920 12:14:33.554381 DQS0 = 0, DQS1 = 0
1921 12:14:33.556478 DQM Delay:
1922 12:14:33.557033 DQM0 = 84, DQM1 = 74
1923 12:14:33.559978 DQ Delay:
1924 12:14:33.564076 DQ0 =88, DQ1 =80, DQ2 =72, DQ3 =84
1925 12:14:33.564640 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1926 12:14:33.566577 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =68
1927 12:14:33.569727 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1928 12:14:33.573552
1929 12:14:33.574114
1930 12:14:33.579742 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d3d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1931 12:14:33.583732 CH1 RK1: MR19=606, MR18=3D3D
1932 12:14:33.590277 CH1_RK1: MR19=0x606, MR18=0x3D3D, DQSOSC=394, MR23=63, INC=95, DEC=63
1933 12:14:33.593429 [RxdqsGatingPostProcess] freq 800
1934 12:14:33.596607 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1935 12:14:33.600055 Pre-setting of DQS Precalculation
1936 12:14:33.603876 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1937 12:14:33.613660 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1938 12:14:33.619784 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1939 12:14:33.620349
1940 12:14:33.620764
1941 12:14:33.623232 [Calibration Summary] 1600 Mbps
1942 12:14:33.623693 CH 0, Rank 0
1943 12:14:33.626454 SW Impedance : PASS
1944 12:14:33.626916 DUTY Scan : NO K
1945 12:14:33.629984 ZQ Calibration : PASS
1946 12:14:33.634043 Jitter Meter : NO K
1947 12:14:33.634569 CBT Training : PASS
1948 12:14:33.636200 Write leveling : PASS
1949 12:14:33.639838 RX DQS gating : PASS
1950 12:14:33.640215 RX DQ/DQS(RDDQC) : PASS
1951 12:14:33.643529 TX DQ/DQS : PASS
1952 12:14:33.646787 RX DATLAT : PASS
1953 12:14:33.647245 RX DQ/DQS(Engine): PASS
1954 12:14:33.649993 TX OE : NO K
1955 12:14:33.650554 All Pass.
1956 12:14:33.650922
1957 12:14:33.653211 CH 0, Rank 1
1958 12:14:33.653763 SW Impedance : PASS
1959 12:14:33.656929 DUTY Scan : NO K
1960 12:14:33.660023 ZQ Calibration : PASS
1961 12:14:33.660578 Jitter Meter : NO K
1962 12:14:33.663336 CBT Training : PASS
1963 12:14:33.663889 Write leveling : PASS
1964 12:14:33.666663 RX DQS gating : PASS
1965 12:14:33.670131 RX DQ/DQS(RDDQC) : PASS
1966 12:14:33.670698 TX DQ/DQS : PASS
1967 12:14:33.673310 RX DATLAT : PASS
1968 12:14:33.676506 RX DQ/DQS(Engine): PASS
1969 12:14:33.677138 TX OE : NO K
1970 12:14:33.679929 All Pass.
1971 12:14:33.680481
1972 12:14:33.680937 CH 1, Rank 0
1973 12:14:33.683378 SW Impedance : PASS
1974 12:14:33.683938 DUTY Scan : NO K
1975 12:14:33.686814 ZQ Calibration : PASS
1976 12:14:33.689914 Jitter Meter : NO K
1977 12:14:33.690372 CBT Training : PASS
1978 12:14:33.693108 Write leveling : PASS
1979 12:14:33.696424 RX DQS gating : PASS
1980 12:14:33.697043 RX DQ/DQS(RDDQC) : PASS
1981 12:14:33.699882 TX DQ/DQS : PASS
1982 12:14:33.703188 RX DATLAT : PASS
1983 12:14:33.703742 RX DQ/DQS(Engine): PASS
1984 12:14:33.706339 TX OE : NO K
1985 12:14:33.707044 All Pass.
1986 12:14:33.707460
1987 12:14:33.709948 CH 1, Rank 1
1988 12:14:33.710407 SW Impedance : PASS
1989 12:14:33.715156 DUTY Scan : NO K
1990 12:14:33.715713 ZQ Calibration : PASS
1991 12:14:33.716988 Jitter Meter : NO K
1992 12:14:33.719647 CBT Training : PASS
1993 12:14:33.720214 Write leveling : PASS
1994 12:14:33.723661 RX DQS gating : PASS
1995 12:14:33.726082 RX DQ/DQS(RDDQC) : PASS
1996 12:14:33.726542 TX DQ/DQS : PASS
1997 12:14:33.729319 RX DATLAT : PASS
1998 12:14:33.733211 RX DQ/DQS(Engine): PASS
1999 12:14:33.733819 TX OE : NO K
2000 12:14:33.735853 All Pass.
2001 12:14:33.736312
2002 12:14:33.736674 DramC Write-DBI off
2003 12:14:33.739541 PER_BANK_REFRESH: Hybrid Mode
2004 12:14:33.742847 TX_TRACKING: ON
2005 12:14:33.746416 [GetDramInforAfterCalByMRR] Vendor 6.
2006 12:14:33.749650 [GetDramInforAfterCalByMRR] Revision 606.
2007 12:14:33.752548 [GetDramInforAfterCalByMRR] Revision 2 0.
2008 12:14:33.753177 MR0 0x3939
2009 12:14:33.753555 MR8 0x1111
2010 12:14:33.756263 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2011 12:14:33.759719
2012 12:14:33.760281 MR0 0x3939
2013 12:14:33.760653 MR8 0x1111
2014 12:14:33.762671 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2015 12:14:33.763236
2016 12:14:33.772492 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2017 12:14:33.776543 [FAST_K] Save calibration result to emmc
2018 12:14:33.779863 [FAST_K] Save calibration result to emmc
2019 12:14:33.782429 dram_init: config_dvfs: 1
2020 12:14:33.785988 dramc_set_vcore_voltage set vcore to 662500
2021 12:14:33.790188 Read voltage for 1200, 2
2022 12:14:33.790750 Vio18 = 0
2023 12:14:33.791122 Vcore = 662500
2024 12:14:33.792401 Vdram = 0
2025 12:14:33.792896 Vddq = 0
2026 12:14:33.793269 Vmddr = 0
2027 12:14:33.799396 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2028 12:14:33.803212 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2029 12:14:33.805864 MEM_TYPE=3, freq_sel=15
2030 12:14:33.809516 sv_algorithm_assistance_LP4_1600
2031 12:14:33.813059 ============ PULL DRAM RESETB DOWN ============
2032 12:14:33.815914 ========== PULL DRAM RESETB DOWN end =========
2033 12:14:33.822623 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2034 12:14:33.825595 ===================================
2035 12:14:33.826075 LPDDR4 DRAM CONFIGURATION
2036 12:14:33.829449 ===================================
2037 12:14:33.832787 EX_ROW_EN[0] = 0x0
2038 12:14:33.836486 EX_ROW_EN[1] = 0x0
2039 12:14:33.836995 LP4Y_EN = 0x0
2040 12:14:33.839504 WORK_FSP = 0x0
2041 12:14:33.839962 WL = 0x4
2042 12:14:33.842707 RL = 0x4
2043 12:14:33.843163 BL = 0x2
2044 12:14:33.846039 RPST = 0x0
2045 12:14:33.846598 RD_PRE = 0x0
2046 12:14:33.849096 WR_PRE = 0x1
2047 12:14:33.849557 WR_PST = 0x0
2048 12:14:33.853970 DBI_WR = 0x0
2049 12:14:33.854534 DBI_RD = 0x0
2050 12:14:33.855873 OTF = 0x1
2051 12:14:33.860217 ===================================
2052 12:14:33.863310 ===================================
2053 12:14:33.863876 ANA top config
2054 12:14:33.866484 ===================================
2055 12:14:33.869547 DLL_ASYNC_EN = 0
2056 12:14:33.872864 ALL_SLAVE_EN = 0
2057 12:14:33.876244 NEW_RANK_MODE = 1
2058 12:14:33.876851 DLL_IDLE_MODE = 1
2059 12:14:33.879141 LP45_APHY_COMB_EN = 1
2060 12:14:33.882710 TX_ODT_DIS = 1
2061 12:14:33.886811 NEW_8X_MODE = 1
2062 12:14:33.889574 ===================================
2063 12:14:33.892391 ===================================
2064 12:14:33.896227 data_rate = 2400
2065 12:14:33.896824 CKR = 1
2066 12:14:33.899679 DQ_P2S_RATIO = 8
2067 12:14:33.902293 ===================================
2068 12:14:33.905838 CA_P2S_RATIO = 8
2069 12:14:33.909925 DQ_CA_OPEN = 0
2070 12:14:33.912655 DQ_SEMI_OPEN = 0
2071 12:14:33.913269 CA_SEMI_OPEN = 0
2072 12:14:33.916891 CA_FULL_RATE = 0
2073 12:14:33.919455 DQ_CKDIV4_EN = 0
2074 12:14:33.922252 CA_CKDIV4_EN = 0
2075 12:14:33.926022 CA_PREDIV_EN = 0
2076 12:14:33.929463 PH8_DLY = 17
2077 12:14:33.929927 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2078 12:14:33.932404 DQ_AAMCK_DIV = 4
2079 12:14:33.935834 CA_AAMCK_DIV = 4
2080 12:14:33.939218 CA_ADMCK_DIV = 4
2081 12:14:33.942845 DQ_TRACK_CA_EN = 0
2082 12:14:33.945926 CA_PICK = 1200
2083 12:14:33.949007 CA_MCKIO = 1200
2084 12:14:33.949503 MCKIO_SEMI = 0
2085 12:14:33.952511 PLL_FREQ = 2366
2086 12:14:33.955929 DQ_UI_PI_RATIO = 32
2087 12:14:33.960098 CA_UI_PI_RATIO = 0
2088 12:14:33.962961 ===================================
2089 12:14:33.966474 ===================================
2090 12:14:33.969107 memory_type:LPDDR4
2091 12:14:33.969656 GP_NUM : 10
2092 12:14:33.973425 SRAM_EN : 1
2093 12:14:33.976017 MD32_EN : 0
2094 12:14:33.979899 ===================================
2095 12:14:33.980504 [ANA_INIT] >>>>>>>>>>>>>>
2096 12:14:33.982377 <<<<<< [CONFIGURE PHASE]: ANA_TX
2097 12:14:33.985839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2098 12:14:33.989628 ===================================
2099 12:14:33.992666 data_rate = 2400,PCW = 0X5b00
2100 12:14:33.997665 ===================================
2101 12:14:33.998994 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2102 12:14:34.006572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2103 12:14:34.009495 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2104 12:14:34.016038 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2105 12:14:34.019482 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2106 12:14:34.022855 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2107 12:14:34.023451 [ANA_INIT] flow start
2108 12:14:34.026061 [ANA_INIT] PLL >>>>>>>>
2109 12:14:34.029513 [ANA_INIT] PLL <<<<<<<<
2110 12:14:34.030075 [ANA_INIT] MIDPI >>>>>>>>
2111 12:14:34.032409 [ANA_INIT] MIDPI <<<<<<<<
2112 12:14:34.035891 [ANA_INIT] DLL >>>>>>>>
2113 12:14:34.036347 [ANA_INIT] DLL <<<<<<<<
2114 12:14:34.039386 [ANA_INIT] flow end
2115 12:14:34.042477 ============ LP4 DIFF to SE enter ============
2116 12:14:34.049129 ============ LP4 DIFF to SE exit ============
2117 12:14:34.049690 [ANA_INIT] <<<<<<<<<<<<<
2118 12:14:34.052962 [Flow] Enable top DCM control >>>>>
2119 12:14:34.055922 [Flow] Enable top DCM control <<<<<
2120 12:14:34.059983 Enable DLL master slave shuffle
2121 12:14:34.065860 ==============================================================
2122 12:14:34.066450 Gating Mode config
2123 12:14:34.072539 ==============================================================
2124 12:14:34.073173 Config description:
2125 12:14:34.082896 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2126 12:14:34.089300 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2127 12:14:34.096081 SELPH_MODE 0: By rank 1: By Phase
2128 12:14:34.103430 ==============================================================
2129 12:14:34.103987 GAT_TRACK_EN = 1
2130 12:14:34.106443 RX_GATING_MODE = 2
2131 12:14:34.109766 RX_GATING_TRACK_MODE = 2
2132 12:14:34.112342 SELPH_MODE = 1
2133 12:14:34.116369 PICG_EARLY_EN = 1
2134 12:14:34.119051 VALID_LAT_VALUE = 1
2135 12:14:34.125213 ==============================================================
2136 12:14:34.129395 Enter into Gating configuration >>>>
2137 12:14:34.132373 Exit from Gating configuration <<<<
2138 12:14:34.135692 Enter into DVFS_PRE_config >>>>>
2139 12:14:34.146014 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2140 12:14:34.148844 Exit from DVFS_PRE_config <<<<<
2141 12:14:34.152203 Enter into PICG configuration >>>>
2142 12:14:34.155187 Exit from PICG configuration <<<<
2143 12:14:34.159520 [RX_INPUT] configuration >>>>>
2144 12:14:34.159980 [RX_INPUT] configuration <<<<<
2145 12:14:34.165423 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2146 12:14:34.171902 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2147 12:14:34.175976 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2148 12:14:34.181886 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2149 12:14:34.188470 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2150 12:14:34.196070 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2151 12:14:34.198646 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2152 12:14:34.201456 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2153 12:14:34.208628 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2154 12:14:34.211909 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2155 12:14:34.215264 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2156 12:14:34.222327 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2157 12:14:34.225315 ===================================
2158 12:14:34.225778 LPDDR4 DRAM CONFIGURATION
2159 12:14:34.228405 ===================================
2160 12:14:34.232271 EX_ROW_EN[0] = 0x0
2161 12:14:34.232896 EX_ROW_EN[1] = 0x0
2162 12:14:34.235047 LP4Y_EN = 0x0
2163 12:14:34.237986 WORK_FSP = 0x0
2164 12:14:34.238445 WL = 0x4
2165 12:14:34.241698 RL = 0x4
2166 12:14:34.242247 BL = 0x2
2167 12:14:34.245224 RPST = 0x0
2168 12:14:34.245702 RD_PRE = 0x0
2169 12:14:34.248630 WR_PRE = 0x1
2170 12:14:34.249244 WR_PST = 0x0
2171 12:14:34.251956 DBI_WR = 0x0
2172 12:14:34.252516 DBI_RD = 0x0
2173 12:14:34.255279 OTF = 0x1
2174 12:14:34.258331 ===================================
2175 12:14:34.262357 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2176 12:14:34.265041 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2177 12:14:34.268500 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2178 12:14:34.271739 ===================================
2179 12:14:34.275913 LPDDR4 DRAM CONFIGURATION
2180 12:14:34.278234 ===================================
2181 12:14:34.282327 EX_ROW_EN[0] = 0x10
2182 12:14:34.282787 EX_ROW_EN[1] = 0x0
2183 12:14:34.285117 LP4Y_EN = 0x0
2184 12:14:34.285675 WORK_FSP = 0x0
2185 12:14:34.288294 WL = 0x4
2186 12:14:34.288782 RL = 0x4
2187 12:14:34.292471 BL = 0x2
2188 12:14:34.293057 RPST = 0x0
2189 12:14:34.295302 RD_PRE = 0x0
2190 12:14:34.298659 WR_PRE = 0x1
2191 12:14:34.299214 WR_PST = 0x0
2192 12:14:34.301570 DBI_WR = 0x0
2193 12:14:34.302124 DBI_RD = 0x0
2194 12:14:34.305398 OTF = 0x1
2195 12:14:34.308618 ===================================
2196 12:14:34.311985 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2197 12:14:34.315360 ==
2198 12:14:34.315918 Dram Type= 6, Freq= 0, CH_0, rank 0
2199 12:14:34.321636 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2200 12:14:34.322201 ==
2201 12:14:34.324472 [Duty_Offset_Calibration]
2202 12:14:34.324964 B0:0 B1:2 CA:1
2203 12:14:34.325331
2204 12:14:34.328500 [DutyScan_Calibration_Flow] k_type=0
2205 12:14:34.337250
2206 12:14:34.337822 ==CLK 0==
2207 12:14:34.340988 Final CLK duty delay cell = 0
2208 12:14:34.344078 [0] MAX Duty = 5093%(X100), DQS PI = 12
2209 12:14:34.347766 [0] MIN Duty = 4938%(X100), DQS PI = 52
2210 12:14:34.348325 [0] AVG Duty = 5015%(X100)
2211 12:14:34.350738
2212 12:14:34.354542 CH0 CLK Duty spec in!! Max-Min= 155%
2213 12:14:34.357521 [DutyScan_Calibration_Flow] ====Done====
2214 12:14:34.358080
2215 12:14:34.360687 [DutyScan_Calibration_Flow] k_type=1
2216 12:14:34.377092
2217 12:14:34.377664 ==DQS 0 ==
2218 12:14:34.380512 Final DQS duty delay cell = 0
2219 12:14:34.383488 [0] MAX Duty = 5125%(X100), DQS PI = 28
2220 12:14:34.387339 [0] MIN Duty = 5031%(X100), DQS PI = 4
2221 12:14:34.387893 [0] AVG Duty = 5078%(X100)
2222 12:14:34.390057
2223 12:14:34.390513 ==DQS 1 ==
2224 12:14:34.393310 Final DQS duty delay cell = 0
2225 12:14:34.396813 [0] MAX Duty = 5031%(X100), DQS PI = 52
2226 12:14:34.400510 [0] MIN Duty = 4906%(X100), DQS PI = 14
2227 12:14:34.403596 [0] AVG Duty = 4968%(X100)
2228 12:14:34.404147
2229 12:14:34.407035 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2230 12:14:34.407596
2231 12:14:34.410718 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2232 12:14:34.413090 [DutyScan_Calibration_Flow] ====Done====
2233 12:14:34.413549
2234 12:14:34.416493 [DutyScan_Calibration_Flow] k_type=3
2235 12:14:34.433169
2236 12:14:34.433747 ==DQM 0 ==
2237 12:14:34.436280 Final DQM duty delay cell = 0
2238 12:14:34.439871 [0] MAX Duty = 5156%(X100), DQS PI = 20
2239 12:14:34.443338 [0] MIN Duty = 4969%(X100), DQS PI = 54
2240 12:14:34.446651 [0] AVG Duty = 5062%(X100)
2241 12:14:34.447130
2242 12:14:34.447493 ==DQM 1 ==
2243 12:14:34.450370 Final DQM duty delay cell = 0
2244 12:14:34.453260 [0] MAX Duty = 5000%(X100), DQS PI = 56
2245 12:14:34.456000 [0] MIN Duty = 4844%(X100), DQS PI = 0
2246 12:14:34.456459 [0] AVG Duty = 4922%(X100)
2247 12:14:34.459796
2248 12:14:34.463185 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2249 12:14:34.463743
2250 12:14:34.466495 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2251 12:14:34.469358 [DutyScan_Calibration_Flow] ====Done====
2252 12:14:34.469913
2253 12:14:34.472748 [DutyScan_Calibration_Flow] k_type=2
2254 12:14:34.487915
2255 12:14:34.488535 ==DQ 0 ==
2256 12:14:34.491632 Final DQ duty delay cell = -4
2257 12:14:34.494790 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2258 12:14:34.497992 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2259 12:14:34.502160 [-4] AVG Duty = 4937%(X100)
2260 12:14:34.502720
2261 12:14:34.503080 ==DQ 1 ==
2262 12:14:34.505212 Final DQ duty delay cell = -4
2263 12:14:34.508476 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2264 12:14:34.511081 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2265 12:14:34.515135 [-4] AVG Duty = 4969%(X100)
2266 12:14:34.515697
2267 12:14:34.518502 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2268 12:14:34.519065
2269 12:14:34.521213 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2270 12:14:34.524283 [DutyScan_Calibration_Flow] ====Done====
2271 12:14:34.524774 ==
2272 12:14:34.527719 Dram Type= 6, Freq= 0, CH_1, rank 0
2273 12:14:34.531666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2274 12:14:34.532231 ==
2275 12:14:34.534908 [Duty_Offset_Calibration]
2276 12:14:34.535397 B0:0 B1:4 CA:-5
2277 12:14:34.535788
2278 12:14:34.537801 [DutyScan_Calibration_Flow] k_type=0
2279 12:14:34.548826
2280 12:14:34.549279 ==CLK 0==
2281 12:14:34.552665 Final CLK duty delay cell = 0
2282 12:14:34.555487 [0] MAX Duty = 5094%(X100), DQS PI = 24
2283 12:14:34.558345 [0] MIN Duty = 4875%(X100), DQS PI = 46
2284 12:14:34.561800 [0] AVG Duty = 4984%(X100)
2285 12:14:34.562385
2286 12:14:34.564623 CH1 CLK Duty spec in!! Max-Min= 219%
2287 12:14:34.568555 [DutyScan_Calibration_Flow] ====Done====
2288 12:14:34.569185
2289 12:14:34.572190 [DutyScan_Calibration_Flow] k_type=1
2290 12:14:34.587087
2291 12:14:34.587723 ==DQS 0 ==
2292 12:14:34.590677 Final DQS duty delay cell = 0
2293 12:14:34.593532 [0] MAX Duty = 5125%(X100), DQS PI = 16
2294 12:14:34.597254 [0] MIN Duty = 4875%(X100), DQS PI = 40
2295 12:14:34.597810 [0] AVG Duty = 5000%(X100)
2296 12:14:34.600298
2297 12:14:34.600910 ==DQS 1 ==
2298 12:14:34.604506 Final DQS duty delay cell = -4
2299 12:14:34.607067 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2300 12:14:34.610988 [-4] MIN Duty = 4876%(X100), DQS PI = 56
2301 12:14:34.613987 [-4] AVG Duty = 4938%(X100)
2302 12:14:34.614544
2303 12:14:34.617148 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2304 12:14:34.617708
2305 12:14:34.620512 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2306 12:14:34.623627 [DutyScan_Calibration_Flow] ====Done====
2307 12:14:34.624186
2308 12:14:34.627254 [DutyScan_Calibration_Flow] k_type=3
2309 12:14:34.642941
2310 12:14:34.643496 ==DQM 0 ==
2311 12:14:34.645471 Final DQM duty delay cell = -4
2312 12:14:34.648845 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2313 12:14:34.652207 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2314 12:14:34.656051 [-4] AVG Duty = 4969%(X100)
2315 12:14:34.656508
2316 12:14:34.656957 ==DQM 1 ==
2317 12:14:34.658901 Final DQM duty delay cell = -4
2318 12:14:34.662701 [-4] MAX Duty = 5093%(X100), DQS PI = 22
2319 12:14:34.666919 [-4] MIN Duty = 4875%(X100), DQS PI = 58
2320 12:14:34.668743 [-4] AVG Duty = 4984%(X100)
2321 12:14:34.669203
2322 12:14:34.673641 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2323 12:14:34.674205
2324 12:14:34.675972 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2325 12:14:34.678974 [DutyScan_Calibration_Flow] ====Done====
2326 12:14:34.679537
2327 12:14:34.682291 [DutyScan_Calibration_Flow] k_type=2
2328 12:14:34.699576
2329 12:14:34.700263 ==DQ 0 ==
2330 12:14:34.702890 Final DQ duty delay cell = 0
2331 12:14:34.706943 [0] MAX Duty = 5062%(X100), DQS PI = 0
2332 12:14:34.710247 [0] MIN Duty = 4969%(X100), DQS PI = 42
2333 12:14:34.710700 [0] AVG Duty = 5015%(X100)
2334 12:14:34.711057
2335 12:14:34.713729 ==DQ 1 ==
2336 12:14:34.716051 Final DQ duty delay cell = 0
2337 12:14:34.720069 [0] MAX Duty = 5000%(X100), DQS PI = 8
2338 12:14:34.723251 [0] MIN Duty = 4875%(X100), DQS PI = 0
2339 12:14:34.723705 [0] AVG Duty = 4937%(X100)
2340 12:14:34.724063
2341 12:14:34.726565 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2342 12:14:34.727287
2343 12:14:34.730375 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2344 12:14:34.732642 [DutyScan_Calibration_Flow] ====Done====
2345 12:14:34.738262 nWR fixed to 30
2346 12:14:34.741665 [ModeRegInit_LP4] CH0 RK0
2347 12:14:34.742117 [ModeRegInit_LP4] CH0 RK1
2348 12:14:34.744903 [ModeRegInit_LP4] CH1 RK0
2349 12:14:34.749303 [ModeRegInit_LP4] CH1 RK1
2350 12:14:34.749759 match AC timing 6
2351 12:14:34.755395 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2352 12:14:34.758478 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2353 12:14:34.761930 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2354 12:14:34.768170 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2355 12:14:34.771936 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2356 12:14:34.772388 ==
2357 12:14:34.775256 Dram Type= 6, Freq= 0, CH_0, rank 0
2358 12:14:34.779492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2359 12:14:34.780056 ==
2360 12:14:34.785563 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2361 12:14:34.791635 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2362 12:14:34.798910 [CA 0] Center 39 (9~70) winsize 62
2363 12:14:34.802352 [CA 1] Center 39 (8~70) winsize 63
2364 12:14:34.805668 [CA 2] Center 36 (5~67) winsize 63
2365 12:14:34.809252 [CA 3] Center 35 (5~66) winsize 62
2366 12:14:34.812321 [CA 4] Center 34 (3~65) winsize 63
2367 12:14:34.816648 [CA 5] Center 33 (3~64) winsize 62
2368 12:14:34.817242
2369 12:14:34.819561 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2370 12:14:34.820121
2371 12:14:34.822391 [CATrainingPosCal] consider 1 rank data
2372 12:14:34.826133 u2DelayCellTimex100 = 270/100 ps
2373 12:14:34.829038 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2374 12:14:34.832345 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2375 12:14:34.839262 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2376 12:14:34.842876 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2377 12:14:34.845479 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2378 12:14:34.849370 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2379 12:14:34.849974
2380 12:14:34.852028 CA PerBit enable=1, Macro0, CA PI delay=33
2381 12:14:34.852484
2382 12:14:34.855602 [CBTSetCACLKResult] CA Dly = 33
2383 12:14:34.856164 CS Dly: 7 (0~38)
2384 12:14:34.860299 ==
2385 12:14:34.862476 Dram Type= 6, Freq= 0, CH_0, rank 1
2386 12:14:34.867806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2387 12:14:34.868389 ==
2388 12:14:34.869176 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2389 12:14:34.875680 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2390 12:14:34.884561 [CA 0] Center 39 (8~70) winsize 63
2391 12:14:34.887643 [CA 1] Center 39 (8~70) winsize 63
2392 12:14:34.891007 [CA 2] Center 36 (5~67) winsize 63
2393 12:14:34.894927 [CA 3] Center 35 (4~66) winsize 63
2394 12:14:34.898019 [CA 4] Center 33 (3~64) winsize 62
2395 12:14:34.901096 [CA 5] Center 34 (3~65) winsize 63
2396 12:14:34.901557
2397 12:14:34.904352 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2398 12:14:34.904955
2399 12:14:34.908493 [CATrainingPosCal] consider 2 rank data
2400 12:14:34.911400 u2DelayCellTimex100 = 270/100 ps
2401 12:14:34.914996 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2402 12:14:34.918030 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2403 12:14:34.924962 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2404 12:14:34.928383 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2405 12:14:34.932375 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2406 12:14:34.935273 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2407 12:14:34.935856
2408 12:14:34.938228 CA PerBit enable=1, Macro0, CA PI delay=33
2409 12:14:34.938787
2410 12:14:34.941200 [CBTSetCACLKResult] CA Dly = 33
2411 12:14:34.941655 CS Dly: 7 (0~39)
2412 12:14:34.942015
2413 12:14:34.944965 ----->DramcWriteLeveling(PI) begin...
2414 12:14:34.947947 ==
2415 12:14:34.948503 Dram Type= 6, Freq= 0, CH_0, rank 0
2416 12:14:34.954938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2417 12:14:34.955502 ==
2418 12:14:34.958256 Write leveling (Byte 0): 27 => 27
2419 12:14:34.961092 Write leveling (Byte 1): 24 => 24
2420 12:14:34.964917 DramcWriteLeveling(PI) end<-----
2421 12:14:34.965477
2422 12:14:34.965845 ==
2423 12:14:34.967938 Dram Type= 6, Freq= 0, CH_0, rank 0
2424 12:14:34.971162 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2425 12:14:34.971726 ==
2426 12:14:34.974512 [Gating] SW mode calibration
2427 12:14:34.981944 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2428 12:14:34.984383 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2429 12:14:34.990953 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2430 12:14:34.994490 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2431 12:14:34.997781 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2432 12:14:35.004338 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2433 12:14:35.007763 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
2434 12:14:35.011399 0 11 20 | B1->B0 | 3030 2c2c | 1 0 | (1 0) (1 0)
2435 12:14:35.017809 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2436 12:14:35.021752 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2437 12:14:35.024779 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2438 12:14:35.031597 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2439 12:14:35.034887 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2440 12:14:35.037833 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2441 12:14:35.045195 0 12 16 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
2442 12:14:35.047677 0 12 20 | B1->B0 | 3c3c 4141 | 0 0 | (0 0) (0 0)
2443 12:14:35.051735 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2444 12:14:35.058099 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2445 12:14:35.061564 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2446 12:14:35.064832 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2447 12:14:35.071636 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2448 12:14:35.074735 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2449 12:14:35.077550 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2450 12:14:35.084789 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2451 12:14:35.088283 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2452 12:14:35.090673 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2453 12:14:35.094805 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2454 12:14:35.102052 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2455 12:14:35.104157 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2456 12:14:35.108308 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2457 12:14:35.114622 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2458 12:14:35.117707 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2459 12:14:35.121294 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2460 12:14:35.128659 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2461 12:14:35.130980 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2462 12:14:35.134655 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2463 12:14:35.141678 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2464 12:14:35.144140 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2465 12:14:35.147839 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2466 12:14:35.154644 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2467 12:14:35.158099 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2468 12:14:35.161409 Total UI for P1: 0, mck2ui 16
2469 12:14:35.164948 best dqsien dly found for B0: ( 0, 15, 18)
2470 12:14:35.167708 Total UI for P1: 0, mck2ui 16
2471 12:14:35.171324 best dqsien dly found for B1: ( 0, 15, 18)
2472 12:14:35.174206 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2473 12:14:35.177703 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2474 12:14:35.178373
2475 12:14:35.181343 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2476 12:14:35.184178 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2477 12:14:35.188226 [Gating] SW calibration Done
2478 12:14:35.188843 ==
2479 12:14:35.191001 Dram Type= 6, Freq= 0, CH_0, rank 0
2480 12:14:35.193973 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2481 12:14:35.197599 ==
2482 12:14:35.198307 RX Vref Scan: 0
2483 12:14:35.198835
2484 12:14:35.201762 RX Vref 0 -> 0, step: 1
2485 12:14:35.202271
2486 12:14:35.205176 RX Delay -40 -> 252, step: 8
2487 12:14:35.208104 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2488 12:14:35.211298 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2489 12:14:35.215053 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2490 12:14:35.217417 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2491 12:14:35.224181 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2492 12:14:35.227927 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2493 12:14:35.230945 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2494 12:14:35.234075 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2495 12:14:35.237427 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2496 12:14:35.241107 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2497 12:14:35.248000 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2498 12:14:35.250813 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2499 12:14:35.254476 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2500 12:14:35.257714 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2501 12:14:35.260882 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2502 12:14:35.267719 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2503 12:14:35.268278 ==
2504 12:14:35.271329 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 12:14:35.274605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2506 12:14:35.275076 ==
2507 12:14:35.275452 DQS Delay:
2508 12:14:35.277109 DQS0 = 0, DQS1 = 0
2509 12:14:35.277573 DQM Delay:
2510 12:14:35.281392 DQM0 = 116, DQM1 = 106
2511 12:14:35.281855 DQ Delay:
2512 12:14:35.284334 DQ0 =111, DQ1 =115, DQ2 =119, DQ3 =111
2513 12:14:35.287367 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2514 12:14:35.291113 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2515 12:14:35.293921 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =119
2516 12:14:35.294386
2517 12:14:35.294754
2518 12:14:35.298388 ==
2519 12:14:35.301277 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 12:14:35.304702 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2521 12:14:35.305285 ==
2522 12:14:35.305655
2523 12:14:35.306000
2524 12:14:35.307069 TX Vref Scan disable
2525 12:14:35.307530 == TX Byte 0 ==
2526 12:14:35.310891 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2527 12:14:35.317319 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2528 12:14:35.317879 == TX Byte 1 ==
2529 12:14:35.321284 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2530 12:14:35.327747 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2531 12:14:35.328325 ==
2532 12:14:35.330796 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 12:14:35.334116 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2534 12:14:35.334586 ==
2535 12:14:35.346743 TX Vref=22, minBit 10, minWin=24, winSum=415
2536 12:14:35.349481 TX Vref=24, minBit 8, minWin=25, winSum=423
2537 12:14:35.353232 TX Vref=26, minBit 9, minWin=25, winSum=428
2538 12:14:35.355839 TX Vref=28, minBit 8, minWin=26, winSum=431
2539 12:14:35.359588 TX Vref=30, minBit 5, minWin=26, winSum=431
2540 12:14:35.365888 TX Vref=32, minBit 5, minWin=26, winSum=427
2541 12:14:35.369402 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 28
2542 12:14:35.369963
2543 12:14:35.372955 Final TX Range 1 Vref 28
2544 12:14:35.373510
2545 12:14:35.373878 ==
2546 12:14:35.376045 Dram Type= 6, Freq= 0, CH_0, rank 0
2547 12:14:35.379404 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2548 12:14:35.379874 ==
2549 12:14:35.383138
2550 12:14:35.383708
2551 12:14:35.384079 TX Vref Scan disable
2552 12:14:35.386588 == TX Byte 0 ==
2553 12:14:35.389199 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2554 12:14:35.393031 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2555 12:14:35.395933 == TX Byte 1 ==
2556 12:14:35.399412 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2557 12:14:35.402469 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2558 12:14:35.406702
2559 12:14:35.407254 [DATLAT]
2560 12:14:35.407621 Freq=1200, CH0 RK0
2561 12:14:35.407963
2562 12:14:35.409430 DATLAT Default: 0xd
2563 12:14:35.409894 0, 0xFFFF, sum = 0
2564 12:14:35.413055 1, 0xFFFF, sum = 0
2565 12:14:35.413622 2, 0xFFFF, sum = 0
2566 12:14:35.416053 3, 0xFFFF, sum = 0
2567 12:14:35.416626 4, 0xFFFF, sum = 0
2568 12:14:35.419641 5, 0xFFFF, sum = 0
2569 12:14:35.420204 6, 0xFFFF, sum = 0
2570 12:14:35.422588 7, 0xFFFF, sum = 0
2571 12:14:35.426057 8, 0xFFFF, sum = 0
2572 12:14:35.426620 9, 0xFFFF, sum = 0
2573 12:14:35.429489 10, 0xFFFF, sum = 0
2574 12:14:35.430053 11, 0x0, sum = 1
2575 12:14:35.432325 12, 0x0, sum = 2
2576 12:14:35.432855 13, 0x0, sum = 3
2577 12:14:35.433246 14, 0x0, sum = 4
2578 12:14:35.435850 best_step = 12
2579 12:14:35.436309
2580 12:14:35.436673 ==
2581 12:14:35.439795 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 12:14:35.442531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2583 12:14:35.442998 ==
2584 12:14:35.445564 RX Vref Scan: 1
2585 12:14:35.446027
2586 12:14:35.449362 Set Vref Range= 32 -> 127
2587 12:14:35.449824
2588 12:14:35.450192 RX Vref 32 -> 127, step: 1
2589 12:14:35.450745
2590 12:14:35.452350 RX Delay -21 -> 252, step: 4
2591 12:14:35.452850
2592 12:14:35.455759 Set Vref, RX VrefLevel [Byte0]: 32
2593 12:14:35.459281 [Byte1]: 32
2594 12:14:35.463435
2595 12:14:35.463997 Set Vref, RX VrefLevel [Byte0]: 33
2596 12:14:35.465566 [Byte1]: 33
2597 12:14:35.470671
2598 12:14:35.471242 Set Vref, RX VrefLevel [Byte0]: 34
2599 12:14:35.473516 [Byte1]: 34
2600 12:14:35.478580
2601 12:14:35.479148 Set Vref, RX VrefLevel [Byte0]: 35
2602 12:14:35.481528 [Byte1]: 35
2603 12:14:35.486776
2604 12:14:35.487348 Set Vref, RX VrefLevel [Byte0]: 36
2605 12:14:35.489355 [Byte1]: 36
2606 12:14:35.494063
2607 12:14:35.494523 Set Vref, RX VrefLevel [Byte0]: 37
2608 12:14:35.497509 [Byte1]: 37
2609 12:14:35.501989
2610 12:14:35.502551 Set Vref, RX VrefLevel [Byte0]: 38
2611 12:14:35.505634 [Byte1]: 38
2612 12:14:35.510280
2613 12:14:35.510839 Set Vref, RX VrefLevel [Byte0]: 39
2614 12:14:35.513520 [Byte1]: 39
2615 12:14:35.518321
2616 12:14:35.518880 Set Vref, RX VrefLevel [Byte0]: 40
2617 12:14:35.522810 [Byte1]: 40
2618 12:14:35.525982
2619 12:14:35.526535 Set Vref, RX VrefLevel [Byte0]: 41
2620 12:14:35.529297 [Byte1]: 41
2621 12:14:35.534522
2622 12:14:35.535080 Set Vref, RX VrefLevel [Byte0]: 42
2623 12:14:35.537120 [Byte1]: 42
2624 12:14:35.541394
2625 12:14:35.541854 Set Vref, RX VrefLevel [Byte0]: 43
2626 12:14:35.545366 [Byte1]: 43
2627 12:14:35.549998
2628 12:14:35.550558 Set Vref, RX VrefLevel [Byte0]: 44
2629 12:14:35.553403 [Byte1]: 44
2630 12:14:35.557382
2631 12:14:35.557840 Set Vref, RX VrefLevel [Byte0]: 45
2632 12:14:35.560893 [Byte1]: 45
2633 12:14:35.565802
2634 12:14:35.566367 Set Vref, RX VrefLevel [Byte0]: 46
2635 12:14:35.569298 [Byte1]: 46
2636 12:14:35.573547
2637 12:14:35.574103 Set Vref, RX VrefLevel [Byte0]: 47
2638 12:14:35.577012 [Byte1]: 47
2639 12:14:35.581576
2640 12:14:35.582041 Set Vref, RX VrefLevel [Byte0]: 48
2641 12:14:35.584328 [Byte1]: 48
2642 12:14:35.589505
2643 12:14:35.590055 Set Vref, RX VrefLevel [Byte0]: 49
2644 12:14:35.592328 [Byte1]: 49
2645 12:14:35.597479
2646 12:14:35.598110 Set Vref, RX VrefLevel [Byte0]: 50
2647 12:14:35.600640 [Byte1]: 50
2648 12:14:35.605279
2649 12:14:35.605743 Set Vref, RX VrefLevel [Byte0]: 51
2650 12:14:35.610086 [Byte1]: 51
2651 12:14:35.613356
2652 12:14:35.613818 Set Vref, RX VrefLevel [Byte0]: 52
2653 12:14:35.616387 [Byte1]: 52
2654 12:14:35.621325
2655 12:14:35.621787 Set Vref, RX VrefLevel [Byte0]: 53
2656 12:14:35.624516 [Byte1]: 53
2657 12:14:35.628614
2658 12:14:35.629136 Set Vref, RX VrefLevel [Byte0]: 54
2659 12:14:35.632026 [Byte1]: 54
2660 12:14:35.636866
2661 12:14:35.637341 Set Vref, RX VrefLevel [Byte0]: 55
2662 12:14:35.640318 [Byte1]: 55
2663 12:14:35.645067
2664 12:14:35.645631 Set Vref, RX VrefLevel [Byte0]: 56
2665 12:14:35.651381 [Byte1]: 56
2666 12:14:35.651954
2667 12:14:35.654956 Set Vref, RX VrefLevel [Byte0]: 57
2668 12:14:35.657750 [Byte1]: 57
2669 12:14:35.658318
2670 12:14:35.661534 Set Vref, RX VrefLevel [Byte0]: 58
2671 12:14:35.664518 [Byte1]: 58
2672 12:14:35.668918
2673 12:14:35.669471 Set Vref, RX VrefLevel [Byte0]: 59
2674 12:14:35.672784 [Byte1]: 59
2675 12:14:35.676372
2676 12:14:35.676871 Set Vref, RX VrefLevel [Byte0]: 60
2677 12:14:35.679854 [Byte1]: 60
2678 12:14:35.684544
2679 12:14:35.685265 Set Vref, RX VrefLevel [Byte0]: 61
2680 12:14:35.688049 [Byte1]: 61
2681 12:14:35.693055
2682 12:14:35.693627 Set Vref, RX VrefLevel [Byte0]: 62
2683 12:14:35.695937 [Byte1]: 62
2684 12:14:35.700433
2685 12:14:35.701043 Set Vref, RX VrefLevel [Byte0]: 63
2686 12:14:35.703272 [Byte1]: 63
2687 12:14:35.708423
2688 12:14:35.709025 Set Vref, RX VrefLevel [Byte0]: 64
2689 12:14:35.711215 [Byte1]: 64
2690 12:14:35.716262
2691 12:14:35.716851 Set Vref, RX VrefLevel [Byte0]: 65
2692 12:14:35.719703 [Byte1]: 65
2693 12:14:35.724116
2694 12:14:35.724673 Set Vref, RX VrefLevel [Byte0]: 66
2695 12:14:35.727566 [Byte1]: 66
2696 12:14:35.732273
2697 12:14:35.732769 Set Vref, RX VrefLevel [Byte0]: 67
2698 12:14:35.735658 [Byte1]: 67
2699 12:14:35.740834
2700 12:14:35.741359 Final RX Vref Byte 0 = 46 to rank0
2701 12:14:35.742802 Final RX Vref Byte 1 = 50 to rank0
2702 12:14:35.746727 Final RX Vref Byte 0 = 46 to rank1
2703 12:14:35.751305 Final RX Vref Byte 1 = 50 to rank1==
2704 12:14:35.754150 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 12:14:35.757356 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2706 12:14:35.760858 ==
2707 12:14:35.761322 DQS Delay:
2708 12:14:35.761691 DQS0 = 0, DQS1 = 0
2709 12:14:35.763991 DQM Delay:
2710 12:14:35.764456 DQM0 = 114, DQM1 = 105
2711 12:14:35.766884 DQ Delay:
2712 12:14:35.770235 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2713 12:14:35.773726 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2714 12:14:35.776923 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2715 12:14:35.780472 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2716 12:14:35.781101
2717 12:14:35.781528
2718 12:14:35.786898 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2719 12:14:35.789803 CH0 RK0: MR19=404, MR18=A0A
2720 12:14:35.796863 CH0_RK0: MR19=0x404, MR18=0xA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
2721 12:14:35.797433
2722 12:14:35.801359 ----->DramcWriteLeveling(PI) begin...
2723 12:14:35.801932 ==
2724 12:14:35.803060 Dram Type= 6, Freq= 0, CH_0, rank 1
2725 12:14:35.806874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2726 12:14:35.807444 ==
2727 12:14:35.809904 Write leveling (Byte 0): 27 => 27
2728 12:14:35.814057 Write leveling (Byte 1): 26 => 26
2729 12:14:35.816379 DramcWriteLeveling(PI) end<-----
2730 12:14:35.816990
2731 12:14:35.817362 ==
2732 12:14:35.819706 Dram Type= 6, Freq= 0, CH_0, rank 1
2733 12:14:35.822642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2734 12:14:35.826387 ==
2735 12:14:35.826962 [Gating] SW mode calibration
2736 12:14:35.836062 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2737 12:14:35.839527 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2738 12:14:35.842775 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2739 12:14:35.849318 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2740 12:14:35.853006 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2741 12:14:35.855878 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2742 12:14:35.862473 0 11 16 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
2743 12:14:35.865873 0 11 20 | B1->B0 | 3333 2929 | 0 0 | (0 1) (0 0)
2744 12:14:35.869224 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2745 12:14:35.876441 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2746 12:14:35.879312 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2747 12:14:35.882670 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2748 12:14:35.889316 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2749 12:14:35.892472 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2750 12:14:35.896151 0 12 16 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
2751 12:14:35.902696 0 12 20 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2752 12:14:35.905873 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2753 12:14:35.909230 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2754 12:14:35.915923 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2755 12:14:35.919630 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2756 12:14:35.922566 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2757 12:14:35.929276 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2758 12:14:35.932127 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2759 12:14:35.935713 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2760 12:14:35.942101 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2761 12:14:35.945575 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2762 12:14:35.948831 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2763 12:14:35.955491 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2764 12:14:35.959520 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2765 12:14:35.962505 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2766 12:14:35.965201 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2767 12:14:35.971837 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2768 12:14:35.975636 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2769 12:14:35.979200 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2770 12:14:35.986094 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2771 12:14:35.989041 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2772 12:14:35.992337 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2773 12:14:35.998873 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2774 12:14:36.002797 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2775 12:14:36.006663 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2776 12:14:36.013432 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2777 12:14:36.014006 Total UI for P1: 0, mck2ui 16
2778 12:14:36.019708 best dqsien dly found for B0: ( 0, 15, 16)
2779 12:14:36.020279 Total UI for P1: 0, mck2ui 16
2780 12:14:36.025625 best dqsien dly found for B1: ( 0, 15, 18)
2781 12:14:36.029080 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2782 12:14:36.032908 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2783 12:14:36.033481
2784 12:14:36.035689 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2785 12:14:36.038713 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2786 12:14:36.042413 [Gating] SW calibration Done
2787 12:14:36.042874 ==
2788 12:14:36.045297 Dram Type= 6, Freq= 0, CH_0, rank 1
2789 12:14:36.049124 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2790 12:14:36.049694 ==
2791 12:14:36.052568 RX Vref Scan: 0
2792 12:14:36.053193
2793 12:14:36.053569 RX Vref 0 -> 0, step: 1
2794 12:14:36.053916
2795 12:14:36.055345 RX Delay -40 -> 252, step: 8
2796 12:14:36.058831 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2797 12:14:36.065590 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2798 12:14:36.069345 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2799 12:14:36.072874 iDelay=200, Bit 3, Center 107 (40 ~ 175) 136
2800 12:14:36.076316 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2801 12:14:36.079037 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2802 12:14:36.085511 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2803 12:14:36.089621 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2804 12:14:36.092250 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2805 12:14:36.095632 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2806 12:14:36.098927 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2807 12:14:36.106122 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2808 12:14:36.108914 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2809 12:14:36.113136 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2810 12:14:36.116543 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2811 12:14:36.119027 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2812 12:14:36.119582 ==
2813 12:14:36.122404 Dram Type= 6, Freq= 0, CH_0, rank 1
2814 12:14:36.129417 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2815 12:14:36.129977 ==
2816 12:14:36.130350 DQS Delay:
2817 12:14:36.132030 DQS0 = 0, DQS1 = 0
2818 12:14:36.132492 DQM Delay:
2819 12:14:36.135419 DQM0 = 114, DQM1 = 107
2820 12:14:36.136015 DQ Delay:
2821 12:14:36.138798 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =107
2822 12:14:36.142488 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2823 12:14:36.145582 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2824 12:14:36.149902 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2825 12:14:36.150461
2826 12:14:36.150826
2827 12:14:36.151165 ==
2828 12:14:36.153090 Dram Type= 6, Freq= 0, CH_0, rank 1
2829 12:14:36.156515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2830 12:14:36.159158 ==
2831 12:14:36.159720
2832 12:14:36.160092
2833 12:14:36.160432 TX Vref Scan disable
2834 12:14:36.161881 == TX Byte 0 ==
2835 12:14:36.165192 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2836 12:14:36.168911 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2837 12:14:36.172868 == TX Byte 1 ==
2838 12:14:36.175184 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2839 12:14:36.179045 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2840 12:14:36.182242 ==
2841 12:14:36.182706 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 12:14:36.189520 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2843 12:14:36.190084 ==
2844 12:14:36.199545 TX Vref=22, minBit 8, minWin=25, winSum=416
2845 12:14:36.202788 TX Vref=24, minBit 0, minWin=26, winSum=420
2846 12:14:36.206218 TX Vref=26, minBit 10, minWin=25, winSum=430
2847 12:14:36.209762 TX Vref=28, minBit 1, minWin=26, winSum=429
2848 12:14:36.212882 TX Vref=30, minBit 8, minWin=26, winSum=434
2849 12:14:36.219863 TX Vref=32, minBit 5, minWin=26, winSum=431
2850 12:14:36.222845 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
2851 12:14:36.223406
2852 12:14:36.225848 Final TX Range 1 Vref 30
2853 12:14:36.226311
2854 12:14:36.226673 ==
2855 12:14:36.229387 Dram Type= 6, Freq= 0, CH_0, rank 1
2856 12:14:36.232775 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2857 12:14:36.233248 ==
2858 12:14:36.237241
2859 12:14:36.237854
2860 12:14:36.238232 TX Vref Scan disable
2861 12:14:36.239052 == TX Byte 0 ==
2862 12:14:36.243075 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2863 12:14:36.246202 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2864 12:14:36.249406 == TX Byte 1 ==
2865 12:14:36.252488 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2866 12:14:36.256972 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2867 12:14:36.259721
2868 12:14:36.260178 [DATLAT]
2869 12:14:36.260540 Freq=1200, CH0 RK1
2870 12:14:36.260944
2871 12:14:36.262687 DATLAT Default: 0xc
2872 12:14:36.263143 0, 0xFFFF, sum = 0
2873 12:14:36.266550 1, 0xFFFF, sum = 0
2874 12:14:36.267169 2, 0xFFFF, sum = 0
2875 12:14:36.269379 3, 0xFFFF, sum = 0
2876 12:14:36.273723 4, 0xFFFF, sum = 0
2877 12:14:36.274290 5, 0xFFFF, sum = 0
2878 12:14:36.275834 6, 0xFFFF, sum = 0
2879 12:14:36.276302 7, 0xFFFF, sum = 0
2880 12:14:36.279128 8, 0xFFFF, sum = 0
2881 12:14:36.279594 9, 0xFFFF, sum = 0
2882 12:14:36.282370 10, 0xFFFF, sum = 0
2883 12:14:36.282835 11, 0x0, sum = 1
2884 12:14:36.286682 12, 0x0, sum = 2
2885 12:14:36.287256 13, 0x0, sum = 3
2886 12:14:36.289664 14, 0x0, sum = 4
2887 12:14:36.290233 best_step = 12
2888 12:14:36.290602
2889 12:14:36.290939 ==
2890 12:14:36.292816 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 12:14:36.295808 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2892 12:14:36.296271 ==
2893 12:14:36.299815 RX Vref Scan: 0
2894 12:14:36.300411
2895 12:14:36.302661 RX Vref 0 -> 0, step: 1
2896 12:14:36.303227
2897 12:14:36.303591 RX Delay -21 -> 252, step: 4
2898 12:14:36.309763 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2899 12:14:36.313994 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2900 12:14:36.316926 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2901 12:14:36.319827 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2902 12:14:36.323543 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2903 12:14:36.329933 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2904 12:14:36.333386 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2905 12:14:36.336944 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2906 12:14:36.339709 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2907 12:14:36.343840 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2908 12:14:36.349828 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
2909 12:14:36.352892 iDelay=195, Bit 11, Center 98 (39 ~ 158) 120
2910 12:14:36.356362 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
2911 12:14:36.359515 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2912 12:14:36.363736 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2913 12:14:36.370398 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
2914 12:14:36.370942 ==
2915 12:14:36.373127 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 12:14:36.377075 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2917 12:14:36.377630 ==
2918 12:14:36.378018 DQS Delay:
2919 12:14:36.380350 DQS0 = 0, DQS1 = 0
2920 12:14:36.380839 DQM Delay:
2921 12:14:36.383006 DQM0 = 114, DQM1 = 106
2922 12:14:36.383459 DQ Delay:
2923 12:14:36.386992 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2924 12:14:36.391075 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =122
2925 12:14:36.394037 DQ8 =94, DQ9 =90, DQ10 =108, DQ11 =98
2926 12:14:36.397031 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2927 12:14:36.397487
2928 12:14:36.397846
2929 12:14:36.407117 [DQSOSCAuto] RK1, (LSB)MR18= 0x1010, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2930 12:14:36.410635 CH0 RK1: MR19=404, MR18=1010
2931 12:14:36.413519 CH0_RK1: MR19=0x404, MR18=0x1010, DQSOSC=403, MR23=63, INC=40, DEC=26
2932 12:14:36.417103 [RxdqsGatingPostProcess] freq 1200
2933 12:14:36.423390 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2934 12:14:36.426697 Pre-setting of DQS Precalculation
2935 12:14:36.429680 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2936 12:14:36.430138 ==
2937 12:14:36.433558 Dram Type= 6, Freq= 0, CH_1, rank 0
2938 12:14:36.440468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2939 12:14:36.441042 ==
2940 12:14:36.443756 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2941 12:14:36.449864 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2942 12:14:36.458297 [CA 0] Center 37 (7~68) winsize 62
2943 12:14:36.461635 [CA 1] Center 37 (7~68) winsize 62
2944 12:14:36.464976 [CA 2] Center 34 (4~65) winsize 62
2945 12:14:36.468127 [CA 3] Center 33 (3~64) winsize 62
2946 12:14:36.472094 [CA 4] Center 32 (2~63) winsize 62
2947 12:14:36.475234 [CA 5] Center 32 (1~63) winsize 63
2948 12:14:36.475796
2949 12:14:36.478575 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2950 12:14:36.479141
2951 12:14:36.482566 [CATrainingPosCal] consider 1 rank data
2952 12:14:36.485656 u2DelayCellTimex100 = 270/100 ps
2953 12:14:36.488909 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2954 12:14:36.493062 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2955 12:14:36.498868 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2956 12:14:36.503379 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2957 12:14:36.506281 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2958 12:14:36.509047 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2959 12:14:36.509654
2960 12:14:36.511820 CA PerBit enable=1, Macro0, CA PI delay=32
2961 12:14:36.512380
2962 12:14:36.514891 [CBTSetCACLKResult] CA Dly = 32
2963 12:14:36.515348 CS Dly: 5 (0~36)
2964 12:14:36.515710 ==
2965 12:14:36.518533 Dram Type= 6, Freq= 0, CH_1, rank 1
2966 12:14:36.525353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2967 12:14:36.525907 ==
2968 12:14:36.529288 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2969 12:14:36.535078 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2970 12:14:36.544416 [CA 0] Center 37 (7~68) winsize 62
2971 12:14:36.547149 [CA 1] Center 37 (7~68) winsize 62
2972 12:14:36.549997 [CA 2] Center 34 (3~65) winsize 63
2973 12:14:36.554635 [CA 3] Center 33 (3~64) winsize 62
2974 12:14:36.557768 [CA 4] Center 32 (2~63) winsize 62
2975 12:14:36.560402 [CA 5] Center 32 (1~63) winsize 63
2976 12:14:36.561013
2977 12:14:36.563773 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2978 12:14:36.564335
2979 12:14:36.567215 [CATrainingPosCal] consider 2 rank data
2980 12:14:36.571079 u2DelayCellTimex100 = 270/100 ps
2981 12:14:36.573881 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2982 12:14:36.577422 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2983 12:14:36.583868 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2984 12:14:36.586580 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2985 12:14:36.590213 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2986 12:14:36.593713 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2987 12:14:36.594199
2988 12:14:36.597427 CA PerBit enable=1, Macro0, CA PI delay=32
2989 12:14:36.597985
2990 12:14:36.601132 [CBTSetCACLKResult] CA Dly = 32
2991 12:14:36.601698 CS Dly: 6 (0~38)
2992 12:14:36.602071
2993 12:14:36.603626 ----->DramcWriteLeveling(PI) begin...
2994 12:14:36.607933 ==
2995 12:14:36.610334 Dram Type= 6, Freq= 0, CH_1, rank 0
2996 12:14:36.613332 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2997 12:14:36.613804 ==
2998 12:14:36.616927 Write leveling (Byte 0): 22 => 22
2999 12:14:36.620298 Write leveling (Byte 1): 22 => 22
3000 12:14:36.624517 DramcWriteLeveling(PI) end<-----
3001 12:14:36.625117
3002 12:14:36.625490 ==
3003 12:14:36.626769 Dram Type= 6, Freq= 0, CH_1, rank 0
3004 12:14:36.630595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3005 12:14:36.631152 ==
3006 12:14:36.633546 [Gating] SW mode calibration
3007 12:14:36.640426 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3008 12:14:36.646806 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3009 12:14:36.649923 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3010 12:14:36.653534 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3011 12:14:36.657081 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3012 12:14:36.663685 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3013 12:14:36.667605 0 11 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 1)
3014 12:14:36.670337 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3015 12:14:36.677567 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3016 12:14:36.679923 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3017 12:14:36.683006 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3018 12:14:36.690592 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3019 12:14:36.693540 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3020 12:14:36.697086 0 12 12 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
3021 12:14:36.703625 0 12 16 | B1->B0 | 3535 4545 | 0 0 | (0 0) (0 0)
3022 12:14:36.706844 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3023 12:14:36.710657 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3024 12:14:36.716641 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3025 12:14:36.719980 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3026 12:14:36.724579 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3027 12:14:36.730009 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3028 12:14:36.732817 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3029 12:14:36.736470 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3030 12:14:36.742854 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3031 12:14:36.746150 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3032 12:14:36.749379 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3033 12:14:36.756554 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3034 12:14:36.760448 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3035 12:14:36.763558 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3036 12:14:36.769679 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3037 12:14:36.774361 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3038 12:14:36.776694 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3039 12:14:36.780859 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3040 12:14:36.786832 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3041 12:14:36.789338 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3042 12:14:36.792979 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3043 12:14:36.799589 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3044 12:14:36.803499 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 12:14:36.806518 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3046 12:14:36.812877 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3047 12:14:36.816334 Total UI for P1: 0, mck2ui 16
3048 12:14:36.819447 best dqsien dly found for B0: ( 0, 15, 16)
3049 12:14:36.823078 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3050 12:14:36.826488 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3051 12:14:36.829485 Total UI for P1: 0, mck2ui 16
3052 12:14:36.832619 best dqsien dly found for B1: ( 0, 15, 20)
3053 12:14:36.836196 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3054 12:14:36.839605 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
3055 12:14:36.843016
3056 12:14:36.845907 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3057 12:14:36.849415 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3058 12:14:36.853326 [Gating] SW calibration Done
3059 12:14:36.853785 ==
3060 12:14:36.855873 Dram Type= 6, Freq= 0, CH_1, rank 0
3061 12:14:36.859643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3062 12:14:36.860205 ==
3063 12:14:36.860573 RX Vref Scan: 0
3064 12:14:36.860981
3065 12:14:36.863036 RX Vref 0 -> 0, step: 1
3066 12:14:36.863591
3067 12:14:36.866268 RX Delay -40 -> 252, step: 8
3068 12:14:36.869798 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3069 12:14:36.873470 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3070 12:14:36.880136 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3071 12:14:36.882649 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3072 12:14:36.886672 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3073 12:14:36.889872 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3074 12:14:36.893544 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3075 12:14:36.899999 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3076 12:14:36.903198 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3077 12:14:36.906108 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3078 12:14:36.909492 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3079 12:14:36.913332 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3080 12:14:36.916518 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3081 12:14:36.922707 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3082 12:14:36.926182 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3083 12:14:36.929527 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3084 12:14:36.929987 ==
3085 12:14:36.933369 Dram Type= 6, Freq= 0, CH_1, rank 0
3086 12:14:36.936436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3087 12:14:36.937060 ==
3088 12:14:36.940149 DQS Delay:
3089 12:14:36.940870 DQS0 = 0, DQS1 = 0
3090 12:14:36.943559 DQM Delay:
3091 12:14:36.944131 DQM0 = 116, DQM1 = 107
3092 12:14:36.946078 DQ Delay:
3093 12:14:36.949391 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3094 12:14:36.952685 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3095 12:14:36.956159 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3096 12:14:36.959207 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3097 12:14:36.959670
3098 12:14:36.960034
3099 12:14:36.960373 ==
3100 12:14:36.963026 Dram Type= 6, Freq= 0, CH_1, rank 0
3101 12:14:36.966292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3102 12:14:36.966762 ==
3103 12:14:36.967133
3104 12:14:36.967474
3105 12:14:36.970045 TX Vref Scan disable
3106 12:14:36.973033 == TX Byte 0 ==
3107 12:14:36.976155 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3108 12:14:36.979414 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3109 12:14:36.982944 == TX Byte 1 ==
3110 12:14:36.986131 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3111 12:14:36.989080 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3112 12:14:36.989554 ==
3113 12:14:36.992555 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 12:14:36.996251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3115 12:14:36.999638 ==
3116 12:14:37.009224 TX Vref=22, minBit 9, minWin=25, winSum=417
3117 12:14:37.012855 TX Vref=24, minBit 11, minWin=25, winSum=425
3118 12:14:37.015749 TX Vref=26, minBit 0, minWin=26, winSum=427
3119 12:14:37.019148 TX Vref=28, minBit 1, minWin=26, winSum=431
3120 12:14:37.023398 TX Vref=30, minBit 1, minWin=26, winSum=431
3121 12:14:37.029523 TX Vref=32, minBit 0, minWin=26, winSum=430
3122 12:14:37.032926 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 28
3123 12:14:37.033599
3124 12:14:37.035788 Final TX Range 1 Vref 28
3125 12:14:37.036258
3126 12:14:37.036773 ==
3127 12:14:37.039297 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 12:14:37.042504 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3129 12:14:37.045593 ==
3130 12:14:37.046161
3131 12:14:37.046634
3132 12:14:37.047082 TX Vref Scan disable
3133 12:14:37.048767 == TX Byte 0 ==
3134 12:14:37.052619 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3135 12:14:37.055601 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3136 12:14:37.059042 == TX Byte 1 ==
3137 12:14:37.062492 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3138 12:14:37.065846 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3139 12:14:37.069114
3140 12:14:37.069576 [DATLAT]
3141 12:14:37.069940 Freq=1200, CH1 RK0
3142 12:14:37.070285
3143 12:14:37.072463 DATLAT Default: 0xd
3144 12:14:37.073107 0, 0xFFFF, sum = 0
3145 12:14:37.075706 1, 0xFFFF, sum = 0
3146 12:14:37.076282 2, 0xFFFF, sum = 0
3147 12:14:37.079447 3, 0xFFFF, sum = 0
3148 12:14:37.080043 4, 0xFFFF, sum = 0
3149 12:14:37.082629 5, 0xFFFF, sum = 0
3150 12:14:37.085561 6, 0xFFFF, sum = 0
3151 12:14:37.086050 7, 0xFFFF, sum = 0
3152 12:14:37.089140 8, 0xFFFF, sum = 0
3153 12:14:37.089719 9, 0xFFFF, sum = 0
3154 12:14:37.092164 10, 0xFFFF, sum = 0
3155 12:14:37.092639 11, 0x0, sum = 1
3156 12:14:37.096288 12, 0x0, sum = 2
3157 12:14:37.096812 13, 0x0, sum = 3
3158 12:14:37.097298 14, 0x0, sum = 4
3159 12:14:37.099162 best_step = 12
3160 12:14:37.099615
3161 12:14:37.099976 ==
3162 12:14:37.102011 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 12:14:37.105679 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3164 12:14:37.106245 ==
3165 12:14:37.108878 RX Vref Scan: 1
3166 12:14:37.109442
3167 12:14:37.112932 Set Vref Range= 32 -> 127
3168 12:14:37.113493
3169 12:14:37.113866 RX Vref 32 -> 127, step: 1
3170 12:14:37.114212
3171 12:14:37.115354 RX Delay -29 -> 252, step: 4
3172 12:14:37.115815
3173 12:14:37.118986 Set Vref, RX VrefLevel [Byte0]: 32
3174 12:14:37.122557 [Byte1]: 32
3175 12:14:37.125908
3176 12:14:37.126476 Set Vref, RX VrefLevel [Byte0]: 33
3177 12:14:37.129683 [Byte1]: 33
3178 12:14:37.133702
3179 12:14:37.134164 Set Vref, RX VrefLevel [Byte0]: 34
3180 12:14:37.136864 [Byte1]: 34
3181 12:14:37.141795
3182 12:14:37.142378 Set Vref, RX VrefLevel [Byte0]: 35
3183 12:14:37.144849 [Byte1]: 35
3184 12:14:37.149366
3185 12:14:37.149882 Set Vref, RX VrefLevel [Byte0]: 36
3186 12:14:37.153440 [Byte1]: 36
3187 12:14:37.157502
3188 12:14:37.158158 Set Vref, RX VrefLevel [Byte0]: 37
3189 12:14:37.160692 [Byte1]: 37
3190 12:14:37.165815
3191 12:14:37.166378 Set Vref, RX VrefLevel [Byte0]: 38
3192 12:14:37.169243 [Byte1]: 38
3193 12:14:37.173320
3194 12:14:37.173890 Set Vref, RX VrefLevel [Byte0]: 39
3195 12:14:37.176921 [Byte1]: 39
3196 12:14:37.182306
3197 12:14:37.182926 Set Vref, RX VrefLevel [Byte0]: 40
3198 12:14:37.184581 [Byte1]: 40
3199 12:14:37.188932
3200 12:14:37.189402 Set Vref, RX VrefLevel [Byte0]: 41
3201 12:14:37.193196 [Byte1]: 41
3202 12:14:37.197025
3203 12:14:37.197497 Set Vref, RX VrefLevel [Byte0]: 42
3204 12:14:37.200533 [Byte1]: 42
3205 12:14:37.205735
3206 12:14:37.206301 Set Vref, RX VrefLevel [Byte0]: 43
3207 12:14:37.208331 [Byte1]: 43
3208 12:14:37.214347
3209 12:14:37.214904 Set Vref, RX VrefLevel [Byte0]: 44
3210 12:14:37.217350 [Byte1]: 44
3211 12:14:37.221366
3212 12:14:37.221923 Set Vref, RX VrefLevel [Byte0]: 45
3213 12:14:37.225153 [Byte1]: 45
3214 12:14:37.229406
3215 12:14:37.229962 Set Vref, RX VrefLevel [Byte0]: 46
3216 12:14:37.232387 [Byte1]: 46
3217 12:14:37.237780
3218 12:14:37.238345 Set Vref, RX VrefLevel [Byte0]: 47
3219 12:14:37.240840 [Byte1]: 47
3220 12:14:37.244888
3221 12:14:37.245340 Set Vref, RX VrefLevel [Byte0]: 48
3222 12:14:37.248831 [Byte1]: 48
3223 12:14:37.253476
3224 12:14:37.254039 Set Vref, RX VrefLevel [Byte0]: 49
3225 12:14:37.258402 [Byte1]: 49
3226 12:14:37.261347
3227 12:14:37.261805 Set Vref, RX VrefLevel [Byte0]: 50
3228 12:14:37.264755 [Byte1]: 50
3229 12:14:37.268931
3230 12:14:37.269491 Set Vref, RX VrefLevel [Byte0]: 51
3231 12:14:37.272185 [Byte1]: 51
3232 12:14:37.277038
3233 12:14:37.277592 Set Vref, RX VrefLevel [Byte0]: 52
3234 12:14:37.280458 [Byte1]: 52
3235 12:14:37.285117
3236 12:14:37.285672 Set Vref, RX VrefLevel [Byte0]: 53
3237 12:14:37.288302 [Byte1]: 53
3238 12:14:37.292695
3239 12:14:37.293350 Set Vref, RX VrefLevel [Byte0]: 54
3240 12:14:37.296166 [Byte1]: 54
3241 12:14:37.301635
3242 12:14:37.302197 Set Vref, RX VrefLevel [Byte0]: 55
3243 12:14:37.303872 [Byte1]: 55
3244 12:14:37.309856
3245 12:14:37.310429 Set Vref, RX VrefLevel [Byte0]: 56
3246 12:14:37.312562 [Byte1]: 56
3247 12:14:37.316955
3248 12:14:37.317512 Set Vref, RX VrefLevel [Byte0]: 57
3249 12:14:37.319704 [Byte1]: 57
3250 12:14:37.325948
3251 12:14:37.326505 Set Vref, RX VrefLevel [Byte0]: 58
3252 12:14:37.328535 [Byte1]: 58
3253 12:14:37.332686
3254 12:14:37.333295 Set Vref, RX VrefLevel [Byte0]: 59
3255 12:14:37.335954 [Byte1]: 59
3256 12:14:37.340753
3257 12:14:37.341376 Set Vref, RX VrefLevel [Byte0]: 60
3258 12:14:37.344468 [Byte1]: 60
3259 12:14:37.348992
3260 12:14:37.349562 Set Vref, RX VrefLevel [Byte0]: 61
3261 12:14:37.352959 [Byte1]: 61
3262 12:14:37.356661
3263 12:14:37.357268 Set Vref, RX VrefLevel [Byte0]: 62
3264 12:14:37.359651 [Byte1]: 62
3265 12:14:37.365479
3266 12:14:37.366036 Set Vref, RX VrefLevel [Byte0]: 63
3267 12:14:37.367750 [Byte1]: 63
3268 12:14:37.372354
3269 12:14:37.372949 Set Vref, RX VrefLevel [Byte0]: 64
3270 12:14:37.375265 [Byte1]: 64
3271 12:14:37.380284
3272 12:14:37.380876 Set Vref, RX VrefLevel [Byte0]: 65
3273 12:14:37.383320 [Byte1]: 65
3274 12:14:37.388307
3275 12:14:37.388810 Set Vref, RX VrefLevel [Byte0]: 66
3276 12:14:37.392144 [Byte1]: 66
3277 12:14:37.395824
3278 12:14:37.396282 Set Vref, RX VrefLevel [Byte0]: 67
3279 12:14:37.399955 [Byte1]: 67
3280 12:14:37.404334
3281 12:14:37.404930 Final RX Vref Byte 0 = 52 to rank0
3282 12:14:37.407420 Final RX Vref Byte 1 = 49 to rank0
3283 12:14:37.411336 Final RX Vref Byte 0 = 52 to rank1
3284 12:14:37.414768 Final RX Vref Byte 1 = 49 to rank1==
3285 12:14:37.417556 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 12:14:37.424089 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3287 12:14:37.424668 ==
3288 12:14:37.425110 DQS Delay:
3289 12:14:37.425465 DQS0 = 0, DQS1 = 0
3290 12:14:37.427663 DQM Delay:
3291 12:14:37.428230 DQM0 = 115, DQM1 = 105
3292 12:14:37.431467 DQ Delay:
3293 12:14:37.433941 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =114
3294 12:14:37.437899 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3295 12:14:37.440493 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3296 12:14:37.444062 DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =114
3297 12:14:37.444547
3298 12:14:37.444976
3299 12:14:37.450796 [DQSOSCAuto] RK0, (LSB)MR18= 0x1616, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3300 12:14:37.454030 CH1 RK0: MR19=404, MR18=1616
3301 12:14:37.461615 CH1_RK0: MR19=0x404, MR18=0x1616, DQSOSC=401, MR23=63, INC=40, DEC=27
3302 12:14:37.462185
3303 12:14:37.465231 ----->DramcWriteLeveling(PI) begin...
3304 12:14:37.465807 ==
3305 12:14:37.467264 Dram Type= 6, Freq= 0, CH_1, rank 1
3306 12:14:37.471299 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3307 12:14:37.471875 ==
3308 12:14:37.474590 Write leveling (Byte 0): 22 => 22
3309 12:14:37.477990 Write leveling (Byte 1): 22 => 22
3310 12:14:37.481068 DramcWriteLeveling(PI) end<-----
3311 12:14:37.481532
3312 12:14:37.481900 ==
3313 12:14:37.483922 Dram Type= 6, Freq= 0, CH_1, rank 1
3314 12:14:37.490585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3315 12:14:37.491142 ==
3316 12:14:37.491514 [Gating] SW mode calibration
3317 12:14:37.500674 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3318 12:14:37.503945 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3319 12:14:37.507395 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3320 12:14:37.514000 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3321 12:14:37.517650 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3322 12:14:37.521583 0 11 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
3323 12:14:37.527744 0 11 16 | B1->B0 | 3333 2323 | 1 0 | (0 1) (0 0)
3324 12:14:37.530435 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3325 12:14:37.534055 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3326 12:14:37.540498 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3327 12:14:37.543783 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3328 12:14:37.547134 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3329 12:14:37.553415 0 12 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3330 12:14:37.557637 0 12 12 | B1->B0 | 2424 3f3f | 0 0 | (0 0) (0 0)
3331 12:14:37.560363 0 12 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
3332 12:14:37.566639 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3333 12:14:37.570224 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3334 12:14:37.573418 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3335 12:14:37.580183 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3336 12:14:37.583686 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3337 12:14:37.586988 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3338 12:14:37.593545 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3339 12:14:37.597369 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3340 12:14:37.600270 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3341 12:14:37.607141 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3342 12:14:37.610773 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3343 12:14:37.613296 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3344 12:14:37.620039 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3345 12:14:37.623972 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3346 12:14:37.627808 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3347 12:14:37.630444 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3348 12:14:37.636942 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3349 12:14:37.640816 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3350 12:14:37.643714 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3351 12:14:37.650728 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3352 12:14:37.654178 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3353 12:14:37.657743 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 12:14:37.664034 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3355 12:14:37.666726 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3356 12:14:37.669873 Total UI for P1: 0, mck2ui 16
3357 12:14:37.674945 best dqsien dly found for B0: ( 0, 15, 12)
3358 12:14:37.676505 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3359 12:14:37.679930 Total UI for P1: 0, mck2ui 16
3360 12:14:37.683525 best dqsien dly found for B1: ( 0, 15, 16)
3361 12:14:37.686857 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3362 12:14:37.690348 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3363 12:14:37.693415
3364 12:14:37.696862 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3365 12:14:37.700365 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3366 12:14:37.704026 [Gating] SW calibration Done
3367 12:14:37.704592 ==
3368 12:14:37.707083 Dram Type= 6, Freq= 0, CH_1, rank 1
3369 12:14:37.710225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3370 12:14:37.710793 ==
3371 12:14:37.711161 RX Vref Scan: 0
3372 12:14:37.711570
3373 12:14:37.713617 RX Vref 0 -> 0, step: 1
3374 12:14:37.714077
3375 12:14:37.716892 RX Delay -40 -> 252, step: 8
3376 12:14:37.720209 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3377 12:14:37.723861 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3378 12:14:37.730496 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3379 12:14:37.733811 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3380 12:14:37.736670 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3381 12:14:37.741065 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3382 12:14:37.743819 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3383 12:14:37.750032 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3384 12:14:37.753474 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3385 12:14:37.757566 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3386 12:14:37.759553 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3387 12:14:37.763063 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3388 12:14:37.766575 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3389 12:14:37.773426 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3390 12:14:37.776467 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3391 12:14:37.779731 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3392 12:14:37.780184 ==
3393 12:14:37.783423 Dram Type= 6, Freq= 0, CH_1, rank 1
3394 12:14:37.786808 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3395 12:14:37.789663 ==
3396 12:14:37.790116 DQS Delay:
3397 12:14:37.790476 DQS0 = 0, DQS1 = 0
3398 12:14:37.793639 DQM Delay:
3399 12:14:37.794187 DQM0 = 115, DQM1 = 105
3400 12:14:37.796448 DQ Delay:
3401 12:14:37.799583 DQ0 =115, DQ1 =111, DQ2 =111, DQ3 =115
3402 12:14:37.803469 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3403 12:14:37.806479 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
3404 12:14:37.810944 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3405 12:14:37.811495
3406 12:14:37.811854
3407 12:14:37.812187 ==
3408 12:14:37.813512 Dram Type= 6, Freq= 0, CH_1, rank 1
3409 12:14:37.816352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3410 12:14:37.816896 ==
3411 12:14:37.817270
3412 12:14:37.817609
3413 12:14:37.819931 TX Vref Scan disable
3414 12:14:37.823717 == TX Byte 0 ==
3415 12:14:37.826138 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3416 12:14:37.829817 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3417 12:14:37.833086 == TX Byte 1 ==
3418 12:14:37.837003 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3419 12:14:37.839692 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3420 12:14:37.840149 ==
3421 12:14:37.842867 Dram Type= 6, Freq= 0, CH_1, rank 1
3422 12:14:37.846552 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3423 12:14:37.849584 ==
3424 12:14:37.859709 TX Vref=22, minBit 0, minWin=26, winSum=421
3425 12:14:37.863906 TX Vref=24, minBit 3, minWin=26, winSum=426
3426 12:14:37.866149 TX Vref=26, minBit 3, minWin=26, winSum=429
3427 12:14:37.869572 TX Vref=28, minBit 9, minWin=26, winSum=433
3428 12:14:37.873157 TX Vref=30, minBit 9, minWin=26, winSum=437
3429 12:14:37.876212 TX Vref=32, minBit 0, minWin=26, winSum=428
3430 12:14:37.883762 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
3431 12:14:37.884351
3432 12:14:37.886977 Final TX Range 1 Vref 30
3433 12:14:37.887442
3434 12:14:37.887810 ==
3435 12:14:37.890045 Dram Type= 6, Freq= 0, CH_1, rank 1
3436 12:14:37.893440 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3437 12:14:37.894028 ==
3438 12:14:37.894402
3439 12:14:37.895875
3440 12:14:37.896330 TX Vref Scan disable
3441 12:14:37.899734 == TX Byte 0 ==
3442 12:14:37.903382 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3443 12:14:37.906570 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3444 12:14:37.910249 == TX Byte 1 ==
3445 12:14:37.913315 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3446 12:14:37.917236 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3447 12:14:37.917808
3448 12:14:37.919809 [DATLAT]
3449 12:14:37.920374 Freq=1200, CH1 RK1
3450 12:14:37.920832
3451 12:14:37.923273 DATLAT Default: 0xc
3452 12:14:37.923841 0, 0xFFFF, sum = 0
3453 12:14:37.926410 1, 0xFFFF, sum = 0
3454 12:14:37.926886 2, 0xFFFF, sum = 0
3455 12:14:37.929395 3, 0xFFFF, sum = 0
3456 12:14:37.929868 4, 0xFFFF, sum = 0
3457 12:14:37.933159 5, 0xFFFF, sum = 0
3458 12:14:37.933733 6, 0xFFFF, sum = 0
3459 12:14:37.936982 7, 0xFFFF, sum = 0
3460 12:14:37.937548 8, 0xFFFF, sum = 0
3461 12:14:37.939607 9, 0xFFFF, sum = 0
3462 12:14:37.942862 10, 0xFFFF, sum = 0
3463 12:14:37.943327 11, 0x0, sum = 1
3464 12:14:37.943696 12, 0x0, sum = 2
3465 12:14:37.946269 13, 0x0, sum = 3
3466 12:14:37.946794 14, 0x0, sum = 4
3467 12:14:37.949541 best_step = 12
3468 12:14:37.950000
3469 12:14:37.950367 ==
3470 12:14:37.953265 Dram Type= 6, Freq= 0, CH_1, rank 1
3471 12:14:37.956819 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3472 12:14:37.957391 ==
3473 12:14:37.959613 RX Vref Scan: 0
3474 12:14:37.960076
3475 12:14:37.960445 RX Vref 0 -> 0, step: 1
3476 12:14:37.960838
3477 12:14:37.962689 RX Delay -29 -> 252, step: 4
3478 12:14:37.970072 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3479 12:14:37.972628 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3480 12:14:37.976673 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3481 12:14:37.979682 iDelay=199, Bit 3, Center 110 (39 ~ 182) 144
3482 12:14:37.983376 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3483 12:14:37.989971 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3484 12:14:37.993169 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3485 12:14:37.996579 iDelay=199, Bit 7, Center 110 (39 ~ 182) 144
3486 12:14:37.999809 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3487 12:14:38.003591 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3488 12:14:38.009642 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3489 12:14:38.013603 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3490 12:14:38.016252 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3491 12:14:38.020228 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3492 12:14:38.023323 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3493 12:14:38.029492 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3494 12:14:38.030194 ==
3495 12:14:38.033193 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 12:14:38.036850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3497 12:14:38.037415 ==
3498 12:14:38.037790 DQS Delay:
3499 12:14:38.039348 DQS0 = 0, DQS1 = 0
3500 12:14:38.039824 DQM Delay:
3501 12:14:38.043505 DQM0 = 114, DQM1 = 103
3502 12:14:38.043968 DQ Delay:
3503 12:14:38.047892 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =110
3504 12:14:38.049238 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3505 12:14:38.053120 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3506 12:14:38.056094 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =110
3507 12:14:38.056558
3508 12:14:38.056985
3509 12:14:38.066546 [DQSOSCAuto] RK1, (LSB)MR18= 0xa0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3510 12:14:38.069827 CH1 RK1: MR19=404, MR18=A0A
3511 12:14:38.073507 CH1_RK1: MR19=0x404, MR18=0xA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3512 12:14:38.076615 [RxdqsGatingPostProcess] freq 1200
3513 12:14:38.082926 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3514 12:14:38.085998 Pre-setting of DQS Precalculation
3515 12:14:38.089639 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3516 12:14:38.099268 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3517 12:14:38.106327 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3518 12:14:38.106934
3519 12:14:38.107312
3520 12:14:38.109721 [Calibration Summary] 2400 Mbps
3521 12:14:38.110290 CH 0, Rank 0
3522 12:14:38.113165 SW Impedance : PASS
3523 12:14:38.113841 DUTY Scan : NO K
3524 12:14:38.116314 ZQ Calibration : PASS
3525 12:14:38.119783 Jitter Meter : NO K
3526 12:14:38.120352 CBT Training : PASS
3527 12:14:38.122651 Write leveling : PASS
3528 12:14:38.125840 RX DQS gating : PASS
3529 12:14:38.126305 RX DQ/DQS(RDDQC) : PASS
3530 12:14:38.129507 TX DQ/DQS : PASS
3531 12:14:38.132817 RX DATLAT : PASS
3532 12:14:38.133384 RX DQ/DQS(Engine): PASS
3533 12:14:38.136425 TX OE : NO K
3534 12:14:38.137228 All Pass.
3535 12:14:38.137624
3536 12:14:38.139148 CH 0, Rank 1
3537 12:14:38.139611 SW Impedance : PASS
3538 12:14:38.143197 DUTY Scan : NO K
3539 12:14:38.143660 ZQ Calibration : PASS
3540 12:14:38.146364 Jitter Meter : NO K
3541 12:14:38.149258 CBT Training : PASS
3542 12:14:38.149720 Write leveling : PASS
3543 12:14:38.153524 RX DQS gating : PASS
3544 12:14:38.155826 RX DQ/DQS(RDDQC) : PASS
3545 12:14:38.156288 TX DQ/DQS : PASS
3546 12:14:38.160247 RX DATLAT : PASS
3547 12:14:38.163636 RX DQ/DQS(Engine): PASS
3548 12:14:38.164205 TX OE : NO K
3549 12:14:38.166244 All Pass.
3550 12:14:38.166813
3551 12:14:38.167187 CH 1, Rank 0
3552 12:14:38.169874 SW Impedance : PASS
3553 12:14:38.170648 DUTY Scan : NO K
3554 12:14:38.172821 ZQ Calibration : PASS
3555 12:14:38.176444 Jitter Meter : NO K
3556 12:14:38.176955 CBT Training : PASS
3557 12:14:38.179720 Write leveling : PASS
3558 12:14:38.180183 RX DQS gating : PASS
3559 12:14:38.183507 RX DQ/DQS(RDDQC) : PASS
3560 12:14:38.186307 TX DQ/DQS : PASS
3561 12:14:38.186771 RX DATLAT : PASS
3562 12:14:38.190590 RX DQ/DQS(Engine): PASS
3563 12:14:38.192933 TX OE : NO K
3564 12:14:38.193395 All Pass.
3565 12:14:38.193763
3566 12:14:38.194103 CH 1, Rank 1
3567 12:14:38.196225 SW Impedance : PASS
3568 12:14:38.199800 DUTY Scan : NO K
3569 12:14:38.200368 ZQ Calibration : PASS
3570 12:14:38.203189 Jitter Meter : NO K
3571 12:14:38.207412 CBT Training : PASS
3572 12:14:38.207980 Write leveling : PASS
3573 12:14:38.209348 RX DQS gating : PASS
3574 12:14:38.214298 RX DQ/DQS(RDDQC) : PASS
3575 12:14:38.214861 TX DQ/DQS : PASS
3576 12:14:38.216220 RX DATLAT : PASS
3577 12:14:38.216686 RX DQ/DQS(Engine): PASS
3578 12:14:38.219307 TX OE : NO K
3579 12:14:38.219772 All Pass.
3580 12:14:38.220142
3581 12:14:38.223424 DramC Write-DBI off
3582 12:14:38.226816 PER_BANK_REFRESH: Hybrid Mode
3583 12:14:38.227378 TX_TRACKING: ON
3584 12:14:38.236063 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3585 12:14:38.241202 [FAST_K] Save calibration result to emmc
3586 12:14:38.242618 dramc_set_vcore_voltage set vcore to 650000
3587 12:14:38.246316 Read voltage for 600, 5
3588 12:14:38.246883 Vio18 = 0
3589 12:14:38.249739 Vcore = 650000
3590 12:14:38.250199 Vdram = 0
3591 12:14:38.250564 Vddq = 0
3592 12:14:38.250899 Vmddr = 0
3593 12:14:38.256771 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3594 12:14:38.259611 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3595 12:14:38.263059 MEM_TYPE=3, freq_sel=19
3596 12:14:38.266362 sv_algorithm_assistance_LP4_1600
3597 12:14:38.269897 ============ PULL DRAM RESETB DOWN ============
3598 12:14:38.275965 ========== PULL DRAM RESETB DOWN end =========
3599 12:14:38.279573 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3600 12:14:38.282818 ===================================
3601 12:14:38.285923 LPDDR4 DRAM CONFIGURATION
3602 12:14:38.289838 ===================================
3603 12:14:38.290407 EX_ROW_EN[0] = 0x0
3604 12:14:38.292914 EX_ROW_EN[1] = 0x0
3605 12:14:38.293480 LP4Y_EN = 0x0
3606 12:14:38.297021 WORK_FSP = 0x0
3607 12:14:38.297727 WL = 0x2
3608 12:14:38.299619 RL = 0x2
3609 12:14:38.300185 BL = 0x2
3610 12:14:38.303387 RPST = 0x0
3611 12:14:38.306424 RD_PRE = 0x0
3612 12:14:38.306987 WR_PRE = 0x1
3613 12:14:38.309516 WR_PST = 0x0
3614 12:14:38.309980 DBI_WR = 0x0
3615 12:14:38.312330 DBI_RD = 0x0
3616 12:14:38.312816 OTF = 0x1
3617 12:14:38.315912 ===================================
3618 12:14:38.319001 ===================================
3619 12:14:38.322161 ANA top config
3620 12:14:38.326040 ===================================
3621 12:14:38.326601 DLL_ASYNC_EN = 0
3622 12:14:38.329644 ALL_SLAVE_EN = 1
3623 12:14:38.332226 NEW_RANK_MODE = 1
3624 12:14:38.335591 DLL_IDLE_MODE = 1
3625 12:14:38.336138 LP45_APHY_COMB_EN = 1
3626 12:14:38.338876 TX_ODT_DIS = 1
3627 12:14:38.341714 NEW_8X_MODE = 1
3628 12:14:38.345392 ===================================
3629 12:14:38.349241 ===================================
3630 12:14:38.351987 data_rate = 1200
3631 12:14:38.355263 CKR = 1
3632 12:14:38.359031 DQ_P2S_RATIO = 8
3633 12:14:38.361612 ===================================
3634 12:14:38.362079 CA_P2S_RATIO = 8
3635 12:14:38.365267 DQ_CA_OPEN = 0
3636 12:14:38.368174 DQ_SEMI_OPEN = 0
3637 12:14:38.371992 CA_SEMI_OPEN = 0
3638 12:14:38.375209 CA_FULL_RATE = 0
3639 12:14:38.378505 DQ_CKDIV4_EN = 1
3640 12:14:38.379070 CA_CKDIV4_EN = 1
3641 12:14:38.382127 CA_PREDIV_EN = 0
3642 12:14:38.385439 PH8_DLY = 0
3643 12:14:38.388242 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3644 12:14:38.391658 DQ_AAMCK_DIV = 4
3645 12:14:38.396069 CA_AAMCK_DIV = 4
3646 12:14:38.396635 CA_ADMCK_DIV = 4
3647 12:14:38.398517 DQ_TRACK_CA_EN = 0
3648 12:14:38.401753 CA_PICK = 600
3649 12:14:38.405142 CA_MCKIO = 600
3650 12:14:38.408327 MCKIO_SEMI = 0
3651 12:14:38.411607 PLL_FREQ = 2288
3652 12:14:38.415439 DQ_UI_PI_RATIO = 32
3653 12:14:38.416002 CA_UI_PI_RATIO = 0
3654 12:14:38.418791 ===================================
3655 12:14:38.421797 ===================================
3656 12:14:38.425031 memory_type:LPDDR4
3657 12:14:38.428868 GP_NUM : 10
3658 12:14:38.429436 SRAM_EN : 1
3659 12:14:38.431340 MD32_EN : 0
3660 12:14:38.434939 ===================================
3661 12:14:38.438275 [ANA_INIT] >>>>>>>>>>>>>>
3662 12:14:38.441586 <<<<<< [CONFIGURE PHASE]: ANA_TX
3663 12:14:38.445083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3664 12:14:38.449328 ===================================
3665 12:14:38.449909 data_rate = 1200,PCW = 0X5800
3666 12:14:38.451544 ===================================
3667 12:14:38.454497 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3668 12:14:38.461574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3669 12:14:38.468342 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3670 12:14:38.471655 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3671 12:14:38.475257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3672 12:14:38.478392 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3673 12:14:38.481078 [ANA_INIT] flow start
3674 12:14:38.481622 [ANA_INIT] PLL >>>>>>>>
3675 12:14:38.485308 [ANA_INIT] PLL <<<<<<<<
3676 12:14:38.488404 [ANA_INIT] MIDPI >>>>>>>>
3677 12:14:38.491767 [ANA_INIT] MIDPI <<<<<<<<
3678 12:14:38.492382 [ANA_INIT] DLL >>>>>>>>
3679 12:14:38.494666 [ANA_INIT] flow end
3680 12:14:38.497524 ============ LP4 DIFF to SE enter ============
3681 12:14:38.501803 ============ LP4 DIFF to SE exit ============
3682 12:14:38.504498 [ANA_INIT] <<<<<<<<<<<<<
3683 12:14:38.508226 [Flow] Enable top DCM control >>>>>
3684 12:14:38.511485 [Flow] Enable top DCM control <<<<<
3685 12:14:38.514840 Enable DLL master slave shuffle
3686 12:14:38.520878 ==============================================================
3687 12:14:38.521451 Gating Mode config
3688 12:14:38.527502 ==============================================================
3689 12:14:38.528075 Config description:
3690 12:14:38.537801 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3691 12:14:38.543655 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3692 12:14:38.550822 SELPH_MODE 0: By rank 1: By Phase
3693 12:14:38.557825 ==============================================================
3694 12:14:38.558293 GAT_TRACK_EN = 1
3695 12:14:38.560515 RX_GATING_MODE = 2
3696 12:14:38.564691 RX_GATING_TRACK_MODE = 2
3697 12:14:38.567098 SELPH_MODE = 1
3698 12:14:38.570360 PICG_EARLY_EN = 1
3699 12:14:38.574359 VALID_LAT_VALUE = 1
3700 12:14:38.580062 ==============================================================
3701 12:14:38.583578 Enter into Gating configuration >>>>
3702 12:14:38.586765 Exit from Gating configuration <<<<
3703 12:14:38.590225 Enter into DVFS_PRE_config >>>>>
3704 12:14:38.600300 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3705 12:14:38.603692 Exit from DVFS_PRE_config <<<<<
3706 12:14:38.607905 Enter into PICG configuration >>>>
3707 12:14:38.610506 Exit from PICG configuration <<<<
3708 12:14:38.613578 [RX_INPUT] configuration >>>>>
3709 12:14:38.614141 [RX_INPUT] configuration <<<<<
3710 12:14:38.620357 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3711 12:14:38.626866 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3712 12:14:38.633612 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3713 12:14:38.636612 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3714 12:14:38.643035 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3715 12:14:38.650386 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3716 12:14:38.652923 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3717 12:14:38.659657 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3718 12:14:38.662471 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3719 12:14:38.666425 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3720 12:14:38.670350 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3721 12:14:38.675951 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3722 12:14:38.679110 ===================================
3723 12:14:38.679681 LPDDR4 DRAM CONFIGURATION
3724 12:14:38.683270 ===================================
3725 12:14:38.686281 EX_ROW_EN[0] = 0x0
3726 12:14:38.688970 EX_ROW_EN[1] = 0x0
3727 12:14:38.689459 LP4Y_EN = 0x0
3728 12:14:38.692671 WORK_FSP = 0x0
3729 12:14:38.693278 WL = 0x2
3730 12:14:38.696412 RL = 0x2
3731 12:14:38.697032 BL = 0x2
3732 12:14:38.699510 RPST = 0x0
3733 12:14:38.699971 RD_PRE = 0x0
3734 12:14:38.702491 WR_PRE = 0x1
3735 12:14:38.702950 WR_PST = 0x0
3736 12:14:38.706888 DBI_WR = 0x0
3737 12:14:38.707449 DBI_RD = 0x0
3738 12:14:38.709227 OTF = 0x1
3739 12:14:38.712179 ===================================
3740 12:14:38.715797 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3741 12:14:38.718946 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3742 12:14:38.725763 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3743 12:14:38.728491 ===================================
3744 12:14:38.728983 LPDDR4 DRAM CONFIGURATION
3745 12:14:38.732267 ===================================
3746 12:14:38.735554 EX_ROW_EN[0] = 0x10
3747 12:14:38.739482 EX_ROW_EN[1] = 0x0
3748 12:14:38.740053 LP4Y_EN = 0x0
3749 12:14:38.741886 WORK_FSP = 0x0
3750 12:14:38.742352 WL = 0x2
3751 12:14:38.746157 RL = 0x2
3752 12:14:38.746619 BL = 0x2
3753 12:14:38.748680 RPST = 0x0
3754 12:14:38.749191 RD_PRE = 0x0
3755 12:14:38.752003 WR_PRE = 0x1
3756 12:14:38.752463 WR_PST = 0x0
3757 12:14:38.755437 DBI_WR = 0x0
3758 12:14:38.755899 DBI_RD = 0x0
3759 12:14:38.758220 OTF = 0x1
3760 12:14:38.761920 ===================================
3761 12:14:38.768406 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3762 12:14:38.771641 nWR fixed to 30
3763 12:14:38.775103 [ModeRegInit_LP4] CH0 RK0
3764 12:14:38.775565 [ModeRegInit_LP4] CH0 RK1
3765 12:14:38.778475 [ModeRegInit_LP4] CH1 RK0
3766 12:14:38.781739 [ModeRegInit_LP4] CH1 RK1
3767 12:14:38.782374 match AC timing 16
3768 12:14:38.788034 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3769 12:14:38.791782 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3770 12:14:38.795011 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3771 12:14:38.802366 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3772 12:14:38.805544 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3773 12:14:38.806115 ==
3774 12:14:38.807777 Dram Type= 6, Freq= 0, CH_0, rank 0
3775 12:14:38.811603 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3776 12:14:38.812190 ==
3777 12:14:38.818482 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3778 12:14:38.824876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3779 12:14:38.827749 [CA 0] Center 35 (5~66) winsize 62
3780 12:14:38.831372 [CA 1] Center 35 (5~66) winsize 62
3781 12:14:38.834696 [CA 2] Center 34 (4~65) winsize 62
3782 12:14:38.838517 [CA 3] Center 34 (4~65) winsize 62
3783 12:14:38.840824 [CA 4] Center 33 (3~64) winsize 62
3784 12:14:38.844227 [CA 5] Center 33 (3~64) winsize 62
3785 12:14:38.844686
3786 12:14:38.848138 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3787 12:14:38.848744
3788 12:14:38.851073 [CATrainingPosCal] consider 1 rank data
3789 12:14:38.854809 u2DelayCellTimex100 = 270/100 ps
3790 12:14:38.857262 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3791 12:14:38.861000 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3792 12:14:38.864052 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3793 12:14:38.867522 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3794 12:14:38.870631 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3795 12:14:38.877889 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3796 12:14:38.878456
3797 12:14:38.880821 CA PerBit enable=1, Macro0, CA PI delay=33
3798 12:14:38.881290
3799 12:14:38.883792 [CBTSetCACLKResult] CA Dly = 33
3800 12:14:38.884254 CS Dly: 5 (0~36)
3801 12:14:38.884737 ==
3802 12:14:38.887397 Dram Type= 6, Freq= 0, CH_0, rank 1
3803 12:14:38.890391 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3804 12:14:38.893840 ==
3805 12:14:38.897206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3806 12:14:38.903930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3807 12:14:38.907389 [CA 0] Center 36 (6~66) winsize 61
3808 12:14:38.910677 [CA 1] Center 35 (5~66) winsize 62
3809 12:14:38.913736 [CA 2] Center 34 (4~65) winsize 62
3810 12:14:38.917139 [CA 3] Center 34 (4~65) winsize 62
3811 12:14:38.920073 [CA 4] Center 33 (3~64) winsize 62
3812 12:14:38.923783 [CA 5] Center 33 (3~64) winsize 62
3813 12:14:38.924245
3814 12:14:38.926961 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3815 12:14:38.927576
3816 12:14:38.930852 [CATrainingPosCal] consider 2 rank data
3817 12:14:38.933509 u2DelayCellTimex100 = 270/100 ps
3818 12:14:38.937292 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3819 12:14:38.940285 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3820 12:14:38.947007 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3821 12:14:38.950759 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3822 12:14:38.954719 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3823 12:14:38.956438 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3824 12:14:38.956975
3825 12:14:38.960603 CA PerBit enable=1, Macro0, CA PI delay=33
3826 12:14:38.961175
3827 12:14:38.963545 [CBTSetCACLKResult] CA Dly = 33
3828 12:14:38.964119 CS Dly: 5 (0~36)
3829 12:14:38.964488
3830 12:14:38.969567 ----->DramcWriteLeveling(PI) begin...
3831 12:14:38.970126 ==
3832 12:14:38.973115 Dram Type= 6, Freq= 0, CH_0, rank 0
3833 12:14:38.976249 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3834 12:14:38.976755 ==
3835 12:14:38.980660 Write leveling (Byte 0): 31 => 31
3836 12:14:38.982850 Write leveling (Byte 1): 31 => 31
3837 12:14:38.986632 DramcWriteLeveling(PI) end<-----
3838 12:14:38.987200
3839 12:14:38.987571 ==
3840 12:14:38.989396 Dram Type= 6, Freq= 0, CH_0, rank 0
3841 12:14:38.993307 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3842 12:14:38.993871 ==
3843 12:14:38.996843 [Gating] SW mode calibration
3844 12:14:39.003497 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3845 12:14:39.009858 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3846 12:14:39.013018 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3847 12:14:39.016331 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3848 12:14:39.022402 0 5 8 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 0)
3849 12:14:39.026755 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3850 12:14:39.029627 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3851 12:14:39.035868 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3852 12:14:39.039443 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3853 12:14:39.042812 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3854 12:14:39.050283 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3855 12:14:39.053137 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3856 12:14:39.055920 0 6 8 | B1->B0 | 2c2c 3030 | 0 1 | (0 0) (0 0)
3857 12:14:39.062572 0 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3858 12:14:39.065973 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3859 12:14:39.068866 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3860 12:14:39.075732 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3861 12:14:39.078993 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3862 12:14:39.081889 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3863 12:14:39.089004 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3864 12:14:39.092180 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3865 12:14:39.095835 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3866 12:14:39.101939 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3867 12:14:39.105249 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3868 12:14:39.108407 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3869 12:14:39.115404 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3870 12:14:39.118154 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3871 12:14:39.122552 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3872 12:14:39.128389 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3873 12:14:39.131081 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3874 12:14:39.134678 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3875 12:14:39.141458 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 12:14:39.144848 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 12:14:39.148612 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 12:14:39.154376 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 12:14:39.157953 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 12:14:39.161390 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3881 12:14:39.167561 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3882 12:14:39.168108 Total UI for P1: 0, mck2ui 16
3883 12:14:39.174285 best dqsien dly found for B0: ( 0, 9, 8)
3884 12:14:39.175045 Total UI for P1: 0, mck2ui 16
3885 12:14:39.177765 best dqsien dly found for B1: ( 0, 9, 8)
3886 12:14:39.180964 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3887 12:14:39.187769 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3888 12:14:39.188236
3889 12:14:39.191095 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3890 12:14:39.194937 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3891 12:14:39.197657 [Gating] SW calibration Done
3892 12:14:39.198223 ==
3893 12:14:39.200700 Dram Type= 6, Freq= 0, CH_0, rank 0
3894 12:14:39.204883 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3895 12:14:39.205454 ==
3896 12:14:39.207931 RX Vref Scan: 0
3897 12:14:39.208498
3898 12:14:39.208912 RX Vref 0 -> 0, step: 1
3899 12:14:39.209262
3900 12:14:39.211864 RX Delay -230 -> 252, step: 16
3901 12:14:39.213866 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3902 12:14:39.221117 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3903 12:14:39.223852 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3904 12:14:39.227489 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3905 12:14:39.231402 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3906 12:14:39.238285 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3907 12:14:39.240587 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3908 12:14:39.243741 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3909 12:14:39.247756 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3910 12:14:39.250551 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
3911 12:14:39.257046 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3912 12:14:39.260447 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3913 12:14:39.264112 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3914 12:14:39.267135 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3915 12:14:39.273539 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3916 12:14:39.277098 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3917 12:14:39.277669 ==
3918 12:14:39.280144 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 12:14:39.284071 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3920 12:14:39.284544 ==
3921 12:14:39.286567 DQS Delay:
3922 12:14:39.287105 DQS0 = 0, DQS1 = 0
3923 12:14:39.290854 DQM Delay:
3924 12:14:39.291319 DQM0 = 38, DQM1 = 34
3925 12:14:39.291688 DQ Delay:
3926 12:14:39.293475 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3927 12:14:39.296661 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3928 12:14:39.299772 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
3929 12:14:39.303049 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3930 12:14:39.303514
3931 12:14:39.303880
3932 12:14:39.306721 ==
3933 12:14:39.307281 Dram Type= 6, Freq= 0, CH_0, rank 0
3934 12:14:39.313054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3935 12:14:39.313620 ==
3936 12:14:39.313997
3937 12:14:39.314342
3938 12:14:39.316939 TX Vref Scan disable
3939 12:14:39.317501 == TX Byte 0 ==
3940 12:14:39.323078 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3941 12:14:39.327011 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3942 12:14:39.327574 == TX Byte 1 ==
3943 12:14:39.333562 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3944 12:14:39.336277 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3945 12:14:39.336886 ==
3946 12:14:39.339110 Dram Type= 6, Freq= 0, CH_0, rank 0
3947 12:14:39.342485 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3948 12:14:39.342951 ==
3949 12:14:39.343321
3950 12:14:39.343666
3951 12:14:39.346178 TX Vref Scan disable
3952 12:14:39.349884 == TX Byte 0 ==
3953 12:14:39.353307 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3954 12:14:39.356664 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3955 12:14:39.360080 == TX Byte 1 ==
3956 12:14:39.362740 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3957 12:14:39.366079 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3958 12:14:39.366644
3959 12:14:39.369058 [DATLAT]
3960 12:14:39.369522 Freq=600, CH0 RK0
3961 12:14:39.369892
3962 12:14:39.372341 DATLAT Default: 0x9
3963 12:14:39.372844 0, 0xFFFF, sum = 0
3964 12:14:39.376589 1, 0xFFFF, sum = 0
3965 12:14:39.377227 2, 0xFFFF, sum = 0
3966 12:14:39.379943 3, 0xFFFF, sum = 0
3967 12:14:39.380507 4, 0xFFFF, sum = 0
3968 12:14:39.382700 5, 0xFFFF, sum = 0
3969 12:14:39.383168 6, 0xFFFF, sum = 0
3970 12:14:39.385786 7, 0x0, sum = 1
3971 12:14:39.386256 8, 0x0, sum = 2
3972 12:14:39.389696 9, 0x0, sum = 3
3973 12:14:39.390289 10, 0x0, sum = 4
3974 12:14:39.392633 best_step = 8
3975 12:14:39.393242
3976 12:14:39.393616 ==
3977 12:14:39.396491 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 12:14:39.399510 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3979 12:14:39.399977 ==
3980 12:14:39.400412 RX Vref Scan: 1
3981 12:14:39.402951
3982 12:14:39.403506 RX Vref 0 -> 0, step: 1
3983 12:14:39.403876
3984 12:14:39.405707 RX Delay -179 -> 252, step: 8
3985 12:14:39.406168
3986 12:14:39.409294 Set Vref, RX VrefLevel [Byte0]: 46
3987 12:14:39.412263 [Byte1]: 50
3988 12:14:39.416114
3989 12:14:39.416673 Final RX Vref Byte 0 = 46 to rank0
3990 12:14:39.419752 Final RX Vref Byte 1 = 50 to rank0
3991 12:14:39.422869 Final RX Vref Byte 0 = 46 to rank1
3992 12:14:39.426829 Final RX Vref Byte 1 = 50 to rank1==
3993 12:14:39.429566 Dram Type= 6, Freq= 0, CH_0, rank 0
3994 12:14:39.436494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3995 12:14:39.437113 ==
3996 12:14:39.437495 DQS Delay:
3997 12:14:39.438743 DQS0 = 0, DQS1 = 0
3998 12:14:39.439204 DQM Delay:
3999 12:14:39.439572 DQM0 = 39, DQM1 = 30
4000 12:14:39.442078 DQ Delay:
4001 12:14:39.445835 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =36
4002 12:14:39.448668 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =44
4003 12:14:39.452044 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4004 12:14:39.455346 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4005 12:14:39.455811
4006 12:14:39.456180
4007 12:14:39.461938 [DQSOSCAuto] RK0, (LSB)MR18= 0x5151, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
4008 12:14:39.465213 CH0 RK0: MR19=808, MR18=5151
4009 12:14:39.471619 CH0_RK0: MR19=0x808, MR18=0x5151, DQSOSC=394, MR23=63, INC=168, DEC=112
4010 12:14:39.472083
4011 12:14:39.475718 ----->DramcWriteLeveling(PI) begin...
4012 12:14:39.476279 ==
4013 12:14:39.478537 Dram Type= 6, Freq= 0, CH_0, rank 1
4014 12:14:39.481948 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4015 12:14:39.482413 ==
4016 12:14:39.485016 Write leveling (Byte 0): 31 => 31
4017 12:14:39.489027 Write leveling (Byte 1): 30 => 30
4018 12:14:39.491820 DramcWriteLeveling(PI) end<-----
4019 12:14:39.492379
4020 12:14:39.492799 ==
4021 12:14:39.495726 Dram Type= 6, Freq= 0, CH_0, rank 1
4022 12:14:39.498552 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4023 12:14:39.501779 ==
4024 12:14:39.502240 [Gating] SW mode calibration
4025 12:14:39.508647 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4026 12:14:39.515304 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4027 12:14:39.518345 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4028 12:14:39.524956 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4029 12:14:39.528911 0 5 8 | B1->B0 | 3333 3030 | 0 0 | (0 1) (0 0)
4030 12:14:39.532072 0 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4031 12:14:39.538746 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 12:14:39.542005 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 12:14:39.545312 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 12:14:39.551817 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 12:14:39.554676 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 12:14:39.558079 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 12:14:39.565036 0 6 8 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
4038 12:14:39.568504 0 6 12 | B1->B0 | 4343 4141 | 0 0 | (0 0) (0 0)
4039 12:14:39.571666 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 12:14:39.577829 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 12:14:39.581320 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 12:14:39.584453 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 12:14:39.590888 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 12:14:39.594187 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 12:14:39.597879 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4046 12:14:39.604116 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 12:14:39.607613 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 12:14:39.610780 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 12:14:39.617413 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 12:14:39.620462 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 12:14:39.624051 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 12:14:39.631584 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 12:14:39.634636 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 12:14:39.638917 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 12:14:39.640941 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 12:14:39.647123 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 12:14:39.650961 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 12:14:39.655396 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 12:14:39.661025 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 12:14:39.665212 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 12:14:39.667494 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4062 12:14:39.674618 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 12:14:39.677573 Total UI for P1: 0, mck2ui 16
4064 12:14:39.682087 best dqsien dly found for B0: ( 0, 9, 8)
4065 12:14:39.683679 Total UI for P1: 0, mck2ui 16
4066 12:14:39.686901 best dqsien dly found for B1: ( 0, 9, 8)
4067 12:14:39.690256 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4068 12:14:39.693594 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4069 12:14:39.694219
4070 12:14:39.696969 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4071 12:14:39.700486 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4072 12:14:39.703485 [Gating] SW calibration Done
4073 12:14:39.703947 ==
4074 12:14:39.708324 Dram Type= 6, Freq= 0, CH_0, rank 1
4075 12:14:39.710315 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4076 12:14:39.710889 ==
4077 12:14:39.713389 RX Vref Scan: 0
4078 12:14:39.713854
4079 12:14:39.714218 RX Vref 0 -> 0, step: 1
4080 12:14:39.717239
4081 12:14:39.717697 RX Delay -230 -> 252, step: 16
4082 12:14:39.723669 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4083 12:14:39.726958 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4084 12:14:39.730154 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4085 12:14:39.733528 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4086 12:14:39.737011 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4087 12:14:39.743762 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4088 12:14:39.747691 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4089 12:14:39.751067 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4090 12:14:39.753618 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4091 12:14:39.760657 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4092 12:14:39.764392 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4093 12:14:39.766867 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4094 12:14:39.770125 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4095 12:14:39.776878 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4096 12:14:39.780331 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4097 12:14:39.783443 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4098 12:14:39.784013 ==
4099 12:14:39.786757 Dram Type= 6, Freq= 0, CH_0, rank 1
4100 12:14:39.790280 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4101 12:14:39.793627 ==
4102 12:14:39.794090 DQS Delay:
4103 12:14:39.794457 DQS0 = 0, DQS1 = 0
4104 12:14:39.796243 DQM Delay:
4105 12:14:39.796702 DQM0 = 41, DQM1 = 33
4106 12:14:39.799961 DQ Delay:
4107 12:14:39.800528 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4108 12:14:39.802790 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4109 12:14:39.805947 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4110 12:14:39.809641 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4111 12:14:39.812940
4112 12:14:39.813515
4113 12:14:39.813885 ==
4114 12:14:39.816414 Dram Type= 6, Freq= 0, CH_0, rank 1
4115 12:14:39.820511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4116 12:14:39.821119 ==
4117 12:14:39.821495
4118 12:14:39.821837
4119 12:14:39.822527 TX Vref Scan disable
4120 12:14:39.822885 == TX Byte 0 ==
4121 12:14:39.829416 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4122 12:14:39.833706 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4123 12:14:39.834276 == TX Byte 1 ==
4124 12:14:39.839784 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4125 12:14:39.842788 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4126 12:14:39.843357 ==
4127 12:14:39.846348 Dram Type= 6, Freq= 0, CH_0, rank 1
4128 12:14:39.850037 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4129 12:14:39.850609 ==
4130 12:14:39.850980
4131 12:14:39.851322
4132 12:14:39.852521 TX Vref Scan disable
4133 12:14:39.857187 == TX Byte 0 ==
4134 12:14:39.859187 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4135 12:14:39.862749 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4136 12:14:39.866852 == TX Byte 1 ==
4137 12:14:39.869193 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4138 12:14:39.872892 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4139 12:14:39.873471
4140 12:14:39.876215 [DATLAT]
4141 12:14:39.876829 Freq=600, CH0 RK1
4142 12:14:39.877212
4143 12:14:39.879249 DATLAT Default: 0x8
4144 12:14:39.879813 0, 0xFFFF, sum = 0
4145 12:14:39.882775 1, 0xFFFF, sum = 0
4146 12:14:39.883344 2, 0xFFFF, sum = 0
4147 12:14:39.885797 3, 0xFFFF, sum = 0
4148 12:14:39.886266 4, 0xFFFF, sum = 0
4149 12:14:39.889771 5, 0xFFFF, sum = 0
4150 12:14:39.890356 6, 0xFFFF, sum = 0
4151 12:14:39.892301 7, 0x0, sum = 1
4152 12:14:39.892867 8, 0x0, sum = 2
4153 12:14:39.895753 9, 0x0, sum = 3
4154 12:14:39.896221 10, 0x0, sum = 4
4155 12:14:39.899758 best_step = 8
4156 12:14:39.900328
4157 12:14:39.900701 ==
4158 12:14:39.902555 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 12:14:39.905501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4160 12:14:39.905969 ==
4161 12:14:39.909490 RX Vref Scan: 0
4162 12:14:39.910056
4163 12:14:39.910425 RX Vref 0 -> 0, step: 1
4164 12:14:39.910769
4165 12:14:39.912869 RX Delay -195 -> 252, step: 8
4166 12:14:39.920203 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4167 12:14:39.922813 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4168 12:14:39.926306 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4169 12:14:39.929340 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4170 12:14:39.935607 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4171 12:14:39.939886 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4172 12:14:39.942607 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4173 12:14:39.946657 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4174 12:14:39.949490 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4175 12:14:39.955857 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4176 12:14:39.958789 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4177 12:14:39.962647 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4178 12:14:39.966283 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4179 12:14:39.972513 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4180 12:14:39.976458 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4181 12:14:39.979576 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4182 12:14:39.980040 ==
4183 12:14:39.982363 Dram Type= 6, Freq= 0, CH_0, rank 1
4184 12:14:39.989271 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4185 12:14:39.989852 ==
4186 12:14:39.990233 DQS Delay:
4187 12:14:39.990585 DQS0 = 0, DQS1 = 0
4188 12:14:39.992383 DQM Delay:
4189 12:14:39.992892 DQM0 = 41, DQM1 = 32
4190 12:14:39.996160 DQ Delay:
4191 12:14:39.998982 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4192 12:14:39.999576 DQ4 =44, DQ5 =32, DQ6 =44, DQ7 =52
4193 12:14:40.001913 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4194 12:14:40.008998 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4195 12:14:40.009569
4196 12:14:40.009940
4197 12:14:40.015531 [DQSOSCAuto] RK1, (LSB)MR18= 0x6767, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4198 12:14:40.019244 CH0 RK1: MR19=808, MR18=6767
4199 12:14:40.025806 CH0_RK1: MR19=0x808, MR18=0x6767, DQSOSC=390, MR23=63, INC=172, DEC=114
4200 12:14:40.029039 [RxdqsGatingPostProcess] freq 600
4201 12:14:40.032617 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4202 12:14:40.035553 Pre-setting of DQS Precalculation
4203 12:14:40.041838 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4204 12:14:40.042394 ==
4205 12:14:40.045360 Dram Type= 6, Freq= 0, CH_1, rank 0
4206 12:14:40.048237 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4207 12:14:40.048847 ==
4208 12:14:40.055006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4209 12:14:40.058462 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4210 12:14:40.062664 [CA 0] Center 35 (5~66) winsize 62
4211 12:14:40.066441 [CA 1] Center 35 (4~66) winsize 63
4212 12:14:40.069566 [CA 2] Center 33 (3~64) winsize 62
4213 12:14:40.072657 [CA 3] Center 33 (3~64) winsize 62
4214 12:14:40.076222 [CA 4] Center 33 (2~64) winsize 63
4215 12:14:40.079638 [CA 5] Center 33 (2~64) winsize 63
4216 12:14:40.080204
4217 12:14:40.082612 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4218 12:14:40.083181
4219 12:14:40.085929 [CATrainingPosCal] consider 1 rank data
4220 12:14:40.089942 u2DelayCellTimex100 = 270/100 ps
4221 12:14:40.093740 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4222 12:14:40.099752 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4223 12:14:40.102522 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4224 12:14:40.105640 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4225 12:14:40.108982 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4226 12:14:40.112834 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4227 12:14:40.113403
4228 12:14:40.115939 CA PerBit enable=1, Macro0, CA PI delay=33
4229 12:14:40.116634
4230 12:14:40.118781 [CBTSetCACLKResult] CA Dly = 33
4231 12:14:40.122395 CS Dly: 4 (0~35)
4232 12:14:40.122968 ==
4233 12:14:40.126232 Dram Type= 6, Freq= 0, CH_1, rank 1
4234 12:14:40.129420 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4235 12:14:40.129997 ==
4236 12:14:40.135661 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4237 12:14:40.138589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4238 12:14:40.143599 [CA 0] Center 35 (5~66) winsize 62
4239 12:14:40.146223 [CA 1] Center 34 (4~65) winsize 62
4240 12:14:40.149924 [CA 2] Center 33 (3~64) winsize 62
4241 12:14:40.153363 [CA 3] Center 33 (3~64) winsize 62
4242 12:14:40.156045 [CA 4] Center 32 (2~63) winsize 62
4243 12:14:40.159568 [CA 5] Center 32 (2~63) winsize 62
4244 12:14:40.160224
4245 12:14:40.162884 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4246 12:14:40.163455
4247 12:14:40.166137 [CATrainingPosCal] consider 2 rank data
4248 12:14:40.171271 u2DelayCellTimex100 = 270/100 ps
4249 12:14:40.172500 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4250 12:14:40.179614 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4251 12:14:40.183488 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4252 12:14:40.186191 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4253 12:14:40.189233 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4254 12:14:40.192635 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4255 12:14:40.193235
4256 12:14:40.195986 CA PerBit enable=1, Macro0, CA PI delay=32
4257 12:14:40.196465
4258 12:14:40.198840 [CBTSetCACLKResult] CA Dly = 32
4259 12:14:40.203050 CS Dly: 4 (0~35)
4260 12:14:40.203527
4261 12:14:40.205857 ----->DramcWriteLeveling(PI) begin...
4262 12:14:40.206344 ==
4263 12:14:40.208884 Dram Type= 6, Freq= 0, CH_1, rank 0
4264 12:14:40.213801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4265 12:14:40.214373 ==
4266 12:14:40.215333 Write leveling (Byte 0): 27 => 27
4267 12:14:40.219237 Write leveling (Byte 1): 27 => 27
4268 12:14:40.222564 DramcWriteLeveling(PI) end<-----
4269 12:14:40.223243
4270 12:14:40.223739 ==
4271 12:14:40.225674 Dram Type= 6, Freq= 0, CH_1, rank 0
4272 12:14:40.228800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4273 12:14:40.229373 ==
4274 12:14:40.232306 [Gating] SW mode calibration
4275 12:14:40.239032 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4276 12:14:40.245862 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4277 12:14:40.248396 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4278 12:14:40.251985 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4279 12:14:40.258627 0 5 8 | B1->B0 | 3030 2626 | 0 0 | (0 1) (0 0)
4280 12:14:40.262136 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4281 12:14:40.264913 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4282 12:14:40.271702 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4283 12:14:40.275074 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4284 12:14:40.278877 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4285 12:14:40.285204 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4286 12:14:40.288425 0 6 4 | B1->B0 | 2424 2e2e | 0 1 | (0 0) (1 1)
4287 12:14:40.291685 0 6 8 | B1->B0 | 3636 3d3d | 0 0 | (1 1) (0 0)
4288 12:14:40.298172 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4289 12:14:40.301524 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4290 12:14:40.305067 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 12:14:40.311883 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4292 12:14:40.315662 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4293 12:14:40.318259 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 12:14:40.325281 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4295 12:14:40.328251 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4296 12:14:40.331634 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 12:14:40.338196 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 12:14:40.341109 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 12:14:40.344812 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 12:14:40.351428 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 12:14:40.354657 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 12:14:40.358427 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 12:14:40.361067 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 12:14:40.368005 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 12:14:40.371480 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 12:14:40.374470 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 12:14:40.381593 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 12:14:40.384498 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 12:14:40.388022 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 12:14:40.394865 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4311 12:14:40.398187 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4312 12:14:40.401579 Total UI for P1: 0, mck2ui 16
4313 12:14:40.404443 best dqsien dly found for B0: ( 0, 9, 4)
4314 12:14:40.407549 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4315 12:14:40.410610 Total UI for P1: 0, mck2ui 16
4316 12:14:40.414932 best dqsien dly found for B1: ( 0, 9, 8)
4317 12:14:40.417962 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4318 12:14:40.421134 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4319 12:14:40.421697
4320 12:14:40.428114 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4321 12:14:40.430912 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4322 12:14:40.434704 [Gating] SW calibration Done
4323 12:14:40.435272 ==
4324 12:14:40.436974 Dram Type= 6, Freq= 0, CH_1, rank 0
4325 12:14:40.441732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4326 12:14:40.442298 ==
4327 12:14:40.442676 RX Vref Scan: 0
4328 12:14:40.443022
4329 12:14:40.444520 RX Vref 0 -> 0, step: 1
4330 12:14:40.445011
4331 12:14:40.447082 RX Delay -230 -> 252, step: 16
4332 12:14:40.450667 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4333 12:14:40.456702 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4334 12:14:40.460585 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4335 12:14:40.463981 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4336 12:14:40.467211 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4337 12:14:40.469906 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4338 12:14:40.477314 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4339 12:14:40.480471 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4340 12:14:40.483491 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4341 12:14:40.486507 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4342 12:14:40.494747 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4343 12:14:40.497131 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4344 12:14:40.500156 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4345 12:14:40.503757 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4346 12:14:40.506893 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4347 12:14:40.514471 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4348 12:14:40.515032 ==
4349 12:14:40.518011 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 12:14:40.520125 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4351 12:14:40.520588 ==
4352 12:14:40.520993 DQS Delay:
4353 12:14:40.523263 DQS0 = 0, DQS1 = 0
4354 12:14:40.523723 DQM Delay:
4355 12:14:40.528030 DQM0 = 39, DQM1 = 30
4356 12:14:40.528594 DQ Delay:
4357 12:14:40.531635 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4358 12:14:40.533983 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4359 12:14:40.537416 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4360 12:14:40.540362 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4361 12:14:40.540965
4362 12:14:40.541330
4363 12:14:40.541668 ==
4364 12:14:40.543983 Dram Type= 6, Freq= 0, CH_1, rank 0
4365 12:14:40.546526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4366 12:14:40.550497 ==
4367 12:14:40.550958
4368 12:14:40.551320
4369 12:14:40.551655 TX Vref Scan disable
4370 12:14:40.553255 == TX Byte 0 ==
4371 12:14:40.557597 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4372 12:14:40.563568 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4373 12:14:40.564120 == TX Byte 1 ==
4374 12:14:40.567258 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4375 12:14:40.573707 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4376 12:14:40.574272 ==
4377 12:14:40.576751 Dram Type= 6, Freq= 0, CH_1, rank 0
4378 12:14:40.580082 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4379 12:14:40.580641 ==
4380 12:14:40.581048
4381 12:14:40.581388
4382 12:14:40.582950 TX Vref Scan disable
4383 12:14:40.586306 == TX Byte 0 ==
4384 12:14:40.589316 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4385 12:14:40.593193 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4386 12:14:40.596309 == TX Byte 1 ==
4387 12:14:40.599767 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4388 12:14:40.603024 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4389 12:14:40.603662
4390 12:14:40.604041 [DATLAT]
4391 12:14:40.605894 Freq=600, CH1 RK0
4392 12:14:40.606352
4393 12:14:40.610043 DATLAT Default: 0x9
4394 12:14:40.610609 0, 0xFFFF, sum = 0
4395 12:14:40.613300 1, 0xFFFF, sum = 0
4396 12:14:40.613767 2, 0xFFFF, sum = 0
4397 12:14:40.615915 3, 0xFFFF, sum = 0
4398 12:14:40.616477 4, 0xFFFF, sum = 0
4399 12:14:40.618989 5, 0xFFFF, sum = 0
4400 12:14:40.619455 6, 0xFFFF, sum = 0
4401 12:14:40.623796 7, 0x0, sum = 1
4402 12:14:40.624366 8, 0x0, sum = 2
4403 12:14:40.625903 9, 0x0, sum = 3
4404 12:14:40.626367 10, 0x0, sum = 4
4405 12:14:40.626733 best_step = 8
4406 12:14:40.627071
4407 12:14:40.630008 ==
4408 12:14:40.630569 Dram Type= 6, Freq= 0, CH_1, rank 0
4409 12:14:40.636208 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4410 12:14:40.636839 ==
4411 12:14:40.637218 RX Vref Scan: 1
4412 12:14:40.637555
4413 12:14:40.639754 RX Vref 0 -> 0, step: 1
4414 12:14:40.640221
4415 12:14:40.642992 RX Delay -195 -> 252, step: 8
4416 12:14:40.643456
4417 12:14:40.646333 Set Vref, RX VrefLevel [Byte0]: 52
4418 12:14:40.649037 [Byte1]: 49
4419 12:14:40.649498
4420 12:14:40.653432 Final RX Vref Byte 0 = 52 to rank0
4421 12:14:40.655835 Final RX Vref Byte 1 = 49 to rank0
4422 12:14:40.659287 Final RX Vref Byte 0 = 52 to rank1
4423 12:14:40.663911 Final RX Vref Byte 1 = 49 to rank1==
4424 12:14:40.665656 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 12:14:40.669656 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4426 12:14:40.670221 ==
4427 12:14:40.672542 DQS Delay:
4428 12:14:40.673158 DQS0 = 0, DQS1 = 0
4429 12:14:40.676071 DQM Delay:
4430 12:14:40.676530 DQM0 = 37, DQM1 = 30
4431 12:14:40.676963 DQ Delay:
4432 12:14:40.679151 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4433 12:14:40.682586 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4434 12:14:40.685580 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4435 12:14:40.689112 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4436 12:14:40.689577
4437 12:14:40.689946
4438 12:14:40.699911 [DQSOSCAuto] RK0, (LSB)MR18= 0x7373, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4439 12:14:40.702306 CH1 RK0: MR19=808, MR18=7373
4440 12:14:40.708828 CH1_RK0: MR19=0x808, MR18=0x7373, DQSOSC=388, MR23=63, INC=174, DEC=116
4441 12:14:40.709313
4442 12:14:40.712500 ----->DramcWriteLeveling(PI) begin...
4443 12:14:40.713131 ==
4444 12:14:40.715493 Dram Type= 6, Freq= 0, CH_1, rank 1
4445 12:14:40.718803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4446 12:14:40.719372 ==
4447 12:14:40.722104 Write leveling (Byte 0): 29 => 29
4448 12:14:40.725525 Write leveling (Byte 1): 26 => 26
4449 12:14:40.729078 DramcWriteLeveling(PI) end<-----
4450 12:14:40.729643
4451 12:14:40.730017 ==
4452 12:14:40.732611 Dram Type= 6, Freq= 0, CH_1, rank 1
4453 12:14:40.735806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4454 12:14:40.736427 ==
4455 12:14:40.738580 [Gating] SW mode calibration
4456 12:14:40.745853 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4457 12:14:40.751902 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4458 12:14:40.755267 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4459 12:14:40.758517 0 5 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
4460 12:14:40.765184 0 5 8 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (0 0)
4461 12:14:40.769006 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 12:14:40.771787 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 12:14:40.778899 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 12:14:40.781566 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 12:14:40.785023 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 12:14:40.791994 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 12:14:40.795345 0 6 4 | B1->B0 | 2424 2d2d | 0 1 | (0 0) (0 0)
4468 12:14:40.798684 0 6 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4469 12:14:40.805088 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 12:14:40.808550 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 12:14:40.811847 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 12:14:40.818032 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 12:14:40.821219 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 12:14:40.824484 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 12:14:40.831113 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4476 12:14:40.834574 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 12:14:40.837680 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 12:14:40.844496 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 12:14:40.847841 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 12:14:40.850958 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 12:14:40.857611 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 12:14:40.861344 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 12:14:40.864165 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 12:14:40.871560 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 12:14:40.874245 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 12:14:40.877432 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 12:14:40.884460 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 12:14:40.887769 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 12:14:40.891725 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 12:14:40.897610 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4491 12:14:40.901318 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4492 12:14:40.905086 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4493 12:14:40.907334 Total UI for P1: 0, mck2ui 16
4494 12:14:40.911138 best dqsien dly found for B0: ( 0, 9, 2)
4495 12:14:40.917217 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 12:14:40.917770 Total UI for P1: 0, mck2ui 16
4497 12:14:40.924479 best dqsien dly found for B1: ( 0, 9, 8)
4498 12:14:40.927199 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4499 12:14:40.930448 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4500 12:14:40.931016
4501 12:14:40.933874 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4502 12:14:40.936891 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4503 12:14:40.941013 [Gating] SW calibration Done
4504 12:14:40.941627 ==
4505 12:14:40.943831 Dram Type= 6, Freq= 0, CH_1, rank 1
4506 12:14:40.946519 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4507 12:14:40.946988 ==
4508 12:14:40.950068 RX Vref Scan: 0
4509 12:14:40.950532
4510 12:14:40.950899 RX Vref 0 -> 0, step: 1
4511 12:14:40.951242
4512 12:14:40.953630 RX Delay -230 -> 252, step: 16
4513 12:14:40.957009 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4514 12:14:40.963405 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4515 12:14:40.967289 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4516 12:14:40.970345 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4517 12:14:40.973472 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4518 12:14:40.980209 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4519 12:14:40.983743 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4520 12:14:40.986480 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4521 12:14:40.990426 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4522 12:14:40.993361 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4523 12:14:41.000347 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4524 12:14:41.003239 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4525 12:14:41.006917 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4526 12:14:41.013153 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4527 12:14:41.016580 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4528 12:14:41.020076 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4529 12:14:41.020649 ==
4530 12:14:41.022895 Dram Type= 6, Freq= 0, CH_1, rank 1
4531 12:14:41.026991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4532 12:14:41.027457 ==
4533 12:14:41.029543 DQS Delay:
4534 12:14:41.030004 DQS0 = 0, DQS1 = 0
4535 12:14:41.034627 DQM Delay:
4536 12:14:41.035193 DQM0 = 42, DQM1 = 36
4537 12:14:41.035566 DQ Delay:
4538 12:14:41.036270 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4539 12:14:41.039959 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4540 12:14:41.043022 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4541 12:14:41.046082 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4542 12:14:41.046543
4543 12:14:41.046909
4544 12:14:41.049562 ==
4545 12:14:41.050029 Dram Type= 6, Freq= 0, CH_1, rank 1
4546 12:14:41.056145 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4547 12:14:41.056622 ==
4548 12:14:41.057053
4549 12:14:41.057397
4550 12:14:41.058990 TX Vref Scan disable
4551 12:14:41.059453 == TX Byte 0 ==
4552 12:14:41.062815 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4553 12:14:41.069855 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4554 12:14:41.070216 == TX Byte 1 ==
4555 12:14:41.075304 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4556 12:14:41.078518 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4557 12:14:41.078758 ==
4558 12:14:41.082316 Dram Type= 6, Freq= 0, CH_1, rank 1
4559 12:14:41.085299 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4560 12:14:41.085458 ==
4561 12:14:41.085581
4562 12:14:41.085697
4563 12:14:41.088379 TX Vref Scan disable
4564 12:14:41.091930 == TX Byte 0 ==
4565 12:14:41.095474 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4566 12:14:41.098726 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4567 12:14:41.101912 == TX Byte 1 ==
4568 12:14:41.105752 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4569 12:14:41.108360 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4570 12:14:41.108565
4571 12:14:41.112089 [DATLAT]
4572 12:14:41.112282 Freq=600, CH1 RK1
4573 12:14:41.112462
4574 12:14:41.115353 DATLAT Default: 0x8
4575 12:14:41.115543 0, 0xFFFF, sum = 0
4576 12:14:41.120055 1, 0xFFFF, sum = 0
4577 12:14:41.120249 2, 0xFFFF, sum = 0
4578 12:14:41.121548 3, 0xFFFF, sum = 0
4579 12:14:41.121737 4, 0xFFFF, sum = 0
4580 12:14:41.125135 5, 0xFFFF, sum = 0
4581 12:14:41.125298 6, 0xFFFF, sum = 0
4582 12:14:41.128306 7, 0x0, sum = 1
4583 12:14:41.128489 8, 0x0, sum = 2
4584 12:14:41.131866 9, 0x0, sum = 3
4585 12:14:41.132075 10, 0x0, sum = 4
4586 12:14:41.134973 best_step = 8
4587 12:14:41.135090
4588 12:14:41.135183 ==
4589 12:14:41.137978 Dram Type= 6, Freq= 0, CH_1, rank 1
4590 12:14:41.142084 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4591 12:14:41.142202 ==
4592 12:14:41.145030 RX Vref Scan: 0
4593 12:14:41.145184
4594 12:14:41.145317 RX Vref 0 -> 0, step: 1
4595 12:14:41.145443
4596 12:14:41.147892 RX Delay -195 -> 252, step: 8
4597 12:14:41.155129 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4598 12:14:41.158347 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4599 12:14:41.162184 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4600 12:14:41.165225 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4601 12:14:41.171455 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4602 12:14:41.175527 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4603 12:14:41.178593 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4604 12:14:41.181507 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4605 12:14:41.188474 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4606 12:14:41.191129 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4607 12:14:41.194930 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4608 12:14:41.198425 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4609 12:14:41.201569 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4610 12:14:41.208480 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4611 12:14:41.211501 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4612 12:14:41.214953 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4613 12:14:41.215517 ==
4614 12:14:41.218741 Dram Type= 6, Freq= 0, CH_1, rank 1
4615 12:14:41.224905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4616 12:14:41.225158 ==
4617 12:14:41.225463 DQS Delay:
4618 12:14:41.227758 DQS0 = 0, DQS1 = 0
4619 12:14:41.228006 DQM Delay:
4620 12:14:41.228262 DQM0 = 37, DQM1 = 30
4621 12:14:41.230899 DQ Delay:
4622 12:14:41.234553 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4623 12:14:41.239386 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =32
4624 12:14:41.241937 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4625 12:14:41.244523 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4626 12:14:41.244665
4627 12:14:41.244821
4628 12:14:41.251891 [DQSOSCAuto] RK1, (LSB)MR18= 0x5a5a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4629 12:14:41.254062 CH1 RK1: MR19=808, MR18=5A5A
4630 12:14:41.260930 CH1_RK1: MR19=0x808, MR18=0x5A5A, DQSOSC=392, MR23=63, INC=170, DEC=113
4631 12:14:41.264601 [RxdqsGatingPostProcess] freq 600
4632 12:14:41.267832 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4633 12:14:41.270495 Pre-setting of DQS Precalculation
4634 12:14:41.278040 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4635 12:14:41.284621 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4636 12:14:41.290786 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4637 12:14:41.291221
4638 12:14:41.291661
4639 12:14:41.294166 [Calibration Summary] 1200 Mbps
4640 12:14:41.294476 CH 0, Rank 0
4641 12:14:41.297079 SW Impedance : PASS
4642 12:14:41.300674 DUTY Scan : NO K
4643 12:14:41.300935 ZQ Calibration : PASS
4644 12:14:41.304006 Jitter Meter : NO K
4645 12:14:41.307770 CBT Training : PASS
4646 12:14:41.307959 Write leveling : PASS
4647 12:14:41.310596 RX DQS gating : PASS
4648 12:14:41.313575 RX DQ/DQS(RDDQC) : PASS
4649 12:14:41.313732 TX DQ/DQS : PASS
4650 12:14:41.317195 RX DATLAT : PASS
4651 12:14:41.320493 RX DQ/DQS(Engine): PASS
4652 12:14:41.320649 TX OE : NO K
4653 12:14:41.323461 All Pass.
4654 12:14:41.323618
4655 12:14:41.323777 CH 0, Rank 1
4656 12:14:41.327347 SW Impedance : PASS
4657 12:14:41.327548 DUTY Scan : NO K
4658 12:14:41.330630 ZQ Calibration : PASS
4659 12:14:41.333915 Jitter Meter : NO K
4660 12:14:41.334073 CBT Training : PASS
4661 12:14:41.337043 Write leveling : PASS
4662 12:14:41.340524 RX DQS gating : PASS
4663 12:14:41.340680 RX DQ/DQS(RDDQC) : PASS
4664 12:14:41.343714 TX DQ/DQS : PASS
4665 12:14:41.343870 RX DATLAT : PASS
4666 12:14:41.346768 RX DQ/DQS(Engine): PASS
4667 12:14:41.350019 TX OE : NO K
4668 12:14:41.350253 All Pass.
4669 12:14:41.350419
4670 12:14:41.350572 CH 1, Rank 0
4671 12:14:41.353863 SW Impedance : PASS
4672 12:14:41.356683 DUTY Scan : NO K
4673 12:14:41.356857 ZQ Calibration : PASS
4674 12:14:41.360618 Jitter Meter : NO K
4675 12:14:41.363339 CBT Training : PASS
4676 12:14:41.363496 Write leveling : PASS
4677 12:14:41.367149 RX DQS gating : PASS
4678 12:14:41.370018 RX DQ/DQS(RDDQC) : PASS
4679 12:14:41.370175 TX DQ/DQS : PASS
4680 12:14:41.373562 RX DATLAT : PASS
4681 12:14:41.377231 RX DQ/DQS(Engine): PASS
4682 12:14:41.377389 TX OE : NO K
4683 12:14:41.379962 All Pass.
4684 12:14:41.380154
4685 12:14:41.380337 CH 1, Rank 1
4686 12:14:41.383366 SW Impedance : PASS
4687 12:14:41.383523 DUTY Scan : NO K
4688 12:14:41.386704 ZQ Calibration : PASS
4689 12:14:41.389779 Jitter Meter : NO K
4690 12:14:41.389937 CBT Training : PASS
4691 12:14:41.393279 Write leveling : PASS
4692 12:14:41.396209 RX DQS gating : PASS
4693 12:14:41.396366 RX DQ/DQS(RDDQC) : PASS
4694 12:14:41.400481 TX DQ/DQS : PASS
4695 12:14:41.402973 RX DATLAT : PASS
4696 12:14:41.403130 RX DQ/DQS(Engine): PASS
4697 12:14:41.406547 TX OE : NO K
4698 12:14:41.406704 All Pass.
4699 12:14:41.406867
4700 12:14:41.410802 DramC Write-DBI off
4701 12:14:41.413764 PER_BANK_REFRESH: Hybrid Mode
4702 12:14:41.414004 TX_TRACKING: ON
4703 12:14:41.422871 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4704 12:14:41.426501 [FAST_K] Save calibration result to emmc
4705 12:14:41.430421 dramc_set_vcore_voltage set vcore to 662500
4706 12:14:41.433524 Read voltage for 933, 3
4707 12:14:41.433676 Vio18 = 0
4708 12:14:41.433797 Vcore = 662500
4709 12:14:41.436329 Vdram = 0
4710 12:14:41.436478 Vddq = 0
4711 12:14:41.436598 Vmddr = 0
4712 12:14:41.442568 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4713 12:14:41.445950 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4714 12:14:41.449394 MEM_TYPE=3, freq_sel=17
4715 12:14:41.452430 sv_algorithm_assistance_LP4_1600
4716 12:14:41.456167 ============ PULL DRAM RESETB DOWN ============
4717 12:14:41.459207 ========== PULL DRAM RESETB DOWN end =========
4718 12:14:41.466523 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4719 12:14:41.469031 ===================================
4720 12:14:41.469279 LPDDR4 DRAM CONFIGURATION
4721 12:14:41.472329 ===================================
4722 12:14:41.475630 EX_ROW_EN[0] = 0x0
4723 12:14:41.479363 EX_ROW_EN[1] = 0x0
4724 12:14:41.479616 LP4Y_EN = 0x0
4725 12:14:41.482265 WORK_FSP = 0x0
4726 12:14:41.482503 WL = 0x3
4727 12:14:41.487424 RL = 0x3
4728 12:14:41.487629 BL = 0x2
4729 12:14:41.489270 RPST = 0x0
4730 12:14:41.489405 RD_PRE = 0x0
4731 12:14:41.492407 WR_PRE = 0x1
4732 12:14:41.492567 WR_PST = 0x0
4733 12:14:41.495368 DBI_WR = 0x0
4734 12:14:41.495476 DBI_RD = 0x0
4735 12:14:41.498967 OTF = 0x1
4736 12:14:41.502632 ===================================
4737 12:14:41.505552 ===================================
4738 12:14:41.505658 ANA top config
4739 12:14:41.509506 ===================================
4740 12:14:41.514569 DLL_ASYNC_EN = 0
4741 12:14:41.515427 ALL_SLAVE_EN = 1
4742 12:14:41.518726 NEW_RANK_MODE = 1
4743 12:14:41.518907 DLL_IDLE_MODE = 1
4744 12:14:41.522691 LP45_APHY_COMB_EN = 1
4745 12:14:41.525741 TX_ODT_DIS = 1
4746 12:14:41.529054 NEW_8X_MODE = 1
4747 12:14:41.532276 ===================================
4748 12:14:41.535495 ===================================
4749 12:14:41.538384 data_rate = 1866
4750 12:14:41.541894 CKR = 1
4751 12:14:41.542129 DQ_P2S_RATIO = 8
4752 12:14:41.545165 ===================================
4753 12:14:41.548723 CA_P2S_RATIO = 8
4754 12:14:41.551563 DQ_CA_OPEN = 0
4755 12:14:41.555186 DQ_SEMI_OPEN = 0
4756 12:14:41.558931 CA_SEMI_OPEN = 0
4757 12:14:41.559323 CA_FULL_RATE = 0
4758 12:14:41.562395 DQ_CKDIV4_EN = 1
4759 12:14:41.565675 CA_CKDIV4_EN = 1
4760 12:14:41.568559 CA_PREDIV_EN = 0
4761 12:14:41.571966 PH8_DLY = 0
4762 12:14:41.575652 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4763 12:14:41.576220 DQ_AAMCK_DIV = 4
4764 12:14:41.578582 CA_AAMCK_DIV = 4
4765 12:14:41.582695 CA_ADMCK_DIV = 4
4766 12:14:41.585339 DQ_TRACK_CA_EN = 0
4767 12:14:41.588393 CA_PICK = 933
4768 12:14:41.592187 CA_MCKIO = 933
4769 12:14:41.595190 MCKIO_SEMI = 0
4770 12:14:41.598659 PLL_FREQ = 3732
4771 12:14:41.599203 DQ_UI_PI_RATIO = 32
4772 12:14:41.601566 CA_UI_PI_RATIO = 0
4773 12:14:41.604796 ===================================
4774 12:14:41.609473 ===================================
4775 12:14:41.611675 memory_type:LPDDR4
4776 12:14:41.614916 GP_NUM : 10
4777 12:14:41.615494 SRAM_EN : 1
4778 12:14:41.619563 MD32_EN : 0
4779 12:14:41.622738 ===================================
4780 12:14:41.623315 [ANA_INIT] >>>>>>>>>>>>>>
4781 12:14:41.624833 <<<<<< [CONFIGURE PHASE]: ANA_TX
4782 12:14:41.628522 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4783 12:14:41.631451 ===================================
4784 12:14:41.635245 data_rate = 1866,PCW = 0X8f00
4785 12:14:41.637974 ===================================
4786 12:14:41.642345 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4787 12:14:41.648035 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4788 12:14:41.654650 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4789 12:14:41.657531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4790 12:14:41.660963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4791 12:14:41.664678 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4792 12:14:41.667465 [ANA_INIT] flow start
4793 12:14:41.667949 [ANA_INIT] PLL >>>>>>>>
4794 12:14:41.671753 [ANA_INIT] PLL <<<<<<<<
4795 12:14:41.674321 [ANA_INIT] MIDPI >>>>>>>>
4796 12:14:41.677841 [ANA_INIT] MIDPI <<<<<<<<
4797 12:14:41.678324 [ANA_INIT] DLL >>>>>>>>
4798 12:14:41.680994 [ANA_INIT] flow end
4799 12:14:41.684747 ============ LP4 DIFF to SE enter ============
4800 12:14:41.688221 ============ LP4 DIFF to SE exit ============
4801 12:14:41.690630 [ANA_INIT] <<<<<<<<<<<<<
4802 12:14:41.694374 [Flow] Enable top DCM control >>>>>
4803 12:14:41.698502 [Flow] Enable top DCM control <<<<<
4804 12:14:41.700656 Enable DLL master slave shuffle
4805 12:14:41.707521 ==============================================================
4806 12:14:41.708094 Gating Mode config
4807 12:14:41.714011 ==============================================================
4808 12:14:41.714587 Config description:
4809 12:14:41.724481 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4810 12:14:41.731410 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4811 12:14:41.736970 SELPH_MODE 0: By rank 1: By Phase
4812 12:14:41.740648 ==============================================================
4813 12:14:41.743689 GAT_TRACK_EN = 1
4814 12:14:41.746995 RX_GATING_MODE = 2
4815 12:14:41.750877 RX_GATING_TRACK_MODE = 2
4816 12:14:41.754281 SELPH_MODE = 1
4817 12:14:41.757520 PICG_EARLY_EN = 1
4818 12:14:41.760246 VALID_LAT_VALUE = 1
4819 12:14:41.766984 ==============================================================
4820 12:14:41.770700 Enter into Gating configuration >>>>
4821 12:14:41.773602 Exit from Gating configuration <<<<
4822 12:14:41.774086 Enter into DVFS_PRE_config >>>>>
4823 12:14:41.786606 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4824 12:14:41.789696 Exit from DVFS_PRE_config <<<<<
4825 12:14:41.793506 Enter into PICG configuration >>>>
4826 12:14:41.796664 Exit from PICG configuration <<<<
4827 12:14:41.797282 [RX_INPUT] configuration >>>>>
4828 12:14:41.799738 [RX_INPUT] configuration <<<<<
4829 12:14:41.806521 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4830 12:14:41.813335 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4831 12:14:41.816660 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4832 12:14:41.823968 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4833 12:14:41.829484 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4834 12:14:41.836355 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4835 12:14:41.839691 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4836 12:14:41.843555 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4837 12:14:41.849283 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4838 12:14:41.852853 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4839 12:14:41.856027 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4840 12:14:41.863153 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4841 12:14:41.865744 ===================================
4842 12:14:41.866205 LPDDR4 DRAM CONFIGURATION
4843 12:14:41.869969 ===================================
4844 12:14:41.872632 EX_ROW_EN[0] = 0x0
4845 12:14:41.873258 EX_ROW_EN[1] = 0x0
4846 12:14:41.875933 LP4Y_EN = 0x0
4847 12:14:41.880161 WORK_FSP = 0x0
4848 12:14:41.880767 WL = 0x3
4849 12:14:41.883402 RL = 0x3
4850 12:14:41.883972 BL = 0x2
4851 12:14:41.886198 RPST = 0x0
4852 12:14:41.886770 RD_PRE = 0x0
4853 12:14:41.889560 WR_PRE = 0x1
4854 12:14:41.890037 WR_PST = 0x0
4855 12:14:41.892669 DBI_WR = 0x0
4856 12:14:41.893287 DBI_RD = 0x0
4857 12:14:41.896207 OTF = 0x1
4858 12:14:41.898874 ===================================
4859 12:14:41.902162 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4860 12:14:41.905459 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4861 12:14:41.912060 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4862 12:14:41.915468 ===================================
4863 12:14:41.916039 LPDDR4 DRAM CONFIGURATION
4864 12:14:41.918898 ===================================
4865 12:14:41.922021 EX_ROW_EN[0] = 0x10
4866 12:14:41.922588 EX_ROW_EN[1] = 0x0
4867 12:14:41.926036 LP4Y_EN = 0x0
4868 12:14:41.928612 WORK_FSP = 0x0
4869 12:14:41.929231 WL = 0x3
4870 12:14:41.931864 RL = 0x3
4871 12:14:41.932431 BL = 0x2
4872 12:14:41.935489 RPST = 0x0
4873 12:14:41.936058 RD_PRE = 0x0
4874 12:14:41.939076 WR_PRE = 0x1
4875 12:14:41.939649 WR_PST = 0x0
4876 12:14:41.941918 DBI_WR = 0x0
4877 12:14:41.942491 DBI_RD = 0x0
4878 12:14:41.945325 OTF = 0x1
4879 12:14:41.948360 ===================================
4880 12:14:41.955552 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4881 12:14:41.958429 nWR fixed to 30
4882 12:14:41.958958 [ModeRegInit_LP4] CH0 RK0
4883 12:14:41.961551 [ModeRegInit_LP4] CH0 RK1
4884 12:14:41.965288 [ModeRegInit_LP4] CH1 RK0
4885 12:14:41.965824 [ModeRegInit_LP4] CH1 RK1
4886 12:14:41.968403 match AC timing 8
4887 12:14:41.971618 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4888 12:14:41.974910 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4889 12:14:41.981542 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4890 12:14:41.984863 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4891 12:14:41.991593 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4892 12:14:41.992167 ==
4893 12:14:41.994401 Dram Type= 6, Freq= 0, CH_0, rank 0
4894 12:14:41.998196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4895 12:14:41.998766 ==
4896 12:14:42.004238 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4897 12:14:42.011297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4898 12:14:42.015256 [CA 0] Center 38 (8~69) winsize 62
4899 12:14:42.017393 [CA 1] Center 38 (8~69) winsize 62
4900 12:14:42.021368 [CA 2] Center 36 (6~67) winsize 62
4901 12:14:42.024607 [CA 3] Center 35 (5~66) winsize 62
4902 12:14:42.027695 [CA 4] Center 35 (5~65) winsize 61
4903 12:14:42.031500 [CA 5] Center 34 (4~65) winsize 62
4904 12:14:42.032076
4905 12:14:42.034426 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4906 12:14:42.035005
4907 12:14:42.037686 [CATrainingPosCal] consider 1 rank data
4908 12:14:42.040982 u2DelayCellTimex100 = 270/100 ps
4909 12:14:42.044388 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4910 12:14:42.048212 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4911 12:14:42.050833 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4912 12:14:42.054057 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4913 12:14:42.057220 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4914 12:14:42.061169 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4915 12:14:42.061771
4916 12:14:42.067489 CA PerBit enable=1, Macro0, CA PI delay=34
4917 12:14:42.068052
4918 12:14:42.070793 [CBTSetCACLKResult] CA Dly = 34
4919 12:14:42.071277 CS Dly: 7 (0~38)
4920 12:14:42.071765 ==
4921 12:14:42.073956 Dram Type= 6, Freq= 0, CH_0, rank 1
4922 12:14:42.077098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4923 12:14:42.077562 ==
4924 12:14:42.084024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4925 12:14:42.091511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4926 12:14:42.093842 [CA 0] Center 38 (8~69) winsize 62
4927 12:14:42.097614 [CA 1] Center 38 (8~69) winsize 62
4928 12:14:42.100703 [CA 2] Center 36 (6~67) winsize 62
4929 12:14:42.104102 [CA 3] Center 35 (5~66) winsize 62
4930 12:14:42.108018 [CA 4] Center 34 (4~65) winsize 62
4931 12:14:42.110260 [CA 5] Center 34 (4~65) winsize 62
4932 12:14:42.110739
4933 12:14:42.113813 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4934 12:14:42.114390
4935 12:14:42.117334 [CATrainingPosCal] consider 2 rank data
4936 12:14:42.120470 u2DelayCellTimex100 = 270/100 ps
4937 12:14:42.123917 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4938 12:14:42.126884 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4939 12:14:42.130649 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4940 12:14:42.134010 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4941 12:14:42.140025 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4942 12:14:42.143394 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4943 12:14:42.143925
4944 12:14:42.146599 CA PerBit enable=1, Macro0, CA PI delay=34
4945 12:14:42.147117
4946 12:14:42.149848 [CBTSetCACLKResult] CA Dly = 34
4947 12:14:42.150498 CS Dly: 7 (0~39)
4948 12:14:42.150988
4949 12:14:42.153046 ----->DramcWriteLeveling(PI) begin...
4950 12:14:42.153530 ==
4951 12:14:42.156654 Dram Type= 6, Freq= 0, CH_0, rank 0
4952 12:14:42.166638 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4953 12:14:42.167119 ==
4954 12:14:42.167620 Write leveling (Byte 0): 29 => 29
4955 12:14:42.169818 Write leveling (Byte 1): 29 => 29
4956 12:14:42.170413 DramcWriteLeveling(PI) end<-----
4957 12:14:42.170907
4958 12:14:42.173477 ==
4959 12:14:42.176797 Dram Type= 6, Freq= 0, CH_0, rank 0
4960 12:14:42.179977 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4961 12:14:42.180458 ==
4962 12:14:42.182877 [Gating] SW mode calibration
4963 12:14:42.189578 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4964 12:14:42.192887 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4965 12:14:42.199721 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4966 12:14:42.202693 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4967 12:14:42.205847 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4968 12:14:42.212807 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4969 12:14:42.216512 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4970 12:14:42.219000 0 10 20 | B1->B0 | 3232 2e2e | 0 0 | (0 1) (0 0)
4971 12:14:42.226909 0 10 24 | B1->B0 | 2e2e 2626 | 1 0 | (1 0) (1 0)
4972 12:14:42.229018 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4973 12:14:42.233152 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4974 12:14:42.239087 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4975 12:14:42.242740 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4976 12:14:42.246384 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4977 12:14:42.252222 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4978 12:14:42.255719 0 11 20 | B1->B0 | 2727 2929 | 0 0 | (0 0) (0 0)
4979 12:14:42.259388 0 11 24 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4980 12:14:42.266051 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4981 12:14:42.268996 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4982 12:14:42.272254 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4983 12:14:42.278952 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4984 12:14:42.282631 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4985 12:14:42.285176 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4986 12:14:42.293237 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4987 12:14:42.295569 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4988 12:14:42.298619 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4989 12:14:42.305233 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4990 12:14:42.308785 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4991 12:14:42.311707 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4992 12:14:42.318516 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4993 12:14:42.322230 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4994 12:14:42.325544 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4995 12:14:42.331543 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4996 12:14:42.335230 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4997 12:14:42.339052 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4998 12:14:42.344920 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 12:14:42.347885 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5000 12:14:42.351180 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 12:14:42.358134 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5002 12:14:42.361528 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5003 12:14:42.365193 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5004 12:14:42.367757 Total UI for P1: 0, mck2ui 16
5005 12:14:42.371271 best dqsien dly found for B0: ( 0, 14, 20)
5006 12:14:42.375627 Total UI for P1: 0, mck2ui 16
5007 12:14:42.377943 best dqsien dly found for B1: ( 0, 14, 20)
5008 12:14:42.380977 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5009 12:14:42.384303 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5010 12:14:42.384811
5011 12:14:42.391994 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5012 12:14:42.394413 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5013 12:14:42.397670 [Gating] SW calibration Done
5014 12:14:42.398227 ==
5015 12:14:42.401334 Dram Type= 6, Freq= 0, CH_0, rank 0
5016 12:14:42.404511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5017 12:14:42.405146 ==
5018 12:14:42.405547 RX Vref Scan: 0
5019 12:14:42.405927
5020 12:14:42.408852 RX Vref 0 -> 0, step: 1
5021 12:14:42.409315
5022 12:14:42.410979 RX Delay -80 -> 252, step: 8
5023 12:14:42.414410 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5024 12:14:42.418275 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5025 12:14:42.420556 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5026 12:14:42.427149 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5027 12:14:42.430556 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5028 12:14:42.434166 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5029 12:14:42.436967 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5030 12:14:42.440623 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5031 12:14:42.447511 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5032 12:14:42.450608 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5033 12:14:42.455195 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5034 12:14:42.457106 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5035 12:14:42.460315 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5036 12:14:42.466928 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5037 12:14:42.470581 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5038 12:14:42.473685 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5039 12:14:42.474212 ==
5040 12:14:42.476894 Dram Type= 6, Freq= 0, CH_0, rank 0
5041 12:14:42.480891 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5042 12:14:42.481358 ==
5043 12:14:42.484446 DQS Delay:
5044 12:14:42.485054 DQS0 = 0, DQS1 = 0
5045 12:14:42.487471 DQM Delay:
5046 12:14:42.488049 DQM0 = 96, DQM1 = 84
5047 12:14:42.488646 DQ Delay:
5048 12:14:42.490775 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5049 12:14:42.493321 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5050 12:14:42.496839 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =75
5051 12:14:42.500198 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5052 12:14:42.500816
5053 12:14:42.501208
5054 12:14:42.503994 ==
5055 12:14:42.506786 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 12:14:42.509893 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5057 12:14:42.510377 ==
5058 12:14:42.510750
5059 12:14:42.511093
5060 12:14:42.513097 TX Vref Scan disable
5061 12:14:42.513562 == TX Byte 0 ==
5062 12:14:42.517291 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5063 12:14:42.523443 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5064 12:14:42.523999 == TX Byte 1 ==
5065 12:14:42.529541 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5066 12:14:42.533078 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5067 12:14:42.533637 ==
5068 12:14:42.536252 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 12:14:42.540355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5070 12:14:42.541155 ==
5071 12:14:42.541619
5072 12:14:42.541973
5073 12:14:42.543033 TX Vref Scan disable
5074 12:14:42.546870 == TX Byte 0 ==
5075 12:14:42.549439 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5076 12:14:42.552888 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5077 12:14:42.555935 == TX Byte 1 ==
5078 12:14:42.559409 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5079 12:14:42.563163 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5080 12:14:42.563725
5081 12:14:42.566315 [DATLAT]
5082 12:14:42.566872 Freq=933, CH0 RK0
5083 12:14:42.567247
5084 12:14:42.569532 DATLAT Default: 0xd
5085 12:14:42.569993 0, 0xFFFF, sum = 0
5086 12:14:42.573959 1, 0xFFFF, sum = 0
5087 12:14:42.574525 2, 0xFFFF, sum = 0
5088 12:14:42.576416 3, 0xFFFF, sum = 0
5089 12:14:42.576937 4, 0xFFFF, sum = 0
5090 12:14:42.579060 5, 0xFFFF, sum = 0
5091 12:14:42.579530 6, 0xFFFF, sum = 0
5092 12:14:42.582637 7, 0xFFFF, sum = 0
5093 12:14:42.583216 8, 0xFFFF, sum = 0
5094 12:14:42.586353 9, 0xFFFF, sum = 0
5095 12:14:42.586917 10, 0x0, sum = 1
5096 12:14:42.590310 11, 0x0, sum = 2
5097 12:14:42.590828 12, 0x0, sum = 3
5098 12:14:42.592874 13, 0x0, sum = 4
5099 12:14:42.593344 best_step = 11
5100 12:14:42.593716
5101 12:14:42.594067 ==
5102 12:14:42.596082 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 12:14:42.602381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5104 12:14:42.602930 ==
5105 12:14:42.603304 RX Vref Scan: 1
5106 12:14:42.603650
5107 12:14:42.606398 RX Vref 0 -> 0, step: 1
5108 12:14:42.606860
5109 12:14:42.609552 RX Delay -69 -> 252, step: 4
5110 12:14:42.610015
5111 12:14:42.613122 Set Vref, RX VrefLevel [Byte0]: 46
5112 12:14:42.615326 [Byte1]: 50
5113 12:14:42.615790
5114 12:14:42.618916 Final RX Vref Byte 0 = 46 to rank0
5115 12:14:42.622348 Final RX Vref Byte 1 = 50 to rank0
5116 12:14:42.626237 Final RX Vref Byte 0 = 46 to rank1
5117 12:14:42.628607 Final RX Vref Byte 1 = 50 to rank1==
5118 12:14:42.632871 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 12:14:42.635529 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5120 12:14:42.636090 ==
5121 12:14:42.638938 DQS Delay:
5122 12:14:42.639516 DQS0 = 0, DQS1 = 0
5123 12:14:42.642453 DQM Delay:
5124 12:14:42.643013 DQM0 = 97, DQM1 = 87
5125 12:14:42.643386 DQ Delay:
5126 12:14:42.645579 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =92
5127 12:14:42.649040 DQ4 =100, DQ5 =90, DQ6 =104, DQ7 =106
5128 12:14:42.651752 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =78
5129 12:14:42.655142 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =98
5130 12:14:42.658343
5131 12:14:42.658807
5132 12:14:42.666209 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5133 12:14:42.668818 CH0 RK0: MR19=505, MR18=2626
5134 12:14:42.676333 CH0_RK0: MR19=0x505, MR18=0x2626, DQSOSC=409, MR23=63, INC=64, DEC=43
5135 12:14:42.676939
5136 12:14:42.679183 ----->DramcWriteLeveling(PI) begin...
5137 12:14:42.679747 ==
5138 12:14:42.681510 Dram Type= 6, Freq= 0, CH_0, rank 1
5139 12:14:42.684931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5140 12:14:42.685399 ==
5141 12:14:42.688038 Write leveling (Byte 0): 28 => 28
5142 12:14:42.691593 Write leveling (Byte 1): 27 => 27
5143 12:14:42.696154 DramcWriteLeveling(PI) end<-----
5144 12:14:42.696754
5145 12:14:42.697140 ==
5146 12:14:42.697987 Dram Type= 6, Freq= 0, CH_0, rank 1
5147 12:14:42.701372 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5148 12:14:42.701840 ==
5149 12:14:42.704996 [Gating] SW mode calibration
5150 12:14:42.713264 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5151 12:14:42.718098 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5152 12:14:42.721536 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 12:14:42.724750 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 12:14:42.731878 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 12:14:42.735568 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 12:14:42.737949 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 12:14:42.744782 0 10 20 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 0)
5158 12:14:42.748650 0 10 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5159 12:14:42.751167 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 12:14:42.758126 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 12:14:42.760869 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 12:14:42.764570 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 12:14:42.771278 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 12:14:42.774706 0 11 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5165 12:14:42.777816 0 11 20 | B1->B0 | 2e2e 3838 | 0 0 | (1 1) (0 0)
5166 12:14:42.785462 0 11 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5167 12:14:42.788123 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 12:14:42.790847 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 12:14:42.797965 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 12:14:42.801065 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 12:14:42.804417 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 12:14:42.811267 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 12:14:42.813783 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5174 12:14:42.817647 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5175 12:14:42.824064 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 12:14:42.827656 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 12:14:42.831538 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 12:14:42.837136 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 12:14:42.840770 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 12:14:42.843862 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 12:14:42.850220 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 12:14:42.853803 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 12:14:42.857333 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 12:14:42.864384 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 12:14:42.866985 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 12:14:42.870157 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 12:14:42.877057 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 12:14:42.880467 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 12:14:42.883695 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5190 12:14:42.890408 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 12:14:42.890955 Total UI for P1: 0, mck2ui 16
5192 12:14:42.893957 best dqsien dly found for B0: ( 0, 14, 22)
5193 12:14:42.896952 Total UI for P1: 0, mck2ui 16
5194 12:14:42.900911 best dqsien dly found for B1: ( 0, 14, 20)
5195 12:14:42.907028 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5196 12:14:42.911161 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5197 12:14:42.911718
5198 12:14:42.913246 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5199 12:14:42.916890 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5200 12:14:42.920265 [Gating] SW calibration Done
5201 12:14:42.920871 ==
5202 12:14:42.923909 Dram Type= 6, Freq= 0, CH_0, rank 1
5203 12:14:42.926608 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5204 12:14:42.927070 ==
5205 12:14:42.930122 RX Vref Scan: 0
5206 12:14:42.930679
5207 12:14:42.931045 RX Vref 0 -> 0, step: 1
5208 12:14:42.931387
5209 12:14:42.933206 RX Delay -80 -> 252, step: 8
5210 12:14:42.937306 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5211 12:14:42.943896 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5212 12:14:42.947830 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5213 12:14:42.950051 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5214 12:14:42.954082 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5215 12:14:42.955941 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5216 12:14:42.960701 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5217 12:14:42.967593 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5218 12:14:42.969176 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5219 12:14:42.972866 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5220 12:14:42.976327 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5221 12:14:42.979694 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5222 12:14:42.986919 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5223 12:14:42.989433 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5224 12:14:42.992886 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5225 12:14:42.996088 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5226 12:14:42.996545 ==
5227 12:14:42.999653 Dram Type= 6, Freq= 0, CH_0, rank 1
5228 12:14:43.002976 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5229 12:14:43.006045 ==
5230 12:14:43.006502 DQS Delay:
5231 12:14:43.006865 DQS0 = 0, DQS1 = 0
5232 12:14:43.009189 DQM Delay:
5233 12:14:43.009661 DQM0 = 96, DQM1 = 85
5234 12:14:43.012823 DQ Delay:
5235 12:14:43.015662 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5236 12:14:43.016121 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5237 12:14:43.019245 DQ8 =75, DQ9 =75, DQ10 =83, DQ11 =79
5238 12:14:43.026145 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =95
5239 12:14:43.026699
5240 12:14:43.027062
5241 12:14:43.027397 ==
5242 12:14:43.028821 Dram Type= 6, Freq= 0, CH_0, rank 1
5243 12:14:43.032410 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5244 12:14:43.032923 ==
5245 12:14:43.033296
5246 12:14:43.033633
5247 12:14:43.036327 TX Vref Scan disable
5248 12:14:43.036831 == TX Byte 0 ==
5249 12:14:43.042226 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5250 12:14:43.045417 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5251 12:14:43.045944 == TX Byte 1 ==
5252 12:14:43.052649 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5253 12:14:43.055204 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5254 12:14:43.055664 ==
5255 12:14:43.058872 Dram Type= 6, Freq= 0, CH_0, rank 1
5256 12:14:43.062218 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5257 12:14:43.062678 ==
5258 12:14:43.063041
5259 12:14:43.063380
5260 12:14:43.066144 TX Vref Scan disable
5261 12:14:43.068943 == TX Byte 0 ==
5262 12:14:43.072525 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5263 12:14:43.075754 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5264 12:14:43.078911 == TX Byte 1 ==
5265 12:14:43.082393 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5266 12:14:43.085394 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5267 12:14:43.085860
5268 12:14:43.088947 [DATLAT]
5269 12:14:43.089503 Freq=933, CH0 RK1
5270 12:14:43.089877
5271 12:14:43.092072 DATLAT Default: 0xb
5272 12:14:43.092634 0, 0xFFFF, sum = 0
5273 12:14:43.095685 1, 0xFFFF, sum = 0
5274 12:14:43.096154 2, 0xFFFF, sum = 0
5275 12:14:43.099002 3, 0xFFFF, sum = 0
5276 12:14:43.099565 4, 0xFFFF, sum = 0
5277 12:14:43.102096 5, 0xFFFF, sum = 0
5278 12:14:43.102569 6, 0xFFFF, sum = 0
5279 12:14:43.105122 7, 0xFFFF, sum = 0
5280 12:14:43.108691 8, 0xFFFF, sum = 0
5281 12:14:43.109347 9, 0xFFFF, sum = 0
5282 12:14:43.112278 10, 0x0, sum = 1
5283 12:14:43.112884 11, 0x0, sum = 2
5284 12:14:43.113267 12, 0x0, sum = 3
5285 12:14:43.115255 13, 0x0, sum = 4
5286 12:14:43.115724 best_step = 11
5287 12:14:43.116107
5288 12:14:43.116455 ==
5289 12:14:43.118133 Dram Type= 6, Freq= 0, CH_0, rank 1
5290 12:14:43.124959 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5291 12:14:43.125517 ==
5292 12:14:43.125896 RX Vref Scan: 0
5293 12:14:43.126294
5294 12:14:43.128175 RX Vref 0 -> 0, step: 1
5295 12:14:43.128637
5296 12:14:43.131687 RX Delay -61 -> 252, step: 4
5297 12:14:43.134950 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5298 12:14:43.141903 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5299 12:14:43.145226 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5300 12:14:43.148422 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5301 12:14:43.151462 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5302 12:14:43.154796 iDelay=199, Bit 5, Center 90 (-1 ~ 182) 184
5303 12:14:43.158162 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5304 12:14:43.165246 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5305 12:14:43.167959 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5306 12:14:43.171424 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5307 12:14:43.174642 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5308 12:14:43.177950 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5309 12:14:43.184676 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5310 12:14:43.188279 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5311 12:14:43.191307 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5312 12:14:43.194789 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5313 12:14:43.195347 ==
5314 12:14:43.198130 Dram Type= 6, Freq= 0, CH_0, rank 1
5315 12:14:43.201651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5316 12:14:43.204575 ==
5317 12:14:43.205069 DQS Delay:
5318 12:14:43.205432 DQS0 = 0, DQS1 = 0
5319 12:14:43.208215 DQM Delay:
5320 12:14:43.208666 DQM0 = 97, DQM1 = 86
5321 12:14:43.211428 DQ Delay:
5322 12:14:43.211978 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5323 12:14:43.214190 DQ4 =102, DQ5 =90, DQ6 =104, DQ7 =106
5324 12:14:43.217865 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5325 12:14:43.221740 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =94
5326 12:14:43.224850
5327 12:14:43.225407
5328 12:14:43.230829 [DQSOSCAuto] RK1, (LSB)MR18= 0x2727, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5329 12:14:43.235167 CH0 RK1: MR19=505, MR18=2727
5330 12:14:43.241259 CH0_RK1: MR19=0x505, MR18=0x2727, DQSOSC=409, MR23=63, INC=64, DEC=43
5331 12:14:43.244416 [RxdqsGatingPostProcess] freq 933
5332 12:14:43.247443 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5333 12:14:43.251110 Pre-setting of DQS Precalculation
5334 12:14:43.257248 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5335 12:14:43.257707 ==
5336 12:14:43.260488 Dram Type= 6, Freq= 0, CH_1, rank 0
5337 12:14:43.264103 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5338 12:14:43.264514 ==
5339 12:14:43.271082 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5340 12:14:43.273728 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5341 12:14:43.278325 [CA 0] Center 37 (7~68) winsize 62
5342 12:14:43.281523 [CA 1] Center 37 (6~68) winsize 63
5343 12:14:43.286017 [CA 2] Center 34 (4~65) winsize 62
5344 12:14:43.288425 [CA 3] Center 34 (4~65) winsize 62
5345 12:14:43.291416 [CA 4] Center 33 (2~64) winsize 63
5346 12:14:43.294886 [CA 5] Center 33 (2~64) winsize 63
5347 12:14:43.295273
5348 12:14:43.298272 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5349 12:14:43.298595
5350 12:14:43.301326 [CATrainingPosCal] consider 1 rank data
5351 12:14:43.304988 u2DelayCellTimex100 = 270/100 ps
5352 12:14:43.308191 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5353 12:14:43.314827 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5354 12:14:43.318330 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5355 12:14:43.322023 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5356 12:14:43.324680 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5357 12:14:43.329340 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5358 12:14:43.329897
5359 12:14:43.331808 CA PerBit enable=1, Macro0, CA PI delay=33
5360 12:14:43.332359
5361 12:14:43.336200 [CBTSetCACLKResult] CA Dly = 33
5362 12:14:43.336806 CS Dly: 5 (0~36)
5363 12:14:43.338863 ==
5364 12:14:43.341442 Dram Type= 6, Freq= 0, CH_1, rank 1
5365 12:14:43.345745 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5366 12:14:43.346304 ==
5367 12:14:43.348121 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5368 12:14:43.354732 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5369 12:14:43.358032 [CA 0] Center 37 (7~68) winsize 62
5370 12:14:43.361291 [CA 1] Center 37 (6~68) winsize 63
5371 12:14:43.365480 [CA 2] Center 34 (4~65) winsize 62
5372 12:14:43.368156 [CA 3] Center 33 (3~64) winsize 62
5373 12:14:43.371677 [CA 4] Center 33 (2~64) winsize 63
5374 12:14:43.374803 [CA 5] Center 33 (2~64) winsize 63
5375 12:14:43.375278
5376 12:14:43.377866 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5377 12:14:43.378328
5378 12:14:43.381468 [CATrainingPosCal] consider 2 rank data
5379 12:14:43.384909 u2DelayCellTimex100 = 270/100 ps
5380 12:14:43.388043 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5381 12:14:43.394237 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5382 12:14:43.398644 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5383 12:14:43.401636 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5384 12:14:43.404991 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5385 12:14:43.408151 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5386 12:14:43.408754
5387 12:14:43.411362 CA PerBit enable=1, Macro0, CA PI delay=33
5388 12:14:43.411821
5389 12:14:43.414394 [CBTSetCACLKResult] CA Dly = 33
5390 12:14:43.414950 CS Dly: 5 (0~37)
5391 12:14:43.415455
5392 12:14:43.417911 ----->DramcWriteLeveling(PI) begin...
5393 12:14:43.422443 ==
5394 12:14:43.425060 Dram Type= 6, Freq= 0, CH_1, rank 0
5395 12:14:43.428321 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5396 12:14:43.428922 ==
5397 12:14:43.431507 Write leveling (Byte 0): 25 => 25
5398 12:14:43.435171 Write leveling (Byte 1): 25 => 25
5399 12:14:43.438748 DramcWriteLeveling(PI) end<-----
5400 12:14:43.439297
5401 12:14:43.439661 ==
5402 12:14:43.440931 Dram Type= 6, Freq= 0, CH_1, rank 0
5403 12:14:43.445074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5404 12:14:43.445636 ==
5405 12:14:43.447801 [Gating] SW mode calibration
5406 12:14:43.454468 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5407 12:14:43.461166 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5408 12:14:43.465114 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5409 12:14:43.467450 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5410 12:14:43.474240 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5411 12:14:43.477443 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5412 12:14:43.481101 0 10 16 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
5413 12:14:43.488047 0 10 20 | B1->B0 | 3333 2424 | 0 0 | (0 1) (0 0)
5414 12:14:43.490685 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5415 12:14:43.494246 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 12:14:43.500856 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 12:14:43.503930 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 12:14:43.507117 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5419 12:14:43.513580 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5420 12:14:43.518750 0 11 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5421 12:14:43.519918 0 11 20 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
5422 12:14:43.526821 0 11 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5423 12:14:43.530319 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 12:14:43.533667 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 12:14:43.540311 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 12:14:43.543702 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5427 12:14:43.547273 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 12:14:43.553389 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5429 12:14:43.557220 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 12:14:43.560309 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 12:14:43.566929 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 12:14:43.570356 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 12:14:43.574192 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 12:14:43.579763 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 12:14:43.583165 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 12:14:43.586161 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 12:14:43.592942 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 12:14:43.596147 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 12:14:43.599829 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 12:14:43.606260 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 12:14:43.609871 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 12:14:43.612760 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 12:14:43.619677 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 12:14:43.623474 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5445 12:14:43.626114 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5446 12:14:43.629244 Total UI for P1: 0, mck2ui 16
5447 12:14:43.632792 best dqsien dly found for B0: ( 0, 14, 16)
5448 12:14:43.636634 Total UI for P1: 0, mck2ui 16
5449 12:14:43.639352 best dqsien dly found for B1: ( 0, 14, 18)
5450 12:14:43.642652 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5451 12:14:43.646011 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5452 12:14:43.646478
5453 12:14:43.652829 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5454 12:14:43.656645 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5455 12:14:43.657257 [Gating] SW calibration Done
5456 12:14:43.658773 ==
5457 12:14:43.662666 Dram Type= 6, Freq= 0, CH_1, rank 0
5458 12:14:43.665423 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5459 12:14:43.665888 ==
5460 12:14:43.666261 RX Vref Scan: 0
5461 12:14:43.666610
5462 12:14:43.669148 RX Vref 0 -> 0, step: 1
5463 12:14:43.669709
5464 12:14:43.672822 RX Delay -80 -> 252, step: 8
5465 12:14:43.675784 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5466 12:14:43.678510 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5467 12:14:43.682761 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5468 12:14:43.689182 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5469 12:14:43.692922 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5470 12:14:43.695569 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5471 12:14:43.698784 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5472 12:14:43.702553 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5473 12:14:43.705444 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5474 12:14:43.712090 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5475 12:14:43.715722 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5476 12:14:43.718502 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5477 12:14:43.722242 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5478 12:14:43.725324 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5479 12:14:43.732158 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5480 12:14:43.735273 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5481 12:14:43.735893 ==
5482 12:14:43.738605 Dram Type= 6, Freq= 0, CH_1, rank 0
5483 12:14:43.741651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5484 12:14:43.742115 ==
5485 12:14:43.742479 DQS Delay:
5486 12:14:43.744826 DQS0 = 0, DQS1 = 0
5487 12:14:43.745289 DQM Delay:
5488 12:14:43.748573 DQM0 = 95, DQM1 = 88
5489 12:14:43.749169 DQ Delay:
5490 12:14:43.751847 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5491 12:14:43.755281 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =95
5492 12:14:43.758980 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5493 12:14:43.762062 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5494 12:14:43.762631
5495 12:14:43.763007
5496 12:14:43.763356 ==
5497 12:14:43.764756 Dram Type= 6, Freq= 0, CH_1, rank 0
5498 12:14:43.771654 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5499 12:14:43.772219 ==
5500 12:14:43.772591
5501 12:14:43.773001
5502 12:14:43.773338 TX Vref Scan disable
5503 12:14:43.774845 == TX Byte 0 ==
5504 12:14:43.778906 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5505 12:14:43.784919 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5506 12:14:43.785455 == TX Byte 1 ==
5507 12:14:43.788350 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5508 12:14:43.795593 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5509 12:14:43.796156 ==
5510 12:14:43.798017 Dram Type= 6, Freq= 0, CH_1, rank 0
5511 12:14:43.801432 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5512 12:14:43.801991 ==
5513 12:14:43.802361
5514 12:14:43.802702
5515 12:14:43.804784 TX Vref Scan disable
5516 12:14:43.805245 == TX Byte 0 ==
5517 12:14:43.811851 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5518 12:14:43.815281 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5519 12:14:43.815745 == TX Byte 1 ==
5520 12:14:43.821235 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5521 12:14:43.824443 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5522 12:14:43.825077
5523 12:14:43.825452 [DATLAT]
5524 12:14:43.828752 Freq=933, CH1 RK0
5525 12:14:43.829317
5526 12:14:43.829689 DATLAT Default: 0xd
5527 12:14:43.830813 0, 0xFFFF, sum = 0
5528 12:14:43.831280 1, 0xFFFF, sum = 0
5529 12:14:43.835830 2, 0xFFFF, sum = 0
5530 12:14:43.836392 3, 0xFFFF, sum = 0
5531 12:14:43.837617 4, 0xFFFF, sum = 0
5532 12:14:43.842127 5, 0xFFFF, sum = 0
5533 12:14:43.842688 6, 0xFFFF, sum = 0
5534 12:14:43.844443 7, 0xFFFF, sum = 0
5535 12:14:43.844979 8, 0xFFFF, sum = 0
5536 12:14:43.847635 9, 0xFFFF, sum = 0
5537 12:14:43.848198 10, 0x0, sum = 1
5538 12:14:43.850747 11, 0x0, sum = 2
5539 12:14:43.851214 12, 0x0, sum = 3
5540 12:14:43.854407 13, 0x0, sum = 4
5541 12:14:43.854879 best_step = 11
5542 12:14:43.855247
5543 12:14:43.855591 ==
5544 12:14:43.857210 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 12:14:43.860860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5546 12:14:43.861329 ==
5547 12:14:43.865074 RX Vref Scan: 1
5548 12:14:43.865589
5549 12:14:43.867466 RX Vref 0 -> 0, step: 1
5550 12:14:43.867928
5551 12:14:43.868293 RX Delay -69 -> 252, step: 4
5552 12:14:43.868775
5553 12:14:43.870354 Set Vref, RX VrefLevel [Byte0]: 52
5554 12:14:43.874175 [Byte1]: 49
5555 12:14:43.878878
5556 12:14:43.879445 Final RX Vref Byte 0 = 52 to rank0
5557 12:14:43.882070 Final RX Vref Byte 1 = 49 to rank0
5558 12:14:43.885330 Final RX Vref Byte 0 = 52 to rank1
5559 12:14:43.888872 Final RX Vref Byte 1 = 49 to rank1==
5560 12:14:43.892779 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 12:14:43.899394 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5562 12:14:43.899955 ==
5563 12:14:43.900324 DQS Delay:
5564 12:14:43.902540 DQS0 = 0, DQS1 = 0
5565 12:14:43.903096 DQM Delay:
5566 12:14:43.903493 DQM0 = 94, DQM1 = 88
5567 12:14:43.905742 DQ Delay:
5568 12:14:43.908546 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =90
5569 12:14:43.912405 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5570 12:14:43.915105 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =82
5571 12:14:43.918504 DQ12 =94, DQ13 =100, DQ14 =96, DQ15 =98
5572 12:14:43.918973
5573 12:14:43.919340
5574 12:14:43.925977 [DQSOSCAuto] RK0, (LSB)MR18= 0x3636, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5575 12:14:43.928835 CH1 RK0: MR19=505, MR18=3636
5576 12:14:43.935182 CH1_RK0: MR19=0x505, MR18=0x3636, DQSOSC=404, MR23=63, INC=66, DEC=44
5577 12:14:43.935746
5578 12:14:43.938365 ----->DramcWriteLeveling(PI) begin...
5579 12:14:43.938930 ==
5580 12:14:43.942056 Dram Type= 6, Freq= 0, CH_1, rank 1
5581 12:14:43.944817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5582 12:14:43.945380 ==
5583 12:14:43.949049 Write leveling (Byte 0): 24 => 24
5584 12:14:43.952060 Write leveling (Byte 1): 24 => 24
5585 12:14:43.955011 DramcWriteLeveling(PI) end<-----
5586 12:14:43.955476
5587 12:14:43.955842 ==
5588 12:14:43.958283 Dram Type= 6, Freq= 0, CH_1, rank 1
5589 12:14:43.961579 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5590 12:14:43.964553 ==
5591 12:14:43.965052 [Gating] SW mode calibration
5592 12:14:43.971420 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5593 12:14:43.978114 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5594 12:14:43.981721 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 12:14:43.988473 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 12:14:43.992155 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 12:14:43.995100 0 10 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5598 12:14:44.001372 0 10 16 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
5599 12:14:44.004509 0 10 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5600 12:14:44.007902 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 12:14:44.014567 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 12:14:44.018193 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 12:14:44.021583 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 12:14:44.027903 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 12:14:44.031768 0 11 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5606 12:14:44.034550 0 11 16 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)
5607 12:14:44.041637 0 11 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5608 12:14:44.044751 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 12:14:44.048939 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 12:14:44.052838 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 12:14:44.058610 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 12:14:44.061616 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 12:14:44.065331 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 12:14:44.071775 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 12:14:44.074298 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 12:14:44.077489 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 12:14:44.084203 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 12:14:44.088242 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 12:14:44.091244 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 12:14:44.097689 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 12:14:44.101250 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 12:14:44.104048 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 12:14:44.110316 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 12:14:44.113953 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 12:14:44.117342 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 12:14:44.123514 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 12:14:44.127617 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 12:14:44.130750 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 12:14:44.137261 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 12:14:44.140205 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5631 12:14:44.143414 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5632 12:14:44.147888 Total UI for P1: 0, mck2ui 16
5633 12:14:44.150057 best dqsien dly found for B0: ( 0, 14, 16)
5634 12:14:44.157239 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 12:14:44.160281 Total UI for P1: 0, mck2ui 16
5636 12:14:44.164889 best dqsien dly found for B1: ( 0, 14, 18)
5637 12:14:44.168255 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5638 12:14:44.169854 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5639 12:14:44.170315
5640 12:14:44.173772 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5641 12:14:44.176820 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5642 12:14:44.180467 [Gating] SW calibration Done
5643 12:14:44.181020 ==
5644 12:14:44.183416 Dram Type= 6, Freq= 0, CH_1, rank 1
5645 12:14:44.186167 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5646 12:14:44.190257 ==
5647 12:14:44.190823 RX Vref Scan: 0
5648 12:14:44.191192
5649 12:14:44.193049 RX Vref 0 -> 0, step: 1
5650 12:14:44.193552
5651 12:14:44.193919 RX Delay -80 -> 252, step: 8
5652 12:14:44.200223 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5653 12:14:44.203983 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5654 12:14:44.206895 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5655 12:14:44.209468 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5656 12:14:44.212899 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5657 12:14:44.219450 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5658 12:14:44.223142 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5659 12:14:44.226772 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5660 12:14:44.229535 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5661 12:14:44.233448 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5662 12:14:44.239550 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5663 12:14:44.243080 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5664 12:14:44.247131 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5665 12:14:44.249404 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5666 12:14:44.253088 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5667 12:14:44.260369 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5668 12:14:44.260977 ==
5669 12:14:44.262664 Dram Type= 6, Freq= 0, CH_1, rank 1
5670 12:14:44.265779 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5671 12:14:44.266361 ==
5672 12:14:44.266736 DQS Delay:
5673 12:14:44.269295 DQS0 = 0, DQS1 = 0
5674 12:14:44.269876 DQM Delay:
5675 12:14:44.272449 DQM0 = 97, DQM1 = 86
5676 12:14:44.273066 DQ Delay:
5677 12:14:44.275884 DQ0 =103, DQ1 =87, DQ2 =87, DQ3 =91
5678 12:14:44.279504 DQ4 =99, DQ5 =111, DQ6 =107, DQ7 =91
5679 12:14:44.282575 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =75
5680 12:14:44.285944 DQ12 =91, DQ13 =99, DQ14 =91, DQ15 =99
5681 12:14:44.286408
5682 12:14:44.286776
5683 12:14:44.287119 ==
5684 12:14:44.289399 Dram Type= 6, Freq= 0, CH_1, rank 1
5685 12:14:44.294032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5686 12:14:44.294591 ==
5687 12:14:44.294964
5688 12:14:44.296373
5689 12:14:44.296884 TX Vref Scan disable
5690 12:14:44.298954 == TX Byte 0 ==
5691 12:14:44.302538 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5692 12:14:44.305666 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5693 12:14:44.309668 == TX Byte 1 ==
5694 12:14:44.311833 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5695 12:14:44.315819 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5696 12:14:44.316306 ==
5697 12:14:44.318480 Dram Type= 6, Freq= 0, CH_1, rank 1
5698 12:14:44.325396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5699 12:14:44.325865 ==
5700 12:14:44.326236
5701 12:14:44.326577
5702 12:14:44.326903 TX Vref Scan disable
5703 12:14:44.329948 == TX Byte 0 ==
5704 12:14:44.333572 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5705 12:14:44.339360 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5706 12:14:44.339827 == TX Byte 1 ==
5707 12:14:44.342863 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5708 12:14:44.349613 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5709 12:14:44.350298
5710 12:14:44.350684 [DATLAT]
5711 12:14:44.351030 Freq=933, CH1 RK1
5712 12:14:44.351368
5713 12:14:44.352819 DATLAT Default: 0xb
5714 12:14:44.353283 0, 0xFFFF, sum = 0
5715 12:14:44.356915 1, 0xFFFF, sum = 0
5716 12:14:44.357388 2, 0xFFFF, sum = 0
5717 12:14:44.359851 3, 0xFFFF, sum = 0
5718 12:14:44.362555 4, 0xFFFF, sum = 0
5719 12:14:44.363030 5, 0xFFFF, sum = 0
5720 12:14:44.366094 6, 0xFFFF, sum = 0
5721 12:14:44.366565 7, 0xFFFF, sum = 0
5722 12:14:44.370703 8, 0xFFFF, sum = 0
5723 12:14:44.371227 9, 0xFFFF, sum = 0
5724 12:14:44.372925 10, 0x0, sum = 1
5725 12:14:44.373397 11, 0x0, sum = 2
5726 12:14:44.377337 12, 0x0, sum = 3
5727 12:14:44.377911 13, 0x0, sum = 4
5728 12:14:44.378287 best_step = 11
5729 12:14:44.378629
5730 12:14:44.379626 ==
5731 12:14:44.382638 Dram Type= 6, Freq= 0, CH_1, rank 1
5732 12:14:44.386088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5733 12:14:44.386650 ==
5734 12:14:44.387177 RX Vref Scan: 0
5735 12:14:44.387540
5736 12:14:44.390158 RX Vref 0 -> 0, step: 1
5737 12:14:44.390622
5738 12:14:44.392658 RX Delay -69 -> 252, step: 4
5739 12:14:44.399153 iDelay=203, Bit 0, Center 96 (7 ~ 186) 180
5740 12:14:44.402499 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5741 12:14:44.406186 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5742 12:14:44.409322 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5743 12:14:44.412672 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5744 12:14:44.416817 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5745 12:14:44.422942 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5746 12:14:44.426406 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5747 12:14:44.429045 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5748 12:14:44.432467 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5749 12:14:44.436451 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5750 12:14:44.442324 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5751 12:14:44.445390 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5752 12:14:44.449329 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5753 12:14:44.452154 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5754 12:14:44.455268 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5755 12:14:44.455728 ==
5756 12:14:44.459033 Dram Type= 6, Freq= 0, CH_1, rank 1
5757 12:14:44.462355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5758 12:14:44.465516 ==
5759 12:14:44.466007 DQS Delay:
5760 12:14:44.466390 DQS0 = 0, DQS1 = 0
5761 12:14:44.469877 DQM Delay:
5762 12:14:44.470456 DQM0 = 95, DQM1 = 87
5763 12:14:44.472303 DQ Delay:
5764 12:14:44.475432 DQ0 =96, DQ1 =90, DQ2 =88, DQ3 =92
5765 12:14:44.475884 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5766 12:14:44.480084 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =80
5767 12:14:44.485286 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5768 12:14:44.485745
5769 12:14:44.486111
5770 12:14:44.493259 [DQSOSCAuto] RK1, (LSB)MR18= 0x2727, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5771 12:14:44.496121 CH1 RK1: MR19=505, MR18=2727
5772 12:14:44.502546 CH1_RK1: MR19=0x505, MR18=0x2727, DQSOSC=409, MR23=63, INC=64, DEC=43
5773 12:14:44.505512 [RxdqsGatingPostProcess] freq 933
5774 12:14:44.509107 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5775 12:14:44.512446 Pre-setting of DQS Precalculation
5776 12:14:44.519243 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5777 12:14:44.526138 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5778 12:14:44.532673 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5779 12:14:44.533309
5780 12:14:44.533680
5781 12:14:44.536234 [Calibration Summary] 1866 Mbps
5782 12:14:44.536864 CH 0, Rank 0
5783 12:14:44.540014 SW Impedance : PASS
5784 12:14:44.541534 DUTY Scan : NO K
5785 12:14:44.541990 ZQ Calibration : PASS
5786 12:14:44.545342 Jitter Meter : NO K
5787 12:14:44.548866 CBT Training : PASS
5788 12:14:44.549414 Write leveling : PASS
5789 12:14:44.552888 RX DQS gating : PASS
5790 12:14:44.555391 RX DQ/DQS(RDDQC) : PASS
5791 12:14:44.555847 TX DQ/DQS : PASS
5792 12:14:44.558384 RX DATLAT : PASS
5793 12:14:44.561398 RX DQ/DQS(Engine): PASS
5794 12:14:44.561951 TX OE : NO K
5795 12:14:44.562315 All Pass.
5796 12:14:44.565260
5797 12:14:44.565832 CH 0, Rank 1
5798 12:14:44.568517 SW Impedance : PASS
5799 12:14:44.569078 DUTY Scan : NO K
5800 12:14:44.571626 ZQ Calibration : PASS
5801 12:14:44.572080 Jitter Meter : NO K
5802 12:14:44.574632 CBT Training : PASS
5803 12:14:44.578024 Write leveling : PASS
5804 12:14:44.578581 RX DQS gating : PASS
5805 12:14:44.581317 RX DQ/DQS(RDDQC) : PASS
5806 12:14:44.584753 TX DQ/DQS : PASS
5807 12:14:44.585228 RX DATLAT : PASS
5808 12:14:44.588092 RX DQ/DQS(Engine): PASS
5809 12:14:44.591406 TX OE : NO K
5810 12:14:44.591966 All Pass.
5811 12:14:44.592329
5812 12:14:44.592668 CH 1, Rank 0
5813 12:14:44.594330 SW Impedance : PASS
5814 12:14:44.597817 DUTY Scan : NO K
5815 12:14:44.598275 ZQ Calibration : PASS
5816 12:14:44.601614 Jitter Meter : NO K
5817 12:14:44.605331 CBT Training : PASS
5818 12:14:44.605886 Write leveling : PASS
5819 12:14:44.607605 RX DQS gating : PASS
5820 12:14:44.611690 RX DQ/DQS(RDDQC) : PASS
5821 12:14:44.612247 TX DQ/DQS : PASS
5822 12:14:44.614877 RX DATLAT : PASS
5823 12:14:44.618177 RX DQ/DQS(Engine): PASS
5824 12:14:44.618736 TX OE : NO K
5825 12:14:44.622314 All Pass.
5826 12:14:44.622869
5827 12:14:44.623283 CH 1, Rank 1
5828 12:14:44.625376 SW Impedance : PASS
5829 12:14:44.625834 DUTY Scan : NO K
5830 12:14:44.627889 ZQ Calibration : PASS
5831 12:14:44.631666 Jitter Meter : NO K
5832 12:14:44.632238 CBT Training : PASS
5833 12:14:44.634414 Write leveling : PASS
5834 12:14:44.638178 RX DQS gating : PASS
5835 12:14:44.638733 RX DQ/DQS(RDDQC) : PASS
5836 12:14:44.641234 TX DQ/DQS : PASS
5837 12:14:44.641692 RX DATLAT : PASS
5838 12:14:44.645062 RX DQ/DQS(Engine): PASS
5839 12:14:44.647875 TX OE : NO K
5840 12:14:44.648427 All Pass.
5841 12:14:44.648885
5842 12:14:44.651910 DramC Write-DBI off
5843 12:14:44.652466 PER_BANK_REFRESH: Hybrid Mode
5844 12:14:44.654214 TX_TRACKING: ON
5845 12:14:44.665184 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5846 12:14:44.667470 [FAST_K] Save calibration result to emmc
5847 12:14:44.671039 dramc_set_vcore_voltage set vcore to 650000
5848 12:14:44.671541 Read voltage for 400, 6
5849 12:14:44.675454 Vio18 = 0
5850 12:14:44.676036 Vcore = 650000
5851 12:14:44.676406 Vdram = 0
5852 12:14:44.677385 Vddq = 0
5853 12:14:44.677840 Vmddr = 0
5854 12:14:44.684084 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5855 12:14:44.686963 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5856 12:14:44.690723 MEM_TYPE=3, freq_sel=20
5857 12:14:44.693525 sv_algorithm_assistance_LP4_800
5858 12:14:44.697479 ============ PULL DRAM RESETB DOWN ============
5859 12:14:44.700924 ========== PULL DRAM RESETB DOWN end =========
5860 12:14:44.708127 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5861 12:14:44.710776 ===================================
5862 12:14:44.711338 LPDDR4 DRAM CONFIGURATION
5863 12:14:44.713911 ===================================
5864 12:14:44.717055 EX_ROW_EN[0] = 0x0
5865 12:14:44.720660 EX_ROW_EN[1] = 0x0
5866 12:14:44.721264 LP4Y_EN = 0x0
5867 12:14:44.724999 WORK_FSP = 0x0
5868 12:14:44.725556 WL = 0x2
5869 12:14:44.727646 RL = 0x2
5870 12:14:44.728098 BL = 0x2
5871 12:14:44.730707 RPST = 0x0
5872 12:14:44.731255 RD_PRE = 0x0
5873 12:14:44.733574 WR_PRE = 0x1
5874 12:14:44.734188 WR_PST = 0x0
5875 12:14:44.737477 DBI_WR = 0x0
5876 12:14:44.738036 DBI_RD = 0x0
5877 12:14:44.740242 OTF = 0x1
5878 12:14:44.743766 ===================================
5879 12:14:44.747055 ===================================
5880 12:14:44.747603 ANA top config
5881 12:14:44.750399 ===================================
5882 12:14:44.753631 DLL_ASYNC_EN = 0
5883 12:14:44.756907 ALL_SLAVE_EN = 1
5884 12:14:44.757366 NEW_RANK_MODE = 1
5885 12:14:44.760606 DLL_IDLE_MODE = 1
5886 12:14:44.764637 LP45_APHY_COMB_EN = 1
5887 12:14:44.767531 TX_ODT_DIS = 1
5888 12:14:44.770902 NEW_8X_MODE = 1
5889 12:14:44.773652 ===================================
5890 12:14:44.777336 ===================================
5891 12:14:44.777906 data_rate = 800
5892 12:14:44.780813 CKR = 1
5893 12:14:44.783764 DQ_P2S_RATIO = 4
5894 12:14:44.786660 ===================================
5895 12:14:44.789834 CA_P2S_RATIO = 4
5896 12:14:44.793651 DQ_CA_OPEN = 0
5897 12:14:44.796422 DQ_SEMI_OPEN = 1
5898 12:14:44.797077 CA_SEMI_OPEN = 1
5899 12:14:44.800043 CA_FULL_RATE = 0
5900 12:14:44.803684 DQ_CKDIV4_EN = 0
5901 12:14:44.806393 CA_CKDIV4_EN = 1
5902 12:14:44.810611 CA_PREDIV_EN = 0
5903 12:14:44.813227 PH8_DLY = 0
5904 12:14:44.813720 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5905 12:14:44.816654 DQ_AAMCK_DIV = 0
5906 12:14:44.820294 CA_AAMCK_DIV = 0
5907 12:14:44.823817 CA_ADMCK_DIV = 4
5908 12:14:44.827102 DQ_TRACK_CA_EN = 0
5909 12:14:44.830143 CA_PICK = 800
5910 12:14:44.833685 CA_MCKIO = 400
5911 12:14:44.834238 MCKIO_SEMI = 400
5912 12:14:44.837105 PLL_FREQ = 3016
5913 12:14:44.840282 DQ_UI_PI_RATIO = 32
5914 12:14:44.843195 CA_UI_PI_RATIO = 32
5915 12:14:44.846492 ===================================
5916 12:14:44.849759 ===================================
5917 12:14:44.853933 memory_type:LPDDR4
5918 12:14:44.854477 GP_NUM : 10
5919 12:14:44.856360 SRAM_EN : 1
5920 12:14:44.860099 MD32_EN : 0
5921 12:14:44.864128 ===================================
5922 12:14:44.864585 [ANA_INIT] >>>>>>>>>>>>>>
5923 12:14:44.867106 <<<<<< [CONFIGURE PHASE]: ANA_TX
5924 12:14:44.870220 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5925 12:14:44.873703 ===================================
5926 12:14:44.877303 data_rate = 800,PCW = 0X7400
5927 12:14:44.879717 ===================================
5928 12:14:44.883143 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5929 12:14:44.889430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5930 12:14:44.899753 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5931 12:14:44.903017 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5932 12:14:44.909342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5933 12:14:44.913201 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5934 12:14:44.913780 [ANA_INIT] flow start
5935 12:14:44.916025 [ANA_INIT] PLL >>>>>>>>
5936 12:14:44.919960 [ANA_INIT] PLL <<<<<<<<
5937 12:14:44.920526 [ANA_INIT] MIDPI >>>>>>>>
5938 12:14:44.923186 [ANA_INIT] MIDPI <<<<<<<<
5939 12:14:44.926380 [ANA_INIT] DLL >>>>>>>>
5940 12:14:44.926933 [ANA_INIT] flow end
5941 12:14:44.929660 ============ LP4 DIFF to SE enter ============
5942 12:14:44.936960 ============ LP4 DIFF to SE exit ============
5943 12:14:44.937515 [ANA_INIT] <<<<<<<<<<<<<
5944 12:14:44.938996 [Flow] Enable top DCM control >>>>>
5945 12:14:44.942977 [Flow] Enable top DCM control <<<<<
5946 12:14:44.946126 Enable DLL master slave shuffle
5947 12:14:44.953683 ==============================================================
5948 12:14:44.956010 Gating Mode config
5949 12:14:44.958826 ==============================================================
5950 12:14:44.962684 Config description:
5951 12:14:44.972270 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5952 12:14:44.978967 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5953 12:14:44.982141 SELPH_MODE 0: By rank 1: By Phase
5954 12:14:44.988787 ==============================================================
5955 12:14:44.992436 GAT_TRACK_EN = 0
5956 12:14:44.995165 RX_GATING_MODE = 2
5957 12:14:44.998895 RX_GATING_TRACK_MODE = 2
5958 12:14:45.002166 SELPH_MODE = 1
5959 12:14:45.002719 PICG_EARLY_EN = 1
5960 12:14:45.005439 VALID_LAT_VALUE = 1
5961 12:14:45.012271 ==============================================================
5962 12:14:45.015113 Enter into Gating configuration >>>>
5963 12:14:45.018262 Exit from Gating configuration <<<<
5964 12:14:45.022074 Enter into DVFS_PRE_config >>>>>
5965 12:14:45.032440 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5966 12:14:45.034899 Exit from DVFS_PRE_config <<<<<
5967 12:14:45.039116 Enter into PICG configuration >>>>
5968 12:14:45.041283 Exit from PICG configuration <<<<
5969 12:14:45.044932 [RX_INPUT] configuration >>>>>
5970 12:14:45.048080 [RX_INPUT] configuration <<<<<
5971 12:14:45.051609 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5972 12:14:45.057907 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5973 12:14:45.064676 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5974 12:14:45.071751 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5975 12:14:45.078329 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5976 12:14:45.084779 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5977 12:14:45.087514 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5978 12:14:45.091149 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5979 12:14:45.094523 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5980 12:14:45.101213 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5981 12:14:45.104983 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5982 12:14:45.107387 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5983 12:14:45.111737 ===================================
5984 12:14:45.114640 LPDDR4 DRAM CONFIGURATION
5985 12:14:45.117648 ===================================
5986 12:14:45.118311 EX_ROW_EN[0] = 0x0
5987 12:14:45.120544 EX_ROW_EN[1] = 0x0
5988 12:14:45.121047 LP4Y_EN = 0x0
5989 12:14:45.124323 WORK_FSP = 0x0
5990 12:14:45.127502 WL = 0x2
5991 12:14:45.128048 RL = 0x2
5992 12:14:45.131058 BL = 0x2
5993 12:14:45.131618 RPST = 0x0
5994 12:14:45.134491 RD_PRE = 0x0
5995 12:14:45.135042 WR_PRE = 0x1
5996 12:14:45.137138 WR_PST = 0x0
5997 12:14:45.137593 DBI_WR = 0x0
5998 12:14:45.141013 DBI_RD = 0x0
5999 12:14:45.141570 OTF = 0x1
6000 12:14:45.144379 ===================================
6001 12:14:45.147814 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6002 12:14:45.154707 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6003 12:14:45.157866 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6004 12:14:45.161064 ===================================
6005 12:14:45.164637 LPDDR4 DRAM CONFIGURATION
6006 12:14:45.168331 ===================================
6007 12:14:45.168940 EX_ROW_EN[0] = 0x10
6008 12:14:45.171107 EX_ROW_EN[1] = 0x0
6009 12:14:45.171559 LP4Y_EN = 0x0
6010 12:14:45.173994 WORK_FSP = 0x0
6011 12:14:45.174447 WL = 0x2
6012 12:14:45.177032 RL = 0x2
6013 12:14:45.181269 BL = 0x2
6014 12:14:45.181820 RPST = 0x0
6015 12:14:45.183742 RD_PRE = 0x0
6016 12:14:45.184298 WR_PRE = 0x1
6017 12:14:45.186843 WR_PST = 0x0
6018 12:14:45.187299 DBI_WR = 0x0
6019 12:14:45.190519 DBI_RD = 0x0
6020 12:14:45.191075 OTF = 0x1
6021 12:14:45.193515 ===================================
6022 12:14:45.200372 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6023 12:14:45.204404 nWR fixed to 30
6024 12:14:45.209936 [ModeRegInit_LP4] CH0 RK0
6025 12:14:45.210392 [ModeRegInit_LP4] CH0 RK1
6026 12:14:45.211783 [ModeRegInit_LP4] CH1 RK0
6027 12:14:45.214503 [ModeRegInit_LP4] CH1 RK1
6028 12:14:45.214959 match AC timing 18
6029 12:14:45.220471 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6030 12:14:45.224078 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6031 12:14:45.228047 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6032 12:14:45.233917 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6033 12:14:45.237643 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6034 12:14:45.238197 ==
6035 12:14:45.240411 Dram Type= 6, Freq= 0, CH_0, rank 0
6036 12:14:45.243940 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6037 12:14:45.244493 ==
6038 12:14:45.250798 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6039 12:14:45.257274 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6040 12:14:45.260517 [CA 0] Center 36 (8~64) winsize 57
6041 12:14:45.263645 [CA 1] Center 36 (8~64) winsize 57
6042 12:14:45.266940 [CA 2] Center 36 (8~64) winsize 57
6043 12:14:45.270644 [CA 3] Center 36 (8~64) winsize 57
6044 12:14:45.271194 [CA 4] Center 36 (8~64) winsize 57
6045 12:14:45.273974 [CA 5] Center 36 (8~64) winsize 57
6046 12:14:45.274432
6047 12:14:45.280069 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6048 12:14:45.280607
6049 12:14:45.283723 [CATrainingPosCal] consider 1 rank data
6050 12:14:45.286914 u2DelayCellTimex100 = 270/100 ps
6051 12:14:45.290296 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6052 12:14:45.293398 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6053 12:14:45.297068 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6054 12:14:45.300394 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6055 12:14:45.303905 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6056 12:14:45.307319 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6057 12:14:45.307799
6058 12:14:45.310369 CA PerBit enable=1, Macro0, CA PI delay=36
6059 12:14:45.310952
6060 12:14:45.313404 [CBTSetCACLKResult] CA Dly = 36
6061 12:14:45.317083 CS Dly: 1 (0~32)
6062 12:14:45.317655 ==
6063 12:14:45.320426 Dram Type= 6, Freq= 0, CH_0, rank 1
6064 12:14:45.323876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6065 12:14:45.324482 ==
6066 12:14:45.330077 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6067 12:14:45.336779 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6068 12:14:45.337370 [CA 0] Center 36 (8~64) winsize 57
6069 12:14:45.340490 [CA 1] Center 36 (8~64) winsize 57
6070 12:14:45.345171 [CA 2] Center 36 (8~64) winsize 57
6071 12:14:45.347853 [CA 3] Center 36 (8~64) winsize 57
6072 12:14:45.350414 [CA 4] Center 36 (8~64) winsize 57
6073 12:14:45.353265 [CA 5] Center 36 (8~64) winsize 57
6074 12:14:45.353742
6075 12:14:45.357871 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6076 12:14:45.358348
6077 12:14:45.359554 [CATrainingPosCal] consider 2 rank data
6078 12:14:45.363351 u2DelayCellTimex100 = 270/100 ps
6079 12:14:45.366257 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6080 12:14:45.373651 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6081 12:14:45.376559 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6082 12:14:45.379726 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6083 12:14:45.383250 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6084 12:14:45.386771 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6085 12:14:45.387671
6086 12:14:45.389392 CA PerBit enable=1, Macro0, CA PI delay=36
6087 12:14:45.389854
6088 12:14:45.393367 [CBTSetCACLKResult] CA Dly = 36
6089 12:14:45.396617 CS Dly: 1 (0~32)
6090 12:14:45.397124
6091 12:14:45.399437 ----->DramcWriteLeveling(PI) begin...
6092 12:14:45.399903 ==
6093 12:14:45.403344 Dram Type= 6, Freq= 0, CH_0, rank 0
6094 12:14:45.406760 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6095 12:14:45.407241 ==
6096 12:14:45.409329 Write leveling (Byte 0): 32 => 0
6097 12:14:45.413189 Write leveling (Byte 1): 32 => 0
6098 12:14:45.415752 DramcWriteLeveling(PI) end<-----
6099 12:14:45.416254
6100 12:14:45.416888 ==
6101 12:14:45.419521 Dram Type= 6, Freq= 0, CH_0, rank 0
6102 12:14:45.422818 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6103 12:14:45.423385 ==
6104 12:14:45.425942 [Gating] SW mode calibration
6105 12:14:45.432555 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6106 12:14:45.439582 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6107 12:14:45.442320 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6108 12:14:45.445837 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6109 12:14:45.452363 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6110 12:14:45.456175 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6111 12:14:45.458747 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6112 12:14:45.465637 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6113 12:14:45.468643 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6114 12:14:45.472576 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6115 12:14:45.479228 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6116 12:14:45.479788 Total UI for P1: 0, mck2ui 16
6117 12:14:45.486054 best dqsien dly found for B0: ( 0, 10, 16)
6118 12:14:45.486616 Total UI for P1: 0, mck2ui 16
6119 12:14:45.488466 best dqsien dly found for B1: ( 0, 10, 24)
6120 12:14:45.495583 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6121 12:14:45.498690 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6122 12:14:45.499152
6123 12:14:45.501799 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6124 12:14:45.505590 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6125 12:14:45.509146 [Gating] SW calibration Done
6126 12:14:45.509698 ==
6127 12:14:45.511733 Dram Type= 6, Freq= 0, CH_0, rank 0
6128 12:14:45.515577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6129 12:14:45.516043 ==
6130 12:14:45.519018 RX Vref Scan: 0
6131 12:14:45.519571
6132 12:14:45.519940 RX Vref 0 -> 0, step: 1
6133 12:14:45.520285
6134 12:14:45.521503 RX Delay -410 -> 252, step: 16
6135 12:14:45.528538 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6136 12:14:45.531512 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6137 12:14:45.535394 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6138 12:14:45.538781 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6139 12:14:45.545489 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6140 12:14:45.548477 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6141 12:14:45.551597 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6142 12:14:45.555450 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6143 12:14:45.561540 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6144 12:14:45.565047 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6145 12:14:45.568790 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6146 12:14:45.571821 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6147 12:14:45.578255 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6148 12:14:45.581526 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6149 12:14:45.585651 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6150 12:14:45.592181 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6151 12:14:45.592783 ==
6152 12:14:45.594811 Dram Type= 6, Freq= 0, CH_0, rank 0
6153 12:14:45.597997 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6154 12:14:45.598457 ==
6155 12:14:45.598825 DQS Delay:
6156 12:14:45.601261 DQS0 = 51, DQS1 = 59
6157 12:14:45.601720 DQM Delay:
6158 12:14:45.604460 DQM0 = 12, DQM1 = 13
6159 12:14:45.605064 DQ Delay:
6160 12:14:45.607937 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6161 12:14:45.611186 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6162 12:14:45.614387 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6163 12:14:45.618165 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6164 12:14:45.618724
6165 12:14:45.619090
6166 12:14:45.619432 ==
6167 12:14:45.620842 Dram Type= 6, Freq= 0, CH_0, rank 0
6168 12:14:45.624571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6169 12:14:45.625183 ==
6170 12:14:45.625556
6171 12:14:45.625898
6172 12:14:45.627980 TX Vref Scan disable
6173 12:14:45.628438 == TX Byte 0 ==
6174 12:14:45.634496 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6175 12:14:45.638812 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6176 12:14:45.639371 == TX Byte 1 ==
6177 12:14:45.644125 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6178 12:14:45.647398 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6179 12:14:45.647903 ==
6180 12:14:45.650961 Dram Type= 6, Freq= 0, CH_0, rank 0
6181 12:14:45.654065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6182 12:14:45.654806 ==
6183 12:14:45.655296
6184 12:14:45.657789
6185 12:14:45.658262 TX Vref Scan disable
6186 12:14:45.661185 == TX Byte 0 ==
6187 12:14:45.664578 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6188 12:14:45.667513 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6189 12:14:45.670995 == TX Byte 1 ==
6190 12:14:45.674506 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6191 12:14:45.677562 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6192 12:14:45.678024
6193 12:14:45.680798 [DATLAT]
6194 12:14:45.681349 Freq=400, CH0 RK0
6195 12:14:45.681723
6196 12:14:45.684222 DATLAT Default: 0xf
6197 12:14:45.684819 0, 0xFFFF, sum = 0
6198 12:14:45.687688 1, 0xFFFF, sum = 0
6199 12:14:45.688241 2, 0xFFFF, sum = 0
6200 12:14:45.690762 3, 0xFFFF, sum = 0
6201 12:14:45.691317 4, 0xFFFF, sum = 0
6202 12:14:45.694687 5, 0xFFFF, sum = 0
6203 12:14:45.695154 6, 0xFFFF, sum = 0
6204 12:14:45.698345 7, 0xFFFF, sum = 0
6205 12:14:45.698808 8, 0xFFFF, sum = 0
6206 12:14:45.700302 9, 0xFFFF, sum = 0
6207 12:14:45.700815 10, 0xFFFF, sum = 0
6208 12:14:45.703745 11, 0xFFFF, sum = 0
6209 12:14:45.704302 12, 0x0, sum = 1
6210 12:14:45.707659 13, 0x0, sum = 2
6211 12:14:45.708225 14, 0x0, sum = 3
6212 12:14:45.710168 15, 0x0, sum = 4
6213 12:14:45.710631 best_step = 13
6214 12:14:45.710994
6215 12:14:45.711334 ==
6216 12:14:45.713705 Dram Type= 6, Freq= 0, CH_0, rank 0
6217 12:14:45.720543 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6218 12:14:45.721143 ==
6219 12:14:45.721518 RX Vref Scan: 1
6220 12:14:45.721930
6221 12:14:45.724585 RX Vref 0 -> 0, step: 1
6222 12:14:45.725191
6223 12:14:45.727131 RX Delay -359 -> 252, step: 8
6224 12:14:45.727592
6225 12:14:45.730779 Set Vref, RX VrefLevel [Byte0]: 46
6226 12:14:45.734449 [Byte1]: 50
6227 12:14:45.735004
6228 12:14:45.737423 Final RX Vref Byte 0 = 46 to rank0
6229 12:14:45.740519 Final RX Vref Byte 1 = 50 to rank0
6230 12:14:45.743738 Final RX Vref Byte 0 = 46 to rank1
6231 12:14:45.746863 Final RX Vref Byte 1 = 50 to rank1==
6232 12:14:45.750287 Dram Type= 6, Freq= 0, CH_0, rank 0
6233 12:14:45.754045 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6234 12:14:45.757021 ==
6235 12:14:45.757566 DQS Delay:
6236 12:14:45.757973 DQS0 = 52, DQS1 = 68
6237 12:14:45.760587 DQM Delay:
6238 12:14:45.761072 DQM0 = 8, DQM1 = 16
6239 12:14:45.763809 DQ Delay:
6240 12:14:45.764266 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6241 12:14:45.766345 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6242 12:14:45.770506 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6243 12:14:45.773551 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6244 12:14:45.774106
6245 12:14:45.774472
6246 12:14:45.783451 [DQSOSCAuto] RK0, (LSB)MR18= 0xa1a1, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6247 12:14:45.786804 CH0 RK0: MR19=C0C, MR18=A1A1
6248 12:14:45.792968 CH0_RK0: MR19=0xC0C, MR18=0xA1A1, DQSOSC=389, MR23=63, INC=390, DEC=260
6249 12:14:45.793447 ==
6250 12:14:45.796508 Dram Type= 6, Freq= 0, CH_0, rank 1
6251 12:14:45.799666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6252 12:14:45.800146 ==
6253 12:14:45.803003 [Gating] SW mode calibration
6254 12:14:45.810145 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6255 12:14:45.812952 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6256 12:14:45.819669 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6257 12:14:45.823050 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6258 12:14:45.826523 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6259 12:14:45.833220 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6260 12:14:45.836398 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6261 12:14:45.839645 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6262 12:14:45.846689 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6263 12:14:45.849722 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6264 12:14:45.853170 Total UI for P1: 0, mck2ui 16
6265 12:14:45.856381 best dqsien dly found for B0: ( 0, 10, 8)
6266 12:14:45.859738 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6267 12:14:45.862801 Total UI for P1: 0, mck2ui 16
6268 12:14:45.866850 best dqsien dly found for B1: ( 0, 10, 16)
6269 12:14:45.869443 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6270 12:14:45.872674 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6271 12:14:45.873282
6272 12:14:45.879987 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6273 12:14:45.882599 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6274 12:14:45.886316 [Gating] SW calibration Done
6275 12:14:45.886867 ==
6276 12:14:45.889507 Dram Type= 6, Freq= 0, CH_0, rank 1
6277 12:14:45.893268 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6278 12:14:45.893728 ==
6279 12:14:45.894093 RX Vref Scan: 0
6280 12:14:45.894430
6281 12:14:45.895501 RX Vref 0 -> 0, step: 1
6282 12:14:45.895952
6283 12:14:45.900065 RX Delay -410 -> 252, step: 16
6284 12:14:45.902302 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6285 12:14:45.909189 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6286 12:14:45.912987 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6287 12:14:45.916050 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6288 12:14:45.919149 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6289 12:14:45.926137 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6290 12:14:45.928876 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6291 12:14:45.933072 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6292 12:14:45.935833 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6293 12:14:45.942650 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6294 12:14:45.945644 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6295 12:14:45.948604 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6296 12:14:45.952163 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6297 12:14:45.958718 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6298 12:14:45.962620 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6299 12:14:45.965216 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6300 12:14:45.965673 ==
6301 12:14:45.969283 Dram Type= 6, Freq= 0, CH_0, rank 1
6302 12:14:45.976296 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6303 12:14:45.976908 ==
6304 12:14:45.977287 DQS Delay:
6305 12:14:45.978240 DQS0 = 43, DQS1 = 59
6306 12:14:45.978700 DQM Delay:
6307 12:14:45.979068 DQM0 = 7, DQM1 = 14
6308 12:14:45.981596 DQ Delay:
6309 12:14:45.985234 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6310 12:14:45.988452 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6311 12:14:45.989057 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6312 12:14:45.991703 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6313 12:14:45.994772
6314 12:14:45.995329
6315 12:14:45.995700 ==
6316 12:14:45.998216 Dram Type= 6, Freq= 0, CH_0, rank 1
6317 12:14:46.001228 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6318 12:14:46.001690 ==
6319 12:14:46.002072
6320 12:14:46.002414
6321 12:14:46.004499 TX Vref Scan disable
6322 12:14:46.005015 == TX Byte 0 ==
6323 12:14:46.008212 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6324 12:14:46.015338 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6325 12:14:46.015893 == TX Byte 1 ==
6326 12:14:46.018354 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6327 12:14:46.025485 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6328 12:14:46.026045 ==
6329 12:14:46.028428 Dram Type= 6, Freq= 0, CH_0, rank 1
6330 12:14:46.031900 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6331 12:14:46.032357 ==
6332 12:14:46.032749
6333 12:14:46.033095
6334 12:14:46.034800 TX Vref Scan disable
6335 12:14:46.035254 == TX Byte 0 ==
6336 12:14:46.039336 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6337 12:14:46.044394 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6338 12:14:46.044885 == TX Byte 1 ==
6339 12:14:46.047838 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6340 12:14:46.054398 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6341 12:14:46.054947
6342 12:14:46.055314 [DATLAT]
6343 12:14:46.057795 Freq=400, CH0 RK1
6344 12:14:46.058294
6345 12:14:46.058665 DATLAT Default: 0xd
6346 12:14:46.061064 0, 0xFFFF, sum = 0
6347 12:14:46.061611 1, 0xFFFF, sum = 0
6348 12:14:46.064626 2, 0xFFFF, sum = 0
6349 12:14:46.065226 3, 0xFFFF, sum = 0
6350 12:14:46.067676 4, 0xFFFF, sum = 0
6351 12:14:46.068239 5, 0xFFFF, sum = 0
6352 12:14:46.071224 6, 0xFFFF, sum = 0
6353 12:14:46.071782 7, 0xFFFF, sum = 0
6354 12:14:46.074231 8, 0xFFFF, sum = 0
6355 12:14:46.074692 9, 0xFFFF, sum = 0
6356 12:14:46.077231 10, 0xFFFF, sum = 0
6357 12:14:46.077694 11, 0xFFFF, sum = 0
6358 12:14:46.081020 12, 0x0, sum = 1
6359 12:14:46.081481 13, 0x0, sum = 2
6360 12:14:46.085013 14, 0x0, sum = 3
6361 12:14:46.085572 15, 0x0, sum = 4
6362 12:14:46.087572 best_step = 13
6363 12:14:46.088026
6364 12:14:46.088388 ==
6365 12:14:46.090791 Dram Type= 6, Freq= 0, CH_0, rank 1
6366 12:14:46.093916 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6367 12:14:46.094370 ==
6368 12:14:46.097652 RX Vref Scan: 0
6369 12:14:46.098102
6370 12:14:46.098461 RX Vref 0 -> 0, step: 1
6371 12:14:46.098797
6372 12:14:46.100381 RX Delay -359 -> 252, step: 8
6373 12:14:46.108965 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6374 12:14:46.111867 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6375 12:14:46.115826 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6376 12:14:46.122233 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6377 12:14:46.125165 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6378 12:14:46.129057 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6379 12:14:46.131897 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6380 12:14:46.138560 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6381 12:14:46.141394 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6382 12:14:46.145659 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6383 12:14:46.148686 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6384 12:14:46.154770 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6385 12:14:46.158082 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6386 12:14:46.161811 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6387 12:14:46.165328 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6388 12:14:46.171296 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6389 12:14:46.171863 ==
6390 12:14:46.174838 Dram Type= 6, Freq= 0, CH_0, rank 1
6391 12:14:46.178048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6392 12:14:46.178535 ==
6393 12:14:46.178940 DQS Delay:
6394 12:14:46.181273 DQS0 = 52, DQS1 = 64
6395 12:14:46.181723 DQM Delay:
6396 12:14:46.184891 DQM0 = 10, DQM1 = 14
6397 12:14:46.185342 DQ Delay:
6398 12:14:46.188640 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6399 12:14:46.192470 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6400 12:14:46.196264 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6401 12:14:46.201100 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6402 12:14:46.201875
6403 12:14:46.202278
6404 12:14:46.207837 [DQSOSCAuto] RK1, (LSB)MR18= 0xb9b9, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6405 12:14:46.208302 CH0 RK1: MR19=C0C, MR18=B9B9
6406 12:14:46.214712 CH0_RK1: MR19=0xC0C, MR18=0xB9B9, DQSOSC=386, MR23=63, INC=396, DEC=264
6407 12:14:46.218320 [RxdqsGatingPostProcess] freq 400
6408 12:14:46.224858 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6409 12:14:46.227508 Pre-setting of DQS Precalculation
6410 12:14:46.230942 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6411 12:14:46.231503 ==
6412 12:14:46.234766 Dram Type= 6, Freq= 0, CH_1, rank 0
6413 12:14:46.237944 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6414 12:14:46.240932 ==
6415 12:14:46.244746 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6416 12:14:46.251433 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6417 12:14:46.254894 [CA 0] Center 36 (8~64) winsize 57
6418 12:14:46.257257 [CA 1] Center 36 (8~64) winsize 57
6419 12:14:46.261515 [CA 2] Center 36 (8~64) winsize 57
6420 12:14:46.264265 [CA 3] Center 36 (8~64) winsize 57
6421 12:14:46.268351 [CA 4] Center 36 (8~64) winsize 57
6422 12:14:46.270569 [CA 5] Center 36 (8~64) winsize 57
6423 12:14:46.271031
6424 12:14:46.274003 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6425 12:14:46.274558
6426 12:14:46.277012 [CATrainingPosCal] consider 1 rank data
6427 12:14:46.280960 u2DelayCellTimex100 = 270/100 ps
6428 12:14:46.284090 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6429 12:14:46.287372 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6430 12:14:46.290746 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6431 12:14:46.293373 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6432 12:14:46.297053 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6433 12:14:46.300420 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6434 12:14:46.301017
6435 12:14:46.306969 CA PerBit enable=1, Macro0, CA PI delay=36
6436 12:14:46.307554
6437 12:14:46.310562 [CBTSetCACLKResult] CA Dly = 36
6438 12:14:46.311124 CS Dly: 1 (0~32)
6439 12:14:46.311494 ==
6440 12:14:46.313278 Dram Type= 6, Freq= 0, CH_1, rank 1
6441 12:14:46.316283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6442 12:14:46.316780 ==
6443 12:14:46.323762 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6444 12:14:46.329958 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6445 12:14:46.333976 [CA 0] Center 36 (8~64) winsize 57
6446 12:14:46.336923 [CA 1] Center 36 (8~64) winsize 57
6447 12:14:46.339696 [CA 2] Center 36 (8~64) winsize 57
6448 12:14:46.344851 [CA 3] Center 36 (8~64) winsize 57
6449 12:14:46.347155 [CA 4] Center 36 (8~64) winsize 57
6450 12:14:46.347711 [CA 5] Center 36 (8~64) winsize 57
6451 12:14:46.350440
6452 12:14:46.353186 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6453 12:14:46.353652
6454 12:14:46.356864 [CATrainingPosCal] consider 2 rank data
6455 12:14:46.359821 u2DelayCellTimex100 = 270/100 ps
6456 12:14:46.363633 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6457 12:14:46.366110 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6458 12:14:46.369629 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6459 12:14:46.373609 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6460 12:14:46.376067 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6461 12:14:46.380092 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6462 12:14:46.380652
6463 12:14:46.382623 CA PerBit enable=1, Macro0, CA PI delay=36
6464 12:14:46.383180
6465 12:14:46.386846 [CBTSetCACLKResult] CA Dly = 36
6466 12:14:46.389760 CS Dly: 1 (0~32)
6467 12:14:46.390327
6468 12:14:46.393411 ----->DramcWriteLeveling(PI) begin...
6469 12:14:46.394082 ==
6470 12:14:46.395744 Dram Type= 6, Freq= 0, CH_1, rank 0
6471 12:14:46.399071 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6472 12:14:46.399538 ==
6473 12:14:46.402693 Write leveling (Byte 0): 32 => 0
6474 12:14:46.406557 Write leveling (Byte 1): 32 => 0
6475 12:14:46.409094 DramcWriteLeveling(PI) end<-----
6476 12:14:46.409606
6477 12:14:46.409995 ==
6478 12:14:46.412549 Dram Type= 6, Freq= 0, CH_1, rank 0
6479 12:14:46.417384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6480 12:14:46.417855 ==
6481 12:14:46.419976 [Gating] SW mode calibration
6482 12:14:46.425770 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6483 12:14:46.432699 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6484 12:14:46.435739 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6485 12:14:46.442367 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 12:14:46.445739 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6487 12:14:46.448906 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6488 12:14:46.456045 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 12:14:46.458496 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 12:14:46.462698 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 12:14:46.469370 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6492 12:14:46.471962 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6493 12:14:46.475536 Total UI for P1: 0, mck2ui 16
6494 12:14:46.478831 best dqsien dly found for B0: ( 0, 10, 16)
6495 12:14:46.482177 Total UI for P1: 0, mck2ui 16
6496 12:14:46.485246 best dqsien dly found for B1: ( 0, 10, 16)
6497 12:14:46.488586 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6498 12:14:46.493248 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6499 12:14:46.493712
6500 12:14:46.495767 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6501 12:14:46.498456 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6502 12:14:46.502013 [Gating] SW calibration Done
6503 12:14:46.502473 ==
6504 12:14:46.504901 Dram Type= 6, Freq= 0, CH_1, rank 0
6505 12:14:46.508542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6506 12:14:46.511703 ==
6507 12:14:46.512253 RX Vref Scan: 0
6508 12:14:46.512623
6509 12:14:46.514768 RX Vref 0 -> 0, step: 1
6510 12:14:46.515226
6511 12:14:46.518803 RX Delay -410 -> 252, step: 16
6512 12:14:46.522763 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6513 12:14:46.524932 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6514 12:14:46.529937 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6515 12:14:46.534655 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6516 12:14:46.538653 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6517 12:14:46.541253 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6518 12:14:46.544677 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6519 12:14:46.551140 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6520 12:14:46.554986 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6521 12:14:46.557726 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6522 12:14:46.565303 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6523 12:14:46.568128 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6524 12:14:46.571643 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6525 12:14:46.574733 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6526 12:14:46.580941 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6527 12:14:46.585089 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6528 12:14:46.585638 ==
6529 12:14:46.587769 Dram Type= 6, Freq= 0, CH_1, rank 0
6530 12:14:46.591755 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6531 12:14:46.592309 ==
6532 12:14:46.594582 DQS Delay:
6533 12:14:46.595245 DQS0 = 43, DQS1 = 59
6534 12:14:46.597302 DQM Delay:
6535 12:14:46.597761 DQM0 = 6, DQM1 = 15
6536 12:14:46.598143 DQ Delay:
6537 12:14:46.601197 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6538 12:14:46.604825 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6539 12:14:46.607979 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6540 12:14:46.611845 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6541 12:14:46.612399
6542 12:14:46.612819
6543 12:14:46.613173 ==
6544 12:14:46.614071 Dram Type= 6, Freq= 0, CH_1, rank 0
6545 12:14:46.620817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6546 12:14:46.621279 ==
6547 12:14:46.621647
6548 12:14:46.621985
6549 12:14:46.622311 TX Vref Scan disable
6550 12:14:46.624218 == TX Byte 0 ==
6551 12:14:46.627519 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6552 12:14:46.630467 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6553 12:14:46.633731 == TX Byte 1 ==
6554 12:14:46.638010 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6555 12:14:46.640481 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6556 12:14:46.640997 ==
6557 12:14:46.643427 Dram Type= 6, Freq= 0, CH_1, rank 0
6558 12:14:46.650427 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6559 12:14:46.650976 ==
6560 12:14:46.651348
6561 12:14:46.651691
6562 12:14:46.653902 TX Vref Scan disable
6563 12:14:46.654462 == TX Byte 0 ==
6564 12:14:46.656906 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6565 12:14:46.663323 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6566 12:14:46.663791 == TX Byte 1 ==
6567 12:14:46.666771 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6568 12:14:46.673266 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6569 12:14:46.673731
6570 12:14:46.674100 [DATLAT]
6571 12:14:46.674442 Freq=400, CH1 RK0
6572 12:14:46.674779
6573 12:14:46.676879 DATLAT Default: 0xf
6574 12:14:46.680198 0, 0xFFFF, sum = 0
6575 12:14:46.680804 1, 0xFFFF, sum = 0
6576 12:14:46.684687 2, 0xFFFF, sum = 0
6577 12:14:46.685295 3, 0xFFFF, sum = 0
6578 12:14:46.686528 4, 0xFFFF, sum = 0
6579 12:14:46.686998 5, 0xFFFF, sum = 0
6580 12:14:46.689804 6, 0xFFFF, sum = 0
6581 12:14:46.690366 7, 0xFFFF, sum = 0
6582 12:14:46.693552 8, 0xFFFF, sum = 0
6583 12:14:46.694020 9, 0xFFFF, sum = 0
6584 12:14:46.696299 10, 0xFFFF, sum = 0
6585 12:14:46.696824 11, 0xFFFF, sum = 0
6586 12:14:46.700455 12, 0x0, sum = 1
6587 12:14:46.701085 13, 0x0, sum = 2
6588 12:14:46.703560 14, 0x0, sum = 3
6589 12:14:46.704137 15, 0x0, sum = 4
6590 12:14:46.706864 best_step = 13
6591 12:14:46.707413
6592 12:14:46.707791 ==
6593 12:14:46.710304 Dram Type= 6, Freq= 0, CH_1, rank 0
6594 12:14:46.713394 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6595 12:14:46.713860 ==
6596 12:14:46.716323 RX Vref Scan: 1
6597 12:14:46.716840
6598 12:14:46.717223 RX Vref 0 -> 0, step: 1
6599 12:14:46.717574
6600 12:14:46.720844 RX Delay -359 -> 252, step: 8
6601 12:14:46.721408
6602 12:14:46.723931 Set Vref, RX VrefLevel [Byte0]: 52
6603 12:14:46.727052 [Byte1]: 49
6604 12:14:46.731074
6605 12:14:46.731630 Final RX Vref Byte 0 = 52 to rank0
6606 12:14:46.734051 Final RX Vref Byte 1 = 49 to rank0
6607 12:14:46.737502 Final RX Vref Byte 0 = 52 to rank1
6608 12:14:46.740506 Final RX Vref Byte 1 = 49 to rank1==
6609 12:14:46.744237 Dram Type= 6, Freq= 0, CH_1, rank 0
6610 12:14:46.751361 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6611 12:14:46.751926 ==
6612 12:14:46.752300 DQS Delay:
6613 12:14:46.755347 DQS0 = 48, DQS1 = 64
6614 12:14:46.756028 DQM Delay:
6615 12:14:46.756411 DQM0 = 7, DQM1 = 16
6616 12:14:46.757166 DQ Delay:
6617 12:14:46.760439 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6618 12:14:46.760951 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6619 12:14:46.764371 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6620 12:14:46.767082 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6621 12:14:46.767539
6622 12:14:46.767905
6623 12:14:46.776931 [DQSOSCAuto] RK0, (LSB)MR18= 0xcfcf, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6624 12:14:46.780988 CH1 RK0: MR19=C0C, MR18=CFCF
6625 12:14:46.787432 CH1_RK0: MR19=0xC0C, MR18=0xCFCF, DQSOSC=384, MR23=63, INC=400, DEC=267
6626 12:14:46.787991 ==
6627 12:14:46.790544 Dram Type= 6, Freq= 0, CH_1, rank 1
6628 12:14:46.794093 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6629 12:14:46.794654 ==
6630 12:14:46.797447 [Gating] SW mode calibration
6631 12:14:46.804018 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6632 12:14:46.807116 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6633 12:14:46.814118 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6634 12:14:46.816861 0 7 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
6635 12:14:46.820193 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6636 12:14:46.826820 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6637 12:14:46.830584 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6638 12:14:46.834171 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6639 12:14:46.840452 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6640 12:14:46.843394 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6641 12:14:46.846942 Total UI for P1: 0, mck2ui 16
6642 12:14:46.850202 best dqsien dly found for B0: ( 0, 10, 8)
6643 12:14:46.853608 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6644 12:14:46.856975 Total UI for P1: 0, mck2ui 16
6645 12:14:46.860073 best dqsien dly found for B1: ( 0, 10, 16)
6646 12:14:46.863185 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6647 12:14:46.866486 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6648 12:14:46.870386
6649 12:14:46.873098 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6650 12:14:46.876991 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6651 12:14:46.880030 [Gating] SW calibration Done
6652 12:14:46.880585 ==
6653 12:14:46.883642 Dram Type= 6, Freq= 0, CH_1, rank 1
6654 12:14:46.886280 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6655 12:14:46.886745 ==
6656 12:14:46.887114 RX Vref Scan: 0
6657 12:14:46.889746
6658 12:14:46.890294 RX Vref 0 -> 0, step: 1
6659 12:14:46.890665
6660 12:14:46.893254 RX Delay -410 -> 252, step: 16
6661 12:14:46.896496 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6662 12:14:46.903415 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6663 12:14:46.906620 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6664 12:14:46.909611 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6665 12:14:46.912817 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6666 12:14:46.919166 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6667 12:14:46.923160 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6668 12:14:46.925990 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6669 12:14:46.929759 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6670 12:14:46.936537 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6671 12:14:46.940127 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6672 12:14:46.943958 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6673 12:14:46.946398 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6674 12:14:46.952996 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6675 12:14:46.956170 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6676 12:14:46.959370 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6677 12:14:46.959854 ==
6678 12:14:46.963178 Dram Type= 6, Freq= 0, CH_1, rank 1
6679 12:14:46.969479 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6680 12:14:46.970043 ==
6681 12:14:46.970418 DQS Delay:
6682 12:14:46.972574 DQS0 = 35, DQS1 = 59
6683 12:14:46.973174 DQM Delay:
6684 12:14:46.973549 DQM0 = 5, DQM1 = 18
6685 12:14:46.976187 DQ Delay:
6686 12:14:46.979522 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6687 12:14:46.980083 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6688 12:14:46.982826 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6689 12:14:46.986282 DQ12 =32, DQ13 =24, DQ14 =32, DQ15 =24
6690 12:14:46.986767
6691 12:14:46.987135
6692 12:14:46.989246 ==
6693 12:14:46.993254 Dram Type= 6, Freq= 0, CH_1, rank 1
6694 12:14:46.995773 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6695 12:14:46.996266 ==
6696 12:14:46.996641
6697 12:14:46.997246
6698 12:14:46.999231 TX Vref Scan disable
6699 12:14:46.999689 == TX Byte 0 ==
6700 12:14:47.003034 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6701 12:14:47.009141 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6702 12:14:47.009696 == TX Byte 1 ==
6703 12:14:47.012464 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6704 12:14:47.019403 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6705 12:14:47.019939 ==
6706 12:14:47.022795 Dram Type= 6, Freq= 0, CH_1, rank 1
6707 12:14:47.026090 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6708 12:14:47.026655 ==
6709 12:14:47.027180
6710 12:14:47.027633
6711 12:14:47.028740 TX Vref Scan disable
6712 12:14:47.029206 == TX Byte 0 ==
6713 12:14:47.032196 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6714 12:14:47.039037 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6715 12:14:47.039600 == TX Byte 1 ==
6716 12:14:47.042277 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6717 12:14:47.048659 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6718 12:14:47.049266
6719 12:14:47.049636 [DATLAT]
6720 12:14:47.049975 Freq=400, CH1 RK1
6721 12:14:47.050305
6722 12:14:47.052100 DATLAT Default: 0xd
6723 12:14:47.055984 0, 0xFFFF, sum = 0
6724 12:14:47.056539 1, 0xFFFF, sum = 0
6725 12:14:47.058430 2, 0xFFFF, sum = 0
6726 12:14:47.058895 3, 0xFFFF, sum = 0
6727 12:14:47.062071 4, 0xFFFF, sum = 0
6728 12:14:47.062543 5, 0xFFFF, sum = 0
6729 12:14:47.065663 6, 0xFFFF, sum = 0
6730 12:14:47.066230 7, 0xFFFF, sum = 0
6731 12:14:47.068519 8, 0xFFFF, sum = 0
6732 12:14:47.069148 9, 0xFFFF, sum = 0
6733 12:14:47.071704 10, 0xFFFF, sum = 0
6734 12:14:47.072179 11, 0xFFFF, sum = 0
6735 12:14:47.076160 12, 0x0, sum = 1
6736 12:14:47.076764 13, 0x0, sum = 2
6737 12:14:47.078823 14, 0x0, sum = 3
6738 12:14:47.079385 15, 0x0, sum = 4
6739 12:14:47.081959 best_step = 13
6740 12:14:47.082515
6741 12:14:47.082890 ==
6742 12:14:47.086411 Dram Type= 6, Freq= 0, CH_1, rank 1
6743 12:14:47.088884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6744 12:14:47.089448 ==
6745 12:14:47.091840 RX Vref Scan: 0
6746 12:14:47.092304
6747 12:14:47.092674 RX Vref 0 -> 0, step: 1
6748 12:14:47.093061
6749 12:14:47.096534 RX Delay -359 -> 252, step: 8
6750 12:14:47.103540 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6751 12:14:47.105904 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6752 12:14:47.109769 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6753 12:14:47.113063 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6754 12:14:47.118922 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6755 12:14:47.122904 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6756 12:14:47.126187 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6757 12:14:47.129687 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6758 12:14:47.136101 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6759 12:14:47.138909 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6760 12:14:47.142678 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6761 12:14:47.148940 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6762 12:14:47.152647 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6763 12:14:47.155898 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6764 12:14:47.159247 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6765 12:14:47.165671 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6766 12:14:47.166229 ==
6767 12:14:47.168944 Dram Type= 6, Freq= 0, CH_1, rank 1
6768 12:14:47.172162 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6769 12:14:47.172756 ==
6770 12:14:47.173137 DQS Delay:
6771 12:14:47.175263 DQS0 = 44, DQS1 = 64
6772 12:14:47.175816 DQM Delay:
6773 12:14:47.179015 DQM0 = 6, DQM1 = 15
6774 12:14:47.179571 DQ Delay:
6775 12:14:47.182267 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6776 12:14:47.185969 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6777 12:14:47.189306 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6778 12:14:47.192319 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6779 12:14:47.192912
6780 12:14:47.193283
6781 12:14:47.199220 [DQSOSCAuto] RK1, (LSB)MR18= 0xadad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6782 12:14:47.202870 CH1 RK1: MR19=C0C, MR18=ADAD
6783 12:14:47.208777 CH1_RK1: MR19=0xC0C, MR18=0xADAD, DQSOSC=388, MR23=63, INC=392, DEC=261
6784 12:14:47.212057 [RxdqsGatingPostProcess] freq 400
6785 12:14:47.219044 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6786 12:14:47.221977 Pre-setting of DQS Precalculation
6787 12:14:47.225622 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6788 12:14:47.231609 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6789 12:14:47.238607 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6790 12:14:47.239167
6791 12:14:47.239535
6792 12:14:47.241247 [Calibration Summary] 800 Mbps
6793 12:14:47.244755 CH 0, Rank 0
6794 12:14:47.245232 SW Impedance : PASS
6795 12:14:47.248246 DUTY Scan : NO K
6796 12:14:47.252254 ZQ Calibration : PASS
6797 12:14:47.252873 Jitter Meter : NO K
6798 12:14:47.254625 CBT Training : PASS
6799 12:14:47.257948 Write leveling : PASS
6800 12:14:47.258406 RX DQS gating : PASS
6801 12:14:47.262452 RX DQ/DQS(RDDQC) : PASS
6802 12:14:47.265395 TX DQ/DQS : PASS
6803 12:14:47.265856 RX DATLAT : PASS
6804 12:14:47.268420 RX DQ/DQS(Engine): PASS
6805 12:14:47.272162 TX OE : NO K
6806 12:14:47.272756 All Pass.
6807 12:14:47.273135
6808 12:14:47.273478 CH 0, Rank 1
6809 12:14:47.274166 SW Impedance : PASS
6810 12:14:47.278223 DUTY Scan : NO K
6811 12:14:47.278786 ZQ Calibration : PASS
6812 12:14:47.281550 Jitter Meter : NO K
6813 12:14:47.285092 CBT Training : PASS
6814 12:14:47.285653 Write leveling : NO K
6815 12:14:47.287823 RX DQS gating : PASS
6816 12:14:47.288378 RX DQ/DQS(RDDQC) : PASS
6817 12:14:47.291622 TX DQ/DQS : PASS
6818 12:14:47.294482 RX DATLAT : PASS
6819 12:14:47.295040 RX DQ/DQS(Engine): PASS
6820 12:14:47.298279 TX OE : NO K
6821 12:14:47.298931 All Pass.
6822 12:14:47.299386
6823 12:14:47.300800 CH 1, Rank 0
6824 12:14:47.301257 SW Impedance : PASS
6825 12:14:47.304489 DUTY Scan : NO K
6826 12:14:47.307763 ZQ Calibration : PASS
6827 12:14:47.308312 Jitter Meter : NO K
6828 12:14:47.311297 CBT Training : PASS
6829 12:14:47.314398 Write leveling : PASS
6830 12:14:47.314856 RX DQS gating : PASS
6831 12:14:47.317944 RX DQ/DQS(RDDQC) : PASS
6832 12:14:47.320630 TX DQ/DQS : PASS
6833 12:14:47.321201 RX DATLAT : PASS
6834 12:14:47.324672 RX DQ/DQS(Engine): PASS
6835 12:14:47.328077 TX OE : NO K
6836 12:14:47.328623 All Pass.
6837 12:14:47.329063
6838 12:14:47.329415 CH 1, Rank 1
6839 12:14:47.330945 SW Impedance : PASS
6840 12:14:47.334822 DUTY Scan : NO K
6841 12:14:47.335358 ZQ Calibration : PASS
6842 12:14:47.337552 Jitter Meter : NO K
6843 12:14:47.340512 CBT Training : PASS
6844 12:14:47.341105 Write leveling : NO K
6845 12:14:47.344395 RX DQS gating : PASS
6846 12:14:47.348051 RX DQ/DQS(RDDQC) : PASS
6847 12:14:47.348510 TX DQ/DQS : PASS
6848 12:14:47.350579 RX DATLAT : PASS
6849 12:14:47.351034 RX DQ/DQS(Engine): PASS
6850 12:14:47.353793 TX OE : NO K
6851 12:14:47.354364 All Pass.
6852 12:14:47.354737
6853 12:14:47.357213 DramC Write-DBI off
6854 12:14:47.360738 PER_BANK_REFRESH: Hybrid Mode
6855 12:14:47.361212 TX_TRACKING: ON
6856 12:14:47.370509 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6857 12:14:47.373549 [FAST_K] Save calibration result to emmc
6858 12:14:47.377492 dramc_set_vcore_voltage set vcore to 725000
6859 12:14:47.380014 Read voltage for 1600, 0
6860 12:14:47.380568 Vio18 = 0
6861 12:14:47.383705 Vcore = 725000
6862 12:14:47.384259 Vdram = 0
6863 12:14:47.384636 Vddq = 0
6864 12:14:47.385055 Vmddr = 0
6865 12:14:47.390727 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6866 12:14:47.396873 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6867 12:14:47.397434 MEM_TYPE=3, freq_sel=13
6868 12:14:47.399986 sv_algorithm_assistance_LP4_3733
6869 12:14:47.403570 ============ PULL DRAM RESETB DOWN ============
6870 12:14:47.410011 ========== PULL DRAM RESETB DOWN end =========
6871 12:14:47.414070 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6872 12:14:47.416655 ===================================
6873 12:14:47.419943 LPDDR4 DRAM CONFIGURATION
6874 12:14:47.423309 ===================================
6875 12:14:47.423862 EX_ROW_EN[0] = 0x0
6876 12:14:47.426048 EX_ROW_EN[1] = 0x0
6877 12:14:47.432051 LP4Y_EN = 0x0
6878 12:14:47.432615 WORK_FSP = 0x1
6879 12:14:47.433421 WL = 0x5
6880 12:14:47.433797 RL = 0x5
6881 12:14:47.436642 BL = 0x2
6882 12:14:47.437251 RPST = 0x0
6883 12:14:47.439974 RD_PRE = 0x0
6884 12:14:47.440528 WR_PRE = 0x1
6885 12:14:47.443522 WR_PST = 0x1
6886 12:14:47.444081 DBI_WR = 0x0
6887 12:14:47.446536 DBI_RD = 0x0
6888 12:14:47.447094 OTF = 0x1
6889 12:14:47.449304 ===================================
6890 12:14:47.453284 ===================================
6891 12:14:47.456450 ANA top config
6892 12:14:47.459155 ===================================
6893 12:14:47.459617 DLL_ASYNC_EN = 0
6894 12:14:47.462856 ALL_SLAVE_EN = 0
6895 12:14:47.467529 NEW_RANK_MODE = 1
6896 12:14:47.469129 DLL_IDLE_MODE = 1
6897 12:14:47.472324 LP45_APHY_COMB_EN = 1
6898 12:14:47.472820 TX_ODT_DIS = 0
6899 12:14:47.476510 NEW_8X_MODE = 1
6900 12:14:47.479632 ===================================
6901 12:14:47.483647 ===================================
6902 12:14:47.487103 data_rate = 3200
6903 12:14:47.489247 CKR = 1
6904 12:14:47.492961 DQ_P2S_RATIO = 8
6905 12:14:47.496791 ===================================
6906 12:14:47.497260 CA_P2S_RATIO = 8
6907 12:14:47.499258 DQ_CA_OPEN = 0
6908 12:14:47.502421 DQ_SEMI_OPEN = 0
6909 12:14:47.506128 CA_SEMI_OPEN = 0
6910 12:14:47.509104 CA_FULL_RATE = 0
6911 12:14:47.512531 DQ_CKDIV4_EN = 0
6912 12:14:47.513143 CA_CKDIV4_EN = 0
6913 12:14:47.516455 CA_PREDIV_EN = 0
6914 12:14:47.518991 PH8_DLY = 12
6915 12:14:47.522692 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6916 12:14:47.525866 DQ_AAMCK_DIV = 4
6917 12:14:47.529392 CA_AAMCK_DIV = 4
6918 12:14:47.532367 CA_ADMCK_DIV = 4
6919 12:14:47.532988 DQ_TRACK_CA_EN = 0
6920 12:14:47.535707 CA_PICK = 1600
6921 12:14:47.538687 CA_MCKIO = 1600
6922 12:14:47.542427 MCKIO_SEMI = 0
6923 12:14:47.545458 PLL_FREQ = 3068
6924 12:14:47.548530 DQ_UI_PI_RATIO = 32
6925 12:14:47.552608 CA_UI_PI_RATIO = 0
6926 12:14:47.555283 ===================================
6927 12:14:47.558756 ===================================
6928 12:14:47.559312 memory_type:LPDDR4
6929 12:14:47.562405 GP_NUM : 10
6930 12:14:47.565411 SRAM_EN : 1
6931 12:14:47.565871 MD32_EN : 0
6932 12:14:47.569124 ===================================
6933 12:14:47.571912 [ANA_INIT] >>>>>>>>>>>>>>
6934 12:14:47.576160 <<<<<< [CONFIGURE PHASE]: ANA_TX
6935 12:14:47.578215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6936 12:14:47.581530 ===================================
6937 12:14:47.584883 data_rate = 3200,PCW = 0X7600
6938 12:14:47.588670 ===================================
6939 12:14:47.591562 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6940 12:14:47.595201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6941 12:14:47.601256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6942 12:14:47.604792 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6943 12:14:47.607891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6944 12:14:47.615072 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6945 12:14:47.615762 [ANA_INIT] flow start
6946 12:14:47.618455 [ANA_INIT] PLL >>>>>>>>
6947 12:14:47.622634 [ANA_INIT] PLL <<<<<<<<
6948 12:14:47.623193 [ANA_INIT] MIDPI >>>>>>>>
6949 12:14:47.624637 [ANA_INIT] MIDPI <<<<<<<<
6950 12:14:47.628024 [ANA_INIT] DLL >>>>>>>>
6951 12:14:47.628483 [ANA_INIT] DLL <<<<<<<<
6952 12:14:47.631801 [ANA_INIT] flow end
6953 12:14:47.635157 ============ LP4 DIFF to SE enter ============
6954 12:14:47.637466 ============ LP4 DIFF to SE exit ============
6955 12:14:47.641543 [ANA_INIT] <<<<<<<<<<<<<
6956 12:14:47.644876 [Flow] Enable top DCM control >>>>>
6957 12:14:47.647840 [Flow] Enable top DCM control <<<<<
6958 12:14:47.651139 Enable DLL master slave shuffle
6959 12:14:47.658339 ==============================================================
6960 12:14:47.658912 Gating Mode config
6961 12:14:47.664694 ==============================================================
6962 12:14:47.665308 Config description:
6963 12:14:47.674507 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6964 12:14:47.681190 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6965 12:14:47.687433 SELPH_MODE 0: By rank 1: By Phase
6966 12:14:47.690920 ==============================================================
6967 12:14:47.694324 GAT_TRACK_EN = 1
6968 12:14:47.697590 RX_GATING_MODE = 2
6969 12:14:47.701191 RX_GATING_TRACK_MODE = 2
6970 12:14:47.704239 SELPH_MODE = 1
6971 12:14:47.707602 PICG_EARLY_EN = 1
6972 12:14:47.710523 VALID_LAT_VALUE = 1
6973 12:14:47.717472 ==============================================================
6974 12:14:47.720245 Enter into Gating configuration >>>>
6975 12:14:47.723689 Exit from Gating configuration <<<<
6976 12:14:47.727954 Enter into DVFS_PRE_config >>>>>
6977 12:14:47.737244 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6978 12:14:47.740257 Exit from DVFS_PRE_config <<<<<
6979 12:14:47.743858 Enter into PICG configuration >>>>
6980 12:14:47.746783 Exit from PICG configuration <<<<
6981 12:14:47.750256 [RX_INPUT] configuration >>>>>
6982 12:14:47.754657 [RX_INPUT] configuration <<<<<
6983 12:14:47.756836 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6984 12:14:47.763422 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6985 12:14:47.770309 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6986 12:14:47.773627 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6987 12:14:47.780278 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6988 12:14:47.786769 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6989 12:14:47.790137 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6990 12:14:47.796700 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6991 12:14:47.799846 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6992 12:14:47.804063 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6993 12:14:47.805923 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6994 12:14:47.813589 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6995 12:14:47.816273 ===================================
6996 12:14:47.816879 LPDDR4 DRAM CONFIGURATION
6997 12:14:47.819243 ===================================
6998 12:14:47.822785 EX_ROW_EN[0] = 0x0
6999 12:14:47.825644 EX_ROW_EN[1] = 0x0
7000 12:14:47.826104 LP4Y_EN = 0x0
7001 12:14:47.829705 WORK_FSP = 0x1
7002 12:14:47.830270 WL = 0x5
7003 12:14:47.832613 RL = 0x5
7004 12:14:47.833112 BL = 0x2
7005 12:14:47.836033 RPST = 0x0
7006 12:14:47.836595 RD_PRE = 0x0
7007 12:14:47.839266 WR_PRE = 0x1
7008 12:14:47.839829 WR_PST = 0x1
7009 12:14:47.842395 DBI_WR = 0x0
7010 12:14:47.843052 DBI_RD = 0x0
7011 12:14:47.846002 OTF = 0x1
7012 12:14:47.849174 ===================================
7013 12:14:47.852567 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7014 12:14:47.855806 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7015 12:14:47.862142 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7016 12:14:47.865916 ===================================
7017 12:14:47.866379 LPDDR4 DRAM CONFIGURATION
7018 12:14:47.868835 ===================================
7019 12:14:47.872392 EX_ROW_EN[0] = 0x10
7020 12:14:47.876528 EX_ROW_EN[1] = 0x0
7021 12:14:47.877027 LP4Y_EN = 0x0
7022 12:14:47.878433 WORK_FSP = 0x1
7023 12:14:47.878836 WL = 0x5
7024 12:14:47.882475 RL = 0x5
7025 12:14:47.883036 BL = 0x2
7026 12:14:47.885363 RPST = 0x0
7027 12:14:47.885821 RD_PRE = 0x0
7028 12:14:47.889556 WR_PRE = 0x1
7029 12:14:47.890118 WR_PST = 0x1
7030 12:14:47.892112 DBI_WR = 0x0
7031 12:14:47.892676 DBI_RD = 0x0
7032 12:14:47.896229 OTF = 0x1
7033 12:14:47.898780 ===================================
7034 12:14:47.905190 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7035 12:14:47.905757 ==
7036 12:14:47.908796 Dram Type= 6, Freq= 0, CH_0, rank 0
7037 12:14:47.911919 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7038 12:14:47.912380 ==
7039 12:14:47.915740 [Duty_Offset_Calibration]
7040 12:14:47.916299 B0:0 B1:2 CA:1
7041 12:14:47.916668
7042 12:14:47.918516 [DutyScan_Calibration_Flow] k_type=0
7043 12:14:47.929679
7044 12:14:47.930256 ==CLK 0==
7045 12:14:47.932760 Final CLK duty delay cell = 0
7046 12:14:47.935704 [0] MAX Duty = 5187%(X100), DQS PI = 24
7047 12:14:47.939202 [0] MIN Duty = 4938%(X100), DQS PI = 54
7048 12:14:47.942661 [0] AVG Duty = 5062%(X100)
7049 12:14:47.943308
7050 12:14:47.946121 CH0 CLK Duty spec in!! Max-Min= 249%
7051 12:14:47.949187 [DutyScan_Calibration_Flow] ====Done====
7052 12:14:47.949747
7053 12:14:47.952463 [DutyScan_Calibration_Flow] k_type=1
7054 12:14:47.970901
7055 12:14:47.971502 ==DQS 0 ==
7056 12:14:47.972977 Final DQS duty delay cell = 0
7057 12:14:47.976603 [0] MAX Duty = 5156%(X100), DQS PI = 34
7058 12:14:47.979727 [0] MIN Duty = 5031%(X100), DQS PI = 8
7059 12:14:47.982772 [0] AVG Duty = 5093%(X100)
7060 12:14:47.983334
7061 12:14:47.983702 ==DQS 1 ==
7062 12:14:47.986915 Final DQS duty delay cell = 0
7063 12:14:47.989494 [0] MAX Duty = 5031%(X100), DQS PI = 6
7064 12:14:47.992622 [0] MIN Duty = 4876%(X100), DQS PI = 16
7065 12:14:47.993227 [0] AVG Duty = 4953%(X100)
7066 12:14:47.996369
7067 12:14:47.999544 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7068 12:14:48.000006
7069 12:14:48.002308 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7070 12:14:48.005981 [DutyScan_Calibration_Flow] ====Done====
7071 12:14:48.006444
7072 12:14:48.009308 [DutyScan_Calibration_Flow] k_type=3
7073 12:14:48.027863
7074 12:14:48.028426 ==DQM 0 ==
7075 12:14:48.030062 Final DQM duty delay cell = 0
7076 12:14:48.033238 [0] MAX Duty = 5187%(X100), DQS PI = 22
7077 12:14:48.036490 [0] MIN Duty = 4907%(X100), DQS PI = 42
7078 12:14:48.039550 [0] AVG Duty = 5047%(X100)
7079 12:14:48.040013
7080 12:14:48.040380 ==DQM 1 ==
7081 12:14:48.043227 Final DQM duty delay cell = 0
7082 12:14:48.046512 [0] MAX Duty = 5000%(X100), DQS PI = 4
7083 12:14:48.049914 [0] MIN Duty = 4782%(X100), DQS PI = 14
7084 12:14:48.052897 [0] AVG Duty = 4891%(X100)
7085 12:14:48.053457
7086 12:14:48.056052 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7087 12:14:48.056514
7088 12:14:48.059509 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7089 12:14:48.062613 [DutyScan_Calibration_Flow] ====Done====
7090 12:14:48.063147
7091 12:14:48.066176 [DutyScan_Calibration_Flow] k_type=2
7092 12:14:48.082808
7093 12:14:48.083368 ==DQ 0 ==
7094 12:14:48.085914 Final DQ duty delay cell = 0
7095 12:14:48.089603 [0] MAX Duty = 5218%(X100), DQS PI = 18
7096 12:14:48.092858 [0] MIN Duty = 4938%(X100), DQS PI = 56
7097 12:14:48.093425 [0] AVG Duty = 5078%(X100)
7098 12:14:48.095810
7099 12:14:48.096268 ==DQ 1 ==
7100 12:14:48.099778 Final DQ duty delay cell = -4
7101 12:14:48.102497 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7102 12:14:48.105870 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7103 12:14:48.109518 [-4] AVG Duty = 4953%(X100)
7104 12:14:48.109979
7105 12:14:48.112390 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7106 12:14:48.112896
7107 12:14:48.116026 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7108 12:14:48.119293 [DutyScan_Calibration_Flow] ====Done====
7109 12:14:48.119855 ==
7110 12:14:48.122601 Dram Type= 6, Freq= 0, CH_1, rank 0
7111 12:14:48.126134 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7112 12:14:48.126705 ==
7113 12:14:48.129125 [Duty_Offset_Calibration]
7114 12:14:48.129688 B0:0 B1:4 CA:-5
7115 12:14:48.130052
7116 12:14:48.132807 [DutyScan_Calibration_Flow] k_type=0
7117 12:14:48.143730
7118 12:14:48.144295 ==CLK 0==
7119 12:14:48.146715 Final CLK duty delay cell = 0
7120 12:14:48.150387 [0] MAX Duty = 5156%(X100), DQS PI = 22
7121 12:14:48.153414 [0] MIN Duty = 4906%(X100), DQS PI = 50
7122 12:14:48.153981 [0] AVG Duty = 5031%(X100)
7123 12:14:48.156497
7124 12:14:48.160108 CH1 CLK Duty spec in!! Max-Min= 250%
7125 12:14:48.163006 [DutyScan_Calibration_Flow] ====Done====
7126 12:14:48.163490
7127 12:14:48.166703 [DutyScan_Calibration_Flow] k_type=1
7128 12:14:48.184227
7129 12:14:48.184819 ==DQS 0 ==
7130 12:14:48.186058 Final DQS duty delay cell = 0
7131 12:14:48.190862 [0] MAX Duty = 5187%(X100), DQS PI = 20
7132 12:14:48.193286 [0] MIN Duty = 4876%(X100), DQS PI = 42
7133 12:14:48.196739 [0] AVG Duty = 5031%(X100)
7134 12:14:48.197207
7135 12:14:48.197572 ==DQS 1 ==
7136 12:14:48.199524 Final DQS duty delay cell = 0
7137 12:14:48.203563 [0] MAX Duty = 5187%(X100), DQS PI = 18
7138 12:14:48.206731 [0] MIN Duty = 5093%(X100), DQS PI = 24
7139 12:14:48.209974 [0] AVG Duty = 5140%(X100)
7140 12:14:48.210535
7141 12:14:48.213846 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7142 12:14:48.214408
7143 12:14:48.216091 CH1 DQS 1 Duty spec in!! Max-Min= 94%
7144 12:14:48.219463 [DutyScan_Calibration_Flow] ====Done====
7145 12:14:48.220019
7146 12:14:48.223011 [DutyScan_Calibration_Flow] k_type=3
7147 12:14:48.239143
7148 12:14:48.239723 ==DQM 0 ==
7149 12:14:48.241768 Final DQM duty delay cell = -4
7150 12:14:48.245307 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7151 12:14:48.248277 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7152 12:14:48.252265 [-4] AVG Duty = 4922%(X100)
7153 12:14:48.252888
7154 12:14:48.253275 ==DQM 1 ==
7155 12:14:48.256060 Final DQM duty delay cell = -4
7156 12:14:48.258774 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7157 12:14:48.261393 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7158 12:14:48.264614 [-4] AVG Duty = 5000%(X100)
7159 12:14:48.265112
7160 12:14:48.267916 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7161 12:14:48.268378
7162 12:14:48.271293 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7163 12:14:48.274826 [DutyScan_Calibration_Flow] ====Done====
7164 12:14:48.275287
7165 12:14:48.278148 [DutyScan_Calibration_Flow] k_type=2
7166 12:14:48.296118
7167 12:14:48.296684 ==DQ 0 ==
7168 12:14:48.299986 Final DQ duty delay cell = 0
7169 12:14:48.303170 [0] MAX Duty = 5093%(X100), DQS PI = 18
7170 12:14:48.305962 [0] MIN Duty = 4938%(X100), DQS PI = 48
7171 12:14:48.306425 [0] AVG Duty = 5015%(X100)
7172 12:14:48.309061
7173 12:14:48.309519 ==DQ 1 ==
7174 12:14:48.312420 Final DQ duty delay cell = 0
7175 12:14:48.316353 [0] MAX Duty = 5031%(X100), DQS PI = 4
7176 12:14:48.319521 [0] MIN Duty = 4907%(X100), DQS PI = 14
7177 12:14:48.320081 [0] AVG Duty = 4969%(X100)
7178 12:14:48.322729
7179 12:14:48.325938 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7180 12:14:48.326500
7181 12:14:48.328642 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7182 12:14:48.332325 [DutyScan_Calibration_Flow] ====Done====
7183 12:14:48.335530 nWR fixed to 30
7184 12:14:48.336090 [ModeRegInit_LP4] CH0 RK0
7185 12:14:48.338702 [ModeRegInit_LP4] CH0 RK1
7186 12:14:48.342234 [ModeRegInit_LP4] CH1 RK0
7187 12:14:48.345651 [ModeRegInit_LP4] CH1 RK1
7188 12:14:48.346235 match AC timing 4
7189 12:14:48.352227 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7190 12:14:48.355992 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7191 12:14:48.360448 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7192 12:14:48.365552 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7193 12:14:48.369355 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7194 12:14:48.369917 [MiockJmeterHQA]
7195 12:14:48.370287
7196 12:14:48.372268 [DramcMiockJmeter] u1RxGatingPI = 0
7197 12:14:48.374895 0 : 4255, 4029
7198 12:14:48.375365 4 : 4363, 4137
7199 12:14:48.378610 8 : 4252, 4027
7200 12:14:48.379077 12 : 4253, 4026
7201 12:14:48.379447 16 : 4252, 4027
7202 12:14:48.382478 20 : 4253, 4026
7203 12:14:48.383043 24 : 4255, 4030
7204 12:14:48.385016 28 : 4252, 4027
7205 12:14:48.385484 32 : 4252, 4027
7206 12:14:48.388740 36 : 4366, 4139
7207 12:14:48.389323 40 : 4258, 4030
7208 12:14:48.391782 44 : 4252, 4029
7209 12:14:48.392368 48 : 4361, 4137
7210 12:14:48.392963 52 : 4361, 4137
7211 12:14:48.395084 56 : 4250, 4027
7212 12:14:48.395555 60 : 4255, 4030
7213 12:14:48.398157 64 : 4250, 4027
7214 12:14:48.398629 68 : 4250, 4027
7215 12:14:48.401702 72 : 4250, 4026
7216 12:14:48.402168 76 : 4255, 4029
7217 12:14:48.404909 80 : 4250, 4027
7218 12:14:48.405567 84 : 4360, 4138
7219 12:14:48.405955 88 : 4250, 4027
7220 12:14:48.409636 92 : 4250, 4027
7221 12:14:48.410101 96 : 4363, 4137
7222 12:14:48.412224 100 : 4361, 2094
7223 12:14:48.412693 104 : 4252, 0
7224 12:14:48.415934 108 : 4360, 0
7225 12:14:48.416399 112 : 4249, 0
7226 12:14:48.416833 116 : 4250, 0
7227 12:14:48.417984 120 : 4250, 0
7228 12:14:48.418452 124 : 4250, 0
7229 12:14:48.421649 128 : 4250, 0
7230 12:14:48.422116 132 : 4250, 0
7231 12:14:48.422490 136 : 4252, 0
7232 12:14:48.425033 140 : 4255, 0
7233 12:14:48.425500 144 : 4361, 0
7234 12:14:48.425871 148 : 4361, 0
7235 12:14:48.428388 152 : 4255, 0
7236 12:14:48.428896 156 : 4250, 0
7237 12:14:48.431576 160 : 4250, 0
7238 12:14:48.432138 164 : 4252, 0
7239 12:14:48.432512 168 : 4361, 0
7240 12:14:48.434968 172 : 4361, 0
7241 12:14:48.435530 176 : 4250, 0
7242 12:14:48.437981 180 : 4361, 0
7243 12:14:48.438448 184 : 4250, 0
7244 12:14:48.438822 188 : 4250, 0
7245 12:14:48.442257 192 : 4250, 0
7246 12:14:48.442822 196 : 4251, 0
7247 12:14:48.445303 200 : 4363, 0
7248 12:14:48.445766 204 : 4250, 0
7249 12:14:48.446137 208 : 4249, 0
7250 12:14:48.448304 212 : 4250, 0
7251 12:14:48.448908 216 : 4251, 0
7252 12:14:48.452134 220 : 4361, 556
7253 12:14:48.452697 224 : 4250, 4011
7254 12:14:48.453189 228 : 4253, 4029
7255 12:14:48.455230 232 : 4252, 4030
7256 12:14:48.455793 236 : 4252, 4029
7257 12:14:48.458049 240 : 4363, 4138
7258 12:14:48.458519 244 : 4250, 4027
7259 12:14:48.461440 248 : 4250, 4027
7260 12:14:48.461906 252 : 4250, 4027
7261 12:14:48.464634 256 : 4250, 4027
7262 12:14:48.465137 260 : 4253, 4030
7263 12:14:48.468417 264 : 4250, 4027
7264 12:14:48.469056 268 : 4250, 4027
7265 12:14:48.472509 272 : 4250, 4027
7266 12:14:48.473130 276 : 4253, 4030
7267 12:14:48.474400 280 : 4250, 4026
7268 12:14:48.474889 284 : 4250, 4027
7269 12:14:48.477423 288 : 4361, 4137
7270 12:14:48.477889 292 : 4250, 4027
7271 12:14:48.478263 296 : 4360, 4137
7272 12:14:48.480927 300 : 4250, 4027
7273 12:14:48.481394 304 : 4250, 4027
7274 12:14:48.484891 308 : 4250, 4026
7275 12:14:48.485454 312 : 4250, 4027
7276 12:14:48.487831 316 : 4250, 4027
7277 12:14:48.488299 320 : 4250, 4027
7278 12:14:48.491477 324 : 4250, 4027
7279 12:14:48.492050 328 : 4255, 4029
7280 12:14:48.494421 332 : 4255, 4029
7281 12:14:48.494943 336 : 4250, 3862
7282 12:14:48.497445 340 : 4361, 1882
7283 12:14:48.498089
7284 12:14:48.498466 MIOCK jitter meter ch=0
7285 12:14:48.498809
7286 12:14:48.500859 1T = (340-100) = 240 dly cells
7287 12:14:48.507893 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7288 12:14:48.508442 ==
7289 12:14:48.511795 Dram Type= 6, Freq= 0, CH_0, rank 0
7290 12:14:48.514194 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7291 12:14:48.514660 ==
7292 12:14:48.522719 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7293 12:14:48.524553 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7294 12:14:48.527460 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7295 12:14:48.535235 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7296 12:14:48.544873 [CA 0] Center 42 (12~73) winsize 62
7297 12:14:48.547363 [CA 1] Center 42 (12~73) winsize 62
7298 12:14:48.550279 [CA 2] Center 39 (9~69) winsize 61
7299 12:14:48.553647 [CA 3] Center 38 (9~68) winsize 60
7300 12:14:48.556687 [CA 4] Center 37 (7~67) winsize 61
7301 12:14:48.560065 [CA 5] Center 36 (6~66) winsize 61
7302 12:14:48.560622
7303 12:14:48.563727 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7304 12:14:48.564362
7305 12:14:48.566719 [CATrainingPosCal] consider 1 rank data
7306 12:14:48.569656 u2DelayCellTimex100 = 271/100 ps
7307 12:14:48.573013 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7308 12:14:48.579938 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7309 12:14:48.583875 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7310 12:14:48.587014 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7311 12:14:48.590093 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7312 12:14:48.593190 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7313 12:14:48.593747
7314 12:14:48.596263 CA PerBit enable=1, Macro0, CA PI delay=36
7315 12:14:48.596869
7316 12:14:48.600243 [CBTSetCACLKResult] CA Dly = 36
7317 12:14:48.602820 CS Dly: 10 (0~41)
7318 12:14:48.606051 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7319 12:14:48.609968 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7320 12:14:48.610432 ==
7321 12:14:48.612613 Dram Type= 6, Freq= 0, CH_0, rank 1
7322 12:14:48.619806 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7323 12:14:48.620366 ==
7324 12:14:48.622212 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7325 12:14:48.625913 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7326 12:14:48.633984 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7327 12:14:48.638923 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7328 12:14:48.647008 [CA 0] Center 42 (12~73) winsize 62
7329 12:14:48.648905 [CA 1] Center 41 (11~72) winsize 62
7330 12:14:48.652660 [CA 2] Center 38 (9~68) winsize 60
7331 12:14:48.656316 [CA 3] Center 37 (7~67) winsize 61
7332 12:14:48.659889 [CA 4] Center 35 (5~65) winsize 61
7333 12:14:48.662013 [CA 5] Center 35 (5~66) winsize 62
7334 12:14:48.662470
7335 12:14:48.665674 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7336 12:14:48.666219
7337 12:14:48.669270 [CATrainingPosCal] consider 2 rank data
7338 12:14:48.671930 u2DelayCellTimex100 = 271/100 ps
7339 12:14:48.679853 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7340 12:14:48.682612 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
7341 12:14:48.685382 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7342 12:14:48.688330 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7343 12:14:48.692142 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7344 12:14:48.695228 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7345 12:14:48.695547
7346 12:14:48.698647 CA PerBit enable=1, Macro0, CA PI delay=36
7347 12:14:48.699057
7348 12:14:48.702085 [CBTSetCACLKResult] CA Dly = 36
7349 12:14:48.705516 CS Dly: 11 (0~43)
7350 12:14:48.708459 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7351 12:14:48.712825 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7352 12:14:48.713145
7353 12:14:48.715079 ----->DramcWriteLeveling(PI) begin...
7354 12:14:48.715568 ==
7355 12:14:48.718607 Dram Type= 6, Freq= 0, CH_0, rank 0
7356 12:14:48.724990 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7357 12:14:48.725455 ==
7358 12:14:48.728528 Write leveling (Byte 0): 30 => 30
7359 12:14:48.729049 Write leveling (Byte 1): 25 => 25
7360 12:14:48.732291 DramcWriteLeveling(PI) end<-----
7361 12:14:48.732904
7362 12:14:48.736520 ==
7363 12:14:48.737031 Dram Type= 6, Freq= 0, CH_0, rank 0
7364 12:14:48.742626 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7365 12:14:48.743182 ==
7366 12:14:48.745185 [Gating] SW mode calibration
7367 12:14:48.752613 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7368 12:14:48.755008 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7369 12:14:48.761687 0 12 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7370 12:14:48.764964 0 12 4 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7371 12:14:48.768173 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7372 12:14:48.775559 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7373 12:14:48.778533 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7374 12:14:48.781691 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7375 12:14:48.788620 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7376 12:14:48.792751 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7377 12:14:48.794738 0 13 0 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
7378 12:14:48.801671 0 13 4 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
7379 12:14:48.805556 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7380 12:14:48.807755 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7381 12:14:48.815215 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7382 12:14:48.817699 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7383 12:14:48.821660 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7384 12:14:48.828820 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7385 12:14:48.831303 0 14 0 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
7386 12:14:48.834930 0 14 4 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
7387 12:14:48.841070 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7388 12:14:48.844078 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7389 12:14:48.848458 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7390 12:14:48.854661 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7391 12:14:48.857330 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7392 12:14:48.861368 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7393 12:14:48.867512 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7394 12:14:48.871023 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7395 12:14:48.874884 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7396 12:14:48.880659 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7397 12:14:48.884570 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7398 12:14:48.887926 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7399 12:14:48.893805 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7400 12:14:48.897088 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7401 12:14:48.901103 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7402 12:14:48.907085 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7403 12:14:48.910670 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7404 12:14:48.913545 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7405 12:14:48.920760 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7406 12:14:48.924094 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7407 12:14:48.926687 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7408 12:14:48.934128 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7409 12:14:48.937426 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7410 12:14:48.940668 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7411 12:14:48.943470 Total UI for P1: 0, mck2ui 16
7412 12:14:48.946849 best dqsien dly found for B0: ( 1, 0, 30)
7413 12:14:48.953802 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7414 12:14:48.954352 Total UI for P1: 0, mck2ui 16
7415 12:14:48.956750 best dqsien dly found for B1: ( 1, 1, 4)
7416 12:14:48.963406 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7417 12:14:48.966696 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7418 12:14:48.967159
7419 12:14:48.970009 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7420 12:14:48.974853 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7421 12:14:48.977265 [Gating] SW calibration Done
7422 12:14:48.977730 ==
7423 12:14:48.979335 Dram Type= 6, Freq= 0, CH_0, rank 0
7424 12:14:48.982886 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7425 12:14:48.983354 ==
7426 12:14:48.986449 RX Vref Scan: 0
7427 12:14:48.987017
7428 12:14:48.987391 RX Vref 0 -> 0, step: 1
7429 12:14:48.987735
7430 12:14:48.989602 RX Delay 0 -> 252, step: 8
7431 12:14:48.992976 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
7432 12:14:48.996198 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7433 12:14:49.003259 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7434 12:14:49.006177 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7435 12:14:49.009430 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7436 12:14:49.013341 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7437 12:14:49.016352 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7438 12:14:49.024093 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7439 12:14:49.026111 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7440 12:14:49.030325 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7441 12:14:49.033325 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7442 12:14:49.036122 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7443 12:14:49.043097 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7444 12:14:49.045953 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7445 12:14:49.049266 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7446 12:14:49.052670 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7447 12:14:49.053274 ==
7448 12:14:49.056700 Dram Type= 6, Freq= 0, CH_0, rank 0
7449 12:14:49.062729 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7450 12:14:49.063275 ==
7451 12:14:49.063665 DQS Delay:
7452 12:14:49.065996 DQS0 = 0, DQS1 = 0
7453 12:14:49.066550 DQM Delay:
7454 12:14:49.068974 DQM0 = 129, DQM1 = 123
7455 12:14:49.069439 DQ Delay:
7456 12:14:49.072694 DQ0 =123, DQ1 =131, DQ2 =123, DQ3 =127
7457 12:14:49.076088 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =139
7458 12:14:49.078786 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
7459 12:14:49.084337 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7460 12:14:49.084933
7461 12:14:49.085309
7462 12:14:49.085655 ==
7463 12:14:49.086875 Dram Type= 6, Freq= 0, CH_0, rank 0
7464 12:14:49.092481 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7465 12:14:49.093151 ==
7466 12:14:49.093535
7467 12:14:49.093882
7468 12:14:49.094213 TX Vref Scan disable
7469 12:14:49.095659 == TX Byte 0 ==
7470 12:14:49.100759 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7471 12:14:49.105406 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7472 12:14:49.105872 == TX Byte 1 ==
7473 12:14:49.108552 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7474 12:14:49.115578 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7475 12:14:49.116121 ==
7476 12:14:49.120394 Dram Type= 6, Freq= 0, CH_0, rank 0
7477 12:14:49.122536 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7478 12:14:49.123003 ==
7479 12:14:49.137251
7480 12:14:49.139699 TX Vref early break, caculate TX vref
7481 12:14:49.142609 TX Vref=16, minBit 9, minWin=22, winSum=368
7482 12:14:49.146256 TX Vref=18, minBit 8, minWin=23, winSum=381
7483 12:14:49.149286 TX Vref=20, minBit 8, minWin=22, winSum=386
7484 12:14:49.152508 TX Vref=22, minBit 8, minWin=23, winSum=395
7485 12:14:49.155863 TX Vref=24, minBit 11, minWin=23, winSum=406
7486 12:14:49.163154 TX Vref=26, minBit 8, minWin=24, winSum=411
7487 12:14:49.165874 TX Vref=28, minBit 3, minWin=25, winSum=413
7488 12:14:49.169012 TX Vref=30, minBit 8, minWin=24, winSum=405
7489 12:14:49.172399 TX Vref=32, minBit 6, minWin=24, winSum=399
7490 12:14:49.175415 TX Vref=34, minBit 1, minWin=24, winSum=393
7491 12:14:49.182268 TX Vref=36, minBit 4, minWin=23, winSum=384
7492 12:14:49.186822 [TxChooseVref] Worse bit 3, Min win 25, Win sum 413, Final Vref 28
7493 12:14:49.187385
7494 12:14:49.188648 Final TX Range 0 Vref 28
7495 12:14:49.189188
7496 12:14:49.189560 ==
7497 12:14:49.192928 Dram Type= 6, Freq= 0, CH_0, rank 0
7498 12:14:49.198354 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7499 12:14:49.199014 ==
7500 12:14:49.199750
7501 12:14:49.200125
7502 12:14:49.200466 TX Vref Scan disable
7503 12:14:49.207168 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7504 12:14:49.207730 == TX Byte 0 ==
7505 12:14:49.208911 u2DelayCellOfst[0]=14 cells (4 PI)
7506 12:14:49.212467 u2DelayCellOfst[1]=18 cells (5 PI)
7507 12:14:49.215760 u2DelayCellOfst[2]=14 cells (4 PI)
7508 12:14:49.218984 u2DelayCellOfst[3]=14 cells (4 PI)
7509 12:14:49.222019 u2DelayCellOfst[4]=7 cells (2 PI)
7510 12:14:49.225338 u2DelayCellOfst[5]=0 cells (0 PI)
7511 12:14:49.228969 u2DelayCellOfst[6]=18 cells (5 PI)
7512 12:14:49.232524 u2DelayCellOfst[7]=18 cells (5 PI)
7513 12:14:49.236240 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7514 12:14:49.238896 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7515 12:14:49.242325 == TX Byte 1 ==
7516 12:14:49.245869 u2DelayCellOfst[8]=3 cells (1 PI)
7517 12:14:49.249165 u2DelayCellOfst[9]=0 cells (0 PI)
7518 12:14:49.252117 u2DelayCellOfst[10]=10 cells (3 PI)
7519 12:14:49.255067 u2DelayCellOfst[11]=3 cells (1 PI)
7520 12:14:49.255628 u2DelayCellOfst[12]=14 cells (4 PI)
7521 12:14:49.259125 u2DelayCellOfst[13]=14 cells (4 PI)
7522 12:14:49.262458 u2DelayCellOfst[14]=21 cells (6 PI)
7523 12:14:49.265627 u2DelayCellOfst[15]=14 cells (4 PI)
7524 12:14:49.272293 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7525 12:14:49.275424 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7526 12:14:49.275891 DramC Write-DBI on
7527 12:14:49.276262 ==
7528 12:14:49.279275 Dram Type= 6, Freq= 0, CH_0, rank 0
7529 12:14:49.285062 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7530 12:14:49.285654 ==
7531 12:14:49.286033
7532 12:14:49.286380
7533 12:14:49.288283 TX Vref Scan disable
7534 12:14:49.288792 == TX Byte 0 ==
7535 12:14:49.294925 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7536 12:14:49.295469 == TX Byte 1 ==
7537 12:14:49.298718 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7538 12:14:49.301980 DramC Write-DBI off
7539 12:14:49.302547
7540 12:14:49.302921 [DATLAT]
7541 12:14:49.304883 Freq=1600, CH0 RK0
7542 12:14:49.305441
7543 12:14:49.305817 DATLAT Default: 0xf
7544 12:14:49.308259 0, 0xFFFF, sum = 0
7545 12:14:49.308896 1, 0xFFFF, sum = 0
7546 12:14:49.312120 2, 0xFFFF, sum = 0
7547 12:14:49.312699 3, 0xFFFF, sum = 0
7548 12:14:49.314908 4, 0xFFFF, sum = 0
7549 12:14:49.315380 5, 0xFFFF, sum = 0
7550 12:14:49.318142 6, 0xFFFF, sum = 0
7551 12:14:49.321206 7, 0xFFFF, sum = 0
7552 12:14:49.321677 8, 0xFFFF, sum = 0
7553 12:14:49.324788 9, 0xFFFF, sum = 0
7554 12:14:49.325260 10, 0xFFFF, sum = 0
7555 12:14:49.327813 11, 0xFFFF, sum = 0
7556 12:14:49.328282 12, 0xFFF, sum = 0
7557 12:14:49.331362 13, 0x0, sum = 1
7558 12:14:49.331948 14, 0x0, sum = 2
7559 12:14:49.334770 15, 0x0, sum = 3
7560 12:14:49.335342 16, 0x0, sum = 4
7561 12:14:49.335721 best_step = 14
7562 12:14:49.337896
7563 12:14:49.338483 ==
7564 12:14:49.342094 Dram Type= 6, Freq= 0, CH_0, rank 0
7565 12:14:49.344094 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7566 12:14:49.344562 ==
7567 12:14:49.344982 RX Vref Scan: 1
7568 12:14:49.345333
7569 12:14:49.347991 Set Vref Range= 24 -> 127
7570 12:14:49.348560
7571 12:14:49.351247 RX Vref 24 -> 127, step: 1
7572 12:14:49.351814
7573 12:14:49.354605 RX Delay 11 -> 252, step: 4
7574 12:14:49.355174
7575 12:14:49.358517 Set Vref, RX VrefLevel [Byte0]: 24
7576 12:14:49.361074 [Byte1]: 24
7577 12:14:49.361540
7578 12:14:49.364601 Set Vref, RX VrefLevel [Byte0]: 25
7579 12:14:49.367367 [Byte1]: 25
7580 12:14:49.367831
7581 12:14:49.371659 Set Vref, RX VrefLevel [Byte0]: 26
7582 12:14:49.374173 [Byte1]: 26
7583 12:14:49.379086
7584 12:14:49.379652 Set Vref, RX VrefLevel [Byte0]: 27
7585 12:14:49.381368 [Byte1]: 27
7586 12:14:49.385867
7587 12:14:49.386434 Set Vref, RX VrefLevel [Byte0]: 28
7588 12:14:49.388643 [Byte1]: 28
7589 12:14:49.393841
7590 12:14:49.394441 Set Vref, RX VrefLevel [Byte0]: 29
7591 12:14:49.396847 [Byte1]: 29
7592 12:14:49.400663
7593 12:14:49.401266 Set Vref, RX VrefLevel [Byte0]: 30
7594 12:14:49.404444 [Byte1]: 30
7595 12:14:49.408345
7596 12:14:49.408866 Set Vref, RX VrefLevel [Byte0]: 31
7597 12:14:49.411542 [Byte1]: 31
7598 12:14:49.416883
7599 12:14:49.417430 Set Vref, RX VrefLevel [Byte0]: 32
7600 12:14:49.419151 [Byte1]: 32
7601 12:14:49.423594
7602 12:14:49.424152 Set Vref, RX VrefLevel [Byte0]: 33
7603 12:14:49.427822 [Byte1]: 33
7604 12:14:49.431058
7605 12:14:49.431670 Set Vref, RX VrefLevel [Byte0]: 34
7606 12:14:49.434927 [Byte1]: 34
7607 12:14:49.438926
7608 12:14:49.439399 Set Vref, RX VrefLevel [Byte0]: 35
7609 12:14:49.442566 [Byte1]: 35
7610 12:14:49.446820
7611 12:14:49.447373 Set Vref, RX VrefLevel [Byte0]: 36
7612 12:14:49.449729 [Byte1]: 36
7613 12:14:49.454663
7614 12:14:49.455221 Set Vref, RX VrefLevel [Byte0]: 37
7615 12:14:49.457969 [Byte1]: 37
7616 12:14:49.461942
7617 12:14:49.462498 Set Vref, RX VrefLevel [Byte0]: 38
7618 12:14:49.465061 [Byte1]: 38
7619 12:14:49.470456
7620 12:14:49.471007 Set Vref, RX VrefLevel [Byte0]: 39
7621 12:14:49.472293 [Byte1]: 39
7622 12:14:49.476837
7623 12:14:49.477296 Set Vref, RX VrefLevel [Byte0]: 40
7624 12:14:49.480353 [Byte1]: 40
7625 12:14:49.484485
7626 12:14:49.485099 Set Vref, RX VrefLevel [Byte0]: 41
7627 12:14:49.488146 [Byte1]: 41
7628 12:14:49.492054
7629 12:14:49.492612 Set Vref, RX VrefLevel [Byte0]: 42
7630 12:14:49.496064 [Byte1]: 42
7631 12:14:49.500362
7632 12:14:49.500967 Set Vref, RX VrefLevel [Byte0]: 43
7633 12:14:49.502974 [Byte1]: 43
7634 12:14:49.507335
7635 12:14:49.507892 Set Vref, RX VrefLevel [Byte0]: 44
7636 12:14:49.510383 [Byte1]: 44
7637 12:14:49.515765
7638 12:14:49.516316 Set Vref, RX VrefLevel [Byte0]: 45
7639 12:14:49.518009 [Byte1]: 45
7640 12:14:49.522488
7641 12:14:49.523038 Set Vref, RX VrefLevel [Byte0]: 46
7642 12:14:49.526217 [Byte1]: 46
7643 12:14:49.530200
7644 12:14:49.530663 Set Vref, RX VrefLevel [Byte0]: 47
7645 12:14:49.533571 [Byte1]: 47
7646 12:14:49.537476
7647 12:14:49.537936 Set Vref, RX VrefLevel [Byte0]: 48
7648 12:14:49.541025 [Byte1]: 48
7649 12:14:49.545388
7650 12:14:49.545844 Set Vref, RX VrefLevel [Byte0]: 49
7651 12:14:49.548847 [Byte1]: 49
7652 12:14:49.553731
7653 12:14:49.554305 Set Vref, RX VrefLevel [Byte0]: 50
7654 12:14:49.556365 [Byte1]: 50
7655 12:14:49.561047
7656 12:14:49.561602 Set Vref, RX VrefLevel [Byte0]: 51
7657 12:14:49.564264 [Byte1]: 51
7658 12:14:49.568604
7659 12:14:49.569128 Set Vref, RX VrefLevel [Byte0]: 52
7660 12:14:49.571520 [Byte1]: 52
7661 12:14:49.575679
7662 12:14:49.576138 Set Vref, RX VrefLevel [Byte0]: 53
7663 12:14:49.579093 [Byte1]: 53
7664 12:14:49.584268
7665 12:14:49.584898 Set Vref, RX VrefLevel [Byte0]: 54
7666 12:14:49.586574 [Byte1]: 54
7667 12:14:49.591559
7668 12:14:49.592116 Set Vref, RX VrefLevel [Byte0]: 55
7669 12:14:49.594355 [Byte1]: 55
7670 12:14:49.599030
7671 12:14:49.599600 Set Vref, RX VrefLevel [Byte0]: 56
7672 12:14:49.602454 [Byte1]: 56
7673 12:14:49.606387
7674 12:14:49.606943 Set Vref, RX VrefLevel [Byte0]: 57
7675 12:14:49.609877 [Byte1]: 57
7676 12:14:49.613999
7677 12:14:49.614459 Set Vref, RX VrefLevel [Byte0]: 58
7678 12:14:49.617593 [Byte1]: 58
7679 12:14:49.621559
7680 12:14:49.622018 Set Vref, RX VrefLevel [Byte0]: 59
7681 12:14:49.624434 [Byte1]: 59
7682 12:14:49.628942
7683 12:14:49.629398 Set Vref, RX VrefLevel [Byte0]: 60
7684 12:14:49.632673 [Byte1]: 60
7685 12:14:49.636996
7686 12:14:49.637548 Set Vref, RX VrefLevel [Byte0]: 61
7687 12:14:49.640055 [Byte1]: 61
7688 12:14:49.644778
7689 12:14:49.645238 Set Vref, RX VrefLevel [Byte0]: 62
7690 12:14:49.648898 [Byte1]: 62
7691 12:14:49.651957
7692 12:14:49.652570 Set Vref, RX VrefLevel [Byte0]: 63
7693 12:14:49.655912 [Byte1]: 63
7694 12:14:49.659714
7695 12:14:49.660339 Set Vref, RX VrefLevel [Byte0]: 64
7696 12:14:49.662801 [Byte1]: 64
7697 12:14:49.667738
7698 12:14:49.668194 Set Vref, RX VrefLevel [Byte0]: 65
7699 12:14:49.670724 [Byte1]: 65
7700 12:14:49.674887
7701 12:14:49.675342 Set Vref, RX VrefLevel [Byte0]: 66
7702 12:14:49.678012 [Byte1]: 66
7703 12:14:49.683140
7704 12:14:49.683714 Set Vref, RX VrefLevel [Byte0]: 67
7705 12:14:49.686125 [Byte1]: 67
7706 12:14:49.691330
7707 12:14:49.691899 Set Vref, RX VrefLevel [Byte0]: 68
7708 12:14:49.693765 [Byte1]: 68
7709 12:14:49.697645
7710 12:14:49.698210 Set Vref, RX VrefLevel [Byte0]: 69
7711 12:14:49.701216 [Byte1]: 69
7712 12:14:49.706123
7713 12:14:49.706701 Set Vref, RX VrefLevel [Byte0]: 70
7714 12:14:49.708347 [Byte1]: 70
7715 12:14:49.712832
7716 12:14:49.713293 Final RX Vref Byte 0 = 53 to rank0
7717 12:14:49.717183 Final RX Vref Byte 1 = 55 to rank0
7718 12:14:49.719859 Final RX Vref Byte 0 = 53 to rank1
7719 12:14:49.723369 Final RX Vref Byte 1 = 55 to rank1==
7720 12:14:49.725844 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 12:14:49.732806 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7722 12:14:49.733266 ==
7723 12:14:49.733632 DQS Delay:
7724 12:14:49.736447 DQS0 = 0, DQS1 = 0
7725 12:14:49.737079 DQM Delay:
7726 12:14:49.737452 DQM0 = 126, DQM1 = 120
7727 12:14:49.739501 DQ Delay:
7728 12:14:49.742925 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7729 12:14:49.745876 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7730 12:14:49.749282 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7731 12:14:49.752981 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7732 12:14:49.753600
7733 12:14:49.754045
7734 12:14:49.754394
7735 12:14:49.755839 [DramC_TX_OE_Calibration] TA2
7736 12:14:49.759587 Original DQ_B0 (3 6) =30, OEN = 27
7737 12:14:49.762388 Original DQ_B1 (3 6) =30, OEN = 27
7738 12:14:49.765371 24, 0x0, End_B0=24 End_B1=24
7739 12:14:49.765837 25, 0x0, End_B0=25 End_B1=25
7740 12:14:49.770115 26, 0x0, End_B0=26 End_B1=26
7741 12:14:49.772401 27, 0x0, End_B0=27 End_B1=27
7742 12:14:49.775749 28, 0x0, End_B0=28 End_B1=28
7743 12:14:49.778811 29, 0x0, End_B0=29 End_B1=29
7744 12:14:49.779331 30, 0x0, End_B0=30 End_B1=30
7745 12:14:49.782008 31, 0x4141, End_B0=30 End_B1=30
7746 12:14:49.785965 Byte0 end_step=30 best_step=27
7747 12:14:49.789244 Byte1 end_step=30 best_step=27
7748 12:14:49.792533 Byte0 TX OE(2T, 0.5T) = (3, 3)
7749 12:14:49.795736 Byte1 TX OE(2T, 0.5T) = (3, 3)
7750 12:14:49.796307
7751 12:14:49.796906
7752 12:14:49.803694 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
7753 12:14:49.805428 CH0 RK0: MR19=303, MR18=1919
7754 12:14:49.812405 CH0_RK0: MR19=0x303, MR18=0x1919, DQSOSC=397, MR23=63, INC=23, DEC=15
7755 12:14:49.813181
7756 12:14:49.815639 ----->DramcWriteLeveling(PI) begin...
7757 12:14:49.816208 ==
7758 12:14:49.818947 Dram Type= 6, Freq= 0, CH_0, rank 1
7759 12:14:49.821907 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7760 12:14:49.822370 ==
7761 12:14:49.825085 Write leveling (Byte 0): 26 => 26
7762 12:14:49.829348 Write leveling (Byte 1): 26 => 26
7763 12:14:49.832159 DramcWriteLeveling(PI) end<-----
7764 12:14:49.832764
7765 12:14:49.833148 ==
7766 12:14:49.835292 Dram Type= 6, Freq= 0, CH_0, rank 1
7767 12:14:49.839237 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7768 12:14:49.839792 ==
7769 12:14:49.841433 [Gating] SW mode calibration
7770 12:14:49.848476 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7771 12:14:49.855013 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7772 12:14:49.858802 0 12 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7773 12:14:49.864799 0 12 4 | B1->B0 | 2b2a 3434 | 1 1 | (0 0) (1 1)
7774 12:14:49.868743 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7775 12:14:49.871806 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7776 12:14:49.878161 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7777 12:14:49.881591 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7778 12:14:49.884817 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7779 12:14:49.891401 0 12 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7780 12:14:49.894945 0 13 0 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
7781 12:14:49.897896 0 13 4 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7782 12:14:49.904334 0 13 8 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
7783 12:14:49.910180 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7784 12:14:49.911103 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7785 12:14:49.917399 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7786 12:14:49.921095 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7787 12:14:49.924302 0 13 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7788 12:14:49.931017 0 14 0 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7789 12:14:49.934352 0 14 4 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
7790 12:14:49.938212 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7791 12:14:49.944260 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7792 12:14:49.948611 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7793 12:14:49.950834 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7794 12:14:49.957373 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7795 12:14:49.961532 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7796 12:14:49.964103 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7797 12:14:49.970733 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7798 12:14:49.974119 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7799 12:14:49.977719 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7800 12:14:49.981265 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7801 12:14:49.987338 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7802 12:14:49.990680 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7803 12:14:49.993916 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7804 12:14:50.000689 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7805 12:14:50.003877 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7806 12:14:50.007519 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7807 12:14:50.013845 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7808 12:14:50.017416 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7809 12:14:50.020618 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7810 12:14:50.026903 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7811 12:14:50.030421 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7812 12:14:50.034137 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7813 12:14:50.041232 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7814 12:14:50.043926 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7815 12:14:50.047142 Total UI for P1: 0, mck2ui 16
7816 12:14:50.051400 best dqsien dly found for B0: ( 1, 1, 0)
7817 12:14:50.053919 Total UI for P1: 0, mck2ui 16
7818 12:14:50.057705 best dqsien dly found for B1: ( 1, 1, 2)
7819 12:14:50.060481 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7820 12:14:50.063680 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7821 12:14:50.064138
7822 12:14:50.067585 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7823 12:14:50.070390 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7824 12:14:50.073610 [Gating] SW calibration Done
7825 12:14:50.074174 ==
7826 12:14:50.076534 Dram Type= 6, Freq= 0, CH_0, rank 1
7827 12:14:50.080152 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7828 12:14:50.084008 ==
7829 12:14:50.084574 RX Vref Scan: 0
7830 12:14:50.084984
7831 12:14:50.087229 RX Vref 0 -> 0, step: 1
7832 12:14:50.087685
7833 12:14:50.090299 RX Delay 0 -> 252, step: 8
7834 12:14:50.093702 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7835 12:14:50.096892 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7836 12:14:50.100882 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7837 12:14:50.103354 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7838 12:14:50.109529 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7839 12:14:50.113704 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7840 12:14:50.116670 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7841 12:14:50.119851 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7842 12:14:50.123108 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7843 12:14:50.129522 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7844 12:14:50.132999 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7845 12:14:50.137137 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7846 12:14:50.139565 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7847 12:14:50.143531 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7848 12:14:50.149020 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
7849 12:14:50.152744 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7850 12:14:50.153307 ==
7851 12:14:50.156112 Dram Type= 6, Freq= 0, CH_0, rank 1
7852 12:14:50.159493 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7853 12:14:50.160050 ==
7854 12:14:50.163329 DQS Delay:
7855 12:14:50.163878 DQS0 = 0, DQS1 = 0
7856 12:14:50.164246 DQM Delay:
7857 12:14:50.166742 DQM0 = 130, DQM1 = 123
7858 12:14:50.167198 DQ Delay:
7859 12:14:50.168811 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7860 12:14:50.172461 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7861 12:14:50.179571 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7862 12:14:50.182608 DQ12 =131, DQ13 =131, DQ14 =131, DQ15 =131
7863 12:14:50.183165
7864 12:14:50.183533
7865 12:14:50.183869 ==
7866 12:14:50.185507 Dram Type= 6, Freq= 0, CH_0, rank 1
7867 12:14:50.188942 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7868 12:14:50.189406 ==
7869 12:14:50.189777
7870 12:14:50.190116
7871 12:14:50.192760 TX Vref Scan disable
7872 12:14:50.196229 == TX Byte 0 ==
7873 12:14:50.198981 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7874 12:14:50.203727 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7875 12:14:50.206201 == TX Byte 1 ==
7876 12:14:50.210248 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7877 12:14:50.212535 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7878 12:14:50.213146 ==
7879 12:14:50.215673 Dram Type= 6, Freq= 0, CH_0, rank 1
7880 12:14:50.219851 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7881 12:14:50.223037 ==
7882 12:14:50.233802
7883 12:14:50.237393 TX Vref early break, caculate TX vref
7884 12:14:50.240886 TX Vref=16, minBit 8, minWin=23, winSum=381
7885 12:14:50.243973 TX Vref=18, minBit 8, minWin=22, winSum=387
7886 12:14:50.247172 TX Vref=20, minBit 10, minWin=23, winSum=397
7887 12:14:50.251082 TX Vref=22, minBit 9, minWin=23, winSum=404
7888 12:14:50.253767 TX Vref=24, minBit 8, minWin=24, winSum=411
7889 12:14:50.260818 TX Vref=26, minBit 7, minWin=25, winSum=415
7890 12:14:50.264455 TX Vref=28, minBit 8, minWin=24, winSum=422
7891 12:14:50.267331 TX Vref=30, minBit 8, minWin=24, winSum=415
7892 12:14:50.270546 TX Vref=32, minBit 8, minWin=23, winSum=403
7893 12:14:50.274875 TX Vref=34, minBit 1, minWin=24, winSum=401
7894 12:14:50.277357 TX Vref=36, minBit 8, minWin=23, winSum=392
7895 12:14:50.284319 [TxChooseVref] Worse bit 7, Min win 25, Win sum 415, Final Vref 26
7896 12:14:50.284933
7897 12:14:50.286848 Final TX Range 0 Vref 26
7898 12:14:50.287309
7899 12:14:50.287673 ==
7900 12:14:50.290234 Dram Type= 6, Freq= 0, CH_0, rank 1
7901 12:14:50.294688 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7902 12:14:50.295255 ==
7903 12:14:50.295624
7904 12:14:50.296758
7905 12:14:50.297216 TX Vref Scan disable
7906 12:14:50.304196 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7907 12:14:50.304817 == TX Byte 0 ==
7908 12:14:50.307047 u2DelayCellOfst[0]=14 cells (4 PI)
7909 12:14:50.310031 u2DelayCellOfst[1]=18 cells (5 PI)
7910 12:14:50.313773 u2DelayCellOfst[2]=14 cells (4 PI)
7911 12:14:50.316593 u2DelayCellOfst[3]=14 cells (4 PI)
7912 12:14:50.320256 u2DelayCellOfst[4]=10 cells (3 PI)
7913 12:14:50.323392 u2DelayCellOfst[5]=0 cells (0 PI)
7914 12:14:50.327552 u2DelayCellOfst[6]=18 cells (5 PI)
7915 12:14:50.330551 u2DelayCellOfst[7]=18 cells (5 PI)
7916 12:14:50.333414 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7917 12:14:50.336741 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7918 12:14:50.339988 == TX Byte 1 ==
7919 12:14:50.343755 u2DelayCellOfst[8]=3 cells (1 PI)
7920 12:14:50.346409 u2DelayCellOfst[9]=0 cells (0 PI)
7921 12:14:50.350342 u2DelayCellOfst[10]=10 cells (3 PI)
7922 12:14:50.353356 u2DelayCellOfst[11]=7 cells (2 PI)
7923 12:14:50.356289 u2DelayCellOfst[12]=18 cells (5 PI)
7924 12:14:50.356905 u2DelayCellOfst[13]=18 cells (5 PI)
7925 12:14:50.359654 u2DelayCellOfst[14]=21 cells (6 PI)
7926 12:14:50.362991 u2DelayCellOfst[15]=18 cells (5 PI)
7927 12:14:50.369968 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7928 12:14:50.373373 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7929 12:14:50.373865 DramC Write-DBI on
7930 12:14:50.375926 ==
7931 12:14:50.379893 Dram Type= 6, Freq= 0, CH_0, rank 1
7932 12:14:50.383335 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7933 12:14:50.383902 ==
7934 12:14:50.384270
7935 12:14:50.384609
7936 12:14:50.385808 TX Vref Scan disable
7937 12:14:50.386270 == TX Byte 0 ==
7938 12:14:50.393423 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7939 12:14:50.393993 == TX Byte 1 ==
7940 12:14:50.396517 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7941 12:14:50.399532 DramC Write-DBI off
7942 12:14:50.400093
7943 12:14:50.400461 [DATLAT]
7944 12:14:50.402327 Freq=1600, CH0 RK1
7945 12:14:50.402788
7946 12:14:50.403158 DATLAT Default: 0xe
7947 12:14:50.405722 0, 0xFFFF, sum = 0
7948 12:14:50.406192 1, 0xFFFF, sum = 0
7949 12:14:50.410003 2, 0xFFFF, sum = 0
7950 12:14:50.410574 3, 0xFFFF, sum = 0
7951 12:14:50.412518 4, 0xFFFF, sum = 0
7952 12:14:50.413012 5, 0xFFFF, sum = 0
7953 12:14:50.415952 6, 0xFFFF, sum = 0
7954 12:14:50.416433 7, 0xFFFF, sum = 0
7955 12:14:50.420227 8, 0xFFFF, sum = 0
7956 12:14:50.423063 9, 0xFFFF, sum = 0
7957 12:14:50.423634 10, 0xFFFF, sum = 0
7958 12:14:50.425972 11, 0xFFFF, sum = 0
7959 12:14:50.426439 12, 0xCFFF, sum = 0
7960 12:14:50.429568 13, 0x0, sum = 1
7961 12:14:50.430033 14, 0x0, sum = 2
7962 12:14:50.432465 15, 0x0, sum = 3
7963 12:14:50.433078 16, 0x0, sum = 4
7964 12:14:50.433491 best_step = 14
7965 12:14:50.433835
7966 12:14:50.437107 ==
7967 12:14:50.439555 Dram Type= 6, Freq= 0, CH_0, rank 1
7968 12:14:50.442506 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7969 12:14:50.443078 ==
7970 12:14:50.443589 RX Vref Scan: 0
7971 12:14:50.444057
7972 12:14:50.445586 RX Vref 0 -> 0, step: 1
7973 12:14:50.446050
7974 12:14:50.449650 RX Delay 11 -> 252, step: 4
7975 12:14:50.452669 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7976 12:14:50.460044 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7977 12:14:50.462720 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7978 12:14:50.465913 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7979 12:14:50.468561 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7980 12:14:50.472100 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7981 12:14:50.478701 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7982 12:14:50.482058 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7983 12:14:50.486077 iDelay=195, Bit 8, Center 106 (51 ~ 162) 112
7984 12:14:50.488674 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7985 12:14:50.492170 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7986 12:14:50.498926 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7987 12:14:50.502270 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7988 12:14:50.505132 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7989 12:14:50.508399 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
7990 12:14:50.511526 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7991 12:14:50.515314 ==
7992 12:14:50.518828 Dram Type= 6, Freq= 0, CH_0, rank 1
7993 12:14:50.522490 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7994 12:14:50.523051 ==
7995 12:14:50.523418 DQS Delay:
7996 12:14:50.524787 DQS0 = 0, DQS1 = 0
7997 12:14:50.525252 DQM Delay:
7998 12:14:50.528469 DQM0 = 128, DQM1 = 120
7999 12:14:50.528977 DQ Delay:
8000 12:14:50.531760 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =122
8001 12:14:50.535141 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138
8002 12:14:50.538938 DQ8 =106, DQ9 =106, DQ10 =122, DQ11 =112
8003 12:14:50.541335 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8004 12:14:50.541799
8005 12:14:50.542167
8006 12:14:50.542510
8007 12:14:50.545226 [DramC_TX_OE_Calibration] TA2
8008 12:14:50.548449 Original DQ_B0 (3 6) =30, OEN = 27
8009 12:14:50.551324 Original DQ_B1 (3 6) =30, OEN = 27
8010 12:14:50.556034 24, 0x0, End_B0=24 End_B1=24
8011 12:14:50.558032 25, 0x0, End_B0=25 End_B1=25
8012 12:14:50.558627 26, 0x0, End_B0=26 End_B1=26
8013 12:14:50.561390 27, 0x0, End_B0=27 End_B1=27
8014 12:14:50.564762 28, 0x0, End_B0=28 End_B1=28
8015 12:14:50.568524 29, 0x0, End_B0=29 End_B1=29
8016 12:14:50.571730 30, 0x0, End_B0=30 End_B1=30
8017 12:14:50.572300 31, 0x4141, End_B0=30 End_B1=30
8018 12:14:50.575512 Byte0 end_step=30 best_step=27
8019 12:14:50.577824 Byte1 end_step=30 best_step=27
8020 12:14:50.581510 Byte0 TX OE(2T, 0.5T) = (3, 3)
8021 12:14:50.584408 Byte1 TX OE(2T, 0.5T) = (3, 3)
8022 12:14:50.584914
8023 12:14:50.585284
8024 12:14:50.591563 [DQSOSCAuto] RK1, (LSB)MR18= 0x2424, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8025 12:14:50.594547 CH0 RK1: MR19=303, MR18=2424
8026 12:14:50.601175 CH0_RK1: MR19=0x303, MR18=0x2424, DQSOSC=391, MR23=63, INC=24, DEC=16
8027 12:14:50.604464 [RxdqsGatingPostProcess] freq 1600
8028 12:14:50.610768 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8029 12:14:50.614685 Pre-setting of DQS Precalculation
8030 12:14:50.617890 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8031 12:14:50.618358 ==
8032 12:14:50.620768 Dram Type= 6, Freq= 0, CH_1, rank 0
8033 12:14:50.624350 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8034 12:14:50.624959 ==
8035 12:14:50.631845 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8036 12:14:50.634894 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8037 12:14:50.641109 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8038 12:14:50.645502 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8039 12:14:50.653312 [CA 0] Center 41 (11~71) winsize 61
8040 12:14:50.656934 [CA 1] Center 40 (10~70) winsize 61
8041 12:14:50.659926 [CA 2] Center 36 (6~66) winsize 61
8042 12:14:50.663372 [CA 3] Center 35 (6~65) winsize 60
8043 12:14:50.666437 [CA 4] Center 33 (4~63) winsize 60
8044 12:14:50.669639 [CA 5] Center 33 (4~63) winsize 60
8045 12:14:50.670115
8046 12:14:50.673481 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8047 12:14:50.673947
8048 12:14:50.676317 [CATrainingPosCal] consider 1 rank data
8049 12:14:50.679564 u2DelayCellTimex100 = 271/100 ps
8050 12:14:50.686422 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8051 12:14:50.690168 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8052 12:14:50.692609 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
8053 12:14:50.697301 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8054 12:14:50.700171 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8055 12:14:50.703162 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8056 12:14:50.703733
8057 12:14:50.706023 CA PerBit enable=1, Macro0, CA PI delay=33
8058 12:14:50.706488
8059 12:14:50.709288 [CBTSetCACLKResult] CA Dly = 33
8060 12:14:50.713085 CS Dly: 9 (0~40)
8061 12:14:50.716291 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8062 12:14:50.719577 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8063 12:14:50.720038 ==
8064 12:14:50.722546 Dram Type= 6, Freq= 0, CH_1, rank 1
8065 12:14:50.729116 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8066 12:14:50.729588 ==
8067 12:14:50.732841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8068 12:14:50.735882 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8069 12:14:50.743295 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8070 12:14:50.749403 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8071 12:14:50.756013 [CA 0] Center 40 (10~70) winsize 61
8072 12:14:50.759039 [CA 1] Center 39 (9~70) winsize 62
8073 12:14:50.763167 [CA 2] Center 35 (6~65) winsize 60
8074 12:14:50.766010 [CA 3] Center 35 (6~64) winsize 59
8075 12:14:50.768971 [CA 4] Center 32 (3~62) winsize 60
8076 12:14:50.772553 [CA 5] Center 33 (4~63) winsize 60
8077 12:14:50.773164
8078 12:14:50.775519 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8079 12:14:50.776249
8080 12:14:50.778703 [CATrainingPosCal] consider 2 rank data
8081 12:14:50.782156 u2DelayCellTimex100 = 271/100 ps
8082 12:14:50.785719 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8083 12:14:50.792949 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8084 12:14:50.796253 CA2 delay=35 (6~65),Diff = 2 PI (7 cell)
8085 12:14:50.799370 CA3 delay=35 (6~64),Diff = 2 PI (7 cell)
8086 12:14:50.802227 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8087 12:14:50.805722 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8088 12:14:50.806188
8089 12:14:50.808884 CA PerBit enable=1, Macro0, CA PI delay=33
8090 12:14:50.809461
8091 12:14:50.812151 [CBTSetCACLKResult] CA Dly = 33
8092 12:14:50.815841 CS Dly: 9 (0~41)
8093 12:14:50.818654 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8094 12:14:50.822443 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8095 12:14:50.822902
8096 12:14:50.825484 ----->DramcWriteLeveling(PI) begin...
8097 12:14:50.825949 ==
8098 12:14:50.829046 Dram Type= 6, Freq= 0, CH_1, rank 0
8099 12:14:50.832197 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8100 12:14:50.835400 ==
8101 12:14:50.835860 Write leveling (Byte 0): 21 => 21
8102 12:14:50.838934 Write leveling (Byte 1): 21 => 21
8103 12:14:50.842347 DramcWriteLeveling(PI) end<-----
8104 12:14:50.842907
8105 12:14:50.843323 ==
8106 12:14:50.845324 Dram Type= 6, Freq= 0, CH_1, rank 0
8107 12:14:50.851446 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8108 12:14:50.851930 ==
8109 12:14:50.855114 [Gating] SW mode calibration
8110 12:14:50.862834 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8111 12:14:50.865385 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8112 12:14:50.871705 0 12 0 | B1->B0 | 2a2a 3434 | 0 1 | (1 1) (1 1)
8113 12:14:50.875253 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8114 12:14:50.878122 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8115 12:14:50.885869 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8116 12:14:50.888108 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8117 12:14:50.891817 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8118 12:14:50.898084 0 12 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8119 12:14:50.902090 0 12 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
8120 12:14:50.905075 0 13 0 | B1->B0 | 3333 2323 | 0 0 | (0 1) (1 0)
8121 12:14:50.911381 0 13 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8122 12:14:50.914828 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8123 12:14:50.918171 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8124 12:14:50.924467 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8125 12:14:50.927766 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8126 12:14:50.931485 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8127 12:14:50.937610 0 13 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8128 12:14:50.941089 0 14 0 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
8129 12:14:50.944474 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8130 12:14:50.951451 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8131 12:14:50.954694 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8132 12:14:50.957928 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8133 12:14:50.961337 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8134 12:14:50.967436 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8135 12:14:50.970589 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8136 12:14:50.977828 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8137 12:14:50.981124 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8138 12:14:50.984507 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 12:14:50.987692 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 12:14:50.994717 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 12:14:50.997887 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 12:14:51.001117 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 12:14:51.007830 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8144 12:14:51.010425 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 12:14:51.017340 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 12:14:51.020836 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 12:14:51.023394 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 12:14:51.027165 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 12:14:51.033655 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 12:14:51.036640 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8151 12:14:51.040466 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8152 12:14:51.046608 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8153 12:14:51.050571 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8154 12:14:51.053618 Total UI for P1: 0, mck2ui 16
8155 12:14:51.056856 best dqsien dly found for B0: ( 1, 0, 28)
8156 12:14:51.059874 Total UI for P1: 0, mck2ui 16
8157 12:14:51.063426 best dqsien dly found for B1: ( 1, 0, 30)
8158 12:14:51.067301 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8159 12:14:51.070663 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8160 12:14:51.071172
8161 12:14:51.073134 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8162 12:14:51.080030 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8163 12:14:51.080510 [Gating] SW calibration Done
8164 12:14:51.080929 ==
8165 12:14:51.083505 Dram Type= 6, Freq= 0, CH_1, rank 0
8166 12:14:51.089848 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8167 12:14:51.090420 ==
8168 12:14:51.090795 RX Vref Scan: 0
8169 12:14:51.091142
8170 12:14:51.092876 RX Vref 0 -> 0, step: 1
8171 12:14:51.093433
8172 12:14:51.096384 RX Delay 0 -> 252, step: 8
8173 12:14:51.100674 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8174 12:14:51.103658 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8175 12:14:51.106824 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8176 12:14:51.112680 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8177 12:14:51.115865 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8178 12:14:51.119371 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8179 12:14:51.122591 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8180 12:14:51.126104 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8181 12:14:51.133064 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8182 12:14:51.136576 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8183 12:14:51.140013 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8184 12:14:51.142925 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8185 12:14:51.145303 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8186 12:14:51.152120 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8187 12:14:51.156220 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8188 12:14:51.158560 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8189 12:14:51.159118 ==
8190 12:14:51.162925 Dram Type= 6, Freq= 0, CH_1, rank 0
8191 12:14:51.166132 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8192 12:14:51.166691 ==
8193 12:14:51.168958 DQS Delay:
8194 12:14:51.169506 DQS0 = 0, DQS1 = 0
8195 12:14:51.173144 DQM Delay:
8196 12:14:51.173705 DQM0 = 129, DQM1 = 126
8197 12:14:51.175909 DQ Delay:
8198 12:14:51.179685 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8199 12:14:51.182102 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8200 12:14:51.185734 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =119
8201 12:14:51.188920 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8202 12:14:51.189477
8203 12:14:51.189843
8204 12:14:51.190187 ==
8205 12:14:51.191770 Dram Type= 6, Freq= 0, CH_1, rank 0
8206 12:14:51.195126 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8207 12:14:51.195678 ==
8208 12:14:51.196059
8209 12:14:51.198712
8210 12:14:51.199262 TX Vref Scan disable
8211 12:14:51.202048 == TX Byte 0 ==
8212 12:14:51.205218 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8213 12:14:51.208377 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8214 12:14:51.211947 == TX Byte 1 ==
8215 12:14:51.215736 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8216 12:14:51.218135 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8217 12:14:51.218607 ==
8218 12:14:51.221625 Dram Type= 6, Freq= 0, CH_1, rank 0
8219 12:14:51.228643 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8220 12:14:51.229293 ==
8221 12:14:51.239544
8222 12:14:51.242974 TX Vref early break, caculate TX vref
8223 12:14:51.246006 TX Vref=16, minBit 3, minWin=21, winSum=376
8224 12:14:51.250995 TX Vref=18, minBit 0, minWin=21, winSum=385
8225 12:14:51.252778 TX Vref=20, minBit 0, minWin=23, winSum=396
8226 12:14:51.255826 TX Vref=22, minBit 1, minWin=23, winSum=400
8227 12:14:51.259700 TX Vref=24, minBit 1, minWin=24, winSum=412
8228 12:14:51.266039 TX Vref=26, minBit 3, minWin=24, winSum=423
8229 12:14:51.269401 TX Vref=28, minBit 3, minWin=24, winSum=422
8230 12:14:51.272804 TX Vref=30, minBit 1, minWin=24, winSum=410
8231 12:14:51.276740 TX Vref=32, minBit 1, minWin=24, winSum=407
8232 12:14:51.278991 TX Vref=34, minBit 1, minWin=23, winSum=397
8233 12:14:51.285887 [TxChooseVref] Worse bit 3, Min win 24, Win sum 423, Final Vref 26
8234 12:14:51.286450
8235 12:14:51.289909 Final TX Range 0 Vref 26
8236 12:14:51.290473
8237 12:14:51.290843 ==
8238 12:14:51.292690 Dram Type= 6, Freq= 0, CH_1, rank 0
8239 12:14:51.295604 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8240 12:14:51.296067 ==
8241 12:14:51.296438
8242 12:14:51.296814
8243 12:14:51.299313 TX Vref Scan disable
8244 12:14:51.305706 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8245 12:14:51.306249 == TX Byte 0 ==
8246 12:14:51.309570 u2DelayCellOfst[0]=18 cells (5 PI)
8247 12:14:51.312745 u2DelayCellOfst[1]=14 cells (4 PI)
8248 12:14:51.315611 u2DelayCellOfst[2]=0 cells (0 PI)
8249 12:14:51.319122 u2DelayCellOfst[3]=7 cells (2 PI)
8250 12:14:51.322751 u2DelayCellOfst[4]=10 cells (3 PI)
8251 12:14:51.325413 u2DelayCellOfst[5]=21 cells (6 PI)
8252 12:14:51.328902 u2DelayCellOfst[6]=18 cells (5 PI)
8253 12:14:51.329380 u2DelayCellOfst[7]=7 cells (2 PI)
8254 12:14:51.335721 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8255 12:14:51.338869 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8256 12:14:51.342526 == TX Byte 1 ==
8257 12:14:51.343106 u2DelayCellOfst[8]=0 cells (0 PI)
8258 12:14:51.345554 u2DelayCellOfst[9]=7 cells (2 PI)
8259 12:14:51.348984 u2DelayCellOfst[10]=10 cells (3 PI)
8260 12:14:51.352314 u2DelayCellOfst[11]=3 cells (1 PI)
8261 12:14:51.355024 u2DelayCellOfst[12]=14 cells (4 PI)
8262 12:14:51.359054 u2DelayCellOfst[13]=18 cells (5 PI)
8263 12:14:51.361970 u2DelayCellOfst[14]=18 cells (5 PI)
8264 12:14:51.365603 u2DelayCellOfst[15]=18 cells (5 PI)
8265 12:14:51.368332 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8266 12:14:51.375384 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8267 12:14:51.375944 DramC Write-DBI on
8268 12:14:51.376314 ==
8269 12:14:51.378425 Dram Type= 6, Freq= 0, CH_1, rank 0
8270 12:14:51.383001 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8271 12:14:51.384970 ==
8272 12:14:51.385436
8273 12:14:51.385806
8274 12:14:51.386149 TX Vref Scan disable
8275 12:14:51.388833 == TX Byte 0 ==
8276 12:14:51.392199 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8277 12:14:51.395758 == TX Byte 1 ==
8278 12:14:51.399082 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8279 12:14:51.402788 DramC Write-DBI off
8280 12:14:51.403345
8281 12:14:51.403713 [DATLAT]
8282 12:14:51.404057 Freq=1600, CH1 RK0
8283 12:14:51.404390
8284 12:14:51.405592 DATLAT Default: 0xf
8285 12:14:51.406058 0, 0xFFFF, sum = 0
8286 12:14:51.409016 1, 0xFFFF, sum = 0
8287 12:14:51.412041 2, 0xFFFF, sum = 0
8288 12:14:51.412510 3, 0xFFFF, sum = 0
8289 12:14:51.415449 4, 0xFFFF, sum = 0
8290 12:14:51.416019 5, 0xFFFF, sum = 0
8291 12:14:51.418552 6, 0xFFFF, sum = 0
8292 12:14:51.419024 7, 0xFFFF, sum = 0
8293 12:14:51.422052 8, 0xFFFF, sum = 0
8294 12:14:51.422682 9, 0xFFFF, sum = 0
8295 12:14:51.425619 10, 0xFFFF, sum = 0
8296 12:14:51.426087 11, 0xFFFF, sum = 0
8297 12:14:51.428630 12, 0x8FFF, sum = 0
8298 12:14:51.429139 13, 0x0, sum = 1
8299 12:14:51.431742 14, 0x0, sum = 2
8300 12:14:51.432210 15, 0x0, sum = 3
8301 12:14:51.434728 16, 0x0, sum = 4
8302 12:14:51.435201 best_step = 14
8303 12:14:51.435569
8304 12:14:51.435913 ==
8305 12:14:51.438228 Dram Type= 6, Freq= 0, CH_1, rank 0
8306 12:14:51.441858 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8307 12:14:51.445174 ==
8308 12:14:51.445730 RX Vref Scan: 1
8309 12:14:51.446102
8310 12:14:51.448683 Set Vref Range= 24 -> 127
8311 12:14:51.449229
8312 12:14:51.451486 RX Vref 24 -> 127, step: 1
8313 12:14:51.451946
8314 12:14:51.452416 RX Delay 3 -> 252, step: 4
8315 12:14:51.452813
8316 12:14:51.456008 Set Vref, RX VrefLevel [Byte0]: 24
8317 12:14:51.458795 [Byte1]: 24
8318 12:14:51.461914
8319 12:14:51.462379 Set Vref, RX VrefLevel [Byte0]: 25
8320 12:14:51.465117 [Byte1]: 25
8321 12:14:51.469461
8322 12:14:51.470029 Set Vref, RX VrefLevel [Byte0]: 26
8323 12:14:51.472843 [Byte1]: 26
8324 12:14:51.477695
8325 12:14:51.478249 Set Vref, RX VrefLevel [Byte0]: 27
8326 12:14:51.481124 [Byte1]: 27
8327 12:14:51.484936
8328 12:14:51.485486 Set Vref, RX VrefLevel [Byte0]: 28
8329 12:14:51.488572 [Byte1]: 28
8330 12:14:51.492524
8331 12:14:51.493015 Set Vref, RX VrefLevel [Byte0]: 29
8332 12:14:51.495808 [Byte1]: 29
8333 12:14:51.499956
8334 12:14:51.500410 Set Vref, RX VrefLevel [Byte0]: 30
8335 12:14:51.504307 [Byte1]: 30
8336 12:14:51.507772
8337 12:14:51.508242 Set Vref, RX VrefLevel [Byte0]: 31
8338 12:14:51.511162 [Byte1]: 31
8339 12:14:51.515458
8340 12:14:51.515876 Set Vref, RX VrefLevel [Byte0]: 32
8341 12:14:51.519069 [Byte1]: 32
8342 12:14:51.523587
8343 12:14:51.524100 Set Vref, RX VrefLevel [Byte0]: 33
8344 12:14:51.527433 [Byte1]: 33
8345 12:14:51.530741
8346 12:14:51.531066 Set Vref, RX VrefLevel [Byte0]: 34
8347 12:14:51.533943 [Byte1]: 34
8348 12:14:51.538685
8349 12:14:51.539140 Set Vref, RX VrefLevel [Byte0]: 35
8350 12:14:51.542049 [Byte1]: 35
8351 12:14:51.547204
8352 12:14:51.547761 Set Vref, RX VrefLevel [Byte0]: 36
8353 12:14:51.550043 [Byte1]: 36
8354 12:14:51.554251
8355 12:14:51.554812 Set Vref, RX VrefLevel [Byte0]: 37
8356 12:14:51.557076 [Byte1]: 37
8357 12:14:51.562245
8358 12:14:51.562839 Set Vref, RX VrefLevel [Byte0]: 38
8359 12:14:51.565365 [Byte1]: 38
8360 12:14:51.569312
8361 12:14:51.569830 Set Vref, RX VrefLevel [Byte0]: 39
8362 12:14:51.572632 [Byte1]: 39
8363 12:14:51.576928
8364 12:14:51.577488 Set Vref, RX VrefLevel [Byte0]: 40
8365 12:14:51.579797 [Byte1]: 40
8366 12:14:51.584665
8367 12:14:51.585262 Set Vref, RX VrefLevel [Byte0]: 41
8368 12:14:51.587522 [Byte1]: 41
8369 12:14:51.592491
8370 12:14:51.593090 Set Vref, RX VrefLevel [Byte0]: 42
8371 12:14:51.595427 [Byte1]: 42
8372 12:14:51.599757
8373 12:14:51.600307 Set Vref, RX VrefLevel [Byte0]: 43
8374 12:14:51.603002 [Byte1]: 43
8375 12:14:51.607526
8376 12:14:51.608081 Set Vref, RX VrefLevel [Byte0]: 44
8377 12:14:51.611000 [Byte1]: 44
8378 12:14:51.615401
8379 12:14:51.615852 Set Vref, RX VrefLevel [Byte0]: 45
8380 12:14:51.618228 [Byte1]: 45
8381 12:14:51.622714
8382 12:14:51.623284 Set Vref, RX VrefLevel [Byte0]: 46
8383 12:14:51.626645 [Byte1]: 46
8384 12:14:51.630467
8385 12:14:51.630923 Set Vref, RX VrefLevel [Byte0]: 47
8386 12:14:51.634142 [Byte1]: 47
8387 12:14:51.639162
8388 12:14:51.639712 Set Vref, RX VrefLevel [Byte0]: 48
8389 12:14:51.641975 [Byte1]: 48
8390 12:14:51.645670
8391 12:14:51.646221 Set Vref, RX VrefLevel [Byte0]: 49
8392 12:14:51.649641 [Byte1]: 49
8393 12:14:51.653440
8394 12:14:51.653990 Set Vref, RX VrefLevel [Byte0]: 50
8395 12:14:51.657269 [Byte1]: 50
8396 12:14:51.660986
8397 12:14:51.661534 Set Vref, RX VrefLevel [Byte0]: 51
8398 12:14:51.664559 [Byte1]: 51
8399 12:14:51.668415
8400 12:14:51.668909 Set Vref, RX VrefLevel [Byte0]: 52
8401 12:14:51.672337 [Byte1]: 52
8402 12:14:51.676439
8403 12:14:51.677050 Set Vref, RX VrefLevel [Byte0]: 53
8404 12:14:51.679639 [Byte1]: 53
8405 12:14:51.685216
8406 12:14:51.685676 Set Vref, RX VrefLevel [Byte0]: 54
8407 12:14:51.687527 [Byte1]: 54
8408 12:14:51.693139
8409 12:14:51.693595 Set Vref, RX VrefLevel [Byte0]: 55
8410 12:14:51.694597 [Byte1]: 55
8411 12:14:51.699580
8412 12:14:51.700131 Set Vref, RX VrefLevel [Byte0]: 56
8413 12:14:51.702742 [Byte1]: 56
8414 12:14:51.707844
8415 12:14:51.708397 Set Vref, RX VrefLevel [Byte0]: 57
8416 12:14:51.710844 [Byte1]: 57
8417 12:14:51.715518
8418 12:14:51.716070 Set Vref, RX VrefLevel [Byte0]: 58
8419 12:14:51.718113 [Byte1]: 58
8420 12:14:51.721987
8421 12:14:51.722540 Set Vref, RX VrefLevel [Byte0]: 59
8422 12:14:51.725281 [Byte1]: 59
8423 12:14:51.730121
8424 12:14:51.730753 Set Vref, RX VrefLevel [Byte0]: 60
8425 12:14:51.733043 [Byte1]: 60
8426 12:14:51.737727
8427 12:14:51.738280 Set Vref, RX VrefLevel [Byte0]: 61
8428 12:14:51.741081 [Byte1]: 61
8429 12:14:51.745651
8430 12:14:51.746202 Set Vref, RX VrefLevel [Byte0]: 62
8431 12:14:51.748616 [Byte1]: 62
8432 12:14:51.753158
8433 12:14:51.753712 Set Vref, RX VrefLevel [Byte0]: 63
8434 12:14:51.756366 [Byte1]: 63
8435 12:14:51.760694
8436 12:14:51.761295 Set Vref, RX VrefLevel [Byte0]: 64
8437 12:14:51.763796 [Byte1]: 64
8438 12:14:51.768045
8439 12:14:51.768601 Set Vref, RX VrefLevel [Byte0]: 65
8440 12:14:51.771563 [Byte1]: 65
8441 12:14:51.776212
8442 12:14:51.776811 Set Vref, RX VrefLevel [Byte0]: 66
8443 12:14:51.779692 [Byte1]: 66
8444 12:14:51.783168
8445 12:14:51.783636 Set Vref, RX VrefLevel [Byte0]: 67
8446 12:14:51.786837 [Byte1]: 67
8447 12:14:51.792787
8448 12:14:51.793354 Set Vref, RX VrefLevel [Byte0]: 68
8449 12:14:51.794498 [Byte1]: 68
8450 12:14:51.798549
8451 12:14:51.799121 Set Vref, RX VrefLevel [Byte0]: 69
8452 12:14:51.801702 [Byte1]: 69
8453 12:14:51.807251
8454 12:14:51.807874 Set Vref, RX VrefLevel [Byte0]: 70
8455 12:14:51.809718 [Byte1]: 70
8456 12:14:51.813989
8457 12:14:51.814560 Set Vref, RX VrefLevel [Byte0]: 71
8458 12:14:51.817052 [Byte1]: 71
8459 12:14:51.821575
8460 12:14:51.822038 Set Vref, RX VrefLevel [Byte0]: 72
8461 12:14:51.825299 [Byte1]: 72
8462 12:14:51.829249
8463 12:14:51.829726 Set Vref, RX VrefLevel [Byte0]: 73
8464 12:14:51.832171 [Byte1]: 73
8465 12:14:51.836512
8466 12:14:51.837004 Set Vref, RX VrefLevel [Byte0]: 74
8467 12:14:51.840288 [Byte1]: 74
8468 12:14:51.844533
8469 12:14:51.845140 Set Vref, RX VrefLevel [Byte0]: 75
8470 12:14:51.848171 [Byte1]: 75
8471 12:14:51.852352
8472 12:14:51.852856 Final RX Vref Byte 0 = 61 to rank0
8473 12:14:51.855245 Final RX Vref Byte 1 = 51 to rank0
8474 12:14:51.859148 Final RX Vref Byte 0 = 61 to rank1
8475 12:14:51.862431 Final RX Vref Byte 1 = 51 to rank1==
8476 12:14:51.865316 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 12:14:51.871903 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8478 12:14:51.872370 ==
8479 12:14:51.872791 DQS Delay:
8480 12:14:51.873155 DQS0 = 0, DQS1 = 0
8481 12:14:51.875534 DQM Delay:
8482 12:14:51.876033 DQM0 = 128, DQM1 = 124
8483 12:14:51.879449 DQ Delay:
8484 12:14:51.882773 DQ0 =134, DQ1 =124, DQ2 =116, DQ3 =126
8485 12:14:51.885628 DQ4 =128, DQ5 =138, DQ6 =138, DQ7 =126
8486 12:14:51.888672 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8487 12:14:51.892338 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8488 12:14:51.892837
8489 12:14:51.893206
8490 12:14:51.893542
8491 12:14:51.895505 [DramC_TX_OE_Calibration] TA2
8492 12:14:51.898508 Original DQ_B0 (3 6) =30, OEN = 27
8493 12:14:51.903356 Original DQ_B1 (3 6) =30, OEN = 27
8494 12:14:51.905362 24, 0x0, End_B0=24 End_B1=24
8495 12:14:51.905833 25, 0x0, End_B0=25 End_B1=25
8496 12:14:51.908315 26, 0x0, End_B0=26 End_B1=26
8497 12:14:51.912265 27, 0x0, End_B0=27 End_B1=27
8498 12:14:51.915530 28, 0x0, End_B0=28 End_B1=28
8499 12:14:51.918563 29, 0x0, End_B0=29 End_B1=29
8500 12:14:51.919133 30, 0x0, End_B0=30 End_B1=30
8501 12:14:51.922734 31, 0x4545, End_B0=30 End_B1=30
8502 12:14:51.925311 Byte0 end_step=30 best_step=27
8503 12:14:51.928394 Byte1 end_step=30 best_step=27
8504 12:14:51.932682 Byte0 TX OE(2T, 0.5T) = (3, 3)
8505 12:14:51.934871 Byte1 TX OE(2T, 0.5T) = (3, 3)
8506 12:14:51.935328
8507 12:14:51.935693
8508 12:14:51.942015 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8509 12:14:51.945348 CH1 RK0: MR19=303, MR18=2525
8510 12:14:51.951643 CH1_RK0: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
8511 12:14:51.952177
8512 12:14:51.955318 ----->DramcWriteLeveling(PI) begin...
8513 12:14:51.955952 ==
8514 12:14:51.958137 Dram Type= 6, Freq= 0, CH_1, rank 1
8515 12:14:51.962199 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8516 12:14:51.962764 ==
8517 12:14:51.965155 Write leveling (Byte 0): 23 => 23
8518 12:14:51.968636 Write leveling (Byte 1): 21 => 21
8519 12:14:51.971307 DramcWriteLeveling(PI) end<-----
8520 12:14:51.971766
8521 12:14:51.972132 ==
8522 12:14:51.975355 Dram Type= 6, Freq= 0, CH_1, rank 1
8523 12:14:51.978868 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8524 12:14:51.979472 ==
8525 12:14:51.981555 [Gating] SW mode calibration
8526 12:14:51.989227 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8527 12:14:51.994331 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8528 12:14:51.998499 0 12 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8529 12:14:52.004860 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8530 12:14:52.007986 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8531 12:14:52.011517 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8532 12:14:52.018218 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8533 12:14:52.021332 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8534 12:14:52.024261 0 12 24 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8535 12:14:52.031100 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8536 12:14:52.034642 0 13 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8537 12:14:52.038001 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8538 12:14:52.040926 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8539 12:14:52.048090 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8540 12:14:52.051310 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8541 12:14:52.054422 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8542 12:14:52.061336 0 13 24 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
8543 12:14:52.064610 0 13 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
8544 12:14:52.067552 0 14 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8545 12:14:52.074716 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8546 12:14:52.077336 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8547 12:14:52.080699 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8548 12:14:52.087665 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8549 12:14:52.090488 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8550 12:14:52.094025 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8551 12:14:52.100838 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8552 12:14:52.103955 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8553 12:14:52.107559 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8554 12:14:52.113578 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8555 12:14:52.117119 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8556 12:14:52.120928 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8557 12:14:52.126886 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8558 12:14:52.130756 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8559 12:14:52.133485 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8560 12:14:52.140035 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8561 12:14:52.143448 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8562 12:14:52.147625 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8563 12:14:52.152912 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8564 12:14:52.156618 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8565 12:14:52.159783 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8566 12:14:52.166124 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8567 12:14:52.169525 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8568 12:14:52.174423 Total UI for P1: 0, mck2ui 16
8569 12:14:52.176374 best dqsien dly found for B0: ( 1, 0, 24)
8570 12:14:52.180104 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8571 12:14:52.186352 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8572 12:14:52.189827 Total UI for P1: 0, mck2ui 16
8573 12:14:52.193002 best dqsien dly found for B1: ( 1, 0, 30)
8574 12:14:52.196507 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8575 12:14:52.199922 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8576 12:14:52.200475
8577 12:14:52.203263 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8578 12:14:52.206212 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8579 12:14:52.209673 [Gating] SW calibration Done
8580 12:14:52.210313 ==
8581 12:14:52.212745 Dram Type= 6, Freq= 0, CH_1, rank 1
8582 12:14:52.216282 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8583 12:14:52.216879 ==
8584 12:14:52.219529 RX Vref Scan: 0
8585 12:14:52.219991
8586 12:14:52.220358 RX Vref 0 -> 0, step: 1
8587 12:14:52.222592
8588 12:14:52.223051 RX Delay 0 -> 252, step: 8
8589 12:14:52.229228 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8590 12:14:52.232638 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8591 12:14:52.236299 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8592 12:14:52.240043 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8593 12:14:52.242959 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8594 12:14:52.249793 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8595 12:14:52.252521 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8596 12:14:52.256099 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8597 12:14:52.260841 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8598 12:14:52.262955 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8599 12:14:52.268962 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8600 12:14:52.272109 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8601 12:14:52.275812 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8602 12:14:52.278996 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8603 12:14:52.281891 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8604 12:14:52.288782 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8605 12:14:52.289246 ==
8606 12:14:52.292699 Dram Type= 6, Freq= 0, CH_1, rank 1
8607 12:14:52.295811 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8608 12:14:52.296367 ==
8609 12:14:52.296777 DQS Delay:
8610 12:14:52.299046 DQS0 = 0, DQS1 = 0
8611 12:14:52.299603 DQM Delay:
8612 12:14:52.302586 DQM0 = 131, DQM1 = 125
8613 12:14:52.303140 DQ Delay:
8614 12:14:52.306148 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8615 12:14:52.308742 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8616 12:14:52.312484 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8617 12:14:52.315495 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8618 12:14:52.315955
8619 12:14:52.316317
8620 12:14:52.319254 ==
8621 12:14:52.322724 Dram Type= 6, Freq= 0, CH_1, rank 1
8622 12:14:52.325286 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8623 12:14:52.325843 ==
8624 12:14:52.326226
8625 12:14:52.326570
8626 12:14:52.328553 TX Vref Scan disable
8627 12:14:52.329149 == TX Byte 0 ==
8628 12:14:52.335560 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8629 12:14:52.339783 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8630 12:14:52.340339 == TX Byte 1 ==
8631 12:14:52.342270 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8632 12:14:52.349023 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8633 12:14:52.349578 ==
8634 12:14:52.352162 Dram Type= 6, Freq= 0, CH_1, rank 1
8635 12:14:52.355350 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8636 12:14:52.355907 ==
8637 12:14:52.369048
8638 12:14:52.372671 TX Vref early break, caculate TX vref
8639 12:14:52.376027 TX Vref=16, minBit 0, minWin=21, winSum=383
8640 12:14:52.379698 TX Vref=18, minBit 0, minWin=23, winSum=393
8641 12:14:52.382889 TX Vref=20, minBit 2, minWin=23, winSum=400
8642 12:14:52.386256 TX Vref=22, minBit 0, minWin=24, winSum=407
8643 12:14:52.389074 TX Vref=24, minBit 5, minWin=24, winSum=417
8644 12:14:52.395648 TX Vref=26, minBit 0, minWin=25, winSum=424
8645 12:14:52.399116 TX Vref=28, minBit 0, minWin=24, winSum=426
8646 12:14:52.402227 TX Vref=30, minBit 0, minWin=24, winSum=417
8647 12:14:52.405632 TX Vref=32, minBit 0, minWin=23, winSum=410
8648 12:14:52.408906 TX Vref=34, minBit 0, minWin=23, winSum=405
8649 12:14:52.412637 TX Vref=36, minBit 0, minWin=21, winSum=393
8650 12:14:52.418812 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 26
8651 12:14:52.419470
8652 12:14:52.422231 Final TX Range 0 Vref 26
8653 12:14:52.422694
8654 12:14:52.423134 ==
8655 12:14:52.425389 Dram Type= 6, Freq= 0, CH_1, rank 1
8656 12:14:52.428577 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8657 12:14:52.429474 ==
8658 12:14:52.431734
8659 12:14:52.432272
8660 12:14:52.432667 TX Vref Scan disable
8661 12:14:52.438843 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8662 12:14:52.439401 == TX Byte 0 ==
8663 12:14:52.441980 u2DelayCellOfst[0]=14 cells (4 PI)
8664 12:14:52.445106 u2DelayCellOfst[1]=10 cells (3 PI)
8665 12:14:52.448972 u2DelayCellOfst[2]=0 cells (0 PI)
8666 12:14:52.452369 u2DelayCellOfst[3]=7 cells (2 PI)
8667 12:14:52.455025 u2DelayCellOfst[4]=7 cells (2 PI)
8668 12:14:52.459500 u2DelayCellOfst[5]=14 cells (4 PI)
8669 12:14:52.461891 u2DelayCellOfst[6]=14 cells (4 PI)
8670 12:14:52.466270 u2DelayCellOfst[7]=3 cells (1 PI)
8671 12:14:52.468776 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8672 12:14:52.471743 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8673 12:14:52.475097 == TX Byte 1 ==
8674 12:14:52.478958 u2DelayCellOfst[8]=0 cells (0 PI)
8675 12:14:52.481575 u2DelayCellOfst[9]=3 cells (1 PI)
8676 12:14:52.485755 u2DelayCellOfst[10]=7 cells (2 PI)
8677 12:14:52.486310 u2DelayCellOfst[11]=3 cells (1 PI)
8678 12:14:52.488739 u2DelayCellOfst[12]=14 cells (4 PI)
8679 12:14:52.491953 u2DelayCellOfst[13]=18 cells (5 PI)
8680 12:14:52.494822 u2DelayCellOfst[14]=14 cells (4 PI)
8681 12:14:52.498741 u2DelayCellOfst[15]=14 cells (4 PI)
8682 12:14:52.505199 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8683 12:14:52.508262 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8684 12:14:52.508855 DramC Write-DBI on
8685 12:14:52.511598 ==
8686 12:14:52.512167 Dram Type= 6, Freq= 0, CH_1, rank 1
8687 12:14:52.517755 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8688 12:14:52.518301 ==
8689 12:14:52.518671
8690 12:14:52.519014
8691 12:14:52.521565 TX Vref Scan disable
8692 12:14:52.522129 == TX Byte 0 ==
8693 12:14:52.528743 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8694 12:14:52.529295 == TX Byte 1 ==
8695 12:14:52.531197 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8696 12:14:52.534512 DramC Write-DBI off
8697 12:14:52.535071
8698 12:14:52.535487 [DATLAT]
8699 12:14:52.538064 Freq=1600, CH1 RK1
8700 12:14:52.538632
8701 12:14:52.538996 DATLAT Default: 0xe
8702 12:14:52.541456 0, 0xFFFF, sum = 0
8703 12:14:52.541920 1, 0xFFFF, sum = 0
8704 12:14:52.544242 2, 0xFFFF, sum = 0
8705 12:14:52.544702 3, 0xFFFF, sum = 0
8706 12:14:52.548277 4, 0xFFFF, sum = 0
8707 12:14:52.548906 5, 0xFFFF, sum = 0
8708 12:14:52.552182 6, 0xFFFF, sum = 0
8709 12:14:52.552862 7, 0xFFFF, sum = 0
8710 12:14:52.554744 8, 0xFFFF, sum = 0
8711 12:14:52.555206 9, 0xFFFF, sum = 0
8712 12:14:52.558067 10, 0xFFFF, sum = 0
8713 12:14:52.561114 11, 0xFFFF, sum = 0
8714 12:14:52.561581 12, 0xF7F, sum = 0
8715 12:14:52.561950 13, 0x0, sum = 1
8716 12:14:52.564802 14, 0x0, sum = 2
8717 12:14:52.565387 15, 0x0, sum = 3
8718 12:14:52.567997 16, 0x0, sum = 4
8719 12:14:52.568552 best_step = 14
8720 12:14:52.568985
8721 12:14:52.569326 ==
8722 12:14:52.571540 Dram Type= 6, Freq= 0, CH_1, rank 1
8723 12:14:52.577597 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8724 12:14:52.578111 ==
8725 12:14:52.578481 RX Vref Scan: 0
8726 12:14:52.578819
8727 12:14:52.581051 RX Vref 0 -> 0, step: 1
8728 12:14:52.581525
8729 12:14:52.584283 RX Delay 3 -> 252, step: 4
8730 12:14:52.588247 iDelay=195, Bit 0, Center 130 (79 ~ 182) 104
8731 12:14:52.591333 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8732 12:14:52.597785 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8733 12:14:52.601568 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8734 12:14:52.604617 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8735 12:14:52.608191 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8736 12:14:52.610985 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8737 12:14:52.617386 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8738 12:14:52.621058 iDelay=195, Bit 8, Center 106 (51 ~ 162) 112
8739 12:14:52.623822 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8740 12:14:52.627195 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8741 12:14:52.630617 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8742 12:14:52.637241 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8743 12:14:52.640859 iDelay=195, Bit 13, Center 130 (79 ~ 182) 104
8744 12:14:52.644043 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8745 12:14:52.647293 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8746 12:14:52.647844 ==
8747 12:14:52.650756 Dram Type= 6, Freq= 0, CH_1, rank 1
8748 12:14:52.656973 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8749 12:14:52.657543 ==
8750 12:14:52.657911 DQS Delay:
8751 12:14:52.660361 DQS0 = 0, DQS1 = 0
8752 12:14:52.660859 DQM Delay:
8753 12:14:52.663626 DQM0 = 127, DQM1 = 122
8754 12:14:52.664174 DQ Delay:
8755 12:14:52.666818 DQ0 =130, DQ1 =122, DQ2 =116, DQ3 =124
8756 12:14:52.670228 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8757 12:14:52.674438 DQ8 =106, DQ9 =110, DQ10 =122, DQ11 =114
8758 12:14:52.677104 DQ12 =132, DQ13 =130, DQ14 =134, DQ15 =132
8759 12:14:52.677562
8760 12:14:52.677923
8761 12:14:52.678259
8762 12:14:52.680055 [DramC_TX_OE_Calibration] TA2
8763 12:14:52.683616 Original DQ_B0 (3 6) =30, OEN = 27
8764 12:14:52.686996 Original DQ_B1 (3 6) =30, OEN = 27
8765 12:14:52.690775 24, 0x0, End_B0=24 End_B1=24
8766 12:14:52.693508 25, 0x0, End_B0=25 End_B1=25
8767 12:14:52.693971 26, 0x0, End_B0=26 End_B1=26
8768 12:14:52.697803 27, 0x0, End_B0=27 End_B1=27
8769 12:14:52.700098 28, 0x0, End_B0=28 End_B1=28
8770 12:14:52.703684 29, 0x0, End_B0=29 End_B1=29
8771 12:14:52.704248 30, 0x0, End_B0=30 End_B1=30
8772 12:14:52.706729 31, 0x4141, End_B0=30 End_B1=30
8773 12:14:52.709521 Byte0 end_step=30 best_step=27
8774 12:14:52.713461 Byte1 end_step=30 best_step=27
8775 12:14:52.717217 Byte0 TX OE(2T, 0.5T) = (3, 3)
8776 12:14:52.720050 Byte1 TX OE(2T, 0.5T) = (3, 3)
8777 12:14:52.720605
8778 12:14:52.721011
8779 12:14:52.726035 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8780 12:14:52.729941 CH1 RK1: MR19=303, MR18=1C1C
8781 12:14:52.736186 CH1_RK1: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8782 12:14:52.739407 [RxdqsGatingPostProcess] freq 1600
8783 12:14:52.743014 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8784 12:14:52.746899 Pre-setting of DQS Precalculation
8785 12:14:52.753656 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8786 12:14:52.760107 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8787 12:14:52.766303 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8788 12:14:52.766866
8789 12:14:52.767233
8790 12:14:52.769321 [Calibration Summary] 3200 Mbps
8791 12:14:52.772861 CH 0, Rank 0
8792 12:14:52.773318 SW Impedance : PASS
8793 12:14:52.776241 DUTY Scan : NO K
8794 12:14:52.779651 ZQ Calibration : PASS
8795 12:14:52.780228 Jitter Meter : NO K
8796 12:14:52.782759 CBT Training : PASS
8797 12:14:52.783262 Write leveling : PASS
8798 12:14:52.785809 RX DQS gating : PASS
8799 12:14:52.789514 RX DQ/DQS(RDDQC) : PASS
8800 12:14:52.789970 TX DQ/DQS : PASS
8801 12:14:52.792808 RX DATLAT : PASS
8802 12:14:52.796498 RX DQ/DQS(Engine): PASS
8803 12:14:52.797099 TX OE : PASS
8804 12:14:52.799469 All Pass.
8805 12:14:52.800024
8806 12:14:52.800385 CH 0, Rank 1
8807 12:14:52.802705 SW Impedance : PASS
8808 12:14:52.803163 DUTY Scan : NO K
8809 12:14:52.807615 ZQ Calibration : PASS
8810 12:14:52.809816 Jitter Meter : NO K
8811 12:14:52.810295 CBT Training : PASS
8812 12:14:52.812928 Write leveling : PASS
8813 12:14:52.816883 RX DQS gating : PASS
8814 12:14:52.817441 RX DQ/DQS(RDDQC) : PASS
8815 12:14:52.819686 TX DQ/DQS : PASS
8816 12:14:52.822655 RX DATLAT : PASS
8817 12:14:52.823212 RX DQ/DQS(Engine): PASS
8818 12:14:52.826366 TX OE : PASS
8819 12:14:52.826847 All Pass.
8820 12:14:52.827213
8821 12:14:52.829298 CH 1, Rank 0
8822 12:14:52.829756 SW Impedance : PASS
8823 12:14:52.832188 DUTY Scan : NO K
8824 12:14:52.835670 ZQ Calibration : PASS
8825 12:14:52.836234 Jitter Meter : NO K
8826 12:14:52.839327 CBT Training : PASS
8827 12:14:52.842445 Write leveling : PASS
8828 12:14:52.843003 RX DQS gating : PASS
8829 12:14:52.846004 RX DQ/DQS(RDDQC) : PASS
8830 12:14:52.846555 TX DQ/DQS : PASS
8831 12:14:52.849301 RX DATLAT : PASS
8832 12:14:52.853003 RX DQ/DQS(Engine): PASS
8833 12:14:52.853555 TX OE : PASS
8834 12:14:52.855888 All Pass.
8835 12:14:52.856435
8836 12:14:52.856866 CH 1, Rank 1
8837 12:14:52.859096 SW Impedance : PASS
8838 12:14:52.859649 DUTY Scan : NO K
8839 12:14:52.862253 ZQ Calibration : PASS
8840 12:14:52.865337 Jitter Meter : NO K
8841 12:14:52.865888 CBT Training : PASS
8842 12:14:52.868930 Write leveling : PASS
8843 12:14:52.872536 RX DQS gating : PASS
8844 12:14:52.873042 RX DQ/DQS(RDDQC) : PASS
8845 12:14:52.875350 TX DQ/DQS : PASS
8846 12:14:52.878723 RX DATLAT : PASS
8847 12:14:52.879276 RX DQ/DQS(Engine): PASS
8848 12:14:52.881735 TX OE : PASS
8849 12:14:52.882191 All Pass.
8850 12:14:52.882555
8851 12:14:52.885068 DramC Write-DBI on
8852 12:14:52.888846 PER_BANK_REFRESH: Hybrid Mode
8853 12:14:52.889405 TX_TRACKING: ON
8854 12:14:52.898320 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8855 12:14:52.905259 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8856 12:14:52.911380 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8857 12:14:52.918560 [FAST_K] Save calibration result to emmc
8858 12:14:52.919125 sync common calibartion params.
8859 12:14:52.921276 sync cbt_mode0:0, 1:0
8860 12:14:52.925341 dram_init: ddr_geometry: 0
8861 12:14:52.925905 dram_init: ddr_geometry: 0
8862 12:14:52.928850 dram_init: ddr_geometry: 0
8863 12:14:52.931425 0:dram_rank_size:80000000
8864 12:14:52.934143 1:dram_rank_size:80000000
8865 12:14:52.937917 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8866 12:14:52.941343 DFS_SHUFFLE_HW_MODE: ON
8867 12:14:52.944383 dramc_set_vcore_voltage set vcore to 725000
8868 12:14:52.947464 Read voltage for 1600, 0
8869 12:14:52.947918 Vio18 = 0
8870 12:14:52.950847 Vcore = 725000
8871 12:14:52.951305 Vdram = 0
8872 12:14:52.951667 Vddq = 0
8873 12:14:52.952004 Vmddr = 0
8874 12:14:52.954245 switch to 3200 Mbps bootup
8875 12:14:52.957454 [DramcRunTimeConfig]
8876 12:14:52.957910 PHYPLL
8877 12:14:52.958269 DPM_CONTROL_AFTERK: ON
8878 12:14:52.961401 PER_BANK_REFRESH: ON
8879 12:14:52.964752 REFRESH_OVERHEAD_REDUCTION: ON
8880 12:14:52.965360 CMD_PICG_NEW_MODE: OFF
8881 12:14:52.967982 XRTWTW_NEW_MODE: ON
8882 12:14:52.970938 XRTRTR_NEW_MODE: ON
8883 12:14:52.971397 TX_TRACKING: ON
8884 12:14:52.974465 RDSEL_TRACKING: OFF
8885 12:14:52.974993 DQS Precalculation for DVFS: ON
8886 12:14:52.977700 RX_TRACKING: OFF
8887 12:14:52.978157 HW_GATING DBG: ON
8888 12:14:52.981089 ZQCS_ENABLE_LP4: ON
8889 12:14:52.984382 RX_PICG_NEW_MODE: ON
8890 12:14:52.984993 TX_PICG_NEW_MODE: ON
8891 12:14:52.987608 ENABLE_RX_DCM_DPHY: ON
8892 12:14:52.990754 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8893 12:14:52.991210 DUMMY_READ_FOR_TRACKING: OFF
8894 12:14:52.994093 !!! SPM_CONTROL_AFTERK: OFF
8895 12:14:52.998200 !!! SPM could not control APHY
8896 12:14:53.001078 IMPEDANCE_TRACKING: ON
8897 12:14:53.001633 TEMP_SENSOR: ON
8898 12:14:53.004320 HW_SAVE_FOR_SR: OFF
8899 12:14:53.008304 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8900 12:14:53.010725 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8901 12:14:53.011492 Read ODT Tracking: ON
8902 12:14:53.013594 Refresh Rate DeBounce: ON
8903 12:14:53.017349 DFS_NO_QUEUE_FLUSH: ON
8904 12:14:53.020550 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8905 12:14:53.021054 ENABLE_DFS_RUNTIME_MRW: OFF
8906 12:14:53.024566 DDR_RESERVE_NEW_MODE: ON
8907 12:14:53.027480 MR_CBT_SWITCH_FREQ: ON
8908 12:14:53.027940 =========================
8909 12:14:53.047974 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8910 12:14:53.050398 dram_init: ddr_geometry: 0
8911 12:14:53.068265 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8912 12:14:53.072169 dram_init: dram init end (result: 0)
8913 12:14:53.078046 DRAM-K: Full calibration passed in 23450 msecs
8914 12:14:53.081591 MRC: failed to locate region type 0.
8915 12:14:53.082148 DRAM rank0 size:0x80000000,
8916 12:14:53.084897 DRAM rank1 size=0x80000000
8917 12:14:53.094752 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8918 12:14:53.101089 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8919 12:14:53.107978 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8920 12:14:53.114457 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8921 12:14:53.118216 DRAM rank0 size:0x80000000,
8922 12:14:53.121243 DRAM rank1 size=0x80000000
8923 12:14:53.121797 CBMEM:
8924 12:14:53.124625 IMD: root @ 0xfffff000 254 entries.
8925 12:14:53.128599 IMD: root @ 0xffffec00 62 entries.
8926 12:14:53.131159 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8927 12:14:53.134267 WARNING: RO_VPD is uninitialized or empty.
8928 12:14:53.140676 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8929 12:14:53.147943 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8930 12:14:53.160930 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8931 12:14:53.171861 BS: romstage times (exec / console): total (unknown) / 22985 ms
8932 12:14:53.172480
8933 12:14:53.172911
8934 12:14:53.182448 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8935 12:14:53.185218 ARM64: Exception handlers installed.
8936 12:14:53.189452 ARM64: Testing exception
8937 12:14:53.192141 ARM64: Done test exception
8938 12:14:53.192697 Enumerating buses...
8939 12:14:53.195628 Show all devs... Before device enumeration.
8940 12:14:53.198591 Root Device: enabled 1
8941 12:14:53.201904 CPU_CLUSTER: 0: enabled 1
8942 12:14:53.202462 CPU: 00: enabled 1
8943 12:14:53.205157 Compare with tree...
8944 12:14:53.205616 Root Device: enabled 1
8945 12:14:53.208589 CPU_CLUSTER: 0: enabled 1
8946 12:14:53.211702 CPU: 00: enabled 1
8947 12:14:53.212161 Root Device scanning...
8948 12:14:53.215155 scan_static_bus for Root Device
8949 12:14:53.218172 CPU_CLUSTER: 0 enabled
8950 12:14:53.221637 scan_static_bus for Root Device done
8951 12:14:53.224569 scan_bus: bus Root Device finished in 8 msecs
8952 12:14:53.225097 done
8953 12:14:53.231234 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8954 12:14:53.235132 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8955 12:14:53.241111 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8956 12:14:53.245895 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8957 12:14:53.247889 Allocating resources...
8958 12:14:53.251793 Reading resources...
8959 12:14:53.254681 Root Device read_resources bus 0 link: 0
8960 12:14:53.255239 DRAM rank0 size:0x80000000,
8961 12:14:53.258148 DRAM rank1 size=0x80000000
8962 12:14:53.261277 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8963 12:14:53.265678 CPU: 00 missing read_resources
8964 12:14:53.268616 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8965 12:14:53.274395 Root Device read_resources bus 0 link: 0 done
8966 12:14:53.274938 Done reading resources.
8967 12:14:53.281526 Show resources in subtree (Root Device)...After reading.
8968 12:14:53.284296 Root Device child on link 0 CPU_CLUSTER: 0
8969 12:14:53.287463 CPU_CLUSTER: 0 child on link 0 CPU: 00
8970 12:14:53.298118 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8971 12:14:53.298679 CPU: 00
8972 12:14:53.301200 Root Device assign_resources, bus 0 link: 0
8973 12:14:53.304757 CPU_CLUSTER: 0 missing set_resources
8974 12:14:53.311896 Root Device assign_resources, bus 0 link: 0 done
8975 12:14:53.312448 Done setting resources.
8976 12:14:53.317832 Show resources in subtree (Root Device)...After assigning values.
8977 12:14:53.321636 Root Device child on link 0 CPU_CLUSTER: 0
8978 12:14:53.324371 CPU_CLUSTER: 0 child on link 0 CPU: 00
8979 12:14:53.334528 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8980 12:14:53.335079 CPU: 00
8981 12:14:53.337300 Done allocating resources.
8982 12:14:53.344399 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8983 12:14:53.345018 Enabling resources...
8984 12:14:53.345396 done.
8985 12:14:53.350507 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8986 12:14:53.351055 Initializing devices...
8987 12:14:53.353825 Root Device init
8988 12:14:53.354286 init hardware done!
8989 12:14:53.358474 0x00000018: ctrlr->caps
8990 12:14:53.361838 52.000 MHz: ctrlr->f_max
8991 12:14:53.362544 0.400 MHz: ctrlr->f_min
8992 12:14:53.363571 0x40ff8080: ctrlr->voltages
8993 12:14:53.368305 sclk: 390625
8994 12:14:53.368902 Bus Width = 1
8995 12:14:53.369272 sclk: 390625
8996 12:14:53.371026 Bus Width = 1
8997 12:14:53.371578 Early init status = 3
8998 12:14:53.376941 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8999 12:14:53.380554 in-header: 03 fc 00 00 01 00 00 00
9000 12:14:53.384119 in-data: 00
9001 12:14:53.387948 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9002 12:14:53.390430 in-header: 03 fd 00 00 00 00 00 00
9003 12:14:53.393642 in-data:
9004 12:14:53.396825 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9005 12:14:53.401035 in-header: 03 fc 00 00 01 00 00 00
9006 12:14:53.403836 in-data: 00
9007 12:14:53.407437 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9008 12:14:53.412355 in-header: 03 fd 00 00 00 00 00 00
9009 12:14:53.415331 in-data:
9010 12:14:53.418222 [SSUSB] Setting up USB HOST controller...
9011 12:14:53.421989 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9012 12:14:53.425147 [SSUSB] phy power-on done.
9013 12:14:53.428876 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9014 12:14:53.434559 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9015 12:14:53.438189 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9016 12:14:53.445170 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9017 12:14:53.451116 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9018 12:14:53.457683 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9019 12:14:53.464977 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9020 12:14:53.471619 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9021 12:14:53.474930 SPM: binary array size = 0x9dc
9022 12:14:53.478415 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9023 12:14:53.485260 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9024 12:14:53.491181 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9025 12:14:53.497647 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9026 12:14:53.500957 configure_display: Starting display init
9027 12:14:53.535330 anx7625_power_on_init: Init interface.
9028 12:14:53.538441 anx7625_disable_pd_protocol: Disabled PD feature.
9029 12:14:53.541941 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9030 12:14:53.569546 anx7625_start_dp_work: Secure OCM version=00
9031 12:14:53.573364 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9032 12:14:53.588095 sp_tx_get_edid_block: EDID Block = 1
9033 12:14:53.690507 Extracted contents:
9034 12:14:53.693373 header: 00 ff ff ff ff ff ff 00
9035 12:14:53.696752 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9036 12:14:53.700519 version: 01 04
9037 12:14:53.703606 basic params: 95 1f 11 78 0a
9038 12:14:53.707187 chroma info: 76 90 94 55 54 90 27 21 50 54
9039 12:14:53.710847 established: 00 00 00
9040 12:14:53.716830 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9041 12:14:53.723183 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9042 12:14:53.726635 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9043 12:14:53.733162 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9044 12:14:53.740024 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9045 12:14:53.742768 extensions: 00
9046 12:14:53.743247 checksum: fb
9047 12:14:53.743724
9048 12:14:53.750231 Manufacturer: IVO Model 57d Serial Number 0
9049 12:14:53.750804 Made week 0 of 2020
9050 12:14:53.752555 EDID version: 1.4
9051 12:14:53.753068 Digital display
9052 12:14:53.756493 6 bits per primary color channel
9053 12:14:53.757134 DisplayPort interface
9054 12:14:53.759093 Maximum image size: 31 cm x 17 cm
9055 12:14:53.763009 Gamma: 220%
9056 12:14:53.763578 Check DPMS levels
9057 12:14:53.769062 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9058 12:14:53.772750 First detailed timing is preferred timing
9059 12:14:53.773357 Established timings supported:
9060 12:14:53.776161 Standard timings supported:
9061 12:14:53.778924 Detailed timings
9062 12:14:53.782459 Hex of detail: 383680a07038204018303c0035ae10000019
9063 12:14:53.789024 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9064 12:14:53.792915 0780 0798 07c8 0820 hborder 0
9065 12:14:53.795697 0438 043b 0447 0458 vborder 0
9066 12:14:53.798733 -hsync -vsync
9067 12:14:53.799189 Did detailed timing
9068 12:14:53.806279 Hex of detail: 000000000000000000000000000000000000
9069 12:14:53.809625 Manufacturer-specified data, tag 0
9070 12:14:53.812608 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9071 12:14:53.815358 ASCII string: InfoVision
9072 12:14:53.820114 Hex of detail: 000000fe00523134304e574635205248200a
9073 12:14:53.822851 ASCII string: R140NWF5 RH
9074 12:14:53.823341 Checksum
9075 12:14:53.825358 Checksum: 0xfb (valid)
9076 12:14:53.828369 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9077 12:14:53.832002 DSI data_rate: 832800000 bps
9078 12:14:53.838513 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9079 12:14:53.842402 anx7625_parse_edid: pixelclock(138800).
9080 12:14:53.845436 hactive(1920), hsync(48), hfp(24), hbp(88)
9081 12:14:53.849299 vactive(1080), vsync(12), vfp(3), vbp(17)
9082 12:14:53.851652 anx7625_dsi_config: config dsi.
9083 12:14:53.858754 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9084 12:14:53.872594 anx7625_dsi_config: success to config DSI
9085 12:14:53.875826 anx7625_dp_start: MIPI phy setup OK.
9086 12:14:53.878906 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9087 12:14:53.881992 mtk_ddp_mode_set invalid vrefresh 60
9088 12:14:53.885881 main_disp_path_setup
9089 12:14:53.886518 ovl_layer_smi_id_en
9090 12:14:53.888527 ovl_layer_smi_id_en
9091 12:14:53.889078 ccorr_config
9092 12:14:53.889446 aal_config
9093 12:14:53.892090 gamma_config
9094 12:14:53.892549 postmask_config
9095 12:14:53.895209 dither_config
9096 12:14:53.898377 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9097 12:14:53.905202 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9098 12:14:53.908068 Root Device init finished in 551 msecs
9099 12:14:53.911493 CPU_CLUSTER: 0 init
9100 12:14:53.918426 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9101 12:14:53.925307 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9102 12:14:53.925908 APU_MBOX 0x190000b0 = 0x10001
9103 12:14:53.928239 APU_MBOX 0x190001b0 = 0x10001
9104 12:14:53.931907 APU_MBOX 0x190005b0 = 0x10001
9105 12:14:53.934969 APU_MBOX 0x190006b0 = 0x10001
9106 12:14:53.941083 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9107 12:14:53.951943 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9108 12:14:53.963787 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9109 12:14:53.971116 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9110 12:14:53.981561 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9111 12:14:53.991138 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9112 12:14:53.994642 CPU_CLUSTER: 0 init finished in 81 msecs
9113 12:14:53.998891 Devices initialized
9114 12:14:54.000694 Show all devs... After init.
9115 12:14:54.001204 Root Device: enabled 1
9116 12:14:54.004039 CPU_CLUSTER: 0: enabled 1
9117 12:14:54.007409 CPU: 00: enabled 1
9118 12:14:54.010702 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9119 12:14:54.014378 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9120 12:14:54.017222 ELOG: NV offset 0x57f000 size 0x1000
9121 12:14:54.024813 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9122 12:14:54.031488 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9123 12:14:54.034423 ELOG: Event(17) added with size 13 at 2024-01-31 12:14:57 UTC
9124 12:14:54.037697 out: cmd=0x121: 03 db 21 01 00 00 00 00
9125 12:14:54.041516 in-header: 03 e6 00 00 2c 00 00 00
9126 12:14:54.054468 in-data: 7d 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9127 12:14:54.061483 ELOG: Event(A1) added with size 10 at 2024-01-31 12:14:57 UTC
9128 12:14:54.068219 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9129 12:14:54.074125 ELOG: Event(A0) added with size 9 at 2024-01-31 12:14:57 UTC
9130 12:14:54.077553 elog_add_boot_reason: Logged dev mode boot
9131 12:14:54.081345 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9132 12:14:54.083928 Finalize devices...
9133 12:14:54.084387 Devices finalized
9134 12:14:54.091207 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9135 12:14:54.095019 Writing coreboot table at 0xffe64000
9136 12:14:54.097447 0. 000000000010a000-0000000000113fff: RAMSTAGE
9137 12:14:54.101239 1. 0000000040000000-00000000400fffff: RAM
9138 12:14:54.108940 2. 0000000040100000-000000004032afff: RAMSTAGE
9139 12:14:54.110653 3. 000000004032b000-00000000545fffff: RAM
9140 12:14:54.114187 4. 0000000054600000-000000005465ffff: BL31
9141 12:14:54.117089 5. 0000000054660000-00000000ffe63fff: RAM
9142 12:14:54.123874 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9143 12:14:54.127841 7. 0000000100000000-000000013fffffff: RAM
9144 12:14:54.128396 Passing 5 GPIOs to payload:
9145 12:14:54.134668 NAME | PORT | POLARITY | VALUE
9146 12:14:54.137188 EC in RW | 0x000000aa | low | undefined
9147 12:14:54.144273 EC interrupt | 0x00000005 | low | undefined
9148 12:14:54.147619 TPM interrupt | 0x000000ab | high | undefined
9149 12:14:54.150793 SD card detect | 0x00000011 | high | undefined
9150 12:14:54.158062 speaker enable | 0x00000093 | high | undefined
9151 12:14:54.161213 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9152 12:14:54.163996 in-header: 03 f8 00 00 02 00 00 00
9153 12:14:54.164564 in-data: 03 00
9154 12:14:54.167260 ADC[4]: Raw value=669327 ID=5
9155 12:14:54.171224 ADC[3]: Raw value=212549 ID=1
9156 12:14:54.173514 RAM Code: 0x51
9157 12:14:54.173976 ADC[6]: Raw value=74410 ID=0
9158 12:14:54.177042 ADC[5]: Raw value=211812 ID=1
9159 12:14:54.180837 SKU Code: 0x1
9160 12:14:54.183305 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum dd72
9161 12:14:54.186769 coreboot table: 964 bytes.
9162 12:14:54.190314 IMD ROOT 0. 0xfffff000 0x00001000
9163 12:14:54.193245 IMD SMALL 1. 0xffffe000 0x00001000
9164 12:14:54.196858 RO MCACHE 2. 0xffffc000 0x00001104
9165 12:14:54.200104 CONSOLE 3. 0xfff7c000 0x00080000
9166 12:14:54.203903 FMAP 4. 0xfff7b000 0x00000452
9167 12:14:54.206861 TIME STAMP 5. 0xfff7a000 0x00000910
9168 12:14:54.210194 VBOOT WORK 6. 0xfff66000 0x00014000
9169 12:14:54.213283 RAMOOPS 7. 0xffe66000 0x00100000
9170 12:14:54.216613 COREBOOT 8. 0xffe64000 0x00002000
9171 12:14:54.217249 IMD small region:
9172 12:14:54.219635 IMD ROOT 0. 0xffffec00 0x00000400
9173 12:14:54.224039 VPD 1. 0xffffeb80 0x0000006c
9174 12:14:54.229699 MMC STATUS 2. 0xffffeb60 0x00000004
9175 12:14:54.233010 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9176 12:14:54.236682 Probing TPM: done!
9177 12:14:54.239866 Connected to device vid:did:rid of 1ae0:0028:00
9178 12:14:54.250306 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9179 12:14:54.253444 Initialized TPM device CR50 revision 0
9180 12:14:54.257610 Checking cr50 for pending updates
9181 12:14:54.260627 Reading cr50 TPM mode
9182 12:14:54.269107 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9183 12:14:54.275896 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9184 12:14:54.316646 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9185 12:14:54.319962 Checking segment from ROM address 0x40100000
9186 12:14:54.322706 Checking segment from ROM address 0x4010001c
9187 12:14:54.328998 Loading segment from ROM address 0x40100000
9188 12:14:54.329650 code (compression=0)
9189 12:14:54.339273 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9190 12:14:54.345490 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9191 12:14:54.346081 it's not compressed!
9192 12:14:54.353132 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9193 12:14:54.356264 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9194 12:14:54.377736 Loading segment from ROM address 0x4010001c
9195 12:14:54.378288 Entry Point 0x80000000
9196 12:14:54.379577 Loaded segments
9197 12:14:54.382950 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9198 12:14:54.390251 Jumping to boot code at 0x80000000(0xffe64000)
9199 12:14:54.396189 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9200 12:14:54.402628 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9201 12:14:54.411540 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9202 12:14:54.413870 Checking segment from ROM address 0x40100000
9203 12:14:54.417726 Checking segment from ROM address 0x4010001c
9204 12:14:54.424117 Loading segment from ROM address 0x40100000
9205 12:14:54.424700 code (compression=1)
9206 12:14:54.431258 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9207 12:14:54.440435 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9208 12:14:54.441022 using LZMA
9209 12:14:54.449279 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9210 12:14:54.456091 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9211 12:14:54.458893 Loading segment from ROM address 0x4010001c
9212 12:14:54.459452 Entry Point 0x54601000
9213 12:14:54.462426 Loaded segments
9214 12:14:54.466176 NOTICE: MT8192 bl31_setup
9215 12:14:54.472879 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9216 12:14:54.476198 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9217 12:14:54.479427 WARNING: region 0:
9218 12:14:54.483211 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9219 12:14:54.483799 WARNING: region 1:
9220 12:14:54.489213 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9221 12:14:54.493117 WARNING: region 2:
9222 12:14:54.496291 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9223 12:14:54.499510 WARNING: region 3:
9224 12:14:54.503227 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9225 12:14:54.507471 WARNING: region 4:
9226 12:14:54.512515 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9227 12:14:54.513142 WARNING: region 5:
9228 12:14:54.516235 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9229 12:14:54.519268 WARNING: region 6:
9230 12:14:54.522548 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9231 12:14:54.525985 WARNING: region 7:
9232 12:14:54.529089 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9233 12:14:54.535976 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9234 12:14:54.539357 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9235 12:14:54.542427 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9236 12:14:54.549126 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9237 12:14:54.552509 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9238 12:14:54.555606 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9239 12:14:54.563573 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9240 12:14:54.566489 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9241 12:14:54.573449 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9242 12:14:54.576101 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9243 12:14:54.579023 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9244 12:14:54.585613 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9245 12:14:54.588937 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9246 12:14:54.592539 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9247 12:14:54.599209 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9248 12:14:54.602299 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9249 12:14:54.608834 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9250 12:14:54.612808 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9251 12:14:54.616052 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9252 12:14:54.622636 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9253 12:14:54.626304 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9254 12:14:54.629617 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9255 12:14:54.635980 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9256 12:14:54.639432 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9257 12:14:54.645503 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9258 12:14:54.649273 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9259 12:14:54.652486 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9260 12:14:54.659773 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9261 12:14:54.663370 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9262 12:14:54.669413 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9263 12:14:54.672646 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9264 12:14:54.676184 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9265 12:14:54.682562 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9266 12:14:54.685963 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9267 12:14:54.688827 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9268 12:14:54.692388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9269 12:14:54.700177 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9270 12:14:54.702542 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9271 12:14:54.705869 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9272 12:14:54.709119 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9273 12:14:54.715770 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9274 12:14:54.719555 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9275 12:14:54.725355 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9276 12:14:54.726567 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9277 12:14:54.732070 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9278 12:14:54.736130 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9279 12:14:54.739228 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9280 12:14:54.742388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9281 12:14:54.749410 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9282 12:14:54.752486 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9283 12:14:54.759166 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9284 12:14:54.762626 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9285 12:14:54.769346 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9286 12:14:54.772624 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9287 12:14:54.775926 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9288 12:14:54.782966 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9289 12:14:54.785903 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9290 12:14:54.792361 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9291 12:14:54.795687 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9292 12:14:54.799653 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9293 12:14:54.805685 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9294 12:14:54.809191 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9295 12:14:54.815855 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9296 12:14:54.819550 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9297 12:14:54.825647 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9298 12:14:54.828803 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9299 12:14:54.835674 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9300 12:14:54.838908 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9301 12:14:54.842572 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9302 12:14:54.848642 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9303 12:14:54.851930 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9304 12:14:54.859397 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9305 12:14:54.861886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9306 12:14:54.869284 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9307 12:14:54.871947 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9308 12:14:54.875353 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9309 12:14:54.882334 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9310 12:14:54.885430 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9311 12:14:54.891772 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9312 12:14:54.895068 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9313 12:14:54.902000 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9314 12:14:54.905433 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9315 12:14:54.912374 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9316 12:14:54.915744 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9317 12:14:54.919333 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9318 12:14:54.925366 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9319 12:14:54.928853 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9320 12:14:54.936875 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9321 12:14:54.938908 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9322 12:14:54.946475 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9323 12:14:54.949362 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9324 12:14:54.951986 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9325 12:14:54.958693 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9326 12:14:54.962826 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9327 12:14:54.969725 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9328 12:14:54.971570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9329 12:14:54.975086 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9330 12:14:54.981714 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9331 12:14:54.985153 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9332 12:14:54.988143 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9333 12:14:54.991456 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9334 12:14:54.998136 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9335 12:14:55.002077 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9336 12:14:55.008515 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9337 12:14:55.012222 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9338 12:14:55.015635 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9339 12:14:55.021598 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9340 12:14:55.024654 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9341 12:14:55.031898 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9342 12:14:55.034785 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9343 12:14:55.038057 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9344 12:14:55.044890 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9345 12:14:55.047984 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9346 12:14:55.056538 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9347 12:14:55.058760 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9348 12:14:55.061567 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9349 12:14:55.069087 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9350 12:14:55.071905 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9351 12:14:55.075136 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9352 12:14:55.081332 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9353 12:14:55.084823 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9354 12:14:55.088488 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9355 12:14:55.092212 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9356 12:14:55.098228 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9357 12:14:55.101451 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9358 12:14:55.105120 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9359 12:14:55.112141 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9360 12:14:55.115167 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9361 12:14:55.121334 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9362 12:14:55.124846 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9363 12:14:55.128560 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9364 12:14:55.134830 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9365 12:14:55.138133 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9366 12:14:55.144464 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9367 12:14:55.147926 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9368 12:14:55.151613 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9369 12:14:55.158598 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9370 12:14:55.161280 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9371 12:14:55.164688 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9372 12:14:55.171198 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9373 12:14:55.174853 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9374 12:14:55.180904 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9375 12:14:55.184642 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9376 12:14:55.187799 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9377 12:14:55.194983 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9378 12:14:55.198379 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9379 12:14:55.204872 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9380 12:14:55.208422 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9381 12:14:55.211145 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9382 12:14:55.218668 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9383 12:14:55.221154 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9384 12:14:55.224908 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9385 12:14:55.231430 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9386 12:14:55.234324 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9387 12:14:55.241284 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9388 12:14:55.244528 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9389 12:14:55.248643 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9390 12:14:55.254946 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9391 12:14:55.257891 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9392 12:14:55.264440 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9393 12:14:55.268082 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9394 12:14:55.271674 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9395 12:14:55.279451 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9396 12:14:55.281036 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9397 12:14:55.288167 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9398 12:14:55.290361 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9399 12:14:55.295268 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9400 12:14:55.301138 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9401 12:14:55.303886 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9402 12:14:55.310652 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9403 12:14:55.314030 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9404 12:14:55.317054 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9405 12:14:55.324021 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9406 12:14:55.327158 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9407 12:14:55.334832 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9408 12:14:55.337832 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9409 12:14:55.341380 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9410 12:14:55.347380 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9411 12:14:55.350718 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9412 12:14:55.353998 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9413 12:14:55.360491 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9414 12:14:55.363402 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9415 12:14:55.370477 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9416 12:14:55.374315 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9417 12:14:55.376821 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9418 12:14:55.384551 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9419 12:14:55.387246 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9420 12:14:55.393517 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9421 12:14:55.396831 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9422 12:14:55.401661 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9423 12:14:55.407662 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9424 12:14:55.410891 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9425 12:14:55.417378 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9426 12:14:55.420036 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9427 12:14:55.427203 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9428 12:14:55.429595 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9429 12:14:55.433446 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9430 12:14:55.439886 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9431 12:14:55.442977 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9432 12:14:55.449598 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9433 12:14:55.453050 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9434 12:14:55.459970 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9435 12:14:55.463361 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9436 12:14:55.466280 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9437 12:14:55.472664 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9438 12:14:55.476524 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9439 12:14:55.482385 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9440 12:14:55.485727 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9441 12:14:55.492868 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9442 12:14:55.496258 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9443 12:14:55.499245 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9444 12:14:55.505876 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9445 12:14:55.509443 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9446 12:14:55.515762 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9447 12:14:55.519906 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9448 12:14:55.525873 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9449 12:14:55.529417 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9450 12:14:55.532994 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9451 12:14:55.538988 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9452 12:14:55.542642 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9453 12:14:55.548879 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9454 12:14:55.552437 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9455 12:14:55.555572 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9456 12:14:55.562581 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9457 12:14:55.565566 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9458 12:14:55.571839 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9459 12:14:55.575486 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9460 12:14:55.582658 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9461 12:14:55.585292 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9462 12:14:55.588842 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9463 12:14:55.591948 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9464 12:14:55.598569 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9465 12:14:55.601519 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9466 12:14:55.604765 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9467 12:14:55.612195 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9468 12:14:55.615209 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9469 12:14:55.618139 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9470 12:14:55.624875 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9471 12:14:55.628386 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9472 12:14:55.631769 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9473 12:14:55.638134 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9474 12:14:55.641592 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9475 12:14:55.647633 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9476 12:14:55.651514 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9477 12:14:55.654757 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9478 12:14:55.661035 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9479 12:14:55.664599 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9480 12:14:55.667851 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9481 12:14:55.675079 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9482 12:14:55.677400 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9483 12:14:55.684496 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9484 12:14:55.687582 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9485 12:14:55.691103 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9486 12:14:55.697646 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9487 12:14:55.700999 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9488 12:14:55.704161 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9489 12:14:55.710787 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9490 12:14:55.714105 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9491 12:14:55.717847 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9492 12:14:55.724643 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9493 12:14:55.727881 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9494 12:14:55.735291 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9495 12:14:55.736964 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9496 12:14:55.740621 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9497 12:14:55.746781 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9498 12:14:55.750152 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9499 12:14:55.757701 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9500 12:14:55.760284 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9501 12:14:55.764341 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9502 12:14:55.766601 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9503 12:14:55.773927 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9504 12:14:55.776815 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9505 12:14:55.780801 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9506 12:14:55.783463 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9507 12:14:55.789609 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9508 12:14:55.793656 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9509 12:14:55.796362 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9510 12:14:55.799698 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9511 12:14:55.807130 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9512 12:14:55.810922 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9513 12:14:55.812822 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9514 12:14:55.816096 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9515 12:14:55.823909 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9516 12:14:55.826799 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9517 12:14:55.832934 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9518 12:14:55.836592 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9519 12:14:55.843388 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9520 12:14:55.846964 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9521 12:14:55.850014 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9522 12:14:55.856395 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9523 12:14:55.860128 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9524 12:14:55.866366 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9525 12:14:55.869682 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9526 12:14:55.872828 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9527 12:14:55.879516 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9528 12:14:55.882301 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9529 12:14:55.889005 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9530 12:14:55.893188 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9531 12:14:55.896054 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9532 12:14:55.902614 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9533 12:14:55.905963 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9534 12:14:55.912049 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9535 12:14:55.915994 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9536 12:14:55.922360 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9537 12:14:55.925404 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9538 12:14:55.928894 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9539 12:14:55.935717 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9540 12:14:55.938829 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9541 12:14:55.946589 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9542 12:14:55.948913 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9543 12:14:55.955808 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9544 12:14:55.958563 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9545 12:14:55.962391 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9546 12:14:55.968552 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9547 12:14:55.971920 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9548 12:14:55.978673 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9549 12:14:55.981658 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9550 12:14:55.984988 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9551 12:14:55.991358 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9552 12:14:55.995040 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9553 12:14:56.002489 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9554 12:14:56.004671 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9555 12:14:56.008426 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9556 12:14:56.014869 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9557 12:14:56.018491 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9558 12:14:56.024458 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9559 12:14:56.027449 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9560 12:14:56.034150 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9561 12:14:56.038035 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9562 12:14:56.041078 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9563 12:14:56.047637 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9564 12:14:56.051990 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9565 12:14:56.059888 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9566 12:14:56.060892 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9567 12:14:56.068132 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9568 12:14:56.071343 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9569 12:14:56.074242 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9570 12:14:56.081409 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9571 12:14:56.084178 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9572 12:14:56.087836 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9573 12:14:56.094995 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9574 12:14:56.097433 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9575 12:14:56.104341 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9576 12:14:56.107831 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9577 12:14:56.114105 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9578 12:14:56.117041 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9579 12:14:56.120392 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9580 12:14:56.127223 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9581 12:14:56.130046 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9582 12:14:56.137243 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9583 12:14:56.140403 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9584 12:14:56.147105 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9585 12:14:56.149719 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9586 12:14:56.153035 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9587 12:14:56.159935 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9588 12:14:56.163244 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9589 12:14:56.169964 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9590 12:14:56.173334 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9591 12:14:56.181339 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9592 12:14:56.183950 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9593 12:14:56.189643 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9594 12:14:56.192917 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9595 12:14:56.196299 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9596 12:14:56.203601 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9597 12:14:56.206247 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9598 12:14:56.212967 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9599 12:14:56.216673 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9600 12:14:56.222956 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9601 12:14:56.226011 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9602 12:14:56.229998 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9603 12:14:56.236638 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9604 12:14:56.239716 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9605 12:14:56.246108 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9606 12:14:56.248943 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9607 12:14:56.256026 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9608 12:14:56.259295 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9609 12:14:56.266094 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9610 12:14:56.269400 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9611 12:14:56.272611 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9612 12:14:56.278635 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9613 12:14:56.282019 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9614 12:14:56.288827 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9615 12:14:56.292145 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9616 12:14:56.299462 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9617 12:14:56.302489 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9618 12:14:56.305598 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9619 12:14:56.312337 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9620 12:14:56.315538 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9621 12:14:56.322282 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9622 12:14:56.325595 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9623 12:14:56.332491 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9624 12:14:56.335212 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9625 12:14:56.341857 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9626 12:14:56.345334 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9627 12:14:56.348297 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9628 12:14:56.354933 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9629 12:14:56.358310 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9630 12:14:56.364651 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9631 12:14:56.368019 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9632 12:14:56.374214 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9633 12:14:56.377644 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9634 12:14:56.385539 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9635 12:14:56.387601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9636 12:14:56.391759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9637 12:14:56.397643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9638 12:14:56.401031 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9639 12:14:56.410067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9640 12:14:56.411185 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9641 12:14:56.417896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9642 12:14:56.421230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9643 12:14:56.427251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9644 12:14:56.430622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9645 12:14:56.437162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9646 12:14:56.440496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9647 12:14:56.447332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9648 12:14:56.450311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9649 12:14:56.456686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9650 12:14:56.461287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9651 12:14:56.466865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9652 12:14:56.470697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9653 12:14:56.476820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9654 12:14:56.480650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9655 12:14:56.487343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9656 12:14:56.490919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9657 12:14:56.497666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9658 12:14:56.501577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9659 12:14:56.506856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9660 12:14:56.510254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9661 12:14:56.517479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9662 12:14:56.523048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9663 12:14:56.527167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9664 12:14:56.529845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9665 12:14:56.536250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9666 12:14:56.539931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9667 12:14:56.543153 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9668 12:14:56.546096 INFO: [APUAPC] vio 0
9669 12:14:56.552974 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9670 12:14:56.555877 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9671 12:14:56.559502 INFO: [APUAPC] D0_APC_0: 0x400510
9672 12:14:56.563133 INFO: [APUAPC] D0_APC_1: 0x0
9673 12:14:56.566557 INFO: [APUAPC] D0_APC_2: 0x1540
9674 12:14:56.569407 INFO: [APUAPC] D0_APC_3: 0x0
9675 12:14:56.572645 INFO: [APUAPC] D1_APC_0: 0xffffffff
9676 12:14:56.576288 INFO: [APUAPC] D1_APC_1: 0xffffffff
9677 12:14:56.579227 INFO: [APUAPC] D1_APC_2: 0x3fffff
9678 12:14:56.583056 INFO: [APUAPC] D1_APC_3: 0x0
9679 12:14:56.585932 INFO: [APUAPC] D2_APC_0: 0xffffffff
9680 12:14:56.589015 INFO: [APUAPC] D2_APC_1: 0xffffffff
9681 12:14:56.592486 INFO: [APUAPC] D2_APC_2: 0x3fffff
9682 12:14:56.595884 INFO: [APUAPC] D2_APC_3: 0x0
9683 12:14:56.598942 INFO: [APUAPC] D3_APC_0: 0xffffffff
9684 12:14:56.603113 INFO: [APUAPC] D3_APC_1: 0xffffffff
9685 12:14:56.606470 INFO: [APUAPC] D3_APC_2: 0x3fffff
9686 12:14:56.607027 INFO: [APUAPC] D3_APC_3: 0x0
9687 12:14:56.612388 INFO: [APUAPC] D4_APC_0: 0xffffffff
9688 12:14:56.616109 INFO: [APUAPC] D4_APC_1: 0xffffffff
9689 12:14:56.618636 INFO: [APUAPC] D4_APC_2: 0x3fffff
9690 12:14:56.619097 INFO: [APUAPC] D4_APC_3: 0x0
9691 12:14:56.622594 INFO: [APUAPC] D5_APC_0: 0xffffffff
9692 12:14:56.629621 INFO: [APUAPC] D5_APC_1: 0xffffffff
9693 12:14:56.632566 INFO: [APUAPC] D5_APC_2: 0x3fffff
9694 12:14:56.633198 INFO: [APUAPC] D5_APC_3: 0x0
9695 12:14:56.635631 INFO: [APUAPC] D6_APC_0: 0xffffffff
9696 12:14:56.639479 INFO: [APUAPC] D6_APC_1: 0xffffffff
9697 12:14:56.641873 INFO: [APUAPC] D6_APC_2: 0x3fffff
9698 12:14:56.645932 INFO: [APUAPC] D6_APC_3: 0x0
9699 12:14:56.648925 INFO: [APUAPC] D7_APC_0: 0xffffffff
9700 12:14:56.652351 INFO: [APUAPC] D7_APC_1: 0xffffffff
9701 12:14:56.655645 INFO: [APUAPC] D7_APC_2: 0x3fffff
9702 12:14:56.658380 INFO: [APUAPC] D7_APC_3: 0x0
9703 12:14:56.661608 INFO: [APUAPC] D8_APC_0: 0xffffffff
9704 12:14:56.665435 INFO: [APUAPC] D8_APC_1: 0xffffffff
9705 12:14:56.668960 INFO: [APUAPC] D8_APC_2: 0x3fffff
9706 12:14:56.672028 INFO: [APUAPC] D8_APC_3: 0x0
9707 12:14:56.675339 INFO: [APUAPC] D9_APC_0: 0xffffffff
9708 12:14:56.678955 INFO: [APUAPC] D9_APC_1: 0xffffffff
9709 12:14:56.681451 INFO: [APUAPC] D9_APC_2: 0x3fffff
9710 12:14:56.686273 INFO: [APUAPC] D9_APC_3: 0x0
9711 12:14:56.688877 INFO: [APUAPC] D10_APC_0: 0xffffffff
9712 12:14:56.691814 INFO: [APUAPC] D10_APC_1: 0xffffffff
9713 12:14:56.695362 INFO: [APUAPC] D10_APC_2: 0x3fffff
9714 12:14:56.697987 INFO: [APUAPC] D10_APC_3: 0x0
9715 12:14:56.701479 INFO: [APUAPC] D11_APC_0: 0xffffffff
9716 12:14:56.704686 INFO: [APUAPC] D11_APC_1: 0xffffffff
9717 12:14:56.708485 INFO: [APUAPC] D11_APC_2: 0x3fffff
9718 12:14:56.712228 INFO: [APUAPC] D11_APC_3: 0x0
9719 12:14:56.714658 INFO: [APUAPC] D12_APC_0: 0xffffffff
9720 12:14:56.717760 INFO: [APUAPC] D12_APC_1: 0xffffffff
9721 12:14:56.721444 INFO: [APUAPC] D12_APC_2: 0x3fffff
9722 12:14:56.724251 INFO: [APUAPC] D12_APC_3: 0x0
9723 12:14:56.727604 INFO: [APUAPC] D13_APC_0: 0xffffffff
9724 12:14:56.731569 INFO: [APUAPC] D13_APC_1: 0xffffffff
9725 12:14:56.735332 INFO: [APUAPC] D13_APC_2: 0x3fffff
9726 12:14:56.737695 INFO: [APUAPC] D13_APC_3: 0x0
9727 12:14:56.741401 INFO: [APUAPC] D14_APC_0: 0xffffffff
9728 12:14:56.744281 INFO: [APUAPC] D14_APC_1: 0xffffffff
9729 12:14:56.747745 INFO: [APUAPC] D14_APC_2: 0x3fffff
9730 12:14:56.751540 INFO: [APUAPC] D14_APC_3: 0x0
9731 12:14:56.754613 INFO: [APUAPC] D15_APC_0: 0xffffffff
9732 12:14:56.757898 INFO: [APUAPC] D15_APC_1: 0xffffffff
9733 12:14:56.761167 INFO: [APUAPC] D15_APC_2: 0x3fffff
9734 12:14:56.764149 INFO: [APUAPC] D15_APC_3: 0x0
9735 12:14:56.767397 INFO: [APUAPC] APC_CON: 0x4
9736 12:14:56.770925 INFO: [NOCDAPC] D0_APC_0: 0x0
9737 12:14:56.773913 INFO: [NOCDAPC] D0_APC_1: 0x0
9738 12:14:56.777555 INFO: [NOCDAPC] D1_APC_0: 0x0
9739 12:14:56.780417 INFO: [NOCDAPC] D1_APC_1: 0xfff
9740 12:14:56.783968 INFO: [NOCDAPC] D2_APC_0: 0x0
9741 12:14:56.787956 INFO: [NOCDAPC] D2_APC_1: 0xfff
9742 12:14:56.791412 INFO: [NOCDAPC] D3_APC_0: 0x0
9743 12:14:56.791967 INFO: [NOCDAPC] D3_APC_1: 0xfff
9744 12:14:56.793928 INFO: [NOCDAPC] D4_APC_0: 0x0
9745 12:14:56.798036 INFO: [NOCDAPC] D4_APC_1: 0xfff
9746 12:14:56.801620 INFO: [NOCDAPC] D5_APC_0: 0x0
9747 12:14:56.803970 INFO: [NOCDAPC] D5_APC_1: 0xfff
9748 12:14:56.807637 INFO: [NOCDAPC] D6_APC_0: 0x0
9749 12:14:56.811178 INFO: [NOCDAPC] D6_APC_1: 0xfff
9750 12:14:56.813442 INFO: [NOCDAPC] D7_APC_0: 0x0
9751 12:14:56.816887 INFO: [NOCDAPC] D7_APC_1: 0xfff
9752 12:14:56.820454 INFO: [NOCDAPC] D8_APC_0: 0x0
9753 12:14:56.823585 INFO: [NOCDAPC] D8_APC_1: 0xfff
9754 12:14:56.824048 INFO: [NOCDAPC] D9_APC_0: 0x0
9755 12:14:56.827540 INFO: [NOCDAPC] D9_APC_1: 0xfff
9756 12:14:56.830849 INFO: [NOCDAPC] D10_APC_0: 0x0
9757 12:14:56.834022 INFO: [NOCDAPC] D10_APC_1: 0xfff
9758 12:14:56.837476 INFO: [NOCDAPC] D11_APC_0: 0x0
9759 12:14:56.840760 INFO: [NOCDAPC] D11_APC_1: 0xfff
9760 12:14:56.844335 INFO: [NOCDAPC] D12_APC_0: 0x0
9761 12:14:56.847391 INFO: [NOCDAPC] D12_APC_1: 0xfff
9762 12:14:56.850654 INFO: [NOCDAPC] D13_APC_0: 0x0
9763 12:14:56.853675 INFO: [NOCDAPC] D13_APC_1: 0xfff
9764 12:14:56.856359 INFO: [NOCDAPC] D14_APC_0: 0x0
9765 12:14:56.859995 INFO: [NOCDAPC] D14_APC_1: 0xfff
9766 12:14:56.863259 INFO: [NOCDAPC] D15_APC_0: 0x0
9767 12:14:56.867511 INFO: [NOCDAPC] D15_APC_1: 0xfff
9768 12:14:56.870126 INFO: [NOCDAPC] APC_CON: 0x4
9769 12:14:56.872969 INFO: [APUAPC] set_apusys_apc done
9770 12:14:56.873431 INFO: [DEVAPC] devapc_init done
9771 12:14:56.879935 INFO: GICv3 without legacy support detected.
9772 12:14:56.883935 INFO: ARM GICv3 driver initialized in EL3
9773 12:14:56.886420 INFO: Maximum SPI INTID supported: 639
9774 12:14:56.890223 INFO: BL31: Initializing runtime services
9775 12:14:56.896530 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9776 12:14:56.899638 INFO: SPM: enable CPC mode
9777 12:14:56.903641 INFO: mcdi ready for mcusys-off-idle and system suspend
9778 12:14:56.909567 INFO: BL31: Preparing for EL3 exit to normal world
9779 12:14:56.912867 INFO: Entry point address = 0x80000000
9780 12:14:56.916825 INFO: SPSR = 0x8
9781 12:14:56.920853
9782 12:14:56.921327
9783 12:14:56.921690
9784 12:14:56.923666 Starting depthcharge on Spherion...
9785 12:14:56.924126
9786 12:14:56.924493 Wipe memory regions:
9787 12:14:56.924880
9788 12:14:56.927468 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9789 12:14:56.928007 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9790 12:14:56.928463 Setting prompt string to ['asurada:']
9791 12:14:56.928989 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9792 12:14:56.929724 [0x00000040000000, 0x00000054600000)
9793 12:14:57.049981
9794 12:14:57.050535 [0x00000054660000, 0x00000080000000)
9795 12:14:57.309643
9796 12:14:57.310252 [0x000000821a7280, 0x000000ffe64000)
9797 12:14:58.055175
9798 12:14:58.055741 [0x00000100000000, 0x00000140000000)
9799 12:14:58.435646
9800 12:14:58.439035 Initializing XHCI USB controller at 0x11200000.
9801 12:14:59.477299
9802 12:14:59.480501 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9803 12:14:59.481129
9804 12:14:59.481514
9805 12:14:59.481858
9806 12:14:59.482700 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9808 12:14:59.584048 asurada: tftpboot 192.168.201.1 12669512/tftp-deploy-51zf4tfc/kernel/image.itb 12669512/tftp-deploy-51zf4tfc/kernel/cmdline
9809 12:14:59.584769 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9810 12:14:59.585270 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9811 12:14:59.589640 tftpboot 192.168.201.1 12669512/tftp-deploy-51zf4tfc/kernel/image.itp-deploy-51zf4tfc/kernel/cmdline
9812 12:14:59.589725
9813 12:14:59.589791 Waiting for link
9814 12:14:59.750717
9815 12:14:59.751354 R8152: Initializing
9816 12:14:59.751746
9817 12:14:59.753975 Version 9 (ocp_data = 6010)
9818 12:14:59.754548
9819 12:14:59.757201 R8152: Done initializing
9820 12:14:59.757670
9821 12:14:59.758040 Adding net device
9822 12:15:01.880108
9823 12:15:01.880791 done.
9824 12:15:01.881406
9825 12:15:01.881777 MAC: 00:e0:4c:68:03:bd
9826 12:15:01.882116
9827 12:15:01.883465 Sending DHCP discover... done.
9828 12:15:01.883924
9829 12:15:11.588835 Waiting for reply... R8152: Bulk read error 0xffffffbf
9830 12:15:11.589391
9831 12:15:11.591312 Receive failed.
9832 12:15:11.591879
9833 12:15:11.592251 done.
9834 12:15:11.592591
9835 12:15:11.595182 Sending DHCP request... done.
9836 12:15:11.595646
9837 12:15:11.598390 Waiting for reply... done.
9838 12:15:11.598855
9839 12:15:11.601698 My ip is 192.168.201.16
9840 12:15:11.602254
9841 12:15:11.604628 The DHCP server ip is 192.168.201.1
9842 12:15:11.605595
9843 12:15:11.607723 TFTP server IP predefined by user: 192.168.201.1
9844 12:15:11.608287
9845 12:15:11.614566 Bootfile predefined by user: 12669512/tftp-deploy-51zf4tfc/kernel/image.itb
9846 12:15:11.615112
9847 12:15:11.618002 Sending tftp read request... done.
9848 12:15:11.618474
9849 12:15:11.625676 Waiting for the transfer...
9850 12:15:11.626143
9851 12:15:11.942647 00000000 ################################################################
9852 12:15:11.942791
9853 12:15:12.236251 00080000 ################################################################
9854 12:15:12.236392
9855 12:15:12.529800 00100000 ################################################################
9856 12:15:12.529943
9857 12:15:12.810482 00180000 ################################################################
9858 12:15:12.810627
9859 12:15:13.100826 00200000 ################################################################
9860 12:15:13.100966
9861 12:15:13.377749 00280000 ################################################################
9862 12:15:13.377886
9863 12:15:13.653496 00300000 ################################################################
9864 12:15:13.653635
9865 12:15:13.935142 00380000 ################################################################
9866 12:15:13.935282
9867 12:15:14.224253 00400000 ################################################################
9868 12:15:14.224384
9869 12:15:14.519024 00480000 ################################################################
9870 12:15:14.519158
9871 12:15:14.803206 00500000 ################################################################
9872 12:15:14.803345
9873 12:15:15.067008 00580000 ################################################################
9874 12:15:15.067148
9875 12:15:15.318396 00600000 ################################################################
9876 12:15:15.318526
9877 12:15:15.592059 00680000 ################################################################
9878 12:15:15.592232
9879 12:15:15.885637 00700000 ################################################################
9880 12:15:15.885773
9881 12:15:16.147452 00780000 ################################################################
9882 12:15:16.147587
9883 12:15:16.404205 00800000 ################################################################
9884 12:15:16.404338
9885 12:15:16.699510 00880000 ################################################################
9886 12:15:16.699649
9887 12:15:16.995629 00900000 ################################################################
9888 12:15:16.995771
9889 12:15:17.290432 00980000 ################################################################
9890 12:15:17.290577
9891 12:15:17.577185 00a00000 ################################################################
9892 12:15:17.577329
9893 12:15:17.874501 00a80000 ################################################################
9894 12:15:17.874641
9895 12:15:18.149231 00b00000 ################################################################
9896 12:15:18.149371
9897 12:15:18.428333 00b80000 ################################################################
9898 12:15:18.428498
9899 12:15:18.726475 00c00000 ################################################################
9900 12:15:18.726635
9901 12:15:19.022500 00c80000 ################################################################
9902 12:15:19.022640
9903 12:15:19.296000 00d00000 ################################################################
9904 12:15:19.296140
9905 12:15:19.561444 00d80000 ################################################################
9906 12:15:19.561605
9907 12:15:19.824613 00e00000 ################################################################
9908 12:15:19.824790
9909 12:15:20.118182 00e80000 ################################################################
9910 12:15:20.118318
9911 12:15:20.412776 00f00000 ################################################################
9912 12:15:20.412944
9913 12:15:20.693424 00f80000 ################################################################
9914 12:15:20.693574
9915 12:15:20.944765 01000000 ################################################################
9916 12:15:20.944899
9917 12:15:21.195611 01080000 ################################################################
9918 12:15:21.195747
9919 12:15:21.445906 01100000 ################################################################
9920 12:15:21.446039
9921 12:15:21.724206 01180000 ################################################################
9922 12:15:21.724372
9923 12:15:22.021203 01200000 ################################################################
9924 12:15:22.021340
9925 12:15:22.312919 01280000 ################################################################
9926 12:15:22.313056
9927 12:15:22.585934 01300000 ################################################################
9928 12:15:22.586080
9929 12:15:22.867253 01380000 ################################################################
9930 12:15:22.867421
9931 12:15:23.118255 01400000 ################################################################
9932 12:15:23.118415
9933 12:15:23.391735 01480000 ################################################################
9934 12:15:23.391900
9935 12:15:23.684733 01500000 ################################################################
9936 12:15:23.684901
9937 12:15:23.974742 01580000 ################################################################
9938 12:15:23.974903
9939 12:15:24.271907 01600000 ################################################################
9940 12:15:24.272044
9941 12:15:24.552987 01680000 ################################################################
9942 12:15:24.553129
9943 12:15:24.844458 01700000 ################################################################
9944 12:15:24.844607
9945 12:15:25.120067 01780000 ################################################################
9946 12:15:25.120214
9947 12:15:25.382803 01800000 ################################################################
9948 12:15:25.382962
9949 12:15:25.675473 01880000 ################################################################
9950 12:15:25.675637
9951 12:15:25.940877 01900000 ################################################################
9952 12:15:25.941045
9953 12:15:26.191336 01980000 ################################################################
9954 12:15:26.191494
9955 12:15:26.442247 01a00000 ################################################################
9956 12:15:26.442385
9957 12:15:26.693153 01a80000 ################################################################
9958 12:15:26.693290
9959 12:15:26.944862 01b00000 ################################################################
9960 12:15:26.945001
9961 12:15:27.193959 01b80000 ################################################################
9962 12:15:27.194091
9963 12:15:27.444510 01c00000 ################################################################
9964 12:15:27.444670
9965 12:15:27.449439 01c80000 ## done.
9966 12:15:27.449518
9967 12:15:27.453886 The bootfile was 29896130 bytes long.
9968 12:15:27.453974
9969 12:15:27.456677 Sending tftp read request... done.
9970 12:15:27.456782
9971 12:15:27.459980 Waiting for the transfer...
9972 12:15:27.460073
9973 12:15:27.460148 00000000 # done.
9974 12:15:27.460219
9975 12:15:27.469932 Command line loaded dynamically from TFTP file: 12669512/tftp-deploy-51zf4tfc/kernel/cmdline
9976 12:15:27.470111
9977 12:15:27.489669 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12669512/extract-nfsrootfs-zak5hcs0,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9978 12:15:27.489913
9979 12:15:27.493929 Loading FIT.
9980 12:15:27.494182
9981 12:15:27.497112 Image ramdisk-1 has 17799535 bytes.
9982 12:15:27.497404
9983 12:15:27.497577 Image fdt-1 has 47278 bytes.
9984 12:15:27.500747
9985 12:15:27.501072 Image kernel-1 has 12047284 bytes.
9986 12:15:27.501278
9987 12:15:27.510433 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9988 12:15:27.510922
9989 12:15:27.526449 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9990 12:15:27.526959
9991 12:15:27.533732 Choosing best match conf-1 for compat google,spherion-rev3.
9992 12:15:27.537458
9993 12:15:27.541989 Connected to device vid:did:rid of 1ae0:0028:00
9994 12:15:27.548801
9995 12:15:27.551675 tpm_get_response: command 0x17b, return code 0x0
9996 12:15:27.552062
9997 12:15:27.555135 ec_init: CrosEC protocol v3 supported (256, 248)
9998 12:15:27.560142
9999 12:15:27.562881 tpm_cleanup: add release locality here.
10000 12:15:27.563270
10001 12:15:27.563578 Shutting down all USB controllers.
10002 12:15:27.566293
10003 12:15:27.566677 Removing current net device
10004 12:15:27.566982
10005 12:15:27.573384 Exiting depthcharge with code 4 at timestamp: 58891917
10006 12:15:27.573873
10007 12:15:27.575860 LZMA decompressing kernel-1 to 0x821a6718
10008 12:15:27.576242
10009 12:15:27.579312 LZMA decompressing kernel-1 to 0x40000000
10010 12:15:29.077831
10011 12:15:29.078390 jumping to kernel
10012 12:15:29.080596 end: 2.2.4 bootloader-commands (duration 00:00:32) [common]
10013 12:15:29.081188 start: 2.2.5 auto-login-action (timeout 00:03:54) [common]
10014 12:15:29.081601 Setting prompt string to ['Linux version [0-9]']
10015 12:15:29.081983 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10016 12:15:29.082361 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10017 12:15:29.127897
10018 12:15:29.131102 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10019 12:15:29.135507 start: 2.2.5.1 login-action (timeout 00:03:54) [common]
10020 12:15:29.136097 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10021 12:15:29.136513 Setting prompt string to []
10022 12:15:29.136977 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10023 12:15:29.137367 Using line separator: #'\n'#
10024 12:15:29.137702 No login prompt set.
10025 12:15:29.138042 Parsing kernel messages
10026 12:15:29.138349 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10027 12:15:29.138930 [login-action] Waiting for messages, (timeout 00:03:54)
10028 12:15:29.154697 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j93261-arm64-gcc-10-defconfig-arm64-chromebook-cwjwh) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024
10029 12:15:29.157449 [ 0.000000] random: crng init done
10030 12:15:29.163999 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10031 12:15:29.168074 [ 0.000000] efi: UEFI not found.
10032 12:15:29.174070 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10033 12:15:29.184888 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10034 12:15:29.191090 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10035 12:15:29.200628 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10036 12:15:29.206911 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10037 12:15:29.213753 [ 0.000000] printk: bootconsole [mtk8250] enabled
10038 12:15:29.221513 [ 0.000000] NUMA: No NUMA configuration found
10039 12:15:29.226925 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10040 12:15:29.230439 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10041 12:15:29.233581 [ 0.000000] Zone ranges:
10042 12:15:29.240411 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10043 12:15:29.244127 [ 0.000000] DMA32 empty
10044 12:15:29.250580 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10045 12:15:29.254022 [ 0.000000] Movable zone start for each node
10046 12:15:29.256547 [ 0.000000] Early memory node ranges
10047 12:15:29.263331 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10048 12:15:29.270014 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10049 12:15:29.277735 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10050 12:15:29.282799 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10051 12:15:29.289855 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10052 12:15:29.297182 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10053 12:15:29.326842 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10054 12:15:29.333780 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10055 12:15:29.340056 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10056 12:15:29.343365 [ 0.000000] psci: probing for conduit method from DT.
10057 12:15:29.350201 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10058 12:15:29.354175 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10059 12:15:29.360409 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10060 12:15:29.363791 [ 0.000000] psci: SMC Calling Convention v1.2
10061 12:15:29.369736 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10062 12:15:29.373423 [ 0.000000] Detected VIPT I-cache on CPU0
10063 12:15:29.379947 [ 0.000000] CPU features: detected: GIC system register CPU interface
10064 12:15:29.386298 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10065 12:15:29.392968 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10066 12:15:29.400581 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10067 12:15:29.406685 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10068 12:15:29.416595 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10069 12:15:29.419888 [ 0.000000] alternatives: applying boot alternatives
10070 12:15:29.426235 [ 0.000000] Fallback order for Node 0: 0
10071 12:15:29.432761 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10072 12:15:29.435866 [ 0.000000] Policy zone: Normal
10073 12:15:29.458788 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12669512/extract-nfsrootfs-zak5hcs0,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10074 12:15:29.469939 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10075 12:15:29.479833 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10076 12:15:29.485914 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10077 12:15:29.492639 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10078 12:15:29.496153 <6>[ 0.000000] software IO TLB: area num 8.
10079 12:15:29.553277 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10080 12:15:29.633629 <6>[ 0.000000] Memory: 3835460K/4191232K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 323004K reserved, 32768K cma-reserved)
10081 12:15:29.640957 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10082 12:15:29.648085 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10083 12:15:29.650582 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10084 12:15:29.657550 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10085 12:15:29.663391 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10086 12:15:29.666585 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10087 12:15:29.677518 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10088 12:15:29.683300 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10089 12:15:29.689816 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10090 12:15:29.696436 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10091 12:15:29.699727 <6>[ 0.000000] GICv3: 608 SPIs implemented
10092 12:15:29.703453 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10093 12:15:29.709291 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10094 12:15:29.713055 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10095 12:15:29.719662 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10096 12:15:29.733598 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10097 12:15:29.746521 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10098 12:15:29.752369 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10099 12:15:29.760176 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10100 12:15:29.773196 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10101 12:15:29.781062 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10102 12:15:29.787121 <6>[ 0.009184] Console: colour dummy device 80x25
10103 12:15:29.796674 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10104 12:15:29.804334 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10105 12:15:29.807308 <6>[ 0.029252] LSM: Security Framework initializing
10106 12:15:29.813272 <6>[ 0.034197] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10107 12:15:29.823221 <6>[ 0.041804] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10108 12:15:29.830141 <6>[ 0.051087] cblist_init_generic: Setting adjustable number of callback queues.
10109 12:15:29.836320 <6>[ 0.058575] cblist_init_generic: Setting shift to 3 and lim to 1.
10110 12:15:29.846500 <6>[ 0.064953] cblist_init_generic: Setting adjustable number of callback queues.
10111 12:15:29.853402 <6>[ 0.072379] cblist_init_generic: Setting shift to 3 and lim to 1.
10112 12:15:29.855969 <6>[ 0.078781] rcu: Hierarchical SRCU implementation.
10113 12:15:29.863762 <6>[ 0.083827] rcu: Max phase no-delay instances is 1000.
10114 12:15:29.869687 <6>[ 0.090878] EFI services will not be available.
10115 12:15:29.873635 <6>[ 0.095833] smp: Bringing up secondary CPUs ...
10116 12:15:29.881261 <6>[ 0.100909] Detected VIPT I-cache on CPU1
10117 12:15:29.887768 <6>[ 0.100977] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10118 12:15:29.893961 <6>[ 0.101006] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10119 12:15:29.897298 <6>[ 0.101340] Detected VIPT I-cache on CPU2
10120 12:15:29.904010 <6>[ 0.101391] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10121 12:15:29.910976 <6>[ 0.101407] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10122 12:15:29.917702 <6>[ 0.101664] Detected VIPT I-cache on CPU3
10123 12:15:29.924306 <6>[ 0.101710] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10124 12:15:29.930853 <6>[ 0.101724] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10125 12:15:29.933824 <6>[ 0.102027] CPU features: detected: Spectre-v4
10126 12:15:29.940146 <6>[ 0.102034] CPU features: detected: Spectre-BHB
10127 12:15:29.943907 <6>[ 0.102039] Detected PIPT I-cache on CPU4
10128 12:15:29.950540 <6>[ 0.102096] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10129 12:15:29.957616 <6>[ 0.102112] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10130 12:15:29.963707 <6>[ 0.102402] Detected PIPT I-cache on CPU5
10131 12:15:29.970679 <6>[ 0.102465] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10132 12:15:29.977331 <6>[ 0.102484] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10133 12:15:29.980429 <6>[ 0.102764] Detected PIPT I-cache on CPU6
10134 12:15:29.987895 <6>[ 0.102825] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10135 12:15:29.995578 <6>[ 0.102842] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10136 12:15:30.000038 <6>[ 0.103139] Detected PIPT I-cache on CPU7
10137 12:15:30.006345 <6>[ 0.103204] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10138 12:15:30.013747 <6>[ 0.103220] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10139 12:15:30.016497 <6>[ 0.103267] smp: Brought up 1 node, 8 CPUs
10140 12:15:30.022949 <6>[ 0.244557] SMP: Total of 8 processors activated.
10141 12:15:30.026403 <6>[ 0.249477] CPU features: detected: 32-bit EL0 Support
10142 12:15:30.035940 <6>[ 0.254839] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10143 12:15:30.042671 <6>[ 0.263640] CPU features: detected: Common not Private translations
10144 12:15:30.049736 <6>[ 0.270155] CPU features: detected: CRC32 instructions
10145 12:15:30.053307 <6>[ 0.275540] CPU features: detected: RCpc load-acquire (LDAPR)
10146 12:15:30.059342 <6>[ 0.281500] CPU features: detected: LSE atomic instructions
10147 12:15:30.065772 <6>[ 0.287281] CPU features: detected: Privileged Access Never
10148 12:15:30.072439 <6>[ 0.293061] CPU features: detected: RAS Extension Support
10149 12:15:30.079669 <6>[ 0.298670] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10150 12:15:30.082736 <6>[ 0.305887] CPU: All CPU(s) started at EL2
10151 12:15:30.088686 <6>[ 0.310204] alternatives: applying system-wide alternatives
10152 12:15:30.097383 <6>[ 0.320115] devtmpfs: initialized
10153 12:15:30.112553 <6>[ 0.328319] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10154 12:15:30.119177 <6>[ 0.338278] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10155 12:15:30.125972 <6>[ 0.346515] pinctrl core: initialized pinctrl subsystem
10156 12:15:30.129136 <6>[ 0.353158] DMI not present or invalid.
10157 12:15:30.135495 <6>[ 0.357560] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10158 12:15:30.145080 <6>[ 0.364420] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10159 12:15:30.151851 <6>[ 0.371867] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10160 12:15:30.161687 <6>[ 0.379958] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10161 12:15:30.165052 <6>[ 0.388120] audit: initializing netlink subsys (disabled)
10162 12:15:30.175184 <5>[ 0.393818] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10163 12:15:30.182078 <6>[ 0.394525] thermal_sys: Registered thermal governor 'step_wise'
10164 12:15:30.188558 <6>[ 0.401785] thermal_sys: Registered thermal governor 'power_allocator'
10165 12:15:30.191905 <6>[ 0.408042] cpuidle: using governor menu
10166 12:15:30.198391 <6>[ 0.419003] NET: Registered PF_QIPCRTR protocol family
10167 12:15:30.204697 <6>[ 0.424518] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10168 12:15:30.208153 <6>[ 0.431619] ASID allocator initialised with 32768 entries
10169 12:15:30.215611 <6>[ 0.438162] Serial: AMBA PL011 UART driver
10170 12:15:30.224765 <4>[ 0.446903] Trying to register duplicate clock ID: 134
10171 12:15:30.278113 <6>[ 0.504023] KASLR enabled
10172 12:15:30.292352 <6>[ 0.511688] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10173 12:15:30.299987 <6>[ 0.518699] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10174 12:15:30.306441 <6>[ 0.525188] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10175 12:15:30.312520 <6>[ 0.532191] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10176 12:15:30.319998 <6>[ 0.538679] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10177 12:15:30.325407 <6>[ 0.545683] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10178 12:15:30.332018 <6>[ 0.552170] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10179 12:15:30.338459 <6>[ 0.559176] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10180 12:15:30.341874 <6>[ 0.566592] ACPI: Interpreter disabled.
10181 12:15:30.350774 <6>[ 0.572965] iommu: Default domain type: Translated
10182 12:15:30.357843 <6>[ 0.578115] iommu: DMA domain TLB invalidation policy: strict mode
10183 12:15:30.360241 <5>[ 0.584767] SCSI subsystem initialized
10184 12:15:30.367156 <6>[ 0.589013] usbcore: registered new interface driver usbfs
10185 12:15:30.373548 <6>[ 0.594744] usbcore: registered new interface driver hub
10186 12:15:30.376949 <6>[ 0.600298] usbcore: registered new device driver usb
10187 12:15:30.383878 <6>[ 0.606407] pps_core: LinuxPPS API ver. 1 registered
10188 12:15:30.393850 <6>[ 0.611599] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10189 12:15:30.397160 <6>[ 0.620945] PTP clock support registered
10190 12:15:30.400351 <6>[ 0.625186] EDAC MC: Ver: 3.0.0
10191 12:15:30.408205 <6>[ 0.630357] FPGA manager framework
10192 12:15:30.414360 <6>[ 0.634032] Advanced Linux Sound Architecture Driver Initialized.
10193 12:15:30.417545 <6>[ 0.640734] vgaarb: loaded
10194 12:15:30.424974 <6>[ 0.643882] clocksource: Switched to clocksource arch_sys_counter
10195 12:15:30.427771 <5>[ 0.650326] VFS: Disk quotas dquot_6.6.0
10196 12:15:30.434443 <6>[ 0.654510] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10197 12:15:30.438161 <6>[ 0.661702] pnp: PnP ACPI: disabled
10198 12:15:30.446943 <6>[ 0.668362] NET: Registered PF_INET protocol family
10199 12:15:30.452947 <6>[ 0.673728] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10200 12:15:30.464574 <6>[ 0.683742] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10201 12:15:30.474428 <6>[ 0.692526] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10202 12:15:30.481941 <6>[ 0.700494] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10203 12:15:30.487238 <6>[ 0.708896] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10204 12:15:30.499019 <6>[ 0.717557] TCP: Hash tables configured (established 32768 bind 32768)
10205 12:15:30.505045 <6>[ 0.724357] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10206 12:15:30.511486 <6>[ 0.731377] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10207 12:15:30.518995 <6>[ 0.738901] NET: Registered PF_UNIX/PF_LOCAL protocol family
10208 12:15:30.524480 <6>[ 0.745040] RPC: Registered named UNIX socket transport module.
10209 12:15:30.528388 <6>[ 0.751194] RPC: Registered udp transport module.
10210 12:15:30.534762 <6>[ 0.756125] RPC: Registered tcp transport module.
10211 12:15:30.543409 <6>[ 0.761056] RPC: Registered tcp NFSv4.1 backchannel transport module.
10212 12:15:30.545204 <6>[ 0.767723] PCI: CLS 0 bytes, default 64
10213 12:15:30.548324 <6>[ 0.772082] Unpacking initramfs...
10214 12:15:30.557873 <6>[ 0.775800] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10215 12:15:30.564484 <6>[ 0.784435] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10216 12:15:30.570897 <6>[ 0.793268] kvm [1]: IPA Size Limit: 40 bits
10217 12:15:30.574846 <6>[ 0.797799] kvm [1]: GICv3: no GICV resource entry
10218 12:15:30.581133 <6>[ 0.802819] kvm [1]: disabling GICv2 emulation
10219 12:15:30.588886 <6>[ 0.807504] kvm [1]: GIC system register CPU interface enabled
10220 12:15:30.591463 <6>[ 0.813671] kvm [1]: vgic interrupt IRQ18
10221 12:15:30.597589 <6>[ 0.818033] kvm [1]: VHE mode initialized successfully
10222 12:15:30.600953 <5>[ 0.824447] Initialise system trusted keyrings
10223 12:15:30.607142 <6>[ 0.829292] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10224 12:15:30.617073 <6>[ 0.839340] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10225 12:15:30.625056 <5>[ 0.845726] NFS: Registering the id_resolver key type
10226 12:15:30.626784 <5>[ 0.851029] Key type id_resolver registered
10227 12:15:30.633200 <5>[ 0.855443] Key type id_legacy registered
10228 12:15:30.639747 <6>[ 0.859721] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10229 12:15:30.647160 <6>[ 0.866642] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10230 12:15:30.653365 <6>[ 0.874378] 9p: Installing v9fs 9p2000 file system support
10231 12:15:30.690200 <5>[ 0.912826] Key type asymmetric registered
10232 12:15:30.693454 <5>[ 0.917161] Asymmetric key parser 'x509' registered
10233 12:15:30.704022 <6>[ 0.922309] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10234 12:15:30.706781 <6>[ 0.929924] io scheduler mq-deadline registered
10235 12:15:30.709662 <6>[ 0.934686] io scheduler kyber registered
10236 12:15:30.730493 <6>[ 0.951714] EINJ: ACPI disabled.
10237 12:15:30.760821 <4>[ 0.976593] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10238 12:15:30.770592 <4>[ 0.987231] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10239 12:15:30.787307 <6>[ 1.008197] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10240 12:15:30.793415 <6>[ 1.016210] printk: console [ttyS0] disabled
10241 12:15:30.821650 <6>[ 1.040853] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10242 12:15:30.828288 <6>[ 1.050329] printk: console [ttyS0] enabled
10243 12:15:30.831572 <6>[ 1.050329] printk: console [ttyS0] enabled
10244 12:15:30.839213 <6>[ 1.059226] printk: bootconsole [mtk8250] disabled
10245 12:15:30.841235 <6>[ 1.059226] printk: bootconsole [mtk8250] disabled
10246 12:15:30.848037 <6>[ 1.070460] SuperH (H)SCI(F) driver initialized
10247 12:15:30.851737 <6>[ 1.075727] msm_serial: driver initialized
10248 12:15:30.865128 <6>[ 1.084632] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10249 12:15:30.875637 <6>[ 1.093177] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10250 12:15:30.881870 <6>[ 1.101720] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10251 12:15:30.892098 <6>[ 1.110349] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10252 12:15:30.901666 <6>[ 1.119056] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10253 12:15:30.909348 <6>[ 1.127776] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10254 12:15:30.918144 <6>[ 1.136317] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10255 12:15:30.925104 <6>[ 1.145115] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10256 12:15:30.935101 <6>[ 1.153659] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10257 12:15:30.947016 <6>[ 1.169198] loop: module loaded
10258 12:15:30.953732 <6>[ 1.175147] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10259 12:15:30.976012 <4>[ 1.198541] mtk-pmic-keys: Failed to locate of_node [id: -1]
10260 12:15:30.982793 <6>[ 1.205745] megasas: 07.719.03.00-rc1
10261 12:15:30.992845 <6>[ 1.215523] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10262 12:15:31.001651 <6>[ 1.223250] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10263 12:15:31.017315 <6>[ 1.239693] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10264 12:15:31.073216 <6>[ 1.288536] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10265 12:15:31.283775 <6>[ 1.506489] Freeing initrd memory: 17380K
10266 12:15:31.294267 <6>[ 1.516540] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10267 12:15:31.305063 <6>[ 1.527577] tun: Universal TUN/TAP device driver, 1.6
10268 12:15:31.309544 <6>[ 1.533648] thunder_xcv, ver 1.0
10269 12:15:31.311458 <6>[ 1.537151] thunder_bgx, ver 1.0
10270 12:15:31.314959 <6>[ 1.540649] nicpf, ver 1.0
10271 12:15:31.325307 <6>[ 1.544668] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10272 12:15:31.328990 <6>[ 1.552143] hns3: Copyright (c) 2017 Huawei Corporation.
10273 12:15:31.335118 <6>[ 1.557733] hclge is initializing
10274 12:15:31.338620 <6>[ 1.561313] e1000: Intel(R) PRO/1000 Network Driver
10275 12:15:31.345908 <6>[ 1.566443] e1000: Copyright (c) 1999-2006 Intel Corporation.
10276 12:15:31.348959 <6>[ 1.572454] e1000e: Intel(R) PRO/1000 Network Driver
10277 12:15:31.355028 <6>[ 1.577670] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10278 12:15:31.363142 <6>[ 1.583854] igb: Intel(R) Gigabit Ethernet Network Driver
10279 12:15:31.369400 <6>[ 1.589504] igb: Copyright (c) 2007-2014 Intel Corporation.
10280 12:15:31.375522 <6>[ 1.595340] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10281 12:15:31.381454 <6>[ 1.601857] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10282 12:15:31.385078 <6>[ 1.608323] sky2: driver version 1.30
10283 12:15:31.391237 <6>[ 1.613302] VFIO - User Level meta-driver version: 0.3
10284 12:15:31.398837 <6>[ 1.621505] usbcore: registered new interface driver usb-storage
10285 12:15:31.405108 <6>[ 1.627954] usbcore: registered new device driver onboard-usb-hub
10286 12:15:31.414575 <6>[ 1.637125] mt6397-rtc mt6359-rtc: registered as rtc0
10287 12:15:31.424769 <6>[ 1.642592] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-31T12:15:34 UTC (1706703334)
10288 12:15:31.428674 <6>[ 1.652161] i2c_dev: i2c /dev entries driver
10289 12:15:31.444673 <6>[ 1.663897] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10290 12:15:31.464864 <6>[ 1.686845] cpu cpu0: EM: created perf domain
10291 12:15:31.467334 <6>[ 1.691751] cpu cpu4: EM: created perf domain
10292 12:15:31.474673 <6>[ 1.697268] sdhci: Secure Digital Host Controller Interface driver
10293 12:15:31.481562 <6>[ 1.703701] sdhci: Copyright(c) Pierre Ossman
10294 12:15:31.488813 <6>[ 1.708609] Synopsys Designware Multimedia Card Interface Driver
10295 12:15:31.494761 <6>[ 1.715191] sdhci-pltfm: SDHCI platform and OF driver helper
10296 12:15:31.497800 <6>[ 1.715273] mmc0: CQHCI version 5.10
10297 12:15:31.504531 <6>[ 1.725230] ledtrig-cpu: registered to indicate activity on CPUs
10298 12:15:31.513210 <6>[ 1.732270] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10299 12:15:31.518570 <6>[ 1.739295] usbcore: registered new interface driver usbhid
10300 12:15:31.521285 <6>[ 1.745116] usbhid: USB HID core driver
10301 12:15:31.527848 <6>[ 1.749326] spi_master spi0: will run message pump with realtime priority
10302 12:15:31.569069 <6>[ 1.785337] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10303 12:15:31.588412 <6>[ 1.801777] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10304 12:15:31.592086 <6>[ 1.816846] mmc0: Command Queue Engine enabled
10305 12:15:31.598725 <6>[ 1.817118] cros-ec-spi spi0.0: Chrome EC device registered
10306 12:15:31.605432 <6>[ 1.821588] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10307 12:15:31.612353 <6>[ 1.834634] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10308 12:15:31.622251 <6>[ 1.839612] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10309 12:15:31.625687 <6>[ 1.844619] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10310 12:15:31.632086 <6>[ 1.849822] NET: Registered PF_PACKET protocol family
10311 12:15:31.638912 <6>[ 1.855972] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10312 12:15:31.642116 <6>[ 1.860235] 9pnet: Installing 9P2000 support
10313 12:15:31.648400 <6>[ 1.866055] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10314 12:15:31.652020 <5>[ 1.869919] Key type dns_resolver registered
10315 12:15:31.658385 <6>[ 1.875778] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10316 12:15:31.662093 <6>[ 1.880156] registered taskstats version 1
10317 12:15:31.668936 <5>[ 1.890542] Loading compiled-in X.509 certificates
10318 12:15:31.695369 <4>[ 1.911983] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10319 12:15:31.706423 <4>[ 1.922738] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10320 12:15:31.712305 <3>[ 1.933267] debugfs: File 'uA_load' in directory '/' already present!
10321 12:15:31.718661 <3>[ 1.940011] debugfs: File 'min_uV' in directory '/' already present!
10322 12:15:31.726133 <3>[ 1.946624] debugfs: File 'max_uV' in directory '/' already present!
10323 12:15:31.732222 <3>[ 1.953282] debugfs: File 'constraint_flags' in directory '/' already present!
10324 12:15:31.743102 <3>[ 1.962862] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10325 12:15:31.752108 <6>[ 1.975465] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10326 12:15:31.759173 <6>[ 1.982291] xhci-mtk 11200000.usb: xHCI Host Controller
10327 12:15:31.765853 <6>[ 1.987798] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10328 12:15:31.776284 <6>[ 1.995632] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10329 12:15:31.783570 <6>[ 2.005071] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10330 12:15:31.789899 <6>[ 2.011145] xhci-mtk 11200000.usb: xHCI Host Controller
10331 12:15:31.796059 <6>[ 2.016621] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10332 12:15:31.803000 <6>[ 2.024267] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10333 12:15:31.809658 <6>[ 2.031923] hub 1-0:1.0: USB hub found
10334 12:15:31.812640 <6>[ 2.035937] hub 1-0:1.0: 1 port detected
10335 12:15:31.818829 <6>[ 2.040201] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10336 12:15:31.825861 <6>[ 2.048763] hub 2-0:1.0: USB hub found
10337 12:15:31.829192 <6>[ 2.052765] hub 2-0:1.0: 1 port detected
10338 12:15:31.836217 <6>[ 2.059117] mtk-msdc 11f70000.mmc: Got CD GPIO
10339 12:15:31.853752 <6>[ 2.072983] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10340 12:15:31.860157 <6>[ 2.081041] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10341 12:15:31.870391 <4>[ 2.088961] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10342 12:15:31.879845 <6>[ 2.098476] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10343 12:15:31.887140 <6>[ 2.106553] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10344 12:15:31.893477 <6>[ 2.114558] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10345 12:15:31.904144 <6>[ 2.122471] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10346 12:15:31.911190 <6>[ 2.130287] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10347 12:15:31.919945 <6>[ 2.138103] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10348 12:15:31.930463 <6>[ 2.148462] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10349 12:15:31.936908 <6>[ 2.156820] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10350 12:15:31.946755 <6>[ 2.165164] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10351 12:15:31.953332 <6>[ 2.173501] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10352 12:15:31.963234 <6>[ 2.181839] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10353 12:15:31.969597 <6>[ 2.190178] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10354 12:15:31.979379 <6>[ 2.198515] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10355 12:15:31.986691 <6>[ 2.206854] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10356 12:15:31.995832 <6>[ 2.215191] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10357 12:15:32.002467 <6>[ 2.223528] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10358 12:15:32.012825 <6>[ 2.231867] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10359 12:15:32.019411 <6>[ 2.240204] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10360 12:15:32.029281 <6>[ 2.248541] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10361 12:15:32.039492 <6>[ 2.256887] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10362 12:15:32.046004 <6>[ 2.265227] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10363 12:15:32.052162 <6>[ 2.273958] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10364 12:15:32.059299 <6>[ 2.281076] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10365 12:15:32.065682 <6>[ 2.287805] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10366 12:15:32.072203 <6>[ 2.294529] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10367 12:15:32.082074 <6>[ 2.301433] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10368 12:15:32.089878 <6>[ 2.308275] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10369 12:15:32.098850 <6>[ 2.317410] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10370 12:15:32.108609 <6>[ 2.326527] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10371 12:15:32.118768 <6>[ 2.335820] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10372 12:15:32.128421 <6>[ 2.345289] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10373 12:15:32.135340 <6>[ 2.354755] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10374 12:15:32.144760 <6>[ 2.363874] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10375 12:15:32.154941 <6>[ 2.373342] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10376 12:15:32.165505 <6>[ 2.382460] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10377 12:15:32.174256 <6>[ 2.391754] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10378 12:15:32.184752 <6>[ 2.401913] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10379 12:15:32.194298 <6>[ 2.413803] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10380 12:15:32.200862 <6>[ 2.423456] Trying to probe devices needed for running init ...
10381 12:15:32.240995 <6>[ 2.460152] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10382 12:15:32.395575 <6>[ 2.618143] hub 1-1:1.0: USB hub found
10383 12:15:32.399612 <6>[ 2.622643] hub 1-1:1.0: 4 ports detected
10384 12:15:32.409154 <6>[ 2.631312] hub 1-1:1.0: USB hub found
10385 12:15:32.412196 <6>[ 2.635681] hub 1-1:1.0: 4 ports detected
10386 12:15:32.521332 <6>[ 2.740427] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10387 12:15:32.546979 <6>[ 2.769188] hub 2-1:1.0: USB hub found
10388 12:15:32.550438 <6>[ 2.773657] hub 2-1:1.0: 3 ports detected
10389 12:15:32.558568 <6>[ 2.780787] hub 2-1:1.0: USB hub found
10390 12:15:32.562867 <6>[ 2.785270] hub 2-1:1.0: 3 ports detected
10391 12:15:32.738009 <6>[ 2.956195] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10392 12:15:32.868355 <6>[ 3.091143] hub 1-1.4:1.0: USB hub found
10393 12:15:32.871408 <6>[ 3.095636] hub 1-1.4:1.0: 2 ports detected
10394 12:15:32.880003 <6>[ 3.102855] hub 1-1.4:1.0: USB hub found
10395 12:15:32.883315 <6>[ 3.107490] hub 1-1.4:1.0: 2 ports detected
10396 12:15:32.948926 <6>[ 3.168194] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10397 12:15:33.180864 <6>[ 3.400195] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10398 12:15:33.372142 <6>[ 3.592161] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10399 12:15:44.481807 <6>[ 14.709174] ALSA device list:
10400 12:15:44.488315 <6>[ 14.712473] No soundcards found.
10401 12:15:44.495613 <6>[ 14.720289] Freeing unused kernel memory: 8448K
10402 12:15:44.499467 <6>[ 14.725348] Run /init as init process
10403 12:15:44.509905 Loading, please wait...
10404 12:15:44.531485 Starting version 247.3-7+deb11u2
10405 12:15:44.711946 <6>[ 14.932764] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10406 12:15:44.722026 <6>[ 14.946431] remoteproc remoteproc0: scp is available
10407 12:15:44.728223 <6>[ 14.952214] remoteproc remoteproc0: powering up scp
10408 12:15:44.735392 <6>[ 14.957394] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10409 12:15:44.741861 <6>[ 14.965849] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10410 12:15:44.752296 <3>[ 14.973594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10411 12:15:44.758983 <3>[ 14.981854] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10412 12:15:44.768661 <3>[ 14.989996] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10413 12:15:44.776092 <6>[ 14.993481] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10414 12:15:44.781853 <6>[ 15.004004] usbcore: registered new device driver r8152-cfgselector
10415 12:15:44.791825 <6>[ 15.005881] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10416 12:15:44.798950 <3>[ 15.012952] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10417 12:15:44.806325 <4>[ 15.013138] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10418 12:15:44.815064 <6>[ 15.020897] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10419 12:15:44.825638 <3>[ 15.029122] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10420 12:15:44.831366 <4>[ 15.038136] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10421 12:15:44.835084 <6>[ 15.038670] mc: Linux media interface: v0.10
10422 12:15:44.841479 <6>[ 15.040574] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10423 12:15:44.853094 <3>[ 15.045072] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10424 12:15:44.858753 <3>[ 15.045089] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10425 12:15:44.868300 <3>[ 15.045106] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10426 12:15:44.875596 <3>[ 15.045292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10427 12:15:44.882516 <6>[ 15.062098] videodev: Linux video capture interface: v2.00
10428 12:15:44.889035 <3>[ 15.065137] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10429 12:15:44.898831 <4>[ 15.065266] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10430 12:15:44.901929 <4>[ 15.065266] Fallback method does not support PEC.
10431 12:15:44.912035 <3>[ 15.079852] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10432 12:15:44.919142 <3>[ 15.080846] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10433 12:15:44.928251 <3>[ 15.080855] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10434 12:15:44.935252 <3>[ 15.080977] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10435 12:15:44.944982 <6>[ 15.096870] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10436 12:15:44.952281 <6>[ 15.096874] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10437 12:15:44.958523 <3>[ 15.097035] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10438 12:15:44.965187 <6>[ 15.105128] remoteproc remoteproc0: remote processor scp is now up
10439 12:15:44.974780 <3>[ 15.108668] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10440 12:15:44.981698 <3>[ 15.110847] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10441 12:15:44.991397 <3>[ 15.110852] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10442 12:15:44.998251 <6>[ 15.111769] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10443 12:15:45.007661 <6>[ 15.112986] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10444 12:15:45.014708 <6>[ 15.120400] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10445 12:15:45.024412 <3>[ 15.132559] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10446 12:15:45.031232 <3>[ 15.132582] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10447 12:15:45.040987 <6>[ 15.152972] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10448 12:15:45.048700 <6>[ 15.157293] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10449 12:15:45.054217 <6>[ 15.157296] pci_bus 0000:00: root bus resource [bus 00-ff]
10450 12:15:45.061319 <6>[ 15.157301] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10451 12:15:45.071900 <6>[ 15.157303] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10452 12:15:45.077959 <6>[ 15.157327] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10453 12:15:45.086874 <6>[ 15.157339] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10454 12:15:45.090290 <6>[ 15.157405] pci 0000:00:00.0: supports D1 D2
10455 12:15:45.097298 <6>[ 15.157408] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10456 12:15:45.103727 <6>[ 15.158250] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10457 12:15:45.113410 <6>[ 15.158697] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10458 12:15:45.123672 <6>[ 15.165990] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10459 12:15:45.135338 <4>[ 15.169123] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10460 12:15:45.139942 <4>[ 15.169129] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10461 12:15:45.146834 <6>[ 15.174230] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10462 12:15:45.150525 <6>[ 15.213289] Bluetooth: Core ver 2.22
10463 12:15:45.156576 <6>[ 15.220791] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10464 12:15:45.163042 <6>[ 15.224262] r8152 2-1.3:1.0 eth0: v1.12.13
10465 12:15:45.170887 <6>[ 15.224350] usbcore: registered new interface driver r8152
10466 12:15:45.173030 <6>[ 15.229290] NET: Registered PF_BLUETOOTH protocol family
10467 12:15:45.179911 <6>[ 15.237413] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10468 12:15:45.186088 <6>[ 15.245639] Bluetooth: HCI device and connection manager initialized
10469 12:15:45.193171 <6>[ 15.246124] usbcore: registered new interface driver cdc_ether
10470 12:15:45.199698 <6>[ 15.246545] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10471 12:15:45.212681 <6>[ 15.247552] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10472 12:15:45.219386 <6>[ 15.247638] usbcore: registered new interface driver uvcvideo
10473 12:15:45.226266 <6>[ 15.253728] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10474 12:15:45.232533 <6>[ 15.261809] Bluetooth: HCI socket layer initialized
10475 12:15:45.239098 <6>[ 15.262064] usbcore: registered new interface driver r8153_ecm
10476 12:15:45.242301 <6>[ 15.271988] pci 0000:01:00.0: supports D1 D2
10477 12:15:45.249642 <6>[ 15.274624] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10478 12:15:45.255884 <6>[ 15.278729] Bluetooth: L2CAP socket layer initialized
10479 12:15:45.262683 <6>[ 15.284460] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10480 12:15:45.268628 <6>[ 15.284971] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10481 12:15:45.272186 <6>[ 15.291612] Bluetooth: SCO socket layer initialized
10482 12:15:45.278682 <6>[ 15.316070] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10483 12:15:45.285195 <6>[ 15.388377] usbcore: registered new interface driver btusb
10484 12:15:45.295361 <4>[ 15.389404] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10485 12:15:45.301968 <3>[ 15.389423] Bluetooth: hci0: Failed to load firmware file (-2)
10486 12:15:45.308078 <3>[ 15.389429] Bluetooth: hci0: Failed to set up firmware (-2)
10487 12:15:45.318841 <4>[ 15.389439] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10488 12:15:45.324376 <6>[ 15.392174] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10489 12:15:45.334548 <6>[ 15.555567] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10490 12:15:45.341536 <6>[ 15.563570] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10491 12:15:45.351571 <6>[ 15.571574] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10492 12:15:45.357714 <6>[ 15.579574] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10493 12:15:45.364376 <6>[ 15.587573] pci 0000:00:00.0: PCI bridge to [bus 01]
10494 12:15:45.371725 <6>[ 15.592788] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10495 12:15:45.378278 <6>[ 15.600909] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10496 12:15:45.384887 <6>[ 15.607714] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10497 12:15:45.390844 <6>[ 15.614385] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10498 12:15:45.406514 <5>[ 15.627636] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10499 12:15:45.424341 <5>[ 15.645896] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10500 12:15:45.431143 <5>[ 15.653156] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10501 12:15:45.440701 <4>[ 15.661587] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10502 12:15:45.444039 <6>[ 15.670499] cfg80211: failed to load regulatory.db
10503 12:15:45.486650 <6>[ 15.708377] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10504 12:15:45.493898 <6>[ 15.715866] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10505 12:15:45.517969 <6>[ 15.742480] mt7921e 0000:01:00.0: ASIC revision: 79610010
10506 12:15:45.622405 <6>[ 15.843251] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10507 12:15:45.624976 <6>[ 15.843251]
10508 12:15:45.628939 Begin: Loading essential drivers ... done.
10509 12:15:45.631923 Begin: Running /scripts/init-premount ... done.
10510 12:15:45.638685 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10511 12:15:45.648319 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10512 12:15:45.651555 Device /sys/class/net/enx00e04c6803bd found
10513 12:15:45.651655 done.
10514 12:15:45.722405 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10515 12:15:45.892282 <6>[ 16.113759] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10516 12:15:46.675759 <6>[ 16.900618] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10517 12:15:46.731678 <6>[ 16.956383] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10518 12:15:46.918072 IP-Config: no response after 2 secs - giving up
10519 12:15:46.951928 IP-Config: wlp1s0 hardware address 74:4c:a1:92:35:3b mtu 1500 DHCP
10520 12:15:47.662311 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10521 12:15:47.673433 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10522 12:15:47.679429 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10523 12:15:47.685714 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10524 12:15:47.693001 host : mt8192-asurada-spherion-r0-cbg-4
10525 12:15:47.699588 domain : lava-rack
10526 12:15:47.707330 rootserver: 192.168.201.1 rootpath:
10527 12:15:47.707757 filename :
10528 12:15:47.770389 done.
10529 12:15:47.777097 Begin: Running /scripts/nfs-bottom ... done.
10530 12:15:47.792845 Begin: Running /scripts/init-bottom ... done.
10531 12:15:48.943200 <6>[ 19.168063] NET: Registered PF_INET6 protocol family
10532 12:15:48.950853 <6>[ 19.175568] Segment Routing with IPv6
10533 12:15:48.953354 <6>[ 19.179581] In-situ OAM (IOAM) with IPv6
10534 12:15:49.062925 <30>[ 19.267750] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10535 12:15:49.068864 <30>[ 19.292182] systemd[1]: Detected architecture arm64.
10536 12:15:49.087509
10537 12:15:49.090462 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10538 12:15:49.090999
10539 12:15:49.105711 <30>[ 19.330613] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10540 12:15:49.870425 <30>[ 20.092214] systemd[1]: Queued start job for default target Graphical Interface.
10541 12:15:49.897015 <30>[ 20.122469] systemd[1]: Created slice system-getty.slice.
10542 12:15:49.903529 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10543 12:15:49.920443 <30>[ 20.145564] systemd[1]: Created slice system-modprobe.slice.
10544 12:15:49.927020 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10545 12:15:49.944976 <30>[ 20.169424] systemd[1]: Created slice system-serial\x2dgetty.slice.
10546 12:15:49.954529 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10547 12:15:49.968793 <30>[ 20.193213] systemd[1]: Created slice User and Session Slice.
10548 12:15:49.974569 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10549 12:15:49.995621 <30>[ 20.216998] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10550 12:15:50.005484 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10551 12:15:50.023472 <30>[ 20.244923] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10552 12:15:50.030201 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10553 12:15:50.054227 <30>[ 20.272324] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10554 12:15:50.060842 <30>[ 20.284471] systemd[1]: Reached target Local Encrypted Volumes.
10555 12:15:50.067220 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10556 12:15:50.084700 <30>[ 20.308749] systemd[1]: Reached target Paths.
10557 12:15:50.086918 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10558 12:15:50.103852 <30>[ 20.328162] systemd[1]: Reached target Remote File Systems.
10559 12:15:50.109880 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10560 12:15:50.128988 <30>[ 20.352542] systemd[1]: Reached target Slices.
10561 12:15:50.134170 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10562 12:15:50.147607 <30>[ 20.372191] systemd[1]: Reached target Swap.
10563 12:15:50.150500 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10564 12:15:50.171482 <30>[ 20.392663] systemd[1]: Listening on initctl Compatibility Named Pipe.
10565 12:15:50.177544 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10566 12:15:50.183911 <30>[ 20.408780] systemd[1]: Listening on Journal Audit Socket.
10567 12:15:50.190841 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10568 12:15:50.208094 <30>[ 20.433403] systemd[1]: Listening on Journal Socket (/dev/log).
10569 12:15:50.214606 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10570 12:15:50.232165 <30>[ 20.456724] systemd[1]: Listening on Journal Socket.
10571 12:15:50.237767 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10572 12:15:50.257336 <30>[ 20.477611] systemd[1]: Listening on Network Service Netlink Socket.
10573 12:15:50.264031 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10574 12:15:50.277202 <30>[ 20.502650] systemd[1]: Listening on udev Control Socket.
10575 12:15:50.283989 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10576 12:15:50.299228 <30>[ 20.524600] systemd[1]: Listening on udev Kernel Socket.
10577 12:15:50.305978 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10578 12:15:50.347712 <30>[ 20.572227] systemd[1]: Mounting Huge Pages File System...
10579 12:15:50.353911 Mounting [0;1;39mHuge Pages File System[0m...
10580 12:15:50.371267 <30>[ 20.596478] systemd[1]: Mounting POSIX Message Queue File System...
10581 12:15:50.378009 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10582 12:15:50.400216 <30>[ 20.624590] systemd[1]: Mounting Kernel Debug File System...
10583 12:15:50.406447 Mounting [0;1;39mKernel Debug File System[0m...
10584 12:15:50.422599 <30>[ 20.644641] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10585 12:15:50.444383 <30>[ 20.666129] systemd[1]: Starting Create list of static device nodes for the current kernel...
10586 12:15:50.450854 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10587 12:15:50.471722 <30>[ 20.697263] systemd[1]: Starting Load Kernel Module configfs...
10588 12:15:50.478813 Starting [0;1;39mLoad Kernel Module configfs[0m...
10589 12:15:50.499913 <30>[ 20.724978] systemd[1]: Starting Load Kernel Module drm...
10590 12:15:50.506094 Starting [0;1;39mLoad Kernel Module drm[0m...
10591 12:15:50.522143 <30>[ 20.747684] systemd[1]: Starting Load Kernel Module fuse...
10592 12:15:50.528496 Starting [0;1;39mLoad Kernel Module fuse[0m...
10593 12:15:50.560708 <6>[ 20.785996] fuse: init (API version 7.37)
10594 12:15:50.570766 <30>[ 20.787301] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10595 12:15:50.608056 <30>[ 20.832906] systemd[1]: Starting Journal Service...
10596 12:15:50.614877 Starting [0;1;39mJournal Service[0m...
10597 12:15:50.637818 <30>[ 20.863008] systemd[1]: Starting Load Kernel Modules...
10598 12:15:50.644417 Starting [0;1;39mLoad Kernel Modules[0m...
10599 12:15:50.665842 <30>[ 20.888166] systemd[1]: Starting Remount Root and Kernel File Systems...
10600 12:15:50.673390 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10601 12:15:50.690123 <30>[ 20.915308] systemd[1]: Starting Coldplug All udev Devices...
10602 12:15:50.696600 Starting [0;1;39mColdplug All udev Devices[0m...
10603 12:15:50.716847 <30>[ 20.941675] systemd[1]: Mounted Huge Pages File System.
10604 12:15:50.723118 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10605 12:15:50.739010 <30>[ 20.964396] systemd[1]: Mounted POSIX Message Queue File System.
10606 12:15:50.746239 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10607 12:15:50.763371 <30>[ 20.988581] systemd[1]: Mounted Kernel Debug File System.
10608 12:15:50.769452 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10609 12:15:50.790104 <3>[ 21.012546] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10610 12:15:50.800285 <30>[ 21.013284] systemd[1]: Finished Create list of static device nodes for the current kernel.
10611 12:15:50.807552 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10612 12:15:50.820688 <3>[ 21.042866] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10613 12:15:50.827923 <30>[ 21.052822] systemd[1]: modprobe@configfs.service: Succeeded.
10614 12:15:50.834794 <30>[ 21.059729] systemd[1]: Finished Load Kernel Module configfs.
10615 12:15:50.841454 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10616 12:15:50.860935 <30>[ 21.085490] systemd[1]: modprobe@drm.service: Succeeded.
10617 12:15:50.870265 <3>[ 21.090291] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10618 12:15:50.874269 <30>[ 21.091801] systemd[1]: Finished Load Kernel Module drm.
10619 12:15:50.880401 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10620 12:15:50.899026 <3>[ 21.120188] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10621 12:15:50.904758 <30>[ 21.121122] systemd[1]: modprobe@fuse.service: Succeeded.
10622 12:15:50.911433 <30>[ 21.136022] systemd[1]: Finished Load Kernel Module fuse.
10623 12:15:50.918395 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10624 12:15:50.928759 <3>[ 21.148673] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10625 12:15:50.935136 <30>[ 21.159316] systemd[1]: Finished Load Kernel Modules.
10626 12:15:50.941946 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10627 12:15:50.956873 <3>[ 21.178779] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10628 12:15:50.967295 <30>[ 21.189387] systemd[1]: Finished Remount Root and Kernel File Systems.
10629 12:15:50.974526 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10630 12:15:50.987421 <3>[ 21.209122] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10631 12:15:51.020660 <3>[ 21.242856] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10632 12:15:51.033835 <30>[ 21.259146] systemd[1]: Mounting FUSE Control File System...
10633 12:15:51.040136 Mounting [0;1;39mFUSE Control File System[0m...
10634 12:15:51.054681 <3>[ 21.276723] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10635 12:15:51.068788 <30>[ 21.291027] systemd[1]: Mounting Kernel Configuration File System...
10636 12:15:51.072275 Mounting [0;1;39mKernel Configuration File System[0m...
10637 12:15:51.087779 <3>[ 21.309747] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10638 12:15:51.102709 <30>[ 21.323896] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10639 12:15:51.111945 <30>[ 21.333104] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10640 12:15:51.123024 <30>[ 21.347473] systemd[1]: Starting Load/Save Random Seed...
10641 12:15:51.126527 Starting [0;1;39mLoad/Save Random Seed[0m...
10642 12:15:51.146967 <30>[ 21.372215] systemd[1]: Starting Apply Kernel Variables...
10643 12:15:51.153776 Starting [0;1;39mApply Kernel Variables[0m...
10644 12:15:51.171841 <30>[ 21.396558] systemd[1]: Starting Create System Users...
10645 12:15:51.188116 <4>[ 21.400612] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10646 12:15:51.194970 <3>[ 21.417812] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10647 12:15:51.201751 Starting [0;1;39mCreate System Users[0m...
10648 12:15:51.218374 <30>[ 21.443477] systemd[1]: Started Journal Service.
10649 12:15:51.224848 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10650 12:15:51.249036 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10651 12:15:51.262674 See 'systemctl status systemd-udev-trigger.service' for details.
10652 12:15:51.280196 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10653 12:15:51.295408 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10654 12:15:51.312392 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10655 12:15:51.328817 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10656 12:15:51.344372 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10657 12:15:51.403538 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10658 12:15:51.421260 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10659 12:15:51.455076 <46>[ 21.676884] systemd-journald[290]: Received client request to flush runtime journal.
10660 12:15:51.486635 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10661 12:15:51.504883 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10662 12:15:51.523358 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10663 12:15:51.583401 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10664 12:15:52.854525 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10665 12:15:52.891825 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10666 12:15:52.937809 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10667 12:15:52.974610 Starting [0;1;39mNetwork Service[0m...
10668 12:15:53.303592 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10669 12:15:53.328582 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10670 12:15:53.383514 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10671 12:15:53.649712 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10672 12:15:53.666480 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10673 12:15:53.684037 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10674 12:15:53.735928 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10675 12:15:53.763944 Starting [0;1;39mNetwork Time Synchronization[0m...
10676 12:15:53.784063 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10677 12:15:53.800846 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10678 12:15:53.815891 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10679 12:15:53.836036 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10680 12:15:53.865716 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10681 12:15:53.891168 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10682 12:15:53.911333 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10683 12:15:53.972349 Starting [0;1;39mNetwork Name Resolution[0m...
10684 12:15:54.431095 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10685 12:15:54.447707 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10686 12:15:54.698105 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10687 12:15:55.026554 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10688 12:15:55.047431 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10689 12:15:55.068937 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10690 12:15:55.085972 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10691 12:15:55.098587 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10692 12:15:55.118973 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10693 12:15:55.130786 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10694 12:15:55.150257 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10695 12:15:55.199226 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10696 12:15:55.252080 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10697 12:15:55.347694 Starting [0;1;39mUser Login Management[0m...
10698 12:15:55.831005 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10699 12:15:55.898667 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10700 12:15:55.918940 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10701 12:15:55.942173 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10702 12:15:55.991099 Starting [0;1;39mPermit User Sessions[0m...
10703 12:15:56.012609 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10704 12:15:56.025014 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10705 12:15:56.040116 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10706 12:15:56.063056 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10707 12:15:56.081468 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10708 12:15:56.094430 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10709 12:15:56.110608 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10710 12:15:56.172890 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10711 12:15:56.218944 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10712 12:15:56.281832
10713 12:15:56.281942
10714 12:15:56.284017 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10715 12:15:56.284094
10716 12:15:56.287328 debian-bullseye-arm64 login: root (automatic login)
10717 12:15:56.287408
10718 12:15:56.287472
10719 12:15:56.579802 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024 aarch64
10720 12:15:56.579943
10721 12:15:56.586967 The programs included with the Debian GNU/Linux system are free software;
10722 12:15:56.592597 the exact distribution terms for each program are described in the
10723 12:15:56.596242 individual files in /usr/share/doc/*/copyright.
10724 12:15:56.596317
10725 12:15:56.603094 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10726 12:15:56.606007 permitted by applicable law.
10727 12:15:56.655420 Matched prompt #10: / #
10729 12:15:56.655647 Setting prompt string to ['/ #']
10730 12:15:56.655739 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10732 12:15:56.655936 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10733 12:15:56.656024 start: 2.2.6 expect-shell-connection (timeout 00:03:27) [common]
10734 12:15:56.656093 Setting prompt string to ['/ #']
10735 12:15:56.656168 Forcing a shell prompt, looking for ['/ #']
10737 12:15:56.706388 / #
10738 12:15:56.706488 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10739 12:15:56.706583 Waiting using forced prompt support (timeout 00:02:30)
10740 12:15:56.711866
10741 12:15:56.712135 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10742 12:15:56.712225 start: 2.2.7 export-device-env (timeout 00:03:26) [common]
10744 12:15:56.812593 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12669512/extract-nfsrootfs-zak5hcs0'
10745 12:15:56.819296 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12669512/extract-nfsrootfs-zak5hcs0'
10747 12:15:56.919819 / # export NFS_SERVER_IP='192.168.201.1'
10748 12:15:56.925157 export NFS_SERVER_IP='192.168.201.1'
10749 12:15:56.925434 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10750 12:15:56.925527 end: 2.2 depthcharge-retry (duration 00:01:34) [common]
10751 12:15:56.925614 end: 2 depthcharge-action (duration 00:01:34) [common]
10752 12:15:56.925703 start: 3 lava-test-retry (timeout 00:30:00) [common]
10753 12:15:56.925791 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10754 12:15:56.925865 Using namespace: common
10756 12:15:57.026199 / # #
10757 12:15:57.026319 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
10758 12:15:57.031534 #
10759 12:15:57.031813 Using /lava-12669512
10761 12:15:57.132222 / # export SHELL=/bin/sh
10762 12:15:57.137354 export SHELL=/bin/sh
10764 12:15:57.237914 / # . /lava-12669512/environment
10765 12:15:57.243542 . /lava-12669512/environment
10767 12:15:57.348754 / # /lava-12669512/bin/lava-test-runner /lava-12669512/0
10768 12:15:57.348896 Test shell timeout: 10s (minimum of the action and connection timeout)
10769 12:15:57.354294 /lava-12669512/bin/lava-test-runner /lava-12669512/0
10770 12:15:57.562901 + export TESTRUN_ID=0_lc-compliance
10771 12:15:57.569441 + cd /lava-12669512/0/tests/0_lc-compliance
10772 12:15:57.569564 + cat uuid
10773 12:15:57.574697 + UUID=12669512_1.6.2.3.1
10774 12:15:57.574774 + set +x
10775 12:15:57.581621 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 12669512_1.6.2.3.1>
10776 12:15:57.581876 Received signal: <STARTRUN> 0_lc-compliance 12669512_1.6.2.3.1
10777 12:15:57.581948 Starting test lava.0_lc-compliance (12669512_1.6.2.3.1)
10778 12:15:57.582037 Skipping test definition patterns.
10779 12:15:57.584627 + /usr/bin/lc-compliance-parser.sh
10780 12:15:58.757944 [0:00:28.861747616] [395] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:297 [0mlibcamera v0.0.0+1-1f607da9
10781 12:15:58.761780 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
10782 12:15:58.776989 [0:00:28.880557539] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10783 12:15:58.835429 [0:00:28.938113539] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10784 12:15:58.837527 [==========] Running 120 tests from 1 test suite.
10785 12:15:58.887942 [0:00:28.991334385] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10786 12:15:58.900672 [----------] Global test environment set-up.
10787 12:15:58.945484 [0:00:29.049321308] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10788 12:15:58.969753 [----------] 120 tests from CaptureTests/SingleStream
10789 12:15:59.028012 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
10790 12:15:59.080301 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
10791 12:15:59.080617 Received signal: <TESTSET> START CaptureTests/SingleStream
10792 12:15:59.080744 Starting test_set CaptureTests/SingleStream
10793 12:15:59.083594 Camera needs 4 requests, can't test only 1
10794 12:15:59.145277 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10795 12:15:59.200402
10796 12:15:59.268417 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (58 ms)
10797 12:15:59.311677 [0:00:29.415029924] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10798 12:15:59.349693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
10799 12:15:59.349968 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
10801 12:15:59.363859 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
10802 12:15:59.408354 Camera needs 4 requests, can't test only 2
10803 12:15:59.472863 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10804 12:15:59.548220
10805 12:15:59.614820 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (53 ms)
10806 12:15:59.686206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
10807 12:15:59.686529 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
10809 12:15:59.700558 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
10810 12:15:59.744649 Camera needs 4 requests, can't test only 3
10811 12:15:59.776303 [0:00:29.880280000] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10812 12:15:59.823156 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10813 12:15:59.883065
10814 12:15:59.950170 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (57 ms)
10815 12:16:00.021418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
10816 12:16:00.021741 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
10818 12:16:00.037108 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
10819 12:16:00.085342 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (367 ms)
10820 12:16:00.166523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
10821 12:16:00.166846 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
10823 12:16:00.179918 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
10824 12:16:00.224590 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (464 ms)
10825 12:16:00.300892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
10826 12:16:00.301219 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
10828 12:16:00.314659 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
10829 12:16:00.464854 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (697 ms)
10830 12:16:00.474283 [0:00:30.578049308] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10831 12:16:00.547296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
10832 12:16:00.547580 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
10834 12:16:00.558719 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
10835 12:16:01.462308 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (998 ms)
10836 12:16:01.472956 [0:00:31.576346078] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10837 12:16:01.547945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
10838 12:16:01.548231 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
10840 12:16:01.562693 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
10841 12:16:02.798616 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1335 ms)
10842 12:16:02.807173 [0:00:32.911375001] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10843 12:16:02.879081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
10844 12:16:02.879406 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
10846 12:16:02.892609 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
10847 12:16:04.929455 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2131 ms)
10848 12:16:04.938393 [0:00:35.043052539] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10849 12:16:05.011420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
10850 12:16:05.011794 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
10852 12:16:05.025998 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
10853 12:16:08.159220 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3231 ms)
10854 12:16:08.168682 [0:00:38.273743155] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10855 12:16:08.224563 [0:00:38.329273232] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10856 12:16:08.246168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
10857 12:16:08.246543 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
10859 12:16:08.262853 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
10860 12:16:08.281530 [0:00:38.385579463] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10861 12:16:08.305040 Camera needs 4 requests, can't test only 1
10862 12:16:08.334761 [0:00:38.439684847] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10863 12:16:08.369644 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10864 12:16:08.434642
10865 12:16:08.509948 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (56 ms)
10866 12:16:08.591154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
10867 12:16:08.591521 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
10869 12:16:08.606254 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
10870 12:16:08.655322 Camera needs 4 requests, can't test only 2
10871 12:16:08.701624 [0:00:38.806386924] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10872 12:16:08.730605 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10873 12:16:08.795184
10874 12:16:08.870188 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (56 ms)
10875 12:16:08.953358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
10876 12:16:08.953704 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
10878 12:16:08.967235 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
10879 12:16:09.015982 Camera needs 4 requests, can't test only 3
10880 12:16:09.078314 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10881 12:16:09.143947
10882 12:16:09.167008 [0:00:39.272112463] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10883 12:16:09.229004 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (54 ms)
10884 12:16:09.298955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
10885 12:16:09.299283 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
10887 12:16:09.310873 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
10888 12:16:09.357746 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (365 ms)
10889 12:16:09.424450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
10890 12:16:09.424748 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
10892 12:16:09.438364 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
10893 12:16:09.486786 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (466 ms)
10894 12:16:09.554611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
10895 12:16:09.554984 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
10897 12:16:09.569594 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
10898 12:16:09.855116 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (697 ms)
10899 12:16:09.868583 [0:00:39.969829540] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10900 12:16:09.935724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
10901 12:16:09.936050 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
10903 12:16:09.949845 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
10904 12:16:10.790332 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (935 ms)
10905 12:16:10.804579 [0:00:40.905847463] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10906 12:16:10.871121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
10907 12:16:10.871449 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
10909 12:16:10.885201 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
10910 12:16:12.188899 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1398 ms)
10911 12:16:12.202155 [0:00:42.303964155] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10912 12:16:12.276604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
10913 12:16:12.277010 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
10915 12:16:12.289917 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
10916 12:16:14.320077 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2131 ms)
10917 12:16:14.332622 [0:00:44.435017540] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10918 12:16:14.399271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
10919 12:16:14.399577 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
10921 12:16:14.410353 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
10922 12:16:15.933164 <6>[ 46.164150] vpu: disabling
10923 12:16:15.936388 <6>[ 46.167247] vproc2: disabling
10924 12:16:15.939127 <6>[ 46.170590] vproc1: disabling
10925 12:16:15.942827 <6>[ 46.173899] vaud18: disabling
10926 12:16:15.949600 <6>[ 46.177447] vsram_others: disabling
10927 12:16:15.952450 <6>[ 46.181500] va09: disabling
10928 12:16:15.955739 <6>[ 46.184697] vsram_md: disabling
10929 12:16:15.959115 <6>[ 46.188262] Vgpu: disabling
10930 12:16:17.549886 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3231 ms)
10931 12:16:17.563249 [0:00:47.665497925] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10932 12:16:17.616497 [0:00:47.722113540] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10933 12:16:17.650781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
10934 12:16:17.651054 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
10936 12:16:17.663877 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
10937 12:16:17.674289 [0:00:47.777901694] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10938 12:16:17.712703 Camera needs 4 requests, can't test only 1
10939 12:16:17.725922 [0:00:47.832146540] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10940 12:16:17.789104 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10941 12:16:17.866990
10942 12:16:17.941011 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (57 ms)
10943 12:16:18.031707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
10944 12:16:18.032431 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
10946 12:16:18.048049 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
10947 12:16:18.103899 Camera needs 4 requests, can't test only 2
10948 12:16:18.187787 [0:00:48.292812463] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10949 12:16:18.190578 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10950 12:16:18.270795
10951 12:16:18.358460 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (57 ms)
10952 12:16:18.440444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
10953 12:16:18.440763 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
10955 12:16:18.454175 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
10956 12:16:18.498771 Camera needs 4 requests, can't test only 3
10957 12:16:18.579143 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10958 12:16:18.658770
10959 12:16:18.749778 [0:00:48.855096232] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10960 12:16:18.755748 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (54 ms)
10961 12:16:18.854464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
10962 12:16:18.855234 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
10964 12:16:18.873148 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
10965 12:16:18.932317 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (461 ms)
10966 12:16:19.035289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
10967 12:16:19.036153 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
10969 12:16:19.053279 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
10970 12:16:19.109967 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (561 ms)
10971 12:16:19.203516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
10972 12:16:19.204231 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
10974 12:16:19.220312 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
10975 12:16:19.437405 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (697 ms)
10976 12:16:19.450428 [0:00:49.552578617] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10977 12:16:19.537105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
10978 12:16:19.537876 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
10980 12:16:19.553415 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
10981 12:16:20.337135 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (900 ms)
10982 12:16:20.350126 [0:00:50.452375617] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10983 12:16:20.434012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
10984 12:16:20.434458 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
10986 12:16:20.447858 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
10987 12:16:21.735004 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1398 ms)
10988 12:16:21.748018 [0:00:51.850536156] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10989 12:16:21.832687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
10990 12:16:21.833503 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
10992 12:16:21.849713 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
10993 12:16:23.864659 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2130 ms)
10994 12:16:23.879121 [0:00:53.980652233] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10995 12:16:23.968410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
10996 12:16:23.969228 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
10998 12:16:23.984367 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
10999 12:16:27.095191 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3231 ms)
11000 12:16:27.107463 [0:00:57.211467700] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11001 12:16:27.160676 [0:00:57.267937728] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11002 12:16:27.173313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11003 12:16:27.173575 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11005 12:16:27.186125 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11006 12:16:27.215414 [0:00:57.322557813] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11007 12:16:27.223771 Camera needs 4 requests, can't test only 1
11008 12:16:27.269641 [0:00:57.376201398] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11009 12:16:27.282537 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11010 12:16:27.330140
11011 12:16:27.390132 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (57 ms)
11012 12:16:27.454888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11013 12:16:27.455186 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11015 12:16:27.466229 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11016 12:16:27.512777 Camera needs 4 requests, can't test only 2
11017 12:16:27.580789 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11018 12:16:27.633153 [0:00:57.740596991] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11019 12:16:27.648079
11020 12:16:27.714928 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (56 ms)
11021 12:16:27.790946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11022 12:16:27.791228 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11024 12:16:27.803348 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11025 12:16:27.844092 Camera needs 4 requests, can't test only 3
11026 12:16:27.901734 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11027 12:16:27.960972
11028 12:16:28.024927 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (53 ms)
11029 12:16:28.100238 [0:00:58.206774033] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11030 12:16:28.103604 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11032 12:16:28.106525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11033 12:16:28.115982 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11034 12:16:28.148611 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (363 ms)
11035 12:16:28.213274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11036 12:16:28.213547 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11038 12:16:28.226822 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11039 12:16:28.270365 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (466 ms)
11040 12:16:28.343384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11041 12:16:28.343660 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11043 12:16:28.356989 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11044 12:16:28.788317 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (697 ms)
11045 12:16:28.801554 [0:00:58.904341038] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11046 12:16:28.866897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11047 12:16:28.867186 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11049 12:16:28.878186 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11050 12:16:29.722788 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (935 ms)
11051 12:16:29.736057 [0:00:59.839726857] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11052 12:16:29.799516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11053 12:16:29.799796 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11055 12:16:29.814107 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11056 12:16:31.122267 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1399 ms)
11057 12:16:31.134823 [0:01:01.237934128] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11058 12:16:31.187949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11059 12:16:31.188224 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11061 12:16:31.200424 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11062 12:16:33.252696 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2130 ms)
11063 12:16:33.265486 [0:01:03.368274280] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11064 12:16:33.347070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11065 12:16:33.347815 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11067 12:16:33.362547 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11068 12:16:36.481563 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3230 ms)
11069 12:16:36.494491 [0:01:06.597840321] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11070 12:16:36.546626 [0:01:06.653572641] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11071 12:16:36.553403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11072 12:16:36.553692 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11074 12:16:36.565594 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11075 12:16:36.602340 [0:01:06.709124057] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11076 12:16:36.605864 Camera needs 4 requests, can't test only 1
11077 12:16:36.650317 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11078 12:16:36.660607 [0:01:06.765436005] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11079 12:16:36.700739
11080 12:16:36.752761 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (56 ms)
11081 12:16:36.819405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11082 12:16:36.819681 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11084 12:16:36.831320 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11085 12:16:36.874170 Camera needs 4 requests, can't test only 2
11086 12:16:36.936382 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11087 12:16:37.002698
11088 12:16:37.070859 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (56 ms)
11089 12:16:37.144554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11090 12:16:37.144850 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11092 12:16:37.156850 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11093 12:16:37.194512 Camera needs 4 requests, can't test only 3
11094 12:16:37.244257 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11095 12:16:37.300466
11096 12:16:37.364880 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (56 ms)
11097 12:16:37.433510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11098 12:16:37.433799 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11100 12:16:37.444891 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11101 12:16:37.934413 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1284 ms)
11102 12:16:37.947309 [0:01:08.050447979] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11103 12:16:38.003575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11104 12:16:38.003848 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11106 12:16:38.017258 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11107 12:16:39.616441 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1683 ms)
11108 12:16:39.630026 [0:01:09.733256187] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11109 12:16:39.693956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11110 12:16:39.694240 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11112 12:16:39.706812 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11113 12:16:41.735462 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2118 ms)
11114 12:16:41.748518 [0:01:11.851747521] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11115 12:16:41.828625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11116 12:16:41.829435 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11118 12:16:41.843158 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11119 12:16:44.422382 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2687 ms)
11120 12:16:44.435259 [0:01:14.539200995] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11121 12:16:44.516824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11122 12:16:44.517643 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11124 12:16:44.535425 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11125 12:16:48.605501 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4182 ms)
11126 12:16:48.618477 [0:01:18.722091704] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11127 12:16:48.710860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11128 12:16:48.711694 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11130 12:16:48.725924 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11131 12:16:54.920557 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6316 ms)
11132 12:16:54.933961 [0:01:25.037664663] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11133 12:16:55.031975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11134 12:16:55.032832 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11136 12:16:55.051025 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11137 12:17:04.539068 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9619 ms)
11138 12:17:04.551396 [0:01:34.656624865] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11139 12:17:04.604233 [0:01:34.712721312] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11140 12:17:04.621422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11141 12:17:04.621684 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11143 12:17:04.634450 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11144 12:17:04.658305 [0:01:34.767217404] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11145 12:17:04.676675 Camera needs 4 requests, can't test only 1
11146 12:17:04.715515 [0:01:34.823331850] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11147 12:17:04.744865 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11148 12:17:04.794399
11149 12:17:04.867078 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (57 ms)
11150 12:17:04.940478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11151 12:17:04.941256 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11153 12:17:04.951730 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11154 12:17:05.002082 Camera needs 4 requests, can't test only 2
11155 12:17:05.077695 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11156 12:17:05.151724
11157 12:17:05.227443 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (56 ms)
11158 12:17:05.295976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11159 12:17:05.296260 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11161 12:17:05.304613 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11162 12:17:05.344127 Camera needs 4 requests, can't test only 3
11163 12:17:05.402647 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11164 12:17:05.463248
11165 12:17:05.535250 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (54 ms)
11166 12:17:05.636196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11167 12:17:05.637143 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11169 12:17:05.646993 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11170 12:17:05.995964 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1286 ms)
11171 12:17:06.005113 [0:01:36.110829846] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11172 12:17:06.075785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11173 12:17:06.076077 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11175 12:17:06.084981 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11176 12:17:07.678883 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1683 ms)
11177 12:17:07.689114 [0:01:37.794045917] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11178 12:17:07.775213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11179 12:17:07.775992 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11181 12:17:07.788110 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11182 12:17:09.795279 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2117 ms)
11183 12:17:09.804685 [0:01:39.911029046] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11184 12:17:09.866877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11185 12:17:09.867186 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11187 12:17:09.873839 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11188 12:17:12.581475 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2787 ms)
11189 12:17:12.591190 [0:01:42.697398995] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11190 12:17:12.651737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11191 12:17:12.652042 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11193 12:17:12.659562 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11194 12:17:16.764271 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4182 ms)
11195 12:17:16.773259 [0:01:46.879444698] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11196 12:17:16.854605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11197 12:17:16.854958 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11199 12:17:16.866406 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11200 12:17:23.078255 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6315 ms)
11201 12:17:23.088080 [0:01:53.194977321] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11202 12:17:23.169791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11203 12:17:23.170108 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11205 12:17:23.178978 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11206 12:17:32.694798 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9618 ms)
11207 12:17:32.705007 [0:02:02.812731635] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11208 12:17:32.758209 [0:02:02.868543900] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11209 12:17:32.778519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11210 12:17:32.778815 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11212 12:17:32.790099 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11213 12:17:32.812011 [0:02:02.923547145] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11214 12:17:32.830841 Camera needs 4 requests, can't test only 1
11215 12:17:32.867880 [0:02:02.978466181] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11216 12:17:32.888170 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11217 12:17:32.948183
11218 12:17:33.019018 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (57 ms)
11219 12:17:33.094557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11220 12:17:33.094963 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11222 12:17:33.104866 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11223 12:17:33.150559 Camera needs 4 requests, can't test only 2
11224 12:17:33.211009 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11225 12:17:33.275705
11226 12:17:33.348103 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (56 ms)
11227 12:17:33.417258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11228 12:17:33.417579 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11230 12:17:33.426501 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11231 12:17:33.465950 Camera needs 4 requests, can't test only 3
11232 12:17:33.535877 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11233 12:17:33.610735
11234 12:17:33.695848 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (54 ms)
11235 12:17:33.783846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11236 12:17:33.784583 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11238 12:17:33.795458 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11239 12:17:34.148218 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1286 ms)
11240 12:17:34.158118 [0:02:04.265637994] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11241 12:17:34.217689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11242 12:17:34.217972 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11244 12:17:34.226943 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11245 12:17:35.535816 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1387 ms)
11246 12:17:35.545978 [0:02:05.653166315] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11247 12:17:35.617930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11248 12:17:35.618238 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11250 12:17:35.626538 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11251 12:17:37.653481 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2116 ms)
11252 12:17:37.662705 [0:02:07.770005913] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11253 12:17:37.746240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11254 12:17:37.747007 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11256 12:17:37.758348 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11257 12:17:40.375454 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2722 ms)
11258 12:17:40.385957 [0:02:10.492197282] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11259 12:17:40.472961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11260 12:17:40.473254 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11262 12:17:40.483383 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11263 12:17:44.495352 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4119 ms)
11264 12:17:44.504887 [0:02:14.611280744] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11265 12:17:44.581510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11266 12:17:44.581804 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11268 12:17:44.591731 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11269 12:17:50.809085 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6313 ms)
11270 12:17:50.818842 [0:02:20.924820554] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11271 12:17:50.898527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11272 12:17:50.898879 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11274 12:17:50.906931 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11275 12:18:00.427465 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9618 ms)
11276 12:18:00.436747 [0:02:30.542355618] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11277 12:18:00.488444 [0:02:30.597830876] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11278 12:18:00.508224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11279 12:18:00.508527 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11281 12:18:00.515520 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11282 12:18:00.545879 [0:02:30.654800026] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11283 12:18:00.562612 Camera needs 4 requests, can't test only 1
11284 12:18:00.599974 [0:02:30.708514964] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11285 12:18:00.637233 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11286 12:18:00.702851
11287 12:18:00.784838 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (56 ms)
11288 12:18:00.851716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11289 12:18:00.852036 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11291 12:18:00.861216 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11292 12:18:00.900113 Camera needs 4 requests, can't test only 2
11293 12:18:00.965494 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11294 12:18:01.027831
11295 12:18:01.104000 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (57 ms)
11296 12:18:01.183099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11297 12:18:01.183426 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11299 12:18:01.193462 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11300 12:18:01.239411 Camera needs 4 requests, can't test only 3
11301 12:18:01.300343 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11302 12:18:01.358373
11303 12:18:01.440628 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (53 ms)
11304 12:18:01.512655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11305 12:18:01.513002 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11307 12:18:01.522489 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11308 12:18:01.782181 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1188 ms)
11309 12:18:01.792135 [0:02:31.897257282] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11310 12:18:01.873746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11311 12:18:01.874571 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11313 12:18:01.885476 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11314 12:18:03.176638 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1393 ms)
11315 12:18:03.194828 [0:02:33.291998587] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11316 12:18:03.279373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11317 12:18:03.280125 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11319 12:18:03.294153 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11320 12:18:05.293045 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2117 ms)
11321 12:18:05.302623 [0:02:35.407922856] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11322 12:18:05.383574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11323 12:18:05.383852 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11325 12:18:05.395143 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11326 12:18:08.077952 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2784 ms)
11327 12:18:08.087224 [0:02:38.192546014] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11328 12:18:08.185440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11329 12:18:08.186247 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11331 12:18:08.198976 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11332 12:18:12.326146 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4249 ms)
11333 12:18:12.335667 [0:02:42.441637996] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11334 12:18:12.421697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11335 12:18:12.422426 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11337 12:18:12.434423 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11338 12:18:18.639563 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6314 ms)
11339 12:18:18.649649 [0:02:48.755767529] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11340 12:18:18.739255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11341 12:18:18.740087 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11343 12:18:18.752041 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11344 12:18:28.288638 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9649 ms)
11345 12:18:28.297954 [0:02:58.404685694] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11346 12:18:28.397735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11347 12:18:28.398555 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11349 12:18:28.410365 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11350 12:18:28.551629 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (266 ms)
11351 12:18:28.564030 [0:02:58.670225175] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11352 12:18:28.649664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11353 12:18:28.650371 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11355 12:18:28.666114 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11356 12:18:28.818204 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (267 ms)
11357 12:18:28.832909 [0:02:58.937222249] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11358 12:18:28.912285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11359 12:18:28.912602 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11361 12:18:28.927687 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11362 12:18:29.118835 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (300 ms)
11363 12:18:29.131227 [0:02:59.237660561] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11364 12:18:29.225020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11365 12:18:29.225736 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11367 12:18:29.240484 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11368 12:18:29.583456 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (465 ms)
11369 12:18:29.596799 [0:02:59.702929141] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11370 12:18:29.684627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11371 12:18:29.685368 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11373 12:18:29.702662 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11374 12:18:30.148336 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (565 ms)
11375 12:18:30.161249 [0:03:00.267652201] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11376 12:18:30.248814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11377 12:18:30.249523 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11379 12:18:30.265477 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11380 12:18:30.846741 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (699 ms)
11381 12:18:30.861101 [0:03:00.965962211] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11382 12:18:30.941240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11383 12:18:30.941572 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11385 12:18:30.957988 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11386 12:18:31.745206 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (899 ms)
11387 12:18:31.759682 [0:03:01.865204468] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11388 12:18:31.833014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11389 12:18:31.833330 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11391 12:18:31.847062 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11392 12:18:33.080544 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1335 ms)
11393 12:18:33.093507 [0:03:03.199681103] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11394 12:18:33.194681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11395 12:18:33.195409 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11397 12:18:33.211969 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11398 12:18:35.209904 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2129 ms)
11399 12:18:35.223405 [0:03:05.329840031] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11400 12:18:35.309943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11401 12:18:35.310811 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11403 12:18:35.326828 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11404 12:18:38.440674 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3230 ms)
11405 12:18:38.454271 [0:03:08.560488725] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11406 12:18:38.547243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11407 12:18:38.548137 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11409 12:18:38.565054 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11410 12:18:38.744613 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (299 ms)
11411 12:18:38.753026 [0:03:08.859611836] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11412 12:18:38.850195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11413 12:18:38.851077 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11415 12:18:38.864562 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11416 12:18:39.043055 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (300 ms)
11417 12:18:39.053268 [0:03:09.159676778] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11418 12:18:39.150644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11419 12:18:39.151675 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11421 12:18:39.163636 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11422 12:18:39.343351 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (300 ms)
11423 12:18:39.352978 [0:03:09.459676104] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11424 12:18:39.442104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11425 12:18:39.443065 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11427 12:18:39.454961 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11428 12:18:39.808627 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (466 ms)
11429 12:18:39.819166 [0:03:09.924993141] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11430 12:18:39.903861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11431 12:18:39.904159 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11433 12:18:39.915174 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11434 12:18:40.373197 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (564 ms)
11435 12:18:40.382502 [0:03:10.489491834] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11436 12:18:40.473103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11437 12:18:40.473961 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11439 12:18:40.486602 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11440 12:18:41.072323 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (698 ms)
11441 12:18:41.080532 [0:03:11.187759762] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11442 12:18:41.176563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11443 12:18:41.177417 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11445 12:18:41.190642 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11446 12:18:41.971814 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (900 ms)
11447 12:18:41.980602 [0:03:12.087402587] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11448 12:18:42.070334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11449 12:18:42.071400 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11451 12:18:42.082130 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11452 12:18:43.368490 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1398 ms)
11453 12:18:43.377934 [0:03:13.485247185] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11454 12:18:43.472247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11455 12:18:43.473140 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11457 12:18:43.486431 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11458 12:18:45.467379 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2098 ms)
11459 12:18:45.476043 [0:03:15.583434115] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11460 12:18:45.565674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11461 12:18:45.566459 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11463 12:18:45.578198 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11464 12:18:48.664578 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3199 ms)
11465 12:18:48.674783 [0:03:18.782498084] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11466 12:18:48.748603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11467 12:18:48.748931 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11469 12:18:48.756947 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11470 12:18:48.964476 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (299 ms)
11471 12:18:48.974688 [0:03:19.081597578] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11472 12:18:49.044202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11473 12:18:49.044519 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11475 12:18:49.054529 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11476 12:18:49.264601 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (301 ms)
11477 12:18:49.275101 [0:03:19.381872568] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11478 12:18:49.338511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11479 12:18:49.338789 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11481 12:18:49.347074 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11482 12:18:49.564520 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (300 ms)
11483 12:18:49.575403 [0:03:19.682105505] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11484 12:18:49.643427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11485 12:18:49.643703 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11487 12:18:49.655838 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11488 12:18:50.029804 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (464 ms)
11489 12:18:50.039201 [0:03:20.147154199] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11490 12:18:50.109437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11491 12:18:50.110166 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11493 12:18:50.121206 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11494 12:18:50.594307 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (565 ms)
11495 12:18:50.603811 [0:03:20.711607907] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11496 12:18:50.695390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11497 12:18:50.696283 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11499 12:18:50.709292 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11500 12:18:51.291993 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (698 ms)
11501 12:18:51.302377 [0:03:21.410005686] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11502 12:18:51.381932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11503 12:18:51.382266 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11505 12:18:51.391175 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11506 12:18:52.192801 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (900 ms)
11507 12:18:52.202166 [0:03:22.310156051] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11508 12:18:52.289495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11509 12:18:52.290279 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11511 12:18:52.303449 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11512 12:18:53.528065 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1336 ms)
11513 12:18:53.537745 [0:03:23.645526079] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11514 12:18:53.633237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11515 12:18:53.633959 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11517 12:18:53.647699 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11518 12:18:55.659236 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2131 ms)
11519 12:18:55.669030 [0:03:25.776693746] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11520 12:18:55.757574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11521 12:18:55.758324 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11523 12:18:55.770775 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11524 12:18:58.889394 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3231 ms)
11525 12:18:58.899099 [0:03:29.007362760] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11526 12:18:58.988651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11527 12:18:58.989616 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11529 12:18:59.002349 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11530 12:18:59.187961 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (298 ms)
11531 12:18:59.198266 [0:03:29.304850629] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11532 12:18:59.279350 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11534 12:18:59.282675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11535 12:18:59.293998 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11536 12:18:59.486970 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (298 ms)
11537 12:18:59.496825 [0:03:29.604892513] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11538 12:18:59.584311 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11540 12:18:59.587973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11541 12:18:59.600840 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11542 12:18:59.787234 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (301 ms)
11543 12:18:59.796824 [0:03:29.905413761] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11544 12:18:59.878023 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11546 12:18:59.880906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11547 12:18:59.892390 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11548 12:19:00.252750 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (465 ms)
11549 12:19:00.262135 [0:03:30.370813524] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11550 12:19:00.346216 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11552 12:19:00.348980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11553 12:19:00.361007 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11554 12:19:00.817467 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (565 ms)
11555 12:19:00.826756 [0:03:30.935477808] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11556 12:19:00.908099 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11558 12:19:00.911095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11559 12:19:00.922325 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11560 12:19:01.516000 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (698 ms)
11561 12:19:01.525915 [0:03:31.633885772] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11562 12:19:01.617981 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11564 12:19:01.621191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11565 12:19:01.636324 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11566 12:19:02.416173 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (899 ms)
11567 12:19:02.425741 [0:03:32.534080790] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11568 12:19:02.510550 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11570 12:19:02.513153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11571 12:19:02.526722 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11572 12:19:03.813443 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1397 ms)
11573 12:19:03.823376 [0:03:33.932089761] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11574 12:19:03.907080 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11576 12:19:03.909500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11577 12:19:03.923648 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11578 12:19:05.912499 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2099 ms)
11579 12:19:05.921935 [0:03:36.030887545] [395] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11580 12:19:05.997288 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11582 12:19:05.999963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11583 12:19:06.009089 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11584 12:19:09.112849 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3200 ms)
11585 12:19:09.209294 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11587 12:19:09.212016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11588 12:19:09.227440 [----------] 120 tests from CaptureTests/SingleStream (190349 ms total)
11589 12:19:09.303142
11590 12:19:09.388972 [----------] Global test environment tear-down
11591 12:19:09.473791 [==========] 120 tests from 1 test suite ran. (190349 ms total)
11592 12:19:09.556574 <LAVA_SIGNAL_TESTSET STOP>
11593 12:19:09.557403 Received signal: <TESTSET> STOP
11594 12:19:09.557865 Closing test_set CaptureTests/SingleStream
11595 12:19:09.568350 + set +x
11596 12:19:09.571583 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 12669512_1.6.2.3.1>
11597 12:19:09.572421 Received signal: <ENDRUN> 0_lc-compliance 12669512_1.6.2.3.1
11598 12:19:09.572865 Ending use of test pattern.
11599 12:19:09.573191 Ending test lava.0_lc-compliance (12669512_1.6.2.3.1), duration 191.99
11601 12:19:09.575155 <LAVA_TEST_RUNNER EXIT>
11602 12:19:09.575782 ok: lava_test_shell seems to have completed
11603 12:19:09.587381 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11604 12:19:09.588411 end: 3.1 lava-test-shell (duration 00:03:13) [common]
11605 12:19:09.588982 end: 3 lava-test-retry (duration 00:03:13) [common]
11606 12:19:09.589530 start: 4 finalize (timeout 00:10:00) [common]
11607 12:19:09.589976 start: 4.1 power-off (timeout 00:00:30) [common]
11608 12:19:09.590736 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11609 12:19:09.699382 >> Command sent successfully.
11610 12:19:09.704533 Returned 0 in 0 seconds
11611 12:19:09.805524 end: 4.1 power-off (duration 00:00:00) [common]
11613 12:19:09.807027 start: 4.2 read-feedback (timeout 00:10:00) [common]
11614 12:19:09.808320 Listened to connection for namespace 'common' for up to 1s
11615 12:19:10.808888 Finalising connection for namespace 'common'
11616 12:19:10.809506 Disconnecting from shell: Finalise
11617 12:19:10.809911 / #
11618 12:19:10.910953 end: 4.2 read-feedback (duration 00:00:01) [common]
11619 12:19:10.911709 end: 4 finalize (duration 00:00:01) [common]
11620 12:19:10.912493 Cleaning after the job
11621 12:19:10.913287 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/ramdisk
11622 12:19:10.927299 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/kernel
11623 12:19:10.959457 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/dtb
11624 12:19:10.959701 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/nfsrootfs
11625 12:19:11.021546 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669512/tftp-deploy-51zf4tfc/modules
11626 12:19:11.029066 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12669512
11627 12:19:11.346727 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12669512
11628 12:19:11.346891 Job finished correctly