Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 2
- Kernel Warnings: 16
- Kernel Errors: 35
1 12:14:53.534400 lava-dispatcher, installed at version: 2023.10
2 12:14:53.534613 start: 0 validate
3 12:14:53.534747 Start time: 2024-01-31 12:14:53.534740+00:00 (UTC)
4 12:14:53.534863 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:14:53.534989 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:14:53.816691 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:14:53.817372 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:14:54.087474 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:14:54.088161 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:14:54.355461 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:14:54.356193 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:14:54.640301 validate duration: 1.11
14 12:14:54.641593 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:14:54.642273 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:14:54.642758 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:14:54.643341 Not decompressing ramdisk as can be used compressed.
18 12:14:54.643809 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 12:14:54.644159 saving as /var/lib/lava/dispatcher/tmp/12669525/tftp-deploy-lgfg2yfe/ramdisk/rootfs.cpio.gz
20 12:14:54.644493 total size: 26246609 (25 MB)
21 12:14:54.649261 progress 0 % (0 MB)
22 12:14:54.675625 progress 5 % (1 MB)
23 12:14:54.687846 progress 10 % (2 MB)
24 12:14:54.696880 progress 15 % (3 MB)
25 12:14:54.704471 progress 20 % (5 MB)
26 12:14:54.711537 progress 25 % (6 MB)
27 12:14:54.718459 progress 30 % (7 MB)
28 12:14:54.725342 progress 35 % (8 MB)
29 12:14:54.732334 progress 40 % (10 MB)
30 12:14:54.739090 progress 45 % (11 MB)
31 12:14:54.745771 progress 50 % (12 MB)
32 12:14:54.752463 progress 55 % (13 MB)
33 12:14:54.759181 progress 60 % (15 MB)
34 12:14:54.765853 progress 65 % (16 MB)
35 12:14:54.772566 progress 70 % (17 MB)
36 12:14:54.779535 progress 75 % (18 MB)
37 12:14:54.786368 progress 80 % (20 MB)
38 12:14:54.793072 progress 85 % (21 MB)
39 12:14:54.799771 progress 90 % (22 MB)
40 12:14:54.806310 progress 95 % (23 MB)
41 12:14:54.812857 progress 100 % (25 MB)
42 12:14:54.813098 25 MB downloaded in 0.17 s (148.44 MB/s)
43 12:14:54.813253 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:14:54.813510 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:14:54.813596 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:14:54.813679 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:14:54.813814 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:14:54.813885 saving as /var/lib/lava/dispatcher/tmp/12669525/tftp-deploy-lgfg2yfe/kernel/Image
50 12:14:54.813945 total size: 51532288 (49 MB)
51 12:14:54.814005 No compression specified
52 12:14:54.815135 progress 0 % (0 MB)
53 12:14:54.828660 progress 5 % (2 MB)
54 12:14:54.842052 progress 10 % (4 MB)
55 12:14:54.855333 progress 15 % (7 MB)
56 12:14:54.868819 progress 20 % (9 MB)
57 12:14:54.882269 progress 25 % (12 MB)
58 12:14:54.895409 progress 30 % (14 MB)
59 12:14:54.908555 progress 35 % (17 MB)
60 12:14:54.921840 progress 40 % (19 MB)
61 12:14:54.935069 progress 45 % (22 MB)
62 12:14:54.948330 progress 50 % (24 MB)
63 12:14:54.961489 progress 55 % (27 MB)
64 12:14:54.974956 progress 60 % (29 MB)
65 12:14:54.988405 progress 65 % (31 MB)
66 12:14:55.001821 progress 70 % (34 MB)
67 12:14:55.015166 progress 75 % (36 MB)
68 12:14:55.028310 progress 80 % (39 MB)
69 12:14:55.041336 progress 85 % (41 MB)
70 12:14:55.054466 progress 90 % (44 MB)
71 12:14:55.067528 progress 95 % (46 MB)
72 12:14:55.080427 progress 100 % (49 MB)
73 12:14:55.080635 49 MB downloaded in 0.27 s (184.28 MB/s)
74 12:14:55.080783 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:14:55.081015 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:14:55.081100 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:14:55.081190 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:14:55.081324 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:14:55.081393 saving as /var/lib/lava/dispatcher/tmp/12669525/tftp-deploy-lgfg2yfe/dtb/mt8192-asurada-spherion-r0.dtb
81 12:14:55.081453 total size: 47278 (0 MB)
82 12:14:55.081561 No compression specified
83 12:14:55.082704 progress 69 % (0 MB)
84 12:14:55.082970 progress 100 % (0 MB)
85 12:14:55.083129 0 MB downloaded in 0.00 s (26.95 MB/s)
86 12:14:55.083248 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:14:55.083464 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:14:55.083547 start: 1.4 download-retry (timeout 00:10:00) [common]
90 12:14:55.083628 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 12:14:55.083742 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:14:55.083811 saving as /var/lib/lava/dispatcher/tmp/12669525/tftp-deploy-lgfg2yfe/modules/modules.tar
93 12:14:55.083871 total size: 8639916 (8 MB)
94 12:14:55.083931 Using unxz to decompress xz
95 12:14:55.088101 progress 0 % (0 MB)
96 12:14:55.109029 progress 5 % (0 MB)
97 12:14:55.132507 progress 10 % (0 MB)
98 12:14:55.155643 progress 15 % (1 MB)
99 12:14:55.178761 progress 20 % (1 MB)
100 12:14:55.202308 progress 25 % (2 MB)
101 12:14:55.230712 progress 30 % (2 MB)
102 12:14:55.256783 progress 35 % (2 MB)
103 12:14:55.281073 progress 40 % (3 MB)
104 12:14:55.305531 progress 45 % (3 MB)
105 12:14:55.330424 progress 50 % (4 MB)
106 12:14:55.356125 progress 55 % (4 MB)
107 12:14:55.380994 progress 60 % (4 MB)
108 12:14:55.406843 progress 65 % (5 MB)
109 12:14:55.431404 progress 70 % (5 MB)
110 12:14:55.454528 progress 75 % (6 MB)
111 12:14:55.481563 progress 80 % (6 MB)
112 12:14:55.509310 progress 85 % (7 MB)
113 12:14:55.534412 progress 90 % (7 MB)
114 12:14:55.563523 progress 95 % (7 MB)
115 12:14:55.591043 progress 100 % (8 MB)
116 12:14:55.596834 8 MB downloaded in 0.51 s (16.06 MB/s)
117 12:14:55.597098 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:14:55.597488 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:14:55.597667 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:14:55.597792 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:14:55.597885 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:14:55.597989 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:14:55.598232 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x
125 12:14:55.598379 makedir: /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin
126 12:14:55.598495 makedir: /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/tests
127 12:14:55.598630 makedir: /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/results
128 12:14:55.598785 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-add-keys
129 12:14:55.598945 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-add-sources
130 12:14:55.599092 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-background-process-start
131 12:14:55.599258 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-background-process-stop
132 12:14:55.599401 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-common-functions
133 12:14:55.599568 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-echo-ipv4
134 12:14:55.599733 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-install-packages
135 12:14:55.599898 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-installed-packages
136 12:14:55.600063 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-os-build
137 12:14:55.600227 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-probe-channel
138 12:14:55.600390 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-probe-ip
139 12:14:55.600551 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-target-ip
140 12:14:55.600689 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-target-mac
141 12:14:55.600827 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-target-storage
142 12:14:55.600973 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-test-case
143 12:14:55.601141 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-test-event
144 12:14:55.601307 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-test-feedback
145 12:14:55.601479 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-test-raise
146 12:14:55.601701 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-test-reference
147 12:14:55.601931 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-test-runner
148 12:14:55.602071 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-test-set
149 12:14:55.602211 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-test-shell
150 12:14:55.602357 Updating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-install-packages (oe)
151 12:14:55.602552 Updating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/bin/lava-installed-packages (oe)
152 12:14:55.602712 Creating /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/environment
153 12:14:55.602845 LAVA metadata
154 12:14:55.602953 - LAVA_JOB_ID=12669525
155 12:14:55.603053 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:14:55.603198 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:14:55.603293 skipped lava-vland-overlay
158 12:14:55.603407 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:14:55.603525 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:14:55.603626 skipped lava-multinode-overlay
161 12:14:55.603739 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:14:55.603877 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:14:55.603991 Loading test definitions
164 12:14:55.604125 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:14:55.604234 Using /lava-12669525 at stage 0
166 12:14:55.604657 uuid=12669525_1.5.2.3.1 testdef=None
167 12:14:55.604776 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:14:55.604876 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:14:55.605612 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:14:55.605853 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:14:55.606602 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:14:55.606972 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:14:55.607822 runner path: /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 12669525_1.5.2.3.1
176 12:14:55.608016 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:14:55.608357 Creating lava-test-runner.conf files
179 12:14:55.608455 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12669525/lava-overlay-90srfs_x/lava-12669525/0 for stage 0
180 12:14:55.608567 - 0_v4l2-compliance-mtk-vcodec-enc
181 12:14:55.608675 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:14:55.608772 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:14:55.615508 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:14:55.615618 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:14:55.615736 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:14:55.615902 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:14:55.616004 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:14:56.325226 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:14:56.325692 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:14:56.325824 extracting modules file /var/lib/lava/dispatcher/tmp/12669525/tftp-deploy-lgfg2yfe/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669525/extract-overlay-ramdisk-pxfj7500/ramdisk
191 12:14:56.555101 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:14:56.555268 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:14:56.555361 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669525/compress-overlay-gz1e__mp/overlay-1.5.2.4.tar.gz to ramdisk
194 12:14:56.555430 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669525/compress-overlay-gz1e__mp/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12669525/extract-overlay-ramdisk-pxfj7500/ramdisk
195 12:14:56.562094 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:14:56.562206 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:14:56.562296 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:14:56.562383 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:14:56.562460 Building ramdisk /var/lib/lava/dispatcher/tmp/12669525/extract-overlay-ramdisk-pxfj7500/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12669525/extract-overlay-ramdisk-pxfj7500/ramdisk
200 12:14:57.187441 >> 228443 blocks
201 12:15:01.060980 rename /var/lib/lava/dispatcher/tmp/12669525/extract-overlay-ramdisk-pxfj7500/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12669525/tftp-deploy-lgfg2yfe/ramdisk/ramdisk.cpio.gz
202 12:15:01.061437 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 12:15:01.061623 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 12:15:01.061783 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 12:15:01.061888 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12669525/tftp-deploy-lgfg2yfe/kernel/Image'
206 12:15:13.249230 Returned 0 in 12 seconds
207 12:15:13.350174 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12669525/tftp-deploy-lgfg2yfe/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12669525/tftp-deploy-lgfg2yfe/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12669525/tftp-deploy-lgfg2yfe/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12669525/tftp-deploy-lgfg2yfe/kernel/image.itb
208 12:15:13.982219 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:15:13.982600 output: Created: Wed Jan 31 12:15:13 2024
210 12:15:13.982685 output: Image 0 (kernel-1)
211 12:15:13.982751 output: Description:
212 12:15:13.982812 output: Created: Wed Jan 31 12:15:13 2024
213 12:15:13.982873 output: Type: Kernel Image
214 12:15:13.982935 output: Compression: lzma compressed
215 12:15:13.982997 output: Data Size: 12047284 Bytes = 11764.93 KiB = 11.49 MiB
216 12:15:13.983055 output: Architecture: AArch64
217 12:15:13.983115 output: OS: Linux
218 12:15:13.983172 output: Load Address: 0x00000000
219 12:15:13.983229 output: Entry Point: 0x00000000
220 12:15:13.983287 output: Hash algo: crc32
221 12:15:13.983341 output: Hash value: 5a47eb78
222 12:15:13.983394 output: Image 1 (fdt-1)
223 12:15:13.983446 output: Description: mt8192-asurada-spherion-r0
224 12:15:13.983499 output: Created: Wed Jan 31 12:15:13 2024
225 12:15:13.983551 output: Type: Flat Device Tree
226 12:15:13.983603 output: Compression: uncompressed
227 12:15:13.983655 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 12:15:13.983707 output: Architecture: AArch64
229 12:15:13.983759 output: Hash algo: crc32
230 12:15:13.983811 output: Hash value: cc4352de
231 12:15:13.983863 output: Image 2 (ramdisk-1)
232 12:15:13.983915 output: Description: unavailable
233 12:15:13.983967 output: Created: Wed Jan 31 12:15:13 2024
234 12:15:13.984019 output: Type: RAMDisk Image
235 12:15:13.984070 output: Compression: Unknown Compression
236 12:15:13.984122 output: Data Size: 39354301 Bytes = 38431.93 KiB = 37.53 MiB
237 12:15:13.984174 output: Architecture: AArch64
238 12:15:13.984226 output: OS: Linux
239 12:15:13.984277 output: Load Address: unavailable
240 12:15:13.984329 output: Entry Point: unavailable
241 12:15:13.984380 output: Hash algo: crc32
242 12:15:13.984431 output: Hash value: 9f35971f
243 12:15:13.984483 output: Default Configuration: 'conf-1'
244 12:15:13.984535 output: Configuration 0 (conf-1)
245 12:15:13.984587 output: Description: mt8192-asurada-spherion-r0
246 12:15:13.984639 output: Kernel: kernel-1
247 12:15:13.984691 output: Init Ramdisk: ramdisk-1
248 12:15:13.984743 output: FDT: fdt-1
249 12:15:13.984794 output: Loadables: kernel-1
250 12:15:13.984845 output:
251 12:15:13.985040 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 12:15:13.985137 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 12:15:13.985235 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 12:15:13.985332 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 12:15:13.985411 No LXC device requested
256 12:15:13.985499 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:15:13.985613 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 12:15:13.985692 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:15:13.985765 Checking files for TFTP limit of 4294967296 bytes.
260 12:15:13.986267 end: 1 tftp-deploy (duration 00:00:19) [common]
261 12:15:13.986373 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:15:13.986464 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:15:13.986587 substitutions:
264 12:15:13.986655 - {DTB}: 12669525/tftp-deploy-lgfg2yfe/dtb/mt8192-asurada-spherion-r0.dtb
265 12:15:13.986720 - {INITRD}: 12669525/tftp-deploy-lgfg2yfe/ramdisk/ramdisk.cpio.gz
266 12:15:13.986779 - {KERNEL}: 12669525/tftp-deploy-lgfg2yfe/kernel/Image
267 12:15:13.986835 - {LAVA_MAC}: None
268 12:15:13.986891 - {PRESEED_CONFIG}: None
269 12:15:13.986945 - {PRESEED_LOCAL}: None
270 12:15:13.986998 - {RAMDISK}: 12669525/tftp-deploy-lgfg2yfe/ramdisk/ramdisk.cpio.gz
271 12:15:13.987052 - {ROOT_PART}: None
272 12:15:13.987105 - {ROOT}: None
273 12:15:13.987157 - {SERVER_IP}: 192.168.201.1
274 12:15:13.987210 - {TEE}: None
275 12:15:13.987262 Parsed boot commands:
276 12:15:13.987315 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:15:13.987494 Parsed boot commands: tftpboot 192.168.201.1 12669525/tftp-deploy-lgfg2yfe/kernel/image.itb 12669525/tftp-deploy-lgfg2yfe/kernel/cmdline
278 12:15:13.987581 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:15:13.987667 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:15:13.987760 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:15:13.987841 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:15:13.987913 Not connected, no need to disconnect.
283 12:15:13.987986 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:15:13.988065 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:15:13.988130 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 12:15:13.992048 Setting prompt string to ['lava-test: # ']
287 12:15:13.992403 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:15:13.992509 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:15:13.992607 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:15:13.992698 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:15:13.992898 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 12:15:19.142005 >> Command sent successfully.
293 12:15:19.152579 Returned 0 in 5 seconds
294 12:15:19.253798 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:15:19.255334 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:15:19.255849 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:15:19.256260 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:15:19.256592 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:15:19.256925 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:15:19.258294 [Enter `^Ec?' for help]
302 12:15:19.425314
303 12:15:19.425905
304 12:15:19.426240 F0: 102B 0000
305 12:15:19.426556
306 12:15:19.426868 F3: 1001 0000 [0200]
307 12:15:19.428414
308 12:15:19.428834 F3: 1001 0000
309 12:15:19.429169
310 12:15:19.429510 F7: 102D 0000
311 12:15:19.429832
312 12:15:19.431845 F1: 0000 0000
313 12:15:19.432394
314 12:15:19.432742 V0: 0000 0000 [0001]
315 12:15:19.433070
316 12:15:19.435260 00: 0007 8000
317 12:15:19.435702
318 12:15:19.436045 01: 0000 0000
319 12:15:19.436366
320 12:15:19.438253 BP: 0C00 0209 [0000]
321 12:15:19.438675
322 12:15:19.439011 G0: 1182 0000
323 12:15:19.439320
324 12:15:19.442042 EC: 0000 0021 [4000]
325 12:15:19.442463
326 12:15:19.442800 S7: 0000 0000 [0000]
327 12:15:19.443114
328 12:15:19.445553 CC: 0000 0000 [0001]
329 12:15:19.445977
330 12:15:19.446313 T0: 0000 0040 [010F]
331 12:15:19.446626
332 12:15:19.448537 Jump to BL
333 12:15:19.448953
334 12:15:19.472336
335 12:15:19.472856
336 12:15:19.473192
337 12:15:19.479376 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:15:19.482812 ARM64: Exception handlers installed.
339 12:15:19.486495 ARM64: Testing exception
340 12:15:19.489926 ARM64: Done test exception
341 12:15:19.496764 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:15:19.506789 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:15:19.513109 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:15:19.523327 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:15:19.529970 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:15:19.539957 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:15:19.550570 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:15:19.557555 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:15:19.574943 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:15:19.578404 WDT: Last reset was cold boot
351 12:15:19.581961 SPI1(PAD0) initialized at 2873684 Hz
352 12:15:19.585362 SPI5(PAD0) initialized at 992727 Hz
353 12:15:19.588477 VBOOT: Loading verstage.
354 12:15:19.595324 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:15:19.598618 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:15:19.601721 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:15:19.605083 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:15:19.612551 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:15:19.619132 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:15:19.630404 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
361 12:15:19.630943
362 12:15:19.631283
363 12:15:19.640065 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:15:19.643020 ARM64: Exception handlers installed.
365 12:15:19.646924 ARM64: Testing exception
366 12:15:19.647449 ARM64: Done test exception
367 12:15:19.654744 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:15:19.657630 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:15:19.671565 Probing TPM: . done!
370 12:15:19.672102 TPM ready after 0 ms
371 12:15:19.678206 Connected to device vid:did:rid of 1ae0:0028:00
372 12:15:19.684935 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 12:15:19.762431 Initialized TPM device CR50 revision 0
374 12:15:19.767785 tlcl_send_startup: Startup return code is 0
375 12:15:19.774165 TPM: setup succeeded
376 12:15:19.787092 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:15:19.796084 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:15:19.811753 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:15:19.818957 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:15:19.822184 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:15:19.826011 in-header: 03 07 00 00 08 00 00 00
382 12:15:19.826436 in-data: aa e4 47 04 13 02 00 00
383 12:15:19.829298 Chrome EC: UHEPI supported
384 12:15:19.835598 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:15:19.839263 in-header: 03 95 00 00 08 00 00 00
386 12:15:19.842645 in-data: 18 20 20 08 00 00 00 00
387 12:15:19.843222 Phase 1
388 12:15:19.848992 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:15:19.852901 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:15:19.859797 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:15:19.862899 Recovery requested (1009000e)
392 12:15:19.871272 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:15:19.876489 tlcl_extend: response is 0
394 12:15:19.885986 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:15:19.891309 tlcl_extend: response is 0
396 12:15:19.898346 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:15:19.919294 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
398 12:15:19.926537 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:15:19.927060
400 12:15:19.927410
401 12:15:19.933748 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:15:19.937627 ARM64: Exception handlers installed.
403 12:15:19.941124 ARM64: Testing exception
404 12:15:19.943864 ARM64: Done test exception
405 12:15:19.964607 pmic_efuse_setting: Set efuses in 11 msecs
406 12:15:19.968384 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:15:19.971820 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:15:19.978328 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:15:19.981637 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:15:19.988817 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:15:19.991856 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:15:19.998230 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:15:20.002305 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:15:20.008560 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:15:20.011557 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:15:20.015236 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:15:20.021775 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:15:20.025863 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:15:20.029160 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:15:20.035976 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:15:20.043384 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:15:20.046633 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:15:20.053625 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:15:20.060473 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:15:20.063898 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:15:20.070487 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:15:20.074557 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:15:20.081341 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:15:20.088473 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:15:20.091987 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:15:20.098906 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:15:20.102438 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:15:20.109586 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:15:20.113257 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:15:20.116544 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:15:20.123664 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:15:20.126902 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:15:20.133463 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:15:20.136938 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:15:20.143588 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:15:20.146963 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:15:20.153370 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:15:20.156768 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:15:20.163712 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:15:20.166846 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:15:20.170028 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:15:20.177028 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:15:20.180100 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:15:20.183905 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:15:20.190096 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:15:20.193852 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:15:20.197285 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:15:20.203852 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:15:20.207232 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:15:20.210307 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:15:20.213917 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:15:20.220410 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:15:20.226939 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:15:20.236814 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:15:20.239740 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:15:20.246522 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:15:20.256965 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:15:20.259973 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:15:20.266561 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:15:20.269623 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:15:20.276693 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x23
467 12:15:20.283266 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:15:20.286555 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 12:15:20.289828 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:15:20.301106 [RTC]rtc_get_frequency_meter,154: input=15, output=794
471 12:15:20.304306 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 12:15:20.308370 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 12:15:20.315037 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 12:15:20.318660 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 12:15:20.321861 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 12:15:20.325005 ADC[4]: Raw value=895191 ID=7
477 12:15:20.328540 ADC[3]: Raw value=213070 ID=1
478 12:15:20.329065 RAM Code: 0x71
479 12:15:20.336014 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 12:15:20.339392 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 12:15:20.346698 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 12:15:20.353647 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 12:15:20.357093 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 12:15:20.360732 in-header: 03 07 00 00 08 00 00 00
485 12:15:20.364440 in-data: aa e4 47 04 13 02 00 00
486 12:15:20.368000 Chrome EC: UHEPI supported
487 12:15:20.374423 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 12:15:20.377753 in-header: 03 d5 00 00 08 00 00 00
489 12:15:20.381066 in-data: 98 20 60 08 00 00 00 00
490 12:15:20.384271 MRC: failed to locate region type 0.
491 12:15:20.390863 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 12:15:20.394429 DRAM-K: Running full calibration
493 12:15:20.400809 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 12:15:20.401240 header.status = 0x0
495 12:15:20.404264 header.version = 0x6 (expected: 0x6)
496 12:15:20.407418 header.size = 0xd00 (expected: 0xd00)
497 12:15:20.410860 header.flags = 0x0
498 12:15:20.417407 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 12:15:20.434018 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
500 12:15:20.440593 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 12:15:20.443951 dram_init: ddr_geometry: 2
502 12:15:20.447050 [EMI] MDL number = 2
503 12:15:20.447499 [EMI] Get MDL freq = 0
504 12:15:20.450659 dram_init: ddr_type: 0
505 12:15:20.451083 is_discrete_lpddr4: 1
506 12:15:20.453919 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 12:15:20.454347
508 12:15:20.454684
509 12:15:20.457312 [Bian_co] ETT version 0.0.0.1
510 12:15:20.463969 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 12:15:20.464397
512 12:15:20.467683 dramc_set_vcore_voltage set vcore to 650000
513 12:15:20.468209 Read voltage for 800, 4
514 12:15:20.470750 Vio18 = 0
515 12:15:20.471174 Vcore = 650000
516 12:15:20.471510 Vdram = 0
517 12:15:20.474069 Vddq = 0
518 12:15:20.474490 Vmddr = 0
519 12:15:20.477423 dram_init: config_dvfs: 1
520 12:15:20.480682 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 12:15:20.487851 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 12:15:20.490755 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 12:15:20.494081 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 12:15:20.497372 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 12:15:20.500642 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 12:15:20.504111 MEM_TYPE=3, freq_sel=18
527 12:15:20.507538 sv_algorithm_assistance_LP4_1600
528 12:15:20.510869 ============ PULL DRAM RESETB DOWN ============
529 12:15:20.514069 ========== PULL DRAM RESETB DOWN end =========
530 12:15:20.521021 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 12:15:20.524043 ===================================
532 12:15:20.527255 LPDDR4 DRAM CONFIGURATION
533 12:15:20.530688 ===================================
534 12:15:20.531210 EX_ROW_EN[0] = 0x0
535 12:15:20.534131 EX_ROW_EN[1] = 0x0
536 12:15:20.534652 LP4Y_EN = 0x0
537 12:15:20.537293 WORK_FSP = 0x0
538 12:15:20.537757 WL = 0x2
539 12:15:20.540463 RL = 0x2
540 12:15:20.540879 BL = 0x2
541 12:15:20.544348 RPST = 0x0
542 12:15:20.544848 RD_PRE = 0x0
543 12:15:20.547950 WR_PRE = 0x1
544 12:15:20.548387 WR_PST = 0x0
545 12:15:20.551668 DBI_WR = 0x0
546 12:15:20.552103 DBI_RD = 0x0
547 12:15:20.555379 OTF = 0x1
548 12:15:20.555800 ===================================
549 12:15:20.559295 ===================================
550 12:15:20.562924 ANA top config
551 12:15:20.566390 ===================================
552 12:15:20.566835 DLL_ASYNC_EN = 0
553 12:15:20.570396 ALL_SLAVE_EN = 1
554 12:15:20.574157 NEW_RANK_MODE = 1
555 12:15:20.574626 DLL_IDLE_MODE = 1
556 12:15:20.577696 LP45_APHY_COMB_EN = 1
557 12:15:20.581790 TX_ODT_DIS = 1
558 12:15:20.582501 NEW_8X_MODE = 1
559 12:15:20.585265 ===================================
560 12:15:20.589228 ===================================
561 12:15:20.593084 data_rate = 1600
562 12:15:20.596576 CKR = 1
563 12:15:20.597199 DQ_P2S_RATIO = 8
564 12:15:20.600559 ===================================
565 12:15:20.603997 CA_P2S_RATIO = 8
566 12:15:20.607989 DQ_CA_OPEN = 0
567 12:15:20.612144 DQ_SEMI_OPEN = 0
568 12:15:20.612874 CA_SEMI_OPEN = 0
569 12:15:20.615321 CA_FULL_RATE = 0
570 12:15:20.619229 DQ_CKDIV4_EN = 1
571 12:15:20.619894 CA_CKDIV4_EN = 1
572 12:15:20.623051 CA_PREDIV_EN = 0
573 12:15:20.626805 PH8_DLY = 0
574 12:15:20.630572 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 12:15:20.631297 DQ_AAMCK_DIV = 4
576 12:15:20.633657 CA_AAMCK_DIV = 4
577 12:15:20.636970 CA_ADMCK_DIV = 4
578 12:15:20.640097 DQ_TRACK_CA_EN = 0
579 12:15:20.643367 CA_PICK = 800
580 12:15:20.646664 CA_MCKIO = 800
581 12:15:20.650030 MCKIO_SEMI = 0
582 12:15:20.650457 PLL_FREQ = 3068
583 12:15:20.653394 DQ_UI_PI_RATIO = 32
584 12:15:20.656921 CA_UI_PI_RATIO = 0
585 12:15:20.660402 ===================================
586 12:15:20.663813 ===================================
587 12:15:20.666727 memory_type:LPDDR4
588 12:15:20.667154 GP_NUM : 10
589 12:15:20.670041 SRAM_EN : 1
590 12:15:20.673260 MD32_EN : 0
591 12:15:20.676865 ===================================
592 12:15:20.677390 [ANA_INIT] >>>>>>>>>>>>>>
593 12:15:20.680362 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 12:15:20.683901 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 12:15:20.687843 ===================================
596 12:15:20.690613 data_rate = 1600,PCW = 0X7600
597 12:15:20.694248 ===================================
598 12:15:20.697907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 12:15:20.702027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 12:15:20.709065 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 12:15:20.712308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 12:15:20.715964 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 12:15:20.719867 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 12:15:20.723422 [ANA_INIT] flow start
605 12:15:20.723852 [ANA_INIT] PLL >>>>>>>>
606 12:15:20.726885 [ANA_INIT] PLL <<<<<<<<
607 12:15:20.727478 [ANA_INIT] MIDPI >>>>>>>>
608 12:15:20.730190 [ANA_INIT] MIDPI <<<<<<<<
609 12:15:20.733888 [ANA_INIT] DLL >>>>>>>>
610 12:15:20.734410 [ANA_INIT] flow end
611 12:15:20.740701 ============ LP4 DIFF to SE enter ============
612 12:15:20.743789 ============ LP4 DIFF to SE exit ============
613 12:15:20.746802 [ANA_INIT] <<<<<<<<<<<<<
614 12:15:20.750328 [Flow] Enable top DCM control >>>>>
615 12:15:20.753999 [Flow] Enable top DCM control <<<<<
616 12:15:20.754520 Enable DLL master slave shuffle
617 12:15:20.760715 ==============================================================
618 12:15:20.763833 Gating Mode config
619 12:15:20.766956 ==============================================================
620 12:15:20.770408 Config description:
621 12:15:20.780722 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 12:15:20.786748 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 12:15:20.790352 SELPH_MODE 0: By rank 1: By Phase
624 12:15:20.797008 ==============================================================
625 12:15:20.800318 GAT_TRACK_EN = 1
626 12:15:20.803343 RX_GATING_MODE = 2
627 12:15:20.807214 RX_GATING_TRACK_MODE = 2
628 12:15:20.807735 SELPH_MODE = 1
629 12:15:20.810471 PICG_EARLY_EN = 1
630 12:15:20.813568 VALID_LAT_VALUE = 1
631 12:15:20.820573 ==============================================================
632 12:15:20.823807 Enter into Gating configuration >>>>
633 12:15:20.827080 Exit from Gating configuration <<<<
634 12:15:20.830467 Enter into DVFS_PRE_config >>>>>
635 12:15:20.840291 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 12:15:20.843980 Exit from DVFS_PRE_config <<<<<
637 12:15:20.847190 Enter into PICG configuration >>>>
638 12:15:20.850187 Exit from PICG configuration <<<<
639 12:15:20.853569 [RX_INPUT] configuration >>>>>
640 12:15:20.857103 [RX_INPUT] configuration <<<<<
641 12:15:20.860645 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 12:15:20.867007 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 12:15:20.874063 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 12:15:20.877136 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 12:15:20.883994 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 12:15:20.890873 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 12:15:20.894352 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 12:15:20.897096 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 12:15:20.903677 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 12:15:20.907786 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 12:15:20.910708 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 12:15:20.917360 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 12:15:20.920938 ===================================
654 12:15:20.921539 LPDDR4 DRAM CONFIGURATION
655 12:15:20.923621 ===================================
656 12:15:20.927303 EX_ROW_EN[0] = 0x0
657 12:15:20.930545 EX_ROW_EN[1] = 0x0
658 12:15:20.931080 LP4Y_EN = 0x0
659 12:15:20.933751 WORK_FSP = 0x0
660 12:15:20.934184 WL = 0x2
661 12:15:20.937115 RL = 0x2
662 12:15:20.937590 BL = 0x2
663 12:15:20.940422 RPST = 0x0
664 12:15:20.940852 RD_PRE = 0x0
665 12:15:20.943614 WR_PRE = 0x1
666 12:15:20.944044 WR_PST = 0x0
667 12:15:20.947290 DBI_WR = 0x0
668 12:15:20.947721 DBI_RD = 0x0
669 12:15:20.950361 OTF = 0x1
670 12:15:20.954004 ===================================
671 12:15:20.957510 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 12:15:20.960653 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 12:15:20.964170 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 12:15:20.967193 ===================================
675 12:15:20.970452 LPDDR4 DRAM CONFIGURATION
676 12:15:20.973820 ===================================
677 12:15:20.977300 EX_ROW_EN[0] = 0x10
678 12:15:20.977832 EX_ROW_EN[1] = 0x0
679 12:15:20.980911 LP4Y_EN = 0x0
680 12:15:20.981444 WORK_FSP = 0x0
681 12:15:20.983930 WL = 0x2
682 12:15:20.984463 RL = 0x2
683 12:15:20.987097 BL = 0x2
684 12:15:20.990694 RPST = 0x0
685 12:15:20.991220 RD_PRE = 0x0
686 12:15:20.993936 WR_PRE = 0x1
687 12:15:20.994368 WR_PST = 0x0
688 12:15:20.996916 DBI_WR = 0x0
689 12:15:20.997346 DBI_RD = 0x0
690 12:15:21.000193 OTF = 0x1
691 12:15:21.004071 ===================================
692 12:15:21.007525 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 12:15:21.012508 nWR fixed to 40
694 12:15:21.016187 [ModeRegInit_LP4] CH0 RK0
695 12:15:21.016719 [ModeRegInit_LP4] CH0 RK1
696 12:15:21.019128 [ModeRegInit_LP4] CH1 RK0
697 12:15:21.022354 [ModeRegInit_LP4] CH1 RK1
698 12:15:21.022773 match AC timing 13
699 12:15:21.029103 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 12:15:21.032521 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 12:15:21.036031 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 12:15:21.042213 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 12:15:21.046192 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 12:15:21.046716 [EMI DOE] emi_dcm 0
705 12:15:21.052639 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 12:15:21.053167 ==
707 12:15:21.056523 Dram Type= 6, Freq= 0, CH_0, rank 0
708 12:15:21.059903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 12:15:21.060453 ==
710 12:15:21.063299 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 12:15:21.070359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 12:15:21.080168 [CA 0] Center 38 (7~69) winsize 63
713 12:15:21.083867 [CA 1] Center 37 (7~68) winsize 62
714 12:15:21.087198 [CA 2] Center 35 (5~66) winsize 62
715 12:15:21.090899 [CA 3] Center 35 (5~66) winsize 62
716 12:15:21.094704 [CA 4] Center 34 (4~65) winsize 62
717 12:15:21.098302 [CA 5] Center 34 (4~65) winsize 62
718 12:15:21.098720
719 12:15:21.101848 [CmdBusTrainingLP45] Vref(ca) range 1: 32
720 12:15:21.102384
721 12:15:21.105336 [CATrainingPosCal] consider 1 rank data
722 12:15:21.109386 u2DelayCellTimex100 = 270/100 ps
723 12:15:21.112985 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 12:15:21.116567 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 12:15:21.120544 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 12:15:21.121085 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 12:15:21.124379 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 12:15:21.128003 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 12:15:21.128736
730 12:15:21.131895 CA PerBit enable=1, Macro0, CA PI delay=34
731 12:15:21.132413
732 12:15:21.135435 [CBTSetCACLKResult] CA Dly = 34
733 12:15:21.139144 CS Dly: 6 (0~37)
734 12:15:21.139561 ==
735 12:15:21.142751 Dram Type= 6, Freq= 0, CH_0, rank 1
736 12:15:21.146530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 12:15:21.147173 ==
738 12:15:21.150259 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 12:15:21.157353 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 12:15:21.166953 [CA 0] Center 38 (7~69) winsize 63
741 12:15:21.170057 [CA 1] Center 38 (7~69) winsize 63
742 12:15:21.173662 [CA 2] Center 35 (5~66) winsize 62
743 12:15:21.177784 [CA 3] Center 35 (5~66) winsize 62
744 12:15:21.181462 [CA 4] Center 34 (4~65) winsize 62
745 12:15:21.184985 [CA 5] Center 34 (4~65) winsize 62
746 12:15:21.185405
747 12:15:21.189182 [CmdBusTrainingLP45] Vref(ca) range 1: 34
748 12:15:21.189987
749 12:15:21.190451 [CATrainingPosCal] consider 2 rank data
750 12:15:21.192772 u2DelayCellTimex100 = 270/100 ps
751 12:15:21.196473 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 12:15:21.200156 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 12:15:21.204100 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 12:15:21.207278 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 12:15:21.211515 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 12:15:21.215196 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 12:15:21.215719
758 12:15:21.218983 CA PerBit enable=1, Macro0, CA PI delay=34
759 12:15:21.219403
760 12:15:21.222390 [CBTSetCACLKResult] CA Dly = 34
761 12:15:21.225810 CS Dly: 6 (0~38)
762 12:15:21.226231
763 12:15:21.229980 ----->DramcWriteLeveling(PI) begin...
764 12:15:21.230421 ==
765 12:15:21.230755 Dram Type= 6, Freq= 0, CH_0, rank 0
766 12:15:21.237438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 12:15:21.238008 ==
768 12:15:21.238345 Write leveling (Byte 0): 33 => 33
769 12:15:21.241188 Write leveling (Byte 1): 31 => 31
770 12:15:21.245172 DramcWriteLeveling(PI) end<-----
771 12:15:21.245738
772 12:15:21.246078 ==
773 12:15:21.248686 Dram Type= 6, Freq= 0, CH_0, rank 0
774 12:15:21.252016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 12:15:21.252439 ==
776 12:15:21.255952 [Gating] SW mode calibration
777 12:15:21.263328 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 12:15:21.266971 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 12:15:21.270878 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 12:15:21.278469 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 12:15:21.281900 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
782 12:15:21.285813 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 12:15:21.289068 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 12:15:21.292730 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 12:15:21.296822 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 12:15:21.304110 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 12:15:21.307525 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 12:15:21.311206 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 12:15:21.314874 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:15:21.322180 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:15:21.325771 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:15:21.329854 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:15:21.333416 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:15:21.337427 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:15:21.340830 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:15:21.348114 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:15:21.351774 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
798 12:15:21.355448 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
799 12:15:21.359446 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:15:21.363086 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:15:21.370675 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:15:21.374408 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:15:21.378274 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:15:21.381900 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:15:21.385255 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:15:21.392053 0 9 12 | B1->B0 | 2525 3333 | 0 1 | (0 0) (1 1)
807 12:15:21.395088 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 12:15:21.398456 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 12:15:21.404913 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 12:15:21.408390 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 12:15:21.411691 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 12:15:21.418383 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 12:15:21.421938 0 10 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
814 12:15:21.424838 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
815 12:15:21.431781 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:15:21.434663 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:15:21.438167 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:15:21.444942 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 12:15:21.448238 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 12:15:21.451578 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 12:15:21.458291 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
822 12:15:21.461701 0 11 12 | B1->B0 | 3232 4343 | 1 1 | (0 0) (0 0)
823 12:15:21.465141 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 12:15:21.468201 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 12:15:21.474603 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 12:15:21.478107 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 12:15:21.481663 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 12:15:21.488254 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 12:15:21.491633 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 12:15:21.495032 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 12:15:21.501184 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 12:15:21.504603 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 12:15:21.508060 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 12:15:21.515037 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 12:15:21.517972 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 12:15:21.521334 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 12:15:21.528212 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:15:21.531754 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:15:21.534635 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:15:21.541610 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:15:21.544966 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:15:21.548234 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:15:21.554769 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:15:21.557776 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:15:21.561265 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 12:15:21.568255 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 12:15:21.568791 Total UI for P1: 0, mck2ui 16
848 12:15:21.571203 best dqsien dly found for B0: ( 0, 14, 8)
849 12:15:21.577890 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 12:15:21.581454 Total UI for P1: 0, mck2ui 16
851 12:15:21.584732 best dqsien dly found for B1: ( 0, 14, 12)
852 12:15:21.588161 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
853 12:15:21.591566 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 12:15:21.592093
855 12:15:21.594765 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
856 12:15:21.598068 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 12:15:21.601046 [Gating] SW calibration Done
858 12:15:21.601505 ==
859 12:15:21.604532 Dram Type= 6, Freq= 0, CH_0, rank 0
860 12:15:21.608065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 12:15:21.608486 ==
862 12:15:21.611085 RX Vref Scan: 0
863 12:15:21.611506
864 12:15:21.611836 RX Vref 0 -> 0, step: 1
865 12:15:21.614917
866 12:15:21.615499 RX Delay -130 -> 252, step: 16
867 12:15:21.621642 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
868 12:15:21.624636 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 12:15:21.628404 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 12:15:21.631750 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 12:15:21.635133 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 12:15:21.641451 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
873 12:15:21.644997 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 12:15:21.648469 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 12:15:21.651511 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 12:15:21.654619 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 12:15:21.657961 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 12:15:21.664778 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 12:15:21.668706 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 12:15:21.672114 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 12:15:21.675114 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
882 12:15:21.678395 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 12:15:21.678857 ==
884 12:15:21.682033 Dram Type= 6, Freq= 0, CH_0, rank 0
885 12:15:21.688868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 12:15:21.689400 ==
887 12:15:21.689802 DQS Delay:
888 12:15:21.691983 DQS0 = 0, DQS1 = 0
889 12:15:21.692405 DQM Delay:
890 12:15:21.695263 DQM0 = 80, DQM1 = 70
891 12:15:21.695823 DQ Delay:
892 12:15:21.698300 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
893 12:15:21.701853 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
894 12:15:21.705423 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
895 12:15:21.708737 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
896 12:15:21.709261
897 12:15:21.709644
898 12:15:21.709954 ==
899 12:15:21.712082 Dram Type= 6, Freq= 0, CH_0, rank 0
900 12:15:21.715309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 12:15:21.715842 ==
902 12:15:21.716188
903 12:15:21.716499
904 12:15:21.718536 TX Vref Scan disable
905 12:15:21.721963 == TX Byte 0 ==
906 12:15:21.725097 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
907 12:15:21.728940 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
908 12:15:21.731909 == TX Byte 1 ==
909 12:15:21.735199 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
910 12:15:21.738914 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
911 12:15:21.739440 ==
912 12:15:21.742178 Dram Type= 6, Freq= 0, CH_0, rank 0
913 12:15:21.745374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 12:15:21.745945 ==
915 12:15:21.759766 TX Vref=22, minBit 0, minWin=27, winSum=435
916 12:15:21.762887 TX Vref=24, minBit 11, minWin=26, winSum=436
917 12:15:21.766534 TX Vref=26, minBit 0, minWin=27, winSum=438
918 12:15:21.769662 TX Vref=28, minBit 11, minWin=27, winSum=446
919 12:15:21.773043 TX Vref=30, minBit 12, minWin=26, winSum=440
920 12:15:21.779647 TX Vref=32, minBit 0, minWin=27, winSum=438
921 12:15:21.783343 [TxChooseVref] Worse bit 11, Min win 27, Win sum 446, Final Vref 28
922 12:15:21.783874
923 12:15:21.786406 Final TX Range 1 Vref 28
924 12:15:21.786942
925 12:15:21.787277 ==
926 12:15:21.789552 Dram Type= 6, Freq= 0, CH_0, rank 0
927 12:15:21.793275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 12:15:21.796341 ==
929 12:15:21.796867
930 12:15:21.797198
931 12:15:21.797554 TX Vref Scan disable
932 12:15:21.800039 == TX Byte 0 ==
933 12:15:21.803081 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
934 12:15:21.806538 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
935 12:15:21.810412 == TX Byte 1 ==
936 12:15:21.813363 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
937 12:15:21.816967 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
938 12:15:21.817592
939 12:15:21.820298 [DATLAT]
940 12:15:21.820832 Freq=800, CH0 RK0
941 12:15:21.821182
942 12:15:21.823343 DATLAT Default: 0xa
943 12:15:21.823889 0, 0xFFFF, sum = 0
944 12:15:21.826676 1, 0xFFFF, sum = 0
945 12:15:21.827112 2, 0xFFFF, sum = 0
946 12:15:21.829673 3, 0xFFFF, sum = 0
947 12:15:21.830100 4, 0xFFFF, sum = 0
948 12:15:21.833360 5, 0xFFFF, sum = 0
949 12:15:21.833820 6, 0xFFFF, sum = 0
950 12:15:21.836365 7, 0xFFFF, sum = 0
951 12:15:21.836821 8, 0xFFFF, sum = 0
952 12:15:21.839685 9, 0x0, sum = 1
953 12:15:21.840110 10, 0x0, sum = 2
954 12:15:21.843276 11, 0x0, sum = 3
955 12:15:21.843707 12, 0x0, sum = 4
956 12:15:21.846735 best_step = 10
957 12:15:21.847276
958 12:15:21.847619 ==
959 12:15:21.850447 Dram Type= 6, Freq= 0, CH_0, rank 0
960 12:15:21.853161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 12:15:21.853643 ==
962 12:15:21.856932 RX Vref Scan: 1
963 12:15:21.857455
964 12:15:21.857845 Set Vref Range= 32 -> 127
965 12:15:21.858159
966 12:15:21.860507 RX Vref 32 -> 127, step: 1
967 12:15:21.861034
968 12:15:21.863322 RX Delay -111 -> 252, step: 8
969 12:15:21.863743
970 12:15:21.866933 Set Vref, RX VrefLevel [Byte0]: 32
971 12:15:21.870280 [Byte1]: 32
972 12:15:21.870808
973 12:15:21.873317 Set Vref, RX VrefLevel [Byte0]: 33
974 12:15:21.876623 [Byte1]: 33
975 12:15:21.880753
976 12:15:21.881284 Set Vref, RX VrefLevel [Byte0]: 34
977 12:15:21.883590 [Byte1]: 34
978 12:15:21.888001
979 12:15:21.888519 Set Vref, RX VrefLevel [Byte0]: 35
980 12:15:21.891450 [Byte1]: 35
981 12:15:21.895973
982 12:15:21.896499 Set Vref, RX VrefLevel [Byte0]: 36
983 12:15:21.899088 [Byte1]: 36
984 12:15:21.903621
985 12:15:21.904151 Set Vref, RX VrefLevel [Byte0]: 37
986 12:15:21.906565 [Byte1]: 37
987 12:15:21.911179
988 12:15:21.911736 Set Vref, RX VrefLevel [Byte0]: 38
989 12:15:21.914395 [Byte1]: 38
990 12:15:21.918509
991 12:15:21.919032 Set Vref, RX VrefLevel [Byte0]: 39
992 12:15:21.922045 [Byte1]: 39
993 12:15:21.926289
994 12:15:21.926817 Set Vref, RX VrefLevel [Byte0]: 40
995 12:15:21.929926 [Byte1]: 40
996 12:15:21.934370
997 12:15:21.934895 Set Vref, RX VrefLevel [Byte0]: 41
998 12:15:21.937601 [Byte1]: 41
999 12:15:21.941856
1000 12:15:21.942272 Set Vref, RX VrefLevel [Byte0]: 42
1001 12:15:21.944884 [Byte1]: 42
1002 12:15:21.949533
1003 12:15:21.949961 Set Vref, RX VrefLevel [Byte0]: 43
1004 12:15:21.952788 [Byte1]: 43
1005 12:15:21.957168
1006 12:15:21.957626 Set Vref, RX VrefLevel [Byte0]: 44
1007 12:15:21.960398 [Byte1]: 44
1008 12:15:21.964658
1009 12:15:21.965183 Set Vref, RX VrefLevel [Byte0]: 45
1010 12:15:21.968393 [Byte1]: 45
1011 12:15:21.972047
1012 12:15:21.972585 Set Vref, RX VrefLevel [Byte0]: 46
1013 12:15:21.975711 [Byte1]: 46
1014 12:15:21.979739
1015 12:15:21.980160 Set Vref, RX VrefLevel [Byte0]: 47
1016 12:15:21.983221 [Byte1]: 47
1017 12:15:21.987611
1018 12:15:21.988183 Set Vref, RX VrefLevel [Byte0]: 48
1019 12:15:21.990808 [Byte1]: 48
1020 12:15:21.995302
1021 12:15:21.995826 Set Vref, RX VrefLevel [Byte0]: 49
1022 12:15:21.998459 [Byte1]: 49
1023 12:15:22.002436
1024 12:15:22.002878 Set Vref, RX VrefLevel [Byte0]: 50
1025 12:15:22.006311 [Byte1]: 50
1026 12:15:22.010539
1027 12:15:22.011054 Set Vref, RX VrefLevel [Byte0]: 51
1028 12:15:22.016797 [Byte1]: 51
1029 12:15:22.017313
1030 12:15:22.020265 Set Vref, RX VrefLevel [Byte0]: 52
1031 12:15:22.023291 [Byte1]: 52
1032 12:15:22.023809
1033 12:15:22.026464 Set Vref, RX VrefLevel [Byte0]: 53
1034 12:15:22.030128 [Byte1]: 53
1035 12:15:22.033513
1036 12:15:22.034039 Set Vref, RX VrefLevel [Byte0]: 54
1037 12:15:22.036739 [Byte1]: 54
1038 12:15:22.040858
1039 12:15:22.041267 Set Vref, RX VrefLevel [Byte0]: 55
1040 12:15:22.044196 [Byte1]: 55
1041 12:15:22.048744
1042 12:15:22.049266 Set Vref, RX VrefLevel [Byte0]: 56
1043 12:15:22.052240 [Byte1]: 56
1044 12:15:22.056213
1045 12:15:22.056631 Set Vref, RX VrefLevel [Byte0]: 57
1046 12:15:22.059503 [Byte1]: 57
1047 12:15:22.064149
1048 12:15:22.064668 Set Vref, RX VrefLevel [Byte0]: 58
1049 12:15:22.066959 [Byte1]: 58
1050 12:15:22.071559
1051 12:15:22.072070 Set Vref, RX VrefLevel [Byte0]: 59
1052 12:15:22.075010 [Byte1]: 59
1053 12:15:22.079297
1054 12:15:22.079813 Set Vref, RX VrefLevel [Byte0]: 60
1055 12:15:22.082591 [Byte1]: 60
1056 12:15:22.086598
1057 12:15:22.087095 Set Vref, RX VrefLevel [Byte0]: 61
1058 12:15:22.090375 [Byte1]: 61
1059 12:15:22.094418
1060 12:15:22.094915 Set Vref, RX VrefLevel [Byte0]: 62
1061 12:15:22.097890 [Byte1]: 62
1062 12:15:22.102157
1063 12:15:22.102663 Set Vref, RX VrefLevel [Byte0]: 63
1064 12:15:22.105555 [Byte1]: 63
1065 12:15:22.109789
1066 12:15:22.110310 Set Vref, RX VrefLevel [Byte0]: 64
1067 12:15:22.113203 [Byte1]: 64
1068 12:15:22.117629
1069 12:15:22.118150 Set Vref, RX VrefLevel [Byte0]: 65
1070 12:15:22.120754 [Byte1]: 65
1071 12:15:22.125194
1072 12:15:22.125805 Set Vref, RX VrefLevel [Byte0]: 66
1073 12:15:22.128569 [Byte1]: 66
1074 12:15:22.132958
1075 12:15:22.133507 Set Vref, RX VrefLevel [Byte0]: 67
1076 12:15:22.136048 [Byte1]: 67
1077 12:15:22.140317
1078 12:15:22.140730 Set Vref, RX VrefLevel [Byte0]: 68
1079 12:15:22.143642 [Byte1]: 68
1080 12:15:22.148006
1081 12:15:22.148522 Set Vref, RX VrefLevel [Byte0]: 69
1082 12:15:22.151463 [Byte1]: 69
1083 12:15:22.155437
1084 12:15:22.155851 Set Vref, RX VrefLevel [Byte0]: 70
1085 12:15:22.158798 [Byte1]: 70
1086 12:15:22.163262
1087 12:15:22.163695 Set Vref, RX VrefLevel [Byte0]: 71
1088 12:15:22.166501 [Byte1]: 71
1089 12:15:22.170802
1090 12:15:22.171212 Set Vref, RX VrefLevel [Byte0]: 72
1091 12:15:22.174261 [Byte1]: 72
1092 12:15:22.178550
1093 12:15:22.179065 Set Vref, RX VrefLevel [Byte0]: 73
1094 12:15:22.181869 [Byte1]: 73
1095 12:15:22.186301
1096 12:15:22.186816 Set Vref, RX VrefLevel [Byte0]: 74
1097 12:15:22.189763 [Byte1]: 74
1098 12:15:22.193881
1099 12:15:22.194449 Set Vref, RX VrefLevel [Byte0]: 75
1100 12:15:22.197239 [Byte1]: 75
1101 12:15:22.201860
1102 12:15:22.202368 Set Vref, RX VrefLevel [Byte0]: 76
1103 12:15:22.204904 [Byte1]: 76
1104 12:15:22.209130
1105 12:15:22.209703 Set Vref, RX VrefLevel [Byte0]: 77
1106 12:15:22.212628 [Byte1]: 77
1107 12:15:22.216994
1108 12:15:22.217549 Set Vref, RX VrefLevel [Byte0]: 78
1109 12:15:22.220177 [Byte1]: 78
1110 12:15:22.224737
1111 12:15:22.225247 Set Vref, RX VrefLevel [Byte0]: 79
1112 12:15:22.227827 [Byte1]: 79
1113 12:15:22.232333
1114 12:15:22.232831 Final RX Vref Byte 0 = 60 to rank0
1115 12:15:22.235608 Final RX Vref Byte 1 = 63 to rank0
1116 12:15:22.239301 Final RX Vref Byte 0 = 60 to rank1
1117 12:15:22.241861 Final RX Vref Byte 1 = 63 to rank1==
1118 12:15:22.245215 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 12:15:22.251710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 12:15:22.252216 ==
1121 12:15:22.252549 DQS Delay:
1122 12:15:22.252855 DQS0 = 0, DQS1 = 0
1123 12:15:22.255127 DQM Delay:
1124 12:15:22.255557 DQM0 = 82, DQM1 = 68
1125 12:15:22.258362 DQ Delay:
1126 12:15:22.261891 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1127 12:15:22.265190 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1128 12:15:22.265750 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1129 12:15:22.272018 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1130 12:15:22.272538
1131 12:15:22.272865
1132 12:15:22.278530 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1133 12:15:22.282128 CH0 RK0: MR19=606, MR18=2626
1134 12:15:22.288520 CH0_RK0: MR19=0x606, MR18=0x2626, DQSOSC=400, MR23=63, INC=92, DEC=61
1135 12:15:22.289098
1136 12:15:22.292181 ----->DramcWriteLeveling(PI) begin...
1137 12:15:22.292708 ==
1138 12:15:22.295119 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 12:15:22.298582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 12:15:22.299098 ==
1141 12:15:22.302095 Write leveling (Byte 0): 31 => 31
1142 12:15:22.305574 Write leveling (Byte 1): 31 => 31
1143 12:15:22.308482 DramcWriteLeveling(PI) end<-----
1144 12:15:22.308894
1145 12:15:22.309218 ==
1146 12:15:22.311978 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 12:15:22.315043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 12:15:22.315457 ==
1149 12:15:22.318297 [Gating] SW mode calibration
1150 12:15:22.325315 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 12:15:22.331748 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 12:15:22.335308 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 12:15:22.338493 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 12:15:22.345161 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 12:15:22.389153 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 12:15:22.389812 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:15:22.390301 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:15:22.390821 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:15:22.391554 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:15:22.391887 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:15:22.392185 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:15:22.392474 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:15:22.392812 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:15:22.393091 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:15:22.433312 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:15:22.434354 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:15:22.434710 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:15:22.435019 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:15:22.435316 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1170 12:15:22.435602 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1171 12:15:22.435884 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1172 12:15:22.436161 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:15:22.436436 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:15:22.436709 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:15:22.446509 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:15:22.447342 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:15:22.447689 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:15:22.449730 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1179 12:15:22.453034 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (1 1) (1 1)
1180 12:15:22.459883 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 12:15:22.462932 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 12:15:22.466710 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 12:15:22.473364 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:15:22.476589 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:15:22.479472 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1186 12:15:22.482966 0 10 8 | B1->B0 | 3131 2626 | 1 0 | (1 0) (1 0)
1187 12:15:22.489970 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:15:22.493470 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:15:22.496511 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:15:22.502934 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:15:22.506653 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:15:22.510187 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:15:22.514161 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:15:22.521351 0 11 8 | B1->B0 | 3030 3b3b | 0 0 | (0 0) (0 0)
1195 12:15:22.524561 0 11 12 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
1196 12:15:22.527882 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 12:15:22.535044 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 12:15:22.538310 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 12:15:22.541598 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:15:22.544975 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 12:15:22.551770 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 12:15:22.554953 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1203 12:15:22.558615 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:15:22.564924 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:15:22.568704 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:15:22.571619 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:15:22.578826 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:15:22.581870 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:15:22.585196 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:15:22.592195 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:15:22.595115 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:15:22.598440 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:15:22.601457 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:15:22.608454 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:15:22.611621 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:15:22.615184 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:15:22.621964 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:15:22.625023 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 12:15:22.628512 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 12:15:22.631929 Total UI for P1: 0, mck2ui 16
1221 12:15:22.634998 best dqsien dly found for B0: ( 0, 14, 8)
1222 12:15:22.638467 Total UI for P1: 0, mck2ui 16
1223 12:15:22.641718 best dqsien dly found for B1: ( 0, 14, 8)
1224 12:15:22.645006 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1225 12:15:22.648701 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 12:15:22.649218
1227 12:15:22.655008 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 12:15:22.658387 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 12:15:22.658807 [Gating] SW calibration Done
1230 12:15:22.661816 ==
1231 12:15:22.662236 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 12:15:22.668480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 12:15:22.668998 ==
1234 12:15:22.669327 RX Vref Scan: 0
1235 12:15:22.669700
1236 12:15:22.671768 RX Vref 0 -> 0, step: 1
1237 12:15:22.672184
1238 12:15:22.675016 RX Delay -130 -> 252, step: 16
1239 12:15:22.678187 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1240 12:15:22.681690 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1241 12:15:22.685324 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1242 12:15:22.691777 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1243 12:15:22.695105 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1244 12:15:22.698224 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1245 12:15:22.701837 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1246 12:15:22.704959 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1247 12:15:22.711850 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1248 12:15:22.715294 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1249 12:15:22.718502 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1250 12:15:22.722084 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1251 12:15:22.725366 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1252 12:15:22.732030 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1253 12:15:22.734703 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1254 12:15:22.738353 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1255 12:15:22.738876 ==
1256 12:15:22.741225 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 12:15:22.744944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 12:15:22.748383 ==
1259 12:15:22.749071 DQS Delay:
1260 12:15:22.749417 DQS0 = 0, DQS1 = 0
1261 12:15:22.751469 DQM Delay:
1262 12:15:22.751993 DQM0 = 79, DQM1 = 72
1263 12:15:22.754619 DQ Delay:
1264 12:15:22.757911 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1265 12:15:22.758346 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =85
1266 12:15:22.761703 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1267 12:15:22.764950 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1268 12:15:22.768353
1269 12:15:22.768871
1270 12:15:22.769200 ==
1271 12:15:22.771457 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 12:15:22.774643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 12:15:22.775069 ==
1274 12:15:22.775396
1275 12:15:22.775703
1276 12:15:22.777733 TX Vref Scan disable
1277 12:15:22.778151 == TX Byte 0 ==
1278 12:15:22.784725 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1279 12:15:22.788152 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1280 12:15:22.788681 == TX Byte 1 ==
1281 12:15:22.794805 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1282 12:15:22.798279 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1283 12:15:22.798803 ==
1284 12:15:22.801089 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 12:15:22.804394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 12:15:22.804815 ==
1287 12:15:22.818019 TX Vref=22, minBit 1, minWin=27, winSum=436
1288 12:15:22.821664 TX Vref=24, minBit 1, minWin=27, winSum=441
1289 12:15:22.825197 TX Vref=26, minBit 1, minWin=27, winSum=442
1290 12:15:22.827824 TX Vref=28, minBit 1, minWin=27, winSum=441
1291 12:15:22.831431 TX Vref=30, minBit 2, minWin=27, winSum=440
1292 12:15:22.834452 TX Vref=32, minBit 2, minWin=27, winSum=443
1293 12:15:22.841157 [TxChooseVref] Worse bit 2, Min win 27, Win sum 443, Final Vref 32
1294 12:15:22.841605
1295 12:15:22.844940 Final TX Range 1 Vref 32
1296 12:15:22.845358
1297 12:15:22.845850 ==
1298 12:15:22.847956 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 12:15:22.851291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 12:15:22.851705 ==
1301 12:15:22.852031
1302 12:15:22.852331
1303 12:15:22.854582 TX Vref Scan disable
1304 12:15:22.858113 == TX Byte 0 ==
1305 12:15:22.861238 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1306 12:15:22.864819 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1307 12:15:22.868243 == TX Byte 1 ==
1308 12:15:22.871379 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1309 12:15:22.874449 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1310 12:15:22.877983
1311 12:15:22.878393 [DATLAT]
1312 12:15:22.878716 Freq=800, CH0 RK1
1313 12:15:22.879020
1314 12:15:22.881358 DATLAT Default: 0xa
1315 12:15:22.881814 0, 0xFFFF, sum = 0
1316 12:15:22.884612 1, 0xFFFF, sum = 0
1317 12:15:22.885026 2, 0xFFFF, sum = 0
1318 12:15:22.888200 3, 0xFFFF, sum = 0
1319 12:15:22.888724 4, 0xFFFF, sum = 0
1320 12:15:22.891324 5, 0xFFFF, sum = 0
1321 12:15:22.891739 6, 0xFFFF, sum = 0
1322 12:15:22.894614 7, 0xFFFF, sum = 0
1323 12:15:22.897844 8, 0xFFFF, sum = 0
1324 12:15:22.898259 9, 0x0, sum = 1
1325 12:15:22.898589 10, 0x0, sum = 2
1326 12:15:22.901547 11, 0x0, sum = 3
1327 12:15:22.902082 12, 0x0, sum = 4
1328 12:15:22.904417 best_step = 10
1329 12:15:22.904825
1330 12:15:22.905145 ==
1331 12:15:22.908032 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 12:15:22.911404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 12:15:22.911946 ==
1334 12:15:22.914891 RX Vref Scan: 0
1335 12:15:22.915407
1336 12:15:22.915751 RX Vref 0 -> 0, step: 1
1337 12:15:22.916092
1338 12:15:22.917761 RX Delay -111 -> 252, step: 8
1339 12:15:22.924803 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1340 12:15:22.928011 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1341 12:15:22.931713 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1342 12:15:22.934815 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1343 12:15:22.938171 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1344 12:15:22.945033 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1345 12:15:22.948140 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1346 12:15:22.951232 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1347 12:15:22.955077 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1348 12:15:22.958081 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1349 12:15:22.964868 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1350 12:15:22.968264 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1351 12:15:22.971352 iDelay=209, Bit 12, Center 76 (-39 ~ 192) 232
1352 12:15:22.974627 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1353 12:15:22.978459 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1354 12:15:22.985085 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1355 12:15:22.985644 ==
1356 12:15:22.988570 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 12:15:22.991283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 12:15:22.991695 ==
1359 12:15:22.992019 DQS Delay:
1360 12:15:22.995092 DQS0 = 0, DQS1 = 0
1361 12:15:22.995605 DQM Delay:
1362 12:15:22.998046 DQM0 = 79, DQM1 = 70
1363 12:15:22.998456 DQ Delay:
1364 12:15:23.001724 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1365 12:15:23.004937 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =88
1366 12:15:23.008226 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1367 12:15:23.011847 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1368 12:15:23.012361
1369 12:15:23.012686
1370 12:15:23.018323 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1371 12:15:23.021536 CH0 RK1: MR19=606, MR18=4B26
1372 12:15:23.028140 CH0_RK1: MR19=0x606, MR18=0x4B26, DQSOSC=391, MR23=63, INC=96, DEC=64
1373 12:15:23.031674 [RxdqsGatingPostProcess] freq 800
1374 12:15:23.038113 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 12:15:23.041599 Pre-setting of DQS Precalculation
1376 12:15:23.045022 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 12:15:23.045580 ==
1378 12:15:23.048066 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 12:15:23.051636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 12:15:23.052151 ==
1381 12:15:23.058025 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 12:15:23.064764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 12:15:23.072867 [CA 0] Center 36 (6~66) winsize 61
1384 12:15:23.076438 [CA 1] Center 36 (6~67) winsize 62
1385 12:15:23.079751 [CA 2] Center 34 (5~64) winsize 60
1386 12:15:23.082928 [CA 3] Center 34 (4~64) winsize 61
1387 12:15:23.086488 [CA 4] Center 34 (4~65) winsize 62
1388 12:15:23.090032 [CA 5] Center 34 (4~64) winsize 61
1389 12:15:23.090548
1390 12:15:23.093500 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 12:15:23.094016
1392 12:15:23.096481 [CATrainingPosCal] consider 1 rank data
1393 12:15:23.099671 u2DelayCellTimex100 = 270/100 ps
1394 12:15:23.103017 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1395 12:15:23.106388 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 12:15:23.112954 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1397 12:15:23.116549 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1398 12:15:23.119830 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 12:15:23.122722 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 12:15:23.123135
1401 12:15:23.126473 CA PerBit enable=1, Macro0, CA PI delay=34
1402 12:15:23.126988
1403 12:15:23.129759 [CBTSetCACLKResult] CA Dly = 34
1404 12:15:23.130286 CS Dly: 5 (0~36)
1405 12:15:23.130618 ==
1406 12:15:23.133130 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 12:15:23.139578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 12:15:23.140016 ==
1409 12:15:23.142815 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 12:15:23.149386 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 12:15:23.159130 [CA 0] Center 37 (7~67) winsize 61
1412 12:15:23.162552 [CA 1] Center 37 (6~68) winsize 63
1413 12:15:23.166137 [CA 2] Center 34 (4~65) winsize 62
1414 12:15:23.169659 [CA 3] Center 34 (4~64) winsize 61
1415 12:15:23.173312 [CA 4] Center 34 (4~65) winsize 62
1416 12:15:23.177134 [CA 5] Center 34 (4~64) winsize 61
1417 12:15:23.177841
1418 12:15:23.180598 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1419 12:15:23.181012
1420 12:15:23.184602 [CATrainingPosCal] consider 2 rank data
1421 12:15:23.188111 u2DelayCellTimex100 = 270/100 ps
1422 12:15:23.191513 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1423 12:15:23.195456 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 12:15:23.198948 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1425 12:15:23.202719 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1426 12:15:23.205781 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 12:15:23.209221 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 12:15:23.209661
1429 12:15:23.212949 CA PerBit enable=1, Macro0, CA PI delay=34
1430 12:15:23.213461
1431 12:15:23.216197 [CBTSetCACLKResult] CA Dly = 34
1432 12:15:23.216701 CS Dly: 6 (0~38)
1433 12:15:23.217033
1434 12:15:23.219710 ----->DramcWriteLeveling(PI) begin...
1435 12:15:23.220230 ==
1436 12:15:23.222587 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 12:15:23.229451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 12:15:23.230002 ==
1439 12:15:23.232914 Write leveling (Byte 0): 27 => 27
1440 12:15:23.235843 Write leveling (Byte 1): 29 => 29
1441 12:15:23.236256 DramcWriteLeveling(PI) end<-----
1442 12:15:23.236580
1443 12:15:23.239325 ==
1444 12:15:23.242529 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 12:15:23.246343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 12:15:23.246875 ==
1447 12:15:23.249344 [Gating] SW mode calibration
1448 12:15:23.256165 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 12:15:23.259596 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 12:15:23.266458 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 12:15:23.269576 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 12:15:23.272906 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1453 12:15:23.279901 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:15:23.283140 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:15:23.286096 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:15:23.292882 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:15:23.296383 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:15:23.299601 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:15:23.302784 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:15:23.309652 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:15:23.312884 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:15:23.316301 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:15:23.323076 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:15:23.326265 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:15:23.329888 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:15:23.336253 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:15:23.339971 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:15:23.342623 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1469 12:15:23.349577 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:15:23.353067 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:15:23.356404 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:15:23.362628 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:15:23.365981 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:15:23.369532 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:15:23.376076 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1476 12:15:23.379611 0 9 8 | B1->B0 | 2929 2c2c | 0 0 | (0 0) (0 0)
1477 12:15:23.383028 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 12:15:23.389834 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 12:15:23.393016 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 12:15:23.396454 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 12:15:23.399967 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:15:23.406070 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 12:15:23.409269 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
1484 12:15:23.412899 0 10 8 | B1->B0 | 3030 2f2f | 0 0 | (1 1) (1 1)
1485 12:15:23.419725 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:15:23.423071 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:15:23.426472 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:15:23.432992 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:15:23.436040 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:15:23.439260 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:15:23.445962 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1492 12:15:23.449029 0 11 8 | B1->B0 | 3434 3535 | 0 0 | (1 1) (1 1)
1493 12:15:23.452656 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 12:15:23.459445 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 12:15:23.462331 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 12:15:23.465849 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:15:23.472714 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:15:23.475661 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 12:15:23.479195 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 12:15:23.485881 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1501 12:15:23.489290 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:15:23.492552 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:15:23.499346 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:15:23.502935 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:15:23.505723 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:15:23.509395 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:15:23.516110 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:15:23.519558 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:15:23.522692 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:15:23.529186 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:15:23.532554 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:15:23.535691 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:15:23.542625 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:15:23.545915 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:15:23.548862 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1516 12:15:23.555891 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1517 12:15:23.559210 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 12:15:23.562634 Total UI for P1: 0, mck2ui 16
1519 12:15:23.565517 best dqsien dly found for B0: ( 0, 14, 6)
1520 12:15:23.568745 Total UI for P1: 0, mck2ui 16
1521 12:15:23.572373 best dqsien dly found for B1: ( 0, 14, 6)
1522 12:15:23.575477 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1523 12:15:23.578956 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1524 12:15:23.579473
1525 12:15:23.581961 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1526 12:15:23.585646 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1527 12:15:23.589569 [Gating] SW calibration Done
1528 12:15:23.590082 ==
1529 12:15:23.592485 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 12:15:23.595798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 12:15:23.598641 ==
1532 12:15:23.599149 RX Vref Scan: 0
1533 12:15:23.599474
1534 12:15:23.602164 RX Vref 0 -> 0, step: 1
1535 12:15:23.602578
1536 12:15:23.605259 RX Delay -130 -> 252, step: 16
1537 12:15:23.608975 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1538 12:15:23.611881 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1539 12:15:23.615122 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1540 12:15:23.618438 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1541 12:15:23.625228 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1542 12:15:23.628568 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1543 12:15:23.632018 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1544 12:15:23.635289 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1545 12:15:23.638408 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1546 12:15:23.645142 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1547 12:15:23.648242 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1548 12:15:23.651774 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1549 12:15:23.654922 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1550 12:15:23.658678 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1551 12:15:23.665001 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1552 12:15:23.668753 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1553 12:15:23.669280 ==
1554 12:15:23.671859 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 12:15:23.675176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 12:15:23.675597 ==
1557 12:15:23.678376 DQS Delay:
1558 12:15:23.678813 DQS0 = 0, DQS1 = 0
1559 12:15:23.679148 DQM Delay:
1560 12:15:23.681855 DQM0 = 81, DQM1 = 70
1561 12:15:23.682278 DQ Delay:
1562 12:15:23.685431 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1563 12:15:23.688508 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1564 12:15:23.691872 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1565 12:15:23.695658 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1566 12:15:23.696183
1567 12:15:23.696515
1568 12:15:23.696821 ==
1569 12:15:23.698859 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 12:15:23.705384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 12:15:23.705831 ==
1572 12:15:23.706177
1573 12:15:23.706488
1574 12:15:23.706783 TX Vref Scan disable
1575 12:15:23.708574 == TX Byte 0 ==
1576 12:15:23.711873 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1577 12:15:23.715649 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1578 12:15:23.718961 == TX Byte 1 ==
1579 12:15:23.722354 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1580 12:15:23.725243 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1581 12:15:23.728649 ==
1582 12:15:23.732046 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 12:15:23.735423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 12:15:23.735951 ==
1585 12:15:23.748281 TX Vref=22, minBit 1, minWin=26, winSum=439
1586 12:15:23.751436 TX Vref=24, minBit 1, minWin=27, winSum=440
1587 12:15:23.755229 TX Vref=26, minBit 1, minWin=27, winSum=443
1588 12:15:23.758177 TX Vref=28, minBit 1, minWin=27, winSum=448
1589 12:15:23.761843 TX Vref=30, minBit 5, minWin=27, winSum=449
1590 12:15:23.764879 TX Vref=32, minBit 4, minWin=27, winSum=446
1591 12:15:23.771418 [TxChooseVref] Worse bit 5, Min win 27, Win sum 449, Final Vref 30
1592 12:15:23.771937
1593 12:15:23.774546 Final TX Range 1 Vref 30
1594 12:15:23.774963
1595 12:15:23.775294 ==
1596 12:15:23.778100 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 12:15:23.781813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 12:15:23.782342 ==
1599 12:15:23.782674
1600 12:15:23.782981
1601 12:15:23.784865 TX Vref Scan disable
1602 12:15:23.788285 == TX Byte 0 ==
1603 12:15:23.791590 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1604 12:15:23.794908 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1605 12:15:23.798445 == TX Byte 1 ==
1606 12:15:23.801777 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1607 12:15:23.804838 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1608 12:15:23.805426
1609 12:15:23.808404 [DATLAT]
1610 12:15:23.808920 Freq=800, CH1 RK0
1611 12:15:23.809255
1612 12:15:23.811504 DATLAT Default: 0xa
1613 12:15:23.811953 0, 0xFFFF, sum = 0
1614 12:15:23.814613 1, 0xFFFF, sum = 0
1615 12:15:23.815037 2, 0xFFFF, sum = 0
1616 12:15:23.818257 3, 0xFFFF, sum = 0
1617 12:15:23.818785 4, 0xFFFF, sum = 0
1618 12:15:23.821711 5, 0xFFFF, sum = 0
1619 12:15:23.822233 6, 0xFFFF, sum = 0
1620 12:15:23.825096 7, 0xFFFF, sum = 0
1621 12:15:23.825668 8, 0xFFFF, sum = 0
1622 12:15:23.828487 9, 0x0, sum = 1
1623 12:15:23.829023 10, 0x0, sum = 2
1624 12:15:23.831837 11, 0x0, sum = 3
1625 12:15:23.832435 12, 0x0, sum = 4
1626 12:15:23.834737 best_step = 10
1627 12:15:23.835152
1628 12:15:23.835481 ==
1629 12:15:23.838086 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 12:15:23.841467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 12:15:23.842033 ==
1632 12:15:23.844589 RX Vref Scan: 1
1633 12:15:23.845006
1634 12:15:23.845334 Set Vref Range= 32 -> 127
1635 12:15:23.845674
1636 12:15:23.848237 RX Vref 32 -> 127, step: 1
1637 12:15:23.848762
1638 12:15:23.851587 RX Delay -111 -> 252, step: 8
1639 12:15:23.852114
1640 12:15:23.854674 Set Vref, RX VrefLevel [Byte0]: 32
1641 12:15:23.858040 [Byte1]: 32
1642 12:15:23.858568
1643 12:15:23.861601 Set Vref, RX VrefLevel [Byte0]: 33
1644 12:15:23.864470 [Byte1]: 33
1645 12:15:23.868168
1646 12:15:23.868689 Set Vref, RX VrefLevel [Byte0]: 34
1647 12:15:23.871672 [Byte1]: 34
1648 12:15:23.875736
1649 12:15:23.876256 Set Vref, RX VrefLevel [Byte0]: 35
1650 12:15:23.879197 [Byte1]: 35
1651 12:15:23.883590
1652 12:15:23.884112 Set Vref, RX VrefLevel [Byte0]: 36
1653 12:15:23.886588 [Byte1]: 36
1654 12:15:23.890841
1655 12:15:23.891253 Set Vref, RX VrefLevel [Byte0]: 37
1656 12:15:23.894195 [Byte1]: 37
1657 12:15:23.898955
1658 12:15:23.899470 Set Vref, RX VrefLevel [Byte0]: 38
1659 12:15:23.902168 [Byte1]: 38
1660 12:15:23.906310
1661 12:15:23.906844 Set Vref, RX VrefLevel [Byte0]: 39
1662 12:15:23.909704 [Byte1]: 39
1663 12:15:23.913806
1664 12:15:23.914220 Set Vref, RX VrefLevel [Byte0]: 40
1665 12:15:23.917459 [Byte1]: 40
1666 12:15:23.921918
1667 12:15:23.922459 Set Vref, RX VrefLevel [Byte0]: 41
1668 12:15:23.925041 [Byte1]: 41
1669 12:15:23.929182
1670 12:15:23.929741 Set Vref, RX VrefLevel [Byte0]: 42
1671 12:15:23.932329 [Byte1]: 42
1672 12:15:23.936860
1673 12:15:23.937381 Set Vref, RX VrefLevel [Byte0]: 43
1674 12:15:23.940035 [Byte1]: 43
1675 12:15:23.944528
1676 12:15:23.944959 Set Vref, RX VrefLevel [Byte0]: 44
1677 12:15:23.948111 [Byte1]: 44
1678 12:15:23.952004
1679 12:15:23.952443 Set Vref, RX VrefLevel [Byte0]: 45
1680 12:15:23.955822 [Byte1]: 45
1681 12:15:23.960045
1682 12:15:23.960568 Set Vref, RX VrefLevel [Byte0]: 46
1683 12:15:23.963150 [Byte1]: 46
1684 12:15:23.967606
1685 12:15:23.968115 Set Vref, RX VrefLevel [Byte0]: 47
1686 12:15:23.970842 [Byte1]: 47
1687 12:15:23.974991
1688 12:15:23.975496 Set Vref, RX VrefLevel [Byte0]: 48
1689 12:15:23.978447 [Byte1]: 48
1690 12:15:23.983114
1691 12:15:23.983623 Set Vref, RX VrefLevel [Byte0]: 49
1692 12:15:23.985982 [Byte1]: 49
1693 12:15:23.990848
1694 12:15:23.991356 Set Vref, RX VrefLevel [Byte0]: 50
1695 12:15:23.994032 [Byte1]: 50
1696 12:15:23.998006
1697 12:15:24.001311 Set Vref, RX VrefLevel [Byte0]: 51
1698 12:15:24.001833 [Byte1]: 51
1699 12:15:24.006319
1700 12:15:24.006728 Set Vref, RX VrefLevel [Byte0]: 52
1701 12:15:24.009138 [Byte1]: 52
1702 12:15:24.013163
1703 12:15:24.013821 Set Vref, RX VrefLevel [Byte0]: 53
1704 12:15:24.016305 [Byte1]: 53
1705 12:15:24.021382
1706 12:15:24.021922 Set Vref, RX VrefLevel [Byte0]: 54
1707 12:15:24.024549 [Byte1]: 54
1708 12:15:24.028671
1709 12:15:24.029189 Set Vref, RX VrefLevel [Byte0]: 55
1710 12:15:24.032194 [Byte1]: 55
1711 12:15:24.036900
1712 12:15:24.037515 Set Vref, RX VrefLevel [Byte0]: 56
1713 12:15:24.039557 [Byte1]: 56
1714 12:15:24.043883
1715 12:15:24.044298 Set Vref, RX VrefLevel [Byte0]: 57
1716 12:15:24.047244 [Byte1]: 57
1717 12:15:24.051610
1718 12:15:24.052125 Set Vref, RX VrefLevel [Byte0]: 58
1719 12:15:24.054820 [Byte1]: 58
1720 12:15:24.059367
1721 12:15:24.059878 Set Vref, RX VrefLevel [Byte0]: 59
1722 12:15:24.062776 [Byte1]: 59
1723 12:15:24.066772
1724 12:15:24.067189 Set Vref, RX VrefLevel [Byte0]: 60
1725 12:15:24.070044 [Byte1]: 60
1726 12:15:24.074803
1727 12:15:24.075312 Set Vref, RX VrefLevel [Byte0]: 61
1728 12:15:24.077946 [Byte1]: 61
1729 12:15:24.082432
1730 12:15:24.082941 Set Vref, RX VrefLevel [Byte0]: 62
1731 12:15:24.085408 [Byte1]: 62
1732 12:15:24.090018
1733 12:15:24.090525 Set Vref, RX VrefLevel [Byte0]: 63
1734 12:15:24.093400 [Byte1]: 63
1735 12:15:24.097626
1736 12:15:24.098190 Set Vref, RX VrefLevel [Byte0]: 64
1737 12:15:24.100653 [Byte1]: 64
1738 12:15:24.105212
1739 12:15:24.105773 Set Vref, RX VrefLevel [Byte0]: 65
1740 12:15:24.108541 [Byte1]: 65
1741 12:15:24.112842
1742 12:15:24.113289 Set Vref, RX VrefLevel [Byte0]: 66
1743 12:15:24.116032 [Byte1]: 66
1744 12:15:24.120641
1745 12:15:24.121159 Set Vref, RX VrefLevel [Byte0]: 67
1746 12:15:24.123506 [Byte1]: 67
1747 12:15:24.128133
1748 12:15:24.128658 Set Vref, RX VrefLevel [Byte0]: 68
1749 12:15:24.131353 [Byte1]: 68
1750 12:15:24.135630
1751 12:15:24.136150 Set Vref, RX VrefLevel [Byte0]: 69
1752 12:15:24.138918 [Byte1]: 69
1753 12:15:24.143271
1754 12:15:24.143690 Set Vref, RX VrefLevel [Byte0]: 70
1755 12:15:24.146605 [Byte1]: 70
1756 12:15:24.151684
1757 12:15:24.152207 Set Vref, RX VrefLevel [Byte0]: 71
1758 12:15:24.154173 [Byte1]: 71
1759 12:15:24.158630
1760 12:15:24.159153 Set Vref, RX VrefLevel [Byte0]: 72
1761 12:15:24.161626 [Byte1]: 72
1762 12:15:24.166191
1763 12:15:24.166609 Set Vref, RX VrefLevel [Byte0]: 73
1764 12:15:24.169679 [Byte1]: 73
1765 12:15:24.174132
1766 12:15:24.174653 Set Vref, RX VrefLevel [Byte0]: 74
1767 12:15:24.177187 [Byte1]: 74
1768 12:15:24.182010
1769 12:15:24.182530 Set Vref, RX VrefLevel [Byte0]: 75
1770 12:15:24.184746 [Byte1]: 75
1771 12:15:24.189448
1772 12:15:24.190017 Final RX Vref Byte 0 = 61 to rank0
1773 12:15:24.193053 Final RX Vref Byte 1 = 57 to rank0
1774 12:15:24.196222 Final RX Vref Byte 0 = 61 to rank1
1775 12:15:24.199742 Final RX Vref Byte 1 = 57 to rank1==
1776 12:15:24.202980 Dram Type= 6, Freq= 0, CH_1, rank 0
1777 12:15:24.206004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1778 12:15:24.209619 ==
1779 12:15:24.210145 DQS Delay:
1780 12:15:24.210480 DQS0 = 0, DQS1 = 0
1781 12:15:24.212724 DQM Delay:
1782 12:15:24.213257 DQM0 = 81, DQM1 = 71
1783 12:15:24.215989 DQ Delay:
1784 12:15:24.219187 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1785 12:15:24.219605 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1786 12:15:24.222502 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1787 12:15:24.226007 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1788 12:15:24.229257
1789 12:15:24.229707
1790 12:15:24.235947 [DQSOSCAuto] RK0, (LSB)MR18= 0x151f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
1791 12:15:24.239504 CH1 RK0: MR19=606, MR18=151F
1792 12:15:24.246014 CH1_RK0: MR19=0x606, MR18=0x151F, DQSOSC=402, MR23=63, INC=91, DEC=60
1793 12:15:24.246506
1794 12:15:24.249244 ----->DramcWriteLeveling(PI) begin...
1795 12:15:24.249704 ==
1796 12:15:24.252297 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 12:15:24.255670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 12:15:24.256091 ==
1799 12:15:24.259188 Write leveling (Byte 0): 27 => 27
1800 12:15:24.262260 Write leveling (Byte 1): 28 => 28
1801 12:15:24.265773 DramcWriteLeveling(PI) end<-----
1802 12:15:24.266309
1803 12:15:24.266645 ==
1804 12:15:24.269154 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 12:15:24.272815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 12:15:24.273329 ==
1807 12:15:24.275749 [Gating] SW mode calibration
1808 12:15:24.282591 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1809 12:15:24.289168 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1810 12:15:24.292893 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1811 12:15:24.296128 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1812 12:15:24.302797 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1813 12:15:24.306199 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1814 12:15:24.309237 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:15:24.316244 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:15:24.319585 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:15:24.322874 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:15:24.329337 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:15:24.332587 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:15:24.335684 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:15:24.342588 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:15:24.346179 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:15:24.349602 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:15:24.352693 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:15:24.359377 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:15:24.362386 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1827 12:15:24.365677 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1828 12:15:24.372624 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:15:24.375998 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:15:24.378964 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:15:24.385958 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:15:24.389029 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:15:24.392515 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:15:24.399014 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:15:24.403029 0 9 4 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
1836 12:15:24.405690 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1837 12:15:24.412331 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 12:15:24.416063 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 12:15:24.419544 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 12:15:24.426327 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 12:15:24.429750 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 12:15:24.432726 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1843 12:15:24.435698 0 10 4 | B1->B0 | 3232 2828 | 1 1 | (1 0) (1 0)
1844 12:15:24.442839 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1845 12:15:24.445852 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:15:24.449535 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 12:15:24.456201 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 12:15:24.459576 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 12:15:24.462809 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 12:15:24.469081 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1851 12:15:24.472769 0 11 4 | B1->B0 | 2525 3737 | 0 0 | (0 0) (1 1)
1852 12:15:24.476191 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1853 12:15:24.482631 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 12:15:24.486073 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 12:15:24.489550 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 12:15:24.496143 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 12:15:24.499074 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 12:15:24.502288 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 12:15:24.509009 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1860 12:15:24.512451 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:15:24.516125 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:15:24.522814 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:15:24.526429 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:15:24.529346 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:15:24.536367 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:15:24.538972 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:15:24.542882 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:15:24.545798 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:15:24.552720 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:15:24.555612 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:15:24.559448 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 12:15:24.566134 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 12:15:24.569191 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:15:24.572714 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:15:24.579541 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1876 12:15:24.582452 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 12:15:24.586089 Total UI for P1: 0, mck2ui 16
1878 12:15:24.589351 best dqsien dly found for B0: ( 0, 14, 4)
1879 12:15:24.592721 Total UI for P1: 0, mck2ui 16
1880 12:15:24.595945 best dqsien dly found for B1: ( 0, 14, 4)
1881 12:15:24.599221 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1882 12:15:24.602515 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1883 12:15:24.603061
1884 12:15:24.605819 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1885 12:15:24.609018 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1886 12:15:24.612710 [Gating] SW calibration Done
1887 12:15:24.613245 ==
1888 12:15:24.616020 Dram Type= 6, Freq= 0, CH_1, rank 1
1889 12:15:24.619036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1890 12:15:24.622446 ==
1891 12:15:24.622949 RX Vref Scan: 0
1892 12:15:24.623283
1893 12:15:24.625518 RX Vref 0 -> 0, step: 1
1894 12:15:24.625940
1895 12:15:24.629017 RX Delay -130 -> 252, step: 16
1896 12:15:24.632394 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1897 12:15:24.635790 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1898 12:15:24.638951 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1899 12:15:24.642235 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1900 12:15:24.648923 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1901 12:15:24.652383 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1902 12:15:24.655901 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1903 12:15:24.659168 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1904 12:15:24.662307 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1905 12:15:24.668764 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1906 12:15:24.672379 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1907 12:15:24.675922 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1908 12:15:24.679265 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1909 12:15:24.682124 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1910 12:15:24.689067 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1911 12:15:24.692472 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1912 12:15:24.692975 ==
1913 12:15:24.695531 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 12:15:24.699164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 12:15:24.699676 ==
1916 12:15:24.700011 DQS Delay:
1917 12:15:24.702399 DQS0 = 0, DQS1 = 0
1918 12:15:24.702902 DQM Delay:
1919 12:15:24.706010 DQM0 = 77, DQM1 = 71
1920 12:15:24.706520 DQ Delay:
1921 12:15:24.708971 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1922 12:15:24.712035 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1923 12:15:24.715447 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1924 12:15:24.719182 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1925 12:15:24.719703
1926 12:15:24.720032
1927 12:15:24.720336 ==
1928 12:15:24.722291 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 12:15:24.725575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 12:15:24.728995 ==
1931 12:15:24.729407
1932 12:15:24.729763
1933 12:15:24.730068 TX Vref Scan disable
1934 12:15:24.732227 == TX Byte 0 ==
1935 12:15:24.735448 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1936 12:15:24.738867 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1937 12:15:24.741977 == TX Byte 1 ==
1938 12:15:24.745344 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1939 12:15:24.748898 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1940 12:15:24.749316 ==
1941 12:15:24.752240 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 12:15:24.758814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 12:15:24.759232 ==
1944 12:15:24.770726 TX Vref=22, minBit 6, minWin=27, winSum=450
1945 12:15:24.774230 TX Vref=24, minBit 6, minWin=27, winSum=454
1946 12:15:24.777457 TX Vref=26, minBit 1, minWin=28, winSum=456
1947 12:15:24.781291 TX Vref=28, minBit 1, minWin=27, winSum=457
1948 12:15:24.784438 TX Vref=30, minBit 0, minWin=28, winSum=459
1949 12:15:24.790408 TX Vref=32, minBit 0, minWin=28, winSum=458
1950 12:15:24.794041 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
1951 12:15:24.794589
1952 12:15:24.797584 Final TX Range 1 Vref 30
1953 12:15:24.798129
1954 12:15:24.798574 ==
1955 12:15:24.800915 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 12:15:24.804336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 12:15:24.807037 ==
1958 12:15:24.807473
1959 12:15:24.807911
1960 12:15:24.808328 TX Vref Scan disable
1961 12:15:24.810860 == TX Byte 0 ==
1962 12:15:24.814414 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1963 12:15:24.817639 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1964 12:15:24.820917 == TX Byte 1 ==
1965 12:15:24.824096 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1966 12:15:24.827336 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1967 12:15:24.830714
1968 12:15:24.831144 [DATLAT]
1969 12:15:24.831583 Freq=800, CH1 RK1
1970 12:15:24.831998
1971 12:15:24.833950 DATLAT Default: 0xa
1972 12:15:24.834380 0, 0xFFFF, sum = 0
1973 12:15:24.837576 1, 0xFFFF, sum = 0
1974 12:15:24.838117 2, 0xFFFF, sum = 0
1975 12:15:24.840968 3, 0xFFFF, sum = 0
1976 12:15:24.841408 4, 0xFFFF, sum = 0
1977 12:15:24.844235 5, 0xFFFF, sum = 0
1978 12:15:24.847227 6, 0xFFFF, sum = 0
1979 12:15:24.847672 7, 0xFFFF, sum = 0
1980 12:15:24.850599 8, 0xFFFF, sum = 0
1981 12:15:24.851035 9, 0x0, sum = 1
1982 12:15:24.851477 10, 0x0, sum = 2
1983 12:15:24.854186 11, 0x0, sum = 3
1984 12:15:24.854732 12, 0x0, sum = 4
1985 12:15:24.857467 best_step = 10
1986 12:15:24.858041
1987 12:15:24.858485 ==
1988 12:15:24.860709 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 12:15:24.864006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 12:15:24.864545 ==
1991 12:15:24.867748 RX Vref Scan: 0
1992 12:15:24.868282
1993 12:15:24.868727 RX Vref 0 -> 0, step: 1
1994 12:15:24.869146
1995 12:15:24.870733 RX Delay -111 -> 252, step: 8
1996 12:15:24.877591 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
1997 12:15:24.880992 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1998 12:15:24.884180 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
1999 12:15:24.888013 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2000 12:15:24.891064 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2001 12:15:24.897650 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2002 12:15:24.900990 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2003 12:15:24.904438 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2004 12:15:24.907422 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2005 12:15:24.911064 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2006 12:15:24.917785 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2007 12:15:24.921086 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2008 12:15:24.924281 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2009 12:15:24.927524 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2010 12:15:24.934279 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2011 12:15:24.937416 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2012 12:15:24.937968 ==
2013 12:15:24.940780 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 12:15:24.944212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 12:15:24.944724 ==
2016 12:15:24.945053 DQS Delay:
2017 12:15:24.947277 DQS0 = 0, DQS1 = 0
2018 12:15:24.947691 DQM Delay:
2019 12:15:24.950675 DQM0 = 78, DQM1 = 73
2020 12:15:24.951149 DQ Delay:
2021 12:15:24.954144 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2022 12:15:24.957852 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2023 12:15:24.960557 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2024 12:15:24.963857 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2025 12:15:24.964268
2026 12:15:24.964591
2027 12:15:24.974193 [DQSOSCAuto] RK1, (LSB)MR18= 0x223b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2028 12:15:24.974612 CH1 RK1: MR19=606, MR18=223B
2029 12:15:24.980610 CH1_RK1: MR19=0x606, MR18=0x223B, DQSOSC=394, MR23=63, INC=95, DEC=63
2030 12:15:24.984379 [RxdqsGatingPostProcess] freq 800
2031 12:15:24.990860 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2032 12:15:24.993876 Pre-setting of DQS Precalculation
2033 12:15:24.997307 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2034 12:15:25.004139 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2035 12:15:25.010526 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2036 12:15:25.010941
2037 12:15:25.013941
2038 12:15:25.014350 [Calibration Summary] 1600 Mbps
2039 12:15:25.017574 CH 0, Rank 0
2040 12:15:25.018088 SW Impedance : PASS
2041 12:15:25.021111 DUTY Scan : NO K
2042 12:15:25.024538 ZQ Calibration : PASS
2043 12:15:25.025054 Jitter Meter : NO K
2044 12:15:25.027578 CBT Training : PASS
2045 12:15:25.030827 Write leveling : PASS
2046 12:15:25.031237 RX DQS gating : PASS
2047 12:15:25.034051 RX DQ/DQS(RDDQC) : PASS
2048 12:15:25.037671 TX DQ/DQS : PASS
2049 12:15:25.038198 RX DATLAT : PASS
2050 12:15:25.040659 RX DQ/DQS(Engine): PASS
2051 12:15:25.041078 TX OE : NO K
2052 12:15:25.043738 All Pass.
2053 12:15:25.044156
2054 12:15:25.044482 CH 0, Rank 1
2055 12:15:25.047422 SW Impedance : PASS
2056 12:15:25.047837 DUTY Scan : NO K
2057 12:15:25.050714 ZQ Calibration : PASS
2058 12:15:25.054110 Jitter Meter : NO K
2059 12:15:25.054528 CBT Training : PASS
2060 12:15:25.057855 Write leveling : PASS
2061 12:15:25.060905 RX DQS gating : PASS
2062 12:15:25.061426 RX DQ/DQS(RDDQC) : PASS
2063 12:15:25.064611 TX DQ/DQS : PASS
2064 12:15:25.067647 RX DATLAT : PASS
2065 12:15:25.068063 RX DQ/DQS(Engine): PASS
2066 12:15:25.070973 TX OE : NO K
2067 12:15:25.071395 All Pass.
2068 12:15:25.071720
2069 12:15:25.074622 CH 1, Rank 0
2070 12:15:25.075133 SW Impedance : PASS
2071 12:15:25.077506 DUTY Scan : NO K
2072 12:15:25.081105 ZQ Calibration : PASS
2073 12:15:25.081663 Jitter Meter : NO K
2074 12:15:25.084369 CBT Training : PASS
2075 12:15:25.084880 Write leveling : PASS
2076 12:15:25.087776 RX DQS gating : PASS
2077 12:15:25.091251 RX DQ/DQS(RDDQC) : PASS
2078 12:15:25.091762 TX DQ/DQS : PASS
2079 12:15:25.094266 RX DATLAT : PASS
2080 12:15:25.097372 RX DQ/DQS(Engine): PASS
2081 12:15:25.097843 TX OE : NO K
2082 12:15:25.101049 All Pass.
2083 12:15:25.101560
2084 12:15:25.101910 CH 1, Rank 1
2085 12:15:25.104134 SW Impedance : PASS
2086 12:15:25.104639 DUTY Scan : NO K
2087 12:15:25.107537 ZQ Calibration : PASS
2088 12:15:25.110850 Jitter Meter : NO K
2089 12:15:25.111265 CBT Training : PASS
2090 12:15:25.114200 Write leveling : PASS
2091 12:15:25.117928 RX DQS gating : PASS
2092 12:15:25.118435 RX DQ/DQS(RDDQC) : PASS
2093 12:15:25.120830 TX DQ/DQS : PASS
2094 12:15:25.124287 RX DATLAT : PASS
2095 12:15:25.124804 RX DQ/DQS(Engine): PASS
2096 12:15:25.127551 TX OE : NO K
2097 12:15:25.128075 All Pass.
2098 12:15:25.128412
2099 12:15:25.130564 DramC Write-DBI off
2100 12:15:25.134004 PER_BANK_REFRESH: Hybrid Mode
2101 12:15:25.134509 TX_TRACKING: ON
2102 12:15:25.137697 [GetDramInforAfterCalByMRR] Vendor 6.
2103 12:15:25.141165 [GetDramInforAfterCalByMRR] Revision 606.
2104 12:15:25.144025 [GetDramInforAfterCalByMRR] Revision 2 0.
2105 12:15:25.147260 MR0 0x3b3b
2106 12:15:25.147668 MR8 0x5151
2107 12:15:25.150585 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 12:15:25.151101
2109 12:15:25.151523 MR0 0x3b3b
2110 12:15:25.153824 MR8 0x5151
2111 12:15:25.157575 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 12:15:25.158100
2113 12:15:25.164374 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2114 12:15:25.170795 [FAST_K] Save calibration result to emmc
2115 12:15:25.174116 [FAST_K] Save calibration result to emmc
2116 12:15:25.174544 dram_init: config_dvfs: 1
2117 12:15:25.177582 dramc_set_vcore_voltage set vcore to 662500
2118 12:15:25.180584 Read voltage for 1200, 2
2119 12:15:25.181006 Vio18 = 0
2120 12:15:25.183960 Vcore = 662500
2121 12:15:25.184373 Vdram = 0
2122 12:15:25.184700 Vddq = 0
2123 12:15:25.187670 Vmddr = 0
2124 12:15:25.191059 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2125 12:15:25.197572 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2126 12:15:25.198092 MEM_TYPE=3, freq_sel=15
2127 12:15:25.201244 sv_algorithm_assistance_LP4_1600
2128 12:15:25.207318 ============ PULL DRAM RESETB DOWN ============
2129 12:15:25.210537 ========== PULL DRAM RESETB DOWN end =========
2130 12:15:25.213779 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2131 12:15:25.217515 ===================================
2132 12:15:25.220555 LPDDR4 DRAM CONFIGURATION
2133 12:15:25.224183 ===================================
2134 12:15:25.227456 EX_ROW_EN[0] = 0x0
2135 12:15:25.227993 EX_ROW_EN[1] = 0x0
2136 12:15:25.230610 LP4Y_EN = 0x0
2137 12:15:25.231029 WORK_FSP = 0x0
2138 12:15:25.233913 WL = 0x4
2139 12:15:25.234328 RL = 0x4
2140 12:15:25.237437 BL = 0x2
2141 12:15:25.238001 RPST = 0x0
2142 12:15:25.240507 RD_PRE = 0x0
2143 12:15:25.240921 WR_PRE = 0x1
2144 12:15:25.243984 WR_PST = 0x0
2145 12:15:25.244401 DBI_WR = 0x0
2146 12:15:25.247363 DBI_RD = 0x0
2147 12:15:25.247778 OTF = 0x1
2148 12:15:25.250615 ===================================
2149 12:15:25.253997 ===================================
2150 12:15:25.257215 ANA top config
2151 12:15:25.260560 ===================================
2152 12:15:25.261080 DLL_ASYNC_EN = 0
2153 12:15:25.264140 ALL_SLAVE_EN = 0
2154 12:15:25.267230 NEW_RANK_MODE = 1
2155 12:15:25.270515 DLL_IDLE_MODE = 1
2156 12:15:25.273946 LP45_APHY_COMB_EN = 1
2157 12:15:25.274366 TX_ODT_DIS = 1
2158 12:15:25.277738 NEW_8X_MODE = 1
2159 12:15:25.280665 ===================================
2160 12:15:25.284118 ===================================
2161 12:15:25.287488 data_rate = 2400
2162 12:15:25.290967 CKR = 1
2163 12:15:25.293833 DQ_P2S_RATIO = 8
2164 12:15:25.297400 ===================================
2165 12:15:25.297965 CA_P2S_RATIO = 8
2166 12:15:25.300863 DQ_CA_OPEN = 0
2167 12:15:25.304229 DQ_SEMI_OPEN = 0
2168 12:15:25.307774 CA_SEMI_OPEN = 0
2169 12:15:25.310294 CA_FULL_RATE = 0
2170 12:15:25.313946 DQ_CKDIV4_EN = 0
2171 12:15:25.314468 CA_CKDIV4_EN = 0
2172 12:15:25.317344 CA_PREDIV_EN = 0
2173 12:15:25.320712 PH8_DLY = 17
2174 12:15:25.324271 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2175 12:15:25.327400 DQ_AAMCK_DIV = 4
2176 12:15:25.330320 CA_AAMCK_DIV = 4
2177 12:15:25.330739 CA_ADMCK_DIV = 4
2178 12:15:25.333753 DQ_TRACK_CA_EN = 0
2179 12:15:25.337206 CA_PICK = 1200
2180 12:15:25.340345 CA_MCKIO = 1200
2181 12:15:25.343781 MCKIO_SEMI = 0
2182 12:15:25.347029 PLL_FREQ = 2366
2183 12:15:25.350279 DQ_UI_PI_RATIO = 32
2184 12:15:25.350696 CA_UI_PI_RATIO = 0
2185 12:15:25.354250 ===================================
2186 12:15:25.357407 ===================================
2187 12:15:25.360756 memory_type:LPDDR4
2188 12:15:25.364393 GP_NUM : 10
2189 12:15:25.364913 SRAM_EN : 1
2190 12:15:25.367070 MD32_EN : 0
2191 12:15:25.370612 ===================================
2192 12:15:25.373882 [ANA_INIT] >>>>>>>>>>>>>>
2193 12:15:25.377362 <<<<<< [CONFIGURE PHASE]: ANA_TX
2194 12:15:25.380641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2195 12:15:25.383976 ===================================
2196 12:15:25.384393 data_rate = 2400,PCW = 0X5b00
2197 12:15:25.387336 ===================================
2198 12:15:25.390781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2199 12:15:25.397742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 12:15:25.404039 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 12:15:25.407432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2202 12:15:25.410486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2203 12:15:25.414185 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2204 12:15:25.417546 [ANA_INIT] flow start
2205 12:15:25.418067 [ANA_INIT] PLL >>>>>>>>
2206 12:15:25.420937 [ANA_INIT] PLL <<<<<<<<
2207 12:15:25.424310 [ANA_INIT] MIDPI >>>>>>>>
2208 12:15:25.427817 [ANA_INIT] MIDPI <<<<<<<<
2209 12:15:25.428336 [ANA_INIT] DLL >>>>>>>>
2210 12:15:25.430775 [ANA_INIT] DLL <<<<<<<<
2211 12:15:25.431299 [ANA_INIT] flow end
2212 12:15:25.437523 ============ LP4 DIFF to SE enter ============
2213 12:15:25.440850 ============ LP4 DIFF to SE exit ============
2214 12:15:25.444480 [ANA_INIT] <<<<<<<<<<<<<
2215 12:15:25.447530 [Flow] Enable top DCM control >>>>>
2216 12:15:25.450353 [Flow] Enable top DCM control <<<<<
2217 12:15:25.450774 Enable DLL master slave shuffle
2218 12:15:25.457632 ==============================================================
2219 12:15:25.460935 Gating Mode config
2220 12:15:25.463980 ==============================================================
2221 12:15:25.467480 Config description:
2222 12:15:25.477333 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2223 12:15:25.484049 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2224 12:15:25.487415 SELPH_MODE 0: By rank 1: By Phase
2225 12:15:25.493919 ==============================================================
2226 12:15:25.497465 GAT_TRACK_EN = 1
2227 12:15:25.500934 RX_GATING_MODE = 2
2228 12:15:25.504095 RX_GATING_TRACK_MODE = 2
2229 12:15:25.507164 SELPH_MODE = 1
2230 12:15:25.507585 PICG_EARLY_EN = 1
2231 12:15:25.510879 VALID_LAT_VALUE = 1
2232 12:15:25.517091 ==============================================================
2233 12:15:25.520785 Enter into Gating configuration >>>>
2234 12:15:25.524328 Exit from Gating configuration <<<<
2235 12:15:25.527468 Enter into DVFS_PRE_config >>>>>
2236 12:15:25.537362 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2237 12:15:25.540584 Exit from DVFS_PRE_config <<<<<
2238 12:15:25.543557 Enter into PICG configuration >>>>
2239 12:15:25.547217 Exit from PICG configuration <<<<
2240 12:15:25.550886 [RX_INPUT] configuration >>>>>
2241 12:15:25.553863 [RX_INPUT] configuration <<<<<
2242 12:15:25.557000 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2243 12:15:25.563876 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2244 12:15:25.570740 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2245 12:15:25.577089 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2246 12:15:25.580512 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 12:15:25.587567 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 12:15:25.590496 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2249 12:15:25.597250 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2250 12:15:25.600845 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2251 12:15:25.604077 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2252 12:15:25.607274 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2253 12:15:25.613787 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2254 12:15:25.617065 ===================================
2255 12:15:25.617644 LPDDR4 DRAM CONFIGURATION
2256 12:15:25.620938 ===================================
2257 12:15:25.623959 EX_ROW_EN[0] = 0x0
2258 12:15:25.626994 EX_ROW_EN[1] = 0x0
2259 12:15:25.627405 LP4Y_EN = 0x0
2260 12:15:25.630428 WORK_FSP = 0x0
2261 12:15:25.630939 WL = 0x4
2262 12:15:25.633895 RL = 0x4
2263 12:15:25.634307 BL = 0x2
2264 12:15:25.637531 RPST = 0x0
2265 12:15:25.638038 RD_PRE = 0x0
2266 12:15:25.640563 WR_PRE = 0x1
2267 12:15:25.640974 WR_PST = 0x0
2268 12:15:25.644049 DBI_WR = 0x0
2269 12:15:25.644554 DBI_RD = 0x0
2270 12:15:25.646871 OTF = 0x1
2271 12:15:25.650199 ===================================
2272 12:15:25.653511 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2273 12:15:25.657072 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2274 12:15:25.663947 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2275 12:15:25.667230 ===================================
2276 12:15:25.667744 LPDDR4 DRAM CONFIGURATION
2277 12:15:25.670413 ===================================
2278 12:15:25.673553 EX_ROW_EN[0] = 0x10
2279 12:15:25.676939 EX_ROW_EN[1] = 0x0
2280 12:15:25.677352 LP4Y_EN = 0x0
2281 12:15:25.680456 WORK_FSP = 0x0
2282 12:15:25.680966 WL = 0x4
2283 12:15:25.683863 RL = 0x4
2284 12:15:25.684378 BL = 0x2
2285 12:15:25.687132 RPST = 0x0
2286 12:15:25.687640 RD_PRE = 0x0
2287 12:15:25.690204 WR_PRE = 0x1
2288 12:15:25.690614 WR_PST = 0x0
2289 12:15:25.693872 DBI_WR = 0x0
2290 12:15:25.694381 DBI_RD = 0x0
2291 12:15:25.697228 OTF = 0x1
2292 12:15:25.700261 ===================================
2293 12:15:25.707052 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2294 12:15:25.707464 ==
2295 12:15:25.710365 Dram Type= 6, Freq= 0, CH_0, rank 0
2296 12:15:25.713754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2297 12:15:25.714168 ==
2298 12:15:25.716957 [Duty_Offset_Calibration]
2299 12:15:25.717364 B0:2 B1:0 CA:3
2300 12:15:25.717733
2301 12:15:25.720097 [DutyScan_Calibration_Flow] k_type=0
2302 12:15:25.730256
2303 12:15:25.730771 ==CLK 0==
2304 12:15:25.733450 Final CLK duty delay cell = 0
2305 12:15:25.736740 [0] MAX Duty = 5031%(X100), DQS PI = 12
2306 12:15:25.739872 [0] MIN Duty = 4906%(X100), DQS PI = 54
2307 12:15:25.743615 [0] AVG Duty = 4968%(X100)
2308 12:15:25.744132
2309 12:15:25.746880 CH0 CLK Duty spec in!! Max-Min= 125%
2310 12:15:25.750181 [DutyScan_Calibration_Flow] ====Done====
2311 12:15:25.750692
2312 12:15:25.753398 [DutyScan_Calibration_Flow] k_type=1
2313 12:15:25.769057
2314 12:15:25.769604 ==DQS 0 ==
2315 12:15:25.772375 Final DQS duty delay cell = 0
2316 12:15:25.775004 [0] MAX Duty = 5062%(X100), DQS PI = 18
2317 12:15:25.778636 [0] MIN Duty = 4907%(X100), DQS PI = 44
2318 12:15:25.781691 [0] AVG Duty = 4984%(X100)
2319 12:15:25.782099
2320 12:15:25.782419 ==DQS 1 ==
2321 12:15:25.785139 Final DQS duty delay cell = -4
2322 12:15:25.789002 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2323 12:15:25.792054 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2324 12:15:25.795115 [-4] AVG Duty = 4953%(X100)
2325 12:15:25.795523
2326 12:15:25.798671 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2327 12:15:25.799080
2328 12:15:25.801771 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2329 12:15:25.805253 [DutyScan_Calibration_Flow] ====Done====
2330 12:15:25.805721
2331 12:15:25.808645 [DutyScan_Calibration_Flow] k_type=3
2332 12:15:25.826328
2333 12:15:25.826738 ==DQM 0 ==
2334 12:15:25.829354 Final DQM duty delay cell = 0
2335 12:15:25.832873 [0] MAX Duty = 5124%(X100), DQS PI = 28
2336 12:15:25.836122 [0] MIN Duty = 4876%(X100), DQS PI = 0
2337 12:15:25.836633 [0] AVG Duty = 5000%(X100)
2338 12:15:25.839446
2339 12:15:25.839887 ==DQM 1 ==
2340 12:15:25.842740 Final DQM duty delay cell = 4
2341 12:15:25.846111 [4] MAX Duty = 5124%(X100), DQS PI = 50
2342 12:15:25.849462 [4] MIN Duty = 5000%(X100), DQS PI = 12
2343 12:15:25.849924 [4] AVG Duty = 5062%(X100)
2344 12:15:25.853227
2345 12:15:25.856281 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2346 12:15:25.856694
2347 12:15:25.859835 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2348 12:15:25.862738 [DutyScan_Calibration_Flow] ====Done====
2349 12:15:25.863149
2350 12:15:25.866027 [DutyScan_Calibration_Flow] k_type=2
2351 12:15:25.881082
2352 12:15:25.881609 ==DQ 0 ==
2353 12:15:25.884546 Final DQ duty delay cell = -4
2354 12:15:25.888010 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2355 12:15:25.890952 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2356 12:15:25.894471 [-4] AVG Duty = 4969%(X100)
2357 12:15:25.894979
2358 12:15:25.895307 ==DQ 1 ==
2359 12:15:25.897882 Final DQ duty delay cell = -4
2360 12:15:25.901245 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2361 12:15:25.904156 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2362 12:15:25.908077 [-4] AVG Duty = 4938%(X100)
2363 12:15:25.908585
2364 12:15:25.911303 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2365 12:15:25.911813
2366 12:15:25.914543 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2367 12:15:25.917783 [DutyScan_Calibration_Flow] ====Done====
2368 12:15:25.918195 ==
2369 12:15:25.921017 Dram Type= 6, Freq= 0, CH_1, rank 0
2370 12:15:25.924315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 12:15:25.924831 ==
2372 12:15:25.927793 [Duty_Offset_Calibration]
2373 12:15:25.928301 B0:1 B1:-2 CA:0
2374 12:15:25.928630
2375 12:15:25.930836 [DutyScan_Calibration_Flow] k_type=0
2376 12:15:25.942020
2377 12:15:25.942523 ==CLK 0==
2378 12:15:25.945155 Final CLK duty delay cell = 0
2379 12:15:25.948282 [0] MAX Duty = 5031%(X100), DQS PI = 16
2380 12:15:25.951586 [0] MIN Duty = 4844%(X100), DQS PI = 58
2381 12:15:25.952001 [0] AVG Duty = 4937%(X100)
2382 12:15:25.954871
2383 12:15:25.958573 CH1 CLK Duty spec in!! Max-Min= 187%
2384 12:15:25.961522 [DutyScan_Calibration_Flow] ====Done====
2385 12:15:25.962052
2386 12:15:25.964595 [DutyScan_Calibration_Flow] k_type=1
2387 12:15:25.980592
2388 12:15:25.981104 ==DQS 0 ==
2389 12:15:25.983968 Final DQS duty delay cell = -4
2390 12:15:25.986923 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2391 12:15:25.990419 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2392 12:15:25.993636 [-4] AVG Duty = 4969%(X100)
2393 12:15:25.994138
2394 12:15:25.994467 ==DQS 1 ==
2395 12:15:25.997147 Final DQS duty delay cell = 0
2396 12:15:26.000394 [0] MAX Duty = 5093%(X100), DQS PI = 0
2397 12:15:26.003909 [0] MIN Duty = 4876%(X100), DQS PI = 26
2398 12:15:26.006648 [0] AVG Duty = 4984%(X100)
2399 12:15:26.007065
2400 12:15:26.010080 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2401 12:15:26.010493
2402 12:15:26.013619 CH1 DQS 1 Duty spec in!! Max-Min= 217%
2403 12:15:26.017115 [DutyScan_Calibration_Flow] ====Done====
2404 12:15:26.017682
2405 12:15:26.020253 [DutyScan_Calibration_Flow] k_type=3
2406 12:15:26.037324
2407 12:15:26.037869 ==DQM 0 ==
2408 12:15:26.040596 Final DQM duty delay cell = 0
2409 12:15:26.043911 [0] MAX Duty = 5000%(X100), DQS PI = 22
2410 12:15:26.046768 [0] MIN Duty = 4844%(X100), DQS PI = 54
2411 12:15:26.050454 [0] AVG Duty = 4922%(X100)
2412 12:15:26.050962
2413 12:15:26.051289 ==DQM 1 ==
2414 12:15:26.053868 Final DQM duty delay cell = 0
2415 12:15:26.056790 [0] MAX Duty = 5031%(X100), DQS PI = 36
2416 12:15:26.060221 [0] MIN Duty = 4907%(X100), DQS PI = 2
2417 12:15:26.060634 [0] AVG Duty = 4969%(X100)
2418 12:15:26.063795
2419 12:15:26.067155 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2420 12:15:26.067669
2421 12:15:26.070298 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2422 12:15:26.073889 [DutyScan_Calibration_Flow] ====Done====
2423 12:15:26.074400
2424 12:15:26.076528 [DutyScan_Calibration_Flow] k_type=2
2425 12:15:26.093516
2426 12:15:26.094028 ==DQ 0 ==
2427 12:15:26.096886 Final DQ duty delay cell = 0
2428 12:15:26.100516 [0] MAX Duty = 5062%(X100), DQS PI = 20
2429 12:15:26.103527 [0] MIN Duty = 4907%(X100), DQS PI = 56
2430 12:15:26.104041 [0] AVG Duty = 4984%(X100)
2431 12:15:26.104369
2432 12:15:26.106709 ==DQ 1 ==
2433 12:15:26.110201 Final DQ duty delay cell = 0
2434 12:15:26.113195 [0] MAX Duty = 5125%(X100), DQS PI = 36
2435 12:15:26.116920 [0] MIN Duty = 4969%(X100), DQS PI = 26
2436 12:15:26.117429 [0] AVG Duty = 5047%(X100)
2437 12:15:26.117795
2438 12:15:26.120111 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2439 12:15:26.120620
2440 12:15:26.127143 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2441 12:15:26.130018 [DutyScan_Calibration_Flow] ====Done====
2442 12:15:26.133616 nWR fixed to 30
2443 12:15:26.134126 [ModeRegInit_LP4] CH0 RK0
2444 12:15:26.137129 [ModeRegInit_LP4] CH0 RK1
2445 12:15:26.139793 [ModeRegInit_LP4] CH1 RK0
2446 12:15:26.140203 [ModeRegInit_LP4] CH1 RK1
2447 12:15:26.143177 match AC timing 7
2448 12:15:26.146866 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2449 12:15:26.149862 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2450 12:15:26.156781 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2451 12:15:26.160216 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2452 12:15:26.166788 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2453 12:15:26.167299 ==
2454 12:15:26.169921 Dram Type= 6, Freq= 0, CH_0, rank 0
2455 12:15:26.173596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2456 12:15:26.174106 ==
2457 12:15:26.180233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2458 12:15:26.183657 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2459 12:15:26.193644 [CA 0] Center 40 (10~71) winsize 62
2460 12:15:26.196980 [CA 1] Center 40 (10~70) winsize 61
2461 12:15:26.200114 [CA 2] Center 36 (6~66) winsize 61
2462 12:15:26.203471 [CA 3] Center 35 (5~66) winsize 62
2463 12:15:26.206982 [CA 4] Center 34 (4~65) winsize 62
2464 12:15:26.209712 [CA 5] Center 33 (3~64) winsize 62
2465 12:15:26.210131
2466 12:15:26.213376 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2467 12:15:26.213929
2468 12:15:26.216311 [CATrainingPosCal] consider 1 rank data
2469 12:15:26.220300 u2DelayCellTimex100 = 270/100 ps
2470 12:15:26.223133 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2471 12:15:26.230168 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2472 12:15:26.233348 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2473 12:15:26.236474 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2474 12:15:26.240189 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2475 12:15:26.242949 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2476 12:15:26.243364
2477 12:15:26.246333 CA PerBit enable=1, Macro0, CA PI delay=33
2478 12:15:26.246846
2479 12:15:26.250155 [CBTSetCACLKResult] CA Dly = 33
2480 12:15:26.253419 CS Dly: 7 (0~38)
2481 12:15:26.254143 ==
2482 12:15:26.256469 Dram Type= 6, Freq= 0, CH_0, rank 1
2483 12:15:26.259792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2484 12:15:26.260308 ==
2485 12:15:26.266448 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2486 12:15:26.269935 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2487 12:15:26.279694 [CA 0] Center 40 (10~70) winsize 61
2488 12:15:26.283021 [CA 1] Center 40 (10~70) winsize 61
2489 12:15:26.286442 [CA 2] Center 35 (5~66) winsize 62
2490 12:15:26.289584 [CA 3] Center 35 (5~66) winsize 62
2491 12:15:26.293211 [CA 4] Center 34 (4~65) winsize 62
2492 12:15:26.296499 [CA 5] Center 33 (3~64) winsize 62
2493 12:15:26.297024
2494 12:15:26.299513 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2495 12:15:26.300092
2496 12:15:26.302886 [CATrainingPosCal] consider 2 rank data
2497 12:15:26.306160 u2DelayCellTimex100 = 270/100 ps
2498 12:15:26.309454 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2499 12:15:26.316022 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2500 12:15:26.319387 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2501 12:15:26.323198 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2502 12:15:26.326346 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2503 12:15:26.329466 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2504 12:15:26.330014
2505 12:15:26.333032 CA PerBit enable=1, Macro0, CA PI delay=33
2506 12:15:26.333580
2507 12:15:26.336262 [CBTSetCACLKResult] CA Dly = 33
2508 12:15:26.339315 CS Dly: 8 (0~40)
2509 12:15:26.339728
2510 12:15:26.342635 ----->DramcWriteLeveling(PI) begin...
2511 12:15:26.343053 ==
2512 12:15:26.345986 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 12:15:26.349754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 12:15:26.350261 ==
2515 12:15:26.353063 Write leveling (Byte 0): 32 => 32
2516 12:15:26.356316 Write leveling (Byte 1): 29 => 29
2517 12:15:26.359904 DramcWriteLeveling(PI) end<-----
2518 12:15:26.360416
2519 12:15:26.360740 ==
2520 12:15:26.362760 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 12:15:26.366124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 12:15:26.366635 ==
2523 12:15:26.369529 [Gating] SW mode calibration
2524 12:15:26.376287 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2525 12:15:26.382602 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2526 12:15:26.386190 0 15 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
2527 12:15:26.389578 0 15 4 | B1->B0 | 2828 3434 | 1 0 | (1 1) (0 0)
2528 12:15:26.396004 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 12:15:26.399525 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 12:15:26.402895 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 12:15:26.409041 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 12:15:26.412676 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 12:15:26.416068 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2534 12:15:26.422430 1 0 0 | B1->B0 | 3434 2c2c | 0 0 | (0 1) (0 1)
2535 12:15:26.426102 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2536 12:15:26.429180 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 12:15:26.432744 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 12:15:26.439464 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 12:15:26.442645 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 12:15:26.446175 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 12:15:26.452818 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 12:15:26.455762 1 1 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2543 12:15:26.459312 1 1 4 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
2544 12:15:26.466072 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 12:15:26.469643 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 12:15:26.472837 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 12:15:26.479278 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 12:15:26.482403 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 12:15:26.485974 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 12:15:26.492603 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2551 12:15:26.496064 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2552 12:15:26.499345 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 12:15:26.506362 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 12:15:26.509249 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:15:26.512687 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:15:26.519155 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:15:26.522437 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:15:26.526364 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:15:26.532697 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:15:26.536110 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 12:15:26.539496 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 12:15:26.542654 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 12:15:26.549279 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 12:15:26.553181 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:15:26.556134 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2566 12:15:26.562478 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2567 12:15:26.565801 Total UI for P1: 0, mck2ui 16
2568 12:15:26.569023 best dqsien dly found for B0: ( 1, 3, 28)
2569 12:15:26.572591 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2570 12:15:26.575696 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 12:15:26.579095 Total UI for P1: 0, mck2ui 16
2572 12:15:26.582491 best dqsien dly found for B1: ( 1, 4, 2)
2573 12:15:26.586032 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2574 12:15:26.589433 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2575 12:15:26.589989
2576 12:15:26.595913 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2577 12:15:26.599637 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2578 12:15:26.600149 [Gating] SW calibration Done
2579 12:15:26.602886 ==
2580 12:15:26.603395 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 12:15:26.609664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2582 12:15:26.610173 ==
2583 12:15:26.610502 RX Vref Scan: 0
2584 12:15:26.610811
2585 12:15:26.612619 RX Vref 0 -> 0, step: 1
2586 12:15:26.613029
2587 12:15:26.616327 RX Delay -40 -> 252, step: 8
2588 12:15:26.619372 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2589 12:15:26.622760 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2590 12:15:26.626100 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2591 12:15:26.632898 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2592 12:15:26.635957 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2593 12:15:26.639398 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2594 12:15:26.642521 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2595 12:15:26.645882 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2596 12:15:26.652525 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2597 12:15:26.655493 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2598 12:15:26.659105 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2599 12:15:26.662760 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2600 12:15:26.665924 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2601 12:15:26.669657 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2602 12:15:26.675573 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2603 12:15:26.679281 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2604 12:15:26.679938 ==
2605 12:15:26.682401 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 12:15:26.685837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 12:15:26.686252 ==
2608 12:15:26.689078 DQS Delay:
2609 12:15:26.689526 DQS0 = 0, DQS1 = 0
2610 12:15:26.689861 DQM Delay:
2611 12:15:26.692769 DQM0 = 112, DQM1 = 103
2612 12:15:26.693285 DQ Delay:
2613 12:15:26.695880 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2614 12:15:26.699279 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2615 12:15:26.702525 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2616 12:15:26.709241 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2617 12:15:26.709681
2618 12:15:26.710005
2619 12:15:26.710305 ==
2620 12:15:26.712361 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 12:15:26.716008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 12:15:26.716534 ==
2623 12:15:26.716864
2624 12:15:26.717166
2625 12:15:26.719153 TX Vref Scan disable
2626 12:15:26.719565 == TX Byte 0 ==
2627 12:15:26.726339 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2628 12:15:26.729613 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2629 12:15:26.730125 == TX Byte 1 ==
2630 12:15:26.735805 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2631 12:15:26.739423 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2632 12:15:26.739943 ==
2633 12:15:26.742263 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 12:15:26.745777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 12:15:26.746190 ==
2636 12:15:26.758570 TX Vref=22, minBit 12, minWin=25, winSum=417
2637 12:15:26.762203 TX Vref=24, minBit 1, minWin=26, winSum=426
2638 12:15:26.765630 TX Vref=26, minBit 10, minWin=26, winSum=432
2639 12:15:26.768619 TX Vref=28, minBit 10, minWin=26, winSum=435
2640 12:15:26.772114 TX Vref=30, minBit 8, minWin=25, winSum=436
2641 12:15:26.778483 TX Vref=32, minBit 3, minWin=26, winSum=431
2642 12:15:26.781964 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 28
2643 12:15:26.782437
2644 12:15:26.785063 Final TX Range 1 Vref 28
2645 12:15:26.785510
2646 12:15:26.785848 ==
2647 12:15:26.788436 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 12:15:26.791827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 12:15:26.795033 ==
2650 12:15:26.795448
2651 12:15:26.795770
2652 12:15:26.796069 TX Vref Scan disable
2653 12:15:26.798561 == TX Byte 0 ==
2654 12:15:26.801874 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2655 12:15:26.805343 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2656 12:15:26.808974 == TX Byte 1 ==
2657 12:15:26.812112 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2658 12:15:26.815801 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2659 12:15:26.816314
2660 12:15:26.818588 [DATLAT]
2661 12:15:26.819001 Freq=1200, CH0 RK0
2662 12:15:26.819330
2663 12:15:26.822115 DATLAT Default: 0xd
2664 12:15:26.822523 0, 0xFFFF, sum = 0
2665 12:15:26.825811 1, 0xFFFF, sum = 0
2666 12:15:26.826324 2, 0xFFFF, sum = 0
2667 12:15:26.828557 3, 0xFFFF, sum = 0
2668 12:15:26.828974 4, 0xFFFF, sum = 0
2669 12:15:26.832434 5, 0xFFFF, sum = 0
2670 12:15:26.835087 6, 0xFFFF, sum = 0
2671 12:15:26.835506 7, 0xFFFF, sum = 0
2672 12:15:26.838862 8, 0xFFFF, sum = 0
2673 12:15:26.839376 9, 0xFFFF, sum = 0
2674 12:15:26.842086 10, 0xFFFF, sum = 0
2675 12:15:26.842607 11, 0xFFFF, sum = 0
2676 12:15:26.845177 12, 0x0, sum = 1
2677 12:15:26.845732 13, 0x0, sum = 2
2678 12:15:26.848857 14, 0x0, sum = 3
2679 12:15:26.849275 15, 0x0, sum = 4
2680 12:15:26.849654 best_step = 13
2681 12:15:26.850081
2682 12:15:26.852058 ==
2683 12:15:26.855286 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 12:15:26.858661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 12:15:26.859077 ==
2686 12:15:26.859405 RX Vref Scan: 1
2687 12:15:26.859709
2688 12:15:26.862060 Set Vref Range= 32 -> 127
2689 12:15:26.862472
2690 12:15:26.865265 RX Vref 32 -> 127, step: 1
2691 12:15:26.865741
2692 12:15:26.869088 RX Delay -37 -> 252, step: 4
2693 12:15:26.869906
2694 12:15:26.872128 Set Vref, RX VrefLevel [Byte0]: 32
2695 12:15:26.875400 [Byte1]: 32
2696 12:15:26.875813
2697 12:15:26.878325 Set Vref, RX VrefLevel [Byte0]: 33
2698 12:15:26.881472 [Byte1]: 33
2699 12:15:26.885309
2700 12:15:26.885784 Set Vref, RX VrefLevel [Byte0]: 34
2701 12:15:26.888559 [Byte1]: 34
2702 12:15:26.893300
2703 12:15:26.893860 Set Vref, RX VrefLevel [Byte0]: 35
2704 12:15:26.896654 [Byte1]: 35
2705 12:15:26.901020
2706 12:15:26.901431 Set Vref, RX VrefLevel [Byte0]: 36
2707 12:15:26.904481 [Byte1]: 36
2708 12:15:26.909203
2709 12:15:26.909812 Set Vref, RX VrefLevel [Byte0]: 37
2710 12:15:26.912695 [Byte1]: 37
2711 12:15:26.917157
2712 12:15:26.917918 Set Vref, RX VrefLevel [Byte0]: 38
2713 12:15:26.920467 [Byte1]: 38
2714 12:15:26.925551
2715 12:15:26.926056 Set Vref, RX VrefLevel [Byte0]: 39
2716 12:15:26.928605 [Byte1]: 39
2717 12:15:26.933315
2718 12:15:26.933967 Set Vref, RX VrefLevel [Byte0]: 40
2719 12:15:26.936414 [Byte1]: 40
2720 12:15:26.941411
2721 12:15:26.941954 Set Vref, RX VrefLevel [Byte0]: 41
2722 12:15:26.944413 [Byte1]: 41
2723 12:15:26.949382
2724 12:15:26.949941 Set Vref, RX VrefLevel [Byte0]: 42
2725 12:15:26.952690 [Byte1]: 42
2726 12:15:26.957470
2727 12:15:26.958018 Set Vref, RX VrefLevel [Byte0]: 43
2728 12:15:26.960763 [Byte1]: 43
2729 12:15:26.965301
2730 12:15:26.965851 Set Vref, RX VrefLevel [Byte0]: 44
2731 12:15:26.968612 [Byte1]: 44
2732 12:15:26.973621
2733 12:15:26.974136 Set Vref, RX VrefLevel [Byte0]: 45
2734 12:15:26.976622 [Byte1]: 45
2735 12:15:26.981104
2736 12:15:26.981568 Set Vref, RX VrefLevel [Byte0]: 46
2737 12:15:26.984714 [Byte1]: 46
2738 12:15:26.989683
2739 12:15:26.990187 Set Vref, RX VrefLevel [Byte0]: 47
2740 12:15:26.992915 [Byte1]: 47
2741 12:15:26.997442
2742 12:15:26.997985 Set Vref, RX VrefLevel [Byte0]: 48
2743 12:15:27.000368 [Byte1]: 48
2744 12:15:27.005346
2745 12:15:27.005914 Set Vref, RX VrefLevel [Byte0]: 49
2746 12:15:27.008799 [Byte1]: 49
2747 12:15:27.013517
2748 12:15:27.014024 Set Vref, RX VrefLevel [Byte0]: 50
2749 12:15:27.016432 [Byte1]: 50
2750 12:15:27.021235
2751 12:15:27.021796 Set Vref, RX VrefLevel [Byte0]: 51
2752 12:15:27.024899 [Byte1]: 51
2753 12:15:27.029370
2754 12:15:27.029918 Set Vref, RX VrefLevel [Byte0]: 52
2755 12:15:27.032893 [Byte1]: 52
2756 12:15:27.037227
2757 12:15:27.037708 Set Vref, RX VrefLevel [Byte0]: 53
2758 12:15:27.040809 [Byte1]: 53
2759 12:15:27.045653
2760 12:15:27.046305 Set Vref, RX VrefLevel [Byte0]: 54
2761 12:15:27.048525 [Byte1]: 54
2762 12:15:27.053536
2763 12:15:27.054041 Set Vref, RX VrefLevel [Byte0]: 55
2764 12:15:27.056441 [Byte1]: 55
2765 12:15:27.061280
2766 12:15:27.061811 Set Vref, RX VrefLevel [Byte0]: 56
2767 12:15:27.065053 [Byte1]: 56
2768 12:15:27.069279
2769 12:15:27.069826 Set Vref, RX VrefLevel [Byte0]: 57
2770 12:15:27.072649 [Byte1]: 57
2771 12:15:27.077372
2772 12:15:27.077938 Set Vref, RX VrefLevel [Byte0]: 58
2773 12:15:27.080916 [Byte1]: 58
2774 12:15:27.085473
2775 12:15:27.086019 Set Vref, RX VrefLevel [Byte0]: 59
2776 12:15:27.088787 [Byte1]: 59
2777 12:15:27.093703
2778 12:15:27.094206 Set Vref, RX VrefLevel [Byte0]: 60
2779 12:15:27.096797 [Byte1]: 60
2780 12:15:27.101555
2781 12:15:27.102068 Set Vref, RX VrefLevel [Byte0]: 61
2782 12:15:27.104748 [Byte1]: 61
2783 12:15:27.109544
2784 12:15:27.110049 Set Vref, RX VrefLevel [Byte0]: 62
2785 12:15:27.112389 [Byte1]: 62
2786 12:15:27.117467
2787 12:15:27.118011 Set Vref, RX VrefLevel [Byte0]: 63
2788 12:15:27.120934 [Byte1]: 63
2789 12:15:27.125381
2790 12:15:27.125916 Set Vref, RX VrefLevel [Byte0]: 64
2791 12:15:27.128432 [Byte1]: 64
2792 12:15:27.133448
2793 12:15:27.134019 Set Vref, RX VrefLevel [Byte0]: 65
2794 12:15:27.136463 [Byte1]: 65
2795 12:15:27.140986
2796 12:15:27.141642 Set Vref, RX VrefLevel [Byte0]: 66
2797 12:15:27.144669 [Byte1]: 66
2798 12:15:27.149327
2799 12:15:27.149875 Set Vref, RX VrefLevel [Byte0]: 67
2800 12:15:27.152666 [Byte1]: 67
2801 12:15:27.157020
2802 12:15:27.157431 Set Vref, RX VrefLevel [Byte0]: 68
2803 12:15:27.160253 [Byte1]: 68
2804 12:15:27.165281
2805 12:15:27.165839 Set Vref, RX VrefLevel [Byte0]: 69
2806 12:15:27.168584 [Byte1]: 69
2807 12:15:27.173424
2808 12:15:27.173960 Set Vref, RX VrefLevel [Byte0]: 70
2809 12:15:27.176834 [Byte1]: 70
2810 12:15:27.181661
2811 12:15:27.182418 Set Vref, RX VrefLevel [Byte0]: 71
2812 12:15:27.184269 [Byte1]: 71
2813 12:15:27.189394
2814 12:15:27.189967 Set Vref, RX VrefLevel [Byte0]: 72
2815 12:15:27.192818 [Byte1]: 72
2816 12:15:27.197436
2817 12:15:27.197979 Set Vref, RX VrefLevel [Byte0]: 73
2818 12:15:27.200969 [Byte1]: 73
2819 12:15:27.205331
2820 12:15:27.205904 Set Vref, RX VrefLevel [Byte0]: 74
2821 12:15:27.208935 [Byte1]: 74
2822 12:15:27.213145
2823 12:15:27.213597 Set Vref, RX VrefLevel [Byte0]: 75
2824 12:15:27.216663 [Byte1]: 75
2825 12:15:27.220992
2826 12:15:27.221397 Final RX Vref Byte 0 = 57 to rank0
2827 12:15:27.224953 Final RX Vref Byte 1 = 52 to rank0
2828 12:15:27.228416 Final RX Vref Byte 0 = 57 to rank1
2829 12:15:27.231503 Final RX Vref Byte 1 = 52 to rank1==
2830 12:15:27.234661 Dram Type= 6, Freq= 0, CH_0, rank 0
2831 12:15:27.241357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2832 12:15:27.241914 ==
2833 12:15:27.242248 DQS Delay:
2834 12:15:27.242552 DQS0 = 0, DQS1 = 0
2835 12:15:27.244618 DQM Delay:
2836 12:15:27.245358 DQM0 = 111, DQM1 = 101
2837 12:15:27.248016 DQ Delay:
2838 12:15:27.251142 DQ0 =110, DQ1 =112, DQ2 =110, DQ3 =108
2839 12:15:27.254494 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =122
2840 12:15:27.257676 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2841 12:15:27.261377 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2842 12:15:27.261956
2843 12:15:27.262283
2844 12:15:27.267750 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2845 12:15:27.271128 CH0 RK0: MR19=303, MR18=FBFB
2846 12:15:27.277767 CH0_RK0: MR19=0x303, MR18=0xFBFB, DQSOSC=412, MR23=63, INC=38, DEC=25
2847 12:15:27.278308
2848 12:15:27.281106 ----->DramcWriteLeveling(PI) begin...
2849 12:15:27.281581 ==
2850 12:15:27.284291 Dram Type= 6, Freq= 0, CH_0, rank 1
2851 12:15:27.287998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2852 12:15:27.288475 ==
2853 12:15:27.291632 Write leveling (Byte 0): 33 => 33
2854 12:15:27.294639 Write leveling (Byte 1): 30 => 30
2855 12:15:27.298130 DramcWriteLeveling(PI) end<-----
2856 12:15:27.298643
2857 12:15:27.298966 ==
2858 12:15:27.301338 Dram Type= 6, Freq= 0, CH_0, rank 1
2859 12:15:27.308002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2860 12:15:27.308510 ==
2861 12:15:27.308838 [Gating] SW mode calibration
2862 12:15:27.318078 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2863 12:15:27.321242 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2864 12:15:27.324645 0 15 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2865 12:15:27.331703 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2866 12:15:27.334541 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 12:15:27.337918 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 12:15:27.344390 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 12:15:27.347652 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 12:15:27.351374 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
2871 12:15:27.357838 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
2872 12:15:27.361628 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2873 12:15:27.364734 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 12:15:27.371374 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 12:15:27.374495 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 12:15:27.377826 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2877 12:15:27.384671 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 12:15:27.388210 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2879 12:15:27.391325 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2880 12:15:27.398198 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2881 12:15:27.401536 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 12:15:27.404892 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 12:15:27.408102 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 12:15:27.414513 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 12:15:27.417936 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 12:15:27.420904 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 12:15:27.427704 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2888 12:15:27.431107 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2889 12:15:27.434694 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 12:15:27.441372 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 12:15:27.444682 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 12:15:27.447687 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 12:15:27.454755 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 12:15:27.457974 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 12:15:27.461019 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 12:15:27.467608 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 12:15:27.471396 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 12:15:27.474396 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 12:15:27.481657 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 12:15:27.484645 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 12:15:27.488157 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 12:15:27.494712 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 12:15:27.497749 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2904 12:15:27.501020 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 12:15:27.504650 Total UI for P1: 0, mck2ui 16
2906 12:15:27.507757 best dqsien dly found for B0: ( 1, 3, 28)
2907 12:15:27.511262 Total UI for P1: 0, mck2ui 16
2908 12:15:27.514874 best dqsien dly found for B1: ( 1, 3, 30)
2909 12:15:27.518170 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2910 12:15:27.521096 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2911 12:15:27.521569
2912 12:15:27.524898 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2913 12:15:27.528613 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2914 12:15:27.531313 [Gating] SW calibration Done
2915 12:15:27.531729 ==
2916 12:15:27.534958 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 12:15:27.541717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 12:15:27.542284 ==
2919 12:15:27.542620 RX Vref Scan: 0
2920 12:15:27.542925
2921 12:15:27.544538 RX Vref 0 -> 0, step: 1
2922 12:15:27.544949
2923 12:15:27.548171 RX Delay -40 -> 252, step: 8
2924 12:15:27.551392 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2925 12:15:27.554774 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2926 12:15:27.558125 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
2927 12:15:27.561386 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2928 12:15:27.568016 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2929 12:15:27.571564 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2930 12:15:27.575331 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2931 12:15:27.578142 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2932 12:15:27.581468 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2933 12:15:27.584446 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2934 12:15:27.591941 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2935 12:15:27.595097 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2936 12:15:27.598165 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2937 12:15:27.601703 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2938 12:15:27.604789 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2939 12:15:27.611550 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2940 12:15:27.612065 ==
2941 12:15:27.614954 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 12:15:27.617860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 12:15:27.618278 ==
2944 12:15:27.618605 DQS Delay:
2945 12:15:27.621281 DQS0 = 0, DQS1 = 0
2946 12:15:27.621733 DQM Delay:
2947 12:15:27.624376 DQM0 = 111, DQM1 = 101
2948 12:15:27.624787 DQ Delay:
2949 12:15:27.628315 DQ0 =111, DQ1 =111, DQ2 =107, DQ3 =107
2950 12:15:27.631476 DQ4 =115, DQ5 =99, DQ6 =123, DQ7 =119
2951 12:15:27.634900 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2952 12:15:27.638206 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
2953 12:15:27.638639
2954 12:15:27.638964
2955 12:15:27.641337 ==
2956 12:15:27.644560 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 12:15:27.648062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 12:15:27.648575 ==
2959 12:15:27.648904
2960 12:15:27.649205
2961 12:15:27.651026 TX Vref Scan disable
2962 12:15:27.651440 == TX Byte 0 ==
2963 12:15:27.654318 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2964 12:15:27.661071 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2965 12:15:27.661643 == TX Byte 1 ==
2966 12:15:27.664472 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2967 12:15:27.671435 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2968 12:15:27.671949 ==
2969 12:15:27.674551 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 12:15:27.677645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 12:15:27.678147 ==
2972 12:15:27.690289 TX Vref=22, minBit 1, minWin=25, winSum=427
2973 12:15:27.693116 TX Vref=24, minBit 2, minWin=26, winSum=429
2974 12:15:27.696584 TX Vref=26, minBit 8, minWin=26, winSum=434
2975 12:15:27.700216 TX Vref=28, minBit 1, minWin=27, winSum=440
2976 12:15:27.703250 TX Vref=30, minBit 13, minWin=26, winSum=439
2977 12:15:27.710207 TX Vref=32, minBit 8, minWin=26, winSum=440
2978 12:15:27.713382 [TxChooseVref] Worse bit 1, Min win 27, Win sum 440, Final Vref 28
2979 12:15:27.713934
2980 12:15:27.716750 Final TX Range 1 Vref 28
2981 12:15:27.717285
2982 12:15:27.717650 ==
2983 12:15:27.719607 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 12:15:27.723205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 12:15:27.726484 ==
2986 12:15:27.726991
2987 12:15:27.727316
2988 12:15:27.727620 TX Vref Scan disable
2989 12:15:27.729891 == TX Byte 0 ==
2990 12:15:27.732893 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2991 12:15:27.736268 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2992 12:15:27.739918 == TX Byte 1 ==
2993 12:15:27.742869 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2994 12:15:27.749827 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2995 12:15:27.750240
2996 12:15:27.750566 [DATLAT]
2997 12:15:27.750869 Freq=1200, CH0 RK1
2998 12:15:27.751165
2999 12:15:27.753402 DATLAT Default: 0xd
3000 12:15:27.753958 0, 0xFFFF, sum = 0
3001 12:15:27.756554 1, 0xFFFF, sum = 0
3002 12:15:27.757091 2, 0xFFFF, sum = 0
3003 12:15:27.759591 3, 0xFFFF, sum = 0
3004 12:15:27.763223 4, 0xFFFF, sum = 0
3005 12:15:27.763748 5, 0xFFFF, sum = 0
3006 12:15:27.766469 6, 0xFFFF, sum = 0
3007 12:15:27.766890 7, 0xFFFF, sum = 0
3008 12:15:27.769618 8, 0xFFFF, sum = 0
3009 12:15:27.770127 9, 0xFFFF, sum = 0
3010 12:15:27.773292 10, 0xFFFF, sum = 0
3011 12:15:27.773849 11, 0xFFFF, sum = 0
3012 12:15:27.776617 12, 0x0, sum = 1
3013 12:15:27.777134 13, 0x0, sum = 2
3014 12:15:27.779917 14, 0x0, sum = 3
3015 12:15:27.780434 15, 0x0, sum = 4
3016 12:15:27.780764 best_step = 13
3017 12:15:27.783210
3018 12:15:27.783620 ==
3019 12:15:27.786016 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 12:15:27.789521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 12:15:27.789944 ==
3022 12:15:27.790270 RX Vref Scan: 0
3023 12:15:27.790577
3024 12:15:27.792946 RX Vref 0 -> 0, step: 1
3025 12:15:27.793357
3026 12:15:27.796583 RX Delay -37 -> 252, step: 4
3027 12:15:27.799466 iDelay=195, Bit 0, Center 108 (35 ~ 182) 148
3028 12:15:27.806126 iDelay=195, Bit 1, Center 112 (39 ~ 186) 148
3029 12:15:27.809887 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3030 12:15:27.813052 iDelay=195, Bit 3, Center 106 (35 ~ 178) 144
3031 12:15:27.816238 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3032 12:15:27.819612 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3033 12:15:27.826028 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3034 12:15:27.829518 iDelay=195, Bit 7, Center 118 (47 ~ 190) 144
3035 12:15:27.833281 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3036 12:15:27.836368 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3037 12:15:27.840029 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3038 12:15:27.842859 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3039 12:15:27.850004 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3040 12:15:27.852769 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3041 12:15:27.856542 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3042 12:15:27.859708 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3043 12:15:27.860126 ==
3044 12:15:27.863251 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 12:15:27.869682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 12:15:27.870184 ==
3047 12:15:27.870510 DQS Delay:
3048 12:15:27.873611 DQS0 = 0, DQS1 = 0
3049 12:15:27.874220 DQM Delay:
3050 12:15:27.874556 DQM0 = 110, DQM1 = 101
3051 12:15:27.876718 DQ Delay:
3052 12:15:27.880233 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =106
3053 12:15:27.882932 DQ4 =110, DQ5 =102, DQ6 =122, DQ7 =118
3054 12:15:27.886240 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =92
3055 12:15:27.890223 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3056 12:15:27.890733
3057 12:15:27.891061
3058 12:15:27.897073 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3059 12:15:27.899895 CH0 RK1: MR19=403, MR18=11F9
3060 12:15:27.906417 CH0_RK1: MR19=0x403, MR18=0x11F9, DQSOSC=403, MR23=63, INC=40, DEC=26
3061 12:15:27.909753 [RxdqsGatingPostProcess] freq 1200
3062 12:15:27.916965 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3063 12:15:27.920045 best DQS0 dly(2T, 0.5T) = (0, 11)
3064 12:15:27.920457 best DQS1 dly(2T, 0.5T) = (0, 12)
3065 12:15:27.922925 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3066 12:15:27.926461 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3067 12:15:27.929704 best DQS0 dly(2T, 0.5T) = (0, 11)
3068 12:15:27.932862 best DQS1 dly(2T, 0.5T) = (0, 11)
3069 12:15:27.936136 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3070 12:15:27.940064 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3071 12:15:27.942957 Pre-setting of DQS Precalculation
3072 12:15:27.949881 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3073 12:15:27.950304 ==
3074 12:15:27.953332 Dram Type= 6, Freq= 0, CH_1, rank 0
3075 12:15:27.956378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 12:15:27.956796 ==
3077 12:15:27.962987 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3078 12:15:27.966206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3079 12:15:27.976038 [CA 0] Center 37 (7~67) winsize 61
3080 12:15:27.979144 [CA 1] Center 37 (7~68) winsize 62
3081 12:15:27.982564 [CA 2] Center 34 (4~64) winsize 61
3082 12:15:27.986098 [CA 3] Center 34 (4~64) winsize 61
3083 12:15:27.989249 [CA 4] Center 34 (4~64) winsize 61
3084 12:15:27.992894 [CA 5] Center 33 (3~63) winsize 61
3085 12:15:27.993302
3086 12:15:27.995999 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3087 12:15:27.996410
3088 12:15:27.999338 [CATrainingPosCal] consider 1 rank data
3089 12:15:28.003198 u2DelayCellTimex100 = 270/100 ps
3090 12:15:28.006311 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3091 12:15:28.009616 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3092 12:15:28.016580 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3093 12:15:28.019742 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3094 12:15:28.022904 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3095 12:15:28.026579 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3096 12:15:28.027084
3097 12:15:28.030024 CA PerBit enable=1, Macro0, CA PI delay=33
3098 12:15:28.030533
3099 12:15:28.033209 [CBTSetCACLKResult] CA Dly = 33
3100 12:15:28.033753 CS Dly: 5 (0~36)
3101 12:15:28.034100 ==
3102 12:15:28.036297 Dram Type= 6, Freq= 0, CH_1, rank 1
3103 12:15:28.043088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 12:15:28.043604 ==
3105 12:15:28.046382 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3106 12:15:28.052725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3107 12:15:28.061793 [CA 0] Center 37 (7~68) winsize 62
3108 12:15:28.065384 [CA 1] Center 37 (7~68) winsize 62
3109 12:15:28.068352 [CA 2] Center 34 (4~65) winsize 62
3110 12:15:28.071691 [CA 3] Center 33 (3~64) winsize 62
3111 12:15:28.074837 [CA 4] Center 34 (4~65) winsize 62
3112 12:15:28.078494 [CA 5] Center 33 (3~63) winsize 61
3113 12:15:28.079015
3114 12:15:28.081790 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3115 12:15:28.082298
3116 12:15:28.084771 [CATrainingPosCal] consider 2 rank data
3117 12:15:28.088569 u2DelayCellTimex100 = 270/100 ps
3118 12:15:28.091784 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3119 12:15:28.095252 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3120 12:15:28.101727 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3121 12:15:28.104941 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3122 12:15:28.108422 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3123 12:15:28.111964 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3124 12:15:28.112473
3125 12:15:28.115024 CA PerBit enable=1, Macro0, CA PI delay=33
3126 12:15:28.115433
3127 12:15:28.118153 [CBTSetCACLKResult] CA Dly = 33
3128 12:15:28.118560 CS Dly: 7 (0~40)
3129 12:15:28.118881
3130 12:15:28.121627 ----->DramcWriteLeveling(PI) begin...
3131 12:15:28.125467 ==
3132 12:15:28.128616 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 12:15:28.131938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 12:15:28.132450 ==
3135 12:15:28.135286 Write leveling (Byte 0): 27 => 27
3136 12:15:28.138163 Write leveling (Byte 1): 27 => 27
3137 12:15:28.141403 DramcWriteLeveling(PI) end<-----
3138 12:15:28.141843
3139 12:15:28.142164 ==
3140 12:15:28.144635 Dram Type= 6, Freq= 0, CH_1, rank 0
3141 12:15:28.148250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3142 12:15:28.148662 ==
3143 12:15:28.151698 [Gating] SW mode calibration
3144 12:15:28.158215 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3145 12:15:28.161634 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3146 12:15:28.168294 0 15 0 | B1->B0 | 2f2f 2828 | 1 1 | (0 0) (0 0)
3147 12:15:28.171932 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 12:15:28.174909 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 12:15:28.182053 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 12:15:28.185353 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 12:15:28.188258 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 12:15:28.195207 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3153 12:15:28.198209 0 15 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (0 0)
3154 12:15:28.201514 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 12:15:28.208777 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 12:15:28.212054 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 12:15:28.215003 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 12:15:28.221762 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 12:15:28.225262 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 12:15:28.228642 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 12:15:28.232153 1 0 28 | B1->B0 | 4343 4141 | 0 0 | (0 0) (0 0)
3162 12:15:28.238391 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 12:15:28.241757 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 12:15:28.245518 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 12:15:28.251829 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 12:15:28.255363 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 12:15:28.258459 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 12:15:28.265277 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 12:15:28.268612 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3170 12:15:28.271921 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 12:15:28.278724 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 12:15:28.281765 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 12:15:28.285601 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 12:15:28.292095 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 12:15:28.295140 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 12:15:28.298583 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 12:15:28.305350 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 12:15:28.308902 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 12:15:28.311992 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 12:15:28.315311 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 12:15:28.321876 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 12:15:28.325601 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 12:15:28.328781 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 12:15:28.335641 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 12:15:28.338622 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3186 12:15:28.342104 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 12:15:28.345106 Total UI for P1: 0, mck2ui 16
3188 12:15:28.348723 best dqsien dly found for B0: ( 1, 3, 28)
3189 12:15:28.352041 Total UI for P1: 0, mck2ui 16
3190 12:15:28.355754 best dqsien dly found for B1: ( 1, 3, 28)
3191 12:15:28.358702 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3192 12:15:28.362139 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3193 12:15:28.362556
3194 12:15:28.368834 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3195 12:15:28.372448 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3196 12:15:28.372956 [Gating] SW calibration Done
3197 12:15:28.375699 ==
3198 12:15:28.378894 Dram Type= 6, Freq= 0, CH_1, rank 0
3199 12:15:28.382146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 12:15:28.382560 ==
3201 12:15:28.382888 RX Vref Scan: 0
3202 12:15:28.383190
3203 12:15:28.385456 RX Vref 0 -> 0, step: 1
3204 12:15:28.385899
3205 12:15:28.388615 RX Delay -40 -> 252, step: 8
3206 12:15:28.392185 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3207 12:15:28.395481 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3208 12:15:28.399063 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3209 12:15:28.405466 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3210 12:15:28.408535 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3211 12:15:28.412097 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3212 12:15:28.415428 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3213 12:15:28.418850 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3214 12:15:28.425362 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3215 12:15:28.429028 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3216 12:15:28.432113 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3217 12:15:28.435413 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3218 12:15:28.438446 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3219 12:15:28.445278 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3220 12:15:28.448563 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3221 12:15:28.452154 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3222 12:15:28.452667 ==
3223 12:15:28.455576 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 12:15:28.458369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 12:15:28.458788 ==
3226 12:15:28.461654 DQS Delay:
3227 12:15:28.462065 DQS0 = 0, DQS1 = 0
3228 12:15:28.465716 DQM Delay:
3229 12:15:28.466224 DQM0 = 114, DQM1 = 105
3230 12:15:28.466550 DQ Delay:
3231 12:15:28.468486 DQ0 =123, DQ1 =107, DQ2 =99, DQ3 =115
3232 12:15:28.475226 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3233 12:15:28.478463 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3234 12:15:28.481989 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3235 12:15:28.482464
3236 12:15:28.482820
3237 12:15:28.483126 ==
3238 12:15:28.484963 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 12:15:28.488350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 12:15:28.488936 ==
3241 12:15:28.489282
3242 12:15:28.489636
3243 12:15:28.491789 TX Vref Scan disable
3244 12:15:28.495211 == TX Byte 0 ==
3245 12:15:28.498319 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3246 12:15:28.501804 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3247 12:15:28.505049 == TX Byte 1 ==
3248 12:15:28.508243 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3249 12:15:28.511975 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3250 12:15:28.512487 ==
3251 12:15:28.515006 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 12:15:28.518441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 12:15:28.518927 ==
3254 12:15:28.531672 TX Vref=22, minBit 11, minWin=24, winSum=407
3255 12:15:28.534883 TX Vref=24, minBit 10, minWin=24, winSum=414
3256 12:15:28.538002 TX Vref=26, minBit 9, minWin=25, winSum=416
3257 12:15:28.541589 TX Vref=28, minBit 11, minWin=25, winSum=420
3258 12:15:28.544666 TX Vref=30, minBit 9, minWin=25, winSum=422
3259 12:15:28.551836 TX Vref=32, minBit 9, minWin=25, winSum=422
3260 12:15:28.554930 [TxChooseVref] Worse bit 9, Min win 25, Win sum 422, Final Vref 30
3261 12:15:28.555347
3262 12:15:28.558164 Final TX Range 1 Vref 30
3263 12:15:28.558675
3264 12:15:28.559002 ==
3265 12:15:28.561679 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 12:15:28.564995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 12:15:28.568436 ==
3268 12:15:28.568949
3269 12:15:28.569274
3270 12:15:28.569627 TX Vref Scan disable
3271 12:15:28.571856 == TX Byte 0 ==
3272 12:15:28.574941 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3273 12:15:28.578373 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3274 12:15:28.581720 == TX Byte 1 ==
3275 12:15:28.584759 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3276 12:15:28.588357 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3277 12:15:28.591887
3278 12:15:28.592401 [DATLAT]
3279 12:15:28.592730 Freq=1200, CH1 RK0
3280 12:15:28.593036
3281 12:15:28.594990 DATLAT Default: 0xd
3282 12:15:28.595497 0, 0xFFFF, sum = 0
3283 12:15:28.598117 1, 0xFFFF, sum = 0
3284 12:15:28.598536 2, 0xFFFF, sum = 0
3285 12:15:28.601758 3, 0xFFFF, sum = 0
3286 12:15:28.602275 4, 0xFFFF, sum = 0
3287 12:15:28.604924 5, 0xFFFF, sum = 0
3288 12:15:28.608499 6, 0xFFFF, sum = 0
3289 12:15:28.609016 7, 0xFFFF, sum = 0
3290 12:15:28.611783 8, 0xFFFF, sum = 0
3291 12:15:28.612299 9, 0xFFFF, sum = 0
3292 12:15:28.614627 10, 0xFFFF, sum = 0
3293 12:15:28.615045 11, 0xFFFF, sum = 0
3294 12:15:28.618140 12, 0x0, sum = 1
3295 12:15:28.618555 13, 0x0, sum = 2
3296 12:15:28.621431 14, 0x0, sum = 3
3297 12:15:28.622021 15, 0x0, sum = 4
3298 12:15:28.622376 best_step = 13
3299 12:15:28.622679
3300 12:15:28.624655 ==
3301 12:15:28.628185 Dram Type= 6, Freq= 0, CH_1, rank 0
3302 12:15:28.631259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3303 12:15:28.631671 ==
3304 12:15:28.631990 RX Vref Scan: 1
3305 12:15:28.632287
3306 12:15:28.634865 Set Vref Range= 32 -> 127
3307 12:15:28.635271
3308 12:15:28.638202 RX Vref 32 -> 127, step: 1
3309 12:15:28.638715
3310 12:15:28.641359 RX Delay -21 -> 252, step: 4
3311 12:15:28.641889
3312 12:15:28.645092 Set Vref, RX VrefLevel [Byte0]: 32
3313 12:15:28.648122 [Byte1]: 32
3314 12:15:28.648563
3315 12:15:28.651866 Set Vref, RX VrefLevel [Byte0]: 33
3316 12:15:28.654862 [Byte1]: 33
3317 12:15:28.655274
3318 12:15:28.657933 Set Vref, RX VrefLevel [Byte0]: 34
3319 12:15:28.661378 [Byte1]: 34
3320 12:15:28.666029
3321 12:15:28.666532 Set Vref, RX VrefLevel [Byte0]: 35
3322 12:15:28.669247 [Byte1]: 35
3323 12:15:28.674142
3324 12:15:28.674649 Set Vref, RX VrefLevel [Byte0]: 36
3325 12:15:28.677090 [Byte1]: 36
3326 12:15:28.682013
3327 12:15:28.682518 Set Vref, RX VrefLevel [Byte0]: 37
3328 12:15:28.685137 [Byte1]: 37
3329 12:15:28.689752
3330 12:15:28.690384 Set Vref, RX VrefLevel [Byte0]: 38
3331 12:15:28.692982 [Byte1]: 38
3332 12:15:28.697392
3333 12:15:28.698007 Set Vref, RX VrefLevel [Byte0]: 39
3334 12:15:28.701013 [Byte1]: 39
3335 12:15:28.705648
3336 12:15:28.706151 Set Vref, RX VrefLevel [Byte0]: 40
3337 12:15:28.709041 [Byte1]: 40
3338 12:15:28.713404
3339 12:15:28.713873 Set Vref, RX VrefLevel [Byte0]: 41
3340 12:15:28.716718 [Byte1]: 41
3341 12:15:28.721254
3342 12:15:28.721709 Set Vref, RX VrefLevel [Byte0]: 42
3343 12:15:28.724609 [Byte1]: 42
3344 12:15:28.729128
3345 12:15:28.729564 Set Vref, RX VrefLevel [Byte0]: 43
3346 12:15:28.732738 [Byte1]: 43
3347 12:15:28.737408
3348 12:15:28.737955 Set Vref, RX VrefLevel [Byte0]: 44
3349 12:15:28.740638 [Byte1]: 44
3350 12:15:28.745218
3351 12:15:28.745771 Set Vref, RX VrefLevel [Byte0]: 45
3352 12:15:28.748616 [Byte1]: 45
3353 12:15:28.753417
3354 12:15:28.753955 Set Vref, RX VrefLevel [Byte0]: 46
3355 12:15:28.756173 [Byte1]: 46
3356 12:15:28.760881
3357 12:15:28.761294 Set Vref, RX VrefLevel [Byte0]: 47
3358 12:15:28.764367 [Byte1]: 47
3359 12:15:28.769144
3360 12:15:28.769696 Set Vref, RX VrefLevel [Byte0]: 48
3361 12:15:28.772152 [Byte1]: 48
3362 12:15:28.777125
3363 12:15:28.777695 Set Vref, RX VrefLevel [Byte0]: 49
3364 12:15:28.780306 [Byte1]: 49
3365 12:15:28.784342
3366 12:15:28.787926 Set Vref, RX VrefLevel [Byte0]: 50
3367 12:15:28.790977 [Byte1]: 50
3368 12:15:28.791394
3369 12:15:28.794807 Set Vref, RX VrefLevel [Byte0]: 51
3370 12:15:28.798059 [Byte1]: 51
3371 12:15:28.798474
3372 12:15:28.801419 Set Vref, RX VrefLevel [Byte0]: 52
3373 12:15:28.804525 [Byte1]: 52
3374 12:15:28.808800
3375 12:15:28.809311 Set Vref, RX VrefLevel [Byte0]: 53
3376 12:15:28.812166 [Byte1]: 53
3377 12:15:28.816581
3378 12:15:28.817093 Set Vref, RX VrefLevel [Byte0]: 54
3379 12:15:28.820010 [Byte1]: 54
3380 12:15:28.824607
3381 12:15:28.825127 Set Vref, RX VrefLevel [Byte0]: 55
3382 12:15:28.827763 [Byte1]: 55
3383 12:15:28.832386
3384 12:15:28.832934 Set Vref, RX VrefLevel [Byte0]: 56
3385 12:15:28.835405 [Byte1]: 56
3386 12:15:28.839939
3387 12:15:28.840347 Set Vref, RX VrefLevel [Byte0]: 57
3388 12:15:28.843676 [Byte1]: 57
3389 12:15:28.848079
3390 12:15:28.848585 Set Vref, RX VrefLevel [Byte0]: 58
3391 12:15:28.851408 [Byte1]: 58
3392 12:15:28.856310
3393 12:15:28.856820 Set Vref, RX VrefLevel [Byte0]: 59
3394 12:15:28.859592 [Byte1]: 59
3395 12:15:28.863699
3396 12:15:28.864109 Set Vref, RX VrefLevel [Byte0]: 60
3397 12:15:28.867453 [Byte1]: 60
3398 12:15:28.871829
3399 12:15:28.872358 Set Vref, RX VrefLevel [Byte0]: 61
3400 12:15:28.875421 [Byte1]: 61
3401 12:15:28.880262
3402 12:15:28.880769 Set Vref, RX VrefLevel [Byte0]: 62
3403 12:15:28.882876 [Byte1]: 62
3404 12:15:28.887451
3405 12:15:28.887860 Set Vref, RX VrefLevel [Byte0]: 63
3406 12:15:28.891070 [Byte1]: 63
3407 12:15:28.896007
3408 12:15:28.896515 Set Vref, RX VrefLevel [Byte0]: 64
3409 12:15:28.898705 [Byte1]: 64
3410 12:15:28.903212
3411 12:15:28.903622 Final RX Vref Byte 0 = 59 to rank0
3412 12:15:28.906710 Final RX Vref Byte 1 = 54 to rank0
3413 12:15:28.910217 Final RX Vref Byte 0 = 59 to rank1
3414 12:15:28.913552 Final RX Vref Byte 1 = 54 to rank1==
3415 12:15:28.916620 Dram Type= 6, Freq= 0, CH_1, rank 0
3416 12:15:28.923434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3417 12:15:28.923948 ==
3418 12:15:28.924278 DQS Delay:
3419 12:15:28.924583 DQS0 = 0, DQS1 = 0
3420 12:15:28.927105 DQM Delay:
3421 12:15:28.927611 DQM0 = 113, DQM1 = 106
3422 12:15:28.930418 DQ Delay:
3423 12:15:28.933681 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =108
3424 12:15:28.937297 DQ4 =110, DQ5 =126, DQ6 =126, DQ7 =110
3425 12:15:28.940237 DQ8 =92, DQ9 =98, DQ10 =104, DQ11 =102
3426 12:15:28.943715 DQ12 =114, DQ13 =112, DQ14 =114, DQ15 =112
3427 12:15:28.944230
3428 12:15:28.944563
3429 12:15:28.950026 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f6, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 416 ps
3430 12:15:28.953535 CH1 RK0: MR19=303, MR18=F0F6
3431 12:15:28.960553 CH1_RK0: MR19=0x303, MR18=0xF0F6, DQSOSC=414, MR23=63, INC=38, DEC=25
3432 12:15:28.961077
3433 12:15:28.963597 ----->DramcWriteLeveling(PI) begin...
3434 12:15:28.964021 ==
3435 12:15:28.967174 Dram Type= 6, Freq= 0, CH_1, rank 1
3436 12:15:28.970117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3437 12:15:28.973648 ==
3438 12:15:28.974156 Write leveling (Byte 0): 24 => 24
3439 12:15:28.977013 Write leveling (Byte 1): 29 => 29
3440 12:15:28.979808 DramcWriteLeveling(PI) end<-----
3441 12:15:28.980307
3442 12:15:28.980637 ==
3443 12:15:28.983801 Dram Type= 6, Freq= 0, CH_1, rank 1
3444 12:15:28.990468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3445 12:15:28.991032 ==
3446 12:15:28.991381 [Gating] SW mode calibration
3447 12:15:29.000141 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3448 12:15:29.003542 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3449 12:15:29.006771 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3450 12:15:29.013218 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 12:15:29.016832 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 12:15:29.020241 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 12:15:29.026611 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 12:15:29.030110 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3455 12:15:29.033377 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (0 1) (1 0)
3456 12:15:29.040025 0 15 28 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
3457 12:15:29.043119 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 12:15:29.046455 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 12:15:29.053051 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 12:15:29.056946 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 12:15:29.059588 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 12:15:29.066320 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
3463 12:15:29.069630 1 0 24 | B1->B0 | 2929 4444 | 1 0 | (0 0) (0 0)
3464 12:15:29.073069 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3465 12:15:29.079601 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 12:15:29.082679 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 12:15:29.086164 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 12:15:29.092755 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 12:15:29.096198 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 12:15:29.099442 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 12:15:29.105986 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3472 12:15:29.109217 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3473 12:15:29.112605 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 12:15:29.119363 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 12:15:29.122320 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 12:15:29.125457 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 12:15:29.132061 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 12:15:29.135429 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 12:15:29.138801 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 12:15:29.145517 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 12:15:29.148545 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 12:15:29.151970 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 12:15:29.158468 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 12:15:29.162217 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 12:15:29.165213 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 12:15:29.171858 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 12:15:29.175227 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3488 12:15:29.178708 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3489 12:15:29.181598 Total UI for P1: 0, mck2ui 16
3490 12:15:29.185235 best dqsien dly found for B0: ( 1, 3, 24)
3491 12:15:29.188242 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 12:15:29.191636 Total UI for P1: 0, mck2ui 16
3493 12:15:29.195175 best dqsien dly found for B1: ( 1, 3, 26)
3494 12:15:29.198441 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3495 12:15:29.204978 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3496 12:15:29.205131
3497 12:15:29.208083 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3498 12:15:29.211477 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3499 12:15:29.214681 [Gating] SW calibration Done
3500 12:15:29.214831 ==
3501 12:15:29.218069 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 12:15:29.221435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 12:15:29.221568 ==
3504 12:15:29.224844 RX Vref Scan: 0
3505 12:15:29.224957
3506 12:15:29.225046 RX Vref 0 -> 0, step: 1
3507 12:15:29.225164
3508 12:15:29.228203 RX Delay -40 -> 252, step: 8
3509 12:15:29.231448 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3510 12:15:29.237900 iDelay=200, Bit 1, Center 103 (32 ~ 175) 144
3511 12:15:29.241502 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3512 12:15:29.245069 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3513 12:15:29.248100 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3514 12:15:29.251201 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3515 12:15:29.258061 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3516 12:15:29.261433 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3517 12:15:29.264477 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3518 12:15:29.268162 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3519 12:15:29.271565 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3520 12:15:29.277927 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3521 12:15:29.281560 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3522 12:15:29.284953 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3523 12:15:29.288298 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3524 12:15:29.291626 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3525 12:15:29.294645 ==
3526 12:15:29.295071 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 12:15:29.301128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 12:15:29.301594 ==
3529 12:15:29.301934 DQS Delay:
3530 12:15:29.305100 DQS0 = 0, DQS1 = 0
3531 12:15:29.305664 DQM Delay:
3532 12:15:29.308263 DQM0 = 110, DQM1 = 109
3533 12:15:29.308774 DQ Delay:
3534 12:15:29.311687 DQ0 =115, DQ1 =103, DQ2 =99, DQ3 =107
3535 12:15:29.314707 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3536 12:15:29.317773 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3537 12:15:29.321329 DQ12 =119, DQ13 =119, DQ14 =111, DQ15 =115
3538 12:15:29.321917
3539 12:15:29.322251
3540 12:15:29.322562 ==
3541 12:15:29.324671 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 12:15:29.331046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 12:15:29.331563 ==
3544 12:15:29.331896
3545 12:15:29.332203
3546 12:15:29.332496 TX Vref Scan disable
3547 12:15:29.334367 == TX Byte 0 ==
3548 12:15:29.337947 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3549 12:15:29.344493 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3550 12:15:29.344990 == TX Byte 1 ==
3551 12:15:29.347934 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3552 12:15:29.354423 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3553 12:15:29.354945 ==
3554 12:15:29.357831 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 12:15:29.361130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 12:15:29.361697 ==
3557 12:15:29.372489 TX Vref=22, minBit 3, minWin=25, winSum=423
3558 12:15:29.376159 TX Vref=24, minBit 1, minWin=26, winSum=431
3559 12:15:29.378982 TX Vref=26, minBit 3, minWin=26, winSum=432
3560 12:15:29.382846 TX Vref=28, minBit 7, minWin=26, winSum=432
3561 12:15:29.386095 TX Vref=30, minBit 3, minWin=26, winSum=431
3562 12:15:29.392841 TX Vref=32, minBit 1, minWin=26, winSum=433
3563 12:15:29.396205 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 32
3564 12:15:29.396719
3565 12:15:29.399546 Final TX Range 1 Vref 32
3566 12:15:29.400059
3567 12:15:29.400387 ==
3568 12:15:29.402277 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 12:15:29.405661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 12:15:29.409356 ==
3571 12:15:29.409921
3572 12:15:29.410252
3573 12:15:29.410557 TX Vref Scan disable
3574 12:15:29.412754 == TX Byte 0 ==
3575 12:15:29.415897 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3576 12:15:29.419246 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3577 12:15:29.422338 == TX Byte 1 ==
3578 12:15:29.425795 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3579 12:15:29.432498 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3580 12:15:29.433011
3581 12:15:29.433340 [DATLAT]
3582 12:15:29.433686 Freq=1200, CH1 RK1
3583 12:15:29.433990
3584 12:15:29.435975 DATLAT Default: 0xd
3585 12:15:29.436494 0, 0xFFFF, sum = 0
3586 12:15:29.438847 1, 0xFFFF, sum = 0
3587 12:15:29.442083 2, 0xFFFF, sum = 0
3588 12:15:29.442576 3, 0xFFFF, sum = 0
3589 12:15:29.445568 4, 0xFFFF, sum = 0
3590 12:15:29.445994 5, 0xFFFF, sum = 0
3591 12:15:29.449013 6, 0xFFFF, sum = 0
3592 12:15:29.449557 7, 0xFFFF, sum = 0
3593 12:15:29.451950 8, 0xFFFF, sum = 0
3594 12:15:29.452373 9, 0xFFFF, sum = 0
3595 12:15:29.455301 10, 0xFFFF, sum = 0
3596 12:15:29.455821 11, 0xFFFF, sum = 0
3597 12:15:29.458802 12, 0x0, sum = 1
3598 12:15:29.459321 13, 0x0, sum = 2
3599 12:15:29.462365 14, 0x0, sum = 3
3600 12:15:29.462887 15, 0x0, sum = 4
3601 12:15:29.465553 best_step = 13
3602 12:15:29.466068
3603 12:15:29.466401 ==
3604 12:15:29.468685 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 12:15:29.472061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 12:15:29.472583 ==
3607 12:15:29.472920 RX Vref Scan: 0
3608 12:15:29.475349
3609 12:15:29.475855 RX Vref 0 -> 0, step: 1
3610 12:15:29.476188
3611 12:15:29.478470 RX Delay -21 -> 252, step: 4
3612 12:15:29.485350 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3613 12:15:29.488382 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3614 12:15:29.491699 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3615 12:15:29.494809 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3616 12:15:29.498127 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3617 12:15:29.505157 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3618 12:15:29.508403 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3619 12:15:29.511791 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3620 12:15:29.515033 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3621 12:15:29.518086 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3622 12:15:29.521561 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3623 12:15:29.528393 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3624 12:15:29.531787 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3625 12:15:29.535046 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3626 12:15:29.537990 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3627 12:15:29.544937 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3628 12:15:29.545458 ==
3629 12:15:29.548654 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 12:15:29.551579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 12:15:29.552023 ==
3632 12:15:29.552369 DQS Delay:
3633 12:15:29.554635 DQS0 = 0, DQS1 = 0
3634 12:15:29.555164 DQM Delay:
3635 12:15:29.558089 DQM0 = 111, DQM1 = 110
3636 12:15:29.558592 DQ Delay:
3637 12:15:29.561586 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3638 12:15:29.564912 DQ4 =110, DQ5 =120, DQ6 =122, DQ7 =110
3639 12:15:29.568348 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =102
3640 12:15:29.571740 DQ12 =120, DQ13 =118, DQ14 =120, DQ15 =118
3641 12:15:29.572251
3642 12:15:29.572581
3643 12:15:29.580963 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa09, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3644 12:15:29.584151 CH1 RK1: MR19=304, MR18=FA09
3645 12:15:29.591359 CH1_RK1: MR19=0x304, MR18=0xFA09, DQSOSC=406, MR23=63, INC=39, DEC=26
3646 12:15:29.591873 [RxdqsGatingPostProcess] freq 1200
3647 12:15:29.598104 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3648 12:15:29.601143 best DQS0 dly(2T, 0.5T) = (0, 11)
3649 12:15:29.604399 best DQS1 dly(2T, 0.5T) = (0, 11)
3650 12:15:29.607928 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3651 12:15:29.610953 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3652 12:15:29.614247 best DQS0 dly(2T, 0.5T) = (0, 11)
3653 12:15:29.617550 best DQS1 dly(2T, 0.5T) = (0, 11)
3654 12:15:29.621360 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3655 12:15:29.624183 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3656 12:15:29.627551 Pre-setting of DQS Precalculation
3657 12:15:29.630758 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3658 12:15:29.637513 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3659 12:15:29.647684 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3660 12:15:29.648214
3661 12:15:29.648742
3662 12:15:29.650736 [Calibration Summary] 2400 Mbps
3663 12:15:29.651166 CH 0, Rank 0
3664 12:15:29.654066 SW Impedance : PASS
3665 12:15:29.654499 DUTY Scan : NO K
3666 12:15:29.657366 ZQ Calibration : PASS
3667 12:15:29.657852 Jitter Meter : NO K
3668 12:15:29.660450 CBT Training : PASS
3669 12:15:29.664086 Write leveling : PASS
3670 12:15:29.664538 RX DQS gating : PASS
3671 12:15:29.667698 RX DQ/DQS(RDDQC) : PASS
3672 12:15:29.670876 TX DQ/DQS : PASS
3673 12:15:29.671313 RX DATLAT : PASS
3674 12:15:29.674424 RX DQ/DQS(Engine): PASS
3675 12:15:29.677596 TX OE : NO K
3676 12:15:29.678118 All Pass.
3677 12:15:29.678562
3678 12:15:29.678980 CH 0, Rank 1
3679 12:15:29.680907 SW Impedance : PASS
3680 12:15:29.684205 DUTY Scan : NO K
3681 12:15:29.684732 ZQ Calibration : PASS
3682 12:15:29.687248 Jitter Meter : NO K
3683 12:15:29.691040 CBT Training : PASS
3684 12:15:29.691562 Write leveling : PASS
3685 12:15:29.693879 RX DQS gating : PASS
3686 12:15:29.697224 RX DQ/DQS(RDDQC) : PASS
3687 12:15:29.697693 TX DQ/DQS : PASS
3688 12:15:29.700568 RX DATLAT : PASS
3689 12:15:29.704167 RX DQ/DQS(Engine): PASS
3690 12:15:29.704694 TX OE : NO K
3691 12:15:29.705140 All Pass.
3692 12:15:29.707505
3693 12:15:29.708032 CH 1, Rank 0
3694 12:15:29.710612 SW Impedance : PASS
3695 12:15:29.711150 DUTY Scan : NO K
3696 12:15:29.713534 ZQ Calibration : PASS
3697 12:15:29.713968 Jitter Meter : NO K
3698 12:15:29.717036 CBT Training : PASS
3699 12:15:29.720748 Write leveling : PASS
3700 12:15:29.721262 RX DQS gating : PASS
3701 12:15:29.723750 RX DQ/DQS(RDDQC) : PASS
3702 12:15:29.726751 TX DQ/DQS : PASS
3703 12:15:29.727186 RX DATLAT : PASS
3704 12:15:29.730241 RX DQ/DQS(Engine): PASS
3705 12:15:29.733535 TX OE : NO K
3706 12:15:29.733967 All Pass.
3707 12:15:29.734401
3708 12:15:29.734814 CH 1, Rank 1
3709 12:15:29.737136 SW Impedance : PASS
3710 12:15:29.740113 DUTY Scan : NO K
3711 12:15:29.740542 ZQ Calibration : PASS
3712 12:15:29.743461 Jitter Meter : NO K
3713 12:15:29.747003 CBT Training : PASS
3714 12:15:29.747537 Write leveling : PASS
3715 12:15:29.750194 RX DQS gating : PASS
3716 12:15:29.753722 RX DQ/DQS(RDDQC) : PASS
3717 12:15:29.754249 TX DQ/DQS : PASS
3718 12:15:29.756972 RX DATLAT : PASS
3719 12:15:29.760281 RX DQ/DQS(Engine): PASS
3720 12:15:29.760803 TX OE : NO K
3721 12:15:29.761254 All Pass.
3722 12:15:29.763464
3723 12:15:29.763893 DramC Write-DBI off
3724 12:15:29.766887 PER_BANK_REFRESH: Hybrid Mode
3725 12:15:29.767316 TX_TRACKING: ON
3726 12:15:29.777169 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3727 12:15:29.780078 [FAST_K] Save calibration result to emmc
3728 12:15:29.783919 dramc_set_vcore_voltage set vcore to 650000
3729 12:15:29.786633 Read voltage for 600, 5
3730 12:15:29.787063 Vio18 = 0
3731 12:15:29.790195 Vcore = 650000
3732 12:15:29.790624 Vdram = 0
3733 12:15:29.791062 Vddq = 0
3734 12:15:29.791477 Vmddr = 0
3735 12:15:29.796701 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3736 12:15:29.803695 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3737 12:15:29.804224 MEM_TYPE=3, freq_sel=19
3738 12:15:29.807206 sv_algorithm_assistance_LP4_1600
3739 12:15:29.810045 ============ PULL DRAM RESETB DOWN ============
3740 12:15:29.816984 ========== PULL DRAM RESETB DOWN end =========
3741 12:15:29.820369 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3742 12:15:29.823381 ===================================
3743 12:15:29.826816 LPDDR4 DRAM CONFIGURATION
3744 12:15:29.829879 ===================================
3745 12:15:29.830313 EX_ROW_EN[0] = 0x0
3746 12:15:29.833599 EX_ROW_EN[1] = 0x0
3747 12:15:29.834121 LP4Y_EN = 0x0
3748 12:15:29.836483 WORK_FSP = 0x0
3749 12:15:29.837002 WL = 0x2
3750 12:15:29.840042 RL = 0x2
3751 12:15:29.840569 BL = 0x2
3752 12:15:29.843246 RPST = 0x0
3753 12:15:29.846525 RD_PRE = 0x0
3754 12:15:29.846955 WR_PRE = 0x1
3755 12:15:29.850071 WR_PST = 0x0
3756 12:15:29.850500 DBI_WR = 0x0
3757 12:15:29.853670 DBI_RD = 0x0
3758 12:15:29.854280 OTF = 0x1
3759 12:15:29.856834 ===================================
3760 12:15:29.859889 ===================================
3761 12:15:29.860409 ANA top config
3762 12:15:29.863309 ===================================
3763 12:15:29.866317 DLL_ASYNC_EN = 0
3764 12:15:29.870205 ALL_SLAVE_EN = 1
3765 12:15:29.873261 NEW_RANK_MODE = 1
3766 12:15:29.876683 DLL_IDLE_MODE = 1
3767 12:15:29.877202 LP45_APHY_COMB_EN = 1
3768 12:15:29.879812 TX_ODT_DIS = 1
3769 12:15:29.883367 NEW_8X_MODE = 1
3770 12:15:29.886519 ===================================
3771 12:15:29.889697 ===================================
3772 12:15:29.892959 data_rate = 1200
3773 12:15:29.896187 CKR = 1
3774 12:15:29.896711 DQ_P2S_RATIO = 8
3775 12:15:29.899846 ===================================
3776 12:15:29.902914 CA_P2S_RATIO = 8
3777 12:15:29.906325 DQ_CA_OPEN = 0
3778 12:15:29.909517 DQ_SEMI_OPEN = 0
3779 12:15:29.912671 CA_SEMI_OPEN = 0
3780 12:15:29.916512 CA_FULL_RATE = 0
3781 12:15:29.917028 DQ_CKDIV4_EN = 1
3782 12:15:29.919933 CA_CKDIV4_EN = 1
3783 12:15:29.922542 CA_PREDIV_EN = 0
3784 12:15:29.926086 PH8_DLY = 0
3785 12:15:29.929665 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3786 12:15:29.932963 DQ_AAMCK_DIV = 4
3787 12:15:29.933528 CA_AAMCK_DIV = 4
3788 12:15:29.936111 CA_ADMCK_DIV = 4
3789 12:15:29.939709 DQ_TRACK_CA_EN = 0
3790 12:15:29.942784 CA_PICK = 600
3791 12:15:29.946220 CA_MCKIO = 600
3792 12:15:29.949284 MCKIO_SEMI = 0
3793 12:15:29.952803 PLL_FREQ = 2288
3794 12:15:29.953333 DQ_UI_PI_RATIO = 32
3795 12:15:29.956208 CA_UI_PI_RATIO = 0
3796 12:15:29.959313 ===================================
3797 12:15:29.962704 ===================================
3798 12:15:29.965635 memory_type:LPDDR4
3799 12:15:29.969316 GP_NUM : 10
3800 12:15:29.969796 SRAM_EN : 1
3801 12:15:29.972431 MD32_EN : 0
3802 12:15:29.976189 ===================================
3803 12:15:29.979283 [ANA_INIT] >>>>>>>>>>>>>>
3804 12:15:29.979715 <<<<<< [CONFIGURE PHASE]: ANA_TX
3805 12:15:29.982231 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3806 12:15:29.985605 ===================================
3807 12:15:29.989019 data_rate = 1200,PCW = 0X5800
3808 12:15:29.992674 ===================================
3809 12:15:29.996067 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3810 12:15:30.002178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3811 12:15:30.009390 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3812 12:15:30.012342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3813 12:15:30.015825 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3814 12:15:30.018876 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3815 12:15:30.021953 [ANA_INIT] flow start
3816 12:15:30.022383 [ANA_INIT] PLL >>>>>>>>
3817 12:15:30.025348 [ANA_INIT] PLL <<<<<<<<
3818 12:15:30.028566 [ANA_INIT] MIDPI >>>>>>>>
3819 12:15:30.031889 [ANA_INIT] MIDPI <<<<<<<<
3820 12:15:30.032359 [ANA_INIT] DLL >>>>>>>>
3821 12:15:30.035494 [ANA_INIT] flow end
3822 12:15:30.038498 ============ LP4 DIFF to SE enter ============
3823 12:15:30.041845 ============ LP4 DIFF to SE exit ============
3824 12:15:30.045168 [ANA_INIT] <<<<<<<<<<<<<
3825 12:15:30.048946 [Flow] Enable top DCM control >>>>>
3826 12:15:30.051994 [Flow] Enable top DCM control <<<<<
3827 12:15:30.055217 Enable DLL master slave shuffle
3828 12:15:30.062163 ==============================================================
3829 12:15:30.062667 Gating Mode config
3830 12:15:30.068397 ==============================================================
3831 12:15:30.068830 Config description:
3832 12:15:30.078560 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3833 12:15:30.084830 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3834 12:15:30.091684 SELPH_MODE 0: By rank 1: By Phase
3835 12:15:30.095127 ==============================================================
3836 12:15:30.098561 GAT_TRACK_EN = 1
3837 12:15:30.101536 RX_GATING_MODE = 2
3838 12:15:30.105144 RX_GATING_TRACK_MODE = 2
3839 12:15:30.108505 SELPH_MODE = 1
3840 12:15:30.111998 PICG_EARLY_EN = 1
3841 12:15:30.115102 VALID_LAT_VALUE = 1
3842 12:15:30.122018 ==============================================================
3843 12:15:30.124630 Enter into Gating configuration >>>>
3844 12:15:30.128238 Exit from Gating configuration <<<<
3845 12:15:30.128653 Enter into DVFS_PRE_config >>>>>
3846 12:15:30.141299 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3847 12:15:30.145059 Exit from DVFS_PRE_config <<<<<
3848 12:15:30.147913 Enter into PICG configuration >>>>
3849 12:15:30.151665 Exit from PICG configuration <<<<
3850 12:15:30.152179 [RX_INPUT] configuration >>>>>
3851 12:15:30.154848 [RX_INPUT] configuration <<<<<
3852 12:15:30.161450 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3853 12:15:30.164672 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3854 12:15:30.171221 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3855 12:15:30.177916 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3856 12:15:30.184741 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 12:15:30.191559 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 12:15:30.195062 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3859 12:15:30.198055 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3860 12:15:30.204664 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3861 12:15:30.207987 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3862 12:15:30.211219 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3863 12:15:30.214484 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3864 12:15:30.217685 ===================================
3865 12:15:30.221277 LPDDR4 DRAM CONFIGURATION
3866 12:15:30.224328 ===================================
3867 12:15:30.227726 EX_ROW_EN[0] = 0x0
3868 12:15:30.228144 EX_ROW_EN[1] = 0x0
3869 12:15:30.231365 LP4Y_EN = 0x0
3870 12:15:30.231873 WORK_FSP = 0x0
3871 12:15:30.234575 WL = 0x2
3872 12:15:30.235088 RL = 0x2
3873 12:15:30.237794 BL = 0x2
3874 12:15:30.238303 RPST = 0x0
3875 12:15:30.241052 RD_PRE = 0x0
3876 12:15:30.241585 WR_PRE = 0x1
3877 12:15:30.244406 WR_PST = 0x0
3878 12:15:30.247851 DBI_WR = 0x0
3879 12:15:30.248363 DBI_RD = 0x0
3880 12:15:30.251269 OTF = 0x1
3881 12:15:30.253969 ===================================
3882 12:15:30.257155 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3883 12:15:30.260966 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3884 12:15:30.263902 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3885 12:15:30.267338 ===================================
3886 12:15:30.270670 LPDDR4 DRAM CONFIGURATION
3887 12:15:30.274118 ===================================
3888 12:15:30.277587 EX_ROW_EN[0] = 0x10
3889 12:15:30.278106 EX_ROW_EN[1] = 0x0
3890 12:15:30.280609 LP4Y_EN = 0x0
3891 12:15:30.281128 WORK_FSP = 0x0
3892 12:15:30.284236 WL = 0x2
3893 12:15:30.284749 RL = 0x2
3894 12:15:30.287255 BL = 0x2
3895 12:15:30.287733 RPST = 0x0
3896 12:15:30.290402 RD_PRE = 0x0
3897 12:15:30.290821 WR_PRE = 0x1
3898 12:15:30.294174 WR_PST = 0x0
3899 12:15:30.294690 DBI_WR = 0x0
3900 12:15:30.297367 DBI_RD = 0x0
3901 12:15:30.300276 OTF = 0x1
3902 12:15:30.303983 ===================================
3903 12:15:30.307313 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3904 12:15:30.312343 nWR fixed to 30
3905 12:15:30.315618 [ModeRegInit_LP4] CH0 RK0
3906 12:15:30.316129 [ModeRegInit_LP4] CH0 RK1
3907 12:15:30.318975 [ModeRegInit_LP4] CH1 RK0
3908 12:15:30.322073 [ModeRegInit_LP4] CH1 RK1
3909 12:15:30.322490 match AC timing 17
3910 12:15:30.328927 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3911 12:15:30.332531 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3912 12:15:30.335836 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3913 12:15:30.342399 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3914 12:15:30.345346 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3915 12:15:30.345827 ==
3916 12:15:30.348795 Dram Type= 6, Freq= 0, CH_0, rank 0
3917 12:15:30.352293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3918 12:15:30.352807 ==
3919 12:15:30.358869 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3920 12:15:30.365424 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3921 12:15:30.368662 [CA 0] Center 37 (7~67) winsize 61
3922 12:15:30.372103 [CA 1] Center 36 (6~67) winsize 62
3923 12:15:30.375429 [CA 2] Center 35 (5~65) winsize 61
3924 12:15:30.378543 [CA 3] Center 35 (5~65) winsize 61
3925 12:15:30.382012 [CA 4] Center 34 (4~65) winsize 62
3926 12:15:30.385254 [CA 5] Center 34 (4~64) winsize 61
3927 12:15:30.385803
3928 12:15:30.388532 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3929 12:15:30.389042
3930 12:15:30.391902 [CATrainingPosCal] consider 1 rank data
3931 12:15:30.394822 u2DelayCellTimex100 = 270/100 ps
3932 12:15:30.398212 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3933 12:15:30.401507 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3934 12:15:30.405010 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3935 12:15:30.408390 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3936 12:15:30.415078 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3937 12:15:30.418221 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3938 12:15:30.418633
3939 12:15:30.421350 CA PerBit enable=1, Macro0, CA PI delay=34
3940 12:15:30.421783
3941 12:15:30.424696 [CBTSetCACLKResult] CA Dly = 34
3942 12:15:30.425103 CS Dly: 5 (0~36)
3943 12:15:30.425426 ==
3944 12:15:30.428186 Dram Type= 6, Freq= 0, CH_0, rank 1
3945 12:15:30.431798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3946 12:15:30.434957 ==
3947 12:15:30.438216 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3948 12:15:30.444899 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3949 12:15:30.448317 [CA 0] Center 37 (7~67) winsize 61
3950 12:15:30.451630 [CA 1] Center 36 (6~67) winsize 62
3951 12:15:30.454918 [CA 2] Center 35 (5~65) winsize 61
3952 12:15:30.458041 [CA 3] Center 34 (4~65) winsize 62
3953 12:15:30.461453 [CA 4] Center 34 (4~65) winsize 62
3954 12:15:30.464595 [CA 5] Center 34 (4~64) winsize 61
3955 12:15:30.465018
3956 12:15:30.467946 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3957 12:15:30.468366
3958 12:15:30.471343 [CATrainingPosCal] consider 2 rank data
3959 12:15:30.474418 u2DelayCellTimex100 = 270/100 ps
3960 12:15:30.478055 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3961 12:15:30.481435 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3962 12:15:30.487571 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3963 12:15:30.490849 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3964 12:15:30.494537 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3965 12:15:30.497450 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3966 12:15:30.498036
3967 12:15:30.500771 CA PerBit enable=1, Macro0, CA PI delay=34
3968 12:15:30.501194
3969 12:15:30.504252 [CBTSetCACLKResult] CA Dly = 34
3970 12:15:30.504671 CS Dly: 5 (0~37)
3971 12:15:30.505097
3972 12:15:30.507888 ----->DramcWriteLeveling(PI) begin...
3973 12:15:30.510898 ==
3974 12:15:30.514238 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 12:15:30.517318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 12:15:30.517775 ==
3977 12:15:30.520505 Write leveling (Byte 0): 34 => 34
3978 12:15:30.524097 Write leveling (Byte 1): 31 => 31
3979 12:15:30.527298 DramcWriteLeveling(PI) end<-----
3980 12:15:30.527705
3981 12:15:30.528023 ==
3982 12:15:30.530988 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 12:15:30.534483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 12:15:30.534993 ==
3985 12:15:30.537366 [Gating] SW mode calibration
3986 12:15:30.544037 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3987 12:15:30.547677 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3988 12:15:30.554350 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 12:15:30.557697 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3990 12:15:30.561095 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 12:15:30.567026 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
3992 12:15:30.570727 0 9 16 | B1->B0 | 2f2f 2d2d | 1 0 | (1 1) (0 0)
3993 12:15:30.574264 0 9 20 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
3994 12:15:30.580923 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 12:15:30.584217 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 12:15:30.587733 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 12:15:30.593942 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 12:15:30.597343 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 12:15:30.600147 0 10 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4000 12:15:30.607386 0 10 16 | B1->B0 | 2f2f 3d3d | 0 0 | (0 0) (0 0)
4001 12:15:30.610307 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4002 12:15:30.614064 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 12:15:30.620404 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 12:15:30.623915 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 12:15:30.626937 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 12:15:30.633736 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 12:15:30.636982 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4008 12:15:30.640595 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4009 12:15:30.647005 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 12:15:30.649810 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 12:15:30.653131 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 12:15:30.660232 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 12:15:30.663113 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 12:15:30.666407 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 12:15:30.673310 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 12:15:30.676844 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 12:15:30.680267 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 12:15:30.686644 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 12:15:30.689585 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 12:15:30.693276 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 12:15:30.700143 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 12:15:30.703119 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 12:15:30.706681 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4024 12:15:30.709903 Total UI for P1: 0, mck2ui 16
4025 12:15:30.713160 best dqsien dly found for B0: ( 0, 13, 10)
4026 12:15:30.719456 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4027 12:15:30.723202 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 12:15:30.726145 Total UI for P1: 0, mck2ui 16
4029 12:15:30.729657 best dqsien dly found for B1: ( 0, 13, 18)
4030 12:15:30.732633 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4031 12:15:30.736496 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4032 12:15:30.737011
4033 12:15:30.739981 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4034 12:15:30.742985 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4035 12:15:30.746041 [Gating] SW calibration Done
4036 12:15:30.746449 ==
4037 12:15:30.749411 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 12:15:30.753195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 12:15:30.753752 ==
4040 12:15:30.756368 RX Vref Scan: 0
4041 12:15:30.756886
4042 12:15:30.759570 RX Vref 0 -> 0, step: 1
4043 12:15:30.759983
4044 12:15:30.763064 RX Delay -230 -> 252, step: 16
4045 12:15:30.766040 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4046 12:15:30.769530 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4047 12:15:30.772683 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4048 12:15:30.775918 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4049 12:15:30.782770 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4050 12:15:30.786070 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4051 12:15:30.789515 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4052 12:15:30.792421 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4053 12:15:30.799394 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4054 12:15:30.802465 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4055 12:15:30.805920 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4056 12:15:30.809704 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4057 12:15:30.815641 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4058 12:15:30.819002 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4059 12:15:30.822307 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4060 12:15:30.825715 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4061 12:15:30.826130 ==
4062 12:15:30.828940 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 12:15:30.836022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 12:15:30.836568 ==
4065 12:15:30.836906 DQS Delay:
4066 12:15:30.839320 DQS0 = 0, DQS1 = 0
4067 12:15:30.839829 DQM Delay:
4068 12:15:30.840155 DQM0 = 38, DQM1 = 31
4069 12:15:30.842328 DQ Delay:
4070 12:15:30.845472 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4071 12:15:30.849145 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4072 12:15:30.852567 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4073 12:15:30.855934 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4074 12:15:30.856450
4075 12:15:30.856777
4076 12:15:30.857076 ==
4077 12:15:30.859411 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 12:15:30.862252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 12:15:30.862765 ==
4080 12:15:30.863089
4081 12:15:30.863394
4082 12:15:30.865387 TX Vref Scan disable
4083 12:15:30.868512 == TX Byte 0 ==
4084 12:15:30.872280 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4085 12:15:30.875554 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4086 12:15:30.878660 == TX Byte 1 ==
4087 12:15:30.882417 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4088 12:15:30.885413 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4089 12:15:30.885968 ==
4090 12:15:30.888866 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 12:15:30.892028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 12:15:30.895113 ==
4093 12:15:30.895529
4094 12:15:30.895868
4095 12:15:30.896176 TX Vref Scan disable
4096 12:15:30.899071 == TX Byte 0 ==
4097 12:15:30.902662 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4098 12:15:30.909322 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4099 12:15:30.909894 == TX Byte 1 ==
4100 12:15:30.912597 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4101 12:15:30.919249 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4102 12:15:30.919764
4103 12:15:30.920100 [DATLAT]
4104 12:15:30.920405 Freq=600, CH0 RK0
4105 12:15:30.920697
4106 12:15:30.922669 DATLAT Default: 0x9
4107 12:15:30.923178 0, 0xFFFF, sum = 0
4108 12:15:30.925522 1, 0xFFFF, sum = 0
4109 12:15:30.926046 2, 0xFFFF, sum = 0
4110 12:15:30.928940 3, 0xFFFF, sum = 0
4111 12:15:30.932663 4, 0xFFFF, sum = 0
4112 12:15:30.933180 5, 0xFFFF, sum = 0
4113 12:15:30.935887 6, 0xFFFF, sum = 0
4114 12:15:30.936434 7, 0xFFFF, sum = 0
4115 12:15:30.939107 8, 0x0, sum = 1
4116 12:15:30.939624 9, 0x0, sum = 2
4117 12:15:30.939956 10, 0x0, sum = 3
4118 12:15:30.942444 11, 0x0, sum = 4
4119 12:15:30.942959 best_step = 9
4120 12:15:30.943299
4121 12:15:30.943601 ==
4122 12:15:30.945350 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 12:15:30.952438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 12:15:30.952953 ==
4125 12:15:30.953280 RX Vref Scan: 1
4126 12:15:30.953656
4127 12:15:30.955270 RX Vref 0 -> 0, step: 1
4128 12:15:30.955679
4129 12:15:30.958835 RX Delay -195 -> 252, step: 8
4130 12:15:30.959243
4131 12:15:30.962420 Set Vref, RX VrefLevel [Byte0]: 57
4132 12:15:30.965555 [Byte1]: 52
4133 12:15:30.965976
4134 12:15:30.968696 Final RX Vref Byte 0 = 57 to rank0
4135 12:15:30.972334 Final RX Vref Byte 1 = 52 to rank0
4136 12:15:30.975612 Final RX Vref Byte 0 = 57 to rank1
4137 12:15:30.979239 Final RX Vref Byte 1 = 52 to rank1==
4138 12:15:30.982184 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 12:15:30.985501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 12:15:30.986018 ==
4141 12:15:30.989060 DQS Delay:
4142 12:15:30.989619 DQS0 = 0, DQS1 = 0
4143 12:15:30.992260 DQM Delay:
4144 12:15:30.992769 DQM0 = 36, DQM1 = 28
4145 12:15:30.993144 DQ Delay:
4146 12:15:30.995787 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4147 12:15:30.998993 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =48
4148 12:15:31.002110 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4149 12:15:31.005090 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4150 12:15:31.005543
4151 12:15:31.005881
4152 12:15:31.015444 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4153 12:15:31.018579 CH0 RK0: MR19=808, MR18=3F3E
4154 12:15:31.022106 CH0_RK0: MR19=0x808, MR18=0x3F3E, DQSOSC=397, MR23=63, INC=166, DEC=110
4155 12:15:31.025659
4156 12:15:31.028567 ----->DramcWriteLeveling(PI) begin...
4157 12:15:31.029085 ==
4158 12:15:31.032372 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 12:15:31.035316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 12:15:31.035832 ==
4161 12:15:31.038494 Write leveling (Byte 0): 35 => 35
4162 12:15:31.041943 Write leveling (Byte 1): 31 => 31
4163 12:15:31.044849 DramcWriteLeveling(PI) end<-----
4164 12:15:31.045260
4165 12:15:31.045640 ==
4166 12:15:31.048671 Dram Type= 6, Freq= 0, CH_0, rank 1
4167 12:15:31.051567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 12:15:31.052049 ==
4169 12:15:31.054982 [Gating] SW mode calibration
4170 12:15:31.061834 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4171 12:15:31.068484 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4172 12:15:31.071535 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4173 12:15:31.075331 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 12:15:31.082054 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 12:15:31.085435 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4176 12:15:31.088531 0 9 16 | B1->B0 | 3030 2424 | 0 0 | (1 1) (0 0)
4177 12:15:31.095326 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 12:15:31.098424 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 12:15:31.101714 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 12:15:31.108792 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 12:15:31.111364 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 12:15:31.115105 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 12:15:31.118048 0 10 12 | B1->B0 | 2626 3535 | 1 0 | (0 0) (1 1)
4184 12:15:31.125088 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4185 12:15:31.127747 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 12:15:31.131079 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 12:15:31.137876 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 12:15:31.141656 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 12:15:31.144525 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 12:15:31.151039 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 12:15:31.154370 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 12:15:31.157564 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 12:15:31.164303 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 12:15:31.167486 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 12:15:31.170843 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 12:15:31.177507 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 12:15:31.180973 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 12:15:31.184419 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 12:15:31.190778 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 12:15:31.194205 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 12:15:31.197437 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 12:15:31.203922 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 12:15:31.207303 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 12:15:31.210880 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 12:15:31.217546 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 12:15:31.220293 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 12:15:31.223958 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4208 12:15:31.227450 Total UI for P1: 0, mck2ui 16
4209 12:15:31.230192 best dqsien dly found for B0: ( 0, 13, 10)
4210 12:15:31.236936 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4211 12:15:31.240558 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 12:15:31.244225 Total UI for P1: 0, mck2ui 16
4213 12:15:31.246989 best dqsien dly found for B1: ( 0, 13, 14)
4214 12:15:31.250223 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4215 12:15:31.253879 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4216 12:15:31.254415
4217 12:15:31.257011 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4218 12:15:31.263708 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4219 12:15:31.264219 [Gating] SW calibration Done
4220 12:15:31.264545 ==
4221 12:15:31.266641 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 12:15:31.273684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 12:15:31.274201 ==
4224 12:15:31.274528 RX Vref Scan: 0
4225 12:15:31.274835
4226 12:15:31.277249 RX Vref 0 -> 0, step: 1
4227 12:15:31.277806
4228 12:15:31.280300 RX Delay -230 -> 252, step: 16
4229 12:15:31.283687 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4230 12:15:31.287105 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4231 12:15:31.290315 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4232 12:15:31.297206 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4233 12:15:31.300466 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4234 12:15:31.303234 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4235 12:15:31.306976 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4236 12:15:31.313278 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4237 12:15:31.316924 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4238 12:15:31.320326 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4239 12:15:31.323717 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4240 12:15:31.327233 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4241 12:15:31.333358 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4242 12:15:31.336959 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4243 12:15:31.340162 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4244 12:15:31.343384 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4245 12:15:31.346462 ==
4246 12:15:31.346868 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 12:15:31.353069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 12:15:31.353602 ==
4249 12:15:31.353929 DQS Delay:
4250 12:15:31.356504 DQS0 = 0, DQS1 = 0
4251 12:15:31.356910 DQM Delay:
4252 12:15:31.359864 DQM0 = 35, DQM1 = 30
4253 12:15:31.360272 DQ Delay:
4254 12:15:31.363231 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4255 12:15:31.366396 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4256 12:15:31.370149 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4257 12:15:31.373156 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4258 12:15:31.373712
4259 12:15:31.374043
4260 12:15:31.374345 ==
4261 12:15:31.376682 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 12:15:31.380227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 12:15:31.380748 ==
4264 12:15:31.381076
4265 12:15:31.381379
4266 12:15:31.383354 TX Vref Scan disable
4267 12:15:31.386125 == TX Byte 0 ==
4268 12:15:31.389878 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4269 12:15:31.393258 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4270 12:15:31.396337 == TX Byte 1 ==
4271 12:15:31.400267 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4272 12:15:31.403091 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4273 12:15:31.403614 ==
4274 12:15:31.406060 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 12:15:31.409584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 12:15:31.412819 ==
4277 12:15:31.413335
4278 12:15:31.413720
4279 12:15:31.414029 TX Vref Scan disable
4280 12:15:31.417293 == TX Byte 0 ==
4281 12:15:31.420649 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4282 12:15:31.424019 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4283 12:15:31.427568 == TX Byte 1 ==
4284 12:15:31.430185 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4285 12:15:31.434031 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4286 12:15:31.437442
4287 12:15:31.438003 [DATLAT]
4288 12:15:31.438335 Freq=600, CH0 RK1
4289 12:15:31.438653
4290 12:15:31.440397 DATLAT Default: 0x9
4291 12:15:31.440912 0, 0xFFFF, sum = 0
4292 12:15:31.443449 1, 0xFFFF, sum = 0
4293 12:15:31.443865 2, 0xFFFF, sum = 0
4294 12:15:31.446672 3, 0xFFFF, sum = 0
4295 12:15:31.450156 4, 0xFFFF, sum = 0
4296 12:15:31.450573 5, 0xFFFF, sum = 0
4297 12:15:31.453308 6, 0xFFFF, sum = 0
4298 12:15:31.453795 7, 0xFFFF, sum = 0
4299 12:15:31.456683 8, 0x0, sum = 1
4300 12:15:31.457098 9, 0x0, sum = 2
4301 12:15:31.457433 10, 0x0, sum = 3
4302 12:15:31.460064 11, 0x0, sum = 4
4303 12:15:31.460481 best_step = 9
4304 12:15:31.460806
4305 12:15:31.461103 ==
4306 12:15:31.463452 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 12:15:31.470060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 12:15:31.470476 ==
4309 12:15:31.470802 RX Vref Scan: 0
4310 12:15:31.471109
4311 12:15:31.473533 RX Vref 0 -> 0, step: 1
4312 12:15:31.474054
4313 12:15:31.477121 RX Delay -195 -> 252, step: 8
4314 12:15:31.479904 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4315 12:15:31.487165 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4316 12:15:31.490137 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4317 12:15:31.493190 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4318 12:15:31.496773 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4319 12:15:31.503441 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4320 12:15:31.506602 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4321 12:15:31.510100 iDelay=205, Bit 7, Center 40 (-115 ~ 196) 312
4322 12:15:31.513244 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4323 12:15:31.516630 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4324 12:15:31.523369 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4325 12:15:31.526793 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4326 12:15:31.530159 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4327 12:15:31.533342 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4328 12:15:31.539560 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4329 12:15:31.543283 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4330 12:15:31.543795 ==
4331 12:15:31.546642 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 12:15:31.550134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 12:15:31.550657 ==
4334 12:15:31.552789 DQS Delay:
4335 12:15:31.553298 DQS0 = 0, DQS1 = 0
4336 12:15:31.556443 DQM Delay:
4337 12:15:31.557119 DQM0 = 32, DQM1 = 28
4338 12:15:31.557464 DQ Delay:
4339 12:15:31.559748 DQ0 =28, DQ1 =36, DQ2 =28, DQ3 =28
4340 12:15:31.563141 DQ4 =36, DQ5 =20, DQ6 =44, DQ7 =40
4341 12:15:31.566401 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4342 12:15:31.569607 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4343 12:15:31.570020
4344 12:15:31.570378
4345 12:15:31.579564 [DQSOSCAuto] RK1, (LSB)MR18= 0x6938, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4346 12:15:31.582971 CH0 RK1: MR19=808, MR18=6938
4347 12:15:31.586211 CH0_RK1: MR19=0x808, MR18=0x6938, DQSOSC=390, MR23=63, INC=172, DEC=114
4348 12:15:31.589546 [RxdqsGatingPostProcess] freq 600
4349 12:15:31.596319 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4350 12:15:31.599868 Pre-setting of DQS Precalculation
4351 12:15:31.603157 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4352 12:15:31.603661 ==
4353 12:15:31.606039 Dram Type= 6, Freq= 0, CH_1, rank 0
4354 12:15:31.612974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 12:15:31.613531 ==
4356 12:15:31.615779 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4357 12:15:31.622407 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4358 12:15:31.625970 [CA 0] Center 36 (6~66) winsize 61
4359 12:15:31.629648 [CA 1] Center 36 (6~66) winsize 61
4360 12:15:31.632739 [CA 2] Center 34 (4~65) winsize 62
4361 12:15:31.636300 [CA 3] Center 34 (3~65) winsize 63
4362 12:15:31.639470 [CA 4] Center 34 (4~65) winsize 62
4363 12:15:31.642824 [CA 5] Center 33 (3~64) winsize 62
4364 12:15:31.643341
4365 12:15:31.646428 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4366 12:15:31.646945
4367 12:15:31.649576 [CATrainingPosCal] consider 1 rank data
4368 12:15:31.652981 u2DelayCellTimex100 = 270/100 ps
4369 12:15:31.656011 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4370 12:15:31.659715 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4371 12:15:31.666231 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4372 12:15:31.669434 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4373 12:15:31.672984 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4374 12:15:31.675981 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4375 12:15:31.676493
4376 12:15:31.678986 CA PerBit enable=1, Macro0, CA PI delay=33
4377 12:15:31.679405
4378 12:15:31.682905 [CBTSetCACLKResult] CA Dly = 33
4379 12:15:31.683413 CS Dly: 4 (0~35)
4380 12:15:31.686067 ==
4381 12:15:31.689539 Dram Type= 6, Freq= 0, CH_1, rank 1
4382 12:15:31.692244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 12:15:31.692667 ==
4384 12:15:31.695880 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4385 12:15:31.702264 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4386 12:15:31.706375 [CA 0] Center 35 (5~66) winsize 62
4387 12:15:31.709670 [CA 1] Center 35 (5~66) winsize 62
4388 12:15:31.713177 [CA 2] Center 34 (4~65) winsize 62
4389 12:15:31.716412 [CA 3] Center 34 (3~65) winsize 63
4390 12:15:31.719813 [CA 4] Center 34 (4~65) winsize 62
4391 12:15:31.722818 [CA 5] Center 33 (3~64) winsize 62
4392 12:15:31.723235
4393 12:15:31.725984 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4394 12:15:31.726403
4395 12:15:31.729841 [CATrainingPosCal] consider 2 rank data
4396 12:15:31.732868 u2DelayCellTimex100 = 270/100 ps
4397 12:15:31.735959 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4398 12:15:31.739280 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4399 12:15:31.746039 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4400 12:15:31.749819 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4401 12:15:31.752533 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4402 12:15:31.756142 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4403 12:15:31.756654
4404 12:15:31.759229 CA PerBit enable=1, Macro0, CA PI delay=33
4405 12:15:31.759648
4406 12:15:31.762892 [CBTSetCACLKResult] CA Dly = 33
4407 12:15:31.763405 CS Dly: 4 (0~36)
4408 12:15:31.766236
4409 12:15:31.769134 ----->DramcWriteLeveling(PI) begin...
4410 12:15:31.769628 ==
4411 12:15:31.772652 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 12:15:31.775737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 12:15:31.776212 ==
4414 12:15:31.779561 Write leveling (Byte 0): 31 => 31
4415 12:15:31.782414 Write leveling (Byte 1): 31 => 31
4416 12:15:31.786086 DramcWriteLeveling(PI) end<-----
4417 12:15:31.786597
4418 12:15:31.786926 ==
4419 12:15:31.788992 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 12:15:31.792486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 12:15:31.793000 ==
4422 12:15:31.795937 [Gating] SW mode calibration
4423 12:15:31.802187 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4424 12:15:31.808732 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4425 12:15:31.812298 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4426 12:15:31.815401 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 12:15:31.821648 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 12:15:31.825395 0 9 12 | B1->B0 | 3232 3030 | 1 1 | (1 1) (1 1)
4429 12:15:31.828569 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4430 12:15:31.835271 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 12:15:31.838364 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 12:15:31.842176 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 12:15:31.848190 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 12:15:31.851767 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 12:15:31.855118 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 12:15:31.861700 0 10 12 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (0 0)
4437 12:15:31.865000 0 10 16 | B1->B0 | 4141 4343 | 0 0 | (0 0) (0 0)
4438 12:15:31.868296 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 12:15:31.874791 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 12:15:31.878073 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 12:15:31.881211 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 12:15:31.888018 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 12:15:31.891442 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 12:15:31.894761 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4445 12:15:31.901223 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 12:15:31.904542 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 12:15:31.907603 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 12:15:31.914492 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 12:15:31.917431 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 12:15:31.920932 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 12:15:31.927547 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 12:15:31.930744 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 12:15:31.933991 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 12:15:31.940734 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 12:15:31.944194 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 12:15:31.947305 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 12:15:31.953863 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 12:15:31.957359 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 12:15:31.960748 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 12:15:31.966922 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4461 12:15:31.970574 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 12:15:31.973904 Total UI for P1: 0, mck2ui 16
4463 12:15:31.977378 best dqsien dly found for B0: ( 0, 13, 12)
4464 12:15:31.980542 Total UI for P1: 0, mck2ui 16
4465 12:15:31.983539 best dqsien dly found for B1: ( 0, 13, 12)
4466 12:15:31.987164 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4467 12:15:31.990321 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4468 12:15:31.990825
4469 12:15:31.993656 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4470 12:15:31.996923 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4471 12:15:32.000404 [Gating] SW calibration Done
4472 12:15:32.000910 ==
4473 12:15:32.003882 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 12:15:32.006868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 12:15:32.009895 ==
4476 12:15:32.010318 RX Vref Scan: 0
4477 12:15:32.010649
4478 12:15:32.013367 RX Vref 0 -> 0, step: 1
4479 12:15:32.013829
4480 12:15:32.016815 RX Delay -230 -> 252, step: 16
4481 12:15:32.020218 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4482 12:15:32.022913 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4483 12:15:32.026237 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4484 12:15:32.033136 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4485 12:15:32.036618 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4486 12:15:32.040103 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4487 12:15:32.043269 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4488 12:15:32.046326 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4489 12:15:32.053339 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4490 12:15:32.056628 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4491 12:15:32.059933 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4492 12:15:32.063311 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4493 12:15:32.069597 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4494 12:15:32.072786 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4495 12:15:32.076341 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4496 12:15:32.079675 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4497 12:15:32.082915 ==
4498 12:15:32.085952 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 12:15:32.089585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 12:15:32.090099 ==
4501 12:15:32.090434 DQS Delay:
4502 12:15:32.092615 DQS0 = 0, DQS1 = 0
4503 12:15:32.093032 DQM Delay:
4504 12:15:32.095978 DQM0 = 38, DQM1 = 28
4505 12:15:32.096481 DQ Delay:
4506 12:15:32.099486 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4507 12:15:32.102795 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4508 12:15:32.105876 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4509 12:15:32.109262 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4510 12:15:32.110086
4511 12:15:32.110443
4512 12:15:32.110752 ==
4513 12:15:32.112237 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 12:15:32.115889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 12:15:32.116394 ==
4516 12:15:32.116729
4517 12:15:32.117038
4518 12:15:32.119116 TX Vref Scan disable
4519 12:15:32.122275 == TX Byte 0 ==
4520 12:15:32.125735 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4521 12:15:32.128770 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4522 12:15:32.132422 == TX Byte 1 ==
4523 12:15:32.135455 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4524 12:15:32.139039 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4525 12:15:32.139554 ==
4526 12:15:32.142167 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 12:15:32.148422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 12:15:32.148927 ==
4529 12:15:32.149258
4530 12:15:32.149608
4531 12:15:32.149910 TX Vref Scan disable
4532 12:15:32.152964 == TX Byte 0 ==
4533 12:15:32.156450 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4534 12:15:32.163293 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4535 12:15:32.163805 == TX Byte 1 ==
4536 12:15:32.166133 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4537 12:15:32.173411 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4538 12:15:32.173972
4539 12:15:32.174303 [DATLAT]
4540 12:15:32.174611 Freq=600, CH1 RK0
4541 12:15:32.174915
4542 12:15:32.176136 DATLAT Default: 0x9
4543 12:15:32.176547 0, 0xFFFF, sum = 0
4544 12:15:32.179862 1, 0xFFFF, sum = 0
4545 12:15:32.183204 2, 0xFFFF, sum = 0
4546 12:15:32.183726 3, 0xFFFF, sum = 0
4547 12:15:32.186162 4, 0xFFFF, sum = 0
4548 12:15:32.186579 5, 0xFFFF, sum = 0
4549 12:15:32.189627 6, 0xFFFF, sum = 0
4550 12:15:32.190137 7, 0xFFFF, sum = 0
4551 12:15:32.192551 8, 0x0, sum = 1
4552 12:15:32.192969 9, 0x0, sum = 2
4553 12:15:32.193316 10, 0x0, sum = 3
4554 12:15:32.196162 11, 0x0, sum = 4
4555 12:15:32.196679 best_step = 9
4556 12:15:32.197008
4557 12:15:32.197307 ==
4558 12:15:32.199303 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 12:15:32.206283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 12:15:32.206790 ==
4561 12:15:32.207119 RX Vref Scan: 1
4562 12:15:32.207426
4563 12:15:32.209199 RX Vref 0 -> 0, step: 1
4564 12:15:32.209653
4565 12:15:32.212564 RX Delay -195 -> 252, step: 8
4566 12:15:32.212978
4567 12:15:32.216208 Set Vref, RX VrefLevel [Byte0]: 59
4568 12:15:32.219251 [Byte1]: 54
4569 12:15:32.219666
4570 12:15:32.222640 Final RX Vref Byte 0 = 59 to rank0
4571 12:15:32.226035 Final RX Vref Byte 1 = 54 to rank0
4572 12:15:32.229404 Final RX Vref Byte 0 = 59 to rank1
4573 12:15:32.232678 Final RX Vref Byte 1 = 54 to rank1==
4574 12:15:32.236045 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 12:15:32.239814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 12:15:32.240328 ==
4577 12:15:32.242414 DQS Delay:
4578 12:15:32.242926 DQS0 = 0, DQS1 = 0
4579 12:15:32.245719 DQM Delay:
4580 12:15:32.246133 DQM0 = 38, DQM1 = 27
4581 12:15:32.246463 DQ Delay:
4582 12:15:32.249067 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4583 12:15:32.252474 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4584 12:15:32.255986 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4585 12:15:32.258948 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4586 12:15:32.259365
4587 12:15:32.259689
4588 12:15:32.269154 [DQSOSCAuto] RK0, (LSB)MR18= 0x2735, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
4589 12:15:32.272231 CH1 RK0: MR19=808, MR18=2735
4590 12:15:32.279178 CH1_RK0: MR19=0x808, MR18=0x2735, DQSOSC=399, MR23=63, INC=164, DEC=109
4591 12:15:32.279691
4592 12:15:32.282247 ----->DramcWriteLeveling(PI) begin...
4593 12:15:32.282668 ==
4594 12:15:32.285579 Dram Type= 6, Freq= 0, CH_1, rank 1
4595 12:15:32.289377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 12:15:32.289936 ==
4597 12:15:32.292323 Write leveling (Byte 0): 31 => 31
4598 12:15:32.295225 Write leveling (Byte 1): 31 => 31
4599 12:15:32.299226 DramcWriteLeveling(PI) end<-----
4600 12:15:32.299732
4601 12:15:32.300059 ==
4602 12:15:32.302121 Dram Type= 6, Freq= 0, CH_1, rank 1
4603 12:15:32.305390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 12:15:32.305851 ==
4605 12:15:32.308837 [Gating] SW mode calibration
4606 12:15:32.315508 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4607 12:15:32.322045 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4608 12:15:32.325323 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4609 12:15:32.328431 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 12:15:32.335600 0 9 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4611 12:15:32.338597 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
4612 12:15:32.341955 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4613 12:15:32.348518 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 12:15:32.351952 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 12:15:32.355237 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 12:15:32.361876 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 12:15:32.365535 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 12:15:32.368545 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4619 12:15:32.375332 0 10 12 | B1->B0 | 3333 4242 | 1 0 | (0 0) (0 0)
4620 12:15:32.378321 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4621 12:15:32.381927 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 12:15:32.388660 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 12:15:32.392261 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 12:15:32.395173 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 12:15:32.401937 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 12:15:32.405560 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 12:15:32.408403 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4628 12:15:32.414693 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 12:15:32.418075 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 12:15:32.421582 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 12:15:32.428408 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 12:15:32.431705 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 12:15:32.434946 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 12:15:32.438194 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 12:15:32.444980 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 12:15:32.447874 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 12:15:32.451442 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 12:15:32.457821 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 12:15:32.461419 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 12:15:32.464518 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 12:15:32.471069 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 12:15:32.474327 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 12:15:32.477885 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4644 12:15:32.484643 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 12:15:32.487548 Total UI for P1: 0, mck2ui 16
4646 12:15:32.490901 best dqsien dly found for B0: ( 0, 13, 12)
4647 12:15:32.494362 Total UI for P1: 0, mck2ui 16
4648 12:15:32.497875 best dqsien dly found for B1: ( 0, 13, 12)
4649 12:15:32.500958 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4650 12:15:32.504429 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4651 12:15:32.504939
4652 12:15:32.507353 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4653 12:15:32.511025 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4654 12:15:32.514061 [Gating] SW calibration Done
4655 12:15:32.514479 ==
4656 12:15:32.517586 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 12:15:32.520898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 12:15:32.521409 ==
4659 12:15:32.524038 RX Vref Scan: 0
4660 12:15:32.524462
4661 12:15:32.527316 RX Vref 0 -> 0, step: 1
4662 12:15:32.527825
4663 12:15:32.528158 RX Delay -230 -> 252, step: 16
4664 12:15:32.534092 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4665 12:15:32.537310 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4666 12:15:32.540767 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4667 12:15:32.544338 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4668 12:15:32.550889 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4669 12:15:32.554147 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4670 12:15:32.556938 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4671 12:15:32.560873 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4672 12:15:32.563827 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4673 12:15:32.570574 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4674 12:15:32.574331 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4675 12:15:32.577401 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4676 12:15:32.580630 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4677 12:15:32.587125 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4678 12:15:32.590707 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4679 12:15:32.594150 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4680 12:15:32.594663 ==
4681 12:15:32.597143 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 12:15:32.600428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 12:15:32.604047 ==
4684 12:15:32.604564 DQS Delay:
4685 12:15:32.604897 DQS0 = 0, DQS1 = 0
4686 12:15:32.606977 DQM Delay:
4687 12:15:32.607396 DQM0 = 36, DQM1 = 30
4688 12:15:32.610499 DQ Delay:
4689 12:15:32.613657 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4690 12:15:32.614080 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4691 12:15:32.617099 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4692 12:15:32.620430 DQ12 =41, DQ13 =41, DQ14 =33, DQ15 =33
4693 12:15:32.623528
4694 12:15:32.623945
4695 12:15:32.624272 ==
4696 12:15:32.627148 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 12:15:32.630014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 12:15:32.630435 ==
4699 12:15:32.630768
4700 12:15:32.631075
4701 12:15:32.633332 TX Vref Scan disable
4702 12:15:32.633784 == TX Byte 0 ==
4703 12:15:32.640314 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4704 12:15:32.643365 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4705 12:15:32.643881 == TX Byte 1 ==
4706 12:15:32.650069 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4707 12:15:32.653295 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4708 12:15:32.653870 ==
4709 12:15:32.656769 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 12:15:32.660287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 12:15:32.660797 ==
4712 12:15:32.661126
4713 12:15:32.661431
4714 12:15:32.663117 TX Vref Scan disable
4715 12:15:32.666736 == TX Byte 0 ==
4716 12:15:32.670186 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4717 12:15:32.673147 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4718 12:15:32.677242 == TX Byte 1 ==
4719 12:15:32.680202 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4720 12:15:32.683629 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4721 12:15:32.686865
4722 12:15:32.687377 [DATLAT]
4723 12:15:32.687709 Freq=600, CH1 RK1
4724 12:15:32.688018
4725 12:15:32.689990 DATLAT Default: 0x9
4726 12:15:32.690403 0, 0xFFFF, sum = 0
4727 12:15:32.693645 1, 0xFFFF, sum = 0
4728 12:15:32.694157 2, 0xFFFF, sum = 0
4729 12:15:32.696704 3, 0xFFFF, sum = 0
4730 12:15:32.697126 4, 0xFFFF, sum = 0
4731 12:15:32.700104 5, 0xFFFF, sum = 0
4732 12:15:32.700620 6, 0xFFFF, sum = 0
4733 12:15:32.703209 7, 0xFFFF, sum = 0
4734 12:15:32.703625 8, 0x0, sum = 1
4735 12:15:32.706704 9, 0x0, sum = 2
4736 12:15:32.707123 10, 0x0, sum = 3
4737 12:15:32.710130 11, 0x0, sum = 4
4738 12:15:32.710645 best_step = 9
4739 12:15:32.710979
4740 12:15:32.711287 ==
4741 12:15:32.713231 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 12:15:32.720390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 12:15:32.720905 ==
4744 12:15:32.721238 RX Vref Scan: 0
4745 12:15:32.721597
4746 12:15:32.723231 RX Vref 0 -> 0, step: 1
4747 12:15:32.723641
4748 12:15:32.726487 RX Delay -195 -> 252, step: 8
4749 12:15:32.730095 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4750 12:15:32.736613 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4751 12:15:32.739967 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4752 12:15:32.742990 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4753 12:15:32.746545 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4754 12:15:32.749890 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4755 12:15:32.756204 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4756 12:15:32.759868 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4757 12:15:32.762657 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4758 12:15:32.766327 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4759 12:15:32.772649 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4760 12:15:32.776159 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4761 12:15:32.779793 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4762 12:15:32.782834 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4763 12:15:32.789632 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4764 12:15:32.792965 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4765 12:15:32.793524 ==
4766 12:15:32.796045 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 12:15:32.799427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 12:15:32.799951 ==
4769 12:15:32.802595 DQS Delay:
4770 12:15:32.803104 DQS0 = 0, DQS1 = 0
4771 12:15:32.803434 DQM Delay:
4772 12:15:32.805665 DQM0 = 36, DQM1 = 30
4773 12:15:32.806117 DQ Delay:
4774 12:15:32.808974 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4775 12:15:32.812463 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =36
4776 12:15:32.815941 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =24
4777 12:15:32.818977 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4778 12:15:32.819408
4779 12:15:32.819734
4780 12:15:32.828856 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b5b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4781 12:15:32.832438 CH1 RK1: MR19=808, MR18=3B5B
4782 12:15:32.838702 CH1_RK1: MR19=0x808, MR18=0x3B5B, DQSOSC=392, MR23=63, INC=170, DEC=113
4783 12:15:32.839217 [RxdqsGatingPostProcess] freq 600
4784 12:15:32.845563 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4785 12:15:32.848888 Pre-setting of DQS Precalculation
4786 12:15:32.852174 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4787 12:15:32.862216 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4788 12:15:32.868807 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4789 12:15:32.869426
4790 12:15:32.869815
4791 12:15:32.871738 [Calibration Summary] 1200 Mbps
4792 12:15:32.872153 CH 0, Rank 0
4793 12:15:32.875081 SW Impedance : PASS
4794 12:15:32.875497 DUTY Scan : NO K
4795 12:15:32.878366 ZQ Calibration : PASS
4796 12:15:32.881712 Jitter Meter : NO K
4797 12:15:32.882219 CBT Training : PASS
4798 12:15:32.885141 Write leveling : PASS
4799 12:15:32.888156 RX DQS gating : PASS
4800 12:15:32.888573 RX DQ/DQS(RDDQC) : PASS
4801 12:15:32.891672 TX DQ/DQS : PASS
4802 12:15:32.895065 RX DATLAT : PASS
4803 12:15:32.895482 RX DQ/DQS(Engine): PASS
4804 12:15:32.898394 TX OE : NO K
4805 12:15:32.898904 All Pass.
4806 12:15:32.899235
4807 12:15:32.901890 CH 0, Rank 1
4808 12:15:32.902403 SW Impedance : PASS
4809 12:15:32.905220 DUTY Scan : NO K
4810 12:15:32.908345 ZQ Calibration : PASS
4811 12:15:32.908860 Jitter Meter : NO K
4812 12:15:32.911899 CBT Training : PASS
4813 12:15:32.914802 Write leveling : PASS
4814 12:15:32.915224 RX DQS gating : PASS
4815 12:15:32.918114 RX DQ/DQS(RDDQC) : PASS
4816 12:15:32.918533 TX DQ/DQS : PASS
4817 12:15:32.921448 RX DATLAT : PASS
4818 12:15:32.924784 RX DQ/DQS(Engine): PASS
4819 12:15:32.925199 TX OE : NO K
4820 12:15:32.928274 All Pass.
4821 12:15:32.928688
4822 12:15:32.929017 CH 1, Rank 0
4823 12:15:32.931468 SW Impedance : PASS
4824 12:15:32.931975 DUTY Scan : NO K
4825 12:15:32.934543 ZQ Calibration : PASS
4826 12:15:32.937993 Jitter Meter : NO K
4827 12:15:32.938503 CBT Training : PASS
4828 12:15:32.941289 Write leveling : PASS
4829 12:15:32.944907 RX DQS gating : PASS
4830 12:15:32.945419 RX DQ/DQS(RDDQC) : PASS
4831 12:15:32.947848 TX DQ/DQS : PASS
4832 12:15:32.951669 RX DATLAT : PASS
4833 12:15:32.952182 RX DQ/DQS(Engine): PASS
4834 12:15:32.955104 TX OE : NO K
4835 12:15:32.955670 All Pass.
4836 12:15:32.956006
4837 12:15:32.958182 CH 1, Rank 1
4838 12:15:32.958697 SW Impedance : PASS
4839 12:15:32.961548 DUTY Scan : NO K
4840 12:15:32.964846 ZQ Calibration : PASS
4841 12:15:32.965356 Jitter Meter : NO K
4842 12:15:32.968049 CBT Training : PASS
4843 12:15:32.971055 Write leveling : PASS
4844 12:15:32.971472 RX DQS gating : PASS
4845 12:15:32.974260 RX DQ/DQS(RDDQC) : PASS
4846 12:15:32.974701 TX DQ/DQS : PASS
4847 12:15:32.977976 RX DATLAT : PASS
4848 12:15:32.981404 RX DQ/DQS(Engine): PASS
4849 12:15:32.981977 TX OE : NO K
4850 12:15:32.984423 All Pass.
4851 12:15:32.984836
4852 12:15:32.985164 DramC Write-DBI off
4853 12:15:32.987882 PER_BANK_REFRESH: Hybrid Mode
4854 12:15:32.991347 TX_TRACKING: ON
4855 12:15:32.998038 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4856 12:15:33.001410 [FAST_K] Save calibration result to emmc
4857 12:15:33.004673 dramc_set_vcore_voltage set vcore to 662500
4858 12:15:33.008002 Read voltage for 933, 3
4859 12:15:33.008517 Vio18 = 0
4860 12:15:33.011165 Vcore = 662500
4861 12:15:33.011676 Vdram = 0
4862 12:15:33.012009 Vddq = 0
4863 12:15:33.014374 Vmddr = 0
4864 12:15:33.017834 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4865 12:15:33.024564 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4866 12:15:33.025077 MEM_TYPE=3, freq_sel=17
4867 12:15:33.027492 sv_algorithm_assistance_LP4_1600
4868 12:15:33.034348 ============ PULL DRAM RESETB DOWN ============
4869 12:15:33.037814 ========== PULL DRAM RESETB DOWN end =========
4870 12:15:33.041343 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4871 12:15:33.044484 ===================================
4872 12:15:33.047585 LPDDR4 DRAM CONFIGURATION
4873 12:15:33.050890 ===================================
4874 12:15:33.054336 EX_ROW_EN[0] = 0x0
4875 12:15:33.054846 EX_ROW_EN[1] = 0x0
4876 12:15:33.058016 LP4Y_EN = 0x0
4877 12:15:33.058527 WORK_FSP = 0x0
4878 12:15:33.061370 WL = 0x3
4879 12:15:33.061907 RL = 0x3
4880 12:15:33.064354 BL = 0x2
4881 12:15:33.064862 RPST = 0x0
4882 12:15:33.067368 RD_PRE = 0x0
4883 12:15:33.067786 WR_PRE = 0x1
4884 12:15:33.070688 WR_PST = 0x0
4885 12:15:33.071143 DBI_WR = 0x0
4886 12:15:33.074185 DBI_RD = 0x0
4887 12:15:33.074701 OTF = 0x1
4888 12:15:33.077681 ===================================
4889 12:15:33.081232 ===================================
4890 12:15:33.083995 ANA top config
4891 12:15:33.087702 ===================================
4892 12:15:33.090851 DLL_ASYNC_EN = 0
4893 12:15:33.091361 ALL_SLAVE_EN = 1
4894 12:15:33.094236 NEW_RANK_MODE = 1
4895 12:15:33.097684 DLL_IDLE_MODE = 1
4896 12:15:33.100476 LP45_APHY_COMB_EN = 1
4897 12:15:33.100985 TX_ODT_DIS = 1
4898 12:15:33.104284 NEW_8X_MODE = 1
4899 12:15:33.107329 ===================================
4900 12:15:33.110381 ===================================
4901 12:15:33.113607 data_rate = 1866
4902 12:15:33.116822 CKR = 1
4903 12:15:33.120367 DQ_P2S_RATIO = 8
4904 12:15:33.123777 ===================================
4905 12:15:33.127148 CA_P2S_RATIO = 8
4906 12:15:33.127668 DQ_CA_OPEN = 0
4907 12:15:33.130263 DQ_SEMI_OPEN = 0
4908 12:15:33.133856 CA_SEMI_OPEN = 0
4909 12:15:33.136883 CA_FULL_RATE = 0
4910 12:15:33.140530 DQ_CKDIV4_EN = 1
4911 12:15:33.143719 CA_CKDIV4_EN = 1
4912 12:15:33.144236 CA_PREDIV_EN = 0
4913 12:15:33.147247 PH8_DLY = 0
4914 12:15:33.150241 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4915 12:15:33.153573 DQ_AAMCK_DIV = 4
4916 12:15:33.156997 CA_AAMCK_DIV = 4
4917 12:15:33.160316 CA_ADMCK_DIV = 4
4918 12:15:33.160830 DQ_TRACK_CA_EN = 0
4919 12:15:33.163365 CA_PICK = 933
4920 12:15:33.167034 CA_MCKIO = 933
4921 12:15:33.170520 MCKIO_SEMI = 0
4922 12:15:33.173365 PLL_FREQ = 3732
4923 12:15:33.177061 DQ_UI_PI_RATIO = 32
4924 12:15:33.180486 CA_UI_PI_RATIO = 0
4925 12:15:33.183790 ===================================
4926 12:15:33.186643 ===================================
4927 12:15:33.187064 memory_type:LPDDR4
4928 12:15:33.189858 GP_NUM : 10
4929 12:15:33.193324 SRAM_EN : 1
4930 12:15:33.193887 MD32_EN : 0
4931 12:15:33.196578 ===================================
4932 12:15:33.200138 [ANA_INIT] >>>>>>>>>>>>>>
4933 12:15:33.203323 <<<<<< [CONFIGURE PHASE]: ANA_TX
4934 12:15:33.206447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4935 12:15:33.209854 ===================================
4936 12:15:33.213354 data_rate = 1866,PCW = 0X8f00
4937 12:15:33.216263 ===================================
4938 12:15:33.219863 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4939 12:15:33.222948 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4940 12:15:33.229906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4941 12:15:33.233320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4942 12:15:33.236657 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4943 12:15:33.240045 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4944 12:15:33.243456 [ANA_INIT] flow start
4945 12:15:33.246206 [ANA_INIT] PLL >>>>>>>>
4946 12:15:33.246625 [ANA_INIT] PLL <<<<<<<<
4947 12:15:33.249417 [ANA_INIT] MIDPI >>>>>>>>
4948 12:15:33.253126 [ANA_INIT] MIDPI <<<<<<<<
4949 12:15:33.256159 [ANA_INIT] DLL >>>>>>>>
4950 12:15:33.256575 [ANA_INIT] flow end
4951 12:15:33.259872 ============ LP4 DIFF to SE enter ============
4952 12:15:33.266002 ============ LP4 DIFF to SE exit ============
4953 12:15:33.266424 [ANA_INIT] <<<<<<<<<<<<<
4954 12:15:33.269469 [Flow] Enable top DCM control >>>>>
4955 12:15:33.272941 [Flow] Enable top DCM control <<<<<
4956 12:15:33.276285 Enable DLL master slave shuffle
4957 12:15:33.283085 ==============================================================
4958 12:15:33.283602 Gating Mode config
4959 12:15:33.289454 ==============================================================
4960 12:15:33.292796 Config description:
4961 12:15:33.302718 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4962 12:15:33.308908 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4963 12:15:33.312480 SELPH_MODE 0: By rank 1: By Phase
4964 12:15:33.319064 ==============================================================
4965 12:15:33.322057 GAT_TRACK_EN = 1
4966 12:15:33.325322 RX_GATING_MODE = 2
4967 12:15:33.325776 RX_GATING_TRACK_MODE = 2
4968 12:15:33.328614 SELPH_MODE = 1
4969 12:15:33.332336 PICG_EARLY_EN = 1
4970 12:15:33.335381 VALID_LAT_VALUE = 1
4971 12:15:33.342430 ==============================================================
4972 12:15:33.345358 Enter into Gating configuration >>>>
4973 12:15:33.348739 Exit from Gating configuration <<<<
4974 12:15:33.352002 Enter into DVFS_PRE_config >>>>>
4975 12:15:33.361910 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4976 12:15:33.365132 Exit from DVFS_PRE_config <<<<<
4977 12:15:33.368485 Enter into PICG configuration >>>>
4978 12:15:33.371896 Exit from PICG configuration <<<<
4979 12:15:33.375083 [RX_INPUT] configuration >>>>>
4980 12:15:33.378780 [RX_INPUT] configuration <<<<<
4981 12:15:33.381716 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4982 12:15:33.388631 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4983 12:15:33.395103 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4984 12:15:33.401986 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4985 12:15:33.404972 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4986 12:15:33.411715 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4987 12:15:33.414845 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4988 12:15:33.421567 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4989 12:15:33.424572 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4990 12:15:33.428343 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4991 12:15:33.431183 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4992 12:15:33.438148 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4993 12:15:33.441328 ===================================
4994 12:15:33.444848 LPDDR4 DRAM CONFIGURATION
4995 12:15:33.448058 ===================================
4996 12:15:33.448503 EX_ROW_EN[0] = 0x0
4997 12:15:33.451688 EX_ROW_EN[1] = 0x0
4998 12:15:33.452199 LP4Y_EN = 0x0
4999 12:15:33.454382 WORK_FSP = 0x0
5000 12:15:33.454800 WL = 0x3
5001 12:15:33.457868 RL = 0x3
5002 12:15:33.458380 BL = 0x2
5003 12:15:33.461522 RPST = 0x0
5004 12:15:33.462039 RD_PRE = 0x0
5005 12:15:33.464958 WR_PRE = 0x1
5006 12:15:33.465464 WR_PST = 0x0
5007 12:15:33.468143 DBI_WR = 0x0
5008 12:15:33.468658 DBI_RD = 0x0
5009 12:15:33.471494 OTF = 0x1
5010 12:15:33.474567 ===================================
5011 12:15:33.478137 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5012 12:15:33.481122 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5013 12:15:33.488104 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5014 12:15:33.491048 ===================================
5015 12:15:33.491470 LPDDR4 DRAM CONFIGURATION
5016 12:15:33.494750 ===================================
5017 12:15:33.497674 EX_ROW_EN[0] = 0x10
5018 12:15:33.501131 EX_ROW_EN[1] = 0x0
5019 12:15:33.501682 LP4Y_EN = 0x0
5020 12:15:33.504407 WORK_FSP = 0x0
5021 12:15:33.504918 WL = 0x3
5022 12:15:33.507690 RL = 0x3
5023 12:15:33.508203 BL = 0x2
5024 12:15:33.510921 RPST = 0x0
5025 12:15:33.511416 RD_PRE = 0x0
5026 12:15:33.514015 WR_PRE = 0x1
5027 12:15:33.514429 WR_PST = 0x0
5028 12:15:33.517588 DBI_WR = 0x0
5029 12:15:33.518250 DBI_RD = 0x0
5030 12:15:33.521148 OTF = 0x1
5031 12:15:33.523957 ===================================
5032 12:15:33.530557 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5033 12:15:33.533821 nWR fixed to 30
5034 12:15:33.537353 [ModeRegInit_LP4] CH0 RK0
5035 12:15:33.537865 [ModeRegInit_LP4] CH0 RK1
5036 12:15:33.541104 [ModeRegInit_LP4] CH1 RK0
5037 12:15:33.544123 [ModeRegInit_LP4] CH1 RK1
5038 12:15:33.544642 match AC timing 9
5039 12:15:33.550716 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5040 12:15:33.554163 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5041 12:15:33.557550 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5042 12:15:33.563880 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5043 12:15:33.567425 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5044 12:15:33.567939 ==
5045 12:15:33.570582 Dram Type= 6, Freq= 0, CH_0, rank 0
5046 12:15:33.574164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5047 12:15:33.574733 ==
5048 12:15:33.580749 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5049 12:15:33.587175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5050 12:15:33.590686 [CA 0] Center 38 (8~69) winsize 62
5051 12:15:33.594047 [CA 1] Center 38 (8~69) winsize 62
5052 12:15:33.597297 [CA 2] Center 35 (5~65) winsize 61
5053 12:15:33.600622 [CA 3] Center 35 (5~65) winsize 61
5054 12:15:33.604446 [CA 4] Center 34 (4~64) winsize 61
5055 12:15:33.607520 [CA 5] Center 33 (3~64) winsize 62
5056 12:15:33.608032
5057 12:15:33.610511 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5058 12:15:33.610929
5059 12:15:33.613928 [CATrainingPosCal] consider 1 rank data
5060 12:15:33.617595 u2DelayCellTimex100 = 270/100 ps
5061 12:15:33.620666 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5062 12:15:33.623741 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5063 12:15:33.627528 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5064 12:15:33.630373 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5065 12:15:33.633867 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5066 12:15:33.636931 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5067 12:15:33.637389
5068 12:15:33.643679 CA PerBit enable=1, Macro0, CA PI delay=33
5069 12:15:33.644229
5070 12:15:33.647345 [CBTSetCACLKResult] CA Dly = 33
5071 12:15:33.647901 CS Dly: 7 (0~38)
5072 12:15:33.648416 ==
5073 12:15:33.650253 Dram Type= 6, Freq= 0, CH_0, rank 1
5074 12:15:33.653679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5075 12:15:33.654102 ==
5076 12:15:33.660174 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5077 12:15:33.667144 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5078 12:15:33.670126 [CA 0] Center 38 (8~69) winsize 62
5079 12:15:33.673731 [CA 1] Center 38 (8~69) winsize 62
5080 12:15:33.677173 [CA 2] Center 35 (5~66) winsize 62
5081 12:15:33.680530 [CA 3] Center 35 (5~66) winsize 62
5082 12:15:33.683517 [CA 4] Center 34 (4~65) winsize 62
5083 12:15:33.686563 [CA 5] Center 34 (4~64) winsize 61
5084 12:15:33.687071
5085 12:15:33.689841 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5086 12:15:33.690259
5087 12:15:33.693291 [CATrainingPosCal] consider 2 rank data
5088 12:15:33.696411 u2DelayCellTimex100 = 270/100 ps
5089 12:15:33.699848 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5090 12:15:33.703085 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5091 12:15:33.706642 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5092 12:15:33.710259 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5093 12:15:33.716715 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5094 12:15:33.719610 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5095 12:15:33.720028
5096 12:15:33.723361 CA PerBit enable=1, Macro0, CA PI delay=34
5097 12:15:33.723782
5098 12:15:33.726320 [CBTSetCACLKResult] CA Dly = 34
5099 12:15:33.726737 CS Dly: 7 (0~38)
5100 12:15:33.727066
5101 12:15:33.729691 ----->DramcWriteLeveling(PI) begin...
5102 12:15:33.730113 ==
5103 12:15:33.733156 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 12:15:33.739874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 12:15:33.740408 ==
5106 12:15:33.742875 Write leveling (Byte 0): 30 => 30
5107 12:15:33.743286 Write leveling (Byte 1): 29 => 29
5108 12:15:33.746451 DramcWriteLeveling(PI) end<-----
5109 12:15:33.746959
5110 12:15:33.747282 ==
5111 12:15:33.749748 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 12:15:33.756706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 12:15:33.757235 ==
5114 12:15:33.760094 [Gating] SW mode calibration
5115 12:15:33.766395 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5116 12:15:33.769696 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5117 12:15:33.776054 0 14 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
5118 12:15:33.779734 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5119 12:15:33.783117 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 12:15:33.789570 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 12:15:33.792837 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 12:15:33.796069 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 12:15:33.802877 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 12:15:33.805842 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5125 12:15:33.809628 0 15 0 | B1->B0 | 3131 2e2e | 0 0 | (0 1) (1 1)
5126 12:15:33.815848 0 15 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
5127 12:15:33.818965 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 12:15:33.822619 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 12:15:33.828878 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 12:15:33.832484 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 12:15:33.835708 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 12:15:33.842473 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 12:15:33.845520 1 0 0 | B1->B0 | 2b2b 3b3b | 1 0 | (0 0) (0 0)
5134 12:15:33.849150 1 0 4 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
5135 12:15:33.855299 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 12:15:33.858886 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 12:15:33.861967 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 12:15:33.869191 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 12:15:33.872307 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 12:15:33.875374 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5141 12:15:33.882211 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5142 12:15:33.885614 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5143 12:15:33.888678 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 12:15:33.895406 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 12:15:33.898497 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 12:15:33.901772 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 12:15:33.908279 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 12:15:33.911539 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 12:15:33.914830 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 12:15:33.921432 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 12:15:33.924774 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 12:15:33.928367 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 12:15:33.934816 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 12:15:33.938129 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 12:15:33.941354 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 12:15:33.945009 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5157 12:15:33.951742 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5158 12:15:33.954519 Total UI for P1: 0, mck2ui 16
5159 12:15:33.958369 best dqsien dly found for B0: ( 1, 2, 28)
5160 12:15:33.961192 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5161 12:15:33.964668 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 12:15:33.967874 Total UI for P1: 0, mck2ui 16
5163 12:15:33.971153 best dqsien dly found for B1: ( 1, 3, 4)
5164 12:15:33.974320 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5165 12:15:33.981395 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5166 12:15:33.981939
5167 12:15:33.984477 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5168 12:15:33.988102 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5169 12:15:33.991004 [Gating] SW calibration Done
5170 12:15:33.991512 ==
5171 12:15:33.994420 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 12:15:33.997643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 12:15:33.998151 ==
5174 12:15:34.000833 RX Vref Scan: 0
5175 12:15:34.001336
5176 12:15:34.001715 RX Vref 0 -> 0, step: 1
5177 12:15:34.002025
5178 12:15:34.004322 RX Delay -80 -> 252, step: 8
5179 12:15:34.007598 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5180 12:15:34.010728 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5181 12:15:34.017657 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5182 12:15:34.020596 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5183 12:15:34.024007 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5184 12:15:34.026950 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5185 12:15:34.030490 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5186 12:15:34.033627 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5187 12:15:34.040950 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5188 12:15:34.043758 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5189 12:15:34.047301 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5190 12:15:34.050336 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5191 12:15:34.053988 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5192 12:15:34.060438 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5193 12:15:34.063753 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5194 12:15:34.067090 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5195 12:15:34.067510 ==
5196 12:15:34.070119 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 12:15:34.073665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 12:15:34.076966 ==
5199 12:15:34.077506 DQS Delay:
5200 12:15:34.077846 DQS0 = 0, DQS1 = 0
5201 12:15:34.079956 DQM Delay:
5202 12:15:34.080371 DQM0 = 95, DQM1 = 83
5203 12:15:34.085226 DQ Delay:
5204 12:15:34.085817 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =95
5205 12:15:34.086497 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5206 12:15:34.089976 DQ8 =79, DQ9 =67, DQ10 =83, DQ11 =79
5207 12:15:34.093675 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5208 12:15:34.096590
5209 12:15:34.097128
5210 12:15:34.097465 ==
5211 12:15:34.100064 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 12:15:34.103446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 12:15:34.103961 ==
5214 12:15:34.104293
5215 12:15:34.104599
5216 12:15:34.106416 TX Vref Scan disable
5217 12:15:34.106833 == TX Byte 0 ==
5218 12:15:34.112950 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5219 12:15:34.116384 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5220 12:15:34.116904 == TX Byte 1 ==
5221 12:15:34.123010 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5222 12:15:34.126150 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5223 12:15:34.126567 ==
5224 12:15:34.129988 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 12:15:34.132678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 12:15:34.133098 ==
5227 12:15:34.133428
5228 12:15:34.133841
5229 12:15:34.136013 TX Vref Scan disable
5230 12:15:34.139637 == TX Byte 0 ==
5231 12:15:34.142527 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5232 12:15:34.145926 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5233 12:15:34.149366 == TX Byte 1 ==
5234 12:15:34.153006 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5235 12:15:34.156234 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5236 12:15:34.159076
5237 12:15:34.159495 [DATLAT]
5238 12:15:34.159824 Freq=933, CH0 RK0
5239 12:15:34.160132
5240 12:15:34.162709 DATLAT Default: 0xd
5241 12:15:34.163226 0, 0xFFFF, sum = 0
5242 12:15:34.165872 1, 0xFFFF, sum = 0
5243 12:15:34.166391 2, 0xFFFF, sum = 0
5244 12:15:34.169280 3, 0xFFFF, sum = 0
5245 12:15:34.169836 4, 0xFFFF, sum = 0
5246 12:15:34.172838 5, 0xFFFF, sum = 0
5247 12:15:34.175717 6, 0xFFFF, sum = 0
5248 12:15:34.176157 7, 0xFFFF, sum = 0
5249 12:15:34.179220 8, 0xFFFF, sum = 0
5250 12:15:34.179642 9, 0xFFFF, sum = 0
5251 12:15:34.182795 10, 0x0, sum = 1
5252 12:15:34.183316 11, 0x0, sum = 2
5253 12:15:34.183654 12, 0x0, sum = 3
5254 12:15:34.185901 13, 0x0, sum = 4
5255 12:15:34.186419 best_step = 11
5256 12:15:34.186746
5257 12:15:34.188760 ==
5258 12:15:34.189177 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 12:15:34.195904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 12:15:34.196447 ==
5261 12:15:34.196792 RX Vref Scan: 1
5262 12:15:34.197110
5263 12:15:34.199271 RX Vref 0 -> 0, step: 1
5264 12:15:34.199784
5265 12:15:34.202391 RX Delay -77 -> 252, step: 4
5266 12:15:34.202900
5267 12:15:34.205879 Set Vref, RX VrefLevel [Byte0]: 57
5268 12:15:34.209105 [Byte1]: 52
5269 12:15:34.209653
5270 12:15:34.212055 Final RX Vref Byte 0 = 57 to rank0
5271 12:15:34.215702 Final RX Vref Byte 1 = 52 to rank0
5272 12:15:34.218863 Final RX Vref Byte 0 = 57 to rank1
5273 12:15:34.222120 Final RX Vref Byte 1 = 52 to rank1==
5274 12:15:34.225660 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 12:15:34.228699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 12:15:34.232023 ==
5277 12:15:34.232435 DQS Delay:
5278 12:15:34.232756 DQS0 = 0, DQS1 = 0
5279 12:15:34.235450 DQM Delay:
5280 12:15:34.235961 DQM0 = 95, DQM1 = 84
5281 12:15:34.238792 DQ Delay:
5282 12:15:34.241877 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =94
5283 12:15:34.245252 DQ4 =98, DQ5 =82, DQ6 =102, DQ7 =106
5284 12:15:34.245699 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =76
5285 12:15:34.251673 DQ12 =88, DQ13 =90, DQ14 =94, DQ15 =90
5286 12:15:34.252211
5287 12:15:34.252539
5288 12:15:34.258232 [DQSOSCAuto] RK0, (LSB)MR18= 0x1716, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5289 12:15:34.261881 CH0 RK0: MR19=505, MR18=1716
5290 12:15:34.268151 CH0_RK0: MR19=0x505, MR18=0x1716, DQSOSC=414, MR23=63, INC=63, DEC=42
5291 12:15:34.268651
5292 12:15:34.271319 ----->DramcWriteLeveling(PI) begin...
5293 12:15:34.271728 ==
5294 12:15:34.274895 Dram Type= 6, Freq= 0, CH_0, rank 1
5295 12:15:34.278224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 12:15:34.278633 ==
5297 12:15:34.281524 Write leveling (Byte 0): 33 => 33
5298 12:15:34.284660 Write leveling (Byte 1): 29 => 29
5299 12:15:34.288181 DramcWriteLeveling(PI) end<-----
5300 12:15:34.288584
5301 12:15:34.288901 ==
5302 12:15:34.291453 Dram Type= 6, Freq= 0, CH_0, rank 1
5303 12:15:34.294720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 12:15:34.295230 ==
5305 12:15:34.297815 [Gating] SW mode calibration
5306 12:15:34.304942 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5307 12:15:34.311128 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5308 12:15:34.314407 0 14 0 | B1->B0 | 2626 3434 | 1 1 | (1 1) (0 0)
5309 12:15:34.321001 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 12:15:34.324207 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 12:15:34.327631 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 12:15:34.334341 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 12:15:34.337362 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 12:15:34.340710 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5315 12:15:34.347851 0 14 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 1)
5316 12:15:34.350790 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5317 12:15:34.353957 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 12:15:34.360635 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 12:15:34.364069 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 12:15:34.367526 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 12:15:34.374094 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 12:15:34.377366 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 12:15:34.380845 0 15 28 | B1->B0 | 2626 3f3f | 0 0 | (0 0) (0 0)
5324 12:15:34.387636 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5325 12:15:34.390401 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 12:15:34.394080 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 12:15:34.397051 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 12:15:34.403872 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 12:15:34.407170 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 12:15:34.414034 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 12:15:34.417421 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5332 12:15:34.420482 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5333 12:15:34.423528 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 12:15:34.430165 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 12:15:34.433403 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 12:15:34.436657 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 12:15:34.443524 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 12:15:34.447092 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 12:15:34.450021 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 12:15:34.456689 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 12:15:34.460097 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 12:15:34.463205 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 12:15:34.469951 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 12:15:34.473134 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 12:15:34.476950 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 12:15:34.483184 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5347 12:15:34.487080 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5348 12:15:34.490100 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5349 12:15:34.493307 Total UI for P1: 0, mck2ui 16
5350 12:15:34.496910 best dqsien dly found for B0: ( 1, 2, 26)
5351 12:15:34.503132 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 12:15:34.503579 Total UI for P1: 0, mck2ui 16
5353 12:15:34.509798 best dqsien dly found for B1: ( 1, 3, 0)
5354 12:15:34.513294 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5355 12:15:34.516233 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5356 12:15:34.516674
5357 12:15:34.520194 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5358 12:15:34.523145 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5359 12:15:34.526309 [Gating] SW calibration Done
5360 12:15:34.526792 ==
5361 12:15:34.529797 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 12:15:34.533314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 12:15:34.533885 ==
5364 12:15:34.536229 RX Vref Scan: 0
5365 12:15:34.536647
5366 12:15:34.536975 RX Vref 0 -> 0, step: 1
5367 12:15:34.537282
5368 12:15:34.539611 RX Delay -80 -> 252, step: 8
5369 12:15:34.542649 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5370 12:15:34.549617 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5371 12:15:34.552912 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5372 12:15:34.556119 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5373 12:15:34.559423 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5374 12:15:34.562526 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5375 12:15:34.569227 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5376 12:15:34.572501 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5377 12:15:34.576263 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5378 12:15:34.579176 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5379 12:15:34.582885 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5380 12:15:34.589429 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5381 12:15:34.592585 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5382 12:15:34.596051 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5383 12:15:34.599236 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5384 12:15:34.602371 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5385 12:15:34.602887 ==
5386 12:15:34.605765 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 12:15:34.612312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 12:15:34.612827 ==
5389 12:15:34.613160 DQS Delay:
5390 12:15:34.615807 DQS0 = 0, DQS1 = 0
5391 12:15:34.616322 DQM Delay:
5392 12:15:34.616739 DQM0 = 92, DQM1 = 83
5393 12:15:34.618688 DQ Delay:
5394 12:15:34.622360 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5395 12:15:34.625577 DQ4 =91, DQ5 =79, DQ6 =99, DQ7 =103
5396 12:15:34.629056 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =79
5397 12:15:34.631980 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5398 12:15:34.632401
5399 12:15:34.632729
5400 12:15:34.633033 ==
5401 12:15:34.635772 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 12:15:34.638621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 12:15:34.639044 ==
5404 12:15:34.639373
5405 12:15:34.639679
5406 12:15:34.642279 TX Vref Scan disable
5407 12:15:34.645564 == TX Byte 0 ==
5408 12:15:34.649167 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5409 12:15:34.652231 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5410 12:15:34.655165 == TX Byte 1 ==
5411 12:15:34.658586 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5412 12:15:34.662327 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5413 12:15:34.662835 ==
5414 12:15:34.665628 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 12:15:34.668952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 12:15:34.671712 ==
5417 12:15:34.672129
5418 12:15:34.672455
5419 12:15:34.672763 TX Vref Scan disable
5420 12:15:34.675303 == TX Byte 0 ==
5421 12:15:34.678741 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5422 12:15:34.685418 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5423 12:15:34.686022 == TX Byte 1 ==
5424 12:15:34.688719 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5425 12:15:34.695500 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5426 12:15:34.696017
5427 12:15:34.696346 [DATLAT]
5428 12:15:34.696657 Freq=933, CH0 RK1
5429 12:15:34.696960
5430 12:15:34.698523 DATLAT Default: 0xb
5431 12:15:34.698940 0, 0xFFFF, sum = 0
5432 12:15:34.702077 1, 0xFFFF, sum = 0
5433 12:15:34.705527 2, 0xFFFF, sum = 0
5434 12:15:34.706043 3, 0xFFFF, sum = 0
5435 12:15:34.708660 4, 0xFFFF, sum = 0
5436 12:15:34.709180 5, 0xFFFF, sum = 0
5437 12:15:34.711986 6, 0xFFFF, sum = 0
5438 12:15:34.712502 7, 0xFFFF, sum = 0
5439 12:15:34.715423 8, 0xFFFF, sum = 0
5440 12:15:34.715940 9, 0xFFFF, sum = 0
5441 12:15:34.718161 10, 0x0, sum = 1
5442 12:15:34.718583 11, 0x0, sum = 2
5443 12:15:34.721714 12, 0x0, sum = 3
5444 12:15:34.722227 13, 0x0, sum = 4
5445 12:15:34.722619 best_step = 11
5446 12:15:34.724852
5447 12:15:34.725335 ==
5448 12:15:34.728505 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 12:15:34.731665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 12:15:34.732086 ==
5451 12:15:34.732414 RX Vref Scan: 0
5452 12:15:34.732718
5453 12:15:34.734831 RX Vref 0 -> 0, step: 1
5454 12:15:34.735245
5455 12:15:34.738101 RX Delay -77 -> 252, step: 4
5456 12:15:34.745131 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5457 12:15:34.748287 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5458 12:15:34.751711 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5459 12:15:34.754860 iDelay=199, Bit 3, Center 88 (-5 ~ 182) 188
5460 12:15:34.758401 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5461 12:15:34.761520 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5462 12:15:34.768152 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5463 12:15:34.771684 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5464 12:15:34.774633 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5465 12:15:34.778044 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5466 12:15:34.781467 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5467 12:15:34.788235 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5468 12:15:34.791318 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5469 12:15:34.794457 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5470 12:15:34.798155 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5471 12:15:34.801336 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5472 12:15:34.801886 ==
5473 12:15:34.804722 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 12:15:34.811577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 12:15:34.812098 ==
5476 12:15:34.812433 DQS Delay:
5477 12:15:34.814883 DQS0 = 0, DQS1 = 0
5478 12:15:34.815413 DQM Delay:
5479 12:15:34.815750 DQM0 = 92, DQM1 = 84
5480 12:15:34.817849 DQ Delay:
5481 12:15:34.821562 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =88
5482 12:15:34.824889 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =102
5483 12:15:34.827919 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =76
5484 12:15:34.831580 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =92
5485 12:15:34.832094
5486 12:15:34.832425
5487 12:15:34.837811 [DQSOSCAuto] RK1, (LSB)MR18= 0x3314, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
5488 12:15:34.841224 CH0 RK1: MR19=505, MR18=3314
5489 12:15:34.848215 CH0_RK1: MR19=0x505, MR18=0x3314, DQSOSC=405, MR23=63, INC=66, DEC=44
5490 12:15:34.851055 [RxdqsGatingPostProcess] freq 933
5491 12:15:34.854786 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5492 12:15:34.858086 best DQS0 dly(2T, 0.5T) = (0, 10)
5493 12:15:34.861360 best DQS1 dly(2T, 0.5T) = (0, 11)
5494 12:15:34.864719 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5495 12:15:34.868163 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5496 12:15:34.871126 best DQS0 dly(2T, 0.5T) = (0, 10)
5497 12:15:34.874694 best DQS1 dly(2T, 0.5T) = (0, 11)
5498 12:15:34.878088 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5499 12:15:34.881591 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5500 12:15:34.884294 Pre-setting of DQS Precalculation
5501 12:15:34.887707 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5502 12:15:34.891300 ==
5503 12:15:34.891812 Dram Type= 6, Freq= 0, CH_1, rank 0
5504 12:15:34.897686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 12:15:34.898223 ==
5506 12:15:34.900954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5507 12:15:34.907645 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5508 12:15:34.911538 [CA 0] Center 37 (7~67) winsize 61
5509 12:15:34.914755 [CA 1] Center 37 (7~68) winsize 62
5510 12:15:34.917681 [CA 2] Center 35 (5~65) winsize 61
5511 12:15:34.921047 [CA 3] Center 34 (4~65) winsize 62
5512 12:15:34.924568 [CA 4] Center 35 (5~65) winsize 61
5513 12:15:34.927644 [CA 5] Center 34 (4~64) winsize 61
5514 12:15:34.928064
5515 12:15:34.930962 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5516 12:15:34.931379
5517 12:15:34.934333 [CATrainingPosCal] consider 1 rank data
5518 12:15:34.937634 u2DelayCellTimex100 = 270/100 ps
5519 12:15:34.940703 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5520 12:15:34.947722 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5521 12:15:34.950901 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5522 12:15:34.954418 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5523 12:15:34.957548 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5524 12:15:34.960822 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5525 12:15:34.961326
5526 12:15:34.963883 CA PerBit enable=1, Macro0, CA PI delay=34
5527 12:15:34.964299
5528 12:15:34.967240 [CBTSetCACLKResult] CA Dly = 34
5529 12:15:34.967657 CS Dly: 6 (0~37)
5530 12:15:34.970488 ==
5531 12:15:34.973824 Dram Type= 6, Freq= 0, CH_1, rank 1
5532 12:15:34.977460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 12:15:34.978182 ==
5534 12:15:34.984259 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5535 12:15:34.987538 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5536 12:15:34.991303 [CA 0] Center 37 (8~67) winsize 60
5537 12:15:34.994583 [CA 1] Center 37 (7~68) winsize 62
5538 12:15:34.998096 [CA 2] Center 35 (5~65) winsize 61
5539 12:15:35.000949 [CA 3] Center 34 (4~64) winsize 61
5540 12:15:35.004339 [CA 4] Center 34 (5~64) winsize 60
5541 12:15:35.008019 [CA 5] Center 34 (4~64) winsize 61
5542 12:15:35.008532
5543 12:15:35.011275 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5544 12:15:35.011821
5545 12:15:35.014416 [CATrainingPosCal] consider 2 rank data
5546 12:15:35.017350 u2DelayCellTimex100 = 270/100 ps
5547 12:15:35.021142 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5548 12:15:35.027432 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5549 12:15:35.030754 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5550 12:15:35.034233 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5551 12:15:35.037650 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5552 12:15:35.040844 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5553 12:15:35.041356
5554 12:15:35.044250 CA PerBit enable=1, Macro0, CA PI delay=34
5555 12:15:35.044761
5556 12:15:35.047630 [CBTSetCACLKResult] CA Dly = 34
5557 12:15:35.050960 CS Dly: 6 (0~38)
5558 12:15:35.051469
5559 12:15:35.054035 ----->DramcWriteLeveling(PI) begin...
5560 12:15:35.054556 ==
5561 12:15:35.057430 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 12:15:35.060896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 12:15:35.061422 ==
5564 12:15:35.063759 Write leveling (Byte 0): 24 => 24
5565 12:15:35.067357 Write leveling (Byte 1): 28 => 28
5566 12:15:35.070541 DramcWriteLeveling(PI) end<-----
5567 12:15:35.070959
5568 12:15:35.071289 ==
5569 12:15:35.073595 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 12:15:35.077298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 12:15:35.077908 ==
5572 12:15:35.080612 [Gating] SW mode calibration
5573 12:15:35.087163 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5574 12:15:35.093866 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5575 12:15:35.097275 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5576 12:15:35.100364 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 12:15:35.107146 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 12:15:35.110352 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 12:15:35.113403 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 12:15:35.120366 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 12:15:35.123694 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 12:15:35.126726 0 14 28 | B1->B0 | 2c2c 2929 | 1 0 | (1 0) (1 0)
5583 12:15:35.133840 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
5584 12:15:35.137110 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 12:15:35.139837 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 12:15:35.146526 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 12:15:35.150394 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 12:15:35.153780 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 12:15:35.160119 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 12:15:35.163505 0 15 28 | B1->B0 | 3232 3636 | 0 1 | (1 1) (0 0)
5591 12:15:35.166554 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5592 12:15:35.173626 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 12:15:35.176801 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 12:15:35.180398 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 12:15:35.183054 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 12:15:35.190069 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 12:15:35.193463 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 12:15:35.196523 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5599 12:15:35.203386 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 12:15:35.206540 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 12:15:35.210209 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 12:15:35.216411 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 12:15:35.220051 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 12:15:35.222822 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 12:15:35.229364 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 12:15:35.233030 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 12:15:35.236003 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 12:15:35.242945 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 12:15:35.246122 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 12:15:35.249941 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 12:15:35.256356 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 12:15:35.259410 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 12:15:35.262791 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5614 12:15:35.269313 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5615 12:15:35.272827 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 12:15:35.276379 Total UI for P1: 0, mck2ui 16
5617 12:15:35.279092 best dqsien dly found for B0: ( 1, 2, 26)
5618 12:15:35.282448 Total UI for P1: 0, mck2ui 16
5619 12:15:35.286172 best dqsien dly found for B1: ( 1, 2, 26)
5620 12:15:35.289551 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5621 12:15:35.292260 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5622 12:15:35.292675
5623 12:15:35.295910 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5624 12:15:35.299179 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5625 12:15:35.302465 [Gating] SW calibration Done
5626 12:15:35.302984 ==
5627 12:15:35.306008 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 12:15:35.312464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 12:15:35.312978 ==
5630 12:15:35.313307 RX Vref Scan: 0
5631 12:15:35.313640
5632 12:15:35.315675 RX Vref 0 -> 0, step: 1
5633 12:15:35.316183
5634 12:15:35.318951 RX Delay -80 -> 252, step: 8
5635 12:15:35.322303 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5636 12:15:35.325635 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5637 12:15:35.328507 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5638 12:15:35.332643 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5639 12:15:35.338725 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5640 12:15:35.342245 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5641 12:15:35.345450 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5642 12:15:35.348838 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5643 12:15:35.352393 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5644 12:15:35.355148 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5645 12:15:35.362002 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5646 12:15:35.365412 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5647 12:15:35.368556 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5648 12:15:35.372173 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5649 12:15:35.375534 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5650 12:15:35.381831 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5651 12:15:35.382346 ==
5652 12:15:35.385246 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 12:15:35.388309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 12:15:35.388821 ==
5655 12:15:35.389152 DQS Delay:
5656 12:15:35.391834 DQS0 = 0, DQS1 = 0
5657 12:15:35.392342 DQM Delay:
5658 12:15:35.394910 DQM0 = 94, DQM1 = 86
5659 12:15:35.395330 DQ Delay:
5660 12:15:35.398308 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5661 12:15:35.401668 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5662 12:15:35.404772 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5663 12:15:35.408032 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5664 12:15:35.408538
5665 12:15:35.408863
5666 12:15:35.409168 ==
5667 12:15:35.412017 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 12:15:35.414839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 12:15:35.418183 ==
5670 12:15:35.418669
5671 12:15:35.419005
5672 12:15:35.419311 TX Vref Scan disable
5673 12:15:35.421847 == TX Byte 0 ==
5674 12:15:35.424775 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5675 12:15:35.428122 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5676 12:15:35.431703 == TX Byte 1 ==
5677 12:15:35.434614 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5678 12:15:35.437973 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5679 12:15:35.441303 ==
5680 12:15:35.444922 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 12:15:35.448008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 12:15:35.448524 ==
5683 12:15:35.448856
5684 12:15:35.449162
5685 12:15:35.451498 TX Vref Scan disable
5686 12:15:35.452005 == TX Byte 0 ==
5687 12:15:35.457917 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5688 12:15:35.461140 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5689 12:15:35.461627 == TX Byte 1 ==
5690 12:15:35.468185 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5691 12:15:35.471590 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5692 12:15:35.472102
5693 12:15:35.472433 [DATLAT]
5694 12:15:35.474958 Freq=933, CH1 RK0
5695 12:15:35.475472
5696 12:15:35.475801 DATLAT Default: 0xd
5697 12:15:35.478119 0, 0xFFFF, sum = 0
5698 12:15:35.478638 1, 0xFFFF, sum = 0
5699 12:15:35.481552 2, 0xFFFF, sum = 0
5700 12:15:35.482070 3, 0xFFFF, sum = 0
5701 12:15:35.484544 4, 0xFFFF, sum = 0
5702 12:15:35.484969 5, 0xFFFF, sum = 0
5703 12:15:35.488022 6, 0xFFFF, sum = 0
5704 12:15:35.491025 7, 0xFFFF, sum = 0
5705 12:15:35.491451 8, 0xFFFF, sum = 0
5706 12:15:35.494397 9, 0xFFFF, sum = 0
5707 12:15:35.494841 10, 0x0, sum = 1
5708 12:15:35.495181 11, 0x0, sum = 2
5709 12:15:35.498153 12, 0x0, sum = 3
5710 12:15:35.498674 13, 0x0, sum = 4
5711 12:15:35.500855 best_step = 11
5712 12:15:35.501271
5713 12:15:35.501628 ==
5714 12:15:35.504428 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 12:15:35.507695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 12:15:35.508214 ==
5717 12:15:35.511226 RX Vref Scan: 1
5718 12:15:35.511739
5719 12:15:35.512073 RX Vref 0 -> 0, step: 1
5720 12:15:35.512383
5721 12:15:35.514087 RX Delay -69 -> 252, step: 4
5722 12:15:35.514504
5723 12:15:35.517628 Set Vref, RX VrefLevel [Byte0]: 59
5724 12:15:35.521282 [Byte1]: 54
5725 12:15:35.525330
5726 12:15:35.525889 Final RX Vref Byte 0 = 59 to rank0
5727 12:15:35.528796 Final RX Vref Byte 1 = 54 to rank0
5728 12:15:35.531939 Final RX Vref Byte 0 = 59 to rank1
5729 12:15:35.535456 Final RX Vref Byte 1 = 54 to rank1==
5730 12:15:35.538259 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 12:15:35.544998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 12:15:35.545546 ==
5733 12:15:35.545889 DQS Delay:
5734 12:15:35.548731 DQS0 = 0, DQS1 = 0
5735 12:15:35.549255 DQM Delay:
5736 12:15:35.549637 DQM0 = 97, DQM1 = 89
5737 12:15:35.551625 DQ Delay:
5738 12:15:35.555031 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =94
5739 12:15:35.558296 DQ4 =94, DQ5 =108, DQ6 =106, DQ7 =94
5740 12:15:35.561584 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
5741 12:15:35.564834 DQ12 =96, DQ13 =94, DQ14 =96, DQ15 =94
5742 12:15:35.565250
5743 12:15:35.565622
5744 12:15:35.571641 [DQSOSCAuto] RK0, (LSB)MR18= 0xff08, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5745 12:15:35.574988 CH1 RK0: MR19=405, MR18=FF08
5746 12:15:35.581562 CH1_RK0: MR19=0x405, MR18=0xFF08, DQSOSC=419, MR23=63, INC=61, DEC=41
5747 12:15:35.581981
5748 12:15:35.584950 ----->DramcWriteLeveling(PI) begin...
5749 12:15:35.585372 ==
5750 12:15:35.588092 Dram Type= 6, Freq= 0, CH_1, rank 1
5751 12:15:35.591937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 12:15:35.592452 ==
5753 12:15:35.594758 Write leveling (Byte 0): 25 => 25
5754 12:15:35.598089 Write leveling (Byte 1): 30 => 30
5755 12:15:35.601297 DramcWriteLeveling(PI) end<-----
5756 12:15:35.601778
5757 12:15:35.602116 ==
5758 12:15:35.604909 Dram Type= 6, Freq= 0, CH_1, rank 1
5759 12:15:35.608029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 12:15:35.608447 ==
5761 12:15:35.611389 [Gating] SW mode calibration
5762 12:15:35.618067 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5763 12:15:35.624505 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5764 12:15:35.628242 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5765 12:15:35.634369 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 12:15:35.637949 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 12:15:35.641357 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 12:15:35.647789 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 12:15:35.651369 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 12:15:35.654613 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
5771 12:15:35.661653 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
5772 12:15:35.664256 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 12:15:35.668340 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 12:15:35.674458 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 12:15:35.677608 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 12:15:35.680971 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 12:15:35.687562 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 12:15:35.691288 0 15 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5779 12:15:35.694809 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
5780 12:15:35.697871 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 12:15:35.704769 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 12:15:35.707766 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 12:15:35.711122 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 12:15:35.717550 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 12:15:35.720721 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5786 12:15:35.724269 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5787 12:15:35.730625 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5788 12:15:35.734412 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 12:15:35.737458 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 12:15:35.744156 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 12:15:35.747267 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 12:15:35.751214 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 12:15:35.757356 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 12:15:35.760538 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 12:15:35.763701 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 12:15:35.770793 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 12:15:35.773689 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 12:15:35.777219 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 12:15:35.783813 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 12:15:35.787337 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 12:15:35.790592 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 12:15:35.797149 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5803 12:15:35.800463 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 12:15:35.804059 Total UI for P1: 0, mck2ui 16
5805 12:15:35.807135 best dqsien dly found for B0: ( 1, 2, 24)
5806 12:15:35.810465 Total UI for P1: 0, mck2ui 16
5807 12:15:35.813843 best dqsien dly found for B1: ( 1, 2, 24)
5808 12:15:35.817227 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5809 12:15:35.820460 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5810 12:15:35.820969
5811 12:15:35.823653 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5812 12:15:35.827170 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5813 12:15:35.830189 [Gating] SW calibration Done
5814 12:15:35.830607 ==
5815 12:15:35.833545 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 12:15:35.836933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 12:15:35.840359 ==
5818 12:15:35.840889 RX Vref Scan: 0
5819 12:15:35.841334
5820 12:15:35.843657 RX Vref 0 -> 0, step: 1
5821 12:15:35.844185
5822 12:15:35.846969 RX Delay -80 -> 252, step: 8
5823 12:15:35.850100 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5824 12:15:35.853635 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5825 12:15:35.857147 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5826 12:15:35.860347 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5827 12:15:35.863755 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5828 12:15:35.870026 iDelay=208, Bit 5, Center 99 (0 ~ 199) 200
5829 12:15:35.873630 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5830 12:15:35.876999 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5831 12:15:35.880148 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5832 12:15:35.883134 iDelay=208, Bit 9, Center 79 (-24 ~ 183) 208
5833 12:15:35.890294 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5834 12:15:35.893269 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5835 12:15:35.896730 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5836 12:15:35.900121 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5837 12:15:35.903314 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5838 12:15:35.906898 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5839 12:15:35.907409 ==
5840 12:15:35.910106 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 12:15:35.916756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 12:15:35.917270 ==
5843 12:15:35.917652 DQS Delay:
5844 12:15:35.920163 DQS0 = 0, DQS1 = 0
5845 12:15:35.920672 DQM Delay:
5846 12:15:35.923578 DQM0 = 93, DQM1 = 90
5847 12:15:35.924090 DQ Delay:
5848 12:15:35.926929 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5849 12:15:35.929868 DQ4 =91, DQ5 =99, DQ6 =103, DQ7 =91
5850 12:15:35.933313 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5851 12:15:35.936495 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5852 12:15:35.936911
5853 12:15:35.937237
5854 12:15:35.937603 ==
5855 12:15:35.939620 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 12:15:35.943267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 12:15:35.943686 ==
5858 12:15:35.944015
5859 12:15:35.944318
5860 12:15:35.946888 TX Vref Scan disable
5861 12:15:35.949675 == TX Byte 0 ==
5862 12:15:35.953225 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5863 12:15:35.956685 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5864 12:15:35.959779 == TX Byte 1 ==
5865 12:15:35.963171 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5866 12:15:35.966365 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5867 12:15:35.966784 ==
5868 12:15:35.969309 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 12:15:35.973356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 12:15:35.976318 ==
5871 12:15:35.976849
5872 12:15:35.977242
5873 12:15:35.977602 TX Vref Scan disable
5874 12:15:35.979721 == TX Byte 0 ==
5875 12:15:35.983499 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5876 12:15:35.990061 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5877 12:15:35.990573 == TX Byte 1 ==
5878 12:15:35.992943 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5879 12:15:35.999850 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5880 12:15:36.000416
5881 12:15:36.000755 [DATLAT]
5882 12:15:36.001122 Freq=933, CH1 RK1
5883 12:15:36.001434
5884 12:15:36.002900 DATLAT Default: 0xb
5885 12:15:36.003317 0, 0xFFFF, sum = 0
5886 12:15:36.006149 1, 0xFFFF, sum = 0
5887 12:15:36.010007 2, 0xFFFF, sum = 0
5888 12:15:36.010527 3, 0xFFFF, sum = 0
5889 12:15:36.013200 4, 0xFFFF, sum = 0
5890 12:15:36.013756 5, 0xFFFF, sum = 0
5891 12:15:36.016089 6, 0xFFFF, sum = 0
5892 12:15:36.016636 7, 0xFFFF, sum = 0
5893 12:15:36.019494 8, 0xFFFF, sum = 0
5894 12:15:36.019985 9, 0xFFFF, sum = 0
5895 12:15:36.023044 10, 0x0, sum = 1
5896 12:15:36.023559 11, 0x0, sum = 2
5897 12:15:36.026064 12, 0x0, sum = 3
5898 12:15:36.026490 13, 0x0, sum = 4
5899 12:15:36.026824 best_step = 11
5900 12:15:36.029345
5901 12:15:36.029787 ==
5902 12:15:36.032665 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 12:15:36.036547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 12:15:36.037061 ==
5905 12:15:36.037394 RX Vref Scan: 0
5906 12:15:36.037767
5907 12:15:36.039529 RX Vref 0 -> 0, step: 1
5908 12:15:36.040039
5909 12:15:36.042608 RX Delay -69 -> 252, step: 4
5910 12:15:36.049558 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5911 12:15:36.052802 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5912 12:15:36.056154 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5913 12:15:36.059523 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5914 12:15:36.062499 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5915 12:15:36.066100 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5916 12:15:36.072606 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5917 12:15:36.076247 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5918 12:15:36.079120 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5919 12:15:36.082697 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5920 12:15:36.086034 iDelay=203, Bit 10, Center 92 (-5 ~ 190) 196
5921 12:15:36.092758 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5922 12:15:36.095977 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5923 12:15:36.099468 iDelay=203, Bit 13, Center 100 (7 ~ 194) 188
5924 12:15:36.102207 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5925 12:15:36.105973 iDelay=203, Bit 15, Center 100 (7 ~ 194) 188
5926 12:15:36.106481 ==
5927 12:15:36.109277 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 12:15:36.115811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 12:15:36.116341 ==
5930 12:15:36.116676 DQS Delay:
5931 12:15:36.118892 DQS0 = 0, DQS1 = 0
5932 12:15:36.119402 DQM Delay:
5933 12:15:36.122722 DQM0 = 91, DQM1 = 91
5934 12:15:36.123231 DQ Delay:
5935 12:15:36.125687 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5936 12:15:36.129082 DQ4 =88, DQ5 =102, DQ6 =104, DQ7 =88
5937 12:15:36.132188 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =82
5938 12:15:36.135250 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =100
5939 12:15:36.135663
5940 12:15:36.135984
5941 12:15:36.142075 [DQSOSCAuto] RK1, (LSB)MR18= 0x1226, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 416 ps
5942 12:15:36.145642 CH1 RK1: MR19=505, MR18=1226
5943 12:15:36.152484 CH1_RK1: MR19=0x505, MR18=0x1226, DQSOSC=409, MR23=63, INC=64, DEC=43
5944 12:15:36.155566 [RxdqsGatingPostProcess] freq 933
5945 12:15:36.162597 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5946 12:15:36.165359 best DQS0 dly(2T, 0.5T) = (0, 10)
5947 12:15:36.165827 best DQS1 dly(2T, 0.5T) = (0, 10)
5948 12:15:36.168799 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5949 12:15:36.171947 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5950 12:15:36.175396 best DQS0 dly(2T, 0.5T) = (0, 10)
5951 12:15:36.178599 best DQS1 dly(2T, 0.5T) = (0, 10)
5952 12:15:36.181968 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5953 12:15:36.185170 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5954 12:15:36.188763 Pre-setting of DQS Precalculation
5955 12:15:36.195213 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5956 12:15:36.201604 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5957 12:15:36.208206 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5958 12:15:36.208699
5959 12:15:36.209028
5960 12:15:36.211920 [Calibration Summary] 1866 Mbps
5961 12:15:36.212427 CH 0, Rank 0
5962 12:15:36.215366 SW Impedance : PASS
5963 12:15:36.218389 DUTY Scan : NO K
5964 12:15:36.218873 ZQ Calibration : PASS
5965 12:15:36.221565 Jitter Meter : NO K
5966 12:15:36.225072 CBT Training : PASS
5967 12:15:36.225634 Write leveling : PASS
5968 12:15:36.228467 RX DQS gating : PASS
5969 12:15:36.231763 RX DQ/DQS(RDDQC) : PASS
5970 12:15:36.232265 TX DQ/DQS : PASS
5971 12:15:36.234911 RX DATLAT : PASS
5972 12:15:36.235323 RX DQ/DQS(Engine): PASS
5973 12:15:36.238054 TX OE : NO K
5974 12:15:36.238466 All Pass.
5975 12:15:36.238793
5976 12:15:36.241444 CH 0, Rank 1
5977 12:15:36.244898 SW Impedance : PASS
5978 12:15:36.245412 DUTY Scan : NO K
5979 12:15:36.248265 ZQ Calibration : PASS
5980 12:15:36.248779 Jitter Meter : NO K
5981 12:15:36.251520 CBT Training : PASS
5982 12:15:36.254647 Write leveling : PASS
5983 12:15:36.255065 RX DQS gating : PASS
5984 12:15:36.258436 RX DQ/DQS(RDDQC) : PASS
5985 12:15:36.261368 TX DQ/DQS : PASS
5986 12:15:36.261924 RX DATLAT : PASS
5987 12:15:36.264713 RX DQ/DQS(Engine): PASS
5988 12:15:36.267727 TX OE : NO K
5989 12:15:36.268238 All Pass.
5990 12:15:36.268571
5991 12:15:36.268879 CH 1, Rank 0
5992 12:15:36.271166 SW Impedance : PASS
5993 12:15:36.274288 DUTY Scan : NO K
5994 12:15:36.274703 ZQ Calibration : PASS
5995 12:15:36.278022 Jitter Meter : NO K
5996 12:15:36.281607 CBT Training : PASS
5997 12:15:36.282112 Write leveling : PASS
5998 12:15:36.284560 RX DQS gating : PASS
5999 12:15:36.287995 RX DQ/DQS(RDDQC) : PASS
6000 12:15:36.288502 TX DQ/DQS : PASS
6001 12:15:36.291392 RX DATLAT : PASS
6002 12:15:36.294539 RX DQ/DQS(Engine): PASS
6003 12:15:36.295048 TX OE : NO K
6004 12:15:36.295383 All Pass.
6005 12:15:36.298011
6006 12:15:36.298520 CH 1, Rank 1
6007 12:15:36.300896 SW Impedance : PASS
6008 12:15:36.301307 DUTY Scan : NO K
6009 12:15:36.304314 ZQ Calibration : PASS
6010 12:15:36.304720 Jitter Meter : NO K
6011 12:15:36.307857 CBT Training : PASS
6012 12:15:36.310923 Write leveling : PASS
6013 12:15:36.311428 RX DQS gating : PASS
6014 12:15:36.314376 RX DQ/DQS(RDDQC) : PASS
6015 12:15:36.317730 TX DQ/DQS : PASS
6016 12:15:36.318235 RX DATLAT : PASS
6017 12:15:36.320683 RX DQ/DQS(Engine): PASS
6018 12:15:36.324433 TX OE : NO K
6019 12:15:36.324940 All Pass.
6020 12:15:36.325267
6021 12:15:36.327794 DramC Write-DBI off
6022 12:15:36.328323 PER_BANK_REFRESH: Hybrid Mode
6023 12:15:36.330951 TX_TRACKING: ON
6024 12:15:36.340659 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6025 12:15:36.343931 [FAST_K] Save calibration result to emmc
6026 12:15:36.347341 dramc_set_vcore_voltage set vcore to 650000
6027 12:15:36.347849 Read voltage for 400, 6
6028 12:15:36.350438 Vio18 = 0
6029 12:15:36.350848 Vcore = 650000
6030 12:15:36.351173 Vdram = 0
6031 12:15:36.353780 Vddq = 0
6032 12:15:36.354194 Vmddr = 0
6033 12:15:36.360741 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6034 12:15:36.364123 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6035 12:15:36.367202 MEM_TYPE=3, freq_sel=20
6036 12:15:36.370479 sv_algorithm_assistance_LP4_800
6037 12:15:36.373690 ============ PULL DRAM RESETB DOWN ============
6038 12:15:36.377172 ========== PULL DRAM RESETB DOWN end =========
6039 12:15:36.383448 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6040 12:15:36.387217 ===================================
6041 12:15:36.387731 LPDDR4 DRAM CONFIGURATION
6042 12:15:36.390385 ===================================
6043 12:15:36.393670 EX_ROW_EN[0] = 0x0
6044 12:15:36.397138 EX_ROW_EN[1] = 0x0
6045 12:15:36.397688 LP4Y_EN = 0x0
6046 12:15:36.400373 WORK_FSP = 0x0
6047 12:15:36.400883 WL = 0x2
6048 12:15:36.403782 RL = 0x2
6049 12:15:36.404290 BL = 0x2
6050 12:15:36.406803 RPST = 0x0
6051 12:15:36.407213 RD_PRE = 0x0
6052 12:15:36.410310 WR_PRE = 0x1
6053 12:15:36.410822 WR_PST = 0x0
6054 12:15:36.413681 DBI_WR = 0x0
6055 12:15:36.414193 DBI_RD = 0x0
6056 12:15:36.416762 OTF = 0x1
6057 12:15:36.420118 ===================================
6058 12:15:36.423485 ===================================
6059 12:15:36.424000 ANA top config
6060 12:15:36.426409 ===================================
6061 12:15:36.430045 DLL_ASYNC_EN = 0
6062 12:15:36.432884 ALL_SLAVE_EN = 1
6063 12:15:36.436203 NEW_RANK_MODE = 1
6064 12:15:36.436623 DLL_IDLE_MODE = 1
6065 12:15:36.439830 LP45_APHY_COMB_EN = 1
6066 12:15:36.442910 TX_ODT_DIS = 1
6067 12:15:36.446185 NEW_8X_MODE = 1
6068 12:15:36.449934 ===================================
6069 12:15:36.453128 ===================================
6070 12:15:36.453589 data_rate = 800
6071 12:15:36.456376 CKR = 1
6072 12:15:36.460038 DQ_P2S_RATIO = 4
6073 12:15:36.462905 ===================================
6074 12:15:36.466362 CA_P2S_RATIO = 4
6075 12:15:36.469599 DQ_CA_OPEN = 0
6076 12:15:36.473228 DQ_SEMI_OPEN = 1
6077 12:15:36.476283 CA_SEMI_OPEN = 1
6078 12:15:36.476798 CA_FULL_RATE = 0
6079 12:15:36.479372 DQ_CKDIV4_EN = 0
6080 12:15:36.482954 CA_CKDIV4_EN = 1
6081 12:15:36.485947 CA_PREDIV_EN = 0
6082 12:15:36.489413 PH8_DLY = 0
6083 12:15:36.492481 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6084 12:15:36.492988 DQ_AAMCK_DIV = 0
6085 12:15:36.496211 CA_AAMCK_DIV = 0
6086 12:15:36.499571 CA_ADMCK_DIV = 4
6087 12:15:36.502626 DQ_TRACK_CA_EN = 0
6088 12:15:36.506135 CA_PICK = 800
6089 12:15:36.509363 CA_MCKIO = 400
6090 12:15:36.512846 MCKIO_SEMI = 400
6091 12:15:36.513354 PLL_FREQ = 3016
6092 12:15:36.516145 DQ_UI_PI_RATIO = 32
6093 12:15:36.518951 CA_UI_PI_RATIO = 32
6094 12:15:36.522435 ===================================
6095 12:15:36.526157 ===================================
6096 12:15:36.529212 memory_type:LPDDR4
6097 12:15:36.532447 GP_NUM : 10
6098 12:15:36.532974 SRAM_EN : 1
6099 12:15:36.535443 MD32_EN : 0
6100 12:15:36.538685 ===================================
6101 12:15:36.539107 [ANA_INIT] >>>>>>>>>>>>>>
6102 12:15:36.542187 <<<<<< [CONFIGURE PHASE]: ANA_TX
6103 12:15:36.545538 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6104 12:15:36.548969 ===================================
6105 12:15:36.552108 data_rate = 800,PCW = 0X7400
6106 12:15:36.555406 ===================================
6107 12:15:36.558684 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6108 12:15:36.565506 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6109 12:15:36.575186 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6110 12:15:36.581778 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6111 12:15:36.584986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6112 12:15:36.588247 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6113 12:15:36.588754 [ANA_INIT] flow start
6114 12:15:36.591835 [ANA_INIT] PLL >>>>>>>>
6115 12:15:36.595446 [ANA_INIT] PLL <<<<<<<<
6116 12:15:36.595957 [ANA_INIT] MIDPI >>>>>>>>
6117 12:15:36.598232 [ANA_INIT] MIDPI <<<<<<<<
6118 12:15:36.602063 [ANA_INIT] DLL >>>>>>>>
6119 12:15:36.602578 [ANA_INIT] flow end
6120 12:15:36.608286 ============ LP4 DIFF to SE enter ============
6121 12:15:36.611684 ============ LP4 DIFF to SE exit ============
6122 12:15:36.615190 [ANA_INIT] <<<<<<<<<<<<<
6123 12:15:36.618437 [Flow] Enable top DCM control >>>>>
6124 12:15:36.621953 [Flow] Enable top DCM control <<<<<
6125 12:15:36.624931 Enable DLL master slave shuffle
6126 12:15:36.628309 ==============================================================
6127 12:15:36.631287 Gating Mode config
6128 12:15:36.634793 ==============================================================
6129 12:15:36.638054 Config description:
6130 12:15:36.648145 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6131 12:15:36.654397 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6132 12:15:36.657762 SELPH_MODE 0: By rank 1: By Phase
6133 12:15:36.664554 ==============================================================
6134 12:15:36.667978 GAT_TRACK_EN = 0
6135 12:15:36.671430 RX_GATING_MODE = 2
6136 12:15:36.674676 RX_GATING_TRACK_MODE = 2
6137 12:15:36.677688 SELPH_MODE = 1
6138 12:15:36.681221 PICG_EARLY_EN = 1
6139 12:15:36.681678 VALID_LAT_VALUE = 1
6140 12:15:36.687850 ==============================================================
6141 12:15:36.691155 Enter into Gating configuration >>>>
6142 12:15:36.694553 Exit from Gating configuration <<<<
6143 12:15:36.697839 Enter into DVFS_PRE_config >>>>>
6144 12:15:36.707782 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6145 12:15:36.711199 Exit from DVFS_PRE_config <<<<<
6146 12:15:36.714434 Enter into PICG configuration >>>>
6147 12:15:36.717705 Exit from PICG configuration <<<<
6148 12:15:36.721058 [RX_INPUT] configuration >>>>>
6149 12:15:36.724441 [RX_INPUT] configuration <<<<<
6150 12:15:36.727874 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6151 12:15:36.734357 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6152 12:15:36.741085 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6153 12:15:36.747397 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6154 12:15:36.754409 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6155 12:15:36.760573 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6156 12:15:36.764067 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6157 12:15:36.767612 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6158 12:15:36.770610 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6159 12:15:36.777337 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6160 12:15:36.780825 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6161 12:15:36.783755 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6162 12:15:36.787404 ===================================
6163 12:15:36.790741 LPDDR4 DRAM CONFIGURATION
6164 12:15:36.794066 ===================================
6165 12:15:36.794584 EX_ROW_EN[0] = 0x0
6166 12:15:36.797362 EX_ROW_EN[1] = 0x0
6167 12:15:36.800527 LP4Y_EN = 0x0
6168 12:15:36.800940 WORK_FSP = 0x0
6169 12:15:36.803682 WL = 0x2
6170 12:15:36.804094 RL = 0x2
6171 12:15:36.807267 BL = 0x2
6172 12:15:36.807784 RPST = 0x0
6173 12:15:36.810221 RD_PRE = 0x0
6174 12:15:36.810631 WR_PRE = 0x1
6175 12:15:36.813613 WR_PST = 0x0
6176 12:15:36.814125 DBI_WR = 0x0
6177 12:15:36.816942 DBI_RD = 0x0
6178 12:15:36.817459 OTF = 0x1
6179 12:15:36.820335 ===================================
6180 12:15:36.823638 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6181 12:15:36.830469 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6182 12:15:36.833569 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6183 12:15:36.837071 ===================================
6184 12:15:36.840308 LPDDR4 DRAM CONFIGURATION
6185 12:15:36.843429 ===================================
6186 12:15:36.843837 EX_ROW_EN[0] = 0x10
6187 12:15:36.847115 EX_ROW_EN[1] = 0x0
6188 12:15:36.847618 LP4Y_EN = 0x0
6189 12:15:36.849900 WORK_FSP = 0x0
6190 12:15:36.853320 WL = 0x2
6191 12:15:36.853768 RL = 0x2
6192 12:15:36.856920 BL = 0x2
6193 12:15:36.857422 RPST = 0x0
6194 12:15:36.860338 RD_PRE = 0x0
6195 12:15:36.860840 WR_PRE = 0x1
6196 12:15:36.863693 WR_PST = 0x0
6197 12:15:36.864199 DBI_WR = 0x0
6198 12:15:36.866365 DBI_RD = 0x0
6199 12:15:36.866773 OTF = 0x1
6200 12:15:36.870011 ===================================
6201 12:15:36.876683 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6202 12:15:36.881050 nWR fixed to 30
6203 12:15:36.884345 [ModeRegInit_LP4] CH0 RK0
6204 12:15:36.884849 [ModeRegInit_LP4] CH0 RK1
6205 12:15:36.887348 [ModeRegInit_LP4] CH1 RK0
6206 12:15:36.890504 [ModeRegInit_LP4] CH1 RK1
6207 12:15:36.891007 match AC timing 19
6208 12:15:36.897576 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6209 12:15:36.900879 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6210 12:15:36.903898 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6211 12:15:36.910756 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6212 12:15:36.913800 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6213 12:15:36.914317 ==
6214 12:15:36.917391 Dram Type= 6, Freq= 0, CH_0, rank 0
6215 12:15:36.920834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6216 12:15:36.921349 ==
6217 12:15:36.927034 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6218 12:15:36.933833 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6219 12:15:36.936941 [CA 0] Center 36 (8~64) winsize 57
6220 12:15:36.940063 [CA 1] Center 36 (8~64) winsize 57
6221 12:15:36.943519 [CA 2] Center 36 (8~64) winsize 57
6222 12:15:36.947103 [CA 3] Center 36 (8~64) winsize 57
6223 12:15:36.949808 [CA 4] Center 36 (8~64) winsize 57
6224 12:15:36.950221 [CA 5] Center 36 (8~64) winsize 57
6225 12:15:36.953421
6226 12:15:36.956702 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6227 12:15:36.957206
6228 12:15:36.959818 [CATrainingPosCal] consider 1 rank data
6229 12:15:36.963619 u2DelayCellTimex100 = 270/100 ps
6230 12:15:36.966351 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 12:15:36.970108 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 12:15:36.973157 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 12:15:36.976697 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 12:15:36.979935 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 12:15:36.983100 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 12:15:36.983512
6237 12:15:36.986429 CA PerBit enable=1, Macro0, CA PI delay=36
6238 12:15:36.986941
6239 12:15:36.990056 [CBTSetCACLKResult] CA Dly = 36
6240 12:15:36.993414 CS Dly: 1 (0~32)
6241 12:15:36.993953 ==
6242 12:15:36.996532 Dram Type= 6, Freq= 0, CH_0, rank 1
6243 12:15:36.999599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6244 12:15:37.000017 ==
6245 12:15:37.006453 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6246 12:15:37.012959 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6247 12:15:37.016415 [CA 0] Center 36 (8~64) winsize 57
6248 12:15:37.019353 [CA 1] Center 36 (8~64) winsize 57
6249 12:15:37.019779 [CA 2] Center 36 (8~64) winsize 57
6250 12:15:37.022691 [CA 3] Center 36 (8~64) winsize 57
6251 12:15:37.026302 [CA 4] Center 36 (8~64) winsize 57
6252 12:15:37.030000 [CA 5] Center 36 (8~64) winsize 57
6253 12:15:37.030502
6254 12:15:37.032841 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6255 12:15:37.033374
6256 12:15:37.039318 [CATrainingPosCal] consider 2 rank data
6257 12:15:37.039852 u2DelayCellTimex100 = 270/100 ps
6258 12:15:37.045921 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 12:15:37.049277 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 12:15:37.052821 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 12:15:37.055919 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 12:15:37.059352 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 12:15:37.062607 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 12:15:37.063020
6265 12:15:37.066326 CA PerBit enable=1, Macro0, CA PI delay=36
6266 12:15:37.066838
6267 12:15:37.069007 [CBTSetCACLKResult] CA Dly = 36
6268 12:15:37.072405 CS Dly: 1 (0~32)
6269 12:15:37.072817
6270 12:15:37.075833 ----->DramcWriteLeveling(PI) begin...
6271 12:15:37.076348 ==
6272 12:15:37.079266 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 12:15:37.082237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 12:15:37.082653 ==
6275 12:15:37.085390 Write leveling (Byte 0): 40 => 8
6276 12:15:37.089152 Write leveling (Byte 1): 40 => 8
6277 12:15:37.092850 DramcWriteLeveling(PI) end<-----
6278 12:15:37.093356
6279 12:15:37.093724 ==
6280 12:15:37.095692 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 12:15:37.099029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 12:15:37.099458 ==
6283 12:15:37.102081 [Gating] SW mode calibration
6284 12:15:37.108667 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6285 12:15:37.115591 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6286 12:15:37.118723 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6287 12:15:37.122332 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6288 12:15:37.128841 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 12:15:37.132030 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6290 12:15:37.135628 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 12:15:37.141915 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 12:15:37.145074 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 12:15:37.148357 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 12:15:37.154932 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 12:15:37.155348 Total UI for P1: 0, mck2ui 16
6296 12:15:37.161609 best dqsien dly found for B0: ( 0, 14, 24)
6297 12:15:37.162026 Total UI for P1: 0, mck2ui 16
6298 12:15:37.168807 best dqsien dly found for B1: ( 0, 14, 24)
6299 12:15:37.171812 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6300 12:15:37.175006 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6301 12:15:37.175464
6302 12:15:37.178633 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6303 12:15:37.181770 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6304 12:15:37.185006 [Gating] SW calibration Done
6305 12:15:37.185555 ==
6306 12:15:37.188595 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 12:15:37.191857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 12:15:37.192366 ==
6309 12:15:37.195273 RX Vref Scan: 0
6310 12:15:37.195774
6311 12:15:37.196103 RX Vref 0 -> 0, step: 1
6312 12:15:37.196408
6313 12:15:37.198708 RX Delay -410 -> 252, step: 16
6314 12:15:37.205171 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6315 12:15:37.208791 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6316 12:15:37.212195 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6317 12:15:37.215259 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6318 12:15:37.222234 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6319 12:15:37.225203 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6320 12:15:37.228372 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6321 12:15:37.231805 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6322 12:15:37.238228 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6323 12:15:37.241580 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6324 12:15:37.244583 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6325 12:15:37.248296 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6326 12:15:37.255091 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6327 12:15:37.257867 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6328 12:15:37.261330 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6329 12:15:37.264907 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6330 12:15:37.268071 ==
6331 12:15:37.271093 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 12:15:37.274348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 12:15:37.274802 ==
6334 12:15:37.275128 DQS Delay:
6335 12:15:37.277745 DQS0 = 59, DQS1 = 59
6336 12:15:37.278154 DQM Delay:
6337 12:15:37.281458 DQM0 = 18, DQM1 = 11
6338 12:15:37.282176 DQ Delay:
6339 12:15:37.284590 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6340 12:15:37.287881 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6341 12:15:37.291398 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6342 12:15:37.294885 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6343 12:15:37.295394
6344 12:15:37.295717
6345 12:15:37.296015 ==
6346 12:15:37.297901 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 12:15:37.301038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 12:15:37.301582 ==
6349 12:15:37.301915
6350 12:15:37.302212
6351 12:15:37.304197 TX Vref Scan disable
6352 12:15:37.304607 == TX Byte 0 ==
6353 12:15:37.311092 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 12:15:37.314394 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 12:15:37.314868 == TX Byte 1 ==
6356 12:15:37.321003 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6357 12:15:37.324612 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6358 12:15:37.325120 ==
6359 12:15:37.327657 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 12:15:37.330771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 12:15:37.331189 ==
6362 12:15:37.331513
6363 12:15:37.331820
6364 12:15:37.334062 TX Vref Scan disable
6365 12:15:37.337759 == TX Byte 0 ==
6366 12:15:37.340450 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 12:15:37.344202 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 12:15:37.347512 == TX Byte 1 ==
6369 12:15:37.350734 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6370 12:15:37.353844 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6371 12:15:37.354298
6372 12:15:37.354783 [DATLAT]
6373 12:15:37.357135 Freq=400, CH0 RK0
6374 12:15:37.357626
6375 12:15:37.357959 DATLAT Default: 0xf
6376 12:15:37.360687 0, 0xFFFF, sum = 0
6377 12:15:37.361103 1, 0xFFFF, sum = 0
6378 12:15:37.363660 2, 0xFFFF, sum = 0
6379 12:15:37.367129 3, 0xFFFF, sum = 0
6380 12:15:37.367670 4, 0xFFFF, sum = 0
6381 12:15:37.370547 5, 0xFFFF, sum = 0
6382 12:15:37.371096 6, 0xFFFF, sum = 0
6383 12:15:37.373947 7, 0xFFFF, sum = 0
6384 12:15:37.374462 8, 0xFFFF, sum = 0
6385 12:15:37.377355 9, 0xFFFF, sum = 0
6386 12:15:37.377924 10, 0xFFFF, sum = 0
6387 12:15:37.380317 11, 0xFFFF, sum = 0
6388 12:15:37.380733 12, 0xFFFF, sum = 0
6389 12:15:37.383647 13, 0x0, sum = 1
6390 12:15:37.384112 14, 0x0, sum = 2
6391 12:15:37.386606 15, 0x0, sum = 3
6392 12:15:37.387025 16, 0x0, sum = 4
6393 12:15:37.390411 best_step = 14
6394 12:15:37.390937
6395 12:15:37.391267 ==
6396 12:15:37.393588 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 12:15:37.396839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 12:15:37.397357 ==
6399 12:15:37.400122 RX Vref Scan: 1
6400 12:15:37.400633
6401 12:15:37.400964 RX Vref 0 -> 0, step: 1
6402 12:15:37.401269
6403 12:15:37.403422 RX Delay -359 -> 252, step: 8
6404 12:15:37.403872
6405 12:15:37.406652 Set Vref, RX VrefLevel [Byte0]: 57
6406 12:15:37.409974 [Byte1]: 52
6407 12:15:37.414685
6408 12:15:37.415194 Final RX Vref Byte 0 = 57 to rank0
6409 12:15:37.418155 Final RX Vref Byte 1 = 52 to rank0
6410 12:15:37.421638 Final RX Vref Byte 0 = 57 to rank1
6411 12:15:37.424775 Final RX Vref Byte 1 = 52 to rank1==
6412 12:15:37.428016 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 12:15:37.434499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 12:15:37.435018 ==
6415 12:15:37.435361 DQS Delay:
6416 12:15:37.437996 DQS0 = 60, DQS1 = 68
6417 12:15:37.438514 DQM Delay:
6418 12:15:37.438847 DQM0 = 14, DQM1 = 13
6419 12:15:37.441154 DQ Delay:
6420 12:15:37.444245 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =8
6421 12:15:37.447868 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =24
6422 12:15:37.448377 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6423 12:15:37.454456 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6424 12:15:37.454985
6425 12:15:37.455314
6426 12:15:37.460812 [DQSOSCAuto] RK0, (LSB)MR18= 0x8582, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6427 12:15:37.464184 CH0 RK0: MR19=C0C, MR18=8582
6428 12:15:37.470958 CH0_RK0: MR19=0xC0C, MR18=0x8582, DQSOSC=393, MR23=63, INC=382, DEC=254
6429 12:15:37.471509 ==
6430 12:15:37.474563 Dram Type= 6, Freq= 0, CH_0, rank 1
6431 12:15:37.477609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 12:15:37.478171 ==
6433 12:15:37.481018 [Gating] SW mode calibration
6434 12:15:37.487453 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6435 12:15:37.493950 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6436 12:15:37.497652 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6437 12:15:37.500908 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 12:15:37.507707 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 12:15:37.511094 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6440 12:15:37.514039 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 12:15:37.520730 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 12:15:37.524088 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 12:15:37.526934 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 12:15:37.533711 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 12:15:37.534218 Total UI for P1: 0, mck2ui 16
6446 12:15:37.540744 best dqsien dly found for B0: ( 0, 14, 24)
6447 12:15:37.541391 Total UI for P1: 0, mck2ui 16
6448 12:15:37.547112 best dqsien dly found for B1: ( 0, 14, 24)
6449 12:15:37.550210 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6450 12:15:37.553921 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6451 12:15:37.554434
6452 12:15:37.556962 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6453 12:15:37.560278 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6454 12:15:37.563321 [Gating] SW calibration Done
6455 12:15:37.563858 ==
6456 12:15:37.566981 Dram Type= 6, Freq= 0, CH_0, rank 1
6457 12:15:37.569968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 12:15:37.570385 ==
6459 12:15:37.573631 RX Vref Scan: 0
6460 12:15:37.574203
6461 12:15:37.574535 RX Vref 0 -> 0, step: 1
6462 12:15:37.574839
6463 12:15:37.576774 RX Delay -410 -> 252, step: 16
6464 12:15:37.583252 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6465 12:15:37.586894 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6466 12:15:37.590009 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6467 12:15:37.593394 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6468 12:15:37.600135 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6469 12:15:37.603376 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6470 12:15:37.606818 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6471 12:15:37.609954 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6472 12:15:37.616699 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6473 12:15:37.620110 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6474 12:15:37.623481 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6475 12:15:37.626871 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6476 12:15:37.633456 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6477 12:15:37.636814 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6478 12:15:37.639889 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6479 12:15:37.643638 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6480 12:15:37.646155 ==
6481 12:15:37.650090 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 12:15:37.653081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 12:15:37.653638 ==
6484 12:15:37.653973 DQS Delay:
6485 12:15:37.656391 DQS0 = 59, DQS1 = 59
6486 12:15:37.657047 DQM Delay:
6487 12:15:37.659705 DQM0 = 16, DQM1 = 10
6488 12:15:37.660230 DQ Delay:
6489 12:15:37.662809 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6490 12:15:37.666074 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6491 12:15:37.669563 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6492 12:15:37.672998 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6493 12:15:37.673544
6494 12:15:37.673880
6495 12:15:37.674184 ==
6496 12:15:37.676545 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 12:15:37.679343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 12:15:37.679762 ==
6499 12:15:37.680088
6500 12:15:37.680390
6501 12:15:37.682836 TX Vref Scan disable
6502 12:15:37.683247 == TX Byte 0 ==
6503 12:15:37.689510 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6504 12:15:37.693009 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6505 12:15:37.693578 == TX Byte 1 ==
6506 12:15:37.699611 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6507 12:15:37.702917 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6508 12:15:37.703427 ==
6509 12:15:37.706195 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 12:15:37.709869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 12:15:37.710393 ==
6512 12:15:37.710724
6513 12:15:37.711026
6514 12:15:37.712555 TX Vref Scan disable
6515 12:15:37.712967 == TX Byte 0 ==
6516 12:15:37.719456 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6517 12:15:37.722439 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6518 12:15:37.722966 == TX Byte 1 ==
6519 12:15:37.729084 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6520 12:15:37.732110 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6521 12:15:37.732652
6522 12:15:37.733117 [DATLAT]
6523 12:15:37.735407 Freq=400, CH0 RK1
6524 12:15:37.735819
6525 12:15:37.736145 DATLAT Default: 0xe
6526 12:15:37.738881 0, 0xFFFF, sum = 0
6527 12:15:37.739300 1, 0xFFFF, sum = 0
6528 12:15:37.742246 2, 0xFFFF, sum = 0
6529 12:15:37.742850 3, 0xFFFF, sum = 0
6530 12:15:37.745515 4, 0xFFFF, sum = 0
6531 12:15:37.745957 5, 0xFFFF, sum = 0
6532 12:15:37.748966 6, 0xFFFF, sum = 0
6533 12:15:37.752295 7, 0xFFFF, sum = 0
6534 12:15:37.752712 8, 0xFFFF, sum = 0
6535 12:15:37.755410 9, 0xFFFF, sum = 0
6536 12:15:37.755936 10, 0xFFFF, sum = 0
6537 12:15:37.758752 11, 0xFFFF, sum = 0
6538 12:15:37.759179 12, 0xFFFF, sum = 0
6539 12:15:37.762119 13, 0x0, sum = 1
6540 12:15:37.762538 14, 0x0, sum = 2
6541 12:15:37.765400 15, 0x0, sum = 3
6542 12:15:37.765860 16, 0x0, sum = 4
6543 12:15:37.766228 best_step = 14
6544 12:15:37.768786
6545 12:15:37.769194 ==
6546 12:15:37.772327 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 12:15:37.775617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 12:15:37.776128 ==
6549 12:15:37.776457 RX Vref Scan: 0
6550 12:15:37.776761
6551 12:15:37.778732 RX Vref 0 -> 0, step: 1
6552 12:15:37.779142
6553 12:15:37.781875 RX Delay -359 -> 252, step: 8
6554 12:15:37.789108 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6555 12:15:37.792542 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6556 12:15:37.795886 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6557 12:15:37.799076 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6558 12:15:37.806094 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6559 12:15:37.809299 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6560 12:15:37.812228 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6561 12:15:37.815891 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6562 12:15:37.822864 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6563 12:15:37.825821 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6564 12:15:37.829308 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6565 12:15:37.835527 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6566 12:15:37.838972 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6567 12:15:37.842429 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6568 12:15:37.846100 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6569 12:15:37.852293 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6570 12:15:37.852802 ==
6571 12:15:37.855625 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 12:15:37.859295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 12:15:37.859807 ==
6574 12:15:37.860137 DQS Delay:
6575 12:15:37.862306 DQS0 = 60, DQS1 = 72
6576 12:15:37.862840 DQM Delay:
6577 12:15:37.865162 DQM0 = 11, DQM1 = 17
6578 12:15:37.865619 DQ Delay:
6579 12:15:37.868893 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6580 12:15:37.872196 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6581 12:15:37.875673 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6582 12:15:37.878861 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6583 12:15:37.879372
6584 12:15:37.879700
6585 12:15:37.885153 [DQSOSCAuto] RK1, (LSB)MR18= 0xc57a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6586 12:15:37.888712 CH0 RK1: MR19=C0C, MR18=C57A
6587 12:15:37.895508 CH0_RK1: MR19=0xC0C, MR18=0xC57A, DQSOSC=385, MR23=63, INC=398, DEC=265
6588 12:15:37.898429 [RxdqsGatingPostProcess] freq 400
6589 12:15:37.905086 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6590 12:15:37.908482 best DQS0 dly(2T, 0.5T) = (0, 10)
6591 12:15:37.909020 best DQS1 dly(2T, 0.5T) = (0, 10)
6592 12:15:37.911790 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6593 12:15:37.915234 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6594 12:15:37.918604 best DQS0 dly(2T, 0.5T) = (0, 10)
6595 12:15:37.921403 best DQS1 dly(2T, 0.5T) = (0, 10)
6596 12:15:37.925260 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6597 12:15:37.928619 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6598 12:15:37.931577 Pre-setting of DQS Precalculation
6599 12:15:37.938351 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6600 12:15:37.938859 ==
6601 12:15:37.941425 Dram Type= 6, Freq= 0, CH_1, rank 0
6602 12:15:37.944796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 12:15:37.945215 ==
6604 12:15:37.951922 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6605 12:15:37.958218 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6606 12:15:37.958728 [CA 0] Center 36 (8~64) winsize 57
6607 12:15:37.961437 [CA 1] Center 36 (8~64) winsize 57
6608 12:15:37.964919 [CA 2] Center 36 (8~64) winsize 57
6609 12:15:37.968424 [CA 3] Center 36 (8~64) winsize 57
6610 12:15:37.971525 [CA 4] Center 36 (8~64) winsize 57
6611 12:15:37.974672 [CA 5] Center 36 (8~64) winsize 57
6612 12:15:37.975181
6613 12:15:37.978257 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6614 12:15:37.978766
6615 12:15:37.981511 [CATrainingPosCal] consider 1 rank data
6616 12:15:37.984432 u2DelayCellTimex100 = 270/100 ps
6617 12:15:37.988178 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 12:15:37.994724 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 12:15:37.997806 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 12:15:38.001223 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 12:15:38.004652 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 12:15:38.007709 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 12:15:38.008128
6624 12:15:38.010803 CA PerBit enable=1, Macro0, CA PI delay=36
6625 12:15:38.011217
6626 12:15:38.014447 [CBTSetCACLKResult] CA Dly = 36
6627 12:15:38.014952 CS Dly: 1 (0~32)
6628 12:15:38.017738 ==
6629 12:15:38.020967 Dram Type= 6, Freq= 0, CH_1, rank 1
6630 12:15:38.024149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 12:15:38.024563 ==
6632 12:15:38.027581 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6633 12:15:38.034277 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6634 12:15:38.037858 [CA 0] Center 36 (8~64) winsize 57
6635 12:15:38.040623 [CA 1] Center 36 (8~64) winsize 57
6636 12:15:38.044031 [CA 2] Center 36 (8~64) winsize 57
6637 12:15:38.047120 [CA 3] Center 36 (8~64) winsize 57
6638 12:15:38.050751 [CA 4] Center 36 (8~64) winsize 57
6639 12:15:38.054262 [CA 5] Center 36 (8~64) winsize 57
6640 12:15:38.054682
6641 12:15:38.057728 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6642 12:15:38.058257
6643 12:15:38.061092 [CATrainingPosCal] consider 2 rank data
6644 12:15:38.064374 u2DelayCellTimex100 = 270/100 ps
6645 12:15:38.067465 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 12:15:38.070642 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 12:15:38.074097 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 12:15:38.077703 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 12:15:38.083882 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 12:15:38.087551 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 12:15:38.088059
6652 12:15:38.090536 CA PerBit enable=1, Macro0, CA PI delay=36
6653 12:15:38.091048
6654 12:15:38.094078 [CBTSetCACLKResult] CA Dly = 36
6655 12:15:38.094590 CS Dly: 1 (0~32)
6656 12:15:38.094919
6657 12:15:38.097379 ----->DramcWriteLeveling(PI) begin...
6658 12:15:38.097927 ==
6659 12:15:38.100662 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 12:15:38.106948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 12:15:38.107444 ==
6662 12:15:38.110494 Write leveling (Byte 0): 40 => 8
6663 12:15:38.111008 Write leveling (Byte 1): 40 => 8
6664 12:15:38.114001 DramcWriteLeveling(PI) end<-----
6665 12:15:38.114509
6666 12:15:38.117166 ==
6667 12:15:38.120578 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 12:15:38.123800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 12:15:38.124312 ==
6670 12:15:38.127017 [Gating] SW mode calibration
6671 12:15:38.133655 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6672 12:15:38.137006 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6673 12:15:38.143496 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6674 12:15:38.146762 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6675 12:15:38.150378 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 12:15:38.156955 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6677 12:15:38.160605 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 12:15:38.163197 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 12:15:38.169906 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 12:15:38.173448 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 12:15:38.177035 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 12:15:38.180431 Total UI for P1: 0, mck2ui 16
6683 12:15:38.183854 best dqsien dly found for B0: ( 0, 14, 24)
6684 12:15:38.186447 Total UI for P1: 0, mck2ui 16
6685 12:15:38.189825 best dqsien dly found for B1: ( 0, 14, 24)
6686 12:15:38.193553 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6687 12:15:38.196682 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6688 12:15:38.197192
6689 12:15:38.203169 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6690 12:15:38.206192 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6691 12:15:38.206741 [Gating] SW calibration Done
6692 12:15:38.209876 ==
6693 12:15:38.213204 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 12:15:38.216739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 12:15:38.217251 ==
6696 12:15:38.217625 RX Vref Scan: 0
6697 12:15:38.217939
6698 12:15:38.219946 RX Vref 0 -> 0, step: 1
6699 12:15:38.220452
6700 12:15:38.223094 RX Delay -410 -> 252, step: 16
6701 12:15:38.226095 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6702 12:15:38.233260 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6703 12:15:38.236543 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6704 12:15:38.239682 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6705 12:15:38.242955 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6706 12:15:38.246214 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6707 12:15:38.252720 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6708 12:15:38.256305 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6709 12:15:38.259273 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6710 12:15:38.262803 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6711 12:15:38.269336 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6712 12:15:38.273118 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6713 12:15:38.276477 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6714 12:15:38.282905 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6715 12:15:38.286046 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6716 12:15:38.289348 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6717 12:15:38.289940 ==
6718 12:15:38.292556 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 12:15:38.296047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 12:15:38.299190 ==
6721 12:15:38.299602 DQS Delay:
6722 12:15:38.299930 DQS0 = 51, DQS1 = 67
6723 12:15:38.302388 DQM Delay:
6724 12:15:38.302806 DQM0 = 12, DQM1 = 18
6725 12:15:38.305901 DQ Delay:
6726 12:15:38.306331 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6727 12:15:38.308767 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6728 12:15:38.312610 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6729 12:15:38.316097 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6730 12:15:38.316622
6731 12:15:38.317065
6732 12:15:38.319344 ==
6733 12:15:38.319875 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 12:15:38.326204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 12:15:38.326737 ==
6736 12:15:38.327182
6737 12:15:38.327596
6738 12:15:38.329419 TX Vref Scan disable
6739 12:15:38.329982 == TX Byte 0 ==
6740 12:15:38.332780 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 12:15:38.339090 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 12:15:38.339615 == TX Byte 1 ==
6743 12:15:38.342426 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 12:15:38.348980 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 12:15:38.349399 ==
6746 12:15:38.352342 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 12:15:38.356049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 12:15:38.356561 ==
6749 12:15:38.356889
6750 12:15:38.357191
6751 12:15:38.359066 TX Vref Scan disable
6752 12:15:38.359476 == TX Byte 0 ==
6753 12:15:38.362346 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 12:15:38.369023 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 12:15:38.369574 == TX Byte 1 ==
6756 12:15:38.372461 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6757 12:15:38.378678 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6758 12:15:38.379175
6759 12:15:38.379502 [DATLAT]
6760 12:15:38.379807 Freq=400, CH1 RK0
6761 12:15:38.380102
6762 12:15:38.382051 DATLAT Default: 0xf
6763 12:15:38.382461 0, 0xFFFF, sum = 0
6764 12:15:38.385401 1, 0xFFFF, sum = 0
6765 12:15:38.389086 2, 0xFFFF, sum = 0
6766 12:15:38.389649 3, 0xFFFF, sum = 0
6767 12:15:38.392328 4, 0xFFFF, sum = 0
6768 12:15:38.392843 5, 0xFFFF, sum = 0
6769 12:15:38.395213 6, 0xFFFF, sum = 0
6770 12:15:38.395659 7, 0xFFFF, sum = 0
6771 12:15:38.398708 8, 0xFFFF, sum = 0
6772 12:15:38.399216 9, 0xFFFF, sum = 0
6773 12:15:38.401960 10, 0xFFFF, sum = 0
6774 12:15:38.402377 11, 0xFFFF, sum = 0
6775 12:15:38.405466 12, 0xFFFF, sum = 0
6776 12:15:38.406221 13, 0x0, sum = 1
6777 12:15:38.408742 14, 0x0, sum = 2
6778 12:15:38.409252 15, 0x0, sum = 3
6779 12:15:38.411903 16, 0x0, sum = 4
6780 12:15:38.412323 best_step = 14
6781 12:15:38.412647
6782 12:15:38.412948 ==
6783 12:15:38.415297 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 12:15:38.418451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 12:15:38.421837 ==
6786 12:15:38.422256 RX Vref Scan: 1
6787 12:15:38.422599
6788 12:15:38.425228 RX Vref 0 -> 0, step: 1
6789 12:15:38.425794
6790 12:15:38.428185 RX Delay -375 -> 252, step: 8
6791 12:15:38.428604
6792 12:15:38.431451 Set Vref, RX VrefLevel [Byte0]: 59
6793 12:15:38.434601 [Byte1]: 54
6794 12:15:38.435160
6795 12:15:38.438236 Final RX Vref Byte 0 = 59 to rank0
6796 12:15:38.441377 Final RX Vref Byte 1 = 54 to rank0
6797 12:15:38.444588 Final RX Vref Byte 0 = 59 to rank1
6798 12:15:38.448156 Final RX Vref Byte 1 = 54 to rank1==
6799 12:15:38.451379 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 12:15:38.454412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 12:15:38.457832 ==
6802 12:15:38.458244 DQS Delay:
6803 12:15:38.458572 DQS0 = 56, DQS1 = 64
6804 12:15:38.461228 DQM Delay:
6805 12:15:38.461676 DQM0 = 12, DQM1 = 10
6806 12:15:38.464634 DQ Delay:
6807 12:15:38.467835 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6808 12:15:38.468349 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6809 12:15:38.471160 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6810 12:15:38.474424 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6811 12:15:38.474837
6812 12:15:38.475157
6813 12:15:38.484883 [DQSOSCAuto] RK0, (LSB)MR18= 0x5567, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6814 12:15:38.487659 CH1 RK0: MR19=C0C, MR18=5567
6815 12:15:38.494727 CH1_RK0: MR19=0xC0C, MR18=0x5567, DQSOSC=396, MR23=63, INC=376, DEC=251
6816 12:15:38.495241 ==
6817 12:15:38.497873 Dram Type= 6, Freq= 0, CH_1, rank 1
6818 12:15:38.501470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 12:15:38.502006 ==
6820 12:15:38.504428 [Gating] SW mode calibration
6821 12:15:38.510998 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6822 12:15:38.517360 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6823 12:15:38.521095 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6824 12:15:38.524199 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6825 12:15:38.530871 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 12:15:38.534277 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6827 12:15:38.537175 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 12:15:38.540653 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 12:15:38.547217 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 12:15:38.550760 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 12:15:38.553993 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 12:15:38.556963 Total UI for P1: 0, mck2ui 16
6833 12:15:38.560619 best dqsien dly found for B0: ( 0, 14, 24)
6834 12:15:38.563937 Total UI for P1: 0, mck2ui 16
6835 12:15:38.567482 best dqsien dly found for B1: ( 0, 14, 24)
6836 12:15:38.570489 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6837 12:15:38.577183 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6838 12:15:38.577736
6839 12:15:38.580627 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6840 12:15:38.584410 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6841 12:15:38.586959 [Gating] SW calibration Done
6842 12:15:38.587373 ==
6843 12:15:38.590364 Dram Type= 6, Freq= 0, CH_1, rank 1
6844 12:15:38.593516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 12:15:38.593933 ==
6846 12:15:38.594255 RX Vref Scan: 0
6847 12:15:38.597332
6848 12:15:38.597872 RX Vref 0 -> 0, step: 1
6849 12:15:38.598204
6850 12:15:38.600528 RX Delay -410 -> 252, step: 16
6851 12:15:38.604074 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6852 12:15:38.610628 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6853 12:15:38.613708 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6854 12:15:38.617084 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6855 12:15:38.620598 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6856 12:15:38.626696 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6857 12:15:38.630444 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6858 12:15:38.633858 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6859 12:15:38.637221 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6860 12:15:38.643664 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6861 12:15:38.646552 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6862 12:15:38.649847 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6863 12:15:38.657112 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6864 12:15:38.659937 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6865 12:15:38.663441 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6866 12:15:38.666761 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6867 12:15:38.667277 ==
6868 12:15:38.670242 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 12:15:38.676576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 12:15:38.677090 ==
6871 12:15:38.677418 DQS Delay:
6872 12:15:38.679966 DQS0 = 59, DQS1 = 67
6873 12:15:38.680472 DQM Delay:
6874 12:15:38.680797 DQM0 = 19, DQM1 = 22
6875 12:15:38.683015 DQ Delay:
6876 12:15:38.686391 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6877 12:15:38.689770 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6878 12:15:38.693426 DQ8 =0, DQ9 =16, DQ10 =24, DQ11 =16
6879 12:15:38.696469 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =32
6880 12:15:38.696980
6881 12:15:38.697303
6882 12:15:38.697643 ==
6883 12:15:38.700144 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 12:15:38.703487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 12:15:38.704006 ==
6886 12:15:38.704332
6887 12:15:38.704630
6888 12:15:38.706201 TX Vref Scan disable
6889 12:15:38.706609 == TX Byte 0 ==
6890 12:15:38.712916 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6891 12:15:38.716465 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6892 12:15:38.716979 == TX Byte 1 ==
6893 12:15:38.722686 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6894 12:15:38.726111 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6895 12:15:38.726653 ==
6896 12:15:38.729446 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 12:15:38.732732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 12:15:38.733248 ==
6899 12:15:38.733617
6900 12:15:38.733920
6901 12:15:38.735905 TX Vref Scan disable
6902 12:15:38.736312 == TX Byte 0 ==
6903 12:15:38.742765 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6904 12:15:38.746218 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6905 12:15:38.746732 == TX Byte 1 ==
6906 12:15:38.752412 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6907 12:15:38.755681 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6908 12:15:38.756196
6909 12:15:38.756521 [DATLAT]
6910 12:15:38.759047 Freq=400, CH1 RK1
6911 12:15:38.759456
6912 12:15:38.759847 DATLAT Default: 0xe
6913 12:15:38.762462 0, 0xFFFF, sum = 0
6914 12:15:38.762893 1, 0xFFFF, sum = 0
6915 12:15:38.765741 2, 0xFFFF, sum = 0
6916 12:15:38.766154 3, 0xFFFF, sum = 0
6917 12:15:38.768856 4, 0xFFFF, sum = 0
6918 12:15:38.769269 5, 0xFFFF, sum = 0
6919 12:15:38.772454 6, 0xFFFF, sum = 0
6920 12:15:38.772866 7, 0xFFFF, sum = 0
6921 12:15:38.775908 8, 0xFFFF, sum = 0
6922 12:15:38.778813 9, 0xFFFF, sum = 0
6923 12:15:38.779232 10, 0xFFFF, sum = 0
6924 12:15:38.782227 11, 0xFFFF, sum = 0
6925 12:15:38.782647 12, 0xFFFF, sum = 0
6926 12:15:38.785452 13, 0x0, sum = 1
6927 12:15:38.785914 14, 0x0, sum = 2
6928 12:15:38.788991 15, 0x0, sum = 3
6929 12:15:38.789535 16, 0x0, sum = 4
6930 12:15:38.789877 best_step = 14
6931 12:15:38.792292
6932 12:15:38.792918 ==
6933 12:15:38.795521 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 12:15:38.798756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 12:15:38.799170 ==
6936 12:15:38.799495 RX Vref Scan: 0
6937 12:15:38.799793
6938 12:15:38.802029 RX Vref 0 -> 0, step: 1
6939 12:15:38.802472
6940 12:15:38.805386 RX Delay -375 -> 252, step: 8
6941 12:15:38.813028 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6942 12:15:38.816364 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6943 12:15:38.819107 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6944 12:15:38.825595 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6945 12:15:38.829028 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6946 12:15:38.832344 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6947 12:15:38.835839 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6948 12:15:38.839119 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6949 12:15:38.845403 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6950 12:15:38.849099 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6951 12:15:38.852256 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6952 12:15:38.858705 iDelay=217, Bit 11, Center -56 (-311 ~ 200) 512
6953 12:15:38.862033 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6954 12:15:38.865363 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6955 12:15:38.868925 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6956 12:15:38.875931 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6957 12:15:38.876445 ==
6958 12:15:38.878921 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 12:15:38.882160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 12:15:38.882578 ==
6961 12:15:38.882910 DQS Delay:
6962 12:15:38.885587 DQS0 = 60, DQS1 = 64
6963 12:15:38.886001 DQM Delay:
6964 12:15:38.888928 DQM0 = 13, DQM1 = 11
6965 12:15:38.889340 DQ Delay:
6966 12:15:38.891688 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6967 12:15:38.895138 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6968 12:15:38.898495 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6969 12:15:38.901876 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6970 12:15:38.902288
6971 12:15:38.902613
6972 12:15:38.909089 [DQSOSCAuto] RK1, (LSB)MR18= 0x7dac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6973 12:15:38.912741 CH1 RK1: MR19=C0C, MR18=7DAC
6974 12:15:38.918856 CH1_RK1: MR19=0xC0C, MR18=0x7DAC, DQSOSC=388, MR23=63, INC=392, DEC=261
6975 12:15:38.922204 [RxdqsGatingPostProcess] freq 400
6976 12:15:38.928926 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6977 12:15:38.932072 best DQS0 dly(2T, 0.5T) = (0, 10)
6978 12:15:38.932583 best DQS1 dly(2T, 0.5T) = (0, 10)
6979 12:15:38.935484 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6980 12:15:38.939061 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6981 12:15:38.942061 best DQS0 dly(2T, 0.5T) = (0, 10)
6982 12:15:38.945126 best DQS1 dly(2T, 0.5T) = (0, 10)
6983 12:15:38.948669 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6984 12:15:38.952299 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6985 12:15:38.955644 Pre-setting of DQS Precalculation
6986 12:15:38.961725 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6987 12:15:38.968401 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6988 12:15:38.975355 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6989 12:15:38.975877
6990 12:15:38.976312
6991 12:15:38.978758 [Calibration Summary] 800 Mbps
6992 12:15:38.979276 CH 0, Rank 0
6993 12:15:38.981953 SW Impedance : PASS
6994 12:15:38.985339 DUTY Scan : NO K
6995 12:15:38.985888 ZQ Calibration : PASS
6996 12:15:38.988394 Jitter Meter : NO K
6997 12:15:38.988817 CBT Training : PASS
6998 12:15:38.992037 Write leveling : PASS
6999 12:15:38.995500 RX DQS gating : PASS
7000 12:15:38.996015 RX DQ/DQS(RDDQC) : PASS
7001 12:15:38.998215 TX DQ/DQS : PASS
7002 12:15:39.001550 RX DATLAT : PASS
7003 12:15:39.001947 RX DQ/DQS(Engine): PASS
7004 12:15:39.005284 TX OE : NO K
7005 12:15:39.005856 All Pass.
7006 12:15:39.006292
7007 12:15:39.008629 CH 0, Rank 1
7008 12:15:39.009148 SW Impedance : PASS
7009 12:15:39.011769 DUTY Scan : NO K
7010 12:15:39.015203 ZQ Calibration : PASS
7011 12:15:39.015737 Jitter Meter : NO K
7012 12:15:39.018504 CBT Training : PASS
7013 12:15:39.022017 Write leveling : NO K
7014 12:15:39.022534 RX DQS gating : PASS
7015 12:15:39.025338 RX DQ/DQS(RDDQC) : PASS
7016 12:15:39.028181 TX DQ/DQS : PASS
7017 12:15:39.028696 RX DATLAT : PASS
7018 12:15:39.031512 RX DQ/DQS(Engine): PASS
7019 12:15:39.034966 TX OE : NO K
7020 12:15:39.035475 All Pass.
7021 12:15:39.035806
7022 12:15:39.036110 CH 1, Rank 0
7023 12:15:39.038381 SW Impedance : PASS
7024 12:15:39.041989 DUTY Scan : NO K
7025 12:15:39.042521 ZQ Calibration : PASS
7026 12:15:39.044892 Jitter Meter : NO K
7027 12:15:39.045312 CBT Training : PASS
7028 12:15:39.048101 Write leveling : PASS
7029 12:15:39.051844 RX DQS gating : PASS
7030 12:15:39.052360 RX DQ/DQS(RDDQC) : PASS
7031 12:15:39.054513 TX DQ/DQS : PASS
7032 12:15:39.058294 RX DATLAT : PASS
7033 12:15:39.058706 RX DQ/DQS(Engine): PASS
7034 12:15:39.061457 TX OE : NO K
7035 12:15:39.061908 All Pass.
7036 12:15:39.062381
7037 12:15:39.064780 CH 1, Rank 1
7038 12:15:39.065193 SW Impedance : PASS
7039 12:15:39.068176 DUTY Scan : NO K
7040 12:15:39.071249 ZQ Calibration : PASS
7041 12:15:39.071667 Jitter Meter : NO K
7042 12:15:39.074523 CBT Training : PASS
7043 12:15:39.077853 Write leveling : NO K
7044 12:15:39.078274 RX DQS gating : PASS
7045 12:15:39.081289 RX DQ/DQS(RDDQC) : PASS
7046 12:15:39.084401 TX DQ/DQS : PASS
7047 12:15:39.084818 RX DATLAT : PASS
7048 12:15:39.087802 RX DQ/DQS(Engine): PASS
7049 12:15:39.091253 TX OE : NO K
7050 12:15:39.091669 All Pass.
7051 12:15:39.091999
7052 12:15:39.092305 DramC Write-DBI off
7053 12:15:39.094353 PER_BANK_REFRESH: Hybrid Mode
7054 12:15:39.097716 TX_TRACKING: ON
7055 12:15:39.104599 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7056 12:15:39.107949 [FAST_K] Save calibration result to emmc
7057 12:15:39.114556 dramc_set_vcore_voltage set vcore to 725000
7058 12:15:39.115079 Read voltage for 1600, 0
7059 12:15:39.118011 Vio18 = 0
7060 12:15:39.118424 Vcore = 725000
7061 12:15:39.118753 Vdram = 0
7062 12:15:39.121075 Vddq = 0
7063 12:15:39.121632 Vmddr = 0
7064 12:15:39.124575 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7065 12:15:39.131363 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7066 12:15:39.134712 MEM_TYPE=3, freq_sel=13
7067 12:15:39.137614 sv_algorithm_assistance_LP4_3733
7068 12:15:39.141554 ============ PULL DRAM RESETB DOWN ============
7069 12:15:39.144284 ========== PULL DRAM RESETB DOWN end =========
7070 12:15:39.147556 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7071 12:15:39.150899 ===================================
7072 12:15:39.154202 LPDDR4 DRAM CONFIGURATION
7073 12:15:39.157845 ===================================
7074 12:15:39.161148 EX_ROW_EN[0] = 0x0
7075 12:15:39.161708 EX_ROW_EN[1] = 0x0
7076 12:15:39.164269 LP4Y_EN = 0x0
7077 12:15:39.164679 WORK_FSP = 0x1
7078 12:15:39.167459 WL = 0x5
7079 12:15:39.167827 RL = 0x5
7080 12:15:39.170980 BL = 0x2
7081 12:15:39.171493 RPST = 0x0
7082 12:15:39.174382 RD_PRE = 0x0
7083 12:15:39.174844 WR_PRE = 0x1
7084 12:15:39.177797 WR_PST = 0x1
7085 12:15:39.178208 DBI_WR = 0x0
7086 12:15:39.181056 DBI_RD = 0x0
7087 12:15:39.184106 OTF = 0x1
7088 12:15:39.184519 ===================================
7089 12:15:39.187596 ===================================
7090 12:15:39.190728 ANA top config
7091 12:15:39.194427 ===================================
7092 12:15:39.198032 DLL_ASYNC_EN = 0
7093 12:15:39.198665 ALL_SLAVE_EN = 0
7094 12:15:39.201020 NEW_RANK_MODE = 1
7095 12:15:39.204422 DLL_IDLE_MODE = 1
7096 12:15:39.207377 LP45_APHY_COMB_EN = 1
7097 12:15:39.210978 TX_ODT_DIS = 0
7098 12:15:39.211509 NEW_8X_MODE = 1
7099 12:15:39.214219 ===================================
7100 12:15:39.217444 ===================================
7101 12:15:39.220548 data_rate = 3200
7102 12:15:39.223964 CKR = 1
7103 12:15:39.227316 DQ_P2S_RATIO = 8
7104 12:15:39.230478 ===================================
7105 12:15:39.233892 CA_P2S_RATIO = 8
7106 12:15:39.237443 DQ_CA_OPEN = 0
7107 12:15:39.238003 DQ_SEMI_OPEN = 0
7108 12:15:39.240426 CA_SEMI_OPEN = 0
7109 12:15:39.244141 CA_FULL_RATE = 0
7110 12:15:39.247213 DQ_CKDIV4_EN = 0
7111 12:15:39.250227 CA_CKDIV4_EN = 0
7112 12:15:39.253678 CA_PREDIV_EN = 0
7113 12:15:39.254115 PH8_DLY = 12
7114 12:15:39.257379 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7115 12:15:39.260479 DQ_AAMCK_DIV = 4
7116 12:15:39.263737 CA_AAMCK_DIV = 4
7117 12:15:39.267165 CA_ADMCK_DIV = 4
7118 12:15:39.270204 DQ_TRACK_CA_EN = 0
7119 12:15:39.270616 CA_PICK = 1600
7120 12:15:39.274109 CA_MCKIO = 1600
7121 12:15:39.276924 MCKIO_SEMI = 0
7122 12:15:39.280837 PLL_FREQ = 3068
7123 12:15:39.283897 DQ_UI_PI_RATIO = 32
7124 12:15:39.286837 CA_UI_PI_RATIO = 0
7125 12:15:39.290262 ===================================
7126 12:15:39.293987 ===================================
7127 12:15:39.296785 memory_type:LPDDR4
7128 12:15:39.297200 GP_NUM : 10
7129 12:15:39.300397 SRAM_EN : 1
7130 12:15:39.300919 MD32_EN : 0
7131 12:15:39.303876 ===================================
7132 12:15:39.306820 [ANA_INIT] >>>>>>>>>>>>>>
7133 12:15:39.309988 <<<<<< [CONFIGURE PHASE]: ANA_TX
7134 12:15:39.313568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7135 12:15:39.316768 ===================================
7136 12:15:39.320023 data_rate = 3200,PCW = 0X7600
7137 12:15:39.323340 ===================================
7138 12:15:39.326761 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7139 12:15:39.333341 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7140 12:15:39.336426 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7141 12:15:39.343339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7142 12:15:39.346306 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7143 12:15:39.349948 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7144 12:15:39.350469 [ANA_INIT] flow start
7145 12:15:39.353245 [ANA_INIT] PLL >>>>>>>>
7146 12:15:39.356552 [ANA_INIT] PLL <<<<<<<<
7147 12:15:39.357062 [ANA_INIT] MIDPI >>>>>>>>
7148 12:15:39.359932 [ANA_INIT] MIDPI <<<<<<<<
7149 12:15:39.363115 [ANA_INIT] DLL >>>>>>>>
7150 12:15:39.363623 [ANA_INIT] DLL <<<<<<<<
7151 12:15:39.366465 [ANA_INIT] flow end
7152 12:15:39.369694 ============ LP4 DIFF to SE enter ============
7153 12:15:39.376598 ============ LP4 DIFF to SE exit ============
7154 12:15:39.377160 [ANA_INIT] <<<<<<<<<<<<<
7155 12:15:39.379648 [Flow] Enable top DCM control >>>>>
7156 12:15:39.383005 [Flow] Enable top DCM control <<<<<
7157 12:15:39.386497 Enable DLL master slave shuffle
7158 12:15:39.393161 ==============================================================
7159 12:15:39.393721 Gating Mode config
7160 12:15:39.399582 ==============================================================
7161 12:15:39.402502 Config description:
7162 12:15:39.409604 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7163 12:15:39.416118 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7164 12:15:39.422458 SELPH_MODE 0: By rank 1: By Phase
7165 12:15:39.429283 ==============================================================
7166 12:15:39.432685 GAT_TRACK_EN = 1
7167 12:15:39.433207 RX_GATING_MODE = 2
7168 12:15:39.435964 RX_GATING_TRACK_MODE = 2
7169 12:15:39.438829 SELPH_MODE = 1
7170 12:15:39.442405 PICG_EARLY_EN = 1
7171 12:15:39.445710 VALID_LAT_VALUE = 1
7172 12:15:39.452202 ==============================================================
7173 12:15:39.455630 Enter into Gating configuration >>>>
7174 12:15:39.458888 Exit from Gating configuration <<<<
7175 12:15:39.462150 Enter into DVFS_PRE_config >>>>>
7176 12:15:39.472061 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7177 12:15:39.475602 Exit from DVFS_PRE_config <<<<<
7178 12:15:39.479160 Enter into PICG configuration >>>>
7179 12:15:39.482057 Exit from PICG configuration <<<<
7180 12:15:39.485510 [RX_INPUT] configuration >>>>>
7181 12:15:39.488879 [RX_INPUT] configuration <<<<<
7182 12:15:39.491855 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7183 12:15:39.498923 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7184 12:15:39.505657 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7185 12:15:39.508606 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7186 12:15:39.515244 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7187 12:15:39.522243 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7188 12:15:39.525311 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7189 12:15:39.532155 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7190 12:15:39.535513 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7191 12:15:39.538582 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7192 12:15:39.542030 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7193 12:15:39.548623 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7194 12:15:39.551509 ===================================
7195 12:15:39.551924 LPDDR4 DRAM CONFIGURATION
7196 12:15:39.554838 ===================================
7197 12:15:39.558216 EX_ROW_EN[0] = 0x0
7198 12:15:39.561447 EX_ROW_EN[1] = 0x0
7199 12:15:39.561922 LP4Y_EN = 0x0
7200 12:15:39.564813 WORK_FSP = 0x1
7201 12:15:39.565234 WL = 0x5
7202 12:15:39.568031 RL = 0x5
7203 12:15:39.568455 BL = 0x2
7204 12:15:39.571888 RPST = 0x0
7205 12:15:39.572460 RD_PRE = 0x0
7206 12:15:39.574800 WR_PRE = 0x1
7207 12:15:39.575227 WR_PST = 0x1
7208 12:15:39.578234 DBI_WR = 0x0
7209 12:15:39.578777 DBI_RD = 0x0
7210 12:15:39.581566 OTF = 0x1
7211 12:15:39.585277 ===================================
7212 12:15:39.587878 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7213 12:15:39.591422 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7214 12:15:39.598450 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7215 12:15:39.601390 ===================================
7216 12:15:39.601965 LPDDR4 DRAM CONFIGURATION
7217 12:15:39.605019 ===================================
7218 12:15:39.608271 EX_ROW_EN[0] = 0x10
7219 12:15:39.611290 EX_ROW_EN[1] = 0x0
7220 12:15:39.611812 LP4Y_EN = 0x0
7221 12:15:39.614460 WORK_FSP = 0x1
7222 12:15:39.614886 WL = 0x5
7223 12:15:39.617918 RL = 0x5
7224 12:15:39.618338 BL = 0x2
7225 12:15:39.621371 RPST = 0x0
7226 12:15:39.621943 RD_PRE = 0x0
7227 12:15:39.624730 WR_PRE = 0x1
7228 12:15:39.625265 WR_PST = 0x1
7229 12:15:39.627516 DBI_WR = 0x0
7230 12:15:39.627926 DBI_RD = 0x0
7231 12:15:39.631270 OTF = 0x1
7232 12:15:39.634374 ===================================
7233 12:15:39.641198 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7234 12:15:39.641740 ==
7235 12:15:39.644424 Dram Type= 6, Freq= 0, CH_0, rank 0
7236 12:15:39.647862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7237 12:15:39.648371 ==
7238 12:15:39.650914 [Duty_Offset_Calibration]
7239 12:15:39.651327 B0:2 B1:0 CA:3
7240 12:15:39.651653
7241 12:15:39.653959 [DutyScan_Calibration_Flow] k_type=0
7242 12:15:39.664831
7243 12:15:39.665334 ==CLK 0==
7244 12:15:39.668125 Final CLK duty delay cell = 0
7245 12:15:39.671760 [0] MAX Duty = 5031%(X100), DQS PI = 12
7246 12:15:39.674525 [0] MIN Duty = 4907%(X100), DQS PI = 6
7247 12:15:39.674940 [0] AVG Duty = 4969%(X100)
7248 12:15:39.678020
7249 12:15:39.681707 CH0 CLK Duty spec in!! Max-Min= 124%
7250 12:15:39.684663 [DutyScan_Calibration_Flow] ====Done====
7251 12:15:39.685095
7252 12:15:39.687854 [DutyScan_Calibration_Flow] k_type=1
7253 12:15:39.704724
7254 12:15:39.705231 ==DQS 0 ==
7255 12:15:39.708064 Final DQS duty delay cell = 0
7256 12:15:39.711278 [0] MAX Duty = 5094%(X100), DQS PI = 30
7257 12:15:39.714432 [0] MIN Duty = 4875%(X100), DQS PI = 48
7258 12:15:39.718099 [0] AVG Duty = 4984%(X100)
7259 12:15:39.718687
7260 12:15:39.719021 ==DQS 1 ==
7261 12:15:39.721078 Final DQS duty delay cell = 0
7262 12:15:39.724570 [0] MAX Duty = 5156%(X100), DQS PI = 32
7263 12:15:39.727943 [0] MIN Duty = 5062%(X100), DQS PI = 0
7264 12:15:39.731364 [0] AVG Duty = 5109%(X100)
7265 12:15:39.731879
7266 12:15:39.734133 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7267 12:15:39.734550
7268 12:15:39.737618 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7269 12:15:39.741340 [DutyScan_Calibration_Flow] ====Done====
7270 12:15:39.741918
7271 12:15:39.744039 [DutyScan_Calibration_Flow] k_type=3
7272 12:15:39.761743
7273 12:15:39.762305 ==DQM 0 ==
7274 12:15:39.764963 Final DQM duty delay cell = 0
7275 12:15:39.768234 [0] MAX Duty = 5156%(X100), DQS PI = 30
7276 12:15:39.771390 [0] MIN Duty = 4875%(X100), DQS PI = 46
7277 12:15:39.774734 [0] AVG Duty = 5015%(X100)
7278 12:15:39.775246
7279 12:15:39.775572 ==DQM 1 ==
7280 12:15:39.777848 Final DQM duty delay cell = 0
7281 12:15:39.780915 [0] MAX Duty = 4938%(X100), DQS PI = 0
7282 12:15:39.784695 [0] MIN Duty = 4813%(X100), DQS PI = 20
7283 12:15:39.787763 [0] AVG Duty = 4875%(X100)
7284 12:15:39.788173
7285 12:15:39.790915 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7286 12:15:39.791325
7287 12:15:39.794198 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7288 12:15:39.797669 [DutyScan_Calibration_Flow] ====Done====
7289 12:15:39.798080
7290 12:15:39.801453 [DutyScan_Calibration_Flow] k_type=2
7291 12:15:39.818111
7292 12:15:39.818614 ==DQ 0 ==
7293 12:15:39.820612 Final DQ duty delay cell = -4
7294 12:15:39.824260 [-4] MAX Duty = 5000%(X100), DQS PI = 16
7295 12:15:39.827568 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7296 12:15:39.830688 [-4] AVG Duty = 4938%(X100)
7297 12:15:39.831095
7298 12:15:39.831419 ==DQ 1 ==
7299 12:15:39.833938 Final DQ duty delay cell = 0
7300 12:15:39.837420 [0] MAX Duty = 5156%(X100), DQS PI = 58
7301 12:15:39.840548 [0] MIN Duty = 5000%(X100), DQS PI = 16
7302 12:15:39.844298 [0] AVG Duty = 5078%(X100)
7303 12:15:39.844803
7304 12:15:39.847274 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7305 12:15:39.847686
7306 12:15:39.850593 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7307 12:15:39.853851 [DutyScan_Calibration_Flow] ====Done====
7308 12:15:39.854379 ==
7309 12:15:39.857037 Dram Type= 6, Freq= 0, CH_1, rank 0
7310 12:15:39.860526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7311 12:15:39.861196 ==
7312 12:15:39.864082 [Duty_Offset_Calibration]
7313 12:15:39.864576 B0:1 B1:-2 CA:1
7314 12:15:39.865064
7315 12:15:39.867145 [DutyScan_Calibration_Flow] k_type=0
7316 12:15:39.877874
7317 12:15:39.878428 ==CLK 0==
7318 12:15:39.881326 Final CLK duty delay cell = 0
7319 12:15:39.885050 [0] MAX Duty = 5062%(X100), DQS PI = 22
7320 12:15:39.888201 [0] MIN Duty = 4844%(X100), DQS PI = 2
7321 12:15:39.888755 [0] AVG Duty = 4953%(X100)
7322 12:15:39.891659
7323 12:15:39.894749 CH1 CLK Duty spec in!! Max-Min= 218%
7324 12:15:39.898449 [DutyScan_Calibration_Flow] ====Done====
7325 12:15:39.898958
7326 12:15:39.901527 [DutyScan_Calibration_Flow] k_type=1
7327 12:15:39.917660
7328 12:15:39.918160 ==DQS 0 ==
7329 12:15:39.920783 Final DQS duty delay cell = 0
7330 12:15:39.924175 [0] MAX Duty = 5187%(X100), DQS PI = 24
7331 12:15:39.927642 [0] MIN Duty = 5031%(X100), DQS PI = 54
7332 12:15:39.930588 [0] AVG Duty = 5109%(X100)
7333 12:15:39.930995
7334 12:15:39.931315 ==DQS 1 ==
7335 12:15:39.934339 Final DQS duty delay cell = 0
7336 12:15:39.937510 [0] MAX Duty = 5093%(X100), DQS PI = 60
7337 12:15:39.940841 [0] MIN Duty = 4844%(X100), DQS PI = 26
7338 12:15:39.944249 [0] AVG Duty = 4968%(X100)
7339 12:15:39.944757
7340 12:15:39.947302 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7341 12:15:39.947712
7342 12:15:39.950859 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7343 12:15:39.953757 [DutyScan_Calibration_Flow] ====Done====
7344 12:15:39.954168
7345 12:15:39.957221 [DutyScan_Calibration_Flow] k_type=3
7346 12:15:39.974438
7347 12:15:39.974943 ==DQM 0 ==
7348 12:15:39.977584 Final DQM duty delay cell = 0
7349 12:15:39.981209 [0] MAX Duty = 5031%(X100), DQS PI = 26
7350 12:15:39.984398 [0] MIN Duty = 4813%(X100), DQS PI = 58
7351 12:15:39.987487 [0] AVG Duty = 4922%(X100)
7352 12:15:39.987896
7353 12:15:39.988222 ==DQM 1 ==
7354 12:15:39.990774 Final DQM duty delay cell = 0
7355 12:15:39.994059 [0] MAX Duty = 5093%(X100), DQS PI = 36
7356 12:15:39.997820 [0] MIN Duty = 4875%(X100), DQS PI = 24
7357 12:15:40.000848 [0] AVG Duty = 4984%(X100)
7358 12:15:40.001514
7359 12:15:40.003997 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7360 12:15:40.004489
7361 12:15:40.007514 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7362 12:15:40.010674 [DutyScan_Calibration_Flow] ====Done====
7363 12:15:40.011099
7364 12:15:40.014149 [DutyScan_Calibration_Flow] k_type=2
7365 12:15:40.031477
7366 12:15:40.031980 ==DQ 0 ==
7367 12:15:40.034691 Final DQ duty delay cell = 0
7368 12:15:40.038037 [0] MAX Duty = 5093%(X100), DQS PI = 22
7369 12:15:40.040842 [0] MIN Duty = 4907%(X100), DQS PI = 62
7370 12:15:40.041356 [0] AVG Duty = 5000%(X100)
7371 12:15:40.044186
7372 12:15:40.044593 ==DQ 1 ==
7373 12:15:40.047530 Final DQ duty delay cell = 0
7374 12:15:40.050954 [0] MAX Duty = 5125%(X100), DQS PI = 34
7375 12:15:40.054563 [0] MIN Duty = 4969%(X100), DQS PI = 24
7376 12:15:40.055074 [0] AVG Duty = 5047%(X100)
7377 12:15:40.057606
7378 12:15:40.060855 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7379 12:15:40.061553
7380 12:15:40.064720 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7381 12:15:40.068117 [DutyScan_Calibration_Flow] ====Done====
7382 12:15:40.070847 nWR fixed to 30
7383 12:15:40.071261 [ModeRegInit_LP4] CH0 RK0
7384 12:15:40.074239 [ModeRegInit_LP4] CH0 RK1
7385 12:15:40.077517 [ModeRegInit_LP4] CH1 RK0
7386 12:15:40.080753 [ModeRegInit_LP4] CH1 RK1
7387 12:15:40.081242 match AC timing 5
7388 12:15:40.087562 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7389 12:15:40.090713 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7390 12:15:40.093756 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7391 12:15:40.100715 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7392 12:15:40.104179 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7393 12:15:40.104696 [MiockJmeterHQA]
7394 12:15:40.105151
7395 12:15:40.107754 [DramcMiockJmeter] u1RxGatingPI = 0
7396 12:15:40.110988 0 : 4255, 4029
7397 12:15:40.111498 4 : 4255, 4027
7398 12:15:40.114064 8 : 4254, 4029
7399 12:15:40.114482 12 : 4366, 4140
7400 12:15:40.114812 16 : 4255, 4029
7401 12:15:40.117392 20 : 4254, 4029
7402 12:15:40.117891 24 : 4258, 4031
7403 12:15:40.120906 28 : 4257, 4029
7404 12:15:40.121418 32 : 4259, 4032
7405 12:15:40.124248 36 : 4368, 4142
7406 12:15:40.124760 40 : 4366, 4140
7407 12:15:40.127021 44 : 4252, 4029
7408 12:15:40.127455 48 : 4255, 4029
7409 12:15:40.127785 52 : 4363, 4140
7410 12:15:40.130289 56 : 4255, 4029
7411 12:15:40.130705 60 : 4363, 4140
7412 12:15:40.133887 64 : 4250, 4027
7413 12:15:40.134404 68 : 4252, 4030
7414 12:15:40.136877 72 : 4253, 4029
7415 12:15:40.137390 76 : 4257, 4031
7416 12:15:40.140450 80 : 4363, 4140
7417 12:15:40.140867 84 : 4252, 4030
7418 12:15:40.141194 88 : 4255, 4030
7419 12:15:40.144311 92 : 4366, 4140
7420 12:15:40.144821 96 : 4255, 4029
7421 12:15:40.147002 100 : 4361, 4138
7422 12:15:40.147427 104 : 4252, 3658
7423 12:15:40.150468 108 : 4253, 2
7424 12:15:40.150882 112 : 4363, 0
7425 12:15:40.151292 116 : 4255, 0
7426 12:15:40.153657 120 : 4363, 0
7427 12:15:40.154074 124 : 4250, 0
7428 12:15:40.156969 128 : 4255, 0
7429 12:15:40.157383 132 : 4250, 0
7430 12:15:40.157773 136 : 4252, 0
7431 12:15:40.160579 140 : 4368, 0
7432 12:15:40.160992 144 : 4252, 0
7433 12:15:40.163426 148 : 4252, 0
7434 12:15:40.163840 152 : 4255, 0
7435 12:15:40.164171 156 : 4255, 0
7436 12:15:40.167072 160 : 4363, 0
7437 12:15:40.167582 164 : 4363, 0
7438 12:15:40.170206 168 : 4255, 0
7439 12:15:40.170624 172 : 4252, 0
7440 12:15:40.170955 176 : 4252, 0
7441 12:15:40.173694 180 : 4255, 0
7442 12:15:40.174189 184 : 4252, 0
7443 12:15:40.174524 188 : 4252, 0
7444 12:15:40.176859 192 : 4252, 0
7445 12:15:40.177270 196 : 4255, 0
7446 12:15:40.179906 200 : 4250, 0
7447 12:15:40.180321 204 : 4255, 0
7448 12:15:40.180651 208 : 4368, 0
7449 12:15:40.183591 212 : 4363, 0
7450 12:15:40.184107 216 : 4363, 0
7451 12:15:40.186991 220 : 4250, 0
7452 12:15:40.187508 224 : 4252, 0
7453 12:15:40.187845 228 : 4253, 0
7454 12:15:40.190157 232 : 4255, 0
7455 12:15:40.190697 236 : 4252, 1219
7456 12:15:40.193634 240 : 4258, 4032
7457 12:15:40.194145 244 : 4255, 4029
7458 12:15:40.196886 248 : 4252, 4030
7459 12:15:40.197402 252 : 4253, 4029
7460 12:15:40.200333 256 : 4257, 4031
7461 12:15:40.200846 260 : 4255, 4029
7462 12:15:40.203563 264 : 4252, 4029
7463 12:15:40.204078 268 : 4252, 4030
7464 12:15:40.204438 272 : 4257, 4031
7465 12:15:40.206767 276 : 4252, 4030
7466 12:15:40.207409 280 : 4363, 4140
7467 12:15:40.210204 284 : 4253, 4029
7468 12:15:40.210719 288 : 4253, 4029
7469 12:15:40.213463 292 : 4255, 4029
7470 12:15:40.214024 296 : 4363, 4139
7471 12:15:40.216509 300 : 4250, 4027
7472 12:15:40.217030 304 : 4363, 4140
7473 12:15:40.219883 308 : 4252, 4030
7474 12:15:40.220399 312 : 4255, 4030
7475 12:15:40.223450 316 : 4366, 4140
7476 12:15:40.223971 320 : 4364, 4140
7477 12:15:40.226208 324 : 4250, 4026
7478 12:15:40.226629 328 : 4255, 4029
7479 12:15:40.226962 332 : 4255, 4029
7480 12:15:40.229587 336 : 4363, 4140
7481 12:15:40.230003 340 : 4252, 4026
7482 12:15:40.232947 344 : 4368, 4142
7483 12:15:40.233367 348 : 4250, 4027
7484 12:15:40.236576 352 : 4252, 3992
7485 12:15:40.237094 356 : 4363, 2771
7486 12:15:40.239572 360 : 4255, 0
7487 12:15:40.240085
7488 12:15:40.240414 MIOCK jitter meter ch=0
7489 12:15:40.242951
7490 12:15:40.243370 1T = (360-108) = 252 dly cells
7491 12:15:40.249591 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7492 12:15:40.250108 ==
7493 12:15:40.252686 Dram Type= 6, Freq= 0, CH_0, rank 0
7494 12:15:40.255972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7495 12:15:40.256389 ==
7496 12:15:40.262591 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7497 12:15:40.265681 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7498 12:15:40.272717 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7499 12:15:40.276091 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7500 12:15:40.286022 [CA 0] Center 43 (13~74) winsize 62
7501 12:15:40.289319 [CA 1] Center 43 (13~74) winsize 62
7502 12:15:40.293145 [CA 2] Center 39 (10~68) winsize 59
7503 12:15:40.296605 [CA 3] Center 39 (10~68) winsize 59
7504 12:15:40.299411 [CA 4] Center 36 (7~66) winsize 60
7505 12:15:40.302651 [CA 5] Center 36 (7~66) winsize 60
7506 12:15:40.303160
7507 12:15:40.306323 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7508 12:15:40.306835
7509 12:15:40.312771 [CATrainingPosCal] consider 1 rank data
7510 12:15:40.313273 u2DelayCellTimex100 = 258/100 ps
7511 12:15:40.319365 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7512 12:15:40.322527 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7513 12:15:40.326238 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7514 12:15:40.329091 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7515 12:15:40.332340 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7516 12:15:40.335712 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7517 12:15:40.336229
7518 12:15:40.338746 CA PerBit enable=1, Macro0, CA PI delay=36
7519 12:15:40.342198
7520 12:15:40.342603 [CBTSetCACLKResult] CA Dly = 36
7521 12:15:40.345835 CS Dly: 11 (0~42)
7522 12:15:40.348508 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7523 12:15:40.351871 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7524 12:15:40.355305 ==
7525 12:15:40.358334 Dram Type= 6, Freq= 0, CH_0, rank 1
7526 12:15:40.362119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 12:15:40.362635 ==
7528 12:15:40.368832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7529 12:15:40.371819 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7530 12:15:40.374979 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7531 12:15:40.381879 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7532 12:15:40.390206 [CA 0] Center 43 (13~74) winsize 62
7533 12:15:40.393785 [CA 1] Center 43 (13~74) winsize 62
7534 12:15:40.397074 [CA 2] Center 39 (10~68) winsize 59
7535 12:15:40.400575 [CA 3] Center 39 (10~68) winsize 59
7536 12:15:40.403803 [CA 4] Center 36 (6~66) winsize 61
7537 12:15:40.406926 [CA 5] Center 36 (6~66) winsize 61
7538 12:15:40.407443
7539 12:15:40.410279 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7540 12:15:40.410794
7541 12:15:40.413459 [CATrainingPosCal] consider 2 rank data
7542 12:15:40.416593 u2DelayCellTimex100 = 258/100 ps
7543 12:15:40.423521 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7544 12:15:40.426876 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7545 12:15:40.430447 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7546 12:15:40.433441 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7547 12:15:40.436672 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7548 12:15:40.440243 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7549 12:15:40.440755
7550 12:15:40.443408 CA PerBit enable=1, Macro0, CA PI delay=36
7551 12:15:40.443926
7552 12:15:40.446350 [CBTSetCACLKResult] CA Dly = 36
7553 12:15:40.449738 CS Dly: 11 (0~42)
7554 12:15:40.453146 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7555 12:15:40.456431 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7556 12:15:40.456945
7557 12:15:40.459792 ----->DramcWriteLeveling(PI) begin...
7558 12:15:40.462989 ==
7559 12:15:40.463417 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 12:15:40.469335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 12:15:40.469909 ==
7562 12:15:40.472843 Write leveling (Byte 0): 38 => 38
7563 12:15:40.476260 Write leveling (Byte 1): 26 => 26
7564 12:15:40.479458 DramcWriteLeveling(PI) end<-----
7565 12:15:40.479871
7566 12:15:40.480193 ==
7567 12:15:40.482802 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 12:15:40.486106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 12:15:40.486621 ==
7570 12:15:40.489249 [Gating] SW mode calibration
7571 12:15:40.495703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7572 12:15:40.502390 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7573 12:15:40.505901 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 12:15:40.509380 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 12:15:40.515509 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 12:15:40.519305 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 12:15:40.522379 1 4 16 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7578 12:15:40.529016 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7579 12:15:40.532373 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7580 12:15:40.535878 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 12:15:40.538776 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 12:15:40.545298 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7583 12:15:40.549049 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 12:15:40.552197 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7585 12:15:40.558984 1 5 16 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
7586 12:15:40.562453 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7587 12:15:40.565720 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7588 12:15:40.572434 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 12:15:40.575572 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 12:15:40.578804 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 12:15:40.586047 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 12:15:40.589160 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 12:15:40.592240 1 6 16 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7594 12:15:40.598854 1 6 20 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
7595 12:15:40.602414 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 12:15:40.605713 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 12:15:40.611831 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 12:15:40.615573 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 12:15:40.618996 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 12:15:40.625467 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 12:15:40.628406 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7602 12:15:40.631779 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7603 12:15:40.638384 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7604 12:15:40.641779 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 12:15:40.644995 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 12:15:40.652071 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 12:15:40.655016 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 12:15:40.658176 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 12:15:40.664704 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 12:15:40.667977 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 12:15:40.671624 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 12:15:40.677764 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 12:15:40.681410 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 12:15:40.684596 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 12:15:40.691156 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 12:15:40.694414 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7617 12:15:40.697937 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7618 12:15:40.704766 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7619 12:15:40.705281 Total UI for P1: 0, mck2ui 16
7620 12:15:40.710994 best dqsien dly found for B0: ( 1, 9, 14)
7621 12:15:40.714421 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7622 12:15:40.718039 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 12:15:40.720996 Total UI for P1: 0, mck2ui 16
7624 12:15:40.724498 best dqsien dly found for B1: ( 1, 9, 22)
7625 12:15:40.727459 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7626 12:15:40.730853 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7627 12:15:40.731364
7628 12:15:40.737539 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7629 12:15:40.740504 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7630 12:15:40.744157 [Gating] SW calibration Done
7631 12:15:40.744662 ==
7632 12:15:40.747298 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 12:15:40.750936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 12:15:40.751444 ==
7635 12:15:40.751774 RX Vref Scan: 0
7636 12:15:40.752077
7637 12:15:40.754046 RX Vref 0 -> 0, step: 1
7638 12:15:40.754454
7639 12:15:40.757395 RX Delay 0 -> 252, step: 8
7640 12:15:40.760346 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7641 12:15:40.763936 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7642 12:15:40.770446 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7643 12:15:40.773659 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7644 12:15:40.776879 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7645 12:15:40.780118 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7646 12:15:40.783619 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7647 12:15:40.790204 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7648 12:15:40.793592 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7649 12:15:40.797089 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7650 12:15:40.800263 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7651 12:15:40.803785 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7652 12:15:40.810403 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7653 12:15:40.813046 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7654 12:15:40.816855 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7655 12:15:40.820248 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7656 12:15:40.820769 ==
7657 12:15:40.823296 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 12:15:40.829566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 12:15:40.830093 ==
7660 12:15:40.830424 DQS Delay:
7661 12:15:40.833305 DQS0 = 0, DQS1 = 0
7662 12:15:40.833872 DQM Delay:
7663 12:15:40.836791 DQM0 = 128, DQM1 = 124
7664 12:15:40.837307 DQ Delay:
7665 12:15:40.839591 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7666 12:15:40.843155 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7667 12:15:40.846431 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7668 12:15:40.849590 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7669 12:15:40.850005
7670 12:15:40.850331
7671 12:15:40.850634 ==
7672 12:15:40.852747 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 12:15:40.859137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 12:15:40.859639 ==
7675 12:15:40.859989
7676 12:15:40.860585
7677 12:15:40.860917 TX Vref Scan disable
7678 12:15:40.862897 == TX Byte 0 ==
7679 12:15:40.866234 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
7680 12:15:40.872861 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
7681 12:15:40.873367 == TX Byte 1 ==
7682 12:15:40.875894 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7683 12:15:40.883011 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7684 12:15:40.883517 ==
7685 12:15:40.886004 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 12:15:40.889316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 12:15:40.889892 ==
7688 12:15:40.904417
7689 12:15:40.907963 TX Vref early break, caculate TX vref
7690 12:15:40.911393 TX Vref=16, minBit 11, minWin=21, winSum=370
7691 12:15:40.914795 TX Vref=18, minBit 11, minWin=21, winSum=376
7692 12:15:40.917754 TX Vref=20, minBit 8, minWin=22, winSum=385
7693 12:15:40.920899 TX Vref=22, minBit 8, minWin=23, winSum=395
7694 12:15:40.923983 TX Vref=24, minBit 8, minWin=23, winSum=403
7695 12:15:40.930741 TX Vref=26, minBit 9, minWin=24, winSum=406
7696 12:15:40.934279 TX Vref=28, minBit 8, minWin=23, winSum=405
7697 12:15:40.937607 TX Vref=30, minBit 9, minWin=23, winSum=403
7698 12:15:40.940963 TX Vref=32, minBit 9, minWin=22, winSum=397
7699 12:15:40.944162 TX Vref=34, minBit 8, minWin=22, winSum=386
7700 12:15:40.947386 TX Vref=36, minBit 9, minWin=21, winSum=372
7701 12:15:40.953860 [TxChooseVref] Worse bit 9, Min win 24, Win sum 406, Final Vref 26
7702 12:15:40.954369
7703 12:15:40.957322 Final TX Range 0 Vref 26
7704 12:15:40.957767
7705 12:15:40.958092 ==
7706 12:15:40.960585 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 12:15:40.963740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 12:15:40.964160 ==
7709 12:15:40.967351
7710 12:15:40.967966
7711 12:15:40.968300 TX Vref Scan disable
7712 12:15:40.973917 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7713 12:15:40.974330 == TX Byte 0 ==
7714 12:15:40.976996 u2DelayCellOfst[0]=15 cells (4 PI)
7715 12:15:40.980416 u2DelayCellOfst[1]=15 cells (4 PI)
7716 12:15:40.984060 u2DelayCellOfst[2]=11 cells (3 PI)
7717 12:15:40.987147 u2DelayCellOfst[3]=11 cells (3 PI)
7718 12:15:40.990226 u2DelayCellOfst[4]=7 cells (2 PI)
7719 12:15:40.993574 u2DelayCellOfst[5]=0 cells (0 PI)
7720 12:15:40.997168 u2DelayCellOfst[6]=15 cells (4 PI)
7721 12:15:41.000412 u2DelayCellOfst[7]=15 cells (4 PI)
7722 12:15:41.004234 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7723 12:15:41.007063 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7724 12:15:41.010152 == TX Byte 1 ==
7725 12:15:41.013815 u2DelayCellOfst[8]=0 cells (0 PI)
7726 12:15:41.017206 u2DelayCellOfst[9]=0 cells (0 PI)
7727 12:15:41.020154 u2DelayCellOfst[10]=3 cells (1 PI)
7728 12:15:41.023641 u2DelayCellOfst[11]=3 cells (1 PI)
7729 12:15:41.027073 u2DelayCellOfst[12]=11 cells (3 PI)
7730 12:15:41.027587 u2DelayCellOfst[13]=11 cells (3 PI)
7731 12:15:41.030192 u2DelayCellOfst[14]=15 cells (4 PI)
7732 12:15:41.033414 u2DelayCellOfst[15]=11 cells (3 PI)
7733 12:15:41.040284 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7734 12:15:41.043766 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7735 12:15:41.044284 DramC Write-DBI on
7736 12:15:41.046444 ==
7737 12:15:41.050034 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 12:15:41.053279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 12:15:41.053745 ==
7740 12:15:41.054073
7741 12:15:41.054378
7742 12:15:41.056613 TX Vref Scan disable
7743 12:15:41.057025 == TX Byte 0 ==
7744 12:15:41.063362 Update DQM dly =739 (2 ,6, 35) DQM OEN =(3 ,3)
7745 12:15:41.063884 == TX Byte 1 ==
7746 12:15:41.066308 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7747 12:15:41.069948 DramC Write-DBI off
7748 12:15:41.070374
7749 12:15:41.070703 [DATLAT]
7750 12:15:41.072939 Freq=1600, CH0 RK0
7751 12:15:41.073351
7752 12:15:41.073726 DATLAT Default: 0xf
7753 12:15:41.076507 0, 0xFFFF, sum = 0
7754 12:15:41.076929 1, 0xFFFF, sum = 0
7755 12:15:41.079814 2, 0xFFFF, sum = 0
7756 12:15:41.080409 3, 0xFFFF, sum = 0
7757 12:15:41.082906 4, 0xFFFF, sum = 0
7758 12:15:41.086466 5, 0xFFFF, sum = 0
7759 12:15:41.086991 6, 0xFFFF, sum = 0
7760 12:15:41.089611 7, 0xFFFF, sum = 0
7761 12:15:41.090030 8, 0xFFFF, sum = 0
7762 12:15:41.093361 9, 0xFFFF, sum = 0
7763 12:15:41.093934 10, 0xFFFF, sum = 0
7764 12:15:41.096851 11, 0xFFFF, sum = 0
7765 12:15:41.097375 12, 0xFFFF, sum = 0
7766 12:15:41.100039 13, 0xEFFF, sum = 0
7767 12:15:41.100561 14, 0x0, sum = 1
7768 12:15:41.103151 15, 0x0, sum = 2
7769 12:15:41.103570 16, 0x0, sum = 3
7770 12:15:41.106478 17, 0x0, sum = 4
7771 12:15:41.106897 best_step = 15
7772 12:15:41.107222
7773 12:15:41.107524 ==
7774 12:15:41.109792 Dram Type= 6, Freq= 0, CH_0, rank 0
7775 12:15:41.113142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7776 12:15:41.113604 ==
7777 12:15:41.116514 RX Vref Scan: 1
7778 12:15:41.116925
7779 12:15:41.119604 Set Vref Range= 24 -> 127
7780 12:15:41.120019
7781 12:15:41.120345 RX Vref 24 -> 127, step: 1
7782 12:15:41.123308
7783 12:15:41.123824 RX Delay 11 -> 252, step: 4
7784 12:15:41.124155
7785 12:15:41.126141 Set Vref, RX VrefLevel [Byte0]: 24
7786 12:15:41.129330 [Byte1]: 24
7787 12:15:41.133114
7788 12:15:41.133551 Set Vref, RX VrefLevel [Byte0]: 25
7789 12:15:41.136439 [Byte1]: 25
7790 12:15:41.140601
7791 12:15:41.141014 Set Vref, RX VrefLevel [Byte0]: 26
7792 12:15:41.144305 [Byte1]: 26
7793 12:15:41.148407
7794 12:15:41.148819 Set Vref, RX VrefLevel [Byte0]: 27
7795 12:15:41.151439 [Byte1]: 27
7796 12:15:41.155929
7797 12:15:41.156344 Set Vref, RX VrefLevel [Byte0]: 28
7798 12:15:41.159075 [Byte1]: 28
7799 12:15:41.163544
7800 12:15:41.163956 Set Vref, RX VrefLevel [Byte0]: 29
7801 12:15:41.166590 [Byte1]: 29
7802 12:15:41.171046
7803 12:15:41.171454 Set Vref, RX VrefLevel [Byte0]: 30
7804 12:15:41.174432 [Byte1]: 30
7805 12:15:41.179215
7806 12:15:41.179731 Set Vref, RX VrefLevel [Byte0]: 31
7807 12:15:41.182122 [Byte1]: 31
7808 12:15:41.186457
7809 12:15:41.186870 Set Vref, RX VrefLevel [Byte0]: 32
7810 12:15:41.189851 [Byte1]: 32
7811 12:15:41.193764
7812 12:15:41.194291 Set Vref, RX VrefLevel [Byte0]: 33
7813 12:15:41.197503 [Byte1]: 33
7814 12:15:41.201993
7815 12:15:41.202690 Set Vref, RX VrefLevel [Byte0]: 34
7816 12:15:41.205520 [Byte1]: 34
7817 12:15:41.209296
7818 12:15:41.209857 Set Vref, RX VrefLevel [Byte0]: 35
7819 12:15:41.212780 [Byte1]: 35
7820 12:15:41.217125
7821 12:15:41.217677 Set Vref, RX VrefLevel [Byte0]: 36
7822 12:15:41.220272 [Byte1]: 36
7823 12:15:41.224602
7824 12:15:41.225118 Set Vref, RX VrefLevel [Byte0]: 37
7825 12:15:41.227656 [Byte1]: 37
7826 12:15:41.232455
7827 12:15:41.232972 Set Vref, RX VrefLevel [Byte0]: 38
7828 12:15:41.235394 [Byte1]: 38
7829 12:15:41.239881
7830 12:15:41.240430 Set Vref, RX VrefLevel [Byte0]: 39
7831 12:15:41.242991 [Byte1]: 39
7832 12:15:41.247480
7833 12:15:41.247995 Set Vref, RX VrefLevel [Byte0]: 40
7834 12:15:41.250525 [Byte1]: 40
7835 12:15:41.255314
7836 12:15:41.255835 Set Vref, RX VrefLevel [Byte0]: 41
7837 12:15:41.258197 [Byte1]: 41
7838 12:15:41.262354
7839 12:15:41.263002 Set Vref, RX VrefLevel [Byte0]: 42
7840 12:15:41.265650 [Byte1]: 42
7841 12:15:41.270366
7842 12:15:41.270882 Set Vref, RX VrefLevel [Byte0]: 43
7843 12:15:41.273631 [Byte1]: 43
7844 12:15:41.277768
7845 12:15:41.278287 Set Vref, RX VrefLevel [Byte0]: 44
7846 12:15:41.281352 [Byte1]: 44
7847 12:15:41.285472
7848 12:15:41.286040 Set Vref, RX VrefLevel [Byte0]: 45
7849 12:15:41.288938 [Byte1]: 45
7850 12:15:41.292816
7851 12:15:41.293228 Set Vref, RX VrefLevel [Byte0]: 46
7852 12:15:41.296493 [Byte1]: 46
7853 12:15:41.300741
7854 12:15:41.301250 Set Vref, RX VrefLevel [Byte0]: 47
7855 12:15:41.304144 [Byte1]: 47
7856 12:15:41.308203
7857 12:15:41.308709 Set Vref, RX VrefLevel [Byte0]: 48
7858 12:15:41.311355 [Byte1]: 48
7859 12:15:41.315654
7860 12:15:41.316067 Set Vref, RX VrefLevel [Byte0]: 49
7861 12:15:41.319439 [Byte1]: 49
7862 12:15:41.323437
7863 12:15:41.323951 Set Vref, RX VrefLevel [Byte0]: 50
7864 12:15:41.326749 [Byte1]: 50
7865 12:15:41.331012
7866 12:15:41.331714 Set Vref, RX VrefLevel [Byte0]: 51
7867 12:15:41.334233 [Byte1]: 51
7868 12:15:41.338560
7869 12:15:41.339076 Set Vref, RX VrefLevel [Byte0]: 52
7870 12:15:41.342133 [Byte1]: 52
7871 12:15:41.346504
7872 12:15:41.347019 Set Vref, RX VrefLevel [Byte0]: 53
7873 12:15:41.349686 [Byte1]: 53
7874 12:15:41.354166
7875 12:15:41.354687 Set Vref, RX VrefLevel [Byte0]: 54
7876 12:15:41.357644 [Byte1]: 54
7877 12:15:41.362075
7878 12:15:41.362596 Set Vref, RX VrefLevel [Byte0]: 55
7879 12:15:41.364920 [Byte1]: 55
7880 12:15:41.369154
7881 12:15:41.369727 Set Vref, RX VrefLevel [Byte0]: 56
7882 12:15:41.372361 [Byte1]: 56
7883 12:15:41.377015
7884 12:15:41.377576 Set Vref, RX VrefLevel [Byte0]: 57
7885 12:15:41.380017 [Byte1]: 57
7886 12:15:41.384417
7887 12:15:41.384943 Set Vref, RX VrefLevel [Byte0]: 58
7888 12:15:41.387787 [Byte1]: 58
7889 12:15:41.392272
7890 12:15:41.392788 Set Vref, RX VrefLevel [Byte0]: 59
7891 12:15:41.395084 [Byte1]: 59
7892 12:15:41.399812
7893 12:15:41.400330 Set Vref, RX VrefLevel [Byte0]: 60
7894 12:15:41.403140 [Byte1]: 60
7895 12:15:41.407296
7896 12:15:41.407837 Set Vref, RX VrefLevel [Byte0]: 61
7897 12:15:41.410428 [Byte1]: 61
7898 12:15:41.414631
7899 12:15:41.415150 Set Vref, RX VrefLevel [Byte0]: 62
7900 12:15:41.418215 [Byte1]: 62
7901 12:15:41.422562
7902 12:15:41.423079 Set Vref, RX VrefLevel [Byte0]: 63
7903 12:15:41.426063 [Byte1]: 63
7904 12:15:41.430244
7905 12:15:41.430765 Set Vref, RX VrefLevel [Byte0]: 64
7906 12:15:41.433631 [Byte1]: 64
7907 12:15:41.437888
7908 12:15:41.438403 Set Vref, RX VrefLevel [Byte0]: 65
7909 12:15:41.441332 [Byte1]: 65
7910 12:15:41.445430
7911 12:15:41.445985 Set Vref, RX VrefLevel [Byte0]: 66
7912 12:15:41.448350 [Byte1]: 66
7913 12:15:41.453119
7914 12:15:41.453665 Set Vref, RX VrefLevel [Byte0]: 67
7915 12:15:41.456209 [Byte1]: 67
7916 12:15:41.460496
7917 12:15:41.461011 Set Vref, RX VrefLevel [Byte0]: 68
7918 12:15:41.463625 [Byte1]: 68
7919 12:15:41.468221
7920 12:15:41.468755 Set Vref, RX VrefLevel [Byte0]: 69
7921 12:15:41.471451 [Byte1]: 69
7922 12:15:41.476139
7923 12:15:41.476655 Set Vref, RX VrefLevel [Byte0]: 70
7924 12:15:41.479214 [Byte1]: 70
7925 12:15:41.483447
7926 12:15:41.483960 Set Vref, RX VrefLevel [Byte0]: 71
7927 12:15:41.486382 [Byte1]: 71
7928 12:15:41.491368
7929 12:15:41.491882 Set Vref, RX VrefLevel [Byte0]: 72
7930 12:15:41.494155 [Byte1]: 72
7931 12:15:41.498866
7932 12:15:41.499381 Set Vref, RX VrefLevel [Byte0]: 73
7933 12:15:41.502004 [Byte1]: 73
7934 12:15:41.506248
7935 12:15:41.506764 Set Vref, RX VrefLevel [Byte0]: 74
7936 12:15:41.509469 [Byte1]: 74
7937 12:15:41.514120
7938 12:15:41.514645 Set Vref, RX VrefLevel [Byte0]: 75
7939 12:15:41.517159 [Byte1]: 75
7940 12:15:41.521313
7941 12:15:41.521863 Set Vref, RX VrefLevel [Byte0]: 76
7942 12:15:41.525041 [Byte1]: 76
7943 12:15:41.529439
7944 12:15:41.529991 Final RX Vref Byte 0 = 64 to rank0
7945 12:15:41.532335 Final RX Vref Byte 1 = 60 to rank0
7946 12:15:41.535676 Final RX Vref Byte 0 = 64 to rank1
7947 12:15:41.538933 Final RX Vref Byte 1 = 60 to rank1==
7948 12:15:41.542228 Dram Type= 6, Freq= 0, CH_0, rank 0
7949 12:15:41.549282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7950 12:15:41.549842 ==
7951 12:15:41.550176 DQS Delay:
7952 12:15:41.551853 DQS0 = 0, DQS1 = 0
7953 12:15:41.552263 DQM Delay:
7954 12:15:41.555201 DQM0 = 126, DQM1 = 119
7955 12:15:41.555614 DQ Delay:
7956 12:15:41.558282 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7957 12:15:41.562441 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7958 12:15:41.565088 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7959 12:15:41.568499 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7960 12:15:41.568910
7961 12:15:41.569298
7962 12:15:41.569648
7963 12:15:41.571640 [DramC_TX_OE_Calibration] TA2
7964 12:15:41.575146 Original DQ_B0 (3 6) =30, OEN = 27
7965 12:15:41.578175 Original DQ_B1 (3 6) =30, OEN = 27
7966 12:15:41.581583 24, 0x0, End_B0=24 End_B1=24
7967 12:15:41.584987 25, 0x0, End_B0=25 End_B1=25
7968 12:15:41.585552 26, 0x0, End_B0=26 End_B1=26
7969 12:15:41.588393 27, 0x0, End_B0=27 End_B1=27
7970 12:15:41.591899 28, 0x0, End_B0=28 End_B1=28
7971 12:15:41.594684 29, 0x0, End_B0=29 End_B1=29
7972 12:15:41.595107 30, 0x0, End_B0=30 End_B1=30
7973 12:15:41.598722 31, 0x4101, End_B0=30 End_B1=30
7974 12:15:41.601526 Byte0 end_step=30 best_step=27
7975 12:15:41.605016 Byte1 end_step=30 best_step=27
7976 12:15:41.608640 Byte0 TX OE(2T, 0.5T) = (3, 3)
7977 12:15:41.611348 Byte1 TX OE(2T, 0.5T) = (3, 3)
7978 12:15:41.611766
7979 12:15:41.612094
7980 12:15:41.618406 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
7981 12:15:41.621560 CH0 RK0: MR19=303, MR18=1515
7982 12:15:41.627899 CH0_RK0: MR19=0x303, MR18=0x1515, DQSOSC=399, MR23=63, INC=23, DEC=15
7983 12:15:41.628408
7984 12:15:41.631360 ----->DramcWriteLeveling(PI) begin...
7985 12:15:41.631782 ==
7986 12:15:41.634415 Dram Type= 6, Freq= 0, CH_0, rank 1
7987 12:15:41.637663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 12:15:41.638081 ==
7989 12:15:41.641208 Write leveling (Byte 0): 35 => 35
7990 12:15:41.644840 Write leveling (Byte 1): 26 => 26
7991 12:15:41.648442 DramcWriteLeveling(PI) end<-----
7992 12:15:41.648950
7993 12:15:41.649281 ==
7994 12:15:41.651055 Dram Type= 6, Freq= 0, CH_0, rank 1
7995 12:15:41.654497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7996 12:15:41.657824 ==
7997 12:15:41.658238 [Gating] SW mode calibration
7998 12:15:41.664658 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7999 12:15:41.671016 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8000 12:15:41.674259 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 12:15:41.681294 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 12:15:41.684667 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 12:15:41.687936 1 4 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
8004 12:15:41.693989 1 4 16 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
8005 12:15:41.697149 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8006 12:15:41.701000 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8007 12:15:41.707593 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 12:15:41.710967 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 12:15:41.713874 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8010 12:15:41.720805 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
8011 12:15:41.723719 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8012 12:15:41.727463 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8013 12:15:41.733614 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8014 12:15:41.737279 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 12:15:41.740047 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 12:15:41.747138 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 12:15:41.750072 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 12:15:41.753729 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8019 12:15:41.759969 1 6 12 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8020 12:15:41.763526 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (1 1) (0 0)
8021 12:15:41.766555 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8022 12:15:41.773149 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 12:15:41.776782 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 12:15:41.779964 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 12:15:41.786500 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 12:15:41.790054 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8027 12:15:41.793237 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8028 12:15:41.799625 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8029 12:15:41.803046 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8030 12:15:41.806384 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 12:15:41.812939 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 12:15:41.816301 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 12:15:41.819605 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 12:15:41.826234 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 12:15:41.829600 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 12:15:41.832471 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 12:15:41.839214 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 12:15:41.842341 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 12:15:41.845932 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 12:15:41.852400 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 12:15:41.855492 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 12:15:41.858783 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8043 12:15:41.865831 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8044 12:15:41.869047 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8045 12:15:41.872309 Total UI for P1: 0, mck2ui 16
8046 12:15:41.875953 best dqsien dly found for B0: ( 1, 9, 10)
8047 12:15:41.879009 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8048 12:15:41.885706 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 12:15:41.886226 Total UI for P1: 0, mck2ui 16
8050 12:15:41.892577 best dqsien dly found for B1: ( 1, 9, 18)
8051 12:15:41.895287 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8052 12:15:41.898896 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8053 12:15:41.899417
8054 12:15:41.902392 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8055 12:15:41.905711 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8056 12:15:41.908702 [Gating] SW calibration Done
8057 12:15:41.909223 ==
8058 12:15:41.912002 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 12:15:41.914992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 12:15:41.915414 ==
8061 12:15:41.918438 RX Vref Scan: 0
8062 12:15:41.918952
8063 12:15:41.919279 RX Vref 0 -> 0, step: 1
8064 12:15:41.921711
8065 12:15:41.922120 RX Delay 0 -> 252, step: 8
8066 12:15:41.925136 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8067 12:15:41.931928 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8068 12:15:41.935108 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8069 12:15:41.938193 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8070 12:15:41.941401 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8071 12:15:41.944698 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8072 12:15:41.951456 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8073 12:15:41.954878 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8074 12:15:41.958167 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8075 12:15:41.961561 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8076 12:15:41.967848 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8077 12:15:41.971258 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8078 12:15:41.974566 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8079 12:15:41.977850 iDelay=200, Bit 13, Center 123 (64 ~ 183) 120
8080 12:15:41.980760 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8081 12:15:41.987691 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8082 12:15:41.988213 ==
8083 12:15:41.991295 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 12:15:41.994532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 12:15:41.995066 ==
8086 12:15:41.995467 DQS Delay:
8087 12:15:41.998008 DQS0 = 0, DQS1 = 0
8088 12:15:41.998525 DQM Delay:
8089 12:15:42.000977 DQM0 = 127, DQM1 = 120
8090 12:15:42.001525 DQ Delay:
8091 12:15:42.004389 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8092 12:15:42.007688 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8093 12:15:42.011057 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8094 12:15:42.017679 DQ12 =127, DQ13 =123, DQ14 =131, DQ15 =127
8095 12:15:42.018228
8096 12:15:42.018556
8097 12:15:42.018857 ==
8098 12:15:42.020917 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 12:15:42.023916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 12:15:42.024438 ==
8101 12:15:42.024772
8102 12:15:42.025071
8103 12:15:42.026966 TX Vref Scan disable
8104 12:15:42.027379 == TX Byte 0 ==
8105 12:15:42.034051 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8106 12:15:42.037336 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8107 12:15:42.037894 == TX Byte 1 ==
8108 12:15:42.043857 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8109 12:15:42.047308 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8110 12:15:42.047837 ==
8111 12:15:42.050481 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 12:15:42.053939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 12:15:42.054464 ==
8114 12:15:42.069738
8115 12:15:42.072863 TX Vref early break, caculate TX vref
8116 12:15:42.076610 TX Vref=16, minBit 8, minWin=21, winSum=367
8117 12:15:42.079811 TX Vref=18, minBit 9, minWin=22, winSum=377
8118 12:15:42.082910 TX Vref=20, minBit 8, minWin=22, winSum=382
8119 12:15:42.086352 TX Vref=22, minBit 10, minWin=23, winSum=396
8120 12:15:42.089716 TX Vref=24, minBit 8, minWin=24, winSum=401
8121 12:15:42.096055 TX Vref=26, minBit 8, minWin=24, winSum=405
8122 12:15:42.099366 TX Vref=28, minBit 8, minWin=24, winSum=410
8123 12:15:42.102586 TX Vref=30, minBit 8, minWin=23, winSum=410
8124 12:15:42.106467 TX Vref=32, minBit 8, minWin=23, winSum=397
8125 12:15:42.109646 TX Vref=34, minBit 8, minWin=23, winSum=390
8126 12:15:42.113126 TX Vref=36, minBit 8, minWin=22, winSum=382
8127 12:15:42.119937 [TxChooseVref] Worse bit 8, Min win 24, Win sum 410, Final Vref 28
8128 12:15:42.120456
8129 12:15:42.123226 Final TX Range 0 Vref 28
8130 12:15:42.123759
8131 12:15:42.124120 ==
8132 12:15:42.126170 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 12:15:42.129642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 12:15:42.130224 ==
8135 12:15:42.130561
8136 12:15:42.130867
8137 12:15:42.132691 TX Vref Scan disable
8138 12:15:42.139468 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8139 12:15:42.139985 == TX Byte 0 ==
8140 12:15:42.142683 u2DelayCellOfst[0]=11 cells (3 PI)
8141 12:15:42.146000 u2DelayCellOfst[1]=18 cells (5 PI)
8142 12:15:42.149562 u2DelayCellOfst[2]=11 cells (3 PI)
8143 12:15:42.152621 u2DelayCellOfst[3]=15 cells (4 PI)
8144 12:15:42.155797 u2DelayCellOfst[4]=7 cells (2 PI)
8145 12:15:42.159182 u2DelayCellOfst[5]=0 cells (0 PI)
8146 12:15:42.162199 u2DelayCellOfst[6]=18 cells (5 PI)
8147 12:15:42.165997 u2DelayCellOfst[7]=18 cells (5 PI)
8148 12:15:42.168900 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8149 12:15:42.172199 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8150 12:15:42.175859 == TX Byte 1 ==
8151 12:15:42.178707 u2DelayCellOfst[8]=0 cells (0 PI)
8152 12:15:42.182144 u2DelayCellOfst[9]=0 cells (0 PI)
8153 12:15:42.185512 u2DelayCellOfst[10]=7 cells (2 PI)
8154 12:15:42.185934 u2DelayCellOfst[11]=3 cells (1 PI)
8155 12:15:42.189137 u2DelayCellOfst[12]=15 cells (4 PI)
8156 12:15:42.192505 u2DelayCellOfst[13]=11 cells (3 PI)
8157 12:15:42.195533 u2DelayCellOfst[14]=15 cells (4 PI)
8158 12:15:42.199042 u2DelayCellOfst[15]=11 cells (3 PI)
8159 12:15:42.205710 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8160 12:15:42.208670 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8161 12:15:42.209097 DramC Write-DBI on
8162 12:15:42.212270 ==
8163 12:15:42.215550 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 12:15:42.218469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 12:15:42.219014 ==
8166 12:15:42.219379
8167 12:15:42.219686
8168 12:15:42.221802 TX Vref Scan disable
8169 12:15:42.222215 == TX Byte 0 ==
8170 12:15:42.228357 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8171 12:15:42.228992 == TX Byte 1 ==
8172 12:15:42.231703 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8173 12:15:42.235410 DramC Write-DBI off
8174 12:15:42.235981
8175 12:15:42.236481 [DATLAT]
8176 12:15:42.238498 Freq=1600, CH0 RK1
8177 12:15:42.238912
8178 12:15:42.239237 DATLAT Default: 0xf
8179 12:15:42.241464 0, 0xFFFF, sum = 0
8180 12:15:42.241927 1, 0xFFFF, sum = 0
8181 12:15:42.244973 2, 0xFFFF, sum = 0
8182 12:15:42.245391 3, 0xFFFF, sum = 0
8183 12:15:42.248442 4, 0xFFFF, sum = 0
8184 12:15:42.249097 5, 0xFFFF, sum = 0
8185 12:15:42.251337 6, 0xFFFF, sum = 0
8186 12:15:42.254677 7, 0xFFFF, sum = 0
8187 12:15:42.255093 8, 0xFFFF, sum = 0
8188 12:15:42.258301 9, 0xFFFF, sum = 0
8189 12:15:42.258721 10, 0xFFFF, sum = 0
8190 12:15:42.261772 11, 0xFFFF, sum = 0
8191 12:15:42.262195 12, 0xFFFF, sum = 0
8192 12:15:42.264880 13, 0xCFFF, sum = 0
8193 12:15:42.265297 14, 0x0, sum = 1
8194 12:15:42.268145 15, 0x0, sum = 2
8195 12:15:42.268561 16, 0x0, sum = 3
8196 12:15:42.271578 17, 0x0, sum = 4
8197 12:15:42.272009 best_step = 15
8198 12:15:42.272338
8199 12:15:42.272645 ==
8200 12:15:42.274969 Dram Type= 6, Freq= 0, CH_0, rank 1
8201 12:15:42.278156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8202 12:15:42.281365 ==
8203 12:15:42.281817 RX Vref Scan: 0
8204 12:15:42.282145
8205 12:15:42.284758 RX Vref 0 -> 0, step: 1
8206 12:15:42.285281
8207 12:15:42.285676 RX Delay 3 -> 252, step: 4
8208 12:15:42.292149 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8209 12:15:42.295318 iDelay=191, Bit 1, Center 126 (75 ~ 178) 104
8210 12:15:42.298847 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8211 12:15:42.301813 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8212 12:15:42.308754 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8213 12:15:42.312103 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8214 12:15:42.315125 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8215 12:15:42.318715 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8216 12:15:42.322087 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8217 12:15:42.325117 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8218 12:15:42.332219 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8219 12:15:42.335282 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8220 12:15:42.338242 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8221 12:15:42.341829 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8222 12:15:42.348261 iDelay=191, Bit 14, Center 126 (67 ~ 186) 120
8223 12:15:42.351482 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8224 12:15:42.351901 ==
8225 12:15:42.354869 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 12:15:42.358125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 12:15:42.358547 ==
8228 12:15:42.361426 DQS Delay:
8229 12:15:42.361870 DQS0 = 0, DQS1 = 0
8230 12:15:42.362200 DQM Delay:
8231 12:15:42.365150 DQM0 = 124, DQM1 = 117
8232 12:15:42.365738 DQ Delay:
8233 12:15:42.368288 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8234 12:15:42.371525 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8235 12:15:42.374741 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8236 12:15:42.381531 DQ12 =124, DQ13 =122, DQ14 =126, DQ15 =124
8237 12:15:42.382060
8238 12:15:42.382395
8239 12:15:42.382773
8240 12:15:42.384823 [DramC_TX_OE_Calibration] TA2
8241 12:15:42.385241 Original DQ_B0 (3 6) =30, OEN = 27
8242 12:15:42.387892 Original DQ_B1 (3 6) =30, OEN = 27
8243 12:15:42.391241 24, 0x0, End_B0=24 End_B1=24
8244 12:15:42.394540 25, 0x0, End_B0=25 End_B1=25
8245 12:15:42.398159 26, 0x0, End_B0=26 End_B1=26
8246 12:15:42.401620 27, 0x0, End_B0=27 End_B1=27
8247 12:15:42.402160 28, 0x0, End_B0=28 End_B1=28
8248 12:15:42.404715 29, 0x0, End_B0=29 End_B1=29
8249 12:15:42.408238 30, 0x0, End_B0=30 End_B1=30
8250 12:15:42.411583 31, 0x4141, End_B0=30 End_B1=30
8251 12:15:42.414836 Byte0 end_step=30 best_step=27
8252 12:15:42.415342 Byte1 end_step=30 best_step=27
8253 12:15:42.417960 Byte0 TX OE(2T, 0.5T) = (3, 3)
8254 12:15:42.421766 Byte1 TX OE(2T, 0.5T) = (3, 3)
8255 12:15:42.422291
8256 12:15:42.422623
8257 12:15:42.431490 [DQSOSCAuto] RK1, (LSB)MR18= 0x2411, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
8258 12:15:42.432017 CH0 RK1: MR19=303, MR18=2411
8259 12:15:42.438140 CH0_RK1: MR19=0x303, MR18=0x2411, DQSOSC=391, MR23=63, INC=24, DEC=16
8260 12:15:42.441344 [RxdqsGatingPostProcess] freq 1600
8261 12:15:42.447728 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8262 12:15:42.451377 best DQS0 dly(2T, 0.5T) = (1, 1)
8263 12:15:42.454405 best DQS1 dly(2T, 0.5T) = (1, 1)
8264 12:15:42.457832 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8265 12:15:42.461080 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8266 12:15:42.464113 best DQS0 dly(2T, 0.5T) = (1, 1)
8267 12:15:42.464562 best DQS1 dly(2T, 0.5T) = (1, 1)
8268 12:15:42.467469 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8269 12:15:42.470640 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8270 12:15:42.473730 Pre-setting of DQS Precalculation
8271 12:15:42.480463 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8272 12:15:42.480964 ==
8273 12:15:42.484091 Dram Type= 6, Freq= 0, CH_1, rank 0
8274 12:15:42.487590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8275 12:15:42.488117 ==
8276 12:15:42.494138 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8277 12:15:42.497072 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8278 12:15:42.500731 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8279 12:15:42.507061 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8280 12:15:42.516827 [CA 0] Center 41 (12~71) winsize 60
8281 12:15:42.519608 [CA 1] Center 42 (13~72) winsize 60
8282 12:15:42.523138 [CA 2] Center 37 (9~66) winsize 58
8283 12:15:42.526279 [CA 3] Center 36 (7~66) winsize 60
8284 12:15:42.529905 [CA 4] Center 36 (7~66) winsize 60
8285 12:15:42.533000 [CA 5] Center 36 (7~66) winsize 60
8286 12:15:42.533557
8287 12:15:42.536381 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8288 12:15:42.536896
8289 12:15:42.539902 [CATrainingPosCal] consider 1 rank data
8290 12:15:42.543268 u2DelayCellTimex100 = 258/100 ps
8291 12:15:42.546319 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8292 12:15:42.552701 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8293 12:15:42.555850 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8294 12:15:42.559322 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8295 12:15:42.562793 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8296 12:15:42.566055 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8297 12:15:42.566487
8298 12:15:42.569432 CA PerBit enable=1, Macro0, CA PI delay=36
8299 12:15:42.569990
8300 12:15:42.572817 [CBTSetCACLKResult] CA Dly = 36
8301 12:15:42.576079 CS Dly: 9 (0~40)
8302 12:15:42.580218 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8303 12:15:42.582578 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8304 12:15:42.583009 ==
8305 12:15:42.586149 Dram Type= 6, Freq= 0, CH_1, rank 1
8306 12:15:42.589196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 12:15:42.592386 ==
8308 12:15:42.595853 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8309 12:15:42.599016 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8310 12:15:42.605847 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8311 12:15:42.609057 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8312 12:15:42.619808 [CA 0] Center 42 (13~71) winsize 59
8313 12:15:42.622850 [CA 1] Center 42 (12~72) winsize 61
8314 12:15:42.626049 [CA 2] Center 37 (8~67) winsize 60
8315 12:15:42.629632 [CA 3] Center 36 (7~66) winsize 60
8316 12:15:42.632905 [CA 4] Center 37 (7~67) winsize 61
8317 12:15:42.636108 [CA 5] Center 36 (6~66) winsize 61
8318 12:15:42.636620
8319 12:15:42.639638 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8320 12:15:42.640144
8321 12:15:42.642783 [CATrainingPosCal] consider 2 rank data
8322 12:15:42.646046 u2DelayCellTimex100 = 258/100 ps
8323 12:15:42.649698 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8324 12:15:42.656453 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8325 12:15:42.659138 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8326 12:15:42.662774 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8327 12:15:42.666092 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8328 12:15:42.669399 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8329 12:15:42.669961
8330 12:15:42.672587 CA PerBit enable=1, Macro0, CA PI delay=36
8331 12:15:42.673002
8332 12:15:42.676208 [CBTSetCACLKResult] CA Dly = 36
8333 12:15:42.679145 CS Dly: 10 (0~43)
8334 12:15:42.682213 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8335 12:15:42.686160 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8336 12:15:42.686667
8337 12:15:42.689147 ----->DramcWriteLeveling(PI) begin...
8338 12:15:42.689704 ==
8339 12:15:42.692351 Dram Type= 6, Freq= 0, CH_1, rank 0
8340 12:15:42.698823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 12:15:42.699347 ==
8342 12:15:42.702068 Write leveling (Byte 0): 25 => 25
8343 12:15:42.702480 Write leveling (Byte 1): 29 => 29
8344 12:15:42.705944 DramcWriteLeveling(PI) end<-----
8345 12:15:42.706457
8346 12:15:42.709412 ==
8347 12:15:42.709988 Dram Type= 6, Freq= 0, CH_1, rank 0
8348 12:15:42.715361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8349 12:15:42.715857 ==
8350 12:15:42.719118 [Gating] SW mode calibration
8351 12:15:42.725651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8352 12:15:42.728524 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8353 12:15:42.735476 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 12:15:42.738614 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 12:15:42.741902 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 12:15:42.748642 1 4 12 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
8357 12:15:42.751730 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8358 12:15:42.754959 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 12:15:42.762072 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 12:15:42.765370 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 12:15:42.768896 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 12:15:42.774841 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 12:15:42.778369 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 12:15:42.781741 1 5 12 | B1->B0 | 3333 3434 | 1 0 | (0 0) (0 1)
8365 12:15:42.788737 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (1 0) (1 0)
8366 12:15:42.791553 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 12:15:42.794940 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 12:15:42.801631 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 12:15:42.805213 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 12:15:42.808372 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 12:15:42.811805 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 12:15:42.818361 1 6 12 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
8373 12:15:42.821850 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8374 12:15:42.825196 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 12:15:42.831629 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 12:15:42.834857 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 12:15:42.838116 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 12:15:42.844805 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 12:15:42.848325 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 12:15:42.851373 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 12:15:42.857821 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8382 12:15:42.861188 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 12:15:42.864716 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 12:15:42.871128 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 12:15:42.874181 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 12:15:42.877619 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 12:15:42.884359 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 12:15:42.888042 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 12:15:42.891177 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 12:15:42.897776 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 12:15:42.901120 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 12:15:42.904536 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 12:15:42.911308 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 12:15:42.914041 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 12:15:42.917294 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 12:15:42.924258 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8397 12:15:42.927613 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8398 12:15:42.930893 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8399 12:15:42.937527 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 12:15:42.940978 Total UI for P1: 0, mck2ui 16
8401 12:15:42.943654 best dqsien dly found for B0: ( 1, 9, 16)
8402 12:15:42.944089 Total UI for P1: 0, mck2ui 16
8403 12:15:42.950497 best dqsien dly found for B1: ( 1, 9, 16)
8404 12:15:42.954101 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8405 12:15:42.957292 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8406 12:15:42.957853
8407 12:15:42.960195 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8408 12:15:42.963574 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8409 12:15:42.967033 [Gating] SW calibration Done
8410 12:15:42.967453 ==
8411 12:15:42.970139 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 12:15:42.973614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 12:15:42.974032 ==
8414 12:15:42.976956 RX Vref Scan: 0
8415 12:15:42.977363
8416 12:15:42.977730 RX Vref 0 -> 0, step: 1
8417 12:15:42.980282
8418 12:15:42.980688 RX Delay 0 -> 252, step: 8
8419 12:15:42.987117 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8420 12:15:42.990022 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8421 12:15:42.993432 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8422 12:15:42.996641 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8423 12:15:43.000163 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8424 12:15:43.006792 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8425 12:15:43.010034 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8426 12:15:43.013469 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8427 12:15:43.016742 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8428 12:15:43.020067 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8429 12:15:43.026799 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8430 12:15:43.029836 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8431 12:15:43.033152 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8432 12:15:43.036850 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8433 12:15:43.040258 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8434 12:15:43.046466 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8435 12:15:43.046982 ==
8436 12:15:43.050054 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 12:15:43.053523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 12:15:43.054038 ==
8439 12:15:43.054366 DQS Delay:
8440 12:15:43.057031 DQS0 = 0, DQS1 = 0
8441 12:15:43.057589 DQM Delay:
8442 12:15:43.059884 DQM0 = 132, DQM1 = 126
8443 12:15:43.060398 DQ Delay:
8444 12:15:43.063250 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8445 12:15:43.066477 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8446 12:15:43.069880 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8447 12:15:43.072794 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8448 12:15:43.073206
8449 12:15:43.076124
8450 12:15:43.076533 ==
8451 12:15:43.079564 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 12:15:43.083080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 12:15:43.083593 ==
8454 12:15:43.083956
8455 12:15:43.084262
8456 12:15:43.086060 TX Vref Scan disable
8457 12:15:43.086474 == TX Byte 0 ==
8458 12:15:43.092937 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8459 12:15:43.096092 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8460 12:15:43.096504 == TX Byte 1 ==
8461 12:15:43.102948 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8462 12:15:43.106073 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8463 12:15:43.106485 ==
8464 12:15:43.109368 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 12:15:43.112937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 12:15:43.113509 ==
8467 12:15:43.126038
8468 12:15:43.129194 TX Vref early break, caculate TX vref
8469 12:15:43.132826 TX Vref=16, minBit 11, minWin=20, winSum=362
8470 12:15:43.136160 TX Vref=18, minBit 11, minWin=21, winSum=374
8471 12:15:43.139481 TX Vref=20, minBit 5, minWin=23, winSum=383
8472 12:15:43.142642 TX Vref=22, minBit 11, minWin=22, winSum=392
8473 12:15:43.146224 TX Vref=24, minBit 10, minWin=24, winSum=403
8474 12:15:43.152607 TX Vref=26, minBit 12, minWin=24, winSum=413
8475 12:15:43.155751 TX Vref=28, minBit 5, minWin=25, winSum=414
8476 12:15:43.159594 TX Vref=30, minBit 1, minWin=25, winSum=416
8477 12:15:43.162828 TX Vref=32, minBit 5, minWin=24, winSum=407
8478 12:15:43.166059 TX Vref=34, minBit 9, minWin=22, winSum=393
8479 12:15:43.172660 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 30
8480 12:15:43.173170
8481 12:15:43.175859 Final TX Range 0 Vref 30
8482 12:15:43.176270
8483 12:15:43.176589 ==
8484 12:15:43.179068 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 12:15:43.182366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 12:15:43.182819 ==
8487 12:15:43.183147
8488 12:15:43.183449
8489 12:15:43.185654 TX Vref Scan disable
8490 12:15:43.192663 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8491 12:15:43.193175 == TX Byte 0 ==
8492 12:15:43.196112 u2DelayCellOfst[0]=22 cells (6 PI)
8493 12:15:43.198891 u2DelayCellOfst[1]=15 cells (4 PI)
8494 12:15:43.202713 u2DelayCellOfst[2]=0 cells (0 PI)
8495 12:15:43.205824 u2DelayCellOfst[3]=7 cells (2 PI)
8496 12:15:43.209270 u2DelayCellOfst[4]=7 cells (2 PI)
8497 12:15:43.212747 u2DelayCellOfst[5]=22 cells (6 PI)
8498 12:15:43.215715 u2DelayCellOfst[6]=22 cells (6 PI)
8499 12:15:43.219044 u2DelayCellOfst[7]=7 cells (2 PI)
8500 12:15:43.222448 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8501 12:15:43.225630 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8502 12:15:43.229290 == TX Byte 1 ==
8503 12:15:43.229842 u2DelayCellOfst[8]=0 cells (0 PI)
8504 12:15:43.232614 u2DelayCellOfst[9]=7 cells (2 PI)
8505 12:15:43.235310 u2DelayCellOfst[10]=11 cells (3 PI)
8506 12:15:43.238808 u2DelayCellOfst[11]=7 cells (2 PI)
8507 12:15:43.242226 u2DelayCellOfst[12]=15 cells (4 PI)
8508 12:15:43.245877 u2DelayCellOfst[13]=18 cells (5 PI)
8509 12:15:43.248705 u2DelayCellOfst[14]=18 cells (5 PI)
8510 12:15:43.252056 u2DelayCellOfst[15]=18 cells (5 PI)
8511 12:15:43.255852 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8512 12:15:43.262086 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8513 12:15:43.262695 DramC Write-DBI on
8514 12:15:43.263115 ==
8515 12:15:43.265302 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 12:15:43.271987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 12:15:43.272608 ==
8518 12:15:43.272944
8519 12:15:43.273248
8520 12:15:43.273593 TX Vref Scan disable
8521 12:15:43.275504 == TX Byte 0 ==
8522 12:15:43.278914 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8523 12:15:43.282158 == TX Byte 1 ==
8524 12:15:43.285845 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8525 12:15:43.289005 DramC Write-DBI off
8526 12:15:43.289418
8527 12:15:43.289781 [DATLAT]
8528 12:15:43.290092 Freq=1600, CH1 RK0
8529 12:15:43.290397
8530 12:15:43.292238 DATLAT Default: 0xf
8531 12:15:43.292650 0, 0xFFFF, sum = 0
8532 12:15:43.295458 1, 0xFFFF, sum = 0
8533 12:15:43.296170 2, 0xFFFF, sum = 0
8534 12:15:43.298768 3, 0xFFFF, sum = 0
8535 12:15:43.302133 4, 0xFFFF, sum = 0
8536 12:15:43.302552 5, 0xFFFF, sum = 0
8537 12:15:43.305799 6, 0xFFFF, sum = 0
8538 12:15:43.306250 7, 0xFFFF, sum = 0
8539 12:15:43.308925 8, 0xFFFF, sum = 0
8540 12:15:43.309342 9, 0xFFFF, sum = 0
8541 12:15:43.312389 10, 0xFFFF, sum = 0
8542 12:15:43.313211 11, 0xFFFF, sum = 0
8543 12:15:43.315865 12, 0xFFFF, sum = 0
8544 12:15:43.316284 13, 0x8FFF, sum = 0
8545 12:15:43.318890 14, 0x0, sum = 1
8546 12:15:43.319309 15, 0x0, sum = 2
8547 12:15:43.322391 16, 0x0, sum = 3
8548 12:15:43.322880 17, 0x0, sum = 4
8549 12:15:43.325680 best_step = 15
8550 12:15:43.326092
8551 12:15:43.326417 ==
8552 12:15:43.329156 Dram Type= 6, Freq= 0, CH_1, rank 0
8553 12:15:43.332250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8554 12:15:43.332668 ==
8555 12:15:43.332997 RX Vref Scan: 1
8556 12:15:43.335625
8557 12:15:43.336037 Set Vref Range= 24 -> 127
8558 12:15:43.336362
8559 12:15:43.338731 RX Vref 24 -> 127, step: 1
8560 12:15:43.339233
8561 12:15:43.342005 RX Delay 11 -> 252, step: 4
8562 12:15:43.342416
8563 12:15:43.345278 Set Vref, RX VrefLevel [Byte0]: 24
8564 12:15:43.349087 [Byte1]: 24
8565 12:15:43.349850
8566 12:15:43.352201 Set Vref, RX VrefLevel [Byte0]: 25
8567 12:15:43.355761 [Byte1]: 25
8568 12:15:43.356274
8569 12:15:43.359077 Set Vref, RX VrefLevel [Byte0]: 26
8570 12:15:43.361859 [Byte1]: 26
8571 12:15:43.365964
8572 12:15:43.366374 Set Vref, RX VrefLevel [Byte0]: 27
8573 12:15:43.369671 [Byte1]: 27
8574 12:15:43.373633
8575 12:15:43.374049 Set Vref, RX VrefLevel [Byte0]: 28
8576 12:15:43.376829 [Byte1]: 28
8577 12:15:43.381163
8578 12:15:43.381640 Set Vref, RX VrefLevel [Byte0]: 29
8579 12:15:43.384481 [Byte1]: 29
8580 12:15:43.388922
8581 12:15:43.389332 Set Vref, RX VrefLevel [Byte0]: 30
8582 12:15:43.392011 [Byte1]: 30
8583 12:15:43.396325
8584 12:15:43.396738 Set Vref, RX VrefLevel [Byte0]: 31
8585 12:15:43.399460 [Byte1]: 31
8586 12:15:43.404426
8587 12:15:43.404938 Set Vref, RX VrefLevel [Byte0]: 32
8588 12:15:43.407427 [Byte1]: 32
8589 12:15:43.411698
8590 12:15:43.412230 Set Vref, RX VrefLevel [Byte0]: 33
8591 12:15:43.415110 [Byte1]: 33
8592 12:15:43.419096
8593 12:15:43.419509 Set Vref, RX VrefLevel [Byte0]: 34
8594 12:15:43.422882 [Byte1]: 34
8595 12:15:43.427259
8596 12:15:43.427768 Set Vref, RX VrefLevel [Byte0]: 35
8597 12:15:43.430443 [Byte1]: 35
8598 12:15:43.434488
8599 12:15:43.434905 Set Vref, RX VrefLevel [Byte0]: 36
8600 12:15:43.437811 [Byte1]: 36
8601 12:15:43.442411
8602 12:15:43.442939 Set Vref, RX VrefLevel [Byte0]: 37
8603 12:15:43.445688 [Byte1]: 37
8604 12:15:43.450112
8605 12:15:43.450619 Set Vref, RX VrefLevel [Byte0]: 38
8606 12:15:43.453128 [Byte1]: 38
8607 12:15:43.457732
8608 12:15:43.458237 Set Vref, RX VrefLevel [Byte0]: 39
8609 12:15:43.460950 [Byte1]: 39
8610 12:15:43.465207
8611 12:15:43.465764 Set Vref, RX VrefLevel [Byte0]: 40
8612 12:15:43.468733 [Byte1]: 40
8613 12:15:43.472795
8614 12:15:43.473302 Set Vref, RX VrefLevel [Byte0]: 41
8615 12:15:43.475862 [Byte1]: 41
8616 12:15:43.480700
8617 12:15:43.481211 Set Vref, RX VrefLevel [Byte0]: 42
8618 12:15:43.483926 [Byte1]: 42
8619 12:15:43.488191
8620 12:15:43.488701 Set Vref, RX VrefLevel [Byte0]: 43
8621 12:15:43.491562 [Byte1]: 43
8622 12:15:43.495666
8623 12:15:43.496193 Set Vref, RX VrefLevel [Byte0]: 44
8624 12:15:43.498662 [Byte1]: 44
8625 12:15:43.503071
8626 12:15:43.503636 Set Vref, RX VrefLevel [Byte0]: 45
8627 12:15:43.506250 [Byte1]: 45
8628 12:15:43.510785
8629 12:15:43.511357 Set Vref, RX VrefLevel [Byte0]: 46
8630 12:15:43.514185 [Byte1]: 46
8631 12:15:43.518080
8632 12:15:43.518505 Set Vref, RX VrefLevel [Byte0]: 47
8633 12:15:43.521601 [Byte1]: 47
8634 12:15:43.526036
8635 12:15:43.526565 Set Vref, RX VrefLevel [Byte0]: 48
8636 12:15:43.529298 [Byte1]: 48
8637 12:15:43.533869
8638 12:15:43.534393 Set Vref, RX VrefLevel [Byte0]: 49
8639 12:15:43.536946 [Byte1]: 49
8640 12:15:43.541413
8641 12:15:43.541993 Set Vref, RX VrefLevel [Byte0]: 50
8642 12:15:43.544663 [Byte1]: 50
8643 12:15:43.549192
8644 12:15:43.549770 Set Vref, RX VrefLevel [Byte0]: 51
8645 12:15:43.552147 [Byte1]: 51
8646 12:15:43.556511
8647 12:15:43.557037 Set Vref, RX VrefLevel [Byte0]: 52
8648 12:15:43.559542 [Byte1]: 52
8649 12:15:43.563980
8650 12:15:43.564405 Set Vref, RX VrefLevel [Byte0]: 53
8651 12:15:43.567494 [Byte1]: 53
8652 12:15:43.571972
8653 12:15:43.572497 Set Vref, RX VrefLevel [Byte0]: 54
8654 12:15:43.575075 [Byte1]: 54
8655 12:15:43.579285
8656 12:15:43.579706 Set Vref, RX VrefLevel [Byte0]: 55
8657 12:15:43.582630 [Byte1]: 55
8658 12:15:43.587144
8659 12:15:43.587669 Set Vref, RX VrefLevel [Byte0]: 56
8660 12:15:43.590092 [Byte1]: 56
8661 12:15:43.594322
8662 12:15:43.594745 Set Vref, RX VrefLevel [Byte0]: 57
8663 12:15:43.597780 [Byte1]: 57
8664 12:15:43.602241
8665 12:15:43.602792 Set Vref, RX VrefLevel [Byte0]: 58
8666 12:15:43.605360 [Byte1]: 58
8667 12:15:43.609702
8668 12:15:43.610214 Set Vref, RX VrefLevel [Byte0]: 59
8669 12:15:43.613252 [Byte1]: 59
8670 12:15:43.617644
8671 12:15:43.618163 Set Vref, RX VrefLevel [Byte0]: 60
8672 12:15:43.620704 [Byte1]: 60
8673 12:15:43.624977
8674 12:15:43.625540 Set Vref, RX VrefLevel [Byte0]: 61
8675 12:15:43.628164 [Byte1]: 61
8676 12:15:43.632550
8677 12:15:43.633072 Set Vref, RX VrefLevel [Byte0]: 62
8678 12:15:43.636132 [Byte1]: 62
8679 12:15:43.640284
8680 12:15:43.640804 Set Vref, RX VrefLevel [Byte0]: 63
8681 12:15:43.643526 [Byte1]: 63
8682 12:15:43.648113
8683 12:15:43.648642 Set Vref, RX VrefLevel [Byte0]: 64
8684 12:15:43.651444 [Byte1]: 64
8685 12:15:43.655886
8686 12:15:43.656406 Set Vref, RX VrefLevel [Byte0]: 65
8687 12:15:43.659124 [Byte1]: 65
8688 12:15:43.662803
8689 12:15:43.663227 Set Vref, RX VrefLevel [Byte0]: 66
8690 12:15:43.666208 [Byte1]: 66
8691 12:15:43.670508
8692 12:15:43.671025 Set Vref, RX VrefLevel [Byte0]: 67
8693 12:15:43.673674 [Byte1]: 67
8694 12:15:43.677980
8695 12:15:43.678414 Set Vref, RX VrefLevel [Byte0]: 68
8696 12:15:43.681819 [Byte1]: 68
8697 12:15:43.685754
8698 12:15:43.686270 Set Vref, RX VrefLevel [Byte0]: 69
8699 12:15:43.688870 [Byte1]: 69
8700 12:15:43.693360
8701 12:15:43.693811 Set Vref, RX VrefLevel [Byte0]: 70
8702 12:15:43.696662 [Byte1]: 70
8703 12:15:43.700801
8704 12:15:43.701215 Set Vref, RX VrefLevel [Byte0]: 71
8705 12:15:43.704653 [Byte1]: 71
8706 12:15:43.708869
8707 12:15:43.709369 Set Vref, RX VrefLevel [Byte0]: 72
8708 12:15:43.711781 [Byte1]: 72
8709 12:15:43.716382
8710 12:15:43.716902 Final RX Vref Byte 0 = 59 to rank0
8711 12:15:43.719570 Final RX Vref Byte 1 = 54 to rank0
8712 12:15:43.723302 Final RX Vref Byte 0 = 59 to rank1
8713 12:15:43.726357 Final RX Vref Byte 1 = 54 to rank1==
8714 12:15:43.729520 Dram Type= 6, Freq= 0, CH_1, rank 0
8715 12:15:43.736077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8716 12:15:43.736592 ==
8717 12:15:43.736927 DQS Delay:
8718 12:15:43.737233 DQS0 = 0, DQS1 = 0
8719 12:15:43.739585 DQM Delay:
8720 12:15:43.740098 DQM0 = 131, DQM1 = 123
8721 12:15:43.742610 DQ Delay:
8722 12:15:43.746127 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =126
8723 12:15:43.749352 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8724 12:15:43.752793 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8725 12:15:43.756030 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8726 12:15:43.756543
8727 12:15:43.756876
8728 12:15:43.757186
8729 12:15:43.759309 [DramC_TX_OE_Calibration] TA2
8730 12:15:43.762807 Original DQ_B0 (3 6) =30, OEN = 27
8731 12:15:43.766231 Original DQ_B1 (3 6) =30, OEN = 27
8732 12:15:43.769343 24, 0x0, End_B0=24 End_B1=24
8733 12:15:43.769905 25, 0x0, End_B0=25 End_B1=25
8734 12:15:43.772763 26, 0x0, End_B0=26 End_B1=26
8735 12:15:43.776148 27, 0x0, End_B0=27 End_B1=27
8736 12:15:43.779118 28, 0x0, End_B0=28 End_B1=28
8737 12:15:43.782456 29, 0x0, End_B0=29 End_B1=29
8738 12:15:43.782876 30, 0x0, End_B0=30 End_B1=30
8739 12:15:43.786120 31, 0x4141, End_B0=30 End_B1=30
8740 12:15:43.789087 Byte0 end_step=30 best_step=27
8741 12:15:43.792616 Byte1 end_step=30 best_step=27
8742 12:15:43.795965 Byte0 TX OE(2T, 0.5T) = (3, 3)
8743 12:15:43.799036 Byte1 TX OE(2T, 0.5T) = (3, 3)
8744 12:15:43.799451
8745 12:15:43.799777
8746 12:15:43.806013 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8747 12:15:43.809172 CH1 RK0: MR19=303, MR18=A0F
8748 12:15:43.815478 CH1_RK0: MR19=0x303, MR18=0xA0F, DQSOSC=402, MR23=63, INC=22, DEC=15
8749 12:15:43.815976
8750 12:15:43.818827 ----->DramcWriteLeveling(PI) begin...
8751 12:15:43.819346 ==
8752 12:15:43.822438 Dram Type= 6, Freq= 0, CH_1, rank 1
8753 12:15:43.825925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8754 12:15:43.826439 ==
8755 12:15:43.828885 Write leveling (Byte 0): 25 => 25
8756 12:15:43.832357 Write leveling (Byte 1): 27 => 27
8757 12:15:43.835755 DramcWriteLeveling(PI) end<-----
8758 12:15:43.836268
8759 12:15:43.836598 ==
8760 12:15:43.838823 Dram Type= 6, Freq= 0, CH_1, rank 1
8761 12:15:43.842835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8762 12:15:43.843345 ==
8763 12:15:43.845559 [Gating] SW mode calibration
8764 12:15:43.852297 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8765 12:15:43.858886 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8766 12:15:43.861951 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 12:15:43.865843 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 12:15:43.872313 1 4 8 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
8769 12:15:43.875599 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8770 12:15:43.878414 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 12:15:43.885752 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 12:15:43.889151 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 12:15:43.892035 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 12:15:43.898630 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 12:15:43.901969 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 12:15:43.905367 1 5 8 | B1->B0 | 3333 2424 | 0 0 | (0 1) (1 0)
8777 12:15:43.912135 1 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8778 12:15:43.915364 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 12:15:43.918402 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 12:15:43.925286 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 12:15:43.928414 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 12:15:43.931933 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 12:15:43.938444 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 12:15:43.941517 1 6 8 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
8785 12:15:43.945161 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8786 12:15:43.951320 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 12:15:43.955324 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 12:15:43.958029 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 12:15:43.964732 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 12:15:43.968403 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 12:15:43.971470 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 12:15:43.978050 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8793 12:15:43.981261 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8794 12:15:43.984664 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 12:15:43.990974 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 12:15:43.994113 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 12:15:43.997999 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 12:15:44.004781 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 12:15:44.007967 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 12:15:44.010896 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 12:15:44.017574 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 12:15:44.021077 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 12:15:44.024162 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 12:15:44.031164 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 12:15:44.034264 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 12:15:44.037192 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 12:15:44.044027 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 12:15:44.047745 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8809 12:15:44.051224 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8810 12:15:44.057455 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 12:15:44.058031 Total UI for P1: 0, mck2ui 16
8812 12:15:44.063869 best dqsien dly found for B0: ( 1, 9, 10)
8813 12:15:44.064476 Total UI for P1: 0, mck2ui 16
8814 12:15:44.067420 best dqsien dly found for B1: ( 1, 9, 12)
8815 12:15:44.074210 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8816 12:15:44.077401 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8817 12:15:44.077947
8818 12:15:44.080151 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8819 12:15:44.083851 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8820 12:15:44.086889 [Gating] SW calibration Done
8821 12:15:44.087303 ==
8822 12:15:44.090344 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 12:15:44.093788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 12:15:44.094302 ==
8825 12:15:44.097073 RX Vref Scan: 0
8826 12:15:44.097634
8827 12:15:44.097972 RX Vref 0 -> 0, step: 1
8828 12:15:44.098285
8829 12:15:44.100384 RX Delay 0 -> 252, step: 8
8830 12:15:44.103835 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8831 12:15:44.110149 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8832 12:15:44.113997 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8833 12:15:44.117002 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8834 12:15:44.120172 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8835 12:15:44.123684 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8836 12:15:44.130077 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8837 12:15:44.133638 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8838 12:15:44.137184 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8839 12:15:44.140101 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8840 12:15:44.143486 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8841 12:15:44.150076 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8842 12:15:44.153081 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8843 12:15:44.156659 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8844 12:15:44.160139 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8845 12:15:44.166389 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8846 12:15:44.166901 ==
8847 12:15:44.169691 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 12:15:44.173308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 12:15:44.173872 ==
8850 12:15:44.174253 DQS Delay:
8851 12:15:44.176338 DQS0 = 0, DQS1 = 0
8852 12:15:44.176744 DQM Delay:
8853 12:15:44.179541 DQM0 = 129, DQM1 = 128
8854 12:15:44.179966 DQ Delay:
8855 12:15:44.183063 DQ0 =135, DQ1 =127, DQ2 =115, DQ3 =127
8856 12:15:44.186267 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8857 12:15:44.189844 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8858 12:15:44.193268 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8859 12:15:44.193845
8860 12:15:44.194174
8861 12:15:44.196132 ==
8862 12:15:44.196643 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 12:15:44.203098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 12:15:44.203612 ==
8865 12:15:44.203944
8866 12:15:44.204247
8867 12:15:44.206046 TX Vref Scan disable
8868 12:15:44.206456 == TX Byte 0 ==
8869 12:15:44.209565 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8870 12:15:44.216217 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8871 12:15:44.216722 == TX Byte 1 ==
8872 12:15:44.219181 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8873 12:15:44.225974 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8874 12:15:44.226509 ==
8875 12:15:44.229470 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 12:15:44.232565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 12:15:44.233071 ==
8878 12:15:44.246671
8879 12:15:44.250057 TX Vref early break, caculate TX vref
8880 12:15:44.253182 TX Vref=16, minBit 0, minWin=23, winSum=386
8881 12:15:44.256673 TX Vref=18, minBit 0, minWin=24, winSum=398
8882 12:15:44.260229 TX Vref=20, minBit 0, minWin=23, winSum=402
8883 12:15:44.262938 TX Vref=22, minBit 0, minWin=24, winSum=410
8884 12:15:44.266415 TX Vref=24, minBit 0, minWin=24, winSum=423
8885 12:15:44.273419 TX Vref=26, minBit 0, minWin=25, winSum=429
8886 12:15:44.276707 TX Vref=28, minBit 0, minWin=26, winSum=429
8887 12:15:44.280068 TX Vref=30, minBit 0, minWin=25, winSum=422
8888 12:15:44.283209 TX Vref=32, minBit 5, minWin=24, winSum=416
8889 12:15:44.286281 TX Vref=34, minBit 1, minWin=24, winSum=408
8890 12:15:44.289846 TX Vref=36, minBit 1, minWin=23, winSum=399
8891 12:15:44.296219 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8892 12:15:44.296734
8893 12:15:44.299501 Final TX Range 0 Vref 28
8894 12:15:44.299911
8895 12:15:44.300233 ==
8896 12:15:44.303594 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 12:15:44.306310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 12:15:44.306729 ==
8899 12:15:44.307052
8900 12:15:44.310080
8901 12:15:44.310584 TX Vref Scan disable
8902 12:15:44.316507 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8903 12:15:44.317017 == TX Byte 0 ==
8904 12:15:44.319891 u2DelayCellOfst[0]=22 cells (6 PI)
8905 12:15:44.322935 u2DelayCellOfst[1]=15 cells (4 PI)
8906 12:15:44.326396 u2DelayCellOfst[2]=0 cells (0 PI)
8907 12:15:44.329672 u2DelayCellOfst[3]=7 cells (2 PI)
8908 12:15:44.333169 u2DelayCellOfst[4]=11 cells (3 PI)
8909 12:15:44.336228 u2DelayCellOfst[5]=22 cells (6 PI)
8910 12:15:44.339681 u2DelayCellOfst[6]=18 cells (5 PI)
8911 12:15:44.342772 u2DelayCellOfst[7]=7 cells (2 PI)
8912 12:15:44.346468 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8913 12:15:44.349454 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8914 12:15:44.352620 == TX Byte 1 ==
8915 12:15:44.356192 u2DelayCellOfst[8]=0 cells (0 PI)
8916 12:15:44.359146 u2DelayCellOfst[9]=7 cells (2 PI)
8917 12:15:44.362326 u2DelayCellOfst[10]=15 cells (4 PI)
8918 12:15:44.362737 u2DelayCellOfst[11]=7 cells (2 PI)
8919 12:15:44.365664 u2DelayCellOfst[12]=18 cells (5 PI)
8920 12:15:44.369114 u2DelayCellOfst[13]=18 cells (5 PI)
8921 12:15:44.372704 u2DelayCellOfst[14]=18 cells (5 PI)
8922 12:15:44.375754 u2DelayCellOfst[15]=18 cells (5 PI)
8923 12:15:44.382176 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8924 12:15:44.385677 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8925 12:15:44.386180 DramC Write-DBI on
8926 12:15:44.389237 ==
8927 12:15:44.389801 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 12:15:44.395875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 12:15:44.396405 ==
8930 12:15:44.396740
8931 12:15:44.397040
8932 12:15:44.397330 TX Vref Scan disable
8933 12:15:44.399722 == TX Byte 0 ==
8934 12:15:44.403090 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8935 12:15:44.406626 == TX Byte 1 ==
8936 12:15:44.409791 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8937 12:15:44.412861 DramC Write-DBI off
8938 12:15:44.413289
8939 12:15:44.413767 [DATLAT]
8940 12:15:44.414195 Freq=1600, CH1 RK1
8941 12:15:44.414598
8942 12:15:44.416675 DATLAT Default: 0xf
8943 12:15:44.417098 0, 0xFFFF, sum = 0
8944 12:15:44.419466 1, 0xFFFF, sum = 0
8945 12:15:44.422918 2, 0xFFFF, sum = 0
8946 12:15:44.423573 3, 0xFFFF, sum = 0
8947 12:15:44.426155 4, 0xFFFF, sum = 0
8948 12:15:44.426583 5, 0xFFFF, sum = 0
8949 12:15:44.429623 6, 0xFFFF, sum = 0
8950 12:15:44.430049 7, 0xFFFF, sum = 0
8951 12:15:44.433009 8, 0xFFFF, sum = 0
8952 12:15:44.433518 9, 0xFFFF, sum = 0
8953 12:15:44.436809 10, 0xFFFF, sum = 0
8954 12:15:44.437338 11, 0xFFFF, sum = 0
8955 12:15:44.439842 12, 0xFFFF, sum = 0
8956 12:15:44.440475 13, 0x8FFF, sum = 0
8957 12:15:44.442953 14, 0x0, sum = 1
8958 12:15:44.443483 15, 0x0, sum = 2
8959 12:15:44.446193 16, 0x0, sum = 3
8960 12:15:44.446665 17, 0x0, sum = 4
8961 12:15:44.449641 best_step = 15
8962 12:15:44.450099
8963 12:15:44.450522 ==
8964 12:15:44.452614 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 12:15:44.456353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 12:15:44.456883 ==
8967 12:15:44.459279 RX Vref Scan: 0
8968 12:15:44.459703
8969 12:15:44.460136 RX Vref 0 -> 0, step: 1
8970 12:15:44.460545
8971 12:15:44.462502 RX Delay 3 -> 252, step: 4
8972 12:15:44.465814 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8973 12:15:44.472537 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8974 12:15:44.475836 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8975 12:15:44.479031 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8976 12:15:44.482289 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8977 12:15:44.485775 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8978 12:15:44.492924 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8979 12:15:44.496334 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
8980 12:15:44.499178 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8981 12:15:44.502689 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8982 12:15:44.505767 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8983 12:15:44.512785 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8984 12:15:44.516134 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8985 12:15:44.519050 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8986 12:15:44.522614 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8987 12:15:44.529449 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8988 12:15:44.530016 ==
8989 12:15:44.532199 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 12:15:44.535865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 12:15:44.536390 ==
8992 12:15:44.536833 DQS Delay:
8993 12:15:44.538830 DQS0 = 0, DQS1 = 0
8994 12:15:44.539263 DQM Delay:
8995 12:15:44.542255 DQM0 = 127, DQM1 = 125
8996 12:15:44.542908 DQ Delay:
8997 12:15:44.545604 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =126
8998 12:15:44.548924 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
8999 12:15:44.552130 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9000 12:15:44.555575 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9001 12:15:44.556089
9002 12:15:44.558655
9003 12:15:44.559063
9004 12:15:44.559385 [DramC_TX_OE_Calibration] TA2
9005 12:15:44.561997 Original DQ_B0 (3 6) =30, OEN = 27
9006 12:15:44.565147 Original DQ_B1 (3 6) =30, OEN = 27
9007 12:15:44.569077 24, 0x0, End_B0=24 End_B1=24
9008 12:15:44.571858 25, 0x0, End_B0=25 End_B1=25
9009 12:15:44.575164 26, 0x0, End_B0=26 End_B1=26
9010 12:15:44.575699 27, 0x0, End_B0=27 End_B1=27
9011 12:15:44.578575 28, 0x0, End_B0=28 End_B1=28
9012 12:15:44.581875 29, 0x0, End_B0=29 End_B1=29
9013 12:15:44.585438 30, 0x0, End_B0=30 End_B1=30
9014 12:15:44.588367 31, 0x4141, End_B0=30 End_B1=30
9015 12:15:44.588884 Byte0 end_step=30 best_step=27
9016 12:15:44.592124 Byte1 end_step=30 best_step=27
9017 12:15:44.594854 Byte0 TX OE(2T, 0.5T) = (3, 3)
9018 12:15:44.598145 Byte1 TX OE(2T, 0.5T) = (3, 3)
9019 12:15:44.598559
9020 12:15:44.598880
9021 12:15:44.608148 [DQSOSCAuto] RK1, (LSB)MR18= 0x111e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9022 12:15:44.608662 CH1 RK1: MR19=303, MR18=111E
9023 12:15:44.614972 CH1_RK1: MR19=0x303, MR18=0x111E, DQSOSC=394, MR23=63, INC=23, DEC=15
9024 12:15:44.618335 [RxdqsGatingPostProcess] freq 1600
9025 12:15:44.624768 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9026 12:15:44.628620 best DQS0 dly(2T, 0.5T) = (1, 1)
9027 12:15:44.631465 best DQS1 dly(2T, 0.5T) = (1, 1)
9028 12:15:44.634958 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9029 12:15:44.638389 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9030 12:15:44.638916 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 12:15:44.641337 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 12:15:44.645058 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 12:15:44.648050 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 12:15:44.651270 Pre-setting of DQS Precalculation
9035 12:15:44.658262 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9036 12:15:44.664370 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9037 12:15:44.671467 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9038 12:15:44.671979
9039 12:15:44.672305
9040 12:15:44.674410 [Calibration Summary] 3200 Mbps
9041 12:15:44.674819 CH 0, Rank 0
9042 12:15:44.677449 SW Impedance : PASS
9043 12:15:44.680872 DUTY Scan : NO K
9044 12:15:44.681279 ZQ Calibration : PASS
9045 12:15:44.684331 Jitter Meter : NO K
9046 12:15:44.687461 CBT Training : PASS
9047 12:15:44.688141 Write leveling : PASS
9048 12:15:44.690815 RX DQS gating : PASS
9049 12:15:44.694279 RX DQ/DQS(RDDQC) : PASS
9050 12:15:44.694688 TX DQ/DQS : PASS
9051 12:15:44.697757 RX DATLAT : PASS
9052 12:15:44.698168 RX DQ/DQS(Engine): PASS
9053 12:15:44.700979 TX OE : PASS
9054 12:15:44.701388 All Pass.
9055 12:15:44.701760
9056 12:15:44.703904 CH 0, Rank 1
9057 12:15:44.704195 SW Impedance : PASS
9058 12:15:44.707176 DUTY Scan : NO K
9059 12:15:44.710877 ZQ Calibration : PASS
9060 12:15:44.711188 Jitter Meter : NO K
9061 12:15:44.713825 CBT Training : PASS
9062 12:15:44.717278 Write leveling : PASS
9063 12:15:44.717576 RX DQS gating : PASS
9064 12:15:44.720624 RX DQ/DQS(RDDQC) : PASS
9065 12:15:44.723971 TX DQ/DQS : PASS
9066 12:15:44.724238 RX DATLAT : PASS
9067 12:15:44.727259 RX DQ/DQS(Engine): PASS
9068 12:15:44.730379 TX OE : PASS
9069 12:15:44.730644 All Pass.
9070 12:15:44.730795
9071 12:15:44.730926 CH 1, Rank 0
9072 12:15:44.733943 SW Impedance : PASS
9073 12:15:44.737710 DUTY Scan : NO K
9074 12:15:44.738221 ZQ Calibration : PASS
9075 12:15:44.740821 Jitter Meter : NO K
9076 12:15:44.744371 CBT Training : PASS
9077 12:15:44.744884 Write leveling : PASS
9078 12:15:44.747172 RX DQS gating : PASS
9079 12:15:44.750689 RX DQ/DQS(RDDQC) : PASS
9080 12:15:44.751266 TX DQ/DQS : PASS
9081 12:15:44.754306 RX DATLAT : PASS
9082 12:15:44.754816 RX DQ/DQS(Engine): PASS
9083 12:15:44.757735 TX OE : PASS
9084 12:15:44.758251 All Pass.
9085 12:15:44.758582
9086 12:15:44.760374 CH 1, Rank 1
9087 12:15:44.760781 SW Impedance : PASS
9088 12:15:44.764078 DUTY Scan : NO K
9089 12:15:44.767313 ZQ Calibration : PASS
9090 12:15:44.767726 Jitter Meter : NO K
9091 12:15:44.770773 CBT Training : PASS
9092 12:15:44.773806 Write leveling : PASS
9093 12:15:44.774219 RX DQS gating : PASS
9094 12:15:44.777371 RX DQ/DQS(RDDQC) : PASS
9095 12:15:44.780352 TX DQ/DQS : PASS
9096 12:15:44.780775 RX DATLAT : PASS
9097 12:15:44.783568 RX DQ/DQS(Engine): PASS
9098 12:15:44.787291 TX OE : PASS
9099 12:15:44.787802 All Pass.
9100 12:15:44.788126
9101 12:15:44.788428 DramC Write-DBI on
9102 12:15:44.790351 PER_BANK_REFRESH: Hybrid Mode
9103 12:15:44.793793 TX_TRACKING: ON
9104 12:15:44.800533 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9105 12:15:44.810166 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9106 12:15:44.817232 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9107 12:15:44.820559 [FAST_K] Save calibration result to emmc
9108 12:15:44.823991 sync common calibartion params.
9109 12:15:44.827258 sync cbt_mode0:1, 1:1
9110 12:15:44.827773 dram_init: ddr_geometry: 2
9111 12:15:44.830228 dram_init: ddr_geometry: 2
9112 12:15:44.833809 dram_init: ddr_geometry: 2
9113 12:15:44.834319 0:dram_rank_size:100000000
9114 12:15:44.837054 1:dram_rank_size:100000000
9115 12:15:44.843218 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9116 12:15:44.846736 DFS_SHUFFLE_HW_MODE: ON
9117 12:15:44.850025 dramc_set_vcore_voltage set vcore to 725000
9118 12:15:44.850536 Read voltage for 1600, 0
9119 12:15:44.853554 Vio18 = 0
9120 12:15:44.854060 Vcore = 725000
9121 12:15:44.854388 Vdram = 0
9122 12:15:44.856575 Vddq = 0
9123 12:15:44.856985 Vmddr = 0
9124 12:15:44.859925 switch to 3200 Mbps bootup
9125 12:15:44.860331 [DramcRunTimeConfig]
9126 12:15:44.860655 PHYPLL
9127 12:15:44.863569 DPM_CONTROL_AFTERK: ON
9128 12:15:44.866418 PER_BANK_REFRESH: ON
9129 12:15:44.866927 REFRESH_OVERHEAD_REDUCTION: ON
9130 12:15:44.870082 CMD_PICG_NEW_MODE: OFF
9131 12:15:44.873165 XRTWTW_NEW_MODE: ON
9132 12:15:44.873597 XRTRTR_NEW_MODE: ON
9133 12:15:44.876648 TX_TRACKING: ON
9134 12:15:44.877159 RDSEL_TRACKING: OFF
9135 12:15:44.879898 DQS Precalculation for DVFS: ON
9136 12:15:44.882890 RX_TRACKING: OFF
9137 12:15:44.883299 HW_GATING DBG: ON
9138 12:15:44.886680 ZQCS_ENABLE_LP4: ON
9139 12:15:44.887088 RX_PICG_NEW_MODE: ON
9140 12:15:44.889646 TX_PICG_NEW_MODE: ON
9141 12:15:44.890056 ENABLE_RX_DCM_DPHY: ON
9142 12:15:44.892696 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9143 12:15:44.896339 DUMMY_READ_FOR_TRACKING: OFF
9144 12:15:44.899621 !!! SPM_CONTROL_AFTERK: OFF
9145 12:15:44.902982 !!! SPM could not control APHY
9146 12:15:44.903394 IMPEDANCE_TRACKING: ON
9147 12:15:44.906196 TEMP_SENSOR: ON
9148 12:15:44.906606 HW_SAVE_FOR_SR: OFF
9149 12:15:44.909787 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9150 12:15:44.912693 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9151 12:15:44.916574 Read ODT Tracking: ON
9152 12:15:44.919670 Refresh Rate DeBounce: ON
9153 12:15:44.920181 DFS_NO_QUEUE_FLUSH: ON
9154 12:15:44.923151 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9155 12:15:44.925947 ENABLE_DFS_RUNTIME_MRW: OFF
9156 12:15:44.929421 DDR_RESERVE_NEW_MODE: ON
9157 12:15:44.929966 MR_CBT_SWITCH_FREQ: ON
9158 12:15:44.932866 =========================
9159 12:15:44.951603 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9160 12:15:44.954816 dram_init: ddr_geometry: 2
9161 12:15:44.973174 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9162 12:15:44.976250 dram_init: dram init end (result: 0)
9163 12:15:44.982869 DRAM-K: Full calibration passed in 24577 msecs
9164 12:15:44.986019 MRC: failed to locate region type 0.
9165 12:15:44.986431 DRAM rank0 size:0x100000000,
9166 12:15:44.989166 DRAM rank1 size=0x100000000
9167 12:15:44.999768 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9168 12:15:45.006113 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9169 12:15:45.012455 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9170 12:15:45.019638 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9171 12:15:45.022620 DRAM rank0 size:0x100000000,
9172 12:15:45.026002 DRAM rank1 size=0x100000000
9173 12:15:45.026514 CBMEM:
9174 12:15:45.028977 IMD: root @ 0xfffff000 254 entries.
9175 12:15:45.032799 IMD: root @ 0xffffec00 62 entries.
9176 12:15:45.036048 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9177 12:15:45.042486 WARNING: RO_VPD is uninitialized or empty.
9178 12:15:45.045428 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9179 12:15:45.052959 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9180 12:15:45.065819 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9181 12:15:45.077045 BS: romstage times (exec / console): total (unknown) / 24040 ms
9182 12:15:45.077563
9183 12:15:45.077887
9184 12:15:45.086815 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9185 12:15:45.090079 ARM64: Exception handlers installed.
9186 12:15:45.093525 ARM64: Testing exception
9187 12:15:45.097213 ARM64: Done test exception
9188 12:15:45.097792 Enumerating buses...
9189 12:15:45.100030 Show all devs... Before device enumeration.
9190 12:15:45.103428 Root Device: enabled 1
9191 12:15:45.107060 CPU_CLUSTER: 0: enabled 1
9192 12:15:45.107571 CPU: 00: enabled 1
9193 12:15:45.110198 Compare with tree...
9194 12:15:45.110608 Root Device: enabled 1
9195 12:15:45.113834 CPU_CLUSTER: 0: enabled 1
9196 12:15:45.116937 CPU: 00: enabled 1
9197 12:15:45.117346 Root Device scanning...
9198 12:15:45.119875 scan_static_bus for Root Device
9199 12:15:45.123717 CPU_CLUSTER: 0 enabled
9200 12:15:45.127319 scan_static_bus for Root Device done
9201 12:15:45.130138 scan_bus: bus Root Device finished in 8 msecs
9202 12:15:45.130652 done
9203 12:15:45.136771 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9204 12:15:45.140013 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9205 12:15:45.147084 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9206 12:15:45.150226 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9207 12:15:45.153632 Allocating resources...
9208 12:15:45.154041 Reading resources...
9209 12:15:45.160483 Root Device read_resources bus 0 link: 0
9210 12:15:45.161002 DRAM rank0 size:0x100000000,
9211 12:15:45.163460 DRAM rank1 size=0x100000000
9212 12:15:45.167100 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9213 12:15:45.170042 CPU: 00 missing read_resources
9214 12:15:45.173429 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9215 12:15:45.179834 Root Device read_resources bus 0 link: 0 done
9216 12:15:45.180333 Done reading resources.
9217 12:15:45.186724 Show resources in subtree (Root Device)...After reading.
9218 12:15:45.190042 Root Device child on link 0 CPU_CLUSTER: 0
9219 12:15:45.193382 CPU_CLUSTER: 0 child on link 0 CPU: 00
9220 12:15:45.203128 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9221 12:15:45.203623 CPU: 00
9222 12:15:45.206814 Root Device assign_resources, bus 0 link: 0
9223 12:15:45.209675 CPU_CLUSTER: 0 missing set_resources
9224 12:15:45.216868 Root Device assign_resources, bus 0 link: 0 done
9225 12:15:45.217407 Done setting resources.
9226 12:15:45.222937 Show resources in subtree (Root Device)...After assigning values.
9227 12:15:45.226450 Root Device child on link 0 CPU_CLUSTER: 0
9228 12:15:45.230069 CPU_CLUSTER: 0 child on link 0 CPU: 00
9229 12:15:45.239825 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9230 12:15:45.240348 CPU: 00
9231 12:15:45.242971 Done allocating resources.
9232 12:15:45.246390 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9233 12:15:45.249531 Enabling resources...
9234 12:15:45.249943 done.
9235 12:15:45.256114 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9236 12:15:45.256667 Initializing devices...
9237 12:15:45.259518 Root Device init
9238 12:15:45.260025 init hardware done!
9239 12:15:45.262413 0x00000018: ctrlr->caps
9240 12:15:45.265824 52.000 MHz: ctrlr->f_max
9241 12:15:45.266245 0.400 MHz: ctrlr->f_min
9242 12:15:45.269025 0x40ff8080: ctrlr->voltages
9243 12:15:45.272547 sclk: 390625
9244 12:15:45.273088 Bus Width = 1
9245 12:15:45.273595 sclk: 390625
9246 12:15:45.275872 Bus Width = 1
9247 12:15:45.276279 Early init status = 3
9248 12:15:45.282090 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9249 12:15:45.285637 in-header: 03 fc 00 00 01 00 00 00
9250 12:15:45.288940 in-data: 00
9251 12:15:45.292240 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9252 12:15:45.297111 in-header: 03 fd 00 00 00 00 00 00
9253 12:15:45.299948 in-data:
9254 12:15:45.303116 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9255 12:15:45.307876 in-header: 03 fc 00 00 01 00 00 00
9256 12:15:45.310962 in-data: 00
9257 12:15:45.314849 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9258 12:15:45.320137 in-header: 03 fd 00 00 00 00 00 00
9259 12:15:45.323229 in-data:
9260 12:15:45.326780 [SSUSB] Setting up USB HOST controller...
9261 12:15:45.330114 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9262 12:15:45.333150 [SSUSB] phy power-on done.
9263 12:15:45.336768 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9264 12:15:45.343274 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9265 12:15:45.346529 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9266 12:15:45.353159 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9267 12:15:45.360378 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9268 12:15:45.366237 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9269 12:15:45.373615 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9270 12:15:45.379554 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9271 12:15:45.383249 SPM: binary array size = 0x9dc
9272 12:15:45.386175 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9273 12:15:45.393157 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9274 12:15:45.399817 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9275 12:15:45.406472 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9276 12:15:45.409673 configure_display: Starting display init
9277 12:15:45.443206 anx7625_power_on_init: Init interface.
9278 12:15:45.446916 anx7625_disable_pd_protocol: Disabled PD feature.
9279 12:15:45.449769 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9280 12:15:45.477984 anx7625_start_dp_work: Secure OCM version=00
9281 12:15:45.481321 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9282 12:15:45.495642 sp_tx_get_edid_block: EDID Block = 1
9283 12:15:45.598364 Extracted contents:
9284 12:15:45.601728 header: 00 ff ff ff ff ff ff 00
9285 12:15:45.605170 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9286 12:15:45.608447 version: 01 04
9287 12:15:45.612073 basic params: 95 1f 11 78 0a
9288 12:15:45.615094 chroma info: 76 90 94 55 54 90 27 21 50 54
9289 12:15:45.617946 established: 00 00 00
9290 12:15:45.625019 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9291 12:15:45.631508 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9292 12:15:45.634437 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9293 12:15:45.640925 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9294 12:15:45.647855 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9295 12:15:45.651019 extensions: 00
9296 12:15:45.651457 checksum: fb
9297 12:15:45.651794
9298 12:15:45.654192 Manufacturer: IVO Model 57d Serial Number 0
9299 12:15:45.657998 Made week 0 of 2020
9300 12:15:45.661127 EDID version: 1.4
9301 12:15:45.661763 Digital display
9302 12:15:45.664482 6 bits per primary color channel
9303 12:15:45.665019 DisplayPort interface
9304 12:15:45.667532 Maximum image size: 31 cm x 17 cm
9305 12:15:45.671071 Gamma: 220%
9306 12:15:45.671485 Check DPMS levels
9307 12:15:45.674305 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9308 12:15:45.681147 First detailed timing is preferred timing
9309 12:15:45.681726 Established timings supported:
9310 12:15:45.684292 Standard timings supported:
9311 12:15:45.687525 Detailed timings
9312 12:15:45.691025 Hex of detail: 383680a07038204018303c0035ae10000019
9313 12:15:45.694245 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9314 12:15:45.701234 0780 0798 07c8 0820 hborder 0
9315 12:15:45.703982 0438 043b 0447 0458 vborder 0
9316 12:15:45.708055 -hsync -vsync
9317 12:15:45.708569 Did detailed timing
9318 12:15:45.714367 Hex of detail: 000000000000000000000000000000000000
9319 12:15:45.717457 Manufacturer-specified data, tag 0
9320 12:15:45.721161 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9321 12:15:45.724403 ASCII string: InfoVision
9322 12:15:45.727477 Hex of detail: 000000fe00523134304e574635205248200a
9323 12:15:45.730973 ASCII string: R140NWF5 RH
9324 12:15:45.731494 Checksum
9325 12:15:45.734205 Checksum: 0xfb (valid)
9326 12:15:45.737375 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9327 12:15:45.740666 DSI data_rate: 832800000 bps
9328 12:15:45.747190 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9329 12:15:45.750446 anx7625_parse_edid: pixelclock(138800).
9330 12:15:45.754056 hactive(1920), hsync(48), hfp(24), hbp(88)
9331 12:15:45.757379 vactive(1080), vsync(12), vfp(3), vbp(17)
9332 12:15:45.760436 anx7625_dsi_config: config dsi.
9333 12:15:45.766610 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9334 12:15:45.780711 anx7625_dsi_config: success to config DSI
9335 12:15:45.783587 anx7625_dp_start: MIPI phy setup OK.
9336 12:15:45.787286 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9337 12:15:45.790215 mtk_ddp_mode_set invalid vrefresh 60
9338 12:15:45.793932 main_disp_path_setup
9339 12:15:45.794440 ovl_layer_smi_id_en
9340 12:15:45.797115 ovl_layer_smi_id_en
9341 12:15:45.797663 ccorr_config
9342 12:15:45.797998 aal_config
9343 12:15:45.800523 gamma_config
9344 12:15:45.801032 postmask_config
9345 12:15:45.803673 dither_config
9346 12:15:45.807087 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9347 12:15:45.813574 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9348 12:15:45.816703 Root Device init finished in 554 msecs
9349 12:15:45.819900 CPU_CLUSTER: 0 init
9350 12:15:45.827162 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9351 12:15:45.830273 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9352 12:15:45.833620 APU_MBOX 0x190000b0 = 0x10001
9353 12:15:45.837028 APU_MBOX 0x190001b0 = 0x10001
9354 12:15:45.840020 APU_MBOX 0x190005b0 = 0x10001
9355 12:15:45.843547 APU_MBOX 0x190006b0 = 0x10001
9356 12:15:45.847244 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9357 12:15:45.859640 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9358 12:15:45.872127 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9359 12:15:45.878514 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9360 12:15:45.890513 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9361 12:15:45.899377 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9362 12:15:45.902433 CPU_CLUSTER: 0 init finished in 81 msecs
9363 12:15:45.905852 Devices initialized
9364 12:15:45.909237 Show all devs... After init.
9365 12:15:45.909800 Root Device: enabled 1
9366 12:15:45.912661 CPU_CLUSTER: 0: enabled 1
9367 12:15:45.915710 CPU: 00: enabled 1
9368 12:15:45.919445 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9369 12:15:45.922093 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9370 12:15:45.925822 ELOG: NV offset 0x57f000 size 0x1000
9371 12:15:45.932288 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9372 12:15:45.938721 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9373 12:15:45.942466 ELOG: Event(17) added with size 13 at 2024-01-31 12:15:45 UTC
9374 12:15:45.949149 out: cmd=0x121: 03 db 21 01 00 00 00 00
9375 12:15:45.952180 in-header: 03 31 00 00 2c 00 00 00
9376 12:15:45.962252 in-data: 2d 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9377 12:15:45.968540 ELOG: Event(A1) added with size 10 at 2024-01-31 12:15:45 UTC
9378 12:15:45.975108 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9379 12:15:45.982086 ELOG: Event(A0) added with size 9 at 2024-01-31 12:15:45 UTC
9380 12:15:45.985356 elog_add_boot_reason: Logged dev mode boot
9381 12:15:45.991799 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9382 12:15:45.992221 Finalize devices...
9383 12:15:45.994742 Devices finalized
9384 12:15:45.998191 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9385 12:15:46.001860 Writing coreboot table at 0xffe64000
9386 12:15:46.005061 0. 000000000010a000-0000000000113fff: RAMSTAGE
9387 12:15:46.008538 1. 0000000040000000-00000000400fffff: RAM
9388 12:15:46.014819 2. 0000000040100000-000000004032afff: RAMSTAGE
9389 12:15:46.018264 3. 000000004032b000-00000000545fffff: RAM
9390 12:15:46.021400 4. 0000000054600000-000000005465ffff: BL31
9391 12:15:46.024997 5. 0000000054660000-00000000ffe63fff: RAM
9392 12:15:46.031667 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9393 12:15:46.034981 7. 0000000100000000-000000023fffffff: RAM
9394 12:15:46.038071 Passing 5 GPIOs to payload:
9395 12:15:46.041301 NAME | PORT | POLARITY | VALUE
9396 12:15:46.048253 EC in RW | 0x000000aa | low | undefined
9397 12:15:46.051479 EC interrupt | 0x00000005 | low | undefined
9398 12:15:46.054579 TPM interrupt | 0x000000ab | high | undefined
9399 12:15:46.061228 SD card detect | 0x00000011 | high | undefined
9400 12:15:46.064857 speaker enable | 0x00000093 | high | undefined
9401 12:15:46.068207 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9402 12:15:46.071239 in-header: 03 f9 00 00 02 00 00 00
9403 12:15:46.074767 in-data: 02 00
9404 12:15:46.078023 ADC[4]: Raw value=894821 ID=7
9405 12:15:46.078440 ADC[3]: Raw value=212700 ID=1
9406 12:15:46.081575 RAM Code: 0x71
9407 12:15:46.084592 ADC[6]: Raw value=74722 ID=0
9408 12:15:46.085101 ADC[5]: Raw value=212330 ID=1
9409 12:15:46.088119 SKU Code: 0x1
9410 12:15:46.091184 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum e0ef
9411 12:15:46.094283 coreboot table: 964 bytes.
9412 12:15:46.098148 IMD ROOT 0. 0xfffff000 0x00001000
9413 12:15:46.100988 IMD SMALL 1. 0xffffe000 0x00001000
9414 12:15:46.104203 RO MCACHE 2. 0xffffc000 0x00001104
9415 12:15:46.107744 CONSOLE 3. 0xfff7c000 0x00080000
9416 12:15:46.111117 FMAP 4. 0xfff7b000 0x00000452
9417 12:15:46.114495 TIME STAMP 5. 0xfff7a000 0x00000910
9418 12:15:46.118034 VBOOT WORK 6. 0xfff66000 0x00014000
9419 12:15:46.121275 RAMOOPS 7. 0xffe66000 0x00100000
9420 12:15:46.124569 COREBOOT 8. 0xffe64000 0x00002000
9421 12:15:46.127653 IMD small region:
9422 12:15:46.131161 IMD ROOT 0. 0xffffec00 0x00000400
9423 12:15:46.134443 VPD 1. 0xffffeb80 0x0000006c
9424 12:15:46.137659 MMC STATUS 2. 0xffffeb60 0x00000004
9425 12:15:46.141162 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9426 12:15:46.144347 Probing TPM: done!
9427 12:15:46.147884 Connected to device vid:did:rid of 1ae0:0028:00
9428 12:15:46.158436 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9429 12:15:46.161602 Initialized TPM device CR50 revision 0
9430 12:15:46.165160 Checking cr50 for pending updates
9431 12:15:46.169095 Reading cr50 TPM mode
9432 12:15:46.177613 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9433 12:15:46.184054 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9434 12:15:46.224635 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9435 12:15:46.228036 Checking segment from ROM address 0x40100000
9436 12:15:46.230984 Checking segment from ROM address 0x4010001c
9437 12:15:46.237674 Loading segment from ROM address 0x40100000
9438 12:15:46.238202 code (compression=0)
9439 12:15:46.247825 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9440 12:15:46.254446 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9441 12:15:46.254963 it's not compressed!
9442 12:15:46.260803 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9443 12:15:46.264010 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9444 12:15:46.284565 Loading segment from ROM address 0x4010001c
9445 12:15:46.285070 Entry Point 0x80000000
9446 12:15:46.288278 Loaded segments
9447 12:15:46.291122 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9448 12:15:46.297847 Jumping to boot code at 0x80000000(0xffe64000)
9449 12:15:46.304397 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9450 12:15:46.311431 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9451 12:15:46.319325 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9452 12:15:46.322622 Checking segment from ROM address 0x40100000
9453 12:15:46.326251 Checking segment from ROM address 0x4010001c
9454 12:15:46.332660 Loading segment from ROM address 0x40100000
9455 12:15:46.333313 code (compression=1)
9456 12:15:46.339917 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9457 12:15:46.349739 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9458 12:15:46.350263 using LZMA
9459 12:15:46.357547 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9460 12:15:46.363854 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9461 12:15:46.367866 Loading segment from ROM address 0x4010001c
9462 12:15:46.368396 Entry Point 0x54601000
9463 12:15:46.370992 Loaded segments
9464 12:15:46.374407 NOTICE: MT8192 bl31_setup
9465 12:15:46.381438 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9466 12:15:46.384475 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9467 12:15:46.387661 WARNING: region 0:
9468 12:15:46.391034 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 12:15:46.391510 WARNING: region 1:
9470 12:15:46.397823 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9471 12:15:46.400976 WARNING: region 2:
9472 12:15:46.403994 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9473 12:15:46.407844 WARNING: region 3:
9474 12:15:46.411158 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9475 12:15:46.414117 WARNING: region 4:
9476 12:15:46.421182 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9477 12:15:46.421861 WARNING: region 5:
9478 12:15:46.424607 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 12:15:46.427998 WARNING: region 6:
9480 12:15:46.431344 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 12:15:46.434268 WARNING: region 7:
9482 12:15:46.437943 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 12:15:46.444527 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9484 12:15:46.447527 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9485 12:15:46.450914 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9486 12:15:46.457712 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9487 12:15:46.461131 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9488 12:15:46.464142 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9489 12:15:46.471234 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9490 12:15:46.474760 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9491 12:15:46.481518 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9492 12:15:46.484286 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9493 12:15:46.487944 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9494 12:15:46.494387 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9495 12:15:46.497560 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9496 12:15:46.501004 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9497 12:15:46.507765 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9498 12:15:46.510489 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9499 12:15:46.517858 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9500 12:15:46.521183 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9501 12:15:46.524488 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9502 12:15:46.531052 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9503 12:15:46.534126 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9504 12:15:46.537629 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9505 12:15:46.544147 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9506 12:15:46.547157 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9507 12:15:46.554049 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9508 12:15:46.557360 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9509 12:15:46.564407 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9510 12:15:46.567179 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9511 12:15:46.570470 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9512 12:15:46.577224 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9513 12:15:46.580401 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9514 12:15:46.586924 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9515 12:15:46.590156 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9516 12:15:46.593550 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9517 12:15:46.596847 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9518 12:15:46.600123 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9519 12:15:46.606982 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9520 12:15:46.610315 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9521 12:15:46.613548 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9522 12:15:46.616893 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9523 12:15:46.623723 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9524 12:15:46.626933 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9525 12:15:46.630190 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9526 12:15:46.633654 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9527 12:15:46.640568 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9528 12:15:46.643656 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9529 12:15:46.647037 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9530 12:15:46.653507 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9531 12:15:46.656698 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9532 12:15:46.660174 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9533 12:15:46.666787 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9534 12:15:46.669666 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9535 12:15:46.676936 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9536 12:15:46.680259 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9537 12:15:46.683660 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9538 12:15:46.690219 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9539 12:15:46.693528 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9540 12:15:46.699999 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9541 12:15:46.703823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9542 12:15:46.710102 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9543 12:15:46.713654 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9544 12:15:46.720438 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9545 12:15:46.723592 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9546 12:15:46.727158 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9547 12:15:46.733891 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9548 12:15:46.737321 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9549 12:15:46.743917 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9550 12:15:46.747149 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9551 12:15:46.753734 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9552 12:15:46.757320 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9553 12:15:46.760870 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9554 12:15:46.767156 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9555 12:15:46.770388 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9556 12:15:46.776909 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9557 12:15:46.780139 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9558 12:15:46.787010 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9559 12:15:46.790430 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9560 12:15:46.793779 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9561 12:15:46.800368 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9562 12:15:46.803597 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9563 12:15:46.809987 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9564 12:15:46.813655 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9565 12:15:46.820423 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9566 12:15:46.823503 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9567 12:15:46.830255 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9568 12:15:46.833648 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9569 12:15:46.837001 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9570 12:15:46.843766 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9571 12:15:46.846625 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9572 12:15:46.853437 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9573 12:15:46.856524 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9574 12:15:46.863505 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9575 12:15:46.866603 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9576 12:15:46.869992 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9577 12:15:46.876907 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9578 12:15:46.880544 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9579 12:15:46.886973 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9580 12:15:46.890181 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9581 12:15:46.893648 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9582 12:15:46.896724 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9583 12:15:46.900307 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9584 12:15:46.906773 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9585 12:15:46.909974 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9586 12:15:46.916997 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9587 12:15:46.920370 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9588 12:15:46.923759 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9589 12:15:46.930158 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9590 12:15:46.933195 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9591 12:15:46.940430 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9592 12:15:46.943505 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9593 12:15:46.946596 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9594 12:15:46.953417 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9595 12:15:46.956843 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9596 12:15:46.963182 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9597 12:15:46.966502 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9598 12:15:46.973205 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9599 12:15:46.976469 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9600 12:15:46.979906 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9601 12:15:46.983069 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9602 12:15:46.989640 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9603 12:15:46.993224 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9604 12:15:46.996308 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9605 12:15:47.000006 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9606 12:15:47.006299 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9607 12:15:47.009775 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9608 12:15:47.013077 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9609 12:15:47.019970 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9610 12:15:47.023241 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9611 12:15:47.030021 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9612 12:15:47.033378 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9613 12:15:47.036978 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9614 12:15:47.043688 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9615 12:15:47.046900 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9616 12:15:47.053608 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9617 12:15:47.056670 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9618 12:15:47.060208 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9619 12:15:47.066862 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9620 12:15:47.070179 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9621 12:15:47.073551 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9622 12:15:47.080320 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9623 12:15:47.083128 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9624 12:15:47.090141 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9625 12:15:47.093438 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9626 12:15:47.096312 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9627 12:15:47.103119 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9628 12:15:47.106034 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9629 12:15:47.112912 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9630 12:15:47.116647 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9631 12:15:47.120206 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9632 12:15:47.126399 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9633 12:15:47.129865 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9634 12:15:47.133433 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9635 12:15:47.139839 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9636 12:15:47.143419 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9637 12:15:47.150042 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9638 12:15:47.153097 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9639 12:15:47.156399 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9640 12:15:47.163273 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9641 12:15:47.166696 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9642 12:15:47.173029 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9643 12:15:47.176706 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9644 12:15:47.180127 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9645 12:15:47.186478 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9646 12:15:47.189681 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9647 12:15:47.196471 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9648 12:15:47.199859 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9649 12:15:47.203295 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9650 12:15:47.210055 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9651 12:15:47.213241 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9652 12:15:47.216480 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9653 12:15:47.223013 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9654 12:15:47.226070 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9655 12:15:47.233113 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9656 12:15:47.236213 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9657 12:15:47.239818 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9658 12:15:47.246231 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9659 12:15:47.249702 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9660 12:15:47.256175 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9661 12:15:47.259395 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9662 12:15:47.262824 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9663 12:15:47.269377 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9664 12:15:47.272744 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9665 12:15:47.279020 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9666 12:15:47.282917 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9667 12:15:47.285654 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9668 12:15:47.292426 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9669 12:15:47.296065 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9670 12:15:47.302541 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9671 12:15:47.305891 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9672 12:15:47.309252 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9673 12:15:47.316065 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9674 12:15:47.318955 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9675 12:15:47.325471 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9676 12:15:47.329092 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9677 12:15:47.335145 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9678 12:15:47.339129 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9679 12:15:47.342174 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9680 12:15:47.348691 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9681 12:15:47.352034 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9682 12:15:47.358647 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9683 12:15:47.362345 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9684 12:15:47.365328 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9685 12:15:47.371863 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9686 12:15:47.375364 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9687 12:15:47.381631 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9688 12:15:47.385219 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9689 12:15:47.391734 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9690 12:15:47.395325 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9691 12:15:47.398223 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9692 12:15:47.404788 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9693 12:15:47.408215 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9694 12:15:47.415353 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9695 12:15:47.417993 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9696 12:15:47.424987 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9697 12:15:47.428357 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9698 12:15:47.431734 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9699 12:15:47.438024 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9700 12:15:47.441396 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9701 12:15:47.448197 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9702 12:15:47.451543 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9703 12:15:47.458095 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9704 12:15:47.461416 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9705 12:15:47.464710 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9706 12:15:47.471276 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9707 12:15:47.474357 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9708 12:15:47.481145 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9709 12:15:47.484321 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9710 12:15:47.487810 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9711 12:15:47.494131 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9712 12:15:47.497703 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9713 12:15:47.500817 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9714 12:15:47.504391 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9715 12:15:47.510937 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9716 12:15:47.514090 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9717 12:15:47.517126 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9718 12:15:47.524198 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9719 12:15:47.527632 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9720 12:15:47.534412 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9721 12:15:47.537098 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9722 12:15:47.540744 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9723 12:15:47.546969 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9724 12:15:47.550388 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9725 12:15:47.554017 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9726 12:15:47.560766 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9727 12:15:47.563753 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9728 12:15:47.566680 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9729 12:15:47.573928 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9730 12:15:47.577330 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9731 12:15:47.583386 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9732 12:15:47.586812 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9733 12:15:47.589831 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9734 12:15:47.596829 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9735 12:15:47.599813 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9736 12:15:47.603226 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9737 12:15:47.609988 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9738 12:15:47.613370 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9739 12:15:47.620014 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9740 12:15:47.623248 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9741 12:15:47.626250 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9742 12:15:47.633062 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9743 12:15:47.636400 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9744 12:15:47.640212 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9745 12:15:47.646473 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9746 12:15:47.649414 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9747 12:15:47.653331 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9748 12:15:47.659722 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9749 12:15:47.662869 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9750 12:15:47.669668 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9751 12:15:47.672668 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9752 12:15:47.676030 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9753 12:15:47.679108 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9754 12:15:47.686039 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9755 12:15:47.689248 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9756 12:15:47.692264 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9757 12:15:47.695453 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9758 12:15:47.702142 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9759 12:15:47.705625 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9760 12:15:47.708798 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9761 12:15:47.712084 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9762 12:15:47.718639 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9763 12:15:47.721688 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9764 12:15:47.725168 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9765 12:15:47.732125 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9766 12:15:47.735321 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9767 12:15:47.741754 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9768 12:15:47.744991 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9769 12:15:47.748442 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9770 12:15:47.755084 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9771 12:15:47.758017 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9772 12:15:47.765251 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9773 12:15:47.768366 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9774 12:15:47.771544 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9775 12:15:47.778249 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9776 12:15:47.781640 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9777 12:15:47.788154 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9778 12:15:47.791733 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9779 12:15:47.798162 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9780 12:15:47.801246 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9781 12:15:47.804823 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9782 12:15:47.811522 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9783 12:15:47.814902 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9784 12:15:47.821564 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9785 12:15:47.824646 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9786 12:15:47.831430 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9787 12:15:47.834762 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9788 12:15:47.837720 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9789 12:15:47.844408 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9790 12:15:47.847633 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9791 12:15:47.854189 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9792 12:15:47.857297 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9793 12:15:47.860780 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9794 12:15:47.867107 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9795 12:15:47.870495 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9796 12:15:47.877106 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9797 12:15:47.881082 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9798 12:15:47.883672 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9799 12:15:47.890161 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9800 12:15:47.893776 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9801 12:15:47.900521 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9802 12:15:47.904285 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9803 12:15:47.910230 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9804 12:15:47.913939 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9805 12:15:47.917325 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9806 12:15:47.924239 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9807 12:15:47.926875 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9808 12:15:47.933715 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9809 12:15:47.937372 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9810 12:15:47.940617 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9811 12:15:47.946912 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9812 12:15:47.950175 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9813 12:15:47.956640 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9814 12:15:47.960049 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9815 12:15:47.963500 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9816 12:15:47.970237 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9817 12:15:47.973380 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9818 12:15:47.979997 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9819 12:15:47.983458 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9820 12:15:47.986386 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9821 12:15:47.993364 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9822 12:15:47.996532 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9823 12:15:48.003812 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9824 12:15:48.006240 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9825 12:15:48.013340 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9826 12:15:48.016607 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9827 12:15:48.020035 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9828 12:15:48.026400 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9829 12:15:48.029831 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9830 12:15:48.036253 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9831 12:15:48.039890 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9832 12:15:48.043116 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9833 12:15:48.049582 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9834 12:15:48.053017 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9835 12:15:48.059576 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9836 12:15:48.062590 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9837 12:15:48.069275 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9838 12:15:48.072646 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9839 12:15:48.075600 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9840 12:15:48.082286 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9841 12:15:48.085826 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9842 12:15:48.092498 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9843 12:15:48.095537 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9844 12:15:48.102617 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9845 12:15:48.106241 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9846 12:15:48.108848 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9847 12:15:48.115922 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9848 12:15:48.119417 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9849 12:15:48.126071 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9850 12:15:48.129432 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9851 12:15:48.136193 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9852 12:15:48.139015 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9853 12:15:48.145929 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9854 12:15:48.148517 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9855 12:15:48.151849 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9856 12:15:48.159041 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9857 12:15:48.162311 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9858 12:15:48.168602 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9859 12:15:48.172060 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9860 12:15:48.178719 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9861 12:15:48.182407 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9862 12:15:48.185532 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9863 12:15:48.191950 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9864 12:15:48.195130 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9865 12:15:48.201756 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9866 12:15:48.205219 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9867 12:15:48.212156 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9868 12:15:48.215165 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9869 12:15:48.218366 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9870 12:15:48.224943 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9871 12:15:48.228677 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9872 12:15:48.234863 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9873 12:15:48.238208 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9874 12:15:48.245472 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9875 12:15:48.248470 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9876 12:15:48.254662 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9877 12:15:48.258425 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9878 12:15:48.261822 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9879 12:15:48.267903 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9880 12:15:48.271481 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9881 12:15:48.278429 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9882 12:15:48.281736 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9883 12:15:48.288337 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9884 12:15:48.291634 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9885 12:15:48.294727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9886 12:15:48.301892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9887 12:15:48.304981 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9888 12:15:48.311598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9889 12:15:48.314896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9890 12:15:48.321558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9891 12:15:48.324977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9892 12:15:48.331498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9893 12:15:48.334851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9894 12:15:48.341465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9895 12:15:48.344997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9896 12:15:48.351060 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9897 12:15:48.354832 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9898 12:15:48.361299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9899 12:15:48.364453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9900 12:15:48.371124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9901 12:15:48.374198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9902 12:15:48.377533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9903 12:15:48.383974 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9904 12:15:48.387651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9905 12:15:48.394188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9906 12:15:48.397890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9907 12:15:48.403939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9908 12:15:48.407350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9909 12:15:48.414145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9910 12:15:48.421050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9911 12:15:48.424113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9912 12:15:48.430672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9913 12:15:48.434143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9914 12:15:48.440586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9915 12:15:48.443659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9916 12:15:48.450293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9917 12:15:48.453695 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9918 12:15:48.454207 INFO: [APUAPC] vio 0
9919 12:15:48.461458 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9920 12:15:48.464458 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9921 12:15:48.467847 INFO: [APUAPC] D0_APC_0: 0x400510
9922 12:15:48.471223 INFO: [APUAPC] D0_APC_1: 0x0
9923 12:15:48.474176 INFO: [APUAPC] D0_APC_2: 0x1540
9924 12:15:48.477588 INFO: [APUAPC] D0_APC_3: 0x0
9925 12:15:48.480879 INFO: [APUAPC] D1_APC_0: 0xffffffff
9926 12:15:48.484437 INFO: [APUAPC] D1_APC_1: 0xffffffff
9927 12:15:48.487534 INFO: [APUAPC] D1_APC_2: 0x3fffff
9928 12:15:48.490665 INFO: [APUAPC] D1_APC_3: 0x0
9929 12:15:48.494132 INFO: [APUAPC] D2_APC_0: 0xffffffff
9930 12:15:48.497646 INFO: [APUAPC] D2_APC_1: 0xffffffff
9931 12:15:48.500620 INFO: [APUAPC] D2_APC_2: 0x3fffff
9932 12:15:48.504257 INFO: [APUAPC] D2_APC_3: 0x0
9933 12:15:48.507535 INFO: [APUAPC] D3_APC_0: 0xffffffff
9934 12:15:48.510814 INFO: [APUAPC] D3_APC_1: 0xffffffff
9935 12:15:48.514314 INFO: [APUAPC] D3_APC_2: 0x3fffff
9936 12:15:48.517565 INFO: [APUAPC] D3_APC_3: 0x0
9937 12:15:48.520607 INFO: [APUAPC] D4_APC_0: 0xffffffff
9938 12:15:48.524370 INFO: [APUAPC] D4_APC_1: 0xffffffff
9939 12:15:48.527584 INFO: [APUAPC] D4_APC_2: 0x3fffff
9940 12:15:48.528103 INFO: [APUAPC] D4_APC_3: 0x0
9941 12:15:48.533859 INFO: [APUAPC] D5_APC_0: 0xffffffff
9942 12:15:48.537608 INFO: [APUAPC] D5_APC_1: 0xffffffff
9943 12:15:48.540958 INFO: [APUAPC] D5_APC_2: 0x3fffff
9944 12:15:48.541469 INFO: [APUAPC] D5_APC_3: 0x0
9945 12:15:48.544479 INFO: [APUAPC] D6_APC_0: 0xffffffff
9946 12:15:48.547309 INFO: [APUAPC] D6_APC_1: 0xffffffff
9947 12:15:48.550858 INFO: [APUAPC] D6_APC_2: 0x3fffff
9948 12:15:48.553879 INFO: [APUAPC] D6_APC_3: 0x0
9949 12:15:48.557261 INFO: [APUAPC] D7_APC_0: 0xffffffff
9950 12:15:48.560800 INFO: [APUAPC] D7_APC_1: 0xffffffff
9951 12:15:48.564122 INFO: [APUAPC] D7_APC_2: 0x3fffff
9952 12:15:48.567273 INFO: [APUAPC] D7_APC_3: 0x0
9953 12:15:48.570140 INFO: [APUAPC] D8_APC_0: 0xffffffff
9954 12:15:48.573908 INFO: [APUAPC] D8_APC_1: 0xffffffff
9955 12:15:48.577171 INFO: [APUAPC] D8_APC_2: 0x3fffff
9956 12:15:48.580345 INFO: [APUAPC] D8_APC_3: 0x0
9957 12:15:48.583715 INFO: [APUAPC] D9_APC_0: 0xffffffff
9958 12:15:48.586764 INFO: [APUAPC] D9_APC_1: 0xffffffff
9959 12:15:48.590204 INFO: [APUAPC] D9_APC_2: 0x3fffff
9960 12:15:48.593618 INFO: [APUAPC] D9_APC_3: 0x0
9961 12:15:48.596896 INFO: [APUAPC] D10_APC_0: 0xffffffff
9962 12:15:48.600243 INFO: [APUAPC] D10_APC_1: 0xffffffff
9963 12:15:48.603286 INFO: [APUAPC] D10_APC_2: 0x3fffff
9964 12:15:48.606835 INFO: [APUAPC] D10_APC_3: 0x0
9965 12:15:48.609817 INFO: [APUAPC] D11_APC_0: 0xffffffff
9966 12:15:48.613368 INFO: [APUAPC] D11_APC_1: 0xffffffff
9967 12:15:48.616815 INFO: [APUAPC] D11_APC_2: 0x3fffff
9968 12:15:48.620099 INFO: [APUAPC] D11_APC_3: 0x0
9969 12:15:48.623395 INFO: [APUAPC] D12_APC_0: 0xffffffff
9970 12:15:48.626748 INFO: [APUAPC] D12_APC_1: 0xffffffff
9971 12:15:48.629999 INFO: [APUAPC] D12_APC_2: 0x3fffff
9972 12:15:48.633270 INFO: [APUAPC] D12_APC_3: 0x0
9973 12:15:48.636525 INFO: [APUAPC] D13_APC_0: 0xffffffff
9974 12:15:48.639698 INFO: [APUAPC] D13_APC_1: 0xffffffff
9975 12:15:48.643123 INFO: [APUAPC] D13_APC_2: 0x3fffff
9976 12:15:48.646419 INFO: [APUAPC] D13_APC_3: 0x0
9977 12:15:48.649896 INFO: [APUAPC] D14_APC_0: 0xffffffff
9978 12:15:48.653252 INFO: [APUAPC] D14_APC_1: 0xffffffff
9979 12:15:48.656101 INFO: [APUAPC] D14_APC_2: 0x3fffff
9980 12:15:48.659688 INFO: [APUAPC] D14_APC_3: 0x0
9981 12:15:48.663137 INFO: [APUAPC] D15_APC_0: 0xffffffff
9982 12:15:48.669512 INFO: [APUAPC] D15_APC_1: 0xffffffff
9983 12:15:48.673071 INFO: [APUAPC] D15_APC_2: 0x3fffff
9984 12:15:48.673622 INFO: [APUAPC] D15_APC_3: 0x0
9985 12:15:48.676258 INFO: [APUAPC] APC_CON: 0x4
9986 12:15:48.679169 INFO: [NOCDAPC] D0_APC_0: 0x0
9987 12:15:48.682704 INFO: [NOCDAPC] D0_APC_1: 0x0
9988 12:15:48.685835 INFO: [NOCDAPC] D1_APC_0: 0x0
9989 12:15:48.689218 INFO: [NOCDAPC] D1_APC_1: 0xfff
9990 12:15:48.692649 INFO: [NOCDAPC] D2_APC_0: 0x0
9991 12:15:48.696019 INFO: [NOCDAPC] D2_APC_1: 0xfff
9992 12:15:48.699205 INFO: [NOCDAPC] D3_APC_0: 0x0
9993 12:15:48.702303 INFO: [NOCDAPC] D3_APC_1: 0xfff
9994 12:15:48.702812 INFO: [NOCDAPC] D4_APC_0: 0x0
9995 12:15:48.705690 INFO: [NOCDAPC] D4_APC_1: 0xfff
9996 12:15:48.708988 INFO: [NOCDAPC] D5_APC_0: 0x0
9997 12:15:48.712461 INFO: [NOCDAPC] D5_APC_1: 0xfff
9998 12:15:48.715606 INFO: [NOCDAPC] D6_APC_0: 0x0
9999 12:15:48.718804 INFO: [NOCDAPC] D6_APC_1: 0xfff
10000 12:15:48.721996 INFO: [NOCDAPC] D7_APC_0: 0x0
10001 12:15:48.725717 INFO: [NOCDAPC] D7_APC_1: 0xfff
10002 12:15:48.728880 INFO: [NOCDAPC] D8_APC_0: 0x0
10003 12:15:48.732370 INFO: [NOCDAPC] D8_APC_1: 0xfff
10004 12:15:48.735482 INFO: [NOCDAPC] D9_APC_0: 0x0
10005 12:15:48.736045 INFO: [NOCDAPC] D9_APC_1: 0xfff
10006 12:15:48.738626 INFO: [NOCDAPC] D10_APC_0: 0x0
10007 12:15:48.742180 INFO: [NOCDAPC] D10_APC_1: 0xfff
10008 12:15:48.745552 INFO: [NOCDAPC] D11_APC_0: 0x0
10009 12:15:48.748909 INFO: [NOCDAPC] D11_APC_1: 0xfff
10010 12:15:48.752121 INFO: [NOCDAPC] D12_APC_0: 0x0
10011 12:15:48.755544 INFO: [NOCDAPC] D12_APC_1: 0xfff
10012 12:15:48.758671 INFO: [NOCDAPC] D13_APC_0: 0x0
10013 12:15:48.762020 INFO: [NOCDAPC] D13_APC_1: 0xfff
10014 12:15:48.765300 INFO: [NOCDAPC] D14_APC_0: 0x0
10015 12:15:48.768558 INFO: [NOCDAPC] D14_APC_1: 0xfff
10016 12:15:48.772356 INFO: [NOCDAPC] D15_APC_0: 0x0
10017 12:15:48.775442 INFO: [NOCDAPC] D15_APC_1: 0xfff
10018 12:15:48.778452 INFO: [NOCDAPC] APC_CON: 0x4
10019 12:15:48.782118 INFO: [APUAPC] set_apusys_apc done
10020 12:15:48.785448 INFO: [DEVAPC] devapc_init done
10021 12:15:48.788615 INFO: GICv3 without legacy support detected.
10022 12:15:48.791953 INFO: ARM GICv3 driver initialized in EL3
10023 12:15:48.795435 INFO: Maximum SPI INTID supported: 639
10024 12:15:48.798188 INFO: BL31: Initializing runtime services
10025 12:15:48.805170 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10026 12:15:48.808505 INFO: SPM: enable CPC mode
10027 12:15:48.811562 INFO: mcdi ready for mcusys-off-idle and system suspend
10028 12:15:48.818208 INFO: BL31: Preparing for EL3 exit to normal world
10029 12:15:48.821375 INFO: Entry point address = 0x80000000
10030 12:15:48.824923 INFO: SPSR = 0x8
10031 12:15:48.828978
10032 12:15:48.829393
10033 12:15:48.829758
10034 12:15:48.832669 Starting depthcharge on Spherion...
10035 12:15:48.833188
10036 12:15:48.833559 Wipe memory regions:
10037 12:15:48.833875
10038 12:15:48.836326 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10039 12:15:48.836827 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10040 12:15:48.837228 Setting prompt string to ['asurada:']
10041 12:15:48.837646 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10042 12:15:48.838309 [0x00000040000000, 0x00000054600000)
10043 12:15:48.958341
10044 12:15:48.958860 [0x00000054660000, 0x00000080000000)
10045 12:15:49.218574
10046 12:15:49.219080 [0x000000821a7280, 0x000000ffe64000)
10047 12:15:49.963747
10048 12:15:49.964270 [0x00000100000000, 0x00000240000000)
10049 12:15:51.853898
10050 12:15:51.856570 Initializing XHCI USB controller at 0x11200000.
10051 12:15:52.895248
10052 12:15:52.898608 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10053 12:15:52.898702
10054 12:15:52.898800
10055 12:15:52.898885
10056 12:15:52.899191 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10058 12:15:52.999819 asurada: tftpboot 192.168.201.1 12669525/tftp-deploy-lgfg2yfe/kernel/image.itb 12669525/tftp-deploy-lgfg2yfe/kernel/cmdline
10059 12:15:53.000393 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 12:15:53.000868 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10061 12:15:53.005267 tftpboot 192.168.201.1 12669525/tftp-deploy-lgfg2yfe/kernel/image.ittp-deploy-lgfg2yfe/kernel/cmdline
10062 12:15:53.005860
10063 12:15:53.006312 Waiting for link
10064 12:15:53.165871
10065 12:15:53.166418 R8152: Initializing
10066 12:15:53.166871
10067 12:15:53.169077 Version 6 (ocp_data = 5c30)
10068 12:15:53.169662
10069 12:15:53.172256 R8152: Done initializing
10070 12:15:53.172687
10071 12:15:53.173123 Adding net device
10072 12:15:55.121845
10073 12:15:55.122003 done.
10074 12:15:55.122098
10075 12:15:55.122179 MAC: 00:24:32:30:78:ff
10076 12:15:55.122258
10077 12:15:55.124902 Sending DHCP discover... done.
10078 12:15:55.124987
10079 12:15:55.128229 Waiting for reply... done.
10080 12:15:55.128314
10081 12:15:55.131752 Sending DHCP request... done.
10082 12:15:55.131837
10083 12:15:55.141188 Waiting for reply... done.
10084 12:15:55.141285
10085 12:15:55.141385 My ip is 192.168.201.21
10086 12:15:55.141488
10087 12:15:55.144225 The DHCP server ip is 192.168.201.1
10088 12:15:55.144324
10089 12:15:55.151256 TFTP server IP predefined by user: 192.168.201.1
10090 12:15:55.151436
10091 12:15:55.157667 Bootfile predefined by user: 12669525/tftp-deploy-lgfg2yfe/kernel/image.itb
10092 12:15:55.157838
10093 12:15:55.160933 Sending tftp read request... done.
10094 12:15:55.161092
10095 12:15:55.165254 Waiting for the transfer...
10096 12:15:55.165419
10097 12:15:55.894278 00000000 ################################################################
10098 12:15:55.894884
10099 12:15:56.623190 00080000 ################################################################
10100 12:15:56.623871
10101 12:15:57.380636 00100000 ################################################################
10102 12:15:57.381186
10103 12:15:58.118593 00180000 ################################################################
10104 12:15:58.119133
10105 12:15:58.866272 00200000 ################################################################
10106 12:15:58.866784
10107 12:15:59.590008 00280000 ################################################################
10108 12:15:59.590513
10109 12:16:00.338320 00300000 ################################################################
10110 12:16:00.338851
10111 12:16:01.088707 00380000 ################################################################
10112 12:16:01.089236
10113 12:16:01.847091 00400000 ################################################################
10114 12:16:01.847620
10115 12:16:02.603168 00480000 ################################################################
10116 12:16:02.603686
10117 12:16:03.349990 00500000 ################################################################
10118 12:16:03.350509
10119 12:16:04.100796 00580000 ################################################################
10120 12:16:04.101306
10121 12:16:04.849414 00600000 ################################################################
10122 12:16:04.850001
10123 12:16:05.602707 00680000 ################################################################
10124 12:16:05.603218
10125 12:16:06.346569 00700000 ################################################################
10126 12:16:06.347091
10127 12:16:07.094872 00780000 ################################################################
10128 12:16:07.095409
10129 12:16:07.848874 00800000 ################################################################
10130 12:16:07.849393
10131 12:16:08.604944 00880000 ################################################################
10132 12:16:08.605457
10133 12:16:09.359104 00900000 ################################################################
10134 12:16:09.359619
10135 12:16:10.102320 00980000 ################################################################
10136 12:16:10.102866
10137 12:16:10.841858 00a00000 ################################################################
10138 12:16:10.842441
10139 12:16:11.593344 00a80000 ################################################################
10140 12:16:11.593913
10141 12:16:12.349732 00b00000 ################################################################
10142 12:16:12.350255
10143 12:16:13.090276 00b80000 ################################################################
10144 12:16:13.090841
10145 12:16:13.838567 00c00000 ################################################################
10146 12:16:13.839087
10147 12:16:14.573351 00c80000 ################################################################
10148 12:16:14.573971
10149 12:16:15.327083 00d00000 ################################################################
10150 12:16:15.327614
10151 12:16:16.069853 00d80000 ################################################################
10152 12:16:16.070392
10153 12:16:16.810356 00e00000 ################################################################
10154 12:16:16.810875
10155 12:16:17.563975 00e80000 ################################################################
10156 12:16:17.564487
10157 12:16:18.302930 00f00000 ################################################################
10158 12:16:18.303467
10159 12:16:19.036453 00f80000 ################################################################
10160 12:16:19.036976
10161 12:16:19.763716 01000000 ################################################################
10162 12:16:19.764242
10163 12:16:20.501541 01080000 ################################################################
10164 12:16:20.502064
10165 12:16:21.233801 01100000 ################################################################
10166 12:16:21.234351
10167 12:16:21.965283 01180000 ################################################################
10168 12:16:21.965855
10169 12:16:22.715130 01200000 ################################################################
10170 12:16:22.715644
10171 12:16:23.457145 01280000 ################################################################
10172 12:16:23.457762
10173 12:16:24.194536 01300000 ################################################################
10174 12:16:24.195043
10175 12:16:24.937212 01380000 ################################################################
10176 12:16:24.937749
10177 12:16:25.656874 01400000 ################################################################
10178 12:16:25.657382
10179 12:16:26.380413 01480000 ################################################################
10180 12:16:26.380980
10181 12:16:27.109165 01500000 ################################################################
10182 12:16:27.109935
10183 12:16:27.826780 01580000 ################################################################
10184 12:16:27.827304
10185 12:16:28.558114 01600000 ################################################################
10186 12:16:28.558631
10187 12:16:29.310694 01680000 ################################################################
10188 12:16:29.311237
10189 12:16:30.041963 01700000 ################################################################
10190 12:16:30.042509
10191 12:16:30.785376 01780000 ################################################################
10192 12:16:30.785952
10193 12:16:31.536301 01800000 ################################################################
10194 12:16:31.536838
10195 12:16:32.289036 01880000 ################################################################
10196 12:16:32.289656
10197 12:16:33.040183 01900000 ################################################################
10198 12:16:33.040693
10199 12:16:33.781626 01980000 ################################################################
10200 12:16:33.782130
10201 12:16:34.512965 01a00000 ################################################################
10202 12:16:34.513507
10203 12:16:35.256583 01a80000 ################################################################
10204 12:16:35.257095
10205 12:16:36.011846 01b00000 ################################################################
10206 12:16:36.012376
10207 12:16:36.760741 01b80000 ################################################################
10208 12:16:36.761273
10209 12:16:37.490584 01c00000 ################################################################
10210 12:16:37.491090
10211 12:16:38.214977 01c80000 ################################################################
10212 12:16:38.215777
10213 12:16:38.945699 01d00000 ################################################################
10214 12:16:38.946232
10215 12:16:39.686776 01d80000 ################################################################
10216 12:16:39.687311
10217 12:16:40.426481 01e00000 ################################################################
10218 12:16:40.427015
10219 12:16:41.176399 01e80000 ################################################################
10220 12:16:41.176919
10221 12:16:41.929392 01f00000 ################################################################
10222 12:16:41.929936
10223 12:16:42.683417 01f80000 ################################################################
10224 12:16:42.683951
10225 12:16:43.413057 02000000 ################################################################
10226 12:16:43.413643
10227 12:16:44.146176 02080000 ################################################################
10228 12:16:44.146694
10229 12:16:44.881619 02100000 ################################################################
10230 12:16:44.882155
10231 12:16:45.623846 02180000 ################################################################
10232 12:16:45.624368
10233 12:16:46.361149 02200000 ################################################################
10234 12:16:46.361759
10235 12:16:46.997929 02280000 ################################################################
10236 12:16:46.998294
10237 12:16:47.642994 02300000 ################################################################
10238 12:16:47.643372
10239 12:16:48.307125 02380000 ################################################################
10240 12:16:48.307316
10241 12:16:48.894078 02400000 ################################################################
10242 12:16:48.894235
10243 12:16:49.479545 02480000 ################################################################
10244 12:16:49.479698
10245 12:16:50.167899 02500000 ################################################################
10246 12:16:50.168422
10247 12:16:50.902078 02580000 ################################################################
10248 12:16:50.902589
10249 12:16:51.634773 02600000 ################################################################
10250 12:16:51.635297
10251 12:16:52.366322 02680000 ################################################################
10252 12:16:52.366831
10253 12:16:53.087833 02700000 ################################################################
10254 12:16:53.088354
10255 12:16:53.754859 02780000 ################################################################
10256 12:16:53.755367
10257 12:16:54.477681 02800000 ################################################################
10258 12:16:54.478219
10259 12:16:55.183915 02880000 ################################################################
10260 12:16:55.184053
10261 12:16:55.795814 02900000 ################################################################
10262 12:16:55.795951
10263 12:16:56.396754 02980000 ################################################################
10264 12:16:56.396904
10265 12:16:56.986382 02a00000 ################################################################
10266 12:16:56.986530
10267 12:16:57.558315 02a80000 ################################################################
10268 12:16:57.558463
10269 12:16:58.128740 02b00000 ################################################################
10270 12:16:58.128878
10271 12:16:58.697239 02b80000 ################################################################
10272 12:16:58.697388
10273 12:16:59.278485 02c00000 ################################################################
10274 12:16:59.278630
10275 12:16:59.882278 02c80000 ################################################################
10276 12:16:59.882434
10277 12:17:00.492400 02d00000 ################################################################
10278 12:17:00.492554
10279 12:17:01.099038 02d80000 ################################################################
10280 12:17:01.099187
10281 12:17:01.695770 02e00000 ################################################################
10282 12:17:01.695941
10283 12:17:02.297432 02e80000 ################################################################
10284 12:17:02.297589
10285 12:17:02.877803 02f00000 ################################################################
10286 12:17:02.877955
10287 12:17:03.484655 02f80000 ################################################################
10288 12:17:03.484812
10289 12:17:04.088745 03000000 ################################################################
10290 12:17:04.088901
10291 12:17:04.671340 03080000 ################################################################
10292 12:17:04.671498
10293 12:17:04.748337 03100000 ######### done.
10294 12:17:04.748493
10295 12:17:04.751778 The bootfile was 51450898 bytes long.
10296 12:17:04.751875
10297 12:17:04.754822 Sending tftp read request... done.
10298 12:17:04.754907
10299 12:17:04.754972 Waiting for the transfer...
10300 12:17:04.755045
10301 12:17:04.758348 00000000 # done.
10302 12:17:04.758446
10303 12:17:04.764823 Command line loaded dynamically from TFTP file: 12669525/tftp-deploy-lgfg2yfe/kernel/cmdline
10304 12:17:04.764922
10305 12:17:04.778060 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10306 12:17:04.778198
10307 12:17:04.781400 Loading FIT.
10308 12:17:04.781547
10309 12:17:04.785056 Image ramdisk-1 has 39354301 bytes.
10310 12:17:04.785144
10311 12:17:04.785243 Image fdt-1 has 47278 bytes.
10312 12:17:04.788042
10313 12:17:04.788127 Image kernel-1 has 12047284 bytes.
10314 12:17:04.788211
10315 12:17:04.798234 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10316 12:17:04.798344
10317 12:17:04.814923 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10318 12:17:04.815067
10319 12:17:04.821212 Choosing best match conf-1 for compat google,spherion-rev2.
10320 12:17:04.825309
10321 12:17:04.830165 Connected to device vid:did:rid of 1ae0:0028:00
10322 12:17:04.836974
10323 12:17:04.840014 tpm_get_response: command 0x17b, return code 0x0
10324 12:17:04.840134
10325 12:17:04.843510 ec_init: CrosEC protocol v3 supported (256, 248)
10326 12:17:04.847736
10327 12:17:04.850587 tpm_cleanup: add release locality here.
10328 12:17:04.850677
10329 12:17:04.850778 Shutting down all USB controllers.
10330 12:17:04.853960
10331 12:17:04.854045 Removing current net device
10332 12:17:04.854130
10333 12:17:04.860736 Exiting depthcharge with code 4 at timestamp: 105385234
10334 12:17:04.860843
10335 12:17:04.864227 LZMA decompressing kernel-1 to 0x821a6718
10336 12:17:04.864318
10337 12:17:04.867220 LZMA decompressing kernel-1 to 0x40000000
10338 12:17:06.367007
10339 12:17:06.367165 jumping to kernel
10340 12:17:06.367908 end: 2.2.4 bootloader-commands (duration 00:01:18) [common]
10341 12:17:06.368047 start: 2.2.5 auto-login-action (timeout 00:03:08) [common]
10342 12:17:06.368161 Setting prompt string to ['Linux version [0-9]']
10343 12:17:06.368267 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10344 12:17:06.368371 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10345 12:17:06.448800
10346 12:17:06.452217 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10347 12:17:06.455409 start: 2.2.5.1 login-action (timeout 00:03:08) [common]
10348 12:17:06.455511 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10349 12:17:06.455594 Setting prompt string to []
10350 12:17:06.455696 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10351 12:17:06.455781 Using line separator: #'\n'#
10352 12:17:06.455874 No login prompt set.
10353 12:17:06.455975 Parsing kernel messages
10354 12:17:06.456065 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10355 12:17:06.456241 [login-action] Waiting for messages, (timeout 00:03:08)
10356 12:17:06.475062 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j93261-arm64-gcc-10-defconfig-arm64-chromebook-cwjwh) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024
10357 12:17:06.478386 [ 0.000000] random: crng init done
10358 12:17:06.485006 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10359 12:17:06.488350 [ 0.000000] efi: UEFI not found.
10360 12:17:06.494797 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10361 12:17:06.501448 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10362 12:17:06.511387 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10363 12:17:06.521657 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10364 12:17:06.528145 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10365 12:17:06.534767 [ 0.000000] printk: bootconsole [mtk8250] enabled
10366 12:17:06.541180 [ 0.000000] NUMA: No NUMA configuration found
10367 12:17:06.548124 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10368 12:17:06.551213 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10369 12:17:06.554458 [ 0.000000] Zone ranges:
10370 12:17:06.561182 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10371 12:17:06.564347 [ 0.000000] DMA32 empty
10372 12:17:06.571054 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10373 12:17:06.574153 [ 0.000000] Movable zone start for each node
10374 12:17:06.577882 [ 0.000000] Early memory node ranges
10375 12:17:06.584037 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10376 12:17:06.590714 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10377 12:17:06.597241 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10378 12:17:06.603826 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10379 12:17:06.610450 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10380 12:17:06.617078 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10381 12:17:06.673136 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10382 12:17:06.679768 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10383 12:17:06.686343 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10384 12:17:06.689890 [ 0.000000] psci: probing for conduit method from DT.
10385 12:17:06.696424 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10386 12:17:06.699541 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10387 12:17:06.706269 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10388 12:17:06.709466 [ 0.000000] psci: SMC Calling Convention v1.2
10389 12:17:06.716015 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10390 12:17:06.719369 [ 0.000000] Detected VIPT I-cache on CPU0
10391 12:17:06.726038 [ 0.000000] CPU features: detected: GIC system register CPU interface
10392 12:17:06.732651 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10393 12:17:06.739164 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10394 12:17:06.745987 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10395 12:17:06.752386 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10396 12:17:06.762347 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10397 12:17:06.765406 [ 0.000000] alternatives: applying boot alternatives
10398 12:17:06.772074 [ 0.000000] Fallback order for Node 0: 0
10399 12:17:06.779034 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10400 12:17:06.782054 [ 0.000000] Policy zone: Normal
10401 12:17:06.795126 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10402 12:17:06.805029 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10403 12:17:06.817027 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10404 12:17:06.827082 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10405 12:17:06.833866 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10406 12:17:06.837001 <6>[ 0.000000] software IO TLB: area num 8.
10407 12:17:06.893600 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10408 12:17:07.042725 <6>[ 0.000000] Memory: 7928824K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 423944K reserved, 32768K cma-reserved)
10409 12:17:07.049359 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10410 12:17:07.055926 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10411 12:17:07.059090 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10412 12:17:07.065810 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10413 12:17:07.072300 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10414 12:17:07.075752 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10415 12:17:07.085577 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10416 12:17:07.092102 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10417 12:17:07.098709 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10418 12:17:07.105222 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10419 12:17:07.108611 <6>[ 0.000000] GICv3: 608 SPIs implemented
10420 12:17:07.111855 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10421 12:17:07.118733 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10422 12:17:07.122078 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10423 12:17:07.128656 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10424 12:17:07.141710 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10425 12:17:07.154780 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10426 12:17:07.161395 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10427 12:17:07.169270 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10428 12:17:07.182679 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10429 12:17:07.189054 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10430 12:17:07.195733 <6>[ 0.009237] Console: colour dummy device 80x25
10431 12:17:07.205520 <6>[ 0.013984] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10432 12:17:07.212435 <6>[ 0.024426] pid_max: default: 32768 minimum: 301
10433 12:17:07.215655 <6>[ 0.029327] LSM: Security Framework initializing
10434 12:17:07.222295 <6>[ 0.034295] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10435 12:17:07.232030 <6>[ 0.042108] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10436 12:17:07.239068 <6>[ 0.051525] cblist_init_generic: Setting adjustable number of callback queues.
10437 12:17:07.245418 <6>[ 0.058967] cblist_init_generic: Setting shift to 3 and lim to 1.
10438 12:17:07.255644 <6>[ 0.065307] cblist_init_generic: Setting adjustable number of callback queues.
10439 12:17:07.261801 <6>[ 0.072733] cblist_init_generic: Setting shift to 3 and lim to 1.
10440 12:17:07.265230 <6>[ 0.079132] rcu: Hierarchical SRCU implementation.
10441 12:17:07.271956 <6>[ 0.084148] rcu: Max phase no-delay instances is 1000.
10442 12:17:07.278465 <6>[ 0.091172] EFI services will not be available.
10443 12:17:07.281817 <6>[ 0.096157] smp: Bringing up secondary CPUs ...
10444 12:17:07.289977 <6>[ 0.101235] Detected VIPT I-cache on CPU1
10445 12:17:07.296603 <6>[ 0.101305] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10446 12:17:07.303245 <6>[ 0.101337] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10447 12:17:07.306633 <6>[ 0.101674] Detected VIPT I-cache on CPU2
10448 12:17:07.313176 <6>[ 0.101724] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10449 12:17:07.323004 <6>[ 0.101740] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10450 12:17:07.326463 <6>[ 0.101997] Detected VIPT I-cache on CPU3
10451 12:17:07.332878 <6>[ 0.102043] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10452 12:17:07.339491 <6>[ 0.102057] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10453 12:17:07.346343 <6>[ 0.102360] CPU features: detected: Spectre-v4
10454 12:17:07.349444 <6>[ 0.102366] CPU features: detected: Spectre-BHB
10455 12:17:07.352578 <6>[ 0.102371] Detected PIPT I-cache on CPU4
10456 12:17:07.359589 <6>[ 0.102427] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10457 12:17:07.365847 <6>[ 0.102444] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10458 12:17:07.372607 <6>[ 0.102733] Detected PIPT I-cache on CPU5
10459 12:17:07.379272 <6>[ 0.102795] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10460 12:17:07.385822 <6>[ 0.102812] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10461 12:17:07.389180 <6>[ 0.103090] Detected PIPT I-cache on CPU6
10462 12:17:07.395609 <6>[ 0.103155] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10463 12:17:07.402435 <6>[ 0.103172] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10464 12:17:07.409170 <6>[ 0.103468] Detected PIPT I-cache on CPU7
10465 12:17:07.415882 <6>[ 0.103532] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10466 12:17:07.422126 <6>[ 0.103549] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10467 12:17:07.425472 <6>[ 0.103596] smp: Brought up 1 node, 8 CPUs
10468 12:17:07.432082 <6>[ 0.245059] SMP: Total of 8 processors activated.
10469 12:17:07.435415 <6>[ 0.249980] CPU features: detected: 32-bit EL0 Support
10470 12:17:07.445603 <6>[ 0.255343] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10471 12:17:07.452200 <6>[ 0.264143] CPU features: detected: Common not Private translations
10472 12:17:07.458761 <6>[ 0.270618] CPU features: detected: CRC32 instructions
10473 12:17:07.461888 <6>[ 0.275970] CPU features: detected: RCpc load-acquire (LDAPR)
10474 12:17:07.468950 <6>[ 0.281967] CPU features: detected: LSE atomic instructions
10475 12:17:07.475383 <6>[ 0.287748] CPU features: detected: Privileged Access Never
10476 12:17:07.481817 <6>[ 0.293527] CPU features: detected: RAS Extension Support
10477 12:17:07.488472 <6>[ 0.299171] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10478 12:17:07.491805 <6>[ 0.306435] CPU: All CPU(s) started at EL2
10479 12:17:07.498430 <6>[ 0.310752] alternatives: applying system-wide alternatives
10480 12:17:07.507987 <6>[ 0.321475] devtmpfs: initialized
10481 12:17:07.523597 <6>[ 0.330460] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10482 12:17:07.530214 <6>[ 0.340420] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10483 12:17:07.536875 <6>[ 0.348654] pinctrl core: initialized pinctrl subsystem
10484 12:17:07.540357 <6>[ 0.355291] DMI not present or invalid.
10485 12:17:07.546644 <6>[ 0.359702] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10486 12:17:07.556523 <6>[ 0.366515] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10487 12:17:07.563236 <6>[ 0.374100] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10488 12:17:07.573019 <6>[ 0.382330] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10489 12:17:07.576326 <6>[ 0.390575] audit: initializing netlink subsys (disabled)
10490 12:17:07.586280 <5>[ 0.396268] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10491 12:17:07.592815 <6>[ 0.396966] thermal_sys: Registered thermal governor 'step_wise'
10492 12:17:07.599462 <6>[ 0.404237] thermal_sys: Registered thermal governor 'power_allocator'
10493 12:17:07.602874 <6>[ 0.410494] cpuidle: using governor menu
10494 12:17:07.609432 <6>[ 0.421456] NET: Registered PF_QIPCRTR protocol family
10495 12:17:07.616172 <6>[ 0.426930] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10496 12:17:07.622625 <6>[ 0.434032] ASID allocator initialised with 32768 entries
10497 12:17:07.625955 <6>[ 0.440594] Serial: AMBA PL011 UART driver
10498 12:17:07.635908 <4>[ 0.449366] Trying to register duplicate clock ID: 134
10499 12:17:07.691810 <6>[ 0.508755] KASLR enabled
10500 12:17:07.705980 <6>[ 0.516523] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10501 12:17:07.713010 <6>[ 0.523535] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10502 12:17:07.719566 <6>[ 0.530023] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10503 12:17:07.725942 <6>[ 0.537029] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10504 12:17:07.732852 <6>[ 0.543516] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10505 12:17:07.739320 <6>[ 0.550521] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10506 12:17:07.745869 <6>[ 0.557010] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10507 12:17:07.752257 <6>[ 0.564014] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10508 12:17:07.755672 <6>[ 0.571537] ACPI: Interpreter disabled.
10509 12:17:07.764474 <6>[ 0.577974] iommu: Default domain type: Translated
10510 12:17:07.771085 <6>[ 0.583088] iommu: DMA domain TLB invalidation policy: strict mode
10511 12:17:07.774551 <5>[ 0.589748] SCSI subsystem initialized
10512 12:17:07.781041 <6>[ 0.593912] usbcore: registered new interface driver usbfs
10513 12:17:07.787546 <6>[ 0.599646] usbcore: registered new interface driver hub
10514 12:17:07.790732 <6>[ 0.605197] usbcore: registered new device driver usb
10515 12:17:07.797863 <6>[ 0.611307] pps_core: LinuxPPS API ver. 1 registered
10516 12:17:07.807852 <6>[ 0.616499] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10517 12:17:07.810791 <6>[ 0.625846] PTP clock support registered
10518 12:17:07.813968 <6>[ 0.630090] EDAC MC: Ver: 3.0.0
10519 12:17:07.821812 <6>[ 0.635242] FPGA manager framework
10520 12:17:07.828391 <6>[ 0.638924] Advanced Linux Sound Architecture Driver Initialized.
10521 12:17:07.831455 <6>[ 0.645699] vgaarb: loaded
10522 12:17:07.838622 <6>[ 0.648860] clocksource: Switched to clocksource arch_sys_counter
10523 12:17:07.841576 <5>[ 0.655308] VFS: Disk quotas dquot_6.6.0
10524 12:17:07.848095 <6>[ 0.659494] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10525 12:17:07.851409 <6>[ 0.666682] pnp: PnP ACPI: disabled
10526 12:17:07.860022 <6>[ 0.673476] NET: Registered PF_INET protocol family
10527 12:17:07.869635 <6>[ 0.679084] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10528 12:17:07.881418 <6>[ 0.691444] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10529 12:17:07.891072 <6>[ 0.700262] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10530 12:17:07.897800 <6>[ 0.708232] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10531 12:17:07.907522 <6>[ 0.716936] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10532 12:17:07.914243 <6>[ 0.726694] TCP: Hash tables configured (established 65536 bind 65536)
10533 12:17:07.920768 <6>[ 0.733558] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10534 12:17:07.931028 <6>[ 0.740759] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10535 12:17:07.937393 <6>[ 0.748465] NET: Registered PF_UNIX/PF_LOCAL protocol family
10536 12:17:07.940634 <6>[ 0.754611] RPC: Registered named UNIX socket transport module.
10537 12:17:07.947582 <6>[ 0.760764] RPC: Registered udp transport module.
10538 12:17:07.950697 <6>[ 0.765698] RPC: Registered tcp transport module.
10539 12:17:07.957195 <6>[ 0.770630] RPC: Registered tcp NFSv4.1 backchannel transport module.
10540 12:17:07.963717 <6>[ 0.777295] PCI: CLS 0 bytes, default 64
10541 12:17:07.967043 <6>[ 0.781626] Unpacking initramfs...
10542 12:17:07.990690 <6>[ 0.800971] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10543 12:17:08.000620 <6>[ 0.809642] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10544 12:17:08.003781 <6>[ 0.818417] kvm [1]: IPA Size Limit: 40 bits
10545 12:17:08.010367 <6>[ 0.822945] kvm [1]: GICv3: no GICV resource entry
10546 12:17:08.013500 <6>[ 0.827966] kvm [1]: disabling GICv2 emulation
10547 12:17:08.020452 <6>[ 0.832655] kvm [1]: GIC system register CPU interface enabled
10548 12:17:08.023750 <6>[ 0.838821] kvm [1]: vgic interrupt IRQ18
10549 12:17:08.030320 <6>[ 0.843185] kvm [1]: VHE mode initialized successfully
10550 12:17:08.036798 <5>[ 0.849636] Initialise system trusted keyrings
10551 12:17:08.043330 <6>[ 0.854437] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10552 12:17:08.050747 <6>[ 0.864430] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10553 12:17:08.057366 <5>[ 0.870818] NFS: Registering the id_resolver key type
10554 12:17:08.060472 <5>[ 0.876120] Key type id_resolver registered
10555 12:17:08.067570 <5>[ 0.880537] Key type id_legacy registered
10556 12:17:08.073909 <6>[ 0.884817] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10557 12:17:08.080283 <6>[ 0.891736] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10558 12:17:08.086812 <6>[ 0.899435] 9p: Installing v9fs 9p2000 file system support
10559 12:17:08.123873 <5>[ 0.937671] Key type asymmetric registered
10560 12:17:08.127293 <5>[ 0.942002] Asymmetric key parser 'x509' registered
10561 12:17:08.137419 <6>[ 0.947140] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10562 12:17:08.140594 <6>[ 0.954759] io scheduler mq-deadline registered
10563 12:17:08.143735 <6>[ 0.959539] io scheduler kyber registered
10564 12:17:08.163014 <6>[ 0.976692] EINJ: ACPI disabled.
10565 12:17:08.195144 <4>[ 1.002146] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10566 12:17:08.204723 <4>[ 1.012768] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10567 12:17:08.220035 <6>[ 1.033607] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10568 12:17:08.227994 <6>[ 1.041642] printk: console [ttyS0] disabled
10569 12:17:08.255986 <6>[ 1.066286] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10570 12:17:08.262762 <6>[ 1.075757] printk: console [ttyS0] enabled
10571 12:17:08.265831 <6>[ 1.075757] printk: console [ttyS0] enabled
10572 12:17:08.272607 <6>[ 1.084651] printk: bootconsole [mtk8250] disabled
10573 12:17:08.275934 <6>[ 1.084651] printk: bootconsole [mtk8250] disabled
10574 12:17:08.282499 <6>[ 1.095670] SuperH (H)SCI(F) driver initialized
10575 12:17:08.285754 <6>[ 1.100949] msm_serial: driver initialized
10576 12:17:08.299427 <6>[ 1.109883] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10577 12:17:08.309431 <6>[ 1.118437] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10578 12:17:08.315931 <6>[ 1.126981] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10579 12:17:08.326145 <6>[ 1.135609] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10580 12:17:08.336421 <6>[ 1.144316] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10581 12:17:08.342620 <6>[ 1.153034] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10582 12:17:08.352456 <6>[ 1.161575] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10583 12:17:08.359375 <6>[ 1.170362] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10584 12:17:08.369063 <6>[ 1.178904] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10585 12:17:08.380503 <6>[ 1.194342] loop: module loaded
10586 12:17:08.387193 <6>[ 1.200391] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10587 12:17:08.410228 <4>[ 1.223805] mtk-pmic-keys: Failed to locate of_node [id: -1]
10588 12:17:08.417014 <6>[ 1.230616] megasas: 07.719.03.00-rc1
10589 12:17:08.426553 <6>[ 1.240270] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10590 12:17:08.434654 <6>[ 1.248241] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10591 12:17:08.451537 <6>[ 1.264925] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10592 12:17:08.507438 <6>[ 1.314320] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10593 12:17:09.566836 <6>[ 2.380605] Freeing initrd memory: 38428K
10594 12:17:09.577048 <6>[ 2.390993] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10595 12:17:09.588370 <6>[ 2.402166] tun: Universal TUN/TAP device driver, 1.6
10596 12:17:09.591691 <6>[ 2.408236] thunder_xcv, ver 1.0
10597 12:17:09.595103 <6>[ 2.411745] thunder_bgx, ver 1.0
10598 12:17:09.598442 <6>[ 2.415242] nicpf, ver 1.0
10599 12:17:09.608795 <6>[ 2.419272] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10600 12:17:09.612081 <6>[ 2.426748] hns3: Copyright (c) 2017 Huawei Corporation.
10601 12:17:09.618815 <6>[ 2.432336] hclge is initializing
10602 12:17:09.622033 <6>[ 2.435915] e1000: Intel(R) PRO/1000 Network Driver
10603 12:17:09.628498 <6>[ 2.441044] e1000: Copyright (c) 1999-2006 Intel Corporation.
10604 12:17:09.632206 <6>[ 2.447057] e1000e: Intel(R) PRO/1000 Network Driver
10605 12:17:09.638698 <6>[ 2.452273] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10606 12:17:09.645379 <6>[ 2.458459] igb: Intel(R) Gigabit Ethernet Network Driver
10607 12:17:09.651669 <6>[ 2.464109] igb: Copyright (c) 2007-2014 Intel Corporation.
10608 12:17:09.658328 <6>[ 2.469947] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10609 12:17:09.665103 <6>[ 2.476466] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10610 12:17:09.668430 <6>[ 2.482927] sky2: driver version 1.30
10611 12:17:09.675025 <6>[ 2.487919] VFIO - User Level meta-driver version: 0.3
10612 12:17:09.682443 <6>[ 2.496131] usbcore: registered new interface driver usb-storage
10613 12:17:09.688997 <6>[ 2.502584] usbcore: registered new device driver onboard-usb-hub
10614 12:17:09.697853 <6>[ 2.511746] mt6397-rtc mt6359-rtc: registered as rtc0
10615 12:17:09.707926 <6>[ 2.517214] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-31T12:17:09 UTC (1706703429)
10616 12:17:09.711042 <6>[ 2.526781] i2c_dev: i2c /dev entries driver
10617 12:17:09.728138 <6>[ 2.538627] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10618 12:17:09.747691 <6>[ 2.561616] cpu cpu0: EM: created perf domain
10619 12:17:09.750970 <6>[ 2.566542] cpu cpu4: EM: created perf domain
10620 12:17:09.758562 <6>[ 2.572191] sdhci: Secure Digital Host Controller Interface driver
10621 12:17:09.764871 <6>[ 2.578625] sdhci: Copyright(c) Pierre Ossman
10622 12:17:09.771641 <6>[ 2.583583] Synopsys Designware Multimedia Card Interface Driver
10623 12:17:09.778256 <6>[ 2.590218] sdhci-pltfm: SDHCI platform and OF driver helper
10624 12:17:09.781466 <6>[ 2.590257] mmc0: CQHCI version 5.10
10625 12:17:09.788174 <6>[ 2.600415] ledtrig-cpu: registered to indicate activity on CPUs
10626 12:17:09.794611 <6>[ 2.607597] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10627 12:17:09.801299 <6>[ 2.614665] usbcore: registered new interface driver usbhid
10628 12:17:09.804725 <6>[ 2.620487] usbhid: USB HID core driver
10629 12:17:09.814411 <6>[ 2.624687] spi_master spi0: will run message pump with realtime priority
10630 12:17:09.855271 <6>[ 2.662116] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10631 12:17:09.873799 <6>[ 2.677353] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10632 12:17:09.881000 <6>[ 2.692352] cros-ec-spi spi0.0: Chrome EC device registered
10633 12:17:09.884121 <6>[ 2.698386] mmc0: Command Queue Engine enabled
10634 12:17:09.890737 <6>[ 2.703158] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10635 12:17:09.897264 <6>[ 2.711048] mmcblk0: mmc0:0001 DA4128 116 GiB
10636 12:17:09.907109 <6>[ 2.720894] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10637 12:17:09.914856 <6>[ 2.728700] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10638 12:17:09.924753 <6>[ 2.734165] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10639 12:17:09.931361 <6>[ 2.734926] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10640 12:17:09.934478 <6>[ 2.744901] NET: Registered PF_PACKET protocol family
10641 12:17:09.941159 <6>[ 2.749393] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10642 12:17:09.947945 <6>[ 2.754087] 9pnet: Installing 9P2000 support
10643 12:17:09.951304 <5>[ 2.765091] Key type dns_resolver registered
10644 12:17:09.954456 <6>[ 2.770074] registered taskstats version 1
10645 12:17:09.962029 <5>[ 2.774458] Loading compiled-in X.509 certificates
10646 12:17:09.989874 <4>[ 2.796990] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10647 12:17:09.999664 <4>[ 2.807742] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10648 12:17:10.006438 <3>[ 2.818296] debugfs: File 'uA_load' in directory '/' already present!
10649 12:17:10.012972 <3>[ 2.825070] debugfs: File 'min_uV' in directory '/' already present!
10650 12:17:10.019561 <3>[ 2.831696] debugfs: File 'max_uV' in directory '/' already present!
10651 12:17:10.026195 <3>[ 2.838363] debugfs: File 'constraint_flags' in directory '/' already present!
10652 12:17:10.037212 <3>[ 2.847754] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10653 12:17:10.047182 <6>[ 2.861135] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10654 12:17:10.054236 <6>[ 2.867959] xhci-mtk 11200000.usb: xHCI Host Controller
10655 12:17:10.060763 <6>[ 2.873466] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10656 12:17:10.071041 <6>[ 2.881402] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10657 12:17:10.077615 <6>[ 2.890833] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10658 12:17:10.084130 <6>[ 2.896910] xhci-mtk 11200000.usb: xHCI Host Controller
10659 12:17:10.090774 <6>[ 2.902388] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10660 12:17:10.097257 <6>[ 2.910039] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10661 12:17:10.104284 <6>[ 2.917828] hub 1-0:1.0: USB hub found
10662 12:17:10.107204 <6>[ 2.921848] hub 1-0:1.0: 1 port detected
10663 12:17:10.117251 <6>[ 2.926118] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10664 12:17:10.120518 <6>[ 2.934846] hub 2-0:1.0: USB hub found
10665 12:17:10.123747 <6>[ 2.938865] hub 2-0:1.0: 1 port detected
10666 12:17:10.133015 <6>[ 2.946725] mtk-msdc 11f70000.mmc: Got CD GPIO
10667 12:17:10.149247 <6>[ 2.959883] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10668 12:17:10.156055 <6>[ 2.968012] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10669 12:17:10.165972 <4>[ 2.975931] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10670 12:17:10.175860 <6>[ 2.985480] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10671 12:17:10.182434 <6>[ 2.993561] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10672 12:17:10.192338 <6>[ 3.001588] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10673 12:17:10.198916 <6>[ 3.009503] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10674 12:17:10.205725 <6>[ 3.017337] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10675 12:17:10.215614 <6>[ 3.025155] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10676 12:17:10.225441 <6>[ 3.035575] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10677 12:17:10.231889 <6>[ 3.043935] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10678 12:17:10.241872 <6>[ 3.052300] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10679 12:17:10.248464 <6>[ 3.060642] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10680 12:17:10.258489 <6>[ 3.068995] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10681 12:17:10.268326 <6>[ 3.077334] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10682 12:17:10.274897 <6>[ 3.085684] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10683 12:17:10.284932 <6>[ 3.094022] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10684 12:17:10.291593 <6>[ 3.102371] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10685 12:17:10.301354 <6>[ 3.110710] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10686 12:17:10.308127 <6>[ 3.119048] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10687 12:17:10.317976 <6>[ 3.127387] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10688 12:17:10.324540 <6>[ 3.135726] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10689 12:17:10.334515 <6>[ 3.144064] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10690 12:17:10.341157 <6>[ 3.152405] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10691 12:17:10.347649 <6>[ 3.161185] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10692 12:17:10.354637 <6>[ 3.168386] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10693 12:17:10.361186 <6>[ 3.175145] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10694 12:17:10.371226 <6>[ 3.181899] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10695 12:17:10.378007 <6>[ 3.188834] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10696 12:17:10.384739 <6>[ 3.195678] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10697 12:17:10.394440 <6>[ 3.204805] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10698 12:17:10.404378 <6>[ 3.213947] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10699 12:17:10.414226 <6>[ 3.223245] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10700 12:17:10.424422 <6>[ 3.232712] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10701 12:17:10.431023 <6>[ 3.242186] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10702 12:17:10.440753 <6>[ 3.251305] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10703 12:17:10.450696 <6>[ 3.260770] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10704 12:17:10.460554 <6>[ 3.269888] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10705 12:17:10.470332 <6>[ 3.279183] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10706 12:17:10.480181 <6>[ 3.289344] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10707 12:17:10.490290 <6>[ 3.300875] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10708 12:17:10.514532 <6>[ 3.325160] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10709 12:17:10.542062 <6>[ 3.355947] hub 2-1:1.0: USB hub found
10710 12:17:10.545383 <6>[ 3.360369] hub 2-1:1.0: 3 ports detected
10711 12:17:10.553264 <6>[ 3.367231] hub 2-1:1.0: USB hub found
10712 12:17:10.556650 <6>[ 3.371701] hub 2-1:1.0: 3 ports detected
10713 12:17:10.666625 <6>[ 3.477159] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10714 12:17:10.821247 <6>[ 3.635158] hub 1-1:1.0: USB hub found
10715 12:17:10.824905 <6>[ 3.639638] hub 1-1:1.0: 4 ports detected
10716 12:17:10.834384 <6>[ 3.648242] hub 1-1:1.0: USB hub found
10717 12:17:10.837547 <6>[ 3.652596] hub 1-1:1.0: 4 ports detected
10718 12:17:10.906765 <6>[ 3.717211] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10719 12:17:11.158674 <6>[ 3.969161] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10720 12:17:11.290860 <6>[ 4.104907] hub 1-1.4:1.0: USB hub found
10721 12:17:11.294289 <6>[ 4.109536] hub 1-1.4:1.0: 2 ports detected
10722 12:17:11.303820 <6>[ 4.117863] hub 1-1.4:1.0: USB hub found
10723 12:17:11.307109 <6>[ 4.122475] hub 1-1.4:1.0: 2 ports detected
10724 12:17:11.606351 <6>[ 4.417171] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10725 12:17:11.798439 <6>[ 4.609174] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10726 12:17:22.779338 <6>[ 15.598143] ALSA device list:
10727 12:17:22.785782 <6>[ 15.601432] No soundcards found.
10728 12:17:22.794158 <6>[ 15.609452] Freeing unused kernel memory: 8448K
10729 12:17:22.797356 <6>[ 15.614471] Run /init as init process
10730 12:17:22.843559 <6>[ 15.658701] NET: Registered PF_INET6 protocol family
10731 12:17:22.850311 <6>[ 15.664800] Segment Routing with IPv6
10732 12:17:22.853340 <6>[ 15.668744] In-situ OAM (IOAM) with IPv6
10733 12:17:22.887472 <30>[ 15.682907] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10734 12:17:22.890807 <30>[ 15.706765] systemd[1]: Detected architecture arm64.
10735 12:17:22.891399
10736 12:17:22.897639 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10737 12:17:22.898042
10738 12:17:22.910309 <30>[ 15.725222] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10739 12:17:23.031861 <30>[ 15.843773] systemd[1]: Queued start job for default target Graphical Interface.
10740 12:17:23.070556 <30>[ 15.886114] systemd[1]: Created slice system-getty.slice.
10741 12:17:23.077279 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10742 12:17:23.093983 <30>[ 15.909475] systemd[1]: Created slice system-modprobe.slice.
10743 12:17:23.100423 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10744 12:17:23.118581 <30>[ 15.933989] systemd[1]: Created slice system-serial\x2dgetty.slice.
10745 12:17:23.128778 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10746 12:17:23.142276 <30>[ 15.957689] systemd[1]: Created slice User and Session Slice.
10747 12:17:23.148998 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10748 12:17:23.170083 <30>[ 15.981938] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10749 12:17:23.180279 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10750 12:17:23.198235 <30>[ 16.009333] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10751 12:17:23.204298 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10752 12:17:23.224730 <30>[ 16.033195] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10753 12:17:23.231373 <30>[ 16.045356] systemd[1]: Reached target Local Encrypted Volumes.
10754 12:17:23.237849 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10755 12:17:23.254984 <30>[ 16.069685] systemd[1]: Reached target Paths.
10756 12:17:23.258129 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10757 12:17:23.274257 <30>[ 16.089139] systemd[1]: Reached target Remote File Systems.
10758 12:17:23.280532 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10759 12:17:23.298490 <30>[ 16.113505] systemd[1]: Reached target Slices.
10760 12:17:23.305018 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10761 12:17:23.318230 <30>[ 16.133136] systemd[1]: Reached target Swap.
10762 12:17:23.321412 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10763 12:17:23.341859 <30>[ 16.153615] systemd[1]: Listening on initctl Compatibility Named Pipe.
10764 12:17:23.348293 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10765 12:17:23.363154 <30>[ 16.177986] systemd[1]: Listening on Journal Audit Socket.
10766 12:17:23.369550 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10767 12:17:23.387216 <30>[ 16.202320] systemd[1]: Listening on Journal Socket (/dev/log).
10768 12:17:23.394094 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10769 12:17:23.410660 <30>[ 16.225703] systemd[1]: Listening on Journal Socket.
10770 12:17:23.417245 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10771 12:17:23.434032 <30>[ 16.245837] systemd[1]: Listening on Network Service Netlink Socket.
10772 12:17:23.440654 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10773 12:17:23.455385 <30>[ 16.270409] systemd[1]: Listening on udev Control Socket.
10774 12:17:23.462032 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10775 12:17:23.478898 <30>[ 16.294209] systemd[1]: Listening on udev Kernel Socket.
10776 12:17:23.485286 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10777 12:17:23.525952 <30>[ 16.341201] systemd[1]: Mounting Huge Pages File System...
10778 12:17:23.532698 Mounting [0;1;39mHuge Pages File System[0m...
10779 12:17:23.550103 <30>[ 16.365167] systemd[1]: Mounting POSIX Message Queue File System...
10780 12:17:23.557049 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10781 12:17:23.606405 <30>[ 16.421224] systemd[1]: Mounting Kernel Debug File System...
10782 12:17:23.612509 Mounting [0;1;39mKernel Debug File System[0m...
10783 12:17:23.629769 <30>[ 16.441537] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10784 12:17:23.657718 <30>[ 16.469380] systemd[1]: Starting Create list of static device nodes for the current kernel...
10785 12:17:23.664030 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10786 12:17:23.686821 <30>[ 16.501531] systemd[1]: Starting Load Kernel Module configfs...
10787 12:17:23.693001 Starting [0;1;39mLoad Kernel Module configfs[0m...
10788 12:17:23.710410 <30>[ 16.525419] systemd[1]: Starting Load Kernel Module drm...
10789 12:17:23.717121 Starting [0;1;39mLoad Kernel Module drm[0m...
10790 12:17:23.733944 <30>[ 16.545474] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10791 12:17:23.767057 <30>[ 16.581667] systemd[1]: Starting Journal Service...
10792 12:17:23.770199 Starting [0;1;39mJournal Service[0m...
10793 12:17:23.789605 <30>[ 16.604054] systemd[1]: Starting Load Kernel Modules...
10794 12:17:23.795970 Starting [0;1;39mLoad Kernel Modules[0m...
10795 12:17:23.818758 <30>[ 16.630216] systemd[1]: Starting Remount Root and Kernel File Systems...
10796 12:17:23.825431 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10797 12:17:23.842062 <30>[ 16.656590] systemd[1]: Starting Coldplug All udev Devices...
10798 12:17:23.848520 Starting [0;1;39mColdplug All udev Devices[0m...
10799 12:17:23.864927 <30>[ 16.679938] systemd[1]: Started Journal Service.
10800 12:17:23.871746 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10801 12:17:23.888379 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10802 12:17:23.907132 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10803 12:17:23.923189 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10804 12:17:23.943833 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10805 12:17:23.960185 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10806 12:17:23.975838 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10807 12:17:23.992867 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10808 12:17:24.012312 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10809 12:17:24.026189 See 'systemctl status systemd-remount-fs.service' for details.
10810 12:17:24.064381 Mounting [0;1;39mKernel Configuration File System[0m...
10811 12:17:24.081823 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10812 12:17:24.094732 <46>[ 16.906391] systemd-journald[177]: Received client request to flush runtime journal.
10813 12:17:24.104821 Starting [0;1;39mLoad/Save Random Seed[0m...
10814 12:17:24.122253 Starting [0;1;39mApply Kernel Variables[0m...
10815 12:17:24.142342 Starting [0;1;39mCreate System Users[0m...
10816 12:17:24.161897 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10817 12:17:24.179554 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10818 12:17:24.199529 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10819 12:17:24.212378 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10820 12:17:24.228742 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10821 12:17:24.247865 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10822 12:17:24.295265 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10823 12:17:24.314974 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10824 12:17:24.326892 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10825 12:17:24.342331 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10826 12:17:24.387456 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10827 12:17:24.417875 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10828 12:17:24.436715 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10829 12:17:24.448334 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10830 12:17:24.503581 Starting [0;1;39mNetwork Service[0m...
10831 12:17:24.525192 Starting [0;1;39mNetwork Time Synchronization[0m...
10832 12:17:24.549635 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10833 12:17:24.594657 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10834 12:17:24.617816 <6>[ 17.428844] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10835 12:17:24.623970 <6>[ 17.431752] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10836 12:17:24.633683 <6>[ 17.436996] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10837 12:17:24.637176 <6>[ 17.448137] remoteproc remoteproc0: scp is available
10838 12:17:24.647330 <6>[ 17.452743] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10839 12:17:24.650440 <6>[ 17.459013] remoteproc remoteproc0: powering up scp
10840 12:17:24.660790 <6>[ 17.472627] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10841 12:17:24.667692 <3>[ 17.473157] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10842 12:17:24.677616 [[0;32m OK [<6>[ 17.481194] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10843 12:17:24.684137 <3>[ 17.489359] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10844 12:17:24.694002 0m] Started [0;<6>[ 17.498201] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10845 12:17:24.701279 <4>[ 17.498212] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10846 12:17:24.710711 1;39mNetwork Tim<4>[ 17.498349] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10847 12:17:24.717115 <3>[ 17.504307] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10848 12:17:24.723581 e Synchronizatio<6>[ 17.510899] mc: Linux media interface: v0.10
10849 12:17:24.724074 n[0m.
10850 12:17:24.733372 <3>[ 17.532337] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10851 12:17:24.740075 <4>[ 17.542892] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10852 12:17:24.747481 <4>[ 17.542892] Fallback method does not support PEC.
10853 12:17:24.754021 <3>[ 17.543655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 12:17:24.760908 <6>[ 17.567162] usbcore: registered new device driver r8152-cfgselector
10855 12:17:24.770591 <3>[ 17.569865] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10856 12:17:24.777601 <3>[ 17.574278] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10857 12:17:24.784108 <6>[ 17.596153] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10858 12:17:24.791571 <3>[ 17.597581] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10859 12:17:24.801347 <3>[ 17.597593] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10860 12:17:24.808341 <3>[ 17.598692] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10861 12:17:24.814655 <6>[ 17.604486] pci_bus 0000:00: root bus resource [bus 00-ff]
10862 12:17:24.821764 <6>[ 17.604494] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10863 12:17:24.831766 <6>[ 17.604499] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10864 12:17:24.838737 <6>[ 17.604553] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10865 12:17:24.845157 <3>[ 17.607317] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10866 12:17:24.855903 <3>[ 17.608135] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10867 12:17:24.862505 <3>[ 17.613206] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10868 12:17:24.873073 <6>[ 17.620782] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10869 12:17:24.879809 <6>[ 17.621752] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10870 12:17:24.885960 <6>[ 17.621758] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10871 12:17:24.892794 <6>[ 17.621764] remoteproc remoteproc0: remote processor scp is now up
10872 12:17:24.902748 <3>[ 17.628829] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10873 12:17:24.909262 <3>[ 17.631225] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 12:17:24.915722 <6>[ 17.634966] pci 0000:00:00.0: supports D1 D2
10875 12:17:24.925754 <6>[ 17.637104] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10876 12:17:24.932794 <3>[ 17.641738] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10877 12:17:24.940301 <3>[ 17.641790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10878 12:17:24.947349 <6>[ 17.651662] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10879 12:17:24.957086 <6>[ 17.652656] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10880 12:17:24.963737 <6>[ 17.653897] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10881 12:17:24.973934 <3>[ 17.656500] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 12:17:24.980901 <3>[ 17.657902] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10883 12:17:24.987564 <6>[ 17.667599] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10884 12:17:24.997375 <3>[ 17.675789] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10885 12:17:25.004737 <3>[ 17.675793] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10886 12:17:25.014404 <6>[ 17.677311] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10887 12:17:25.024630 <6>[ 17.677769] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10888 12:17:25.031901 <6>[ 17.678176] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10889 12:17:25.041441 <3>[ 17.678926] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 12:17:25.048607 <6>[ 17.684050] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10891 12:17:25.055508 <3>[ 17.691342] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10892 12:17:25.062125 <6>[ 17.691951] videodev: Linux video capture interface: v2.00
10893 12:17:25.068883 <6>[ 17.699889] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10894 12:17:25.076379 <4>[ 17.704407] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10895 12:17:25.085959 <4>[ 17.704417] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10896 12:17:25.092817 <3>[ 17.706934] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10897 12:17:25.096690 <6>[ 17.707675] Bluetooth: Core ver 2.22
10898 12:17:25.103525 <6>[ 17.707726] NET: Registered PF_BLUETOOTH protocol family
10899 12:17:25.110344 <6>[ 17.707727] Bluetooth: HCI device and connection manager initialized
10900 12:17:25.116519 <6>[ 17.707741] Bluetooth: HCI socket layer initialized
10901 12:17:25.120166 <6>[ 17.707745] Bluetooth: L2CAP socket layer initialized
10902 12:17:25.126538 <6>[ 17.707752] Bluetooth: SCO socket layer initialized
10903 12:17:25.133592 <6>[ 17.713352] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10904 12:17:25.136940 <6>[ 17.753416] r8152 2-1.3:1.0 eth0: v1.12.13
10905 12:17:25.143387 <6>[ 17.760301] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10906 12:17:25.150174 <6>[ 17.762501] usbcore: registered new interface driver btusb
10907 12:17:25.156446 <6>[ 17.762545] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10908 12:17:25.169655 <4>[ 17.763081] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10909 12:17:25.173148 <3>[ 17.763101] Bluetooth: hci0: Failed to load firmware file (-2)
10910 12:17:25.179453 <3>[ 17.763107] Bluetooth: hci0: Failed to set up firmware (-2)
10911 12:17:25.189149 <4>[ 17.763114] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10912 12:17:25.202625 <6>[ 17.765237] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10913 12:17:25.209245 <6>[ 17.765368] usbcore: registered new interface driver uvcvideo
10914 12:17:25.215475 <6>[ 17.767807] usbcore: registered new interface driver r8152
10915 12:17:25.219197 <6>[ 17.775514] pci 0000:01:00.0: supports D1 D2
10916 12:17:25.229066 <3>[ 17.786684] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10917 12:17:25.235864 <6>[ 17.792436] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10918 12:17:25.241887 <6>[ 17.793496] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10919 12:17:25.249061 <6>[ 17.800904] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10920 12:17:25.255406 <3>[ 17.800913] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 12:17:25.265655 <3>[ 17.801720] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 12:17:25.271831 <6>[ 17.809188] usbcore: registered new interface driver cdc_ether
10923 12:17:25.278403 <6>[ 17.817001] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10924 12:17:25.288308 <3>[ 17.824754] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 12:17:25.294875 <6>[ 17.843612] usbcore: registered new interface driver r8153_ecm
10926 12:17:25.301761 <6>[ 17.852506] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10927 12:17:25.311776 <6>[ 17.852516] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10928 12:17:25.317906 <6>[ 17.876267] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10929 12:17:25.324876 <6>[ 17.881353] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10930 12:17:25.331127 <6>[ 18.144784] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10931 12:17:25.338200 <6>[ 18.153039] pci 0000:00:00.0: PCI bridge to [bus 01]
10932 12:17:25.348269 [[0;32m OK [<6>[ 18.158488] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10933 12:17:25.354478 0m] Found device<6>[ 18.168024] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10934 12:17:25.364406 [0;1;39m/dev/t<6>[ 18.176297] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10935 12:17:25.364906 tyS0[0m.
10936 12:17:25.371114 <6>[ 18.183892] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10937 12:17:25.390448 <5>[ 18.201876] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10938 12:17:25.397056 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10939 12:17:25.413238 <5>[ 18.224976] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10940 12:17:25.420001 <5>[ 18.232379] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10941 12:17:25.429622 <4>[ 18.240791] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10942 12:17:25.433160 <6>[ 18.249675] cfg80211: failed to load regulatory.db
10943 12:17:25.475725 <6>[ 18.287126] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10944 12:17:25.482070 <6>[ 18.294724] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10945 12:17:25.488862 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10946 12:17:25.505787 [[0;32m OK [0m] Reached target [0;1;39mBlue<6>[ 18.321509] mt7921e 0000:01:00.0: ASIC revision: 79610010
10947 12:17:25.509075 tooth[0m.
10948 12:17:25.522449 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10949 12:17:25.538302 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10950 12:17:25.557769 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10951 12:17:25.589842 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10952 12:17:25.609902 <6>[ 18.421442] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10953 12:17:25.613253 <6>[ 18.421442]
10954 12:17:25.619842 Starting [0;1;39mNetwork Name Resolution[0m...
10955 12:17:25.639317 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10956 12:17:25.655673 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10957 12:17:25.674766 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10958 12:17:25.690357 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10959 12:17:25.706668 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10960 12:17:25.726685 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10961 12:17:25.738463 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10962 12:17:25.754591 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10963 12:17:25.786966 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10964 12:17:25.820395 Starting [0;1;39mUser Login Management[0m...
10965 12:17:25.837155 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10966 12:17:25.855237 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10967 12:17:25.877898 [[0;32m OK [0m] Started [0;1;39mLoad/Save R<6>[ 18.689554] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10968 12:17:25.881325 F Kill Switch Status[0m.
10969 12:17:25.899285 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10970 12:17:25.917426 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10971 12:17:25.955440 Starting [0;1;39mPermit User Sessions[0m...
10972 12:17:25.972979 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10973 12:17:25.991344 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10974 12:17:26.019949 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10975 12:17:26.039777 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10976 12:17:26.055119 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10977 12:17:26.070590 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10978 12:17:26.086409 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10979 12:17:26.123297 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10980 12:17:26.158225 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10981 12:17:26.200792
10982 12:17:26.201304
10983 12:17:26.203734 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10984 12:17:26.204145
10985 12:17:26.206867 debian-bullseye-arm64 login: root (automatic login)
10986 12:17:26.207279
10987 12:17:26.207601
10988 12:17:26.235841 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024 aarch64
10989 12:17:26.236354
10990 12:17:26.241855 The programs included with the Debian GNU/Linux system are free software;
10991 12:17:26.248999 the exact distribution terms for each program are described in the
10992 12:17:26.252129 individual files in /usr/share/doc/*/copyright.
10993 12:17:26.252646
10994 12:17:26.258492 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10995 12:17:26.261674 permitted by applicable law.
10996 12:17:26.262948 Matched prompt #10: / #
10998 12:17:26.263924 Setting prompt string to ['/ #']
10999 12:17:26.264348 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11001 12:17:26.265299 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11002 12:17:26.265840 start: 2.2.6 expect-shell-connection (timeout 00:02:48) [common]
11003 12:17:26.266359 Setting prompt string to ['/ #']
11004 12:17:26.266689 Forcing a shell prompt, looking for ['/ #']
11006 12:17:26.317531 / #
11007 12:17:26.318139 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11008 12:17:26.318567 Waiting using forced prompt support (timeout 00:02:30)
11009 12:17:26.323886
11010 12:17:26.324764 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11011 12:17:26.325246 start: 2.2.7 export-device-env (timeout 00:02:48) [common]
11012 12:17:26.325786 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11013 12:17:26.326215 end: 2.2 depthcharge-retry (duration 00:02:12) [common]
11014 12:17:26.326652 end: 2 depthcharge-action (duration 00:02:12) [common]
11015 12:17:26.327082 start: 3 lava-test-retry (timeout 00:07:28) [common]
11016 12:17:26.327502 start: 3.1 lava-test-shell (timeout 00:07:28) [common]
11017 12:17:26.327863 Using namespace: common
11019 12:17:26.429053 / # #
11020 12:17:26.429689 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11021 12:17:26.435234 #
11022 12:17:26.436064 Using /lava-12669525
11024 12:17:26.537167 / # export SHELL=/bin/sh
11025 12:17:26.582020 export SHELL=/bin/sh<6>[ 19.353390] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11026 12:17:26.582547 <6>[ 19.361589] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11027 12:17:26.582892
11029 12:17:26.684277 / # . /lava-12669525/environment
11030 12:17:26.690880 . /lava-12669525/environment
11032 12:17:26.792547 / # /lava-12669525/bin/lava-test-runner /lava-12669525/0
11033 12:17:26.793125 Test shell timeout: 10s (minimum of the action and connection timeout)
11034 12:17:26.794725 <6>[ 19.543569] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11035 12:17:26.798751 /lava-12669525/bin/lava-test-runner /lava-12669525/0
11036 12:17:26.845930 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11037 12:17:26.846454 + cd /lava-12669525/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11038 12:17:26.846788 + cat uuid
11039 12:17:26.847099 + UUID=12669525_1.5.2.3.1
11040 12:17:26.847400 + set +x
11041 12:17:26.847695 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 12669525_1.5.2.3.1>
11042 12:17:26.847985 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11043 12:17:26.848541 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 12669525_1.5.2.3.1
11044 12:17:26.848880 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (12669525_1.5.2.3.1)
11045 12:17:26.849268 Skipping test definition patterns.
11046 12:17:26.850035 Received signal: <TESTCASE> TEST_CASE_ID<4
11047 12:17:26.850423 Ignoring malformed parameter for signal: "TEST_CASE_ID<4".
11048 12:17:26.852196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID<4>[ 19.665048] use of bytesused == 0 is deprecated and will be removed in the future,
11049 12:17:26.859072 <4>[ 19.673485] use the actual size instead.
11050 12:17:26.859494 =device-presence RESULT=pass>
11051 12:17:26.862046 device: /dev/video2
11052 12:17:26.871369 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11053 12:17:26.881043 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11054 12:17:26.888514
11055 12:17:26.900718 Compliance test for mtk-vcodec-enc device /dev/video2:
11056 12:17:26.907439
11057 12:17:26.918165 Driver Info:
11058 12:17:26.929317 Driver name : mtk-vcodec-enc
11059 12:17:26.942386 Card type : MT8192 video encoder
11060 12:17:26.954452 Bus info : platform:17020000.vcodec
11061 12:17:26.961306 Driver version : 6.1.72
11062 12:17:26.972655 Capabilities : 0x84204000
11063 12:17:26.985943 Video Memory-to-Memory Multiplanar
11064 12:17:26.999255 Streaming
11065 12:17:27.008597 Extended Pix Format
11066 12:17:27.018731 Device Capabilities
11067 12:17:27.032189 Device Caps : 0x04204000
11068 12:17:27.043421 Video Memory-to-Memory Multiplanar
11069 12:17:27.053566 Streaming
11070 12:17:27.066882 Extended Pix Format
11071 12:17:27.079863 Detected Stateful Encoder
11072 12:17:27.091806
11073 12:17:27.103983 Required ioctls:
11074 12:17:27.120446 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11075 12:17:27.120965 test VIDIOC_QUERYCAP: OK
11076 12:17:27.121614 Received signal: <TESTSET> START Required-ioctls
11077 12:17:27.121968 Starting test_set Required-ioctls
11078 12:17:27.144579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11079 12:17:27.145370 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11081 12:17:27.148008 test invalid ioctls: OK
11082 12:17:27.174050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11083 12:17:27.174557
11084 12:17:27.175139 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11086 12:17:27.185630 Allow for multiple opens:
11087 12:17:27.193827 <LAVA_SIGNAL_TESTSET STOP>
11088 12:17:27.194604 Received signal: <TESTSET> STOP
11089 12:17:27.194964 Closing test_set Required-ioctls
11090 12:17:27.205153 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11091 12:17:27.205958 Received signal: <TESTSET> START Allow-for-multiple-opens
11092 12:17:27.206317 Starting test_set Allow-for-multiple-opens
11093 12:17:27.208385 test second /dev/video2 open: OK
11094 12:17:27.230510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11095 12:17:27.231309 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11097 12:17:27.233680 test VIDIOC_QUERYCAP: OK
11098 12:17:27.256171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11099 12:17:27.256997 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11101 12:17:27.259139 test VIDIOC_G/S_PRIORITY: OK
11102 12:17:27.280105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11103 12:17:27.280942 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11105 12:17:27.283303 test for unlimited opens: OK
11106 12:17:27.305256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11107 12:17:27.305807
11108 12:17:27.306420 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11110 12:17:27.314949 Debug ioctls:
11111 12:17:27.325857 <LAVA_SIGNAL_TESTSET STOP>
11112 12:17:27.326659 Received signal: <TESTSET> STOP
11113 12:17:27.327006 Closing test_set Allow-for-multiple-opens
11114 12:17:27.335980 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11115 12:17:27.336763 Received signal: <TESTSET> START Debug-ioctls
11116 12:17:27.337111 Starting test_set Debug-ioctls
11117 12:17:27.339020 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11118 12:17:27.364311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11119 12:17:27.365095 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11121 12:17:27.370878 test VIDIOC_LOG_STATUS: OK (Not Supported)
11122 12:17:27.388789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11123 12:17:27.389310
11124 12:17:27.389977 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11126 12:17:27.399013 Input ioctls:
11127 12:17:27.405693 <LAVA_SIGNAL_TESTSET STOP>
11128 12:17:27.406478 Received signal: <TESTSET> STOP
11129 12:17:27.406833 Closing test_set Debug-ioctls
11130 12:17:27.415369 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11131 12:17:27.416152 Received signal: <TESTSET> START Input-ioctls
11132 12:17:27.416514 Starting test_set Input-ioctls
11133 12:17:27.418680 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11134 12:17:27.441862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11135 12:17:27.442625 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11137 12:17:27.444933 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11138 12:17:27.467826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11139 12:17:27.468604 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11141 12:17:27.474101 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11142 12:17:27.492442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11143 12:17:27.493223 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11145 12:17:27.498910 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11146 12:17:27.516685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11147 12:17:27.517441 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11149 12:17:27.523200 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11150 12:17:27.544910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11151 12:17:27.545692 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11153 12:17:27.548057 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11154 12:17:27.569349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11155 12:17:27.570170 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11157 12:17:27.572239 Inputs: 0 Audio Inputs: 0 Tuners: 0
11158 12:17:27.579863
11159 12:17:27.595505 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11160 12:17:27.617054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11161 12:17:27.617878 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11163 12:17:27.623432 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11164 12:17:27.641893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11165 12:17:27.642665 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11167 12:17:27.648759 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11168 12:17:27.669185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11169 12:17:27.670022 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11171 12:17:27.675977 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11172 12:17:27.695669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11173 12:17:27.696453 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11175 12:17:27.702453 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11176 12:17:27.720289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11177 12:17:27.721105 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11179 12:17:27.724370
11180 12:17:27.741742 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11181 12:17:27.769147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11182 12:17:27.769972 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11184 12:17:27.775606 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11185 12:17:27.799262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11186 12:17:27.800047 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11188 12:17:27.801994 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11189 12:17:27.824377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11190 12:17:27.825153 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11192 12:17:27.828012 test VIDIOC_G/S_EDID: OK (Not Supported)
11193 12:17:27.851036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11194 12:17:27.851553
11195 12:17:27.852159 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11197 12:17:27.860851 Control ioctls:
11198 12:17:27.870696 <LAVA_SIGNAL_TESTSET STOP>
11199 12:17:27.871641 Received signal: <TESTSET> STOP
11200 12:17:27.872196 Closing test_set Input-ioctls
11201 12:17:27.881302 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11202 12:17:27.882055 Received signal: <TESTSET> START Control-ioctls
11203 12:17:27.882475 Starting test_set Control-ioctls
11204 12:17:27.895086 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11205 12:17:27.919282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11206 12:17:27.919701 test VIDIOC_QUERYCTRL: OK
11207 12:17:27.920281 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11209 12:17:27.945586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11210 12:17:27.946377 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11212 12:17:27.948962 test VIDIOC_G/S_CTRL: OK
11213 12:17:27.971869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11214 12:17:27.972533 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11216 12:17:27.974902 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11217 12:17:27.998939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11218 12:17:27.999681 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11220 12:17:28.008844 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11221 12:17:28.015705 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11222 12:17:28.039431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11223 12:17:28.040257 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11225 12:17:28.042244 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11226 12:17:28.062456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11227 12:17:28.063176 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11229 12:17:28.065344 Standard Controls: 16 Private Controls: 0
11230 12:17:28.072441
11231 12:17:28.082541 Format ioctls:
11232 12:17:28.089304 <LAVA_SIGNAL_TESTSET STOP>
11233 12:17:28.090057 Received signal: <TESTSET> STOP
11234 12:17:28.090439 Closing test_set Control-ioctls
11235 12:17:28.098946 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11236 12:17:28.099610 Received signal: <TESTSET> START Format-ioctls
11237 12:17:28.099954 Starting test_set Format-ioctls
11238 12:17:28.102274 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11239 12:17:28.125085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11240 12:17:28.125336 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11242 12:17:28.128505 test VIDIOC_G/S_PARM: OK
11243 12:17:28.145323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11244 12:17:28.145579 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11246 12:17:28.148371 test VIDIOC_G_FBUF: OK (Not Supported)
11247 12:17:28.172705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11248 12:17:28.172956 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11250 12:17:28.175612 test VIDIOC_G_FMT: OK
11251 12:17:28.201461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11252 12:17:28.201735 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11254 12:17:28.204861 test VIDIOC_TRY_FMT: OK
11255 12:17:28.226500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11256 12:17:28.226751 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11258 12:17:28.236350 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11259 12:17:28.236431 test VIDIOC_S_FMT: FAIL
11260 12:17:28.260604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11261 12:17:28.260860 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11263 12:17:28.263888 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11264 12:17:28.285733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11265 12:17:28.285986 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11267 12:17:28.288938 test Cropping: OK
11268 12:17:28.316668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11269 12:17:28.316923 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11271 12:17:28.319909 test Composing: OK (Not Supported)
11272 12:17:28.344863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11273 12:17:28.345118 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11275 12:17:28.348188 test Scaling: OK (Not Supported)
11276 12:17:28.370030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11277 12:17:28.370112
11278 12:17:28.370346 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11280 12:17:28.379966 Codec ioctls:
11281 12:17:28.390543 <LAVA_SIGNAL_TESTSET STOP>
11282 12:17:28.390794 Received signal: <TESTSET> STOP
11283 12:17:28.390863 Closing test_set Format-ioctls
11284 12:17:28.400716 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11285 12:17:28.400968 Received signal: <TESTSET> START Codec-ioctls
11286 12:17:28.401039 Starting test_set Codec-ioctls
11287 12:17:28.404307 test VIDIOC_(TRY_)ENCODER_CMD: OK
11288 12:17:28.427553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11289 12:17:28.427804 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11291 12:17:28.433838 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11292 12:17:28.452995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11293 12:17:28.453277 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11295 12:17:28.459423 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11296 12:17:28.475966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11297 12:17:28.476047
11298 12:17:28.476295 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11300 12:17:28.487657 Buffer ioctls:
11301 12:17:28.493840 <LAVA_SIGNAL_TESTSET STOP>
11302 12:17:28.494105 Received signal: <TESTSET> STOP
11303 12:17:28.494186 Closing test_set Codec-ioctls
11304 12:17:28.503588 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11305 12:17:28.503837 Received signal: <TESTSET> START Buffer-ioctls
11306 12:17:28.503907 Starting test_set Buffer-ioctls
11307 12:17:28.506716 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11308 12:17:28.530840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11309 12:17:28.530923 test VIDIOC_EXPBUF: OK
11310 12:17:28.531158 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11312 12:17:28.553078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11313 12:17:28.553333 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11315 12:17:28.556316 test Requests: OK (Not Supported)
11316 12:17:28.577355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11317 12:17:28.577437
11318 12:17:28.577711 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11320 12:17:28.587919 Test input 0:
11321 12:17:28.598462
11322 12:17:28.609980 Streaming ioctls:
11323 12:17:28.617808 <LAVA_SIGNAL_TESTSET STOP>
11324 12:17:28.618060 Received signal: <TESTSET> STOP
11325 12:17:28.618127 Closing test_set Buffer-ioctls
11326 12:17:28.627090 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11327 12:17:28.627342 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11328 12:17:28.627413 Starting test_set Streaming-ioctls_Test-input-0
11329 12:17:28.630468 test read/write: OK (Not Supported)
11330 12:17:28.652661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11331 12:17:28.652914 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11333 12:17:28.659317 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11334 12:17:28.669290 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11335 12:17:28.676111 test blocking wait: FAIL
11336 12:17:28.701391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11337 12:17:28.701650 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11339 12:17:28.707767 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11340 12:17:28.711356 test MMAP (select): FAIL
11341 12:17:28.735191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11342 12:17:28.735444 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11344 12:17:28.741878 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11345 12:17:28.746004 test MMAP (epoll): FAIL
11346 12:17:28.775875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11347 12:17:28.776127 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11349 12:17:28.785405 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11350 12:17:28.792285 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11351 12:17:28.802834 test USERPTR (select): FAIL
11352 12:17:28.827827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11353 12:17:28.828085 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11355 12:17:28.834440 test DMABUF: Cannot test, specify --expbuf-device
11356 12:17:28.837705
11357 12:17:28.855580 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11358 12:17:28.863644 <LAVA_TEST_RUNNER EXIT>
11359 12:17:28.863893 ok: lava_test_shell seems to have completed
11360 12:17:28.863965 Marking unfinished test run as failed
11362 12:17:28.864908 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11363 12:17:28.865040 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11364 12:17:28.865128 end: 3 lava-test-retry (duration 00:00:03) [common]
11365 12:17:28.865215 start: 4 finalize (timeout 00:07:26) [common]
11366 12:17:28.865322 start: 4.1 power-off (timeout 00:00:30) [common]
11367 12:17:28.865472 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11368 12:17:28.941155 >> Command sent successfully.
11369 12:17:28.943621 Returned 0 in 0 seconds
11370 12:17:29.044020 end: 4.1 power-off (duration 00:00:00) [common]
11372 12:17:29.044362 start: 4.2 read-feedback (timeout 00:07:26) [common]
11373 12:17:29.044647 Listened to connection for namespace 'common' for up to 1s
11374 12:17:30.045569 Finalising connection for namespace 'common'
11375 12:17:30.045736 Disconnecting from shell: Finalise
11376 12:17:30.045816 / #
11377 12:17:30.146144 end: 4.2 read-feedback (duration 00:00:01) [common]
11378 12:17:30.146296 end: 4 finalize (duration 00:00:01) [common]
11379 12:17:30.146410 Cleaning after the job
11380 12:17:30.146559 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669525/tftp-deploy-lgfg2yfe/ramdisk
11381 12:17:30.152080 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669525/tftp-deploy-lgfg2yfe/kernel
11382 12:17:30.160888 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669525/tftp-deploy-lgfg2yfe/dtb
11383 12:17:30.161053 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669525/tftp-deploy-lgfg2yfe/modules
11384 12:17:30.168405 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12669525
11385 12:17:30.236004 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12669525
11386 12:17:30.236186 Job finished correctly