Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 16
- Kernel Errors: 32
1 12:19:54.501578 lava-dispatcher, installed at version: 2023.10
2 12:19:54.501784 start: 0 validate
3 12:19:54.501916 Start time: 2024-01-31 12:19:54.501908+00:00 (UTC)
4 12:19:54.502031 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:19:54.502161 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:19:54.768609 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:19:54.768775 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:19:55.033508 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:19:55.033682 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:19:55.297543 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:19:55.297725 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:19:55.561597 validate duration: 1.06
14 12:19:55.561871 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:19:55.561968 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:19:55.562058 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:19:55.562183 Not decompressing ramdisk as can be used compressed.
18 12:19:55.562272 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 12:19:55.562341 saving as /var/lib/lava/dispatcher/tmp/12669542/tftp-deploy-z9t3o5tx/ramdisk/rootfs.cpio.gz
20 12:19:55.562405 total size: 26246609 (25 MB)
21 12:19:55.563470 progress 0 % (0 MB)
22 12:19:55.570617 progress 5 % (1 MB)
23 12:19:55.577678 progress 10 % (2 MB)
24 12:19:55.584548 progress 15 % (3 MB)
25 12:19:55.591437 progress 20 % (5 MB)
26 12:19:55.598281 progress 25 % (6 MB)
27 12:19:55.605203 progress 30 % (7 MB)
28 12:19:55.612082 progress 35 % (8 MB)
29 12:19:55.619162 progress 40 % (10 MB)
30 12:19:55.626099 progress 45 % (11 MB)
31 12:19:55.632907 progress 50 % (12 MB)
32 12:19:55.639696 progress 55 % (13 MB)
33 12:19:55.646551 progress 60 % (15 MB)
34 12:19:55.653365 progress 65 % (16 MB)
35 12:19:55.660259 progress 70 % (17 MB)
36 12:19:55.667145 progress 75 % (18 MB)
37 12:19:55.674033 progress 80 % (20 MB)
38 12:19:55.680911 progress 85 % (21 MB)
39 12:19:55.687599 progress 90 % (22 MB)
40 12:19:55.694372 progress 95 % (23 MB)
41 12:19:55.701110 progress 100 % (25 MB)
42 12:19:55.701363 25 MB downloaded in 0.14 s (180.13 MB/s)
43 12:19:55.701522 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:19:55.701764 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:19:55.701851 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:19:55.701936 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:19:55.702073 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:19:55.702146 saving as /var/lib/lava/dispatcher/tmp/12669542/tftp-deploy-z9t3o5tx/kernel/Image
50 12:19:55.702207 total size: 51532288 (49 MB)
51 12:19:55.702267 No compression specified
52 12:19:55.703394 progress 0 % (0 MB)
53 12:19:55.716746 progress 5 % (2 MB)
54 12:19:55.730283 progress 10 % (4 MB)
55 12:19:55.743641 progress 15 % (7 MB)
56 12:19:55.757394 progress 20 % (9 MB)
57 12:19:55.770897 progress 25 % (12 MB)
58 12:19:55.784119 progress 30 % (14 MB)
59 12:19:55.797579 progress 35 % (17 MB)
60 12:19:55.811067 progress 40 % (19 MB)
61 12:19:55.824345 progress 45 % (22 MB)
62 12:19:55.837683 progress 50 % (24 MB)
63 12:19:55.850848 progress 55 % (27 MB)
64 12:19:55.864452 progress 60 % (29 MB)
65 12:19:55.878022 progress 65 % (31 MB)
66 12:19:55.891248 progress 70 % (34 MB)
67 12:19:55.904724 progress 75 % (36 MB)
68 12:19:55.918237 progress 80 % (39 MB)
69 12:19:55.931534 progress 85 % (41 MB)
70 12:19:55.944879 progress 90 % (44 MB)
71 12:19:55.958139 progress 95 % (46 MB)
72 12:19:55.971211 progress 100 % (49 MB)
73 12:19:55.971430 49 MB downloaded in 0.27 s (182.55 MB/s)
74 12:19:55.971582 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:19:55.971819 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:19:55.971908 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:19:55.972000 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:19:55.972140 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:19:55.972210 saving as /var/lib/lava/dispatcher/tmp/12669542/tftp-deploy-z9t3o5tx/dtb/mt8192-asurada-spherion-r0.dtb
81 12:19:55.972272 total size: 47278 (0 MB)
82 12:19:55.972381 No compression specified
83 12:19:55.973569 progress 69 % (0 MB)
84 12:19:55.973842 progress 100 % (0 MB)
85 12:19:55.973997 0 MB downloaded in 0.00 s (26.18 MB/s)
86 12:19:55.974119 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:19:55.974339 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:19:55.974424 start: 1.4 download-retry (timeout 00:10:00) [common]
90 12:19:55.974507 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 12:19:55.974623 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:19:55.974693 saving as /var/lib/lava/dispatcher/tmp/12669542/tftp-deploy-z9t3o5tx/modules/modules.tar
93 12:19:55.974755 total size: 8639916 (8 MB)
94 12:19:55.974815 Using unxz to decompress xz
95 12:19:55.979046 progress 0 % (0 MB)
96 12:19:56.000136 progress 5 % (0 MB)
97 12:19:56.023855 progress 10 % (0 MB)
98 12:19:56.047315 progress 15 % (1 MB)
99 12:19:56.070644 progress 20 % (1 MB)
100 12:19:56.094536 progress 25 % (2 MB)
101 12:19:56.122484 progress 30 % (2 MB)
102 12:19:56.146781 progress 35 % (2 MB)
103 12:19:56.170061 progress 40 % (3 MB)
104 12:19:56.194350 progress 45 % (3 MB)
105 12:19:56.219370 progress 50 % (4 MB)
106 12:19:56.246962 progress 55 % (4 MB)
107 12:19:56.274244 progress 60 % (4 MB)
108 12:19:56.300111 progress 65 % (5 MB)
109 12:19:56.324982 progress 70 % (5 MB)
110 12:19:56.348071 progress 75 % (6 MB)
111 12:19:56.375777 progress 80 % (6 MB)
112 12:19:56.403615 progress 85 % (7 MB)
113 12:19:56.428743 progress 90 % (7 MB)
114 12:19:56.458258 progress 95 % (7 MB)
115 12:19:56.486297 progress 100 % (8 MB)
116 12:19:56.492169 8 MB downloaded in 0.52 s (15.92 MB/s)
117 12:19:56.492464 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:19:56.492733 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:19:56.492826 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:19:56.492921 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:19:56.493002 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:19:56.493089 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:19:56.493306 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v
125 12:19:56.493442 makedir: /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin
126 12:19:56.493548 makedir: /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/tests
127 12:19:56.493646 makedir: /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/results
128 12:19:56.493765 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-add-keys
129 12:19:56.493912 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-add-sources
130 12:19:56.494045 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-background-process-start
131 12:19:56.494174 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-background-process-stop
132 12:19:56.494358 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-common-functions
133 12:19:56.494631 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-echo-ipv4
134 12:19:56.494764 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-install-packages
135 12:19:56.494891 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-installed-packages
136 12:19:56.495020 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-os-build
137 12:19:56.495147 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-probe-channel
138 12:19:56.495292 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-probe-ip
139 12:19:56.495461 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-target-ip
140 12:19:56.495589 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-target-mac
141 12:19:56.495745 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-target-storage
142 12:19:56.495875 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-test-case
143 12:19:56.496001 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-test-event
144 12:19:56.496144 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-test-feedback
145 12:19:56.496272 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-test-raise
146 12:19:56.496424 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-test-reference
147 12:19:56.496550 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-test-runner
148 12:19:56.496675 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-test-set
149 12:19:56.496802 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-test-shell
150 12:19:56.496931 Updating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-install-packages (oe)
151 12:19:56.497085 Updating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/bin/lava-installed-packages (oe)
152 12:19:56.497208 Creating /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/environment
153 12:19:56.497307 LAVA metadata
154 12:19:56.497380 - LAVA_JOB_ID=12669542
155 12:19:56.497444 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:19:56.497543 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:19:56.497611 skipped lava-vland-overlay
158 12:19:56.497683 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:19:56.497760 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:19:56.497827 skipped lava-multinode-overlay
161 12:19:56.497899 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:19:56.497982 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:19:56.498056 Loading test definitions
164 12:19:56.498149 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:19:56.498222 Using /lava-12669542 at stage 0
166 12:19:56.498527 uuid=12669542_1.5.2.3.1 testdef=None
167 12:19:56.498613 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:19:56.498695 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:19:56.499209 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:19:56.499422 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:19:56.500025 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:19:56.500253 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:19:56.500939 runner path: /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/0/tests/0_v4l2-compliance-uvc test_uuid 12669542_1.5.2.3.1
176 12:19:56.501145 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:19:56.501349 Creating lava-test-runner.conf files
179 12:19:56.501414 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12669542/lava-overlay-25abmh9v/lava-12669542/0 for stage 0
180 12:19:56.501503 - 0_v4l2-compliance-uvc
181 12:19:56.501598 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:19:56.501681 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:19:56.508416 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:19:56.508520 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:19:56.508606 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:19:56.508688 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:19:56.508776 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:19:57.232673 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:19:57.233057 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:19:57.233170 extracting modules file /var/lib/lava/dispatcher/tmp/12669542/tftp-deploy-z9t3o5tx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669542/extract-overlay-ramdisk-u_00cfno/ramdisk
191 12:19:57.463875 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:19:57.464045 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:19:57.464171 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669542/compress-overlay-pbqwi_bt/overlay-1.5.2.4.tar.gz to ramdisk
194 12:19:57.464245 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669542/compress-overlay-pbqwi_bt/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12669542/extract-overlay-ramdisk-u_00cfno/ramdisk
195 12:19:57.470846 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:19:57.470962 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:19:57.471053 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:19:57.471143 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:19:57.471221 Building ramdisk /var/lib/lava/dispatcher/tmp/12669542/extract-overlay-ramdisk-u_00cfno/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12669542/extract-overlay-ramdisk-u_00cfno/ramdisk
200 12:19:58.155351 >> 228442 blocks
201 12:20:02.060510 rename /var/lib/lava/dispatcher/tmp/12669542/extract-overlay-ramdisk-u_00cfno/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12669542/tftp-deploy-z9t3o5tx/ramdisk/ramdisk.cpio.gz
202 12:20:02.060962 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 12:20:02.061091 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 12:20:02.061193 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 12:20:02.061294 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12669542/tftp-deploy-z9t3o5tx/kernel/Image'
206 12:20:15.120907 Returned 0 in 13 seconds
207 12:20:15.221573 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12669542/tftp-deploy-z9t3o5tx/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12669542/tftp-deploy-z9t3o5tx/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12669542/tftp-deploy-z9t3o5tx/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12669542/tftp-deploy-z9t3o5tx/kernel/image.itb
208 12:20:15.863527 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:20:15.863896 output: Created: Wed Jan 31 12:20:15 2024
210 12:20:15.863970 output: Image 0 (kernel-1)
211 12:20:15.864036 output: Description:
212 12:20:15.864099 output: Created: Wed Jan 31 12:20:15 2024
213 12:20:15.864161 output: Type: Kernel Image
214 12:20:15.864220 output: Compression: lzma compressed
215 12:20:15.864278 output: Data Size: 12047284 Bytes = 11764.93 KiB = 11.49 MiB
216 12:20:15.864378 output: Architecture: AArch64
217 12:20:15.864431 output: OS: Linux
218 12:20:15.864484 output: Load Address: 0x00000000
219 12:20:15.864539 output: Entry Point: 0x00000000
220 12:20:15.864591 output: Hash algo: crc32
221 12:20:15.864645 output: Hash value: 5a47eb78
222 12:20:15.864698 output: Image 1 (fdt-1)
223 12:20:15.864750 output: Description: mt8192-asurada-spherion-r0
224 12:20:15.864801 output: Created: Wed Jan 31 12:20:15 2024
225 12:20:15.864852 output: Type: Flat Device Tree
226 12:20:15.864903 output: Compression: uncompressed
227 12:20:15.864954 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 12:20:15.865005 output: Architecture: AArch64
229 12:20:15.865056 output: Hash algo: crc32
230 12:20:15.865107 output: Hash value: cc4352de
231 12:20:15.865158 output: Image 2 (ramdisk-1)
232 12:20:15.865209 output: Description: unavailable
233 12:20:15.865259 output: Created: Wed Jan 31 12:20:15 2024
234 12:20:15.865310 output: Type: RAMDisk Image
235 12:20:15.865361 output: Compression: Unknown Compression
236 12:20:15.865411 output: Data Size: 39362318 Bytes = 38439.76 KiB = 37.54 MiB
237 12:20:15.865462 output: Architecture: AArch64
238 12:20:15.865513 output: OS: Linux
239 12:20:15.865564 output: Load Address: unavailable
240 12:20:15.865614 output: Entry Point: unavailable
241 12:20:15.865665 output: Hash algo: crc32
242 12:20:15.865715 output: Hash value: 2a9fc8fd
243 12:20:15.865766 output: Default Configuration: 'conf-1'
244 12:20:15.865816 output: Configuration 0 (conf-1)
245 12:20:15.865867 output: Description: mt8192-asurada-spherion-r0
246 12:20:15.865918 output: Kernel: kernel-1
247 12:20:15.865969 output: Init Ramdisk: ramdisk-1
248 12:20:15.866019 output: FDT: fdt-1
249 12:20:15.866070 output: Loadables: kernel-1
250 12:20:15.866120 output:
251 12:20:15.866324 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:20:15.866421 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:20:15.866518 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 12:20:15.866612 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 12:20:15.866689 No LXC device requested
256 12:20:15.866770 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:20:15.866850 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 12:20:15.866924 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:20:15.866995 Checking files for TFTP limit of 4294967296 bytes.
260 12:20:15.867492 end: 1 tftp-deploy (duration 00:00:20) [common]
261 12:20:15.867595 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:20:15.867685 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:20:15.867807 substitutions:
264 12:20:15.867873 - {DTB}: 12669542/tftp-deploy-z9t3o5tx/dtb/mt8192-asurada-spherion-r0.dtb
265 12:20:15.867936 - {INITRD}: 12669542/tftp-deploy-z9t3o5tx/ramdisk/ramdisk.cpio.gz
266 12:20:15.867993 - {KERNEL}: 12669542/tftp-deploy-z9t3o5tx/kernel/Image
267 12:20:15.868049 - {LAVA_MAC}: None
268 12:20:15.868103 - {PRESEED_CONFIG}: None
269 12:20:15.868168 - {PRESEED_LOCAL}: None
270 12:20:15.868257 - {RAMDISK}: 12669542/tftp-deploy-z9t3o5tx/ramdisk/ramdisk.cpio.gz
271 12:20:15.868367 - {ROOT_PART}: None
272 12:20:15.868422 - {ROOT}: None
273 12:20:15.868475 - {SERVER_IP}: 192.168.201.1
274 12:20:15.868528 - {TEE}: None
275 12:20:15.868581 Parsed boot commands:
276 12:20:15.868634 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:20:15.868816 Parsed boot commands: tftpboot 192.168.201.1 12669542/tftp-deploy-z9t3o5tx/kernel/image.itb 12669542/tftp-deploy-z9t3o5tx/kernel/cmdline
278 12:20:15.868902 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:20:15.868989 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:20:15.869087 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:20:15.869169 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:20:15.869237 Not connected, no need to disconnect.
283 12:20:15.869308 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:20:15.869387 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:20:15.869450 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 12:20:15.873499 Setting prompt string to ['lava-test: # ']
287 12:20:15.873871 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:20:15.873983 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:20:15.874079 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:20:15.874220 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:20:15.874456 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 12:20:21.011964 >> Command sent successfully.
293 12:20:21.014327 Returned 0 in 5 seconds
294 12:20:21.114742 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:20:21.115102 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:20:21.115215 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:20:21.115316 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:20:21.115394 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:20:21.115484 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:20:21.115838 [Enter `^Ec?' for help]
302 12:20:21.287234
303 12:20:21.287377
304 12:20:21.287473 F0: 102B 0000
305 12:20:21.287560
306 12:20:21.287644 F3: 1001 0000 [0200]
307 12:20:21.290337
308 12:20:21.290412 F3: 1001 0000
309 12:20:21.290493
310 12:20:21.290571 F7: 102D 0000
311 12:20:21.290647
312 12:20:21.294228 F1: 0000 0000
313 12:20:21.294313
314 12:20:21.294415 V0: 0000 0000 [0001]
315 12:20:21.294518
316 12:20:21.297504 00: 0007 8000
317 12:20:21.297593
318 12:20:21.297680 01: 0000 0000
319 12:20:21.297783
320 12:20:21.300468 BP: 0C00 0209 [0000]
321 12:20:21.300553
322 12:20:21.300655 G0: 1182 0000
323 12:20:21.300755
324 12:20:21.300853 EC: 0000 0021 [4000]
325 12:20:21.304324
326 12:20:21.304424 S7: 0000 0000 [0000]
327 12:20:21.304522
328 12:20:21.307798 CC: 0000 0000 [0001]
329 12:20:21.307908
330 12:20:21.308011 T0: 0000 0040 [010F]
331 12:20:21.308093
332 12:20:21.308190 Jump to BL
333 12:20:21.308295
334 12:20:21.334659
335 12:20:21.334746
336 12:20:21.334832
337 12:20:21.341099 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:20:21.344899 ARM64: Exception handlers installed.
339 12:20:21.348299 ARM64: Testing exception
340 12:20:21.351353 ARM64: Done test exception
341 12:20:21.358359 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:20:21.368222 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:20:21.375103 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:20:21.385034 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:20:21.391475 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:20:21.401937 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:20:21.412650 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:20:21.419236 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:20:21.436871 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:20:21.440054 WDT: Last reset was cold boot
351 12:20:21.443940 SPI1(PAD0) initialized at 2873684 Hz
352 12:20:21.446895 SPI5(PAD0) initialized at 992727 Hz
353 12:20:21.450157 VBOOT: Loading verstage.
354 12:20:21.457309 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:20:21.461137 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:20:21.464187 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:20:21.467947 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:20:21.474887 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:20:21.481135 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:20:21.492489 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 12:20:21.492573
362 12:20:21.492657
363 12:20:21.502716 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:20:21.506394 ARM64: Exception handlers installed.
365 12:20:21.506475 ARM64: Testing exception
366 12:20:21.509347 ARM64: Done test exception
367 12:20:21.513423 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:20:21.519600 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:20:21.532567 Probing TPM: . done!
370 12:20:21.532650 TPM ready after 0 ms
371 12:20:21.540135 Connected to device vid:did:rid of 1ae0:0028:00
372 12:20:21.546756 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 12:20:21.605832 Initialized TPM device CR50 revision 0
374 12:20:21.617648 tlcl_send_startup: Startup return code is 0
375 12:20:21.617737 TPM: setup succeeded
376 12:20:21.629254 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:20:21.638221 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:20:21.650002 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:20:21.660347 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:20:21.664279 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:20:21.667731 in-header: 03 07 00 00 08 00 00 00
382 12:20:21.671737 in-data: aa e4 47 04 13 02 00 00
383 12:20:21.671821 Chrome EC: UHEPI supported
384 12:20:21.678256 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:20:21.682064 in-header: 03 95 00 00 08 00 00 00
386 12:20:21.686195 in-data: 18 20 20 08 00 00 00 00
387 12:20:21.686279 Phase 1
388 12:20:21.690042 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:20:21.697536 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:20:21.705241 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:20:21.705329 Recovery requested (1009000e)
392 12:20:21.714638 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:20:21.720060 tlcl_extend: response is 0
394 12:20:21.729996 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:20:21.735653 tlcl_extend: response is 0
396 12:20:21.741442 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:20:21.762219 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 12:20:21.768692 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:20:21.768779
400 12:20:21.768844
401 12:20:21.778973 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:20:21.782258 ARM64: Exception handlers installed.
403 12:20:21.785448 ARM64: Testing exception
404 12:20:21.785531 ARM64: Done test exception
405 12:20:21.807871 pmic_efuse_setting: Set efuses in 11 msecs
406 12:20:21.811230 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:20:21.817640 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:20:21.821277 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:20:21.828409 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:20:21.832028 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:20:21.835845 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:20:21.842944 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:20:21.846595 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:20:21.850529 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:20:21.853688 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:20:21.861441 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:20:21.865398 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:20:21.869051 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:20:21.872238 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:20:21.880093 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:20:21.884149 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:20:21.891841 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:20:21.898878 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:20:21.902780 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:20:21.910400 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:20:21.914000 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:20:21.917807 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:20:21.924716 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:20:21.932535 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:20:21.936808 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:20:21.939942 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:20:21.947201 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:20:21.951295 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:20:21.958460 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:20:21.961903 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:20:21.965920 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:20:21.972985 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:20:21.976676 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:20:21.980454 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:20:21.987832 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:20:21.991373 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:20:21.995011 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:20:22.002348 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:20:22.006645 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:20:22.009799 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:20:22.017362 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:20:22.020971 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:20:22.024813 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:20:22.028608 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:20:22.032181 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:20:22.036044 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:20:22.043324 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:20:22.047300 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:20:22.050507 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:20:22.054825 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:20:22.058692 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:20:22.061934 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:20:22.069320 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:20:22.080828 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:20:22.084759 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:20:22.092145 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:20:22.099309 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:20:22.106794 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:20:22.110417 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:20:22.113707 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:20:22.121188 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 12:20:22.124537 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:20:22.129679 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 12:20:22.136707 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:20:22.145298 [RTC]rtc_get_frequency_meter,154: input=15, output=758
471 12:20:22.154285 [RTC]rtc_get_frequency_meter,154: input=23, output=943
472 12:20:22.163767 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 12:20:22.173490 [RTC]rtc_get_frequency_meter,154: input=17, output=806
474 12:20:22.183272 [RTC]rtc_get_frequency_meter,154: input=16, output=781
475 12:20:22.192526 [RTC]rtc_get_frequency_meter,154: input=16, output=780
476 12:20:22.202656 [RTC]rtc_get_frequency_meter,154: input=17, output=804
477 12:20:22.206259 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 12:20:22.210660 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde71
479 12:20:22.213964 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:20:22.221258 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:20:22.225285 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:20:22.228594 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:20:22.232602 ADC[4]: Raw value=906203 ID=7
484 12:20:22.232702 ADC[3]: Raw value=213441 ID=1
485 12:20:22.236188 RAM Code: 0x71
486 12:20:22.240218 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:20:22.243404 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:20:22.255118 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 12:20:22.258843 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 12:20:22.261918 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:20:22.266436 in-header: 03 07 00 00 08 00 00 00
492 12:20:22.270801 in-data: aa e4 47 04 13 02 00 00
493 12:20:22.274304 Chrome EC: UHEPI supported
494 12:20:22.281508 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:20:22.284678 in-header: 03 95 00 00 08 00 00 00
496 12:20:22.288155 in-data: 18 20 20 08 00 00 00 00
497 12:20:22.292087 MRC: failed to locate region type 0.
498 12:20:22.296071 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:20:22.299382 DRAM-K: Running full calibration
500 12:20:22.306967 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 12:20:22.307070 header.status = 0x0
502 12:20:22.311120 header.version = 0x6 (expected: 0x6)
503 12:20:22.314779 header.size = 0xd00 (expected: 0xd00)
504 12:20:22.317932 header.flags = 0x0
505 12:20:22.321662 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:20:22.340211 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 12:20:22.348345 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:20:22.352235 dram_init: ddr_geometry: 2
509 12:20:22.352414 [EMI] MDL number = 2
510 12:20:22.355895 [EMI] Get MDL freq = 0
511 12:20:22.356005 dram_init: ddr_type: 0
512 12:20:22.359195 is_discrete_lpddr4: 1
513 12:20:22.362908 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:20:22.362999
515 12:20:22.363084
516 12:20:22.363164 [Bian_co] ETT version 0.0.0.1
517 12:20:22.370478 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 12:20:22.370587
519 12:20:22.374345 dramc_set_vcore_voltage set vcore to 650000
520 12:20:22.374436 Read voltage for 800, 4
521 12:20:22.378099 Vio18 = 0
522 12:20:22.378188 Vcore = 650000
523 12:20:22.378304 Vdram = 0
524 12:20:22.378385 Vddq = 0
525 12:20:22.382019 Vmddr = 0
526 12:20:22.382107 dram_init: config_dvfs: 1
527 12:20:22.389420 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:20:22.392754 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:20:22.396675 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 12:20:22.400357 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 12:20:22.403823 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 12:20:22.407916 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 12:20:22.411246 MEM_TYPE=3, freq_sel=18
534 12:20:22.415059 sv_algorithm_assistance_LP4_1600
535 12:20:22.418369 ============ PULL DRAM RESETB DOWN ============
536 12:20:22.421383 ========== PULL DRAM RESETB DOWN end =========
537 12:20:22.424492 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:20:22.427952 ===================================
539 12:20:22.431732 LPDDR4 DRAM CONFIGURATION
540 12:20:22.435412 ===================================
541 12:20:22.439406 EX_ROW_EN[0] = 0x0
542 12:20:22.439536 EX_ROW_EN[1] = 0x0
543 12:20:22.443028 LP4Y_EN = 0x0
544 12:20:22.443151 WORK_FSP = 0x0
545 12:20:22.443246 WL = 0x2
546 12:20:22.446541 RL = 0x2
547 12:20:22.446675 BL = 0x2
548 12:20:22.450183 RPST = 0x0
549 12:20:22.450316 RD_PRE = 0x0
550 12:20:22.454227 WR_PRE = 0x1
551 12:20:22.454391 WR_PST = 0x0
552 12:20:22.457820 DBI_WR = 0x0
553 12:20:22.457944 DBI_RD = 0x0
554 12:20:22.460583 OTF = 0x1
555 12:20:22.463836 ===================================
556 12:20:22.466922 ===================================
557 12:20:22.467018 ANA top config
558 12:20:22.470673 ===================================
559 12:20:22.473949 DLL_ASYNC_EN = 0
560 12:20:22.477213 ALL_SLAVE_EN = 1
561 12:20:22.480509 NEW_RANK_MODE = 1
562 12:20:22.480604 DLL_IDLE_MODE = 1
563 12:20:22.484192 LP45_APHY_COMB_EN = 1
564 12:20:22.486739 TX_ODT_DIS = 1
565 12:20:22.490587 NEW_8X_MODE = 1
566 12:20:22.494225 ===================================
567 12:20:22.494318 ===================================
568 12:20:22.498101 data_rate = 1600
569 12:20:22.501111 CKR = 1
570 12:20:22.504355 DQ_P2S_RATIO = 8
571 12:20:22.508048 ===================================
572 12:20:22.511484 CA_P2S_RATIO = 8
573 12:20:22.514633 DQ_CA_OPEN = 0
574 12:20:22.514716 DQ_SEMI_OPEN = 0
575 12:20:22.517847 CA_SEMI_OPEN = 0
576 12:20:22.521271 CA_FULL_RATE = 0
577 12:20:22.524885 DQ_CKDIV4_EN = 1
578 12:20:22.527681 CA_CKDIV4_EN = 1
579 12:20:22.527773 CA_PREDIV_EN = 0
580 12:20:22.531412 PH8_DLY = 0
581 12:20:22.534836 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:20:22.537791 DQ_AAMCK_DIV = 4
583 12:20:22.541188 CA_AAMCK_DIV = 4
584 12:20:22.544753 CA_ADMCK_DIV = 4
585 12:20:22.544842 DQ_TRACK_CA_EN = 0
586 12:20:22.548183 CA_PICK = 800
587 12:20:22.551668 CA_MCKIO = 800
588 12:20:22.554796 MCKIO_SEMI = 0
589 12:20:22.558851 PLL_FREQ = 3068
590 12:20:22.562694 DQ_UI_PI_RATIO = 32
591 12:20:22.562823 CA_UI_PI_RATIO = 0
592 12:20:22.565781 ===================================
593 12:20:22.569507 ===================================
594 12:20:22.573565 memory_type:LPDDR4
595 12:20:22.573697 GP_NUM : 10
596 12:20:22.577460 SRAM_EN : 1
597 12:20:22.577613 MD32_EN : 0
598 12:20:22.581964 ===================================
599 12:20:22.585255 [ANA_INIT] >>>>>>>>>>>>>>
600 12:20:22.589207 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:20:22.589331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:20:22.592381 ===================================
603 12:20:22.595567 data_rate = 1600,PCW = 0X7600
604 12:20:22.599198 ===================================
605 12:20:22.602289 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:20:22.609265 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:20:22.615785 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:20:22.619117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:20:22.622739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:20:22.625988 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:20:22.629306 [ANA_INIT] flow start
612 12:20:22.629396 [ANA_INIT] PLL >>>>>>>>
613 12:20:22.632598 [ANA_INIT] PLL <<<<<<<<
614 12:20:22.635680 [ANA_INIT] MIDPI >>>>>>>>
615 12:20:22.635768 [ANA_INIT] MIDPI <<<<<<<<
616 12:20:22.639262 [ANA_INIT] DLL >>>>>>>>
617 12:20:22.642186 [ANA_INIT] flow end
618 12:20:22.645486 ============ LP4 DIFF to SE enter ============
619 12:20:22.649088 ============ LP4 DIFF to SE exit ============
620 12:20:22.652317 [ANA_INIT] <<<<<<<<<<<<<
621 12:20:22.655978 [Flow] Enable top DCM control >>>>>
622 12:20:22.659602 [Flow] Enable top DCM control <<<<<
623 12:20:22.662329 Enable DLL master slave shuffle
624 12:20:22.665686 ==============================================================
625 12:20:22.669453 Gating Mode config
626 12:20:22.672474 ==============================================================
627 12:20:22.675968 Config description:
628 12:20:22.686597 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:20:22.692667 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:20:22.695941 SELPH_MODE 0: By rank 1: By Phase
631 12:20:22.702751 ==============================================================
632 12:20:22.706483 GAT_TRACK_EN = 1
633 12:20:22.709547 RX_GATING_MODE = 2
634 12:20:22.712813 RX_GATING_TRACK_MODE = 2
635 12:20:22.715938 SELPH_MODE = 1
636 12:20:22.716014 PICG_EARLY_EN = 1
637 12:20:22.719998 VALID_LAT_VALUE = 1
638 12:20:22.726406 ==============================================================
639 12:20:22.729588 Enter into Gating configuration >>>>
640 12:20:22.733043 Exit from Gating configuration <<<<
641 12:20:22.736084 Enter into DVFS_PRE_config >>>>>
642 12:20:22.745903 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:20:22.749364 Exit from DVFS_PRE_config <<<<<
644 12:20:22.753078 Enter into PICG configuration >>>>
645 12:20:22.755902 Exit from PICG configuration <<<<
646 12:20:22.759281 [RX_INPUT] configuration >>>>>
647 12:20:22.763116 [RX_INPUT] configuration <<<<<
648 12:20:22.766334 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:20:22.773165 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:20:22.779500 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:20:22.785962 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:20:22.789499 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:20:22.796697 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:20:22.799544 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:20:22.806063 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:20:22.809226 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:20:22.813069 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:20:22.816237 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:20:22.822853 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:20:22.826244 ===================================
661 12:20:22.830008 LPDDR4 DRAM CONFIGURATION
662 12:20:22.830098 ===================================
663 12:20:22.833242 EX_ROW_EN[0] = 0x0
664 12:20:22.836471 EX_ROW_EN[1] = 0x0
665 12:20:22.836557 LP4Y_EN = 0x0
666 12:20:22.839747 WORK_FSP = 0x0
667 12:20:22.839832 WL = 0x2
668 12:20:22.842898 RL = 0x2
669 12:20:22.842987 BL = 0x2
670 12:20:22.846482 RPST = 0x0
671 12:20:22.846568 RD_PRE = 0x0
672 12:20:22.849493 WR_PRE = 0x1
673 12:20:22.849577 WR_PST = 0x0
674 12:20:22.853011 DBI_WR = 0x0
675 12:20:22.853097 DBI_RD = 0x0
676 12:20:22.856279 OTF = 0x1
677 12:20:22.859907 ===================================
678 12:20:22.862922 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:20:22.866151 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:20:22.872934 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:20:22.876706 ===================================
682 12:20:22.876802 LPDDR4 DRAM CONFIGURATION
683 12:20:22.879558 ===================================
684 12:20:22.883333 EX_ROW_EN[0] = 0x10
685 12:20:22.883421 EX_ROW_EN[1] = 0x0
686 12:20:22.886575 LP4Y_EN = 0x0
687 12:20:22.889689 WORK_FSP = 0x0
688 12:20:22.889775 WL = 0x2
689 12:20:22.892797 RL = 0x2
690 12:20:22.892884 BL = 0x2
691 12:20:22.896423 RPST = 0x0
692 12:20:22.896509 RD_PRE = 0x0
693 12:20:22.900070 WR_PRE = 0x1
694 12:20:22.900157 WR_PST = 0x0
695 12:20:22.903324 DBI_WR = 0x0
696 12:20:22.903409 DBI_RD = 0x0
697 12:20:22.906518 OTF = 0x1
698 12:20:22.909724 ===================================
699 12:20:22.912890 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:20:22.918455 nWR fixed to 40
701 12:20:22.922081 [ModeRegInit_LP4] CH0 RK0
702 12:20:22.922184 [ModeRegInit_LP4] CH0 RK1
703 12:20:22.925088 [ModeRegInit_LP4] CH1 RK0
704 12:20:22.928847 [ModeRegInit_LP4] CH1 RK1
705 12:20:22.928937 match AC timing 13
706 12:20:22.935956 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 12:20:22.939155 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:20:22.942668 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:20:22.948921 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:20:22.951955 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:20:22.952049 [EMI DOE] emi_dcm 0
712 12:20:22.958606 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:20:22.958702 ==
714 12:20:22.962395 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:20:22.965341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 12:20:22.965431 ==
717 12:20:22.971867 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:20:22.978669 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:20:22.986012 [CA 0] Center 36 (6~67) winsize 62
720 12:20:22.989190 [CA 1] Center 36 (6~67) winsize 62
721 12:20:22.992629 [CA 2] Center 34 (4~65) winsize 62
722 12:20:22.996144 [CA 3] Center 34 (4~64) winsize 61
723 12:20:22.999474 [CA 4] Center 33 (2~64) winsize 63
724 12:20:23.002273 [CA 5] Center 32 (2~62) winsize 61
725 12:20:23.002362
726 12:20:23.006595 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 12:20:23.006689
728 12:20:23.009200 [CATrainingPosCal] consider 1 rank data
729 12:20:23.012294 u2DelayCellTimex100 = 270/100 ps
730 12:20:23.015758 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 12:20:23.019406 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 12:20:23.026036 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 12:20:23.029419 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
734 12:20:23.032832 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
735 12:20:23.035898 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 12:20:23.035986
737 12:20:23.039413 CA PerBit enable=1, Macro0, CA PI delay=32
738 12:20:23.039503
739 12:20:23.042900 [CBTSetCACLKResult] CA Dly = 32
740 12:20:23.042988 CS Dly: 4 (0~35)
741 12:20:23.043055 ==
742 12:20:23.046109 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:20:23.052781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 12:20:23.052877 ==
745 12:20:23.056720 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:20:23.062671 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:20:23.072051 [CA 0] Center 36 (6~67) winsize 62
748 12:20:23.076043 [CA 1] Center 36 (6~67) winsize 62
749 12:20:23.078921 [CA 2] Center 34 (4~65) winsize 62
750 12:20:23.082291 [CA 3] Center 34 (4~65) winsize 62
751 12:20:23.085565 [CA 4] Center 32 (2~63) winsize 62
752 12:20:23.089447 [CA 5] Center 32 (2~63) winsize 62
753 12:20:23.089565
754 12:20:23.092662 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 12:20:23.092746
756 12:20:23.095722 [CATrainingPosCal] consider 2 rank data
757 12:20:23.099488 u2DelayCellTimex100 = 270/100 ps
758 12:20:23.102902 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 12:20:23.105886 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 12:20:23.109080 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 12:20:23.115932 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 12:20:23.119406 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
763 12:20:23.122613 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 12:20:23.122713
765 12:20:23.125758 CA PerBit enable=1, Macro0, CA PI delay=32
766 12:20:23.125846
767 12:20:23.129373 [CBTSetCACLKResult] CA Dly = 32
768 12:20:23.129462 CS Dly: 4 (0~36)
769 12:20:23.129528
770 12:20:23.133068 ----->DramcWriteLeveling(PI) begin...
771 12:20:23.133156 ==
772 12:20:23.136380 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:20:23.143441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 12:20:23.143557 ==
775 12:20:23.143624 Write leveling (Byte 0): 35 => 35
776 12:20:23.147069 Write leveling (Byte 1): 31 => 31
777 12:20:23.150807 DramcWriteLeveling(PI) end<-----
778 12:20:23.150901
779 12:20:23.150967 ==
780 12:20:23.154772 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:20:23.157311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 12:20:23.157402 ==
783 12:20:23.160888 [Gating] SW mode calibration
784 12:20:23.167914 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:20:23.174962 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:20:23.177954 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 12:20:23.181567 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 12:20:23.188139 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 12:20:23.192032 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:20:23.195056 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:20:23.202015 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:20:23.205118 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:20:23.208677 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:20:23.214890 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:20:23.218829 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:20:23.221366 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:20:23.225114 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:20:23.232009 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:20:23.235387 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:20:23.238241 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:20:23.245115 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:20:23.248942 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:20:23.252068 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
804 12:20:23.258483 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
805 12:20:23.262206 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 12:20:23.265549 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:20:23.269062 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:20:23.275988 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:20:23.279109 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:20:23.282519 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:20:23.289118 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:20:23.292505 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
813 12:20:23.295691 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
814 12:20:23.302317 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:20:23.306180 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:20:23.309147 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:20:23.315831 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:20:23.319039 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:20:23.322170 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 12:20:23.329271 0 10 8 | B1->B0 | 3232 2727 | 0 0 | (0 0) (0 0)
821 12:20:23.332482 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
822 12:20:23.335652 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:20:23.339473 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:20:23.345963 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:20:23.349081 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:20:23.352539 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:20:23.359369 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
828 12:20:23.362697 0 11 8 | B1->B0 | 2e2e 4242 | 0 0 | (1 1) (0 0)
829 12:20:23.366153 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
830 12:20:23.372561 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:20:23.376463 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:20:23.379535 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:20:23.386195 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:20:23.389202 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:20:23.392797 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:20:23.399795 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
837 12:20:23.403336 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 12:20:23.406562 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:20:23.413055 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:20:23.416252 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:20:23.419986 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:20:23.422905 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:20:23.429679 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:20:23.432860 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:20:23.436598 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:20:23.442951 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:20:23.446277 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:20:23.449287 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:20:23.456573 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:20:23.459668 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:20:23.462916 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 12:20:23.469599 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 12:20:23.469710 Total UI for P1: 0, mck2ui 16
854 12:20:23.476161 best dqsien dly found for B0: ( 0, 14, 4)
855 12:20:23.479441 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 12:20:23.483257 Total UI for P1: 0, mck2ui 16
857 12:20:23.486967 best dqsien dly found for B1: ( 0, 14, 8)
858 12:20:23.490146 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 12:20:23.494078 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 12:20:23.494174
861 12:20:23.497199 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 12:20:23.500336 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 12:20:23.503749 [Gating] SW calibration Done
864 12:20:23.503838 ==
865 12:20:23.507194 Dram Type= 6, Freq= 0, CH_0, rank 0
866 12:20:23.510101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 12:20:23.510190 ==
868 12:20:23.513561 RX Vref Scan: 0
869 12:20:23.513652
870 12:20:23.513718 RX Vref 0 -> 0, step: 1
871 12:20:23.513779
872 12:20:23.516941 RX Delay -130 -> 252, step: 16
873 12:20:23.520201 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 12:20:23.527324 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 12:20:23.530498 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 12:20:23.533670 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 12:20:23.537197 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 12:20:23.540213 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 12:20:23.547230 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 12:20:23.550630 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 12:20:23.553762 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
882 12:20:23.557101 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
883 12:20:23.560696 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 12:20:23.563917 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 12:20:23.570914 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 12:20:23.574154 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
887 12:20:23.577290 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 12:20:23.580766 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 12:20:23.580855 ==
890 12:20:23.583844 Dram Type= 6, Freq= 0, CH_0, rank 0
891 12:20:23.590867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 12:20:23.590973 ==
893 12:20:23.591040 DQS Delay:
894 12:20:23.594229 DQS0 = 0, DQS1 = 0
895 12:20:23.594317 DQM Delay:
896 12:20:23.594383 DQM0 = 89, DQM1 = 83
897 12:20:23.597127 DQ Delay:
898 12:20:23.600801 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 12:20:23.604211 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
900 12:20:23.607391 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
901 12:20:23.610650 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
902 12:20:23.610779
903 12:20:23.610879
904 12:20:23.610976 ==
905 12:20:23.614399 Dram Type= 6, Freq= 0, CH_0, rank 0
906 12:20:23.617745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 12:20:23.617860 ==
908 12:20:23.617959
909 12:20:23.618050
910 12:20:23.621343 TX Vref Scan disable
911 12:20:23.621456 == TX Byte 0 ==
912 12:20:23.627943 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
913 12:20:23.631185 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
914 12:20:23.631303 == TX Byte 1 ==
915 12:20:23.637491 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
916 12:20:23.640989 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
917 12:20:23.641112 ==
918 12:20:23.644517 Dram Type= 6, Freq= 0, CH_0, rank 0
919 12:20:23.647633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 12:20:23.647753 ==
921 12:20:23.661462 TX Vref=22, minBit 8, minWin=27, winSum=446
922 12:20:23.665126 TX Vref=24, minBit 10, minWin=27, winSum=451
923 12:20:23.668143 TX Vref=26, minBit 8, minWin=27, winSum=455
924 12:20:23.671739 TX Vref=28, minBit 8, minWin=28, winSum=458
925 12:20:23.675183 TX Vref=30, minBit 5, minWin=28, winSum=458
926 12:20:23.678522 TX Vref=32, minBit 5, minWin=28, winSum=457
927 12:20:23.684968 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 28
928 12:20:23.685103
929 12:20:23.688200 Final TX Range 1 Vref 28
930 12:20:23.688356
931 12:20:23.688453 ==
932 12:20:23.691816 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:20:23.695378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:20:23.695496 ==
935 12:20:23.695593
936 12:20:23.698174
937 12:20:23.698284 TX Vref Scan disable
938 12:20:23.701619 == TX Byte 0 ==
939 12:20:23.705232 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
940 12:20:23.708570 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
941 12:20:23.711802 == TX Byte 1 ==
942 12:20:23.714838 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 12:20:23.718460 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 12:20:23.721526
945 12:20:23.721650 [DATLAT]
946 12:20:23.721747 Freq=800, CH0 RK0
947 12:20:23.721840
948 12:20:23.725228 DATLAT Default: 0xa
949 12:20:23.725343 0, 0xFFFF, sum = 0
950 12:20:23.728515 1, 0xFFFF, sum = 0
951 12:20:23.728634 2, 0xFFFF, sum = 0
952 12:20:23.732249 3, 0xFFFF, sum = 0
953 12:20:23.732388 4, 0xFFFF, sum = 0
954 12:20:23.735479 5, 0xFFFF, sum = 0
955 12:20:23.735592 6, 0xFFFF, sum = 0
956 12:20:23.739049 7, 0xFFFF, sum = 0
957 12:20:23.739166 8, 0xFFFF, sum = 0
958 12:20:23.742403 9, 0x0, sum = 1
959 12:20:23.742514 10, 0x0, sum = 2
960 12:20:23.745144 11, 0x0, sum = 3
961 12:20:23.745256 12, 0x0, sum = 4
962 12:20:23.748674 best_step = 10
963 12:20:23.748817
964 12:20:23.748946 ==
965 12:20:23.751813 Dram Type= 6, Freq= 0, CH_0, rank 0
966 12:20:23.755667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 12:20:23.755789 ==
968 12:20:23.758757 RX Vref Scan: 1
969 12:20:23.758867
970 12:20:23.758961 Set Vref Range= 32 -> 127
971 12:20:23.759053
972 12:20:23.761702 RX Vref 32 -> 127, step: 1
973 12:20:23.761812
974 12:20:23.765605 RX Delay -79 -> 252, step: 8
975 12:20:23.765719
976 12:20:23.768830 Set Vref, RX VrefLevel [Byte0]: 32
977 12:20:23.772115 [Byte1]: 32
978 12:20:23.772232
979 12:20:23.775531 Set Vref, RX VrefLevel [Byte0]: 33
980 12:20:23.778938 [Byte1]: 33
981 12:20:23.781817
982 12:20:23.781937 Set Vref, RX VrefLevel [Byte0]: 34
983 12:20:23.785590 [Byte1]: 34
984 12:20:23.789308
985 12:20:23.792908 Set Vref, RX VrefLevel [Byte0]: 35
986 12:20:23.793029 [Byte1]: 35
987 12:20:23.797599
988 12:20:23.797717 Set Vref, RX VrefLevel [Byte0]: 36
989 12:20:23.801155 [Byte1]: 36
990 12:20:23.805049
991 12:20:23.805169 Set Vref, RX VrefLevel [Byte0]: 37
992 12:20:23.808031 [Byte1]: 37
993 12:20:23.812372
994 12:20:23.812505 Set Vref, RX VrefLevel [Byte0]: 38
995 12:20:23.816057 [Byte1]: 38
996 12:20:23.820396
997 12:20:23.820523 Set Vref, RX VrefLevel [Byte0]: 39
998 12:20:23.823515 [Byte1]: 39
999 12:20:23.827949
1000 12:20:23.828081 Set Vref, RX VrefLevel [Byte0]: 40
1001 12:20:23.831027 [Byte1]: 40
1002 12:20:23.835026
1003 12:20:23.835148 Set Vref, RX VrefLevel [Byte0]: 41
1004 12:20:23.838365 [Byte1]: 41
1005 12:20:23.842723
1006 12:20:23.842843 Set Vref, RX VrefLevel [Byte0]: 42
1007 12:20:23.845296 [Byte1]: 42
1008 12:20:23.849772
1009 12:20:23.849890 Set Vref, RX VrefLevel [Byte0]: 43
1010 12:20:23.852838 [Byte1]: 43
1011 12:20:23.857505
1012 12:20:23.857638 Set Vref, RX VrefLevel [Byte0]: 44
1013 12:20:23.861030 [Byte1]: 44
1014 12:20:23.864848
1015 12:20:23.864968 Set Vref, RX VrefLevel [Byte0]: 45
1016 12:20:23.868000 [Byte1]: 45
1017 12:20:23.872691
1018 12:20:23.872815 Set Vref, RX VrefLevel [Byte0]: 46
1019 12:20:23.875585 [Byte1]: 46
1020 12:20:23.880085
1021 12:20:23.880203 Set Vref, RX VrefLevel [Byte0]: 47
1022 12:20:23.883455 [Byte1]: 47
1023 12:20:23.887532
1024 12:20:23.887647 Set Vref, RX VrefLevel [Byte0]: 48
1025 12:20:23.890790 [Byte1]: 48
1026 12:20:23.895361
1027 12:20:23.895482 Set Vref, RX VrefLevel [Byte0]: 49
1028 12:20:23.898344 [Byte1]: 49
1029 12:20:23.902774
1030 12:20:23.902897 Set Vref, RX VrefLevel [Byte0]: 50
1031 12:20:23.906233 [Byte1]: 50
1032 12:20:23.910374
1033 12:20:23.910492 Set Vref, RX VrefLevel [Byte0]: 51
1034 12:20:23.913570 [Byte1]: 51
1035 12:20:23.917759
1036 12:20:23.917877 Set Vref, RX VrefLevel [Byte0]: 52
1037 12:20:23.920987 [Byte1]: 52
1038 12:20:23.925425
1039 12:20:23.925547 Set Vref, RX VrefLevel [Byte0]: 53
1040 12:20:23.928926 [Byte1]: 53
1041 12:20:23.932853
1042 12:20:23.932968 Set Vref, RX VrefLevel [Byte0]: 54
1043 12:20:23.935951 [Byte1]: 54
1044 12:20:23.940661
1045 12:20:23.940783 Set Vref, RX VrefLevel [Byte0]: 55
1046 12:20:23.944442 [Byte1]: 55
1047 12:20:23.947767
1048 12:20:23.947878 Set Vref, RX VrefLevel [Byte0]: 56
1049 12:20:23.951528 [Byte1]: 56
1050 12:20:23.955169
1051 12:20:23.955283 Set Vref, RX VrefLevel [Byte0]: 57
1052 12:20:23.958601 [Byte1]: 57
1053 12:20:23.963398
1054 12:20:23.963516 Set Vref, RX VrefLevel [Byte0]: 58
1055 12:20:23.966354 [Byte1]: 58
1056 12:20:23.970433
1057 12:20:23.970549 Set Vref, RX VrefLevel [Byte0]: 59
1058 12:20:23.974317 [Byte1]: 59
1059 12:20:23.978271
1060 12:20:23.978387 Set Vref, RX VrefLevel [Byte0]: 60
1061 12:20:23.981332 [Byte1]: 60
1062 12:20:23.985762
1063 12:20:23.985875 Set Vref, RX VrefLevel [Byte0]: 61
1064 12:20:23.988979 [Byte1]: 61
1065 12:20:23.993609
1066 12:20:23.993725 Set Vref, RX VrefLevel [Byte0]: 62
1067 12:20:23.996536 [Byte1]: 62
1068 12:20:24.001072
1069 12:20:24.001184 Set Vref, RX VrefLevel [Byte0]: 63
1070 12:20:24.004076 [Byte1]: 63
1071 12:20:24.008184
1072 12:20:24.008270 Set Vref, RX VrefLevel [Byte0]: 64
1073 12:20:24.011829 [Byte1]: 64
1074 12:20:24.016132
1075 12:20:24.016226 Set Vref, RX VrefLevel [Byte0]: 65
1076 12:20:24.019145 [Byte1]: 65
1077 12:20:24.023548
1078 12:20:24.023640 Set Vref, RX VrefLevel [Byte0]: 66
1079 12:20:24.026604 [Byte1]: 66
1080 12:20:24.030950
1081 12:20:24.031052 Set Vref, RX VrefLevel [Byte0]: 67
1082 12:20:24.034283 [Byte1]: 67
1083 12:20:24.038587
1084 12:20:24.038684 Set Vref, RX VrefLevel [Byte0]: 68
1085 12:20:24.041651 [Byte1]: 68
1086 12:20:24.046419
1087 12:20:24.046546 Set Vref, RX VrefLevel [Byte0]: 69
1088 12:20:24.049640 [Byte1]: 69
1089 12:20:24.053603
1090 12:20:24.053781 Set Vref, RX VrefLevel [Byte0]: 70
1091 12:20:24.057076 [Byte1]: 70
1092 12:20:24.061586
1093 12:20:24.061679 Set Vref, RX VrefLevel [Byte0]: 71
1094 12:20:24.064611 [Byte1]: 71
1095 12:20:24.068531
1096 12:20:24.068617 Set Vref, RX VrefLevel [Byte0]: 72
1097 12:20:24.072263 [Byte1]: 72
1098 12:20:24.076528
1099 12:20:24.076616 Set Vref, RX VrefLevel [Byte0]: 73
1100 12:20:24.079735 [Byte1]: 73
1101 12:20:24.084251
1102 12:20:24.084363 Set Vref, RX VrefLevel [Byte0]: 74
1103 12:20:24.087420 [Byte1]: 74
1104 12:20:24.091285
1105 12:20:24.091372 Set Vref, RX VrefLevel [Byte0]: 75
1106 12:20:24.095155 [Byte1]: 75
1107 12:20:24.099318
1108 12:20:24.099407 Set Vref, RX VrefLevel [Byte0]: 76
1109 12:20:24.102607 [Byte1]: 76
1110 12:20:24.106496
1111 12:20:24.106592 Set Vref, RX VrefLevel [Byte0]: 77
1112 12:20:24.109916 [Byte1]: 77
1113 12:20:24.113733
1114 12:20:24.113864 Set Vref, RX VrefLevel [Byte0]: 78
1115 12:20:24.117577 [Byte1]: 78
1116 12:20:24.121883
1117 12:20:24.121977 Final RX Vref Byte 0 = 58 to rank0
1118 12:20:24.125164 Final RX Vref Byte 1 = 61 to rank0
1119 12:20:24.128406 Final RX Vref Byte 0 = 58 to rank1
1120 12:20:24.132020 Final RX Vref Byte 1 = 61 to rank1==
1121 12:20:24.135129 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 12:20:24.138470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 12:20:24.141618 ==
1124 12:20:24.141727 DQS Delay:
1125 12:20:24.141794 DQS0 = 0, DQS1 = 0
1126 12:20:24.145000 DQM Delay:
1127 12:20:24.145084 DQM0 = 91, DQM1 = 85
1128 12:20:24.148342 DQ Delay:
1129 12:20:24.148427 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1130 12:20:24.151694 DQ4 =92, DQ5 =80, DQ6 =96, DQ7 =100
1131 12:20:24.155065 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1132 12:20:24.158523 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1133 12:20:24.158612
1134 12:20:24.161778
1135 12:20:24.168699 [DQSOSCAuto] RK0, (LSB)MR18= 0x473d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
1136 12:20:24.172179 CH0 RK0: MR19=606, MR18=473D
1137 12:20:24.178802 CH0_RK0: MR19=0x606, MR18=0x473D, DQSOSC=392, MR23=63, INC=96, DEC=64
1138 12:20:24.178915
1139 12:20:24.181715 ----->DramcWriteLeveling(PI) begin...
1140 12:20:24.181804 ==
1141 12:20:24.185371 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 12:20:24.188305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 12:20:24.188441 ==
1144 12:20:24.191635 Write leveling (Byte 0): 33 => 33
1145 12:20:24.195732 Write leveling (Byte 1): 30 => 30
1146 12:20:24.198323 DramcWriteLeveling(PI) end<-----
1147 12:20:24.198435
1148 12:20:24.198527 ==
1149 12:20:24.202185 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 12:20:24.205143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 12:20:24.205254 ==
1152 12:20:24.208353 [Gating] SW mode calibration
1153 12:20:24.252616 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 12:20:24.253022 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 12:20:24.253148 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 12:20:24.253259 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 12:20:24.253557 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1158 12:20:24.253856 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:20:24.253957 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:20:24.254508 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:20:24.254804 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:20:24.264545 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:20:24.264904 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:20:24.265014 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:20:24.268386 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:20:24.274312 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:20:24.277804 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:20:24.281189 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:20:24.287884 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:20:24.291194 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:20:24.294496 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:20:24.300999 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:20:24.304252 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1174 12:20:24.308106 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:20:24.314664 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:20:24.317651 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:20:24.321324 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:20:24.324481 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:20:24.331154 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:20:24.334998 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:20:24.338145 0 9 8 | B1->B0 | 2c2c 2727 | 1 1 | (1 1) (0 0)
1182 12:20:24.344865 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 12:20:24.348161 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:20:24.351296 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:20:24.358554 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 12:20:24.361121 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 12:20:24.365178 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 12:20:24.371509 0 10 4 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
1189 12:20:24.374908 0 10 8 | B1->B0 | 2525 2c2c | 0 0 | (1 0) (1 0)
1190 12:20:24.378715 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:20:24.382626 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:20:24.386070 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:20:24.393950 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:20:24.397262 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 12:20:24.400648 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 12:20:24.403803 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1197 12:20:24.411181 0 11 8 | B1->B0 | 3c3c 3939 | 0 0 | (0 0) (0 0)
1198 12:20:24.414433 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 12:20:24.418206 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:20:24.421037 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 12:20:24.427667 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 12:20:24.431403 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 12:20:24.434758 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 12:20:24.441309 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 12:20:24.444771 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1206 12:20:24.447952 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:20:24.454660 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:20:24.457709 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:20:24.461392 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:20:24.467858 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:20:24.471035 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:20:24.474939 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:20:24.481060 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:20:24.484591 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:20:24.487635 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:20:24.494532 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:20:24.497849 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:20:24.501185 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:20:24.508146 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 12:20:24.511391 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 12:20:24.514571 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1222 12:20:24.520966 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 12:20:24.521103 Total UI for P1: 0, mck2ui 16
1224 12:20:24.524870 best dqsien dly found for B0: ( 0, 14, 8)
1225 12:20:24.527963 Total UI for P1: 0, mck2ui 16
1226 12:20:24.531189 best dqsien dly found for B1: ( 0, 14, 8)
1227 12:20:24.534296 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1228 12:20:24.537605 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1229 12:20:24.541440
1230 12:20:24.544714 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 12:20:24.547745 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 12:20:24.551323 [Gating] SW calibration Done
1233 12:20:24.551452 ==
1234 12:20:24.554854 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 12:20:24.557925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 12:20:24.558036 ==
1237 12:20:24.558129 RX Vref Scan: 0
1238 12:20:24.558218
1239 12:20:24.561509 RX Vref 0 -> 0, step: 1
1240 12:20:24.561618
1241 12:20:24.564312 RX Delay -130 -> 252, step: 16
1242 12:20:24.567724 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1243 12:20:24.571792 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1244 12:20:24.578068 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1245 12:20:24.581040 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1246 12:20:24.584459 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1247 12:20:24.587938 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1248 12:20:24.591005 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1249 12:20:24.597653 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1250 12:20:24.601045 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1251 12:20:24.604556 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1252 12:20:24.607859 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1253 12:20:24.611616 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1254 12:20:24.617994 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1255 12:20:24.621222 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1256 12:20:24.624546 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1257 12:20:24.628294 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1258 12:20:24.628447 ==
1259 12:20:24.631568 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 12:20:24.634757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 12:20:24.637945 ==
1262 12:20:24.638055 DQS Delay:
1263 12:20:24.638148 DQS0 = 0, DQS1 = 0
1264 12:20:24.641012 DQM Delay:
1265 12:20:24.641119 DQM0 = 91, DQM1 = 83
1266 12:20:24.644905 DQ Delay:
1267 12:20:24.645016 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1268 12:20:24.648487 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1269 12:20:24.651589 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1270 12:20:24.654923 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =93
1271 12:20:24.655044
1272 12:20:24.658020
1273 12:20:24.658127 ==
1274 12:20:24.661451 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 12:20:24.664494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 12:20:24.664604 ==
1277 12:20:24.664697
1278 12:20:24.664787
1279 12:20:24.668090 TX Vref Scan disable
1280 12:20:24.668196 == TX Byte 0 ==
1281 12:20:24.675126 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1282 12:20:24.678174 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1283 12:20:24.678284 == TX Byte 1 ==
1284 12:20:24.684925 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1285 12:20:24.688111 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1286 12:20:24.688224 ==
1287 12:20:24.691617 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 12:20:24.694641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 12:20:24.694753 ==
1290 12:20:24.709002 TX Vref=22, minBit 10, minWin=27, winSum=446
1291 12:20:24.711744 TX Vref=24, minBit 11, minWin=27, winSum=457
1292 12:20:24.714866 TX Vref=26, minBit 4, minWin=28, winSum=454
1293 12:20:24.718731 TX Vref=28, minBit 5, minWin=28, winSum=458
1294 12:20:24.721639 TX Vref=30, minBit 1, minWin=28, winSum=457
1295 12:20:24.728364 TX Vref=32, minBit 4, minWin=28, winSum=454
1296 12:20:24.732133 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 28
1297 12:20:24.732254
1298 12:20:24.735271 Final TX Range 1 Vref 28
1299 12:20:24.735379
1300 12:20:24.735471 ==
1301 12:20:24.738442 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 12:20:24.741684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 12:20:24.741796 ==
1304 12:20:24.741888
1305 12:20:24.745489
1306 12:20:24.745600 TX Vref Scan disable
1307 12:20:24.748668 == TX Byte 0 ==
1308 12:20:24.751786 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1309 12:20:24.755415 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1310 12:20:24.758585 == TX Byte 1 ==
1311 12:20:24.762431 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1312 12:20:24.765566 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1313 12:20:24.765677
1314 12:20:24.768888 [DATLAT]
1315 12:20:24.768995 Freq=800, CH0 RK1
1316 12:20:24.769090
1317 12:20:24.771976 DATLAT Default: 0xa
1318 12:20:24.772080 0, 0xFFFF, sum = 0
1319 12:20:24.775706 1, 0xFFFF, sum = 0
1320 12:20:24.775817 2, 0xFFFF, sum = 0
1321 12:20:24.779004 3, 0xFFFF, sum = 0
1322 12:20:24.779113 4, 0xFFFF, sum = 0
1323 12:20:24.782287 5, 0xFFFF, sum = 0
1324 12:20:24.782396 6, 0xFFFF, sum = 0
1325 12:20:24.785510 7, 0xFFFF, sum = 0
1326 12:20:24.785618 8, 0xFFFF, sum = 0
1327 12:20:24.788653 9, 0x0, sum = 1
1328 12:20:24.788759 10, 0x0, sum = 2
1329 12:20:24.791884 11, 0x0, sum = 3
1330 12:20:24.791992 12, 0x0, sum = 4
1331 12:20:24.795458 best_step = 10
1332 12:20:24.795568
1333 12:20:24.795660 ==
1334 12:20:24.798663 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 12:20:24.801865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 12:20:24.801978 ==
1337 12:20:24.805543 RX Vref Scan: 0
1338 12:20:24.805652
1339 12:20:24.805744 RX Vref 0 -> 0, step: 1
1340 12:20:24.805835
1341 12:20:24.808682 RX Delay -79 -> 252, step: 8
1342 12:20:24.815376 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1343 12:20:24.818973 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1344 12:20:24.822396 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1345 12:20:24.825247 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1346 12:20:24.828926 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1347 12:20:24.835730 iDelay=209, Bit 5, Center 84 (-31 ~ 200) 232
1348 12:20:24.838773 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1349 12:20:24.841960 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1350 12:20:24.845793 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1351 12:20:24.848723 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1352 12:20:24.852871 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1353 12:20:24.859138 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1354 12:20:24.862330 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1355 12:20:24.865903 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1356 12:20:24.868858 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1357 12:20:24.875975 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1358 12:20:24.876111 ==
1359 12:20:24.879134 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 12:20:24.882235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 12:20:24.882348 ==
1362 12:20:24.882442 DQS Delay:
1363 12:20:24.885531 DQS0 = 0, DQS1 = 0
1364 12:20:24.885638 DQM Delay:
1365 12:20:24.888753 DQM0 = 93, DQM1 = 83
1366 12:20:24.888860 DQ Delay:
1367 12:20:24.892595 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =88
1368 12:20:24.895869 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1369 12:20:24.898925 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1370 12:20:24.902052 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1371 12:20:24.902162
1372 12:20:24.902262
1373 12:20:24.909144 [DQSOSCAuto] RK1, (LSB)MR18= 0x4113, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1374 12:20:24.912176 CH0 RK1: MR19=606, MR18=4113
1375 12:20:24.918854 CH0_RK1: MR19=0x606, MR18=0x4113, DQSOSC=393, MR23=63, INC=95, DEC=63
1376 12:20:24.922255 [RxdqsGatingPostProcess] freq 800
1377 12:20:24.925879 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 12:20:24.929157 Pre-setting of DQS Precalculation
1379 12:20:24.935662 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 12:20:24.935769 ==
1381 12:20:24.939027 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 12:20:24.942687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 12:20:24.942778 ==
1384 12:20:24.949557 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 12:20:24.955489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 12:20:24.964020 [CA 0] Center 36 (6~67) winsize 62
1387 12:20:24.966943 [CA 1] Center 36 (6~67) winsize 62
1388 12:20:24.970275 [CA 2] Center 34 (4~65) winsize 62
1389 12:20:24.973586 [CA 3] Center 34 (4~65) winsize 62
1390 12:20:24.976877 [CA 4] Center 35 (5~65) winsize 61
1391 12:20:24.979984 [CA 5] Center 34 (4~64) winsize 61
1392 12:20:24.980073
1393 12:20:24.983431 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1394 12:20:24.983515
1395 12:20:24.986864 [CATrainingPosCal] consider 1 rank data
1396 12:20:24.990080 u2DelayCellTimex100 = 270/100 ps
1397 12:20:24.993356 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 12:20:24.996598 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 12:20:25.003424 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 12:20:25.006684 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 12:20:25.010032 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1402 12:20:25.013841 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1403 12:20:25.013963
1404 12:20:25.017020 CA PerBit enable=1, Macro0, CA PI delay=34
1405 12:20:25.017130
1406 12:20:25.020641 [CBTSetCACLKResult] CA Dly = 34
1407 12:20:25.020753 CS Dly: 6 (0~37)
1408 12:20:25.020845 ==
1409 12:20:25.023716 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 12:20:25.030192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 12:20:25.030297 ==
1412 12:20:25.034008 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 12:20:25.040180 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 12:20:25.050315 [CA 0] Center 36 (6~67) winsize 62
1415 12:20:25.053808 [CA 1] Center 37 (6~68) winsize 63
1416 12:20:25.058080 [CA 2] Center 35 (4~66) winsize 63
1417 12:20:25.061596 [CA 3] Center 34 (4~65) winsize 62
1418 12:20:25.065381 [CA 4] Center 35 (5~66) winsize 62
1419 12:20:25.065512 [CA 5] Center 34 (4~65) winsize 62
1420 12:20:25.065626
1421 12:20:25.069118 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1422 12:20:25.072270
1423 12:20:25.076212 [CATrainingPosCal] consider 2 rank data
1424 12:20:25.076339 u2DelayCellTimex100 = 270/100 ps
1425 12:20:25.079871 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 12:20:25.082881 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 12:20:25.089331 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 12:20:25.092799 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 12:20:25.096478 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1430 12:20:25.099884 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1431 12:20:25.099975
1432 12:20:25.103331 CA PerBit enable=1, Macro0, CA PI delay=34
1433 12:20:25.103416
1434 12:20:25.106569 [CBTSetCACLKResult] CA Dly = 34
1435 12:20:25.106655 CS Dly: 6 (0~38)
1436 12:20:25.106720
1437 12:20:25.109707 ----->DramcWriteLeveling(PI) begin...
1438 12:20:25.113494 ==
1439 12:20:25.113657 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 12:20:25.120071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 12:20:25.120176 ==
1442 12:20:25.123259 Write leveling (Byte 0): 28 => 28
1443 12:20:25.126709 Write leveling (Byte 1): 27 => 27
1444 12:20:25.129631 DramcWriteLeveling(PI) end<-----
1445 12:20:25.129723
1446 12:20:25.129787 ==
1447 12:20:25.133164 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 12:20:25.136670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 12:20:25.136759 ==
1450 12:20:25.139699 [Gating] SW mode calibration
1451 12:20:25.146865 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 12:20:25.149746 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 12:20:25.156855 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1454 12:20:25.159948 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 12:20:25.163145 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1456 12:20:25.169902 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:20:25.173049 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:20:25.176373 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:20:25.183564 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:20:25.186458 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:20:25.190176 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:20:25.196777 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:20:25.200506 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:20:25.203656 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:20:25.206940 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:20:25.213340 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:20:25.217047 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:20:25.220032 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:20:25.226870 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1470 12:20:25.230003 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1471 12:20:25.233761 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:20:25.239957 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:20:25.243260 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:20:25.246889 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:20:25.253675 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:20:25.256850 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:20:25.260015 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:20:25.266950 0 9 4 | B1->B0 | 2323 2727 | 1 1 | (1 1) (1 1)
1479 12:20:25.270572 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1480 12:20:25.273836 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 12:20:25.280210 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:20:25.283446 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 12:20:25.287015 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 12:20:25.290240 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 12:20:25.296856 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 12:20:25.300031 0 10 4 | B1->B0 | 3232 2c2c | 0 0 | (0 1) (0 1)
1487 12:20:25.303608 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
1488 12:20:25.310168 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:20:25.313405 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:20:25.317378 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:20:25.323459 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:20:25.326857 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:20:25.330579 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 12:20:25.336916 0 11 4 | B1->B0 | 2b2b 3737 | 0 0 | (0 0) (0 0)
1495 12:20:25.339870 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
1496 12:20:25.343891 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:20:25.350080 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:20:25.353508 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 12:20:25.356891 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 12:20:25.363619 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 12:20:25.367057 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 12:20:25.370125 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1503 12:20:25.376883 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:20:25.380118 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:20:25.383486 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:20:25.387188 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:20:25.393873 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:20:25.396982 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:20:25.400848 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:20:25.407195 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:20:25.410511 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:20:25.413664 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:20:25.420070 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:20:25.423933 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:20:25.426910 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:20:25.434026 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:20:25.437266 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1518 12:20:25.440217 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1519 12:20:25.444039 Total UI for P1: 0, mck2ui 16
1520 12:20:25.447147 best dqsien dly found for B1: ( 0, 14, 0)
1521 12:20:25.450333 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 12:20:25.453599 Total UI for P1: 0, mck2ui 16
1523 12:20:25.457438 best dqsien dly found for B0: ( 0, 14, 4)
1524 12:20:25.460680 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1525 12:20:25.467060 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1526 12:20:25.467164
1527 12:20:25.470093 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1528 12:20:25.473995 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1529 12:20:25.477367 [Gating] SW calibration Done
1530 12:20:25.477457 ==
1531 12:20:25.480579 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 12:20:25.483683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 12:20:25.483770 ==
1534 12:20:25.483835 RX Vref Scan: 0
1535 12:20:25.483896
1536 12:20:25.487193 RX Vref 0 -> 0, step: 1
1537 12:20:25.487267
1538 12:20:25.490587 RX Delay -130 -> 252, step: 16
1539 12:20:25.493829 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1540 12:20:25.498070 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1541 12:20:25.503851 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1542 12:20:25.507314 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1543 12:20:25.510213 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1544 12:20:25.513938 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1545 12:20:25.516819 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1546 12:20:25.523737 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1547 12:20:25.527572 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1548 12:20:25.530659 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1549 12:20:25.533979 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1550 12:20:25.537356 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1551 12:20:25.544014 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1552 12:20:25.547138 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1553 12:20:25.550857 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1554 12:20:25.554220 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1555 12:20:25.554318 ==
1556 12:20:25.557502 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 12:20:25.561110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 12:20:25.561208 ==
1559 12:20:25.564407 DQS Delay:
1560 12:20:25.564493 DQS0 = 0, DQS1 = 0
1561 12:20:25.567614 DQM Delay:
1562 12:20:25.567698 DQM0 = 92, DQM1 = 87
1563 12:20:25.567763 DQ Delay:
1564 12:20:25.570826 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1565 12:20:25.574026 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1566 12:20:25.577887 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1567 12:20:25.581075 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1568 12:20:25.581163
1569 12:20:25.581229
1570 12:20:25.584280 ==
1571 12:20:25.587472 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 12:20:25.590649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 12:20:25.590738 ==
1574 12:20:25.590802
1575 12:20:25.590861
1576 12:20:25.593793 TX Vref Scan disable
1577 12:20:25.593876 == TX Byte 0 ==
1578 12:20:25.597789 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1579 12:20:25.604104 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1580 12:20:25.604203 == TX Byte 1 ==
1581 12:20:25.607199 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1582 12:20:25.613978 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1583 12:20:25.614083 ==
1584 12:20:25.617307 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 12:20:25.621232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 12:20:25.621326 ==
1587 12:20:25.634400 TX Vref=22, minBit 1, minWin=26, winSum=437
1588 12:20:25.637406 TX Vref=24, minBit 0, minWin=27, winSum=442
1589 12:20:25.640686 TX Vref=26, minBit 1, minWin=27, winSum=448
1590 12:20:25.643933 TX Vref=28, minBit 1, minWin=27, winSum=449
1591 12:20:25.647364 TX Vref=30, minBit 1, minWin=27, winSum=450
1592 12:20:25.650396 TX Vref=32, minBit 1, minWin=27, winSum=447
1593 12:20:25.657426 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 30
1594 12:20:25.657534
1595 12:20:25.660550 Final TX Range 1 Vref 30
1596 12:20:25.660637
1597 12:20:25.660702 ==
1598 12:20:25.664176 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 12:20:25.667377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 12:20:25.667472 ==
1601 12:20:25.667539
1602 12:20:25.670561
1603 12:20:25.670645 TX Vref Scan disable
1604 12:20:25.674231 == TX Byte 0 ==
1605 12:20:25.677141 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1606 12:20:25.680924 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1607 12:20:25.684228 == TX Byte 1 ==
1608 12:20:25.687279 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1609 12:20:25.690599 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1610 12:20:25.690687
1611 12:20:25.694493 [DATLAT]
1612 12:20:25.694579 Freq=800, CH1 RK0
1613 12:20:25.694644
1614 12:20:25.697550 DATLAT Default: 0xa
1615 12:20:25.697633 0, 0xFFFF, sum = 0
1616 12:20:25.700640 1, 0xFFFF, sum = 0
1617 12:20:25.700726 2, 0xFFFF, sum = 0
1618 12:20:25.704530 3, 0xFFFF, sum = 0
1619 12:20:25.704617 4, 0xFFFF, sum = 0
1620 12:20:25.707925 5, 0xFFFF, sum = 0
1621 12:20:25.708011 6, 0xFFFF, sum = 0
1622 12:20:25.710973 7, 0xFFFF, sum = 0
1623 12:20:25.711058 8, 0xFFFF, sum = 0
1624 12:20:25.714123 9, 0x0, sum = 1
1625 12:20:25.714208 10, 0x0, sum = 2
1626 12:20:25.717647 11, 0x0, sum = 3
1627 12:20:25.717736 12, 0x0, sum = 4
1628 12:20:25.721490 best_step = 10
1629 12:20:25.721579
1630 12:20:25.721644 ==
1631 12:20:25.724676 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 12:20:25.727923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 12:20:25.728009 ==
1634 12:20:25.731110 RX Vref Scan: 1
1635 12:20:25.731194
1636 12:20:25.731260 Set Vref Range= 32 -> 127
1637 12:20:25.731320
1638 12:20:25.734731 RX Vref 32 -> 127, step: 1
1639 12:20:25.734815
1640 12:20:25.737693 RX Delay -79 -> 252, step: 8
1641 12:20:25.737775
1642 12:20:25.740938 Set Vref, RX VrefLevel [Byte0]: 32
1643 12:20:25.744595 [Byte1]: 32
1644 12:20:25.744682
1645 12:20:25.747919 Set Vref, RX VrefLevel [Byte0]: 33
1646 12:20:25.751168 [Byte1]: 33
1647 12:20:25.751254
1648 12:20:25.754356 Set Vref, RX VrefLevel [Byte0]: 34
1649 12:20:25.757987 [Byte1]: 34
1650 12:20:25.761851
1651 12:20:25.761939 Set Vref, RX VrefLevel [Byte0]: 35
1652 12:20:25.764851 [Byte1]: 35
1653 12:20:25.769550
1654 12:20:25.769661 Set Vref, RX VrefLevel [Byte0]: 36
1655 12:20:25.772604 [Byte1]: 36
1656 12:20:25.776644
1657 12:20:25.776731 Set Vref, RX VrefLevel [Byte0]: 37
1658 12:20:25.780247 [Byte1]: 37
1659 12:20:25.784546
1660 12:20:25.784638 Set Vref, RX VrefLevel [Byte0]: 38
1661 12:20:25.787615 [Byte1]: 38
1662 12:20:25.791843
1663 12:20:25.791932 Set Vref, RX VrefLevel [Byte0]: 39
1664 12:20:25.795050 [Byte1]: 39
1665 12:20:25.799493
1666 12:20:25.799585 Set Vref, RX VrefLevel [Byte0]: 40
1667 12:20:25.802798 [Byte1]: 40
1668 12:20:25.806983
1669 12:20:25.807071 Set Vref, RX VrefLevel [Byte0]: 41
1670 12:20:25.810160 [Byte1]: 41
1671 12:20:25.814210
1672 12:20:25.814298 Set Vref, RX VrefLevel [Byte0]: 42
1673 12:20:25.818141 [Byte1]: 42
1674 12:20:25.822185
1675 12:20:25.822291 Set Vref, RX VrefLevel [Byte0]: 43
1676 12:20:25.825332 [Byte1]: 43
1677 12:20:25.829702
1678 12:20:25.829820 Set Vref, RX VrefLevel [Byte0]: 44
1679 12:20:25.833590 [Byte1]: 44
1680 12:20:25.837442
1681 12:20:25.837532 Set Vref, RX VrefLevel [Byte0]: 45
1682 12:20:25.840582 [Byte1]: 45
1683 12:20:25.844979
1684 12:20:25.845072 Set Vref, RX VrefLevel [Byte0]: 46
1685 12:20:25.848196 [Byte1]: 46
1686 12:20:25.852021
1687 12:20:25.852109 Set Vref, RX VrefLevel [Byte0]: 47
1688 12:20:25.855677 [Byte1]: 47
1689 12:20:25.859963
1690 12:20:25.860057 Set Vref, RX VrefLevel [Byte0]: 48
1691 12:20:25.862893 [Byte1]: 48
1692 12:20:25.867571
1693 12:20:25.867666 Set Vref, RX VrefLevel [Byte0]: 49
1694 12:20:25.870631 [Byte1]: 49
1695 12:20:25.875050
1696 12:20:25.875149 Set Vref, RX VrefLevel [Byte0]: 50
1697 12:20:25.878536 [Byte1]: 50
1698 12:20:25.882746
1699 12:20:25.882839 Set Vref, RX VrefLevel [Byte0]: 51
1700 12:20:25.885824 [Byte1]: 51
1701 12:20:25.889759
1702 12:20:25.889851 Set Vref, RX VrefLevel [Byte0]: 52
1703 12:20:25.893855 [Byte1]: 52
1704 12:20:25.897494
1705 12:20:25.897584 Set Vref, RX VrefLevel [Byte0]: 53
1706 12:20:25.901420 [Byte1]: 53
1707 12:20:25.904986
1708 12:20:25.905076 Set Vref, RX VrefLevel [Byte0]: 54
1709 12:20:25.908175 [Byte1]: 54
1710 12:20:25.912568
1711 12:20:25.912662 Set Vref, RX VrefLevel [Byte0]: 55
1712 12:20:25.916054 [Byte1]: 55
1713 12:20:25.920323
1714 12:20:25.920431 Set Vref, RX VrefLevel [Byte0]: 56
1715 12:20:25.923660 [Byte1]: 56
1716 12:20:25.927661
1717 12:20:25.927756 Set Vref, RX VrefLevel [Byte0]: 57
1718 12:20:25.931128 [Byte1]: 57
1719 12:20:25.935579
1720 12:20:25.935674 Set Vref, RX VrefLevel [Byte0]: 58
1721 12:20:25.938603 [Byte1]: 58
1722 12:20:25.943090
1723 12:20:25.943186 Set Vref, RX VrefLevel [Byte0]: 59
1724 12:20:25.946017 [Byte1]: 59
1725 12:20:25.950150
1726 12:20:25.950242 Set Vref, RX VrefLevel [Byte0]: 60
1727 12:20:25.953667 [Byte1]: 60
1728 12:20:25.957967
1729 12:20:25.958061 Set Vref, RX VrefLevel [Byte0]: 61
1730 12:20:25.961396 [Byte1]: 61
1731 12:20:25.965504
1732 12:20:25.965597 Set Vref, RX VrefLevel [Byte0]: 62
1733 12:20:25.968797 [Byte1]: 62
1734 12:20:25.973170
1735 12:20:25.973268 Set Vref, RX VrefLevel [Byte0]: 63
1736 12:20:25.976616 [Byte1]: 63
1737 12:20:25.980708
1738 12:20:25.980804 Set Vref, RX VrefLevel [Byte0]: 64
1739 12:20:25.983484 [Byte1]: 64
1740 12:20:25.988252
1741 12:20:25.988411 Set Vref, RX VrefLevel [Byte0]: 65
1742 12:20:25.991615 [Byte1]: 65
1743 12:20:25.995460
1744 12:20:25.995567 Set Vref, RX VrefLevel [Byte0]: 66
1745 12:20:25.998739 [Byte1]: 66
1746 12:20:26.003463
1747 12:20:26.003568 Set Vref, RX VrefLevel [Byte0]: 67
1748 12:20:26.006399 [Byte1]: 67
1749 12:20:26.010969
1750 12:20:26.011058 Set Vref, RX VrefLevel [Byte0]: 68
1751 12:20:26.014411 [Byte1]: 68
1752 12:20:26.018252
1753 12:20:26.018354 Set Vref, RX VrefLevel [Byte0]: 69
1754 12:20:26.021436 [Byte1]: 69
1755 12:20:26.025798
1756 12:20:26.025894 Set Vref, RX VrefLevel [Byte0]: 70
1757 12:20:26.028962 [Byte1]: 70
1758 12:20:26.033217
1759 12:20:26.033317 Set Vref, RX VrefLevel [Byte0]: 71
1760 12:20:26.036706 [Byte1]: 71
1761 12:20:26.040827
1762 12:20:26.040924 Set Vref, RX VrefLevel [Byte0]: 72
1763 12:20:26.044567 [Byte1]: 72
1764 12:20:26.048464
1765 12:20:26.048558 Set Vref, RX VrefLevel [Byte0]: 73
1766 12:20:26.051660 [Byte1]: 73
1767 12:20:26.055874
1768 12:20:26.055968 Final RX Vref Byte 0 = 56 to rank0
1769 12:20:26.059079 Final RX Vref Byte 1 = 56 to rank0
1770 12:20:26.062649 Final RX Vref Byte 0 = 56 to rank1
1771 12:20:26.066068 Final RX Vref Byte 1 = 56 to rank1==
1772 12:20:26.069340 Dram Type= 6, Freq= 0, CH_1, rank 0
1773 12:20:26.075799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1774 12:20:26.075907 ==
1775 12:20:26.075973 DQS Delay:
1776 12:20:26.076033 DQS0 = 0, DQS1 = 0
1777 12:20:26.079170 DQM Delay:
1778 12:20:26.079256 DQM0 = 95, DQM1 = 89
1779 12:20:26.082600 DQ Delay:
1780 12:20:26.085921 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1781 12:20:26.089036 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1782 12:20:26.092585 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1783 12:20:26.096456 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1784 12:20:26.096555
1785 12:20:26.096620
1786 12:20:26.102740 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1787 12:20:26.105785 CH1 RK0: MR19=606, MR18=2D4A
1788 12:20:26.112560 CH1_RK0: MR19=0x606, MR18=0x2D4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1789 12:20:26.112674
1790 12:20:26.116348 ----->DramcWriteLeveling(PI) begin...
1791 12:20:26.116445 ==
1792 12:20:26.119664 Dram Type= 6, Freq= 0, CH_1, rank 1
1793 12:20:26.122796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1794 12:20:26.122884 ==
1795 12:20:26.126100 Write leveling (Byte 0): 25 => 25
1796 12:20:26.129326 Write leveling (Byte 1): 28 => 28
1797 12:20:26.132604 DramcWriteLeveling(PI) end<-----
1798 12:20:26.132696
1799 12:20:26.132760 ==
1800 12:20:26.136434 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 12:20:26.139522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 12:20:26.139612 ==
1803 12:20:26.143108 [Gating] SW mode calibration
1804 12:20:26.149295 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1805 12:20:26.156531 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1806 12:20:26.159444 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1807 12:20:26.163106 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1808 12:20:26.169482 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 12:20:26.172751 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 12:20:26.176657 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 12:20:26.183057 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 12:20:26.186063 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:20:26.189627 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:20:26.192722 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:20:26.199964 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:20:26.202968 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:20:26.206184 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:20:26.213013 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:20:26.216195 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:20:26.219882 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:20:26.226243 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1822 12:20:26.230128 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1823 12:20:26.232941 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1824 12:20:26.239894 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:20:26.243252 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:20:26.246807 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:20:26.253241 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:20:26.256715 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:20:26.259784 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:20:26.263292 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:20:26.270152 0 9 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1832 12:20:26.273246 0 9 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1833 12:20:26.276527 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 12:20:26.283513 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 12:20:26.286657 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 12:20:26.289811 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 12:20:26.296613 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 12:20:26.300321 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1839 12:20:26.303672 0 10 4 | B1->B0 | 2e2e 3030 | 1 1 | (1 0) (1 1)
1840 12:20:26.309797 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1841 12:20:26.313565 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:20:26.317107 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:20:26.323473 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:20:26.326535 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:20:26.330508 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:20:26.336625 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1847 12:20:26.340676 0 11 4 | B1->B0 | 3c3c 2e2e | 0 1 | (1 1) (0 0)
1848 12:20:26.343523 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1849 12:20:26.347106 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 12:20:26.353737 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 12:20:26.356975 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 12:20:26.360422 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 12:20:26.366788 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 12:20:26.370057 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 12:20:26.373875 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 12:20:26.380263 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 12:20:26.383384 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 12:20:26.386702 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 12:20:26.393836 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 12:20:26.397010 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:20:26.400108 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:20:26.406962 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:20:26.410832 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:20:26.414043 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:20:26.417007 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:20:26.424201 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:20:26.427184 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:20:26.430479 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:20:26.437685 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:20:26.440924 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:20:26.444422 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1872 12:20:26.451193 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 12:20:26.451299 Total UI for P1: 0, mck2ui 16
1874 12:20:26.457213 best dqsien dly found for B0: ( 0, 14, 4)
1875 12:20:26.457339 Total UI for P1: 0, mck2ui 16
1876 12:20:26.461177 best dqsien dly found for B1: ( 0, 14, 4)
1877 12:20:26.467507 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1878 12:20:26.470562 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1879 12:20:26.470659
1880 12:20:26.474514 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1881 12:20:26.477291 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1882 12:20:26.480895 [Gating] SW calibration Done
1883 12:20:26.481013 ==
1884 12:20:26.484221 Dram Type= 6, Freq= 0, CH_1, rank 1
1885 12:20:26.487321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1886 12:20:26.487404 ==
1887 12:20:26.487469 RX Vref Scan: 0
1888 12:20:26.491131
1889 12:20:26.491215 RX Vref 0 -> 0, step: 1
1890 12:20:26.491279
1891 12:20:26.494316 RX Delay -130 -> 252, step: 16
1892 12:20:26.497588 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1893 12:20:26.501013 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1894 12:20:26.507938 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1895 12:20:26.511057 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1896 12:20:26.514642 iDelay=222, Bit 4, Center 93 (-2 ~ 189) 192
1897 12:20:26.517796 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1898 12:20:26.520965 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1899 12:20:26.527549 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1900 12:20:26.531395 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1901 12:20:26.534556 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1902 12:20:26.537926 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1903 12:20:26.540946 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1904 12:20:26.547897 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1905 12:20:26.550849 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1906 12:20:26.554214 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1907 12:20:26.557874 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1908 12:20:26.557961 ==
1909 12:20:26.561132 Dram Type= 6, Freq= 0, CH_1, rank 1
1910 12:20:26.564551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1911 12:20:26.567497 ==
1912 12:20:26.567583 DQS Delay:
1913 12:20:26.567649 DQS0 = 0, DQS1 = 0
1914 12:20:26.570922 DQM Delay:
1915 12:20:26.571037 DQM0 = 93, DQM1 = 92
1916 12:20:26.574316 DQ Delay:
1917 12:20:26.577767 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1918 12:20:26.577858 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1919 12:20:26.581194 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1920 12:20:26.588231 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1921 12:20:26.588366
1922 12:20:26.588435
1923 12:20:26.588499 ==
1924 12:20:26.591352 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 12:20:26.594653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 12:20:26.594746 ==
1927 12:20:26.594808
1928 12:20:26.594884
1929 12:20:26.597899 TX Vref Scan disable
1930 12:20:26.597977 == TX Byte 0 ==
1931 12:20:26.604701 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1932 12:20:26.607656 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1933 12:20:26.607818 == TX Byte 1 ==
1934 12:20:26.614482 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1935 12:20:26.617542 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1936 12:20:26.617632 ==
1937 12:20:26.620767 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 12:20:26.624615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 12:20:26.624704 ==
1940 12:20:26.638759 TX Vref=22, minBit 2, minWin=26, winSum=440
1941 12:20:26.641965 TX Vref=24, minBit 5, minWin=26, winSum=445
1942 12:20:26.645190 TX Vref=26, minBit 0, minWin=27, winSum=446
1943 12:20:26.648765 TX Vref=28, minBit 0, minWin=27, winSum=450
1944 12:20:26.651816 TX Vref=30, minBit 0, minWin=27, winSum=449
1945 12:20:26.655380 TX Vref=32, minBit 0, minWin=27, winSum=448
1946 12:20:26.661941 [TxChooseVref] Worse bit 0, Min win 27, Win sum 450, Final Vref 28
1947 12:20:26.662048
1948 12:20:26.665313 Final TX Range 1 Vref 28
1949 12:20:26.665394
1950 12:20:26.665456 ==
1951 12:20:26.668435 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 12:20:26.671680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 12:20:26.671756 ==
1954 12:20:26.671816
1955 12:20:26.671873
1956 12:20:26.674972 TX Vref Scan disable
1957 12:20:26.678639 == TX Byte 0 ==
1958 12:20:26.681724 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1959 12:20:26.685196 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1960 12:20:26.688768 == TX Byte 1 ==
1961 12:20:26.691741 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1962 12:20:26.694810 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1963 12:20:26.698318
1964 12:20:26.698397 [DATLAT]
1965 12:20:26.698462 Freq=800, CH1 RK1
1966 12:20:26.698521
1967 12:20:26.702014 DATLAT Default: 0xa
1968 12:20:26.702081 0, 0xFFFF, sum = 0
1969 12:20:26.705260 1, 0xFFFF, sum = 0
1970 12:20:26.705335 2, 0xFFFF, sum = 0
1971 12:20:26.708656 3, 0xFFFF, sum = 0
1972 12:20:26.708733 4, 0xFFFF, sum = 0
1973 12:20:26.711507 5, 0xFFFF, sum = 0
1974 12:20:26.711577 6, 0xFFFF, sum = 0
1975 12:20:26.715518 7, 0xFFFF, sum = 0
1976 12:20:26.718704 8, 0xFFFF, sum = 0
1977 12:20:26.718786 9, 0x0, sum = 1
1978 12:20:26.718864 10, 0x0, sum = 2
1979 12:20:26.721714 11, 0x0, sum = 3
1980 12:20:26.721789 12, 0x0, sum = 4
1981 12:20:26.725116 best_step = 10
1982 12:20:26.725190
1983 12:20:26.725262 ==
1984 12:20:26.728480 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 12:20:26.731685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 12:20:26.731760 ==
1987 12:20:26.735313 RX Vref Scan: 0
1988 12:20:26.735386
1989 12:20:26.735447 RX Vref 0 -> 0, step: 1
1990 12:20:26.735504
1991 12:20:26.738558 RX Delay -79 -> 252, step: 8
1992 12:20:26.745262 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1993 12:20:26.748514 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1994 12:20:26.751904 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1995 12:20:26.755008 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1996 12:20:26.758757 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1997 12:20:26.761790 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1998 12:20:26.768539 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1999 12:20:26.771958 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2000 12:20:26.775880 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2001 12:20:26.778551 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2002 12:20:26.782345 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2003 12:20:26.788700 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2004 12:20:26.791815 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2005 12:20:26.795321 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2006 12:20:26.798857 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2007 12:20:26.802053 iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216
2008 12:20:26.802138 ==
2009 12:20:26.805373 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 12:20:26.811725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 12:20:26.811817 ==
2012 12:20:26.811883 DQS Delay:
2013 12:20:26.815610 DQS0 = 0, DQS1 = 0
2014 12:20:26.815684 DQM Delay:
2015 12:20:26.815744 DQM0 = 97, DQM1 = 91
2016 12:20:26.818840 DQ Delay:
2017 12:20:26.822033 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2018 12:20:26.825924 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2019 12:20:26.828841 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2020 12:20:26.832199 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
2021 12:20:26.832349
2022 12:20:26.832440
2023 12:20:26.838638 [DQSOSCAuto] RK1, (LSB)MR18= 0x420b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
2024 12:20:26.842424 CH1 RK1: MR19=606, MR18=420B
2025 12:20:26.848923 CH1_RK1: MR19=0x606, MR18=0x420B, DQSOSC=393, MR23=63, INC=95, DEC=63
2026 12:20:26.852098 [RxdqsGatingPostProcess] freq 800
2027 12:20:26.855457 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2028 12:20:26.858753 Pre-setting of DQS Precalculation
2029 12:20:26.865869 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2030 12:20:26.872195 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2031 12:20:26.878853 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2032 12:20:26.878968
2033 12:20:26.879036
2034 12:20:26.881941 [Calibration Summary] 1600 Mbps
2035 12:20:26.882021 CH 0, Rank 0
2036 12:20:26.885851 SW Impedance : PASS
2037 12:20:26.888998 DUTY Scan : NO K
2038 12:20:26.889078 ZQ Calibration : PASS
2039 12:20:26.892346 Jitter Meter : NO K
2040 12:20:26.895570 CBT Training : PASS
2041 12:20:26.895650 Write leveling : PASS
2042 12:20:26.899113 RX DQS gating : PASS
2043 12:20:26.901970 RX DQ/DQS(RDDQC) : PASS
2044 12:20:26.902052 TX DQ/DQS : PASS
2045 12:20:26.905449 RX DATLAT : PASS
2046 12:20:26.908745 RX DQ/DQS(Engine): PASS
2047 12:20:26.908840 TX OE : NO K
2048 12:20:26.908938 All Pass.
2049 12:20:26.912087
2050 12:20:26.912158 CH 0, Rank 1
2051 12:20:26.915288 SW Impedance : PASS
2052 12:20:26.915361 DUTY Scan : NO K
2053 12:20:26.919212 ZQ Calibration : PASS
2054 12:20:26.919295 Jitter Meter : NO K
2055 12:20:26.922531 CBT Training : PASS
2056 12:20:26.925756 Write leveling : PASS
2057 12:20:26.925833 RX DQS gating : PASS
2058 12:20:26.928734 RX DQ/DQS(RDDQC) : PASS
2059 12:20:26.932528 TX DQ/DQS : PASS
2060 12:20:26.932607 RX DATLAT : PASS
2061 12:20:26.935730 RX DQ/DQS(Engine): PASS
2062 12:20:26.938876 TX OE : NO K
2063 12:20:26.938948 All Pass.
2064 12:20:26.939007
2065 12:20:26.939065 CH 1, Rank 0
2066 12:20:26.942078 SW Impedance : PASS
2067 12:20:26.945282 DUTY Scan : NO K
2068 12:20:26.945359 ZQ Calibration : PASS
2069 12:20:26.948490 Jitter Meter : NO K
2070 12:20:26.952388 CBT Training : PASS
2071 12:20:26.952494 Write leveling : PASS
2072 12:20:26.955240 RX DQS gating : PASS
2073 12:20:26.958494 RX DQ/DQS(RDDQC) : PASS
2074 12:20:26.958568 TX DQ/DQS : PASS
2075 12:20:26.962084 RX DATLAT : PASS
2076 12:20:26.965484 RX DQ/DQS(Engine): PASS
2077 12:20:26.965561 TX OE : NO K
2078 12:20:26.965624 All Pass.
2079 12:20:26.965682
2080 12:20:26.968736 CH 1, Rank 1
2081 12:20:26.971923 SW Impedance : PASS
2082 12:20:26.971998 DUTY Scan : NO K
2083 12:20:26.975395 ZQ Calibration : PASS
2084 12:20:26.975470 Jitter Meter : NO K
2085 12:20:26.978402 CBT Training : PASS
2086 12:20:26.982160 Write leveling : PASS
2087 12:20:26.982243 RX DQS gating : PASS
2088 12:20:26.985329 RX DQ/DQS(RDDQC) : PASS
2089 12:20:26.988611 TX DQ/DQS : PASS
2090 12:20:26.988721 RX DATLAT : PASS
2091 12:20:26.991913 RX DQ/DQS(Engine): PASS
2092 12:20:26.995650 TX OE : NO K
2093 12:20:26.995729 All Pass.
2094 12:20:26.995794
2095 12:20:26.995852 DramC Write-DBI off
2096 12:20:26.998978 PER_BANK_REFRESH: Hybrid Mode
2097 12:20:27.002058 TX_TRACKING: ON
2098 12:20:27.005451 [GetDramInforAfterCalByMRR] Vendor 6.
2099 12:20:27.008952 [GetDramInforAfterCalByMRR] Revision 606.
2100 12:20:27.012069 [GetDramInforAfterCalByMRR] Revision 2 0.
2101 12:20:27.012145 MR0 0x3b3b
2102 12:20:27.015265 MR8 0x5151
2103 12:20:27.018747 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 12:20:27.018867
2105 12:20:27.018963 MR0 0x3b3b
2106 12:20:27.019032 MR8 0x5151
2107 12:20:27.022126 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 12:20:27.022230
2109 12:20:27.032260 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2110 12:20:27.035443 [FAST_K] Save calibration result to emmc
2111 12:20:27.039268 [FAST_K] Save calibration result to emmc
2112 12:20:27.042494 dram_init: config_dvfs: 1
2113 12:20:27.045777 dramc_set_vcore_voltage set vcore to 662500
2114 12:20:27.049002 Read voltage for 1200, 2
2115 12:20:27.049083 Vio18 = 0
2116 12:20:27.052432 Vcore = 662500
2117 12:20:27.052523 Vdram = 0
2118 12:20:27.052584 Vddq = 0
2119 12:20:27.052642 Vmddr = 0
2120 12:20:27.059080 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2121 12:20:27.062239 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2122 12:20:27.065892 MEM_TYPE=3, freq_sel=15
2123 12:20:27.069310 sv_algorithm_assistance_LP4_1600
2124 12:20:27.072125 ============ PULL DRAM RESETB DOWN ============
2125 12:20:27.075755 ========== PULL DRAM RESETB DOWN end =========
2126 12:20:27.082438 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2127 12:20:27.085575 ===================================
2128 12:20:27.089138 LPDDR4 DRAM CONFIGURATION
2129 12:20:27.092282 ===================================
2130 12:20:27.092381 EX_ROW_EN[0] = 0x0
2131 12:20:27.095782 EX_ROW_EN[1] = 0x0
2132 12:20:27.095865 LP4Y_EN = 0x0
2133 12:20:27.099452 WORK_FSP = 0x0
2134 12:20:27.099538 WL = 0x4
2135 12:20:27.102607 RL = 0x4
2136 12:20:27.102684 BL = 0x2
2137 12:20:27.105915 RPST = 0x0
2138 12:20:27.105988 RD_PRE = 0x0
2139 12:20:27.109121 WR_PRE = 0x1
2140 12:20:27.109197 WR_PST = 0x0
2141 12:20:27.112345 DBI_WR = 0x0
2142 12:20:27.112428 DBI_RD = 0x0
2143 12:20:27.115686 OTF = 0x1
2144 12:20:27.118923 ===================================
2145 12:20:27.122671 ===================================
2146 12:20:27.122767 ANA top config
2147 12:20:27.125609 ===================================
2148 12:20:27.129426 DLL_ASYNC_EN = 0
2149 12:20:27.132419 ALL_SLAVE_EN = 0
2150 12:20:27.135725 NEW_RANK_MODE = 1
2151 12:20:27.135826 DLL_IDLE_MODE = 1
2152 12:20:27.139298 LP45_APHY_COMB_EN = 1
2153 12:20:27.142191 TX_ODT_DIS = 1
2154 12:20:27.145853 NEW_8X_MODE = 1
2155 12:20:27.149229 ===================================
2156 12:20:27.152137 ===================================
2157 12:20:27.156181 data_rate = 2400
2158 12:20:27.156320 CKR = 1
2159 12:20:27.158856 DQ_P2S_RATIO = 8
2160 12:20:27.162533 ===================================
2161 12:20:27.165659 CA_P2S_RATIO = 8
2162 12:20:27.169242 DQ_CA_OPEN = 0
2163 12:20:27.172489 DQ_SEMI_OPEN = 0
2164 12:20:27.175747 CA_SEMI_OPEN = 0
2165 12:20:27.175827 CA_FULL_RATE = 0
2166 12:20:27.179550 DQ_CKDIV4_EN = 0
2167 12:20:27.182093 CA_CKDIV4_EN = 0
2168 12:20:27.185564 CA_PREDIV_EN = 0
2169 12:20:27.189236 PH8_DLY = 17
2170 12:20:27.192586 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2171 12:20:27.192671 DQ_AAMCK_DIV = 4
2172 12:20:27.195832 CA_AAMCK_DIV = 4
2173 12:20:27.198886 CA_ADMCK_DIV = 4
2174 12:20:27.202782 DQ_TRACK_CA_EN = 0
2175 12:20:27.206112 CA_PICK = 1200
2176 12:20:27.209279 CA_MCKIO = 1200
2177 12:20:27.209364 MCKIO_SEMI = 0
2178 12:20:27.212491 PLL_FREQ = 2366
2179 12:20:27.216137 DQ_UI_PI_RATIO = 32
2180 12:20:27.219270 CA_UI_PI_RATIO = 0
2181 12:20:27.222581 ===================================
2182 12:20:27.225678 ===================================
2183 12:20:27.229372 memory_type:LPDDR4
2184 12:20:27.229484 GP_NUM : 10
2185 12:20:27.232990 SRAM_EN : 1
2186 12:20:27.235917 MD32_EN : 0
2187 12:20:27.239661 ===================================
2188 12:20:27.239768 [ANA_INIT] >>>>>>>>>>>>>>
2189 12:20:27.243090 <<<<<< [CONFIGURE PHASE]: ANA_TX
2190 12:20:27.246072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2191 12:20:27.249321 ===================================
2192 12:20:27.252436 data_rate = 2400,PCW = 0X5b00
2193 12:20:27.256167 ===================================
2194 12:20:27.259197 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2195 12:20:27.266305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2196 12:20:27.269522 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 12:20:27.276213 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2198 12:20:27.279705 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2199 12:20:27.283110 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2200 12:20:27.283221 [ANA_INIT] flow start
2201 12:20:27.285895 [ANA_INIT] PLL >>>>>>>>
2202 12:20:27.289667 [ANA_INIT] PLL <<<<<<<<
2203 12:20:27.289772 [ANA_INIT] MIDPI >>>>>>>>
2204 12:20:27.292880 [ANA_INIT] MIDPI <<<<<<<<
2205 12:20:27.296638 [ANA_INIT] DLL >>>>>>>>
2206 12:20:27.296743 [ANA_INIT] DLL <<<<<<<<
2207 12:20:27.299700 [ANA_INIT] flow end
2208 12:20:27.302985 ============ LP4 DIFF to SE enter ============
2209 12:20:27.306347 ============ LP4 DIFF to SE exit ============
2210 12:20:27.309552 [ANA_INIT] <<<<<<<<<<<<<
2211 12:20:27.312654 [Flow] Enable top DCM control >>>>>
2212 12:20:27.316173 [Flow] Enable top DCM control <<<<<
2213 12:20:27.319533 Enable DLL master slave shuffle
2214 12:20:27.326251 ==============================================================
2215 12:20:27.326369 Gating Mode config
2216 12:20:27.332753 ==============================================================
2217 12:20:27.332858 Config description:
2218 12:20:27.342766 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2219 12:20:27.350192 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2220 12:20:27.356164 SELPH_MODE 0: By rank 1: By Phase
2221 12:20:27.359950 ==============================================================
2222 12:20:27.363245 GAT_TRACK_EN = 1
2223 12:20:27.366402 RX_GATING_MODE = 2
2224 12:20:27.370154 RX_GATING_TRACK_MODE = 2
2225 12:20:27.372952 SELPH_MODE = 1
2226 12:20:27.376617 PICG_EARLY_EN = 1
2227 12:20:27.379782 VALID_LAT_VALUE = 1
2228 12:20:27.383373 ==============================================================
2229 12:20:27.386256 Enter into Gating configuration >>>>
2230 12:20:27.389887 Exit from Gating configuration <<<<
2231 12:20:27.393245 Enter into DVFS_PRE_config >>>>>
2232 12:20:27.406349 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2233 12:20:27.409534 Exit from DVFS_PRE_config <<<<<
2234 12:20:27.409635 Enter into PICG configuration >>>>
2235 12:20:27.413295 Exit from PICG configuration <<<<
2236 12:20:27.416566 [RX_INPUT] configuration >>>>>
2237 12:20:27.419532 [RX_INPUT] configuration <<<<<
2238 12:20:27.426315 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2239 12:20:27.429874 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2240 12:20:27.436673 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2241 12:20:27.443167 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2242 12:20:27.450386 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 12:20:27.456607 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 12:20:27.460494 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2245 12:20:27.463648 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2246 12:20:27.466778 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2247 12:20:27.473140 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2248 12:20:27.476493 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2249 12:20:27.480107 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2250 12:20:27.483467 ===================================
2251 12:20:27.486345 LPDDR4 DRAM CONFIGURATION
2252 12:20:27.490113 ===================================
2253 12:20:27.490201 EX_ROW_EN[0] = 0x0
2254 12:20:27.493351 EX_ROW_EN[1] = 0x0
2255 12:20:27.496465 LP4Y_EN = 0x0
2256 12:20:27.496544 WORK_FSP = 0x0
2257 12:20:27.499969 WL = 0x4
2258 12:20:27.500046 RL = 0x4
2259 12:20:27.503330 BL = 0x2
2260 12:20:27.503406 RPST = 0x0
2261 12:20:27.506696 RD_PRE = 0x0
2262 12:20:27.506771 WR_PRE = 0x1
2263 12:20:27.509726 WR_PST = 0x0
2264 12:20:27.509807 DBI_WR = 0x0
2265 12:20:27.513262 DBI_RD = 0x0
2266 12:20:27.513361 OTF = 0x1
2267 12:20:27.516854 ===================================
2268 12:20:27.520089 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2269 12:20:27.526838 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2270 12:20:27.530043 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2271 12:20:27.533122 ===================================
2272 12:20:27.536749 LPDDR4 DRAM CONFIGURATION
2273 12:20:27.540274 ===================================
2274 12:20:27.540402 EX_ROW_EN[0] = 0x10
2275 12:20:27.543481 EX_ROW_EN[1] = 0x0
2276 12:20:27.543551 LP4Y_EN = 0x0
2277 12:20:27.546565 WORK_FSP = 0x0
2278 12:20:27.546644 WL = 0x4
2279 12:20:27.550354 RL = 0x4
2280 12:20:27.550438 BL = 0x2
2281 12:20:27.553463 RPST = 0x0
2282 12:20:27.553537 RD_PRE = 0x0
2283 12:20:27.556823 WR_PRE = 0x1
2284 12:20:27.556898 WR_PST = 0x0
2285 12:20:27.560208 DBI_WR = 0x0
2286 12:20:27.560346 DBI_RD = 0x0
2287 12:20:27.564150 OTF = 0x1
2288 12:20:27.566650 ===================================
2289 12:20:27.573765 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2290 12:20:27.573877 ==
2291 12:20:27.577151 Dram Type= 6, Freq= 0, CH_0, rank 0
2292 12:20:27.580275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2293 12:20:27.580365 ==
2294 12:20:27.583480 [Duty_Offset_Calibration]
2295 12:20:27.583568 B0:2 B1:1 CA:1
2296 12:20:27.583631
2297 12:20:27.587079 [DutyScan_Calibration_Flow] k_type=0
2298 12:20:27.597618
2299 12:20:27.597744 ==CLK 0==
2300 12:20:27.601172 Final CLK duty delay cell = 0
2301 12:20:27.603967 [0] MAX Duty = 5187%(X100), DQS PI = 24
2302 12:20:27.607354 [0] MIN Duty = 4875%(X100), DQS PI = 0
2303 12:20:27.607444 [0] AVG Duty = 5031%(X100)
2304 12:20:27.610963
2305 12:20:27.611066 CH0 CLK Duty spec in!! Max-Min= 312%
2306 12:20:27.617637 [DutyScan_Calibration_Flow] ====Done====
2307 12:20:27.617730
2308 12:20:27.620443 [DutyScan_Calibration_Flow] k_type=1
2309 12:20:27.636238
2310 12:20:27.636427 ==DQS 0 ==
2311 12:20:27.639239 Final DQS duty delay cell = -4
2312 12:20:27.642545 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2313 12:20:27.646364 [-4] MIN Duty = 4751%(X100), DQS PI = 62
2314 12:20:27.649204 [-4] AVG Duty = 4937%(X100)
2315 12:20:27.649311
2316 12:20:27.649406 ==DQS 1 ==
2317 12:20:27.652690 Final DQS duty delay cell = 0
2318 12:20:27.656128 [0] MAX Duty = 5187%(X100), DQS PI = 62
2319 12:20:27.659534 [0] MIN Duty = 5031%(X100), DQS PI = 32
2320 12:20:27.662960 [0] AVG Duty = 5109%(X100)
2321 12:20:27.663044
2322 12:20:27.666418 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2323 12:20:27.666494
2324 12:20:27.669589 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2325 12:20:27.672909 [DutyScan_Calibration_Flow] ====Done====
2326 12:20:27.672984
2327 12:20:27.676062 [DutyScan_Calibration_Flow] k_type=3
2328 12:20:27.693086
2329 12:20:27.693228 ==DQM 0 ==
2330 12:20:27.696382 Final DQM duty delay cell = 0
2331 12:20:27.699824 [0] MAX Duty = 5156%(X100), DQS PI = 28
2332 12:20:27.702943 [0] MIN Duty = 4906%(X100), DQS PI = 58
2333 12:20:27.706052 [0] AVG Duty = 5031%(X100)
2334 12:20:27.706134
2335 12:20:27.706196 ==DQM 1 ==
2336 12:20:27.709810 Final DQM duty delay cell = 0
2337 12:20:27.713091 [0] MAX Duty = 5093%(X100), DQS PI = 0
2338 12:20:27.716268 [0] MIN Duty = 5031%(X100), DQS PI = 14
2339 12:20:27.716389 [0] AVG Duty = 5062%(X100)
2340 12:20:27.719394
2341 12:20:27.723114 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2342 12:20:27.723230
2343 12:20:27.726660 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2344 12:20:27.729670 [DutyScan_Calibration_Flow] ====Done====
2345 12:20:27.729750
2346 12:20:27.733120 [DutyScan_Calibration_Flow] k_type=2
2347 12:20:27.749411
2348 12:20:27.749622 ==DQ 0 ==
2349 12:20:27.752415 Final DQ duty delay cell = 0
2350 12:20:27.756322 [0] MAX Duty = 5031%(X100), DQS PI = 26
2351 12:20:27.759559 [0] MIN Duty = 4875%(X100), DQS PI = 62
2352 12:20:27.759635 [0] AVG Duty = 4953%(X100)
2353 12:20:27.762622
2354 12:20:27.762702 ==DQ 1 ==
2355 12:20:27.766034 Final DQ duty delay cell = 0
2356 12:20:27.769398 [0] MAX Duty = 5093%(X100), DQS PI = 24
2357 12:20:27.772419 [0] MIN Duty = 4907%(X100), DQS PI = 36
2358 12:20:27.772505 [0] AVG Duty = 5000%(X100)
2359 12:20:27.772571
2360 12:20:27.776048 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2361 12:20:27.779080
2362 12:20:27.782361 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2363 12:20:27.785856 [DutyScan_Calibration_Flow] ====Done====
2364 12:20:27.785954 ==
2365 12:20:27.789205 Dram Type= 6, Freq= 0, CH_1, rank 0
2366 12:20:27.792971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 12:20:27.793060 ==
2368 12:20:27.795938 [Duty_Offset_Calibration]
2369 12:20:27.796029 B0:1 B1:0 CA:0
2370 12:20:27.796090
2371 12:20:27.799037 [DutyScan_Calibration_Flow] k_type=0
2372 12:20:27.808391
2373 12:20:27.808517 ==CLK 0==
2374 12:20:27.812133 Final CLK duty delay cell = -4
2375 12:20:27.815383 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2376 12:20:27.818535 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2377 12:20:27.821899 [-4] AVG Duty = 4937%(X100)
2378 12:20:27.822014
2379 12:20:27.825385 CH1 CLK Duty spec in!! Max-Min= 125%
2380 12:20:27.828713 [DutyScan_Calibration_Flow] ====Done====
2381 12:20:27.828792
2382 12:20:27.831747 [DutyScan_Calibration_Flow] k_type=1
2383 12:20:27.848611
2384 12:20:27.848763 ==DQS 0 ==
2385 12:20:27.851821 Final DQS duty delay cell = 0
2386 12:20:27.855093 [0] MAX Duty = 5094%(X100), DQS PI = 26
2387 12:20:27.858479 [0] MIN Duty = 4875%(X100), DQS PI = 0
2388 12:20:27.858580 [0] AVG Duty = 4984%(X100)
2389 12:20:27.861805
2390 12:20:27.861896 ==DQS 1 ==
2391 12:20:27.864821 Final DQS duty delay cell = 0
2392 12:20:27.868135 [0] MAX Duty = 5187%(X100), DQS PI = 18
2393 12:20:27.871563 [0] MIN Duty = 4969%(X100), DQS PI = 8
2394 12:20:27.871655 [0] AVG Duty = 5078%(X100)
2395 12:20:27.875465
2396 12:20:27.878569 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2397 12:20:27.878688
2398 12:20:27.881625 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2399 12:20:27.885331 [DutyScan_Calibration_Flow] ====Done====
2400 12:20:27.885421
2401 12:20:27.888483 [DutyScan_Calibration_Flow] k_type=3
2402 12:20:27.904923
2403 12:20:27.905091 ==DQM 0 ==
2404 12:20:27.908106 Final DQM duty delay cell = 0
2405 12:20:27.911449 [0] MAX Duty = 5156%(X100), DQS PI = 8
2406 12:20:27.915169 [0] MIN Duty = 5031%(X100), DQS PI = 0
2407 12:20:27.915285 [0] AVG Duty = 5093%(X100)
2408 12:20:27.915384
2409 12:20:27.918305 ==DQM 1 ==
2410 12:20:27.921572 Final DQM duty delay cell = 0
2411 12:20:27.925553 [0] MAX Duty = 5031%(X100), DQS PI = 26
2412 12:20:27.928489 [0] MIN Duty = 4907%(X100), DQS PI = 34
2413 12:20:27.928585 [0] AVG Duty = 4969%(X100)
2414 12:20:27.928652
2415 12:20:27.931683 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2416 12:20:27.935507
2417 12:20:27.938439 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2418 12:20:27.942122 [DutyScan_Calibration_Flow] ====Done====
2419 12:20:27.942218
2420 12:20:27.945272 [DutyScan_Calibration_Flow] k_type=2
2421 12:20:27.960786
2422 12:20:27.960924 ==DQ 0 ==
2423 12:20:27.963855 Final DQ duty delay cell = -4
2424 12:20:27.967599 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2425 12:20:27.970681 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2426 12:20:27.974029 [-4] AVG Duty = 4984%(X100)
2427 12:20:27.974142
2428 12:20:27.974237 ==DQ 1 ==
2429 12:20:27.977829 Final DQ duty delay cell = 0
2430 12:20:27.980780 [0] MAX Duty = 5125%(X100), DQS PI = 20
2431 12:20:27.984142 [0] MIN Duty = 4969%(X100), DQS PI = 12
2432 12:20:27.984257 [0] AVG Duty = 5047%(X100)
2433 12:20:27.987402
2434 12:20:27.990447 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2435 12:20:27.990530
2436 12:20:27.994141 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2437 12:20:27.997448 [DutyScan_Calibration_Flow] ====Done====
2438 12:20:28.000688 nWR fixed to 30
2439 12:20:28.000787 [ModeRegInit_LP4] CH0 RK0
2440 12:20:28.004305 [ModeRegInit_LP4] CH0 RK1
2441 12:20:28.007044 [ModeRegInit_LP4] CH1 RK0
2442 12:20:28.010808 [ModeRegInit_LP4] CH1 RK1
2443 12:20:28.010893 match AC timing 7
2444 12:20:28.014136 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2445 12:20:28.020655 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2446 12:20:28.024265 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2447 12:20:28.027361 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2448 12:20:28.033915 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2449 12:20:28.034026 ==
2450 12:20:28.037404 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 12:20:28.040995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2452 12:20:28.041078 ==
2453 12:20:28.047460 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2454 12:20:28.054105 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2455 12:20:28.061207 [CA 0] Center 39 (8~70) winsize 63
2456 12:20:28.064378 [CA 1] Center 39 (8~70) winsize 63
2457 12:20:28.067387 [CA 2] Center 35 (5~66) winsize 62
2458 12:20:28.070910 [CA 3] Center 34 (4~65) winsize 62
2459 12:20:28.074470 [CA 4] Center 33 (3~64) winsize 62
2460 12:20:28.077637 [CA 5] Center 32 (3~62) winsize 60
2461 12:20:28.077721
2462 12:20:28.080908 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2463 12:20:28.080981
2464 12:20:28.084777 [CATrainingPosCal] consider 1 rank data
2465 12:20:28.087737 u2DelayCellTimex100 = 270/100 ps
2466 12:20:28.090877 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2467 12:20:28.094634 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2468 12:20:28.097803 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2469 12:20:28.104696 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2470 12:20:28.107929 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2471 12:20:28.111080 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2472 12:20:28.111160
2473 12:20:28.114418 CA PerBit enable=1, Macro0, CA PI delay=32
2474 12:20:28.114494
2475 12:20:28.118000 [CBTSetCACLKResult] CA Dly = 32
2476 12:20:28.118071 CS Dly: 6 (0~37)
2477 12:20:28.118146 ==
2478 12:20:28.121213 Dram Type= 6, Freq= 0, CH_0, rank 1
2479 12:20:28.128281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2480 12:20:28.128432 ==
2481 12:20:28.131318 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2482 12:20:28.138117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2483 12:20:28.146751 [CA 0] Center 38 (8~69) winsize 62
2484 12:20:28.150217 [CA 1] Center 38 (8~69) winsize 62
2485 12:20:28.153257 [CA 2] Center 35 (4~66) winsize 63
2486 12:20:28.156824 [CA 3] Center 34 (4~65) winsize 62
2487 12:20:28.159647 [CA 4] Center 33 (3~64) winsize 62
2488 12:20:28.163421 [CA 5] Center 32 (3~62) winsize 60
2489 12:20:28.163531
2490 12:20:28.166547 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2491 12:20:28.166638
2492 12:20:28.169723 [CATrainingPosCal] consider 2 rank data
2493 12:20:28.173207 u2DelayCellTimex100 = 270/100 ps
2494 12:20:28.176415 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2495 12:20:28.180027 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2496 12:20:28.186937 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2497 12:20:28.190364 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2498 12:20:28.194061 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2499 12:20:28.196741 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2500 12:20:28.196823
2501 12:20:28.200011 CA PerBit enable=1, Macro0, CA PI delay=32
2502 12:20:28.200111
2503 12:20:28.203485 [CBTSetCACLKResult] CA Dly = 32
2504 12:20:28.203570 CS Dly: 6 (0~38)
2505 12:20:28.203634
2506 12:20:28.207014 ----->DramcWriteLeveling(PI) begin...
2507 12:20:28.209721 ==
2508 12:20:28.209809 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 12:20:28.216799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 12:20:28.216897 ==
2511 12:20:28.220119 Write leveling (Byte 0): 36 => 36
2512 12:20:28.223236 Write leveling (Byte 1): 30 => 30
2513 12:20:28.226604 DramcWriteLeveling(PI) end<-----
2514 12:20:28.226686
2515 12:20:28.226751 ==
2516 12:20:28.229963 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 12:20:28.232871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 12:20:28.232949 ==
2519 12:20:28.236765 [Gating] SW mode calibration
2520 12:20:28.243101 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2521 12:20:28.246890 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2522 12:20:28.253406 0 15 0 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
2523 12:20:28.256758 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2524 12:20:28.260355 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 12:20:28.266560 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 12:20:28.270128 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 12:20:28.273155 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 12:20:28.279788 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 12:20:28.283232 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
2530 12:20:28.286817 1 0 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
2531 12:20:28.293410 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 12:20:28.296771 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 12:20:28.299958 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 12:20:28.306668 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 12:20:28.310109 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 12:20:28.313432 1 0 24 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2537 12:20:28.320000 1 0 28 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
2538 12:20:28.323327 1 1 0 | B1->B0 | 3333 4444 | 1 0 | (0 0) (0 0)
2539 12:20:28.327235 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 12:20:28.330225 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 12:20:28.337065 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 12:20:28.340282 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 12:20:28.343466 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 12:20:28.350132 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 12:20:28.353214 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2546 12:20:28.357044 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2547 12:20:28.363626 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 12:20:28.367113 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 12:20:28.370002 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 12:20:28.376921 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 12:20:28.380537 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 12:20:28.383122 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 12:20:28.390344 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 12:20:28.393175 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:20:28.396491 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:20:28.403444 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:20:28.406652 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:20:28.410465 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:20:28.413620 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:20:28.419920 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 12:20:28.423691 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2562 12:20:28.427208 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 12:20:28.430244 Total UI for P1: 0, mck2ui 16
2564 12:20:28.433513 best dqsien dly found for B0: ( 1, 3, 28)
2565 12:20:28.436841 Total UI for P1: 0, mck2ui 16
2566 12:20:28.440438 best dqsien dly found for B1: ( 1, 3, 30)
2567 12:20:28.443669 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2568 12:20:28.447099 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2569 12:20:28.447187
2570 12:20:28.453895 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2571 12:20:28.457119 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2572 12:20:28.460221 [Gating] SW calibration Done
2573 12:20:28.460342 ==
2574 12:20:28.463712 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 12:20:28.467039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 12:20:28.467120 ==
2577 12:20:28.467182 RX Vref Scan: 0
2578 12:20:28.467245
2579 12:20:28.470323 RX Vref 0 -> 0, step: 1
2580 12:20:28.470419
2581 12:20:28.473914 RX Delay -40 -> 252, step: 8
2582 12:20:28.477279 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2583 12:20:28.480488 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2584 12:20:28.483931 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2585 12:20:28.490453 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2586 12:20:28.493790 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2587 12:20:28.497070 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2588 12:20:28.500756 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2589 12:20:28.503790 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2590 12:20:28.510914 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2591 12:20:28.513825 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2592 12:20:28.517315 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2593 12:20:28.520776 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2594 12:20:28.524266 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2595 12:20:28.530775 iDelay=200, Bit 13, Center 119 (56 ~ 183) 128
2596 12:20:28.533993 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2597 12:20:28.537367 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2598 12:20:28.537449 ==
2599 12:20:28.541076 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 12:20:28.544509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 12:20:28.544591 ==
2602 12:20:28.547744 DQS Delay:
2603 12:20:28.547828 DQS0 = 0, DQS1 = 0
2604 12:20:28.547889 DQM Delay:
2605 12:20:28.551249 DQM0 = 121, DQM1 = 113
2606 12:20:28.551320 DQ Delay:
2607 12:20:28.554395 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2608 12:20:28.557595 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2609 12:20:28.564599 DQ8 =103, DQ9 =107, DQ10 =111, DQ11 =107
2610 12:20:28.567858 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2611 12:20:28.567939
2612 12:20:28.568001
2613 12:20:28.568064 ==
2614 12:20:28.570925 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 12:20:28.574256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 12:20:28.574329 ==
2617 12:20:28.574389
2618 12:20:28.574444
2619 12:20:28.577543 TX Vref Scan disable
2620 12:20:28.577611 == TX Byte 0 ==
2621 12:20:28.584597 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2622 12:20:28.587600 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2623 12:20:28.587681 == TX Byte 1 ==
2624 12:20:28.594601 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2625 12:20:28.597854 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2626 12:20:28.597943 ==
2627 12:20:28.601104 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 12:20:28.604435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 12:20:28.604513 ==
2630 12:20:28.617782 TX Vref=22, minBit 4, minWin=24, winSum=404
2631 12:20:28.620703 TX Vref=24, minBit 4, minWin=24, winSum=411
2632 12:20:28.624093 TX Vref=26, minBit 0, minWin=26, winSum=419
2633 12:20:28.627666 TX Vref=28, minBit 10, minWin=25, winSum=420
2634 12:20:28.630795 TX Vref=30, minBit 0, minWin=26, winSum=422
2635 12:20:28.634657 TX Vref=32, minBit 3, minWin=25, winSum=416
2636 12:20:28.640773 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 30
2637 12:20:28.640884
2638 12:20:28.644269 Final TX Range 1 Vref 30
2639 12:20:28.644400
2640 12:20:28.644491 ==
2641 12:20:28.647755 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 12:20:28.651298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 12:20:28.651376 ==
2644 12:20:28.651438
2645 12:20:28.651495
2646 12:20:28.654885 TX Vref Scan disable
2647 12:20:28.657940 == TX Byte 0 ==
2648 12:20:28.661142 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2649 12:20:28.664767 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2650 12:20:28.668132 == TX Byte 1 ==
2651 12:20:28.671247 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2652 12:20:28.674455 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2653 12:20:28.674531
2654 12:20:28.678356 [DATLAT]
2655 12:20:28.678429 Freq=1200, CH0 RK0
2656 12:20:28.678489
2657 12:20:28.681449 DATLAT Default: 0xd
2658 12:20:28.681518 0, 0xFFFF, sum = 0
2659 12:20:28.684672 1, 0xFFFF, sum = 0
2660 12:20:28.684749 2, 0xFFFF, sum = 0
2661 12:20:28.687848 3, 0xFFFF, sum = 0
2662 12:20:28.687924 4, 0xFFFF, sum = 0
2663 12:20:28.691174 5, 0xFFFF, sum = 0
2664 12:20:28.691245 6, 0xFFFF, sum = 0
2665 12:20:28.694816 7, 0xFFFF, sum = 0
2666 12:20:28.694896 8, 0xFFFF, sum = 0
2667 12:20:28.698096 9, 0xFFFF, sum = 0
2668 12:20:28.698171 10, 0xFFFF, sum = 0
2669 12:20:28.701383 11, 0xFFFF, sum = 0
2670 12:20:28.704717 12, 0x0, sum = 1
2671 12:20:28.704797 13, 0x0, sum = 2
2672 12:20:28.704858 14, 0x0, sum = 3
2673 12:20:28.707897 15, 0x0, sum = 4
2674 12:20:28.707966 best_step = 13
2675 12:20:28.708030
2676 12:20:28.708085 ==
2677 12:20:28.711333 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 12:20:28.717633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 12:20:28.717723 ==
2680 12:20:28.717784 RX Vref Scan: 1
2681 12:20:28.717849
2682 12:20:28.721367 Set Vref Range= 32 -> 127
2683 12:20:28.721447
2684 12:20:28.724511 RX Vref 32 -> 127, step: 1
2685 12:20:28.724664
2686 12:20:28.727767 RX Delay -5 -> 252, step: 4
2687 12:20:28.727849
2688 12:20:28.727909 Set Vref, RX VrefLevel [Byte0]: 32
2689 12:20:28.731062 [Byte1]: 32
2690 12:20:28.735705
2691 12:20:28.735791 Set Vref, RX VrefLevel [Byte0]: 33
2692 12:20:28.739195 [Byte1]: 33
2693 12:20:28.743557
2694 12:20:28.743651 Set Vref, RX VrefLevel [Byte0]: 34
2695 12:20:28.747206 [Byte1]: 34
2696 12:20:28.751429
2697 12:20:28.751513 Set Vref, RX VrefLevel [Byte0]: 35
2698 12:20:28.754591 [Byte1]: 35
2699 12:20:28.759619
2700 12:20:28.759702 Set Vref, RX VrefLevel [Byte0]: 36
2701 12:20:28.762898 [Byte1]: 36
2702 12:20:28.767231
2703 12:20:28.767316 Set Vref, RX VrefLevel [Byte0]: 37
2704 12:20:28.771073 [Byte1]: 37
2705 12:20:28.775135
2706 12:20:28.775224 Set Vref, RX VrefLevel [Byte0]: 38
2707 12:20:28.778601 [Byte1]: 38
2708 12:20:28.782919
2709 12:20:28.783006 Set Vref, RX VrefLevel [Byte0]: 39
2710 12:20:28.786128 [Byte1]: 39
2711 12:20:28.791284
2712 12:20:28.791364 Set Vref, RX VrefLevel [Byte0]: 40
2713 12:20:28.793945 [Byte1]: 40
2714 12:20:28.798666
2715 12:20:28.798746 Set Vref, RX VrefLevel [Byte0]: 41
2716 12:20:28.802090 [Byte1]: 41
2717 12:20:28.806684
2718 12:20:28.806765 Set Vref, RX VrefLevel [Byte0]: 42
2719 12:20:28.809800 [Byte1]: 42
2720 12:20:28.814295
2721 12:20:28.814377 Set Vref, RX VrefLevel [Byte0]: 43
2722 12:20:28.817649 [Byte1]: 43
2723 12:20:28.822025
2724 12:20:28.822119 Set Vref, RX VrefLevel [Byte0]: 44
2725 12:20:28.825973 [Byte1]: 44
2726 12:20:28.830352
2727 12:20:28.830442 Set Vref, RX VrefLevel [Byte0]: 45
2728 12:20:28.833379 [Byte1]: 45
2729 12:20:28.838036
2730 12:20:28.838120 Set Vref, RX VrefLevel [Byte0]: 46
2731 12:20:28.841267 [Byte1]: 46
2732 12:20:28.846040
2733 12:20:28.846129 Set Vref, RX VrefLevel [Byte0]: 47
2734 12:20:28.849020 [Byte1]: 47
2735 12:20:28.853597
2736 12:20:28.853691 Set Vref, RX VrefLevel [Byte0]: 48
2737 12:20:28.856832 [Byte1]: 48
2738 12:20:28.861817
2739 12:20:28.861905 Set Vref, RX VrefLevel [Byte0]: 49
2740 12:20:28.864881 [Byte1]: 49
2741 12:20:28.869341
2742 12:20:28.869429 Set Vref, RX VrefLevel [Byte0]: 50
2743 12:20:28.872483 [Byte1]: 50
2744 12:20:28.877347
2745 12:20:28.877435 Set Vref, RX VrefLevel [Byte0]: 51
2746 12:20:28.880523 [Byte1]: 51
2747 12:20:28.884928
2748 12:20:28.885055 Set Vref, RX VrefLevel [Byte0]: 52
2749 12:20:28.888775 [Byte1]: 52
2750 12:20:28.892877
2751 12:20:28.892967 Set Vref, RX VrefLevel [Byte0]: 53
2752 12:20:28.896072 [Byte1]: 53
2753 12:20:28.901281
2754 12:20:28.901366 Set Vref, RX VrefLevel [Byte0]: 54
2755 12:20:28.903819 [Byte1]: 54
2756 12:20:28.908960
2757 12:20:28.909074 Set Vref, RX VrefLevel [Byte0]: 55
2758 12:20:28.912105 [Byte1]: 55
2759 12:20:28.916477
2760 12:20:28.916564 Set Vref, RX VrefLevel [Byte0]: 56
2761 12:20:28.919685 [Byte1]: 56
2762 12:20:28.924072
2763 12:20:28.924161 Set Vref, RX VrefLevel [Byte0]: 57
2764 12:20:28.927921 [Byte1]: 57
2765 12:20:28.932469
2766 12:20:28.932559 Set Vref, RX VrefLevel [Byte0]: 58
2767 12:20:28.935734 [Byte1]: 58
2768 12:20:28.940230
2769 12:20:28.940346 Set Vref, RX VrefLevel [Byte0]: 59
2770 12:20:28.943420 [Byte1]: 59
2771 12:20:28.947841
2772 12:20:28.947933 Set Vref, RX VrefLevel [Byte0]: 60
2773 12:20:28.951473 [Byte1]: 60
2774 12:20:28.955454
2775 12:20:28.955544 Set Vref, RX VrefLevel [Byte0]: 61
2776 12:20:28.958913 [Byte1]: 61
2777 12:20:28.963928
2778 12:20:28.964037 Set Vref, RX VrefLevel [Byte0]: 62
2779 12:20:28.967085 [Byte1]: 62
2780 12:20:28.971415
2781 12:20:28.971503 Set Vref, RX VrefLevel [Byte0]: 63
2782 12:20:28.974909 [Byte1]: 63
2783 12:20:28.979207
2784 12:20:28.979289 Set Vref, RX VrefLevel [Byte0]: 64
2785 12:20:28.982759 [Byte1]: 64
2786 12:20:28.987283
2787 12:20:28.987372 Set Vref, RX VrefLevel [Byte0]: 65
2788 12:20:28.990524 [Byte1]: 65
2789 12:20:28.995049
2790 12:20:28.995179 Set Vref, RX VrefLevel [Byte0]: 66
2791 12:20:28.998378 [Byte1]: 66
2792 12:20:29.002992
2793 12:20:29.003094 Set Vref, RX VrefLevel [Byte0]: 67
2794 12:20:29.006126 [Byte1]: 67
2795 12:20:29.010432
2796 12:20:29.010519 Set Vref, RX VrefLevel [Byte0]: 68
2797 12:20:29.014174 [Byte1]: 68
2798 12:20:29.018559
2799 12:20:29.018654 Final RX Vref Byte 0 = 55 to rank0
2800 12:20:29.021616 Final RX Vref Byte 1 = 50 to rank0
2801 12:20:29.025630 Final RX Vref Byte 0 = 55 to rank1
2802 12:20:29.028733 Final RX Vref Byte 1 = 50 to rank1==
2803 12:20:29.031860 Dram Type= 6, Freq= 0, CH_0, rank 0
2804 12:20:29.034973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2805 12:20:29.038921 ==
2806 12:20:29.039016 DQS Delay:
2807 12:20:29.039082 DQS0 = 0, DQS1 = 0
2808 12:20:29.041990 DQM Delay:
2809 12:20:29.042075 DQM0 = 120, DQM1 = 112
2810 12:20:29.045355 DQ Delay:
2811 12:20:29.049149 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =118
2812 12:20:29.052405 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2813 12:20:29.055352 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2814 12:20:29.058472 DQ12 =118, DQ13 =116, DQ14 =124, DQ15 =122
2815 12:20:29.058580
2816 12:20:29.058674
2817 12:20:29.065539 [DQSOSCAuto] RK0, (LSB)MR18= 0x160f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2818 12:20:29.068907 CH0 RK0: MR19=404, MR18=160F
2819 12:20:29.075436 CH0_RK0: MR19=0x404, MR18=0x160F, DQSOSC=401, MR23=63, INC=40, DEC=27
2820 12:20:29.075544
2821 12:20:29.078631 ----->DramcWriteLeveling(PI) begin...
2822 12:20:29.078707 ==
2823 12:20:29.082558 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 12:20:29.085563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 12:20:29.088732 ==
2826 12:20:29.088832 Write leveling (Byte 0): 32 => 32
2827 12:20:29.092009 Write leveling (Byte 1): 29 => 29
2828 12:20:29.095373 DramcWriteLeveling(PI) end<-----
2829 12:20:29.095483
2830 12:20:29.095585 ==
2831 12:20:29.098558 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 12:20:29.105783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 12:20:29.105907 ==
2834 12:20:29.105976 [Gating] SW mode calibration
2835 12:20:29.115679 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2836 12:20:29.118566 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2837 12:20:29.121905 0 15 0 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
2838 12:20:29.128901 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 12:20:29.132082 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 12:20:29.135364 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 12:20:29.142478 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 12:20:29.145762 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 12:20:29.148865 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 12:20:29.155939 0 15 28 | B1->B0 | 3030 3131 | 0 0 | (1 0) (0 1)
2845 12:20:29.159090 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2846 12:20:29.162444 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 12:20:29.169157 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 12:20:29.172258 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 12:20:29.175540 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 12:20:29.179260 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 12:20:29.185584 1 0 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
2852 12:20:29.188774 1 0 28 | B1->B0 | 3b3b 3939 | 1 0 | (0 0) (0 0)
2853 12:20:29.192619 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2854 12:20:29.199207 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 12:20:29.202584 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 12:20:29.205614 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 12:20:29.212207 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 12:20:29.215492 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 12:20:29.219031 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2860 12:20:29.225409 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2861 12:20:29.228594 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2862 12:20:29.232579 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 12:20:29.239124 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 12:20:29.242403 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 12:20:29.245385 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 12:20:29.252127 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 12:20:29.255268 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 12:20:29.258915 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 12:20:29.265253 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 12:20:29.268514 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 12:20:29.272242 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 12:20:29.279201 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 12:20:29.281804 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 12:20:29.285497 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 12:20:29.291876 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 12:20:29.295167 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2877 12:20:29.299004 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2878 12:20:29.302040 Total UI for P1: 0, mck2ui 16
2879 12:20:29.305242 best dqsien dly found for B1: ( 1, 3, 28)
2880 12:20:29.309075 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 12:20:29.312241 Total UI for P1: 0, mck2ui 16
2882 12:20:29.315550 best dqsien dly found for B0: ( 1, 3, 30)
2883 12:20:29.318729 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2884 12:20:29.322273 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2885 12:20:29.325752
2886 12:20:29.328929 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2887 12:20:29.331819 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2888 12:20:29.336094 [Gating] SW calibration Done
2889 12:20:29.336170 ==
2890 12:20:29.339021 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 12:20:29.342296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 12:20:29.342375 ==
2893 12:20:29.342439 RX Vref Scan: 0
2894 12:20:29.342497
2895 12:20:29.345193 RX Vref 0 -> 0, step: 1
2896 12:20:29.345265
2897 12:20:29.349057 RX Delay -40 -> 252, step: 8
2898 12:20:29.351968 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2899 12:20:29.355090 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2900 12:20:29.362108 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2901 12:20:29.365387 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2902 12:20:29.368922 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2903 12:20:29.371809 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2904 12:20:29.375330 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2905 12:20:29.381779 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2906 12:20:29.385356 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2907 12:20:29.388954 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2908 12:20:29.392377 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2909 12:20:29.395653 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2910 12:20:29.398516 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2911 12:20:29.405426 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2912 12:20:29.408730 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2913 12:20:29.412552 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2914 12:20:29.412626 ==
2915 12:20:29.415765 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 12:20:29.418914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 12:20:29.422143 ==
2918 12:20:29.422217 DQS Delay:
2919 12:20:29.422279 DQS0 = 0, DQS1 = 0
2920 12:20:29.426029 DQM Delay:
2921 12:20:29.426101 DQM0 = 121, DQM1 = 112
2922 12:20:29.429099 DQ Delay:
2923 12:20:29.432201 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2924 12:20:29.435412 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2925 12:20:29.439013 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2926 12:20:29.442228 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2927 12:20:29.442299
2928 12:20:29.442363
2929 12:20:29.442420 ==
2930 12:20:29.445665 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 12:20:29.448814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 12:20:29.448887 ==
2933 12:20:29.448948
2934 12:20:29.449009
2935 12:20:29.452943 TX Vref Scan disable
2936 12:20:29.455363 == TX Byte 0 ==
2937 12:20:29.458635 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2938 12:20:29.462380 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2939 12:20:29.465635 == TX Byte 1 ==
2940 12:20:29.468859 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2941 12:20:29.472129 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2942 12:20:29.472203 ==
2943 12:20:29.475211 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 12:20:29.479054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 12:20:29.481920 ==
2946 12:20:29.492729 TX Vref=22, minBit 1, minWin=25, winSum=410
2947 12:20:29.496061 TX Vref=24, minBit 3, minWin=25, winSum=417
2948 12:20:29.499471 TX Vref=26, minBit 3, minWin=25, winSum=419
2949 12:20:29.502277 TX Vref=28, minBit 13, minWin=25, winSum=425
2950 12:20:29.505730 TX Vref=30, minBit 12, minWin=25, winSum=424
2951 12:20:29.512598 TX Vref=32, minBit 13, minWin=25, winSum=422
2952 12:20:29.516036 [TxChooseVref] Worse bit 13, Min win 25, Win sum 425, Final Vref 28
2953 12:20:29.516117
2954 12:20:29.519511 Final TX Range 1 Vref 28
2955 12:20:29.519675
2956 12:20:29.519830 ==
2957 12:20:29.522526 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 12:20:29.525778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 12:20:29.525866 ==
2960 12:20:29.529136
2961 12:20:29.529217
2962 12:20:29.529280 TX Vref Scan disable
2963 12:20:29.532780 == TX Byte 0 ==
2964 12:20:29.536060 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2965 12:20:29.539441 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2966 12:20:29.542872 == TX Byte 1 ==
2967 12:20:29.546047 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2968 12:20:29.549397 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2969 12:20:29.552957
2970 12:20:29.553039 [DATLAT]
2971 12:20:29.553103 Freq=1200, CH0 RK1
2972 12:20:29.553162
2973 12:20:29.555832 DATLAT Default: 0xd
2974 12:20:29.555912 0, 0xFFFF, sum = 0
2975 12:20:29.559488 1, 0xFFFF, sum = 0
2976 12:20:29.559571 2, 0xFFFF, sum = 0
2977 12:20:29.562697 3, 0xFFFF, sum = 0
2978 12:20:29.562780 4, 0xFFFF, sum = 0
2979 12:20:29.566253 5, 0xFFFF, sum = 0
2980 12:20:29.569526 6, 0xFFFF, sum = 0
2981 12:20:29.569609 7, 0xFFFF, sum = 0
2982 12:20:29.572772 8, 0xFFFF, sum = 0
2983 12:20:29.572855 9, 0xFFFF, sum = 0
2984 12:20:29.575880 10, 0xFFFF, sum = 0
2985 12:20:29.575963 11, 0xFFFF, sum = 0
2986 12:20:29.579720 12, 0x0, sum = 1
2987 12:20:29.579802 13, 0x0, sum = 2
2988 12:20:29.582826 14, 0x0, sum = 3
2989 12:20:29.582909 15, 0x0, sum = 4
2990 12:20:29.582974 best_step = 13
2991 12:20:29.583033
2992 12:20:29.586047 ==
2993 12:20:29.589613 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 12:20:29.592628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 12:20:29.592711 ==
2996 12:20:29.592775 RX Vref Scan: 0
2997 12:20:29.592834
2998 12:20:29.596004 RX Vref 0 -> 0, step: 1
2999 12:20:29.596084
3000 12:20:29.599591 RX Delay -13 -> 252, step: 4
3001 12:20:29.602862 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3002 12:20:29.609504 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3003 12:20:29.612642 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3004 12:20:29.615925 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3005 12:20:29.619233 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3006 12:20:29.622520 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3007 12:20:29.626254 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3008 12:20:29.632695 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3009 12:20:29.636059 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3010 12:20:29.639548 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3011 12:20:29.642915 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3012 12:20:29.646165 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3013 12:20:29.652870 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3014 12:20:29.656628 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3015 12:20:29.659821 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3016 12:20:29.663010 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3017 12:20:29.663080 ==
3018 12:20:29.666085 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 12:20:29.672647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 12:20:29.672722 ==
3021 12:20:29.672782 DQS Delay:
3022 12:20:29.672840 DQS0 = 0, DQS1 = 0
3023 12:20:29.676085 DQM Delay:
3024 12:20:29.676168 DQM0 = 120, DQM1 = 111
3025 12:20:29.679681 DQ Delay:
3026 12:20:29.683016 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3027 12:20:29.686140 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3028 12:20:29.689281 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =104
3029 12:20:29.693091 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =120
3030 12:20:29.693166
3031 12:20:29.693227
3032 12:20:29.699404 [DQSOSCAuto] RK1, (LSB)MR18= 0xef0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 404 ps
3033 12:20:29.702875 CH0 RK1: MR19=403, MR18=EF0
3034 12:20:29.709479 CH0_RK1: MR19=0x403, MR18=0xEF0, DQSOSC=404, MR23=63, INC=40, DEC=26
3035 12:20:29.712660 [RxdqsGatingPostProcess] freq 1200
3036 12:20:29.719765 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3037 12:20:29.722937 best DQS0 dly(2T, 0.5T) = (0, 11)
3038 12:20:29.723016 best DQS1 dly(2T, 0.5T) = (0, 11)
3039 12:20:29.726059 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3040 12:20:29.729407 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3041 12:20:29.733102 best DQS0 dly(2T, 0.5T) = (0, 11)
3042 12:20:29.736001 best DQS1 dly(2T, 0.5T) = (0, 11)
3043 12:20:29.739838 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3044 12:20:29.742975 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3045 12:20:29.746139 Pre-setting of DQS Precalculation
3046 12:20:29.753144 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3047 12:20:29.753222 ==
3048 12:20:29.756111 Dram Type= 6, Freq= 0, CH_1, rank 0
3049 12:20:29.759537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 12:20:29.759608 ==
3051 12:20:29.766094 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3052 12:20:29.769399 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3053 12:20:29.778778 [CA 0] Center 37 (7~68) winsize 62
3054 12:20:29.782126 [CA 1] Center 37 (7~68) winsize 62
3055 12:20:29.785605 [CA 2] Center 35 (5~65) winsize 61
3056 12:20:29.789065 [CA 3] Center 34 (4~64) winsize 61
3057 12:20:29.792274 [CA 4] Center 34 (4~64) winsize 61
3058 12:20:29.795463 [CA 5] Center 33 (3~63) winsize 61
3059 12:20:29.795535
3060 12:20:29.799142 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3061 12:20:29.799218
3062 12:20:29.802334 [CATrainingPosCal] consider 1 rank data
3063 12:20:29.805585 u2DelayCellTimex100 = 270/100 ps
3064 12:20:29.809169 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3065 12:20:29.812709 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3066 12:20:29.815559 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3067 12:20:29.822306 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3068 12:20:29.825941 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3069 12:20:29.829133 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3070 12:20:29.829214
3071 12:20:29.832388 CA PerBit enable=1, Macro0, CA PI delay=33
3072 12:20:29.832461
3073 12:20:29.835684 [CBTSetCACLKResult] CA Dly = 33
3074 12:20:29.835756 CS Dly: 8 (0~39)
3075 12:20:29.835817 ==
3076 12:20:29.839459 Dram Type= 6, Freq= 0, CH_1, rank 1
3077 12:20:29.845708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 12:20:29.845803 ==
3079 12:20:29.849092 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3080 12:20:29.855566 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3081 12:20:29.864518 [CA 0] Center 37 (7~68) winsize 62
3082 12:20:29.867527 [CA 1] Center 37 (7~68) winsize 62
3083 12:20:29.871276 [CA 2] Center 35 (5~65) winsize 61
3084 12:20:29.874198 [CA 3] Center 34 (4~65) winsize 62
3085 12:20:29.877564 [CA 4] Center 34 (4~65) winsize 62
3086 12:20:29.881336 [CA 5] Center 33 (3~64) winsize 62
3087 12:20:29.881415
3088 12:20:29.884852 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3089 12:20:29.884928
3090 12:20:29.887784 [CATrainingPosCal] consider 2 rank data
3091 12:20:29.891107 u2DelayCellTimex100 = 270/100 ps
3092 12:20:29.894384 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3093 12:20:29.897767 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3094 12:20:29.904808 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3095 12:20:29.907877 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 12:20:29.911050 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 12:20:29.914800 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3098 12:20:29.914912
3099 12:20:29.917811 CA PerBit enable=1, Macro0, CA PI delay=33
3100 12:20:29.917883
3101 12:20:29.921388 [CBTSetCACLKResult] CA Dly = 33
3102 12:20:29.921461 CS Dly: 9 (0~41)
3103 12:20:29.921521
3104 12:20:29.924599 ----->DramcWriteLeveling(PI) begin...
3105 12:20:29.927730 ==
3106 12:20:29.927803 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 12:20:29.934957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 12:20:29.935035 ==
3109 12:20:29.937928 Write leveling (Byte 0): 25 => 25
3110 12:20:29.941140 Write leveling (Byte 1): 27 => 27
3111 12:20:29.941218 DramcWriteLeveling(PI) end<-----
3112 12:20:29.944504
3113 12:20:29.944582 ==
3114 12:20:29.948247 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 12:20:29.951201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 12:20:29.951282 ==
3117 12:20:29.954522 [Gating] SW mode calibration
3118 12:20:29.961454 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3119 12:20:29.964490 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3120 12:20:29.971382 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3121 12:20:29.975177 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 12:20:29.978015 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 12:20:29.984878 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 12:20:29.988094 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 12:20:29.991226 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 12:20:29.998683 0 15 24 | B1->B0 | 3333 3232 | 1 0 | (1 0) (0 0)
3127 12:20:30.001757 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3128 12:20:30.004780 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 12:20:30.011492 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 12:20:30.014780 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 12:20:30.018529 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 12:20:30.021456 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 12:20:30.027920 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 12:20:30.031305 1 0 24 | B1->B0 | 2c2c 3c3c | 0 0 | (0 0) (0 0)
3135 12:20:30.035289 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 12:20:30.041405 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 12:20:30.045188 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 12:20:30.048574 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 12:20:30.054755 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 12:20:30.058597 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 12:20:30.061777 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 12:20:30.068012 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3143 12:20:30.071298 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3144 12:20:30.074679 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 12:20:30.081841 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 12:20:30.085200 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 12:20:30.088624 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 12:20:30.095425 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 12:20:30.097897 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 12:20:30.101725 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 12:20:30.108216 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 12:20:30.111812 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 12:20:30.115246 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 12:20:30.118074 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 12:20:30.125009 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 12:20:30.128561 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 12:20:30.131837 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 12:20:30.138191 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3159 12:20:30.141536 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3160 12:20:30.145172 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 12:20:30.148518 Total UI for P1: 0, mck2ui 16
3162 12:20:30.151904 best dqsien dly found for B0: ( 1, 3, 26)
3163 12:20:30.155411 Total UI for P1: 0, mck2ui 16
3164 12:20:30.158093 best dqsien dly found for B1: ( 1, 3, 26)
3165 12:20:30.161824 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3166 12:20:30.164906 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3167 12:20:30.165020
3168 12:20:30.171809 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3169 12:20:30.174949 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3170 12:20:30.175048 [Gating] SW calibration Done
3171 12:20:30.178199 ==
3172 12:20:30.178273 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 12:20:30.185151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 12:20:30.185255 ==
3175 12:20:30.185319 RX Vref Scan: 0
3176 12:20:30.185378
3177 12:20:30.188644 RX Vref 0 -> 0, step: 1
3178 12:20:30.188726
3179 12:20:30.191688 RX Delay -40 -> 252, step: 8
3180 12:20:30.195208 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3181 12:20:30.198155 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3182 12:20:30.201886 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3183 12:20:30.208629 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3184 12:20:30.212096 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3185 12:20:30.215061 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3186 12:20:30.218858 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3187 12:20:30.221915 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3188 12:20:30.228183 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3189 12:20:30.232084 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3190 12:20:30.235076 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3191 12:20:30.238221 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3192 12:20:30.242052 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3193 12:20:30.248713 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3194 12:20:30.251897 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3195 12:20:30.254938 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3196 12:20:30.255012 ==
3197 12:20:30.258509 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 12:20:30.261846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 12:20:30.261920 ==
3200 12:20:30.265186 DQS Delay:
3201 12:20:30.265266 DQS0 = 0, DQS1 = 0
3202 12:20:30.265328 DQM Delay:
3203 12:20:30.268946 DQM0 = 120, DQM1 = 116
3204 12:20:30.269019 DQ Delay:
3205 12:20:30.272244 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3206 12:20:30.275200 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3207 12:20:30.282126 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3208 12:20:30.285828 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3209 12:20:30.285909
3210 12:20:30.285972
3211 12:20:30.286029 ==
3212 12:20:30.288895 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 12:20:30.292187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 12:20:30.292334 ==
3215 12:20:30.292399
3216 12:20:30.292457
3217 12:20:30.295955 TX Vref Scan disable
3218 12:20:30.296026 == TX Byte 0 ==
3219 12:20:30.302673 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3220 12:20:30.306134 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3221 12:20:30.306213 == TX Byte 1 ==
3222 12:20:30.312266 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3223 12:20:30.315664 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3224 12:20:30.315738 ==
3225 12:20:30.318848 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 12:20:30.322700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 12:20:30.322781 ==
3228 12:20:30.335023 TX Vref=22, minBit 12, minWin=24, winSum=410
3229 12:20:30.337954 TX Vref=24, minBit 11, minWin=25, winSum=420
3230 12:20:30.341390 TX Vref=26, minBit 9, minWin=25, winSum=423
3231 12:20:30.344605 TX Vref=28, minBit 9, minWin=25, winSum=425
3232 12:20:30.348060 TX Vref=30, minBit 9, minWin=25, winSum=429
3233 12:20:30.354522 TX Vref=32, minBit 9, minWin=26, winSum=434
3234 12:20:30.358295 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 32
3235 12:20:30.358378
3236 12:20:30.361510 Final TX Range 1 Vref 32
3237 12:20:30.361586
3238 12:20:30.361645 ==
3239 12:20:30.364654 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 12:20:30.367869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 12:20:30.367963 ==
3242 12:20:30.368023
3243 12:20:30.372091
3244 12:20:30.372162 TX Vref Scan disable
3245 12:20:30.375037 == TX Byte 0 ==
3246 12:20:30.378008 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3247 12:20:30.381187 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3248 12:20:30.384807 == TX Byte 1 ==
3249 12:20:30.388028 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3250 12:20:30.391322 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3251 12:20:30.391408
3252 12:20:30.394574 [DATLAT]
3253 12:20:30.394691 Freq=1200, CH1 RK0
3254 12:20:30.394751
3255 12:20:30.397811 DATLAT Default: 0xd
3256 12:20:30.397879 0, 0xFFFF, sum = 0
3257 12:20:30.401711 1, 0xFFFF, sum = 0
3258 12:20:30.401788 2, 0xFFFF, sum = 0
3259 12:20:30.404662 3, 0xFFFF, sum = 0
3260 12:20:30.404733 4, 0xFFFF, sum = 0
3261 12:20:30.408256 5, 0xFFFF, sum = 0
3262 12:20:30.408386 6, 0xFFFF, sum = 0
3263 12:20:30.411607 7, 0xFFFF, sum = 0
3264 12:20:30.414729 8, 0xFFFF, sum = 0
3265 12:20:30.414801 9, 0xFFFF, sum = 0
3266 12:20:30.418013 10, 0xFFFF, sum = 0
3267 12:20:30.418084 11, 0xFFFF, sum = 0
3268 12:20:30.421672 12, 0x0, sum = 1
3269 12:20:30.421745 13, 0x0, sum = 2
3270 12:20:30.424594 14, 0x0, sum = 3
3271 12:20:30.424707 15, 0x0, sum = 4
3272 12:20:30.424785 best_step = 13
3273 12:20:30.424850
3274 12:20:30.427936 ==
3275 12:20:30.431132 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 12:20:30.434466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 12:20:30.434543 ==
3278 12:20:30.434607 RX Vref Scan: 1
3279 12:20:30.434665
3280 12:20:30.438037 Set Vref Range= 32 -> 127
3281 12:20:30.438105
3282 12:20:30.441322 RX Vref 32 -> 127, step: 1
3283 12:20:30.441395
3284 12:20:30.444921 RX Delay -5 -> 252, step: 4
3285 12:20:30.444993
3286 12:20:30.447941 Set Vref, RX VrefLevel [Byte0]: 32
3287 12:20:30.451037 [Byte1]: 32
3288 12:20:30.451113
3289 12:20:30.454668 Set Vref, RX VrefLevel [Byte0]: 33
3290 12:20:30.457747 [Byte1]: 33
3291 12:20:30.457827
3292 12:20:30.460941 Set Vref, RX VrefLevel [Byte0]: 34
3293 12:20:30.464282 [Byte1]: 34
3294 12:20:30.468470
3295 12:20:30.468564 Set Vref, RX VrefLevel [Byte0]: 35
3296 12:20:30.472224 [Byte1]: 35
3297 12:20:30.477070
3298 12:20:30.477141 Set Vref, RX VrefLevel [Byte0]: 36
3299 12:20:30.479842 [Byte1]: 36
3300 12:20:30.484333
3301 12:20:30.484434 Set Vref, RX VrefLevel [Byte0]: 37
3302 12:20:30.487613 [Byte1]: 37
3303 12:20:30.492203
3304 12:20:30.492324 Set Vref, RX VrefLevel [Byte0]: 38
3305 12:20:30.495336 [Byte1]: 38
3306 12:20:30.499965
3307 12:20:30.500037 Set Vref, RX VrefLevel [Byte0]: 39
3308 12:20:30.503701 [Byte1]: 39
3309 12:20:30.507991
3310 12:20:30.508061 Set Vref, RX VrefLevel [Byte0]: 40
3311 12:20:30.511460 [Byte1]: 40
3312 12:20:30.515700
3313 12:20:30.515773 Set Vref, RX VrefLevel [Byte0]: 41
3314 12:20:30.518931 [Byte1]: 41
3315 12:20:30.523645
3316 12:20:30.523773 Set Vref, RX VrefLevel [Byte0]: 42
3317 12:20:30.530312 [Byte1]: 42
3318 12:20:30.530410
3319 12:20:30.533611 Set Vref, RX VrefLevel [Byte0]: 43
3320 12:20:30.536624 [Byte1]: 43
3321 12:20:30.536702
3322 12:20:30.540423 Set Vref, RX VrefLevel [Byte0]: 44
3323 12:20:30.543496 [Byte1]: 44
3324 12:20:30.547486
3325 12:20:30.547564 Set Vref, RX VrefLevel [Byte0]: 45
3326 12:20:30.550405 [Byte1]: 45
3327 12:20:30.555182
3328 12:20:30.555256 Set Vref, RX VrefLevel [Byte0]: 46
3329 12:20:30.558163 [Byte1]: 46
3330 12:20:30.563096
3331 12:20:30.563167 Set Vref, RX VrefLevel [Byte0]: 47
3332 12:20:30.566003 [Byte1]: 47
3333 12:20:30.570810
3334 12:20:30.570892 Set Vref, RX VrefLevel [Byte0]: 48
3335 12:20:30.573780 [Byte1]: 48
3336 12:20:30.578933
3337 12:20:30.579016 Set Vref, RX VrefLevel [Byte0]: 49
3338 12:20:30.582242 [Byte1]: 49
3339 12:20:30.586599
3340 12:20:30.586669 Set Vref, RX VrefLevel [Byte0]: 50
3341 12:20:30.589915 [Byte1]: 50
3342 12:20:30.594306
3343 12:20:30.594383 Set Vref, RX VrefLevel [Byte0]: 51
3344 12:20:30.597547 [Byte1]: 51
3345 12:20:30.602476
3346 12:20:30.602554 Set Vref, RX VrefLevel [Byte0]: 52
3347 12:20:30.605562 [Byte1]: 52
3348 12:20:30.610227
3349 12:20:30.610300 Set Vref, RX VrefLevel [Byte0]: 53
3350 12:20:30.613438 [Byte1]: 53
3351 12:20:30.617764
3352 12:20:30.617837 Set Vref, RX VrefLevel [Byte0]: 54
3353 12:20:30.620987 [Byte1]: 54
3354 12:20:30.625512
3355 12:20:30.625591 Set Vref, RX VrefLevel [Byte0]: 55
3356 12:20:30.629267 [Byte1]: 55
3357 12:20:30.633544
3358 12:20:30.633620 Set Vref, RX VrefLevel [Byte0]: 56
3359 12:20:30.636844 [Byte1]: 56
3360 12:20:30.641683
3361 12:20:30.641761 Set Vref, RX VrefLevel [Byte0]: 57
3362 12:20:30.644622 [Byte1]: 57
3363 12:20:30.649185
3364 12:20:30.649265 Set Vref, RX VrefLevel [Byte0]: 58
3365 12:20:30.652598 [Byte1]: 58
3366 12:20:30.657310
3367 12:20:30.657417 Set Vref, RX VrefLevel [Byte0]: 59
3368 12:20:30.660241 [Byte1]: 59
3369 12:20:30.664903
3370 12:20:30.665020 Set Vref, RX VrefLevel [Byte0]: 60
3371 12:20:30.668443 [Byte1]: 60
3372 12:20:30.672903
3373 12:20:30.672981 Set Vref, RX VrefLevel [Byte0]: 61
3374 12:20:30.676085 [Byte1]: 61
3375 12:20:30.680768
3376 12:20:30.680841 Set Vref, RX VrefLevel [Byte0]: 62
3377 12:20:30.684184 [Byte1]: 62
3378 12:20:30.688311
3379 12:20:30.688391 Set Vref, RX VrefLevel [Byte0]: 63
3380 12:20:30.692142 [Byte1]: 63
3381 12:20:30.696077
3382 12:20:30.696184 Set Vref, RX VrefLevel [Byte0]: 64
3383 12:20:30.699436 [Byte1]: 64
3384 12:20:30.704612
3385 12:20:30.704690 Set Vref, RX VrefLevel [Byte0]: 65
3386 12:20:30.707791 [Byte1]: 65
3387 12:20:30.712183
3388 12:20:30.712293 Set Vref, RX VrefLevel [Byte0]: 66
3389 12:20:30.715475 [Byte1]: 66
3390 12:20:30.719853
3391 12:20:30.719951 Set Vref, RX VrefLevel [Byte0]: 67
3392 12:20:30.723582 [Byte1]: 67
3393 12:20:30.728042
3394 12:20:30.728120 Set Vref, RX VrefLevel [Byte0]: 68
3395 12:20:30.731247 [Byte1]: 68
3396 12:20:30.735579
3397 12:20:30.735653 Set Vref, RX VrefLevel [Byte0]: 69
3398 12:20:30.738761 [Byte1]: 69
3399 12:20:30.743542
3400 12:20:30.743623 Final RX Vref Byte 0 = 54 to rank0
3401 12:20:30.747190 Final RX Vref Byte 1 = 48 to rank0
3402 12:20:30.750131 Final RX Vref Byte 0 = 54 to rank1
3403 12:20:30.753758 Final RX Vref Byte 1 = 48 to rank1==
3404 12:20:30.757113 Dram Type= 6, Freq= 0, CH_1, rank 0
3405 12:20:30.760212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3406 12:20:30.764015 ==
3407 12:20:30.764085 DQS Delay:
3408 12:20:30.764149 DQS0 = 0, DQS1 = 0
3409 12:20:30.767019 DQM Delay:
3410 12:20:30.767090 DQM0 = 120, DQM1 = 116
3411 12:20:30.770171 DQ Delay:
3412 12:20:30.773390 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3413 12:20:30.776994 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3414 12:20:30.780428 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3415 12:20:30.783738 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3416 12:20:30.783814
3417 12:20:30.783874
3418 12:20:30.790170 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3419 12:20:30.793612 CH1 RK0: MR19=404, MR18=114
3420 12:20:30.800260 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3421 12:20:30.800349
3422 12:20:30.803846 ----->DramcWriteLeveling(PI) begin...
3423 12:20:30.803918 ==
3424 12:20:30.806693 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 12:20:30.810213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3426 12:20:30.810282 ==
3427 12:20:30.813738 Write leveling (Byte 0): 26 => 26
3428 12:20:30.817263 Write leveling (Byte 1): 29 => 29
3429 12:20:30.820428 DramcWriteLeveling(PI) end<-----
3430 12:20:30.820498
3431 12:20:30.820558 ==
3432 12:20:30.823601 Dram Type= 6, Freq= 0, CH_1, rank 1
3433 12:20:30.827305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 12:20:30.830484 ==
3435 12:20:30.830558 [Gating] SW mode calibration
3436 12:20:30.839930 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3437 12:20:30.843757 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3438 12:20:30.846971 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3439 12:20:30.853739 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 12:20:30.856995 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 12:20:30.860051 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 12:20:30.867020 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 12:20:30.870324 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3444 12:20:30.873759 0 15 24 | B1->B0 | 2c2c 3333 | 1 1 | (1 0) (1 0)
3445 12:20:30.880123 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3446 12:20:30.883805 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 12:20:30.886800 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 12:20:30.893908 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 12:20:30.897161 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 12:20:30.900421 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 12:20:30.906945 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3452 12:20:30.910224 1 0 24 | B1->B0 | 4040 2727 | 0 0 | (1 1) (0 0)
3453 12:20:30.913414 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3454 12:20:30.919904 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 12:20:30.923436 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 12:20:30.926737 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 12:20:30.930255 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 12:20:30.936818 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 12:20:30.940581 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3460 12:20:30.944011 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3461 12:20:30.950035 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 12:20:30.953867 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 12:20:30.956951 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 12:20:30.963349 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 12:20:30.967154 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 12:20:30.970303 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 12:20:30.976516 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 12:20:30.980481 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 12:20:30.983584 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 12:20:30.989955 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 12:20:30.994608 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 12:20:30.996933 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 12:20:31.003209 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 12:20:31.006929 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 12:20:31.009919 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3476 12:20:31.016486 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3477 12:20:31.019927 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3478 12:20:31.023205 Total UI for P1: 0, mck2ui 16
3479 12:20:31.026541 best dqsien dly found for B1: ( 1, 3, 22)
3480 12:20:31.029911 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 12:20:31.033185 Total UI for P1: 0, mck2ui 16
3482 12:20:31.036532 best dqsien dly found for B0: ( 1, 3, 26)
3483 12:20:31.039269 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3484 12:20:31.043056 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3485 12:20:31.043131
3486 12:20:31.049398 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3487 12:20:31.052673 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3488 12:20:31.052754 [Gating] SW calibration Done
3489 12:20:31.055903 ==
3490 12:20:31.055981 Dram Type= 6, Freq= 0, CH_1, rank 1
3491 12:20:31.063035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 12:20:31.063123 ==
3493 12:20:31.063192 RX Vref Scan: 0
3494 12:20:31.063252
3495 12:20:31.066163 RX Vref 0 -> 0, step: 1
3496 12:20:31.066238
3497 12:20:31.069368 RX Delay -40 -> 252, step: 8
3498 12:20:31.072735 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3499 12:20:31.076426 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3500 12:20:31.079810 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3501 12:20:31.086118 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3502 12:20:31.089528 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3503 12:20:31.092641 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3504 12:20:31.096383 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3505 12:20:31.099563 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3506 12:20:31.106522 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3507 12:20:31.109440 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3508 12:20:31.112814 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3509 12:20:31.116481 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3510 12:20:31.119716 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3511 12:20:31.126422 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3512 12:20:31.129463 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3513 12:20:31.133155 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3514 12:20:31.133229 ==
3515 12:20:31.137065 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 12:20:31.139438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 12:20:31.139513 ==
3518 12:20:31.143297 DQS Delay:
3519 12:20:31.143372 DQS0 = 0, DQS1 = 0
3520 12:20:31.146213 DQM Delay:
3521 12:20:31.146284 DQM0 = 120, DQM1 = 118
3522 12:20:31.146368 DQ Delay:
3523 12:20:31.149462 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3524 12:20:31.156460 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3525 12:20:31.159639 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3526 12:20:31.162693 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =127
3527 12:20:31.162770
3528 12:20:31.162833
3529 12:20:31.162891 ==
3530 12:20:31.165841 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 12:20:31.169367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 12:20:31.169446 ==
3533 12:20:31.169510
3534 12:20:31.169619
3535 12:20:31.172992 TX Vref Scan disable
3536 12:20:31.176129 == TX Byte 0 ==
3537 12:20:31.179451 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3538 12:20:31.182686 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3539 12:20:31.186004 == TX Byte 1 ==
3540 12:20:31.189413 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3541 12:20:31.192574 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3542 12:20:31.192657 ==
3543 12:20:31.195801 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 12:20:31.198969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 12:20:31.202422 ==
3546 12:20:31.212879 TX Vref=22, minBit 9, minWin=24, winSum=419
3547 12:20:31.216186 TX Vref=24, minBit 1, minWin=26, winSum=424
3548 12:20:31.219356 TX Vref=26, minBit 2, minWin=26, winSum=433
3549 12:20:31.222381 TX Vref=28, minBit 2, minWin=26, winSum=433
3550 12:20:31.226050 TX Vref=30, minBit 9, minWin=26, winSum=434
3551 12:20:31.233000 TX Vref=32, minBit 9, minWin=26, winSum=434
3552 12:20:31.235660 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3553 12:20:31.235740
3554 12:20:31.239572 Final TX Range 1 Vref 30
3555 12:20:31.239649
3556 12:20:31.239710 ==
3557 12:20:31.242801 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 12:20:31.245798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 12:20:31.245882 ==
3560 12:20:31.249292
3561 12:20:31.249446
3562 12:20:31.249542 TX Vref Scan disable
3563 12:20:31.252397 == TX Byte 0 ==
3564 12:20:31.255779 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3565 12:20:31.262449 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3566 12:20:31.262546 == TX Byte 1 ==
3567 12:20:31.265622 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3568 12:20:31.272204 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3569 12:20:31.272362
3570 12:20:31.272477 [DATLAT]
3571 12:20:31.272537 Freq=1200, CH1 RK1
3572 12:20:31.272595
3573 12:20:31.275944 DATLAT Default: 0xd
3574 12:20:31.276054 0, 0xFFFF, sum = 0
3575 12:20:31.279178 1, 0xFFFF, sum = 0
3576 12:20:31.279252 2, 0xFFFF, sum = 0
3577 12:20:31.282205 3, 0xFFFF, sum = 0
3578 12:20:31.285422 4, 0xFFFF, sum = 0
3579 12:20:31.285500 5, 0xFFFF, sum = 0
3580 12:20:31.289128 6, 0xFFFF, sum = 0
3581 12:20:31.289204 7, 0xFFFF, sum = 0
3582 12:20:31.292711 8, 0xFFFF, sum = 0
3583 12:20:31.292786 9, 0xFFFF, sum = 0
3584 12:20:31.295851 10, 0xFFFF, sum = 0
3585 12:20:31.295926 11, 0xFFFF, sum = 0
3586 12:20:31.298730 12, 0x0, sum = 1
3587 12:20:31.298798 13, 0x0, sum = 2
3588 12:20:31.302500 14, 0x0, sum = 3
3589 12:20:31.302577 15, 0x0, sum = 4
3590 12:20:31.302639 best_step = 13
3591 12:20:31.305552
3592 12:20:31.305621 ==
3593 12:20:31.309136 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 12:20:31.311976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 12:20:31.312052 ==
3596 12:20:31.312111 RX Vref Scan: 0
3597 12:20:31.312167
3598 12:20:31.315416 RX Vref 0 -> 0, step: 1
3599 12:20:31.315485
3600 12:20:31.319095 RX Delay -5 -> 252, step: 4
3601 12:20:31.322435 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3602 12:20:31.328729 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3603 12:20:31.332329 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3604 12:20:31.335389 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3605 12:20:31.338576 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3606 12:20:31.341647 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3607 12:20:31.348654 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3608 12:20:31.351832 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3609 12:20:31.355558 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3610 12:20:31.358687 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3611 12:20:31.361640 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3612 12:20:31.368599 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3613 12:20:31.371725 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3614 12:20:31.374953 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3615 12:20:31.378326 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3616 12:20:31.381891 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3617 12:20:31.385061 ==
3618 12:20:31.388223 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 12:20:31.391895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 12:20:31.391974 ==
3621 12:20:31.392044 DQS Delay:
3622 12:20:31.395050 DQS0 = 0, DQS1 = 0
3623 12:20:31.395121 DQM Delay:
3624 12:20:31.398482 DQM0 = 120, DQM1 = 116
3625 12:20:31.398553 DQ Delay:
3626 12:20:31.401803 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3627 12:20:31.404916 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3628 12:20:31.408169 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3629 12:20:31.411939 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =124
3630 12:20:31.412015
3631 12:20:31.412077
3632 12:20:31.421811 [DQSOSCAuto] RK1, (LSB)MR18= 0x12ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3633 12:20:31.424862 CH1 RK1: MR19=403, MR18=12EE
3634 12:20:31.428312 CH1_RK1: MR19=0x403, MR18=0x12EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3635 12:20:31.431536 [RxdqsGatingPostProcess] freq 1200
3636 12:20:31.438383 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3637 12:20:31.441791 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 12:20:31.444655 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 12:20:31.447930 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 12:20:31.451613 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 12:20:31.454749 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 12:20:31.458593 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 12:20:31.461557 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 12:20:31.464868 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 12:20:31.467939 Pre-setting of DQS Precalculation
3646 12:20:31.471657 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3647 12:20:31.477806 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3648 12:20:31.484783 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3649 12:20:31.484873
3650 12:20:31.488225
3651 12:20:31.488360 [Calibration Summary] 2400 Mbps
3652 12:20:31.491079 CH 0, Rank 0
3653 12:20:31.491152 SW Impedance : PASS
3654 12:20:31.494701 DUTY Scan : NO K
3655 12:20:31.497748 ZQ Calibration : PASS
3656 12:20:31.497820 Jitter Meter : NO K
3657 12:20:31.501710 CBT Training : PASS
3658 12:20:31.504671 Write leveling : PASS
3659 12:20:31.504754 RX DQS gating : PASS
3660 12:20:31.507943 RX DQ/DQS(RDDQC) : PASS
3661 12:20:31.511671 TX DQ/DQS : PASS
3662 12:20:31.511751 RX DATLAT : PASS
3663 12:20:31.514889 RX DQ/DQS(Engine): PASS
3664 12:20:31.518112 TX OE : NO K
3665 12:20:31.518185 All Pass.
3666 12:20:31.518278
3667 12:20:31.518335 CH 0, Rank 1
3668 12:20:31.521304 SW Impedance : PASS
3669 12:20:31.521373 DUTY Scan : NO K
3670 12:20:31.524791 ZQ Calibration : PASS
3671 12:20:31.527710 Jitter Meter : NO K
3672 12:20:31.527815 CBT Training : PASS
3673 12:20:31.531247 Write leveling : PASS
3674 12:20:31.534432 RX DQS gating : PASS
3675 12:20:31.534505 RX DQ/DQS(RDDQC) : PASS
3676 12:20:31.537524 TX DQ/DQS : PASS
3677 12:20:31.541562 RX DATLAT : PASS
3678 12:20:31.541634 RX DQ/DQS(Engine): PASS
3679 12:20:31.544522 TX OE : NO K
3680 12:20:31.544595 All Pass.
3681 12:20:31.544687
3682 12:20:31.547539 CH 1, Rank 0
3683 12:20:31.547612 SW Impedance : PASS
3684 12:20:31.551526 DUTY Scan : NO K
3685 12:20:31.554230 ZQ Calibration : PASS
3686 12:20:31.554303 Jitter Meter : NO K
3687 12:20:31.558157 CBT Training : PASS
3688 12:20:31.560774 Write leveling : PASS
3689 12:20:31.560845 RX DQS gating : PASS
3690 12:20:31.564103 RX DQ/DQS(RDDQC) : PASS
3691 12:20:31.567356 TX DQ/DQS : PASS
3692 12:20:31.567442 RX DATLAT : PASS
3693 12:20:31.571084 RX DQ/DQS(Engine): PASS
3694 12:20:31.574205 TX OE : NO K
3695 12:20:31.574282 All Pass.
3696 12:20:31.574351
3697 12:20:31.574409 CH 1, Rank 1
3698 12:20:31.577752 SW Impedance : PASS
3699 12:20:31.580890 DUTY Scan : NO K
3700 12:20:31.580969 ZQ Calibration : PASS
3701 12:20:31.584587 Jitter Meter : NO K
3702 12:20:31.584664 CBT Training : PASS
3703 12:20:31.587836 Write leveling : PASS
3704 12:20:31.590860 RX DQS gating : PASS
3705 12:20:31.590941 RX DQ/DQS(RDDQC) : PASS
3706 12:20:31.594485 TX DQ/DQS : PASS
3707 12:20:31.597687 RX DATLAT : PASS
3708 12:20:31.597760 RX DQ/DQS(Engine): PASS
3709 12:20:31.600859 TX OE : NO K
3710 12:20:31.600934 All Pass.
3711 12:20:31.600994
3712 12:20:31.604197 DramC Write-DBI off
3713 12:20:31.607604 PER_BANK_REFRESH: Hybrid Mode
3714 12:20:31.607680 TX_TRACKING: ON
3715 12:20:31.617717 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3716 12:20:31.620889 [FAST_K] Save calibration result to emmc
3717 12:20:31.624228 dramc_set_vcore_voltage set vcore to 650000
3718 12:20:31.627208 Read voltage for 600, 5
3719 12:20:31.627294 Vio18 = 0
3720 12:20:31.627357 Vcore = 650000
3721 12:20:31.630806 Vdram = 0
3722 12:20:31.630877 Vddq = 0
3723 12:20:31.630937 Vmddr = 0
3724 12:20:31.637658 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3725 12:20:31.640608 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3726 12:20:31.643822 MEM_TYPE=3, freq_sel=19
3727 12:20:31.647505 sv_algorithm_assistance_LP4_1600
3728 12:20:31.650835 ============ PULL DRAM RESETB DOWN ============
3729 12:20:31.653841 ========== PULL DRAM RESETB DOWN end =========
3730 12:20:31.660800 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3731 12:20:31.663827 ===================================
3732 12:20:31.667059 LPDDR4 DRAM CONFIGURATION
3733 12:20:31.667134 ===================================
3734 12:20:31.671069 EX_ROW_EN[0] = 0x0
3735 12:20:31.673898 EX_ROW_EN[1] = 0x0
3736 12:20:31.673973 LP4Y_EN = 0x0
3737 12:20:31.677535 WORK_FSP = 0x0
3738 12:20:31.677609 WL = 0x2
3739 12:20:31.680229 RL = 0x2
3740 12:20:31.680337 BL = 0x2
3741 12:20:31.683728 RPST = 0x0
3742 12:20:31.683811 RD_PRE = 0x0
3743 12:20:31.686855 WR_PRE = 0x1
3744 12:20:31.686934 WR_PST = 0x0
3745 12:20:31.690189 DBI_WR = 0x0
3746 12:20:31.690259 DBI_RD = 0x0
3747 12:20:31.694196 OTF = 0x1
3748 12:20:31.697130 ===================================
3749 12:20:31.700540 ===================================
3750 12:20:31.700642 ANA top config
3751 12:20:31.703559 ===================================
3752 12:20:31.706859 DLL_ASYNC_EN = 0
3753 12:20:31.710307 ALL_SLAVE_EN = 1
3754 12:20:31.713321 NEW_RANK_MODE = 1
3755 12:20:31.713420 DLL_IDLE_MODE = 1
3756 12:20:31.716798 LP45_APHY_COMB_EN = 1
3757 12:20:31.720097 TX_ODT_DIS = 1
3758 12:20:31.723346 NEW_8X_MODE = 1
3759 12:20:31.727205 ===================================
3760 12:20:31.730352 ===================================
3761 12:20:31.734269 data_rate = 1200
3762 12:20:31.736897 CKR = 1
3763 12:20:31.736978 DQ_P2S_RATIO = 8
3764 12:20:31.740449 ===================================
3765 12:20:31.743480 CA_P2S_RATIO = 8
3766 12:20:31.746745 DQ_CA_OPEN = 0
3767 12:20:31.750010 DQ_SEMI_OPEN = 0
3768 12:20:31.753132 CA_SEMI_OPEN = 0
3769 12:20:31.753214 CA_FULL_RATE = 0
3770 12:20:31.756890 DQ_CKDIV4_EN = 1
3771 12:20:31.759726 CA_CKDIV4_EN = 1
3772 12:20:31.763369 CA_PREDIV_EN = 0
3773 12:20:31.766536 PH8_DLY = 0
3774 12:20:31.769865 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3775 12:20:31.769947 DQ_AAMCK_DIV = 4
3776 12:20:31.773318 CA_AAMCK_DIV = 4
3777 12:20:31.777096 CA_ADMCK_DIV = 4
3778 12:20:31.780139 DQ_TRACK_CA_EN = 0
3779 12:20:31.783395 CA_PICK = 600
3780 12:20:31.786798 CA_MCKIO = 600
3781 12:20:31.790241 MCKIO_SEMI = 0
3782 12:20:31.790323 PLL_FREQ = 2288
3783 12:20:31.793190 DQ_UI_PI_RATIO = 32
3784 12:20:31.796283 CA_UI_PI_RATIO = 0
3785 12:20:31.799957 ===================================
3786 12:20:31.803518 ===================================
3787 12:20:31.806247 memory_type:LPDDR4
3788 12:20:31.809987 GP_NUM : 10
3789 12:20:31.810068 SRAM_EN : 1
3790 12:20:31.813440 MD32_EN : 0
3791 12:20:31.816188 ===================================
3792 12:20:31.816320 [ANA_INIT] >>>>>>>>>>>>>>
3793 12:20:31.819891 <<<<<< [CONFIGURE PHASE]: ANA_TX
3794 12:20:31.822902 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3795 12:20:31.826243 ===================================
3796 12:20:31.829727 data_rate = 1200,PCW = 0X5800
3797 12:20:31.833077 ===================================
3798 12:20:31.836435 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3799 12:20:31.843007 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 12:20:31.846711 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3801 12:20:31.852741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3802 12:20:31.856036 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3803 12:20:31.860076 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3804 12:20:31.862895 [ANA_INIT] flow start
3805 12:20:31.862979 [ANA_INIT] PLL >>>>>>>>
3806 12:20:31.866459 [ANA_INIT] PLL <<<<<<<<
3807 12:20:31.869589 [ANA_INIT] MIDPI >>>>>>>>
3808 12:20:31.869673 [ANA_INIT] MIDPI <<<<<<<<
3809 12:20:31.873424 [ANA_INIT] DLL >>>>>>>>
3810 12:20:31.876052 [ANA_INIT] flow end
3811 12:20:31.880118 ============ LP4 DIFF to SE enter ============
3812 12:20:31.883020 ============ LP4 DIFF to SE exit ============
3813 12:20:31.886196 [ANA_INIT] <<<<<<<<<<<<<
3814 12:20:31.889452 [Flow] Enable top DCM control >>>>>
3815 12:20:31.892715 [Flow] Enable top DCM control <<<<<
3816 12:20:31.895896 Enable DLL master slave shuffle
3817 12:20:31.899763 ==============================================================
3818 12:20:31.902784 Gating Mode config
3819 12:20:31.909585 ==============================================================
3820 12:20:31.909674 Config description:
3821 12:20:31.919424 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3822 12:20:31.926088 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3823 12:20:31.929303 SELPH_MODE 0: By rank 1: By Phase
3824 12:20:31.936328 ==============================================================
3825 12:20:31.939802 GAT_TRACK_EN = 1
3826 12:20:31.942650 RX_GATING_MODE = 2
3827 12:20:31.946242 RX_GATING_TRACK_MODE = 2
3828 12:20:31.949621 SELPH_MODE = 1
3829 12:20:31.952747 PICG_EARLY_EN = 1
3830 12:20:31.952836 VALID_LAT_VALUE = 1
3831 12:20:31.959674 ==============================================================
3832 12:20:31.962644 Enter into Gating configuration >>>>
3833 12:20:31.965822 Exit from Gating configuration <<<<
3834 12:20:31.969599 Enter into DVFS_PRE_config >>>>>
3835 12:20:31.979702 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3836 12:20:31.982865 Exit from DVFS_PRE_config <<<<<
3837 12:20:31.986237 Enter into PICG configuration >>>>
3838 12:20:31.989873 Exit from PICG configuration <<<<
3839 12:20:31.992432 [RX_INPUT] configuration >>>>>
3840 12:20:31.995707 [RX_INPUT] configuration <<<<<
3841 12:20:32.002318 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3842 12:20:32.005587 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3843 12:20:32.012627 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3844 12:20:32.019275 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3845 12:20:32.025504 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3846 12:20:32.032766 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3847 12:20:32.035910 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3848 12:20:32.039017 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3849 12:20:32.042312 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3850 12:20:32.049501 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3851 12:20:32.052479 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3852 12:20:32.055554 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3853 12:20:32.059031 ===================================
3854 12:20:32.062602 LPDDR4 DRAM CONFIGURATION
3855 12:20:32.065743 ===================================
3856 12:20:32.065831 EX_ROW_EN[0] = 0x0
3857 12:20:32.069277 EX_ROW_EN[1] = 0x0
3858 12:20:32.069360 LP4Y_EN = 0x0
3859 12:20:32.072211 WORK_FSP = 0x0
3860 12:20:32.075850 WL = 0x2
3861 12:20:32.075934 RL = 0x2
3862 12:20:32.079015 BL = 0x2
3863 12:20:32.079111 RPST = 0x0
3864 12:20:32.082222 RD_PRE = 0x0
3865 12:20:32.082303 WR_PRE = 0x1
3866 12:20:32.085659 WR_PST = 0x0
3867 12:20:32.085742 DBI_WR = 0x0
3868 12:20:32.088814 DBI_RD = 0x0
3869 12:20:32.088896 OTF = 0x1
3870 12:20:32.092069 ===================================
3871 12:20:32.095733 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3872 12:20:32.102191 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3873 12:20:32.105226 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3874 12:20:32.109086 ===================================
3875 12:20:32.112179 LPDDR4 DRAM CONFIGURATION
3876 12:20:32.115346 ===================================
3877 12:20:32.115428 EX_ROW_EN[0] = 0x10
3878 12:20:32.118723 EX_ROW_EN[1] = 0x0
3879 12:20:32.118821 LP4Y_EN = 0x0
3880 12:20:32.121867 WORK_FSP = 0x0
3881 12:20:32.121948 WL = 0x2
3882 12:20:32.125545 RL = 0x2
3883 12:20:32.128443 BL = 0x2
3884 12:20:32.128533 RPST = 0x0
3885 12:20:32.132151 RD_PRE = 0x0
3886 12:20:32.132264 WR_PRE = 0x1
3887 12:20:32.135273 WR_PST = 0x0
3888 12:20:32.135356 DBI_WR = 0x0
3889 12:20:32.138660 DBI_RD = 0x0
3890 12:20:32.138745 OTF = 0x1
3891 12:20:32.141836 ===================================
3892 12:20:32.148580 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3893 12:20:32.152660 nWR fixed to 30
3894 12:20:32.155767 [ModeRegInit_LP4] CH0 RK0
3895 12:20:32.155872 [ModeRegInit_LP4] CH0 RK1
3896 12:20:32.159029 [ModeRegInit_LP4] CH1 RK0
3897 12:20:32.162293 [ModeRegInit_LP4] CH1 RK1
3898 12:20:32.162388 match AC timing 17
3899 12:20:32.169076 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3900 12:20:32.172469 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3901 12:20:32.175461 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3902 12:20:32.182544 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3903 12:20:32.185851 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3904 12:20:32.185937 ==
3905 12:20:32.189163 Dram Type= 6, Freq= 0, CH_0, rank 0
3906 12:20:32.192598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3907 12:20:32.192685 ==
3908 12:20:32.198775 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3909 12:20:32.205118 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3910 12:20:32.208609 [CA 0] Center 35 (5~66) winsize 62
3911 12:20:32.211962 [CA 1] Center 35 (5~66) winsize 62
3912 12:20:32.215282 [CA 2] Center 33 (3~64) winsize 62
3913 12:20:32.218444 [CA 3] Center 33 (2~64) winsize 63
3914 12:20:32.222407 [CA 4] Center 33 (2~64) winsize 63
3915 12:20:32.225417 [CA 5] Center 32 (2~63) winsize 62
3916 12:20:32.225515
3917 12:20:32.228547 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3918 12:20:32.228632
3919 12:20:32.231771 [CATrainingPosCal] consider 1 rank data
3920 12:20:32.235266 u2DelayCellTimex100 = 270/100 ps
3921 12:20:32.238708 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3922 12:20:32.241779 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3923 12:20:32.244888 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3924 12:20:32.248813 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3925 12:20:32.252086 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3926 12:20:32.258973 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3927 12:20:32.259059
3928 12:20:32.262066 CA PerBit enable=1, Macro0, CA PI delay=32
3929 12:20:32.262147
3930 12:20:32.265392 [CBTSetCACLKResult] CA Dly = 32
3931 12:20:32.265473 CS Dly: 4 (0~35)
3932 12:20:32.265550 ==
3933 12:20:32.268475 Dram Type= 6, Freq= 0, CH_0, rank 1
3934 12:20:32.271527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3935 12:20:32.275125 ==
3936 12:20:32.278146 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3937 12:20:32.284982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3938 12:20:32.288651 [CA 0] Center 35 (5~66) winsize 62
3939 12:20:32.291772 [CA 1] Center 35 (5~66) winsize 62
3940 12:20:32.294902 [CA 2] Center 34 (3~65) winsize 63
3941 12:20:32.297821 [CA 3] Center 33 (3~64) winsize 62
3942 12:20:32.301722 [CA 4] Center 32 (2~63) winsize 62
3943 12:20:32.304882 [CA 5] Center 32 (2~63) winsize 62
3944 12:20:32.304964
3945 12:20:32.308187 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3946 12:20:32.308318
3947 12:20:32.311740 [CATrainingPosCal] consider 2 rank data
3948 12:20:32.314871 u2DelayCellTimex100 = 270/100 ps
3949 12:20:32.318370 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3950 12:20:32.321548 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3951 12:20:32.324981 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3952 12:20:32.328352 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3953 12:20:32.335048 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3954 12:20:32.338333 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3955 12:20:32.338419
3956 12:20:32.341428 CA PerBit enable=1, Macro0, CA PI delay=32
3957 12:20:32.341499
3958 12:20:32.344834 [CBTSetCACLKResult] CA Dly = 32
3959 12:20:32.344906 CS Dly: 4 (0~36)
3960 12:20:32.345047
3961 12:20:32.348060 ----->DramcWriteLeveling(PI) begin...
3962 12:20:32.348128 ==
3963 12:20:32.351489 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 12:20:32.358172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 12:20:32.358252 ==
3966 12:20:32.361790 Write leveling (Byte 0): 35 => 35
3967 12:20:32.361869 Write leveling (Byte 1): 31 => 31
3968 12:20:32.365114 DramcWriteLeveling(PI) end<-----
3969 12:20:32.365201
3970 12:20:32.368122 ==
3971 12:20:32.368197 Dram Type= 6, Freq= 0, CH_0, rank 0
3972 12:20:32.374585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3973 12:20:32.374668 ==
3974 12:20:32.378142 [Gating] SW mode calibration
3975 12:20:32.384494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3976 12:20:32.388272 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3977 12:20:32.394816 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 12:20:32.398027 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 12:20:32.401249 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 12:20:32.408173 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
3981 12:20:32.411395 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
3982 12:20:32.414804 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 12:20:32.421025 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 12:20:32.424919 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 12:20:32.427816 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 12:20:32.434442 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 12:20:32.438160 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 12:20:32.441042 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
3989 12:20:32.447612 0 10 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
3990 12:20:32.451007 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 12:20:32.454148 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 12:20:32.460603 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 12:20:32.464250 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 12:20:32.467529 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 12:20:32.473763 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 12:20:32.477749 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3997 12:20:32.480745 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3998 12:20:32.484527 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 12:20:32.490706 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 12:20:32.493783 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 12:20:32.497627 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 12:20:32.504063 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 12:20:32.507375 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 12:20:32.510357 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 12:20:32.517214 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 12:20:32.520379 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 12:20:32.524338 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 12:20:32.530623 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 12:20:32.533934 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 12:20:32.537168 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 12:20:32.544550 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 12:20:32.547204 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4013 12:20:32.550322 Total UI for P1: 0, mck2ui 16
4014 12:20:32.553715 best dqsien dly found for B0: ( 0, 13, 10)
4015 12:20:32.556972 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 12:20:32.560617 Total UI for P1: 0, mck2ui 16
4017 12:20:32.563673 best dqsien dly found for B1: ( 0, 13, 14)
4018 12:20:32.567315 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4019 12:20:32.570192 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4020 12:20:32.570271
4021 12:20:32.577210 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4022 12:20:32.580376 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4023 12:20:32.583491 [Gating] SW calibration Done
4024 12:20:32.583569 ==
4025 12:20:32.587433 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 12:20:32.590255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 12:20:32.590352 ==
4028 12:20:32.590448 RX Vref Scan: 0
4029 12:20:32.590534
4030 12:20:32.593868 RX Vref 0 -> 0, step: 1
4031 12:20:32.593940
4032 12:20:32.597353 RX Delay -230 -> 252, step: 16
4033 12:20:32.600356 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4034 12:20:32.603554 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4035 12:20:32.610293 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4036 12:20:32.613737 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4037 12:20:32.616926 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4038 12:20:32.620191 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4039 12:20:32.626591 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4040 12:20:32.630497 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4041 12:20:32.633464 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4042 12:20:32.636794 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4043 12:20:32.640045 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4044 12:20:32.647125 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4045 12:20:32.650417 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4046 12:20:32.653598 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4047 12:20:32.656871 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4048 12:20:32.663175 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4049 12:20:32.663249 ==
4050 12:20:32.666769 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 12:20:32.670173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 12:20:32.670248 ==
4053 12:20:32.670309 DQS Delay:
4054 12:20:32.673258 DQS0 = 0, DQS1 = 0
4055 12:20:32.673327 DQM Delay:
4056 12:20:32.676778 DQM0 = 53, DQM1 = 45
4057 12:20:32.676851 DQ Delay:
4058 12:20:32.680109 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4059 12:20:32.683049 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4060 12:20:32.686507 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4061 12:20:32.690074 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4062 12:20:32.690143
4063 12:20:32.690203
4064 12:20:32.690260 ==
4065 12:20:32.693081 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 12:20:32.696553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 12:20:32.699894 ==
4068 12:20:32.699965
4069 12:20:32.700031
4070 12:20:32.700089 TX Vref Scan disable
4071 12:20:32.702978 == TX Byte 0 ==
4072 12:20:32.706384 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4073 12:20:32.712996 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4074 12:20:32.713073 == TX Byte 1 ==
4075 12:20:32.716597 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4076 12:20:32.722838 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4077 12:20:32.722936 ==
4078 12:20:32.726097 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 12:20:32.729779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 12:20:32.729871 ==
4081 12:20:32.729935
4082 12:20:32.729994
4083 12:20:32.732845 TX Vref Scan disable
4084 12:20:32.736377 == TX Byte 0 ==
4085 12:20:32.739637 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4086 12:20:32.742842 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4087 12:20:32.746185 == TX Byte 1 ==
4088 12:20:32.749943 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4089 12:20:32.753098 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4090 12:20:32.753178
4091 12:20:32.753240 [DATLAT]
4092 12:20:32.756120 Freq=600, CH0 RK0
4093 12:20:32.756228
4094 12:20:32.756337 DATLAT Default: 0x9
4095 12:20:32.759317 0, 0xFFFF, sum = 0
4096 12:20:32.763194 1, 0xFFFF, sum = 0
4097 12:20:32.763275 2, 0xFFFF, sum = 0
4098 12:20:32.765820 3, 0xFFFF, sum = 0
4099 12:20:32.765902 4, 0xFFFF, sum = 0
4100 12:20:32.769600 5, 0xFFFF, sum = 0
4101 12:20:32.769696 6, 0xFFFF, sum = 0
4102 12:20:32.772760 7, 0xFFFF, sum = 0
4103 12:20:32.772841 8, 0x0, sum = 1
4104 12:20:32.776407 9, 0x0, sum = 2
4105 12:20:32.776489 10, 0x0, sum = 3
4106 12:20:32.776552 11, 0x0, sum = 4
4107 12:20:32.779777 best_step = 9
4108 12:20:32.779857
4109 12:20:32.779935 ==
4110 12:20:32.782644 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 12:20:32.786095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 12:20:32.786175 ==
4113 12:20:32.789176 RX Vref Scan: 1
4114 12:20:32.789301
4115 12:20:32.789368 RX Vref 0 -> 0, step: 1
4116 12:20:32.789427
4117 12:20:32.792959 RX Delay -163 -> 252, step: 8
4118 12:20:32.793039
4119 12:20:32.796499 Set Vref, RX VrefLevel [Byte0]: 55
4120 12:20:32.799470 [Byte1]: 50
4121 12:20:32.803359
4122 12:20:32.803441 Final RX Vref Byte 0 = 55 to rank0
4123 12:20:32.806613 Final RX Vref Byte 1 = 50 to rank0
4124 12:20:32.810366 Final RX Vref Byte 0 = 55 to rank1
4125 12:20:32.813617 Final RX Vref Byte 1 = 50 to rank1==
4126 12:20:32.816781 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 12:20:32.823465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 12:20:32.823547 ==
4129 12:20:32.823610 DQS Delay:
4130 12:20:32.823682 DQS0 = 0, DQS1 = 0
4131 12:20:32.826905 DQM Delay:
4132 12:20:32.826999 DQM0 = 53, DQM1 = 46
4133 12:20:32.830206 DQ Delay:
4134 12:20:32.833526 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4135 12:20:32.836744 DQ4 =52, DQ5 =44, DQ6 =64, DQ7 =60
4136 12:20:32.839681 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4137 12:20:32.843362 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4138 12:20:32.843449
4139 12:20:32.843512
4140 12:20:32.849849 [DQSOSCAuto] RK0, (LSB)MR18= 0x7164, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4141 12:20:32.853253 CH0 RK0: MR19=808, MR18=7164
4142 12:20:32.859531 CH0_RK0: MR19=0x808, MR18=0x7164, DQSOSC=388, MR23=63, INC=174, DEC=116
4143 12:20:32.859613
4144 12:20:32.863486 ----->DramcWriteLeveling(PI) begin...
4145 12:20:32.863568 ==
4146 12:20:32.866190 Dram Type= 6, Freq= 0, CH_0, rank 1
4147 12:20:32.869883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 12:20:32.869965 ==
4149 12:20:32.873136 Write leveling (Byte 0): 36 => 36
4150 12:20:32.876192 Write leveling (Byte 1): 32 => 32
4151 12:20:32.879806 DramcWriteLeveling(PI) end<-----
4152 12:20:32.879886
4153 12:20:32.879950 ==
4154 12:20:32.883033 Dram Type= 6, Freq= 0, CH_0, rank 1
4155 12:20:32.886342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 12:20:32.886423 ==
4157 12:20:32.889796 [Gating] SW mode calibration
4158 12:20:32.896272 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4159 12:20:32.902420 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4160 12:20:32.905968 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 12:20:32.912521 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 12:20:32.916081 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4163 12:20:32.919528 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
4164 12:20:32.925769 0 9 16 | B1->B0 | 2e2e 2c2c | 0 0 | (0 1) (0 0)
4165 12:20:32.929130 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 12:20:32.932435 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 12:20:32.939317 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 12:20:32.942722 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 12:20:32.946057 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 12:20:32.952525 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 12:20:32.955937 0 10 12 | B1->B0 | 2727 2929 | 0 0 | (0 0) (0 0)
4172 12:20:32.959224 0 10 16 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
4173 12:20:32.962452 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 12:20:32.969043 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 12:20:32.972782 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 12:20:32.975750 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 12:20:32.982699 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 12:20:32.985844 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 12:20:32.989001 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4180 12:20:32.995892 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 12:20:32.999230 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 12:20:33.002296 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 12:20:33.009182 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 12:20:33.012713 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 12:20:33.015734 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 12:20:33.022197 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 12:20:33.025797 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 12:20:33.028771 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 12:20:33.035671 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 12:20:33.038989 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 12:20:33.042215 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 12:20:33.049136 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 12:20:33.052206 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 12:20:33.055850 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 12:20:33.062439 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4196 12:20:33.066166 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 12:20:33.069034 Total UI for P1: 0, mck2ui 16
4198 12:20:33.072307 best dqsien dly found for B0: ( 0, 13, 12)
4199 12:20:33.075974 Total UI for P1: 0, mck2ui 16
4200 12:20:33.079325 best dqsien dly found for B1: ( 0, 13, 14)
4201 12:20:33.082876 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4202 12:20:33.085522 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4203 12:20:33.085603
4204 12:20:33.089085 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4205 12:20:33.092896 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4206 12:20:33.095911 [Gating] SW calibration Done
4207 12:20:33.096019 ==
4208 12:20:33.099107 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 12:20:33.102044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 12:20:33.102125 ==
4211 12:20:33.105608 RX Vref Scan: 0
4212 12:20:33.105732
4213 12:20:33.109237 RX Vref 0 -> 0, step: 1
4214 12:20:33.109317
4215 12:20:33.109380 RX Delay -230 -> 252, step: 16
4216 12:20:33.115461 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4217 12:20:33.119075 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4218 12:20:33.122275 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4219 12:20:33.125261 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4220 12:20:33.132511 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4221 12:20:33.135434 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4222 12:20:33.139049 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4223 12:20:33.142571 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4224 12:20:33.145635 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4225 12:20:33.148800 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4226 12:20:33.155805 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4227 12:20:33.158991 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4228 12:20:33.162198 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4229 12:20:33.165473 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4230 12:20:33.172433 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4231 12:20:33.175454 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4232 12:20:33.175541 ==
4233 12:20:33.179078 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 12:20:33.182097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 12:20:33.182183 ==
4236 12:20:33.185620 DQS Delay:
4237 12:20:33.185702 DQS0 = 0, DQS1 = 0
4238 12:20:33.185774 DQM Delay:
4239 12:20:33.188585 DQM0 = 57, DQM1 = 46
4240 12:20:33.188667 DQ Delay:
4241 12:20:33.192092 DQ0 =57, DQ1 =57, DQ2 =49, DQ3 =49
4242 12:20:33.195726 DQ4 =65, DQ5 =49, DQ6 =65, DQ7 =65
4243 12:20:33.198648 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4244 12:20:33.202190 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =49
4245 12:20:33.202280
4246 12:20:33.202346
4247 12:20:33.202406 ==
4248 12:20:33.205299 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 12:20:33.212407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 12:20:33.212501 ==
4251 12:20:33.212567
4252 12:20:33.212627
4253 12:20:33.212685 TX Vref Scan disable
4254 12:20:33.216059 == TX Byte 0 ==
4255 12:20:33.219242 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4256 12:20:33.225963 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4257 12:20:33.226082 == TX Byte 1 ==
4258 12:20:33.229059 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4259 12:20:33.235343 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4260 12:20:33.235445 ==
4261 12:20:33.239001 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 12:20:33.242226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 12:20:33.242347 ==
4264 12:20:33.242448
4265 12:20:33.242563
4266 12:20:33.245403 TX Vref Scan disable
4267 12:20:33.248878 == TX Byte 0 ==
4268 12:20:33.252176 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4269 12:20:33.255295 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4270 12:20:33.259108 == TX Byte 1 ==
4271 12:20:33.262284 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4272 12:20:33.265552 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4273 12:20:33.265686
4274 12:20:33.265805 [DATLAT]
4275 12:20:33.268641 Freq=600, CH0 RK1
4276 12:20:33.268723
4277 12:20:33.271874 DATLAT Default: 0x9
4278 12:20:33.271955 0, 0xFFFF, sum = 0
4279 12:20:33.275780 1, 0xFFFF, sum = 0
4280 12:20:33.275895 2, 0xFFFF, sum = 0
4281 12:20:33.278552 3, 0xFFFF, sum = 0
4282 12:20:33.278637 4, 0xFFFF, sum = 0
4283 12:20:33.281866 5, 0xFFFF, sum = 0
4284 12:20:33.281951 6, 0xFFFF, sum = 0
4285 12:20:33.285745 7, 0xFFFF, sum = 0
4286 12:20:33.285843 8, 0x0, sum = 1
4287 12:20:33.288940 9, 0x0, sum = 2
4288 12:20:33.289028 10, 0x0, sum = 3
4289 12:20:33.289095 11, 0x0, sum = 4
4290 12:20:33.292119 best_step = 9
4291 12:20:33.292231
4292 12:20:33.292331 ==
4293 12:20:33.295114 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 12:20:33.298605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 12:20:33.298690 ==
4296 12:20:33.301861 RX Vref Scan: 0
4297 12:20:33.301965
4298 12:20:33.305537 RX Vref 0 -> 0, step: 1
4299 12:20:33.305650
4300 12:20:33.305743 RX Delay -163 -> 252, step: 8
4301 12:20:33.312565 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4302 12:20:33.316251 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4303 12:20:33.319422 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4304 12:20:33.322539 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4305 12:20:33.326147 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4306 12:20:33.332627 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4307 12:20:33.336067 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4308 12:20:33.339296 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4309 12:20:33.342500 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4310 12:20:33.346329 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4311 12:20:33.352689 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4312 12:20:33.356218 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4313 12:20:33.359117 iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280
4314 12:20:33.362522 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4315 12:20:33.369605 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4316 12:20:33.372819 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4317 12:20:33.372897 ==
4318 12:20:33.375998 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 12:20:33.379849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 12:20:33.379948 ==
4321 12:20:33.380049 DQS Delay:
4322 12:20:33.383092 DQS0 = 0, DQS1 = 0
4323 12:20:33.383162 DQM Delay:
4324 12:20:33.386204 DQM0 = 53, DQM1 = 46
4325 12:20:33.386274 DQ Delay:
4326 12:20:33.389434 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4327 12:20:33.393154 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =56
4328 12:20:33.395897 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4329 12:20:33.399330 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4330 12:20:33.399414
4331 12:20:33.399478
4332 12:20:33.409861 [DQSOSCAuto] RK1, (LSB)MR18= 0x6123, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4333 12:20:33.409950 CH0 RK1: MR19=808, MR18=6123
4334 12:20:33.415769 CH0_RK1: MR19=0x808, MR18=0x6123, DQSOSC=391, MR23=63, INC=171, DEC=114
4335 12:20:33.419232 [RxdqsGatingPostProcess] freq 600
4336 12:20:33.425917 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4337 12:20:33.429591 Pre-setting of DQS Precalculation
4338 12:20:33.433283 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4339 12:20:33.433369 ==
4340 12:20:33.436192 Dram Type= 6, Freq= 0, CH_1, rank 0
4341 12:20:33.439457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 12:20:33.439540 ==
4343 12:20:33.446215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4344 12:20:33.452389 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4345 12:20:33.455734 [CA 0] Center 36 (5~67) winsize 63
4346 12:20:33.459700 [CA 1] Center 36 (6~67) winsize 62
4347 12:20:33.462779 [CA 2] Center 35 (4~66) winsize 63
4348 12:20:33.466103 [CA 3] Center 34 (4~65) winsize 62
4349 12:20:33.469088 [CA 4] Center 34 (4~65) winsize 62
4350 12:20:33.472863 [CA 5] Center 34 (4~65) winsize 62
4351 12:20:33.472962
4352 12:20:33.476010 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4353 12:20:33.476091
4354 12:20:33.479174 [CATrainingPosCal] consider 1 rank data
4355 12:20:33.482350 u2DelayCellTimex100 = 270/100 ps
4356 12:20:33.486180 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4357 12:20:33.489343 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4358 12:20:33.492541 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4359 12:20:33.495573 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4360 12:20:33.502350 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4361 12:20:33.505795 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4362 12:20:33.505896
4363 12:20:33.509589 CA PerBit enable=1, Macro0, CA PI delay=34
4364 12:20:33.509669
4365 12:20:33.512189 [CBTSetCACLKResult] CA Dly = 34
4366 12:20:33.512272 CS Dly: 4 (0~35)
4367 12:20:33.512373 ==
4368 12:20:33.515937 Dram Type= 6, Freq= 0, CH_1, rank 1
4369 12:20:33.522129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 12:20:33.522228 ==
4371 12:20:33.525573 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4372 12:20:33.532447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4373 12:20:33.535703 [CA 0] Center 36 (6~67) winsize 62
4374 12:20:33.538768 [CA 1] Center 36 (6~67) winsize 62
4375 12:20:33.542045 [CA 2] Center 35 (4~66) winsize 63
4376 12:20:33.545630 [CA 3] Center 35 (4~66) winsize 63
4377 12:20:33.548890 [CA 4] Center 34 (4~65) winsize 62
4378 12:20:33.552132 [CA 5] Center 34 (4~65) winsize 62
4379 12:20:33.552250
4380 12:20:33.555664 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4381 12:20:33.555740
4382 12:20:33.559145 [CATrainingPosCal] consider 2 rank data
4383 12:20:33.562202 u2DelayCellTimex100 = 270/100 ps
4384 12:20:33.565638 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4385 12:20:33.569070 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4386 12:20:33.572227 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4387 12:20:33.578690 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4388 12:20:33.582517 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4389 12:20:33.585774 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4390 12:20:33.585849
4391 12:20:33.588910 CA PerBit enable=1, Macro0, CA PI delay=34
4392 12:20:33.588987
4393 12:20:33.592172 [CBTSetCACLKResult] CA Dly = 34
4394 12:20:33.592292 CS Dly: 5 (0~38)
4395 12:20:33.592397
4396 12:20:33.595717 ----->DramcWriteLeveling(PI) begin...
4397 12:20:33.595818 ==
4398 12:20:33.598934 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 12:20:33.605094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 12:20:33.605170 ==
4401 12:20:33.608643 Write leveling (Byte 0): 28 => 28
4402 12:20:33.612527 Write leveling (Byte 1): 28 => 28
4403 12:20:33.615085 DramcWriteLeveling(PI) end<-----
4404 12:20:33.615173
4405 12:20:33.615262 ==
4406 12:20:33.618423 Dram Type= 6, Freq= 0, CH_1, rank 0
4407 12:20:33.622384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 12:20:33.622459 ==
4409 12:20:33.625597 [Gating] SW mode calibration
4410 12:20:33.631745 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4411 12:20:33.635321 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4412 12:20:33.642141 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4413 12:20:33.645596 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 12:20:33.649029 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4415 12:20:33.655151 0 9 12 | B1->B0 | 3030 2727 | 0 0 | (0 1) (0 0)
4416 12:20:33.658890 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 12:20:33.662287 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 12:20:33.668194 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 12:20:33.671819 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 12:20:33.675142 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 12:20:33.681921 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 12:20:33.684975 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4423 12:20:33.688751 0 10 12 | B1->B0 | 3333 3f3f | 1 0 | (0 0) (0 0)
4424 12:20:33.695132 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 12:20:33.698495 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 12:20:33.702340 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 12:20:33.708521 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 12:20:33.711734 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 12:20:33.715283 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 12:20:33.722164 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 12:20:33.725510 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4432 12:20:33.728635 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 12:20:33.731846 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 12:20:33.738985 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 12:20:33.742075 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 12:20:33.745272 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 12:20:33.752142 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 12:20:33.755577 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 12:20:33.758547 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 12:20:33.765045 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 12:20:33.768195 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 12:20:33.771550 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 12:20:33.778704 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 12:20:33.781815 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 12:20:33.784955 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 12:20:33.791831 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 12:20:33.794928 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4448 12:20:33.798079 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 12:20:33.801459 Total UI for P1: 0, mck2ui 16
4450 12:20:33.804836 best dqsien dly found for B0: ( 0, 13, 12)
4451 12:20:33.808218 Total UI for P1: 0, mck2ui 16
4452 12:20:33.811275 best dqsien dly found for B1: ( 0, 13, 12)
4453 12:20:33.815035 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4454 12:20:33.818255 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4455 12:20:33.818352
4456 12:20:33.824634 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4457 12:20:33.828270 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4458 12:20:33.828399 [Gating] SW calibration Done
4459 12:20:33.831387 ==
4460 12:20:33.834604 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 12:20:33.837849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 12:20:33.837947 ==
4463 12:20:33.838038 RX Vref Scan: 0
4464 12:20:33.838125
4465 12:20:33.841112 RX Vref 0 -> 0, step: 1
4466 12:20:33.841206
4467 12:20:33.845029 RX Delay -230 -> 252, step: 16
4468 12:20:33.848096 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4469 12:20:33.851633 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4470 12:20:33.858102 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4471 12:20:33.861054 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4472 12:20:33.864782 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4473 12:20:33.867857 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4474 12:20:33.871388 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4475 12:20:33.877544 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4476 12:20:33.881278 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4477 12:20:33.884241 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4478 12:20:33.888004 iDelay=218, Bit 10, Center 57 (-86 ~ 201) 288
4479 12:20:33.894218 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4480 12:20:33.898036 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4481 12:20:33.901215 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4482 12:20:33.904477 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4483 12:20:33.907664 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4484 12:20:33.910866 ==
4485 12:20:33.914413 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 12:20:33.917723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 12:20:33.917804 ==
4488 12:20:33.917868 DQS Delay:
4489 12:20:33.920680 DQS0 = 0, DQS1 = 0
4490 12:20:33.920761 DQM Delay:
4491 12:20:33.924430 DQM0 = 55, DQM1 = 54
4492 12:20:33.924511 DQ Delay:
4493 12:20:33.927385 DQ0 =65, DQ1 =49, DQ2 =49, DQ3 =49
4494 12:20:33.930780 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4495 12:20:33.934788 DQ8 =41, DQ9 =41, DQ10 =57, DQ11 =49
4496 12:20:33.937657 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4497 12:20:33.937739
4498 12:20:33.937802
4499 12:20:33.937860 ==
4500 12:20:33.941010 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 12:20:33.944407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 12:20:33.944489 ==
4503 12:20:33.944552
4504 12:20:33.944611
4505 12:20:33.947653 TX Vref Scan disable
4506 12:20:33.951178 == TX Byte 0 ==
4507 12:20:33.954603 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4508 12:20:33.957884 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4509 12:20:33.961075 == TX Byte 1 ==
4510 12:20:33.964189 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4511 12:20:33.967871 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4512 12:20:33.967952 ==
4513 12:20:33.970816 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 12:20:33.974553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 12:20:33.977685 ==
4516 12:20:33.977762
4517 12:20:33.977828
4518 12:20:33.977889 TX Vref Scan disable
4519 12:20:33.981642 == TX Byte 0 ==
4520 12:20:33.984811 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4521 12:20:33.991512 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4522 12:20:33.991588 == TX Byte 1 ==
4523 12:20:33.994587 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4524 12:20:34.001246 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4525 12:20:34.001371
4526 12:20:34.001462 [DATLAT]
4527 12:20:34.001549 Freq=600, CH1 RK0
4528 12:20:34.001615
4529 12:20:34.004761 DATLAT Default: 0x9
4530 12:20:34.004830 0, 0xFFFF, sum = 0
4531 12:20:34.008206 1, 0xFFFF, sum = 0
4532 12:20:34.008344 2, 0xFFFF, sum = 0
4533 12:20:34.011411 3, 0xFFFF, sum = 0
4534 12:20:34.014552 4, 0xFFFF, sum = 0
4535 12:20:34.014651 5, 0xFFFF, sum = 0
4536 12:20:34.018410 6, 0xFFFF, sum = 0
4537 12:20:34.018509 7, 0xFFFF, sum = 0
4538 12:20:34.021613 8, 0x0, sum = 1
4539 12:20:34.021693 9, 0x0, sum = 2
4540 12:20:34.021782 10, 0x0, sum = 3
4541 12:20:34.024516 11, 0x0, sum = 4
4542 12:20:34.024613 best_step = 9
4543 12:20:34.024699
4544 12:20:34.024782 ==
4545 12:20:34.027921 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 12:20:34.034782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 12:20:34.034891 ==
4548 12:20:34.034985 RX Vref Scan: 1
4549 12:20:34.035073
4550 12:20:34.037959 RX Vref 0 -> 0, step: 1
4551 12:20:34.038052
4552 12:20:34.041235 RX Delay -147 -> 252, step: 8
4553 12:20:34.041331
4554 12:20:34.044916 Set Vref, RX VrefLevel [Byte0]: 54
4555 12:20:34.048383 [Byte1]: 48
4556 12:20:34.048454
4557 12:20:34.051128 Final RX Vref Byte 0 = 54 to rank0
4558 12:20:34.054418 Final RX Vref Byte 1 = 48 to rank0
4559 12:20:34.057951 Final RX Vref Byte 0 = 54 to rank1
4560 12:20:34.061296 Final RX Vref Byte 1 = 48 to rank1==
4561 12:20:34.065433 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 12:20:34.068474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 12:20:34.068576 ==
4564 12:20:34.071415 DQS Delay:
4565 12:20:34.071519 DQS0 = 0, DQS1 = 0
4566 12:20:34.071611 DQM Delay:
4567 12:20:34.074527 DQM0 = 48, DQM1 = 45
4568 12:20:34.074624 DQ Delay:
4569 12:20:34.078168 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4570 12:20:34.081368 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4571 12:20:34.084807 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4572 12:20:34.087838 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4573 12:20:34.087979
4574 12:20:34.088041
4575 12:20:34.098162 [DQSOSCAuto] RK0, (LSB)MR18= 0x466d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4576 12:20:34.098247 CH1 RK0: MR19=808, MR18=466D
4577 12:20:34.104507 CH1_RK0: MR19=0x808, MR18=0x466D, DQSOSC=389, MR23=63, INC=173, DEC=115
4578 12:20:34.104589
4579 12:20:34.108055 ----->DramcWriteLeveling(PI) begin...
4580 12:20:34.110865 ==
4581 12:20:34.114265 Dram Type= 6, Freq= 0, CH_1, rank 1
4582 12:20:34.117719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 12:20:34.117814 ==
4584 12:20:34.121209 Write leveling (Byte 0): 31 => 31
4585 12:20:34.124293 Write leveling (Byte 1): 29 => 29
4586 12:20:34.127703 DramcWriteLeveling(PI) end<-----
4587 12:20:34.127800
4588 12:20:34.127892 ==
4589 12:20:34.131394 Dram Type= 6, Freq= 0, CH_1, rank 1
4590 12:20:34.134565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 12:20:34.134648 ==
4592 12:20:34.138038 [Gating] SW mode calibration
4593 12:20:34.144526 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4594 12:20:34.147932 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4595 12:20:34.154575 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4596 12:20:34.157737 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 12:20:34.161469 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4598 12:20:34.167625 0 9 12 | B1->B0 | 2e2e 2f2f | 0 0 | (1 1) (0 0)
4599 12:20:34.170910 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 12:20:34.174231 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 12:20:34.181689 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 12:20:34.184951 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 12:20:34.188037 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 12:20:34.194750 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 12:20:34.197883 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
4606 12:20:34.201187 0 10 12 | B1->B0 | 3939 3737 | 1 1 | (0 0) (0 0)
4607 12:20:34.207495 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4608 12:20:34.211224 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 12:20:34.214461 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 12:20:34.221218 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 12:20:34.224077 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 12:20:34.227265 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 12:20:34.234565 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 12:20:34.238301 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4615 12:20:34.240929 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 12:20:34.247296 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 12:20:34.250895 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 12:20:34.254636 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 12:20:34.260782 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 12:20:34.264106 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 12:20:34.267241 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 12:20:34.271192 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 12:20:34.277753 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 12:20:34.280806 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 12:20:34.283848 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 12:20:34.290626 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 12:20:34.294251 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 12:20:34.297139 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 12:20:34.303895 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 12:20:34.308206 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4631 12:20:34.311167 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 12:20:34.314325 Total UI for P1: 0, mck2ui 16
4633 12:20:34.317570 best dqsien dly found for B0: ( 0, 13, 12)
4634 12:20:34.320689 Total UI for P1: 0, mck2ui 16
4635 12:20:34.324251 best dqsien dly found for B1: ( 0, 13, 14)
4636 12:20:34.327491 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4637 12:20:34.330540 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4638 12:20:34.330639
4639 12:20:34.337379 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4640 12:20:34.340667 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4641 12:20:34.343768 [Gating] SW calibration Done
4642 12:20:34.343850 ==
4643 12:20:34.347972 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 12:20:34.350422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 12:20:34.350504 ==
4646 12:20:34.350567 RX Vref Scan: 0
4647 12:20:34.350626
4648 12:20:34.354450 RX Vref 0 -> 0, step: 1
4649 12:20:34.354532
4650 12:20:34.357627 RX Delay -230 -> 252, step: 16
4651 12:20:34.361004 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4652 12:20:34.364131 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4653 12:20:34.370529 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4654 12:20:34.374179 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4655 12:20:34.377320 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4656 12:20:34.381275 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4657 12:20:34.384079 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4658 12:20:34.390852 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4659 12:20:34.394210 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4660 12:20:34.397486 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4661 12:20:34.400634 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4662 12:20:34.407549 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4663 12:20:34.410716 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4664 12:20:34.413676 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4665 12:20:34.417634 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4666 12:20:34.424221 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4667 12:20:34.424350 ==
4668 12:20:34.427299 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 12:20:34.430428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 12:20:34.430551 ==
4671 12:20:34.430648 DQS Delay:
4672 12:20:34.433962 DQS0 = 0, DQS1 = 0
4673 12:20:34.434061 DQM Delay:
4674 12:20:34.437123 DQM0 = 50, DQM1 = 46
4675 12:20:34.437219 DQ Delay:
4676 12:20:34.440422 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4677 12:20:34.443666 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4678 12:20:34.446845 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4679 12:20:34.450586 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4680 12:20:34.450679
4681 12:20:34.450769
4682 12:20:34.450856 ==
4683 12:20:34.453806 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 12:20:34.457174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 12:20:34.457259 ==
4686 12:20:34.457348
4687 12:20:34.460211
4688 12:20:34.460335 TX Vref Scan disable
4689 12:20:34.463545 == TX Byte 0 ==
4690 12:20:34.467002 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4691 12:20:34.470289 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4692 12:20:34.473370 == TX Byte 1 ==
4693 12:20:34.476786 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4694 12:20:34.480570 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4695 12:20:34.480659 ==
4696 12:20:34.483751 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 12:20:34.490413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 12:20:34.490487 ==
4699 12:20:34.490549
4700 12:20:34.490607
4701 12:20:34.490662 TX Vref Scan disable
4702 12:20:34.494925 == TX Byte 0 ==
4703 12:20:34.498336 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4704 12:20:34.501637 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4705 12:20:34.504544 == TX Byte 1 ==
4706 12:20:34.508454 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4707 12:20:34.514770 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4708 12:20:34.514855
4709 12:20:34.514940 [DATLAT]
4710 12:20:34.515019 Freq=600, CH1 RK1
4711 12:20:34.515096
4712 12:20:34.517937 DATLAT Default: 0x9
4713 12:20:34.518020 0, 0xFFFF, sum = 0
4714 12:20:34.521254 1, 0xFFFF, sum = 0
4715 12:20:34.521339 2, 0xFFFF, sum = 0
4716 12:20:34.524508 3, 0xFFFF, sum = 0
4717 12:20:34.528002 4, 0xFFFF, sum = 0
4718 12:20:34.528089 5, 0xFFFF, sum = 0
4719 12:20:34.531251 6, 0xFFFF, sum = 0
4720 12:20:34.531336 7, 0xFFFF, sum = 0
4721 12:20:34.534931 8, 0x0, sum = 1
4722 12:20:34.535016 9, 0x0, sum = 2
4723 12:20:34.535100 10, 0x0, sum = 3
4724 12:20:34.537967 11, 0x0, sum = 4
4725 12:20:34.538051 best_step = 9
4726 12:20:34.538134
4727 12:20:34.538212 ==
4728 12:20:34.541239 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 12:20:34.547669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 12:20:34.547800 ==
4731 12:20:34.547883 RX Vref Scan: 0
4732 12:20:34.547981
4733 12:20:34.551695 RX Vref 0 -> 0, step: 1
4734 12:20:34.551778
4735 12:20:34.554288 RX Delay -163 -> 252, step: 8
4736 12:20:34.557972 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4737 12:20:34.564694 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4738 12:20:34.567858 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4739 12:20:34.571007 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4740 12:20:34.574221 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4741 12:20:34.578125 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4742 12:20:34.584416 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4743 12:20:34.588208 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4744 12:20:34.591188 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4745 12:20:34.594304 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4746 12:20:34.598215 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4747 12:20:34.604220 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4748 12:20:34.607824 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4749 12:20:34.611155 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4750 12:20:34.614134 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4751 12:20:34.621291 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4752 12:20:34.621386 ==
4753 12:20:34.624308 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 12:20:34.627615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 12:20:34.627700 ==
4756 12:20:34.627784 DQS Delay:
4757 12:20:34.630685 DQS0 = 0, DQS1 = 0
4758 12:20:34.630793 DQM Delay:
4759 12:20:34.634475 DQM0 = 49, DQM1 = 45
4760 12:20:34.634576 DQ Delay:
4761 12:20:34.637486 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4762 12:20:34.641453 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4763 12:20:34.644658 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4764 12:20:34.647868 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4765 12:20:34.647966
4766 12:20:34.648055
4767 12:20:34.654448 [DQSOSCAuto] RK1, (LSB)MR18= 0x661c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4768 12:20:34.657519 CH1 RK1: MR19=808, MR18=661C
4769 12:20:34.664260 CH1_RK1: MR19=0x808, MR18=0x661C, DQSOSC=390, MR23=63, INC=172, DEC=114
4770 12:20:34.667659 [RxdqsGatingPostProcess] freq 600
4771 12:20:34.674264 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4772 12:20:34.674375 Pre-setting of DQS Precalculation
4773 12:20:34.680602 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4774 12:20:34.687387 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4775 12:20:34.694162 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4776 12:20:34.694257
4777 12:20:34.694342
4778 12:20:34.697179 [Calibration Summary] 1200 Mbps
4779 12:20:34.700771 CH 0, Rank 0
4780 12:20:34.700881 SW Impedance : PASS
4781 12:20:34.703793 DUTY Scan : NO K
4782 12:20:34.707594 ZQ Calibration : PASS
4783 12:20:34.707681 Jitter Meter : NO K
4784 12:20:34.710738 CBT Training : PASS
4785 12:20:34.710821 Write leveling : PASS
4786 12:20:34.714449 RX DQS gating : PASS
4787 12:20:34.717188 RX DQ/DQS(RDDQC) : PASS
4788 12:20:34.717289 TX DQ/DQS : PASS
4789 12:20:34.720635 RX DATLAT : PASS
4790 12:20:34.724025 RX DQ/DQS(Engine): PASS
4791 12:20:34.724127 TX OE : NO K
4792 12:20:34.727727 All Pass.
4793 12:20:34.727828
4794 12:20:34.727918 CH 0, Rank 1
4795 12:20:34.730986 SW Impedance : PASS
4796 12:20:34.731097 DUTY Scan : NO K
4797 12:20:34.734143 ZQ Calibration : PASS
4798 12:20:34.737404 Jitter Meter : NO K
4799 12:20:34.737485 CBT Training : PASS
4800 12:20:34.741152 Write leveling : PASS
4801 12:20:34.744292 RX DQS gating : PASS
4802 12:20:34.744387 RX DQ/DQS(RDDQC) : PASS
4803 12:20:34.747566 TX DQ/DQS : PASS
4804 12:20:34.747647 RX DATLAT : PASS
4805 12:20:34.750786 RX DQ/DQS(Engine): PASS
4806 12:20:34.754028 TX OE : NO K
4807 12:20:34.754113 All Pass.
4808 12:20:34.754181
4809 12:20:34.754240 CH 1, Rank 0
4810 12:20:34.757205 SW Impedance : PASS
4811 12:20:34.760469 DUTY Scan : NO K
4812 12:20:34.760549 ZQ Calibration : PASS
4813 12:20:34.763770 Jitter Meter : NO K
4814 12:20:34.767478 CBT Training : PASS
4815 12:20:34.767558 Write leveling : PASS
4816 12:20:34.770408 RX DQS gating : PASS
4817 12:20:34.773995 RX DQ/DQS(RDDQC) : PASS
4818 12:20:34.774077 TX DQ/DQS : PASS
4819 12:20:34.777045 RX DATLAT : PASS
4820 12:20:34.780237 RX DQ/DQS(Engine): PASS
4821 12:20:34.780374 TX OE : NO K
4822 12:20:34.783807 All Pass.
4823 12:20:34.783889
4824 12:20:34.783972 CH 1, Rank 1
4825 12:20:34.787211 SW Impedance : PASS
4826 12:20:34.787294 DUTY Scan : NO K
4827 12:20:34.790203 ZQ Calibration : PASS
4828 12:20:34.793850 Jitter Meter : NO K
4829 12:20:34.793957 CBT Training : PASS
4830 12:20:34.796871 Write leveling : PASS
4831 12:20:34.800626 RX DQS gating : PASS
4832 12:20:34.800733 RX DQ/DQS(RDDQC) : PASS
4833 12:20:34.803501 TX DQ/DQS : PASS
4834 12:20:34.806917 RX DATLAT : PASS
4835 12:20:34.807000 RX DQ/DQS(Engine): PASS
4836 12:20:34.809993 TX OE : NO K
4837 12:20:34.810069 All Pass.
4838 12:20:34.810129
4839 12:20:34.813375 DramC Write-DBI off
4840 12:20:34.817059 PER_BANK_REFRESH: Hybrid Mode
4841 12:20:34.817133 TX_TRACKING: ON
4842 12:20:34.826997 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4843 12:20:34.829902 [FAST_K] Save calibration result to emmc
4844 12:20:34.833455 dramc_set_vcore_voltage set vcore to 662500
4845 12:20:34.836781 Read voltage for 933, 3
4846 12:20:34.836857 Vio18 = 0
4847 12:20:34.836919 Vcore = 662500
4848 12:20:34.839990 Vdram = 0
4849 12:20:34.840090 Vddq = 0
4850 12:20:34.840178 Vmddr = 0
4851 12:20:34.846853 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4852 12:20:34.850046 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4853 12:20:34.852918 MEM_TYPE=3, freq_sel=17
4854 12:20:34.856736 sv_algorithm_assistance_LP4_1600
4855 12:20:34.859989 ============ PULL DRAM RESETB DOWN ============
4856 12:20:34.863161 ========== PULL DRAM RESETB DOWN end =========
4857 12:20:34.869850 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4858 12:20:34.872780 ===================================
4859 12:20:34.872884 LPDDR4 DRAM CONFIGURATION
4860 12:20:34.876172 ===================================
4861 12:20:34.879485 EX_ROW_EN[0] = 0x0
4862 12:20:34.883242 EX_ROW_EN[1] = 0x0
4863 12:20:34.883338 LP4Y_EN = 0x0
4864 12:20:34.886482 WORK_FSP = 0x0
4865 12:20:34.886577 WL = 0x3
4866 12:20:34.889657 RL = 0x3
4867 12:20:34.889760 BL = 0x2
4868 12:20:34.893239 RPST = 0x0
4869 12:20:34.893333 RD_PRE = 0x0
4870 12:20:34.896405 WR_PRE = 0x1
4871 12:20:34.896474 WR_PST = 0x0
4872 12:20:34.899711 DBI_WR = 0x0
4873 12:20:34.899811 DBI_RD = 0x0
4874 12:20:34.903402 OTF = 0x1
4875 12:20:34.906547 ===================================
4876 12:20:34.909724 ===================================
4877 12:20:34.909794 ANA top config
4878 12:20:34.913500 ===================================
4879 12:20:34.916275 DLL_ASYNC_EN = 0
4880 12:20:34.919824 ALL_SLAVE_EN = 1
4881 12:20:34.922791 NEW_RANK_MODE = 1
4882 12:20:34.922871 DLL_IDLE_MODE = 1
4883 12:20:34.926421 LP45_APHY_COMB_EN = 1
4884 12:20:34.929619 TX_ODT_DIS = 1
4885 12:20:34.932939 NEW_8X_MODE = 1
4886 12:20:34.936230 ===================================
4887 12:20:34.939428 ===================================
4888 12:20:34.942609 data_rate = 1866
4889 12:20:34.942708 CKR = 1
4890 12:20:34.945975 DQ_P2S_RATIO = 8
4891 12:20:34.949532 ===================================
4892 12:20:34.952715 CA_P2S_RATIO = 8
4893 12:20:34.956218 DQ_CA_OPEN = 0
4894 12:20:34.959430 DQ_SEMI_OPEN = 0
4895 12:20:34.962706 CA_SEMI_OPEN = 0
4896 12:20:34.962838 CA_FULL_RATE = 0
4897 12:20:34.966125 DQ_CKDIV4_EN = 1
4898 12:20:34.969749 CA_CKDIV4_EN = 1
4899 12:20:34.972929 CA_PREDIV_EN = 0
4900 12:20:34.975709 PH8_DLY = 0
4901 12:20:34.975804 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4902 12:20:34.979461 DQ_AAMCK_DIV = 4
4903 12:20:34.982648 CA_AAMCK_DIV = 4
4904 12:20:34.986016 CA_ADMCK_DIV = 4
4905 12:20:34.989024 DQ_TRACK_CA_EN = 0
4906 12:20:34.992773 CA_PICK = 933
4907 12:20:34.996102 CA_MCKIO = 933
4908 12:20:34.996198 MCKIO_SEMI = 0
4909 12:20:34.999217 PLL_FREQ = 3732
4910 12:20:35.002836 DQ_UI_PI_RATIO = 32
4911 12:20:35.005796 CA_UI_PI_RATIO = 0
4912 12:20:35.009516 ===================================
4913 12:20:35.012676 ===================================
4914 12:20:35.015932 memory_type:LPDDR4
4915 12:20:35.016027 GP_NUM : 10
4916 12:20:35.019031 SRAM_EN : 1
4917 12:20:35.022731 MD32_EN : 0
4918 12:20:35.025751 ===================================
4919 12:20:35.025855 [ANA_INIT] >>>>>>>>>>>>>>
4920 12:20:35.029261 <<<<<< [CONFIGURE PHASE]: ANA_TX
4921 12:20:35.032491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4922 12:20:35.035733 ===================================
4923 12:20:35.038903 data_rate = 1866,PCW = 0X8f00
4924 12:20:35.042833 ===================================
4925 12:20:35.045625 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4926 12:20:35.052439 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4927 12:20:35.055391 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4928 12:20:35.062045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4929 12:20:35.065237 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4930 12:20:35.068690 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4931 12:20:35.068801 [ANA_INIT] flow start
4932 12:20:35.071959 [ANA_INIT] PLL >>>>>>>>
4933 12:20:35.075405 [ANA_INIT] PLL <<<<<<<<
4934 12:20:35.078571 [ANA_INIT] MIDPI >>>>>>>>
4935 12:20:35.078654 [ANA_INIT] MIDPI <<<<<<<<
4936 12:20:35.081998 [ANA_INIT] DLL >>>>>>>>
4937 12:20:35.082082 [ANA_INIT] flow end
4938 12:20:35.088571 ============ LP4 DIFF to SE enter ============
4939 12:20:35.092007 ============ LP4 DIFF to SE exit ============
4940 12:20:35.095716 [ANA_INIT] <<<<<<<<<<<<<
4941 12:20:35.098373 [Flow] Enable top DCM control >>>>>
4942 12:20:35.102146 [Flow] Enable top DCM control <<<<<
4943 12:20:35.105242 Enable DLL master slave shuffle
4944 12:20:35.108233 ==============================================================
4945 12:20:35.111991 Gating Mode config
4946 12:20:35.115475 ==============================================================
4947 12:20:35.118606 Config description:
4948 12:20:35.128680 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4949 12:20:35.135070 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4950 12:20:35.139116 SELPH_MODE 0: By rank 1: By Phase
4951 12:20:35.145291 ==============================================================
4952 12:20:35.148237 GAT_TRACK_EN = 1
4953 12:20:35.151630 RX_GATING_MODE = 2
4954 12:20:35.154919 RX_GATING_TRACK_MODE = 2
4955 12:20:35.158544 SELPH_MODE = 1
4956 12:20:35.162054 PICG_EARLY_EN = 1
4957 12:20:35.162136 VALID_LAT_VALUE = 1
4958 12:20:35.168710 ==============================================================
4959 12:20:35.171686 Enter into Gating configuration >>>>
4960 12:20:35.174862 Exit from Gating configuration <<<<
4961 12:20:35.178541 Enter into DVFS_PRE_config >>>>>
4962 12:20:35.188615 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4963 12:20:35.191556 Exit from DVFS_PRE_config <<<<<
4964 12:20:35.194762 Enter into PICG configuration >>>>
4965 12:20:35.198371 Exit from PICG configuration <<<<
4966 12:20:35.201721 [RX_INPUT] configuration >>>>>
4967 12:20:35.204763 [RX_INPUT] configuration <<<<<
4968 12:20:35.208191 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4969 12:20:35.215457 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4970 12:20:35.221725 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4971 12:20:35.228028 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4972 12:20:35.235120 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4973 12:20:35.238085 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4974 12:20:35.244824 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4975 12:20:35.248057 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4976 12:20:35.251222 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4977 12:20:35.254829 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4978 12:20:35.261348 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4979 12:20:35.265212 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4980 12:20:35.268180 ===================================
4981 12:20:35.271533 LPDDR4 DRAM CONFIGURATION
4982 12:20:35.274703 ===================================
4983 12:20:35.274801 EX_ROW_EN[0] = 0x0
4984 12:20:35.278392 EX_ROW_EN[1] = 0x0
4985 12:20:35.278589 LP4Y_EN = 0x0
4986 12:20:35.281411 WORK_FSP = 0x0
4987 12:20:35.281587 WL = 0x3
4988 12:20:35.285059 RL = 0x3
4989 12:20:35.285242 BL = 0x2
4990 12:20:35.288033 RPST = 0x0
4991 12:20:35.288201 RD_PRE = 0x0
4992 12:20:35.291183 WR_PRE = 0x1
4993 12:20:35.291259 WR_PST = 0x0
4994 12:20:35.294954 DBI_WR = 0x0
4995 12:20:35.298431 DBI_RD = 0x0
4996 12:20:35.298553 OTF = 0x1
4997 12:20:35.301187 ===================================
4998 12:20:35.304823 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4999 12:20:35.307937 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5000 12:20:35.314826 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5001 12:20:35.318139 ===================================
5002 12:20:35.321374 LPDDR4 DRAM CONFIGURATION
5003 12:20:35.324406 ===================================
5004 12:20:35.324487 EX_ROW_EN[0] = 0x10
5005 12:20:35.328147 EX_ROW_EN[1] = 0x0
5006 12:20:35.328268 LP4Y_EN = 0x0
5007 12:20:35.331121 WORK_FSP = 0x0
5008 12:20:35.331198 WL = 0x3
5009 12:20:35.334328 RL = 0x3
5010 12:20:35.334432 BL = 0x2
5011 12:20:35.337472 RPST = 0x0
5012 12:20:35.337585 RD_PRE = 0x0
5013 12:20:35.340809 WR_PRE = 0x1
5014 12:20:35.343910 WR_PST = 0x0
5015 12:20:35.344012 DBI_WR = 0x0
5016 12:20:35.347581 DBI_RD = 0x0
5017 12:20:35.347665 OTF = 0x1
5018 12:20:35.350662 ===================================
5019 12:20:35.357416 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5020 12:20:35.360861 nWR fixed to 30
5021 12:20:35.364205 [ModeRegInit_LP4] CH0 RK0
5022 12:20:35.364353 [ModeRegInit_LP4] CH0 RK1
5023 12:20:35.368068 [ModeRegInit_LP4] CH1 RK0
5024 12:20:35.371139 [ModeRegInit_LP4] CH1 RK1
5025 12:20:35.371264 match AC timing 9
5026 12:20:35.377493 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5027 12:20:35.381143 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5028 12:20:35.384127 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5029 12:20:35.390747 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5030 12:20:35.394253 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5031 12:20:35.394356 ==
5032 12:20:35.397441 Dram Type= 6, Freq= 0, CH_0, rank 0
5033 12:20:35.400522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5034 12:20:35.400641 ==
5035 12:20:35.407641 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5036 12:20:35.414144 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5037 12:20:35.417293 [CA 0] Center 37 (6~68) winsize 63
5038 12:20:35.420691 [CA 1] Center 37 (7~68) winsize 62
5039 12:20:35.423967 [CA 2] Center 34 (4~65) winsize 62
5040 12:20:35.427154 [CA 3] Center 33 (3~64) winsize 62
5041 12:20:35.430257 [CA 4] Center 33 (3~64) winsize 62
5042 12:20:35.433828 [CA 5] Center 32 (2~62) winsize 61
5043 12:20:35.433945
5044 12:20:35.437217 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5045 12:20:35.437293
5046 12:20:35.440107 [CATrainingPosCal] consider 1 rank data
5047 12:20:35.443962 u2DelayCellTimex100 = 270/100 ps
5048 12:20:35.447141 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5049 12:20:35.450378 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5050 12:20:35.453693 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5051 12:20:35.456761 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5052 12:20:35.460176 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5053 12:20:35.466913 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5054 12:20:35.467012
5055 12:20:35.470429 CA PerBit enable=1, Macro0, CA PI delay=32
5056 12:20:35.470523
5057 12:20:35.473814 [CBTSetCACLKResult] CA Dly = 32
5058 12:20:35.473886 CS Dly: 5 (0~36)
5059 12:20:35.473947 ==
5060 12:20:35.476792 Dram Type= 6, Freq= 0, CH_0, rank 1
5061 12:20:35.480478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5062 12:20:35.483680 ==
5063 12:20:35.486658 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5064 12:20:35.493409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5065 12:20:35.496608 [CA 0] Center 37 (6~68) winsize 63
5066 12:20:35.499979 [CA 1] Center 37 (7~68) winsize 62
5067 12:20:35.503365 [CA 2] Center 34 (4~65) winsize 62
5068 12:20:35.506638 [CA 3] Center 34 (3~65) winsize 63
5069 12:20:35.510000 [CA 4] Center 33 (3~63) winsize 61
5070 12:20:35.513189 [CA 5] Center 32 (2~62) winsize 61
5071 12:20:35.513290
5072 12:20:35.516531 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5073 12:20:35.516629
5074 12:20:35.520050 [CATrainingPosCal] consider 2 rank data
5075 12:20:35.523583 u2DelayCellTimex100 = 270/100 ps
5076 12:20:35.526449 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5077 12:20:35.530559 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5078 12:20:35.533659 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5079 12:20:35.539857 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5080 12:20:35.543707 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5081 12:20:35.546686 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5082 12:20:35.546785
5083 12:20:35.549736 CA PerBit enable=1, Macro0, CA PI delay=32
5084 12:20:35.549823
5085 12:20:35.553094 [CBTSetCACLKResult] CA Dly = 32
5086 12:20:35.553168 CS Dly: 5 (0~37)
5087 12:20:35.553229
5088 12:20:35.556815 ----->DramcWriteLeveling(PI) begin...
5089 12:20:35.556914 ==
5090 12:20:35.560070 Dram Type= 6, Freq= 0, CH_0, rank 0
5091 12:20:35.566573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 12:20:35.566693 ==
5093 12:20:35.570031 Write leveling (Byte 0): 32 => 32
5094 12:20:35.573074 Write leveling (Byte 1): 28 => 28
5095 12:20:35.573146 DramcWriteLeveling(PI) end<-----
5096 12:20:35.576359
5097 12:20:35.576457 ==
5098 12:20:35.580117 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 12:20:35.582803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 12:20:35.582897 ==
5101 12:20:35.586520 [Gating] SW mode calibration
5102 12:20:35.592969 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5103 12:20:35.596704 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5104 12:20:35.603123 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
5105 12:20:35.606227 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 12:20:35.609757 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 12:20:35.616495 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 12:20:35.619632 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 12:20:35.623403 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 12:20:35.629595 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5111 12:20:35.632966 0 14 28 | B1->B0 | 3131 2828 | 0 0 | (0 1) (0 0)
5112 12:20:35.636185 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
5113 12:20:35.642964 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 12:20:35.646451 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 12:20:35.649324 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 12:20:35.656065 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 12:20:35.659453 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 12:20:35.662813 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 12:20:35.669641 0 15 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (1 1)
5120 12:20:35.672643 1 0 0 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5121 12:20:35.675849 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 12:20:35.682949 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 12:20:35.686058 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 12:20:35.689240 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 12:20:35.696153 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 12:20:35.699492 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5127 12:20:35.702444 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5128 12:20:35.709022 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5129 12:20:35.712745 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 12:20:35.715937 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 12:20:35.719127 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 12:20:35.725661 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 12:20:35.729149 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 12:20:35.732240 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 12:20:35.739156 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 12:20:35.742329 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 12:20:35.745708 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 12:20:35.752785 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 12:20:35.756072 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 12:20:35.759161 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 12:20:35.766141 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 12:20:35.769304 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5143 12:20:35.772392 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5144 12:20:35.775793 Total UI for P1: 0, mck2ui 16
5145 12:20:35.778844 best dqsien dly found for B0: ( 1, 2, 24)
5146 12:20:35.785543 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5147 12:20:35.788764 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 12:20:35.792074 Total UI for P1: 0, mck2ui 16
5149 12:20:35.795348 best dqsien dly found for B1: ( 1, 2, 30)
5150 12:20:35.798750 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5151 12:20:35.802685 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5152 12:20:35.802854
5153 12:20:35.805510 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5154 12:20:35.808857 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5155 12:20:35.812168 [Gating] SW calibration Done
5156 12:20:35.812265 ==
5157 12:20:35.815650 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 12:20:35.819056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 12:20:35.819136 ==
5160 12:20:35.822175 RX Vref Scan: 0
5161 12:20:35.822276
5162 12:20:35.825883 RX Vref 0 -> 0, step: 1
5163 12:20:35.825961
5164 12:20:35.826024 RX Delay -80 -> 252, step: 8
5165 12:20:35.832455 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5166 12:20:35.835675 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5167 12:20:35.838911 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5168 12:20:35.842156 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5169 12:20:35.845847 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5170 12:20:35.852442 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5171 12:20:35.855543 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5172 12:20:35.858806 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5173 12:20:35.862676 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5174 12:20:35.865524 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5175 12:20:35.868673 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5176 12:20:35.875738 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5177 12:20:35.878995 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5178 12:20:35.882199 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5179 12:20:35.885987 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5180 12:20:35.888919 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5181 12:20:35.888992 ==
5182 12:20:35.892228 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 12:20:35.898666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 12:20:35.898770 ==
5185 12:20:35.898865 DQS Delay:
5186 12:20:35.901883 DQS0 = 0, DQS1 = 0
5187 12:20:35.901980 DQM Delay:
5188 12:20:35.902071 DQM0 = 105, DQM1 = 94
5189 12:20:35.905056 DQ Delay:
5190 12:20:35.908614 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5191 12:20:35.912187 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5192 12:20:35.915243 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5193 12:20:35.918323 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5194 12:20:35.918425
5195 12:20:35.918515
5196 12:20:35.918601 ==
5197 12:20:35.922003 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 12:20:35.925196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 12:20:35.925278 ==
5200 12:20:35.925341
5201 12:20:35.925399
5202 12:20:35.928442 TX Vref Scan disable
5203 12:20:35.931826 == TX Byte 0 ==
5204 12:20:35.936238 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5205 12:20:35.938644 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5206 12:20:35.941661 == TX Byte 1 ==
5207 12:20:35.945260 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5208 12:20:35.948697 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5209 12:20:35.948783 ==
5210 12:20:35.951985 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 12:20:35.955165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 12:20:35.958507 ==
5213 12:20:35.958611
5214 12:20:35.958704
5215 12:20:35.958792 TX Vref Scan disable
5216 12:20:35.962374 == TX Byte 0 ==
5217 12:20:35.965330 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5218 12:20:35.972097 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5219 12:20:35.972206 == TX Byte 1 ==
5220 12:20:35.975282 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5221 12:20:35.981896 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5222 12:20:35.981974
5223 12:20:35.982036 [DATLAT]
5224 12:20:35.982107 Freq=933, CH0 RK0
5225 12:20:35.982199
5226 12:20:35.985748 DATLAT Default: 0xd
5227 12:20:35.985823 0, 0xFFFF, sum = 0
5228 12:20:35.988781 1, 0xFFFF, sum = 0
5229 12:20:35.988859 2, 0xFFFF, sum = 0
5230 12:20:35.992095 3, 0xFFFF, sum = 0
5231 12:20:35.992196 4, 0xFFFF, sum = 0
5232 12:20:35.995819 5, 0xFFFF, sum = 0
5233 12:20:35.999175 6, 0xFFFF, sum = 0
5234 12:20:35.999279 7, 0xFFFF, sum = 0
5235 12:20:36.002122 8, 0xFFFF, sum = 0
5236 12:20:36.002224 9, 0xFFFF, sum = 0
5237 12:20:36.005536 10, 0x0, sum = 1
5238 12:20:36.005612 11, 0x0, sum = 2
5239 12:20:36.008889 12, 0x0, sum = 3
5240 12:20:36.008962 13, 0x0, sum = 4
5241 12:20:36.009024 best_step = 11
5242 12:20:36.009082
5243 12:20:36.012160 ==
5244 12:20:36.015715 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 12:20:36.018765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 12:20:36.018864 ==
5247 12:20:36.018959 RX Vref Scan: 1
5248 12:20:36.019051
5249 12:20:36.021723 RX Vref 0 -> 0, step: 1
5250 12:20:36.021821
5251 12:20:36.025261 RX Delay -53 -> 252, step: 4
5252 12:20:36.025372
5253 12:20:36.028421 Set Vref, RX VrefLevel [Byte0]: 55
5254 12:20:36.031601 [Byte1]: 50
5255 12:20:36.031670
5256 12:20:36.035947 Final RX Vref Byte 0 = 55 to rank0
5257 12:20:36.038939 Final RX Vref Byte 1 = 50 to rank0
5258 12:20:36.041545 Final RX Vref Byte 0 = 55 to rank1
5259 12:20:36.045326 Final RX Vref Byte 1 = 50 to rank1==
5260 12:20:36.048520 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 12:20:36.051709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 12:20:36.055457 ==
5263 12:20:36.055532 DQS Delay:
5264 12:20:36.055595 DQS0 = 0, DQS1 = 0
5265 12:20:36.058471 DQM Delay:
5266 12:20:36.058542 DQM0 = 104, DQM1 = 97
5267 12:20:36.062021 DQ Delay:
5268 12:20:36.064934 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5269 12:20:36.068528 DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =110
5270 12:20:36.072042 DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =90
5271 12:20:36.075067 DQ12 =102, DQ13 =102, DQ14 =106, DQ15 =104
5272 12:20:36.075185
5273 12:20:36.075248
5274 12:20:36.081820 [DQSOSCAuto] RK0, (LSB)MR18= 0x322a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5275 12:20:36.084883 CH0 RK0: MR19=505, MR18=322A
5276 12:20:36.091726 CH0_RK0: MR19=0x505, MR18=0x322A, DQSOSC=406, MR23=63, INC=65, DEC=43
5277 12:20:36.091801
5278 12:20:36.094908 ----->DramcWriteLeveling(PI) begin...
5279 12:20:36.094983 ==
5280 12:20:36.098410 Dram Type= 6, Freq= 0, CH_0, rank 1
5281 12:20:36.101646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 12:20:36.101750 ==
5283 12:20:36.104920 Write leveling (Byte 0): 33 => 33
5284 12:20:36.108472 Write leveling (Byte 1): 28 => 28
5285 12:20:36.111402 DramcWriteLeveling(PI) end<-----
5286 12:20:36.111478
5287 12:20:36.111543 ==
5288 12:20:36.114879 Dram Type= 6, Freq= 0, CH_0, rank 1
5289 12:20:36.118934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 12:20:36.119029 ==
5291 12:20:36.121799 [Gating] SW mode calibration
5292 12:20:36.128107 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5293 12:20:36.134911 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5294 12:20:36.138225 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
5295 12:20:36.144830 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 12:20:36.148064 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 12:20:36.151887 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 12:20:36.158090 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 12:20:36.161307 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 12:20:36.164305 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 12:20:36.171043 0 14 28 | B1->B0 | 2c2c 2e2e | 0 0 | (0 0) (1 0)
5302 12:20:36.174600 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5303 12:20:36.178184 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 12:20:36.184760 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 12:20:36.188001 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 12:20:36.191254 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 12:20:36.197870 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 12:20:36.200983 0 15 24 | B1->B0 | 2b2b 2323 | 1 0 | (0 0) (0 0)
5309 12:20:36.204213 0 15 28 | B1->B0 | 3636 3636 | 0 0 | (0 0) (0 0)
5310 12:20:36.210805 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5311 12:20:36.214151 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 12:20:36.217331 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 12:20:36.224478 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 12:20:36.227408 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 12:20:36.231116 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 12:20:36.237177 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 12:20:36.240509 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 12:20:36.244422 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5319 12:20:36.250102 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 12:20:36.253592 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 12:20:36.256998 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 12:20:36.263386 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 12:20:36.266877 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 12:20:36.270206 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 12:20:36.276872 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 12:20:36.280124 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 12:20:36.283941 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 12:20:36.290377 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 12:20:36.293156 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 12:20:36.296260 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 12:20:36.303418 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 12:20:36.306560 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 12:20:36.310062 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5334 12:20:36.316636 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 12:20:36.316716 Total UI for P1: 0, mck2ui 16
5336 12:20:36.323041 best dqsien dly found for B0: ( 1, 2, 28)
5337 12:20:36.323120 Total UI for P1: 0, mck2ui 16
5338 12:20:36.327071 best dqsien dly found for B1: ( 1, 2, 28)
5339 12:20:36.332932 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5340 12:20:36.336149 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5341 12:20:36.336245
5342 12:20:36.339737 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5343 12:20:36.343240 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5344 12:20:36.346381 [Gating] SW calibration Done
5345 12:20:36.346450 ==
5346 12:20:36.349594 Dram Type= 6, Freq= 0, CH_0, rank 1
5347 12:20:36.353036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 12:20:36.353111 ==
5349 12:20:36.356258 RX Vref Scan: 0
5350 12:20:36.356356
5351 12:20:36.356415 RX Vref 0 -> 0, step: 1
5352 12:20:36.356471
5353 12:20:36.359434 RX Delay -80 -> 252, step: 8
5354 12:20:36.362904 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5355 12:20:36.369342 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5356 12:20:36.372818 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5357 12:20:36.376439 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5358 12:20:36.379544 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5359 12:20:36.382689 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5360 12:20:36.386008 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5361 12:20:36.392647 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5362 12:20:36.396060 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5363 12:20:36.399503 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5364 12:20:36.402688 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5365 12:20:36.405902 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5366 12:20:36.409565 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5367 12:20:36.416209 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5368 12:20:36.419656 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5369 12:20:36.423016 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5370 12:20:36.423096 ==
5371 12:20:36.426370 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 12:20:36.429525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 12:20:36.429605 ==
5374 12:20:36.432819 DQS Delay:
5375 12:20:36.432890 DQS0 = 0, DQS1 = 0
5376 12:20:36.432951 DQM Delay:
5377 12:20:36.435887 DQM0 = 105, DQM1 = 93
5378 12:20:36.435983 DQ Delay:
5379 12:20:36.439570 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5380 12:20:36.442875 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5381 12:20:36.446243 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5382 12:20:36.449212 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5383 12:20:36.449292
5384 12:20:36.449368
5385 12:20:36.452501 ==
5386 12:20:36.452582 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 12:20:36.459608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 12:20:36.459681 ==
5389 12:20:36.459741
5390 12:20:36.459798
5391 12:20:36.462974 TX Vref Scan disable
5392 12:20:36.463067 == TX Byte 0 ==
5393 12:20:36.465730 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5394 12:20:36.472330 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5395 12:20:36.472411 == TX Byte 1 ==
5396 12:20:36.475826 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5397 12:20:36.482392 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5398 12:20:36.482487 ==
5399 12:20:36.485602 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 12:20:36.489428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 12:20:36.489537 ==
5402 12:20:36.489622
5403 12:20:36.489700
5404 12:20:36.492632 TX Vref Scan disable
5405 12:20:36.495907 == TX Byte 0 ==
5406 12:20:36.499235 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5407 12:20:36.502480 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5408 12:20:36.505445 == TX Byte 1 ==
5409 12:20:36.509048 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5410 12:20:36.512537 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5411 12:20:36.512720
5412 12:20:36.515477 [DATLAT]
5413 12:20:36.515647 Freq=933, CH0 RK1
5414 12:20:36.515801
5415 12:20:36.519461 DATLAT Default: 0xb
5416 12:20:36.519674 0, 0xFFFF, sum = 0
5417 12:20:36.522130 1, 0xFFFF, sum = 0
5418 12:20:36.522497 2, 0xFFFF, sum = 0
5419 12:20:36.525720 3, 0xFFFF, sum = 0
5420 12:20:36.526065 4, 0xFFFF, sum = 0
5421 12:20:36.529128 5, 0xFFFF, sum = 0
5422 12:20:36.529469 6, 0xFFFF, sum = 0
5423 12:20:36.532141 7, 0xFFFF, sum = 0
5424 12:20:36.532669 8, 0xFFFF, sum = 0
5425 12:20:36.535862 9, 0xFFFF, sum = 0
5426 12:20:36.536264 10, 0x0, sum = 1
5427 12:20:36.539046 11, 0x0, sum = 2
5428 12:20:36.539394 12, 0x0, sum = 3
5429 12:20:36.542241 13, 0x0, sum = 4
5430 12:20:36.542674 best_step = 11
5431 12:20:36.543129
5432 12:20:36.543533 ==
5433 12:20:36.545608 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 12:20:36.552067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 12:20:36.552607 ==
5436 12:20:36.552915 RX Vref Scan: 0
5437 12:20:36.553197
5438 12:20:36.555741 RX Vref 0 -> 0, step: 1
5439 12:20:36.556271
5440 12:20:36.558984 RX Delay -45 -> 252, step: 4
5441 12:20:36.562160 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5442 12:20:36.565407 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5443 12:20:36.572388 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5444 12:20:36.575029 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5445 12:20:36.578706 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5446 12:20:36.582153 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5447 12:20:36.585377 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5448 12:20:36.591931 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5449 12:20:36.595252 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5450 12:20:36.598588 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5451 12:20:36.601625 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5452 12:20:36.605182 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5453 12:20:36.608203 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5454 12:20:36.615253 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5455 12:20:36.618651 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5456 12:20:36.621703 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5457 12:20:36.622111 ==
5458 12:20:36.625658 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 12:20:36.629295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 12:20:36.629697 ==
5461 12:20:36.632035 DQS Delay:
5462 12:20:36.632495 DQS0 = 0, DQS1 = 0
5463 12:20:36.635190 DQM Delay:
5464 12:20:36.635589 DQM0 = 104, DQM1 = 93
5465 12:20:36.638380 DQ Delay:
5466 12:20:36.641787 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =100
5467 12:20:36.645250 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5468 12:20:36.648838 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5469 12:20:36.652033 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102
5470 12:20:36.652585
5471 12:20:36.653058
5472 12:20:36.658676 [DQSOSCAuto] RK1, (LSB)MR18= 0x25ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5473 12:20:36.661630 CH0 RK1: MR19=504, MR18=25FF
5474 12:20:36.667976 CH0_RK1: MR19=0x504, MR18=0x25FF, DQSOSC=410, MR23=63, INC=64, DEC=42
5475 12:20:36.671676 [RxdqsGatingPostProcess] freq 933
5476 12:20:36.674888 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5477 12:20:36.678383 best DQS0 dly(2T, 0.5T) = (0, 10)
5478 12:20:36.681600 best DQS1 dly(2T, 0.5T) = (0, 10)
5479 12:20:36.684784 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5480 12:20:36.688258 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5481 12:20:36.692379 best DQS0 dly(2T, 0.5T) = (0, 10)
5482 12:20:36.695242 best DQS1 dly(2T, 0.5T) = (0, 10)
5483 12:20:36.697996 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5484 12:20:36.701349 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5485 12:20:36.704622 Pre-setting of DQS Precalculation
5486 12:20:36.708159 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5487 12:20:36.708786 ==
5488 12:20:36.711260 Dram Type= 6, Freq= 0, CH_1, rank 0
5489 12:20:36.718341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 12:20:36.718719 ==
5491 12:20:36.721308 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5492 12:20:36.728035 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5493 12:20:36.731377 [CA 0] Center 36 (6~67) winsize 62
5494 12:20:36.734682 [CA 1] Center 36 (6~67) winsize 62
5495 12:20:36.738282 [CA 2] Center 35 (5~65) winsize 61
5496 12:20:36.741699 [CA 3] Center 34 (4~64) winsize 61
5497 12:20:36.744882 [CA 4] Center 34 (4~64) winsize 61
5498 12:20:36.748160 [CA 5] Center 33 (3~64) winsize 62
5499 12:20:36.748618
5500 12:20:36.751839 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5501 12:20:36.752247
5502 12:20:36.755186 [CATrainingPosCal] consider 1 rank data
5503 12:20:36.758386 u2DelayCellTimex100 = 270/100 ps
5504 12:20:36.761854 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5505 12:20:36.764789 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5506 12:20:36.771650 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5507 12:20:36.774794 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5508 12:20:36.777909 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5509 12:20:36.781679 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5510 12:20:36.782089
5511 12:20:36.784802 CA PerBit enable=1, Macro0, CA PI delay=33
5512 12:20:36.785221
5513 12:20:36.788758 [CBTSetCACLKResult] CA Dly = 33
5514 12:20:36.789167 CS Dly: 7 (0~38)
5515 12:20:36.789491 ==
5516 12:20:36.791259 Dram Type= 6, Freq= 0, CH_1, rank 1
5517 12:20:36.798343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 12:20:36.798796 ==
5519 12:20:36.801323 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5520 12:20:36.808105 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5521 12:20:36.811337 [CA 0] Center 36 (6~67) winsize 62
5522 12:20:36.814851 [CA 1] Center 37 (7~68) winsize 62
5523 12:20:36.817899 [CA 2] Center 35 (5~65) winsize 61
5524 12:20:36.821506 [CA 3] Center 34 (4~65) winsize 62
5525 12:20:36.824593 [CA 4] Center 34 (4~65) winsize 62
5526 12:20:36.827812 [CA 5] Center 33 (3~64) winsize 62
5527 12:20:36.828187
5528 12:20:36.831006 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5529 12:20:36.831381
5530 12:20:36.834465 [CATrainingPosCal] consider 2 rank data
5531 12:20:36.837579 u2DelayCellTimex100 = 270/100 ps
5532 12:20:36.841050 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5533 12:20:36.847761 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5534 12:20:36.851402 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5535 12:20:36.854951 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5536 12:20:36.857825 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5537 12:20:36.861228 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5538 12:20:36.861603
5539 12:20:36.864498 CA PerBit enable=1, Macro0, CA PI delay=33
5540 12:20:36.864875
5541 12:20:36.867746 [CBTSetCACLKResult] CA Dly = 33
5542 12:20:36.868123 CS Dly: 8 (0~40)
5543 12:20:36.871040
5544 12:20:36.874580 ----->DramcWriteLeveling(PI) begin...
5545 12:20:36.874959 ==
5546 12:20:36.877718 Dram Type= 6, Freq= 0, CH_1, rank 0
5547 12:20:36.880990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 12:20:36.881368 ==
5549 12:20:36.884722 Write leveling (Byte 0): 25 => 25
5550 12:20:36.887882 Write leveling (Byte 1): 26 => 26
5551 12:20:36.890874 DramcWriteLeveling(PI) end<-----
5552 12:20:36.891265
5553 12:20:36.891568 ==
5554 12:20:36.894568 Dram Type= 6, Freq= 0, CH_1, rank 0
5555 12:20:36.897537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5556 12:20:36.897975 ==
5557 12:20:36.901328 [Gating] SW mode calibration
5558 12:20:36.907788 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5559 12:20:36.914000 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5560 12:20:36.917294 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 12:20:36.921342 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 12:20:36.927771 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 12:20:36.930884 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 12:20:36.934148 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 12:20:36.940582 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 12:20:36.943737 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
5567 12:20:36.947112 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5568 12:20:36.953779 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 12:20:36.957145 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 12:20:36.960825 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 12:20:36.967060 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 12:20:36.970522 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 12:20:36.973775 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 12:20:36.977040 0 15 24 | B1->B0 | 2929 3232 | 0 0 | (0 0) (0 0)
5575 12:20:36.983684 0 15 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5576 12:20:36.987271 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 12:20:36.990479 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 12:20:36.997000 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 12:20:37.000403 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 12:20:37.003737 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 12:20:37.010330 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 12:20:37.013986 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5583 12:20:37.017164 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5584 12:20:37.023753 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 12:20:37.026877 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 12:20:37.030452 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 12:20:37.036678 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 12:20:37.040146 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 12:20:37.043341 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 12:20:37.050450 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 12:20:37.053524 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 12:20:37.056915 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 12:20:37.063996 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 12:20:37.067032 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 12:20:37.070384 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 12:20:37.076663 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 12:20:37.080204 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5598 12:20:37.083539 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5599 12:20:37.090310 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5600 12:20:37.090690 Total UI for P1: 0, mck2ui 16
5601 12:20:37.096617 best dqsien dly found for B1: ( 1, 2, 24)
5602 12:20:37.100079 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 12:20:37.103166 Total UI for P1: 0, mck2ui 16
5604 12:20:37.106657 best dqsien dly found for B0: ( 1, 2, 24)
5605 12:20:37.110004 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5606 12:20:37.113390 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5607 12:20:37.113740
5608 12:20:37.116784 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5609 12:20:37.119864 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5610 12:20:37.123273 [Gating] SW calibration Done
5611 12:20:37.123614 ==
5612 12:20:37.126769 Dram Type= 6, Freq= 0, CH_1, rank 0
5613 12:20:37.129803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5614 12:20:37.130205 ==
5615 12:20:37.133256 RX Vref Scan: 0
5616 12:20:37.133820
5617 12:20:37.136634 RX Vref 0 -> 0, step: 1
5618 12:20:37.137214
5619 12:20:37.137707 RX Delay -80 -> 252, step: 8
5620 12:20:37.143134 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5621 12:20:37.146687 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5622 12:20:37.150004 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5623 12:20:37.153226 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5624 12:20:37.156692 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5625 12:20:37.159949 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5626 12:20:37.166543 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5627 12:20:37.169735 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5628 12:20:37.172915 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5629 12:20:37.176244 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5630 12:20:37.179649 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5631 12:20:37.182841 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5632 12:20:37.189984 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5633 12:20:37.193065 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5634 12:20:37.196499 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5635 12:20:37.199668 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5636 12:20:37.200069 ==
5637 12:20:37.202711 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 12:20:37.209160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 12:20:37.209551 ==
5640 12:20:37.209850 DQS Delay:
5641 12:20:37.212507 DQS0 = 0, DQS1 = 0
5642 12:20:37.212886 DQM Delay:
5643 12:20:37.216381 DQM0 = 102, DQM1 = 97
5644 12:20:37.216761 DQ Delay:
5645 12:20:37.219074 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5646 12:20:37.222703 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5647 12:20:37.225891 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5648 12:20:37.229621 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5649 12:20:37.229999
5650 12:20:37.230297
5651 12:20:37.230574 ==
5652 12:20:37.232814 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 12:20:37.235960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 12:20:37.236380 ==
5655 12:20:37.239262
5656 12:20:37.239637
5657 12:20:37.239933 TX Vref Scan disable
5658 12:20:37.242480 == TX Byte 0 ==
5659 12:20:37.245666 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5660 12:20:37.249399 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5661 12:20:37.252411 == TX Byte 1 ==
5662 12:20:37.255969 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5663 12:20:37.259042 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5664 12:20:37.259455 ==
5665 12:20:37.262477 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 12:20:37.268849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 12:20:37.269263 ==
5668 12:20:37.269598
5669 12:20:37.269905
5670 12:20:37.270198 TX Vref Scan disable
5671 12:20:37.273222 == TX Byte 0 ==
5672 12:20:37.276439 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5673 12:20:37.283172 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5674 12:20:37.283586 == TX Byte 1 ==
5675 12:20:37.286431 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5676 12:20:37.292923 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5677 12:20:37.293340
5678 12:20:37.293664 [DATLAT]
5679 12:20:37.293969 Freq=933, CH1 RK0
5680 12:20:37.294264
5681 12:20:37.296640 DATLAT Default: 0xd
5682 12:20:37.297051 0, 0xFFFF, sum = 0
5683 12:20:37.299664 1, 0xFFFF, sum = 0
5684 12:20:37.303275 2, 0xFFFF, sum = 0
5685 12:20:37.303696 3, 0xFFFF, sum = 0
5686 12:20:37.306084 4, 0xFFFF, sum = 0
5687 12:20:37.306506 5, 0xFFFF, sum = 0
5688 12:20:37.309807 6, 0xFFFF, sum = 0
5689 12:20:37.310227 7, 0xFFFF, sum = 0
5690 12:20:37.313529 8, 0xFFFF, sum = 0
5691 12:20:37.313948 9, 0xFFFF, sum = 0
5692 12:20:37.316783 10, 0x0, sum = 1
5693 12:20:37.317202 11, 0x0, sum = 2
5694 12:20:37.319542 12, 0x0, sum = 3
5695 12:20:37.319960 13, 0x0, sum = 4
5696 12:20:37.320322 best_step = 11
5697 12:20:37.320630
5698 12:20:37.323487 ==
5699 12:20:37.326583 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 12:20:37.329558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 12:20:37.329973 ==
5702 12:20:37.330299 RX Vref Scan: 1
5703 12:20:37.330603
5704 12:20:37.333317 RX Vref 0 -> 0, step: 1
5705 12:20:37.333729
5706 12:20:37.336604 RX Delay -45 -> 252, step: 4
5707 12:20:37.337017
5708 12:20:37.339803 Set Vref, RX VrefLevel [Byte0]: 54
5709 12:20:37.342991 [Byte1]: 48
5710 12:20:37.343534
5711 12:20:37.346638 Final RX Vref Byte 0 = 54 to rank0
5712 12:20:37.349831 Final RX Vref Byte 1 = 48 to rank0
5713 12:20:37.353091 Final RX Vref Byte 0 = 54 to rank1
5714 12:20:37.356151 Final RX Vref Byte 1 = 48 to rank1==
5715 12:20:37.359278 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 12:20:37.363230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 12:20:37.363792 ==
5718 12:20:37.366522 DQS Delay:
5719 12:20:37.367041 DQS0 = 0, DQS1 = 0
5720 12:20:37.369812 DQM Delay:
5721 12:20:37.370257 DQM0 = 103, DQM1 = 98
5722 12:20:37.373080 DQ Delay:
5723 12:20:37.373607 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =102
5724 12:20:37.379420 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =102
5725 12:20:37.379884 DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =94
5726 12:20:37.386586 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =108
5727 12:20:37.387122
5728 12:20:37.387576
5729 12:20:37.393145 [DQSOSCAuto] RK0, (LSB)MR18= 0x152c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5730 12:20:37.396162 CH1 RK0: MR19=505, MR18=152C
5731 12:20:37.402920 CH1_RK0: MR19=0x505, MR18=0x152C, DQSOSC=408, MR23=63, INC=65, DEC=43
5732 12:20:37.403342
5733 12:20:37.406146 ----->DramcWriteLeveling(PI) begin...
5734 12:20:37.406579 ==
5735 12:20:37.409717 Dram Type= 6, Freq= 0, CH_1, rank 1
5736 12:20:37.413167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 12:20:37.413584 ==
5738 12:20:37.416066 Write leveling (Byte 0): 27 => 27
5739 12:20:37.420178 Write leveling (Byte 1): 28 => 28
5740 12:20:37.422864 DramcWriteLeveling(PI) end<-----
5741 12:20:37.423280
5742 12:20:37.423605 ==
5743 12:20:37.425908 Dram Type= 6, Freq= 0, CH_1, rank 1
5744 12:20:37.429361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 12:20:37.429779 ==
5746 12:20:37.433046 [Gating] SW mode calibration
5747 12:20:37.439500 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5748 12:20:37.445765 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5749 12:20:37.449556 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 12:20:37.455866 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 12:20:37.459121 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 12:20:37.462217 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 12:20:37.469414 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 12:20:37.472682 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 12:20:37.476005 0 14 24 | B1->B0 | 2c2c 3131 | 0 1 | (0 1) (1 1)
5756 12:20:37.479309 0 14 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 1)
5757 12:20:37.485992 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 12:20:37.489094 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 12:20:37.492435 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 12:20:37.499149 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 12:20:37.502907 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 12:20:37.505923 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 12:20:37.512415 0 15 24 | B1->B0 | 3737 2b2b | 0 0 | (0 0) (0 0)
5764 12:20:37.515538 0 15 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5765 12:20:37.518812 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 12:20:37.525817 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 12:20:37.528610 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 12:20:37.532083 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 12:20:37.539276 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 12:20:37.542179 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 12:20:37.545409 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5772 12:20:37.552005 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5773 12:20:37.555457 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 12:20:37.558731 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 12:20:37.565380 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 12:20:37.568888 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 12:20:37.572032 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 12:20:37.578594 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 12:20:37.582153 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 12:20:37.585364 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 12:20:37.592239 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 12:20:37.595716 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 12:20:37.598931 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 12:20:37.605758 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 12:20:37.608554 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 12:20:37.611812 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 12:20:37.618491 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5788 12:20:37.622262 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5789 12:20:37.625171 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 12:20:37.628689 Total UI for P1: 0, mck2ui 16
5791 12:20:37.631756 best dqsien dly found for B0: ( 1, 2, 28)
5792 12:20:37.635595 Total UI for P1: 0, mck2ui 16
5793 12:20:37.638398 best dqsien dly found for B1: ( 1, 2, 26)
5794 12:20:37.642057 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5795 12:20:37.645316 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5796 12:20:37.645886
5797 12:20:37.648676 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5798 12:20:37.655239 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5799 12:20:37.655673 [Gating] SW calibration Done
5800 12:20:37.656040 ==
5801 12:20:37.658479 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 12:20:37.664907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 12:20:37.665473 ==
5804 12:20:37.665929 RX Vref Scan: 0
5805 12:20:37.666267
5806 12:20:37.668262 RX Vref 0 -> 0, step: 1
5807 12:20:37.668808
5808 12:20:37.671414 RX Delay -80 -> 252, step: 8
5809 12:20:37.674892 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5810 12:20:37.678040 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5811 12:20:37.681673 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5812 12:20:37.685364 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5813 12:20:37.691511 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5814 12:20:37.694624 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5815 12:20:37.698294 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5816 12:20:37.701441 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5817 12:20:37.704602 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5818 12:20:37.708423 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5819 12:20:37.714682 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5820 12:20:37.717863 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5821 12:20:37.721264 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5822 12:20:37.725096 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5823 12:20:37.728120 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5824 12:20:37.734636 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5825 12:20:37.735065 ==
5826 12:20:37.738086 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 12:20:37.741271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 12:20:37.741853 ==
5829 12:20:37.742341 DQS Delay:
5830 12:20:37.744915 DQS0 = 0, DQS1 = 0
5831 12:20:37.745347 DQM Delay:
5832 12:20:37.747975 DQM0 = 102, DQM1 = 97
5833 12:20:37.748608 DQ Delay:
5834 12:20:37.751489 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5835 12:20:37.754253 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5836 12:20:37.758025 DQ8 =83, DQ9 =91, DQ10 =99, DQ11 =91
5837 12:20:37.761450 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5838 12:20:37.762018
5839 12:20:37.762497
5840 12:20:37.763001 ==
5841 12:20:37.764490 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 12:20:37.771051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 12:20:37.771578 ==
5844 12:20:37.771946
5845 12:20:37.772334
5846 12:20:37.772667 TX Vref Scan disable
5847 12:20:37.774908 == TX Byte 0 ==
5848 12:20:37.778014 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5849 12:20:37.781072 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5850 12:20:37.784422 == TX Byte 1 ==
5851 12:20:37.788238 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5852 12:20:37.794924 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5853 12:20:37.795489 ==
5854 12:20:37.797500 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 12:20:37.801489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 12:20:37.801922 ==
5857 12:20:37.802274
5858 12:20:37.802592
5859 12:20:37.804711 TX Vref Scan disable
5860 12:20:37.805141 == TX Byte 0 ==
5861 12:20:37.811221 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5862 12:20:37.814438 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5863 12:20:37.814877 == TX Byte 1 ==
5864 12:20:37.820883 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5865 12:20:37.824642 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5866 12:20:37.825080
5867 12:20:37.825436 [DATLAT]
5868 12:20:37.827855 Freq=933, CH1 RK1
5869 12:20:37.828256
5870 12:20:37.828815 DATLAT Default: 0xb
5871 12:20:37.830968 0, 0xFFFF, sum = 0
5872 12:20:37.831412 1, 0xFFFF, sum = 0
5873 12:20:37.834592 2, 0xFFFF, sum = 0
5874 12:20:37.835043 3, 0xFFFF, sum = 0
5875 12:20:37.837886 4, 0xFFFF, sum = 0
5876 12:20:37.838327 5, 0xFFFF, sum = 0
5877 12:20:37.841192 6, 0xFFFF, sum = 0
5878 12:20:37.841644 7, 0xFFFF, sum = 0
5879 12:20:37.844392 8, 0xFFFF, sum = 0
5880 12:20:37.848042 9, 0xFFFF, sum = 0
5881 12:20:37.848578 10, 0x0, sum = 1
5882 12:20:37.848997 11, 0x0, sum = 2
5883 12:20:37.851054 12, 0x0, sum = 3
5884 12:20:37.851638 13, 0x0, sum = 4
5885 12:20:37.854176 best_step = 11
5886 12:20:37.854642
5887 12:20:37.855066 ==
5888 12:20:37.857365 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 12:20:37.860725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 12:20:37.861220 ==
5891 12:20:37.864275 RX Vref Scan: 0
5892 12:20:37.864802
5893 12:20:37.865214 RX Vref 0 -> 0, step: 1
5894 12:20:37.865614
5895 12:20:37.867459 RX Delay -53 -> 252, step: 4
5896 12:20:37.874734 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5897 12:20:37.877774 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5898 12:20:37.881582 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5899 12:20:37.884510 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5900 12:20:37.887806 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5901 12:20:37.894537 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5902 12:20:37.897785 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5903 12:20:37.901768 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5904 12:20:37.904580 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5905 12:20:37.908049 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5906 12:20:37.914732 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5907 12:20:37.917884 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5908 12:20:37.921061 iDelay=203, Bit 12, Center 106 (19 ~ 194) 176
5909 12:20:37.924363 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5910 12:20:37.928148 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5911 12:20:37.937519 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5912 12:20:37.937942 ==
5913 12:20:37.938607 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 12:20:37.940864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 12:20:37.941293 ==
5916 12:20:37.941623 DQS Delay:
5917 12:20:37.944577 DQS0 = 0, DQS1 = 0
5918 12:20:37.944997 DQM Delay:
5919 12:20:37.947662 DQM0 = 104, DQM1 = 100
5920 12:20:37.948076 DQ Delay:
5921 12:20:37.950826 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5922 12:20:37.954008 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5923 12:20:37.958371 DQ8 =90, DQ9 =90, DQ10 =102, DQ11 =92
5924 12:20:37.960823 DQ12 =106, DQ13 =106, DQ14 =106, DQ15 =108
5925 12:20:37.961237
5926 12:20:37.961559
5927 12:20:37.971042 [DQSOSCAuto] RK1, (LSB)MR18= 0x28fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 409 ps
5928 12:20:37.974298 CH1 RK1: MR19=504, MR18=28FC
5929 12:20:37.977794 CH1_RK1: MR19=0x504, MR18=0x28FC, DQSOSC=409, MR23=63, INC=64, DEC=43
5930 12:20:37.980797 [RxdqsGatingPostProcess] freq 933
5931 12:20:37.987486 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5932 12:20:37.990829 best DQS0 dly(2T, 0.5T) = (0, 10)
5933 12:20:37.994280 best DQS1 dly(2T, 0.5T) = (0, 10)
5934 12:20:37.997609 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5935 12:20:38.000891 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5936 12:20:38.003945 best DQS0 dly(2T, 0.5T) = (0, 10)
5937 12:20:38.007471 best DQS1 dly(2T, 0.5T) = (0, 10)
5938 12:20:38.010736 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5939 12:20:38.014152 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5940 12:20:38.017211 Pre-setting of DQS Precalculation
5941 12:20:38.020908 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5942 12:20:38.027486 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5943 12:20:38.034437 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5944 12:20:38.034934
5945 12:20:38.035270
5946 12:20:38.037484 [Calibration Summary] 1866 Mbps
5947 12:20:38.040805 CH 0, Rank 0
5948 12:20:38.041362 SW Impedance : PASS
5949 12:20:38.044651 DUTY Scan : NO K
5950 12:20:38.047820 ZQ Calibration : PASS
5951 12:20:38.048258 Jitter Meter : NO K
5952 12:20:38.051006 CBT Training : PASS
5953 12:20:38.054260 Write leveling : PASS
5954 12:20:38.054782 RX DQS gating : PASS
5955 12:20:38.057395 RX DQ/DQS(RDDQC) : PASS
5956 12:20:38.060802 TX DQ/DQS : PASS
5957 12:20:38.061244 RX DATLAT : PASS
5958 12:20:38.063913 RX DQ/DQS(Engine): PASS
5959 12:20:38.064396 TX OE : NO K
5960 12:20:38.067656 All Pass.
5961 12:20:38.068091
5962 12:20:38.068562 CH 0, Rank 1
5963 12:20:38.070980 SW Impedance : PASS
5964 12:20:38.071423 DUTY Scan : NO K
5965 12:20:38.074124 ZQ Calibration : PASS
5966 12:20:38.077492 Jitter Meter : NO K
5967 12:20:38.077946 CBT Training : PASS
5968 12:20:38.080592 Write leveling : PASS
5969 12:20:38.083753 RX DQS gating : PASS
5970 12:20:38.084348 RX DQ/DQS(RDDQC) : PASS
5971 12:20:38.087373 TX DQ/DQS : PASS
5972 12:20:38.090809 RX DATLAT : PASS
5973 12:20:38.091244 RX DQ/DQS(Engine): PASS
5974 12:20:38.094417 TX OE : NO K
5975 12:20:38.094854 All Pass.
5976 12:20:38.095212
5977 12:20:38.097343 CH 1, Rank 0
5978 12:20:38.097784 SW Impedance : PASS
5979 12:20:38.100551 DUTY Scan : NO K
5980 12:20:38.104352 ZQ Calibration : PASS
5981 12:20:38.104793 Jitter Meter : NO K
5982 12:20:38.107131 CBT Training : PASS
5983 12:20:38.107597 Write leveling : PASS
5984 12:20:38.110790 RX DQS gating : PASS
5985 12:20:38.114050 RX DQ/DQS(RDDQC) : PASS
5986 12:20:38.114466 TX DQ/DQS : PASS
5987 12:20:38.117254 RX DATLAT : PASS
5988 12:20:38.120816 RX DQ/DQS(Engine): PASS
5989 12:20:38.121234 TX OE : NO K
5990 12:20:38.123712 All Pass.
5991 12:20:38.124127
5992 12:20:38.124490 CH 1, Rank 1
5993 12:20:38.127351 SW Impedance : PASS
5994 12:20:38.127824 DUTY Scan : NO K
5995 12:20:38.130380 ZQ Calibration : PASS
5996 12:20:38.133998 Jitter Meter : NO K
5997 12:20:38.134417 CBT Training : PASS
5998 12:20:38.137091 Write leveling : PASS
5999 12:20:38.140733 RX DQS gating : PASS
6000 12:20:38.141194 RX DQ/DQS(RDDQC) : PASS
6001 12:20:38.143969 TX DQ/DQS : PASS
6002 12:20:38.147307 RX DATLAT : PASS
6003 12:20:38.147849 RX DQ/DQS(Engine): PASS
6004 12:20:38.150656 TX OE : NO K
6005 12:20:38.151067 All Pass.
6006 12:20:38.151386
6007 12:20:38.153854 DramC Write-DBI off
6008 12:20:38.157026 PER_BANK_REFRESH: Hybrid Mode
6009 12:20:38.157435 TX_TRACKING: ON
6010 12:20:38.167261 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6011 12:20:38.170405 [FAST_K] Save calibration result to emmc
6012 12:20:38.173741 dramc_set_vcore_voltage set vcore to 650000
6013 12:20:38.177561 Read voltage for 400, 6
6014 12:20:38.177969 Vio18 = 0
6015 12:20:38.178290 Vcore = 650000
6016 12:20:38.180960 Vdram = 0
6017 12:20:38.181531 Vddq = 0
6018 12:20:38.182018 Vmddr = 0
6019 12:20:38.187225 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6020 12:20:38.190412 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6021 12:20:38.193996 MEM_TYPE=3, freq_sel=20
6022 12:20:38.196958 sv_algorithm_assistance_LP4_800
6023 12:20:38.200393 ============ PULL DRAM RESETB DOWN ============
6024 12:20:38.204002 ========== PULL DRAM RESETB DOWN end =========
6025 12:20:38.210443 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6026 12:20:38.213771 ===================================
6027 12:20:38.214154 LPDDR4 DRAM CONFIGURATION
6028 12:20:38.217044 ===================================
6029 12:20:38.220402 EX_ROW_EN[0] = 0x0
6030 12:20:38.220832 EX_ROW_EN[1] = 0x0
6031 12:20:38.223641 LP4Y_EN = 0x0
6032 12:20:38.227519 WORK_FSP = 0x0
6033 12:20:38.227949 WL = 0x2
6034 12:20:38.230414 RL = 0x2
6035 12:20:38.230890 BL = 0x2
6036 12:20:38.233510 RPST = 0x0
6037 12:20:38.233940 RD_PRE = 0x0
6038 12:20:38.237124 WR_PRE = 0x1
6039 12:20:38.237569 WR_PST = 0x0
6040 12:20:38.240514 DBI_WR = 0x0
6041 12:20:38.240940 DBI_RD = 0x0
6042 12:20:38.243513 OTF = 0x1
6043 12:20:38.246931 ===================================
6044 12:20:38.250172 ===================================
6045 12:20:38.250624 ANA top config
6046 12:20:38.253442 ===================================
6047 12:20:38.257213 DLL_ASYNC_EN = 0
6048 12:20:38.260503 ALL_SLAVE_EN = 1
6049 12:20:38.261062 NEW_RANK_MODE = 1
6050 12:20:38.263459 DLL_IDLE_MODE = 1
6051 12:20:38.266840 LP45_APHY_COMB_EN = 1
6052 12:20:38.270035 TX_ODT_DIS = 1
6053 12:20:38.273311 NEW_8X_MODE = 1
6054 12:20:38.276525 ===================================
6055 12:20:38.280230 ===================================
6056 12:20:38.280721 data_rate = 800
6057 12:20:38.283458 CKR = 1
6058 12:20:38.286822 DQ_P2S_RATIO = 4
6059 12:20:38.290196 ===================================
6060 12:20:38.293480 CA_P2S_RATIO = 4
6061 12:20:38.296623 DQ_CA_OPEN = 0
6062 12:20:38.299876 DQ_SEMI_OPEN = 1
6063 12:20:38.300384 CA_SEMI_OPEN = 1
6064 12:20:38.303475 CA_FULL_RATE = 0
6065 12:20:38.306556 DQ_CKDIV4_EN = 0
6066 12:20:38.309813 CA_CKDIV4_EN = 1
6067 12:20:38.313114 CA_PREDIV_EN = 0
6068 12:20:38.316787 PH8_DLY = 0
6069 12:20:38.317216 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6070 12:20:38.319818 DQ_AAMCK_DIV = 0
6071 12:20:38.323717 CA_AAMCK_DIV = 0
6072 12:20:38.327054 CA_ADMCK_DIV = 4
6073 12:20:38.329526 DQ_TRACK_CA_EN = 0
6074 12:20:38.333358 CA_PICK = 800
6075 12:20:38.336384 CA_MCKIO = 400
6076 12:20:38.336993 MCKIO_SEMI = 400
6077 12:20:38.339943 PLL_FREQ = 3016
6078 12:20:38.343007 DQ_UI_PI_RATIO = 32
6079 12:20:38.346331 CA_UI_PI_RATIO = 32
6080 12:20:38.349584 ===================================
6081 12:20:38.353571 ===================================
6082 12:20:38.356654 memory_type:LPDDR4
6083 12:20:38.357091 GP_NUM : 10
6084 12:20:38.359987 SRAM_EN : 1
6085 12:20:38.363240 MD32_EN : 0
6086 12:20:38.366227 ===================================
6087 12:20:38.366659 [ANA_INIT] >>>>>>>>>>>>>>
6088 12:20:38.369889 <<<<<< [CONFIGURE PHASE]: ANA_TX
6089 12:20:38.373144 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6090 12:20:38.376390 ===================================
6091 12:20:38.379513 data_rate = 800,PCW = 0X7400
6092 12:20:38.382774 ===================================
6093 12:20:38.386092 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6094 12:20:38.393470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6095 12:20:38.403240 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6096 12:20:38.406669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6097 12:20:38.409652 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6098 12:20:38.413003 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6099 12:20:38.416676 [ANA_INIT] flow start
6100 12:20:38.419581 [ANA_INIT] PLL >>>>>>>>
6101 12:20:38.420147 [ANA_INIT] PLL <<<<<<<<
6102 12:20:38.423121 [ANA_INIT] MIDPI >>>>>>>>
6103 12:20:38.426261 [ANA_INIT] MIDPI <<<<<<<<
6104 12:20:38.429480 [ANA_INIT] DLL >>>>>>>>
6105 12:20:38.429923 [ANA_INIT] flow end
6106 12:20:38.432737 ============ LP4 DIFF to SE enter ============
6107 12:20:38.439645 ============ LP4 DIFF to SE exit ============
6108 12:20:38.440078 [ANA_INIT] <<<<<<<<<<<<<
6109 12:20:38.442751 [Flow] Enable top DCM control >>>>>
6110 12:20:38.446018 [Flow] Enable top DCM control <<<<<
6111 12:20:38.449455 Enable DLL master slave shuffle
6112 12:20:38.456172 ==============================================================
6113 12:20:38.456825 Gating Mode config
6114 12:20:38.462474 ==============================================================
6115 12:20:38.466237 Config description:
6116 12:20:38.475699 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6117 12:20:38.482337 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6118 12:20:38.485866 SELPH_MODE 0: By rank 1: By Phase
6119 12:20:38.492459 ==============================================================
6120 12:20:38.495616 GAT_TRACK_EN = 0
6121 12:20:38.498937 RX_GATING_MODE = 2
6122 12:20:38.499351 RX_GATING_TRACK_MODE = 2
6123 12:20:38.502226 SELPH_MODE = 1
6124 12:20:38.505466 PICG_EARLY_EN = 1
6125 12:20:38.508798 VALID_LAT_VALUE = 1
6126 12:20:38.515545 ==============================================================
6127 12:20:38.519034 Enter into Gating configuration >>>>
6128 12:20:38.522383 Exit from Gating configuration <<<<
6129 12:20:38.525791 Enter into DVFS_PRE_config >>>>>
6130 12:20:38.535322 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6131 12:20:38.538574 Exit from DVFS_PRE_config <<<<<
6132 12:20:38.542240 Enter into PICG configuration >>>>
6133 12:20:38.545698 Exit from PICG configuration <<<<
6134 12:20:38.548717 [RX_INPUT] configuration >>>>>
6135 12:20:38.552085 [RX_INPUT] configuration <<<<<
6136 12:20:38.555587 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6137 12:20:38.561834 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6138 12:20:38.568705 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6139 12:20:38.575659 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6140 12:20:38.578639 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6141 12:20:38.585125 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6142 12:20:38.588442 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6143 12:20:38.595664 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6144 12:20:38.598955 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6145 12:20:38.601945 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6146 12:20:38.605305 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6147 12:20:38.611829 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6148 12:20:38.614986 ===================================
6149 12:20:38.615429 LPDDR4 DRAM CONFIGURATION
6150 12:20:38.618265 ===================================
6151 12:20:38.622317 EX_ROW_EN[0] = 0x0
6152 12:20:38.625417 EX_ROW_EN[1] = 0x0
6153 12:20:38.625856 LP4Y_EN = 0x0
6154 12:20:38.628353 WORK_FSP = 0x0
6155 12:20:38.628970 WL = 0x2
6156 12:20:38.631815 RL = 0x2
6157 12:20:38.632359 BL = 0x2
6158 12:20:38.635212 RPST = 0x0
6159 12:20:38.635603 RD_PRE = 0x0
6160 12:20:38.638302 WR_PRE = 0x1
6161 12:20:38.638746 WR_PST = 0x0
6162 12:20:38.641603 DBI_WR = 0x0
6163 12:20:38.642050 DBI_RD = 0x0
6164 12:20:38.645393 OTF = 0x1
6165 12:20:38.648552 ===================================
6166 12:20:38.651674 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6167 12:20:38.655216 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6168 12:20:38.661950 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6169 12:20:38.665118 ===================================
6170 12:20:38.665575 LPDDR4 DRAM CONFIGURATION
6171 12:20:38.668275 ===================================
6172 12:20:38.671865 EX_ROW_EN[0] = 0x10
6173 12:20:38.674932 EX_ROW_EN[1] = 0x0
6174 12:20:38.675372 LP4Y_EN = 0x0
6175 12:20:38.678450 WORK_FSP = 0x0
6176 12:20:38.678980 WL = 0x2
6177 12:20:38.681573 RL = 0x2
6178 12:20:38.682023 BL = 0x2
6179 12:20:38.684836 RPST = 0x0
6180 12:20:38.685280 RD_PRE = 0x0
6181 12:20:38.688452 WR_PRE = 0x1
6182 12:20:38.688902 WR_PST = 0x0
6183 12:20:38.691674 DBI_WR = 0x0
6184 12:20:38.692092 DBI_RD = 0x0
6185 12:20:38.695194 OTF = 0x1
6186 12:20:38.698666 ===================================
6187 12:20:38.705208 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6188 12:20:38.708420 nWR fixed to 30
6189 12:20:38.708858 [ModeRegInit_LP4] CH0 RK0
6190 12:20:38.711637 [ModeRegInit_LP4] CH0 RK1
6191 12:20:38.715090 [ModeRegInit_LP4] CH1 RK0
6192 12:20:38.715501 [ModeRegInit_LP4] CH1 RK1
6193 12:20:38.718323 match AC timing 19
6194 12:20:38.721540 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6195 12:20:38.725464 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6196 12:20:38.732095 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6197 12:20:38.735169 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6198 12:20:38.741538 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6199 12:20:38.741974 ==
6200 12:20:38.745148 Dram Type= 6, Freq= 0, CH_0, rank 0
6201 12:20:38.748103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6202 12:20:38.748587 ==
6203 12:20:38.755280 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6204 12:20:38.761482 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6205 12:20:38.761919 [CA 0] Center 36 (8~64) winsize 57
6206 12:20:38.764954 [CA 1] Center 36 (8~64) winsize 57
6207 12:20:38.767720 [CA 2] Center 36 (8~64) winsize 57
6208 12:20:38.771548 [CA 3] Center 36 (8~64) winsize 57
6209 12:20:38.774787 [CA 4] Center 36 (8~64) winsize 57
6210 12:20:38.778162 [CA 5] Center 36 (8~64) winsize 57
6211 12:20:38.778594
6212 12:20:38.781344 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6213 12:20:38.781826
6214 12:20:38.784909 [CATrainingPosCal] consider 1 rank data
6215 12:20:38.788379 u2DelayCellTimex100 = 270/100 ps
6216 12:20:38.791510 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 12:20:38.794620 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 12:20:38.801402 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 12:20:38.804746 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 12:20:38.807931 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 12:20:38.811209 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 12:20:38.811663
6223 12:20:38.814769 CA PerBit enable=1, Macro0, CA PI delay=36
6224 12:20:38.815335
6225 12:20:38.818138 [CBTSetCACLKResult] CA Dly = 36
6226 12:20:38.818610 CS Dly: 1 (0~32)
6227 12:20:38.818946 ==
6228 12:20:38.821001 Dram Type= 6, Freq= 0, CH_0, rank 1
6229 12:20:38.828098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6230 12:20:38.828581 ==
6231 12:20:38.831290 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6232 12:20:38.837649 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6233 12:20:38.841147 [CA 0] Center 36 (8~64) winsize 57
6234 12:20:38.844452 [CA 1] Center 36 (8~64) winsize 57
6235 12:20:38.847525 [CA 2] Center 36 (8~64) winsize 57
6236 12:20:38.851047 [CA 3] Center 36 (8~64) winsize 57
6237 12:20:38.854610 [CA 4] Center 36 (8~64) winsize 57
6238 12:20:38.857647 [CA 5] Center 36 (8~64) winsize 57
6239 12:20:38.858063
6240 12:20:38.861167 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6241 12:20:38.861584
6242 12:20:38.864688 [CATrainingPosCal] consider 2 rank data
6243 12:20:38.868009 u2DelayCellTimex100 = 270/100 ps
6244 12:20:38.871323 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 12:20:38.874725 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 12:20:38.877669 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 12:20:38.881155 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 12:20:38.884589 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 12:20:38.891002 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 12:20:38.891422
6251 12:20:38.894639 CA PerBit enable=1, Macro0, CA PI delay=36
6252 12:20:38.895055
6253 12:20:38.897883 [CBTSetCACLKResult] CA Dly = 36
6254 12:20:38.898300 CS Dly: 1 (0~32)
6255 12:20:38.898631
6256 12:20:38.901123 ----->DramcWriteLeveling(PI) begin...
6257 12:20:38.901551 ==
6258 12:20:38.904169 Dram Type= 6, Freq= 0, CH_0, rank 0
6259 12:20:38.907907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 12:20:38.911013 ==
6261 12:20:38.911426 Write leveling (Byte 0): 40 => 8
6262 12:20:38.914420 Write leveling (Byte 1): 40 => 8
6263 12:20:38.917629 DramcWriteLeveling(PI) end<-----
6264 12:20:38.918046
6265 12:20:38.918372 ==
6266 12:20:38.920908 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 12:20:38.927342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 12:20:38.927763 ==
6269 12:20:38.928174 [Gating] SW mode calibration
6270 12:20:38.937716 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6271 12:20:38.940824 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6272 12:20:38.947472 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 12:20:38.950439 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 12:20:38.954154 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 12:20:38.957074 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 12:20:38.963745 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 12:20:38.967408 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 12:20:38.970646 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 12:20:38.977167 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 12:20:38.980469 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 12:20:38.983761 Total UI for P1: 0, mck2ui 16
6282 12:20:38.987359 best dqsien dly found for B0: ( 0, 14, 24)
6283 12:20:38.990868 Total UI for P1: 0, mck2ui 16
6284 12:20:38.993585 best dqsien dly found for B1: ( 0, 14, 24)
6285 12:20:38.997518 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6286 12:20:39.000666 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6287 12:20:39.001106
6288 12:20:39.003953 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6289 12:20:39.007014 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6290 12:20:39.010609 [Gating] SW calibration Done
6291 12:20:39.011090 ==
6292 12:20:39.013904 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 12:20:39.020159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 12:20:39.020637 ==
6295 12:20:39.020967 RX Vref Scan: 0
6296 12:20:39.021272
6297 12:20:39.023541 RX Vref 0 -> 0, step: 1
6298 12:20:39.023953
6299 12:20:39.027502 RX Delay -410 -> 252, step: 16
6300 12:20:39.030664 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6301 12:20:39.033965 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6302 12:20:39.040377 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6303 12:20:39.043684 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6304 12:20:39.047032 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6305 12:20:39.050196 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6306 12:20:39.056802 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6307 12:20:39.060338 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6308 12:20:39.063614 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6309 12:20:39.067162 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6310 12:20:39.073635 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6311 12:20:39.076953 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6312 12:20:39.080024 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6313 12:20:39.083936 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6314 12:20:39.089870 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6315 12:20:39.093208 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6316 12:20:39.093622 ==
6317 12:20:39.096366 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 12:20:39.100032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 12:20:39.100492 ==
6320 12:20:39.103478 DQS Delay:
6321 12:20:39.103887 DQS0 = 27, DQS1 = 35
6322 12:20:39.106552 DQM Delay:
6323 12:20:39.106966 DQM0 = 11, DQM1 = 12
6324 12:20:39.107405 DQ Delay:
6325 12:20:39.110069 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6326 12:20:39.113585 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6327 12:20:39.116574 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6328 12:20:39.120123 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6329 12:20:39.120587
6330 12:20:39.120913
6331 12:20:39.121217 ==
6332 12:20:39.123393 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 12:20:39.126441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 12:20:39.129683 ==
6335 12:20:39.130096
6336 12:20:39.130420
6337 12:20:39.130723 TX Vref Scan disable
6338 12:20:39.133346 == TX Byte 0 ==
6339 12:20:39.136936 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6340 12:20:39.139989 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6341 12:20:39.143353 == TX Byte 1 ==
6342 12:20:39.146505 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 12:20:39.149960 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 12:20:39.150401 ==
6345 12:20:39.153279 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 12:20:39.156485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 12:20:39.159870 ==
6348 12:20:39.160273
6349 12:20:39.160634
6350 12:20:39.160995 TX Vref Scan disable
6351 12:20:39.163538 == TX Byte 0 ==
6352 12:20:39.166440 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 12:20:39.170021 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 12:20:39.172977 == TX Byte 1 ==
6355 12:20:39.176439 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 12:20:39.179483 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 12:20:39.179906
6358 12:20:39.182742 [DATLAT]
6359 12:20:39.183144 Freq=400, CH0 RK0
6360 12:20:39.183463
6361 12:20:39.186652 DATLAT Default: 0xf
6362 12:20:39.187056 0, 0xFFFF, sum = 0
6363 12:20:39.189926 1, 0xFFFF, sum = 0
6364 12:20:39.190341 2, 0xFFFF, sum = 0
6365 12:20:39.193122 3, 0xFFFF, sum = 0
6366 12:20:39.193537 4, 0xFFFF, sum = 0
6367 12:20:39.196334 5, 0xFFFF, sum = 0
6368 12:20:39.196777 6, 0xFFFF, sum = 0
6369 12:20:39.199551 7, 0xFFFF, sum = 0
6370 12:20:39.199964 8, 0xFFFF, sum = 0
6371 12:20:39.202985 9, 0xFFFF, sum = 0
6372 12:20:39.203404 10, 0xFFFF, sum = 0
6373 12:20:39.206433 11, 0xFFFF, sum = 0
6374 12:20:39.209354 12, 0xFFFF, sum = 0
6375 12:20:39.209776 13, 0x0, sum = 1
6376 12:20:39.210109 14, 0x0, sum = 2
6377 12:20:39.213212 15, 0x0, sum = 3
6378 12:20:39.213642 16, 0x0, sum = 4
6379 12:20:39.216080 best_step = 14
6380 12:20:39.216535
6381 12:20:39.217013 ==
6382 12:20:39.219841 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 12:20:39.222650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 12:20:39.223203 ==
6385 12:20:39.226184 RX Vref Scan: 1
6386 12:20:39.226592
6387 12:20:39.226910 RX Vref 0 -> 0, step: 1
6388 12:20:39.227209
6389 12:20:39.229510 RX Delay -311 -> 252, step: 8
6390 12:20:39.229936
6391 12:20:39.232939 Set Vref, RX VrefLevel [Byte0]: 55
6392 12:20:39.236149 [Byte1]: 50
6393 12:20:39.241165
6394 12:20:39.241573 Final RX Vref Byte 0 = 55 to rank0
6395 12:20:39.244098 Final RX Vref Byte 1 = 50 to rank0
6396 12:20:39.247293 Final RX Vref Byte 0 = 55 to rank1
6397 12:20:39.250916 Final RX Vref Byte 1 = 50 to rank1==
6398 12:20:39.254005 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 12:20:39.260786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 12:20:39.261200 ==
6401 12:20:39.261523 DQS Delay:
6402 12:20:39.264021 DQS0 = 28, DQS1 = 36
6403 12:20:39.264573 DQM Delay:
6404 12:20:39.264904 DQM0 = 11, DQM1 = 13
6405 12:20:39.267200 DQ Delay:
6406 12:20:39.270912 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6407 12:20:39.271340 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6408 12:20:39.274138 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6409 12:20:39.277147 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6410 12:20:39.277556
6411 12:20:39.280621
6412 12:20:39.287019 [DQSOSCAuto] RK0, (LSB)MR18= 0xc6b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6413 12:20:39.290753 CH0 RK0: MR19=C0C, MR18=C6B3
6414 12:20:39.296953 CH0_RK0: MR19=0xC0C, MR18=0xC6B3, DQSOSC=385, MR23=63, INC=398, DEC=265
6415 12:20:39.297367 ==
6416 12:20:39.300333 Dram Type= 6, Freq= 0, CH_0, rank 1
6417 12:20:39.304184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 12:20:39.304668 ==
6419 12:20:39.307616 [Gating] SW mode calibration
6420 12:20:39.314142 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6421 12:20:39.320234 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6422 12:20:39.323837 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6423 12:20:39.327454 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 12:20:39.330397 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 12:20:39.336862 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 12:20:39.340768 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 12:20:39.343842 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 12:20:39.350295 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 12:20:39.353429 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 12:20:39.357048 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 12:20:39.359972 Total UI for P1: 0, mck2ui 16
6432 12:20:39.363431 best dqsien dly found for B0: ( 0, 14, 24)
6433 12:20:39.366814 Total UI for P1: 0, mck2ui 16
6434 12:20:39.370088 best dqsien dly found for B1: ( 0, 14, 24)
6435 12:20:39.373718 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6436 12:20:39.380462 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6437 12:20:39.380888
6438 12:20:39.383412 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6439 12:20:39.386696 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6440 12:20:39.390293 [Gating] SW calibration Done
6441 12:20:39.390704 ==
6442 12:20:39.393359 Dram Type= 6, Freq= 0, CH_0, rank 1
6443 12:20:39.396889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 12:20:39.397299 ==
6445 12:20:39.400160 RX Vref Scan: 0
6446 12:20:39.400599
6447 12:20:39.400924 RX Vref 0 -> 0, step: 1
6448 12:20:39.401229
6449 12:20:39.403295 RX Delay -410 -> 252, step: 16
6450 12:20:39.406811 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6451 12:20:39.413122 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6452 12:20:39.417055 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6453 12:20:39.420044 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6454 12:20:39.422983 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6455 12:20:39.430467 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6456 12:20:39.433429 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6457 12:20:39.436520 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6458 12:20:39.439881 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6459 12:20:39.446329 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6460 12:20:39.450223 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6461 12:20:39.453589 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6462 12:20:39.456618 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6463 12:20:39.462994 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6464 12:20:39.466390 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6465 12:20:39.470144 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6466 12:20:39.470553 ==
6467 12:20:39.473418 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 12:20:39.479539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 12:20:39.480185 ==
6470 12:20:39.480732 DQS Delay:
6471 12:20:39.482669 DQS0 = 27, DQS1 = 35
6472 12:20:39.483361 DQM Delay:
6473 12:20:39.483735 DQM0 = 11, DQM1 = 11
6474 12:20:39.486410 DQ Delay:
6475 12:20:39.489637 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6476 12:20:39.490400 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6477 12:20:39.493128 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6478 12:20:39.496376 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6479 12:20:39.496793
6480 12:20:39.497121
6481 12:20:39.499495 ==
6482 12:20:39.503223 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 12:20:39.506657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 12:20:39.507172 ==
6485 12:20:39.507587
6486 12:20:39.507902
6487 12:20:39.509639 TX Vref Scan disable
6488 12:20:39.510049 == TX Byte 0 ==
6489 12:20:39.513658 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6490 12:20:39.520163 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6491 12:20:39.520627 == TX Byte 1 ==
6492 12:20:39.523206 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6493 12:20:39.529627 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6494 12:20:39.530039 ==
6495 12:20:39.533240 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 12:20:39.537031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 12:20:39.537443 ==
6498 12:20:39.537768
6499 12:20:39.538065
6500 12:20:39.539428 TX Vref Scan disable
6501 12:20:39.539836 == TX Byte 0 ==
6502 12:20:39.542837 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6503 12:20:39.549291 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6504 12:20:39.549704 == TX Byte 1 ==
6505 12:20:39.553064 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6506 12:20:39.559248 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6507 12:20:39.559657
6508 12:20:39.559980 [DATLAT]
6509 12:20:39.560380 Freq=400, CH0 RK1
6510 12:20:39.560893
6511 12:20:39.562697 DATLAT Default: 0xe
6512 12:20:39.566115 0, 0xFFFF, sum = 0
6513 12:20:39.566570 1, 0xFFFF, sum = 0
6514 12:20:39.569175 2, 0xFFFF, sum = 0
6515 12:20:39.569589 3, 0xFFFF, sum = 0
6516 12:20:39.572380 4, 0xFFFF, sum = 0
6517 12:20:39.572840 5, 0xFFFF, sum = 0
6518 12:20:39.576336 6, 0xFFFF, sum = 0
6519 12:20:39.576772 7, 0xFFFF, sum = 0
6520 12:20:39.579471 8, 0xFFFF, sum = 0
6521 12:20:39.579888 9, 0xFFFF, sum = 0
6522 12:20:39.582720 10, 0xFFFF, sum = 0
6523 12:20:39.583135 11, 0xFFFF, sum = 0
6524 12:20:39.586005 12, 0xFFFF, sum = 0
6525 12:20:39.586442 13, 0x0, sum = 1
6526 12:20:39.589263 14, 0x0, sum = 2
6527 12:20:39.589680 15, 0x0, sum = 3
6528 12:20:39.592482 16, 0x0, sum = 4
6529 12:20:39.592934 best_step = 14
6530 12:20:39.593291
6531 12:20:39.593595 ==
6532 12:20:39.595829 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 12:20:39.598934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 12:20:39.602717 ==
6535 12:20:39.603128 RX Vref Scan: 0
6536 12:20:39.603451
6537 12:20:39.605868 RX Vref 0 -> 0, step: 1
6538 12:20:39.606278
6539 12:20:39.609328 RX Delay -311 -> 252, step: 8
6540 12:20:39.612841 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6541 12:20:39.619444 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6542 12:20:39.622241 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6543 12:20:39.625674 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6544 12:20:39.629002 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6545 12:20:39.635782 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6546 12:20:39.639386 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6547 12:20:39.642463 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6548 12:20:39.645647 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6549 12:20:39.652266 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6550 12:20:39.656074 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6551 12:20:39.659101 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6552 12:20:39.662477 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6553 12:20:39.668901 iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432
6554 12:20:39.672614 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6555 12:20:39.676017 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6556 12:20:39.676482 ==
6557 12:20:39.679367 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 12:20:39.682746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 12:20:39.685988 ==
6560 12:20:39.686427 DQS Delay:
6561 12:20:39.686849 DQS0 = 24, DQS1 = 32
6562 12:20:39.689307 DQM Delay:
6563 12:20:39.689659 DQM0 = 8, DQM1 = 10
6564 12:20:39.692656 DQ Delay:
6565 12:20:39.693126 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6566 12:20:39.695736 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6567 12:20:39.699048 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6568 12:20:39.702499 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =16
6569 12:20:39.702910
6570 12:20:39.703232
6571 12:20:39.712844 [DQSOSCAuto] RK1, (LSB)MR18= 0xb556, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6572 12:20:39.715706 CH0 RK1: MR19=C0C, MR18=B556
6573 12:20:39.719832 CH0_RK1: MR19=0xC0C, MR18=0xB556, DQSOSC=387, MR23=63, INC=394, DEC=262
6574 12:20:39.722663 [RxdqsGatingPostProcess] freq 400
6575 12:20:39.729142 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6576 12:20:39.732590 best DQS0 dly(2T, 0.5T) = (0, 10)
6577 12:20:39.736173 best DQS1 dly(2T, 0.5T) = (0, 10)
6578 12:20:39.738944 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6579 12:20:39.742575 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6580 12:20:39.745567 best DQS0 dly(2T, 0.5T) = (0, 10)
6581 12:20:39.748715 best DQS1 dly(2T, 0.5T) = (0, 10)
6582 12:20:39.752078 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6583 12:20:39.755588 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6584 12:20:39.758819 Pre-setting of DQS Precalculation
6585 12:20:39.762056 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6586 12:20:39.762167 ==
6587 12:20:39.764979 Dram Type= 6, Freq= 0, CH_1, rank 0
6588 12:20:39.768810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 12:20:39.768890 ==
6590 12:20:39.775483 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6591 12:20:39.782163 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6592 12:20:39.785165 [CA 0] Center 36 (8~64) winsize 57
6593 12:20:39.788607 [CA 1] Center 36 (8~64) winsize 57
6594 12:20:39.792026 [CA 2] Center 36 (8~64) winsize 57
6595 12:20:39.795181 [CA 3] Center 36 (8~64) winsize 57
6596 12:20:39.795268 [CA 4] Center 36 (8~64) winsize 57
6597 12:20:39.798522 [CA 5] Center 36 (8~64) winsize 57
6598 12:20:39.798602
6599 12:20:39.805338 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6600 12:20:39.805417
6601 12:20:39.808654 [CATrainingPosCal] consider 1 rank data
6602 12:20:39.812117 u2DelayCellTimex100 = 270/100 ps
6603 12:20:39.815102 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 12:20:39.818894 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 12:20:39.821901 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 12:20:39.825303 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 12:20:39.828520 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 12:20:39.831756 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 12:20:39.831835
6610 12:20:39.835089 CA PerBit enable=1, Macro0, CA PI delay=36
6611 12:20:39.835168
6612 12:20:39.838282 [CBTSetCACLKResult] CA Dly = 36
6613 12:20:39.841469 CS Dly: 1 (0~32)
6614 12:20:39.841548 ==
6615 12:20:39.845380 Dram Type= 6, Freq= 0, CH_1, rank 1
6616 12:20:39.848576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 12:20:39.848663 ==
6618 12:20:39.854764 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6619 12:20:39.861400 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6620 12:20:39.861483 [CA 0] Center 36 (8~64) winsize 57
6621 12:20:39.864956 [CA 1] Center 36 (8~64) winsize 57
6622 12:20:39.867851 [CA 2] Center 36 (8~64) winsize 57
6623 12:20:39.871226 [CA 3] Center 36 (8~64) winsize 57
6624 12:20:39.874698 [CA 4] Center 36 (8~64) winsize 57
6625 12:20:39.877845 [CA 5] Center 36 (8~64) winsize 57
6626 12:20:39.877925
6627 12:20:39.881735 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6628 12:20:39.881815
6629 12:20:39.885083 [CATrainingPosCal] consider 2 rank data
6630 12:20:39.888209 u2DelayCellTimex100 = 270/100 ps
6631 12:20:39.891328 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 12:20:39.898529 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 12:20:39.901196 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 12:20:39.904895 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 12:20:39.907955 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 12:20:39.911086 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 12:20:39.911168
6638 12:20:39.914647 CA PerBit enable=1, Macro0, CA PI delay=36
6639 12:20:39.914725
6640 12:20:39.917832 [CBTSetCACLKResult] CA Dly = 36
6641 12:20:39.921200 CS Dly: 1 (0~32)
6642 12:20:39.921280
6643 12:20:39.924411 ----->DramcWriteLeveling(PI) begin...
6644 12:20:39.924493 ==
6645 12:20:39.927569 Dram Type= 6, Freq= 0, CH_1, rank 0
6646 12:20:39.930816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 12:20:39.930919 ==
6648 12:20:39.934148 Write leveling (Byte 0): 40 => 8
6649 12:20:39.937699 Write leveling (Byte 1): 40 => 8
6650 12:20:39.940814 DramcWriteLeveling(PI) end<-----
6651 12:20:39.940890
6652 12:20:39.940975 ==
6653 12:20:39.944121 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 12:20:39.947854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 12:20:39.947953 ==
6656 12:20:39.951012 [Gating] SW mode calibration
6657 12:20:39.957327 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6658 12:20:39.964581 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6659 12:20:39.967529 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6660 12:20:39.970771 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6661 12:20:39.977570 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 12:20:39.980859 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 12:20:39.984032 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 12:20:39.990385 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 12:20:39.993749 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 12:20:39.997269 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 12:20:40.003938 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 12:20:40.004021 Total UI for P1: 0, mck2ui 16
6669 12:20:40.010760 best dqsien dly found for B0: ( 0, 14, 24)
6670 12:20:40.010839 Total UI for P1: 0, mck2ui 16
6671 12:20:40.013695 best dqsien dly found for B1: ( 0, 14, 24)
6672 12:20:40.020490 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6673 12:20:40.023929 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6674 12:20:40.024008
6675 12:20:40.027185 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6676 12:20:40.030347 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6677 12:20:40.033633 [Gating] SW calibration Done
6678 12:20:40.033713 ==
6679 12:20:40.037058 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 12:20:40.040209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 12:20:40.040349 ==
6682 12:20:40.043478 RX Vref Scan: 0
6683 12:20:40.043593
6684 12:20:40.043685 RX Vref 0 -> 0, step: 1
6685 12:20:40.043772
6686 12:20:40.047099 RX Delay -410 -> 252, step: 16
6687 12:20:40.053977 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6688 12:20:40.056750 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6689 12:20:40.059898 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6690 12:20:40.063666 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6691 12:20:40.070311 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6692 12:20:40.073502 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6693 12:20:40.076721 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6694 12:20:40.080107 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6695 12:20:40.086619 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6696 12:20:40.090285 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6697 12:20:40.093473 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6698 12:20:40.096716 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6699 12:20:40.103051 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6700 12:20:40.106813 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6701 12:20:40.109817 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6702 12:20:40.113610 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6703 12:20:40.113693 ==
6704 12:20:40.116563 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 12:20:40.123521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 12:20:40.123623 ==
6707 12:20:40.123706 DQS Delay:
6708 12:20:40.126623 DQS0 = 35, DQS1 = 35
6709 12:20:40.126698 DQM Delay:
6710 12:20:40.129902 DQM0 = 17, DQM1 = 12
6711 12:20:40.129985 DQ Delay:
6712 12:20:40.133112 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6713 12:20:40.136220 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6714 12:20:40.140008 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6715 12:20:40.143009 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6716 12:20:40.143091
6717 12:20:40.143174
6718 12:20:40.143251 ==
6719 12:20:40.146616 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 12:20:40.149820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 12:20:40.149931 ==
6722 12:20:40.150015
6723 12:20:40.150093
6724 12:20:40.153284 TX Vref Scan disable
6725 12:20:40.153370 == TX Byte 0 ==
6726 12:20:40.160203 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6727 12:20:40.163246 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6728 12:20:40.163329 == TX Byte 1 ==
6729 12:20:40.166600 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 12:20:40.173641 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 12:20:40.173785 ==
6732 12:20:40.176182 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 12:20:40.179467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 12:20:40.179570 ==
6735 12:20:40.179670
6736 12:20:40.179767
6737 12:20:40.183242 TX Vref Scan disable
6738 12:20:40.183324 == TX Byte 0 ==
6739 12:20:40.189865 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 12:20:40.193034 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 12:20:40.193117 == TX Byte 1 ==
6742 12:20:40.199416 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 12:20:40.203216 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 12:20:40.203299
6745 12:20:40.203382 [DATLAT]
6746 12:20:40.206457 Freq=400, CH1 RK0
6747 12:20:40.206540
6748 12:20:40.206623 DATLAT Default: 0xf
6749 12:20:40.209562 0, 0xFFFF, sum = 0
6750 12:20:40.209669 1, 0xFFFF, sum = 0
6751 12:20:40.212710 2, 0xFFFF, sum = 0
6752 12:20:40.212794 3, 0xFFFF, sum = 0
6753 12:20:40.216429 4, 0xFFFF, sum = 0
6754 12:20:40.216513 5, 0xFFFF, sum = 0
6755 12:20:40.219674 6, 0xFFFF, sum = 0
6756 12:20:40.219757 7, 0xFFFF, sum = 0
6757 12:20:40.222924 8, 0xFFFF, sum = 0
6758 12:20:40.223008 9, 0xFFFF, sum = 0
6759 12:20:40.226035 10, 0xFFFF, sum = 0
6760 12:20:40.226118 11, 0xFFFF, sum = 0
6761 12:20:40.229752 12, 0xFFFF, sum = 0
6762 12:20:40.232611 13, 0x0, sum = 1
6763 12:20:40.232694 14, 0x0, sum = 2
6764 12:20:40.232778 15, 0x0, sum = 3
6765 12:20:40.236202 16, 0x0, sum = 4
6766 12:20:40.236348 best_step = 14
6767 12:20:40.236431
6768 12:20:40.236510 ==
6769 12:20:40.239521 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 12:20:40.246133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 12:20:40.246216 ==
6772 12:20:40.246300 RX Vref Scan: 1
6773 12:20:40.246378
6774 12:20:40.249094 RX Vref 0 -> 0, step: 1
6775 12:20:40.249176
6776 12:20:40.252601 RX Delay -311 -> 252, step: 8
6777 12:20:40.252684
6778 12:20:40.255792 Set Vref, RX VrefLevel [Byte0]: 54
6779 12:20:40.259061 [Byte1]: 48
6780 12:20:40.262636
6781 12:20:40.262743 Final RX Vref Byte 0 = 54 to rank0
6782 12:20:40.265684 Final RX Vref Byte 1 = 48 to rank0
6783 12:20:40.269713 Final RX Vref Byte 0 = 54 to rank1
6784 12:20:40.272626 Final RX Vref Byte 1 = 48 to rank1==
6785 12:20:40.275823 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 12:20:40.282388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 12:20:40.282471 ==
6788 12:20:40.282570 DQS Delay:
6789 12:20:40.286043 DQS0 = 32, DQS1 = 32
6790 12:20:40.286150 DQM Delay:
6791 12:20:40.286235 DQM0 = 13, DQM1 = 12
6792 12:20:40.289398 DQ Delay:
6793 12:20:40.292203 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6794 12:20:40.292347 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6795 12:20:40.296100 DQ8 =0, DQ9 =4, DQ10 =8, DQ11 =4
6796 12:20:40.299036 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6797 12:20:40.299119
6798 12:20:40.302797
6799 12:20:40.309334 [DQSOSCAuto] RK0, (LSB)MR18= 0x8ec7, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6800 12:20:40.312289 CH1 RK0: MR19=C0C, MR18=8EC7
6801 12:20:40.318963 CH1_RK0: MR19=0xC0C, MR18=0x8EC7, DQSOSC=385, MR23=63, INC=398, DEC=265
6802 12:20:40.319046 ==
6803 12:20:40.322251 Dram Type= 6, Freq= 0, CH_1, rank 1
6804 12:20:40.325311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 12:20:40.325394 ==
6806 12:20:40.328645 [Gating] SW mode calibration
6807 12:20:40.335462 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6808 12:20:40.342084 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6809 12:20:40.345235 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6810 12:20:40.348376 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6811 12:20:40.354905 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 12:20:40.358443 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 12:20:40.361499 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 12:20:40.368567 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 12:20:40.371737 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 12:20:40.375082 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 12:20:40.381433 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 12:20:40.381518 Total UI for P1: 0, mck2ui 16
6819 12:20:40.388775 best dqsien dly found for B0: ( 0, 14, 24)
6820 12:20:40.388855 Total UI for P1: 0, mck2ui 16
6821 12:20:40.391783 best dqsien dly found for B1: ( 0, 14, 24)
6822 12:20:40.398426 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6823 12:20:40.401242 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6824 12:20:40.401322
6825 12:20:40.405162 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6826 12:20:40.408511 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6827 12:20:40.411301 [Gating] SW calibration Done
6828 12:20:40.411380 ==
6829 12:20:40.414806 Dram Type= 6, Freq= 0, CH_1, rank 1
6830 12:20:40.418233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 12:20:40.418313 ==
6832 12:20:40.421609 RX Vref Scan: 0
6833 12:20:40.421694
6834 12:20:40.421757 RX Vref 0 -> 0, step: 1
6835 12:20:40.421816
6836 12:20:40.425073 RX Delay -410 -> 252, step: 16
6837 12:20:40.431362 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6838 12:20:40.434979 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6839 12:20:40.437846 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6840 12:20:40.441544 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6841 12:20:40.448050 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6842 12:20:40.451250 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6843 12:20:40.454438 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6844 12:20:40.457712 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6845 12:20:40.461163 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6846 12:20:40.468215 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6847 12:20:40.471379 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6848 12:20:40.474751 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6849 12:20:40.481719 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6850 12:20:40.484772 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6851 12:20:40.487711 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6852 12:20:40.491156 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6853 12:20:40.491236 ==
6854 12:20:40.494832 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 12:20:40.501209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 12:20:40.501290 ==
6857 12:20:40.501352 DQS Delay:
6858 12:20:40.504535 DQS0 = 35, DQS1 = 35
6859 12:20:40.504647 DQM Delay:
6860 12:20:40.504710 DQM0 = 18, DQM1 = 14
6861 12:20:40.507892 DQ Delay:
6862 12:20:40.511425 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6863 12:20:40.514468 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6864 12:20:40.517696 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6865 12:20:40.521468 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6866 12:20:40.521537
6867 12:20:40.521596
6868 12:20:40.521651 ==
6869 12:20:40.524454 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 12:20:40.527964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 12:20:40.528044 ==
6872 12:20:40.528106
6873 12:20:40.528165
6874 12:20:40.530890 TX Vref Scan disable
6875 12:20:40.530969 == TX Byte 0 ==
6876 12:20:40.534417 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6877 12:20:40.541199 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6878 12:20:40.541280 == TX Byte 1 ==
6879 12:20:40.544550 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6880 12:20:40.550756 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6881 12:20:40.550836 ==
6882 12:20:40.554330 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 12:20:40.557836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 12:20:40.557950 ==
6885 12:20:40.558033
6886 12:20:40.558110
6887 12:20:40.561139 TX Vref Scan disable
6888 12:20:40.561219 == TX Byte 0 ==
6889 12:20:40.567581 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6890 12:20:40.571229 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6891 12:20:40.571310 == TX Byte 1 ==
6892 12:20:40.574193 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6893 12:20:40.581168 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6894 12:20:40.581248
6895 12:20:40.581310 [DATLAT]
6896 12:20:40.584514 Freq=400, CH1 RK1
6897 12:20:40.584593
6898 12:20:40.584656 DATLAT Default: 0xe
6899 12:20:40.587591 0, 0xFFFF, sum = 0
6900 12:20:40.587672 1, 0xFFFF, sum = 0
6901 12:20:40.590681 2, 0xFFFF, sum = 0
6902 12:20:40.590765 3, 0xFFFF, sum = 0
6903 12:20:40.594332 4, 0xFFFF, sum = 0
6904 12:20:40.594412 5, 0xFFFF, sum = 0
6905 12:20:40.597658 6, 0xFFFF, sum = 0
6906 12:20:40.597739 7, 0xFFFF, sum = 0
6907 12:20:40.601244 8, 0xFFFF, sum = 0
6908 12:20:40.601325 9, 0xFFFF, sum = 0
6909 12:20:40.603882 10, 0xFFFF, sum = 0
6910 12:20:40.603963 11, 0xFFFF, sum = 0
6911 12:20:40.607864 12, 0xFFFF, sum = 0
6912 12:20:40.607945 13, 0x0, sum = 1
6913 12:20:40.611082 14, 0x0, sum = 2
6914 12:20:40.611162 15, 0x0, sum = 3
6915 12:20:40.614243 16, 0x0, sum = 4
6916 12:20:40.614324 best_step = 14
6917 12:20:40.614387
6918 12:20:40.614446 ==
6919 12:20:40.617447 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 12:20:40.623912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 12:20:40.623992 ==
6922 12:20:40.624055 RX Vref Scan: 0
6923 12:20:40.624114
6924 12:20:40.627275 RX Vref 0 -> 0, step: 1
6925 12:20:40.627354
6926 12:20:40.630916 RX Delay -311 -> 252, step: 8
6927 12:20:40.637835 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6928 12:20:40.641137 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6929 12:20:40.644791 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6930 12:20:40.647819 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6931 12:20:40.654114 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6932 12:20:40.657239 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6933 12:20:40.660950 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6934 12:20:40.663904 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6935 12:20:40.667650 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6936 12:20:40.673805 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6937 12:20:40.677487 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6938 12:20:40.680579 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6939 12:20:40.684182 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6940 12:20:40.690669 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6941 12:20:40.693890 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6942 12:20:40.697240 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6943 12:20:40.697321 ==
6944 12:20:40.700502 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 12:20:40.707287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 12:20:40.707367 ==
6947 12:20:40.707430 DQS Delay:
6948 12:20:40.711024 DQS0 = 28, DQS1 = 32
6949 12:20:40.711103 DQM Delay:
6950 12:20:40.711166 DQM0 = 11, DQM1 = 12
6951 12:20:40.714230 DQ Delay:
6952 12:20:40.717520 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6953 12:20:40.720532 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
6954 12:20:40.720611 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6955 12:20:40.723831 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6956 12:20:40.727610
6957 12:20:40.727707
6958 12:20:40.733981 [DQSOSCAuto] RK1, (LSB)MR18= 0xc456, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6959 12:20:40.737186 CH1 RK1: MR19=C0C, MR18=C456
6960 12:20:40.743943 CH1_RK1: MR19=0xC0C, MR18=0xC456, DQSOSC=385, MR23=63, INC=398, DEC=265
6961 12:20:40.747146 [RxdqsGatingPostProcess] freq 400
6962 12:20:40.750545 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6963 12:20:40.753718 best DQS0 dly(2T, 0.5T) = (0, 10)
6964 12:20:40.757092 best DQS1 dly(2T, 0.5T) = (0, 10)
6965 12:20:40.760819 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6966 12:20:40.764093 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6967 12:20:40.767240 best DQS0 dly(2T, 0.5T) = (0, 10)
6968 12:20:40.770549 best DQS1 dly(2T, 0.5T) = (0, 10)
6969 12:20:40.774258 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6970 12:20:40.777281 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6971 12:20:40.780496 Pre-setting of DQS Precalculation
6972 12:20:40.783617 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6973 12:20:40.790392 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6974 12:20:40.800448 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6975 12:20:40.800527
6976 12:20:40.800590
6977 12:20:40.803862 [Calibration Summary] 800 Mbps
6978 12:20:40.803942 CH 0, Rank 0
6979 12:20:40.807105 SW Impedance : PASS
6980 12:20:40.807184 DUTY Scan : NO K
6981 12:20:40.810171 ZQ Calibration : PASS
6982 12:20:40.813510 Jitter Meter : NO K
6983 12:20:40.813589 CBT Training : PASS
6984 12:20:40.817159 Write leveling : PASS
6985 12:20:40.817239 RX DQS gating : PASS
6986 12:20:40.820266 RX DQ/DQS(RDDQC) : PASS
6987 12:20:40.823582 TX DQ/DQS : PASS
6988 12:20:40.823662 RX DATLAT : PASS
6989 12:20:40.826999 RX DQ/DQS(Engine): PASS
6990 12:20:40.830252 TX OE : NO K
6991 12:20:40.830352 All Pass.
6992 12:20:40.830441
6993 12:20:40.830536 CH 0, Rank 1
6994 12:20:40.833700 SW Impedance : PASS
6995 12:20:40.836784 DUTY Scan : NO K
6996 12:20:40.836857 ZQ Calibration : PASS
6997 12:20:40.840268 Jitter Meter : NO K
6998 12:20:40.843389 CBT Training : PASS
6999 12:20:40.843468 Write leveling : NO K
7000 12:20:40.846984 RX DQS gating : PASS
7001 12:20:40.849890 RX DQ/DQS(RDDQC) : PASS
7002 12:20:40.849970 TX DQ/DQS : PASS
7003 12:20:40.853251 RX DATLAT : PASS
7004 12:20:40.857100 RX DQ/DQS(Engine): PASS
7005 12:20:40.857180 TX OE : NO K
7006 12:20:40.857243 All Pass.
7007 12:20:40.860170
7008 12:20:40.860249 CH 1, Rank 0
7009 12:20:40.863519 SW Impedance : PASS
7010 12:20:40.863601 DUTY Scan : NO K
7011 12:20:40.866822 ZQ Calibration : PASS
7012 12:20:40.869934 Jitter Meter : NO K
7013 12:20:40.870014 CBT Training : PASS
7014 12:20:40.873165 Write leveling : PASS
7015 12:20:40.873244 RX DQS gating : PASS
7016 12:20:40.876543 RX DQ/DQS(RDDQC) : PASS
7017 12:20:40.880148 TX DQ/DQS : PASS
7018 12:20:40.880229 RX DATLAT : PASS
7019 12:20:40.883537 RX DQ/DQS(Engine): PASS
7020 12:20:40.886389 TX OE : NO K
7021 12:20:40.886461 All Pass.
7022 12:20:40.886522
7023 12:20:40.886579 CH 1, Rank 1
7024 12:20:40.890013 SW Impedance : PASS
7025 12:20:40.893241 DUTY Scan : NO K
7026 12:20:40.893315 ZQ Calibration : PASS
7027 12:20:40.896352 Jitter Meter : NO K
7028 12:20:40.900214 CBT Training : PASS
7029 12:20:40.900358 Write leveling : NO K
7030 12:20:40.903424 RX DQS gating : PASS
7031 12:20:40.906800 RX DQ/DQS(RDDQC) : PASS
7032 12:20:40.906888 TX DQ/DQS : PASS
7033 12:20:40.910105 RX DATLAT : PASS
7034 12:20:40.910190 RX DQ/DQS(Engine): PASS
7035 12:20:40.913466 TX OE : NO K
7036 12:20:40.913538 All Pass.
7037 12:20:40.913598
7038 12:20:40.916881 DramC Write-DBI off
7039 12:20:40.920048 PER_BANK_REFRESH: Hybrid Mode
7040 12:20:40.920158 TX_TRACKING: ON
7041 12:20:40.929927 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7042 12:20:40.932917 [FAST_K] Save calibration result to emmc
7043 12:20:40.936837 dramc_set_vcore_voltage set vcore to 725000
7044 12:20:40.939624 Read voltage for 1600, 0
7045 12:20:40.939695 Vio18 = 0
7046 12:20:40.943255 Vcore = 725000
7047 12:20:40.943326 Vdram = 0
7048 12:20:40.943387 Vddq = 0
7049 12:20:40.943444 Vmddr = 0
7050 12:20:40.949939 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7051 12:20:40.956402 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7052 12:20:40.956482 MEM_TYPE=3, freq_sel=13
7053 12:20:40.959792 sv_algorithm_assistance_LP4_3733
7054 12:20:40.963452 ============ PULL DRAM RESETB DOWN ============
7055 12:20:40.969632 ========== PULL DRAM RESETB DOWN end =========
7056 12:20:40.972988 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7057 12:20:40.976412 ===================================
7058 12:20:40.979539 LPDDR4 DRAM CONFIGURATION
7059 12:20:40.983344 ===================================
7060 12:20:40.983425 EX_ROW_EN[0] = 0x0
7061 12:20:40.986416 EX_ROW_EN[1] = 0x0
7062 12:20:40.986538 LP4Y_EN = 0x0
7063 12:20:40.989772 WORK_FSP = 0x1
7064 12:20:40.989855 WL = 0x5
7065 12:20:40.993384 RL = 0x5
7066 12:20:40.993465 BL = 0x2
7067 12:20:40.996277 RPST = 0x0
7068 12:20:40.999302 RD_PRE = 0x0
7069 12:20:40.999382 WR_PRE = 0x1
7070 12:20:41.002997 WR_PST = 0x1
7071 12:20:41.003077 DBI_WR = 0x0
7072 12:20:41.006250 DBI_RD = 0x0
7073 12:20:41.006329 OTF = 0x1
7074 12:20:41.009468 ===================================
7075 12:20:41.012745 ===================================
7076 12:20:41.016603 ANA top config
7077 12:20:41.016682 ===================================
7078 12:20:41.019552 DLL_ASYNC_EN = 0
7079 12:20:41.022793 ALL_SLAVE_EN = 0
7080 12:20:41.026273 NEW_RANK_MODE = 1
7081 12:20:41.029463 DLL_IDLE_MODE = 1
7082 12:20:41.029542 LP45_APHY_COMB_EN = 1
7083 12:20:41.032944 TX_ODT_DIS = 0
7084 12:20:41.036107 NEW_8X_MODE = 1
7085 12:20:41.039235 ===================================
7086 12:20:41.042597 ===================================
7087 12:20:41.045787 data_rate = 3200
7088 12:20:41.049609 CKR = 1
7089 12:20:41.049685 DQ_P2S_RATIO = 8
7090 12:20:41.052323 ===================================
7091 12:20:41.055769 CA_P2S_RATIO = 8
7092 12:20:41.059459 DQ_CA_OPEN = 0
7093 12:20:41.062639 DQ_SEMI_OPEN = 0
7094 12:20:41.065923 CA_SEMI_OPEN = 0
7095 12:20:41.069122 CA_FULL_RATE = 0
7096 12:20:41.069197 DQ_CKDIV4_EN = 0
7097 12:20:41.072392 CA_CKDIV4_EN = 0
7098 12:20:41.075944 CA_PREDIV_EN = 0
7099 12:20:41.079052 PH8_DLY = 12
7100 12:20:41.082336 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7101 12:20:41.086039 DQ_AAMCK_DIV = 4
7102 12:20:41.086114 CA_AAMCK_DIV = 4
7103 12:20:41.089138 CA_ADMCK_DIV = 4
7104 12:20:41.092606 DQ_TRACK_CA_EN = 0
7105 12:20:41.095641 CA_PICK = 1600
7106 12:20:41.099214 CA_MCKIO = 1600
7107 12:20:41.102301 MCKIO_SEMI = 0
7108 12:20:41.105725 PLL_FREQ = 3068
7109 12:20:41.105807 DQ_UI_PI_RATIO = 32
7110 12:20:41.109120 CA_UI_PI_RATIO = 0
7111 12:20:41.112673 ===================================
7112 12:20:41.116069 ===================================
7113 12:20:41.119211 memory_type:LPDDR4
7114 12:20:41.122540 GP_NUM : 10
7115 12:20:41.122638 SRAM_EN : 1
7116 12:20:41.125900 MD32_EN : 0
7117 12:20:41.128925 ===================================
7118 12:20:41.132806 [ANA_INIT] >>>>>>>>>>>>>>
7119 12:20:41.132876 <<<<<< [CONFIGURE PHASE]: ANA_TX
7120 12:20:41.138955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7121 12:20:41.142494 ===================================
7122 12:20:41.142568 data_rate = 3200,PCW = 0X7600
7123 12:20:41.145751 ===================================
7124 12:20:41.149087 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7125 12:20:41.155581 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7126 12:20:41.161941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7127 12:20:41.165826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7128 12:20:41.169138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7129 12:20:41.172248 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7130 12:20:41.175470 [ANA_INIT] flow start
7131 12:20:41.175548 [ANA_INIT] PLL >>>>>>>>
7132 12:20:41.178699 [ANA_INIT] PLL <<<<<<<<
7133 12:20:41.182058 [ANA_INIT] MIDPI >>>>>>>>
7134 12:20:41.185510 [ANA_INIT] MIDPI <<<<<<<<
7135 12:20:41.185590 [ANA_INIT] DLL >>>>>>>>
7136 12:20:41.189134 [ANA_INIT] DLL <<<<<<<<
7137 12:20:41.189248 [ANA_INIT] flow end
7138 12:20:41.195358 ============ LP4 DIFF to SE enter ============
7139 12:20:41.198935 ============ LP4 DIFF to SE exit ============
7140 12:20:41.201795 [ANA_INIT] <<<<<<<<<<<<<
7141 12:20:41.205244 [Flow] Enable top DCM control >>>>>
7142 12:20:41.208219 [Flow] Enable top DCM control <<<<<
7143 12:20:41.211659 Enable DLL master slave shuffle
7144 12:20:41.215355 ==============================================================
7145 12:20:41.218659 Gating Mode config
7146 12:20:41.225149 ==============================================================
7147 12:20:41.225230 Config description:
7148 12:20:41.234878 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7149 12:20:41.241304 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7150 12:20:41.244816 SELPH_MODE 0: By rank 1: By Phase
7151 12:20:41.251113 ==============================================================
7152 12:20:41.254555 GAT_TRACK_EN = 1
7153 12:20:41.257903 RX_GATING_MODE = 2
7154 12:20:41.261778 RX_GATING_TRACK_MODE = 2
7155 12:20:41.264989 SELPH_MODE = 1
7156 12:20:41.268139 PICG_EARLY_EN = 1
7157 12:20:41.271502 VALID_LAT_VALUE = 1
7158 12:20:41.274615 ==============================================================
7159 12:20:41.278241 Enter into Gating configuration >>>>
7160 12:20:41.281176 Exit from Gating configuration <<<<
7161 12:20:41.284515 Enter into DVFS_PRE_config >>>>>
7162 12:20:41.298210 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7163 12:20:41.298292 Exit from DVFS_PRE_config <<<<<
7164 12:20:41.301478 Enter into PICG configuration >>>>
7165 12:20:41.304613 Exit from PICG configuration <<<<
7166 12:20:41.307720 [RX_INPUT] configuration >>>>>
7167 12:20:41.311529 [RX_INPUT] configuration <<<<<
7168 12:20:41.318163 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7169 12:20:41.321329 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7170 12:20:41.327766 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7171 12:20:41.334216 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7172 12:20:41.340901 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7173 12:20:41.347737 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7174 12:20:41.350893 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7175 12:20:41.354641 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7176 12:20:41.357448 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7177 12:20:41.364096 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7178 12:20:41.367556 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7179 12:20:41.370884 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7180 12:20:41.374332 ===================================
7181 12:20:41.377686 LPDDR4 DRAM CONFIGURATION
7182 12:20:41.380742 ===================================
7183 12:20:41.380822 EX_ROW_EN[0] = 0x0
7184 12:20:41.384183 EX_ROW_EN[1] = 0x0
7185 12:20:41.388136 LP4Y_EN = 0x0
7186 12:20:41.388215 WORK_FSP = 0x1
7187 12:20:41.391090 WL = 0x5
7188 12:20:41.391169 RL = 0x5
7189 12:20:41.394364 BL = 0x2
7190 12:20:41.394444 RPST = 0x0
7191 12:20:41.397585 RD_PRE = 0x0
7192 12:20:41.397679 WR_PRE = 0x1
7193 12:20:41.400860 WR_PST = 0x1
7194 12:20:41.400939 DBI_WR = 0x0
7195 12:20:41.404214 DBI_RD = 0x0
7196 12:20:41.404303 OTF = 0x1
7197 12:20:41.407346 ===================================
7198 12:20:41.411169 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7199 12:20:41.417635 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7200 12:20:41.420923 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7201 12:20:41.424184 ===================================
7202 12:20:41.427432 LPDDR4 DRAM CONFIGURATION
7203 12:20:41.430514 ===================================
7204 12:20:41.430634 EX_ROW_EN[0] = 0x10
7205 12:20:41.434210 EX_ROW_EN[1] = 0x0
7206 12:20:41.434290 LP4Y_EN = 0x0
7207 12:20:41.437362 WORK_FSP = 0x1
7208 12:20:41.437441 WL = 0x5
7209 12:20:41.440503 RL = 0x5
7210 12:20:41.444415 BL = 0x2
7211 12:20:41.444495 RPST = 0x0
7212 12:20:41.447194 RD_PRE = 0x0
7213 12:20:41.447273 WR_PRE = 0x1
7214 12:20:41.450957 WR_PST = 0x1
7215 12:20:41.451036 DBI_WR = 0x0
7216 12:20:41.453911 DBI_RD = 0x0
7217 12:20:41.453990 OTF = 0x1
7218 12:20:41.457685 ===================================
7219 12:20:41.464077 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7220 12:20:41.464157 ==
7221 12:20:41.467370 Dram Type= 6, Freq= 0, CH_0, rank 0
7222 12:20:41.470674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7223 12:20:41.470754 ==
7224 12:20:41.474272 [Duty_Offset_Calibration]
7225 12:20:41.474351 B0:2 B1:1 CA:1
7226 12:20:41.477380
7227 12:20:41.480594 [DutyScan_Calibration_Flow] k_type=0
7228 12:20:41.489173
7229 12:20:41.489255 ==CLK 0==
7230 12:20:41.492090 Final CLK duty delay cell = 0
7231 12:20:41.495192 [0] MAX Duty = 5156%(X100), DQS PI = 22
7232 12:20:41.498693 [0] MIN Duty = 4876%(X100), DQS PI = 48
7233 12:20:41.502260 [0] AVG Duty = 5016%(X100)
7234 12:20:41.502342
7235 12:20:41.505249 CH0 CLK Duty spec in!! Max-Min= 280%
7236 12:20:41.508528 [DutyScan_Calibration_Flow] ====Done====
7237 12:20:41.508624
7238 12:20:41.511830 [DutyScan_Calibration_Flow] k_type=1
7239 12:20:41.528026
7240 12:20:41.528124 ==DQS 0 ==
7241 12:20:41.531240 Final DQS duty delay cell = -4
7242 12:20:41.534451 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7243 12:20:41.537727 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7244 12:20:41.541343 [-4] AVG Duty = 4906%(X100)
7245 12:20:41.541448
7246 12:20:41.541541 ==DQS 1 ==
7247 12:20:41.544372 Final DQS duty delay cell = 0
7248 12:20:41.547706 [0] MAX Duty = 5187%(X100), DQS PI = 20
7249 12:20:41.550941 [0] MIN Duty = 5031%(X100), DQS PI = 32
7250 12:20:41.554561 [0] AVG Duty = 5109%(X100)
7251 12:20:41.554671
7252 12:20:41.557682 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7253 12:20:41.557861
7254 12:20:41.561352 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7255 12:20:41.564165 [DutyScan_Calibration_Flow] ====Done====
7256 12:20:41.564290
7257 12:20:41.567375 [DutyScan_Calibration_Flow] k_type=3
7258 12:20:41.584604
7259 12:20:41.584686 ==DQM 0 ==
7260 12:20:41.587958 Final DQM duty delay cell = 0
7261 12:20:41.591285 [0] MAX Duty = 5218%(X100), DQS PI = 32
7262 12:20:41.594438 [0] MIN Duty = 4907%(X100), DQS PI = 56
7263 12:20:41.598048 [0] AVG Duty = 5062%(X100)
7264 12:20:41.598130
7265 12:20:41.598195 ==DQM 1 ==
7266 12:20:41.601147 Final DQM duty delay cell = -4
7267 12:20:41.605128 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7268 12:20:41.607740 [-4] MIN Duty = 4813%(X100), DQS PI = 12
7269 12:20:41.611249 [-4] AVG Duty = 4891%(X100)
7270 12:20:41.611331
7271 12:20:41.614396 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7272 12:20:41.614479
7273 12:20:41.617943 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7274 12:20:41.621907 [DutyScan_Calibration_Flow] ====Done====
7275 12:20:41.621990
7276 12:20:41.624428 [DutyScan_Calibration_Flow] k_type=2
7277 12:20:41.642180
7278 12:20:41.642268 ==DQ 0 ==
7279 12:20:41.645428 Final DQ duty delay cell = 0
7280 12:20:41.649104 [0] MAX Duty = 5062%(X100), DQS PI = 24
7281 12:20:41.652034 [0] MIN Duty = 4907%(X100), DQS PI = 0
7282 12:20:41.652143 [0] AVG Duty = 4984%(X100)
7283 12:20:41.655299
7284 12:20:41.655382 ==DQ 1 ==
7285 12:20:41.658613 Final DQ duty delay cell = 0
7286 12:20:41.662142 [0] MAX Duty = 5125%(X100), DQS PI = 6
7287 12:20:41.665412 [0] MIN Duty = 4907%(X100), DQS PI = 34
7288 12:20:41.665495 [0] AVG Duty = 5016%(X100)
7289 12:20:41.665560
7290 12:20:41.668876 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7291 12:20:41.672327
7292 12:20:41.675315 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7293 12:20:41.678692 [DutyScan_Calibration_Flow] ====Done====
7294 12:20:41.678773 ==
7295 12:20:41.682087 Dram Type= 6, Freq= 0, CH_1, rank 0
7296 12:20:41.685249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7297 12:20:41.685329 ==
7298 12:20:41.688536 [Duty_Offset_Calibration]
7299 12:20:41.688615 B0:2 B1:0 CA:0
7300 12:20:41.688678
7301 12:20:41.692100 [DutyScan_Calibration_Flow] k_type=0
7302 12:20:41.701835
7303 12:20:41.701914 ==CLK 0==
7304 12:20:41.705153 Final CLK duty delay cell = -4
7305 12:20:41.708232 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7306 12:20:41.711351 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7307 12:20:41.715119 [-4] AVG Duty = 4906%(X100)
7308 12:20:41.715222
7309 12:20:41.718341 CH1 CLK Duty spec in!! Max-Min= 125%
7310 12:20:41.721685 [DutyScan_Calibration_Flow] ====Done====
7311 12:20:41.721765
7312 12:20:41.724807 [DutyScan_Calibration_Flow] k_type=1
7313 12:20:41.741744
7314 12:20:41.741824 ==DQS 0 ==
7315 12:20:41.744743 Final DQS duty delay cell = 0
7316 12:20:41.748498 [0] MAX Duty = 5093%(X100), DQS PI = 46
7317 12:20:41.751692 [0] MIN Duty = 4844%(X100), DQS PI = 14
7318 12:20:41.754718 [0] AVG Duty = 4968%(X100)
7319 12:20:41.754798
7320 12:20:41.754861 ==DQS 1 ==
7321 12:20:41.758153 Final DQS duty delay cell = 0
7322 12:20:41.761256 [0] MAX Duty = 5249%(X100), DQS PI = 48
7323 12:20:41.764646 [0] MIN Duty = 4907%(X100), DQS PI = 42
7324 12:20:41.767878 [0] AVG Duty = 5078%(X100)
7325 12:20:41.767957
7326 12:20:41.771555 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7327 12:20:41.771635
7328 12:20:41.774754 CH1 DQS 1 Duty spec in!! Max-Min= 342%
7329 12:20:41.777912 [DutyScan_Calibration_Flow] ====Done====
7330 12:20:41.777996
7331 12:20:41.781590 [DutyScan_Calibration_Flow] k_type=3
7332 12:20:41.798675
7333 12:20:41.798763 ==DQM 0 ==
7334 12:20:41.802001 Final DQM duty delay cell = 0
7335 12:20:41.805406 [0] MAX Duty = 5187%(X100), DQS PI = 40
7336 12:20:41.808496 [0] MIN Duty = 5000%(X100), DQS PI = 16
7337 12:20:41.811852 [0] AVG Duty = 5093%(X100)
7338 12:20:41.811932
7339 12:20:41.811994 ==DQM 1 ==
7340 12:20:41.815402 Final DQM duty delay cell = 0
7341 12:20:41.818745 [0] MAX Duty = 5093%(X100), DQS PI = 10
7342 12:20:41.821920 [0] MIN Duty = 4907%(X100), DQS PI = 0
7343 12:20:41.821999 [0] AVG Duty = 5000%(X100)
7344 12:20:41.825392
7345 12:20:41.828754 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7346 12:20:41.828841
7347 12:20:41.831821 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7348 12:20:41.835108 [DutyScan_Calibration_Flow] ====Done====
7349 12:20:41.835206
7350 12:20:41.838351 [DutyScan_Calibration_Flow] k_type=2
7351 12:20:41.854678
7352 12:20:41.854789 ==DQ 0 ==
7353 12:20:41.857739 Final DQ duty delay cell = -4
7354 12:20:41.860801 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7355 12:20:41.864525 [-4] MIN Duty = 4876%(X100), DQS PI = 14
7356 12:20:41.867531 [-4] AVG Duty = 4953%(X100)
7357 12:20:41.867641
7358 12:20:41.867704 ==DQ 1 ==
7359 12:20:41.871311 Final DQ duty delay cell = 0
7360 12:20:41.874555 [0] MAX Duty = 5093%(X100), DQS PI = 50
7361 12:20:41.877593 [0] MIN Duty = 4938%(X100), DQS PI = 0
7362 12:20:41.877688 [0] AVG Duty = 5015%(X100)
7363 12:20:41.881076
7364 12:20:41.884469 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7365 12:20:41.884574
7366 12:20:41.888104 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7367 12:20:41.891175 [DutyScan_Calibration_Flow] ====Done====
7368 12:20:41.894751 nWR fixed to 30
7369 12:20:41.894832 [ModeRegInit_LP4] CH0 RK0
7370 12:20:41.897879 [ModeRegInit_LP4] CH0 RK1
7371 12:20:41.901100 [ModeRegInit_LP4] CH1 RK0
7372 12:20:41.904426 [ModeRegInit_LP4] CH1 RK1
7373 12:20:41.904511 match AC timing 5
7374 12:20:41.911021 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7375 12:20:41.914187 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7376 12:20:41.917803 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7377 12:20:41.924846 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7378 12:20:41.927743 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7379 12:20:41.927849 [MiockJmeterHQA]
7380 12:20:41.927939
7381 12:20:41.931154 [DramcMiockJmeter] u1RxGatingPI = 0
7382 12:20:41.934194 0 : 4255, 4030
7383 12:20:41.934277 4 : 4252, 4027
7384 12:20:41.937404 8 : 4252, 4027
7385 12:20:41.937486 12 : 4253, 4026
7386 12:20:41.937552 16 : 4252, 4027
7387 12:20:41.941130 20 : 4363, 4137
7388 12:20:41.941212 24 : 4252, 4027
7389 12:20:41.944108 28 : 4363, 4137
7390 12:20:41.944189 32 : 4252, 4027
7391 12:20:41.947893 36 : 4252, 4027
7392 12:20:41.947974 40 : 4253, 4026
7393 12:20:41.951040 44 : 4254, 4029
7394 12:20:41.951120 48 : 4363, 4137
7395 12:20:41.951185 52 : 4253, 4027
7396 12:20:41.954216 56 : 4363, 4137
7397 12:20:41.954298 60 : 4252, 4027
7398 12:20:41.957479 64 : 4253, 4027
7399 12:20:41.957560 68 : 4253, 4026
7400 12:20:41.961081 72 : 4361, 4137
7401 12:20:41.961163 76 : 4252, 4027
7402 12:20:41.961227 80 : 4361, 4137
7403 12:20:41.964427 84 : 4250, 4027
7404 12:20:41.964508 88 : 4250, 147
7405 12:20:41.967576 92 : 4361, 0
7406 12:20:41.967657 96 : 4253, 0
7407 12:20:41.967722 100 : 4250, 0
7408 12:20:41.970782 104 : 4250, 0
7409 12:20:41.970864 108 : 4250, 0
7410 12:20:41.974588 112 : 4250, 0
7411 12:20:41.974669 116 : 4250, 0
7412 12:20:41.974734 120 : 4363, 0
7413 12:20:41.977391 124 : 4250, 0
7414 12:20:41.977473 128 : 4250, 0
7415 12:20:41.980989 132 : 4252, 0
7416 12:20:41.981070 136 : 4363, 0
7417 12:20:41.981135 140 : 4249, 0
7418 12:20:41.984199 144 : 4250, 0
7419 12:20:41.984347 148 : 4250, 0
7420 12:20:41.987440 152 : 4249, 0
7421 12:20:41.987551 156 : 4250, 0
7422 12:20:41.987646 160 : 4253, 0
7423 12:20:41.990867 164 : 4250, 0
7424 12:20:41.990948 168 : 4250, 0
7425 12:20:41.991014 172 : 4252, 0
7426 12:20:41.993996 176 : 4252, 0
7427 12:20:41.994078 180 : 4250, 0
7428 12:20:41.997113 184 : 4252, 0
7429 12:20:41.997194 188 : 4250, 0
7430 12:20:41.997259 192 : 4250, 0
7431 12:20:42.000335 196 : 4250, 0
7432 12:20:42.000417 200 : 4253, 0
7433 12:20:42.004055 204 : 4360, 1188
7434 12:20:42.004162 208 : 4363, 4068
7435 12:20:42.007104 212 : 4247, 4025
7436 12:20:42.007195 216 : 4361, 4138
7437 12:20:42.010343 220 : 4249, 4027
7438 12:20:42.010424 224 : 4250, 4026
7439 12:20:42.010489 228 : 4250, 4027
7440 12:20:42.013722 232 : 4250, 4027
7441 12:20:42.013804 236 : 4250, 4027
7442 12:20:42.017071 240 : 4250, 4026
7443 12:20:42.017153 244 : 4250, 4027
7444 12:20:42.020280 248 : 4252, 4030
7445 12:20:42.020381 252 : 4250, 4026
7446 12:20:42.024050 256 : 4361, 4137
7447 12:20:42.024131 260 : 4361, 4137
7448 12:20:42.027177 264 : 4250, 4027
7449 12:20:42.027288 268 : 4363, 4140
7450 12:20:42.030538 272 : 4361, 4137
7451 12:20:42.030613 276 : 4250, 4026
7452 12:20:42.033562 280 : 4250, 4027
7453 12:20:42.033643 284 : 4252, 4030
7454 12:20:42.033710 288 : 4250, 4026
7455 12:20:42.037228 292 : 4250, 4026
7456 12:20:42.037303 296 : 4250, 4027
7457 12:20:42.040199 300 : 4252, 4030
7458 12:20:42.040292 304 : 4250, 4027
7459 12:20:42.043696 308 : 4363, 4065
7460 12:20:42.043855 312 : 4361, 2171
7461 12:20:42.043955
7462 12:20:42.047058 MIOCK jitter meter ch=0
7463 12:20:42.047139
7464 12:20:42.050258 1T = (312-88) = 224 dly cells
7465 12:20:42.057176 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7466 12:20:42.057258 ==
7467 12:20:42.060406 Dram Type= 6, Freq= 0, CH_0, rank 0
7468 12:20:42.063616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7469 12:20:42.063724 ==
7470 12:20:42.070277 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7471 12:20:42.073640 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7472 12:20:42.076914 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7473 12:20:42.083230 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7474 12:20:42.092097 [CA 0] Center 42 (12~73) winsize 62
7475 12:20:42.095829 [CA 1] Center 42 (12~73) winsize 62
7476 12:20:42.098522 [CA 2] Center 37 (8~67) winsize 60
7477 12:20:42.102326 [CA 3] Center 37 (7~67) winsize 61
7478 12:20:42.105643 [CA 4] Center 36 (6~66) winsize 61
7479 12:20:42.108749 [CA 5] Center 35 (6~64) winsize 59
7480 12:20:42.108829
7481 12:20:42.112249 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7482 12:20:42.112376
7483 12:20:42.115308 [CATrainingPosCal] consider 1 rank data
7484 12:20:42.118413 u2DelayCellTimex100 = 290/100 ps
7485 12:20:42.121838 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7486 12:20:42.128646 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7487 12:20:42.131876 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7488 12:20:42.135279 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7489 12:20:42.138779 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7490 12:20:42.141971 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7491 12:20:42.142076
7492 12:20:42.145126 CA PerBit enable=1, Macro0, CA PI delay=35
7493 12:20:42.145226
7494 12:20:42.148703 [CBTSetCACLKResult] CA Dly = 35
7495 12:20:42.152108 CS Dly: 9 (0~40)
7496 12:20:42.155253 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7497 12:20:42.158715 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7498 12:20:42.158796 ==
7499 12:20:42.162222 Dram Type= 6, Freq= 0, CH_0, rank 1
7500 12:20:42.165352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7501 12:20:42.168202 ==
7502 12:20:42.171731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7503 12:20:42.174821 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7504 12:20:42.181509 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7505 12:20:42.184699 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7506 12:20:42.195562 [CA 0] Center 43 (13~73) winsize 61
7507 12:20:42.199033 [CA 1] Center 43 (13~73) winsize 61
7508 12:20:42.202208 [CA 2] Center 38 (8~68) winsize 61
7509 12:20:42.205598 [CA 3] Center 38 (8~68) winsize 61
7510 12:20:42.209018 [CA 4] Center 36 (6~66) winsize 61
7511 12:20:42.212567 [CA 5] Center 35 (6~65) winsize 60
7512 12:20:42.212672
7513 12:20:42.215535 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7514 12:20:42.215616
7515 12:20:42.218809 [CATrainingPosCal] consider 2 rank data
7516 12:20:42.222104 u2DelayCellTimex100 = 290/100 ps
7517 12:20:42.225104 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7518 12:20:42.232140 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7519 12:20:42.235462 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7520 12:20:42.238513 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7521 12:20:42.241833 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7522 12:20:42.245201 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7523 12:20:42.245282
7524 12:20:42.248382 CA PerBit enable=1, Macro0, CA PI delay=35
7525 12:20:42.248463
7526 12:20:42.251713 [CBTSetCACLKResult] CA Dly = 35
7527 12:20:42.255021 CS Dly: 9 (0~41)
7528 12:20:42.258177 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7529 12:20:42.261487 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7530 12:20:42.261566
7531 12:20:42.265357 ----->DramcWriteLeveling(PI) begin...
7532 12:20:42.265497 ==
7533 12:20:42.268519 Dram Type= 6, Freq= 0, CH_0, rank 0
7534 12:20:42.271924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 12:20:42.274939 ==
7536 12:20:42.275038 Write leveling (Byte 0): 35 => 35
7537 12:20:42.278588 Write leveling (Byte 1): 29 => 29
7538 12:20:42.281512 DramcWriteLeveling(PI) end<-----
7539 12:20:42.281617
7540 12:20:42.281717 ==
7541 12:20:42.285224 Dram Type= 6, Freq= 0, CH_0, rank 0
7542 12:20:42.291733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 12:20:42.291817 ==
7544 12:20:42.291883 [Gating] SW mode calibration
7545 12:20:42.301478 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7546 12:20:42.305017 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7547 12:20:42.311487 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 12:20:42.314937 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7549 12:20:42.318339 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7550 12:20:42.324518 1 4 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
7551 12:20:42.327796 1 4 16 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
7552 12:20:42.331670 1 4 20 | B1->B0 | 3232 3636 | 1 1 | (1 1) (1 1)
7553 12:20:42.334994 1 4 24 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
7554 12:20:42.341508 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7555 12:20:42.344893 1 5 0 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7556 12:20:42.348264 1 5 4 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7557 12:20:42.354839 1 5 8 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (0 1)
7558 12:20:42.358038 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
7559 12:20:42.361491 1 5 16 | B1->B0 | 3434 2f2e | 1 1 | (1 1) (0 0)
7560 12:20:42.367860 1 5 20 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
7561 12:20:42.371413 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7562 12:20:42.374618 1 5 28 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7563 12:20:42.381258 1 6 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
7564 12:20:42.384595 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7565 12:20:42.387783 1 6 8 | B1->B0 | 2323 3938 | 0 1 | (0 0) (1 1)
7566 12:20:42.394909 1 6 12 | B1->B0 | 2323 4544 | 0 1 | (0 0) (0 0)
7567 12:20:42.397854 1 6 16 | B1->B0 | 2d2d 4646 | 0 1 | (0 0) (1 1)
7568 12:20:42.401130 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7569 12:20:42.407866 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7570 12:20:42.411151 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 12:20:42.414325 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 12:20:42.421333 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 12:20:42.424520 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7574 12:20:42.427955 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7575 12:20:42.434414 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7576 12:20:42.438031 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 12:20:42.441232 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 12:20:42.447776 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 12:20:42.451174 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 12:20:42.454527 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 12:20:42.460760 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 12:20:42.464522 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 12:20:42.467686 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 12:20:42.474380 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 12:20:42.477564 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 12:20:42.481072 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 12:20:42.484491 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 12:20:42.490545 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 12:20:42.494409 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7590 12:20:42.497014 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7591 12:20:42.503878 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7592 12:20:42.507156 Total UI for P1: 0, mck2ui 16
7593 12:20:42.510556 best dqsien dly found for B0: ( 1, 9, 10)
7594 12:20:42.513829 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7595 12:20:42.517296 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 12:20:42.520405 Total UI for P1: 0, mck2ui 16
7597 12:20:42.524046 best dqsien dly found for B1: ( 1, 9, 18)
7598 12:20:42.527509 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7599 12:20:42.530777 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7600 12:20:42.530854
7601 12:20:42.537056 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7602 12:20:42.540784 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7603 12:20:42.543964 [Gating] SW calibration Done
7604 12:20:42.544065 ==
7605 12:20:42.547380 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 12:20:42.550665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 12:20:42.550787 ==
7608 12:20:42.550896 RX Vref Scan: 0
7609 12:20:42.554069
7610 12:20:42.554181 RX Vref 0 -> 0, step: 1
7611 12:20:42.554273
7612 12:20:42.557144 RX Delay 0 -> 252, step: 8
7613 12:20:42.560626 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7614 12:20:42.564071 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7615 12:20:42.570507 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7616 12:20:42.573719 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7617 12:20:42.577024 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7618 12:20:42.580280 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7619 12:20:42.583426 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7620 12:20:42.590285 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7621 12:20:42.593669 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7622 12:20:42.596922 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7623 12:20:42.600231 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7624 12:20:42.604054 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7625 12:20:42.610196 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7626 12:20:42.613504 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7627 12:20:42.616928 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7628 12:20:42.620349 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7629 12:20:42.620437 ==
7630 12:20:42.623467 Dram Type= 6, Freq= 0, CH_0, rank 0
7631 12:20:42.630102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7632 12:20:42.630190 ==
7633 12:20:42.630276 DQS Delay:
7634 12:20:42.633649 DQS0 = 0, DQS1 = 0
7635 12:20:42.633734 DQM Delay:
7636 12:20:42.633821 DQM0 = 137, DQM1 = 130
7637 12:20:42.636593 DQ Delay:
7638 12:20:42.640089 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7639 12:20:42.643897 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7640 12:20:42.646864 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7641 12:20:42.650407 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
7642 12:20:42.650490
7643 12:20:42.650554
7644 12:20:42.650614 ==
7645 12:20:42.653721 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 12:20:42.656824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 12:20:42.659904 ==
7648 12:20:42.659986
7649 12:20:42.660050
7650 12:20:42.660110 TX Vref Scan disable
7651 12:20:42.663493 == TX Byte 0 ==
7652 12:20:42.666690 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7653 12:20:42.669919 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7654 12:20:42.673053 == TX Byte 1 ==
7655 12:20:42.676629 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7656 12:20:42.680086 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7657 12:20:42.680168 ==
7658 12:20:42.683299 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 12:20:42.690169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 12:20:42.690253 ==
7661 12:20:42.700983
7662 12:20:42.704324 TX Vref early break, caculate TX vref
7663 12:20:42.707721 TX Vref=16, minBit 1, minWin=23, winSum=381
7664 12:20:42.711154 TX Vref=18, minBit 0, minWin=23, winSum=388
7665 12:20:42.714194 TX Vref=20, minBit 7, minWin=23, winSum=398
7666 12:20:42.717832 TX Vref=22, minBit 7, minWin=23, winSum=408
7667 12:20:42.721329 TX Vref=24, minBit 0, minWin=25, winSum=420
7668 12:20:42.727711 TX Vref=26, minBit 7, minWin=25, winSum=428
7669 12:20:42.730965 TX Vref=28, minBit 1, minWin=25, winSum=420
7670 12:20:42.734187 TX Vref=30, minBit 6, minWin=24, winSum=415
7671 12:20:42.737520 TX Vref=32, minBit 6, minWin=23, winSum=402
7672 12:20:42.744053 [TxChooseVref] Worse bit 7, Min win 25, Win sum 428, Final Vref 26
7673 12:20:42.744136
7674 12:20:42.747790 Final TX Range 0 Vref 26
7675 12:20:42.747872
7676 12:20:42.747937 ==
7677 12:20:42.750932 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 12:20:42.754077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 12:20:42.754161 ==
7680 12:20:42.754225
7681 12:20:42.754286
7682 12:20:42.757652 TX Vref Scan disable
7683 12:20:42.761468 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7684 12:20:42.764645 == TX Byte 0 ==
7685 12:20:42.767273 u2DelayCellOfst[0]=10 cells (3 PI)
7686 12:20:42.770637 u2DelayCellOfst[1]=13 cells (4 PI)
7687 12:20:42.774649 u2DelayCellOfst[2]=10 cells (3 PI)
7688 12:20:42.777353 u2DelayCellOfst[3]=10 cells (3 PI)
7689 12:20:42.780659 u2DelayCellOfst[4]=6 cells (2 PI)
7690 12:20:42.780740 u2DelayCellOfst[5]=0 cells (0 PI)
7691 12:20:42.784379 u2DelayCellOfst[6]=16 cells (5 PI)
7692 12:20:42.787404 u2DelayCellOfst[7]=16 cells (5 PI)
7693 12:20:42.793890 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7694 12:20:42.797545 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7695 12:20:42.797626 == TX Byte 1 ==
7696 12:20:42.800849 u2DelayCellOfst[8]=0 cells (0 PI)
7697 12:20:42.803763 u2DelayCellOfst[9]=3 cells (1 PI)
7698 12:20:42.807586 u2DelayCellOfst[10]=6 cells (2 PI)
7699 12:20:42.810381 u2DelayCellOfst[11]=3 cells (1 PI)
7700 12:20:42.813622 u2DelayCellOfst[12]=10 cells (3 PI)
7701 12:20:42.817382 u2DelayCellOfst[13]=13 cells (4 PI)
7702 12:20:42.820706 u2DelayCellOfst[14]=16 cells (5 PI)
7703 12:20:42.823720 u2DelayCellOfst[15]=10 cells (3 PI)
7704 12:20:42.827021 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7705 12:20:42.830638 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7706 12:20:42.833796 DramC Write-DBI on
7707 12:20:42.833880 ==
7708 12:20:42.837760 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 12:20:42.840903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 12:20:42.840992 ==
7711 12:20:42.841068
7712 12:20:42.841130
7713 12:20:42.844028 TX Vref Scan disable
7714 12:20:42.847376 == TX Byte 0 ==
7715 12:20:42.850823 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7716 12:20:42.853984 == TX Byte 1 ==
7717 12:20:42.857470 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7718 12:20:42.857552 DramC Write-DBI off
7719 12:20:42.857616
7720 12:20:42.860801 [DATLAT]
7721 12:20:42.860882 Freq=1600, CH0 RK0
7722 12:20:42.860946
7723 12:20:42.863876 DATLAT Default: 0xf
7724 12:20:42.863957 0, 0xFFFF, sum = 0
7725 12:20:42.867025 1, 0xFFFF, sum = 0
7726 12:20:42.867107 2, 0xFFFF, sum = 0
7727 12:20:42.870389 3, 0xFFFF, sum = 0
7728 12:20:42.870472 4, 0xFFFF, sum = 0
7729 12:20:42.873552 5, 0xFFFF, sum = 0
7730 12:20:42.873634 6, 0xFFFF, sum = 0
7731 12:20:42.877113 7, 0xFFFF, sum = 0
7732 12:20:42.877195 8, 0xFFFF, sum = 0
7733 12:20:42.880228 9, 0xFFFF, sum = 0
7734 12:20:42.883554 10, 0xFFFF, sum = 0
7735 12:20:42.883636 11, 0xFFFF, sum = 0
7736 12:20:42.887098 12, 0xFFFF, sum = 0
7737 12:20:42.887195 13, 0xFFFF, sum = 0
7738 12:20:42.890245 14, 0x0, sum = 1
7739 12:20:42.890327 15, 0x0, sum = 2
7740 12:20:42.893498 16, 0x0, sum = 3
7741 12:20:42.893580 17, 0x0, sum = 4
7742 12:20:42.893646 best_step = 15
7743 12:20:42.896896
7744 12:20:42.896981 ==
7745 12:20:42.900216 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 12:20:42.903528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 12:20:42.903609 ==
7748 12:20:42.903673 RX Vref Scan: 1
7749 12:20:42.903734
7750 12:20:42.906847 Set Vref Range= 24 -> 127
7751 12:20:42.906928
7752 12:20:42.910718 RX Vref 24 -> 127, step: 1
7753 12:20:42.910799
7754 12:20:42.913771 RX Delay 19 -> 252, step: 4
7755 12:20:42.913853
7756 12:20:42.917252 Set Vref, RX VrefLevel [Byte0]: 24
7757 12:20:42.920406 [Byte1]: 24
7758 12:20:42.920493
7759 12:20:42.924067 Set Vref, RX VrefLevel [Byte0]: 25
7760 12:20:42.927217 [Byte1]: 25
7761 12:20:42.927318
7762 12:20:42.930359 Set Vref, RX VrefLevel [Byte0]: 26
7763 12:20:42.933672 [Byte1]: 26
7764 12:20:42.936987
7765 12:20:42.937155 Set Vref, RX VrefLevel [Byte0]: 27
7766 12:20:42.940619 [Byte1]: 27
7767 12:20:42.944357
7768 12:20:42.944517 Set Vref, RX VrefLevel [Byte0]: 28
7769 12:20:42.947523 [Byte1]: 28
7770 12:20:42.952264
7771 12:20:42.952454 Set Vref, RX VrefLevel [Byte0]: 29
7772 12:20:42.955519 [Byte1]: 29
7773 12:20:42.959503
7774 12:20:42.959792 Set Vref, RX VrefLevel [Byte0]: 30
7775 12:20:42.963004 [Byte1]: 30
7776 12:20:42.967718
7777 12:20:42.968106 Set Vref, RX VrefLevel [Byte0]: 31
7778 12:20:42.970906 [Byte1]: 31
7779 12:20:42.974889
7780 12:20:42.975276 Set Vref, RX VrefLevel [Byte0]: 32
7781 12:20:42.978856 [Byte1]: 32
7782 12:20:42.982730
7783 12:20:42.983285 Set Vref, RX VrefLevel [Byte0]: 33
7784 12:20:42.986139 [Byte1]: 33
7785 12:20:42.990753
7786 12:20:42.991166 Set Vref, RX VrefLevel [Byte0]: 34
7787 12:20:42.993938 [Byte1]: 34
7788 12:20:42.998484
7789 12:20:42.998995 Set Vref, RX VrefLevel [Byte0]: 35
7790 12:20:43.001739 [Byte1]: 35
7791 12:20:43.005234
7792 12:20:43.005660 Set Vref, RX VrefLevel [Byte0]: 36
7793 12:20:43.008879 [Byte1]: 36
7794 12:20:43.013390
7795 12:20:43.013806 Set Vref, RX VrefLevel [Byte0]: 37
7796 12:20:43.016643 [Byte1]: 37
7797 12:20:43.020651
7798 12:20:43.021105 Set Vref, RX VrefLevel [Byte0]: 38
7799 12:20:43.023902 [Byte1]: 38
7800 12:20:43.028222
7801 12:20:43.028737 Set Vref, RX VrefLevel [Byte0]: 39
7802 12:20:43.031481 [Byte1]: 39
7803 12:20:43.035926
7804 12:20:43.036591 Set Vref, RX VrefLevel [Byte0]: 40
7805 12:20:43.039055 [Byte1]: 40
7806 12:20:43.043146
7807 12:20:43.043645 Set Vref, RX VrefLevel [Byte0]: 41
7808 12:20:43.046569 [Byte1]: 41
7809 12:20:43.051242
7810 12:20:43.051732 Set Vref, RX VrefLevel [Byte0]: 42
7811 12:20:43.054542 [Byte1]: 42
7812 12:20:43.058723
7813 12:20:43.059205 Set Vref, RX VrefLevel [Byte0]: 43
7814 12:20:43.061829 [Byte1]: 43
7815 12:20:43.066394
7816 12:20:43.066826 Set Vref, RX VrefLevel [Byte0]: 44
7817 12:20:43.069302 [Byte1]: 44
7818 12:20:43.073684
7819 12:20:43.074172 Set Vref, RX VrefLevel [Byte0]: 45
7820 12:20:43.076967 [Byte1]: 45
7821 12:20:43.081434
7822 12:20:43.081896 Set Vref, RX VrefLevel [Byte0]: 46
7823 12:20:43.084339 [Byte1]: 46
7824 12:20:43.088736
7825 12:20:43.089155 Set Vref, RX VrefLevel [Byte0]: 47
7826 12:20:43.092398 [Byte1]: 47
7827 12:20:43.096474
7828 12:20:43.096928 Set Vref, RX VrefLevel [Byte0]: 48
7829 12:20:43.099485 [Byte1]: 48
7830 12:20:43.104387
7831 12:20:43.104809 Set Vref, RX VrefLevel [Byte0]: 49
7832 12:20:43.107197 [Byte1]: 49
7833 12:20:43.111322
7834 12:20:43.111741 Set Vref, RX VrefLevel [Byte0]: 50
7835 12:20:43.115108 [Byte1]: 50
7836 12:20:43.119188
7837 12:20:43.119605 Set Vref, RX VrefLevel [Byte0]: 51
7838 12:20:43.122494 [Byte1]: 51
7839 12:20:43.126514
7840 12:20:43.126930 Set Vref, RX VrefLevel [Byte0]: 52
7841 12:20:43.129633 [Byte1]: 52
7842 12:20:43.134570
7843 12:20:43.135017 Set Vref, RX VrefLevel [Byte0]: 53
7844 12:20:43.137188 [Byte1]: 53
7845 12:20:43.141822
7846 12:20:43.142237 Set Vref, RX VrefLevel [Byte0]: 54
7847 12:20:43.145416 [Byte1]: 54
7848 12:20:43.149430
7849 12:20:43.149972 Set Vref, RX VrefLevel [Byte0]: 55
7850 12:20:43.152833 [Byte1]: 55
7851 12:20:43.156921
7852 12:20:43.157356 Set Vref, RX VrefLevel [Byte0]: 56
7853 12:20:43.160170 [Byte1]: 56
7854 12:20:43.164564
7855 12:20:43.165020 Set Vref, RX VrefLevel [Byte0]: 57
7856 12:20:43.167994 [Byte1]: 57
7857 12:20:43.172565
7858 12:20:43.172982 Set Vref, RX VrefLevel [Byte0]: 58
7859 12:20:43.175577 [Byte1]: 58
7860 12:20:43.179631
7861 12:20:43.180183 Set Vref, RX VrefLevel [Byte0]: 59
7862 12:20:43.182747 [Byte1]: 59
7863 12:20:43.187559
7864 12:20:43.188110 Set Vref, RX VrefLevel [Byte0]: 60
7865 12:20:43.190459 [Byte1]: 60
7866 12:20:43.194824
7867 12:20:43.195270 Set Vref, RX VrefLevel [Byte0]: 61
7868 12:20:43.198269 [Byte1]: 61
7869 12:20:43.202368
7870 12:20:43.202954 Set Vref, RX VrefLevel [Byte0]: 62
7871 12:20:43.205717 [Byte1]: 62
7872 12:20:43.209786
7873 12:20:43.210362 Set Vref, RX VrefLevel [Byte0]: 63
7874 12:20:43.212847 [Byte1]: 63
7875 12:20:43.217545
7876 12:20:43.218030 Set Vref, RX VrefLevel [Byte0]: 64
7877 12:20:43.221039 [Byte1]: 64
7878 12:20:43.225099
7879 12:20:43.225544 Set Vref, RX VrefLevel [Byte0]: 65
7880 12:20:43.228208 [Byte1]: 65
7881 12:20:43.232879
7882 12:20:43.233288 Set Vref, RX VrefLevel [Byte0]: 66
7883 12:20:43.235815 [Byte1]: 66
7884 12:20:43.240245
7885 12:20:43.240704 Set Vref, RX VrefLevel [Byte0]: 67
7886 12:20:43.243543 [Byte1]: 67
7887 12:20:43.247702
7888 12:20:43.248120 Set Vref, RX VrefLevel [Byte0]: 68
7889 12:20:43.251017 [Byte1]: 68
7890 12:20:43.255461
7891 12:20:43.255885 Set Vref, RX VrefLevel [Byte0]: 69
7892 12:20:43.258819 [Byte1]: 69
7893 12:20:43.263128
7894 12:20:43.263546 Set Vref, RX VrefLevel [Byte0]: 70
7895 12:20:43.266090 [Byte1]: 70
7896 12:20:43.270521
7897 12:20:43.271120 Set Vref, RX VrefLevel [Byte0]: 71
7898 12:20:43.273924 [Byte1]: 71
7899 12:20:43.278349
7900 12:20:43.278764 Set Vref, RX VrefLevel [Byte0]: 72
7901 12:20:43.281467 [Byte1]: 72
7902 12:20:43.285579
7903 12:20:43.285997 Set Vref, RX VrefLevel [Byte0]: 73
7904 12:20:43.289179 [Byte1]: 73
7905 12:20:43.293366
7906 12:20:43.293836 Set Vref, RX VrefLevel [Byte0]: 74
7907 12:20:43.296542 [Byte1]: 74
7908 12:20:43.300782
7909 12:20:43.301202 Set Vref, RX VrefLevel [Byte0]: 75
7910 12:20:43.304802 [Byte1]: 75
7911 12:20:43.308995
7912 12:20:43.309511 Set Vref, RX VrefLevel [Byte0]: 76
7913 12:20:43.311563 [Byte1]: 76
7914 12:20:43.316257
7915 12:20:43.316814 Set Vref, RX VrefLevel [Byte0]: 77
7916 12:20:43.319542 [Byte1]: 77
7917 12:20:43.323922
7918 12:20:43.324554 Final RX Vref Byte 0 = 57 to rank0
7919 12:20:43.327337 Final RX Vref Byte 1 = 62 to rank0
7920 12:20:43.330618 Final RX Vref Byte 0 = 57 to rank1
7921 12:20:43.333914 Final RX Vref Byte 1 = 62 to rank1==
7922 12:20:43.337546 Dram Type= 6, Freq= 0, CH_0, rank 0
7923 12:20:43.343898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7924 12:20:43.344538 ==
7925 12:20:43.344927 DQS Delay:
7926 12:20:43.345269 DQS0 = 0, DQS1 = 0
7927 12:20:43.346943 DQM Delay:
7928 12:20:43.347398 DQM0 = 134, DQM1 = 128
7929 12:20:43.350140 DQ Delay:
7930 12:20:43.353302 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7931 12:20:43.357029 DQ4 =132, DQ5 =124, DQ6 =142, DQ7 =138
7932 12:20:43.360084 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7933 12:20:43.363889 DQ12 =134, DQ13 =134, DQ14 =138, DQ15 =134
7934 12:20:43.364355
7935 12:20:43.364699
7936 12:20:43.365009
7937 12:20:43.367214 [DramC_TX_OE_Calibration] TA2
7938 12:20:43.370703 Original DQ_B0 (3 6) =30, OEN = 27
7939 12:20:43.373454 Original DQ_B1 (3 6) =30, OEN = 27
7940 12:20:43.376998 24, 0x0, End_B0=24 End_B1=24
7941 12:20:43.377424 25, 0x0, End_B0=25 End_B1=25
7942 12:20:43.380342 26, 0x0, End_B0=26 End_B1=26
7943 12:20:43.383645 27, 0x0, End_B0=27 End_B1=27
7944 12:20:43.387419 28, 0x0, End_B0=28 End_B1=28
7945 12:20:43.387844 29, 0x0, End_B0=29 End_B1=29
7946 12:20:43.390107 30, 0x0, End_B0=30 End_B1=30
7947 12:20:43.393201 31, 0x4141, End_B0=30 End_B1=30
7948 12:20:43.397244 Byte0 end_step=30 best_step=27
7949 12:20:43.400114 Byte1 end_step=30 best_step=27
7950 12:20:43.403765 Byte0 TX OE(2T, 0.5T) = (3, 3)
7951 12:20:43.404185 Byte1 TX OE(2T, 0.5T) = (3, 3)
7952 12:20:43.407032
7953 12:20:43.407536
7954 12:20:43.413607 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7955 12:20:43.416793 CH0 RK0: MR19=303, MR18=2521
7956 12:20:43.423293 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
7957 12:20:43.423777
7958 12:20:43.426736 ----->DramcWriteLeveling(PI) begin...
7959 12:20:43.427162 ==
7960 12:20:43.430460 Dram Type= 6, Freq= 0, CH_0, rank 1
7961 12:20:43.433837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7962 12:20:43.434262 ==
7963 12:20:43.436989 Write leveling (Byte 0): 36 => 36
7964 12:20:43.439946 Write leveling (Byte 1): 27 => 27
7965 12:20:43.443301 DramcWriteLeveling(PI) end<-----
7966 12:20:43.443814
7967 12:20:43.444145 ==
7968 12:20:43.446760 Dram Type= 6, Freq= 0, CH_0, rank 1
7969 12:20:43.449838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7970 12:20:43.450310 ==
7971 12:20:43.453289 [Gating] SW mode calibration
7972 12:20:43.460161 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7973 12:20:43.466778 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7974 12:20:43.470743 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7975 12:20:43.473907 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7976 12:20:43.479830 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7977 12:20:43.483036 1 4 12 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7978 12:20:43.486839 1 4 16 | B1->B0 | 3131 3737 | 1 1 | (1 1) (0 0)
7979 12:20:43.493457 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7980 12:20:43.496714 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7981 12:20:43.500062 1 4 28 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7982 12:20:43.507041 1 5 0 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7983 12:20:43.509915 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7984 12:20:43.513187 1 5 8 | B1->B0 | 3434 909 | 1 1 | (1 1) (0 0)
7985 12:20:43.520230 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
7986 12:20:43.523078 1 5 16 | B1->B0 | 2d2d 2424 | 1 0 | (1 0) (1 0)
7987 12:20:43.527376 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7988 12:20:43.533167 1 5 24 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7989 12:20:43.536577 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7990 12:20:43.539712 1 6 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
7991 12:20:43.546997 1 6 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (1 1)
7992 12:20:43.549861 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 12:20:43.552938 1 6 12 | B1->B0 | 2323 3736 | 0 1 | (0 0) (1 1)
7994 12:20:43.556215 1 6 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7995 12:20:43.562758 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7996 12:20:43.566317 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7997 12:20:43.569529 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 12:20:43.576278 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 12:20:43.579649 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 12:20:43.582698 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 12:20:43.589843 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8002 12:20:43.592992 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8003 12:20:43.596173 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8004 12:20:43.603011 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 12:20:43.606370 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 12:20:43.609333 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 12:20:43.616167 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 12:20:43.619465 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 12:20:43.622753 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 12:20:43.629666 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 12:20:43.632913 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 12:20:43.636170 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 12:20:43.642999 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 12:20:43.645791 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 12:20:43.649410 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 12:20:43.655657 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 12:20:43.659747 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8018 12:20:43.662575 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8019 12:20:43.665713 Total UI for P1: 0, mck2ui 16
8020 12:20:43.669169 best dqsien dly found for B0: ( 1, 9, 12)
8021 12:20:43.675693 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 12:20:43.676209 Total UI for P1: 0, mck2ui 16
8023 12:20:43.678884 best dqsien dly found for B1: ( 1, 9, 14)
8024 12:20:43.686272 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8025 12:20:43.688954 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8026 12:20:43.689376
8027 12:20:43.692507 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8028 12:20:43.696444 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8029 12:20:43.699559 [Gating] SW calibration Done
8030 12:20:43.700106 ==
8031 12:20:43.702886 Dram Type= 6, Freq= 0, CH_0, rank 1
8032 12:20:43.706105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8033 12:20:43.706688 ==
8034 12:20:43.708983 RX Vref Scan: 0
8035 12:20:43.709542
8036 12:20:43.709912 RX Vref 0 -> 0, step: 1
8037 12:20:43.710255
8038 12:20:43.712456 RX Delay 0 -> 252, step: 8
8039 12:20:43.715822 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8040 12:20:43.722694 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8041 12:20:43.725456 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8042 12:20:43.729109 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8043 12:20:43.732062 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8044 12:20:43.735537 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8045 12:20:43.742703 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8046 12:20:43.745679 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8047 12:20:43.748821 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8048 12:20:43.751903 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8049 12:20:43.755313 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8050 12:20:43.762439 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8051 12:20:43.765426 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8052 12:20:43.768580 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8053 12:20:43.772362 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8054 12:20:43.775784 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8055 12:20:43.776507 ==
8056 12:20:43.778442 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 12:20:43.785244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 12:20:43.785747 ==
8059 12:20:43.786083 DQS Delay:
8060 12:20:43.788530 DQS0 = 0, DQS1 = 0
8061 12:20:43.788946 DQM Delay:
8062 12:20:43.792232 DQM0 = 137, DQM1 = 128
8063 12:20:43.792701 DQ Delay:
8064 12:20:43.795616 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8065 12:20:43.799252 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8066 12:20:43.802162 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8067 12:20:43.805064 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8068 12:20:43.805480
8069 12:20:43.805804
8070 12:20:43.806108 ==
8071 12:20:43.808273 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 12:20:43.815514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 12:20:43.816031 ==
8074 12:20:43.816402
8075 12:20:43.816711
8076 12:20:43.817075 TX Vref Scan disable
8077 12:20:43.818876 == TX Byte 0 ==
8078 12:20:43.822376 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8079 12:20:43.829113 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8080 12:20:43.829631 == TX Byte 1 ==
8081 12:20:43.832014 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8082 12:20:43.838373 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8083 12:20:43.838875 ==
8084 12:20:43.842367 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 12:20:43.845148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 12:20:43.845567 ==
8087 12:20:43.858597
8088 12:20:43.862088 TX Vref early break, caculate TX vref
8089 12:20:43.865435 TX Vref=16, minBit 1, minWin=23, winSum=387
8090 12:20:43.868843 TX Vref=18, minBit 0, minWin=24, winSum=400
8091 12:20:43.872257 TX Vref=20, minBit 4, minWin=23, winSum=402
8092 12:20:43.875692 TX Vref=22, minBit 1, minWin=24, winSum=410
8093 12:20:43.878567 TX Vref=24, minBit 1, minWin=24, winSum=418
8094 12:20:43.885162 TX Vref=26, minBit 7, minWin=25, winSum=429
8095 12:20:43.888843 TX Vref=28, minBit 3, minWin=25, winSum=422
8096 12:20:43.891892 TX Vref=30, minBit 1, minWin=25, winSum=417
8097 12:20:43.895161 TX Vref=32, minBit 1, minWin=24, winSum=408
8098 12:20:43.898470 TX Vref=34, minBit 1, minWin=24, winSum=401
8099 12:20:43.904948 [TxChooseVref] Worse bit 7, Min win 25, Win sum 429, Final Vref 26
8100 12:20:43.905464
8101 12:20:43.908311 Final TX Range 0 Vref 26
8102 12:20:43.908875
8103 12:20:43.909235 ==
8104 12:20:43.911835 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 12:20:43.915345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 12:20:43.915862 ==
8107 12:20:43.916197
8108 12:20:43.916552
8109 12:20:43.918911 TX Vref Scan disable
8110 12:20:43.925337 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8111 12:20:43.925938 == TX Byte 0 ==
8112 12:20:43.928519 u2DelayCellOfst[0]=10 cells (3 PI)
8113 12:20:43.931725 u2DelayCellOfst[1]=13 cells (4 PI)
8114 12:20:43.934791 u2DelayCellOfst[2]=10 cells (3 PI)
8115 12:20:43.938341 u2DelayCellOfst[3]=10 cells (3 PI)
8116 12:20:43.941263 u2DelayCellOfst[4]=6 cells (2 PI)
8117 12:20:43.944799 u2DelayCellOfst[5]=0 cells (0 PI)
8118 12:20:43.948537 u2DelayCellOfst[6]=16 cells (5 PI)
8119 12:20:43.951561 u2DelayCellOfst[7]=13 cells (4 PI)
8120 12:20:43.954533 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8121 12:20:43.958256 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8122 12:20:43.961732 == TX Byte 1 ==
8123 12:20:43.964434 u2DelayCellOfst[8]=3 cells (1 PI)
8124 12:20:43.964944 u2DelayCellOfst[9]=0 cells (0 PI)
8125 12:20:43.968016 u2DelayCellOfst[10]=6 cells (2 PI)
8126 12:20:43.971143 u2DelayCellOfst[11]=6 cells (2 PI)
8127 12:20:43.975198 u2DelayCellOfst[12]=10 cells (3 PI)
8128 12:20:43.978037 u2DelayCellOfst[13]=13 cells (4 PI)
8129 12:20:43.981261 u2DelayCellOfst[14]=16 cells (5 PI)
8130 12:20:43.984798 u2DelayCellOfst[15]=10 cells (3 PI)
8131 12:20:43.988461 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8132 12:20:43.994953 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8133 12:20:43.995517 DramC Write-DBI on
8134 12:20:43.995880 ==
8135 12:20:43.997993 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 12:20:44.005015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 12:20:44.005572 ==
8138 12:20:44.005939
8139 12:20:44.006277
8140 12:20:44.006598 TX Vref Scan disable
8141 12:20:44.008054 == TX Byte 0 ==
8142 12:20:44.011997 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8143 12:20:44.015258 == TX Byte 1 ==
8144 12:20:44.018227 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8145 12:20:44.021990 DramC Write-DBI off
8146 12:20:44.022403
8147 12:20:44.022790 [DATLAT]
8148 12:20:44.023259 Freq=1600, CH0 RK1
8149 12:20:44.023637
8150 12:20:44.024769 DATLAT Default: 0xf
8151 12:20:44.025184 0, 0xFFFF, sum = 0
8152 12:20:44.028487 1, 0xFFFF, sum = 0
8153 12:20:44.028927 2, 0xFFFF, sum = 0
8154 12:20:44.031754 3, 0xFFFF, sum = 0
8155 12:20:44.034519 4, 0xFFFF, sum = 0
8156 12:20:44.034995 5, 0xFFFF, sum = 0
8157 12:20:44.038524 6, 0xFFFF, sum = 0
8158 12:20:44.038946 7, 0xFFFF, sum = 0
8159 12:20:44.041600 8, 0xFFFF, sum = 0
8160 12:20:44.042020 9, 0xFFFF, sum = 0
8161 12:20:44.044825 10, 0xFFFF, sum = 0
8162 12:20:44.045246 11, 0xFFFF, sum = 0
8163 12:20:44.047881 12, 0xFFFF, sum = 0
8164 12:20:44.048328 13, 0xFFFF, sum = 0
8165 12:20:44.051518 14, 0x0, sum = 1
8166 12:20:44.052040 15, 0x0, sum = 2
8167 12:20:44.054418 16, 0x0, sum = 3
8168 12:20:44.054906 17, 0x0, sum = 4
8169 12:20:44.058169 best_step = 15
8170 12:20:44.058582
8171 12:20:44.058906 ==
8172 12:20:44.061129 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 12:20:44.064638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 12:20:44.065055 ==
8175 12:20:44.067838 RX Vref Scan: 0
8176 12:20:44.068399
8177 12:20:44.068740 RX Vref 0 -> 0, step: 1
8178 12:20:44.069140
8179 12:20:44.071316 RX Delay 19 -> 252, step: 4
8180 12:20:44.074536 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8181 12:20:44.080988 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8182 12:20:44.084543 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8183 12:20:44.088205 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8184 12:20:44.091304 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8185 12:20:44.095086 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8186 12:20:44.101265 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8187 12:20:44.104467 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8188 12:20:44.108056 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8189 12:20:44.111033 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8190 12:20:44.114301 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8191 12:20:44.121063 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8192 12:20:44.124872 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8193 12:20:44.127616 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8194 12:20:44.131164 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8195 12:20:44.134604 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8196 12:20:44.138352 ==
8197 12:20:44.140837 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 12:20:44.144278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 12:20:44.144849 ==
8200 12:20:44.145180 DQS Delay:
8201 12:20:44.147335 DQS0 = 0, DQS1 = 0
8202 12:20:44.147750 DQM Delay:
8203 12:20:44.150699 DQM0 = 134, DQM1 = 127
8204 12:20:44.151114 DQ Delay:
8205 12:20:44.153947 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8206 12:20:44.157481 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8207 12:20:44.161194 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8208 12:20:44.164318 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8209 12:20:44.164755
8210 12:20:44.165078
8211 12:20:44.165379
8212 12:20:44.167371 [DramC_TX_OE_Calibration] TA2
8213 12:20:44.170493 Original DQ_B0 (3 6) =30, OEN = 27
8214 12:20:44.174277 Original DQ_B1 (3 6) =30, OEN = 27
8215 12:20:44.177785 24, 0x0, End_B0=24 End_B1=24
8216 12:20:44.180729 25, 0x0, End_B0=25 End_B1=25
8217 12:20:44.181153 26, 0x0, End_B0=26 End_B1=26
8218 12:20:44.184158 27, 0x0, End_B0=27 End_B1=27
8219 12:20:44.187270 28, 0x0, End_B0=28 End_B1=28
8220 12:20:44.190338 29, 0x0, End_B0=29 End_B1=29
8221 12:20:44.194606 30, 0x0, End_B0=30 End_B1=30
8222 12:20:44.195127 31, 0x4141, End_B0=30 End_B1=30
8223 12:20:44.197397 Byte0 end_step=30 best_step=27
8224 12:20:44.200324 Byte1 end_step=30 best_step=27
8225 12:20:44.204505 Byte0 TX OE(2T, 0.5T) = (3, 3)
8226 12:20:44.207659 Byte1 TX OE(2T, 0.5T) = (3, 3)
8227 12:20:44.208175
8228 12:20:44.208554
8229 12:20:44.213794 [DQSOSCAuto] RK1, (LSB)MR18= 0x2209, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
8230 12:20:44.216978 CH0 RK1: MR19=303, MR18=2209
8231 12:20:44.223889 CH0_RK1: MR19=0x303, MR18=0x2209, DQSOSC=392, MR23=63, INC=24, DEC=16
8232 12:20:44.227401 [RxdqsGatingPostProcess] freq 1600
8233 12:20:44.233774 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8234 12:20:44.234286 best DQS0 dly(2T, 0.5T) = (1, 1)
8235 12:20:44.237056 best DQS1 dly(2T, 0.5T) = (1, 1)
8236 12:20:44.240698 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8237 12:20:44.243698 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8238 12:20:44.247375 best DQS0 dly(2T, 0.5T) = (1, 1)
8239 12:20:44.250540 best DQS1 dly(2T, 0.5T) = (1, 1)
8240 12:20:44.253949 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8241 12:20:44.256910 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8242 12:20:44.260050 Pre-setting of DQS Precalculation
8243 12:20:44.263784 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8244 12:20:44.264537 ==
8245 12:20:44.267013 Dram Type= 6, Freq= 0, CH_1, rank 0
8246 12:20:44.273466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8247 12:20:44.274012 ==
8248 12:20:44.276612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8249 12:20:44.283433 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8250 12:20:44.286636 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8251 12:20:44.293319 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8252 12:20:44.301196 [CA 0] Center 41 (12~71) winsize 60
8253 12:20:44.305034 [CA 1] Center 41 (12~71) winsize 60
8254 12:20:44.308078 [CA 2] Center 38 (9~68) winsize 60
8255 12:20:44.311191 [CA 3] Center 37 (8~66) winsize 59
8256 12:20:44.314489 [CA 4] Center 37 (8~67) winsize 60
8257 12:20:44.318048 [CA 5] Center 36 (7~66) winsize 60
8258 12:20:44.318607
8259 12:20:44.320900 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8260 12:20:44.321356
8261 12:20:44.325217 [CATrainingPosCal] consider 1 rank data
8262 12:20:44.328365 u2DelayCellTimex100 = 290/100 ps
8263 12:20:44.331537 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8264 12:20:44.337660 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8265 12:20:44.341198 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8266 12:20:44.345051 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8267 12:20:44.347974 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8268 12:20:44.351892 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8269 12:20:44.352501
8270 12:20:44.354766 CA PerBit enable=1, Macro0, CA PI delay=36
8271 12:20:44.355222
8272 12:20:44.358280 [CBTSetCACLKResult] CA Dly = 36
8273 12:20:44.361352 CS Dly: 11 (0~42)
8274 12:20:44.364933 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8275 12:20:44.367775 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8276 12:20:44.368359 ==
8277 12:20:44.371245 Dram Type= 6, Freq= 0, CH_1, rank 1
8278 12:20:44.374008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 12:20:44.377692 ==
8280 12:20:44.381104 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8281 12:20:44.384329 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8282 12:20:44.391037 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8283 12:20:44.394241 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8284 12:20:44.404539 [CA 0] Center 42 (12~72) winsize 61
8285 12:20:44.407811 [CA 1] Center 41 (12~71) winsize 60
8286 12:20:44.410966 [CA 2] Center 38 (9~68) winsize 60
8287 12:20:44.414530 [CA 3] Center 38 (8~68) winsize 61
8288 12:20:44.417318 [CA 4] Center 39 (9~69) winsize 61
8289 12:20:44.421101 [CA 5] Center 37 (8~67) winsize 60
8290 12:20:44.421624
8291 12:20:44.424511 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8292 12:20:44.425025
8293 12:20:44.427374 [CATrainingPosCal] consider 2 rank data
8294 12:20:44.430978 u2DelayCellTimex100 = 290/100 ps
8295 12:20:44.433912 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8296 12:20:44.440552 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8297 12:20:44.444504 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8298 12:20:44.447706 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8299 12:20:44.450758 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8300 12:20:44.454276 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8301 12:20:44.454682
8302 12:20:44.457578 CA PerBit enable=1, Macro0, CA PI delay=37
8303 12:20:44.457989
8304 12:20:44.460847 [CBTSetCACLKResult] CA Dly = 37
8305 12:20:44.464157 CS Dly: 12 (0~45)
8306 12:20:44.468040 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8307 12:20:44.470936 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8308 12:20:44.471350
8309 12:20:44.474428 ----->DramcWriteLeveling(PI) begin...
8310 12:20:44.474937 ==
8311 12:20:44.477651 Dram Type= 6, Freq= 0, CH_1, rank 0
8312 12:20:44.484140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 12:20:44.484736 ==
8314 12:20:44.487318 Write leveling (Byte 0): 25 => 25
8315 12:20:44.487731 Write leveling (Byte 1): 26 => 26
8316 12:20:44.490413 DramcWriteLeveling(PI) end<-----
8317 12:20:44.490819
8318 12:20:44.491137 ==
8319 12:20:44.494135 Dram Type= 6, Freq= 0, CH_1, rank 0
8320 12:20:44.501383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 12:20:44.501896 ==
8322 12:20:44.504010 [Gating] SW mode calibration
8323 12:20:44.511078 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8324 12:20:44.514117 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8325 12:20:44.520494 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 12:20:44.523902 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 12:20:44.527640 1 4 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
8328 12:20:44.533918 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8329 12:20:44.537199 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 12:20:44.540509 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 12:20:44.547553 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 12:20:44.550567 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 12:20:44.553751 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 12:20:44.557035 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 12:20:44.563875 1 5 8 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 0)
8336 12:20:44.567122 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
8337 12:20:44.570818 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 12:20:44.577265 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 12:20:44.580425 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 12:20:44.584463 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 12:20:44.590567 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 12:20:44.593739 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 12:20:44.597445 1 6 8 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
8344 12:20:44.603872 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8345 12:20:44.607399 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 12:20:44.610415 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 12:20:44.617003 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 12:20:44.620039 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 12:20:44.623565 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 12:20:44.630463 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 12:20:44.633623 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 12:20:44.636732 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8353 12:20:44.643701 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8354 12:20:44.646719 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 12:20:44.650083 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 12:20:44.656674 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 12:20:44.660246 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 12:20:44.663199 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 12:20:44.670110 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 12:20:44.673478 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 12:20:44.676799 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 12:20:44.683755 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 12:20:44.686666 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 12:20:44.690566 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 12:20:44.693655 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 12:20:44.700050 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 12:20:44.703373 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8368 12:20:44.706860 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8369 12:20:44.713292 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 12:20:44.716563 Total UI for P1: 0, mck2ui 16
8371 12:20:44.720097 best dqsien dly found for B0: ( 1, 9, 10)
8372 12:20:44.720645 Total UI for P1: 0, mck2ui 16
8373 12:20:44.726796 best dqsien dly found for B1: ( 1, 9, 10)
8374 12:20:44.730354 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8375 12:20:44.733032 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8376 12:20:44.733483
8377 12:20:44.736573 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8378 12:20:44.740230 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8379 12:20:44.743393 [Gating] SW calibration Done
8380 12:20:44.743799 ==
8381 12:20:44.746434 Dram Type= 6, Freq= 0, CH_1, rank 0
8382 12:20:44.750116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8383 12:20:44.750526 ==
8384 12:20:44.753039 RX Vref Scan: 0
8385 12:20:44.753445
8386 12:20:44.756383 RX Vref 0 -> 0, step: 1
8387 12:20:44.756790
8388 12:20:44.757108 RX Delay 0 -> 252, step: 8
8389 12:20:44.763572 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8390 12:20:44.766764 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8391 12:20:44.769870 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8392 12:20:44.772922 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8393 12:20:44.776466 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8394 12:20:44.779790 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8395 12:20:44.786184 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8396 12:20:44.789739 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8397 12:20:44.792993 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8398 12:20:44.796387 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8399 12:20:44.799826 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8400 12:20:44.806501 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8401 12:20:44.809901 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8402 12:20:44.813115 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8403 12:20:44.816341 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8404 12:20:44.819939 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8405 12:20:44.823094 ==
8406 12:20:44.826835 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 12:20:44.829770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 12:20:44.830291 ==
8409 12:20:44.830623 DQS Delay:
8410 12:20:44.833596 DQS0 = 0, DQS1 = 0
8411 12:20:44.834118 DQM Delay:
8412 12:20:44.836637 DQM0 = 135, DQM1 = 132
8413 12:20:44.837052 DQ Delay:
8414 12:20:44.840239 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8415 12:20:44.843329 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8416 12:20:44.846639 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8417 12:20:44.849918 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8418 12:20:44.850514
8419 12:20:44.851058
8420 12:20:44.851543 ==
8421 12:20:44.852907 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 12:20:44.859718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 12:20:44.860181 ==
8424 12:20:44.860613
8425 12:20:44.861072
8426 12:20:44.861584 TX Vref Scan disable
8427 12:20:44.862982 == TX Byte 0 ==
8428 12:20:44.866317 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8429 12:20:44.873157 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8430 12:20:44.873266 == TX Byte 1 ==
8431 12:20:44.876038 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8432 12:20:44.882816 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8433 12:20:44.882923 ==
8434 12:20:44.885895 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 12:20:44.889213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 12:20:44.889294 ==
8437 12:20:44.901305
8438 12:20:44.904917 TX Vref early break, caculate TX vref
8439 12:20:44.907950 TX Vref=16, minBit 0, minWin=23, winSum=383
8440 12:20:44.911105 TX Vref=18, minBit 0, minWin=23, winSum=388
8441 12:20:44.914799 TX Vref=20, minBit 6, minWin=23, winSum=399
8442 12:20:44.917699 TX Vref=22, minBit 0, minWin=24, winSum=410
8443 12:20:44.921130 TX Vref=24, minBit 0, minWin=25, winSum=418
8444 12:20:44.927570 TX Vref=26, minBit 0, minWin=25, winSum=424
8445 12:20:44.931250 TX Vref=28, minBit 0, minWin=25, winSum=427
8446 12:20:44.934548 TX Vref=30, minBit 0, minWin=25, winSum=418
8447 12:20:44.937984 TX Vref=32, minBit 6, minWin=24, winSum=413
8448 12:20:44.940930 TX Vref=34, minBit 0, minWin=24, winSum=404
8449 12:20:44.947707 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 28
8450 12:20:44.947881
8451 12:20:44.951340 Final TX Range 0 Vref 28
8452 12:20:44.951542
8453 12:20:44.951740 ==
8454 12:20:44.954206 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 12:20:44.957783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 12:20:44.958026 ==
8457 12:20:44.958215
8458 12:20:44.958392
8459 12:20:44.961399 TX Vref Scan disable
8460 12:20:44.968478 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8461 12:20:44.968779 == TX Byte 0 ==
8462 12:20:44.971599 u2DelayCellOfst[0]=20 cells (6 PI)
8463 12:20:44.974462 u2DelayCellOfst[1]=13 cells (4 PI)
8464 12:20:44.977934 u2DelayCellOfst[2]=0 cells (0 PI)
8465 12:20:44.980990 u2DelayCellOfst[3]=10 cells (3 PI)
8466 12:20:44.985054 u2DelayCellOfst[4]=13 cells (4 PI)
8467 12:20:44.988160 u2DelayCellOfst[5]=20 cells (6 PI)
8468 12:20:44.991313 u2DelayCellOfst[6]=20 cells (6 PI)
8469 12:20:44.991730 u2DelayCellOfst[7]=6 cells (2 PI)
8470 12:20:44.998026 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8471 12:20:45.001218 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8472 12:20:45.001638 == TX Byte 1 ==
8473 12:20:45.004769 u2DelayCellOfst[8]=0 cells (0 PI)
8474 12:20:45.007687 u2DelayCellOfst[9]=3 cells (1 PI)
8475 12:20:45.011558 u2DelayCellOfst[10]=13 cells (4 PI)
8476 12:20:45.014948 u2DelayCellOfst[11]=3 cells (1 PI)
8477 12:20:45.018116 u2DelayCellOfst[12]=16 cells (5 PI)
8478 12:20:45.021441 u2DelayCellOfst[13]=16 cells (5 PI)
8479 12:20:45.024704 u2DelayCellOfst[14]=16 cells (5 PI)
8480 12:20:45.027828 u2DelayCellOfst[15]=16 cells (5 PI)
8481 12:20:45.031083 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8482 12:20:45.037886 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8483 12:20:45.038330 DramC Write-DBI on
8484 12:20:45.038667 ==
8485 12:20:45.041530 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 12:20:45.044796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 12:20:45.045224 ==
8488 12:20:45.047766
8489 12:20:45.048200
8490 12:20:45.048590 TX Vref Scan disable
8491 12:20:45.051356 == TX Byte 0 ==
8492 12:20:45.054381 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8493 12:20:45.057507 == TX Byte 1 ==
8494 12:20:45.060990 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8495 12:20:45.064266 DramC Write-DBI off
8496 12:20:45.064750
8497 12:20:45.064999 [DATLAT]
8498 12:20:45.065218 Freq=1600, CH1 RK0
8499 12:20:45.065431
8500 12:20:45.067363 DATLAT Default: 0xf
8501 12:20:45.067660 0, 0xFFFF, sum = 0
8502 12:20:45.070653 1, 0xFFFF, sum = 0
8503 12:20:45.074023 2, 0xFFFF, sum = 0
8504 12:20:45.074325 3, 0xFFFF, sum = 0
8505 12:20:45.077841 4, 0xFFFF, sum = 0
8506 12:20:45.078159 5, 0xFFFF, sum = 0
8507 12:20:45.080314 6, 0xFFFF, sum = 0
8508 12:20:45.080545 7, 0xFFFF, sum = 0
8509 12:20:45.083913 8, 0xFFFF, sum = 0
8510 12:20:45.084238 9, 0xFFFF, sum = 0
8511 12:20:45.087277 10, 0xFFFF, sum = 0
8512 12:20:45.087504 11, 0xFFFF, sum = 0
8513 12:20:45.090303 12, 0xFFFF, sum = 0
8514 12:20:45.090546 13, 0xFFFF, sum = 0
8515 12:20:45.094163 14, 0x0, sum = 1
8516 12:20:45.094392 15, 0x0, sum = 2
8517 12:20:45.097485 16, 0x0, sum = 3
8518 12:20:45.097714 17, 0x0, sum = 4
8519 12:20:45.100726 best_step = 15
8520 12:20:45.100950
8521 12:20:45.101127 ==
8522 12:20:45.103839 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 12:20:45.107562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 12:20:45.107788 ==
8525 12:20:45.110481 RX Vref Scan: 1
8526 12:20:45.110732
8527 12:20:45.110913 Set Vref Range= 24 -> 127
8528 12:20:45.111079
8529 12:20:45.113813 RX Vref 24 -> 127, step: 1
8530 12:20:45.113895
8531 12:20:45.116965 RX Delay 27 -> 252, step: 4
8532 12:20:45.117047
8533 12:20:45.120458 Set Vref, RX VrefLevel [Byte0]: 24
8534 12:20:45.123892 [Byte1]: 24
8535 12:20:45.123972
8536 12:20:45.127101 Set Vref, RX VrefLevel [Byte0]: 25
8537 12:20:45.130375 [Byte1]: 25
8538 12:20:45.130456
8539 12:20:45.133837 Set Vref, RX VrefLevel [Byte0]: 26
8540 12:20:45.136856 [Byte1]: 26
8541 12:20:45.140662
8542 12:20:45.140741 Set Vref, RX VrefLevel [Byte0]: 27
8543 12:20:45.143870 [Byte1]: 27
8544 12:20:45.148572
8545 12:20:45.148652 Set Vref, RX VrefLevel [Byte0]: 28
8546 12:20:45.151871 [Byte1]: 28
8547 12:20:45.156318
8548 12:20:45.156740 Set Vref, RX VrefLevel [Byte0]: 29
8549 12:20:45.159870 [Byte1]: 29
8550 12:20:45.163949
8551 12:20:45.164563 Set Vref, RX VrefLevel [Byte0]: 30
8552 12:20:45.166985 [Byte1]: 30
8553 12:20:45.171522
8554 12:20:45.171971 Set Vref, RX VrefLevel [Byte0]: 31
8555 12:20:45.174875 [Byte1]: 31
8556 12:20:45.179020
8557 12:20:45.179435 Set Vref, RX VrefLevel [Byte0]: 32
8558 12:20:45.182233 [Byte1]: 32
8559 12:20:45.186660
8560 12:20:45.187070 Set Vref, RX VrefLevel [Byte0]: 33
8561 12:20:45.189750 [Byte1]: 33
8562 12:20:45.193865
8563 12:20:45.194277 Set Vref, RX VrefLevel [Byte0]: 34
8564 12:20:45.197328 [Byte1]: 34
8565 12:20:45.201523
8566 12:20:45.201932 Set Vref, RX VrefLevel [Byte0]: 35
8567 12:20:45.204643 [Byte1]: 35
8568 12:20:45.209057
8569 12:20:45.209467 Set Vref, RX VrefLevel [Byte0]: 36
8570 12:20:45.212371 [Byte1]: 36
8571 12:20:45.216420
8572 12:20:45.216877 Set Vref, RX VrefLevel [Byte0]: 37
8573 12:20:45.219809 [Byte1]: 37
8574 12:20:45.224126
8575 12:20:45.224777 Set Vref, RX VrefLevel [Byte0]: 38
8576 12:20:45.227619 [Byte1]: 38
8577 12:20:45.231926
8578 12:20:45.232380 Set Vref, RX VrefLevel [Byte0]: 39
8579 12:20:45.235067 [Byte1]: 39
8580 12:20:45.239018
8581 12:20:45.239438 Set Vref, RX VrefLevel [Byte0]: 40
8582 12:20:45.242457 [Byte1]: 40
8583 12:20:45.246882
8584 12:20:45.247296 Set Vref, RX VrefLevel [Byte0]: 41
8585 12:20:45.250072 [Byte1]: 41
8586 12:20:45.253906
8587 12:20:45.254319 Set Vref, RX VrefLevel [Byte0]: 42
8588 12:20:45.258004 [Byte1]: 42
8589 12:20:45.261456
8590 12:20:45.261884 Set Vref, RX VrefLevel [Byte0]: 43
8591 12:20:45.264848 [Byte1]: 43
8592 12:20:45.269320
8593 12:20:45.269862 Set Vref, RX VrefLevel [Byte0]: 44
8594 12:20:45.272500 [Byte1]: 44
8595 12:20:45.277127
8596 12:20:45.277631 Set Vref, RX VrefLevel [Byte0]: 45
8597 12:20:45.280056 [Byte1]: 45
8598 12:20:45.284110
8599 12:20:45.284563 Set Vref, RX VrefLevel [Byte0]: 46
8600 12:20:45.287459 [Byte1]: 46
8601 12:20:45.291872
8602 12:20:45.292555 Set Vref, RX VrefLevel [Byte0]: 47
8603 12:20:45.295093 [Byte1]: 47
8604 12:20:45.300026
8605 12:20:45.300497 Set Vref, RX VrefLevel [Byte0]: 48
8606 12:20:45.302893 [Byte1]: 48
8607 12:20:45.306874
8608 12:20:45.307287 Set Vref, RX VrefLevel [Byte0]: 49
8609 12:20:45.310463 [Byte1]: 49
8610 12:20:45.314293
8611 12:20:45.314707 Set Vref, RX VrefLevel [Byte0]: 50
8612 12:20:45.317729 [Byte1]: 50
8613 12:20:45.322110
8614 12:20:45.322549 Set Vref, RX VrefLevel [Byte0]: 51
8615 12:20:45.325534 [Byte1]: 51
8616 12:20:45.329848
8617 12:20:45.330365 Set Vref, RX VrefLevel [Byte0]: 52
8618 12:20:45.333205 [Byte1]: 52
8619 12:20:45.337185
8620 12:20:45.337698 Set Vref, RX VrefLevel [Byte0]: 53
8621 12:20:45.340465 [Byte1]: 53
8622 12:20:45.344777
8623 12:20:45.345214 Set Vref, RX VrefLevel [Byte0]: 54
8624 12:20:45.347670 [Byte1]: 54
8625 12:20:45.351897
8626 12:20:45.352398 Set Vref, RX VrefLevel [Byte0]: 55
8627 12:20:45.355164 [Byte1]: 55
8628 12:20:45.359601
8629 12:20:45.360015 Set Vref, RX VrefLevel [Byte0]: 56
8630 12:20:45.362996 [Byte1]: 56
8631 12:20:45.367364
8632 12:20:45.367779 Set Vref, RX VrefLevel [Byte0]: 57
8633 12:20:45.370298 [Byte1]: 57
8634 12:20:45.374285
8635 12:20:45.374700 Set Vref, RX VrefLevel [Byte0]: 58
8636 12:20:45.377933 [Byte1]: 58
8637 12:20:45.382460
8638 12:20:45.382872 Set Vref, RX VrefLevel [Byte0]: 59
8639 12:20:45.385776 [Byte1]: 59
8640 12:20:45.389761
8641 12:20:45.390176 Set Vref, RX VrefLevel [Byte0]: 60
8642 12:20:45.392900 [Byte1]: 60
8643 12:20:45.397171
8644 12:20:45.397581 Set Vref, RX VrefLevel [Byte0]: 61
8645 12:20:45.400238 [Byte1]: 61
8646 12:20:45.404736
8647 12:20:45.405314 Set Vref, RX VrefLevel [Byte0]: 62
8648 12:20:45.407899 [Byte1]: 62
8649 12:20:45.412666
8650 12:20:45.413174 Set Vref, RX VrefLevel [Byte0]: 63
8651 12:20:45.415793 [Byte1]: 63
8652 12:20:45.420171
8653 12:20:45.420778 Set Vref, RX VrefLevel [Byte0]: 64
8654 12:20:45.423365 [Byte1]: 64
8655 12:20:45.427174
8656 12:20:45.427758 Set Vref, RX VrefLevel [Byte0]: 65
8657 12:20:45.430598 [Byte1]: 65
8658 12:20:45.434977
8659 12:20:45.435553 Set Vref, RX VrefLevel [Byte0]: 66
8660 12:20:45.438008 [Byte1]: 66
8661 12:20:45.442422
8662 12:20:45.442823 Set Vref, RX VrefLevel [Byte0]: 67
8663 12:20:45.445665 [Byte1]: 67
8664 12:20:45.449924
8665 12:20:45.450147 Set Vref, RX VrefLevel [Byte0]: 68
8666 12:20:45.452821 [Byte1]: 68
8667 12:20:45.457122
8668 12:20:45.457428 Set Vref, RX VrefLevel [Byte0]: 69
8669 12:20:45.460348 [Byte1]: 69
8670 12:20:45.465036
8671 12:20:45.465340 Set Vref, RX VrefLevel [Byte0]: 70
8672 12:20:45.468243 [Byte1]: 70
8673 12:20:45.472098
8674 12:20:45.472178 Set Vref, RX VrefLevel [Byte0]: 71
8675 12:20:45.475750 [Byte1]: 71
8676 12:20:45.480115
8677 12:20:45.480202 Set Vref, RX VrefLevel [Byte0]: 72
8678 12:20:45.483182 [Byte1]: 72
8679 12:20:45.487614
8680 12:20:45.487720 Set Vref, RX VrefLevel [Byte0]: 73
8681 12:20:45.490916 [Byte1]: 73
8682 12:20:45.495054
8683 12:20:45.495162 Set Vref, RX VrefLevel [Byte0]: 74
8684 12:20:45.498121 [Byte1]: 74
8685 12:20:45.502648
8686 12:20:45.502728 Set Vref, RX VrefLevel [Byte0]: 75
8687 12:20:45.505788 [Byte1]: 75
8688 12:20:45.510317
8689 12:20:45.510425 Set Vref, RX VrefLevel [Byte0]: 76
8690 12:20:45.513437 [Byte1]: 76
8691 12:20:45.517368
8692 12:20:45.517449 Set Vref, RX VrefLevel [Byte0]: 77
8693 12:20:45.520616 [Byte1]: 77
8694 12:20:45.524969
8695 12:20:45.525049 Set Vref, RX VrefLevel [Byte0]: 78
8696 12:20:45.528158 [Byte1]: 78
8697 12:20:45.532563
8698 12:20:45.532668 Final RX Vref Byte 0 = 57 to rank0
8699 12:20:45.536173 Final RX Vref Byte 1 = 57 to rank0
8700 12:20:45.539298 Final RX Vref Byte 0 = 57 to rank1
8701 12:20:45.542579 Final RX Vref Byte 1 = 57 to rank1==
8702 12:20:45.546165 Dram Type= 6, Freq= 0, CH_1, rank 0
8703 12:20:45.552189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8704 12:20:45.552337 ==
8705 12:20:45.552404 DQS Delay:
8706 12:20:45.552463 DQS0 = 0, DQS1 = 0
8707 12:20:45.555522 DQM Delay:
8708 12:20:45.555602 DQM0 = 134, DQM1 = 131
8709 12:20:45.559269 DQ Delay:
8710 12:20:45.562392 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8711 12:20:45.566150 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =132
8712 12:20:45.569477 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8713 12:20:45.572955 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8714 12:20:45.573035
8715 12:20:45.573099
8716 12:20:45.573157
8717 12:20:45.576070 [DramC_TX_OE_Calibration] TA2
8718 12:20:45.579051 Original DQ_B0 (3 6) =30, OEN = 27
8719 12:20:45.582551 Original DQ_B1 (3 6) =30, OEN = 27
8720 12:20:45.585472 24, 0x0, End_B0=24 End_B1=24
8721 12:20:45.585553 25, 0x0, End_B0=25 End_B1=25
8722 12:20:45.589218 26, 0x0, End_B0=26 End_B1=26
8723 12:20:45.592049 27, 0x0, End_B0=27 End_B1=27
8724 12:20:45.595466 28, 0x0, End_B0=28 End_B1=28
8725 12:20:45.595547 29, 0x0, End_B0=29 End_B1=29
8726 12:20:45.599413 30, 0x0, End_B0=30 End_B1=30
8727 12:20:45.602167 31, 0x4141, End_B0=30 End_B1=30
8728 12:20:45.605751 Byte0 end_step=30 best_step=27
8729 12:20:45.609025 Byte1 end_step=30 best_step=27
8730 12:20:45.612154 Byte0 TX OE(2T, 0.5T) = (3, 3)
8731 12:20:45.612240 Byte1 TX OE(2T, 0.5T) = (3, 3)
8732 12:20:45.615713
8733 12:20:45.615841
8734 12:20:45.622080 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8735 12:20:45.625526 CH1 RK0: MR19=303, MR18=1725
8736 12:20:45.632567 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8737 12:20:45.632692
8738 12:20:45.635335 ----->DramcWriteLeveling(PI) begin...
8739 12:20:45.635483 ==
8740 12:20:45.639282 Dram Type= 6, Freq= 0, CH_1, rank 1
8741 12:20:45.642413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8742 12:20:45.642610 ==
8743 12:20:45.645291 Write leveling (Byte 0): 26 => 26
8744 12:20:45.648967 Write leveling (Byte 1): 29 => 29
8745 12:20:45.652098 DramcWriteLeveling(PI) end<-----
8746 12:20:45.652367
8747 12:20:45.652544 ==
8748 12:20:45.655580 Dram Type= 6, Freq= 0, CH_1, rank 1
8749 12:20:45.658839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8750 12:20:45.659149 ==
8751 12:20:45.661952 [Gating] SW mode calibration
8752 12:20:45.669140 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8753 12:20:45.675462 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8754 12:20:45.679274 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 12:20:45.682021 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 12:20:45.688996 1 4 8 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
8757 12:20:45.692337 1 4 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 1)
8758 12:20:45.695455 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 12:20:45.702008 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 12:20:45.704989 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 12:20:45.708320 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 12:20:45.715540 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 12:20:45.718654 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8764 12:20:45.721729 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
8765 12:20:45.728185 1 5 12 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
8766 12:20:45.731490 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 12:20:45.734877 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 12:20:45.742156 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 12:20:45.745486 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 12:20:45.748770 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 12:20:45.754821 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 12:20:45.758131 1 6 8 | B1->B0 | 3e3e 2525 | 0 0 | (0 0) (0 0)
8773 12:20:45.761983 1 6 12 | B1->B0 | 4646 3e3e | 0 1 | (0 0) (0 0)
8774 12:20:45.768151 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 12:20:45.772296 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 12:20:45.775757 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 12:20:45.781844 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 12:20:45.785790 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 12:20:45.788854 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8780 12:20:45.792003 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8781 12:20:45.798543 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8782 12:20:45.801834 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8783 12:20:45.805205 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 12:20:45.812256 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 12:20:45.815383 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 12:20:45.818304 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 12:20:45.825357 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 12:20:45.828666 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 12:20:45.832082 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 12:20:45.838611 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 12:20:45.841507 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 12:20:45.845202 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 12:20:45.851988 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 12:20:45.854815 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 12:20:45.858492 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8796 12:20:45.865318 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8797 12:20:45.868444 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8798 12:20:45.871137 Total UI for P1: 0, mck2ui 16
8799 12:20:45.875008 best dqsien dly found for B1: ( 1, 9, 6)
8800 12:20:45.878640 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8801 12:20:45.885026 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 12:20:45.885326 Total UI for P1: 0, mck2ui 16
8803 12:20:45.891284 best dqsien dly found for B0: ( 1, 9, 14)
8804 12:20:45.894684 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8805 12:20:45.897827 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8806 12:20:45.898096
8807 12:20:45.901310 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8808 12:20:45.904722 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8809 12:20:45.907803 [Gating] SW calibration Done
8810 12:20:45.908155 ==
8811 12:20:45.911415 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 12:20:45.914538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 12:20:45.914920 ==
8814 12:20:45.917972 RX Vref Scan: 0
8815 12:20:45.918333
8816 12:20:45.918624 RX Vref 0 -> 0, step: 1
8817 12:20:45.918971
8818 12:20:45.921498 RX Delay 0 -> 252, step: 8
8819 12:20:45.924705 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8820 12:20:45.931248 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8821 12:20:45.934422 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8822 12:20:45.937636 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8823 12:20:45.940929 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8824 12:20:45.944561 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8825 12:20:45.950968 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8826 12:20:45.954985 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8827 12:20:45.957683 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8828 12:20:45.961176 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8829 12:20:45.964524 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8830 12:20:45.970758 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8831 12:20:45.974517 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8832 12:20:45.977349 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8833 12:20:45.980832 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8834 12:20:45.983957 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8835 12:20:45.987480 ==
8836 12:20:45.987711 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 12:20:45.994130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 12:20:45.994323 ==
8839 12:20:45.994548 DQS Delay:
8840 12:20:45.997638 DQS0 = 0, DQS1 = 0
8841 12:20:45.997807 DQM Delay:
8842 12:20:46.000920 DQM0 = 136, DQM1 = 133
8843 12:20:46.001090 DQ Delay:
8844 12:20:46.004063 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8845 12:20:46.007456 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8846 12:20:46.010566 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8847 12:20:46.014282 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8848 12:20:46.014460
8849 12:20:46.014592
8850 12:20:46.014716 ==
8851 12:20:46.017347 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 12:20:46.024341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 12:20:46.024514 ==
8854 12:20:46.024651
8855 12:20:46.024776
8856 12:20:46.024897 TX Vref Scan disable
8857 12:20:46.027479 == TX Byte 0 ==
8858 12:20:46.030685 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8859 12:20:46.037680 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8860 12:20:46.037851 == TX Byte 1 ==
8861 12:20:46.040978 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8862 12:20:46.044138 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8863 12:20:46.047320 ==
8864 12:20:46.051021 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 12:20:46.054196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 12:20:46.054366 ==
8867 12:20:46.067372
8868 12:20:46.071226 TX Vref early break, caculate TX vref
8869 12:20:46.073914 TX Vref=16, minBit 0, minWin=23, winSum=380
8870 12:20:46.077742 TX Vref=18, minBit 0, minWin=23, winSum=393
8871 12:20:46.080499 TX Vref=20, minBit 0, minWin=24, winSum=400
8872 12:20:46.084228 TX Vref=22, minBit 0, minWin=24, winSum=409
8873 12:20:46.087174 TX Vref=24, minBit 1, minWin=25, winSum=419
8874 12:20:46.094139 TX Vref=26, minBit 0, minWin=25, winSum=422
8875 12:20:46.097563 TX Vref=28, minBit 0, minWin=26, winSum=427
8876 12:20:46.101090 TX Vref=30, minBit 1, minWin=25, winSum=420
8877 12:20:46.104463 TX Vref=32, minBit 0, minWin=24, winSum=409
8878 12:20:46.107626 TX Vref=34, minBit 0, minWin=24, winSum=405
8879 12:20:46.110713 TX Vref=36, minBit 0, minWin=23, winSum=399
8880 12:20:46.117285 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8881 12:20:46.117520
8882 12:20:46.120657 Final TX Range 0 Vref 28
8883 12:20:46.120892
8884 12:20:46.121093 ==
8885 12:20:46.123651 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 12:20:46.127411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 12:20:46.127584 ==
8888 12:20:46.127720
8889 12:20:46.127845
8890 12:20:46.130679 TX Vref Scan disable
8891 12:20:46.137073 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8892 12:20:46.137265 == TX Byte 0 ==
8893 12:20:46.140505 u2DelayCellOfst[0]=20 cells (6 PI)
8894 12:20:46.144131 u2DelayCellOfst[1]=10 cells (3 PI)
8895 12:20:46.147358 u2DelayCellOfst[2]=0 cells (0 PI)
8896 12:20:46.150699 u2DelayCellOfst[3]=6 cells (2 PI)
8897 12:20:46.153536 u2DelayCellOfst[4]=10 cells (3 PI)
8898 12:20:46.157001 u2DelayCellOfst[5]=16 cells (5 PI)
8899 12:20:46.161287 u2DelayCellOfst[6]=16 cells (5 PI)
8900 12:20:46.163942 u2DelayCellOfst[7]=6 cells (2 PI)
8901 12:20:46.167660 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8902 12:20:46.170740 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8903 12:20:46.174515 == TX Byte 1 ==
8904 12:20:46.177653 u2DelayCellOfst[8]=0 cells (0 PI)
8905 12:20:46.178179 u2DelayCellOfst[9]=3 cells (1 PI)
8906 12:20:46.181378 u2DelayCellOfst[10]=10 cells (3 PI)
8907 12:20:46.183789 u2DelayCellOfst[11]=3 cells (1 PI)
8908 12:20:46.187578 u2DelayCellOfst[12]=13 cells (4 PI)
8909 12:20:46.190867 u2DelayCellOfst[13]=16 cells (5 PI)
8910 12:20:46.193837 u2DelayCellOfst[14]=16 cells (5 PI)
8911 12:20:46.197420 u2DelayCellOfst[15]=16 cells (5 PI)
8912 12:20:46.200712 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8913 12:20:46.207115 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8914 12:20:46.207525 DramC Write-DBI on
8915 12:20:46.207847 ==
8916 12:20:46.210955 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 12:20:46.217463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 12:20:46.217880 ==
8919 12:20:46.218208
8920 12:20:46.218508
8921 12:20:46.218796 TX Vref Scan disable
8922 12:20:46.220714 == TX Byte 0 ==
8923 12:20:46.224598 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8924 12:20:46.227519 == TX Byte 1 ==
8925 12:20:46.231062 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8926 12:20:46.234338 DramC Write-DBI off
8927 12:20:46.234754
8928 12:20:46.235082 [DATLAT]
8929 12:20:46.235389 Freq=1600, CH1 RK1
8930 12:20:46.235689
8931 12:20:46.237547 DATLAT Default: 0xf
8932 12:20:46.238216 0, 0xFFFF, sum = 0
8933 12:20:46.240548 1, 0xFFFF, sum = 0
8934 12:20:46.243881 2, 0xFFFF, sum = 0
8935 12:20:46.244337 3, 0xFFFF, sum = 0
8936 12:20:46.247411 4, 0xFFFF, sum = 0
8937 12:20:46.247837 5, 0xFFFF, sum = 0
8938 12:20:46.250973 6, 0xFFFF, sum = 0
8939 12:20:46.251396 7, 0xFFFF, sum = 0
8940 12:20:46.254119 8, 0xFFFF, sum = 0
8941 12:20:46.254542 9, 0xFFFF, sum = 0
8942 12:20:46.257374 10, 0xFFFF, sum = 0
8943 12:20:46.257862 11, 0xFFFF, sum = 0
8944 12:20:46.260348 12, 0xFFFF, sum = 0
8945 12:20:46.260898 13, 0xFFFF, sum = 0
8946 12:20:46.264446 14, 0x0, sum = 1
8947 12:20:46.264874 15, 0x0, sum = 2
8948 12:20:46.267472 16, 0x0, sum = 3
8949 12:20:46.267895 17, 0x0, sum = 4
8950 12:20:46.270608 best_step = 15
8951 12:20:46.271026
8952 12:20:46.271353 ==
8953 12:20:46.274011 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 12:20:46.277503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 12:20:46.278043 ==
8956 12:20:46.278570 RX Vref Scan: 0
8957 12:20:46.281219
8958 12:20:46.281878 RX Vref 0 -> 0, step: 1
8959 12:20:46.282230
8960 12:20:46.284142 RX Delay 19 -> 252, step: 4
8961 12:20:46.287493 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8962 12:20:46.294003 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8963 12:20:46.297201 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8964 12:20:46.300959 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8965 12:20:46.303936 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8966 12:20:46.308027 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8967 12:20:46.310833 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8968 12:20:46.317349 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8969 12:20:46.320543 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8970 12:20:46.323909 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8971 12:20:46.327255 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8972 12:20:46.330421 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8973 12:20:46.336733 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8974 12:20:46.340527 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8975 12:20:46.343748 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8976 12:20:46.347068 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8977 12:20:46.347248 ==
8978 12:20:46.350380 Dram Type= 6, Freq= 0, CH_1, rank 1
8979 12:20:46.356985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8980 12:20:46.357400 ==
8981 12:20:46.357731 DQS Delay:
8982 12:20:46.360368 DQS0 = 0, DQS1 = 0
8983 12:20:46.360939 DQM Delay:
8984 12:20:46.363783 DQM0 = 134, DQM1 = 130
8985 12:20:46.364378 DQ Delay:
8986 12:20:46.366733 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8987 12:20:46.370165 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8988 12:20:46.373739 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8989 12:20:46.377151 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8990 12:20:46.377714
8991 12:20:46.378251
8992 12:20:46.378726
8993 12:20:46.380564 [DramC_TX_OE_Calibration] TA2
8994 12:20:46.383499 Original DQ_B0 (3 6) =30, OEN = 27
8995 12:20:46.386761 Original DQ_B1 (3 6) =30, OEN = 27
8996 12:20:46.390507 24, 0x0, End_B0=24 End_B1=24
8997 12:20:46.393759 25, 0x0, End_B0=25 End_B1=25
8998 12:20:46.394360 26, 0x0, End_B0=26 End_B1=26
8999 12:20:46.396885 27, 0x0, End_B0=27 End_B1=27
9000 12:20:46.399928 28, 0x0, End_B0=28 End_B1=28
9001 12:20:46.403611 29, 0x0, End_B0=29 End_B1=29
9002 12:20:46.404033 30, 0x0, End_B0=30 End_B1=30
9003 12:20:46.406664 31, 0x4545, End_B0=30 End_B1=30
9004 12:20:46.410327 Byte0 end_step=30 best_step=27
9005 12:20:46.413567 Byte1 end_step=30 best_step=27
9006 12:20:46.416718 Byte0 TX OE(2T, 0.5T) = (3, 3)
9007 12:20:46.420175 Byte1 TX OE(2T, 0.5T) = (3, 3)
9008 12:20:46.420429
9009 12:20:46.420668
9010 12:20:46.427162 [DQSOSCAuto] RK1, (LSB)MR18= 0x2107, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
9011 12:20:46.430459 CH1 RK1: MR19=303, MR18=2107
9012 12:20:46.437070 CH1_RK1: MR19=0x303, MR18=0x2107, DQSOSC=393, MR23=63, INC=23, DEC=15
9013 12:20:46.440083 [RxdqsGatingPostProcess] freq 1600
9014 12:20:46.443648 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9015 12:20:46.447035 best DQS0 dly(2T, 0.5T) = (1, 1)
9016 12:20:46.450382 best DQS1 dly(2T, 0.5T) = (1, 1)
9017 12:20:46.453204 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9018 12:20:46.456660 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9019 12:20:46.460060 best DQS0 dly(2T, 0.5T) = (1, 1)
9020 12:20:46.464057 best DQS1 dly(2T, 0.5T) = (1, 1)
9021 12:20:46.467115 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9022 12:20:46.470410 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9023 12:20:46.473838 Pre-setting of DQS Precalculation
9024 12:20:46.476890 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9025 12:20:46.483521 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9026 12:20:46.493696 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9027 12:20:46.494262
9028 12:20:46.494751
9029 12:20:46.495226 [Calibration Summary] 3200 Mbps
9030 12:20:46.496875 CH 0, Rank 0
9031 12:20:46.497355 SW Impedance : PASS
9032 12:20:46.500265 DUTY Scan : NO K
9033 12:20:46.503395 ZQ Calibration : PASS
9034 12:20:46.503993 Jitter Meter : NO K
9035 12:20:46.506805 CBT Training : PASS
9036 12:20:46.510445 Write leveling : PASS
9037 12:20:46.511028 RX DQS gating : PASS
9038 12:20:46.513873 RX DQ/DQS(RDDQC) : PASS
9039 12:20:46.516762 TX DQ/DQS : PASS
9040 12:20:46.517275 RX DATLAT : PASS
9041 12:20:46.520539 RX DQ/DQS(Engine): PASS
9042 12:20:46.523551 TX OE : PASS
9043 12:20:46.524311 All Pass.
9044 12:20:46.524836
9045 12:20:46.525301 CH 0, Rank 1
9046 12:20:46.526888 SW Impedance : PASS
9047 12:20:46.530102 DUTY Scan : NO K
9048 12:20:46.530582 ZQ Calibration : PASS
9049 12:20:46.533607 Jitter Meter : NO K
9050 12:20:46.534189 CBT Training : PASS
9051 12:20:46.537233 Write leveling : PASS
9052 12:20:46.539988 RX DQS gating : PASS
9053 12:20:46.540497 RX DQ/DQS(RDDQC) : PASS
9054 12:20:46.543514 TX DQ/DQS : PASS
9055 12:20:46.547212 RX DATLAT : PASS
9056 12:20:46.547766 RX DQ/DQS(Engine): PASS
9057 12:20:46.550462 TX OE : PASS
9058 12:20:46.551024 All Pass.
9059 12:20:46.551384
9060 12:20:46.553809 CH 1, Rank 0
9061 12:20:46.554262 SW Impedance : PASS
9062 12:20:46.556861 DUTY Scan : NO K
9063 12:20:46.560422 ZQ Calibration : PASS
9064 12:20:46.560984 Jitter Meter : NO K
9065 12:20:46.563768 CBT Training : PASS
9066 12:20:46.566784 Write leveling : PASS
9067 12:20:46.567239 RX DQS gating : PASS
9068 12:20:46.570042 RX DQ/DQS(RDDQC) : PASS
9069 12:20:46.574064 TX DQ/DQS : PASS
9070 12:20:46.574638 RX DATLAT : PASS
9071 12:20:46.577095 RX DQ/DQS(Engine): PASS
9072 12:20:46.577547 TX OE : PASS
9073 12:20:46.580661 All Pass.
9074 12:20:46.581211
9075 12:20:46.581568 CH 1, Rank 1
9076 12:20:46.583949 SW Impedance : PASS
9077 12:20:46.584568 DUTY Scan : NO K
9078 12:20:46.586790 ZQ Calibration : PASS
9079 12:20:46.590101 Jitter Meter : NO K
9080 12:20:46.590554 CBT Training : PASS
9081 12:20:46.593154 Write leveling : PASS
9082 12:20:46.597022 RX DQS gating : PASS
9083 12:20:46.597588 RX DQ/DQS(RDDQC) : PASS
9084 12:20:46.600059 TX DQ/DQS : PASS
9085 12:20:46.603895 RX DATLAT : PASS
9086 12:20:46.604525 RX DQ/DQS(Engine): PASS
9087 12:20:46.607270 TX OE : PASS
9088 12:20:46.607826 All Pass.
9089 12:20:46.608185
9090 12:20:46.610331 DramC Write-DBI on
9091 12:20:46.613326 PER_BANK_REFRESH: Hybrid Mode
9092 12:20:46.613782 TX_TRACKING: ON
9093 12:20:46.623764 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9094 12:20:46.630101 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9095 12:20:46.637013 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9096 12:20:46.640075 [FAST_K] Save calibration result to emmc
9097 12:20:46.643698 sync common calibartion params.
9098 12:20:46.646896 sync cbt_mode0:1, 1:1
9099 12:20:46.650148 dram_init: ddr_geometry: 2
9100 12:20:46.650626 dram_init: ddr_geometry: 2
9101 12:20:46.653101 dram_init: ddr_geometry: 2
9102 12:20:46.656576 0:dram_rank_size:100000000
9103 12:20:46.657065 1:dram_rank_size:100000000
9104 12:20:46.663266 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9105 12:20:46.666530 DFS_SHUFFLE_HW_MODE: ON
9106 12:20:46.670032 dramc_set_vcore_voltage set vcore to 725000
9107 12:20:46.673200 Read voltage for 1600, 0
9108 12:20:46.673636 Vio18 = 0
9109 12:20:46.674074 Vcore = 725000
9110 12:20:46.676456 Vdram = 0
9111 12:20:46.676941 Vddq = 0
9112 12:20:46.677381 Vmddr = 0
9113 12:20:46.679350 switch to 3200 Mbps bootup
9114 12:20:46.679784 [DramcRunTimeConfig]
9115 12:20:46.683233 PHYPLL
9116 12:20:46.683686 DPM_CONTROL_AFTERK: ON
9117 12:20:46.686665 PER_BANK_REFRESH: ON
9118 12:20:46.690047 REFRESH_OVERHEAD_REDUCTION: ON
9119 12:20:46.690558 CMD_PICG_NEW_MODE: OFF
9120 12:20:46.693181 XRTWTW_NEW_MODE: ON
9121 12:20:46.693597 XRTRTR_NEW_MODE: ON
9122 12:20:46.696568 TX_TRACKING: ON
9123 12:20:46.696984 RDSEL_TRACKING: OFF
9124 12:20:46.700455 DQS Precalculation for DVFS: ON
9125 12:20:46.702902 RX_TRACKING: OFF
9126 12:20:46.703194 HW_GATING DBG: ON
9127 12:20:46.706827 ZQCS_ENABLE_LP4: ON
9128 12:20:46.707205 RX_PICG_NEW_MODE: ON
9129 12:20:46.710145 TX_PICG_NEW_MODE: ON
9130 12:20:46.710489 ENABLE_RX_DCM_DPHY: ON
9131 12:20:46.713319 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9132 12:20:46.716205 DUMMY_READ_FOR_TRACKING: OFF
9133 12:20:46.719683 !!! SPM_CONTROL_AFTERK: OFF
9134 12:20:46.723087 !!! SPM could not control APHY
9135 12:20:46.723492 IMPEDANCE_TRACKING: ON
9136 12:20:46.726220 TEMP_SENSOR: ON
9137 12:20:46.726670 HW_SAVE_FOR_SR: OFF
9138 12:20:46.729801 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9139 12:20:46.733016 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9140 12:20:46.736820 Read ODT Tracking: ON
9141 12:20:46.739808 Refresh Rate DeBounce: ON
9142 12:20:46.740107 DFS_NO_QUEUE_FLUSH: ON
9143 12:20:46.742629 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9144 12:20:46.745837 ENABLE_DFS_RUNTIME_MRW: OFF
9145 12:20:46.749886 DDR_RESERVE_NEW_MODE: ON
9146 12:20:46.750193 MR_CBT_SWITCH_FREQ: ON
9147 12:20:46.752824 =========================
9148 12:20:46.771925 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9149 12:20:46.775219 dram_init: ddr_geometry: 2
9150 12:20:46.793070 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9151 12:20:46.796396 dram_init: dram init end (result: 0)
9152 12:20:46.803802 DRAM-K: Full calibration passed in 24491 msecs
9153 12:20:46.807051 MRC: failed to locate region type 0.
9154 12:20:46.807474 DRAM rank0 size:0x100000000,
9155 12:20:46.810212 DRAM rank1 size=0x100000000
9156 12:20:46.820226 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9157 12:20:46.827151 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9158 12:20:46.833825 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9159 12:20:46.840494 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9160 12:20:46.843724 DRAM rank0 size:0x100000000,
9161 12:20:46.846653 DRAM rank1 size=0x100000000
9162 12:20:46.847069 CBMEM:
9163 12:20:46.849912 IMD: root @ 0xfffff000 254 entries.
9164 12:20:46.853723 IMD: root @ 0xffffec00 62 entries.
9165 12:20:46.856775 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9166 12:20:46.859988 WARNING: RO_VPD is uninitialized or empty.
9167 12:20:46.867159 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9168 12:20:46.873912 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9169 12:20:46.886683 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9170 12:20:46.897897 BS: romstage times (exec / console): total (unknown) / 24019 ms
9171 12:20:46.898456
9172 12:20:46.898935
9173 12:20:46.908004 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9174 12:20:46.911786 ARM64: Exception handlers installed.
9175 12:20:46.914479 ARM64: Testing exception
9176 12:20:46.917683 ARM64: Done test exception
9177 12:20:46.918181 Enumerating buses...
9178 12:20:46.921263 Show all devs... Before device enumeration.
9179 12:20:46.924724 Root Device: enabled 1
9180 12:20:46.928032 CPU_CLUSTER: 0: enabled 1
9181 12:20:46.928502 CPU: 00: enabled 1
9182 12:20:46.931282 Compare with tree...
9183 12:20:46.931711 Root Device: enabled 1
9184 12:20:46.934600 CPU_CLUSTER: 0: enabled 1
9185 12:20:46.937846 CPU: 00: enabled 1
9186 12:20:46.938274 Root Device scanning...
9187 12:20:46.940895 scan_static_bus for Root Device
9188 12:20:46.944114 CPU_CLUSTER: 0 enabled
9189 12:20:46.947828 scan_static_bus for Root Device done
9190 12:20:46.950853 scan_bus: bus Root Device finished in 8 msecs
9191 12:20:46.951284 done
9192 12:20:46.957433 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9193 12:20:46.960743 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9194 12:20:46.967393 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9195 12:20:46.970900 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9196 12:20:46.973962 Allocating resources...
9197 12:20:46.977128 Reading resources...
9198 12:20:46.980346 Root Device read_resources bus 0 link: 0
9199 12:20:46.980681 DRAM rank0 size:0x100000000,
9200 12:20:46.983646 DRAM rank1 size=0x100000000
9201 12:20:46.987116 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9202 12:20:46.990383 CPU: 00 missing read_resources
9203 12:20:46.993753 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9204 12:20:47.000170 Root Device read_resources bus 0 link: 0 done
9205 12:20:47.000516 Done reading resources.
9206 12:20:47.007422 Show resources in subtree (Root Device)...After reading.
9207 12:20:47.010499 Root Device child on link 0 CPU_CLUSTER: 0
9208 12:20:47.014072 CPU_CLUSTER: 0 child on link 0 CPU: 00
9209 12:20:47.023961 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9210 12:20:47.024189 CPU: 00
9211 12:20:47.027204 Root Device assign_resources, bus 0 link: 0
9212 12:20:47.030240 CPU_CLUSTER: 0 missing set_resources
9213 12:20:47.033554 Root Device assign_resources, bus 0 link: 0 done
9214 12:20:47.036760 Done setting resources.
9215 12:20:47.043411 Show resources in subtree (Root Device)...After assigning values.
9216 12:20:47.046661 Root Device child on link 0 CPU_CLUSTER: 0
9217 12:20:47.050016 CPU_CLUSTER: 0 child on link 0 CPU: 00
9218 12:20:47.059809 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9219 12:20:47.059911 CPU: 00
9220 12:20:47.063450 Done allocating resources.
9221 12:20:47.066855 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9222 12:20:47.070034 Enabling resources...
9223 12:20:47.070106 done.
9224 12:20:47.076394 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9225 12:20:47.076475 Initializing devices...
9226 12:20:47.080050 Root Device init
9227 12:20:47.080157 init hardware done!
9228 12:20:47.083263 0x00000018: ctrlr->caps
9229 12:20:47.086492 52.000 MHz: ctrlr->f_max
9230 12:20:47.086580 0.400 MHz: ctrlr->f_min
9231 12:20:47.089706 0x40ff8080: ctrlr->voltages
9232 12:20:47.089833 sclk: 390625
9233 12:20:47.093778 Bus Width = 1
9234 12:20:47.093873 sclk: 390625
9235 12:20:47.097290 Bus Width = 1
9236 12:20:47.097719 Early init status = 3
9237 12:20:47.103845 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9238 12:20:47.107184 in-header: 03 fc 00 00 01 00 00 00
9239 12:20:47.107619 in-data: 00
9240 12:20:47.113575 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9241 12:20:47.116577 in-header: 03 fd 00 00 00 00 00 00
9242 12:20:47.119702 in-data:
9243 12:20:47.123768 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9244 12:20:47.126473 in-header: 03 fc 00 00 01 00 00 00
9245 12:20:47.130345 in-data: 00
9246 12:20:47.133143 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9247 12:20:47.137820 in-header: 03 fd 00 00 00 00 00 00
9248 12:20:47.140996 in-data:
9249 12:20:47.144217 [SSUSB] Setting up USB HOST controller...
9250 12:20:47.147949 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9251 12:20:47.150872 [SSUSB] phy power-on done.
9252 12:20:47.154141 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9253 12:20:47.161262 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9254 12:20:47.164716 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9255 12:20:47.171076 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9256 12:20:47.177636 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9257 12:20:47.184422 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9258 12:20:47.190928 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9259 12:20:47.197289 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9260 12:20:47.200346 SPM: binary array size = 0x9dc
9261 12:20:47.203561 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9262 12:20:47.210809 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9263 12:20:47.217182 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9264 12:20:47.223823 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9265 12:20:47.226802 configure_display: Starting display init
9266 12:20:47.261060 anx7625_power_on_init: Init interface.
9267 12:20:47.264343 anx7625_disable_pd_protocol: Disabled PD feature.
9268 12:20:47.267807 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9269 12:20:47.295120 anx7625_start_dp_work: Secure OCM version=00
9270 12:20:47.298771 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9271 12:20:47.313590 sp_tx_get_edid_block: EDID Block = 1
9272 12:20:47.416216 Extracted contents:
9273 12:20:47.419241 header: 00 ff ff ff ff ff ff 00
9274 12:20:47.422660 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9275 12:20:47.425691 version: 01 04
9276 12:20:47.429259 basic params: 95 1f 11 78 0a
9277 12:20:47.432272 chroma info: 76 90 94 55 54 90 27 21 50 54
9278 12:20:47.436110 established: 00 00 00
9279 12:20:47.442245 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9280 12:20:47.446282 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9281 12:20:47.452402 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9282 12:20:47.459905 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9283 12:20:47.466558 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9284 12:20:47.469797 extensions: 00
9285 12:20:47.470344 checksum: fb
9286 12:20:47.470675
9287 12:20:47.472594 Manufacturer: IVO Model 57d Serial Number 0
9288 12:20:47.476380 Made week 0 of 2020
9289 12:20:47.476818 EDID version: 1.4
9290 12:20:47.479656 Digital display
9291 12:20:47.482827 6 bits per primary color channel
9292 12:20:47.483353 DisplayPort interface
9293 12:20:47.485606 Maximum image size: 31 cm x 17 cm
9294 12:20:47.489530 Gamma: 220%
9295 12:20:47.489944 Check DPMS levels
9296 12:20:47.492764 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9297 12:20:47.495889 First detailed timing is preferred timing
9298 12:20:47.499353 Established timings supported:
9299 12:20:47.502455 Standard timings supported:
9300 12:20:47.502871 Detailed timings
9301 12:20:47.509037 Hex of detail: 383680a07038204018303c0035ae10000019
9302 12:20:47.512191 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9303 12:20:47.518967 0780 0798 07c8 0820 hborder 0
9304 12:20:47.522346 0438 043b 0447 0458 vborder 0
9305 12:20:47.525531 -hsync -vsync
9306 12:20:47.525947 Did detailed timing
9307 12:20:47.528724 Hex of detail: 000000000000000000000000000000000000
9308 12:20:47.532721 Manufacturer-specified data, tag 0
9309 12:20:47.539129 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9310 12:20:47.539649 ASCII string: InfoVision
9311 12:20:47.545599 Hex of detail: 000000fe00523134304e574635205248200a
9312 12:20:47.549066 ASCII string: R140NWF5 RH
9313 12:20:47.549584 Checksum
9314 12:20:47.549911 Checksum: 0xfb (valid)
9315 12:20:47.555586 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9316 12:20:47.558360 DSI data_rate: 832800000 bps
9317 12:20:47.562361 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9318 12:20:47.568768 anx7625_parse_edid: pixelclock(138800).
9319 12:20:47.571965 hactive(1920), hsync(48), hfp(24), hbp(88)
9320 12:20:47.575459 vactive(1080), vsync(12), vfp(3), vbp(17)
9321 12:20:47.578314 anx7625_dsi_config: config dsi.
9322 12:20:47.584920 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9323 12:20:47.598331 anx7625_dsi_config: success to config DSI
9324 12:20:47.601251 anx7625_dp_start: MIPI phy setup OK.
9325 12:20:47.605072 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9326 12:20:47.608586 mtk_ddp_mode_set invalid vrefresh 60
9327 12:20:47.611558 main_disp_path_setup
9328 12:20:47.612075 ovl_layer_smi_id_en
9329 12:20:47.614523 ovl_layer_smi_id_en
9330 12:20:47.614936 ccorr_config
9331 12:20:47.615269 aal_config
9332 12:20:47.618000 gamma_config
9333 12:20:47.618413 postmask_config
9334 12:20:47.621218 dither_config
9335 12:20:47.624891 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9336 12:20:47.631071 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9337 12:20:47.634527 Root Device init finished in 551 msecs
9338 12:20:47.637881 CPU_CLUSTER: 0 init
9339 12:20:47.644165 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9340 12:20:47.647638 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9341 12:20:47.651065 APU_MBOX 0x190000b0 = 0x10001
9342 12:20:47.654330 APU_MBOX 0x190001b0 = 0x10001
9343 12:20:47.657939 APU_MBOX 0x190005b0 = 0x10001
9344 12:20:47.661258 APU_MBOX 0x190006b0 = 0x10001
9345 12:20:47.664234 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9346 12:20:47.677174 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9347 12:20:47.689295 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9348 12:20:47.696115 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9349 12:20:47.707161 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9350 12:20:47.716305 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9351 12:20:47.719723 CPU_CLUSTER: 0 init finished in 81 msecs
9352 12:20:47.723424 Devices initialized
9353 12:20:47.726846 Show all devs... After init.
9354 12:20:47.726955 Root Device: enabled 1
9355 12:20:47.730113 CPU_CLUSTER: 0: enabled 1
9356 12:20:47.733732 CPU: 00: enabled 1
9357 12:20:47.737103 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9358 12:20:47.739869 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9359 12:20:47.743149 ELOG: NV offset 0x57f000 size 0x1000
9360 12:20:47.750116 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9361 12:20:47.756338 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9362 12:20:47.760020 ELOG: Event(17) added with size 13 at 2024-01-31 12:18:05 UTC
9363 12:20:47.762894 out: cmd=0x121: 03 db 21 01 00 00 00 00
9364 12:20:47.766687 in-header: 03 bc 00 00 2c 00 00 00
9365 12:20:47.779733 in-data: a3 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9366 12:20:47.786630 ELOG: Event(A1) added with size 10 at 2024-01-31 12:18:05 UTC
9367 12:20:47.793208 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9368 12:20:47.799716 ELOG: Event(A0) added with size 9 at 2024-01-31 12:18:05 UTC
9369 12:20:47.803062 elog_add_boot_reason: Logged dev mode boot
9370 12:20:47.806637 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9371 12:20:47.810139 Finalize devices...
9372 12:20:47.810262 Devices finalized
9373 12:20:47.816567 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9374 12:20:47.819921 Writing coreboot table at 0xffe64000
9375 12:20:47.823662 0. 000000000010a000-0000000000113fff: RAMSTAGE
9376 12:20:47.826417 1. 0000000040000000-00000000400fffff: RAM
9377 12:20:47.830287 2. 0000000040100000-000000004032afff: RAMSTAGE
9378 12:20:47.836875 3. 000000004032b000-00000000545fffff: RAM
9379 12:20:47.839771 4. 0000000054600000-000000005465ffff: BL31
9380 12:20:47.843474 5. 0000000054660000-00000000ffe63fff: RAM
9381 12:20:47.846675 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9382 12:20:47.853518 7. 0000000100000000-000000023fffffff: RAM
9383 12:20:47.853698 Passing 5 GPIOs to payload:
9384 12:20:47.860049 NAME | PORT | POLARITY | VALUE
9385 12:20:47.862987 EC in RW | 0x000000aa | low | undefined
9386 12:20:47.869703 EC interrupt | 0x00000005 | low | undefined
9387 12:20:47.873678 TPM interrupt | 0x000000ab | high | undefined
9388 12:20:47.876425 SD card detect | 0x00000011 | high | undefined
9389 12:20:47.882906 speaker enable | 0x00000093 | high | undefined
9390 12:20:47.886532 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9391 12:20:47.889778 in-header: 03 f9 00 00 02 00 00 00
9392 12:20:47.889976 in-data: 02 00
9393 12:20:47.892892 ADC[4]: Raw value=904357 ID=7
9394 12:20:47.896526 ADC[3]: Raw value=213441 ID=1
9395 12:20:47.896764 RAM Code: 0x71
9396 12:20:47.899792 ADC[6]: Raw value=75701 ID=0
9397 12:20:47.903574 ADC[5]: Raw value=213072 ID=1
9398 12:20:47.903996 SKU Code: 0x1
9399 12:20:47.910024 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3c49
9400 12:20:47.913941 coreboot table: 964 bytes.
9401 12:20:47.917018 IMD ROOT 0. 0xfffff000 0x00001000
9402 12:20:47.920160 IMD SMALL 1. 0xffffe000 0x00001000
9403 12:20:47.923525 RO MCACHE 2. 0xffffc000 0x00001104
9404 12:20:47.926589 CONSOLE 3. 0xfff7c000 0x00080000
9405 12:20:47.930348 FMAP 4. 0xfff7b000 0x00000452
9406 12:20:47.933104 TIME STAMP 5. 0xfff7a000 0x00000910
9407 12:20:47.937251 VBOOT WORK 6. 0xfff66000 0x00014000
9408 12:20:47.940532 RAMOOPS 7. 0xffe66000 0x00100000
9409 12:20:47.943392 COREBOOT 8. 0xffe64000 0x00002000
9410 12:20:47.943851 IMD small region:
9411 12:20:47.946639 IMD ROOT 0. 0xffffec00 0x00000400
9412 12:20:47.949680 VPD 1. 0xffffeb80 0x0000006c
9413 12:20:47.953363 MMC STATUS 2. 0xffffeb60 0x00000004
9414 12:20:47.959744 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9415 12:20:47.960342 Probing TPM: done!
9416 12:20:47.966490 Connected to device vid:did:rid of 1ae0:0028:00
9417 12:20:47.976648 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9418 12:20:47.980851 Initialized TPM device CR50 revision 0
9419 12:20:47.981428 Checking cr50 for pending updates
9420 12:20:47.986738 Reading cr50 TPM mode
9421 12:20:47.994860 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9422 12:20:48.001399 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9423 12:20:48.041807 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9424 12:20:48.044943 Checking segment from ROM address 0x40100000
9425 12:20:48.048398 Checking segment from ROM address 0x4010001c
9426 12:20:48.055103 Loading segment from ROM address 0x40100000
9427 12:20:48.055234 code (compression=0)
9428 12:20:48.062139 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9429 12:20:48.071928 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9430 12:20:48.072059 it's not compressed!
9431 12:20:48.078273 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9432 12:20:48.081720 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9433 12:20:48.101873 Loading segment from ROM address 0x4010001c
9434 12:20:48.102060 Entry Point 0x80000000
9435 12:20:48.105141 Loaded segments
9436 12:20:48.108969 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9437 12:20:48.115642 Jumping to boot code at 0x80000000(0xffe64000)
9438 12:20:48.121930 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9439 12:20:48.128327 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9440 12:20:48.136397 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9441 12:20:48.139797 Checking segment from ROM address 0x40100000
9442 12:20:48.143517 Checking segment from ROM address 0x4010001c
9443 12:20:48.149697 Loading segment from ROM address 0x40100000
9444 12:20:48.149920 code (compression=1)
9445 12:20:48.156312 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9446 12:20:48.166974 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9447 12:20:48.167289 using LZMA
9448 12:20:48.175584 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9449 12:20:48.181793 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9450 12:20:48.185575 Loading segment from ROM address 0x4010001c
9451 12:20:48.186010 Entry Point 0x54601000
9452 12:20:48.188595 Loaded segments
9453 12:20:48.192435 NOTICE: MT8192 bl31_setup
9454 12:20:48.198718 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9455 12:20:48.201993 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9456 12:20:48.205573 WARNING: region 0:
9457 12:20:48.208959 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 12:20:48.209376 WARNING: region 1:
9459 12:20:48.215463 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9460 12:20:48.218978 WARNING: region 2:
9461 12:20:48.222353 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9462 12:20:48.225165 WARNING: region 3:
9463 12:20:48.228982 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9464 12:20:48.232873 WARNING: region 4:
9465 12:20:48.239484 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9466 12:20:48.240074 WARNING: region 5:
9467 12:20:48.242116 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 12:20:48.245655 WARNING: region 6:
9469 12:20:48.248706 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 12:20:48.251970 WARNING: region 7:
9471 12:20:48.255324 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 12:20:48.262429 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9473 12:20:48.265475 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9474 12:20:48.268891 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9475 12:20:48.275729 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9476 12:20:48.278965 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9477 12:20:48.282012 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9478 12:20:48.289079 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9479 12:20:48.292861 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9480 12:20:48.296132 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9481 12:20:48.302619 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9482 12:20:48.306103 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9483 12:20:48.308945 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9484 12:20:48.315564 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9485 12:20:48.319481 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9486 12:20:48.326117 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9487 12:20:48.329024 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9488 12:20:48.332804 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9489 12:20:48.339270 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9490 12:20:48.342724 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9491 12:20:48.346420 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9492 12:20:48.352550 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9493 12:20:48.356094 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9494 12:20:48.362887 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9495 12:20:48.365867 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9496 12:20:48.369118 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9497 12:20:48.375905 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9498 12:20:48.379451 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9499 12:20:48.385800 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9500 12:20:48.389341 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9501 12:20:48.392843 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9502 12:20:48.399205 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9503 12:20:48.402956 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9504 12:20:48.406043 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9505 12:20:48.412816 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9506 12:20:48.415931 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9507 12:20:48.419313 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9508 12:20:48.422774 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9509 12:20:48.429436 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9510 12:20:48.432545 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9511 12:20:48.436695 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9512 12:20:48.439611 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9513 12:20:48.446868 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9514 12:20:48.449831 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9515 12:20:48.453968 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9516 12:20:48.456531 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9517 12:20:48.463040 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9518 12:20:48.466959 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9519 12:20:48.470058 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9520 12:20:48.476449 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9521 12:20:48.479127 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9522 12:20:48.483140 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9523 12:20:48.489107 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9524 12:20:48.492816 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9525 12:20:48.499817 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9526 12:20:48.502810 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9527 12:20:48.506122 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9528 12:20:48.512920 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9529 12:20:48.516250 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9530 12:20:48.522940 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9531 12:20:48.526483 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9532 12:20:48.533399 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9533 12:20:48.536470 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9534 12:20:48.543112 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9535 12:20:48.546765 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9536 12:20:48.549619 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9537 12:20:48.556979 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9538 12:20:48.559848 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9539 12:20:48.566695 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9540 12:20:48.569521 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9541 12:20:48.573391 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9542 12:20:48.579683 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9543 12:20:48.582957 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9544 12:20:48.590131 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9545 12:20:48.593349 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9546 12:20:48.600114 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9547 12:20:48.603681 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9548 12:20:48.606808 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9549 12:20:48.613744 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9550 12:20:48.616618 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9551 12:20:48.623709 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9552 12:20:48.626680 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9553 12:20:48.633108 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9554 12:20:48.636811 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9555 12:20:48.640697 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9556 12:20:48.646929 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9557 12:20:48.650071 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9558 12:20:48.656821 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9559 12:20:48.660162 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9560 12:20:48.666374 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9561 12:20:48.670604 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9562 12:20:48.673727 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9563 12:20:48.679891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9564 12:20:48.683658 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9565 12:20:48.690586 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9566 12:20:48.693747 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9567 12:20:48.700770 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9568 12:20:48.703811 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9569 12:20:48.707098 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9570 12:20:48.710583 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9571 12:20:48.716729 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9572 12:20:48.720044 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9573 12:20:48.723818 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9574 12:20:48.730105 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9575 12:20:48.733364 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9576 12:20:48.736642 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9577 12:20:48.743173 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9578 12:20:48.747046 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9579 12:20:48.754153 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9580 12:20:48.756638 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9581 12:20:48.760090 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9582 12:20:48.766905 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9583 12:20:48.770139 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9584 12:20:48.776764 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9585 12:20:48.780485 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9586 12:20:48.783378 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9587 12:20:48.790229 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9588 12:20:48.793716 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9589 12:20:48.796633 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9590 12:20:48.803560 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9591 12:20:48.806597 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9592 12:20:48.809917 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9593 12:20:48.813553 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9594 12:20:48.816869 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9595 12:20:48.823087 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9596 12:20:48.826667 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9597 12:20:48.833554 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9598 12:20:48.837161 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9599 12:20:48.840347 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9600 12:20:48.847051 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9601 12:20:48.850085 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9602 12:20:48.853338 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9603 12:20:48.860254 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9604 12:20:48.863589 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9605 12:20:48.870342 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9606 12:20:48.873326 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9607 12:20:48.876963 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9608 12:20:48.883506 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9609 12:20:48.886962 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9610 12:20:48.894011 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9611 12:20:48.897206 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9612 12:20:48.900422 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9613 12:20:48.906930 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9614 12:20:48.910502 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9615 12:20:48.913998 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9616 12:20:48.920102 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9617 12:20:48.923211 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9618 12:20:48.930585 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9619 12:20:48.933964 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9620 12:20:48.936952 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9621 12:20:48.943299 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9622 12:20:48.947249 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9623 12:20:48.950276 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9624 12:20:48.957261 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9625 12:20:48.960324 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9626 12:20:48.966863 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9627 12:20:48.969992 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9628 12:20:48.973824 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9629 12:20:48.980043 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9630 12:20:48.983767 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9631 12:20:48.990101 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9632 12:20:48.993974 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9633 12:20:48.996987 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9634 12:20:49.003691 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9635 12:20:49.007463 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9636 12:20:49.014212 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9637 12:20:49.016999 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9638 12:20:49.020611 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9639 12:20:49.027690 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9640 12:20:49.030240 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9641 12:20:49.033986 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9642 12:20:49.040939 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9643 12:20:49.043851 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9644 12:20:49.050515 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9645 12:20:49.054085 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9646 12:20:49.057104 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9647 12:20:49.063860 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9648 12:20:49.066783 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9649 12:20:49.074318 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9650 12:20:49.077646 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9651 12:20:49.080411 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9652 12:20:49.087178 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9653 12:20:49.090406 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9654 12:20:49.096960 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9655 12:20:49.100327 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9656 12:20:49.103868 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9657 12:20:49.110693 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9658 12:20:49.113644 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9659 12:20:49.116739 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9660 12:20:49.123617 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9661 12:20:49.126960 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9662 12:20:49.133632 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9663 12:20:49.137657 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9664 12:20:49.143633 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9665 12:20:49.146781 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9666 12:20:49.150384 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9667 12:20:49.157100 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9668 12:20:49.160389 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9669 12:20:49.166551 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9670 12:20:49.170619 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9671 12:20:49.173551 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9672 12:20:49.180198 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9673 12:20:49.183611 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9674 12:20:49.189965 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9675 12:20:49.193346 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9676 12:20:49.196944 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9677 12:20:49.203912 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9678 12:20:49.206965 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9679 12:20:49.213480 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9680 12:20:49.216552 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9681 12:20:49.223345 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9682 12:20:49.226486 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9683 12:20:49.229673 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9684 12:20:49.236454 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9685 12:20:49.240081 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9686 12:20:49.246562 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9687 12:20:49.249775 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9688 12:20:49.256447 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9689 12:20:49.259984 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9690 12:20:49.263207 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9691 12:20:49.269716 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9692 12:20:49.273332 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9693 12:20:49.279558 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9694 12:20:49.282644 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9695 12:20:49.286493 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9696 12:20:49.292487 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9697 12:20:49.296360 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9698 12:20:49.302969 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9699 12:20:49.305993 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9700 12:20:49.312624 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9701 12:20:49.315994 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9702 12:20:49.319858 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9703 12:20:49.322854 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9704 12:20:49.326176 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9705 12:20:49.333118 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9706 12:20:49.336501 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9707 12:20:49.339859 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9708 12:20:49.346500 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9709 12:20:49.349786 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9710 12:20:49.353142 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9711 12:20:49.359550 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9712 12:20:49.362674 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9713 12:20:49.369977 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9714 12:20:49.372772 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9715 12:20:49.375970 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9716 12:20:49.382685 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9717 12:20:49.386023 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9718 12:20:49.389224 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9719 12:20:49.395839 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9720 12:20:49.399681 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9721 12:20:49.402833 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9722 12:20:49.409811 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9723 12:20:49.412441 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9724 12:20:49.418911 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9725 12:20:49.422175 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9726 12:20:49.425613 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9727 12:20:49.432738 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9728 12:20:49.435476 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9729 12:20:49.442335 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9730 12:20:49.445307 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9731 12:20:49.448959 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9732 12:20:49.455488 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9733 12:20:49.458545 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9734 12:20:49.461694 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9735 12:20:49.468479 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9736 12:20:49.472492 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9737 12:20:49.475132 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9738 12:20:49.481768 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9739 12:20:49.485474 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9740 12:20:49.488398 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9741 12:20:49.495204 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9742 12:20:49.498209 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9743 12:20:49.502118 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9744 12:20:49.505093 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9745 12:20:49.508360 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9746 12:20:49.515206 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9747 12:20:49.518982 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9748 12:20:49.521855 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9749 12:20:49.528571 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9750 12:20:49.531517 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9751 12:20:49.534928 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9752 12:20:49.538886 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9753 12:20:49.545467 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9754 12:20:49.548868 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9755 12:20:49.555250 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9756 12:20:49.558639 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9757 12:20:49.561471 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9758 12:20:49.568074 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9759 12:20:49.572206 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9760 12:20:49.578466 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9761 12:20:49.581572 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9762 12:20:49.584765 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9763 12:20:49.591479 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9764 12:20:49.594716 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9765 12:20:49.601582 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9766 12:20:49.604600 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9767 12:20:49.608025 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9768 12:20:49.614988 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9769 12:20:49.617933 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9770 12:20:49.624590 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9771 12:20:49.628456 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9772 12:20:49.631581 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9773 12:20:49.637915 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9774 12:20:49.640966 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9775 12:20:49.648368 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9776 12:20:49.651165 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9777 12:20:49.654794 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9778 12:20:49.661251 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9779 12:20:49.664878 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9780 12:20:49.671839 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9781 12:20:49.675086 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9782 12:20:49.681321 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9783 12:20:49.684322 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9784 12:20:49.688036 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9785 12:20:49.694595 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9786 12:20:49.697903 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9787 12:20:49.704750 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9788 12:20:49.708144 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9789 12:20:49.711358 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9790 12:20:49.718162 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9791 12:20:49.720953 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9792 12:20:49.728022 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9793 12:20:49.730988 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9794 12:20:49.734898 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9795 12:20:49.741159 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9796 12:20:49.744382 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9797 12:20:49.750860 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9798 12:20:49.753780 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9799 12:20:49.760574 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9800 12:20:49.763965 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9801 12:20:49.767686 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9802 12:20:49.774477 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9803 12:20:49.777553 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9804 12:20:49.780981 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9805 12:20:49.787511 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9806 12:20:49.791179 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9807 12:20:49.798015 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9808 12:20:49.801042 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9809 12:20:49.804467 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9810 12:20:49.810625 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9811 12:20:49.814738 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9812 12:20:49.820903 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9813 12:20:49.824025 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9814 12:20:49.831009 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9815 12:20:49.834224 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9816 12:20:49.837331 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9817 12:20:49.844192 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9818 12:20:49.847606 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9819 12:20:49.853806 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9820 12:20:49.857588 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9821 12:20:49.860592 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9822 12:20:49.867508 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9823 12:20:49.870872 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9824 12:20:49.877202 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9825 12:20:49.880486 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9826 12:20:49.884118 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9827 12:20:49.890942 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9828 12:20:49.893658 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9829 12:20:49.900801 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9830 12:20:49.904239 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9831 12:20:49.910802 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9832 12:20:49.914330 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9833 12:20:49.916896 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9834 12:20:49.924127 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9835 12:20:49.927108 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9836 12:20:49.933942 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9837 12:20:49.936992 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9838 12:20:49.944626 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9839 12:20:49.947758 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9840 12:20:49.953979 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9841 12:20:49.957117 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9842 12:20:49.960690 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9843 12:20:49.966857 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9844 12:20:49.970388 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9845 12:20:49.976900 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9846 12:20:49.980433 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9847 12:20:49.986855 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9848 12:20:49.989970 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9849 12:20:49.993766 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9850 12:20:50.000622 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9851 12:20:50.003861 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9852 12:20:50.010332 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9853 12:20:50.013922 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9854 12:20:50.020405 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9855 12:20:50.023704 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9856 12:20:50.027030 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9857 12:20:50.033670 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9858 12:20:50.037504 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9859 12:20:50.043863 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9860 12:20:50.046782 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9861 12:20:50.054197 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9862 12:20:50.057022 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9863 12:20:50.060387 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9864 12:20:50.066786 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9865 12:20:50.070521 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9866 12:20:50.076586 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9867 12:20:50.080361 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9868 12:20:50.086996 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9869 12:20:50.090260 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9870 12:20:50.093329 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9871 12:20:50.100048 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9872 12:20:50.103770 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9873 12:20:50.110183 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9874 12:20:50.113161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9875 12:20:50.116645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9876 12:20:50.123372 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9877 12:20:50.126809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9878 12:20:50.133603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9879 12:20:50.136371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9880 12:20:50.143188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9881 12:20:50.146396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9882 12:20:50.153471 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9883 12:20:50.156861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9884 12:20:50.163341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9885 12:20:50.166661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9886 12:20:50.172972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9887 12:20:50.176383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9888 12:20:50.182916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9889 12:20:50.186104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9890 12:20:50.192620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9891 12:20:50.195960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9892 12:20:50.202482 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9893 12:20:50.205627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9894 12:20:50.212829 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9895 12:20:50.216121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9896 12:20:50.222522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9897 12:20:50.225935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9898 12:20:50.232116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9899 12:20:50.236491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9900 12:20:50.242833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9901 12:20:50.245623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9902 12:20:50.252362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9903 12:20:50.255642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9904 12:20:50.261872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9905 12:20:50.264999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9906 12:20:50.272428 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9907 12:20:50.272963 INFO: [APUAPC] vio 0
9908 12:20:50.278685 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9909 12:20:50.282041 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9910 12:20:50.285394 INFO: [APUAPC] D0_APC_0: 0x400510
9911 12:20:50.288607 INFO: [APUAPC] D0_APC_1: 0x0
9912 12:20:50.291907 INFO: [APUAPC] D0_APC_2: 0x1540
9913 12:20:50.295962 INFO: [APUAPC] D0_APC_3: 0x0
9914 12:20:50.298747 INFO: [APUAPC] D1_APC_0: 0xffffffff
9915 12:20:50.301843 INFO: [APUAPC] D1_APC_1: 0xffffffff
9916 12:20:50.305402 INFO: [APUAPC] D1_APC_2: 0x3fffff
9917 12:20:50.308404 INFO: [APUAPC] D1_APC_3: 0x0
9918 12:20:50.312368 INFO: [APUAPC] D2_APC_0: 0xffffffff
9919 12:20:50.315326 INFO: [APUAPC] D2_APC_1: 0xffffffff
9920 12:20:50.318724 INFO: [APUAPC] D2_APC_2: 0x3fffff
9921 12:20:50.321908 INFO: [APUAPC] D2_APC_3: 0x0
9922 12:20:50.325178 INFO: [APUAPC] D3_APC_0: 0xffffffff
9923 12:20:50.329015 INFO: [APUAPC] D3_APC_1: 0xffffffff
9924 12:20:50.331862 INFO: [APUAPC] D3_APC_2: 0x3fffff
9925 12:20:50.332315 INFO: [APUAPC] D3_APC_3: 0x0
9926 12:20:50.335555 INFO: [APUAPC] D4_APC_0: 0xffffffff
9927 12:20:50.342330 INFO: [APUAPC] D4_APC_1: 0xffffffff
9928 12:20:50.345469 INFO: [APUAPC] D4_APC_2: 0x3fffff
9929 12:20:50.345998 INFO: [APUAPC] D4_APC_3: 0x0
9930 12:20:50.349190 INFO: [APUAPC] D5_APC_0: 0xffffffff
9931 12:20:50.352160 INFO: [APUAPC] D5_APC_1: 0xffffffff
9932 12:20:50.355918 INFO: [APUAPC] D5_APC_2: 0x3fffff
9933 12:20:50.358635 INFO: [APUAPC] D5_APC_3: 0x0
9934 12:20:50.361584 INFO: [APUAPC] D6_APC_0: 0xffffffff
9935 12:20:50.365590 INFO: [APUAPC] D6_APC_1: 0xffffffff
9936 12:20:50.368712 INFO: [APUAPC] D6_APC_2: 0x3fffff
9937 12:20:50.372340 INFO: [APUAPC] D6_APC_3: 0x0
9938 12:20:50.375230 INFO: [APUAPC] D7_APC_0: 0xffffffff
9939 12:20:50.378866 INFO: [APUAPC] D7_APC_1: 0xffffffff
9940 12:20:50.382125 INFO: [APUAPC] D7_APC_2: 0x3fffff
9941 12:20:50.385614 INFO: [APUAPC] D7_APC_3: 0x0
9942 12:20:50.388054 INFO: [APUAPC] D8_APC_0: 0xffffffff
9943 12:20:50.391725 INFO: [APUAPC] D8_APC_1: 0xffffffff
9944 12:20:50.395090 INFO: [APUAPC] D8_APC_2: 0x3fffff
9945 12:20:50.398227 INFO: [APUAPC] D8_APC_3: 0x0
9946 12:20:50.401523 INFO: [APUAPC] D9_APC_0: 0xffffffff
9947 12:20:50.405026 INFO: [APUAPC] D9_APC_1: 0xffffffff
9948 12:20:50.408453 INFO: [APUAPC] D9_APC_2: 0x3fffff
9949 12:20:50.412004 INFO: [APUAPC] D9_APC_3: 0x0
9950 12:20:50.415093 INFO: [APUAPC] D10_APC_0: 0xffffffff
9951 12:20:50.418288 INFO: [APUAPC] D10_APC_1: 0xffffffff
9952 12:20:50.422028 INFO: [APUAPC] D10_APC_2: 0x3fffff
9953 12:20:50.424795 INFO: [APUAPC] D10_APC_3: 0x0
9954 12:20:50.428511 INFO: [APUAPC] D11_APC_0: 0xffffffff
9955 12:20:50.431296 INFO: [APUAPC] D11_APC_1: 0xffffffff
9956 12:20:50.434954 INFO: [APUAPC] D11_APC_2: 0x3fffff
9957 12:20:50.437934 INFO: [APUAPC] D11_APC_3: 0x0
9958 12:20:50.441451 INFO: [APUAPC] D12_APC_0: 0xffffffff
9959 12:20:50.445178 INFO: [APUAPC] D12_APC_1: 0xffffffff
9960 12:20:50.447764 INFO: [APUAPC] D12_APC_2: 0x3fffff
9961 12:20:50.451860 INFO: [APUAPC] D12_APC_3: 0x0
9962 12:20:50.454908 INFO: [APUAPC] D13_APC_0: 0xffffffff
9963 12:20:50.458018 INFO: [APUAPC] D13_APC_1: 0xffffffff
9964 12:20:50.461702 INFO: [APUAPC] D13_APC_2: 0x3fffff
9965 12:20:50.464752 INFO: [APUAPC] D13_APC_3: 0x0
9966 12:20:50.468768 INFO: [APUAPC] D14_APC_0: 0xffffffff
9967 12:20:50.471384 INFO: [APUAPC] D14_APC_1: 0xffffffff
9968 12:20:50.475250 INFO: [APUAPC] D14_APC_2: 0x3fffff
9969 12:20:50.478778 INFO: [APUAPC] D14_APC_3: 0x0
9970 12:20:50.481185 INFO: [APUAPC] D15_APC_0: 0xffffffff
9971 12:20:50.484766 INFO: [APUAPC] D15_APC_1: 0xffffffff
9972 12:20:50.488242 INFO: [APUAPC] D15_APC_2: 0x3fffff
9973 12:20:50.491157 INFO: [APUAPC] D15_APC_3: 0x0
9974 12:20:50.494586 INFO: [APUAPC] APC_CON: 0x4
9975 12:20:50.498118 INFO: [NOCDAPC] D0_APC_0: 0x0
9976 12:20:50.501297 INFO: [NOCDAPC] D0_APC_1: 0x0
9977 12:20:50.504403 INFO: [NOCDAPC] D1_APC_0: 0x0
9978 12:20:50.504840 INFO: [NOCDAPC] D1_APC_1: 0xfff
9979 12:20:50.508026 INFO: [NOCDAPC] D2_APC_0: 0x0
9980 12:20:50.511538 INFO: [NOCDAPC] D2_APC_1: 0xfff
9981 12:20:50.514799 INFO: [NOCDAPC] D3_APC_0: 0x0
9982 12:20:50.518284 INFO: [NOCDAPC] D3_APC_1: 0xfff
9983 12:20:50.521155 INFO: [NOCDAPC] D4_APC_0: 0x0
9984 12:20:50.524670 INFO: [NOCDAPC] D4_APC_1: 0xfff
9985 12:20:50.527872 INFO: [NOCDAPC] D5_APC_0: 0x0
9986 12:20:50.531157 INFO: [NOCDAPC] D5_APC_1: 0xfff
9987 12:20:50.535131 INFO: [NOCDAPC] D6_APC_0: 0x0
9988 12:20:50.537983 INFO: [NOCDAPC] D6_APC_1: 0xfff
9989 12:20:50.538406 INFO: [NOCDAPC] D7_APC_0: 0x0
9990 12:20:50.541870 INFO: [NOCDAPC] D7_APC_1: 0xfff
9991 12:20:50.544511 INFO: [NOCDAPC] D8_APC_0: 0x0
9992 12:20:50.547659 INFO: [NOCDAPC] D8_APC_1: 0xfff
9993 12:20:50.551135 INFO: [NOCDAPC] D9_APC_0: 0x0
9994 12:20:50.554719 INFO: [NOCDAPC] D9_APC_1: 0xfff
9995 12:20:50.557783 INFO: [NOCDAPC] D10_APC_0: 0x0
9996 12:20:50.561129 INFO: [NOCDAPC] D10_APC_1: 0xfff
9997 12:20:50.564281 INFO: [NOCDAPC] D11_APC_0: 0x0
9998 12:20:50.567962 INFO: [NOCDAPC] D11_APC_1: 0xfff
9999 12:20:50.571282 INFO: [NOCDAPC] D12_APC_0: 0x0
10000 12:20:50.574320 INFO: [NOCDAPC] D12_APC_1: 0xfff
10001 12:20:50.578181 INFO: [NOCDAPC] D13_APC_0: 0x0
10002 12:20:50.578708 INFO: [NOCDAPC] D13_APC_1: 0xfff
10003 12:20:50.581207 INFO: [NOCDAPC] D14_APC_0: 0x0
10004 12:20:50.584550 INFO: [NOCDAPC] D14_APC_1: 0xfff
10005 12:20:50.587994 INFO: [NOCDAPC] D15_APC_0: 0x0
10006 12:20:50.590804 INFO: [NOCDAPC] D15_APC_1: 0xfff
10007 12:20:50.594509 INFO: [NOCDAPC] APC_CON: 0x4
10008 12:20:50.597239 INFO: [APUAPC] set_apusys_apc done
10009 12:20:50.600543 INFO: [DEVAPC] devapc_init done
10010 12:20:50.604040 INFO: GICv3 without legacy support detected.
10011 12:20:50.610474 INFO: ARM GICv3 driver initialized in EL3
10012 12:20:50.613930 INFO: Maximum SPI INTID supported: 639
10013 12:20:50.617284 INFO: BL31: Initializing runtime services
10014 12:20:50.623925 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10015 12:20:50.624532 INFO: SPM: enable CPC mode
10016 12:20:50.630524 INFO: mcdi ready for mcusys-off-idle and system suspend
10017 12:20:50.634458 INFO: BL31: Preparing for EL3 exit to normal world
10018 12:20:50.637753 INFO: Entry point address = 0x80000000
10019 12:20:50.640857 INFO: SPSR = 0x8
10020 12:20:50.646939
10021 12:20:50.647474
10022 12:20:50.647810
10023 12:20:50.649906 Starting depthcharge on Spherion...
10024 12:20:50.650324
10025 12:20:50.650657 Wipe memory regions:
10026 12:20:50.650979
10027 12:20:50.653575 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10028 12:20:50.654086 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10029 12:20:50.654490 Setting prompt string to ['asurada:']
10030 12:20:50.654880 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10031 12:20:50.655533 [0x00000040000000, 0x00000054600000)
10032 12:20:50.776110
10033 12:20:50.776912 [0x00000054660000, 0x00000080000000)
10034 12:20:51.036327
10035 12:20:51.036905 [0x000000821a7280, 0x000000ffe64000)
10036 12:20:51.781160
10037 12:20:51.781737 [0x00000100000000, 0x00000240000000)
10038 12:20:53.671810
10039 12:20:53.674703 Initializing XHCI USB controller at 0x11200000.
10040 12:20:54.712362
10041 12:20:54.715567 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10042 12:20:54.715676
10043 12:20:54.715759
10044 12:20:54.715859
10045 12:20:54.716180 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10047 12:20:54.816565 asurada: tftpboot 192.168.201.1 12669542/tftp-deploy-z9t3o5tx/kernel/image.itb 12669542/tftp-deploy-z9t3o5tx/kernel/cmdline
10048 12:20:54.816702 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10049 12:20:54.816803 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10050 12:20:54.821790 tftpboot 192.168.201.1 12669542/tftp-deploy-z9t3o5tx/kernel/image.ittp-deploy-z9t3o5tx/kernel/cmdline
10051 12:20:54.821899
10052 12:20:54.822002 Waiting for link
10053 12:20:54.981777
10054 12:20:54.981910 R8152: Initializing
10055 12:20:54.982012
10056 12:20:54.985607 Version 9 (ocp_data = 6010)
10057 12:20:54.985707
10058 12:20:54.988229 R8152: Done initializing
10059 12:20:54.988360
10060 12:20:54.988439 Adding net device
10061 12:20:56.933851
10062 12:20:56.934006 done.
10063 12:20:56.934102
10064 12:20:56.934182 MAC: 00:e0:4c:78:7a:aa
10065 12:20:56.934265
10066 12:20:56.937068 Sending DHCP discover... done.
10067 12:20:56.937145
10068 12:20:56.940319 Waiting for reply... done.
10069 12:20:56.940397
10070 12:20:56.943851 Sending DHCP request... done.
10071 12:20:56.943925
10072 12:20:56.948570 Waiting for reply... done.
10073 12:20:56.948645
10074 12:20:56.948729 My ip is 192.168.201.12
10075 12:20:56.948806
10076 12:20:56.951973 The DHCP server ip is 192.168.201.1
10077 12:20:56.952073
10078 12:20:56.958507 TFTP server IP predefined by user: 192.168.201.1
10079 12:20:56.958583
10080 12:20:56.965023 Bootfile predefined by user: 12669542/tftp-deploy-z9t3o5tx/kernel/image.itb
10081 12:20:56.965136
10082 12:20:56.965225 Sending tftp read request... done.
10083 12:20:56.968582
10084 12:20:56.972143 Waiting for the transfer...
10085 12:20:56.972244
10086 12:20:57.239462 00000000 ################################################################
10087 12:20:57.239625
10088 12:20:57.506680 00080000 ################################################################
10089 12:20:57.506811
10090 12:20:57.772769 00100000 ################################################################
10091 12:20:57.772901
10092 12:20:58.038690 00180000 ################################################################
10093 12:20:58.038866
10094 12:20:58.303787 00200000 ################################################################
10095 12:20:58.303923
10096 12:20:58.569811 00280000 ################################################################
10097 12:20:58.569945
10098 12:20:58.834386 00300000 ################################################################
10099 12:20:58.834522
10100 12:20:59.095668 00380000 ################################################################
10101 12:20:59.095840
10102 12:20:59.361591 00400000 ################################################################
10103 12:20:59.361761
10104 12:20:59.621846 00480000 ################################################################
10105 12:20:59.622012
10106 12:20:59.887996 00500000 ################################################################
10107 12:20:59.888140
10108 12:21:00.158198 00580000 ################################################################
10109 12:21:00.158366
10110 12:21:00.422664 00600000 ################################################################
10111 12:21:00.422824
10112 12:21:00.691638 00680000 ################################################################
10113 12:21:00.691781
10114 12:21:00.949220 00700000 ################################################################
10115 12:21:00.949364
10116 12:21:01.209856 00780000 ################################################################
10117 12:21:01.210004
10118 12:21:01.479396 00800000 ################################################################
10119 12:21:01.479550
10120 12:21:01.743999 00880000 ################################################################
10121 12:21:01.744131
10122 12:21:02.014083 00900000 ################################################################
10123 12:21:02.014246
10124 12:21:02.270235 00980000 ################################################################
10125 12:21:02.270391
10126 12:21:02.530657 00a00000 ################################################################
10127 12:21:02.530790
10128 12:21:02.792510 00a80000 ################################################################
10129 12:21:02.792648
10130 12:21:03.053051 00b00000 ################################################################
10131 12:21:03.053199
10132 12:21:03.321622 00b80000 ################################################################
10133 12:21:03.321770
10134 12:21:03.585486 00c00000 ################################################################
10135 12:21:03.585639
10136 12:21:03.855619 00c80000 ################################################################
10137 12:21:03.855754
10138 12:21:04.120606 00d00000 ################################################################
10139 12:21:04.120736
10140 12:21:04.381639 00d80000 ################################################################
10141 12:21:04.381773
10142 12:21:04.654455 00e00000 ################################################################
10143 12:21:04.654589
10144 12:21:04.927334 00e80000 ################################################################
10145 12:21:04.927469
10146 12:21:05.190663 00f00000 ################################################################
10147 12:21:05.190809
10148 12:21:05.448562 00f80000 ################################################################
10149 12:21:05.448703
10150 12:21:05.711001 01000000 ################################################################
10151 12:21:05.711135
10152 12:21:05.977384 01080000 ################################################################
10153 12:21:05.977522
10154 12:21:06.235035 01100000 ################################################################
10155 12:21:06.235198
10156 12:21:06.497305 01180000 ################################################################
10157 12:21:06.497445
10158 12:21:06.754892 01200000 ################################################################
10159 12:21:06.755029
10160 12:21:07.011929 01280000 ################################################################
10161 12:21:07.012066
10162 12:21:07.272761 01300000 ################################################################
10163 12:21:07.272902
10164 12:21:07.545547 01380000 ################################################################
10165 12:21:07.545717
10166 12:21:07.812670 01400000 ################################################################
10167 12:21:07.812811
10168 12:21:08.081207 01480000 ################################################################
10169 12:21:08.081379
10170 12:21:08.343514 01500000 ################################################################
10171 12:21:08.343660
10172 12:21:08.604198 01580000 ################################################################
10173 12:21:08.604402
10174 12:21:08.868772 01600000 ################################################################
10175 12:21:08.868935
10176 12:21:09.137882 01680000 ################################################################
10177 12:21:09.138049
10178 12:21:09.399512 01700000 ################################################################
10179 12:21:09.399843
10180 12:21:09.668793 01780000 ################################################################
10181 12:21:09.668943
10182 12:21:09.943611 01800000 ################################################################
10183 12:21:09.943755
10184 12:21:10.213763 01880000 ################################################################
10185 12:21:10.213894
10186 12:21:10.478744 01900000 ################################################################
10187 12:21:10.478909
10188 12:21:10.743293 01980000 ################################################################
10189 12:21:10.743425
10190 12:21:11.009027 01a00000 ################################################################
10191 12:21:11.009161
10192 12:21:11.276998 01a80000 ################################################################
10193 12:21:11.277132
10194 12:21:11.547741 01b00000 ################################################################
10195 12:21:11.547880
10196 12:21:11.822000 01b80000 ################################################################
10197 12:21:11.822140
10198 12:21:12.092778 01c00000 ################################################################
10199 12:21:12.092920
10200 12:21:12.366378 01c80000 ################################################################
10201 12:21:12.366519
10202 12:21:12.641485 01d00000 ################################################################
10203 12:21:12.641656
10204 12:21:12.916644 01d80000 ################################################################
10205 12:21:12.916788
10206 12:21:13.186746 01e00000 ################################################################
10207 12:21:13.186889
10208 12:21:13.456169 01e80000 ################################################################
10209 12:21:13.456353
10210 12:21:13.728162 01f00000 ################################################################
10211 12:21:13.728346
10212 12:21:13.992506 01f80000 ################################################################
10213 12:21:13.992652
10214 12:21:14.249304 02000000 ################################################################
10215 12:21:14.249445
10216 12:21:14.507535 02080000 ################################################################
10217 12:21:14.507699
10218 12:21:14.778201 02100000 ################################################################
10219 12:21:14.778415
10220 12:21:15.075392 02180000 ################################################################
10221 12:21:15.075535
10222 12:21:15.355565 02200000 ################################################################
10223 12:21:15.355707
10224 12:21:15.647010 02280000 ################################################################
10225 12:21:15.647173
10226 12:21:15.923588 02300000 ################################################################
10227 12:21:15.923786
10228 12:21:16.194359 02380000 ################################################################
10229 12:21:16.194526
10230 12:21:16.464531 02400000 ################################################################
10231 12:21:16.464698
10232 12:21:16.738122 02480000 ################################################################
10233 12:21:16.738270
10234 12:21:17.006089 02500000 ################################################################
10235 12:21:17.006224
10236 12:21:17.264407 02580000 ################################################################
10237 12:21:17.264540
10238 12:21:17.523111 02600000 ################################################################
10239 12:21:17.523272
10240 12:21:17.789620 02680000 ################################################################
10241 12:21:17.789782
10242 12:21:18.047800 02700000 ################################################################
10243 12:21:18.047935
10244 12:21:18.318403 02780000 ################################################################
10245 12:21:18.318536
10246 12:21:18.612719 02800000 ################################################################
10247 12:21:18.612863
10248 12:21:18.970728 02880000 ################################################################
10249 12:21:18.970909
10250 12:21:19.323096 02900000 ################################################################
10251 12:21:19.323259
10252 12:21:19.663872 02980000 ################################################################
10253 12:21:19.664021
10254 12:21:19.980853 02a00000 ################################################################
10255 12:21:19.981053
10256 12:21:20.249200 02a80000 ################################################################
10257 12:21:20.249335
10258 12:21:20.516426 02b00000 ################################################################
10259 12:21:20.516562
10260 12:21:20.793816 02b80000 ################################################################
10261 12:21:20.793965
10262 12:21:21.075092 02c00000 ################################################################
10263 12:21:21.075227
10264 12:21:21.352891 02c80000 ################################################################
10265 12:21:21.353027
10266 12:21:21.649662 02d00000 ################################################################
10267 12:21:21.649818
10268 12:21:21.944905 02d80000 ################################################################
10269 12:21:21.945065
10270 12:21:22.232721 02e00000 ################################################################
10271 12:21:22.232884
10272 12:21:22.516562 02e80000 ################################################################
10273 12:21:22.516697
10274 12:21:22.781192 02f00000 ################################################################
10275 12:21:22.781328
10276 12:21:23.040546 02f80000 ################################################################
10277 12:21:23.040684
10278 12:21:23.322222 03000000 ################################################################
10279 12:21:23.322362
10280 12:21:23.588204 03080000 ################################################################
10281 12:21:23.588382
10282 12:21:23.628818 03100000 ########## done.
10283 12:21:23.632311
10284 12:21:23.635232 The bootfile was 51458914 bytes long.
10285 12:21:23.635321
10286 12:21:23.635393 Sending tftp read request... done.
10287 12:21:23.635459
10288 12:21:23.638658 Waiting for the transfer...
10289 12:21:23.638746
10290 12:21:23.642055 00000000 # done.
10291 12:21:23.642152
10292 12:21:23.648777 Command line loaded dynamically from TFTP file: 12669542/tftp-deploy-z9t3o5tx/kernel/cmdline
10293 12:21:23.648879
10294 12:21:23.661879 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10295 12:21:23.662038
10296 12:21:23.665217 Loading FIT.
10297 12:21:23.665401
10298 12:21:23.668527 Image ramdisk-1 has 39362318 bytes.
10299 12:21:23.668678
10300 12:21:23.668795 Image fdt-1 has 47278 bytes.
10301 12:21:23.668906
10302 12:21:23.671725 Image kernel-1 has 12047284 bytes.
10303 12:21:23.671896
10304 12:21:23.682153 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10305 12:21:23.682470
10306 12:21:23.698894 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10307 12:21:23.698982
10308 12:21:23.704960 Choosing best match conf-1 for compat google,spherion-rev2.
10309 12:21:23.708466
10310 12:21:23.713403 Connected to device vid:did:rid of 1ae0:0028:00
10311 12:21:23.721316
10312 12:21:23.724797 tpm_get_response: command 0x17b, return code 0x0
10313 12:21:23.724878
10314 12:21:23.728633 ec_init: CrosEC protocol v3 supported (256, 248)
10315 12:21:23.731751
10316 12:21:23.735035 tpm_cleanup: add release locality here.
10317 12:21:23.735117
10318 12:21:23.735181 Shutting down all USB controllers.
10319 12:21:23.738959
10320 12:21:23.739038 Removing current net device
10321 12:21:23.739102
10322 12:21:23.745318 Exiting depthcharge with code 4 at timestamp: 62407275
10323 12:21:23.745399
10324 12:21:23.748841 LZMA decompressing kernel-1 to 0x821a6718
10325 12:21:23.748923
10326 12:21:23.752164 LZMA decompressing kernel-1 to 0x40000000
10327 12:21:25.251701
10328 12:21:25.251841 jumping to kernel
10329 12:21:25.252443 end: 2.2.4 bootloader-commands (duration 00:00:35) [common]
10330 12:21:25.252558 start: 2.2.5 auto-login-action (timeout 00:03:51) [common]
10331 12:21:25.252635 Setting prompt string to ['Linux version [0-9]']
10332 12:21:25.252704 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10333 12:21:25.252776 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10334 12:21:25.333620
10335 12:21:25.337040 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10336 12:21:25.340457 start: 2.2.5.1 login-action (timeout 00:03:51) [common]
10337 12:21:25.340557 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10338 12:21:25.340631 Setting prompt string to []
10339 12:21:25.340711 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10340 12:21:25.340817 Using line separator: #'\n'#
10341 12:21:25.340914 No login prompt set.
10342 12:21:25.341012 Parsing kernel messages
10343 12:21:25.341068 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10344 12:21:25.341171 [login-action] Waiting for messages, (timeout 00:03:51)
10345 12:21:25.360157 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j93261-arm64-gcc-10-defconfig-arm64-chromebook-cwjwh) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024
10346 12:21:25.363368 [ 0.000000] random: crng init done
10347 12:21:25.370020 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10348 12:21:25.373347 [ 0.000000] efi: UEFI not found.
10349 12:21:25.379534 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10350 12:21:25.386762 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10351 12:21:25.396166 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10352 12:21:25.406370 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10353 12:21:25.412585 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10354 12:21:25.419871 [ 0.000000] printk: bootconsole [mtk8250] enabled
10355 12:21:25.426268 [ 0.000000] NUMA: No NUMA configuration found
10356 12:21:25.432796 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10357 12:21:25.436511 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10358 12:21:25.439811 [ 0.000000] Zone ranges:
10359 12:21:25.446078 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10360 12:21:25.449452 [ 0.000000] DMA32 empty
10361 12:21:25.455929 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10362 12:21:25.459292 [ 0.000000] Movable zone start for each node
10363 12:21:25.462849 [ 0.000000] Early memory node ranges
10364 12:21:25.469723 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10365 12:21:25.475800 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10366 12:21:25.482819 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10367 12:21:25.485764 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10368 12:21:25.492571 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10369 12:21:25.499209 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10370 12:21:25.557991 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10371 12:21:25.564599 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10372 12:21:25.571031 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10373 12:21:25.574736 [ 0.000000] psci: probing for conduit method from DT.
10374 12:21:25.581491 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10375 12:21:25.584459 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10376 12:21:25.591282 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10377 12:21:25.594552 [ 0.000000] psci: SMC Calling Convention v1.2
10378 12:21:25.601443 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10379 12:21:25.604407 [ 0.000000] Detected VIPT I-cache on CPU0
10380 12:21:25.610811 [ 0.000000] CPU features: detected: GIC system register CPU interface
10381 12:21:25.617822 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10382 12:21:25.624131 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10383 12:21:25.630737 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10384 12:21:25.637338 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10385 12:21:25.644378 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10386 12:21:25.651216 [ 0.000000] alternatives: applying boot alternatives
10387 12:21:25.654154 [ 0.000000] Fallback order for Node 0: 0
10388 12:21:25.664051 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10389 12:21:25.664224 [ 0.000000] Policy zone: Normal
10390 12:21:25.681019 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10391 12:21:25.690399 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10392 12:21:25.702055 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10393 12:21:25.712240 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10394 12:21:25.718952 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10395 12:21:25.721978 <6>[ 0.000000] software IO TLB: area num 8.
10396 12:21:25.778927 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10397 12:21:25.928081 <6>[ 0.000000] Memory: 7928816K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 423952K reserved, 32768K cma-reserved)
10398 12:21:25.934789 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10399 12:21:25.941500 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10400 12:21:25.944338 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10401 12:21:25.951366 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10402 12:21:25.958295 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10403 12:21:25.961436 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10404 12:21:25.970738 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10405 12:21:25.977461 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10406 12:21:25.984244 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10407 12:21:25.990768 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10408 12:21:25.993976 <6>[ 0.000000] GICv3: 608 SPIs implemented
10409 12:21:25.997746 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10410 12:21:26.004245 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10411 12:21:26.007132 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10412 12:21:26.014425 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10413 12:21:26.027188 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10414 12:21:26.040548 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10415 12:21:26.047624 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10416 12:21:26.054426 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10417 12:21:26.067939 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10418 12:21:26.074773 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10419 12:21:26.081065 <6>[ 0.009234] Console: colour dummy device 80x25
10420 12:21:26.091199 <6>[ 0.013960] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10421 12:21:26.097834 <6>[ 0.024466] pid_max: default: 32768 minimum: 301
10422 12:21:26.101150 <6>[ 0.029338] LSM: Security Framework initializing
10423 12:21:26.108125 <6>[ 0.034278] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10424 12:21:26.117914 <6>[ 0.042093] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10425 12:21:26.127340 <6>[ 0.051555] cblist_init_generic: Setting adjustable number of callback queues.
10426 12:21:26.130897 <6>[ 0.058999] cblist_init_generic: Setting shift to 3 and lim to 1.
10427 12:21:26.140625 <6>[ 0.065338] cblist_init_generic: Setting adjustable number of callback queues.
10428 12:21:26.147540 <6>[ 0.072765] cblist_init_generic: Setting shift to 3 and lim to 1.
10429 12:21:26.150261 <6>[ 0.079166] rcu: Hierarchical SRCU implementation.
10430 12:21:26.157153 <6>[ 0.084181] rcu: Max phase no-delay instances is 1000.
10431 12:21:26.163663 <6>[ 0.091205] EFI services will not be available.
10432 12:21:26.166905 <6>[ 0.096189] smp: Bringing up secondary CPUs ...
10433 12:21:26.175488 <6>[ 0.101235] Detected VIPT I-cache on CPU1
10434 12:21:26.182430 <6>[ 0.101304] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10435 12:21:26.188771 <6>[ 0.101336] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10436 12:21:26.192309 <6>[ 0.101677] Detected VIPT I-cache on CPU2
10437 12:21:26.202005 <6>[ 0.101728] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10438 12:21:26.208332 <6>[ 0.101746] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10439 12:21:26.211969 <6>[ 0.102005] Detected VIPT I-cache on CPU3
10440 12:21:26.218417 <6>[ 0.102052] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10441 12:21:26.225491 <6>[ 0.102066] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10442 12:21:26.231615 <6>[ 0.102373] CPU features: detected: Spectre-v4
10443 12:21:26.234726 <6>[ 0.102380] CPU features: detected: Spectre-BHB
10444 12:21:26.237893 <6>[ 0.102385] Detected PIPT I-cache on CPU4
10445 12:21:26.244612 <6>[ 0.102443] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10446 12:21:26.251583 <6>[ 0.102459] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10447 12:21:26.258672 <6>[ 0.102757] Detected PIPT I-cache on CPU5
10448 12:21:26.264664 <6>[ 0.102819] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10449 12:21:26.271641 <6>[ 0.102837] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10450 12:21:26.274676 <6>[ 0.103116] Detected PIPT I-cache on CPU6
10451 12:21:26.281099 <6>[ 0.103182] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10452 12:21:26.291112 <6>[ 0.103198] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10453 12:21:26.294796 <6>[ 0.103490] Detected PIPT I-cache on CPU7
10454 12:21:26.301192 <6>[ 0.103554] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10455 12:21:26.307720 <6>[ 0.103571] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10456 12:21:26.311200 <6>[ 0.103618] smp: Brought up 1 node, 8 CPUs
10457 12:21:26.317646 <6>[ 0.245146] SMP: Total of 8 processors activated.
10458 12:21:26.320550 <6>[ 0.250066] CPU features: detected: 32-bit EL0 Support
10459 12:21:26.330640 <6>[ 0.255429] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10460 12:21:26.337653 <6>[ 0.264229] CPU features: detected: Common not Private translations
10461 12:21:26.344475 <6>[ 0.270704] CPU features: detected: CRC32 instructions
10462 12:21:26.347935 <6>[ 0.276056] CPU features: detected: RCpc load-acquire (LDAPR)
10463 12:21:26.354091 <6>[ 0.282052] CPU features: detected: LSE atomic instructions
10464 12:21:26.360570 <6>[ 0.287834] CPU features: detected: Privileged Access Never
10465 12:21:26.367237 <6>[ 0.293645] CPU features: detected: RAS Extension Support
10466 12:21:26.374092 <6>[ 0.299254] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10467 12:21:26.377032 <6>[ 0.306473] CPU: All CPU(s) started at EL2
10468 12:21:26.383983 <6>[ 0.310790] alternatives: applying system-wide alternatives
10469 12:21:26.393266 <6>[ 0.321462] devtmpfs: initialized
10470 12:21:26.405801 <6>[ 0.330327] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10471 12:21:26.416000 <6>[ 0.340287] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10472 12:21:26.422001 <6>[ 0.348505] pinctrl core: initialized pinctrl subsystem
10473 12:21:26.425668 <6>[ 0.355140] DMI not present or invalid.
10474 12:21:26.432498 <6>[ 0.359546] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10475 12:21:26.442044 <6>[ 0.366407] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10476 12:21:26.449044 <6>[ 0.373992] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10477 12:21:26.458924 <6>[ 0.382222] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10478 12:21:26.461885 <6>[ 0.390465] audit: initializing netlink subsys (disabled)
10479 12:21:26.471682 <5>[ 0.396154] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10480 12:21:26.478643 <6>[ 0.396848] thermal_sys: Registered thermal governor 'step_wise'
10481 12:21:26.485388 <6>[ 0.404121] thermal_sys: Registered thermal governor 'power_allocator'
10482 12:21:26.488523 <6>[ 0.410375] cpuidle: using governor menu
10483 12:21:26.495307 <6>[ 0.421334] NET: Registered PF_QIPCRTR protocol family
10484 12:21:26.502038 <6>[ 0.426809] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10485 12:21:26.505047 <6>[ 0.433912] ASID allocator initialised with 32768 entries
10486 12:21:26.512046 <6>[ 0.440473] Serial: AMBA PL011 UART driver
10487 12:21:26.520974 <4>[ 0.449242] Trying to register duplicate clock ID: 134
10488 12:21:26.574945 <6>[ 0.506654] KASLR enabled
10489 12:21:26.589764 <6>[ 0.514474] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10490 12:21:26.596561 <6>[ 0.521489] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10491 12:21:26.602560 <6>[ 0.527981] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10492 12:21:26.609328 <6>[ 0.534986] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10493 12:21:26.616406 <6>[ 0.541474] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10494 12:21:26.622526 <6>[ 0.548478] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10495 12:21:26.629589 <6>[ 0.554965] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10496 12:21:26.636022 <6>[ 0.561969] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10497 12:21:26.639660 <6>[ 0.569447] ACPI: Interpreter disabled.
10498 12:21:26.647977 <6>[ 0.575863] iommu: Default domain type: Translated
10499 12:21:26.654324 <6>[ 0.580976] iommu: DMA domain TLB invalidation policy: strict mode
10500 12:21:26.657624 <5>[ 0.587630] SCSI subsystem initialized
10501 12:21:26.664142 <6>[ 0.591797] usbcore: registered new interface driver usbfs
10502 12:21:26.671236 <6>[ 0.597532] usbcore: registered new interface driver hub
10503 12:21:26.674537 <6>[ 0.603083] usbcore: registered new device driver usb
10504 12:21:26.680939 <6>[ 0.609184] pps_core: LinuxPPS API ver. 1 registered
10505 12:21:26.691491 <6>[ 0.614378] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10506 12:21:26.694571 <6>[ 0.623727] PTP clock support registered
10507 12:21:26.697654 <6>[ 0.627967] EDAC MC: Ver: 3.0.0
10508 12:21:26.705503 <6>[ 0.633123] FPGA manager framework
10509 12:21:26.708411 <6>[ 0.636804] Advanced Linux Sound Architecture Driver Initialized.
10510 12:21:26.711954 <6>[ 0.643577] vgaarb: loaded
10511 12:21:26.718961 <6>[ 0.646727] clocksource: Switched to clocksource arch_sys_counter
10512 12:21:26.725283 <5>[ 0.653162] VFS: Disk quotas dquot_6.6.0
10513 12:21:26.732355 <6>[ 0.657348] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10514 12:21:26.735426 <6>[ 0.664533] pnp: PnP ACPI: disabled
10515 12:21:26.743050 <6>[ 0.671234] NET: Registered PF_INET protocol family
10516 12:21:26.752850 <6>[ 0.676822] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10517 12:21:26.764659 <6>[ 0.689127] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10518 12:21:26.774650 <6>[ 0.697941] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10519 12:21:26.781088 <6>[ 0.705911] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10520 12:21:26.787764 <6>[ 0.714613] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10521 12:21:26.799395 <6>[ 0.724360] TCP: Hash tables configured (established 65536 bind 65536)
10522 12:21:26.805841 <6>[ 0.731219] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10523 12:21:26.812795 <6>[ 0.738423] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10524 12:21:26.819194 <6>[ 0.746126] NET: Registered PF_UNIX/PF_LOCAL protocol family
10525 12:21:26.825809 <6>[ 0.752296] RPC: Registered named UNIX socket transport module.
10526 12:21:26.829577 <6>[ 0.758448] RPC: Registered udp transport module.
10527 12:21:26.835722 <6>[ 0.763379] RPC: Registered tcp transport module.
10528 12:21:26.842534 <6>[ 0.768312] RPC: Registered tcp NFSv4.1 backchannel transport module.
10529 12:21:26.845774 <6>[ 0.774981] PCI: CLS 0 bytes, default 64
10530 12:21:26.848879 <6>[ 0.779376] Unpacking initramfs...
10531 12:21:26.866495 <6>[ 0.791357] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10532 12:21:26.876473 <6>[ 0.800025] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10533 12:21:26.879914 <6>[ 0.808879] kvm [1]: IPA Size Limit: 40 bits
10534 12:21:26.886590 <6>[ 0.813408] kvm [1]: GICv3: no GICV resource entry
10535 12:21:26.889930 <6>[ 0.818429] kvm [1]: disabling GICv2 emulation
10536 12:21:26.896244 <6>[ 0.823115] kvm [1]: GIC system register CPU interface enabled
10537 12:21:26.899833 <6>[ 0.829288] kvm [1]: vgic interrupt IRQ18
10538 12:21:26.906428 <6>[ 0.833644] kvm [1]: VHE mode initialized successfully
10539 12:21:26.912926 <5>[ 0.840168] Initialise system trusted keyrings
10540 12:21:26.919787 <6>[ 0.844964] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10541 12:21:26.926795 <6>[ 0.854914] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10542 12:21:26.933284 <5>[ 0.861302] NFS: Registering the id_resolver key type
10543 12:21:26.936403 <5>[ 0.866603] Key type id_resolver registered
10544 12:21:26.943432 <5>[ 0.871018] Key type id_legacy registered
10545 12:21:26.949679 <6>[ 0.875296] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10546 12:21:26.956673 <6>[ 0.882219] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10547 12:21:26.962770 <6>[ 0.889934] 9p: Installing v9fs 9p2000 file system support
10548 12:21:26.998867 <5>[ 0.927231] Key type asymmetric registered
10549 12:21:27.002493 <5>[ 0.931560] Asymmetric key parser 'x509' registered
10550 12:21:27.012083 <6>[ 0.936703] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10551 12:21:27.015651 <6>[ 0.944332] io scheduler mq-deadline registered
10552 12:21:27.019076 <6>[ 0.949115] io scheduler kyber registered
10553 12:21:27.037837 <6>[ 0.966009] EINJ: ACPI disabled.
10554 12:21:27.070299 <4>[ 0.991524] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10555 12:21:27.079618 <4>[ 1.002148] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10556 12:21:27.094828 <6>[ 1.022866] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10557 12:21:27.102416 <6>[ 1.030890] printk: console [ttyS0] disabled
10558 12:21:27.130689 <6>[ 1.055537] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10559 12:21:27.137347 <6>[ 1.065009] printk: console [ttyS0] enabled
10560 12:21:27.140569 <6>[ 1.065009] printk: console [ttyS0] enabled
10561 12:21:27.147498 <6>[ 1.073905] printk: bootconsole [mtk8250] disabled
10562 12:21:27.150830 <6>[ 1.073905] printk: bootconsole [mtk8250] disabled
10563 12:21:27.157634 <6>[ 1.085265] SuperH (H)SCI(F) driver initialized
10564 12:21:27.160124 <6>[ 1.090547] msm_serial: driver initialized
10565 12:21:27.174700 <6>[ 1.099535] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10566 12:21:27.184409 <6>[ 1.108082] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10567 12:21:27.191050 <6>[ 1.116625] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10568 12:21:27.201414 <6>[ 1.125260] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10569 12:21:27.208118 <6>[ 1.133975] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10570 12:21:27.218076 <6>[ 1.142694] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10571 12:21:27.227909 <6>[ 1.151235] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10572 12:21:27.234542 <6>[ 1.160058] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10573 12:21:27.244303 <6>[ 1.168605] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10574 12:21:27.256021 <6>[ 1.184183] loop: module loaded
10575 12:21:27.262842 <6>[ 1.189896] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10576 12:21:27.284677 <4>[ 1.213115] mtk-pmic-keys: Failed to locate of_node [id: -1]
10577 12:21:27.291882 <6>[ 1.220008] megasas: 07.719.03.00-rc1
10578 12:21:27.301591 <6>[ 1.229773] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10579 12:21:27.310222 <6>[ 1.238116] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10580 12:21:27.326705 <6>[ 1.254760] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10581 12:21:27.383083 <6>[ 1.304742] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10582 12:21:28.450117 <6>[ 2.378264] Freeing initrd memory: 38436K
10583 12:21:28.460502 <6>[ 2.388670] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10584 12:21:28.471588 <6>[ 2.399482] tun: Universal TUN/TAP device driver, 1.6
10585 12:21:28.474738 <6>[ 2.405534] thunder_xcv, ver 1.0
10586 12:21:28.478085 <6>[ 2.409038] thunder_bgx, ver 1.0
10587 12:21:28.481458 <6>[ 2.412534] nicpf, ver 1.0
10588 12:21:28.491580 <6>[ 2.416547] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10589 12:21:28.494850 <6>[ 2.424023] hns3: Copyright (c) 2017 Huawei Corporation.
10590 12:21:28.498054 <6>[ 2.429610] hclge is initializing
10591 12:21:28.504918 <6>[ 2.433189] e1000: Intel(R) PRO/1000 Network Driver
10592 12:21:28.511584 <6>[ 2.438318] e1000: Copyright (c) 1999-2006 Intel Corporation.
10593 12:21:28.514712 <6>[ 2.444329] e1000e: Intel(R) PRO/1000 Network Driver
10594 12:21:28.521536 <6>[ 2.449545] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10595 12:21:28.528271 <6>[ 2.455732] igb: Intel(R) Gigabit Ethernet Network Driver
10596 12:21:28.535002 <6>[ 2.461382] igb: Copyright (c) 2007-2014 Intel Corporation.
10597 12:21:28.541718 <6>[ 2.467218] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10598 12:21:28.547991 <6>[ 2.473736] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10599 12:21:28.551495 <6>[ 2.480194] sky2: driver version 1.30
10600 12:21:28.558183 <6>[ 2.485180] VFIO - User Level meta-driver version: 0.3
10601 12:21:28.565540 <6>[ 2.493420] usbcore: registered new interface driver usb-storage
10602 12:21:28.572070 <6>[ 2.499862] usbcore: registered new device driver onboard-usb-hub
10603 12:21:28.581029 <6>[ 2.509044] mt6397-rtc mt6359-rtc: registered as rtc0
10604 12:21:28.590586 <6>[ 2.514511] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-31T12:18:46 UTC (1706703526)
10605 12:21:28.593951 <6>[ 2.524070] i2c_dev: i2c /dev entries driver
10606 12:21:28.610753 <6>[ 2.535711] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10607 12:21:28.631470 <6>[ 2.559700] cpu cpu0: EM: created perf domain
10608 12:21:28.634624 <6>[ 2.564609] cpu cpu4: EM: created perf domain
10609 12:21:28.641962 <6>[ 2.570189] sdhci: Secure Digital Host Controller Interface driver
10610 12:21:28.648217 <6>[ 2.576623] sdhci: Copyright(c) Pierre Ossman
10611 12:21:28.654969 <6>[ 2.581578] Synopsys Designware Multimedia Card Interface Driver
10612 12:21:28.661677 <6>[ 2.588213] sdhci-pltfm: SDHCI platform and OF driver helper
10613 12:21:28.664801 <6>[ 2.588271] mmc0: CQHCI version 5.10
10614 12:21:28.671584 <6>[ 2.598293] ledtrig-cpu: registered to indicate activity on CPUs
10615 12:21:28.678474 <6>[ 2.605376] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10616 12:21:28.685325 <6>[ 2.612454] usbcore: registered new interface driver usbhid
10617 12:21:28.688525 <6>[ 2.618276] usbhid: USB HID core driver
10618 12:21:28.695183 <6>[ 2.622487] spi_master spi0: will run message pump with realtime priority
10619 12:21:28.741987 <6>[ 2.663542] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10620 12:21:28.761712 <6>[ 2.680104] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10621 12:21:28.768545 <6>[ 2.695631] cros-ec-spi spi0.0: Chrome EC device registered
10622 12:21:28.772156 <6>[ 2.695721] mmc0: Command Queue Engine enabled
10623 12:21:28.779040 <6>[ 2.706196] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10624 12:21:28.785348 <6>[ 2.713631] mmcblk0: mmc0:0001 DA4128 116 GiB
10625 12:21:28.795493 <6>[ 2.715098] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10626 12:21:28.798815 <6>[ 2.722775] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10627 12:21:28.805583 <6>[ 2.728699] NET: Registered PF_PACKET protocol family
10628 12:21:28.811751 <6>[ 2.734763] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10629 12:21:28.815521 <6>[ 2.738954] 9pnet: Installing 9P2000 support
10630 12:21:28.822364 <6>[ 2.744810] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10631 12:21:28.824941 <5>[ 2.748631] Key type dns_resolver registered
10632 12:21:28.831549 <6>[ 2.754522] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10633 12:21:28.835295 <6>[ 2.758839] registered taskstats version 1
10634 12:21:28.841989 <5>[ 2.769217] Loading compiled-in X.509 certificates
10635 12:21:28.869526 <4>[ 2.791179] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10636 12:21:28.879555 <4>[ 2.801885] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10637 12:21:28.886181 <3>[ 2.812411] debugfs: File 'uA_load' in directory '/' already present!
10638 12:21:28.892790 <3>[ 2.819110] debugfs: File 'min_uV' in directory '/' already present!
10639 12:21:28.899177 <3>[ 2.825717] debugfs: File 'max_uV' in directory '/' already present!
10640 12:21:28.905719 <3>[ 2.832382] debugfs: File 'constraint_flags' in directory '/' already present!
10641 12:21:28.916607 <3>[ 2.841749] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10642 12:21:28.926061 <6>[ 2.854528] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10643 12:21:28.932922 <6>[ 2.861420] xhci-mtk 11200000.usb: xHCI Host Controller
10644 12:21:28.939682 <6>[ 2.866924] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10645 12:21:28.949974 <6>[ 2.874767] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10646 12:21:28.956378 <6>[ 2.884201] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10647 12:21:28.963138 <6>[ 2.890271] xhci-mtk 11200000.usb: xHCI Host Controller
10648 12:21:28.969769 <6>[ 2.895751] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10649 12:21:28.975984 <6>[ 2.903397] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10650 12:21:28.982982 <6>[ 2.911067] hub 1-0:1.0: USB hub found
10651 12:21:28.986478 <6>[ 2.915080] hub 1-0:1.0: 1 port detected
10652 12:21:28.993129 <6>[ 2.919342] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10653 12:21:28.999791 <6>[ 2.927975] hub 2-0:1.0: USB hub found
10654 12:21:29.003023 <6>[ 2.931999] hub 2-0:1.0: 1 port detected
10655 12:21:29.012170 <6>[ 2.940337] mtk-msdc 11f70000.mmc: Got CD GPIO
10656 12:21:29.023233 <6>[ 2.948299] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10657 12:21:29.029822 <6>[ 2.956310] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10658 12:21:29.040008 <4>[ 2.964224] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10659 12:21:29.049940 <6>[ 2.973752] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10660 12:21:29.056613 <6>[ 2.981829] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10661 12:21:29.063348 <6>[ 2.989836] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10662 12:21:29.073505 <6>[ 2.997756] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10663 12:21:29.079442 <6>[ 3.005573] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10664 12:21:29.089800 <6>[ 3.013391] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10665 12:21:29.099681 <6>[ 3.023849] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10666 12:21:29.106375 <6>[ 3.032238] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10667 12:21:29.116220 <6>[ 3.040587] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10668 12:21:29.123067 <6>[ 3.048925] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10669 12:21:29.132526 <6>[ 3.057264] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10670 12:21:29.139194 <6>[ 3.065604] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10671 12:21:29.149365 <6>[ 3.073942] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10672 12:21:29.155822 <6>[ 3.082281] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10673 12:21:29.165856 <6>[ 3.090619] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10674 12:21:29.172162 <6>[ 3.098957] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10675 12:21:29.182501 <6>[ 3.107297] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10676 12:21:29.192199 <6>[ 3.115635] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10677 12:21:29.198492 <6>[ 3.123973] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10678 12:21:29.208908 <6>[ 3.132311] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10679 12:21:29.215491 <6>[ 3.140649] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10680 12:21:29.222137 <6>[ 3.149223] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10681 12:21:29.228623 <6>[ 3.156384] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10682 12:21:29.235463 <6>[ 3.163150] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10683 12:21:29.242193 <6>[ 3.169907] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10684 12:21:29.248734 <6>[ 3.176843] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10685 12:21:29.258442 <6>[ 3.183691] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10686 12:21:29.268457 <6>[ 3.192820] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10687 12:21:29.278495 <6>[ 3.201939] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10688 12:21:29.288410 <6>[ 3.211232] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10689 12:21:29.298110 <6>[ 3.220698] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10690 12:21:29.304761 <6>[ 3.230165] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10691 12:21:29.315227 <6>[ 3.239284] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10692 12:21:29.324685 <6>[ 3.248751] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10693 12:21:29.334850 <6>[ 3.257869] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10694 12:21:29.344798 <6>[ 3.267163] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10695 12:21:29.354217 <6>[ 3.277323] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10696 12:21:29.364256 <6>[ 3.288991] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10697 12:21:29.414231 <6>[ 3.338999] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10698 12:21:29.568976 <6>[ 3.497007] hub 1-1:1.0: USB hub found
10699 12:21:29.571754 <6>[ 3.501514] hub 1-1:1.0: 4 ports detected
10700 12:21:29.581448 <6>[ 3.509818] hub 1-1:1.0: USB hub found
10701 12:21:29.584604 <6>[ 3.514142] hub 1-1:1.0: 4 ports detected
10702 12:21:29.694133 <6>[ 3.619359] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10703 12:21:29.719703 <6>[ 3.648607] hub 2-1:1.0: USB hub found
10704 12:21:29.722996 <6>[ 3.653111] hub 2-1:1.0: 3 ports detected
10705 12:21:29.732819 <6>[ 3.661120] hub 2-1:1.0: USB hub found
10706 12:21:29.736015 <6>[ 3.665577] hub 2-1:1.0: 3 ports detected
10707 12:21:29.910137 <6>[ 3.835028] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10708 12:21:30.041693 <6>[ 3.969826] hub 1-1.4:1.0: USB hub found
10709 12:21:30.044915 <6>[ 3.974350] hub 1-1.4:1.0: 2 ports detected
10710 12:21:30.053230 <6>[ 3.981568] hub 1-1.4:1.0: USB hub found
10711 12:21:30.056520 <6>[ 3.986132] hub 1-1.4:1.0: 2 ports detected
10712 12:21:30.125680 <6>[ 4.051157] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10713 12:21:30.353782 <6>[ 4.279040] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10714 12:21:30.545648 <6>[ 4.471011] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10715 12:21:41.635196 <6>[ 15.567974] ALSA device list:
10716 12:21:41.705191 <6>[ 15.571263] No soundcards found.
10717 12:21:41.705586 <6>[ 15.578506] Freeing unused kernel memory: 8448K
10718 12:21:41.705892 <6>[ 15.583552] Run /init as init process
10719 12:21:41.706188 <6>[ 15.629172] NET: Registered PF_INET6 protocol family
10720 12:21:41.707799 <6>[ 15.635538] Segment Routing with IPv6
10721 12:21:41.709884 <6>[ 15.639576] In-situ OAM (IOAM) with IPv6
10722 12:21:41.740178 <30>[ 15.652858] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10723 12:21:41.746937 <30>[ 15.676586] systemd[1]: Detected architecture arm64.
10724 12:21:41.747080
10725 12:21:41.753336 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10726 12:21:41.753430
10727 12:21:41.775670 <30>[ 15.695015] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10728 12:21:41.896950 <30>[ 15.823597] systemd[1]: Queued start job for default target Graphical Interface.
10729 12:21:41.950305 <30>[ 15.879869] systemd[1]: Created slice system-getty.slice.
10730 12:21:41.956553 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10731 12:21:41.974336 <30>[ 15.904274] systemd[1]: Created slice system-modprobe.slice.
10732 12:21:41.981070 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10733 12:21:41.997872 <30>[ 15.927403] systemd[1]: Created slice system-serial\x2dgetty.slice.
10734 12:21:42.007819 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10735 12:21:42.023069 <30>[ 15.952377] systemd[1]: Created slice User and Session Slice.
10736 12:21:42.028965 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10737 12:21:42.049371 <30>[ 15.975715] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10738 12:21:42.059283 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10739 12:21:42.076650 <30>[ 16.003237] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10740 12:21:42.083836 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10741 12:21:42.103625 <30>[ 16.027098] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10742 12:21:42.110878 <30>[ 16.039254] systemd[1]: Reached target Local Encrypted Volumes.
10743 12:21:42.117685 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10744 12:21:42.133922 <30>[ 16.063516] systemd[1]: Reached target Paths.
10745 12:21:42.137360 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10746 12:21:42.153268 <30>[ 16.083033] systemd[1]: Reached target Remote File Systems.
10747 12:21:42.159779 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10748 12:21:42.177595 <30>[ 16.107351] systemd[1]: Reached target Slices.
10749 12:21:42.184300 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10750 12:21:42.197867 <30>[ 16.127418] systemd[1]: Reached target Swap.
10751 12:21:42.201090 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10752 12:21:42.221059 <30>[ 16.147512] systemd[1]: Listening on initctl Compatibility Named Pipe.
10753 12:21:42.227964 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10754 12:21:42.234463 <30>[ 16.162644] systemd[1]: Listening on Journal Audit Socket.
10755 12:21:42.241059 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10756 12:21:42.253987 <30>[ 16.183527] systemd[1]: Listening on Journal Socket (/dev/log).
10757 12:21:42.260188 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10758 12:21:42.278592 <30>[ 16.208132] systemd[1]: Listening on Journal Socket.
10759 12:21:42.285372 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10760 12:21:42.301149 <30>[ 16.227727] systemd[1]: Listening on Network Service Netlink Socket.
10761 12:21:42.308487 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10762 12:21:42.321755 <30>[ 16.251603] systemd[1]: Listening on udev Control Socket.
10763 12:21:42.328795 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10764 12:21:42.346245 <30>[ 16.275987] systemd[1]: Listening on udev Kernel Socket.
10765 12:21:42.352732 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10766 12:21:42.406031 <30>[ 16.335278] systemd[1]: Mounting Huge Pages File System...
10767 12:21:42.412334 Mounting [0;1;39mHuge Pages File System[0m...
10768 12:21:42.429419 <30>[ 16.359073] systemd[1]: Mounting POSIX Message Queue File System...
10769 12:21:42.436177 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10770 12:21:42.457216 <30>[ 16.387001] systemd[1]: Mounting Kernel Debug File System...
10771 12:21:42.463568 Mounting [0;1;39mKernel Debug File System[0m...
10772 12:21:42.480743 <30>[ 16.407131] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10773 12:21:42.529336 <30>[ 16.455573] systemd[1]: Starting Create list of static device nodes for the current kernel...
10774 12:21:42.535951 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10775 12:21:42.557665 <30>[ 16.487270] systemd[1]: Starting Load Kernel Module configfs...
10776 12:21:42.564495 Starting [0;1;39mLoad Kernel Module configfs[0m...
10777 12:21:42.581788 <30>[ 16.511403] systemd[1]: Starting Load Kernel Module drm...
10778 12:21:42.588207 Starting [0;1;39mLoad Kernel Module drm[0m...
10779 12:21:42.604842 <30>[ 16.531115] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10780 12:21:42.637629 <30>[ 16.567472] systemd[1]: Starting Journal Service...
10781 12:21:42.641046 Starting [0;1;39mJournal Service[0m...
10782 12:21:42.659563 <30>[ 16.589556] systemd[1]: Starting Load Kernel Modules...
10783 12:21:42.666349 Starting [0;1;39mLoad Kernel Modules[0m...
10784 12:21:42.686594 <30>[ 16.612997] systemd[1]: Starting Remount Root and Kernel File Systems...
10785 12:21:42.693334 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10786 12:21:42.707668 <30>[ 16.637148] systemd[1]: Starting Coldplug All udev Devices...
10787 12:21:42.713905 Starting [0;1;39mColdplug All udev Devices[0m...
10788 12:21:42.733368 <30>[ 16.663166] systemd[1]: Started Journal Service.
10789 12:21:42.739719 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10790 12:21:42.754529 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10791 12:21:42.770061 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10792 12:21:42.785806 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10793 12:21:42.805746 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10794 12:21:42.823031 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10795 12:21:42.838286 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10796 12:21:42.854831 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10797 12:21:42.875617 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10798 12:21:42.889456 See 'systemctl status systemd-remount-fs.service' for details.
10799 12:21:42.942213 Mounting [0;1;39mKernel Configuration File System[0m...
10800 12:21:42.964477 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10801 12:21:42.984684 <46>[ 16.911235] systemd-journald[184]: Received client request to flush runtime journal.
10802 12:21:42.992439 Starting [0;1;39mLoad/Save Random Seed[0m...
10803 12:21:43.013206 Starting [0;1;39mApply Kernel Variables[0m...
10804 12:21:43.035315 Starting [0;1;39mCreate System Users[0m...
10805 12:21:43.057502 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10806 12:21:43.074363 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10807 12:21:43.098013 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10808 12:21:43.115056 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10809 12:21:43.130760 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10810 12:21:43.146060 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10811 12:21:43.206312 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10812 12:21:43.233345 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10813 12:21:43.245671 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10814 12:21:43.265228 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10815 12:21:43.301530 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10816 12:21:43.325185 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10817 12:21:43.345543 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10818 12:21:43.365798 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10819 12:21:43.424557 Starting [0;1;39mNetwo<6>[ 17.349473] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10820 12:21:43.424727 rk Service[0m...
10821 12:21:43.434040 <6>[ 17.360412] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10822 12:21:43.444531 <6>[ 17.369300] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10823 12:21:43.459064 <3>[ 17.385131] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10824 12:21:43.468686 Startin<3>[ 17.394088] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10825 12:21:43.478263 g [0;1;39mNetwo<3>[ 17.402831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10826 12:21:43.484894 <4>[ 17.406980] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10827 12:21:43.488540 rk Time Synchronization[0m...
10828 12:21:43.502779 <4>[ 17.429159] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10829 12:21:43.509166 <3>[ 17.429168] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10830 12:21:43.519269 <3>[ 17.444587] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10831 12:21:43.522511 <6>[ 17.450587] mc: Linux media interface: v0.10
10832 12:21:43.529369 <3>[ 17.452684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10833 12:21:43.539485 <3>[ 17.452688] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10834 12:21:43.545575 <3>[ 17.452691] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10835 12:21:43.555383 <3>[ 17.457265] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10836 12:21:43.562643 <6>[ 17.461840] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10837 12:21:43.568853 <3>[ 17.465585] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10838 12:21:43.575656 <6>[ 17.473785] usbcore: registered new device driver r8152-cfgselector
10839 12:21:43.585622 <3>[ 17.481597] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10840 12:21:43.595231 <6>[ 17.490150] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10841 12:21:43.602288 <3>[ 17.497307] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10842 12:21:43.611999 <3>[ 17.497349] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10843 12:21:43.618795 <4>[ 17.497443] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10844 12:21:43.625127 <4>[ 17.497443] Fallback method does not support PEC.
10845 12:21:43.631507 <6>[ 17.502967] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10846 12:21:43.638298 <6>[ 17.502974] pci_bus 0000:00: root bus resource [bus 00-ff]
10847 12:21:43.645047 <6>[ 17.502980] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10848 12:21:43.655262 <6>[ 17.502985] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10849 12:21:43.661808 <6>[ 17.503012] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10850 12:21:43.668815 <6>[ 17.503031] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10851 12:21:43.671640 <6>[ 17.503122] pci 0000:00:00.0: supports D1 D2
10852 12:21:43.678686 <6>[ 17.503126] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10853 12:21:43.688663 <6>[ 17.504875] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10854 12:21:43.695239 <6>[ 17.504991] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10855 12:21:43.701737 <6>[ 17.505025] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10856 12:21:43.708194 <6>[ 17.505046] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10857 12:21:43.718500 <6>[ 17.505095] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10858 12:21:43.721214 <6>[ 17.505234] pci 0000:01:00.0: supports D1 D2
10859 12:21:43.728456 <6>[ 17.505237] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10860 12:21:43.738258 <6>[ 17.507519] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10861 12:21:43.744926 <3>[ 17.511911] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10862 12:21:43.752248 <3>[ 17.511914] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10863 12:21:43.759031 <6>[ 17.514794] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10864 12:21:43.769046 <6>[ 17.514824] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10865 12:21:43.775571 <6>[ 17.514831] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10866 12:21:43.785820 <6>[ 17.514844] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10867 12:21:43.792315 <6>[ 17.514860] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10868 12:21:43.799583 <6>[ 17.514876] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10869 12:21:43.806638 <6>[ 17.514892] pci 0000:00:00.0: PCI bridge to [bus 01]
10870 12:21:43.813377 <6>[ 17.514900] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10871 12:21:43.819929 <6>[ 17.515032] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10872 12:21:43.826448 <6>[ 17.515979] pcieport 0000:00:00.0: PME: Signaling with IRQ 281
10873 12:21:43.834031 <6>[ 17.516179] pcieport 0000:00:00.0: AER: enabled with IRQ 281
10874 12:21:43.840312 <6>[ 17.549737] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10875 12:21:43.850611 <3>[ 17.559852] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 12:21:43.857233 <3>[ 17.559856] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10877 12:21:43.867135 <3>[ 17.559872] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10878 12:21:43.873649 <6>[ 17.571097] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10879 12:21:43.880149 <6>[ 17.580427] videodev: Linux video capture interface: v2.00
10880 12:21:43.887030 <6>[ 17.590871] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10881 12:21:43.893558 <5>[ 17.591268] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10882 12:21:43.900355 <6>[ 17.596575] Bluetooth: Core ver 2.22
10883 12:21:43.906646 <5>[ 17.600822] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10884 12:21:43.913096 <5>[ 17.601269] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10885 12:21:43.923192 <4>[ 17.601344] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10886 12:21:43.926791 <6>[ 17.601351] cfg80211: failed to load regulatory.db
10887 12:21:43.933194 <6>[ 17.604344] remoteproc remoteproc0: scp is available
10888 12:21:43.939659 <6>[ 17.607850] NET: Registered PF_BLUETOOTH protocol family
10889 12:21:43.946342 <4>[ 17.613770] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10890 12:21:43.956236 <4>[ 17.613779] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10891 12:21:43.959571 <6>[ 17.614734] remoteproc remoteproc0: powering up scp
10892 12:21:43.966292 <6>[ 17.622949] Bluetooth: HCI device and connection manager initialized
10893 12:21:43.972856 <6>[ 17.622958] Bluetooth: HCI socket layer initialized
10894 12:21:43.979436 <6>[ 17.629550] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10895 12:21:43.986064 <6>[ 17.636683] Bluetooth: L2CAP socket layer initialized
10896 12:21:43.992663 <6>[ 17.636695] Bluetooth: SCO socket layer initialized
10897 12:21:43.996137 <6>[ 17.644167] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10898 12:21:44.002713 <6>[ 17.646200] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10899 12:21:44.015739 <6>[ 17.647467] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10900 12:21:44.022375 <6>[ 17.647645] usbcore: registered new interface driver uvcvideo
10901 12:21:44.025926 <6>[ 17.663669] r8152 2-1.3:1.0 eth0: v1.12.13
10902 12:21:44.032191 <6>[ 17.672538] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10903 12:21:44.039073 <6>[ 17.680267] usbcore: registered new interface driver r8152
10904 12:21:44.049123 <3>[ 17.684249] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 12:21:44.055663 <3>[ 17.686773] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
10906 12:21:44.062585 <6>[ 17.699252] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10907 12:21:44.069085 <6>[ 17.719410] usbcore: registered new interface driver cdc_ether
10908 12:21:44.076045 <6>[ 17.719556] usbcore: registered new interface driver btusb
10909 12:21:44.085844 <4>[ 17.720189] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10910 12:21:44.092345 <3>[ 17.720198] Bluetooth: hci0: Failed to load firmware file (-2)
10911 12:21:44.099191 <3>[ 17.720201] Bluetooth: hci0: Failed to set up firmware (-2)
10912 12:21:44.109237 <4>[ 17.720204] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10913 12:21:44.115695 <6>[ 17.727355] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10914 12:21:44.122385 <3>[ 17.739462] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 12:21:44.128907 <6>[ 17.740607] usbcore: registered new interface driver r8153_ecm
10916 12:21:44.136805 <3>[ 17.748615] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10917 12:21:44.143021 <6>[ 17.759068] mt7921e 0000:01:00.0: ASIC revision: 79610010
10918 12:21:44.150404 <6>[ 17.763719] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10919 12:21:44.159429 <3>[ 17.774174] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 12:21:44.166163 <6>[ 17.798010] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10921 12:21:44.173057 <6>[ 17.798045] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10922 12:21:44.180160 <6>[ 17.798051] remoteproc remoteproc0: remote processor scp is now up
10923 12:21:44.190316 <6>[ 18.058308] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10924 12:21:44.190474 <6>[ 18.058308]
10925 12:21:44.200231 <3>[ 18.071092] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 12:21:44.206787 <6>[ 18.079895] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10927 12:21:44.216974 <3>[ 18.113059] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 12:21:44.223304 <6>[ 18.117485] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10929 12:21:44.229789 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10930 12:21:44.257103 [[0;32m OK [<3>[ 18.180457] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 12:21:44.260309 0m] Started [0;1;39mNetwork Service[0m.
10932 12:21:44.273759 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10933 12:21:44.289307 <3>[ 18.216135] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 12:21:44.330487 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10935 12:21:44.347551 <3>[ 18.273908] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 12:21:44.375628 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10937 12:21:44.405572 <6>[ 18.332558] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10938 12:21:44.514975 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10939 12:21:44.528760 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10940 12:21:44.544731 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10941 12:21:44.561185 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10942 12:21:44.580240 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10943 12:21:44.616869 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10944 12:21:44.633474 Starting [0;1;39mNetwork Name Resolution[0m...
10945 12:21:44.655249 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10946 12:21:44.669683 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10947 12:21:44.689657 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10948 12:21:44.705006 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10949 12:21:44.717277 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10950 12:21:44.737594 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10951 12:21:44.748994 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10952 12:21:44.765613 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10953 12:21:44.809073 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10954 12:21:44.840241 Starting [0;1;39mUser Login Management[0m...
10955 12:21:44.856798 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10956 12:21:44.874124 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10957 12:21:44.882233 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10958 12:21:44.897972 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10959 12:21:44.916098 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10960 12:21:44.949325 Starting [0;1;39mPermit User Sessions[0m...
10961 12:21:44.967173 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10962 12:21:44.985767 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10963 12:21:45.022277 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10964 12:21:45.058225 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10965 12:21:45.074461 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10966 12:21:45.089739 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10967 12:21:45.106772 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10968 12:21:45.158641 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10969 12:21:45.200244 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10970 12:21:45.246701
10971 12:21:45.246819
10972 12:21:45.249749 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10973 12:21:45.249831
10974 12:21:45.256720 debian-bullseye-arm64 logi<6>[ 19.185445] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10975 12:21:45.260031 n: root (automatic login)
10976 12:21:45.260146
10977 12:21:45.260228
10978 12:21:45.270122 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024 aarch64
10979 12:21:45.270259
10980 12:21:45.277367 The programs included with the Debian GNU/Linux system are free software;
10981 12:21:45.283400 the exact distribution terms for each program are described in the
10982 12:21:45.286769 individual files in /usr/share/doc/*/copyright.
10983 12:21:45.286852
10984 12:21:45.293302 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10985 12:21:45.296778 permitted by applicable law.
10986 12:21:45.297273 Matched prompt #10: / #
10988 12:21:45.297514 Setting prompt string to ['/ #']
10989 12:21:45.297605 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10991 12:21:45.297794 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10992 12:21:45.297881 start: 2.2.6 expect-shell-connection (timeout 00:03:31) [common]
10993 12:21:45.297949 Setting prompt string to ['/ #']
10994 12:21:45.298009 Forcing a shell prompt, looking for ['/ #']
10996 12:21:45.348223 / #
10997 12:21:45.348396 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10998 12:21:45.348509 Waiting using forced prompt support (timeout 00:02:30)
10999 12:21:45.348608 <6>[ 19.251426] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
11000 12:21:45.348674 <6>[ 19.259352] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
11001 12:21:45.354169
11002 12:21:45.354444 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11003 12:21:45.354536 start: 2.2.7 export-device-env (timeout 00:03:31) [common]
11004 12:21:45.354628 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11005 12:21:45.354713 end: 2.2 depthcharge-retry (duration 00:01:29) [common]
11006 12:21:45.354798 end: 2 depthcharge-action (duration 00:01:29) [common]
11007 12:21:45.354883 start: 3 lava-test-retry (timeout 00:08:10) [common]
11008 12:21:45.354965 start: 3.1 lava-test-shell (timeout 00:08:10) [common]
11009 12:21:45.355035 Using namespace: common
11011 12:21:45.455391 / # #
11012 12:21:45.455567 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11013 12:21:45.460502 #
11014 12:21:45.460771 Using /lava-12669542
11016 12:21:45.561118 / # export SHELL=/bin/sh
11017 12:21:45.566923 export SHELL=/bin/sh
11019 12:21:45.667446 / # . /lava-12669542/environment
11020 12:21:45.672672 . /lava-12669542/environment
11022 12:21:45.773204 / # /lava-12669542/bin/lava-test-runner /lava-12669542/0
11023 12:21:45.773347 Test shell timeout: 10s (minimum of the action and connection timeout)
11024 12:21:45.778383 /lava-12669542/bin/lava-test-runner /lava-12669542/0
11025 12:21:45.795743 + export TESTRUN_ID=0_v4l2-compliance-uvc
11026 12:21:45.799323 + cd /lava-12669542/0/tests/0_v4l2-compliance-uvc
11027 12:21:45.799408 + cat uuid
11028 12:21:45.802899 + UUID=12669542_1.5.2.3.1
11029 12:21:45.802982 + set +x
11030 12:21:45.809476 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 12669542_1.5.2.3.1>
11031 12:21:45.809737 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 12669542_1.5.2.3.1
11032 12:21:45.809813 Starting test lava.0_v4l2-compliance-uvc (12669542_1.5.2.3.1)
11033 12:21:45.809901 Skipping test definition patterns.
11034 12:21:45.812326 + /usr/bin/v4l2-parser.sh -d uvcvideo
11035 12:21:45.874665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11036 12:21:45.875092 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11038 12:21:45.877874 device: /dev/video0
11039 12:21:52.365644 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11040 12:21:52.376653 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11041 12:21:52.383928
11042 12:21:52.397899 Compliance test for uvcvideo device /dev/video0:
11043 12:21:52.409539
11044 12:21:52.420005 Driver Info:
11045 12:21:52.432862 Driver name : uvcvideo
11046 12:21:52.448193 Card type : HD User Facing: HD User Facing
11047 12:21:52.456066 Bus info : usb-11200000.usb-1.4.1
11048 12:21:52.464024 Driver version : 6.1.72
11049 12:21:52.474684 Capabilities : 0x84a00001
11050 12:21:52.489153 Metadata Capture
11051 12:21:52.499245 Streaming
11052 12:21:52.513150 Extended Pix Format
11053 12:21:52.522681 Device Capabilities
11054 12:21:52.535426 Device Caps : 0x04200001
11055 12:21:52.547940 Streaming
11056 12:21:52.559716 Extended Pix Format
11057 12:21:52.570318 Media Driver Info:
11058 12:21:52.582395 Driver name : uvcvideo
11059 12:21:52.597732 Model : HD User Facing: HD User Facing
11060 12:21:52.604293 Serial : 200901010001
11061 12:21:52.616965 Bus info : usb-11200000.usb-1.4.1
11062 12:21:52.623310 Media version : 6.1.72
11063 12:21:52.639365 Hardware revision: 0x00009758 (38744)
11064 12:21:52.645962 Driver version : 6.1.72
11065 12:21:52.660225 Interface Info:
11066 12:21:52.674405 <LAVA_SIGNAL_TESTSET START Interface-Info>
11067 12:21:52.674529 ID : 0x03000002
11068 12:21:52.674807 Received signal: <TESTSET> START Interface-Info
11069 12:21:52.674939 Starting test_set Interface-Info
11070 12:21:52.683702 Type : V4L Video
11071 12:21:52.695977 Entity Info:
11072 12:21:52.705169 <LAVA_SIGNAL_TESTSET STOP>
11073 12:21:52.705525 Received signal: <TESTSET> STOP
11074 12:21:52.705645 Closing test_set Interface-Info
11075 12:21:52.714351 <LAVA_SIGNAL_TESTSET START Entity-Info>
11076 12:21:52.714680 Received signal: <TESTSET> START Entity-Info
11077 12:21:52.714790 Starting test_set Entity-Info
11078 12:21:52.717986 ID : 0x00000001 (1)
11079 12:21:52.727233 Name : HD User Facing: HD User Facing
11080 12:21:52.734352 Function : V4L2 I/O
11081 12:21:52.747044 Flags : default
11082 12:21:52.757075 Pad 0x01000007 : 0: Sink
11083 12:21:52.778472 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11084 12:21:52.778602
11085 12:21:52.790329 Required ioctls:
11086 12:21:52.796836 <LAVA_SIGNAL_TESTSET STOP>
11087 12:21:52.797108 Received signal: <TESTSET> STOP
11088 12:21:52.797187 Closing test_set Entity-Info
11089 12:21:52.806014 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11090 12:21:52.806288 Received signal: <TESTSET> START Required-ioctls
11091 12:21:52.806364 Starting test_set Required-ioctls
11092 12:21:52.809065 test MC information (see 'Media Driver Info' above): OK
11093 12:21:52.831914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11094 12:21:52.832204 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11096 12:21:52.834759 test VIDIOC_QUERYCAP: OK
11097 12:21:52.848624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11098 12:21:52.848910 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11100 12:21:52.851225 test invalid ioctls: OK
11101 12:21:52.871362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11102 12:21:52.871455
11103 12:21:52.871691 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11105 12:21:52.880716 Allow for multiple opens:
11106 12:21:52.886483 <LAVA_SIGNAL_TESTSET STOP>
11107 12:21:52.886735 Received signal: <TESTSET> STOP
11108 12:21:52.886807 Closing test_set Required-ioctls
11109 12:21:52.895060 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11110 12:21:52.895320 Received signal: <TESTSET> START Allow-for-multiple-opens
11111 12:21:52.895392 Starting test_set Allow-for-multiple-opens
11112 12:21:52.898122 test second /dev/video0 open: OK
11113 12:21:52.916792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11114 12:21:52.917056 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11116 12:21:52.920133 test VIDIOC_QUERYCAP: OK
11117 12:21:52.937801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11118 12:21:52.938059 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11120 12:21:52.941447 test VIDIOC_G/S_PRIORITY: OK
11121 12:21:52.960130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11122 12:21:52.960390 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11124 12:21:52.963732 test for unlimited opens: OK
11125 12:21:52.982435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11126 12:21:52.982559
11127 12:21:52.982822 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11129 12:21:52.991647 Debug ioctls:
11130 12:21:52.998418 <LAVA_SIGNAL_TESTSET STOP>
11131 12:21:52.998759 Received signal: <TESTSET> STOP
11132 12:21:52.998871 Closing test_set Allow-for-multiple-opens
11133 12:21:53.007208 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11134 12:21:53.007467 Received signal: <TESTSET> START Debug-ioctls
11135 12:21:53.007559 Starting test_set Debug-ioctls
11136 12:21:53.010100 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11137 12:21:53.029003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11138 12:21:53.029264 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11140 12:21:53.035256 test VIDIOC_LOG_STATUS: OK (Not Supported)
11141 12:21:53.050245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11142 12:21:53.050362
11143 12:21:53.050631 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11145 12:21:53.059140 Input ioctls:
11146 12:21:53.066929 <LAVA_SIGNAL_TESTSET STOP>
11147 12:21:53.067209 Received signal: <TESTSET> STOP
11148 12:21:53.067308 Closing test_set Debug-ioctls
11149 12:21:53.076721 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11150 12:21:53.076984 Received signal: <TESTSET> START Input-ioctls
11151 12:21:53.077057 Starting test_set Input-ioctls
11152 12:21:53.079547 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11153 12:21:53.103864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11154 12:21:53.104134 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11156 12:21:53.107459 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11157 12:21:53.122137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11158 12:21:53.122429 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11160 12:21:53.129169 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11161 12:21:53.148670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11162 12:21:53.148926 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11164 12:21:53.151896 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11165 12:21:53.169454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11166 12:21:53.169741 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11168 12:21:53.172892 test VIDIOC_G/S/ENUMINPUT: OK
11169 12:21:53.193259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11170 12:21:53.193529 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11172 12:21:53.196692 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11173 12:21:53.214238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11174 12:21:53.214503 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11176 12:21:53.217887 Inputs: 1 Audio Inputs: 0 Tuners: 0
11177 12:21:53.226071
11178 12:21:53.241148 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11179 12:21:53.265431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11180 12:21:53.265697 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11182 12:21:53.272130 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11183 12:21:53.288336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11184 12:21:53.288636 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11186 12:21:53.295020 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11187 12:21:53.312885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11188 12:21:53.313169 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11190 12:21:53.319514 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11191 12:21:53.341782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11192 12:21:53.342041 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11194 12:21:53.348178 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11195 12:21:53.362276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11196 12:21:53.362359
11197 12:21:53.362622 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11199 12:21:53.380040 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11200 12:21:53.398515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11201 12:21:53.398821 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11203 12:21:53.405250 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11204 12:21:53.423148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11205 12:21:53.423445 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11207 12:21:53.426652 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11208 12:21:53.442356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11209 12:21:53.442644 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11211 12:21:53.445174 test VIDIOC_G/S_EDID: OK (Not Supported)
11212 12:21:53.465410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11213 12:21:53.465525
11214 12:21:53.465800 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11216 12:21:53.474065 Control ioctls (Input 0):
11217 12:21:53.481988 <LAVA_SIGNAL_TESTSET STOP>
11218 12:21:53.482272 Received signal: <TESTSET> STOP
11219 12:21:53.482372 Closing test_set Input-ioctls
11220 12:21:53.490447 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11221 12:21:53.490729 Received signal: <TESTSET> START Control-ioctls-Input-0
11222 12:21:53.490835 Starting test_set Control-ioctls-Input-0
11223 12:21:53.493947 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11224 12:21:53.513705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11225 12:21:53.513829 test VIDIOC_QUERYCTRL: OK
11226 12:21:53.514100 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11228 12:21:53.536575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11229 12:21:53.536833 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11231 12:21:53.539919 test VIDIOC_G/S_CTRL: OK
11232 12:21:53.558801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11233 12:21:53.559123 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11235 12:21:53.561468 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11236 12:21:53.580616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11237 12:21:53.580882 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11239 12:21:53.586662 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11240 12:21:53.605246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11241 12:21:53.605530 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11243 12:21:53.608061 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11244 12:21:53.623564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11245 12:21:53.623825 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11247 12:21:53.627090 Standard Controls: 16 Private Controls: 0
11248 12:21:53.637042
11249 12:21:53.647643 Format ioctls (Input 0):
11250 12:21:53.654195 <LAVA_SIGNAL_TESTSET STOP>
11251 12:21:53.654454 Received signal: <TESTSET> STOP
11252 12:21:53.654530 Closing test_set Control-ioctls-Input-0
11253 12:21:53.663322 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11254 12:21:53.663578 Received signal: <TESTSET> START Format-ioctls-Input-0
11255 12:21:53.663653 Starting test_set Format-ioctls-Input-0
11256 12:21:53.666295 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11257 12:21:53.689244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11258 12:21:53.689510 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11260 12:21:53.692058 test VIDIOC_G/S_PARM: OK
11261 12:21:53.707260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11262 12:21:53.707586 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11264 12:21:53.709452 test VIDIOC_G_FBUF: OK (Not Supported)
11265 12:21:53.726724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11266 12:21:53.727002 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11268 12:21:53.730140 test VIDIOC_G_FMT: OK
11269 12:21:53.750716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11270 12:21:53.750994 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11272 12:21:53.753528 test VIDIOC_TRY_FMT: OK
11273 12:21:53.773410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11274 12:21:53.773669 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11276 12:21:53.780218 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11277 12:21:53.783534 test VIDIOC_S_FMT: OK
11278 12:21:53.805766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11279 12:21:53.806029 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11281 12:21:53.809109 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11282 12:21:53.832413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11283 12:21:53.832682 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11285 12:21:53.835599 test Cropping: OK (Not Supported)
11286 12:21:53.853587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11287 12:21:53.853880 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11289 12:21:53.856359 test Composing: OK (Not Supported)
11290 12:21:53.875257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11291 12:21:53.875538 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11293 12:21:53.878775 test Scaling: OK (Not Supported)
11294 12:21:53.897496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11295 12:21:53.897604
11296 12:21:53.897873 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11298 12:21:53.907755 Codec ioctls (Input 0):
11299 12:21:53.915924 <LAVA_SIGNAL_TESTSET STOP>
11300 12:21:53.916174 Received signal: <TESTSET> STOP
11301 12:21:53.916244 Closing test_set Format-ioctls-Input-0
11302 12:21:53.926658 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11303 12:21:53.926936 Received signal: <TESTSET> START Codec-ioctls-Input-0
11304 12:21:53.927034 Starting test_set Codec-ioctls-Input-0
11305 12:21:53.930096 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11306 12:21:53.949741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11307 12:21:53.949994 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11309 12:21:53.956351 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11310 12:21:53.970474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11311 12:21:53.970737 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11313 12:21:53.976704 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11314 12:21:53.993101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11315 12:21:53.993183
11316 12:21:53.993426 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11318 12:21:54.003169 Buffer ioctls (Input 0):
11319 12:21:54.010631 <LAVA_SIGNAL_TESTSET STOP>
11320 12:21:54.010917 Received signal: <TESTSET> STOP
11321 12:21:54.011021 Closing test_set Codec-ioctls-Input-0
11322 12:21:54.019289 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11323 12:21:54.019573 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11324 12:21:54.019676 Starting test_set Buffer-ioctls-Input-0
11325 12:21:54.022605 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11326 12:21:54.044842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11327 12:21:54.044953 test VIDIOC_EXPBUF: OK
11328 12:21:54.045229 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11330 12:21:54.063563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11331 12:21:54.063853 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11333 12:21:54.066513 test Requests: OK (Not Supported)
11334 12:21:54.085257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11335 12:21:54.085367
11336 12:21:54.085637 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11338 12:21:54.096470 Test input 0:
11339 12:21:54.104965
11340 12:21:54.114191 Streaming ioctls:
11341 12:21:54.121218 <LAVA_SIGNAL_TESTSET STOP>
11342 12:21:54.121487 Received signal: <TESTSET> STOP
11343 12:21:54.121563 Closing test_set Buffer-ioctls-Input-0
11344 12:21:54.133246 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11345 12:21:54.133506 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11346 12:21:54.133614 Starting test_set Streaming-ioctls_Test-input-0
11347 12:21:54.136177 test read/write: OK (Not Supported)
11348 12:21:54.156627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11349 12:21:54.156907 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11351 12:21:54.159667 test blocking wait: OK
11352 12:21:54.178190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11353 12:21:54.178472 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11355 12:21:54.188546 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11356 12:21:54.191299 test MMAP (no poll): FAIL
11357 12:21:54.214405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11358 12:21:54.214690 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11360 12:21:54.224495 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11361 12:21:54.229265 test MMAP (select): FAIL
11362 12:21:54.250330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11363 12:21:54.250621 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11365 12:21:54.260235 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11366 12:21:54.260353 test MMAP (epoll): FAIL
11367 12:21:54.288134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11368 12:21:54.288216
11369 12:21:54.288451 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11371 12:21:54.299221
11372 12:21:54.505667
11373 12:21:54.515330 test USERPTR (no poll): OK
11374 12:21:54.541494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11375 12:21:54.541615
11376 12:21:54.541893 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11378 12:21:54.551636
11379 12:21:54.722274
11380 12:21:54.732124 test USERPTR (select): OK
11381 12:21:54.752606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11382 12:21:54.752872 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11384 12:21:54.759179 test DMABUF: Cannot test, specify --expbuf-device
11385 12:21:54.762935
11386 12:21:54.784385 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11387 12:21:54.784691 ok: lava_test_shell seems to have completed
11388 12:21:54.784802 Marking unfinished test run as failed
11390 12:21:54.786429 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11391 12:21:54.786560 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11392 12:21:54.786658 end: 3 lava-test-retry (duration 00:00:09) [common]
11393 12:21:54.786763 start: 4 finalize (timeout 00:08:01) [common]
11394 12:21:54.786900 start: 4.1 power-off (timeout 00:00:30) [common]
11395 12:21:54.787169 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11396 12:21:54.864080 >> Command sent successfully.
11397 12:21:54.866897 Returned 0 in 0 seconds
11398 12:21:54.967328 end: 4.1 power-off (duration 00:00:00) [common]
11400 12:21:54.967663 start: 4.2 read-feedback (timeout 00:08:01) [common]
11402 12:21:54.968252 Listened to connection for namespace 'common' for up to 1s
11403 12:21:55.968388 Finalising connection for namespace 'common'
11404 12:21:55.968550 Disconnecting from shell: Finalise
11405 12:21:55.968662 / #
11406 12:21:56.068968 end: 4.2 read-feedback (duration 00:00:01) [common]
11407 12:21:56.069124 end: 4 finalize (duration 00:00:01) [common]
11408 12:21:56.069247 Cleaning after the job
11409 12:21:56.069348 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669542/tftp-deploy-z9t3o5tx/ramdisk
11410 12:21:56.075090 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669542/tftp-deploy-z9t3o5tx/kernel
11411 12:21:56.091406 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669542/tftp-deploy-z9t3o5tx/dtb
11412 12:21:56.091603 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669542/tftp-deploy-z9t3o5tx/modules
11413 12:21:56.099217 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12669542
11414 12:21:56.185342 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12669542
11415 12:21:56.185513 Job finished correctly