Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: FAIL
- Errors: 2
- Kernel Warnings: 13
- Kernel Errors: 27
1 04:42:52.714697 lava-dispatcher, installed at version: 2023.10
2 04:42:52.714913 start: 0 validate
3 04:42:52.715045 Start time: 2024-02-04 04:42:52.715037+00:00 (UTC)
4 04:42:52.715164 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:42:52.715299 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 04:42:52.976220 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:42:52.977111 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:43:22.985799 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:43:22.986467 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:43:23.247021 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:43:23.247705 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 04:43:29.008668 validate duration: 36.29
14 04:43:29.008933 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:43:29.009042 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:43:29.009164 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:43:29.009315 Not decompressing ramdisk as can be used compressed.
18 04:43:29.009406 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 04:43:29.009473 saving as /var/lib/lava/dispatcher/tmp/12699833/tftp-deploy-7_8yyls4/ramdisk/rootfs.cpio.gz
20 04:43:29.009538 total size: 8181372 (7 MB)
21 04:43:29.274045 progress 0 % (0 MB)
22 04:43:29.277060 progress 5 % (0 MB)
23 04:43:29.279236 progress 10 % (0 MB)
24 04:43:29.281755 progress 15 % (1 MB)
25 04:43:29.283945 progress 20 % (1 MB)
26 04:43:29.286425 progress 25 % (1 MB)
27 04:43:29.288846 progress 30 % (2 MB)
28 04:43:29.291351 progress 35 % (2 MB)
29 04:43:29.293637 progress 40 % (3 MB)
30 04:43:29.296207 progress 45 % (3 MB)
31 04:43:29.298539 progress 50 % (3 MB)
32 04:43:29.301030 progress 55 % (4 MB)
33 04:43:29.303263 progress 60 % (4 MB)
34 04:43:29.305704 progress 65 % (5 MB)
35 04:43:29.308050 progress 70 % (5 MB)
36 04:43:29.310482 progress 75 % (5 MB)
37 04:43:29.312750 progress 80 % (6 MB)
38 04:43:29.315147 progress 85 % (6 MB)
39 04:43:29.317515 progress 90 % (7 MB)
40 04:43:29.319915 progress 95 % (7 MB)
41 04:43:29.322185 progress 100 % (7 MB)
42 04:43:29.322400 7 MB downloaded in 0.31 s (24.94 MB/s)
43 04:43:29.322564 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:43:29.322826 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:43:29.322917 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:43:29.323003 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:43:29.323151 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 04:43:29.323260 saving as /var/lib/lava/dispatcher/tmp/12699833/tftp-deploy-7_8yyls4/kernel/Image
50 04:43:29.323352 total size: 51597824 (49 MB)
51 04:43:29.323440 No compression specified
52 04:43:29.324626 progress 0 % (0 MB)
53 04:43:29.338827 progress 5 % (2 MB)
54 04:43:29.353469 progress 10 % (4 MB)
55 04:43:29.368228 progress 15 % (7 MB)
56 04:43:29.382496 progress 20 % (9 MB)
57 04:43:29.396829 progress 25 % (12 MB)
58 04:43:29.411061 progress 30 % (14 MB)
59 04:43:29.426226 progress 35 % (17 MB)
60 04:43:29.441740 progress 40 % (19 MB)
61 04:43:29.457924 progress 45 % (22 MB)
62 04:43:29.474393 progress 50 % (24 MB)
63 04:43:29.490896 progress 55 % (27 MB)
64 04:43:29.505966 progress 60 % (29 MB)
65 04:43:29.520773 progress 65 % (32 MB)
66 04:43:29.536054 progress 70 % (34 MB)
67 04:43:29.550515 progress 75 % (36 MB)
68 04:43:29.565419 progress 80 % (39 MB)
69 04:43:29.579258 progress 85 % (41 MB)
70 04:43:29.592825 progress 90 % (44 MB)
71 04:43:29.606075 progress 95 % (46 MB)
72 04:43:29.619661 progress 100 % (49 MB)
73 04:43:29.619917 49 MB downloaded in 0.30 s (165.93 MB/s)
74 04:43:29.620080 end: 1.2.1 http-download (duration 00:00:00) [common]
76 04:43:29.620335 end: 1.2 download-retry (duration 00:00:00) [common]
77 04:43:29.620426 start: 1.3 download-retry (timeout 00:09:59) [common]
78 04:43:29.620519 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 04:43:29.620663 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 04:43:29.620735 saving as /var/lib/lava/dispatcher/tmp/12699833/tftp-deploy-7_8yyls4/dtb/mt8192-asurada-spherion-r0.dtb
81 04:43:29.620799 total size: 47278 (0 MB)
82 04:43:29.620863 No compression specified
83 04:43:29.622025 progress 69 % (0 MB)
84 04:43:29.622310 progress 100 % (0 MB)
85 04:43:29.622471 0 MB downloaded in 0.00 s (27.01 MB/s)
86 04:43:29.622599 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:43:29.622829 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:43:29.622924 start: 1.4 download-retry (timeout 00:09:59) [common]
90 04:43:29.623011 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 04:43:29.623131 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 04:43:29.623205 saving as /var/lib/lava/dispatcher/tmp/12699833/tftp-deploy-7_8yyls4/modules/modules.tar
93 04:43:29.623268 total size: 8633524 (8 MB)
94 04:43:29.623332 Using unxz to decompress xz
95 04:43:29.628128 progress 0 % (0 MB)
96 04:43:29.650050 progress 5 % (0 MB)
97 04:43:29.674780 progress 10 % (0 MB)
98 04:43:29.699077 progress 15 % (1 MB)
99 04:43:29.723323 progress 20 % (1 MB)
100 04:43:29.748021 progress 25 % (2 MB)
101 04:43:29.776609 progress 30 % (2 MB)
102 04:43:29.802630 progress 35 % (2 MB)
103 04:43:29.828141 progress 40 % (3 MB)
104 04:43:29.854023 progress 45 % (3 MB)
105 04:43:29.882189 progress 50 % (4 MB)
106 04:43:29.908741 progress 55 % (4 MB)
107 04:43:29.937257 progress 60 % (4 MB)
108 04:43:29.965197 progress 65 % (5 MB)
109 04:43:29.992454 progress 70 % (5 MB)
110 04:43:30.017823 progress 75 % (6 MB)
111 04:43:30.047207 progress 80 % (6 MB)
112 04:43:30.075565 progress 85 % (7 MB)
113 04:43:30.107241 progress 90 % (7 MB)
114 04:43:30.141854 progress 95 % (7 MB)
115 04:43:30.171541 progress 100 % (8 MB)
116 04:43:30.177613 8 MB downloaded in 0.55 s (14.85 MB/s)
117 04:43:30.177895 end: 1.4.1 http-download (duration 00:00:01) [common]
119 04:43:30.178171 end: 1.4 download-retry (duration 00:00:01) [common]
120 04:43:30.178265 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 04:43:30.178422 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 04:43:30.178544 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:43:30.178635 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 04:43:30.178905 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe
125 04:43:30.179058 makedir: /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin
126 04:43:30.179179 makedir: /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/tests
127 04:43:30.179314 makedir: /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/results
128 04:43:30.179465 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-add-keys
129 04:43:30.179645 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-add-sources
130 04:43:30.179782 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-background-process-start
131 04:43:30.179917 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-background-process-stop
132 04:43:30.180074 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-common-functions
133 04:43:30.180237 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-echo-ipv4
134 04:43:30.180410 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-install-packages
135 04:43:30.180591 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-installed-packages
136 04:43:30.180733 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-os-build
137 04:43:30.180869 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-probe-channel
138 04:43:30.180997 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-probe-ip
139 04:43:30.181127 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-target-ip
140 04:43:30.181259 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-target-mac
141 04:43:30.181388 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-target-storage
142 04:43:30.181523 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-test-case
143 04:43:30.181658 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-test-event
144 04:43:30.181787 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-test-feedback
145 04:43:30.181917 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-test-raise
146 04:43:30.182047 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-test-reference
147 04:43:30.182222 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-test-runner
148 04:43:30.182386 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-test-set
149 04:43:30.182523 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-test-shell
150 04:43:30.182657 Updating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-install-packages (oe)
151 04:43:30.182813 Updating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/bin/lava-installed-packages (oe)
152 04:43:30.182950 Creating /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/environment
153 04:43:30.183088 LAVA metadata
154 04:43:30.183194 - LAVA_JOB_ID=12699833
155 04:43:30.183291 - LAVA_DISPATCHER_IP=192.168.201.1
156 04:43:30.183428 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 04:43:30.183498 skipped lava-vland-overlay
158 04:43:30.183574 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 04:43:30.183658 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 04:43:30.183722 skipped lava-multinode-overlay
161 04:43:30.183819 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 04:43:30.183945 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 04:43:30.184083 Loading test definitions
164 04:43:30.184216 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 04:43:30.184328 Using /lava-12699833 at stage 0
166 04:43:30.184671 uuid=12699833_1.5.2.3.1 testdef=None
167 04:43:30.184763 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 04:43:30.184849 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 04:43:30.185412 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 04:43:30.185729 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 04:43:30.186405 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 04:43:30.186637 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 04:43:30.187499 runner path: /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/0/tests/0_dmesg test_uuid 12699833_1.5.2.3.1
176 04:43:30.187668 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 04:43:30.187902 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 04:43:30.187977 Using /lava-12699833 at stage 1
180 04:43:30.188372 uuid=12699833_1.5.2.3.5 testdef=None
181 04:43:30.188467 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 04:43:30.188554 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 04:43:30.189106 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 04:43:30.189349 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 04:43:30.190529 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 04:43:30.190881 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 04:43:30.191716 runner path: /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/1/tests/1_bootrr test_uuid 12699833_1.5.2.3.5
190 04:43:30.191873 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 04:43:30.192218 Creating lava-test-runner.conf files
193 04:43:30.192324 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/0 for stage 0
194 04:43:30.192461 - 0_dmesg
195 04:43:30.192570 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12699833/lava-overlay-eismpzhe/lava-12699833/1 for stage 1
196 04:43:30.192668 - 1_bootrr
197 04:43:30.192770 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 04:43:30.192861 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 04:43:30.202296 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 04:43:30.202434 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 04:43:30.202527 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 04:43:30.202615 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 04:43:30.202707 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 04:43:30.459050 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 04:43:30.459483 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 04:43:30.459630 extracting modules file /var/lib/lava/dispatcher/tmp/12699833/tftp-deploy-7_8yyls4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699833/extract-overlay-ramdisk-3uzju5v2/ramdisk
207 04:43:30.694333 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 04:43:30.694511 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 04:43:30.694639 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699833/compress-overlay-61e_ryzz/overlay-1.5.2.4.tar.gz to ramdisk
210 04:43:30.694743 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699833/compress-overlay-61e_ryzz/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12699833/extract-overlay-ramdisk-3uzju5v2/ramdisk
211 04:43:30.704142 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 04:43:30.704333 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 04:43:30.704437 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 04:43:30.704529 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 04:43:30.704614 Building ramdisk /var/lib/lava/dispatcher/tmp/12699833/extract-overlay-ramdisk-3uzju5v2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12699833/extract-overlay-ramdisk-3uzju5v2/ramdisk
216 04:43:31.109126 >> 145349 blocks
217 04:43:33.502198 rename /var/lib/lava/dispatcher/tmp/12699833/extract-overlay-ramdisk-3uzju5v2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12699833/tftp-deploy-7_8yyls4/ramdisk/ramdisk.cpio.gz
218 04:43:33.502742 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 04:43:33.502900 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 04:43:33.503060 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 04:43:33.503236 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12699833/tftp-deploy-7_8yyls4/kernel/Image'
222 04:43:48.275096 Returned 0 in 14 seconds
223 04:43:48.375735 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12699833/tftp-deploy-7_8yyls4/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12699833/tftp-deploy-7_8yyls4/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12699833/tftp-deploy-7_8yyls4/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12699833/tftp-deploy-7_8yyls4/kernel/image.itb
224 04:43:48.785740 output: FIT description: Kernel Image image with one or more FDT blobs
225 04:43:48.786178 output: Created: Sun Feb 4 04:43:48 2024
226 04:43:48.786301 output: Image 0 (kernel-1)
227 04:43:48.786392 output: Description:
228 04:43:48.786478 output: Created: Sun Feb 4 04:43:48 2024
229 04:43:48.786563 output: Type: Kernel Image
230 04:43:48.786667 output: Compression: lzma compressed
231 04:43:48.786778 output: Data Size: 12048508 Bytes = 11766.12 KiB = 11.49 MiB
232 04:43:48.786884 output: Architecture: AArch64
233 04:43:48.786990 output: OS: Linux
234 04:43:48.787097 output: Load Address: 0x00000000
235 04:43:48.787205 output: Entry Point: 0x00000000
236 04:43:48.787287 output: Hash algo: crc32
237 04:43:48.787369 output: Hash value: 3b31d50c
238 04:43:48.787450 output: Image 1 (fdt-1)
239 04:43:48.787551 output: Description: mt8192-asurada-spherion-r0
240 04:43:48.787649 output: Created: Sun Feb 4 04:43:48 2024
241 04:43:48.787746 output: Type: Flat Device Tree
242 04:43:48.787843 output: Compression: uncompressed
243 04:43:48.787944 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 04:43:48.788041 output: Architecture: AArch64
245 04:43:48.788137 output: Hash algo: crc32
246 04:43:48.788233 output: Hash value: cc4352de
247 04:43:48.788344 output: Image 2 (ramdisk-1)
248 04:43:48.788443 output: Description: unavailable
249 04:43:48.788540 output: Created: Sun Feb 4 04:43:48 2024
250 04:43:48.788638 output: Type: RAMDisk Image
251 04:43:48.788735 output: Compression: Unknown Compression
252 04:43:48.788832 output: Data Size: 21410577 Bytes = 20908.77 KiB = 20.42 MiB
253 04:43:48.788928 output: Architecture: AArch64
254 04:43:48.789024 output: OS: Linux
255 04:43:48.789119 output: Load Address: unavailable
256 04:43:48.789214 output: Entry Point: unavailable
257 04:43:48.789309 output: Hash algo: crc32
258 04:43:48.789421 output: Hash value: a4b58e6a
259 04:43:48.789515 output: Default Configuration: 'conf-1'
260 04:43:48.789609 output: Configuration 0 (conf-1)
261 04:43:48.789701 output: Description: mt8192-asurada-spherion-r0
262 04:43:48.789797 output: Kernel: kernel-1
263 04:43:48.789886 output: Init Ramdisk: ramdisk-1
264 04:43:48.789961 output: FDT: fdt-1
265 04:43:48.790022 output: Loadables: kernel-1
266 04:43:48.790080 output:
267 04:43:48.790293 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
268 04:43:48.790399 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
269 04:43:48.790506 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
270 04:43:48.790610 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
271 04:43:48.790720 No LXC device requested
272 04:43:48.790837 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 04:43:48.790967 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
274 04:43:48.791085 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 04:43:48.791207 Checking files for TFTP limit of 4294967296 bytes.
276 04:43:48.791874 end: 1 tftp-deploy (duration 00:00:20) [common]
277 04:43:48.792002 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 04:43:48.792138 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 04:43:48.792331 substitutions:
280 04:43:48.792434 - {DTB}: 12699833/tftp-deploy-7_8yyls4/dtb/mt8192-asurada-spherion-r0.dtb
281 04:43:48.792539 - {INITRD}: 12699833/tftp-deploy-7_8yyls4/ramdisk/ramdisk.cpio.gz
282 04:43:48.792641 - {KERNEL}: 12699833/tftp-deploy-7_8yyls4/kernel/Image
283 04:43:48.792742 - {LAVA_MAC}: None
284 04:43:48.792851 - {PRESEED_CONFIG}: None
285 04:43:48.792954 - {PRESEED_LOCAL}: None
286 04:43:48.793047 - {RAMDISK}: 12699833/tftp-deploy-7_8yyls4/ramdisk/ramdisk.cpio.gz
287 04:43:48.793152 - {ROOT_PART}: None
288 04:43:48.793254 - {ROOT}: None
289 04:43:48.793360 - {SERVER_IP}: 192.168.201.1
290 04:43:48.793451 - {TEE}: None
291 04:43:48.793540 Parsed boot commands:
292 04:43:48.793627 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 04:43:48.793869 Parsed boot commands: tftpboot 192.168.201.1 12699833/tftp-deploy-7_8yyls4/kernel/image.itb 12699833/tftp-deploy-7_8yyls4/kernel/cmdline
294 04:43:48.793996 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 04:43:48.794115 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 04:43:48.794242 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 04:43:48.794359 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 04:43:48.794464 Not connected, no need to disconnect.
299 04:43:48.794572 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 04:43:48.794689 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 04:43:48.794786 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
302 04:43:48.799074 Setting prompt string to ['lava-test: # ']
303 04:43:48.799556 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 04:43:48.799715 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 04:43:48.799853 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 04:43:48.800186 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 04:43:48.800556 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
308 04:43:53.935701 >> Command sent successfully.
309 04:43:53.938332 Returned 0 in 5 seconds
310 04:43:54.038739 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 04:43:54.039071 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 04:43:54.039171 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 04:43:54.039262 Setting prompt string to 'Starting depthcharge on Spherion...'
315 04:43:54.039333 Changing prompt to 'Starting depthcharge on Spherion...'
316 04:43:54.039452 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 04:43:54.039785 [Enter `^Ec?' for help]
318 04:43:54.209960
319 04:43:54.210109
320 04:43:54.210179 F0: 102B 0000
321 04:43:54.210244
322 04:43:54.210307 F3: 1001 0000 [0200]
323 04:43:54.212843
324 04:43:54.212945 F3: 1001 0000
325 04:43:54.213013
326 04:43:54.213076 F7: 102D 0000
327 04:43:54.213137
328 04:43:54.216641 F1: 0000 0000
329 04:43:54.216726
330 04:43:54.216793 V0: 0000 0000 [0001]
331 04:43:54.216858
332 04:43:54.219548 00: 0007 8000
333 04:43:54.219636
334 04:43:54.219702 01: 0000 0000
335 04:43:54.219765
336 04:43:54.223283 BP: 0C00 0209 [0000]
337 04:43:54.223367
338 04:43:54.223433 G0: 1182 0000
339 04:43:54.223494
340 04:43:54.226234 EC: 0000 0021 [4000]
341 04:43:54.226318
342 04:43:54.226384 S7: 0000 0000 [0000]
343 04:43:54.226446
344 04:43:54.230448 CC: 0000 0000 [0001]
345 04:43:54.230534
346 04:43:54.230600 T0: 0000 0040 [010F]
347 04:43:54.230662
348 04:43:54.230720 Jump to BL
349 04:43:54.230778
350 04:43:54.257052
351 04:43:54.257201
352 04:43:54.257266
353 04:43:54.264652 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 04:43:54.268894 ARM64: Exception handlers installed.
355 04:43:54.272360 ARM64: Testing exception
356 04:43:54.272451 ARM64: Done test exception
357 04:43:54.282125 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 04:43:54.292127 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 04:43:54.298835 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 04:43:54.309068 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 04:43:54.315770 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 04:43:54.322329 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 04:43:54.333409 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 04:43:54.340541 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 04:43:54.359378 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 04:43:54.362771 WDT: Last reset was cold boot
367 04:43:54.366171 SPI1(PAD0) initialized at 2873684 Hz
368 04:43:54.369502 SPI5(PAD0) initialized at 992727 Hz
369 04:43:54.372998 VBOOT: Loading verstage.
370 04:43:54.379341 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 04:43:54.382762 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 04:43:54.386092 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 04:43:54.389468 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 04:43:54.397244 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 04:43:54.403556 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 04:43:54.414495 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 04:43:54.414638
378 04:43:54.414709
379 04:43:54.425496 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 04:43:54.428848 ARM64: Exception handlers installed.
381 04:43:54.431733 ARM64: Testing exception
382 04:43:54.431833 ARM64: Done test exception
383 04:43:54.438367 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 04:43:54.441859 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 04:43:54.455959 Probing TPM: . done!
386 04:43:54.456091 TPM ready after 0 ms
387 04:43:54.463569 Connected to device vid:did:rid of 1ae0:0028:00
388 04:43:54.470579 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
389 04:43:54.529894 Initialized TPM device CR50 revision 0
390 04:43:54.540904 tlcl_send_startup: Startup return code is 0
391 04:43:54.541161 TPM: setup succeeded
392 04:43:54.552313 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 04:43:54.561107 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 04:43:54.572951 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 04:43:54.583279 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 04:43:54.587380 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 04:43:54.591015 in-header: 03 07 00 00 08 00 00 00
398 04:43:54.594344 in-data: aa e4 47 04 13 02 00 00
399 04:43:54.598007 Chrome EC: UHEPI supported
400 04:43:54.601944 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 04:43:54.606014 in-header: 03 95 00 00 08 00 00 00
402 04:43:54.609861 in-data: 18 20 20 08 00 00 00 00
403 04:43:54.609983 Phase 1
404 04:43:54.613797 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 04:43:54.620583 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 04:43:54.628695 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 04:43:54.628816 Recovery requested (1009000e)
408 04:43:54.641077 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 04:43:54.645159 tlcl_extend: response is 0
410 04:43:54.653615 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 04:43:54.659118 tlcl_extend: response is 0
412 04:43:54.665434 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 04:43:54.685682 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
414 04:43:54.692411 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 04:43:54.692535
416 04:43:54.692616
417 04:43:54.702725 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 04:43:54.706008 ARM64: Exception handlers installed.
419 04:43:54.709101 ARM64: Testing exception
420 04:43:54.709233 ARM64: Done test exception
421 04:43:54.731430 pmic_efuse_setting: Set efuses in 11 msecs
422 04:43:54.734765 pmwrap_interface_init: Select PMIF_VLD_RDY
423 04:43:54.741851 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 04:43:54.744931 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 04:43:54.752496 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 04:43:54.755826 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 04:43:54.759974 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 04:43:54.763436 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 04:43:54.770558 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 04:43:54.774262 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 04:43:54.777925 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 04:43:54.785313 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 04:43:54.789439 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 04:43:54.792947 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 04:43:54.796335 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 04:43:54.804534 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 04:43:54.807934 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 04:43:54.815408 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 04:43:54.819491 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 04:43:54.826922 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 04:43:54.831164 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 04:43:54.838259 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 04:43:54.842322 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 04:43:54.849616 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 04:43:54.853248 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 04:43:54.861030 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 04:43:54.864973 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 04:43:54.871927 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 04:43:54.876106 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 04:43:54.879541 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 04:43:54.887069 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 04:43:54.890938 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 04:43:54.894795 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 04:43:54.901445 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 04:43:54.905434 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 04:43:54.909326 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 04:43:54.916319 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 04:43:54.920339 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 04:43:54.927627 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 04:43:54.931754 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 04:43:54.935281 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 04:43:54.939363 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 04:43:54.942886 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 04:43:54.950421 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 04:43:54.953862 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 04:43:54.957343 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 04:43:54.960803 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 04:43:54.965037 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 04:43:54.968372 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 04:43:54.975949 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 04:43:54.979177 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 04:43:54.982845 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 04:43:54.986357 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 04:43:54.994518 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 04:43:55.001664 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 04:43:55.009104 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 04:43:55.015998 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 04:43:55.024165 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 04:43:55.027723 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 04:43:55.035773 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 04:43:55.039148 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 04:43:55.046595 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x34
483 04:43:55.050026 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 04:43:55.054144 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 04:43:55.057586 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 04:43:55.069198 [RTC]rtc_get_frequency_meter,154: input=15, output=759
487 04:43:55.078248 [RTC]rtc_get_frequency_meter,154: input=23, output=942
488 04:43:55.087960 [RTC]rtc_get_frequency_meter,154: input=19, output=851
489 04:43:55.097435 [RTC]rtc_get_frequency_meter,154: input=17, output=804
490 04:43:55.107235 [RTC]rtc_get_frequency_meter,154: input=16, output=782
491 04:43:55.116884 [RTC]rtc_get_frequency_meter,154: input=16, output=781
492 04:43:55.127264 [RTC]rtc_get_frequency_meter,154: input=17, output=805
493 04:43:55.130895 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
494 04:43:55.134808 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
495 04:43:55.138245 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 04:43:55.142442 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 04:43:55.150431 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 04:43:55.153736 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 04:43:55.153830 ADC[4]: Raw value=906203 ID=7
500 04:43:55.157322 ADC[3]: Raw value=213810 ID=1
501 04:43:55.157415 RAM Code: 0x71
502 04:43:55.164972 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 04:43:55.168282 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 04:43:55.175984 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 04:43:55.183608 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 04:43:55.187029 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 04:43:55.191188 in-header: 03 07 00 00 08 00 00 00
508 04:43:55.194816 in-data: aa e4 47 04 13 02 00 00
509 04:43:55.198892 Chrome EC: UHEPI supported
510 04:43:55.206629 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 04:43:55.206727 in-header: 03 95 00 00 08 00 00 00
512 04:43:55.210019 in-data: 18 20 20 08 00 00 00 00
513 04:43:55.213873 MRC: failed to locate region type 0.
514 04:43:55.221583 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 04:43:55.225055 DRAM-K: Running full calibration
516 04:43:55.231968 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 04:43:55.232108 header.status = 0x0
518 04:43:55.235953 header.version = 0x6 (expected: 0x6)
519 04:43:55.239899 header.size = 0xd00 (expected: 0xd00)
520 04:43:55.239989 header.flags = 0x0
521 04:43:55.246400 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 04:43:55.264638 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
523 04:43:55.271706 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 04:43:55.275548 dram_init: ddr_geometry: 2
525 04:43:55.275686 [EMI] MDL number = 2
526 04:43:55.278775 [EMI] Get MDL freq = 0
527 04:43:55.278867 dram_init: ddr_type: 0
528 04:43:55.282770 is_discrete_lpddr4: 1
529 04:43:55.286387 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 04:43:55.286480
531 04:43:55.286548
532 04:43:55.290052 [Bian_co] ETT version 0.0.0.1
533 04:43:55.294161 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 04:43:55.294239
535 04:43:55.297595 dramc_set_vcore_voltage set vcore to 650000
536 04:43:55.297679 Read voltage for 800, 4
537 04:43:55.300910 Vio18 = 0
538 04:43:55.301040 Vcore = 650000
539 04:43:55.301105 Vdram = 0
540 04:43:55.304963 Vddq = 0
541 04:43:55.305047 Vmddr = 0
542 04:43:55.305114 dram_init: config_dvfs: 1
543 04:43:55.312684 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 04:43:55.316061 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 04:43:55.320085 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
546 04:43:55.323465 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
547 04:43:55.327288 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
548 04:43:55.331757 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
549 04:43:55.335077 MEM_TYPE=3, freq_sel=18
550 04:43:55.338547 sv_algorithm_assistance_LP4_1600
551 04:43:55.341228 ============ PULL DRAM RESETB DOWN ============
552 04:43:55.344749 ========== PULL DRAM RESETB DOWN end =========
553 04:43:55.351771 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 04:43:55.355171 ===================================
555 04:43:55.355287 LPDDR4 DRAM CONFIGURATION
556 04:43:55.358641 ===================================
557 04:43:55.362711 EX_ROW_EN[0] = 0x0
558 04:43:55.362821 EX_ROW_EN[1] = 0x0
559 04:43:55.366062 LP4Y_EN = 0x0
560 04:43:55.366147 WORK_FSP = 0x0
561 04:43:55.369875 WL = 0x2
562 04:43:55.369960 RL = 0x2
563 04:43:55.373417 BL = 0x2
564 04:43:55.373501 RPST = 0x0
565 04:43:55.377141 RD_PRE = 0x0
566 04:43:55.377232 WR_PRE = 0x1
567 04:43:55.377313 WR_PST = 0x0
568 04:43:55.380522 DBI_WR = 0x0
569 04:43:55.383900 DBI_RD = 0x0
570 04:43:55.384013 OTF = 0x1
571 04:43:55.387231 ===================================
572 04:43:55.390703 ===================================
573 04:43:55.390813 ANA top config
574 04:43:55.393708 ===================================
575 04:43:55.396974 DLL_ASYNC_EN = 0
576 04:43:55.400067 ALL_SLAVE_EN = 1
577 04:43:55.404015 NEW_RANK_MODE = 1
578 04:43:55.404104 DLL_IDLE_MODE = 1
579 04:43:55.406922 LP45_APHY_COMB_EN = 1
580 04:43:55.410241 TX_ODT_DIS = 1
581 04:43:55.413920 NEW_8X_MODE = 1
582 04:43:55.417592 ===================================
583 04:43:55.421382 ===================================
584 04:43:55.421523 data_rate = 1600
585 04:43:55.424739 CKR = 1
586 04:43:55.428161 DQ_P2S_RATIO = 8
587 04:43:55.430962 ===================================
588 04:43:55.434330 CA_P2S_RATIO = 8
589 04:43:55.437620 DQ_CA_OPEN = 0
590 04:43:55.441440 DQ_SEMI_OPEN = 0
591 04:43:55.441529 CA_SEMI_OPEN = 0
592 04:43:55.444687 CA_FULL_RATE = 0
593 04:43:55.448055 DQ_CKDIV4_EN = 1
594 04:43:55.450921 CA_CKDIV4_EN = 1
595 04:43:55.454280 CA_PREDIV_EN = 0
596 04:43:55.457703 PH8_DLY = 0
597 04:43:55.457783 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 04:43:55.461177 DQ_AAMCK_DIV = 4
599 04:43:55.464741 CA_AAMCK_DIV = 4
600 04:43:55.468111 CA_ADMCK_DIV = 4
601 04:43:55.471638 DQ_TRACK_CA_EN = 0
602 04:43:55.474381 CA_PICK = 800
603 04:43:55.474456 CA_MCKIO = 800
604 04:43:55.477863 MCKIO_SEMI = 0
605 04:43:55.482319 PLL_FREQ = 3068
606 04:43:55.485709 DQ_UI_PI_RATIO = 32
607 04:43:55.485794 CA_UI_PI_RATIO = 0
608 04:43:55.489684 ===================================
609 04:43:55.493309 ===================================
610 04:43:55.497310 memory_type:LPDDR4
611 04:43:55.497406 GP_NUM : 10
612 04:43:55.500727 SRAM_EN : 1
613 04:43:55.500812 MD32_EN : 0
614 04:43:55.504769 ===================================
615 04:43:55.508093 [ANA_INIT] >>>>>>>>>>>>>>
616 04:43:55.512099 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 04:43:55.515562 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 04:43:55.518970 ===================================
619 04:43:55.519059 data_rate = 1600,PCW = 0X7600
620 04:43:55.522239 ===================================
621 04:43:55.528755 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 04:43:55.531859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 04:43:55.538602 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 04:43:55.542195 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 04:43:55.545631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 04:43:55.548932 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 04:43:55.552091 [ANA_INIT] flow start
628 04:43:55.555664 [ANA_INIT] PLL >>>>>>>>
629 04:43:55.555751 [ANA_INIT] PLL <<<<<<<<
630 04:43:55.558819 [ANA_INIT] MIDPI >>>>>>>>
631 04:43:55.562275 [ANA_INIT] MIDPI <<<<<<<<
632 04:43:55.562363 [ANA_INIT] DLL >>>>>>>>
633 04:43:55.565734 [ANA_INIT] flow end
634 04:43:55.569203 ============ LP4 DIFF to SE enter ============
635 04:43:55.572071 ============ LP4 DIFF to SE exit ============
636 04:43:55.575403 [ANA_INIT] <<<<<<<<<<<<<
637 04:43:55.578796 [Flow] Enable top DCM control >>>>>
638 04:43:55.582204 [Flow] Enable top DCM control <<<<<
639 04:43:55.585611 Enable DLL master slave shuffle
640 04:43:55.592467 ==============================================================
641 04:43:55.592555 Gating Mode config
642 04:43:55.599124 ==============================================================
643 04:43:55.599224 Config description:
644 04:43:55.608603 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 04:43:55.615782 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 04:43:55.622491 SELPH_MODE 0: By rank 1: By Phase
647 04:43:55.625852 ==============================================================
648 04:43:55.629264 GAT_TRACK_EN = 1
649 04:43:55.631980 RX_GATING_MODE = 2
650 04:43:55.635434 RX_GATING_TRACK_MODE = 2
651 04:43:55.638844 SELPH_MODE = 1
652 04:43:55.642216 PICG_EARLY_EN = 1
653 04:43:55.645446 VALID_LAT_VALUE = 1
654 04:43:55.648798 ==============================================================
655 04:43:55.652202 Enter into Gating configuration >>>>
656 04:43:55.655280 Exit from Gating configuration <<<<
657 04:43:55.658695 Enter into DVFS_PRE_config >>>>>
658 04:43:55.672391 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 04:43:55.675515 Exit from DVFS_PRE_config <<<<<
660 04:43:55.675628 Enter into PICG configuration >>>>
661 04:43:55.678651 Exit from PICG configuration <<<<
662 04:43:55.682163 [RX_INPUT] configuration >>>>>
663 04:43:55.685695 [RX_INPUT] configuration <<<<<
664 04:43:55.692590 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 04:43:55.695530 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 04:43:55.702190 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 04:43:55.709062 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 04:43:55.715909 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 04:43:55.722621 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 04:43:55.725763 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 04:43:55.728876 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 04:43:55.732070 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 04:43:55.738903 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 04:43:55.742369 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 04:43:55.745835 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 04:43:55.749167 ===================================
677 04:43:55.752007 LPDDR4 DRAM CONFIGURATION
678 04:43:55.755549 ===================================
679 04:43:55.755637 EX_ROW_EN[0] = 0x0
680 04:43:55.758960 EX_ROW_EN[1] = 0x0
681 04:43:55.762279 LP4Y_EN = 0x0
682 04:43:55.762369 WORK_FSP = 0x0
683 04:43:55.765702 WL = 0x2
684 04:43:55.765801 RL = 0x2
685 04:43:55.769187 BL = 0x2
686 04:43:55.769273 RPST = 0x0
687 04:43:55.771964 RD_PRE = 0x0
688 04:43:55.772050 WR_PRE = 0x1
689 04:43:55.775281 WR_PST = 0x0
690 04:43:55.775367 DBI_WR = 0x0
691 04:43:55.779128 DBI_RD = 0x0
692 04:43:55.779213 OTF = 0x1
693 04:43:55.782177 ===================================
694 04:43:55.785357 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 04:43:55.791949 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 04:43:55.795309 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 04:43:55.798712 ===================================
698 04:43:55.802282 LPDDR4 DRAM CONFIGURATION
699 04:43:55.805443 ===================================
700 04:43:55.805537 EX_ROW_EN[0] = 0x10
701 04:43:55.809097 EX_ROW_EN[1] = 0x0
702 04:43:55.809184 LP4Y_EN = 0x0
703 04:43:55.812128 WORK_FSP = 0x0
704 04:43:55.812242 WL = 0x2
705 04:43:55.815482 RL = 0x2
706 04:43:55.819099 BL = 0x2
707 04:43:55.819198 RPST = 0x0
708 04:43:55.821870 RD_PRE = 0x0
709 04:43:55.821961 WR_PRE = 0x1
710 04:43:55.825314 WR_PST = 0x0
711 04:43:55.825432 DBI_WR = 0x0
712 04:43:55.828733 DBI_RD = 0x0
713 04:43:55.828819 OTF = 0x1
714 04:43:55.832179 ===================================
715 04:43:55.838886 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 04:43:55.842661 nWR fixed to 40
717 04:43:55.845862 [ModeRegInit_LP4] CH0 RK0
718 04:43:55.845959 [ModeRegInit_LP4] CH0 RK1
719 04:43:55.849330 [ModeRegInit_LP4] CH1 RK0
720 04:43:55.852687 [ModeRegInit_LP4] CH1 RK1
721 04:43:55.852784 match AC timing 13
722 04:43:55.859602 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 04:43:55.863019 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 04:43:55.866334 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 04:43:55.873070 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 04:43:55.876585 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 04:43:55.876679 [EMI DOE] emi_dcm 0
728 04:43:55.882765 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 04:43:55.882855 ==
730 04:43:55.886158 Dram Type= 6, Freq= 0, CH_0, rank 0
731 04:43:55.889677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 04:43:55.889768 ==
733 04:43:55.896442 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 04:43:55.899186 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 04:43:55.910090 [CA 0] Center 36 (6~67) winsize 62
736 04:43:55.913291 [CA 1] Center 36 (6~67) winsize 62
737 04:43:55.916485 [CA 2] Center 34 (4~65) winsize 62
738 04:43:55.919710 [CA 3] Center 33 (3~64) winsize 62
739 04:43:55.923202 [CA 4] Center 33 (2~64) winsize 63
740 04:43:55.926608 [CA 5] Center 32 (2~62) winsize 61
741 04:43:55.926706
742 04:43:55.929906 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 04:43:55.929996
744 04:43:55.933252 [CATrainingPosCal] consider 1 rank data
745 04:43:55.936564 u2DelayCellTimex100 = 270/100 ps
746 04:43:55.939927 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
747 04:43:55.943662 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
748 04:43:55.950439 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
749 04:43:55.953836 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
750 04:43:55.957003 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
751 04:43:55.960139 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
752 04:43:55.960260
753 04:43:55.963510 CA PerBit enable=1, Macro0, CA PI delay=32
754 04:43:55.963603
755 04:43:55.966989 [CBTSetCACLKResult] CA Dly = 32
756 04:43:55.967078 CS Dly: 4 (0~35)
757 04:43:55.967169 ==
758 04:43:55.970423 Dram Type= 6, Freq= 0, CH_0, rank 1
759 04:43:55.976523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 04:43:55.976614 ==
761 04:43:55.979984 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 04:43:55.986924 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 04:43:55.996558 [CA 0] Center 36 (6~67) winsize 62
764 04:43:55.999247 [CA 1] Center 36 (6~67) winsize 62
765 04:43:56.002713 [CA 2] Center 34 (4~65) winsize 62
766 04:43:56.006115 [CA 3] Center 33 (3~64) winsize 62
767 04:43:56.009639 [CA 4] Center 32 (2~63) winsize 62
768 04:43:56.012877 [CA 5] Center 32 (2~63) winsize 62
769 04:43:56.012972
770 04:43:56.016359 [CmdBusTrainingLP45] Vref(ca) range 1: 32
771 04:43:56.016452
772 04:43:56.019871 [CATrainingPosCal] consider 2 rank data
773 04:43:56.022658 u2DelayCellTimex100 = 270/100 ps
774 04:43:56.026084 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
775 04:43:56.029460 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
776 04:43:56.036214 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
777 04:43:56.039326 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
778 04:43:56.042642 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
779 04:43:56.045931 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
780 04:43:56.046028
781 04:43:56.050035 CA PerBit enable=1, Macro0, CA PI delay=32
782 04:43:56.050157
783 04:43:56.053040 [CBTSetCACLKResult] CA Dly = 32
784 04:43:56.053124 CS Dly: 5 (0~37)
785 04:43:56.053210
786 04:43:56.056536 ----->DramcWriteLeveling(PI) begin...
787 04:43:56.056639 ==
788 04:43:56.060018 Dram Type= 6, Freq= 0, CH_0, rank 0
789 04:43:56.064076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 04:43:56.067203 ==
791 04:43:56.067324 Write leveling (Byte 0): 33 => 33
792 04:43:56.071237 Write leveling (Byte 1): 33 => 33
793 04:43:56.074666 DramcWriteLeveling(PI) end<-----
794 04:43:56.074762
795 04:43:56.074854 ==
796 04:43:56.078207 Dram Type= 6, Freq= 0, CH_0, rank 0
797 04:43:56.081366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 04:43:56.081480 ==
799 04:43:56.085014 [Gating] SW mode calibration
800 04:43:56.092531 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 04:43:56.098797 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 04:43:56.102305 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 04:43:56.105688 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
804 04:43:56.109052 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
805 04:43:56.116029 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 04:43:56.119451 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 04:43:56.122280 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 04:43:56.129096 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 04:43:56.132641 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 04:43:56.136154 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 04:43:56.142439 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 04:43:56.145845 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 04:43:56.149089 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 04:43:56.156097 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 04:43:56.159470 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 04:43:56.162937 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 04:43:56.169742 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 04:43:56.173063 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 04:43:56.175739 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 04:43:56.183128 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
821 04:43:56.186333 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 04:43:56.189562 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 04:43:56.192620 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 04:43:56.199247 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 04:43:56.202361 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 04:43:56.206081 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 04:43:56.212655 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 04:43:56.215906 0 9 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
829 04:43:56.219430 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
830 04:43:56.225930 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 04:43:56.229371 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 04:43:56.232816 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 04:43:56.238988 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 04:43:56.242545 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 04:43:56.246051 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
836 04:43:56.252814 0 10 8 | B1->B0 | 3030 2525 | 0 0 | (0 1) (0 0)
837 04:43:56.256046 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 04:43:56.259634 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 04:43:56.266318 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 04:43:56.269168 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 04:43:56.272391 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 04:43:56.279389 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 04:43:56.282869 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 04:43:56.286181 0 11 8 | B1->B0 | 2d2d 3e3e | 0 0 | (0 0) (0 0)
845 04:43:56.289275 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
846 04:43:56.296141 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 04:43:56.299494 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 04:43:56.303311 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 04:43:56.310006 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 04:43:56.313172 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 04:43:56.316598 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
852 04:43:56.323222 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
853 04:43:56.326308 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
854 04:43:56.329843 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 04:43:56.333472 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 04:43:56.340203 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 04:43:56.343203 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 04:43:56.346738 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 04:43:56.353496 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 04:43:56.356858 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 04:43:56.360184 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 04:43:56.367098 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 04:43:56.370385 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 04:43:56.373806 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 04:43:56.379965 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 04:43:56.383431 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 04:43:56.387012 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 04:43:56.393729 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
869 04:43:56.393830 Total UI for P1: 0, mck2ui 16
870 04:43:56.396947 best dqsien dly found for B0: ( 0, 14, 4)
871 04:43:56.403708 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 04:43:56.407233 Total UI for P1: 0, mck2ui 16
873 04:43:56.411136 best dqsien dly found for B1: ( 0, 14, 8)
874 04:43:56.414569 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
875 04:43:56.417990 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
876 04:43:56.418089
877 04:43:56.420850 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
878 04:43:56.424208 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
879 04:43:56.427703 [Gating] SW calibration Done
880 04:43:56.427792 ==
881 04:43:56.431102 Dram Type= 6, Freq= 0, CH_0, rank 0
882 04:43:56.434427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 04:43:56.434521 ==
884 04:43:56.434589 RX Vref Scan: 0
885 04:43:56.437935
886 04:43:56.438021 RX Vref 0 -> 0, step: 1
887 04:43:56.438089
888 04:43:56.441369 RX Delay -130 -> 252, step: 16
889 04:43:56.444652 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
890 04:43:56.447830 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
891 04:43:56.454481 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
892 04:43:56.457683 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
893 04:43:56.461332 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
894 04:43:56.464267 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
895 04:43:56.467825 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
896 04:43:56.474354 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
897 04:43:56.477967 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
898 04:43:56.481168 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
899 04:43:56.485068 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
900 04:43:56.487880 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
901 04:43:56.491666 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
902 04:43:56.498358 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
903 04:43:56.501634 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
904 04:43:56.504786 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
905 04:43:56.504876 ==
906 04:43:56.508197 Dram Type= 6, Freq= 0, CH_0, rank 0
907 04:43:56.511656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 04:43:56.515098 ==
909 04:43:56.515188 DQS Delay:
910 04:43:56.515274 DQS0 = 0, DQS1 = 0
911 04:43:56.518304 DQM Delay:
912 04:43:56.518423 DQM0 = 88, DQM1 = 82
913 04:43:56.518525 DQ Delay:
914 04:43:56.521428 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
915 04:43:56.525188 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
916 04:43:56.528041 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
917 04:43:56.531583 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
918 04:43:56.531668
919 04:43:56.531735
920 04:43:56.534948 ==
921 04:43:56.538424 Dram Type= 6, Freq= 0, CH_0, rank 0
922 04:43:56.541824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 04:43:56.541910 ==
924 04:43:56.541978
925 04:43:56.542041
926 04:43:56.544655 TX Vref Scan disable
927 04:43:56.544740 == TX Byte 0 ==
928 04:43:56.548800 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
929 04:43:56.555253 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
930 04:43:56.555339 == TX Byte 1 ==
931 04:43:56.558497 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
932 04:43:56.565183 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
933 04:43:56.565272 ==
934 04:43:56.568683 Dram Type= 6, Freq= 0, CH_0, rank 0
935 04:43:56.571954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 04:43:56.572056 ==
937 04:43:56.584724 TX Vref=22, minBit 8, minWin=27, winSum=447
938 04:43:56.588276 TX Vref=24, minBit 8, minWin=27, winSum=451
939 04:43:56.591074 TX Vref=26, minBit 8, minWin=27, winSum=450
940 04:43:56.595003 TX Vref=28, minBit 12, minWin=27, winSum=456
941 04:43:56.597760 TX Vref=30, minBit 10, minWin=27, winSum=455
942 04:43:56.604739 TX Vref=32, minBit 10, minWin=27, winSum=450
943 04:43:56.608208 [TxChooseVref] Worse bit 12, Min win 27, Win sum 456, Final Vref 28
944 04:43:56.608298
945 04:43:56.611407 Final TX Range 1 Vref 28
946 04:43:56.611495
947 04:43:56.611562 ==
948 04:43:56.614568 Dram Type= 6, Freq= 0, CH_0, rank 0
949 04:43:56.618023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 04:43:56.621476 ==
951 04:43:56.621603
952 04:43:56.621704
953 04:43:56.621779 TX Vref Scan disable
954 04:43:56.624872 == TX Byte 0 ==
955 04:43:56.628262 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
956 04:43:56.631537 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
957 04:43:56.634956 == TX Byte 1 ==
958 04:43:56.638084 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
959 04:43:56.641554 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
960 04:43:56.645018
961 04:43:56.645102 [DATLAT]
962 04:43:56.645169 Freq=800, CH0 RK0
963 04:43:56.645231
964 04:43:56.647808 DATLAT Default: 0xa
965 04:43:56.647892 0, 0xFFFF, sum = 0
966 04:43:56.651346 1, 0xFFFF, sum = 0
967 04:43:56.651433 2, 0xFFFF, sum = 0
968 04:43:56.654863 3, 0xFFFF, sum = 0
969 04:43:56.658204 4, 0xFFFF, sum = 0
970 04:43:56.658290 5, 0xFFFF, sum = 0
971 04:43:56.661126 6, 0xFFFF, sum = 0
972 04:43:56.661212 7, 0xFFFF, sum = 0
973 04:43:56.664362 8, 0xFFFF, sum = 0
974 04:43:56.664447 9, 0x0, sum = 1
975 04:43:56.664516 10, 0x0, sum = 2
976 04:43:56.667962 11, 0x0, sum = 3
977 04:43:56.668048 12, 0x0, sum = 4
978 04:43:56.671453 best_step = 10
979 04:43:56.671537
980 04:43:56.671605 ==
981 04:43:56.674727 Dram Type= 6, Freq= 0, CH_0, rank 0
982 04:43:56.678154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 04:43:56.678240 ==
984 04:43:56.681637 RX Vref Scan: 1
985 04:43:56.681721
986 04:43:56.681789 Set Vref Range= 32 -> 127
987 04:43:56.685132
988 04:43:56.685216 RX Vref 32 -> 127, step: 1
989 04:43:56.685283
990 04:43:56.688526 RX Delay -79 -> 252, step: 8
991 04:43:56.688612
992 04:43:56.691422 Set Vref, RX VrefLevel [Byte0]: 32
993 04:43:56.694754 [Byte1]: 32
994 04:43:56.694846
995 04:43:56.698134 Set Vref, RX VrefLevel [Byte0]: 33
996 04:43:56.701293 [Byte1]: 33
997 04:43:56.705163
998 04:43:56.705247 Set Vref, RX VrefLevel [Byte0]: 34
999 04:43:56.708291 [Byte1]: 34
1000 04:43:56.712403
1001 04:43:56.712490 Set Vref, RX VrefLevel [Byte0]: 35
1002 04:43:56.715725 [Byte1]: 35
1003 04:43:56.720720
1004 04:43:56.720809 Set Vref, RX VrefLevel [Byte0]: 36
1005 04:43:56.723887 [Byte1]: 36
1006 04:43:56.727751
1007 04:43:56.727892 Set Vref, RX VrefLevel [Byte0]: 37
1008 04:43:56.731279 [Byte1]: 37
1009 04:43:56.735425
1010 04:43:56.735527 Set Vref, RX VrefLevel [Byte0]: 38
1011 04:43:56.738591 [Byte1]: 38
1012 04:43:56.742955
1013 04:43:56.743077 Set Vref, RX VrefLevel [Byte0]: 39
1014 04:43:56.746306 [Byte1]: 39
1015 04:43:56.750495
1016 04:43:56.750614 Set Vref, RX VrefLevel [Byte0]: 40
1017 04:43:56.753962 [Byte1]: 40
1018 04:43:56.758160
1019 04:43:56.758274 Set Vref, RX VrefLevel [Byte0]: 41
1020 04:43:56.761502 [Byte1]: 41
1021 04:43:56.765628
1022 04:43:56.765737 Set Vref, RX VrefLevel [Byte0]: 42
1023 04:43:56.769133 [Byte1]: 42
1024 04:43:56.773152
1025 04:43:56.773275 Set Vref, RX VrefLevel [Byte0]: 43
1026 04:43:56.776576 [Byte1]: 43
1027 04:43:56.780744
1028 04:43:56.780827 Set Vref, RX VrefLevel [Byte0]: 44
1029 04:43:56.784070 [Byte1]: 44
1030 04:43:56.788148
1031 04:43:56.788257 Set Vref, RX VrefLevel [Byte0]: 45
1032 04:43:56.791722 [Byte1]: 45
1033 04:43:56.795895
1034 04:43:56.795978 Set Vref, RX VrefLevel [Byte0]: 46
1035 04:43:56.798711 [Byte1]: 46
1036 04:43:56.803496
1037 04:43:56.803580 Set Vref, RX VrefLevel [Byte0]: 47
1038 04:43:56.806275 [Byte1]: 47
1039 04:43:56.811108
1040 04:43:56.811195 Set Vref, RX VrefLevel [Byte0]: 48
1041 04:43:56.813899 [Byte1]: 48
1042 04:43:56.818585
1043 04:43:56.818679 Set Vref, RX VrefLevel [Byte0]: 49
1044 04:43:56.821937 [Byte1]: 49
1045 04:43:56.825906
1046 04:43:56.826002 Set Vref, RX VrefLevel [Byte0]: 50
1047 04:43:56.829223 [Byte1]: 50
1048 04:43:56.833673
1049 04:43:56.833758 Set Vref, RX VrefLevel [Byte0]: 51
1050 04:43:56.836663 [Byte1]: 51
1051 04:43:56.840653
1052 04:43:56.840739 Set Vref, RX VrefLevel [Byte0]: 52
1053 04:43:56.844469 [Byte1]: 52
1054 04:43:56.848409
1055 04:43:56.848498 Set Vref, RX VrefLevel [Byte0]: 53
1056 04:43:56.852007 [Byte1]: 53
1057 04:43:56.856265
1058 04:43:56.856357 Set Vref, RX VrefLevel [Byte0]: 54
1059 04:43:56.859488 [Byte1]: 54
1060 04:43:56.863626
1061 04:43:56.863710 Set Vref, RX VrefLevel [Byte0]: 55
1062 04:43:56.866720 [Byte1]: 55
1063 04:43:56.870972
1064 04:43:56.871057 Set Vref, RX VrefLevel [Byte0]: 56
1065 04:43:56.874335 [Byte1]: 56
1066 04:43:56.879162
1067 04:43:56.879284 Set Vref, RX VrefLevel [Byte0]: 57
1068 04:43:56.881763 [Byte1]: 57
1069 04:43:56.886393
1070 04:43:56.886508 Set Vref, RX VrefLevel [Byte0]: 58
1071 04:43:56.889773 [Byte1]: 58
1072 04:43:56.893988
1073 04:43:56.894105 Set Vref, RX VrefLevel [Byte0]: 59
1074 04:43:56.897432 [Byte1]: 59
1075 04:43:56.901694
1076 04:43:56.901778 Set Vref, RX VrefLevel [Byte0]: 60
1077 04:43:56.904343 [Byte1]: 60
1078 04:43:56.909189
1079 04:43:56.909272 Set Vref, RX VrefLevel [Byte0]: 61
1080 04:43:56.911974 [Byte1]: 61
1081 04:43:56.916941
1082 04:43:56.917026 Set Vref, RX VrefLevel [Byte0]: 62
1083 04:43:56.919581 [Byte1]: 62
1084 04:43:56.924216
1085 04:43:56.924306 Set Vref, RX VrefLevel [Byte0]: 63
1086 04:43:56.927097 [Byte1]: 63
1087 04:43:56.931869
1088 04:43:56.931954 Set Vref, RX VrefLevel [Byte0]: 64
1089 04:43:56.935171 [Byte1]: 64
1090 04:43:56.939152
1091 04:43:56.939238 Set Vref, RX VrefLevel [Byte0]: 65
1092 04:43:56.942406 [Byte1]: 65
1093 04:43:56.946541
1094 04:43:56.946625 Set Vref, RX VrefLevel [Byte0]: 66
1095 04:43:56.950000 [Byte1]: 66
1096 04:43:56.953998
1097 04:43:56.954104 Set Vref, RX VrefLevel [Byte0]: 67
1098 04:43:56.957377 [Byte1]: 67
1099 04:43:56.961476
1100 04:43:56.961561 Set Vref, RX VrefLevel [Byte0]: 68
1101 04:43:56.964791 [Byte1]: 68
1102 04:43:56.968936
1103 04:43:56.969024 Set Vref, RX VrefLevel [Byte0]: 69
1104 04:43:56.972403 [Byte1]: 69
1105 04:43:56.976804
1106 04:43:56.976888 Set Vref, RX VrefLevel [Byte0]: 70
1107 04:43:56.980051 [Byte1]: 70
1108 04:43:56.984490
1109 04:43:56.984581 Set Vref, RX VrefLevel [Byte0]: 71
1110 04:43:56.987592 [Byte1]: 71
1111 04:43:56.991948
1112 04:43:56.992032 Set Vref, RX VrefLevel [Byte0]: 72
1113 04:43:56.995374 [Byte1]: 72
1114 04:43:56.999325
1115 04:43:56.999409 Set Vref, RX VrefLevel [Byte0]: 73
1116 04:43:57.002498 [Byte1]: 73
1117 04:43:57.007335
1118 04:43:57.007419 Set Vref, RX VrefLevel [Byte0]: 74
1119 04:43:57.010049 [Byte1]: 74
1120 04:43:57.014341
1121 04:43:57.014464 Set Vref, RX VrefLevel [Byte0]: 75
1122 04:43:57.017743 [Byte1]: 75
1123 04:43:57.021895
1124 04:43:57.022029 Set Vref, RX VrefLevel [Byte0]: 76
1125 04:43:57.025347 [Byte1]: 76
1126 04:43:57.029501
1127 04:43:57.029587 Set Vref, RX VrefLevel [Byte0]: 77
1128 04:43:57.032944 [Byte1]: 77
1129 04:43:57.037614
1130 04:43:57.037698 Set Vref, RX VrefLevel [Byte0]: 78
1131 04:43:57.040220 [Byte1]: 78
1132 04:43:57.044789
1133 04:43:57.044920 Set Vref, RX VrefLevel [Byte0]: 79
1134 04:43:57.047860 [Byte1]: 79
1135 04:43:57.052564
1136 04:43:57.052652 Final RX Vref Byte 0 = 57 to rank0
1137 04:43:57.055998 Final RX Vref Byte 1 = 57 to rank0
1138 04:43:57.059413 Final RX Vref Byte 0 = 57 to rank1
1139 04:43:57.062689 Final RX Vref Byte 1 = 57 to rank1==
1140 04:43:57.066067 Dram Type= 6, Freq= 0, CH_0, rank 0
1141 04:43:57.068909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 04:43:57.072806 ==
1143 04:43:57.072899 DQS Delay:
1144 04:43:57.072965 DQS0 = 0, DQS1 = 0
1145 04:43:57.075558 DQM Delay:
1146 04:43:57.075639 DQM0 = 91, DQM1 = 85
1147 04:43:57.078910 DQ Delay:
1148 04:43:57.082277 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1149 04:43:57.082359 DQ4 =92, DQ5 =80, DQ6 =96, DQ7 =100
1150 04:43:57.085644 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1151 04:43:57.088988 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1152 04:43:57.092133
1153 04:43:57.092256
1154 04:43:57.098940 [DQSOSCAuto] RK0, (LSB)MR18= 0x473d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
1155 04:43:57.102152 CH0 RK0: MR19=606, MR18=473D
1156 04:43:57.108810 CH0_RK0: MR19=0x606, MR18=0x473D, DQSOSC=392, MR23=63, INC=96, DEC=64
1157 04:43:57.108927
1158 04:43:57.112175 ----->DramcWriteLeveling(PI) begin...
1159 04:43:57.112316 ==
1160 04:43:57.115511 Dram Type= 6, Freq= 0, CH_0, rank 1
1161 04:43:57.119221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1162 04:43:57.119349 ==
1163 04:43:57.122696 Write leveling (Byte 0): 32 => 32
1164 04:43:57.125459 Write leveling (Byte 1): 31 => 31
1165 04:43:57.128929 DramcWriteLeveling(PI) end<-----
1166 04:43:57.129042
1167 04:43:57.129137 ==
1168 04:43:57.173153 Dram Type= 6, Freq= 0, CH_0, rank 1
1169 04:43:57.173293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1170 04:43:57.173580 ==
1171 04:43:57.173650 [Gating] SW mode calibration
1172 04:43:57.173731 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1173 04:43:57.173812 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1174 04:43:57.173886 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1175 04:43:57.173947 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1176 04:43:57.174541 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1177 04:43:57.174625 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 04:43:57.175233 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 04:43:57.217340 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 04:43:57.217508 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 04:43:57.217810 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 04:43:57.217891 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 04:43:57.217957 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 04:43:57.218019 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 04:43:57.218078 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 04:43:57.218135 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 04:43:57.218192 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 04:43:57.218260 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 04:43:57.261491 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 04:43:57.261735 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 04:43:57.262055 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1192 04:43:57.262154 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1193 04:43:57.262256 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1194 04:43:57.262347 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 04:43:57.262435 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 04:43:57.262536 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 04:43:57.262625 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 04:43:57.262711 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 04:43:57.265414 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 04:43:57.269180 0 9 8 | B1->B0 | 3030 2c2b | 1 1 | (0 0) (1 1)
1201 04:43:57.275803 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1202 04:43:57.279078 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1203 04:43:57.282736 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1204 04:43:57.289051 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1205 04:43:57.292353 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1206 04:43:57.295758 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1207 04:43:57.302560 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1208 04:43:57.306641 0 10 8 | B1->B0 | 2828 2b2b | 1 1 | (1 1) (1 1)
1209 04:43:57.310087 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 04:43:57.314216 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 04:43:57.317787 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 04:43:57.321228 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 04:43:57.327466 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 04:43:57.331705 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 04:43:57.335108 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
1216 04:43:57.341813 0 11 8 | B1->B0 | 3f3f 3b3b | 0 0 | (0 0) (1 1)
1217 04:43:57.345362 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 04:43:57.348661 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 04:43:57.355336 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 04:43:57.358223 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 04:43:57.361604 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 04:43:57.364964 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 04:43:57.371672 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 04:43:57.375064 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1225 04:43:57.378453 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 04:43:57.384899 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 04:43:57.388154 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 04:43:57.391489 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 04:43:57.398584 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 04:43:57.401892 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 04:43:57.405055 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 04:43:57.411927 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 04:43:57.414880 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 04:43:57.418312 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 04:43:57.425301 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 04:43:57.428674 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 04:43:57.432159 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 04:43:57.438375 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 04:43:57.441720 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 04:43:57.445172 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1241 04:43:57.448791 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1242 04:43:57.452152 Total UI for P1: 0, mck2ui 16
1243 04:43:57.454911 best dqsien dly found for B0: ( 0, 14, 10)
1244 04:43:57.458399 Total UI for P1: 0, mck2ui 16
1245 04:43:57.461709 best dqsien dly found for B1: ( 0, 14, 8)
1246 04:43:57.464980 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1247 04:43:57.468405 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1248 04:43:57.471726
1249 04:43:57.475011 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1250 04:43:57.478742 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1251 04:43:57.481777 [Gating] SW calibration Done
1252 04:43:57.481891 ==
1253 04:43:57.485197 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 04:43:57.488353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 04:43:57.488464 ==
1256 04:43:57.488576 RX Vref Scan: 0
1257 04:43:57.488668
1258 04:43:57.492064 RX Vref 0 -> 0, step: 1
1259 04:43:57.492173
1260 04:43:57.495376 RX Delay -130 -> 252, step: 16
1261 04:43:57.498754 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1262 04:43:57.501891 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1263 04:43:57.508862 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1264 04:43:57.512058 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1265 04:43:57.515275 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1266 04:43:57.518566 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1267 04:43:57.522357 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1268 04:43:57.529000 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1269 04:43:57.531708 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1270 04:43:57.535155 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1271 04:43:57.538632 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1272 04:43:57.542048 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1273 04:43:57.549036 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1274 04:43:57.551841 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1275 04:43:57.555347 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1276 04:43:57.558814 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1277 04:43:57.558920 ==
1278 04:43:57.562293 Dram Type= 6, Freq= 0, CH_0, rank 1
1279 04:43:57.565663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1280 04:43:57.569120 ==
1281 04:43:57.569233 DQS Delay:
1282 04:43:57.569300 DQS0 = 0, DQS1 = 0
1283 04:43:57.571826 DQM Delay:
1284 04:43:57.571958 DQM0 = 91, DQM1 = 81
1285 04:43:57.575222 DQ Delay:
1286 04:43:57.578766 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1287 04:43:57.578910 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1288 04:43:57.582180 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1289 04:43:57.585527 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1290 04:43:57.588962
1291 04:43:57.589093
1292 04:43:57.589248 ==
1293 04:43:57.592448 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 04:43:57.595824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 04:43:57.595908 ==
1296 04:43:57.596012
1297 04:43:57.596131
1298 04:43:57.599022 TX Vref Scan disable
1299 04:43:57.599114 == TX Byte 0 ==
1300 04:43:57.605518 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1301 04:43:57.608600 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1302 04:43:57.608707 == TX Byte 1 ==
1303 04:43:57.615922 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1304 04:43:57.618717 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1305 04:43:57.618827 ==
1306 04:43:57.622468 Dram Type= 6, Freq= 0, CH_0, rank 1
1307 04:43:57.625519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1308 04:43:57.625636 ==
1309 04:43:57.639220 TX Vref=22, minBit 9, minWin=27, winSum=449
1310 04:43:57.642418 TX Vref=24, minBit 10, minWin=27, winSum=450
1311 04:43:57.645546 TX Vref=26, minBit 8, minWin=28, winSum=457
1312 04:43:57.649031 TX Vref=28, minBit 4, minWin=28, winSum=460
1313 04:43:57.652424 TX Vref=30, minBit 4, minWin=28, winSum=458
1314 04:43:57.658772 TX Vref=32, minBit 4, minWin=28, winSum=455
1315 04:43:57.662059 [TxChooseVref] Worse bit 4, Min win 28, Win sum 460, Final Vref 28
1316 04:43:57.662171
1317 04:43:57.665464 Final TX Range 1 Vref 28
1318 04:43:57.665566
1319 04:43:57.665632 ==
1320 04:43:57.669035 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 04:43:57.672319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 04:43:57.672432 ==
1323 04:43:57.675748
1324 04:43:57.675854
1325 04:43:57.675922 TX Vref Scan disable
1326 04:43:57.679114 == TX Byte 0 ==
1327 04:43:57.682521 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1328 04:43:57.688781 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1329 04:43:57.688887 == TX Byte 1 ==
1330 04:43:57.692222 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1331 04:43:57.695746 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1332 04:43:57.699258
1333 04:43:57.699355 [DATLAT]
1334 04:43:57.699422 Freq=800, CH0 RK1
1335 04:43:57.699483
1336 04:43:57.702703 DATLAT Default: 0xa
1337 04:43:57.702791 0, 0xFFFF, sum = 0
1338 04:43:57.706018 1, 0xFFFF, sum = 0
1339 04:43:57.706108 2, 0xFFFF, sum = 0
1340 04:43:57.709322 3, 0xFFFF, sum = 0
1341 04:43:57.709412 4, 0xFFFF, sum = 0
1342 04:43:57.712641 5, 0xFFFF, sum = 0
1343 04:43:57.712748 6, 0xFFFF, sum = 0
1344 04:43:57.716091 7, 0xFFFF, sum = 0
1345 04:43:57.718872 8, 0xFFFF, sum = 0
1346 04:43:57.718970 9, 0x0, sum = 1
1347 04:43:57.719037 10, 0x0, sum = 2
1348 04:43:57.722332 11, 0x0, sum = 3
1349 04:43:57.722421 12, 0x0, sum = 4
1350 04:43:57.725785 best_step = 10
1351 04:43:57.725875
1352 04:43:57.725942 ==
1353 04:43:57.729116 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 04:43:57.732346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 04:43:57.732450 ==
1356 04:43:57.735512 RX Vref Scan: 0
1357 04:43:57.735601
1358 04:43:57.735665 RX Vref 0 -> 0, step: 1
1359 04:43:57.735726
1360 04:43:57.738972 RX Delay -95 -> 252, step: 8
1361 04:43:57.745741 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1362 04:43:57.749234 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1363 04:43:57.752142 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1364 04:43:57.756083 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1365 04:43:57.759108 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1366 04:43:57.762412 iDelay=209, Bit 5, Center 84 (-31 ~ 200) 232
1367 04:43:57.769199 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1368 04:43:57.772716 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1369 04:43:57.776044 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1370 04:43:57.779483 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1371 04:43:57.782776 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1372 04:43:57.789143 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1373 04:43:57.792615 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1374 04:43:57.796081 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1375 04:43:57.799647 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1376 04:43:57.805815 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1377 04:43:57.805926 ==
1378 04:43:57.809372 Dram Type= 6, Freq= 0, CH_0, rank 1
1379 04:43:57.812825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 04:43:57.812925 ==
1381 04:43:57.812992 DQS Delay:
1382 04:43:57.816168 DQS0 = 0, DQS1 = 0
1383 04:43:57.816302 DQM Delay:
1384 04:43:57.819443 DQM0 = 93, DQM1 = 82
1385 04:43:57.819543 DQ Delay:
1386 04:43:57.822895 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1387 04:43:57.826443 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1388 04:43:57.829882 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1389 04:43:57.832675 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1390 04:43:57.832794
1391 04:43:57.832889
1392 04:43:57.839444 [DQSOSCAuto] RK1, (LSB)MR18= 0x4012, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1393 04:43:57.842860 CH0 RK1: MR19=606, MR18=4012
1394 04:43:57.849177 CH0_RK1: MR19=0x606, MR18=0x4012, DQSOSC=393, MR23=63, INC=95, DEC=63
1395 04:43:57.852702 [RxdqsGatingPostProcess] freq 800
1396 04:43:57.859584 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1397 04:43:57.859713 Pre-setting of DQS Precalculation
1398 04:43:57.866021 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1399 04:43:57.866141 ==
1400 04:43:57.869838 Dram Type= 6, Freq= 0, CH_1, rank 0
1401 04:43:57.872966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 04:43:57.873087 ==
1403 04:43:57.879478 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1404 04:43:57.885981 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1405 04:43:57.894101 [CA 0] Center 36 (6~67) winsize 62
1406 04:43:57.897399 [CA 1] Center 36 (6~67) winsize 62
1407 04:43:57.900436 [CA 2] Center 34 (4~65) winsize 62
1408 04:43:57.904126 [CA 3] Center 34 (4~65) winsize 62
1409 04:43:57.907003 [CA 4] Center 34 (4~65) winsize 62
1410 04:43:57.910573 [CA 5] Center 34 (4~64) winsize 61
1411 04:43:57.910730
1412 04:43:57.913943 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1413 04:43:57.914070
1414 04:43:57.917359 [CATrainingPosCal] consider 1 rank data
1415 04:43:57.920854 u2DelayCellTimex100 = 270/100 ps
1416 04:43:57.924223 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1417 04:43:57.927610 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1418 04:43:57.933975 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1419 04:43:57.937349 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1420 04:43:57.940821 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1421 04:43:57.944194 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1422 04:43:57.944342
1423 04:43:57.947694 CA PerBit enable=1, Macro0, CA PI delay=34
1424 04:43:57.947804
1425 04:43:57.950526 [CBTSetCACLKResult] CA Dly = 34
1426 04:43:57.950623 CS Dly: 5 (0~36)
1427 04:43:57.950691 ==
1428 04:43:57.953892 Dram Type= 6, Freq= 0, CH_1, rank 1
1429 04:43:57.960785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1430 04:43:57.960898 ==
1431 04:43:57.964114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1432 04:43:57.971080 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1433 04:43:57.980897 [CA 0] Center 36 (6~67) winsize 62
1434 04:43:57.984684 [CA 1] Center 37 (6~68) winsize 63
1435 04:43:57.987949 [CA 2] Center 35 (4~66) winsize 63
1436 04:43:57.991726 [CA 3] Center 35 (5~65) winsize 61
1437 04:43:57.994979 [CA 4] Center 35 (5~65) winsize 61
1438 04:43:57.999200 [CA 5] Center 34 (4~65) winsize 62
1439 04:43:57.999313
1440 04:43:58.002766 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1441 04:43:58.002867
1442 04:43:58.006253 [CATrainingPosCal] consider 2 rank data
1443 04:43:58.006352 u2DelayCellTimex100 = 270/100 ps
1444 04:43:58.012895 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1445 04:43:58.016316 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1446 04:43:58.019690 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1447 04:43:58.022686 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1448 04:43:58.026205 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1449 04:43:58.029640 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1450 04:43:58.029744
1451 04:43:58.032820 CA PerBit enable=1, Macro0, CA PI delay=34
1452 04:43:58.032956
1453 04:43:58.036296 [CBTSetCACLKResult] CA Dly = 34
1454 04:43:58.039676 CS Dly: 6 (0~39)
1455 04:43:58.039778
1456 04:43:58.043062 ----->DramcWriteLeveling(PI) begin...
1457 04:43:58.043146 ==
1458 04:43:58.046372 Dram Type= 6, Freq= 0, CH_1, rank 0
1459 04:43:58.049665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1460 04:43:58.049756 ==
1461 04:43:58.053013 Write leveling (Byte 0): 27 => 27
1462 04:43:58.056464 Write leveling (Byte 1): 27 => 27
1463 04:43:58.059951 DramcWriteLeveling(PI) end<-----
1464 04:43:58.060046
1465 04:43:58.060113 ==
1466 04:43:58.062656 Dram Type= 6, Freq= 0, CH_1, rank 0
1467 04:43:58.066127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1468 04:43:58.066220 ==
1469 04:43:58.069664 [Gating] SW mode calibration
1470 04:43:58.076477 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1471 04:43:58.082655 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1472 04:43:58.086609 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1473 04:43:58.089735 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1474 04:43:58.096260 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 04:43:58.099624 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 04:43:58.102697 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 04:43:58.109991 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 04:43:58.112749 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 04:43:58.116153 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 04:43:58.119729 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 04:43:58.126517 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 04:43:58.130032 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 04:43:58.133429 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 04:43:58.140043 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 04:43:58.143205 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 04:43:58.146445 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 04:43:58.153098 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 04:43:58.156247 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1489 04:43:58.160061 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1490 04:43:58.166464 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 04:43:58.169704 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 04:43:58.173172 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 04:43:58.180130 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 04:43:58.182967 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 04:43:58.186452 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 04:43:58.189988 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 04:43:58.196831 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 04:43:58.199893 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1499 04:43:58.203151 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1500 04:43:58.209976 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1501 04:43:58.213274 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1502 04:43:58.216444 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1503 04:43:58.223465 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1504 04:43:58.227023 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1505 04:43:58.230413 0 10 4 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (1 0)
1506 04:43:58.236621 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 04:43:58.239948 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 04:43:58.243371 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 04:43:58.250146 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 04:43:58.253596 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 04:43:58.257080 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 04:43:58.260444 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 04:43:58.267103 0 11 4 | B1->B0 | 2626 3737 | 0 0 | (0 0) (0 0)
1514 04:43:58.270193 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
1515 04:43:58.273678 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 04:43:58.280178 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 04:43:58.283492 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 04:43:58.286969 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 04:43:58.293487 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 04:43:58.297160 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1521 04:43:58.300169 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1522 04:43:58.306893 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 04:43:58.310177 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 04:43:58.313408 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 04:43:58.320159 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 04:43:58.323456 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 04:43:58.326631 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 04:43:58.333793 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 04:43:58.336616 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 04:43:58.340001 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 04:43:58.343448 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 04:43:58.350326 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 04:43:58.353852 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 04:43:58.357213 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 04:43:58.363604 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 04:43:58.367257 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 04:43:58.370636 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1538 04:43:58.377396 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 04:43:58.377514 Total UI for P1: 0, mck2ui 16
1540 04:43:58.384206 best dqsien dly found for B0: ( 0, 14, 4)
1541 04:43:58.384361 Total UI for P1: 0, mck2ui 16
1542 04:43:58.386984 best dqsien dly found for B1: ( 0, 14, 4)
1543 04:43:58.393972 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1544 04:43:58.397396 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1545 04:43:58.397504
1546 04:43:58.400841 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1547 04:43:58.404084 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1548 04:43:58.407375 [Gating] SW calibration Done
1549 04:43:58.407483 ==
1550 04:43:58.410461 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 04:43:58.414110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1552 04:43:58.414240 ==
1553 04:43:58.417354 RX Vref Scan: 0
1554 04:43:58.417451
1555 04:43:58.417516 RX Vref 0 -> 0, step: 1
1556 04:43:58.417577
1557 04:43:58.420757 RX Delay -130 -> 252, step: 16
1558 04:43:58.424083 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1559 04:43:58.427493 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1560 04:43:58.433901 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1561 04:43:58.437398 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1562 04:43:58.440856 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1563 04:43:58.444008 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1564 04:43:58.447257 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1565 04:43:58.454015 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1566 04:43:58.457475 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1567 04:43:58.460635 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1568 04:43:58.463863 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1569 04:43:58.467253 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1570 04:43:58.474326 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1571 04:43:58.477197 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1572 04:43:58.480579 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1573 04:43:58.484085 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1574 04:43:58.484236 ==
1575 04:43:58.487388 Dram Type= 6, Freq= 0, CH_1, rank 0
1576 04:43:58.494386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1577 04:43:58.494544 ==
1578 04:43:58.494650 DQS Delay:
1579 04:43:58.494747 DQS0 = 0, DQS1 = 0
1580 04:43:58.497291 DQM Delay:
1581 04:43:58.497435 DQM0 = 94, DQM1 = 89
1582 04:43:58.500759 DQ Delay:
1583 04:43:58.504125 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1584 04:43:58.507706 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1585 04:43:58.511039 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1586 04:43:58.514539 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1587 04:43:58.514676
1588 04:43:58.514779
1589 04:43:58.514877 ==
1590 04:43:58.517307 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 04:43:58.520611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 04:43:58.520756 ==
1593 04:43:58.520860
1594 04:43:58.520959
1595 04:43:58.524080 TX Vref Scan disable
1596 04:43:58.524209 == TX Byte 0 ==
1597 04:43:58.531001 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1598 04:43:58.534433 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1599 04:43:58.534607 == TX Byte 1 ==
1600 04:43:58.540738 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1601 04:43:58.544215 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1602 04:43:58.544373 ==
1603 04:43:58.547857 Dram Type= 6, Freq= 0, CH_1, rank 0
1604 04:43:58.551445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1605 04:43:58.551599 ==
1606 04:43:58.564578 TX Vref=22, minBit 1, minWin=26, winSum=438
1607 04:43:58.567751 TX Vref=24, minBit 0, minWin=27, winSum=441
1608 04:43:58.571272 TX Vref=26, minBit 1, minWin=27, winSum=451
1609 04:43:58.574639 TX Vref=28, minBit 1, minWin=27, winSum=445
1610 04:43:58.577899 TX Vref=30, minBit 1, minWin=27, winSum=452
1611 04:43:58.581380 TX Vref=32, minBit 1, minWin=27, winSum=446
1612 04:43:58.587951 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 30
1613 04:43:58.588128
1614 04:43:58.590928 Final TX Range 1 Vref 30
1615 04:43:58.591052
1616 04:43:58.591154 ==
1617 04:43:58.594601 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 04:43:58.598094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 04:43:58.598271 ==
1620 04:43:58.598379
1621 04:43:58.598473
1622 04:43:58.601289 TX Vref Scan disable
1623 04:43:58.604655 == TX Byte 0 ==
1624 04:43:58.607822 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1625 04:43:58.611177 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1626 04:43:58.614495 == TX Byte 1 ==
1627 04:43:58.617839 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1628 04:43:58.621405 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1629 04:43:58.621510
1630 04:43:58.624873 [DATLAT]
1631 04:43:58.624963 Freq=800, CH1 RK0
1632 04:43:58.625030
1633 04:43:58.628239 DATLAT Default: 0xa
1634 04:43:58.628341 0, 0xFFFF, sum = 0
1635 04:43:58.630969 1, 0xFFFF, sum = 0
1636 04:43:58.631098 2, 0xFFFF, sum = 0
1637 04:43:58.634500 3, 0xFFFF, sum = 0
1638 04:43:58.634626 4, 0xFFFF, sum = 0
1639 04:43:58.638022 5, 0xFFFF, sum = 0
1640 04:43:58.638144 6, 0xFFFF, sum = 0
1641 04:43:58.641527 7, 0xFFFF, sum = 0
1642 04:43:58.641641 8, 0xFFFF, sum = 0
1643 04:43:58.645007 9, 0x0, sum = 1
1644 04:43:58.645124 10, 0x0, sum = 2
1645 04:43:58.647838 11, 0x0, sum = 3
1646 04:43:58.647955 12, 0x0, sum = 4
1647 04:43:58.651228 best_step = 10
1648 04:43:58.651341
1649 04:43:58.651441 ==
1650 04:43:58.654632 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 04:43:58.658115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 04:43:58.658239 ==
1653 04:43:58.661640 RX Vref Scan: 1
1654 04:43:58.661753
1655 04:43:58.661851 Set Vref Range= 32 -> 127
1656 04:43:58.661946
1657 04:43:58.665101 RX Vref 32 -> 127, step: 1
1658 04:43:58.665219
1659 04:43:58.667879 RX Delay -63 -> 252, step: 8
1660 04:43:58.667994
1661 04:43:58.671851 Set Vref, RX VrefLevel [Byte0]: 32
1662 04:43:58.674493 [Byte1]: 32
1663 04:43:58.674609
1664 04:43:58.677879 Set Vref, RX VrefLevel [Byte0]: 33
1665 04:43:58.681328 [Byte1]: 33
1666 04:43:58.681445
1667 04:43:58.684773 Set Vref, RX VrefLevel [Byte0]: 34
1668 04:43:58.688104 [Byte1]: 34
1669 04:43:58.692082
1670 04:43:58.692216 Set Vref, RX VrefLevel [Byte0]: 35
1671 04:43:58.695145 [Byte1]: 35
1672 04:43:58.699714
1673 04:43:58.699891 Set Vref, RX VrefLevel [Byte0]: 36
1674 04:43:58.702805 [Byte1]: 36
1675 04:43:58.707458
1676 04:43:58.707583 Set Vref, RX VrefLevel [Byte0]: 37
1677 04:43:58.710505 [Byte1]: 37
1678 04:43:58.714732
1679 04:43:58.714878 Set Vref, RX VrefLevel [Byte0]: 38
1680 04:43:58.717879 [Byte1]: 38
1681 04:43:58.722193
1682 04:43:58.722340 Set Vref, RX VrefLevel [Byte0]: 39
1683 04:43:58.725200 [Byte1]: 39
1684 04:43:58.729511
1685 04:43:58.729648 Set Vref, RX VrefLevel [Byte0]: 40
1686 04:43:58.732627 [Byte1]: 40
1687 04:43:58.736894
1688 04:43:58.737040 Set Vref, RX VrefLevel [Byte0]: 41
1689 04:43:58.740613 [Byte1]: 41
1690 04:43:58.744679
1691 04:43:58.744876 Set Vref, RX VrefLevel [Byte0]: 42
1692 04:43:58.748093 [Byte1]: 42
1693 04:43:58.752229
1694 04:43:58.752368 Set Vref, RX VrefLevel [Byte0]: 43
1695 04:43:58.755243 [Byte1]: 43
1696 04:43:58.759220
1697 04:43:58.759367 Set Vref, RX VrefLevel [Byte0]: 44
1698 04:43:58.762725 [Byte1]: 44
1699 04:43:58.766936
1700 04:43:58.767084 Set Vref, RX VrefLevel [Byte0]: 45
1701 04:43:58.770370 [Byte1]: 45
1702 04:43:58.774672
1703 04:43:58.774812 Set Vref, RX VrefLevel [Byte0]: 46
1704 04:43:58.777480 [Byte1]: 46
1705 04:43:58.781641
1706 04:43:58.781796 Set Vref, RX VrefLevel [Byte0]: 47
1707 04:43:58.785004 [Byte1]: 47
1708 04:43:58.789766
1709 04:43:58.789912 Set Vref, RX VrefLevel [Byte0]: 48
1710 04:43:58.792624 [Byte1]: 48
1711 04:43:58.796676
1712 04:43:58.796796 Set Vref, RX VrefLevel [Byte0]: 49
1713 04:43:58.800479 [Byte1]: 49
1714 04:43:58.804406
1715 04:43:58.804537 Set Vref, RX VrefLevel [Byte0]: 50
1716 04:43:58.807719 [Byte1]: 50
1717 04:43:58.811824
1718 04:43:58.811961 Set Vref, RX VrefLevel [Byte0]: 51
1719 04:43:58.815301 [Byte1]: 51
1720 04:43:58.819465
1721 04:43:58.819657 Set Vref, RX VrefLevel [Byte0]: 52
1722 04:43:58.822664 [Byte1]: 52
1723 04:43:58.826665
1724 04:43:58.826814 Set Vref, RX VrefLevel [Byte0]: 53
1725 04:43:58.830106 [Byte1]: 53
1726 04:43:58.834258
1727 04:43:58.834425 Set Vref, RX VrefLevel [Byte0]: 54
1728 04:43:58.837627 [Byte1]: 54
1729 04:43:58.841574
1730 04:43:58.841723 Set Vref, RX VrefLevel [Byte0]: 55
1731 04:43:58.845012 [Byte1]: 55
1732 04:43:58.849800
1733 04:43:58.849971 Set Vref, RX VrefLevel [Byte0]: 56
1734 04:43:58.853022 [Byte1]: 56
1735 04:43:58.856869
1736 04:43:58.857009 Set Vref, RX VrefLevel [Byte0]: 57
1737 04:43:58.860369 [Byte1]: 57
1738 04:43:58.864407
1739 04:43:58.864548 Set Vref, RX VrefLevel [Byte0]: 58
1740 04:43:58.867703 [Byte1]: 58
1741 04:43:58.871849
1742 04:43:58.872004 Set Vref, RX VrefLevel [Byte0]: 59
1743 04:43:58.875275 [Byte1]: 59
1744 04:43:58.879553
1745 04:43:58.879677 Set Vref, RX VrefLevel [Byte0]: 60
1746 04:43:58.883006 [Byte1]: 60
1747 04:43:58.887186
1748 04:43:58.887346 Set Vref, RX VrefLevel [Byte0]: 61
1749 04:43:58.890527 [Byte1]: 61
1750 04:43:58.894723
1751 04:43:58.894865 Set Vref, RX VrefLevel [Byte0]: 62
1752 04:43:58.897433 [Byte1]: 62
1753 04:43:58.901605
1754 04:43:58.901759 Set Vref, RX VrefLevel [Byte0]: 63
1755 04:43:58.905412 [Byte1]: 63
1756 04:43:58.909634
1757 04:43:58.909773 Set Vref, RX VrefLevel [Byte0]: 64
1758 04:43:58.912874 [Byte1]: 64
1759 04:43:58.916798
1760 04:43:58.916960 Set Vref, RX VrefLevel [Byte0]: 65
1761 04:43:58.920281 [Byte1]: 65
1762 04:43:58.924617
1763 04:43:58.924777 Set Vref, RX VrefLevel [Byte0]: 66
1764 04:43:58.928021 [Byte1]: 66
1765 04:43:58.931981
1766 04:43:58.932098 Set Vref, RX VrefLevel [Byte0]: 67
1767 04:43:58.935444 [Byte1]: 67
1768 04:43:58.939651
1769 04:43:58.939817 Set Vref, RX VrefLevel [Byte0]: 68
1770 04:43:58.942358 [Byte1]: 68
1771 04:43:58.947117
1772 04:43:58.947271 Set Vref, RX VrefLevel [Byte0]: 69
1773 04:43:58.949844 [Byte1]: 69
1774 04:43:58.954794
1775 04:43:58.954946 Set Vref, RX VrefLevel [Byte0]: 70
1776 04:43:58.957490 [Byte1]: 70
1777 04:43:58.961789
1778 04:43:58.961936 Set Vref, RX VrefLevel [Byte0]: 71
1779 04:43:58.965269 [Byte1]: 71
1780 04:43:58.969299
1781 04:43:58.969456 Set Vref, RX VrefLevel [Byte0]: 72
1782 04:43:58.972637 [Byte1]: 72
1783 04:43:58.976886
1784 04:43:58.977004 Final RX Vref Byte 0 = 58 to rank0
1785 04:43:58.980129 Final RX Vref Byte 1 = 58 to rank0
1786 04:43:58.983597 Final RX Vref Byte 0 = 58 to rank1
1787 04:43:58.986768 Final RX Vref Byte 1 = 58 to rank1==
1788 04:43:58.990625 Dram Type= 6, Freq= 0, CH_1, rank 0
1789 04:43:58.996723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 04:43:58.996853 ==
1791 04:43:58.996942 DQS Delay:
1792 04:43:58.997008 DQS0 = 0, DQS1 = 0
1793 04:43:59.000231 DQM Delay:
1794 04:43:59.000410 DQM0 = 96, DQM1 = 90
1795 04:43:59.003772 DQ Delay:
1796 04:43:59.007096 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1797 04:43:59.007249 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1798 04:43:59.010433 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1799 04:43:59.017229 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =100
1800 04:43:59.017397
1801 04:43:59.017496
1802 04:43:59.023943 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a47, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1803 04:43:59.027166 CH1 RK0: MR19=606, MR18=2A47
1804 04:43:59.033900 CH1_RK0: MR19=0x606, MR18=0x2A47, DQSOSC=392, MR23=63, INC=96, DEC=64
1805 04:43:59.034066
1806 04:43:59.036704 ----->DramcWriteLeveling(PI) begin...
1807 04:43:59.036794 ==
1808 04:43:59.040090 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 04:43:59.043428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 04:43:59.043541 ==
1811 04:43:59.046942 Write leveling (Byte 0): 27 => 27
1812 04:43:59.050597 Write leveling (Byte 1): 30 => 30
1813 04:43:59.053803 DramcWriteLeveling(PI) end<-----
1814 04:43:59.053919
1815 04:43:59.054003 ==
1816 04:43:59.057150 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 04:43:59.060726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 04:43:59.060836 ==
1819 04:43:59.063632 [Gating] SW mode calibration
1820 04:43:59.070397 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1821 04:43:59.077199 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1822 04:43:59.080634 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1823 04:43:59.084023 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1824 04:43:59.090721 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1825 04:43:59.094297 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 04:43:59.097497 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 04:43:59.103911 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 04:43:59.107044 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 04:43:59.110618 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 04:43:59.114222 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 04:43:59.120745 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 04:43:59.124181 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 04:43:59.127692 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 04:43:59.134353 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 04:43:59.137239 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 04:43:59.140682 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 04:43:59.147458 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1838 04:43:59.151007 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1839 04:43:59.154414 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1840 04:43:59.161341 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 04:43:59.164013 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 04:43:59.167621 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 04:43:59.174423 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 04:43:59.177886 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 04:43:59.180694 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 04:43:59.187591 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 04:43:59.190921 0 9 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1848 04:43:59.194306 0 9 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
1849 04:43:59.197782 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 04:43:59.203898 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 04:43:59.207454 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 04:43:59.213735 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 04:43:59.217181 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 04:43:59.220928 0 10 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1855 04:43:59.224006 0 10 4 | B1->B0 | 2b2b 3030 | 1 1 | (0 0) (1 0)
1856 04:43:59.230587 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1857 04:43:59.234289 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 04:43:59.237246 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 04:43:59.243979 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 04:43:59.247139 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 04:43:59.250965 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 04:43:59.257390 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 04:43:59.260861 0 11 4 | B1->B0 | 3f3f 2c2c | 0 0 | (0 0) (0 0)
1864 04:43:59.264173 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 04:43:59.270971 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 04:43:59.274390 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 04:43:59.277742 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 04:43:59.283915 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 04:43:59.287472 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 04:43:59.290974 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 04:43:59.294367 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1872 04:43:59.301057 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 04:43:59.304471 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 04:43:59.307266 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 04:43:59.314171 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 04:43:59.317612 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 04:43:59.321053 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 04:43:59.327398 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 04:43:59.331328 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 04:43:59.334122 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 04:43:59.340823 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 04:43:59.344180 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 04:43:59.347982 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 04:43:59.354635 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 04:43:59.357650 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 04:43:59.361327 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 04:43:59.364387 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1888 04:43:59.371184 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 04:43:59.374558 Total UI for P1: 0, mck2ui 16
1890 04:43:59.378386 best dqsien dly found for B0: ( 0, 14, 6)
1891 04:43:59.378573 Total UI for P1: 0, mck2ui 16
1892 04:43:59.384799 best dqsien dly found for B1: ( 0, 14, 4)
1893 04:43:59.388270 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1894 04:43:59.391079 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1895 04:43:59.391214
1896 04:43:59.394631 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1897 04:43:59.398213 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1898 04:43:59.401879 [Gating] SW calibration Done
1899 04:43:59.402026 ==
1900 04:43:59.405003 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 04:43:59.408183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 04:43:59.408331 ==
1903 04:43:59.411726 RX Vref Scan: 0
1904 04:43:59.411848
1905 04:43:59.411940 RX Vref 0 -> 0, step: 1
1906 04:43:59.412028
1907 04:43:59.415159 RX Delay -130 -> 252, step: 16
1908 04:43:59.418050 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1909 04:43:59.424923 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1910 04:43:59.428553 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1911 04:43:59.431966 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1912 04:43:59.434771 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1913 04:43:59.438076 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1914 04:43:59.441569 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1915 04:43:59.448503 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1916 04:43:59.451815 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1917 04:43:59.455105 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1918 04:43:59.458568 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1919 04:43:59.461904 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1920 04:43:59.468673 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1921 04:43:59.472037 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1922 04:43:59.475107 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1923 04:43:59.478844 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1924 04:43:59.478994 ==
1925 04:43:59.482021 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 04:43:59.488329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 04:43:59.488491 ==
1928 04:43:59.488603 DQS Delay:
1929 04:43:59.492159 DQS0 = 0, DQS1 = 0
1930 04:43:59.492314 DQM Delay:
1931 04:43:59.492413 DQM0 = 91, DQM1 = 88
1932 04:43:59.495287 DQ Delay:
1933 04:43:59.498399 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1934 04:43:59.501725 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1935 04:43:59.504957 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1936 04:43:59.508338 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1937 04:43:59.508443
1938 04:43:59.508510
1939 04:43:59.508571 ==
1940 04:43:59.511711 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 04:43:59.515061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 04:43:59.515207 ==
1943 04:43:59.515306
1944 04:43:59.515396
1945 04:43:59.518324 TX Vref Scan disable
1946 04:43:59.518456 == TX Byte 0 ==
1947 04:43:59.525377 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1948 04:43:59.528820 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1949 04:43:59.528958 == TX Byte 1 ==
1950 04:43:59.534983 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1951 04:43:59.538611 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1952 04:43:59.538759 ==
1953 04:43:59.542093 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 04:43:59.545391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 04:43:59.545537 ==
1956 04:43:59.559637 TX Vref=22, minBit 1, minWin=26, winSum=441
1957 04:43:59.562439 TX Vref=24, minBit 2, minWin=27, winSum=446
1958 04:43:59.565944 TX Vref=26, minBit 1, minWin=27, winSum=449
1959 04:43:59.569295 TX Vref=28, minBit 2, minWin=27, winSum=450
1960 04:43:59.572633 TX Vref=30, minBit 2, minWin=27, winSum=450
1961 04:43:59.576205 TX Vref=32, minBit 2, minWin=27, winSum=448
1962 04:43:59.582822 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 28
1963 04:43:59.582979
1964 04:43:59.586080 Final TX Range 1 Vref 28
1965 04:43:59.586213
1966 04:43:59.586311 ==
1967 04:43:59.589662 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 04:43:59.593077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 04:43:59.593188 ==
1970 04:43:59.593257
1971 04:43:59.593322
1972 04:43:59.595756 TX Vref Scan disable
1973 04:43:59.599210 == TX Byte 0 ==
1974 04:43:59.602590 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1975 04:43:59.605921 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1976 04:43:59.609134 == TX Byte 1 ==
1977 04:43:59.612408 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1978 04:43:59.616323 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1979 04:43:59.616448
1980 04:43:59.619421 [DATLAT]
1981 04:43:59.619545 Freq=800, CH1 RK1
1982 04:43:59.619642
1983 04:43:59.622722 DATLAT Default: 0xa
1984 04:43:59.622869 0, 0xFFFF, sum = 0
1985 04:43:59.625902 1, 0xFFFF, sum = 0
1986 04:43:59.626033 2, 0xFFFF, sum = 0
1987 04:43:59.629146 3, 0xFFFF, sum = 0
1988 04:43:59.629288 4, 0xFFFF, sum = 0
1989 04:43:59.632725 5, 0xFFFF, sum = 0
1990 04:43:59.632863 6, 0xFFFF, sum = 0
1991 04:43:59.636029 7, 0xFFFF, sum = 0
1992 04:43:59.636160 8, 0xFFFF, sum = 0
1993 04:43:59.639606 9, 0x0, sum = 1
1994 04:43:59.639734 10, 0x0, sum = 2
1995 04:43:59.643114 11, 0x0, sum = 3
1996 04:43:59.643259 12, 0x0, sum = 4
1997 04:43:59.646644 best_step = 10
1998 04:43:59.646760
1999 04:43:59.646856 ==
2000 04:43:59.649842 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 04:43:59.652722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 04:43:59.652831 ==
2003 04:43:59.656061 RX Vref Scan: 0
2004 04:43:59.656190
2005 04:43:59.656316 RX Vref 0 -> 0, step: 1
2006 04:43:59.656381
2007 04:43:59.659465 RX Delay -79 -> 252, step: 8
2008 04:43:59.666364 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2009 04:43:59.669763 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2010 04:43:59.672617 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2011 04:43:59.676646 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2012 04:43:59.679307 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2013 04:43:59.682926 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2014 04:43:59.689602 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2015 04:43:59.692830 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2016 04:43:59.696282 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2017 04:43:59.699718 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2018 04:43:59.702935 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
2019 04:43:59.706407 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2020 04:43:59.713052 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2021 04:43:59.716409 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2022 04:43:59.719628 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2023 04:43:59.722970 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2024 04:43:59.723127 ==
2025 04:43:59.726061 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 04:43:59.733334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 04:43:59.733509 ==
2028 04:43:59.733613 DQS Delay:
2029 04:43:59.733707 DQS0 = 0, DQS1 = 0
2030 04:43:59.736550 DQM Delay:
2031 04:43:59.736643 DQM0 = 97, DQM1 = 91
2032 04:43:59.739573 DQ Delay:
2033 04:43:59.742852 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2034 04:43:59.746391 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2035 04:43:59.749814 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2036 04:43:59.753211 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2037 04:43:59.753322
2038 04:43:59.753389
2039 04:43:59.759414 [DQSOSCAuto] RK1, (LSB)MR18= 0x440e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2040 04:43:59.762942 CH1 RK1: MR19=606, MR18=440E
2041 04:43:59.769830 CH1_RK1: MR19=0x606, MR18=0x440E, DQSOSC=392, MR23=63, INC=96, DEC=64
2042 04:43:59.773331 [RxdqsGatingPostProcess] freq 800
2043 04:43:59.776833 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2044 04:43:59.780180 Pre-setting of DQS Precalculation
2045 04:43:59.786267 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2046 04:43:59.793067 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2047 04:43:59.799906 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2048 04:43:59.800067
2049 04:43:59.800166
2050 04:43:59.803228 [Calibration Summary] 1600 Mbps
2051 04:43:59.803368 CH 0, Rank 0
2052 04:43:59.806584 SW Impedance : PASS
2053 04:43:59.809963 DUTY Scan : NO K
2054 04:43:59.810110 ZQ Calibration : PASS
2055 04:43:59.813234 Jitter Meter : NO K
2056 04:43:59.816646 CBT Training : PASS
2057 04:43:59.816766 Write leveling : PASS
2058 04:43:59.819967 RX DQS gating : PASS
2059 04:43:59.820103 RX DQ/DQS(RDDQC) : PASS
2060 04:43:59.823319 TX DQ/DQS : PASS
2061 04:43:59.826832 RX DATLAT : PASS
2062 04:43:59.826977 RX DQ/DQS(Engine): PASS
2063 04:43:59.830254 TX OE : NO K
2064 04:43:59.830388 All Pass.
2065 04:43:59.830485
2066 04:43:59.833525 CH 0, Rank 1
2067 04:43:59.833626 SW Impedance : PASS
2068 04:43:59.836911 DUTY Scan : NO K
2069 04:43:59.840204 ZQ Calibration : PASS
2070 04:43:59.840354 Jitter Meter : NO K
2071 04:43:59.843686 CBT Training : PASS
2072 04:43:59.846923 Write leveling : PASS
2073 04:43:59.847070 RX DQS gating : PASS
2074 04:43:59.850033 RX DQ/DQS(RDDQC) : PASS
2075 04:43:59.850156 TX DQ/DQS : PASS
2076 04:43:59.853250 RX DATLAT : PASS
2077 04:43:59.856685 RX DQ/DQS(Engine): PASS
2078 04:43:59.856798 TX OE : NO K
2079 04:43:59.860133 All Pass.
2080 04:43:59.860258
2081 04:43:59.860353 CH 1, Rank 0
2082 04:43:59.863420 SW Impedance : PASS
2083 04:43:59.863507 DUTY Scan : NO K
2084 04:43:59.866918 ZQ Calibration : PASS
2085 04:43:59.870238 Jitter Meter : NO K
2086 04:43:59.870341 CBT Training : PASS
2087 04:43:59.873700 Write leveling : PASS
2088 04:43:59.876538 RX DQS gating : PASS
2089 04:43:59.876638 RX DQ/DQS(RDDQC) : PASS
2090 04:43:59.880069 TX DQ/DQS : PASS
2091 04:43:59.883451 RX DATLAT : PASS
2092 04:43:59.883562 RX DQ/DQS(Engine): PASS
2093 04:43:59.886835 TX OE : NO K
2094 04:43:59.886968 All Pass.
2095 04:43:59.887066
2096 04:43:59.890094 CH 1, Rank 1
2097 04:43:59.890230 SW Impedance : PASS
2098 04:43:59.893668 DUTY Scan : NO K
2099 04:43:59.897119 ZQ Calibration : PASS
2100 04:43:59.897274 Jitter Meter : NO K
2101 04:43:59.899931 CBT Training : PASS
2102 04:43:59.900051 Write leveling : PASS
2103 04:43:59.903477 RX DQS gating : PASS
2104 04:43:59.906600 RX DQ/DQS(RDDQC) : PASS
2105 04:43:59.906696 TX DQ/DQS : PASS
2106 04:43:59.909810 RX DATLAT : PASS
2107 04:43:59.913231 RX DQ/DQS(Engine): PASS
2108 04:43:59.913339 TX OE : NO K
2109 04:43:59.916624 All Pass.
2110 04:43:59.916719
2111 04:43:59.916788 DramC Write-DBI off
2112 04:43:59.920038 PER_BANK_REFRESH: Hybrid Mode
2113 04:43:59.920175 TX_TRACKING: ON
2114 04:43:59.923202 [GetDramInforAfterCalByMRR] Vendor 6.
2115 04:43:59.930005 [GetDramInforAfterCalByMRR] Revision 606.
2116 04:43:59.933452 [GetDramInforAfterCalByMRR] Revision 2 0.
2117 04:43:59.933607 MR0 0x3b3b
2118 04:43:59.933703 MR8 0x5151
2119 04:43:59.936961 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 04:43:59.937088
2121 04:43:59.940258 MR0 0x3b3b
2122 04:43:59.940381 MR8 0x5151
2123 04:43:59.943610 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2124 04:43:59.943746
2125 04:43:59.953525 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2126 04:43:59.956827 [FAST_K] Save calibration result to emmc
2127 04:43:59.960043 [FAST_K] Save calibration result to emmc
2128 04:43:59.963944 dram_init: config_dvfs: 1
2129 04:43:59.967199 dramc_set_vcore_voltage set vcore to 662500
2130 04:43:59.970590 Read voltage for 1200, 2
2131 04:43:59.970751 Vio18 = 0
2132 04:43:59.970863 Vcore = 662500
2133 04:43:59.973941 Vdram = 0
2134 04:43:59.974103 Vddq = 0
2135 04:43:59.974210 Vmddr = 0
2136 04:43:59.980331 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2137 04:43:59.983883 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2138 04:43:59.986645 MEM_TYPE=3, freq_sel=15
2139 04:43:59.990226 sv_algorithm_assistance_LP4_1600
2140 04:43:59.993458 ============ PULL DRAM RESETB DOWN ============
2141 04:43:59.996761 ========== PULL DRAM RESETB DOWN end =========
2142 04:44:00.003562 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2143 04:44:00.006912 ===================================
2144 04:44:00.007088 LPDDR4 DRAM CONFIGURATION
2145 04:44:00.010358 ===================================
2146 04:44:00.013904 EX_ROW_EN[0] = 0x0
2147 04:44:00.017316 EX_ROW_EN[1] = 0x0
2148 04:44:00.017512 LP4Y_EN = 0x0
2149 04:44:00.020541 WORK_FSP = 0x0
2150 04:44:00.020680 WL = 0x4
2151 04:44:00.023930 RL = 0x4
2152 04:44:00.024100 BL = 0x2
2153 04:44:00.027314 RPST = 0x0
2154 04:44:00.027436 RD_PRE = 0x0
2155 04:44:00.030104 WR_PRE = 0x1
2156 04:44:00.030234 WR_PST = 0x0
2157 04:44:00.033509 DBI_WR = 0x0
2158 04:44:00.033642 DBI_RD = 0x0
2159 04:44:00.036815 OTF = 0x1
2160 04:44:00.040141 ===================================
2161 04:44:00.043671 ===================================
2162 04:44:00.043815 ANA top config
2163 04:44:00.046917 ===================================
2164 04:44:00.050411 DLL_ASYNC_EN = 0
2165 04:44:00.053951 ALL_SLAVE_EN = 0
2166 04:44:00.054098 NEW_RANK_MODE = 1
2167 04:44:00.057106 DLL_IDLE_MODE = 1
2168 04:44:00.060256 LP45_APHY_COMB_EN = 1
2169 04:44:00.063416 TX_ODT_DIS = 1
2170 04:44:00.066909 NEW_8X_MODE = 1
2171 04:44:00.067058 ===================================
2172 04:44:00.070257 ===================================
2173 04:44:00.073692 data_rate = 2400
2174 04:44:00.076824 CKR = 1
2175 04:44:00.080348 DQ_P2S_RATIO = 8
2176 04:44:00.083483 ===================================
2177 04:44:00.087058 CA_P2S_RATIO = 8
2178 04:44:00.090522 DQ_CA_OPEN = 0
2179 04:44:00.090690 DQ_SEMI_OPEN = 0
2180 04:44:00.094019 CA_SEMI_OPEN = 0
2181 04:44:00.097396 CA_FULL_RATE = 0
2182 04:44:00.100748 DQ_CKDIV4_EN = 0
2183 04:44:00.103518 CA_CKDIV4_EN = 0
2184 04:44:00.106991 CA_PREDIV_EN = 0
2185 04:44:00.107146 PH8_DLY = 17
2186 04:44:00.110365 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2187 04:44:00.114024 DQ_AAMCK_DIV = 4
2188 04:44:00.117320 CA_AAMCK_DIV = 4
2189 04:44:00.120081 CA_ADMCK_DIV = 4
2190 04:44:00.123575 DQ_TRACK_CA_EN = 0
2191 04:44:00.123730 CA_PICK = 1200
2192 04:44:00.126935 CA_MCKIO = 1200
2193 04:44:00.130346 MCKIO_SEMI = 0
2194 04:44:00.133509 PLL_FREQ = 2366
2195 04:44:00.136824 DQ_UI_PI_RATIO = 32
2196 04:44:00.140237 CA_UI_PI_RATIO = 0
2197 04:44:00.143641 ===================================
2198 04:44:00.146858 ===================================
2199 04:44:00.150347 memory_type:LPDDR4
2200 04:44:00.150498 GP_NUM : 10
2201 04:44:00.153737 SRAM_EN : 1
2202 04:44:00.153877 MD32_EN : 0
2203 04:44:00.157115 ===================================
2204 04:44:00.160557 [ANA_INIT] >>>>>>>>>>>>>>
2205 04:44:00.164023 <<<<<< [CONFIGURE PHASE]: ANA_TX
2206 04:44:00.166828 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2207 04:44:00.170185 ===================================
2208 04:44:00.173996 data_rate = 2400,PCW = 0X5b00
2209 04:44:00.177191 ===================================
2210 04:44:00.180701 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2211 04:44:00.184033 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 04:44:00.190440 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 04:44:00.193566 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2214 04:44:00.196844 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2215 04:44:00.200305 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2216 04:44:00.203861 [ANA_INIT] flow start
2217 04:44:00.207112 [ANA_INIT] PLL >>>>>>>>
2218 04:44:00.207240 [ANA_INIT] PLL <<<<<<<<
2219 04:44:00.210652 [ANA_INIT] MIDPI >>>>>>>>
2220 04:44:00.213974 [ANA_INIT] MIDPI <<<<<<<<
2221 04:44:00.216782 [ANA_INIT] DLL >>>>>>>>
2222 04:44:00.216886 [ANA_INIT] DLL <<<<<<<<
2223 04:44:00.220305 [ANA_INIT] flow end
2224 04:44:00.223804 ============ LP4 DIFF to SE enter ============
2225 04:44:00.227127 ============ LP4 DIFF to SE exit ============
2226 04:44:00.230658 [ANA_INIT] <<<<<<<<<<<<<
2227 04:44:00.233520 [Flow] Enable top DCM control >>>>>
2228 04:44:00.237479 [Flow] Enable top DCM control <<<<<
2229 04:44:00.240590 Enable DLL master slave shuffle
2230 04:44:00.243867 ==============================================================
2231 04:44:00.247186 Gating Mode config
2232 04:44:00.253660 ==============================================================
2233 04:44:00.253818 Config description:
2234 04:44:00.263950 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2235 04:44:00.270844 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2236 04:44:00.277049 SELPH_MODE 0: By rank 1: By Phase
2237 04:44:00.280354 ==============================================================
2238 04:44:00.283603 GAT_TRACK_EN = 1
2239 04:44:00.287289 RX_GATING_MODE = 2
2240 04:44:00.290593 RX_GATING_TRACK_MODE = 2
2241 04:44:00.294009 SELPH_MODE = 1
2242 04:44:00.297399 PICG_EARLY_EN = 1
2243 04:44:00.300732 VALID_LAT_VALUE = 1
2244 04:44:00.303872 ==============================================================
2245 04:44:00.307071 Enter into Gating configuration >>>>
2246 04:44:00.310581 Exit from Gating configuration <<<<
2247 04:44:00.313732 Enter into DVFS_PRE_config >>>>>
2248 04:44:00.326900 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2249 04:44:00.327067 Exit from DVFS_PRE_config <<<<<
2250 04:44:00.330583 Enter into PICG configuration >>>>
2251 04:44:00.333952 Exit from PICG configuration <<<<
2252 04:44:00.337417 [RX_INPUT] configuration >>>>>
2253 04:44:00.340399 [RX_INPUT] configuration <<<<<
2254 04:44:00.347056 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2255 04:44:00.350412 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2256 04:44:00.357219 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 04:44:00.364098 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 04:44:00.370293 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 04:44:00.377315 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 04:44:00.380617 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2261 04:44:00.384187 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2262 04:44:00.387090 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2263 04:44:00.393746 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2264 04:44:00.397652 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2265 04:44:00.400470 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2266 04:44:00.404353 ===================================
2267 04:44:00.407660 LPDDR4 DRAM CONFIGURATION
2268 04:44:00.410859 ===================================
2269 04:44:00.410997 EX_ROW_EN[0] = 0x0
2270 04:44:00.414257 EX_ROW_EN[1] = 0x0
2271 04:44:00.414392 LP4Y_EN = 0x0
2272 04:44:00.417544 WORK_FSP = 0x0
2273 04:44:00.417638 WL = 0x4
2274 04:44:00.420621 RL = 0x4
2275 04:44:00.423966 BL = 0x2
2276 04:44:00.424094 RPST = 0x0
2277 04:44:00.427407 RD_PRE = 0x0
2278 04:44:00.427541 WR_PRE = 0x1
2279 04:44:00.430899 WR_PST = 0x0
2280 04:44:00.431026 DBI_WR = 0x0
2281 04:44:00.433589 DBI_RD = 0x0
2282 04:44:00.433708 OTF = 0x1
2283 04:44:00.437083 ===================================
2284 04:44:00.440646 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2285 04:44:00.447538 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2286 04:44:00.450759 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 04:44:00.453583 ===================================
2288 04:44:00.457033 LPDDR4 DRAM CONFIGURATION
2289 04:44:00.460387 ===================================
2290 04:44:00.460529 EX_ROW_EN[0] = 0x10
2291 04:44:00.463843 EX_ROW_EN[1] = 0x0
2292 04:44:00.463980 LP4Y_EN = 0x0
2293 04:44:00.467142 WORK_FSP = 0x0
2294 04:44:00.467272 WL = 0x4
2295 04:44:00.470542 RL = 0x4
2296 04:44:00.470679 BL = 0x2
2297 04:44:00.474036 RPST = 0x0
2298 04:44:00.474177 RD_PRE = 0x0
2299 04:44:00.477424 WR_PRE = 0x1
2300 04:44:00.477558 WR_PST = 0x0
2301 04:44:00.480309 DBI_WR = 0x0
2302 04:44:00.483581 DBI_RD = 0x0
2303 04:44:00.483745 OTF = 0x1
2304 04:44:00.486867 ===================================
2305 04:44:00.494161 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2306 04:44:00.494334 ==
2307 04:44:00.496938 Dram Type= 6, Freq= 0, CH_0, rank 0
2308 04:44:00.500417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2309 04:44:00.500575 ==
2310 04:44:00.503868 [Duty_Offset_Calibration]
2311 04:44:00.504021 B0:2 B1:1 CA:1
2312 04:44:00.504122
2313 04:44:00.507284 [DutyScan_Calibration_Flow] k_type=0
2314 04:44:00.517984
2315 04:44:00.518146 ==CLK 0==
2316 04:44:00.521675 Final CLK duty delay cell = 0
2317 04:44:00.524599 [0] MAX Duty = 5187%(X100), DQS PI = 24
2318 04:44:00.528221 [0] MIN Duty = 4875%(X100), DQS PI = 0
2319 04:44:00.528399 [0] AVG Duty = 5031%(X100)
2320 04:44:00.528509
2321 04:44:00.531348 CH0 CLK Duty spec in!! Max-Min= 312%
2322 04:44:00.537787 [DutyScan_Calibration_Flow] ====Done====
2323 04:44:00.537930
2324 04:44:00.540985 [DutyScan_Calibration_Flow] k_type=1
2325 04:44:00.556891
2326 04:44:00.557056 ==DQS 0 ==
2327 04:44:00.559783 Final DQS duty delay cell = -4
2328 04:44:00.563140 [-4] MAX Duty = 5156%(X100), DQS PI = 24
2329 04:44:00.566591 [-4] MIN Duty = 4751%(X100), DQS PI = 62
2330 04:44:00.570093 [-4] AVG Duty = 4953%(X100)
2331 04:44:00.570217
2332 04:44:00.570284 ==DQS 1 ==
2333 04:44:00.573469 Final DQS duty delay cell = 0
2334 04:44:00.576875 [0] MAX Duty = 5187%(X100), DQS PI = 0
2335 04:44:00.579673 [0] MIN Duty = 5031%(X100), DQS PI = 34
2336 04:44:00.583025 [0] AVG Duty = 5109%(X100)
2337 04:44:00.583188
2338 04:44:00.586384 CH0 DQS 0 Duty spec in!! Max-Min= 405%
2339 04:44:00.586536
2340 04:44:00.589912 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2341 04:44:00.593342 [DutyScan_Calibration_Flow] ====Done====
2342 04:44:00.593501
2343 04:44:00.596706 [DutyScan_Calibration_Flow] k_type=3
2344 04:44:00.613409
2345 04:44:00.613608 ==DQM 0 ==
2346 04:44:00.616765 Final DQM duty delay cell = 0
2347 04:44:00.620125 [0] MAX Duty = 5156%(X100), DQS PI = 30
2348 04:44:00.623311 [0] MIN Duty = 4938%(X100), DQS PI = 0
2349 04:44:00.623480 [0] AVG Duty = 5047%(X100)
2350 04:44:00.626766
2351 04:44:00.626912 ==DQM 1 ==
2352 04:44:00.630206 Final DQM duty delay cell = 0
2353 04:44:00.633368 [0] MAX Duty = 5125%(X100), DQS PI = 58
2354 04:44:00.636672 [0] MIN Duty = 5062%(X100), DQS PI = 14
2355 04:44:00.636827 [0] AVG Duty = 5093%(X100)
2356 04:44:00.639739
2357 04:44:00.643427 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2358 04:44:00.643586
2359 04:44:00.646771 CH0 DQM 1 Duty spec in!! Max-Min= 63%
2360 04:44:00.650050 [DutyScan_Calibration_Flow] ====Done====
2361 04:44:00.650204
2362 04:44:00.653187 [DutyScan_Calibration_Flow] k_type=2
2363 04:44:00.669580
2364 04:44:00.669781 ==DQ 0 ==
2365 04:44:00.672888 Final DQ duty delay cell = 0
2366 04:44:00.676457 [0] MAX Duty = 5062%(X100), DQS PI = 32
2367 04:44:00.679600 [0] MIN Duty = 4875%(X100), DQS PI = 62
2368 04:44:00.679739 [0] AVG Duty = 4968%(X100)
2369 04:44:00.679839
2370 04:44:00.683231 ==DQ 1 ==
2371 04:44:00.683360 Final DQ duty delay cell = 0
2372 04:44:00.690131 [0] MAX Duty = 5093%(X100), DQS PI = 10
2373 04:44:00.693714 [0] MIN Duty = 4938%(X100), DQS PI = 36
2374 04:44:00.693881 [0] AVG Duty = 5015%(X100)
2375 04:44:00.693983
2376 04:44:00.696523 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2377 04:44:00.696651
2378 04:44:00.699984 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2379 04:44:00.706763 [DutyScan_Calibration_Flow] ====Done====
2380 04:44:00.706953 ==
2381 04:44:00.710381 Dram Type= 6, Freq= 0, CH_1, rank 0
2382 04:44:00.713734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2383 04:44:00.713887 ==
2384 04:44:00.716515 [Duty_Offset_Calibration]
2385 04:44:00.716640 B0:1 B1:0 CA:0
2386 04:44:00.716737
2387 04:44:00.720016 [DutyScan_Calibration_Flow] k_type=0
2388 04:44:00.729025
2389 04:44:00.729202 ==CLK 0==
2390 04:44:00.732323 Final CLK duty delay cell = -4
2391 04:44:00.735482 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2392 04:44:00.738981 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2393 04:44:00.742367 [-4] AVG Duty = 4937%(X100)
2394 04:44:00.742534
2395 04:44:00.745869 CH1 CLK Duty spec in!! Max-Min= 125%
2396 04:44:00.748684 [DutyScan_Calibration_Flow] ====Done====
2397 04:44:00.748830
2398 04:44:00.752019 [DutyScan_Calibration_Flow] k_type=1
2399 04:44:00.768731
2400 04:44:00.768908 ==DQS 0 ==
2401 04:44:00.772383 Final DQS duty delay cell = 0
2402 04:44:00.775568 [0] MAX Duty = 5094%(X100), DQS PI = 26
2403 04:44:00.778930 [0] MIN Duty = 4875%(X100), DQS PI = 0
2404 04:44:00.779088 [0] AVG Duty = 4984%(X100)
2405 04:44:00.782388
2406 04:44:00.782538 ==DQS 1 ==
2407 04:44:00.785701 Final DQS duty delay cell = 0
2408 04:44:00.789031 [0] MAX Duty = 5187%(X100), DQS PI = 18
2409 04:44:00.792547 [0] MIN Duty = 4969%(X100), DQS PI = 10
2410 04:44:00.792698 [0] AVG Duty = 5078%(X100)
2411 04:44:00.795286
2412 04:44:00.798672 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2413 04:44:00.798820
2414 04:44:00.802116 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2415 04:44:00.805703 [DutyScan_Calibration_Flow] ====Done====
2416 04:44:00.805856
2417 04:44:00.808401 [DutyScan_Calibration_Flow] k_type=3
2418 04:44:00.825241
2419 04:44:00.825421 ==DQM 0 ==
2420 04:44:00.828775 Final DQM duty delay cell = 0
2421 04:44:00.832163 [0] MAX Duty = 5187%(X100), DQS PI = 10
2422 04:44:00.835821 [0] MIN Duty = 5031%(X100), DQS PI = 0
2423 04:44:00.835989 [0] AVG Duty = 5109%(X100)
2424 04:44:00.838585
2425 04:44:00.838717 ==DQM 1 ==
2426 04:44:00.841899 Final DQM duty delay cell = 0
2427 04:44:00.845241 [0] MAX Duty = 5031%(X100), DQS PI = 16
2428 04:44:00.849106 [0] MIN Duty = 4907%(X100), DQS PI = 36
2429 04:44:00.849272 [0] AVG Duty = 4969%(X100)
2430 04:44:00.851817
2431 04:44:00.855252 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2432 04:44:00.855415
2433 04:44:00.858677 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2434 04:44:00.862095 [DutyScan_Calibration_Flow] ====Done====
2435 04:44:00.862241
2436 04:44:00.865235 [DutyScan_Calibration_Flow] k_type=2
2437 04:44:00.881303
2438 04:44:00.881478 ==DQ 0 ==
2439 04:44:00.884760 Final DQ duty delay cell = -4
2440 04:44:00.888338 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2441 04:44:00.891659 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2442 04:44:00.891814 [-4] AVG Duty = 5016%(X100)
2443 04:44:00.894782
2444 04:44:00.894914 ==DQ 1 ==
2445 04:44:00.897923 Final DQ duty delay cell = 0
2446 04:44:00.901025 [0] MAX Duty = 5125%(X100), DQS PI = 20
2447 04:44:00.904335 [0] MIN Duty = 4969%(X100), DQS PI = 10
2448 04:44:00.904459 [0] AVG Duty = 5047%(X100)
2449 04:44:00.907824
2450 04:44:00.911293 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2451 04:44:00.911399
2452 04:44:00.914852 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2453 04:44:00.918167 [DutyScan_Calibration_Flow] ====Done====
2454 04:44:00.921041 nWR fixed to 30
2455 04:44:00.921144 [ModeRegInit_LP4] CH0 RK0
2456 04:44:00.924394 [ModeRegInit_LP4] CH0 RK1
2457 04:44:00.927737 [ModeRegInit_LP4] CH1 RK0
2458 04:44:00.931680 [ModeRegInit_LP4] CH1 RK1
2459 04:44:00.931832 match AC timing 7
2460 04:44:00.934928 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2461 04:44:00.941195 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2462 04:44:00.944855 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2463 04:44:00.948097 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2464 04:44:00.954888 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2465 04:44:00.955018 ==
2466 04:44:00.958162 Dram Type= 6, Freq= 0, CH_0, rank 0
2467 04:44:00.961484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2468 04:44:00.961609 ==
2469 04:44:00.967806 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2470 04:44:00.971140 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2471 04:44:00.981793 [CA 0] Center 39 (8~70) winsize 63
2472 04:44:00.985104 [CA 1] Center 39 (8~70) winsize 63
2473 04:44:00.988441 [CA 2] Center 35 (5~66) winsize 62
2474 04:44:00.991733 [CA 3] Center 34 (4~65) winsize 62
2475 04:44:00.994892 [CA 4] Center 33 (3~64) winsize 62
2476 04:44:00.997985 [CA 5] Center 32 (3~62) winsize 60
2477 04:44:00.998113
2478 04:44:01.001545 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2479 04:44:01.001671
2480 04:44:01.004763 [CATrainingPosCal] consider 1 rank data
2481 04:44:01.008148 u2DelayCellTimex100 = 270/100 ps
2482 04:44:01.011409 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2483 04:44:01.015240 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2484 04:44:01.021717 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2485 04:44:01.025162 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2486 04:44:01.028017 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2487 04:44:01.031453 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2488 04:44:01.031616
2489 04:44:01.034836 CA PerBit enable=1, Macro0, CA PI delay=32
2490 04:44:01.034975
2491 04:44:01.038113 [CBTSetCACLKResult] CA Dly = 32
2492 04:44:01.038243 CS Dly: 6 (0~37)
2493 04:44:01.038343 ==
2494 04:44:01.041338 Dram Type= 6, Freq= 0, CH_0, rank 1
2495 04:44:01.047992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2496 04:44:01.048168 ==
2497 04:44:01.051422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2498 04:44:01.058572 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2499 04:44:01.067419 [CA 0] Center 38 (8~69) winsize 62
2500 04:44:01.070807 [CA 1] Center 38 (8~69) winsize 62
2501 04:44:01.073660 [CA 2] Center 35 (4~66) winsize 63
2502 04:44:01.077051 [CA 3] Center 34 (4~65) winsize 62
2503 04:44:01.080454 [CA 4] Center 33 (3~64) winsize 62
2504 04:44:01.083676 [CA 5] Center 32 (3~62) winsize 60
2505 04:44:01.083823
2506 04:44:01.086941 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2507 04:44:01.087078
2508 04:44:01.090438 [CATrainingPosCal] consider 2 rank data
2509 04:44:01.093841 u2DelayCellTimex100 = 270/100 ps
2510 04:44:01.097231 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2511 04:44:01.100600 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2512 04:44:01.107319 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2513 04:44:01.110471 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2514 04:44:01.114187 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2515 04:44:01.117644 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2516 04:44:01.117810
2517 04:44:01.120368 CA PerBit enable=1, Macro0, CA PI delay=32
2518 04:44:01.120496
2519 04:44:01.123781 [CBTSetCACLKResult] CA Dly = 32
2520 04:44:01.123926 CS Dly: 6 (0~38)
2521 04:44:01.124026
2522 04:44:01.127601 ----->DramcWriteLeveling(PI) begin...
2523 04:44:01.130785 ==
2524 04:44:01.130968 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 04:44:01.137398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 04:44:01.137600 ==
2527 04:44:01.140716 Write leveling (Byte 0): 34 => 34
2528 04:44:01.144160 Write leveling (Byte 1): 30 => 30
2529 04:44:01.147534 DramcWriteLeveling(PI) end<-----
2530 04:44:01.147696
2531 04:44:01.147796 ==
2532 04:44:01.150762 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 04:44:01.153972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 04:44:01.154135 ==
2535 04:44:01.157626 [Gating] SW mode calibration
2536 04:44:01.164353 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2537 04:44:01.167807 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2538 04:44:01.173958 0 15 0 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
2539 04:44:01.177970 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2540 04:44:01.180659 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 04:44:01.187380 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 04:44:01.190713 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 04:44:01.194687 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 04:44:01.200799 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2545 04:44:01.204299 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2546 04:44:01.207710 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2547 04:44:01.211091 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2548 04:44:01.217802 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 04:44:01.221111 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 04:44:01.224345 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 04:44:01.231057 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 04:44:01.234734 1 0 24 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2553 04:44:01.238058 1 0 28 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
2554 04:44:01.244461 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2555 04:44:01.247890 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 04:44:01.251389 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 04:44:01.257598 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 04:44:01.261138 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 04:44:01.264511 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 04:44:01.270949 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 04:44:01.274702 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2562 04:44:01.277925 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2563 04:44:01.284675 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 04:44:01.288054 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 04:44:01.291330 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 04:44:01.297872 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 04:44:01.301318 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 04:44:01.304730 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 04:44:01.308043 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 04:44:01.314216 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 04:44:01.317684 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 04:44:01.321124 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 04:44:01.327348 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 04:44:01.330828 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 04:44:01.334732 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 04:44:01.341381 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 04:44:01.344044 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2578 04:44:01.347326 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2579 04:44:01.351252 Total UI for P1: 0, mck2ui 16
2580 04:44:01.354559 best dqsien dly found for B0: ( 1, 3, 28)
2581 04:44:01.360813 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 04:44:01.360954 Total UI for P1: 0, mck2ui 16
2583 04:44:01.367694 best dqsien dly found for B1: ( 1, 4, 0)
2584 04:44:01.371039 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2585 04:44:01.374445 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2586 04:44:01.374612
2587 04:44:01.377387 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2588 04:44:01.380636 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2589 04:44:01.384546 [Gating] SW calibration Done
2590 04:44:01.384685 ==
2591 04:44:01.387623 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 04:44:01.391324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 04:44:01.391497 ==
2594 04:44:01.394364 RX Vref Scan: 0
2595 04:44:01.394511
2596 04:44:01.394614 RX Vref 0 -> 0, step: 1
2597 04:44:01.394707
2598 04:44:01.397462 RX Delay -40 -> 252, step: 8
2599 04:44:01.401309 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2600 04:44:01.407684 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2601 04:44:01.410811 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2602 04:44:01.414215 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2603 04:44:01.417723 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2604 04:44:01.421146 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2605 04:44:01.424636 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2606 04:44:01.430951 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2607 04:44:01.434432 iDelay=200, Bit 8, Center 99 (40 ~ 159) 120
2608 04:44:01.437791 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2609 04:44:01.440979 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2610 04:44:01.444374 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2611 04:44:01.451289 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2612 04:44:01.454741 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2613 04:44:01.457974 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2614 04:44:01.461339 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2615 04:44:01.461527 ==
2616 04:44:01.464674 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 04:44:01.471494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 04:44:01.471706 ==
2619 04:44:01.471820 DQS Delay:
2620 04:44:01.471930 DQS0 = 0, DQS1 = 0
2621 04:44:01.474248 DQM Delay:
2622 04:44:01.474367 DQM0 = 121, DQM1 = 113
2623 04:44:01.477762 DQ Delay:
2624 04:44:01.481208 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2625 04:44:01.484725 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2626 04:44:01.488009 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2627 04:44:01.491539 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2628 04:44:01.491696
2629 04:44:01.491793
2630 04:44:01.491882 ==
2631 04:44:01.494967 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 04:44:01.498266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 04:44:01.498485 ==
2634 04:44:01.498584
2635 04:44:01.498676
2636 04:44:01.501534 TX Vref Scan disable
2637 04:44:01.504742 == TX Byte 0 ==
2638 04:44:01.508062 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2639 04:44:01.511310 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2640 04:44:01.514590 == TX Byte 1 ==
2641 04:44:01.518092 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2642 04:44:01.521590 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2643 04:44:01.521721 ==
2644 04:44:01.524711 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 04:44:01.528216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 04:44:01.531476 ==
2647 04:44:01.541782 TX Vref=22, minBit 0, minWin=25, winSum=404
2648 04:44:01.545119 TX Vref=24, minBit 3, minWin=25, winSum=415
2649 04:44:01.548960 TX Vref=26, minBit 4, minWin=25, winSum=416
2650 04:44:01.551794 TX Vref=28, minBit 7, minWin=25, winSum=417
2651 04:44:01.555197 TX Vref=30, minBit 0, minWin=26, winSum=424
2652 04:44:01.558734 TX Vref=32, minBit 12, minWin=25, winSum=419
2653 04:44:01.565592 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
2654 04:44:01.565743
2655 04:44:01.568375 Final TX Range 1 Vref 30
2656 04:44:01.568480
2657 04:44:01.568550 ==
2658 04:44:01.571751 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 04:44:01.575681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 04:44:01.575806 ==
2661 04:44:01.575877
2662 04:44:01.579073
2663 04:44:01.579167 TX Vref Scan disable
2664 04:44:01.582540 == TX Byte 0 ==
2665 04:44:01.585240 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2666 04:44:01.588729 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2667 04:44:01.592080 == TX Byte 1 ==
2668 04:44:01.595632 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2669 04:44:01.598900 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2670 04:44:01.599020
2671 04:44:01.602350 [DATLAT]
2672 04:44:01.602497 Freq=1200, CH0 RK0
2673 04:44:01.602599
2674 04:44:01.605776 DATLAT Default: 0xd
2675 04:44:01.605905 0, 0xFFFF, sum = 0
2676 04:44:01.608659 1, 0xFFFF, sum = 0
2677 04:44:01.608785 2, 0xFFFF, sum = 0
2678 04:44:01.612618 3, 0xFFFF, sum = 0
2679 04:44:01.612753 4, 0xFFFF, sum = 0
2680 04:44:01.615684 5, 0xFFFF, sum = 0
2681 04:44:01.615830 6, 0xFFFF, sum = 0
2682 04:44:01.618638 7, 0xFFFF, sum = 0
2683 04:44:01.618786 8, 0xFFFF, sum = 0
2684 04:44:01.622072 9, 0xFFFF, sum = 0
2685 04:44:01.625397 10, 0xFFFF, sum = 0
2686 04:44:01.625581 11, 0xFFFF, sum = 0
2687 04:44:01.628709 12, 0x0, sum = 1
2688 04:44:01.628861 13, 0x0, sum = 2
2689 04:44:01.628964 14, 0x0, sum = 3
2690 04:44:01.632431 15, 0x0, sum = 4
2691 04:44:01.632583 best_step = 13
2692 04:44:01.632679
2693 04:44:01.632771 ==
2694 04:44:01.635544 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 04:44:01.642188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 04:44:01.642380 ==
2697 04:44:01.642486 RX Vref Scan: 1
2698 04:44:01.642578
2699 04:44:01.645736 Set Vref Range= 32 -> 127
2700 04:44:01.645870
2701 04:44:01.648777 RX Vref 32 -> 127, step: 1
2702 04:44:01.648906
2703 04:44:01.652486 RX Delay -5 -> 252, step: 4
2704 04:44:01.652621
2705 04:44:01.652697 Set Vref, RX VrefLevel [Byte0]: 32
2706 04:44:01.655401 [Byte1]: 32
2707 04:44:01.660185
2708 04:44:01.660393 Set Vref, RX VrefLevel [Byte0]: 33
2709 04:44:01.663313 [Byte1]: 33
2710 04:44:01.668473
2711 04:44:01.668639 Set Vref, RX VrefLevel [Byte0]: 34
2712 04:44:01.671091 [Byte1]: 34
2713 04:44:01.675743
2714 04:44:01.675915 Set Vref, RX VrefLevel [Byte0]: 35
2715 04:44:01.682535 [Byte1]: 35
2716 04:44:01.682727
2717 04:44:01.685966 Set Vref, RX VrefLevel [Byte0]: 36
2718 04:44:01.688823 [Byte1]: 36
2719 04:44:01.688975
2720 04:44:01.692203 Set Vref, RX VrefLevel [Byte0]: 37
2721 04:44:01.695677 [Byte1]: 37
2722 04:44:01.699918
2723 04:44:01.700092 Set Vref, RX VrefLevel [Byte0]: 38
2724 04:44:01.702649 [Byte1]: 38
2725 04:44:01.707390
2726 04:44:01.707560 Set Vref, RX VrefLevel [Byte0]: 39
2727 04:44:01.710788 [Byte1]: 39
2728 04:44:01.714875
2729 04:44:01.715035 Set Vref, RX VrefLevel [Byte0]: 40
2730 04:44:01.718404 [Byte1]: 40
2731 04:44:01.722977
2732 04:44:01.723137 Set Vref, RX VrefLevel [Byte0]: 41
2733 04:44:01.726117 [Byte1]: 41
2734 04:44:01.731016
2735 04:44:01.731186 Set Vref, RX VrefLevel [Byte0]: 42
2736 04:44:01.733858 [Byte1]: 42
2737 04:44:01.738463
2738 04:44:01.738618 Set Vref, RX VrefLevel [Byte0]: 43
2739 04:44:01.741980 [Byte1]: 43
2740 04:44:01.746774
2741 04:44:01.746933 Set Vref, RX VrefLevel [Byte0]: 44
2742 04:44:01.750135 [Byte1]: 44
2743 04:44:01.754569
2744 04:44:01.754740 Set Vref, RX VrefLevel [Byte0]: 45
2745 04:44:01.757700 [Byte1]: 45
2746 04:44:01.762510
2747 04:44:01.762673 Set Vref, RX VrefLevel [Byte0]: 46
2748 04:44:01.765211 [Byte1]: 46
2749 04:44:01.770288
2750 04:44:01.770457 Set Vref, RX VrefLevel [Byte0]: 47
2751 04:44:01.773187 [Byte1]: 47
2752 04:44:01.777848
2753 04:44:01.780924 Set Vref, RX VrefLevel [Byte0]: 48
2754 04:44:01.784588 [Byte1]: 48
2755 04:44:01.784763
2756 04:44:01.787838 Set Vref, RX VrefLevel [Byte0]: 49
2757 04:44:01.790934 [Byte1]: 49
2758 04:44:01.791105
2759 04:44:01.794337 Set Vref, RX VrefLevel [Byte0]: 50
2760 04:44:01.797740 [Byte1]: 50
2761 04:44:01.801700
2762 04:44:01.801859 Set Vref, RX VrefLevel [Byte0]: 51
2763 04:44:01.805177 [Byte1]: 51
2764 04:44:01.809216
2765 04:44:01.809365 Set Vref, RX VrefLevel [Byte0]: 52
2766 04:44:01.812635 [Byte1]: 52
2767 04:44:01.816937
2768 04:44:01.817094 Set Vref, RX VrefLevel [Byte0]: 53
2769 04:44:01.820330 [Byte1]: 53
2770 04:44:01.825144
2771 04:44:01.825309 Set Vref, RX VrefLevel [Byte0]: 54
2772 04:44:01.828519 [Byte1]: 54
2773 04:44:01.833197
2774 04:44:01.833367 Set Vref, RX VrefLevel [Byte0]: 55
2775 04:44:01.836011 [Byte1]: 55
2776 04:44:01.840825
2777 04:44:01.840959 Set Vref, RX VrefLevel [Byte0]: 56
2778 04:44:01.844349 [Byte1]: 56
2779 04:44:01.848608
2780 04:44:01.848733 Set Vref, RX VrefLevel [Byte0]: 57
2781 04:44:01.852050 [Byte1]: 57
2782 04:44:01.856899
2783 04:44:01.857078 Set Vref, RX VrefLevel [Byte0]: 58
2784 04:44:01.859926 [Byte1]: 58
2785 04:44:01.864431
2786 04:44:01.864608 Set Vref, RX VrefLevel [Byte0]: 59
2787 04:44:01.867617 [Byte1]: 59
2788 04:44:01.872458
2789 04:44:01.872624 Set Vref, RX VrefLevel [Byte0]: 60
2790 04:44:01.875187 [Byte1]: 60
2791 04:44:01.879991
2792 04:44:01.880153 Set Vref, RX VrefLevel [Byte0]: 61
2793 04:44:01.883438 [Byte1]: 61
2794 04:44:01.887981
2795 04:44:01.888140 Set Vref, RX VrefLevel [Byte0]: 62
2796 04:44:01.891377 [Byte1]: 62
2797 04:44:01.896056
2798 04:44:01.896220 Set Vref, RX VrefLevel [Byte0]: 63
2799 04:44:01.899129 [Byte1]: 63
2800 04:44:01.903675
2801 04:44:01.903850 Set Vref, RX VrefLevel [Byte0]: 64
2802 04:44:01.906633 [Byte1]: 64
2803 04:44:01.911435
2804 04:44:01.911590 Set Vref, RX VrefLevel [Byte0]: 65
2805 04:44:01.914501 [Byte1]: 65
2806 04:44:01.919328
2807 04:44:01.919482 Set Vref, RX VrefLevel [Byte0]: 66
2808 04:44:01.922780 [Byte1]: 66
2809 04:44:01.927014
2810 04:44:01.927168 Set Vref, RX VrefLevel [Byte0]: 67
2811 04:44:01.930524 [Byte1]: 67
2812 04:44:01.935179
2813 04:44:01.935347 Set Vref, RX VrefLevel [Byte0]: 68
2814 04:44:01.938446 [Byte1]: 68
2815 04:44:01.942711
2816 04:44:01.942870 Set Vref, RX VrefLevel [Byte0]: 69
2817 04:44:01.945989 [Byte1]: 69
2818 04:44:01.950758
2819 04:44:01.950930 Set Vref, RX VrefLevel [Byte0]: 70
2820 04:44:01.954177 [Byte1]: 70
2821 04:44:01.958271
2822 04:44:01.958473 Set Vref, RX VrefLevel [Byte0]: 71
2823 04:44:01.961713 [Byte1]: 71
2824 04:44:01.966497
2825 04:44:01.966684 Set Vref, RX VrefLevel [Byte0]: 72
2826 04:44:01.969803 [Byte1]: 72
2827 04:44:01.974383
2828 04:44:01.974576 Final RX Vref Byte 0 = 54 to rank0
2829 04:44:01.977728 Final RX Vref Byte 1 = 53 to rank0
2830 04:44:01.981111 Final RX Vref Byte 0 = 54 to rank1
2831 04:44:01.984468 Final RX Vref Byte 1 = 53 to rank1==
2832 04:44:01.987965 Dram Type= 6, Freq= 0, CH_0, rank 0
2833 04:44:01.993958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2834 04:44:01.994120 ==
2835 04:44:01.994220 DQS Delay:
2836 04:44:01.994311 DQS0 = 0, DQS1 = 0
2837 04:44:01.997380 DQM Delay:
2838 04:44:01.997527 DQM0 = 120, DQM1 = 112
2839 04:44:02.000736 DQ Delay:
2840 04:44:02.004093 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2841 04:44:02.007571 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2842 04:44:02.011102 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
2843 04:44:02.014483 DQ12 =118, DQ13 =118, DQ14 =124, DQ15 =120
2844 04:44:02.014632
2845 04:44:02.014735
2846 04:44:02.020692 [DQSOSCAuto] RK0, (LSB)MR18= 0x110b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2847 04:44:02.024705 CH0 RK0: MR19=404, MR18=110B
2848 04:44:02.031338 CH0_RK0: MR19=0x404, MR18=0x110B, DQSOSC=403, MR23=63, INC=40, DEC=26
2849 04:44:02.031518
2850 04:44:02.034257 ----->DramcWriteLeveling(PI) begin...
2851 04:44:02.034398 ==
2852 04:44:02.037615 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 04:44:02.041031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 04:44:02.044447 ==
2855 04:44:02.044602 Write leveling (Byte 0): 35 => 35
2856 04:44:02.047669 Write leveling (Byte 1): 28 => 28
2857 04:44:02.050944 DramcWriteLeveling(PI) end<-----
2858 04:44:02.051106
2859 04:44:02.051209 ==
2860 04:44:02.054366 Dram Type= 6, Freq= 0, CH_0, rank 1
2861 04:44:02.061264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 04:44:02.061429 ==
2863 04:44:02.061530 [Gating] SW mode calibration
2864 04:44:02.070820 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2865 04:44:02.074321 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2866 04:44:02.077695 0 15 0 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 0)
2867 04:44:02.084386 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 04:44:02.087879 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 04:44:02.090976 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 04:44:02.097956 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2871 04:44:02.101303 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 04:44:02.104644 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2873 04:44:02.111208 0 15 28 | B1->B0 | 3131 2c2c | 1 1 | (1 0) (1 1)
2874 04:44:02.114739 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2875 04:44:02.118218 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 04:44:02.124810 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2877 04:44:02.128199 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 04:44:02.131653 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 04:44:02.137680 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 04:44:02.141473 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2881 04:44:02.144797 1 0 28 | B1->B0 | 3c3c 3d3d | 0 1 | (0 0) (0 0)
2882 04:44:02.147701 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 04:44:02.154302 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 04:44:02.157595 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 04:44:02.161309 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 04:44:02.167621 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 04:44:02.171090 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 04:44:02.174441 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 04:44:02.181197 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 04:44:02.184768 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2891 04:44:02.188375 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 04:44:02.195032 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 04:44:02.197708 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 04:44:02.201686 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 04:44:02.207827 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 04:44:02.211203 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 04:44:02.214569 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 04:44:02.221181 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 04:44:02.224722 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 04:44:02.228120 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 04:44:02.231541 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 04:44:02.238473 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 04:44:02.241174 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 04:44:02.244681 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2905 04:44:02.251634 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2906 04:44:02.254340 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 04:44:02.258272 Total UI for P1: 0, mck2ui 16
2908 04:44:02.261384 best dqsien dly found for B0: ( 1, 3, 28)
2909 04:44:02.264446 Total UI for P1: 0, mck2ui 16
2910 04:44:02.267817 best dqsien dly found for B1: ( 1, 3, 26)
2911 04:44:02.271321 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2912 04:44:02.274335 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
2913 04:44:02.274486
2914 04:44:02.278133 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2915 04:44:02.281607 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
2916 04:44:02.284754 [Gating] SW calibration Done
2917 04:44:02.284893 ==
2918 04:44:02.288141 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 04:44:02.291604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 04:44:02.294450 ==
2921 04:44:02.294592 RX Vref Scan: 0
2922 04:44:02.294692
2923 04:44:02.297850 RX Vref 0 -> 0, step: 1
2924 04:44:02.297981
2925 04:44:02.301318 RX Delay -40 -> 252, step: 8
2926 04:44:02.304688 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2927 04:44:02.308116 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2928 04:44:02.311288 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2929 04:44:02.314646 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2930 04:44:02.321617 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2931 04:44:02.324362 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2932 04:44:02.328225 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2933 04:44:02.331580 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2934 04:44:02.334827 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2935 04:44:02.338126 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2936 04:44:02.345019 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2937 04:44:02.348416 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2938 04:44:02.351194 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2939 04:44:02.354725 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2940 04:44:02.358123 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2941 04:44:02.365250 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2942 04:44:02.365419 ==
2943 04:44:02.367968 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 04:44:02.371509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 04:44:02.371658 ==
2946 04:44:02.371763 DQS Delay:
2947 04:44:02.374803 DQS0 = 0, DQS1 = 0
2948 04:44:02.374932 DQM Delay:
2949 04:44:02.378187 DQM0 = 122, DQM1 = 113
2950 04:44:02.378323 DQ Delay:
2951 04:44:02.381830 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2952 04:44:02.384675 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2953 04:44:02.388203 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
2954 04:44:02.391248 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2955 04:44:02.391405
2956 04:44:02.394811
2957 04:44:02.394959 ==
2958 04:44:02.398379 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 04:44:02.401884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 04:44:02.402062 ==
2961 04:44:02.402165
2962 04:44:02.402258
2963 04:44:02.404831 TX Vref Scan disable
2964 04:44:02.404975 == TX Byte 0 ==
2965 04:44:02.408214 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2966 04:44:02.415118 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2967 04:44:02.415286 == TX Byte 1 ==
2968 04:44:02.418432 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2969 04:44:02.425460 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2970 04:44:02.425651 ==
2971 04:44:02.428184 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 04:44:02.431616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 04:44:02.431761 ==
2974 04:44:02.444192 TX Vref=22, minBit 1, minWin=25, winSum=410
2975 04:44:02.447855 TX Vref=24, minBit 13, minWin=25, winSum=416
2976 04:44:02.451280 TX Vref=26, minBit 0, minWin=26, winSum=419
2977 04:44:02.454150 TX Vref=28, minBit 1, minWin=26, winSum=427
2978 04:44:02.457615 TX Vref=30, minBit 5, minWin=25, winSum=425
2979 04:44:02.461180 TX Vref=32, minBit 5, minWin=25, winSum=422
2980 04:44:02.467600 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
2981 04:44:02.467769
2982 04:44:02.471086 Final TX Range 1 Vref 28
2983 04:44:02.471234
2984 04:44:02.471334 ==
2985 04:44:02.474490 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 04:44:02.477905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 04:44:02.478063 ==
2988 04:44:02.478164
2989 04:44:02.481430
2990 04:44:02.481571 TX Vref Scan disable
2991 04:44:02.484145 == TX Byte 0 ==
2992 04:44:02.487714 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2993 04:44:02.491018 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2994 04:44:02.494412 == TX Byte 1 ==
2995 04:44:02.497537 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2996 04:44:02.501338 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2997 04:44:02.501500
2998 04:44:02.504033 [DATLAT]
2999 04:44:02.504154 Freq=1200, CH0 RK1
3000 04:44:02.504253
3001 04:44:02.507909 DATLAT Default: 0xd
3002 04:44:02.508052 0, 0xFFFF, sum = 0
3003 04:44:02.511005 1, 0xFFFF, sum = 0
3004 04:44:02.511136 2, 0xFFFF, sum = 0
3005 04:44:02.514674 3, 0xFFFF, sum = 0
3006 04:44:02.514824 4, 0xFFFF, sum = 0
3007 04:44:02.517883 5, 0xFFFF, sum = 0
3008 04:44:02.518025 6, 0xFFFF, sum = 0
3009 04:44:02.521079 7, 0xFFFF, sum = 0
3010 04:44:02.521224 8, 0xFFFF, sum = 0
3011 04:44:02.524531 9, 0xFFFF, sum = 0
3012 04:44:02.527954 10, 0xFFFF, sum = 0
3013 04:44:02.528120 11, 0xFFFF, sum = 0
3014 04:44:02.531452 12, 0x0, sum = 1
3015 04:44:02.531600 13, 0x0, sum = 2
3016 04:44:02.531702 14, 0x0, sum = 3
3017 04:44:02.534604 15, 0x0, sum = 4
3018 04:44:02.534749 best_step = 13
3019 04:44:02.534848
3020 04:44:02.537793 ==
3021 04:44:02.537930 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 04:44:02.544635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 04:44:02.544813 ==
3024 04:44:02.544917 RX Vref Scan: 0
3025 04:44:02.545011
3026 04:44:02.548086 RX Vref 0 -> 0, step: 1
3027 04:44:02.548224
3028 04:44:02.550939 RX Delay -13 -> 252, step: 4
3029 04:44:02.554783 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3030 04:44:02.557862 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3031 04:44:02.564736 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3032 04:44:02.568220 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3033 04:44:02.571681 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3034 04:44:02.574458 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3035 04:44:02.578016 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3036 04:44:02.584449 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3037 04:44:02.588412 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3038 04:44:02.591780 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3039 04:44:02.595135 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3040 04:44:02.598408 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3041 04:44:02.601685 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3042 04:44:02.608347 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3043 04:44:02.611732 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3044 04:44:02.615151 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3045 04:44:02.615310 ==
3046 04:44:02.618429 Dram Type= 6, Freq= 0, CH_0, rank 1
3047 04:44:02.621825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3048 04:44:02.621981 ==
3049 04:44:02.625263 DQS Delay:
3050 04:44:02.625405 DQS0 = 0, DQS1 = 0
3051 04:44:02.628243 DQM Delay:
3052 04:44:02.628403 DQM0 = 121, DQM1 = 111
3053 04:44:02.631401 DQ Delay:
3054 04:44:02.635178 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
3055 04:44:02.638689 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3056 04:44:02.641369 DQ8 =100, DQ9 =98, DQ10 =112, DQ11 =104
3057 04:44:02.644686 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =118
3058 04:44:02.644850
3059 04:44:02.644951
3060 04:44:02.651341 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3061 04:44:02.655099 CH0 RK1: MR19=403, MR18=10F2
3062 04:44:02.661998 CH0_RK1: MR19=0x403, MR18=0x10F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3063 04:44:02.665450 [RxdqsGatingPostProcess] freq 1200
3064 04:44:02.672072 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3065 04:44:02.672254 best DQS0 dly(2T, 0.5T) = (0, 11)
3066 04:44:02.675254 best DQS1 dly(2T, 0.5T) = (0, 12)
3067 04:44:02.678502 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3068 04:44:02.682045 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3069 04:44:02.685444 best DQS0 dly(2T, 0.5T) = (0, 11)
3070 04:44:02.688150 best DQS1 dly(2T, 0.5T) = (0, 11)
3071 04:44:02.692243 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3072 04:44:02.695015 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3073 04:44:02.698563 Pre-setting of DQS Precalculation
3074 04:44:02.701671 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3075 04:44:02.705283 ==
3076 04:44:02.705446 Dram Type= 6, Freq= 0, CH_1, rank 0
3077 04:44:02.711860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 04:44:02.712032 ==
3079 04:44:02.715349 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3080 04:44:02.721699 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3081 04:44:02.730729 [CA 0] Center 37 (7~68) winsize 62
3082 04:44:02.734063 [CA 1] Center 37 (7~68) winsize 62
3083 04:44:02.737573 [CA 2] Center 34 (4~65) winsize 62
3084 04:44:02.740620 [CA 3] Center 34 (4~64) winsize 61
3085 04:44:02.743835 [CA 4] Center 34 (4~64) winsize 61
3086 04:44:02.747384 [CA 5] Center 33 (3~63) winsize 61
3087 04:44:02.747556
3088 04:44:02.750629 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3089 04:44:02.750787
3090 04:44:02.754310 [CATrainingPosCal] consider 1 rank data
3091 04:44:02.757513 u2DelayCellTimex100 = 270/100 ps
3092 04:44:02.760890 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3093 04:44:02.764227 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3094 04:44:02.771000 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3095 04:44:02.773777 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 04:44:02.777115 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 04:44:02.780344 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3098 04:44:02.780500
3099 04:44:02.784350 CA PerBit enable=1, Macro0, CA PI delay=33
3100 04:44:02.784500
3101 04:44:02.787610 [CBTSetCACLKResult] CA Dly = 33
3102 04:44:02.787746 CS Dly: 8 (0~39)
3103 04:44:02.787846 ==
3104 04:44:02.790995 Dram Type= 6, Freq= 0, CH_1, rank 1
3105 04:44:02.797147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 04:44:02.797338 ==
3107 04:44:02.800693 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3108 04:44:02.807501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3109 04:44:02.816376 [CA 0] Center 37 (7~68) winsize 62
3110 04:44:02.819636 [CA 1] Center 37 (7~68) winsize 62
3111 04:44:02.822899 [CA 2] Center 35 (5~65) winsize 61
3112 04:44:02.826247 [CA 3] Center 34 (4~65) winsize 62
3113 04:44:02.829665 [CA 4] Center 34 (4~65) winsize 62
3114 04:44:02.833132 [CA 5] Center 34 (4~64) winsize 61
3115 04:44:02.833312
3116 04:44:02.836586 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3117 04:44:02.836742
3118 04:44:02.839380 [CATrainingPosCal] consider 2 rank data
3119 04:44:02.842869 u2DelayCellTimex100 = 270/100 ps
3120 04:44:02.846298 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3121 04:44:02.849739 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3122 04:44:02.856269 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3123 04:44:02.859358 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3124 04:44:02.863116 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3125 04:44:02.866212 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3126 04:44:02.866367
3127 04:44:02.869657 CA PerBit enable=1, Macro0, CA PI delay=33
3128 04:44:02.869794
3129 04:44:02.873025 [CBTSetCACLKResult] CA Dly = 33
3130 04:44:02.873168 CS Dly: 9 (0~41)
3131 04:44:02.873266
3132 04:44:02.876446 ----->DramcWriteLeveling(PI) begin...
3133 04:44:02.879564 ==
3134 04:44:02.882866 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 04:44:02.886459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 04:44:02.886628 ==
3137 04:44:02.889745 Write leveling (Byte 0): 25 => 25
3138 04:44:02.893034 Write leveling (Byte 1): 29 => 29
3139 04:44:02.896418 DramcWriteLeveling(PI) end<-----
3140 04:44:02.896587
3141 04:44:02.896690 ==
3142 04:44:02.899664 Dram Type= 6, Freq= 0, CH_1, rank 0
3143 04:44:02.903015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 04:44:02.903172 ==
3145 04:44:02.906368 [Gating] SW mode calibration
3146 04:44:02.912660 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3147 04:44:02.916200 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3148 04:44:02.923096 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3149 04:44:02.926424 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 04:44:02.929860 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 04:44:02.936094 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 04:44:02.940022 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 04:44:02.942792 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 04:44:02.949647 0 15 24 | B1->B0 | 3434 2d2d | 0 1 | (0 0) (1 0)
3155 04:44:02.953123 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3156 04:44:02.956671 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 04:44:02.962855 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 04:44:02.966284 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 04:44:02.969637 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 04:44:02.976530 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 04:44:02.979563 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 04:44:02.982968 1 0 24 | B1->B0 | 3030 3c3c | 0 1 | (1 1) (0 0)
3163 04:44:02.989746 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 04:44:02.993057 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 04:44:02.996323 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 04:44:03.000038 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 04:44:03.006454 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 04:44:03.009757 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 04:44:03.013096 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 04:44:03.019695 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3171 04:44:03.023150 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3172 04:44:03.026651 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 04:44:03.033346 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 04:44:03.036911 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 04:44:03.040294 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 04:44:03.046688 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 04:44:03.050263 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 04:44:03.053562 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 04:44:03.059906 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 04:44:03.063347 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 04:44:03.066707 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 04:44:03.070140 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 04:44:03.077038 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 04:44:03.079903 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 04:44:03.083291 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 04:44:03.089805 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3187 04:44:03.093363 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3188 04:44:03.096498 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 04:44:03.099703 Total UI for P1: 0, mck2ui 16
3190 04:44:03.103116 best dqsien dly found for B0: ( 1, 3, 26)
3191 04:44:03.106661 Total UI for P1: 0, mck2ui 16
3192 04:44:03.110010 best dqsien dly found for B1: ( 1, 3, 26)
3193 04:44:03.113301 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3194 04:44:03.116558 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3195 04:44:03.116724
3196 04:44:03.123434 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3197 04:44:03.126695 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3198 04:44:03.126869 [Gating] SW calibration Done
3199 04:44:03.130242 ==
3200 04:44:03.133142 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 04:44:03.136369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 04:44:03.136544 ==
3203 04:44:03.136649 RX Vref Scan: 0
3204 04:44:03.136742
3205 04:44:03.140233 RX Vref 0 -> 0, step: 1
3206 04:44:03.140419
3207 04:44:03.143706 RX Delay -40 -> 252, step: 8
3208 04:44:03.147229 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3209 04:44:03.149719 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3210 04:44:03.153703 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3211 04:44:03.160280 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3212 04:44:03.163760 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3213 04:44:03.167154 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3214 04:44:03.169877 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3215 04:44:03.173270 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3216 04:44:03.180118 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3217 04:44:03.183680 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3218 04:44:03.187224 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3219 04:44:03.189858 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3220 04:44:03.193301 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3221 04:44:03.200119 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3222 04:44:03.203314 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3223 04:44:03.206568 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3224 04:44:03.206743 ==
3225 04:44:03.210375 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 04:44:03.213447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 04:44:03.213620 ==
3228 04:44:03.216708 DQS Delay:
3229 04:44:03.216883 DQS0 = 0, DQS1 = 0
3230 04:44:03.220093 DQM Delay:
3231 04:44:03.220247 DQM0 = 119, DQM1 = 116
3232 04:44:03.223578 DQ Delay:
3233 04:44:03.226827 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3234 04:44:03.230185 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3235 04:44:03.233718 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3236 04:44:03.237114 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3237 04:44:03.237285
3238 04:44:03.237385
3239 04:44:03.237478 ==
3240 04:44:03.240326 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 04:44:03.243590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 04:44:03.243769 ==
3243 04:44:03.243870
3244 04:44:03.243962
3245 04:44:03.246740 TX Vref Scan disable
3246 04:44:03.250309 == TX Byte 0 ==
3247 04:44:03.253321 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3248 04:44:03.257184 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3249 04:44:03.260354 == TX Byte 1 ==
3250 04:44:03.263437 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3251 04:44:03.267105 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3252 04:44:03.267265 ==
3253 04:44:03.270424 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 04:44:03.273703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 04:44:03.273869 ==
3256 04:44:03.286796 TX Vref=22, minBit 9, minWin=24, winSum=412
3257 04:44:03.290166 TX Vref=24, minBit 10, minWin=25, winSum=418
3258 04:44:03.293795 TX Vref=26, minBit 9, minWin=25, winSum=422
3259 04:44:03.297270 TX Vref=28, minBit 1, minWin=26, winSum=427
3260 04:44:03.300035 TX Vref=30, minBit 2, minWin=26, winSum=431
3261 04:44:03.303571 TX Vref=32, minBit 9, minWin=25, winSum=430
3262 04:44:03.310442 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 30
3263 04:44:03.310624
3264 04:44:03.313844 Final TX Range 1 Vref 30
3265 04:44:03.313982
3266 04:44:03.314078 ==
3267 04:44:03.317395 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 04:44:03.319989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 04:44:03.320128 ==
3270 04:44:03.320231
3271 04:44:03.323888
3272 04:44:03.324029 TX Vref Scan disable
3273 04:44:03.326894 == TX Byte 0 ==
3274 04:44:03.330244 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3275 04:44:03.333671 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3276 04:44:03.336910 == TX Byte 1 ==
3277 04:44:03.340312 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3278 04:44:03.343660 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3279 04:44:03.343812
3280 04:44:03.347055 [DATLAT]
3281 04:44:03.347199 Freq=1200, CH1 RK0
3282 04:44:03.347301
3283 04:44:03.350462 DATLAT Default: 0xd
3284 04:44:03.350596 0, 0xFFFF, sum = 0
3285 04:44:03.353977 1, 0xFFFF, sum = 0
3286 04:44:03.354122 2, 0xFFFF, sum = 0
3287 04:44:03.357246 3, 0xFFFF, sum = 0
3288 04:44:03.357384 4, 0xFFFF, sum = 0
3289 04:44:03.360480 5, 0xFFFF, sum = 0
3290 04:44:03.360616 6, 0xFFFF, sum = 0
3291 04:44:03.363707 7, 0xFFFF, sum = 0
3292 04:44:03.363841 8, 0xFFFF, sum = 0
3293 04:44:03.366811 9, 0xFFFF, sum = 0
3294 04:44:03.370109 10, 0xFFFF, sum = 0
3295 04:44:03.370262 11, 0xFFFF, sum = 0
3296 04:44:03.373415 12, 0x0, sum = 1
3297 04:44:03.373554 13, 0x0, sum = 2
3298 04:44:03.373657 14, 0x0, sum = 3
3299 04:44:03.377330 15, 0x0, sum = 4
3300 04:44:03.377452 best_step = 13
3301 04:44:03.377519
3302 04:44:03.380253 ==
3303 04:44:03.380362 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 04:44:03.387156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 04:44:03.387325 ==
3306 04:44:03.387433 RX Vref Scan: 1
3307 04:44:03.387524
3308 04:44:03.390436 Set Vref Range= 32 -> 127
3309 04:44:03.390574
3310 04:44:03.393256 RX Vref 32 -> 127, step: 1
3311 04:44:03.393379
3312 04:44:03.396744 RX Delay -5 -> 252, step: 4
3313 04:44:03.396849
3314 04:44:03.400211 Set Vref, RX VrefLevel [Byte0]: 32
3315 04:44:03.403689 [Byte1]: 32
3316 04:44:03.403838
3317 04:44:03.407247 Set Vref, RX VrefLevel [Byte0]: 33
3318 04:44:03.410636 [Byte1]: 33
3319 04:44:03.410782
3320 04:44:03.413415 Set Vref, RX VrefLevel [Byte0]: 34
3321 04:44:03.416753 [Byte1]: 34
3322 04:44:03.420838
3323 04:44:03.421004 Set Vref, RX VrefLevel [Byte0]: 35
3324 04:44:03.424436 [Byte1]: 35
3325 04:44:03.428654
3326 04:44:03.428819 Set Vref, RX VrefLevel [Byte0]: 36
3327 04:44:03.432010 [Byte1]: 36
3328 04:44:03.436339
3329 04:44:03.436490 Set Vref, RX VrefLevel [Byte0]: 37
3330 04:44:03.439628 [Byte1]: 37
3331 04:44:03.444462
3332 04:44:03.444622 Set Vref, RX VrefLevel [Byte0]: 38
3333 04:44:03.447745 [Byte1]: 38
3334 04:44:03.452283
3335 04:44:03.452446 Set Vref, RX VrefLevel [Byte0]: 39
3336 04:44:03.455806 [Byte1]: 39
3337 04:44:03.459820
3338 04:44:03.459971 Set Vref, RX VrefLevel [Byte0]: 40
3339 04:44:03.463377 [Byte1]: 40
3340 04:44:03.468147
3341 04:44:03.468325 Set Vref, RX VrefLevel [Byte0]: 41
3342 04:44:03.471374 [Byte1]: 41
3343 04:44:03.475457
3344 04:44:03.475576 Set Vref, RX VrefLevel [Byte0]: 42
3345 04:44:03.478974 [Byte1]: 42
3346 04:44:03.483753
3347 04:44:03.483904 Set Vref, RX VrefLevel [Byte0]: 43
3348 04:44:03.486985 [Byte1]: 43
3349 04:44:03.491752
3350 04:44:03.491901 Set Vref, RX VrefLevel [Byte0]: 44
3351 04:44:03.494704 [Byte1]: 44
3352 04:44:03.499085
3353 04:44:03.499232 Set Vref, RX VrefLevel [Byte0]: 45
3354 04:44:03.502406 [Byte1]: 45
3355 04:44:03.507037
3356 04:44:03.507197 Set Vref, RX VrefLevel [Byte0]: 46
3357 04:44:03.510576 [Byte1]: 46
3358 04:44:03.514781
3359 04:44:03.514908 Set Vref, RX VrefLevel [Byte0]: 47
3360 04:44:03.518211 [Byte1]: 47
3361 04:44:03.523179
3362 04:44:03.523322 Set Vref, RX VrefLevel [Byte0]: 48
3363 04:44:03.526465 [Byte1]: 48
3364 04:44:03.530593
3365 04:44:03.530765 Set Vref, RX VrefLevel [Byte0]: 49
3366 04:44:03.534032 [Byte1]: 49
3367 04:44:03.538294
3368 04:44:03.538445 Set Vref, RX VrefLevel [Byte0]: 50
3369 04:44:03.541782 [Byte1]: 50
3370 04:44:03.546454
3371 04:44:03.546612 Set Vref, RX VrefLevel [Byte0]: 51
3372 04:44:03.549806 [Byte1]: 51
3373 04:44:03.554278
3374 04:44:03.554435 Set Vref, RX VrefLevel [Byte0]: 52
3375 04:44:03.557465 [Byte1]: 52
3376 04:44:03.562535
3377 04:44:03.562682 Set Vref, RX VrefLevel [Byte0]: 53
3378 04:44:03.565239 [Byte1]: 53
3379 04:44:03.569720
3380 04:44:03.569843 Set Vref, RX VrefLevel [Byte0]: 54
3381 04:44:03.573578 [Byte1]: 54
3382 04:44:03.578081
3383 04:44:03.578210 Set Vref, RX VrefLevel [Byte0]: 55
3384 04:44:03.581450 [Byte1]: 55
3385 04:44:03.585323
3386 04:44:03.585453 Set Vref, RX VrefLevel [Byte0]: 56
3387 04:44:03.588658 [Byte1]: 56
3388 04:44:03.593551
3389 04:44:03.593691 Set Vref, RX VrefLevel [Byte0]: 57
3390 04:44:03.596973 [Byte1]: 57
3391 04:44:03.601633
3392 04:44:03.601768 Set Vref, RX VrefLevel [Byte0]: 58
3393 04:44:03.604957 [Byte1]: 58
3394 04:44:03.609463
3395 04:44:03.609616 Set Vref, RX VrefLevel [Byte0]: 59
3396 04:44:03.612583 [Byte1]: 59
3397 04:44:03.617119
3398 04:44:03.617249 Set Vref, RX VrefLevel [Byte0]: 60
3399 04:44:03.620397 [Byte1]: 60
3400 04:44:03.625078
3401 04:44:03.625233 Set Vref, RX VrefLevel [Byte0]: 61
3402 04:44:03.628433 [Byte1]: 61
3403 04:44:03.632705
3404 04:44:03.632873 Set Vref, RX VrefLevel [Byte0]: 62
3405 04:44:03.636085 [Byte1]: 62
3406 04:44:03.640907
3407 04:44:03.641059 Set Vref, RX VrefLevel [Byte0]: 63
3408 04:44:03.643703 [Byte1]: 63
3409 04:44:03.648462
3410 04:44:03.648593 Set Vref, RX VrefLevel [Byte0]: 64
3411 04:44:03.651884 [Byte1]: 64
3412 04:44:03.656017
3413 04:44:03.656166 Set Vref, RX VrefLevel [Byte0]: 65
3414 04:44:03.659363 [Byte1]: 65
3415 04:44:03.664105
3416 04:44:03.664275 Set Vref, RX VrefLevel [Byte0]: 66
3417 04:44:03.667449 [Byte1]: 66
3418 04:44:03.672196
3419 04:44:03.672372 Set Vref, RX VrefLevel [Byte0]: 67
3420 04:44:03.675546 [Byte1]: 67
3421 04:44:03.679854
3422 04:44:03.679971 Set Vref, RX VrefLevel [Byte0]: 68
3423 04:44:03.682917 [Byte1]: 68
3424 04:44:03.687613
3425 04:44:03.687741 Set Vref, RX VrefLevel [Byte0]: 69
3426 04:44:03.690790 [Byte1]: 69
3427 04:44:03.695580
3428 04:44:03.695723 Set Vref, RX VrefLevel [Byte0]: 70
3429 04:44:03.699115 [Byte1]: 70
3430 04:44:03.703420
3431 04:44:03.703576 Final RX Vref Byte 0 = 52 to rank0
3432 04:44:03.706850 Final RX Vref Byte 1 = 49 to rank0
3433 04:44:03.710048 Final RX Vref Byte 0 = 52 to rank1
3434 04:44:03.713199 Final RX Vref Byte 1 = 49 to rank1==
3435 04:44:03.716596 Dram Type= 6, Freq= 0, CH_1, rank 0
3436 04:44:03.723631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3437 04:44:03.723777 ==
3438 04:44:03.723846 DQS Delay:
3439 04:44:03.723909 DQS0 = 0, DQS1 = 0
3440 04:44:03.726699 DQM Delay:
3441 04:44:03.726785 DQM0 = 120, DQM1 = 116
3442 04:44:03.730162 DQ Delay:
3443 04:44:03.733740 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3444 04:44:03.737226 DQ4 =118, DQ5 =130, DQ6 =130, DQ7 =120
3445 04:44:03.740553 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3446 04:44:03.743363 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3447 04:44:03.743488
3448 04:44:03.743562
3449 04:44:03.750420 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe11, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3450 04:44:03.753929 CH1 RK0: MR19=304, MR18=FE11
3451 04:44:03.760112 CH1_RK0: MR19=0x304, MR18=0xFE11, DQSOSC=403, MR23=63, INC=40, DEC=26
3452 04:44:03.760262
3453 04:44:03.763394 ----->DramcWriteLeveling(PI) begin...
3454 04:44:03.763501 ==
3455 04:44:03.766838 Dram Type= 6, Freq= 0, CH_1, rank 1
3456 04:44:03.770290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3457 04:44:03.770416 ==
3458 04:44:03.773773 Write leveling (Byte 0): 25 => 25
3459 04:44:03.777185 Write leveling (Byte 1): 30 => 30
3460 04:44:03.780661 DramcWriteLeveling(PI) end<-----
3461 04:44:03.780778
3462 04:44:03.780847 ==
3463 04:44:03.783415 Dram Type= 6, Freq= 0, CH_1, rank 1
3464 04:44:03.786832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3465 04:44:03.790167 ==
3466 04:44:03.790280 [Gating] SW mode calibration
3467 04:44:03.800694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3468 04:44:03.803807 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3469 04:44:03.806980 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 04:44:03.813671 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 04:44:03.817145 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 04:44:03.820217 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3473 04:44:03.827518 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 04:44:03.830428 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3475 04:44:03.833796 0 15 24 | B1->B0 | 2a2a 3232 | 0 1 | (0 1) (1 0)
3476 04:44:03.840163 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3477 04:44:03.843550 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 04:44:03.847309 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 04:44:03.853534 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 04:44:03.857339 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3481 04:44:03.860811 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 04:44:03.863584 1 0 20 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
3483 04:44:03.870528 1 0 24 | B1->B0 | 4444 2b2b | 0 0 | (0 0) (0 0)
3484 04:44:03.873978 1 0 28 | B1->B0 | 4646 4242 | 0 1 | (0 0) (0 0)
3485 04:44:03.877464 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 04:44:03.883752 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 04:44:03.887109 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 04:44:03.890705 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 04:44:03.896863 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 04:44:03.900304 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 04:44:03.903665 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3492 04:44:03.910395 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3493 04:44:03.913840 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 04:44:03.917115 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 04:44:03.923896 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 04:44:03.926609 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 04:44:03.930521 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 04:44:03.936712 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 04:44:03.940463 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 04:44:03.943789 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 04:44:03.950284 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 04:44:03.953503 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 04:44:03.956609 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 04:44:03.963594 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 04:44:03.966450 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 04:44:03.970348 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3507 04:44:03.976624 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3508 04:44:03.979789 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3509 04:44:03.983159 Total UI for P1: 0, mck2ui 16
3510 04:44:03.986621 best dqsien dly found for B1: ( 1, 3, 22)
3511 04:44:03.990157 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 04:44:03.992933 Total UI for P1: 0, mck2ui 16
3513 04:44:03.996372 best dqsien dly found for B0: ( 1, 3, 28)
3514 04:44:03.999765 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3515 04:44:04.003180 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3516 04:44:04.003300
3517 04:44:04.006720 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3518 04:44:04.012806 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3519 04:44:04.012942 [Gating] SW calibration Done
3520 04:44:04.016746 ==
3521 04:44:04.016864 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 04:44:04.022865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 04:44:04.023006 ==
3524 04:44:04.023078 RX Vref Scan: 0
3525 04:44:04.023140
3526 04:44:04.026143 RX Vref 0 -> 0, step: 1
3527 04:44:04.026267
3528 04:44:04.029596 RX Delay -40 -> 252, step: 8
3529 04:44:04.032999 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3530 04:44:04.036442 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3531 04:44:04.039820 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3532 04:44:04.046275 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3533 04:44:04.049486 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3534 04:44:04.052639 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3535 04:44:04.056071 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3536 04:44:04.059631 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3537 04:44:04.066283 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3538 04:44:04.069542 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3539 04:44:04.072691 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3540 04:44:04.076165 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3541 04:44:04.079233 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3542 04:44:04.086169 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3543 04:44:04.089286 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3544 04:44:04.092752 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3545 04:44:04.092882 ==
3546 04:44:04.095864 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 04:44:04.099616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 04:44:04.102827 ==
3549 04:44:04.102969 DQS Delay:
3550 04:44:04.103073 DQS0 = 0, DQS1 = 0
3551 04:44:04.106309 DQM Delay:
3552 04:44:04.106428 DQM0 = 120, DQM1 = 118
3553 04:44:04.109113 DQ Delay:
3554 04:44:04.112679 DQ0 =127, DQ1 =119, DQ2 =107, DQ3 =115
3555 04:44:04.115990 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3556 04:44:04.119317 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3557 04:44:04.122665 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3558 04:44:04.122846
3559 04:44:04.122948
3560 04:44:04.123050 ==
3561 04:44:04.126238 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 04:44:04.129558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 04:44:04.129693 ==
3564 04:44:04.129796
3565 04:44:04.129902
3566 04:44:04.132789 TX Vref Scan disable
3567 04:44:04.136192 == TX Byte 0 ==
3568 04:44:04.139461 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3569 04:44:04.142307 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3570 04:44:04.145741 == TX Byte 1 ==
3571 04:44:04.149053 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3572 04:44:04.152410 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3573 04:44:04.152529 ==
3574 04:44:04.155736 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 04:44:04.162283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 04:44:04.162444 ==
3577 04:44:04.173477 TX Vref=22, minBit 0, minWin=26, winSum=424
3578 04:44:04.176316 TX Vref=24, minBit 2, minWin=26, winSum=424
3579 04:44:04.179786 TX Vref=26, minBit 2, minWin=26, winSum=430
3580 04:44:04.183005 TX Vref=28, minBit 10, minWin=25, winSum=434
3581 04:44:04.186121 TX Vref=30, minBit 9, minWin=26, winSum=435
3582 04:44:04.192939 TX Vref=32, minBit 9, minWin=26, winSum=434
3583 04:44:04.196348 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3584 04:44:04.196508
3585 04:44:04.199676 Final TX Range 1 Vref 30
3586 04:44:04.199814
3587 04:44:04.199910 ==
3588 04:44:04.202849 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 04:44:04.206607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 04:44:04.206733 ==
3591 04:44:04.209804
3592 04:44:04.209923
3593 04:44:04.210000 TX Vref Scan disable
3594 04:44:04.212793 == TX Byte 0 ==
3595 04:44:04.216518 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3596 04:44:04.219563 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3597 04:44:04.222998 == TX Byte 1 ==
3598 04:44:04.226120 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3599 04:44:04.229539 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3600 04:44:04.229670
3601 04:44:04.232900 [DATLAT]
3602 04:44:04.233012 Freq=1200, CH1 RK1
3603 04:44:04.233112
3604 04:44:04.236175 DATLAT Default: 0xd
3605 04:44:04.236309 0, 0xFFFF, sum = 0
3606 04:44:04.239979 1, 0xFFFF, sum = 0
3607 04:44:04.240120 2, 0xFFFF, sum = 0
3608 04:44:04.242723 3, 0xFFFF, sum = 0
3609 04:44:04.242853 4, 0xFFFF, sum = 0
3610 04:44:04.246243 5, 0xFFFF, sum = 0
3611 04:44:04.246378 6, 0xFFFF, sum = 0
3612 04:44:04.249705 7, 0xFFFF, sum = 0
3613 04:44:04.253258 8, 0xFFFF, sum = 0
3614 04:44:04.253405 9, 0xFFFF, sum = 0
3615 04:44:04.256274 10, 0xFFFF, sum = 0
3616 04:44:04.256410 11, 0xFFFF, sum = 0
3617 04:44:04.259809 12, 0x0, sum = 1
3618 04:44:04.259943 13, 0x0, sum = 2
3619 04:44:04.262941 14, 0x0, sum = 3
3620 04:44:04.263078 15, 0x0, sum = 4
3621 04:44:04.263179 best_step = 13
3622 04:44:04.266115
3623 04:44:04.266241 ==
3624 04:44:04.269358 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 04:44:04.272850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 04:44:04.272995 ==
3627 04:44:04.273101 RX Vref Scan: 0
3628 04:44:04.273201
3629 04:44:04.276315 RX Vref 0 -> 0, step: 1
3630 04:44:04.276441
3631 04:44:04.279130 RX Delay -5 -> 252, step: 4
3632 04:44:04.282553 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3633 04:44:04.289337 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3634 04:44:04.292705 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3635 04:44:04.295923 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3636 04:44:04.299096 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3637 04:44:04.302639 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3638 04:44:04.308814 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3639 04:44:04.312225 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3640 04:44:04.315632 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3641 04:44:04.318851 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3642 04:44:04.322023 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3643 04:44:04.328968 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3644 04:44:04.332256 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3645 04:44:04.335257 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3646 04:44:04.338836 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3647 04:44:04.345262 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3648 04:44:04.345452 ==
3649 04:44:04.348600 Dram Type= 6, Freq= 0, CH_1, rank 1
3650 04:44:04.352306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3651 04:44:04.352441 ==
3652 04:44:04.352517 DQS Delay:
3653 04:44:04.355129 DQS0 = 0, DQS1 = 0
3654 04:44:04.355250 DQM Delay:
3655 04:44:04.358521 DQM0 = 120, DQM1 = 117
3656 04:44:04.358645 DQ Delay:
3657 04:44:04.361818 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3658 04:44:04.365107 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3659 04:44:04.368455 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3660 04:44:04.371761 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =126
3661 04:44:04.371906
3662 04:44:04.372004
3663 04:44:04.381726 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3664 04:44:04.385068 CH1 RK1: MR19=403, MR18=13F1
3665 04:44:04.391950 CH1_RK1: MR19=0x403, MR18=0x13F1, DQSOSC=402, MR23=63, INC=40, DEC=27
3666 04:44:04.392121 [RxdqsGatingPostProcess] freq 1200
3667 04:44:04.398096 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3668 04:44:04.401490 best DQS0 dly(2T, 0.5T) = (0, 11)
3669 04:44:04.405306 best DQS1 dly(2T, 0.5T) = (0, 11)
3670 04:44:04.408708 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3671 04:44:04.411435 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3672 04:44:04.414997 best DQS0 dly(2T, 0.5T) = (0, 11)
3673 04:44:04.418465 best DQS1 dly(2T, 0.5T) = (0, 11)
3674 04:44:04.421905 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3675 04:44:04.425312 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3676 04:44:04.428031 Pre-setting of DQS Precalculation
3677 04:44:04.431398 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3678 04:44:04.438050 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3679 04:44:04.444838 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3680 04:44:04.448106
3681 04:44:04.448247
3682 04:44:04.448350 [Calibration Summary] 2400 Mbps
3683 04:44:04.451356 CH 0, Rank 0
3684 04:44:04.451464 SW Impedance : PASS
3685 04:44:04.454867 DUTY Scan : NO K
3686 04:44:04.457851 ZQ Calibration : PASS
3687 04:44:04.457980 Jitter Meter : NO K
3688 04:44:04.461213 CBT Training : PASS
3689 04:44:04.464691 Write leveling : PASS
3690 04:44:04.464839 RX DQS gating : PASS
3691 04:44:04.467850 RX DQ/DQS(RDDQC) : PASS
3692 04:44:04.471567 TX DQ/DQS : PASS
3693 04:44:04.471714 RX DATLAT : PASS
3694 04:44:04.474644 RX DQ/DQS(Engine): PASS
3695 04:44:04.478387 TX OE : NO K
3696 04:44:04.478543 All Pass.
3697 04:44:04.478645
3698 04:44:04.478748 CH 0, Rank 1
3699 04:44:04.481589 SW Impedance : PASS
3700 04:44:04.484659 DUTY Scan : NO K
3701 04:44:04.484783 ZQ Calibration : PASS
3702 04:44:04.488032 Jitter Meter : NO K
3703 04:44:04.491416 CBT Training : PASS
3704 04:44:04.491557 Write leveling : PASS
3705 04:44:04.494955 RX DQS gating : PASS
3706 04:44:04.495095 RX DQ/DQS(RDDQC) : PASS
3707 04:44:04.498366 TX DQ/DQS : PASS
3708 04:44:04.501082 RX DATLAT : PASS
3709 04:44:04.501206 RX DQ/DQS(Engine): PASS
3710 04:44:04.505080 TX OE : NO K
3711 04:44:04.505191 All Pass.
3712 04:44:04.505262
3713 04:44:04.507886 CH 1, Rank 0
3714 04:44:04.508006 SW Impedance : PASS
3715 04:44:04.511269 DUTY Scan : NO K
3716 04:44:04.514704 ZQ Calibration : PASS
3717 04:44:04.514838 Jitter Meter : NO K
3718 04:44:04.517972 CBT Training : PASS
3719 04:44:04.521468 Write leveling : PASS
3720 04:44:04.521577 RX DQS gating : PASS
3721 04:44:04.524929 RX DQ/DQS(RDDQC) : PASS
3722 04:44:04.527632 TX DQ/DQS : PASS
3723 04:44:04.527755 RX DATLAT : PASS
3724 04:44:04.531087 RX DQ/DQS(Engine): PASS
3725 04:44:04.534439 TX OE : NO K
3726 04:44:04.534580 All Pass.
3727 04:44:04.534678
3728 04:44:04.534768 CH 1, Rank 1
3729 04:44:04.537957 SW Impedance : PASS
3730 04:44:04.541294 DUTY Scan : NO K
3731 04:44:04.541439 ZQ Calibration : PASS
3732 04:44:04.544596 Jitter Meter : NO K
3733 04:44:04.544696 CBT Training : PASS
3734 04:44:04.547843 Write leveling : PASS
3735 04:44:04.551287 RX DQS gating : PASS
3736 04:44:04.551433 RX DQ/DQS(RDDQC) : PASS
3737 04:44:04.554786 TX DQ/DQS : PASS
3738 04:44:04.558114 RX DATLAT : PASS
3739 04:44:04.558257 RX DQ/DQS(Engine): PASS
3740 04:44:04.561039 TX OE : NO K
3741 04:44:04.561167 All Pass.
3742 04:44:04.561273
3743 04:44:04.564455 DramC Write-DBI off
3744 04:44:04.567715 PER_BANK_REFRESH: Hybrid Mode
3745 04:44:04.567847 TX_TRACKING: ON
3746 04:44:04.577981 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3747 04:44:04.580965 [FAST_K] Save calibration result to emmc
3748 04:44:04.584509 dramc_set_vcore_voltage set vcore to 650000
3749 04:44:04.587838 Read voltage for 600, 5
3750 04:44:04.587991 Vio18 = 0
3751 04:44:04.588103 Vcore = 650000
3752 04:44:04.590856 Vdram = 0
3753 04:44:04.590977 Vddq = 0
3754 04:44:04.591085 Vmddr = 0
3755 04:44:04.597611 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3756 04:44:04.600862 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3757 04:44:04.604245 MEM_TYPE=3, freq_sel=19
3758 04:44:04.607626 sv_algorithm_assistance_LP4_1600
3759 04:44:04.610879 ============ PULL DRAM RESETB DOWN ============
3760 04:44:04.614317 ========== PULL DRAM RESETB DOWN end =========
3761 04:44:04.621150 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3762 04:44:04.624410 ===================================
3763 04:44:04.627797 LPDDR4 DRAM CONFIGURATION
3764 04:44:04.630615 ===================================
3765 04:44:04.630763 EX_ROW_EN[0] = 0x0
3766 04:44:04.633946 EX_ROW_EN[1] = 0x0
3767 04:44:04.634096 LP4Y_EN = 0x0
3768 04:44:04.637458 WORK_FSP = 0x0
3769 04:44:04.637583 WL = 0x2
3770 04:44:04.640776 RL = 0x2
3771 04:44:04.640888 BL = 0x2
3772 04:44:04.644163 RPST = 0x0
3773 04:44:04.644295 RD_PRE = 0x0
3774 04:44:04.647452 WR_PRE = 0x1
3775 04:44:04.647589 WR_PST = 0x0
3776 04:44:04.650805 DBI_WR = 0x0
3777 04:44:04.653990 DBI_RD = 0x0
3778 04:44:04.654123 OTF = 0x1
3779 04:44:04.657332 ===================================
3780 04:44:04.660933 ===================================
3781 04:44:04.661104 ANA top config
3782 04:44:04.664261 ===================================
3783 04:44:04.667107 DLL_ASYNC_EN = 0
3784 04:44:04.670537 ALL_SLAVE_EN = 1
3785 04:44:04.673799 NEW_RANK_MODE = 1
3786 04:44:04.677032 DLL_IDLE_MODE = 1
3787 04:44:04.677196 LP45_APHY_COMB_EN = 1
3788 04:44:04.680626 TX_ODT_DIS = 1
3789 04:44:04.684014 NEW_8X_MODE = 1
3790 04:44:04.687368 ===================================
3791 04:44:04.690675 ===================================
3792 04:44:04.694001 data_rate = 1200
3793 04:44:04.697353 CKR = 1
3794 04:44:04.697487 DQ_P2S_RATIO = 8
3795 04:44:04.700549 ===================================
3796 04:44:04.704002 CA_P2S_RATIO = 8
3797 04:44:04.707623 DQ_CA_OPEN = 0
3798 04:44:04.710785 DQ_SEMI_OPEN = 0
3799 04:44:04.713612 CA_SEMI_OPEN = 0
3800 04:44:04.713736 CA_FULL_RATE = 0
3801 04:44:04.717291 DQ_CKDIV4_EN = 1
3802 04:44:04.720743 CA_CKDIV4_EN = 1
3803 04:44:04.723614 CA_PREDIV_EN = 0
3804 04:44:04.726900 PH8_DLY = 0
3805 04:44:04.730414 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3806 04:44:04.730580 DQ_AAMCK_DIV = 4
3807 04:44:04.734114 CA_AAMCK_DIV = 4
3808 04:44:04.737174 CA_ADMCK_DIV = 4
3809 04:44:04.740363 DQ_TRACK_CA_EN = 0
3810 04:44:04.743721 CA_PICK = 600
3811 04:44:04.747153 CA_MCKIO = 600
3812 04:44:04.750642 MCKIO_SEMI = 0
3813 04:44:04.750794 PLL_FREQ = 2288
3814 04:44:04.754087 DQ_UI_PI_RATIO = 32
3815 04:44:04.757424 CA_UI_PI_RATIO = 0
3816 04:44:04.760633 ===================================
3817 04:44:04.764129 ===================================
3818 04:44:04.767546 memory_type:LPDDR4
3819 04:44:04.767657 GP_NUM : 10
3820 04:44:04.770354 SRAM_EN : 1
3821 04:44:04.773829 MD32_EN : 0
3822 04:44:04.777178 ===================================
3823 04:44:04.777291 [ANA_INIT] >>>>>>>>>>>>>>
3824 04:44:04.780494 <<<<<< [CONFIGURE PHASE]: ANA_TX
3825 04:44:04.783644 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3826 04:44:04.787051 ===================================
3827 04:44:04.790388 data_rate = 1200,PCW = 0X5800
3828 04:44:04.793997 ===================================
3829 04:44:04.797504 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3830 04:44:04.803677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3831 04:44:04.807151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3832 04:44:04.813913 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3833 04:44:04.817010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3834 04:44:04.820247 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3835 04:44:04.820383 [ANA_INIT] flow start
3836 04:44:04.823591 [ANA_INIT] PLL >>>>>>>>
3837 04:44:04.826953 [ANA_INIT] PLL <<<<<<<<
3838 04:44:04.830471 [ANA_INIT] MIDPI >>>>>>>>
3839 04:44:04.830602 [ANA_INIT] MIDPI <<<<<<<<
3840 04:44:04.833630 [ANA_INIT] DLL >>>>>>>>
3841 04:44:04.833725 [ANA_INIT] flow end
3842 04:44:04.840526 ============ LP4 DIFF to SE enter ============
3843 04:44:04.843553 ============ LP4 DIFF to SE exit ============
3844 04:44:04.847236 [ANA_INIT] <<<<<<<<<<<<<
3845 04:44:04.850430 [Flow] Enable top DCM control >>>>>
3846 04:44:04.853684 [Flow] Enable top DCM control <<<<<
3847 04:44:04.853810 Enable DLL master slave shuffle
3848 04:44:04.860728 ==============================================================
3849 04:44:04.864021 Gating Mode config
3850 04:44:04.867230 ==============================================================
3851 04:44:04.870608 Config description:
3852 04:44:04.880699 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3853 04:44:04.887354 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3854 04:44:04.890651 SELPH_MODE 0: By rank 1: By Phase
3855 04:44:04.896802 ==============================================================
3856 04:44:04.900192 GAT_TRACK_EN = 1
3857 04:44:04.903694 RX_GATING_MODE = 2
3858 04:44:04.907171 RX_GATING_TRACK_MODE = 2
3859 04:44:04.910670 SELPH_MODE = 1
3860 04:44:04.910779 PICG_EARLY_EN = 1
3861 04:44:04.913477 VALID_LAT_VALUE = 1
3862 04:44:04.920402 ==============================================================
3863 04:44:04.923611 Enter into Gating configuration >>>>
3864 04:44:04.926900 Exit from Gating configuration <<<<
3865 04:44:04.930211 Enter into DVFS_PRE_config >>>>>
3866 04:44:04.940131 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3867 04:44:04.943435 Exit from DVFS_PRE_config <<<<<
3868 04:44:04.946689 Enter into PICG configuration >>>>
3869 04:44:04.950089 Exit from PICG configuration <<<<
3870 04:44:04.953605 [RX_INPUT] configuration >>>>>
3871 04:44:04.956871 [RX_INPUT] configuration <<<<<
3872 04:44:04.960127 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3873 04:44:04.966958 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3874 04:44:04.973617 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3875 04:44:04.979670 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3876 04:44:04.986305 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3877 04:44:04.990232 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3878 04:44:04.996602 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3879 04:44:04.999928 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3880 04:44:05.003395 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3881 04:44:05.006194 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3882 04:44:05.013189 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3883 04:44:05.016717 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3884 04:44:05.020217 ===================================
3885 04:44:05.023058 LPDDR4 DRAM CONFIGURATION
3886 04:44:05.026373 ===================================
3887 04:44:05.026469 EX_ROW_EN[0] = 0x0
3888 04:44:05.029700 EX_ROW_EN[1] = 0x0
3889 04:44:05.029818 LP4Y_EN = 0x0
3890 04:44:05.033181 WORK_FSP = 0x0
3891 04:44:05.033326 WL = 0x2
3892 04:44:05.036643 RL = 0x2
3893 04:44:05.036791 BL = 0x2
3894 04:44:05.039982 RPST = 0x0
3895 04:44:05.040113 RD_PRE = 0x0
3896 04:44:05.043223 WR_PRE = 0x1
3897 04:44:05.043356 WR_PST = 0x0
3898 04:44:05.046535 DBI_WR = 0x0
3899 04:44:05.049739 DBI_RD = 0x0
3900 04:44:05.049882 OTF = 0x1
3901 04:44:05.053415 ===================================
3902 04:44:05.056382 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3903 04:44:05.060089 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3904 04:44:05.066629 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3905 04:44:05.069982 ===================================
3906 04:44:05.073433 LPDDR4 DRAM CONFIGURATION
3907 04:44:05.073554 ===================================
3908 04:44:05.076916 EX_ROW_EN[0] = 0x10
3909 04:44:05.079689 EX_ROW_EN[1] = 0x0
3910 04:44:05.079773 LP4Y_EN = 0x0
3911 04:44:05.083153 WORK_FSP = 0x0
3912 04:44:05.083245 WL = 0x2
3913 04:44:05.086632 RL = 0x2
3914 04:44:05.086714 BL = 0x2
3915 04:44:05.089841 RPST = 0x0
3916 04:44:05.089933 RD_PRE = 0x0
3917 04:44:05.093059 WR_PRE = 0x1
3918 04:44:05.093140 WR_PST = 0x0
3919 04:44:05.096796 DBI_WR = 0x0
3920 04:44:05.096881 DBI_RD = 0x0
3921 04:44:05.099877 OTF = 0x1
3922 04:44:05.103500 ===================================
3923 04:44:05.110011 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3924 04:44:05.113507 nWR fixed to 30
3925 04:44:05.113607 [ModeRegInit_LP4] CH0 RK0
3926 04:44:05.116865 [ModeRegInit_LP4] CH0 RK1
3927 04:44:05.119671 [ModeRegInit_LP4] CH1 RK0
3928 04:44:05.123039 [ModeRegInit_LP4] CH1 RK1
3929 04:44:05.123156 match AC timing 17
3930 04:44:05.129956 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3931 04:44:05.133298 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3932 04:44:05.136800 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3933 04:44:05.142997 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3934 04:44:05.146342 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3935 04:44:05.146445 ==
3936 04:44:05.149822 Dram Type= 6, Freq= 0, CH_0, rank 0
3937 04:44:05.153289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3938 04:44:05.153404 ==
3939 04:44:05.160080 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3940 04:44:05.166283 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3941 04:44:05.170030 [CA 0] Center 35 (5~66) winsize 62
3942 04:44:05.172787 [CA 1] Center 35 (5~66) winsize 62
3943 04:44:05.176409 [CA 2] Center 33 (3~64) winsize 62
3944 04:44:05.179411 [CA 3] Center 33 (2~64) winsize 63
3945 04:44:05.183326 [CA 4] Center 33 (2~64) winsize 63
3946 04:44:05.186630 [CA 5] Center 32 (2~63) winsize 62
3947 04:44:05.186740
3948 04:44:05.189338 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3949 04:44:05.189422
3950 04:44:05.192770 [CATrainingPosCal] consider 1 rank data
3951 04:44:05.196152 u2DelayCellTimex100 = 270/100 ps
3952 04:44:05.199582 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3953 04:44:05.202960 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3954 04:44:05.206318 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3955 04:44:05.209752 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3956 04:44:05.212815 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3957 04:44:05.216017 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3958 04:44:05.216148
3959 04:44:05.222845 CA PerBit enable=1, Macro0, CA PI delay=32
3960 04:44:05.223004
3961 04:44:05.223110 [CBTSetCACLKResult] CA Dly = 32
3962 04:44:05.225797 CS Dly: 4 (0~35)
3963 04:44:05.225917 ==
3964 04:44:05.229726 Dram Type= 6, Freq= 0, CH_0, rank 1
3965 04:44:05.232437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 04:44:05.232544 ==
3967 04:44:05.239389 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3968 04:44:05.246153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3969 04:44:05.249397 [CA 0] Center 35 (5~66) winsize 62
3970 04:44:05.252951 [CA 1] Center 35 (5~66) winsize 62
3971 04:44:05.256194 [CA 2] Center 33 (3~64) winsize 62
3972 04:44:05.259674 [CA 3] Center 33 (3~64) winsize 62
3973 04:44:05.262376 [CA 4] Center 32 (2~63) winsize 62
3974 04:44:05.265787 [CA 5] Center 32 (2~63) winsize 62
3975 04:44:05.265893
3976 04:44:05.269175 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3977 04:44:05.269262
3978 04:44:05.272631 [CATrainingPosCal] consider 2 rank data
3979 04:44:05.276095 u2DelayCellTimex100 = 270/100 ps
3980 04:44:05.279434 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3981 04:44:05.282606 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3982 04:44:05.285668 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3983 04:44:05.288910 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3984 04:44:05.292590 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3985 04:44:05.296036 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3986 04:44:05.298924
3987 04:44:05.302196 CA PerBit enable=1, Macro0, CA PI delay=32
3988 04:44:05.302301
3989 04:44:05.306162 [CBTSetCACLKResult] CA Dly = 32
3990 04:44:05.306276 CS Dly: 4 (0~36)
3991 04:44:05.306343
3992 04:44:05.308905 ----->DramcWriteLeveling(PI) begin...
3993 04:44:05.309002 ==
3994 04:44:05.312397 Dram Type= 6, Freq= 0, CH_0, rank 0
3995 04:44:05.315669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3996 04:44:05.318943 ==
3997 04:44:05.319058 Write leveling (Byte 0): 36 => 36
3998 04:44:05.322436 Write leveling (Byte 1): 32 => 32
3999 04:44:05.325879 DramcWriteLeveling(PI) end<-----
4000 04:44:05.325983
4001 04:44:05.326053 ==
4002 04:44:05.329285 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 04:44:05.335931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 04:44:05.336050 ==
4005 04:44:05.339015 [Gating] SW mode calibration
4006 04:44:05.345351 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4007 04:44:05.348854 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4008 04:44:05.352195 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4009 04:44:05.359057 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4010 04:44:05.362394 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4011 04:44:05.365670 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
4012 04:44:05.372581 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
4013 04:44:05.375431 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 04:44:05.378842 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 04:44:05.385639 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 04:44:05.389047 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 04:44:05.392319 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 04:44:05.399174 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 04:44:05.401926 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
4020 04:44:05.405254 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
4021 04:44:05.411736 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 04:44:05.415220 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 04:44:05.418589 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 04:44:05.425013 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 04:44:05.428944 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 04:44:05.431780 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 04:44:05.438668 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4028 04:44:05.442026 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4029 04:44:05.445360 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 04:44:05.451912 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 04:44:05.455129 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 04:44:05.458859 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 04:44:05.465334 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 04:44:05.468739 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 04:44:05.471920 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 04:44:05.478755 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 04:44:05.481502 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 04:44:05.485053 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 04:44:05.492039 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 04:44:05.495534 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 04:44:05.498759 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 04:44:05.505221 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 04:44:05.508526 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 04:44:05.511922 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4045 04:44:05.514664 Total UI for P1: 0, mck2ui 16
4046 04:44:05.518083 best dqsien dly found for B0: ( 0, 13, 14)
4047 04:44:05.521552 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 04:44:05.524920 Total UI for P1: 0, mck2ui 16
4049 04:44:05.528723 best dqsien dly found for B1: ( 0, 13, 16)
4050 04:44:05.531812 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4051 04:44:05.534903 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4052 04:44:05.538354
4053 04:44:05.541695 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4054 04:44:05.545011 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4055 04:44:05.547990 [Gating] SW calibration Done
4056 04:44:05.548123 ==
4057 04:44:05.551274 Dram Type= 6, Freq= 0, CH_0, rank 0
4058 04:44:05.554675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4059 04:44:05.554806 ==
4060 04:44:05.554902 RX Vref Scan: 0
4061 04:44:05.558128
4062 04:44:05.558247 RX Vref 0 -> 0, step: 1
4063 04:44:05.558344
4064 04:44:05.561546 RX Delay -230 -> 252, step: 16
4065 04:44:05.564796 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4066 04:44:05.571498 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4067 04:44:05.574737 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4068 04:44:05.577983 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4069 04:44:05.581252 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4070 04:44:05.584412 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4071 04:44:05.591420 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4072 04:44:05.594457 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4073 04:44:05.597955 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4074 04:44:05.601303 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4075 04:44:05.608031 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4076 04:44:05.611540 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4077 04:44:05.614328 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4078 04:44:05.617841 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4079 04:44:05.624183 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4080 04:44:05.627641 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4081 04:44:05.627745 ==
4082 04:44:05.631098 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 04:44:05.634571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 04:44:05.634717 ==
4085 04:44:05.638052 DQS Delay:
4086 04:44:05.638180 DQS0 = 0, DQS1 = 0
4087 04:44:05.638278 DQM Delay:
4088 04:44:05.641416 DQM0 = 54, DQM1 = 46
4089 04:44:05.641541 DQ Delay:
4090 04:44:05.644724 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4091 04:44:05.647837 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4092 04:44:05.651184 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4093 04:44:05.654272 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4094 04:44:05.654417
4095 04:44:05.654522
4096 04:44:05.654698 ==
4097 04:44:05.657909 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 04:44:05.660920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 04:44:05.664575 ==
4100 04:44:05.664711
4101 04:44:05.664820
4102 04:44:05.664912 TX Vref Scan disable
4103 04:44:05.667686 == TX Byte 0 ==
4104 04:44:05.671058 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4105 04:44:05.674284 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4106 04:44:05.677415 == TX Byte 1 ==
4107 04:44:05.680863 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4108 04:44:05.687722 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4109 04:44:05.687887 ==
4110 04:44:05.691017 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 04:44:05.694441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 04:44:05.694580 ==
4113 04:44:05.694680
4114 04:44:05.694772
4115 04:44:05.697670 TX Vref Scan disable
4116 04:44:05.700948 == TX Byte 0 ==
4117 04:44:05.703972 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4118 04:44:05.707263 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4119 04:44:05.710715 == TX Byte 1 ==
4120 04:44:05.714397 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4121 04:44:05.717138 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4122 04:44:05.717263
4123 04:44:05.717360 [DATLAT]
4124 04:44:05.720690 Freq=600, CH0 RK0
4125 04:44:05.720812
4126 04:44:05.720920 DATLAT Default: 0x9
4127 04:44:05.724184 0, 0xFFFF, sum = 0
4128 04:44:05.727663 1, 0xFFFF, sum = 0
4129 04:44:05.727791 2, 0xFFFF, sum = 0
4130 04:44:05.730502 3, 0xFFFF, sum = 0
4131 04:44:05.730611 4, 0xFFFF, sum = 0
4132 04:44:05.733907 5, 0xFFFF, sum = 0
4133 04:44:05.734046 6, 0xFFFF, sum = 0
4134 04:44:05.737256 7, 0xFFFF, sum = 0
4135 04:44:05.737384 8, 0x0, sum = 1
4136 04:44:05.740589 9, 0x0, sum = 2
4137 04:44:05.740688 10, 0x0, sum = 3
4138 04:44:05.740789 11, 0x0, sum = 4
4139 04:44:05.744114 best_step = 9
4140 04:44:05.744234
4141 04:44:05.744338 ==
4142 04:44:05.747588 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 04:44:05.750890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 04:44:05.751019 ==
4145 04:44:05.753731 RX Vref Scan: 1
4146 04:44:05.753855
4147 04:44:05.753954 RX Vref 0 -> 0, step: 1
4148 04:44:05.757175
4149 04:44:05.757304 RX Delay -163 -> 252, step: 8
4150 04:44:05.757402
4151 04:44:05.760772 Set Vref, RX VrefLevel [Byte0]: 54
4152 04:44:05.763879 [Byte1]: 53
4153 04:44:05.768004
4154 04:44:05.768155 Final RX Vref Byte 0 = 54 to rank0
4155 04:44:05.771257 Final RX Vref Byte 1 = 53 to rank0
4156 04:44:05.774399 Final RX Vref Byte 0 = 54 to rank1
4157 04:44:05.778173 Final RX Vref Byte 1 = 53 to rank1==
4158 04:44:05.781291 Dram Type= 6, Freq= 0, CH_0, rank 0
4159 04:44:05.788099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 04:44:05.788229 ==
4161 04:44:05.788317 DQS Delay:
4162 04:44:05.791150 DQS0 = 0, DQS1 = 0
4163 04:44:05.791239 DQM Delay:
4164 04:44:05.791351 DQM0 = 53, DQM1 = 46
4165 04:44:05.794572 DQ Delay:
4166 04:44:05.798055 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4167 04:44:05.801564 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56
4168 04:44:05.804454 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4169 04:44:05.807676 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4170 04:44:05.807814
4171 04:44:05.807918
4172 04:44:05.814681 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4173 04:44:05.818139 CH0 RK0: MR19=808, MR18=6C5F
4174 04:44:05.824590 CH0_RK0: MR19=0x808, MR18=0x6C5F, DQSOSC=389, MR23=63, INC=173, DEC=115
4175 04:44:05.824762
4176 04:44:05.827848 ----->DramcWriteLeveling(PI) begin...
4177 04:44:05.827980 ==
4178 04:44:05.831084 Dram Type= 6, Freq= 0, CH_0, rank 1
4179 04:44:05.834989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 04:44:05.835143 ==
4181 04:44:05.838077 Write leveling (Byte 0): 34 => 34
4182 04:44:05.841616 Write leveling (Byte 1): 31 => 31
4183 04:44:05.844828 DramcWriteLeveling(PI) end<-----
4184 04:44:05.844979
4185 04:44:05.845083 ==
4186 04:44:05.848281 Dram Type= 6, Freq= 0, CH_0, rank 1
4187 04:44:05.851626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 04:44:05.851772 ==
4189 04:44:05.854364 [Gating] SW mode calibration
4190 04:44:05.861106 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4191 04:44:05.867826 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4192 04:44:05.871350 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4193 04:44:05.874814 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4194 04:44:05.880957 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4195 04:44:05.884333 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4196 04:44:05.887594 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4197 04:44:05.894481 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 04:44:05.897721 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 04:44:05.900690 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 04:44:05.907945 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 04:44:05.911346 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 04:44:05.914087 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 04:44:05.920969 0 10 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4204 04:44:05.924424 0 10 16 | B1->B0 | 3a3a 3e3e | 1 0 | (0 0) (0 0)
4205 04:44:05.927849 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 04:44:05.934684 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 04:44:05.937809 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 04:44:05.940780 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 04:44:05.947411 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 04:44:05.950820 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 04:44:05.953964 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4212 04:44:05.960998 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 04:44:05.964376 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 04:44:05.967439 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 04:44:05.974128 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 04:44:05.977450 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 04:44:05.980933 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 04:44:05.984348 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 04:44:05.991142 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 04:44:05.994347 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 04:44:05.997150 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 04:44:06.004181 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 04:44:06.007375 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 04:44:06.010671 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 04:44:06.017187 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 04:44:06.020819 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 04:44:06.024340 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 04:44:06.031115 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 04:44:06.031291 Total UI for P1: 0, mck2ui 16
4230 04:44:06.037285 best dqsien dly found for B0: ( 0, 13, 14)
4231 04:44:06.037451 Total UI for P1: 0, mck2ui 16
4232 04:44:06.043966 best dqsien dly found for B1: ( 0, 13, 14)
4233 04:44:06.047323 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4234 04:44:06.050872 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4235 04:44:06.051018
4236 04:44:06.054385 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4237 04:44:06.057767 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4238 04:44:06.060712 [Gating] SW calibration Done
4239 04:44:06.060870 ==
4240 04:44:06.063991 Dram Type= 6, Freq= 0, CH_0, rank 1
4241 04:44:06.067423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4242 04:44:06.067572 ==
4243 04:44:06.070956 RX Vref Scan: 0
4244 04:44:06.071077
4245 04:44:06.071174 RX Vref 0 -> 0, step: 1
4246 04:44:06.071262
4247 04:44:06.074132 RX Delay -230 -> 252, step: 16
4248 04:44:06.080669 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4249 04:44:06.084036 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4250 04:44:06.087427 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4251 04:44:06.090693 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4252 04:44:06.093950 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4253 04:44:06.100844 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4254 04:44:06.104029 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4255 04:44:06.107420 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4256 04:44:06.110864 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4257 04:44:06.114201 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4258 04:44:06.120524 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4259 04:44:06.123974 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4260 04:44:06.127348 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4261 04:44:06.130986 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4262 04:44:06.137205 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4263 04:44:06.140751 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4264 04:44:06.140874 ==
4265 04:44:06.143980 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 04:44:06.147286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 04:44:06.147426 ==
4268 04:44:06.150684 DQS Delay:
4269 04:44:06.150809 DQS0 = 0, DQS1 = 0
4270 04:44:06.150931 DQM Delay:
4271 04:44:06.154164 DQM0 = 53, DQM1 = 43
4272 04:44:06.154277 DQ Delay:
4273 04:44:06.156977 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4274 04:44:06.160499 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4275 04:44:06.163939 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4276 04:44:06.167358 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4277 04:44:06.167475
4278 04:44:06.167545
4279 04:44:06.167605 ==
4280 04:44:06.170839 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 04:44:06.177022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 04:44:06.177141 ==
4283 04:44:06.177216
4284 04:44:06.177285
4285 04:44:06.177345 TX Vref Scan disable
4286 04:44:06.181087 == TX Byte 0 ==
4287 04:44:06.184411 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4288 04:44:06.190572 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4289 04:44:06.190726 == TX Byte 1 ==
4290 04:44:06.194094 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4291 04:44:06.197582 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4292 04:44:06.200906 ==
4293 04:44:06.204162 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 04:44:06.207464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 04:44:06.207586 ==
4296 04:44:06.207666
4297 04:44:06.207752
4298 04:44:06.210523 TX Vref Scan disable
4299 04:44:06.214101 == TX Byte 0 ==
4300 04:44:06.217595 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4301 04:44:06.220533 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4302 04:44:06.224067 == TX Byte 1 ==
4303 04:44:06.227039 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4304 04:44:06.230902 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4305 04:44:06.231013
4306 04:44:06.231085 [DATLAT]
4307 04:44:06.234231 Freq=600, CH0 RK1
4308 04:44:06.234341
4309 04:44:06.234415 DATLAT Default: 0x9
4310 04:44:06.237054 0, 0xFFFF, sum = 0
4311 04:44:06.240523 1, 0xFFFF, sum = 0
4312 04:44:06.240626 2, 0xFFFF, sum = 0
4313 04:44:06.243964 3, 0xFFFF, sum = 0
4314 04:44:06.244086 4, 0xFFFF, sum = 0
4315 04:44:06.247334 5, 0xFFFF, sum = 0
4316 04:44:06.247418 6, 0xFFFF, sum = 0
4317 04:44:06.250556 7, 0xFFFF, sum = 0
4318 04:44:06.250645 8, 0x0, sum = 1
4319 04:44:06.250709 9, 0x0, sum = 2
4320 04:44:06.254223 10, 0x0, sum = 3
4321 04:44:06.254314 11, 0x0, sum = 4
4322 04:44:06.257275 best_step = 9
4323 04:44:06.257368
4324 04:44:06.257429 ==
4325 04:44:06.260665 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 04:44:06.264000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 04:44:06.264327 ==
4328 04:44:06.267578 RX Vref Scan: 0
4329 04:44:06.267663
4330 04:44:06.267726 RX Vref 0 -> 0, step: 1
4331 04:44:06.267788
4332 04:44:06.271008 RX Delay -163 -> 252, step: 8
4333 04:44:06.277739 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4334 04:44:06.281223 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4335 04:44:06.284658 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4336 04:44:06.288119 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4337 04:44:06.291570 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4338 04:44:06.297671 iDelay=197, Bit 5, Center 48 (-91 ~ 188) 280
4339 04:44:06.300990 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4340 04:44:06.304635 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4341 04:44:06.307905 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4342 04:44:06.311437 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4343 04:44:06.317676 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4344 04:44:06.321045 iDelay=197, Bit 11, Center 36 (-107 ~ 180) 288
4345 04:44:06.324443 iDelay=197, Bit 12, Center 56 (-83 ~ 196) 280
4346 04:44:06.327770 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4347 04:44:06.334716 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4348 04:44:06.337934 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4349 04:44:06.338042 ==
4350 04:44:06.341297 Dram Type= 6, Freq= 0, CH_0, rank 1
4351 04:44:06.344470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 04:44:06.344591 ==
4353 04:44:06.344676 DQS Delay:
4354 04:44:06.347890 DQS0 = 0, DQS1 = 0
4355 04:44:06.347998 DQM Delay:
4356 04:44:06.351116 DQM0 = 53, DQM1 = 46
4357 04:44:06.351197 DQ Delay:
4358 04:44:06.354786 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4359 04:44:06.358097 DQ4 =56, DQ5 =48, DQ6 =56, DQ7 =56
4360 04:44:06.361144 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4361 04:44:06.364557 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =52
4362 04:44:06.364647
4363 04:44:06.364712
4364 04:44:06.374634 [DQSOSCAuto] RK1, (LSB)MR18= 0x6426, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
4365 04:44:06.374761 CH0 RK1: MR19=808, MR18=6426
4366 04:44:06.381232 CH0_RK1: MR19=0x808, MR18=0x6426, DQSOSC=391, MR23=63, INC=171, DEC=114
4367 04:44:06.384655 [RxdqsGatingPostProcess] freq 600
4368 04:44:06.391278 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4369 04:44:06.394569 Pre-setting of DQS Precalculation
4370 04:44:06.398011 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4371 04:44:06.398097 ==
4372 04:44:06.401312 Dram Type= 6, Freq= 0, CH_1, rank 0
4373 04:44:06.404664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 04:44:06.408073 ==
4375 04:44:06.411516 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4376 04:44:06.417678 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4377 04:44:06.420944 [CA 0] Center 35 (5~66) winsize 62
4378 04:44:06.424386 [CA 1] Center 36 (5~67) winsize 63
4379 04:44:06.427752 [CA 2] Center 34 (4~65) winsize 62
4380 04:44:06.431206 [CA 3] Center 34 (4~65) winsize 62
4381 04:44:06.434686 [CA 4] Center 34 (4~65) winsize 62
4382 04:44:06.437413 [CA 5] Center 34 (3~65) winsize 63
4383 04:44:06.437507
4384 04:44:06.440863 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4385 04:44:06.440954
4386 04:44:06.444263 [CATrainingPosCal] consider 1 rank data
4387 04:44:06.447777 u2DelayCellTimex100 = 270/100 ps
4388 04:44:06.451200 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4389 04:44:06.454597 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4390 04:44:06.457887 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4391 04:44:06.460647 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4392 04:44:06.467419 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4393 04:44:06.470779 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4394 04:44:06.470874
4395 04:44:06.474181 CA PerBit enable=1, Macro0, CA PI delay=34
4396 04:44:06.474294
4397 04:44:06.477404 [CBTSetCACLKResult] CA Dly = 34
4398 04:44:06.477515 CS Dly: 6 (0~37)
4399 04:44:06.477604 ==
4400 04:44:06.481186 Dram Type= 6, Freq= 0, CH_1, rank 1
4401 04:44:06.484345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 04:44:06.487263 ==
4403 04:44:06.490931 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4404 04:44:06.497396 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4405 04:44:06.500814 [CA 0] Center 36 (5~67) winsize 63
4406 04:44:06.503986 [CA 1] Center 36 (5~67) winsize 63
4407 04:44:06.507829 [CA 2] Center 34 (4~65) winsize 62
4408 04:44:06.510902 [CA 3] Center 34 (4~65) winsize 62
4409 04:44:06.514275 [CA 4] Center 34 (4~65) winsize 62
4410 04:44:06.517879 [CA 5] Center 34 (3~65) winsize 63
4411 04:44:06.517979
4412 04:44:06.520662 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4413 04:44:06.520744
4414 04:44:06.524125 [CATrainingPosCal] consider 2 rank data
4415 04:44:06.527586 u2DelayCellTimex100 = 270/100 ps
4416 04:44:06.530803 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4417 04:44:06.534220 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4418 04:44:06.537704 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4419 04:44:06.540988 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4420 04:44:06.547200 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4421 04:44:06.550739 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4422 04:44:06.550829
4423 04:44:06.554139 CA PerBit enable=1, Macro0, CA PI delay=34
4424 04:44:06.554224
4425 04:44:06.557704 [CBTSetCACLKResult] CA Dly = 34
4426 04:44:06.557785 CS Dly: 6 (0~38)
4427 04:44:06.557849
4428 04:44:06.561142 ----->DramcWriteLeveling(PI) begin...
4429 04:44:06.561224 ==
4430 04:44:06.564517 Dram Type= 6, Freq= 0, CH_1, rank 0
4431 04:44:06.570559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4432 04:44:06.570667 ==
4433 04:44:06.574047 Write leveling (Byte 0): 30 => 30
4434 04:44:06.577374 Write leveling (Byte 1): 30 => 30
4435 04:44:06.577455 DramcWriteLeveling(PI) end<-----
4436 04:44:06.577522
4437 04:44:06.580772 ==
4438 04:44:06.584152 Dram Type= 6, Freq= 0, CH_1, rank 0
4439 04:44:06.587745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 04:44:06.587843 ==
4441 04:44:06.590411 [Gating] SW mode calibration
4442 04:44:06.597085 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4443 04:44:06.600344 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4444 04:44:06.607085 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4445 04:44:06.610466 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4446 04:44:06.613986 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4447 04:44:06.620832 0 9 12 | B1->B0 | 2f2f 2e2e | 1 1 | (1 1) (1 0)
4448 04:44:06.623783 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 04:44:06.626922 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 04:44:06.633728 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 04:44:06.637025 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 04:44:06.640074 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 04:44:06.646703 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 04:44:06.650199 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4455 04:44:06.653634 0 10 12 | B1->B0 | 2e2e 3838 | 0 0 | (0 0) (0 0)
4456 04:44:06.660016 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 04:44:06.663638 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 04:44:06.666970 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 04:44:06.673721 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 04:44:06.676868 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 04:44:06.680236 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 04:44:06.686937 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 04:44:06.690338 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4464 04:44:06.693169 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 04:44:06.699930 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 04:44:06.703268 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 04:44:06.706569 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 04:44:06.713108 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 04:44:06.716631 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 04:44:06.720026 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 04:44:06.723500 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 04:44:06.729693 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 04:44:06.733073 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 04:44:06.736503 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 04:44:06.743290 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 04:44:06.746577 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 04:44:06.749890 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 04:44:06.756713 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4479 04:44:06.759857 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4480 04:44:06.763186 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 04:44:06.766706 Total UI for P1: 0, mck2ui 16
4482 04:44:06.769647 best dqsien dly found for B0: ( 0, 13, 12)
4483 04:44:06.773145 Total UI for P1: 0, mck2ui 16
4484 04:44:06.776546 best dqsien dly found for B1: ( 0, 13, 10)
4485 04:44:06.780002 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4486 04:44:06.783343 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4487 04:44:06.783452
4488 04:44:06.790129 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4489 04:44:06.793256 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4490 04:44:06.793355 [Gating] SW calibration Done
4491 04:44:06.796584 ==
4492 04:44:06.800000 Dram Type= 6, Freq= 0, CH_1, rank 0
4493 04:44:06.803376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4494 04:44:06.803467 ==
4495 04:44:06.803545 RX Vref Scan: 0
4496 04:44:06.803612
4497 04:44:06.806901 RX Vref 0 -> 0, step: 1
4498 04:44:06.806982
4499 04:44:06.809769 RX Delay -230 -> 252, step: 16
4500 04:44:06.813003 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4501 04:44:06.816373 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4502 04:44:06.823206 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4503 04:44:06.826669 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4504 04:44:06.830193 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4505 04:44:06.833001 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4506 04:44:06.836565 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4507 04:44:06.843538 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4508 04:44:06.846275 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4509 04:44:06.849540 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4510 04:44:06.852921 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4511 04:44:06.859814 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4512 04:44:06.863260 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4513 04:44:06.866784 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4514 04:44:06.869432 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4515 04:44:06.876084 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4516 04:44:06.876195 ==
4517 04:44:06.879899 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 04:44:06.882847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 04:44:06.882938 ==
4520 04:44:06.883010 DQS Delay:
4521 04:44:06.886227 DQS0 = 0, DQS1 = 0
4522 04:44:06.886319 DQM Delay:
4523 04:44:06.889585 DQM0 = 50, DQM1 = 46
4524 04:44:06.889671 DQ Delay:
4525 04:44:06.892897 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4526 04:44:06.896268 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4527 04:44:06.899690 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4528 04:44:06.902756 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4529 04:44:06.902850
4530 04:44:06.902916
4531 04:44:06.902977 ==
4532 04:44:06.906088 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 04:44:06.909491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 04:44:06.909579 ==
4535 04:44:06.912543
4536 04:44:06.912654
4537 04:44:06.912748 TX Vref Scan disable
4538 04:44:06.915993 == TX Byte 0 ==
4539 04:44:06.919297 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4540 04:44:06.922581 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4541 04:44:06.925804 == TX Byte 1 ==
4542 04:44:06.929267 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4543 04:44:06.932771 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4544 04:44:06.932860 ==
4545 04:44:06.936153 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 04:44:06.942582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 04:44:06.942720 ==
4548 04:44:06.942794
4549 04:44:06.942880
4550 04:44:06.946041 TX Vref Scan disable
4551 04:44:06.946130 == TX Byte 0 ==
4552 04:44:06.952119 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4553 04:44:06.956053 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4554 04:44:06.956186 == TX Byte 1 ==
4555 04:44:06.962739 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4556 04:44:06.965407 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4557 04:44:06.965508
4558 04:44:06.965581 [DATLAT]
4559 04:44:06.968862 Freq=600, CH1 RK0
4560 04:44:06.968960
4561 04:44:06.969026 DATLAT Default: 0x9
4562 04:44:06.972183 0, 0xFFFF, sum = 0
4563 04:44:06.972308 1, 0xFFFF, sum = 0
4564 04:44:06.975703 2, 0xFFFF, sum = 0
4565 04:44:06.975795 3, 0xFFFF, sum = 0
4566 04:44:06.979181 4, 0xFFFF, sum = 0
4567 04:44:06.979262 5, 0xFFFF, sum = 0
4568 04:44:06.982055 6, 0xFFFF, sum = 0
4569 04:44:06.985553 7, 0xFFFF, sum = 0
4570 04:44:06.985661 8, 0x0, sum = 1
4571 04:44:06.985735 9, 0x0, sum = 2
4572 04:44:06.989093 10, 0x0, sum = 3
4573 04:44:06.989171 11, 0x0, sum = 4
4574 04:44:06.992410 best_step = 9
4575 04:44:06.992507
4576 04:44:06.992571 ==
4577 04:44:06.995721 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 04:44:06.998827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 04:44:06.998907 ==
4580 04:44:07.001868 RX Vref Scan: 1
4581 04:44:07.001972
4582 04:44:07.002064 RX Vref 0 -> 0, step: 1
4583 04:44:07.002155
4584 04:44:07.005516 RX Delay -163 -> 252, step: 8
4585 04:44:07.005594
4586 04:44:07.008914 Set Vref, RX VrefLevel [Byte0]: 52
4587 04:44:07.012174 [Byte1]: 49
4588 04:44:07.015821
4589 04:44:07.015909 Final RX Vref Byte 0 = 52 to rank0
4590 04:44:07.019532 Final RX Vref Byte 1 = 49 to rank0
4591 04:44:07.022732 Final RX Vref Byte 0 = 52 to rank1
4592 04:44:07.025923 Final RX Vref Byte 1 = 49 to rank1==
4593 04:44:07.028977 Dram Type= 6, Freq= 0, CH_1, rank 0
4594 04:44:07.036035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 04:44:07.036190 ==
4596 04:44:07.036301 DQS Delay:
4597 04:44:07.036372 DQS0 = 0, DQS1 = 0
4598 04:44:07.039097 DQM Delay:
4599 04:44:07.039176 DQM0 = 48, DQM1 = 46
4600 04:44:07.042250 DQ Delay:
4601 04:44:07.045557 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4602 04:44:07.049061 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4603 04:44:07.052570 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4604 04:44:07.056084 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =60
4605 04:44:07.056184
4606 04:44:07.056251
4607 04:44:07.062014 [DQSOSCAuto] RK0, (LSB)MR18= 0x486d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4608 04:44:07.065953 CH1 RK0: MR19=808, MR18=486D
4609 04:44:07.072225 CH1_RK0: MR19=0x808, MR18=0x486D, DQSOSC=389, MR23=63, INC=173, DEC=115
4610 04:44:07.072358
4611 04:44:07.075601 ----->DramcWriteLeveling(PI) begin...
4612 04:44:07.075705 ==
4613 04:44:07.079039 Dram Type= 6, Freq= 0, CH_1, rank 1
4614 04:44:07.082512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 04:44:07.082600 ==
4616 04:44:07.085415 Write leveling (Byte 0): 30 => 30
4617 04:44:07.088740 Write leveling (Byte 1): 32 => 32
4618 04:44:07.092311 DramcWriteLeveling(PI) end<-----
4619 04:44:07.092414
4620 04:44:07.092484 ==
4621 04:44:07.095696 Dram Type= 6, Freq= 0, CH_1, rank 1
4622 04:44:07.098568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 04:44:07.098663 ==
4624 04:44:07.101890 [Gating] SW mode calibration
4625 04:44:07.108806 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4626 04:44:07.115715 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4627 04:44:07.119057 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4628 04:44:07.125723 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4629 04:44:07.128743 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4630 04:44:07.132261 0 9 12 | B1->B0 | 3030 3030 | 0 0 | (1 1) (0 0)
4631 04:44:07.135778 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4632 04:44:07.142094 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 04:44:07.145296 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 04:44:07.149046 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 04:44:07.155241 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 04:44:07.158488 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 04:44:07.162231 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 04:44:07.168589 0 10 12 | B1->B0 | 3a3a 3131 | 0 0 | (0 0) (1 1)
4639 04:44:07.172217 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 04:44:07.175343 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 04:44:07.182332 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 04:44:07.185147 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 04:44:07.188564 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 04:44:07.195399 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 04:44:07.198694 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 04:44:07.202092 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 04:44:07.208973 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 04:44:07.212428 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 04:44:07.215255 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 04:44:07.222027 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 04:44:07.225340 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 04:44:07.228742 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 04:44:07.235177 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 04:44:07.238424 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 04:44:07.241881 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 04:44:07.248500 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 04:44:07.251587 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 04:44:07.255132 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 04:44:07.261959 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 04:44:07.265116 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 04:44:07.268069 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 04:44:07.271788 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 04:44:07.274620 Total UI for P1: 0, mck2ui 16
4664 04:44:07.278392 best dqsien dly found for B0: ( 0, 13, 10)
4665 04:44:07.281786 Total UI for P1: 0, mck2ui 16
4666 04:44:07.284954 best dqsien dly found for B1: ( 0, 13, 10)
4667 04:44:07.288067 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4668 04:44:07.294626 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4669 04:44:07.294769
4670 04:44:07.297865 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4671 04:44:07.301529 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4672 04:44:07.304761 [Gating] SW calibration Done
4673 04:44:07.304936 ==
4674 04:44:07.308251 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 04:44:07.311692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 04:44:07.311859 ==
4677 04:44:07.314521 RX Vref Scan: 0
4678 04:44:07.314661
4679 04:44:07.314754 RX Vref 0 -> 0, step: 1
4680 04:44:07.314838
4681 04:44:07.318051 RX Delay -230 -> 252, step: 16
4682 04:44:07.321378 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4683 04:44:07.328198 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4684 04:44:07.331805 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4685 04:44:07.335065 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4686 04:44:07.337857 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4687 04:44:07.341399 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4688 04:44:07.348310 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4689 04:44:07.351767 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4690 04:44:07.354602 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4691 04:44:07.358029 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4692 04:44:07.364991 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4693 04:44:07.368209 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4694 04:44:07.371644 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4695 04:44:07.375009 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4696 04:44:07.381289 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4697 04:44:07.384376 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4698 04:44:07.384469 ==
4699 04:44:07.387935 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 04:44:07.391349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 04:44:07.391444 ==
4702 04:44:07.391510 DQS Delay:
4703 04:44:07.394356 DQS0 = 0, DQS1 = 0
4704 04:44:07.394447 DQM Delay:
4705 04:44:07.397721 DQM0 = 51, DQM1 = 49
4706 04:44:07.397811 DQ Delay:
4707 04:44:07.401221 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4708 04:44:07.404608 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4709 04:44:07.408002 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4710 04:44:07.411243 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4711 04:44:07.411378
4712 04:44:07.411476
4713 04:44:07.411571 ==
4714 04:44:07.414554 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 04:44:07.420738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 04:44:07.420913 ==
4717 04:44:07.421017
4718 04:44:07.421105
4719 04:44:07.421190 TX Vref Scan disable
4720 04:44:07.424410 == TX Byte 0 ==
4721 04:44:07.427379 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4722 04:44:07.434151 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4723 04:44:07.434327 == TX Byte 1 ==
4724 04:44:07.437726 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4725 04:44:07.441111 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4726 04:44:07.444234 ==
4727 04:44:07.447688 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 04:44:07.451085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 04:44:07.451225 ==
4730 04:44:07.451319
4731 04:44:07.451400
4732 04:44:07.454528 TX Vref Scan disable
4733 04:44:07.454648 == TX Byte 0 ==
4734 04:44:07.460672 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4735 04:44:07.464031 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4736 04:44:07.464154 == TX Byte 1 ==
4737 04:44:07.470997 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4738 04:44:07.474178 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4739 04:44:07.474305
4740 04:44:07.474399 [DATLAT]
4741 04:44:07.477242 Freq=600, CH1 RK1
4742 04:44:07.477358
4743 04:44:07.477453 DATLAT Default: 0x9
4744 04:44:07.480639 0, 0xFFFF, sum = 0
4745 04:44:07.480751 1, 0xFFFF, sum = 0
4746 04:44:07.484052 2, 0xFFFF, sum = 0
4747 04:44:07.487529 3, 0xFFFF, sum = 0
4748 04:44:07.487646 4, 0xFFFF, sum = 0
4749 04:44:07.491083 5, 0xFFFF, sum = 0
4750 04:44:07.491202 6, 0xFFFF, sum = 0
4751 04:44:07.494391 7, 0xFFFF, sum = 0
4752 04:44:07.494505 8, 0x0, sum = 1
4753 04:44:07.494596 9, 0x0, sum = 2
4754 04:44:07.497663 10, 0x0, sum = 3
4755 04:44:07.497776 11, 0x0, sum = 4
4756 04:44:07.501040 best_step = 9
4757 04:44:07.501152
4758 04:44:07.501244 ==
4759 04:44:07.504023 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 04:44:07.507127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 04:44:07.507239 ==
4762 04:44:07.510631 RX Vref Scan: 0
4763 04:44:07.510750
4764 04:44:07.510848 RX Vref 0 -> 0, step: 1
4765 04:44:07.510941
4766 04:44:07.513820 RX Delay -163 -> 252, step: 8
4767 04:44:07.521302 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4768 04:44:07.524811 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4769 04:44:07.528116 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4770 04:44:07.531648 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4771 04:44:07.534467 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4772 04:44:07.541678 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4773 04:44:07.544330 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4774 04:44:07.547712 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4775 04:44:07.550992 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4776 04:44:07.554675 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4777 04:44:07.561274 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4778 04:44:07.564468 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4779 04:44:07.567834 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4780 04:44:07.571295 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4781 04:44:07.577445 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4782 04:44:07.580908 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4783 04:44:07.581039 ==
4784 04:44:07.584211 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 04:44:07.587469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 04:44:07.587598 ==
4787 04:44:07.590935 DQS Delay:
4788 04:44:07.591057 DQS0 = 0, DQS1 = 0
4789 04:44:07.591153 DQM Delay:
4790 04:44:07.594406 DQM0 = 49, DQM1 = 45
4791 04:44:07.594524 DQ Delay:
4792 04:44:07.597233 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4793 04:44:07.600723 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4794 04:44:07.604157 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4795 04:44:07.607607 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4796 04:44:07.607741
4797 04:44:07.607838
4798 04:44:07.617512 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4799 04:44:07.620557 CH1 RK1: MR19=808, MR18=6C22
4800 04:44:07.624156 CH1_RK1: MR19=0x808, MR18=0x6C22, DQSOSC=389, MR23=63, INC=173, DEC=115
4801 04:44:07.627195 [RxdqsGatingPostProcess] freq 600
4802 04:44:07.633639 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4803 04:44:07.636937 Pre-setting of DQS Precalculation
4804 04:44:07.640565 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4805 04:44:07.650648 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4806 04:44:07.656934 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4807 04:44:07.657093
4808 04:44:07.657196
4809 04:44:07.660569 [Calibration Summary] 1200 Mbps
4810 04:44:07.660690 CH 0, Rank 0
4811 04:44:07.663892 SW Impedance : PASS
4812 04:44:07.664011 DUTY Scan : NO K
4813 04:44:07.667413 ZQ Calibration : PASS
4814 04:44:07.670419 Jitter Meter : NO K
4815 04:44:07.670540 CBT Training : PASS
4816 04:44:07.674200 Write leveling : PASS
4817 04:44:07.677222 RX DQS gating : PASS
4818 04:44:07.677358 RX DQ/DQS(RDDQC) : PASS
4819 04:44:07.680509 TX DQ/DQS : PASS
4820 04:44:07.680630 RX DATLAT : PASS
4821 04:44:07.683737 RX DQ/DQS(Engine): PASS
4822 04:44:07.687195 TX OE : NO K
4823 04:44:07.687348 All Pass.
4824 04:44:07.687446
4825 04:44:07.687538 CH 0, Rank 1
4826 04:44:07.690765 SW Impedance : PASS
4827 04:44:07.693999 DUTY Scan : NO K
4828 04:44:07.694156 ZQ Calibration : PASS
4829 04:44:07.697191 Jitter Meter : NO K
4830 04:44:07.700712 CBT Training : PASS
4831 04:44:07.700872 Write leveling : PASS
4832 04:44:07.704052 RX DQS gating : PASS
4833 04:44:07.706785 RX DQ/DQS(RDDQC) : PASS
4834 04:44:07.706905 TX DQ/DQS : PASS
4835 04:44:07.710359 RX DATLAT : PASS
4836 04:44:07.713705 RX DQ/DQS(Engine): PASS
4837 04:44:07.713833 TX OE : NO K
4838 04:44:07.717094 All Pass.
4839 04:44:07.717216
4840 04:44:07.717313 CH 1, Rank 0
4841 04:44:07.720650 SW Impedance : PASS
4842 04:44:07.720768 DUTY Scan : NO K
4843 04:44:07.723539 ZQ Calibration : PASS
4844 04:44:07.726782 Jitter Meter : NO K
4845 04:44:07.726924 CBT Training : PASS
4846 04:44:07.730035 Write leveling : PASS
4847 04:44:07.733282 RX DQS gating : PASS
4848 04:44:07.733406 RX DQ/DQS(RDDQC) : PASS
4849 04:44:07.737050 TX DQ/DQS : PASS
4850 04:44:07.737174 RX DATLAT : PASS
4851 04:44:07.740016 RX DQ/DQS(Engine): PASS
4852 04:44:07.743592 TX OE : NO K
4853 04:44:07.743725 All Pass.
4854 04:44:07.743821
4855 04:44:07.743913 CH 1, Rank 1
4856 04:44:07.746720 SW Impedance : PASS
4857 04:44:07.750370 DUTY Scan : NO K
4858 04:44:07.750502 ZQ Calibration : PASS
4859 04:44:07.753650 Jitter Meter : NO K
4860 04:44:07.756951 CBT Training : PASS
4861 04:44:07.757079 Write leveling : PASS
4862 04:44:07.760350 RX DQS gating : PASS
4863 04:44:07.763733 RX DQ/DQS(RDDQC) : PASS
4864 04:44:07.763860 TX DQ/DQS : PASS
4865 04:44:07.767190 RX DATLAT : PASS
4866 04:44:07.770557 RX DQ/DQS(Engine): PASS
4867 04:44:07.770681 TX OE : NO K
4868 04:44:07.770778 All Pass.
4869 04:44:07.773343
4870 04:44:07.773455 DramC Write-DBI off
4871 04:44:07.776669 PER_BANK_REFRESH: Hybrid Mode
4872 04:44:07.776791 TX_TRACKING: ON
4873 04:44:07.787286 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4874 04:44:07.790424 [FAST_K] Save calibration result to emmc
4875 04:44:07.793751 dramc_set_vcore_voltage set vcore to 662500
4876 04:44:07.796968 Read voltage for 933, 3
4877 04:44:07.797100 Vio18 = 0
4878 04:44:07.800143 Vcore = 662500
4879 04:44:07.800257 Vdram = 0
4880 04:44:07.800364 Vddq = 0
4881 04:44:07.800456 Vmddr = 0
4882 04:44:07.807337 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4883 04:44:07.810190 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4884 04:44:07.813565 MEM_TYPE=3, freq_sel=17
4885 04:44:07.817088 sv_algorithm_assistance_LP4_1600
4886 04:44:07.819899 ============ PULL DRAM RESETB DOWN ============
4887 04:44:07.826696 ========== PULL DRAM RESETB DOWN end =========
4888 04:44:07.830255 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4889 04:44:07.833380 ===================================
4890 04:44:07.836655 LPDDR4 DRAM CONFIGURATION
4891 04:44:07.840021 ===================================
4892 04:44:07.840168 EX_ROW_EN[0] = 0x0
4893 04:44:07.843440 EX_ROW_EN[1] = 0x0
4894 04:44:07.843575 LP4Y_EN = 0x0
4895 04:44:07.846854 WORK_FSP = 0x0
4896 04:44:07.846985 WL = 0x3
4897 04:44:07.850165 RL = 0x3
4898 04:44:07.850296 BL = 0x2
4899 04:44:07.853424 RPST = 0x0
4900 04:44:07.853553 RD_PRE = 0x0
4901 04:44:07.856365 WR_PRE = 0x1
4902 04:44:07.860039 WR_PST = 0x0
4903 04:44:07.860175 DBI_WR = 0x0
4904 04:44:07.863093 DBI_RD = 0x0
4905 04:44:07.863213 OTF = 0x1
4906 04:44:07.866782 ===================================
4907 04:44:07.869771 ===================================
4908 04:44:07.873232 ANA top config
4909 04:44:07.873376 ===================================
4910 04:44:07.876629 DLL_ASYNC_EN = 0
4911 04:44:07.880088 ALL_SLAVE_EN = 1
4912 04:44:07.882778 NEW_RANK_MODE = 1
4913 04:44:07.886092 DLL_IDLE_MODE = 1
4914 04:44:07.886216 LP45_APHY_COMB_EN = 1
4915 04:44:07.889627 TX_ODT_DIS = 1
4916 04:44:07.893064 NEW_8X_MODE = 1
4917 04:44:07.896448 ===================================
4918 04:44:07.899822 ===================================
4919 04:44:07.903127 data_rate = 1866
4920 04:44:07.906379 CKR = 1
4921 04:44:07.909411 DQ_P2S_RATIO = 8
4922 04:44:07.912761 ===================================
4923 04:44:07.912862 CA_P2S_RATIO = 8
4924 04:44:07.916558 DQ_CA_OPEN = 0
4925 04:44:07.919737 DQ_SEMI_OPEN = 0
4926 04:44:07.922660 CA_SEMI_OPEN = 0
4927 04:44:07.926004 CA_FULL_RATE = 0
4928 04:44:07.926131 DQ_CKDIV4_EN = 1
4929 04:44:07.929271 CA_CKDIV4_EN = 1
4930 04:44:07.932674 CA_PREDIV_EN = 0
4931 04:44:07.936377 PH8_DLY = 0
4932 04:44:07.939701 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4933 04:44:07.942409 DQ_AAMCK_DIV = 4
4934 04:44:07.942536 CA_AAMCK_DIV = 4
4935 04:44:07.945914 CA_ADMCK_DIV = 4
4936 04:44:07.949266 DQ_TRACK_CA_EN = 0
4937 04:44:07.952822 CA_PICK = 933
4938 04:44:07.955652 CA_MCKIO = 933
4939 04:44:07.959156 MCKIO_SEMI = 0
4940 04:44:07.962595 PLL_FREQ = 3732
4941 04:44:07.965738 DQ_UI_PI_RATIO = 32
4942 04:44:07.965864 CA_UI_PI_RATIO = 0
4943 04:44:07.969640 ===================================
4944 04:44:07.972806 ===================================
4945 04:44:07.976136 memory_type:LPDDR4
4946 04:44:07.979283 GP_NUM : 10
4947 04:44:07.979416 SRAM_EN : 1
4948 04:44:07.982349 MD32_EN : 0
4949 04:44:07.986196 ===================================
4950 04:44:07.989534 [ANA_INIT] >>>>>>>>>>>>>>
4951 04:44:07.989681 <<<<<< [CONFIGURE PHASE]: ANA_TX
4952 04:44:07.995755 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4953 04:44:07.995889 ===================================
4954 04:44:07.999121 data_rate = 1866,PCW = 0X8f00
4955 04:44:08.002661 ===================================
4956 04:44:08.006090 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4957 04:44:08.012359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4958 04:44:08.018927 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4959 04:44:08.022664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4960 04:44:08.025892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4961 04:44:08.029048 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4962 04:44:08.032293 [ANA_INIT] flow start
4963 04:44:08.032428 [ANA_INIT] PLL >>>>>>>>
4964 04:44:08.036138 [ANA_INIT] PLL <<<<<<<<
4965 04:44:08.039219 [ANA_INIT] MIDPI >>>>>>>>
4966 04:44:08.039360 [ANA_INIT] MIDPI <<<<<<<<
4967 04:44:08.042748 [ANA_INIT] DLL >>>>>>>>
4968 04:44:08.045668 [ANA_INIT] flow end
4969 04:44:08.048858 ============ LP4 DIFF to SE enter ============
4970 04:44:08.052307 ============ LP4 DIFF to SE exit ============
4971 04:44:08.055769 [ANA_INIT] <<<<<<<<<<<<<
4972 04:44:08.059169 [Flow] Enable top DCM control >>>>>
4973 04:44:08.062652 [Flow] Enable top DCM control <<<<<
4974 04:44:08.065988 Enable DLL master slave shuffle
4975 04:44:08.069518 ==============================================================
4976 04:44:08.072627 Gating Mode config
4977 04:44:08.078820 ==============================================================
4978 04:44:08.079001 Config description:
4979 04:44:08.089441 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4980 04:44:08.095552 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4981 04:44:08.099317 SELPH_MODE 0: By rank 1: By Phase
4982 04:44:08.105989 ==============================================================
4983 04:44:08.109381 GAT_TRACK_EN = 1
4984 04:44:08.112786 RX_GATING_MODE = 2
4985 04:44:08.115624 RX_GATING_TRACK_MODE = 2
4986 04:44:08.119177 SELPH_MODE = 1
4987 04:44:08.122681 PICG_EARLY_EN = 1
4988 04:44:08.125433 VALID_LAT_VALUE = 1
4989 04:44:08.128805 ==============================================================
4990 04:44:08.132106 Enter into Gating configuration >>>>
4991 04:44:08.135658 Exit from Gating configuration <<<<
4992 04:44:08.139008 Enter into DVFS_PRE_config >>>>>
4993 04:44:08.152422 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4994 04:44:08.152598 Exit from DVFS_PRE_config <<<<<
4995 04:44:08.155808 Enter into PICG configuration >>>>
4996 04:44:08.158985 Exit from PICG configuration <<<<
4997 04:44:08.162091 [RX_INPUT] configuration >>>>>
4998 04:44:08.165418 [RX_INPUT] configuration <<<<<
4999 04:44:08.172335 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5000 04:44:08.175718 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5001 04:44:08.181979 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5002 04:44:08.189094 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5003 04:44:08.195286 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5004 04:44:08.201827 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5005 04:44:08.205567 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5006 04:44:08.208814 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5007 04:44:08.212163 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5008 04:44:08.218869 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5009 04:44:08.222342 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5010 04:44:08.225076 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5011 04:44:08.228717 ===================================
5012 04:44:08.232034 LPDDR4 DRAM CONFIGURATION
5013 04:44:08.235247 ===================================
5014 04:44:08.235380 EX_ROW_EN[0] = 0x0
5015 04:44:08.238575 EX_ROW_EN[1] = 0x0
5016 04:44:08.241999 LP4Y_EN = 0x0
5017 04:44:08.242143 WORK_FSP = 0x0
5018 04:44:08.245282 WL = 0x3
5019 04:44:08.245407 RL = 0x3
5020 04:44:08.248587 BL = 0x2
5021 04:44:08.248725 RPST = 0x0
5022 04:44:08.252000 RD_PRE = 0x0
5023 04:44:08.252142 WR_PRE = 0x1
5024 04:44:08.254780 WR_PST = 0x0
5025 04:44:08.254885 DBI_WR = 0x0
5026 04:44:08.258152 DBI_RD = 0x0
5027 04:44:08.258259 OTF = 0x1
5028 04:44:08.261744 ===================================
5029 04:44:08.265163 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5030 04:44:08.272012 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5031 04:44:08.275386 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5032 04:44:08.278376 ===================================
5033 04:44:08.282056 LPDDR4 DRAM CONFIGURATION
5034 04:44:08.285253 ===================================
5035 04:44:08.285378 EX_ROW_EN[0] = 0x10
5036 04:44:08.288691 EX_ROW_EN[1] = 0x0
5037 04:44:08.288804 LP4Y_EN = 0x0
5038 04:44:08.291950 WORK_FSP = 0x0
5039 04:44:08.295201 WL = 0x3
5040 04:44:08.295321 RL = 0x3
5041 04:44:08.298680 BL = 0x2
5042 04:44:08.298796 RPST = 0x0
5043 04:44:08.301502 RD_PRE = 0x0
5044 04:44:08.301612 WR_PRE = 0x1
5045 04:44:08.304809 WR_PST = 0x0
5046 04:44:08.304918 DBI_WR = 0x0
5047 04:44:08.308735 DBI_RD = 0x0
5048 04:44:08.308856 OTF = 0x1
5049 04:44:08.311960 ===================================
5050 04:44:08.318395 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5051 04:44:08.322189 nWR fixed to 30
5052 04:44:08.325612 [ModeRegInit_LP4] CH0 RK0
5053 04:44:08.325747 [ModeRegInit_LP4] CH0 RK1
5054 04:44:08.328942 [ModeRegInit_LP4] CH1 RK0
5055 04:44:08.332523 [ModeRegInit_LP4] CH1 RK1
5056 04:44:08.332653 match AC timing 9
5057 04:44:08.338758 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5058 04:44:08.342454 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5059 04:44:08.345702 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5060 04:44:08.352349 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5061 04:44:08.355611 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5062 04:44:08.355743 ==
5063 04:44:08.358742 Dram Type= 6, Freq= 0, CH_0, rank 0
5064 04:44:08.362626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5065 04:44:08.362766 ==
5066 04:44:08.368842 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5067 04:44:08.375208 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5068 04:44:08.378614 [CA 0] Center 37 (6~68) winsize 63
5069 04:44:08.382066 [CA 1] Center 37 (7~68) winsize 62
5070 04:44:08.385643 [CA 2] Center 34 (4~65) winsize 62
5071 04:44:08.388742 [CA 3] Center 33 (3~64) winsize 62
5072 04:44:08.391874 [CA 4] Center 33 (3~64) winsize 62
5073 04:44:08.395420 [CA 5] Center 32 (2~62) winsize 61
5074 04:44:08.395559
5075 04:44:08.398725 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5076 04:44:08.398858
5077 04:44:08.401727 [CATrainingPosCal] consider 1 rank data
5078 04:44:08.405640 u2DelayCellTimex100 = 270/100 ps
5079 04:44:08.408432 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5080 04:44:08.411872 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5081 04:44:08.415255 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5082 04:44:08.418659 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5083 04:44:08.422051 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5084 04:44:08.425297 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5085 04:44:08.425425
5086 04:44:08.432348 CA PerBit enable=1, Macro0, CA PI delay=32
5087 04:44:08.432508
5088 04:44:08.435607 [CBTSetCACLKResult] CA Dly = 32
5089 04:44:08.435724 CS Dly: 5 (0~36)
5090 04:44:08.435821 ==
5091 04:44:08.438405 Dram Type= 6, Freq= 0, CH_0, rank 1
5092 04:44:08.441721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 04:44:08.441848 ==
5094 04:44:08.448630 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5095 04:44:08.455277 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5096 04:44:08.458699 [CA 0] Center 37 (7~68) winsize 62
5097 04:44:08.462083 [CA 1] Center 37 (7~68) winsize 62
5098 04:44:08.465320 [CA 2] Center 34 (4~65) winsize 62
5099 04:44:08.468716 [CA 3] Center 34 (4~65) winsize 62
5100 04:44:08.471478 [CA 4] Center 33 (3~63) winsize 61
5101 04:44:08.475199 [CA 5] Center 32 (2~62) winsize 61
5102 04:44:08.475337
5103 04:44:08.478522 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5104 04:44:08.478654
5105 04:44:08.481922 [CATrainingPosCal] consider 2 rank data
5106 04:44:08.485285 u2DelayCellTimex100 = 270/100 ps
5107 04:44:08.487933 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5108 04:44:08.492067 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5109 04:44:08.494891 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5110 04:44:08.498398 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5111 04:44:08.504900 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5112 04:44:08.508379 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5113 04:44:08.508511
5114 04:44:08.511366 CA PerBit enable=1, Macro0, CA PI delay=32
5115 04:44:08.511490
5116 04:44:08.514524 [CBTSetCACLKResult] CA Dly = 32
5117 04:44:08.514653 CS Dly: 5 (0~37)
5118 04:44:08.514753
5119 04:44:08.518408 ----->DramcWriteLeveling(PI) begin...
5120 04:44:08.518537 ==
5121 04:44:08.521254 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 04:44:08.528051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 04:44:08.528203 ==
5124 04:44:08.531523 Write leveling (Byte 0): 31 => 31
5125 04:44:08.534828 Write leveling (Byte 1): 27 => 27
5126 04:44:08.534941 DramcWriteLeveling(PI) end<-----
5127 04:44:08.535037
5128 04:44:08.538006 ==
5129 04:44:08.541128 Dram Type= 6, Freq= 0, CH_0, rank 0
5130 04:44:08.544466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5131 04:44:08.544590 ==
5132 04:44:08.547783 [Gating] SW mode calibration
5133 04:44:08.554945 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5134 04:44:08.558201 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5135 04:44:08.564534 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
5136 04:44:08.567938 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 04:44:08.571378 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 04:44:08.578075 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 04:44:08.581423 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 04:44:08.584719 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 04:44:08.591351 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5142 04:44:08.594776 0 14 28 | B1->B0 | 3434 2525 | 1 1 | (1 0) (1 0)
5143 04:44:08.597594 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5144 04:44:08.604501 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 04:44:08.607920 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 04:44:08.611366 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 04:44:08.614836 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 04:44:08.621043 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 04:44:08.624732 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5150 04:44:08.627947 0 15 28 | B1->B0 | 2929 3737 | 0 1 | (0 0) (0 0)
5151 04:44:08.634244 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5152 04:44:08.638234 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 04:44:08.641426 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 04:44:08.647515 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 04:44:08.650842 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 04:44:08.654576 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 04:44:08.661265 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5158 04:44:08.664604 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5159 04:44:08.667878 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5160 04:44:08.674111 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 04:44:08.677605 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 04:44:08.681176 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 04:44:08.687878 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 04:44:08.690665 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 04:44:08.693959 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 04:44:08.700952 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 04:44:08.704600 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 04:44:08.707843 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 04:44:08.714349 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 04:44:08.717644 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 04:44:08.721059 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 04:44:08.727324 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 04:44:08.730735 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5174 04:44:08.733991 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5175 04:44:08.737396 Total UI for P1: 0, mck2ui 16
5176 04:44:08.740813 best dqsien dly found for B0: ( 1, 2, 24)
5177 04:44:08.747140 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5178 04:44:08.750811 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 04:44:08.754156 Total UI for P1: 0, mck2ui 16
5180 04:44:08.757580 best dqsien dly found for B1: ( 1, 3, 0)
5181 04:44:08.760347 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5182 04:44:08.763915 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5183 04:44:08.764014
5184 04:44:08.767072 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5185 04:44:08.770281 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5186 04:44:08.773684 [Gating] SW calibration Done
5187 04:44:08.773773 ==
5188 04:44:08.777544 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 04:44:08.780596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 04:44:08.780685 ==
5191 04:44:08.783791 RX Vref Scan: 0
5192 04:44:08.783865
5193 04:44:08.787234 RX Vref 0 -> 0, step: 1
5194 04:44:08.787319
5195 04:44:08.787383 RX Delay -80 -> 252, step: 8
5196 04:44:08.794069 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5197 04:44:08.797427 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5198 04:44:08.800227 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5199 04:44:08.803737 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5200 04:44:08.806957 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5201 04:44:08.810171 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5202 04:44:08.817196 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5203 04:44:08.819995 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5204 04:44:08.823594 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5205 04:44:08.826967 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5206 04:44:08.830644 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5207 04:44:08.834006 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5208 04:44:08.840203 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5209 04:44:08.843711 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5210 04:44:08.847052 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5211 04:44:08.850372 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5212 04:44:08.850512 ==
5213 04:44:08.853834 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 04:44:08.857297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 04:44:08.857414 ==
5216 04:44:08.860756 DQS Delay:
5217 04:44:08.860870 DQS0 = 0, DQS1 = 0
5218 04:44:08.864220 DQM Delay:
5219 04:44:08.864344 DQM0 = 104, DQM1 = 93
5220 04:44:08.867282 DQ Delay:
5221 04:44:08.867394 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5222 04:44:08.870519 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5223 04:44:08.874223 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =91
5224 04:44:08.877216 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5225 04:44:08.880185
5226 04:44:08.880314
5227 04:44:08.880414 ==
5228 04:44:08.883826 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 04:44:08.886857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 04:44:08.886975 ==
5231 04:44:08.887072
5232 04:44:08.887166
5233 04:44:08.890653 TX Vref Scan disable
5234 04:44:08.890772 == TX Byte 0 ==
5235 04:44:08.897427 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5236 04:44:08.900604 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5237 04:44:08.900741 == TX Byte 1 ==
5238 04:44:08.907095 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5239 04:44:08.910544 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5240 04:44:08.910687 ==
5241 04:44:08.914036 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 04:44:08.917405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 04:44:08.917530 ==
5244 04:44:08.917629
5245 04:44:08.917723
5246 04:44:08.920567 TX Vref Scan disable
5247 04:44:08.924016 == TX Byte 0 ==
5248 04:44:08.926896 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5249 04:44:08.930312 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5250 04:44:08.933890 == TX Byte 1 ==
5251 04:44:08.937342 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5252 04:44:08.940161 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5253 04:44:08.940315
5254 04:44:08.943684 [DATLAT]
5255 04:44:08.943827 Freq=933, CH0 RK0
5256 04:44:08.943927
5257 04:44:08.947125 DATLAT Default: 0xd
5258 04:44:08.947253 0, 0xFFFF, sum = 0
5259 04:44:08.949885 1, 0xFFFF, sum = 0
5260 04:44:08.949999 2, 0xFFFF, sum = 0
5261 04:44:08.953763 3, 0xFFFF, sum = 0
5262 04:44:08.953885 4, 0xFFFF, sum = 0
5263 04:44:08.957241 5, 0xFFFF, sum = 0
5264 04:44:08.957359 6, 0xFFFF, sum = 0
5265 04:44:08.960019 7, 0xFFFF, sum = 0
5266 04:44:08.960134 8, 0xFFFF, sum = 0
5267 04:44:08.963404 9, 0xFFFF, sum = 0
5268 04:44:08.963521 10, 0x0, sum = 1
5269 04:44:08.966990 11, 0x0, sum = 2
5270 04:44:08.967107 12, 0x0, sum = 3
5271 04:44:08.970375 13, 0x0, sum = 4
5272 04:44:08.970489 best_step = 11
5273 04:44:08.970586
5274 04:44:08.970678 ==
5275 04:44:08.973786 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 04:44:08.980538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 04:44:08.980673 ==
5278 04:44:08.980775 RX Vref Scan: 1
5279 04:44:08.980868
5280 04:44:08.983375 RX Vref 0 -> 0, step: 1
5281 04:44:08.983485
5282 04:44:08.986734 RX Delay -53 -> 252, step: 4
5283 04:44:08.986846
5284 04:44:08.989874 Set Vref, RX VrefLevel [Byte0]: 54
5285 04:44:08.993150 [Byte1]: 53
5286 04:44:08.993277
5287 04:44:08.997106 Final RX Vref Byte 0 = 54 to rank0
5288 04:44:08.999751 Final RX Vref Byte 1 = 53 to rank0
5289 04:44:09.003011 Final RX Vref Byte 0 = 54 to rank1
5290 04:44:09.006418 Final RX Vref Byte 1 = 53 to rank1==
5291 04:44:09.009954 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 04:44:09.013530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 04:44:09.013673 ==
5294 04:44:09.016720 DQS Delay:
5295 04:44:09.016851 DQS0 = 0, DQS1 = 0
5296 04:44:09.016949 DQM Delay:
5297 04:44:09.019960 DQM0 = 104, DQM1 = 96
5298 04:44:09.020080 DQ Delay:
5299 04:44:09.023675 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =104
5300 04:44:09.026656 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5301 04:44:09.030119 DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =90
5302 04:44:09.033655 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5303 04:44:09.036602
5304 04:44:09.036758
5305 04:44:09.043506 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5306 04:44:09.046842 CH0 RK0: MR19=505, MR18=2E26
5307 04:44:09.053653 CH0_RK0: MR19=0x505, MR18=0x2E26, DQSOSC=407, MR23=63, INC=65, DEC=43
5308 04:44:09.053809
5309 04:44:09.057026 ----->DramcWriteLeveling(PI) begin...
5310 04:44:09.057150 ==
5311 04:44:09.059832 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 04:44:09.063307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 04:44:09.063427 ==
5314 04:44:09.066740 Write leveling (Byte 0): 35 => 35
5315 04:44:09.070208 Write leveling (Byte 1): 29 => 29
5316 04:44:09.073521 DramcWriteLeveling(PI) end<-----
5317 04:44:09.073645
5318 04:44:09.073741 ==
5319 04:44:09.076939 Dram Type= 6, Freq= 0, CH_0, rank 1
5320 04:44:09.079637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 04:44:09.079752 ==
5322 04:44:09.083112 [Gating] SW mode calibration
5323 04:44:09.089941 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5324 04:44:09.096626 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5325 04:44:09.099753 0 14 0 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
5326 04:44:09.103090 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 04:44:09.109523 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 04:44:09.113279 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 04:44:09.116706 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 04:44:09.122783 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 04:44:09.126196 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5332 04:44:09.129598 0 14 28 | B1->B0 | 2a2a 2a2a | 0 0 | (0 0) (0 1)
5333 04:44:09.136297 0 15 0 | B1->B0 | 2727 2727 | 1 1 | (1 0) (1 0)
5334 04:44:09.139648 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 04:44:09.142999 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 04:44:09.149808 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 04:44:09.152893 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 04:44:09.155832 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 04:44:09.162829 0 15 24 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
5340 04:44:09.166310 0 15 28 | B1->B0 | 4242 3a3a | 0 1 | (0 0) (0 0)
5341 04:44:09.169091 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 04:44:09.175896 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 04:44:09.179261 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 04:44:09.182773 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 04:44:09.188909 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 04:44:09.192408 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 04:44:09.195804 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 04:44:09.202622 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5349 04:44:09.205845 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 04:44:09.209102 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 04:44:09.215683 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 04:44:09.218945 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 04:44:09.222242 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 04:44:09.229147 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 04:44:09.231971 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 04:44:09.235345 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 04:44:09.242021 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 04:44:09.245354 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 04:44:09.248851 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 04:44:09.255659 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 04:44:09.259085 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 04:44:09.262422 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 04:44:09.265576 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 04:44:09.272238 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 04:44:09.275632 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 04:44:09.279061 Total UI for P1: 0, mck2ui 16
5367 04:44:09.282594 best dqsien dly found for B0: ( 1, 2, 30)
5368 04:44:09.285914 Total UI for P1: 0, mck2ui 16
5369 04:44:09.288759 best dqsien dly found for B1: ( 1, 2, 30)
5370 04:44:09.292348 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5371 04:44:09.295513 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5372 04:44:09.295655
5373 04:44:09.298691 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5374 04:44:09.302050 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5375 04:44:09.305514 [Gating] SW calibration Done
5376 04:44:09.305653 ==
5377 04:44:09.308965 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 04:44:09.315504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 04:44:09.315681 ==
5380 04:44:09.315787 RX Vref Scan: 0
5381 04:44:09.315880
5382 04:44:09.318701 RX Vref 0 -> 0, step: 1
5383 04:44:09.318821
5384 04:44:09.322365 RX Delay -80 -> 252, step: 8
5385 04:44:09.325734 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5386 04:44:09.328886 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5387 04:44:09.331632 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5388 04:44:09.334995 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5389 04:44:09.341853 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5390 04:44:09.345226 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5391 04:44:09.348773 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5392 04:44:09.351640 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5393 04:44:09.354809 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5394 04:44:09.358331 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5395 04:44:09.365245 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5396 04:44:09.368726 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5397 04:44:09.371498 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5398 04:44:09.374996 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5399 04:44:09.378411 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5400 04:44:09.381931 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5401 04:44:09.385193 ==
5402 04:44:09.388646 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 04:44:09.391715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 04:44:09.391858 ==
5405 04:44:09.391959 DQS Delay:
5406 04:44:09.394706 DQS0 = 0, DQS1 = 0
5407 04:44:09.394841 DQM Delay:
5408 04:44:09.398100 DQM0 = 104, DQM1 = 94
5409 04:44:09.398236 DQ Delay:
5410 04:44:09.401436 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5411 04:44:09.404871 DQ4 =103, DQ5 =95, DQ6 =111, DQ7 =115
5412 04:44:09.408129 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5413 04:44:09.411648 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5414 04:44:09.411795
5415 04:44:09.411895
5416 04:44:09.411988 ==
5417 04:44:09.414973 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 04:44:09.418293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 04:44:09.421745 ==
5420 04:44:09.421878
5421 04:44:09.421976
5422 04:44:09.422067 TX Vref Scan disable
5423 04:44:09.424809 == TX Byte 0 ==
5424 04:44:09.428109 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5425 04:44:09.431306 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5426 04:44:09.434533 == TX Byte 1 ==
5427 04:44:09.437817 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5428 04:44:09.441117 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5429 04:44:09.444653 ==
5430 04:44:09.444803 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 04:44:09.451462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 04:44:09.451638 ==
5433 04:44:09.451742
5434 04:44:09.451833
5435 04:44:09.454247 TX Vref Scan disable
5436 04:44:09.454368 == TX Byte 0 ==
5437 04:44:09.461099 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5438 04:44:09.464606 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5439 04:44:09.464752 == TX Byte 1 ==
5440 04:44:09.470748 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5441 04:44:09.474214 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5442 04:44:09.474343
5443 04:44:09.474437 [DATLAT]
5444 04:44:09.477663 Freq=933, CH0 RK1
5445 04:44:09.477774
5446 04:44:09.477866 DATLAT Default: 0xb
5447 04:44:09.481082 0, 0xFFFF, sum = 0
5448 04:44:09.481196 1, 0xFFFF, sum = 0
5449 04:44:09.484513 2, 0xFFFF, sum = 0
5450 04:44:09.484625 3, 0xFFFF, sum = 0
5451 04:44:09.487380 4, 0xFFFF, sum = 0
5452 04:44:09.487490 5, 0xFFFF, sum = 0
5453 04:44:09.490862 6, 0xFFFF, sum = 0
5454 04:44:09.494312 7, 0xFFFF, sum = 0
5455 04:44:09.494432 8, 0xFFFF, sum = 0
5456 04:44:09.497708 9, 0xFFFF, sum = 0
5457 04:44:09.497825 10, 0x0, sum = 1
5458 04:44:09.500625 11, 0x0, sum = 2
5459 04:44:09.500737 12, 0x0, sum = 3
5460 04:44:09.500834 13, 0x0, sum = 4
5461 04:44:09.504377 best_step = 11
5462 04:44:09.504490
5463 04:44:09.504584 ==
5464 04:44:09.507802 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 04:44:09.510501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 04:44:09.510620 ==
5467 04:44:09.513862 RX Vref Scan: 0
5468 04:44:09.513986
5469 04:44:09.514084 RX Vref 0 -> 0, step: 1
5470 04:44:09.517084
5471 04:44:09.517203 RX Delay -53 -> 252, step: 4
5472 04:44:09.524539 iDelay=195, Bit 0, Center 102 (15 ~ 190) 176
5473 04:44:09.528177 iDelay=195, Bit 1, Center 106 (19 ~ 194) 176
5474 04:44:09.531320 iDelay=195, Bit 2, Center 102 (15 ~ 190) 176
5475 04:44:09.534715 iDelay=195, Bit 3, Center 102 (15 ~ 190) 176
5476 04:44:09.537933 iDelay=195, Bit 4, Center 106 (19 ~ 194) 176
5477 04:44:09.544712 iDelay=195, Bit 5, Center 98 (11 ~ 186) 176
5478 04:44:09.548066 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5479 04:44:09.551132 iDelay=195, Bit 7, Center 110 (27 ~ 194) 168
5480 04:44:09.554844 iDelay=195, Bit 8, Center 88 (7 ~ 170) 164
5481 04:44:09.557722 iDelay=195, Bit 9, Center 86 (3 ~ 170) 168
5482 04:44:09.564329 iDelay=195, Bit 10, Center 94 (11 ~ 178) 168
5483 04:44:09.567860 iDelay=195, Bit 11, Center 92 (11 ~ 174) 164
5484 04:44:09.571191 iDelay=195, Bit 12, Center 100 (19 ~ 182) 164
5485 04:44:09.574305 iDelay=195, Bit 13, Center 100 (15 ~ 186) 172
5486 04:44:09.577761 iDelay=195, Bit 14, Center 104 (19 ~ 190) 172
5487 04:44:09.584708 iDelay=195, Bit 15, Center 102 (19 ~ 186) 168
5488 04:44:09.584857 ==
5489 04:44:09.587557 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 04:44:09.591017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 04:44:09.591136 ==
5492 04:44:09.591233 DQS Delay:
5493 04:44:09.594396 DQS0 = 0, DQS1 = 0
5494 04:44:09.594517 DQM Delay:
5495 04:44:09.597801 DQM0 = 104, DQM1 = 95
5496 04:44:09.597923 DQ Delay:
5497 04:44:09.601179 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5498 04:44:09.604706 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =110
5499 04:44:09.608021 DQ8 =88, DQ9 =86, DQ10 =94, DQ11 =92
5500 04:44:09.611279 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5501 04:44:09.611412
5502 04:44:09.611510
5503 04:44:09.620842 [DQSOSCAuto] RK1, (LSB)MR18= 0x27ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5504 04:44:09.621021 CH0 RK1: MR19=504, MR18=27FF
5505 04:44:09.627791 CH0_RK1: MR19=0x504, MR18=0x27FF, DQSOSC=409, MR23=63, INC=64, DEC=43
5506 04:44:09.631246 [RxdqsGatingPostProcess] freq 933
5507 04:44:09.638014 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5508 04:44:09.640726 best DQS0 dly(2T, 0.5T) = (0, 10)
5509 04:44:09.644090 best DQS1 dly(2T, 0.5T) = (0, 11)
5510 04:44:09.647507 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5511 04:44:09.650913 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5512 04:44:09.654916 best DQS0 dly(2T, 0.5T) = (0, 10)
5513 04:44:09.655046 best DQS1 dly(2T, 0.5T) = (0, 10)
5514 04:44:09.657746 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5515 04:44:09.661174 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5516 04:44:09.664349 Pre-setting of DQS Precalculation
5517 04:44:09.671346 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5518 04:44:09.671509 ==
5519 04:44:09.674546 Dram Type= 6, Freq= 0, CH_1, rank 0
5520 04:44:09.677832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 04:44:09.677959 ==
5522 04:44:09.684425 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5523 04:44:09.690927 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5524 04:44:09.694295 [CA 0] Center 36 (6~67) winsize 62
5525 04:44:09.697262 [CA 1] Center 36 (6~67) winsize 62
5526 04:44:09.700634 [CA 2] Center 34 (4~65) winsize 62
5527 04:44:09.704422 [CA 3] Center 34 (4~65) winsize 62
5528 04:44:09.707741 [CA 4] Center 34 (4~64) winsize 61
5529 04:44:09.711167 [CA 5] Center 33 (3~64) winsize 62
5530 04:44:09.711290
5531 04:44:09.714425 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5532 04:44:09.714530
5533 04:44:09.717211 [CATrainingPosCal] consider 1 rank data
5534 04:44:09.720732 u2DelayCellTimex100 = 270/100 ps
5535 04:44:09.724182 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5536 04:44:09.727695 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5537 04:44:09.731145 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5538 04:44:09.733951 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5539 04:44:09.737472 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5540 04:44:09.740873 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5541 04:44:09.741009
5542 04:44:09.747759 CA PerBit enable=1, Macro0, CA PI delay=33
5543 04:44:09.747909
5544 04:44:09.748017 [CBTSetCACLKResult] CA Dly = 33
5545 04:44:09.750354 CS Dly: 7 (0~38)
5546 04:44:09.750472 ==
5547 04:44:09.753752 Dram Type= 6, Freq= 0, CH_1, rank 1
5548 04:44:09.757339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 04:44:09.757499 ==
5550 04:44:09.764123 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5551 04:44:09.770220 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5552 04:44:09.773690 [CA 0] Center 36 (6~67) winsize 62
5553 04:44:09.776961 [CA 1] Center 37 (6~68) winsize 63
5554 04:44:09.780721 [CA 2] Center 35 (5~65) winsize 61
5555 04:44:09.784029 [CA 3] Center 34 (4~65) winsize 62
5556 04:44:09.787392 [CA 4] Center 34 (4~65) winsize 62
5557 04:44:09.790813 [CA 5] Center 33 (3~64) winsize 62
5558 04:44:09.790918
5559 04:44:09.794099 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5560 04:44:09.794200
5561 04:44:09.797442 [CATrainingPosCal] consider 2 rank data
5562 04:44:09.800658 u2DelayCellTimex100 = 270/100 ps
5563 04:44:09.803798 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5564 04:44:09.807112 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5565 04:44:09.810433 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5566 04:44:09.813540 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5567 04:44:09.817296 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5568 04:44:09.820162 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5569 04:44:09.823678
5570 04:44:09.827006 CA PerBit enable=1, Macro0, CA PI delay=33
5571 04:44:09.827110
5572 04:44:09.830029 [CBTSetCACLKResult] CA Dly = 33
5573 04:44:09.830162 CS Dly: 8 (0~40)
5574 04:44:09.830261
5575 04:44:09.833524 ----->DramcWriteLeveling(PI) begin...
5576 04:44:09.833643 ==
5577 04:44:09.836992 Dram Type= 6, Freq= 0, CH_1, rank 0
5578 04:44:09.840443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 04:44:09.843206 ==
5580 04:44:09.843320 Write leveling (Byte 0): 23 => 23
5581 04:44:09.846625 Write leveling (Byte 1): 27 => 27
5582 04:44:09.850086 DramcWriteLeveling(PI) end<-----
5583 04:44:09.850214
5584 04:44:09.850309 ==
5585 04:44:09.853535 Dram Type= 6, Freq= 0, CH_1, rank 0
5586 04:44:09.860180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 04:44:09.860343 ==
5588 04:44:09.860444 [Gating] SW mode calibration
5589 04:44:09.870296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5590 04:44:09.873772 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5591 04:44:09.880111 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 04:44:09.883493 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 04:44:09.886806 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 04:44:09.893463 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 04:44:09.896776 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 04:44:09.900069 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5597 04:44:09.906627 0 14 24 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 1)
5598 04:44:09.910043 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5599 04:44:09.913489 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 04:44:09.916813 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 04:44:09.923174 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 04:44:09.926385 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 04:44:09.929780 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 04:44:09.936308 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 04:44:09.940026 0 15 24 | B1->B0 | 2727 3333 | 0 0 | (0 0) (1 1)
5606 04:44:09.942943 0 15 28 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
5607 04:44:09.949785 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 04:44:09.953032 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 04:44:09.956474 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 04:44:09.963279 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 04:44:09.966620 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 04:44:09.969458 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 04:44:09.976123 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5614 04:44:09.979662 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 04:44:09.983098 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 04:44:09.989331 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 04:44:09.992764 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 04:44:09.996122 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 04:44:10.002761 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 04:44:10.006644 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 04:44:10.009584 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 04:44:10.016391 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 04:44:10.019537 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 04:44:10.022725 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 04:44:10.029619 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 04:44:10.033046 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 04:44:10.036463 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 04:44:10.039170 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 04:44:10.045948 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5630 04:44:10.049402 Total UI for P1: 0, mck2ui 16
5631 04:44:10.052534 best dqsien dly found for B0: ( 1, 2, 22)
5632 04:44:10.056334 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5633 04:44:10.059548 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 04:44:10.062514 Total UI for P1: 0, mck2ui 16
5635 04:44:10.066055 best dqsien dly found for B1: ( 1, 2, 26)
5636 04:44:10.069344 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5637 04:44:10.073043 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5638 04:44:10.075738
5639 04:44:10.079078 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5640 04:44:10.082507 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5641 04:44:10.085943 [Gating] SW calibration Done
5642 04:44:10.086027 ==
5643 04:44:10.089377 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 04:44:10.092863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 04:44:10.092952 ==
5646 04:44:10.093020 RX Vref Scan: 0
5647 04:44:10.096267
5648 04:44:10.096370 RX Vref 0 -> 0, step: 1
5649 04:44:10.096442
5650 04:44:10.099094 RX Delay -80 -> 252, step: 8
5651 04:44:10.102642 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5652 04:44:10.106058 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5653 04:44:10.112991 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5654 04:44:10.115759 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5655 04:44:10.119085 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5656 04:44:10.122319 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5657 04:44:10.126186 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5658 04:44:10.129129 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5659 04:44:10.132533 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5660 04:44:10.139149 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5661 04:44:10.143001 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5662 04:44:10.145753 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5663 04:44:10.148896 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5664 04:44:10.152355 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5665 04:44:10.159059 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5666 04:44:10.162421 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5667 04:44:10.162520 ==
5668 04:44:10.165878 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 04:44:10.169230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 04:44:10.169326 ==
5671 04:44:10.172492 DQS Delay:
5672 04:44:10.172591 DQS0 = 0, DQS1 = 0
5673 04:44:10.172657 DQM Delay:
5674 04:44:10.175559 DQM0 = 102, DQM1 = 98
5675 04:44:10.175647 DQ Delay:
5676 04:44:10.179302 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5677 04:44:10.182271 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5678 04:44:10.185842 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5679 04:44:10.189022 DQ12 =107, DQ13 =103, DQ14 =107, DQ15 =107
5680 04:44:10.189123
5681 04:44:10.189190
5682 04:44:10.192257 ==
5683 04:44:10.195760 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 04:44:10.199108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 04:44:10.199240 ==
5686 04:44:10.199340
5687 04:44:10.199431
5688 04:44:10.202511 TX Vref Scan disable
5689 04:44:10.202632 == TX Byte 0 ==
5690 04:44:10.205951 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5691 04:44:10.212125 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5692 04:44:10.212253 == TX Byte 1 ==
5693 04:44:10.215701 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5694 04:44:10.222727 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5695 04:44:10.222822 ==
5696 04:44:10.225474 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 04:44:10.229027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 04:44:10.229116 ==
5699 04:44:10.229183
5700 04:44:10.229243
5701 04:44:10.232484 TX Vref Scan disable
5702 04:44:10.235364 == TX Byte 0 ==
5703 04:44:10.238756 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5704 04:44:10.242048 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5705 04:44:10.245246 == TX Byte 1 ==
5706 04:44:10.249012 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5707 04:44:10.252049 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5708 04:44:10.252177
5709 04:44:10.255517 [DATLAT]
5710 04:44:10.255630 Freq=933, CH1 RK0
5711 04:44:10.255723
5712 04:44:10.258756 DATLAT Default: 0xd
5713 04:44:10.258880 0, 0xFFFF, sum = 0
5714 04:44:10.261936 1, 0xFFFF, sum = 0
5715 04:44:10.262071 2, 0xFFFF, sum = 0
5716 04:44:10.265263 3, 0xFFFF, sum = 0
5717 04:44:10.265365 4, 0xFFFF, sum = 0
5718 04:44:10.268709 5, 0xFFFF, sum = 0
5719 04:44:10.268815 6, 0xFFFF, sum = 0
5720 04:44:10.272207 7, 0xFFFF, sum = 0
5721 04:44:10.272349 8, 0xFFFF, sum = 0
5722 04:44:10.275672 9, 0xFFFF, sum = 0
5723 04:44:10.275794 10, 0x0, sum = 1
5724 04:44:10.278999 11, 0x0, sum = 2
5725 04:44:10.279104 12, 0x0, sum = 3
5726 04:44:10.282408 13, 0x0, sum = 4
5727 04:44:10.282499 best_step = 11
5728 04:44:10.282566
5729 04:44:10.282627 ==
5730 04:44:10.285191 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 04:44:10.288638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 04:44:10.291799 ==
5733 04:44:10.291917 RX Vref Scan: 1
5734 04:44:10.292015
5735 04:44:10.295334 RX Vref 0 -> 0, step: 1
5736 04:44:10.295442
5737 04:44:10.295535 RX Delay -45 -> 252, step: 4
5738 04:44:10.298329
5739 04:44:10.298417 Set Vref, RX VrefLevel [Byte0]: 52
5740 04:44:10.301919 [Byte1]: 49
5741 04:44:10.306917
5742 04:44:10.307012 Final RX Vref Byte 0 = 52 to rank0
5743 04:44:10.310314 Final RX Vref Byte 1 = 49 to rank0
5744 04:44:10.313784 Final RX Vref Byte 0 = 52 to rank1
5745 04:44:10.317313 Final RX Vref Byte 1 = 49 to rank1==
5746 04:44:10.320079 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 04:44:10.323690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 04:44:10.327006 ==
5749 04:44:10.327103 DQS Delay:
5750 04:44:10.327170 DQS0 = 0, DQS1 = 0
5751 04:44:10.330387 DQM Delay:
5752 04:44:10.330470 DQM0 = 103, DQM1 = 99
5753 04:44:10.333813 DQ Delay:
5754 04:44:10.336572 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5755 04:44:10.340127 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5756 04:44:10.343608 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =94
5757 04:44:10.347156 DQ12 =102, DQ13 =104, DQ14 =104, DQ15 =108
5758 04:44:10.347271
5759 04:44:10.347367
5760 04:44:10.353403 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5761 04:44:10.356930 CH1 RK0: MR19=505, MR18=1A32
5762 04:44:10.363295 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5763 04:44:10.363472
5764 04:44:10.366755 ----->DramcWriteLeveling(PI) begin...
5765 04:44:10.366895 ==
5766 04:44:10.370032 Dram Type= 6, Freq= 0, CH_1, rank 1
5767 04:44:10.373423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 04:44:10.373570 ==
5769 04:44:10.376622 Write leveling (Byte 0): 26 => 26
5770 04:44:10.379955 Write leveling (Byte 1): 27 => 27
5771 04:44:10.383103 DramcWriteLeveling(PI) end<-----
5772 04:44:10.383228
5773 04:44:10.383325 ==
5774 04:44:10.386835 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 04:44:10.393123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 04:44:10.393259 ==
5777 04:44:10.393366 [Gating] SW mode calibration
5778 04:44:10.403198 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5779 04:44:10.406858 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5780 04:44:10.410205 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 04:44:10.416679 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 04:44:10.419809 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 04:44:10.423561 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 04:44:10.429841 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 04:44:10.433645 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5786 04:44:10.436253 0 14 24 | B1->B0 | 2f2f 3232 | 1 0 | (1 0) (0 1)
5787 04:44:10.443267 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (1 0) (0 0)
5788 04:44:10.446894 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 04:44:10.449588 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 04:44:10.456475 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 04:44:10.459931 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 04:44:10.463288 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 04:44:10.470430 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5794 04:44:10.473139 0 15 24 | B1->B0 | 3232 2626 | 0 0 | (1 1) (0 0)
5795 04:44:10.476458 0 15 28 | B1->B0 | 4646 3d3d | 0 1 | (0 0) (0 0)
5796 04:44:10.483213 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 04:44:10.486878 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 04:44:10.490361 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 04:44:10.493153 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 04:44:10.500067 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 04:44:10.503372 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 04:44:10.506519 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5803 04:44:10.513342 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5804 04:44:10.516460 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 04:44:10.520012 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 04:44:10.526376 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 04:44:10.529885 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 04:44:10.532912 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 04:44:10.539711 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 04:44:10.543059 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 04:44:10.546581 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 04:44:10.553110 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 04:44:10.556207 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 04:44:10.559570 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 04:44:10.566377 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 04:44:10.569711 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 04:44:10.573131 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 04:44:10.579989 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5819 04:44:10.583361 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 04:44:10.586917 Total UI for P1: 0, mck2ui 16
5821 04:44:10.589746 best dqsien dly found for B0: ( 1, 2, 24)
5822 04:44:10.593075 Total UI for P1: 0, mck2ui 16
5823 04:44:10.596556 best dqsien dly found for B1: ( 1, 2, 24)
5824 04:44:10.599998 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5825 04:44:10.603463 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5826 04:44:10.603560
5827 04:44:10.606920 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5828 04:44:10.609521 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5829 04:44:10.613423 [Gating] SW calibration Done
5830 04:44:10.613513 ==
5831 04:44:10.616835 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 04:44:10.619540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 04:44:10.619655 ==
5834 04:44:10.623090 RX Vref Scan: 0
5835 04:44:10.623202
5836 04:44:10.626340 RX Vref 0 -> 0, step: 1
5837 04:44:10.626454
5838 04:44:10.626548 RX Delay -80 -> 252, step: 8
5839 04:44:10.632907 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5840 04:44:10.636311 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5841 04:44:10.639541 iDelay=208, Bit 2, Center 91 (8 ~ 175) 168
5842 04:44:10.643674 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5843 04:44:10.646907 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5844 04:44:10.650234 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5845 04:44:10.656713 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5846 04:44:10.659968 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5847 04:44:10.663142 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5848 04:44:10.666400 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5849 04:44:10.669706 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5850 04:44:10.673276 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5851 04:44:10.676312 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5852 04:44:10.682964 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5853 04:44:10.686435 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5854 04:44:10.689814 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5855 04:44:10.689904 ==
5856 04:44:10.693178 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 04:44:10.696617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 04:44:10.700099 ==
5859 04:44:10.700207 DQS Delay:
5860 04:44:10.700309 DQS0 = 0, DQS1 = 0
5861 04:44:10.703552 DQM Delay:
5862 04:44:10.703633 DQM0 = 102, DQM1 = 98
5863 04:44:10.706344 DQ Delay:
5864 04:44:10.706448 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5865 04:44:10.709753 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5866 04:44:10.713112 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5867 04:44:10.719718 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5868 04:44:10.719873
5869 04:44:10.719976
5870 04:44:10.720071 ==
5871 04:44:10.723032 Dram Type= 6, Freq= 0, CH_1, rank 1
5872 04:44:10.726389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5873 04:44:10.726506 ==
5874 04:44:10.726600
5875 04:44:10.726689
5876 04:44:10.729994 TX Vref Scan disable
5877 04:44:10.730109 == TX Byte 0 ==
5878 04:44:10.736543 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5879 04:44:10.739612 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5880 04:44:10.739751 == TX Byte 1 ==
5881 04:44:10.746006 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5882 04:44:10.749347 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5883 04:44:10.749447 ==
5884 04:44:10.752795 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 04:44:10.756012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 04:44:10.756106 ==
5887 04:44:10.756172
5888 04:44:10.759382
5889 04:44:10.759468 TX Vref Scan disable
5890 04:44:10.762746 == TX Byte 0 ==
5891 04:44:10.766010 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5892 04:44:10.770049 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5893 04:44:10.772839 == TX Byte 1 ==
5894 04:44:10.776248 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5895 04:44:10.779789 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5896 04:44:10.779921
5897 04:44:10.782676 [DATLAT]
5898 04:44:10.782856 Freq=933, CH1 RK1
5899 04:44:10.782962
5900 04:44:10.786638 DATLAT Default: 0xb
5901 04:44:10.786763 0, 0xFFFF, sum = 0
5902 04:44:10.789717 1, 0xFFFF, sum = 0
5903 04:44:10.789836 2, 0xFFFF, sum = 0
5904 04:44:10.792737 3, 0xFFFF, sum = 0
5905 04:44:10.792858 4, 0xFFFF, sum = 0
5906 04:44:10.796171 5, 0xFFFF, sum = 0
5907 04:44:10.796300 6, 0xFFFF, sum = 0
5908 04:44:10.799735 7, 0xFFFF, sum = 0
5909 04:44:10.802704 8, 0xFFFF, sum = 0
5910 04:44:10.802819 9, 0xFFFF, sum = 0
5911 04:44:10.802925 10, 0x0, sum = 1
5912 04:44:10.806289 11, 0x0, sum = 2
5913 04:44:10.806400 12, 0x0, sum = 3
5914 04:44:10.809676 13, 0x0, sum = 4
5915 04:44:10.809804 best_step = 11
5916 04:44:10.809898
5917 04:44:10.809998 ==
5918 04:44:10.813005 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 04:44:10.819233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 04:44:10.819358 ==
5921 04:44:10.819456 RX Vref Scan: 0
5922 04:44:10.819548
5923 04:44:10.822810 RX Vref 0 -> 0, step: 1
5924 04:44:10.822924
5925 04:44:10.825995 RX Delay -45 -> 252, step: 4
5926 04:44:10.829189 iDelay=199, Bit 0, Center 108 (27 ~ 190) 164
5927 04:44:10.836032 iDelay=199, Bit 1, Center 100 (19 ~ 182) 164
5928 04:44:10.839436 iDelay=199, Bit 2, Center 94 (11 ~ 178) 168
5929 04:44:10.842820 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5930 04:44:10.845957 iDelay=199, Bit 4, Center 100 (19 ~ 182) 164
5931 04:44:10.848898 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5932 04:44:10.852340 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5933 04:44:10.859096 iDelay=199, Bit 7, Center 102 (19 ~ 186) 168
5934 04:44:10.862360 iDelay=199, Bit 8, Center 88 (3 ~ 174) 172
5935 04:44:10.865869 iDelay=199, Bit 9, Center 90 (3 ~ 178) 176
5936 04:44:10.869327 iDelay=199, Bit 10, Center 100 (15 ~ 186) 172
5937 04:44:10.872678 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5938 04:44:10.879308 iDelay=199, Bit 12, Center 108 (19 ~ 198) 180
5939 04:44:10.882580 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5940 04:44:10.886014 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5941 04:44:10.888779 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5942 04:44:10.888895 ==
5943 04:44:10.892137 Dram Type= 6, Freq= 0, CH_1, rank 1
5944 04:44:10.898922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5945 04:44:10.899080 ==
5946 04:44:10.899182 DQS Delay:
5947 04:44:10.899274 DQS0 = 0, DQS1 = 0
5948 04:44:10.902378 DQM Delay:
5949 04:44:10.902463 DQM0 = 104, DQM1 = 99
5950 04:44:10.905661 DQ Delay:
5951 04:44:10.908878 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5952 04:44:10.912087 DQ4 =100, DQ5 =116, DQ6 =114, DQ7 =102
5953 04:44:10.915703 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92
5954 04:44:10.918911 DQ12 =108, DQ13 =104, DQ14 =104, DQ15 =106
5955 04:44:10.919045
5956 04:44:10.919141
5957 04:44:10.925608 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5958 04:44:10.929083 CH1 RK1: MR19=504, MR18=2BFF
5959 04:44:10.935266 CH1_RK1: MR19=0x504, MR18=0x2BFF, DQSOSC=408, MR23=63, INC=65, DEC=43
5960 04:44:10.938441 [RxdqsGatingPostProcess] freq 933
5961 04:44:10.945521 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5962 04:44:10.948930 best DQS0 dly(2T, 0.5T) = (0, 10)
5963 04:44:10.951665 best DQS1 dly(2T, 0.5T) = (0, 10)
5964 04:44:10.951781 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5965 04:44:10.955073 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5966 04:44:10.958923 best DQS0 dly(2T, 0.5T) = (0, 10)
5967 04:44:10.962321 best DQS1 dly(2T, 0.5T) = (0, 10)
5968 04:44:10.965020 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5969 04:44:10.968804 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5970 04:44:10.972173 Pre-setting of DQS Precalculation
5971 04:44:10.978358 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5972 04:44:10.985374 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5973 04:44:10.991676 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5974 04:44:10.991774
5975 04:44:10.991870
5976 04:44:10.995055 [Calibration Summary] 1866 Mbps
5977 04:44:10.995166 CH 0, Rank 0
5978 04:44:10.998599 SW Impedance : PASS
5979 04:44:11.001381 DUTY Scan : NO K
5980 04:44:11.001489 ZQ Calibration : PASS
5981 04:44:11.004909 Jitter Meter : NO K
5982 04:44:11.008306 CBT Training : PASS
5983 04:44:11.008395 Write leveling : PASS
5984 04:44:11.011837 RX DQS gating : PASS
5985 04:44:11.015305 RX DQ/DQS(RDDQC) : PASS
5986 04:44:11.015412 TX DQ/DQS : PASS
5987 04:44:11.018185 RX DATLAT : PASS
5988 04:44:11.022056 RX DQ/DQS(Engine): PASS
5989 04:44:11.022168 TX OE : NO K
5990 04:44:11.022272 All Pass.
5991 04:44:11.022363
5992 04:44:11.024723 CH 0, Rank 1
5993 04:44:11.028624 SW Impedance : PASS
5994 04:44:11.028715 DUTY Scan : NO K
5995 04:44:11.031921 ZQ Calibration : PASS
5996 04:44:11.032026 Jitter Meter : NO K
5997 04:44:11.035087 CBT Training : PASS
5998 04:44:11.038205 Write leveling : PASS
5999 04:44:11.038324 RX DQS gating : PASS
6000 04:44:11.041523 RX DQ/DQS(RDDQC) : PASS
6001 04:44:11.044877 TX DQ/DQS : PASS
6002 04:44:11.044995 RX DATLAT : PASS
6003 04:44:11.048096 RX DQ/DQS(Engine): PASS
6004 04:44:11.051638 TX OE : NO K
6005 04:44:11.051753 All Pass.
6006 04:44:11.051848
6007 04:44:11.051942 CH 1, Rank 0
6008 04:44:11.055099 SW Impedance : PASS
6009 04:44:11.058009 DUTY Scan : NO K
6010 04:44:11.058118 ZQ Calibration : PASS
6011 04:44:11.061426 Jitter Meter : NO K
6012 04:44:11.064711 CBT Training : PASS
6013 04:44:11.064817 Write leveling : PASS
6014 04:44:11.067921 RX DQS gating : PASS
6015 04:44:11.071254 RX DQ/DQS(RDDQC) : PASS
6016 04:44:11.071366 TX DQ/DQS : PASS
6017 04:44:11.075109 RX DATLAT : PASS
6018 04:44:11.075218 RX DQ/DQS(Engine): PASS
6019 04:44:11.078286 TX OE : NO K
6020 04:44:11.078405 All Pass.
6021 04:44:11.078513
6022 04:44:11.081701 CH 1, Rank 1
6023 04:44:11.081812 SW Impedance : PASS
6024 04:44:11.085052 DUTY Scan : NO K
6025 04:44:11.087812 ZQ Calibration : PASS
6026 04:44:11.087924 Jitter Meter : NO K
6027 04:44:11.091557 CBT Training : PASS
6028 04:44:11.094861 Write leveling : PASS
6029 04:44:11.094969 RX DQS gating : PASS
6030 04:44:11.097824 RX DQ/DQS(RDDQC) : PASS
6031 04:44:11.101043 TX DQ/DQS : PASS
6032 04:44:11.101150 RX DATLAT : PASS
6033 04:44:11.104562 RX DQ/DQS(Engine): PASS
6034 04:44:11.107946 TX OE : NO K
6035 04:44:11.108057 All Pass.
6036 04:44:11.108152
6037 04:44:11.108245 DramC Write-DBI off
6038 04:44:11.111280 PER_BANK_REFRESH: Hybrid Mode
6039 04:44:11.114657 TX_TRACKING: ON
6040 04:44:11.121662 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6041 04:44:11.124927 [FAST_K] Save calibration result to emmc
6042 04:44:11.131008 dramc_set_vcore_voltage set vcore to 650000
6043 04:44:11.131129 Read voltage for 400, 6
6044 04:44:11.134260 Vio18 = 0
6045 04:44:11.134364 Vcore = 650000
6046 04:44:11.134457 Vdram = 0
6047 04:44:11.137717 Vddq = 0
6048 04:44:11.137822 Vmddr = 0
6049 04:44:11.141064 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6050 04:44:11.147542 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6051 04:44:11.151017 MEM_TYPE=3, freq_sel=20
6052 04:44:11.154537 sv_algorithm_assistance_LP4_800
6053 04:44:11.157731 ============ PULL DRAM RESETB DOWN ============
6054 04:44:11.161106 ========== PULL DRAM RESETB DOWN end =========
6055 04:44:11.164660 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6056 04:44:11.167395 ===================================
6057 04:44:11.170851 LPDDR4 DRAM CONFIGURATION
6058 04:44:11.174170 ===================================
6059 04:44:11.177518 EX_ROW_EN[0] = 0x0
6060 04:44:11.177604 EX_ROW_EN[1] = 0x0
6061 04:44:11.180933 LP4Y_EN = 0x0
6062 04:44:11.181049 WORK_FSP = 0x0
6063 04:44:11.184359 WL = 0x2
6064 04:44:11.184445 RL = 0x2
6065 04:44:11.187424 BL = 0x2
6066 04:44:11.187506 RPST = 0x0
6067 04:44:11.190829 RD_PRE = 0x0
6068 04:44:11.194004 WR_PRE = 0x1
6069 04:44:11.194121 WR_PST = 0x0
6070 04:44:11.197396 DBI_WR = 0x0
6071 04:44:11.197503 DBI_RD = 0x0
6072 04:44:11.200615 OTF = 0x1
6073 04:44:11.203952 ===================================
6074 04:44:11.207378 ===================================
6075 04:44:11.207480 ANA top config
6076 04:44:11.210833 ===================================
6077 04:44:11.214310 DLL_ASYNC_EN = 0
6078 04:44:11.217104 ALL_SLAVE_EN = 1
6079 04:44:11.217220 NEW_RANK_MODE = 1
6080 04:44:11.220538 DLL_IDLE_MODE = 1
6081 04:44:11.223947 LP45_APHY_COMB_EN = 1
6082 04:44:11.227378 TX_ODT_DIS = 1
6083 04:44:11.227494 NEW_8X_MODE = 1
6084 04:44:11.230695 ===================================
6085 04:44:11.233996 ===================================
6086 04:44:11.237276 data_rate = 800
6087 04:44:11.240776 CKR = 1
6088 04:44:11.244139 DQ_P2S_RATIO = 4
6089 04:44:11.246949 ===================================
6090 04:44:11.250381 CA_P2S_RATIO = 4
6091 04:44:11.253846 DQ_CA_OPEN = 0
6092 04:44:11.253940 DQ_SEMI_OPEN = 1
6093 04:44:11.257074 CA_SEMI_OPEN = 1
6094 04:44:11.260323 CA_FULL_RATE = 0
6095 04:44:11.263381 DQ_CKDIV4_EN = 0
6096 04:44:11.266738 CA_CKDIV4_EN = 1
6097 04:44:11.270160 CA_PREDIV_EN = 0
6098 04:44:11.270291 PH8_DLY = 0
6099 04:44:11.273407 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6100 04:44:11.276999 DQ_AAMCK_DIV = 0
6101 04:44:11.280172 CA_AAMCK_DIV = 0
6102 04:44:11.283457 CA_ADMCK_DIV = 4
6103 04:44:11.286863 DQ_TRACK_CA_EN = 0
6104 04:44:11.286997 CA_PICK = 800
6105 04:44:11.290144 CA_MCKIO = 400
6106 04:44:11.293543 MCKIO_SEMI = 400
6107 04:44:11.296934 PLL_FREQ = 3016
6108 04:44:11.300163 DQ_UI_PI_RATIO = 32
6109 04:44:11.303472 CA_UI_PI_RATIO = 32
6110 04:44:11.306780 ===================================
6111 04:44:11.310127 ===================================
6112 04:44:11.313557 memory_type:LPDDR4
6113 04:44:11.313695 GP_NUM : 10
6114 04:44:11.316345 SRAM_EN : 1
6115 04:44:11.316426 MD32_EN : 0
6116 04:44:11.319686 ===================================
6117 04:44:11.323065 [ANA_INIT] >>>>>>>>>>>>>>
6118 04:44:11.326430 <<<<<< [CONFIGURE PHASE]: ANA_TX
6119 04:44:11.329947 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6120 04:44:11.333421 ===================================
6121 04:44:11.336744 data_rate = 800,PCW = 0X7400
6122 04:44:11.339582 ===================================
6123 04:44:11.343270 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6124 04:44:11.349454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6125 04:44:11.359756 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6126 04:44:11.363131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6127 04:44:11.366653 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6128 04:44:11.369369 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6129 04:44:11.372832 [ANA_INIT] flow start
6130 04:44:11.376208 [ANA_INIT] PLL >>>>>>>>
6131 04:44:11.376354 [ANA_INIT] PLL <<<<<<<<
6132 04:44:11.379557 [ANA_INIT] MIDPI >>>>>>>>
6133 04:44:11.382688 [ANA_INIT] MIDPI <<<<<<<<
6134 04:44:11.386407 [ANA_INIT] DLL >>>>>>>>
6135 04:44:11.386512 [ANA_INIT] flow end
6136 04:44:11.389452 ============ LP4 DIFF to SE enter ============
6137 04:44:11.396242 ============ LP4 DIFF to SE exit ============
6138 04:44:11.396372 [ANA_INIT] <<<<<<<<<<<<<
6139 04:44:11.399539 [Flow] Enable top DCM control >>>>>
6140 04:44:11.402907 [Flow] Enable top DCM control <<<<<
6141 04:44:11.405953 Enable DLL master slave shuffle
6142 04:44:11.412823 ==============================================================
6143 04:44:11.412924 Gating Mode config
6144 04:44:11.419502 ==============================================================
6145 04:44:11.423057 Config description:
6146 04:44:11.433070 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6147 04:44:11.436468 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6148 04:44:11.442622 SELPH_MODE 0: By rank 1: By Phase
6149 04:44:11.449320 ==============================================================
6150 04:44:11.452556 GAT_TRACK_EN = 0
6151 04:44:11.452680 RX_GATING_MODE = 2
6152 04:44:11.455893 RX_GATING_TRACK_MODE = 2
6153 04:44:11.459393 SELPH_MODE = 1
6154 04:44:11.462817 PICG_EARLY_EN = 1
6155 04:44:11.466336 VALID_LAT_VALUE = 1
6156 04:44:11.472383 ==============================================================
6157 04:44:11.476006 Enter into Gating configuration >>>>
6158 04:44:11.479655 Exit from Gating configuration <<<<
6159 04:44:11.483084 Enter into DVFS_PRE_config >>>>>
6160 04:44:11.492708 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6161 04:44:11.496127 Exit from DVFS_PRE_config <<<<<
6162 04:44:11.499390 Enter into PICG configuration >>>>
6163 04:44:11.502766 Exit from PICG configuration <<<<
6164 04:44:11.506234 [RX_INPUT] configuration >>>>>
6165 04:44:11.509605 [RX_INPUT] configuration <<<<<
6166 04:44:11.512826 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6167 04:44:11.519239 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6168 04:44:11.525926 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6169 04:44:11.529422 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6170 04:44:11.535777 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6171 04:44:11.542580 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6172 04:44:11.546086 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6173 04:44:11.549078 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6174 04:44:11.555899 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6175 04:44:11.558916 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6176 04:44:11.562410 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6177 04:44:11.569306 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6178 04:44:11.572457 ===================================
6179 04:44:11.572561 LPDDR4 DRAM CONFIGURATION
6180 04:44:11.575590 ===================================
6181 04:44:11.579537 EX_ROW_EN[0] = 0x0
6182 04:44:11.579632 EX_ROW_EN[1] = 0x0
6183 04:44:11.582227 LP4Y_EN = 0x0
6184 04:44:11.585720 WORK_FSP = 0x0
6185 04:44:11.585808 WL = 0x2
6186 04:44:11.589159 RL = 0x2
6187 04:44:11.589243 BL = 0x2
6188 04:44:11.592617 RPST = 0x0
6189 04:44:11.592706 RD_PRE = 0x0
6190 04:44:11.595999 WR_PRE = 0x1
6191 04:44:11.596110 WR_PST = 0x0
6192 04:44:11.599455 DBI_WR = 0x0
6193 04:44:11.599542 DBI_RD = 0x0
6194 04:44:11.602761 OTF = 0x1
6195 04:44:11.605956 ===================================
6196 04:44:11.609431 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6197 04:44:11.612982 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6198 04:44:11.615707 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6199 04:44:11.619125 ===================================
6200 04:44:11.622588 LPDDR4 DRAM CONFIGURATION
6201 04:44:11.626050 ===================================
6202 04:44:11.629402 EX_ROW_EN[0] = 0x10
6203 04:44:11.629506 EX_ROW_EN[1] = 0x0
6204 04:44:11.632138 LP4Y_EN = 0x0
6205 04:44:11.632255 WORK_FSP = 0x0
6206 04:44:11.635627 WL = 0x2
6207 04:44:11.635732 RL = 0x2
6208 04:44:11.639055 BL = 0x2
6209 04:44:11.639184 RPST = 0x0
6210 04:44:11.642327 RD_PRE = 0x0
6211 04:44:11.645678 WR_PRE = 0x1
6212 04:44:11.645833 WR_PST = 0x0
6213 04:44:11.649001 DBI_WR = 0x0
6214 04:44:11.649165 DBI_RD = 0x0
6215 04:44:11.652401 OTF = 0x1
6216 04:44:11.655716 ===================================
6217 04:44:11.658947 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6218 04:44:11.663941 nWR fixed to 30
6219 04:44:11.667425 [ModeRegInit_LP4] CH0 RK0
6220 04:44:11.667538 [ModeRegInit_LP4] CH0 RK1
6221 04:44:11.671047 [ModeRegInit_LP4] CH1 RK0
6222 04:44:11.674095 [ModeRegInit_LP4] CH1 RK1
6223 04:44:11.674195 match AC timing 19
6224 04:44:11.680676 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6225 04:44:11.684024 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6226 04:44:11.687654 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6227 04:44:11.694022 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6228 04:44:11.697449 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6229 04:44:11.697586 ==
6230 04:44:11.700686 Dram Type= 6, Freq= 0, CH_0, rank 0
6231 04:44:11.703862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6232 04:44:11.704014 ==
6233 04:44:11.711149 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6234 04:44:11.717124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6235 04:44:11.720695 [CA 0] Center 36 (8~64) winsize 57
6236 04:44:11.723931 [CA 1] Center 36 (8~64) winsize 57
6237 04:44:11.727193 [CA 2] Center 36 (8~64) winsize 57
6238 04:44:11.727336 [CA 3] Center 36 (8~64) winsize 57
6239 04:44:11.730701 [CA 4] Center 36 (8~64) winsize 57
6240 04:44:11.733972 [CA 5] Center 36 (8~64) winsize 57
6241 04:44:11.734117
6242 04:44:11.740707 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6243 04:44:11.740861
6244 04:44:11.744035 [CATrainingPosCal] consider 1 rank data
6245 04:44:11.746792 u2DelayCellTimex100 = 270/100 ps
6246 04:44:11.750162 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 04:44:11.753608 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 04:44:11.756929 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 04:44:11.760395 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 04:44:11.763777 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 04:44:11.767198 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 04:44:11.767344
6253 04:44:11.769925 CA PerBit enable=1, Macro0, CA PI delay=36
6254 04:44:11.770065
6255 04:44:11.773364 [CBTSetCACLKResult] CA Dly = 36
6256 04:44:11.776656 CS Dly: 1 (0~32)
6257 04:44:11.776801 ==
6258 04:44:11.779948 Dram Type= 6, Freq= 0, CH_0, rank 1
6259 04:44:11.783306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 04:44:11.783453 ==
6261 04:44:11.790228 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6262 04:44:11.797018 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6263 04:44:11.799829 [CA 0] Center 36 (8~64) winsize 57
6264 04:44:11.799994 [CA 1] Center 36 (8~64) winsize 57
6265 04:44:11.803666 [CA 2] Center 36 (8~64) winsize 57
6266 04:44:11.806259 [CA 3] Center 36 (8~64) winsize 57
6267 04:44:11.809583 [CA 4] Center 36 (8~64) winsize 57
6268 04:44:11.813288 [CA 5] Center 36 (8~64) winsize 57
6269 04:44:11.813416
6270 04:44:11.816208 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6271 04:44:11.816330
6272 04:44:11.819743 [CATrainingPosCal] consider 2 rank data
6273 04:44:11.823227 u2DelayCellTimex100 = 270/100 ps
6274 04:44:11.826512 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 04:44:11.833431 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 04:44:11.836596 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 04:44:11.840018 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 04:44:11.843499 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 04:44:11.846185 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 04:44:11.846325
6281 04:44:11.849570 CA PerBit enable=1, Macro0, CA PI delay=36
6282 04:44:11.849657
6283 04:44:11.852925 [CBTSetCACLKResult] CA Dly = 36
6284 04:44:11.853038 CS Dly: 1 (0~32)
6285 04:44:11.853143
6286 04:44:11.859716 ----->DramcWriteLeveling(PI) begin...
6287 04:44:11.859859 ==
6288 04:44:11.862742 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 04:44:11.866055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 04:44:11.866173 ==
6291 04:44:11.869509 Write leveling (Byte 0): 40 => 8
6292 04:44:11.872896 Write leveling (Byte 1): 40 => 8
6293 04:44:11.876153 DramcWriteLeveling(PI) end<-----
6294 04:44:11.876274
6295 04:44:11.876384 ==
6296 04:44:11.879621 Dram Type= 6, Freq= 0, CH_0, rank 0
6297 04:44:11.883040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 04:44:11.883184 ==
6299 04:44:11.886226 [Gating] SW mode calibration
6300 04:44:11.892846 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6301 04:44:11.899247 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6302 04:44:11.902770 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6303 04:44:11.906018 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6304 04:44:11.912961 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6305 04:44:11.915685 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 04:44:11.919054 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 04:44:11.926005 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 04:44:11.929346 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 04:44:11.932675 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 04:44:11.939330 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6311 04:44:11.939488 Total UI for P1: 0, mck2ui 16
6312 04:44:11.942508 best dqsien dly found for B0: ( 0, 14, 24)
6313 04:44:11.945545 Total UI for P1: 0, mck2ui 16
6314 04:44:11.949258 best dqsien dly found for B1: ( 0, 14, 24)
6315 04:44:11.955420 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6316 04:44:11.959211 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6317 04:44:11.959366
6318 04:44:11.962284 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6319 04:44:11.965792 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6320 04:44:11.968854 [Gating] SW calibration Done
6321 04:44:11.969011 ==
6322 04:44:11.972347 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 04:44:11.975743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 04:44:11.975856 ==
6325 04:44:11.978998 RX Vref Scan: 0
6326 04:44:11.979111
6327 04:44:11.979207 RX Vref 0 -> 0, step: 1
6328 04:44:11.979301
6329 04:44:11.982509 RX Delay -410 -> 252, step: 16
6330 04:44:11.985906 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6331 04:44:11.992248 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6332 04:44:11.995730 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6333 04:44:11.999048 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6334 04:44:12.002439 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6335 04:44:12.009199 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6336 04:44:12.012369 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6337 04:44:12.015346 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6338 04:44:12.018902 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6339 04:44:12.025631 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6340 04:44:12.028993 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6341 04:44:12.032467 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6342 04:44:12.035761 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6343 04:44:12.041734 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6344 04:44:12.045217 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6345 04:44:12.048750 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6346 04:44:12.048904 ==
6347 04:44:12.052185 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 04:44:12.058985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 04:44:12.059145 ==
6350 04:44:12.059242 DQS Delay:
6351 04:44:12.062355 DQS0 = 27, DQS1 = 35
6352 04:44:12.062466 DQM Delay:
6353 04:44:12.062560 DQM0 = 9, DQM1 = 12
6354 04:44:12.065797 DQ Delay:
6355 04:44:12.068904 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6356 04:44:12.069016 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =16
6357 04:44:12.071907 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6358 04:44:12.075662 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6359 04:44:12.075780
6360 04:44:12.078508
6361 04:44:12.078617 ==
6362 04:44:12.081887 Dram Type= 6, Freq= 0, CH_0, rank 0
6363 04:44:12.085488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6364 04:44:12.085604 ==
6365 04:44:12.085701
6366 04:44:12.085790
6367 04:44:12.088436 TX Vref Scan disable
6368 04:44:12.088558 == TX Byte 0 ==
6369 04:44:12.092041 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6370 04:44:12.098344 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6371 04:44:12.098488 == TX Byte 1 ==
6372 04:44:12.101495 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6373 04:44:12.108193 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6374 04:44:12.108348 ==
6375 04:44:12.111724 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 04:44:12.115216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 04:44:12.115304 ==
6378 04:44:12.115383
6379 04:44:12.115450
6380 04:44:12.118402 TX Vref Scan disable
6381 04:44:12.118478 == TX Byte 0 ==
6382 04:44:12.121823 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6383 04:44:12.128451 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6384 04:44:12.128566 == TX Byte 1 ==
6385 04:44:12.131560 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 04:44:12.138411 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 04:44:12.138537
6388 04:44:12.138604 [DATLAT]
6389 04:44:12.138677 Freq=400, CH0 RK0
6390 04:44:12.138737
6391 04:44:12.141830 DATLAT Default: 0xf
6392 04:44:12.145202 0, 0xFFFF, sum = 0
6393 04:44:12.145312 1, 0xFFFF, sum = 0
6394 04:44:12.148558 2, 0xFFFF, sum = 0
6395 04:44:12.148686 3, 0xFFFF, sum = 0
6396 04:44:12.151907 4, 0xFFFF, sum = 0
6397 04:44:12.152032 5, 0xFFFF, sum = 0
6398 04:44:12.155339 6, 0xFFFF, sum = 0
6399 04:44:12.155456 7, 0xFFFF, sum = 0
6400 04:44:12.158024 8, 0xFFFF, sum = 0
6401 04:44:12.158142 9, 0xFFFF, sum = 0
6402 04:44:12.161526 10, 0xFFFF, sum = 0
6403 04:44:12.161651 11, 0xFFFF, sum = 0
6404 04:44:12.165027 12, 0xFFFF, sum = 0
6405 04:44:12.165156 13, 0x0, sum = 1
6406 04:44:12.168278 14, 0x0, sum = 2
6407 04:44:12.168430 15, 0x0, sum = 3
6408 04:44:12.171832 16, 0x0, sum = 4
6409 04:44:12.171956 best_step = 14
6410 04:44:12.172052
6411 04:44:12.172143 ==
6412 04:44:12.175230 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 04:44:12.178312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 04:44:12.181694 ==
6415 04:44:12.181828 RX Vref Scan: 1
6416 04:44:12.181926
6417 04:44:12.185102 RX Vref 0 -> 0, step: 1
6418 04:44:12.185219
6419 04:44:12.188513 RX Delay -311 -> 252, step: 8
6420 04:44:12.188627
6421 04:44:12.191753 Set Vref, RX VrefLevel [Byte0]: 54
6422 04:44:12.195015 [Byte1]: 53
6423 04:44:12.195134
6424 04:44:12.198367 Final RX Vref Byte 0 = 54 to rank0
6425 04:44:12.201651 Final RX Vref Byte 1 = 53 to rank0
6426 04:44:12.204870 Final RX Vref Byte 0 = 54 to rank1
6427 04:44:12.208122 Final RX Vref Byte 1 = 53 to rank1==
6428 04:44:12.211860 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 04:44:12.214886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 04:44:12.215011 ==
6431 04:44:12.217885 DQS Delay:
6432 04:44:12.218001 DQS0 = 28, DQS1 = 36
6433 04:44:12.221666 DQM Delay:
6434 04:44:12.221785 DQM0 = 11, DQM1 = 13
6435 04:44:12.221882 DQ Delay:
6436 04:44:12.224926 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6437 04:44:12.228517 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6438 04:44:12.231886 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6439 04:44:12.234541 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6440 04:44:12.234659
6441 04:44:12.234754
6442 04:44:12.244531 [DQSOSCAuto] RK0, (LSB)MR18= 0xc5b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6443 04:44:12.244702 CH0 RK0: MR19=C0C, MR18=C5B3
6444 04:44:12.251109 CH0_RK0: MR19=0xC0C, MR18=0xC5B3, DQSOSC=385, MR23=63, INC=398, DEC=265
6445 04:44:12.251277 ==
6446 04:44:12.254637 Dram Type= 6, Freq= 0, CH_0, rank 1
6447 04:44:12.261495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 04:44:12.261659 ==
6449 04:44:12.261764 [Gating] SW mode calibration
6450 04:44:12.271650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6451 04:44:12.275086 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6452 04:44:12.281217 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6453 04:44:12.284810 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6454 04:44:12.288036 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6455 04:44:12.294424 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 04:44:12.297851 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 04:44:12.301146 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 04:44:12.304385 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 04:44:12.311182 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 04:44:12.314722 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 04:44:12.318168 Total UI for P1: 0, mck2ui 16
6462 04:44:12.321569 best dqsien dly found for B0: ( 0, 14, 24)
6463 04:44:12.324233 Total UI for P1: 0, mck2ui 16
6464 04:44:12.327522 best dqsien dly found for B1: ( 0, 14, 24)
6465 04:44:12.331374 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6466 04:44:12.334581 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6467 04:44:12.334692
6468 04:44:12.337819 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6469 04:44:12.344659 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6470 04:44:12.344788 [Gating] SW calibration Done
6471 04:44:12.344889 ==
6472 04:44:12.348040 Dram Type= 6, Freq= 0, CH_0, rank 1
6473 04:44:12.354149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 04:44:12.354271 ==
6475 04:44:12.354362 RX Vref Scan: 0
6476 04:44:12.354447
6477 04:44:12.357522 RX Vref 0 -> 0, step: 1
6478 04:44:12.357627
6479 04:44:12.360867 RX Delay -410 -> 252, step: 16
6480 04:44:12.364000 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6481 04:44:12.367549 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6482 04:44:12.374370 iDelay=230, Bit 2, Center -11 (-234 ~ 213) 448
6483 04:44:12.377606 iDelay=230, Bit 3, Center -11 (-234 ~ 213) 448
6484 04:44:12.381044 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6485 04:44:12.384456 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6486 04:44:12.391008 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6487 04:44:12.394416 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6488 04:44:12.397183 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6489 04:44:12.400564 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6490 04:44:12.407210 iDelay=230, Bit 10, Center -11 (-234 ~ 213) 448
6491 04:44:12.410471 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6492 04:44:12.413817 iDelay=230, Bit 12, Center -11 (-234 ~ 213) 448
6493 04:44:12.417373 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6494 04:44:12.424101 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6495 04:44:12.427539 iDelay=230, Bit 15, Center -11 (-234 ~ 213) 448
6496 04:44:12.427719 ==
6497 04:44:12.430368 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 04:44:12.433764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 04:44:12.433919 ==
6500 04:44:12.437084 DQS Delay:
6501 04:44:12.437213 DQS0 = 27, DQS1 = 35
6502 04:44:12.437307 DQM Delay:
6503 04:44:12.440581 DQM0 = 17, DQM1 = 15
6504 04:44:12.440687 DQ Delay:
6505 04:44:12.444193 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6506 04:44:12.446962 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6507 04:44:12.450361 DQ8 =0, DQ9 =0, DQ10 =24, DQ11 =0
6508 04:44:12.453549 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6509 04:44:12.453663
6510 04:44:12.453760
6511 04:44:12.453849 ==
6512 04:44:12.457284 Dram Type= 6, Freq= 0, CH_0, rank 1
6513 04:44:12.463630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6514 04:44:12.463742 ==
6515 04:44:12.463837
6516 04:44:12.463924
6517 04:44:12.464013 TX Vref Scan disable
6518 04:44:12.467162 == TX Byte 0 ==
6519 04:44:12.470616 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6520 04:44:12.474147 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6521 04:44:12.477522 == TX Byte 1 ==
6522 04:44:12.480668 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6523 04:44:12.483773 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6524 04:44:12.483879 ==
6525 04:44:12.486837 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 04:44:12.493881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 04:44:12.493991 ==
6528 04:44:12.494083
6529 04:44:12.494171
6530 04:44:12.494258 TX Vref Scan disable
6531 04:44:12.497099 == TX Byte 0 ==
6532 04:44:12.500547 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6533 04:44:12.503817 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6534 04:44:12.507238 == TX Byte 1 ==
6535 04:44:12.510770 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6536 04:44:12.514031 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6537 04:44:12.514141
6538 04:44:12.517194 [DATLAT]
6539 04:44:12.517306 Freq=400, CH0 RK1
6540 04:44:12.517403
6541 04:44:12.520577 DATLAT Default: 0xe
6542 04:44:12.520686 0, 0xFFFF, sum = 0
6543 04:44:12.523982 1, 0xFFFF, sum = 0
6544 04:44:12.524089 2, 0xFFFF, sum = 0
6545 04:44:12.526696 3, 0xFFFF, sum = 0
6546 04:44:12.526805 4, 0xFFFF, sum = 0
6547 04:44:12.530080 5, 0xFFFF, sum = 0
6548 04:44:12.530187 6, 0xFFFF, sum = 0
6549 04:44:12.533565 7, 0xFFFF, sum = 0
6550 04:44:12.533677 8, 0xFFFF, sum = 0
6551 04:44:12.536989 9, 0xFFFF, sum = 0
6552 04:44:12.537100 10, 0xFFFF, sum = 0
6553 04:44:12.540332 11, 0xFFFF, sum = 0
6554 04:44:12.543932 12, 0xFFFF, sum = 0
6555 04:44:12.544043 13, 0x0, sum = 1
6556 04:44:12.544139 14, 0x0, sum = 2
6557 04:44:12.547182 15, 0x0, sum = 3
6558 04:44:12.547291 16, 0x0, sum = 4
6559 04:44:12.550003 best_step = 14
6560 04:44:12.550112
6561 04:44:12.550206 ==
6562 04:44:12.553394 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 04:44:12.556787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 04:44:12.556896 ==
6565 04:44:12.560134 RX Vref Scan: 0
6566 04:44:12.560238
6567 04:44:12.560337 RX Vref 0 -> 0, step: 1
6568 04:44:12.560427
6569 04:44:12.563576 RX Delay -311 -> 252, step: 8
6570 04:44:12.571542 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6571 04:44:12.574749 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6572 04:44:12.578109 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6573 04:44:12.581632 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6574 04:44:12.587750 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6575 04:44:12.591154 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6576 04:44:12.594694 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6577 04:44:12.598012 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6578 04:44:12.604568 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6579 04:44:12.607984 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6580 04:44:12.611518 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6581 04:44:12.617906 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6582 04:44:12.621118 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6583 04:44:12.624010 iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432
6584 04:44:12.627390 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6585 04:44:12.634565 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6586 04:44:12.634705 ==
6587 04:44:12.637779 Dram Type= 6, Freq= 0, CH_0, rank 1
6588 04:44:12.641074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 04:44:12.641186 ==
6590 04:44:12.641281 DQS Delay:
6591 04:44:12.644301 DQS0 = 24, DQS1 = 32
6592 04:44:12.644408 DQM Delay:
6593 04:44:12.647847 DQM0 = 9, DQM1 = 10
6594 04:44:12.647959 DQ Delay:
6595 04:44:12.651200 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6596 04:44:12.653902 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6597 04:44:12.657202 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6598 04:44:12.660664 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =16
6599 04:44:12.660774
6600 04:44:12.660868
6601 04:44:12.667413 [DQSOSCAuto] RK1, (LSB)MR18= 0xb455, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6602 04:44:12.670957 CH0 RK1: MR19=C0C, MR18=B455
6603 04:44:12.677657 CH0_RK1: MR19=0xC0C, MR18=0xB455, DQSOSC=387, MR23=63, INC=394, DEC=262
6604 04:44:12.680836 [RxdqsGatingPostProcess] freq 400
6605 04:44:12.687391 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6606 04:44:12.690794 best DQS0 dly(2T, 0.5T) = (0, 10)
6607 04:44:12.690900 best DQS1 dly(2T, 0.5T) = (0, 10)
6608 04:44:12.694218 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6609 04:44:12.697050 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6610 04:44:12.700592 best DQS0 dly(2T, 0.5T) = (0, 10)
6611 04:44:12.704002 best DQS1 dly(2T, 0.5T) = (0, 10)
6612 04:44:12.707335 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6613 04:44:12.710841 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6614 04:44:12.713812 Pre-setting of DQS Precalculation
6615 04:44:12.720383 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6616 04:44:12.720555 ==
6617 04:44:12.723541 Dram Type= 6, Freq= 0, CH_1, rank 0
6618 04:44:12.727198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 04:44:12.727313 ==
6620 04:44:12.733767 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6621 04:44:12.736832 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6622 04:44:12.740646 [CA 0] Center 36 (8~64) winsize 57
6623 04:44:12.743869 [CA 1] Center 36 (8~64) winsize 57
6624 04:44:12.746860 [CA 2] Center 36 (8~64) winsize 57
6625 04:44:12.750241 [CA 3] Center 36 (8~64) winsize 57
6626 04:44:12.753535 [CA 4] Center 36 (8~64) winsize 57
6627 04:44:12.756864 [CA 5] Center 36 (8~64) winsize 57
6628 04:44:12.756993
6629 04:44:12.760306 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6630 04:44:12.760390
6631 04:44:12.763768 [CATrainingPosCal] consider 1 rank data
6632 04:44:12.766846 u2DelayCellTimex100 = 270/100 ps
6633 04:44:12.770030 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 04:44:12.774171 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 04:44:12.776757 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 04:44:12.783695 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 04:44:12.787095 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 04:44:12.790579 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 04:44:12.790656
6640 04:44:12.794055 CA PerBit enable=1, Macro0, CA PI delay=36
6641 04:44:12.794126
6642 04:44:12.797117 [CBTSetCACLKResult] CA Dly = 36
6643 04:44:12.797204 CS Dly: 1 (0~32)
6644 04:44:12.797285 ==
6645 04:44:12.800280 Dram Type= 6, Freq= 0, CH_1, rank 1
6646 04:44:12.807056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 04:44:12.807215 ==
6648 04:44:12.810538 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6649 04:44:12.817300 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6650 04:44:12.820061 [CA 0] Center 36 (8~64) winsize 57
6651 04:44:12.823410 [CA 1] Center 36 (8~64) winsize 57
6652 04:44:12.826876 [CA 2] Center 36 (8~64) winsize 57
6653 04:44:12.830223 [CA 3] Center 36 (8~64) winsize 57
6654 04:44:12.833432 [CA 4] Center 36 (8~64) winsize 57
6655 04:44:12.836732 [CA 5] Center 36 (8~64) winsize 57
6656 04:44:12.836839
6657 04:44:12.840040 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6658 04:44:12.840179
6659 04:44:12.843512 [CATrainingPosCal] consider 2 rank data
6660 04:44:12.846882 u2DelayCellTimex100 = 270/100 ps
6661 04:44:12.850300 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 04:44:12.853775 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 04:44:12.857087 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 04:44:12.860312 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 04:44:12.863431 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 04:44:12.866633 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 04:44:12.866834
6668 04:44:12.873556 CA PerBit enable=1, Macro0, CA PI delay=36
6669 04:44:12.873719
6670 04:44:12.876707 [CBTSetCACLKResult] CA Dly = 36
6671 04:44:12.876885 CS Dly: 1 (0~32)
6672 04:44:12.876995
6673 04:44:12.880138 ----->DramcWriteLeveling(PI) begin...
6674 04:44:12.880315 ==
6675 04:44:12.883558 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 04:44:12.886467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 04:44:12.886601 ==
6678 04:44:12.889799 Write leveling (Byte 0): 40 => 8
6679 04:44:12.893449 Write leveling (Byte 1): 40 => 8
6680 04:44:12.896674 DramcWriteLeveling(PI) end<-----
6681 04:44:12.896798
6682 04:44:12.896873 ==
6683 04:44:12.899984 Dram Type= 6, Freq= 0, CH_1, rank 0
6684 04:44:12.903445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 04:44:12.906796 ==
6686 04:44:12.906945 [Gating] SW mode calibration
6687 04:44:12.916678 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6688 04:44:12.920026 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6689 04:44:12.923301 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6690 04:44:12.930283 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6691 04:44:12.933677 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6692 04:44:12.937108 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 04:44:12.943535 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 04:44:12.946767 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 04:44:12.950169 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 04:44:12.956348 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 04:44:12.959828 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6698 04:44:12.963194 Total UI for P1: 0, mck2ui 16
6699 04:44:12.966530 best dqsien dly found for B0: ( 0, 14, 24)
6700 04:44:12.969824 Total UI for P1: 0, mck2ui 16
6701 04:44:12.973292 best dqsien dly found for B1: ( 0, 14, 24)
6702 04:44:12.976846 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6703 04:44:12.980327 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6704 04:44:12.980438
6705 04:44:12.982927 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6706 04:44:12.986276 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6707 04:44:12.989694 [Gating] SW calibration Done
6708 04:44:12.989775 ==
6709 04:44:12.993057 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 04:44:12.996869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 04:44:12.996980 ==
6712 04:44:12.999918 RX Vref Scan: 0
6713 04:44:12.999993
6714 04:44:13.003408 RX Vref 0 -> 0, step: 1
6715 04:44:13.003493
6716 04:44:13.003558 RX Delay -410 -> 252, step: 16
6717 04:44:13.009950 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6718 04:44:13.013578 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6719 04:44:13.016514 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6720 04:44:13.023306 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6721 04:44:13.026407 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6722 04:44:13.029645 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6723 04:44:13.033629 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6724 04:44:13.036441 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6725 04:44:13.043247 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6726 04:44:13.046540 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6727 04:44:13.049945 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6728 04:44:13.056410 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6729 04:44:13.059717 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6730 04:44:13.063147 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6731 04:44:13.066638 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6732 04:44:13.073420 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6733 04:44:13.073537 ==
6734 04:44:13.076143 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 04:44:13.079982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 04:44:13.080104 ==
6737 04:44:13.080201 DQS Delay:
6738 04:44:13.082738 DQS0 = 35, DQS1 = 35
6739 04:44:13.082844 DQM Delay:
6740 04:44:13.086226 DQM0 = 17, DQM1 = 12
6741 04:44:13.086333 DQ Delay:
6742 04:44:13.089697 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6743 04:44:13.093016 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6744 04:44:13.096489 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6745 04:44:13.099928 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6746 04:44:13.100037
6747 04:44:13.100134
6748 04:44:13.100230 ==
6749 04:44:13.102749 Dram Type= 6, Freq= 0, CH_1, rank 0
6750 04:44:13.106247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6751 04:44:13.106399 ==
6752 04:44:13.106531
6753 04:44:13.106660
6754 04:44:13.109502 TX Vref Scan disable
6755 04:44:13.112852 == TX Byte 0 ==
6756 04:44:13.116236 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6757 04:44:13.119660 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6758 04:44:13.122914 == TX Byte 1 ==
6759 04:44:13.126116 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 04:44:13.129186 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 04:44:13.129361 ==
6762 04:44:13.133000 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 04:44:13.136150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 04:44:13.136327 ==
6765 04:44:13.139358
6766 04:44:13.139470
6767 04:44:13.139538 TX Vref Scan disable
6768 04:44:13.142503 == TX Byte 0 ==
6769 04:44:13.146053 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6770 04:44:13.149125 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6771 04:44:13.152903 == TX Byte 1 ==
6772 04:44:13.156427 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 04:44:13.159693 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 04:44:13.159810
6775 04:44:13.159905 [DATLAT]
6776 04:44:13.162916 Freq=400, CH1 RK0
6777 04:44:13.163020
6778 04:44:13.163120 DATLAT Default: 0xf
6779 04:44:13.166119 0, 0xFFFF, sum = 0
6780 04:44:13.166250 1, 0xFFFF, sum = 0
6781 04:44:13.169418 2, 0xFFFF, sum = 0
6782 04:44:13.172770 3, 0xFFFF, sum = 0
6783 04:44:13.172898 4, 0xFFFF, sum = 0
6784 04:44:13.176196 5, 0xFFFF, sum = 0
6785 04:44:13.176332 6, 0xFFFF, sum = 0
6786 04:44:13.179025 7, 0xFFFF, sum = 0
6787 04:44:13.179145 8, 0xFFFF, sum = 0
6788 04:44:13.182821 9, 0xFFFF, sum = 0
6789 04:44:13.182933 10, 0xFFFF, sum = 0
6790 04:44:13.186286 11, 0xFFFF, sum = 0
6791 04:44:13.186393 12, 0xFFFF, sum = 0
6792 04:44:13.188920 13, 0x0, sum = 1
6793 04:44:13.189028 14, 0x0, sum = 2
6794 04:44:13.192318 15, 0x0, sum = 3
6795 04:44:13.192423 16, 0x0, sum = 4
6796 04:44:13.195643 best_step = 14
6797 04:44:13.195745
6798 04:44:13.195838 ==
6799 04:44:13.199011 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 04:44:13.202366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 04:44:13.202523 ==
6802 04:44:13.202654 RX Vref Scan: 1
6803 04:44:13.205766
6804 04:44:13.205914 RX Vref 0 -> 0, step: 1
6805 04:44:13.206048
6806 04:44:13.209197 RX Delay -311 -> 252, step: 8
6807 04:44:13.209343
6808 04:44:13.212625 Set Vref, RX VrefLevel [Byte0]: 52
6809 04:44:13.215492 [Byte1]: 49
6810 04:44:13.219511
6811 04:44:13.219676 Final RX Vref Byte 0 = 52 to rank0
6812 04:44:13.222731 Final RX Vref Byte 1 = 49 to rank0
6813 04:44:13.226237 Final RX Vref Byte 0 = 52 to rank1
6814 04:44:13.229664 Final RX Vref Byte 1 = 49 to rank1==
6815 04:44:13.233061 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 04:44:13.239674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 04:44:13.239794 ==
6818 04:44:13.239894 DQS Delay:
6819 04:44:13.243071 DQS0 = 32, DQS1 = 32
6820 04:44:13.243177 DQM Delay:
6821 04:44:13.243273 DQM0 = 14, DQM1 = 11
6822 04:44:13.246353 DQ Delay:
6823 04:44:13.249803 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6824 04:44:13.252611 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6825 04:44:13.252732 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6826 04:44:13.255808 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6827 04:44:13.259689
6828 04:44:13.259802
6829 04:44:13.265835 [DQSOSCAuto] RK0, (LSB)MR18= 0x90c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6830 04:44:13.269463 CH1 RK0: MR19=C0C, MR18=90C9
6831 04:44:13.276009 CH1_RK0: MR19=0xC0C, MR18=0x90C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6832 04:44:13.276198 ==
6833 04:44:13.279107 Dram Type= 6, Freq= 0, CH_1, rank 1
6834 04:44:13.282398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 04:44:13.282588 ==
6836 04:44:13.285817 [Gating] SW mode calibration
6837 04:44:13.292670 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6838 04:44:13.299569 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6839 04:44:13.302383 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6840 04:44:13.305945 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6841 04:44:13.312251 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6842 04:44:13.315886 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 04:44:13.319316 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 04:44:13.325595 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 04:44:13.329456 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 04:44:13.332170 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 04:44:13.339158 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6848 04:44:13.339274 Total UI for P1: 0, mck2ui 16
6849 04:44:13.342675 best dqsien dly found for B0: ( 0, 14, 24)
6850 04:44:13.345389 Total UI for P1: 0, mck2ui 16
6851 04:44:13.348713 best dqsien dly found for B1: ( 0, 14, 24)
6852 04:44:13.355638 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6853 04:44:13.358946 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6854 04:44:13.359060
6855 04:44:13.362632 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6856 04:44:13.365997 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6857 04:44:13.368773 [Gating] SW calibration Done
6858 04:44:13.368876 ==
6859 04:44:13.372099 Dram Type= 6, Freq= 0, CH_1, rank 1
6860 04:44:13.375655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 04:44:13.375803 ==
6862 04:44:13.379054 RX Vref Scan: 0
6863 04:44:13.379193
6864 04:44:13.379316 RX Vref 0 -> 0, step: 1
6865 04:44:13.379446
6866 04:44:13.382358 RX Delay -410 -> 252, step: 16
6867 04:44:13.385485 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6868 04:44:13.392184 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6869 04:44:13.395798 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6870 04:44:13.398585 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6871 04:44:13.402341 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6872 04:44:13.409161 iDelay=230, Bit 5, Center 5 (-218 ~ 229) 448
6873 04:44:13.412301 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6874 04:44:13.415842 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6875 04:44:13.418694 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6876 04:44:13.425666 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6877 04:44:13.428938 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6878 04:44:13.432322 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6879 04:44:13.435688 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6880 04:44:13.442381 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6881 04:44:13.445879 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6882 04:44:13.449295 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6883 04:44:13.449410 ==
6884 04:44:13.451938 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 04:44:13.455322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 04:44:13.458784 ==
6887 04:44:13.458914 DQS Delay:
6888 04:44:13.459015 DQS0 = 35, DQS1 = 35
6889 04:44:13.462269 DQM Delay:
6890 04:44:13.462379 DQM0 = 18, DQM1 = 13
6891 04:44:13.465670 DQ Delay:
6892 04:44:13.469169 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6893 04:44:13.469286 DQ4 =16, DQ5 =40, DQ6 =24, DQ7 =16
6894 04:44:13.472149 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6895 04:44:13.475346 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6896 04:44:13.475434
6897 04:44:13.478660
6898 04:44:13.478749 ==
6899 04:44:13.482130 Dram Type= 6, Freq= 0, CH_1, rank 1
6900 04:44:13.485633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6901 04:44:13.485738 ==
6902 04:44:13.485808
6903 04:44:13.485871
6904 04:44:13.488611 TX Vref Scan disable
6905 04:44:13.488715 == TX Byte 0 ==
6906 04:44:13.492032 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6907 04:44:13.498644 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6908 04:44:13.498774 == TX Byte 1 ==
6909 04:44:13.501987 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6910 04:44:13.508617 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6911 04:44:13.508745 ==
6912 04:44:13.511714 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 04:44:13.515389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 04:44:13.515505 ==
6915 04:44:13.515610
6916 04:44:13.515698
6917 04:44:13.518395 TX Vref Scan disable
6918 04:44:13.518482 == TX Byte 0 ==
6919 04:44:13.522110 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6920 04:44:13.528323 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6921 04:44:13.528414 == TX Byte 1 ==
6922 04:44:13.532141 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6923 04:44:13.538541 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6924 04:44:13.538630
6925 04:44:13.538697 [DATLAT]
6926 04:44:13.538766 Freq=400, CH1 RK1
6927 04:44:13.538833
6928 04:44:13.541839 DATLAT Default: 0xe
6929 04:44:13.545025 0, 0xFFFF, sum = 0
6930 04:44:13.545108 1, 0xFFFF, sum = 0
6931 04:44:13.548282 2, 0xFFFF, sum = 0
6932 04:44:13.548383 3, 0xFFFF, sum = 0
6933 04:44:13.551708 4, 0xFFFF, sum = 0
6934 04:44:13.551790 5, 0xFFFF, sum = 0
6935 04:44:13.555194 6, 0xFFFF, sum = 0
6936 04:44:13.555281 7, 0xFFFF, sum = 0
6937 04:44:13.558689 8, 0xFFFF, sum = 0
6938 04:44:13.558782 9, 0xFFFF, sum = 0
6939 04:44:13.562134 10, 0xFFFF, sum = 0
6940 04:44:13.562226 11, 0xFFFF, sum = 0
6941 04:44:13.565666 12, 0xFFFF, sum = 0
6942 04:44:13.565763 13, 0x0, sum = 1
6943 04:44:13.568853 14, 0x0, sum = 2
6944 04:44:13.568945 15, 0x0, sum = 3
6945 04:44:13.571622 16, 0x0, sum = 4
6946 04:44:13.571709 best_step = 14
6947 04:44:13.571775
6948 04:44:13.571838 ==
6949 04:44:13.575193 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 04:44:13.578731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 04:44:13.582193 ==
6952 04:44:13.582277 RX Vref Scan: 0
6953 04:44:13.582343
6954 04:44:13.585364 RX Vref 0 -> 0, step: 1
6955 04:44:13.585482
6956 04:44:13.588138 RX Delay -311 -> 252, step: 8
6957 04:44:13.591646 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6958 04:44:13.598511 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6959 04:44:13.601870 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6960 04:44:13.605342 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6961 04:44:13.608144 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6962 04:44:13.615005 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6963 04:44:13.618210 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6964 04:44:13.621651 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6965 04:44:13.625205 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6966 04:44:13.631436 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6967 04:44:13.634623 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6968 04:44:13.637883 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6969 04:44:13.641633 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6970 04:44:13.647773 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6971 04:44:13.651211 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6972 04:44:13.654772 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6973 04:44:13.654881 ==
6974 04:44:13.658079 Dram Type= 6, Freq= 0, CH_1, rank 1
6975 04:44:13.664866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6976 04:44:13.664963 ==
6977 04:44:13.665035 DQS Delay:
6978 04:44:13.667916 DQS0 = 28, DQS1 = 36
6979 04:44:13.668032 DQM Delay:
6980 04:44:13.668128 DQM0 = 11, DQM1 = 15
6981 04:44:13.671117 DQ Delay:
6982 04:44:13.674378 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6983 04:44:13.677759 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6984 04:44:13.677868 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6985 04:44:13.681297 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6986 04:44:13.684141
6987 04:44:13.684245
6988 04:44:13.690996 [DQSOSCAuto] RK1, (LSB)MR18= 0xc557, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6989 04:44:13.694488 CH1 RK1: MR19=C0C, MR18=C557
6990 04:44:13.701373 CH1_RK1: MR19=0xC0C, MR18=0xC557, DQSOSC=385, MR23=63, INC=398, DEC=265
6991 04:44:13.704152 [RxdqsGatingPostProcess] freq 400
6992 04:44:13.707569 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6993 04:44:13.711049 best DQS0 dly(2T, 0.5T) = (0, 10)
6994 04:44:13.714576 best DQS1 dly(2T, 0.5T) = (0, 10)
6995 04:44:13.717980 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6996 04:44:13.720723 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6997 04:44:13.724145 best DQS0 dly(2T, 0.5T) = (0, 10)
6998 04:44:13.727523 best DQS1 dly(2T, 0.5T) = (0, 10)
6999 04:44:13.730880 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7000 04:44:13.734406 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7001 04:44:13.737174 Pre-setting of DQS Precalculation
7002 04:44:13.740622 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7003 04:44:13.750973 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7004 04:44:13.757300 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7005 04:44:13.757400
7006 04:44:13.757467
7007 04:44:13.760514 [Calibration Summary] 800 Mbps
7008 04:44:13.760600 CH 0, Rank 0
7009 04:44:13.764252 SW Impedance : PASS
7010 04:44:13.764357 DUTY Scan : NO K
7011 04:44:13.767555 ZQ Calibration : PASS
7012 04:44:13.770634 Jitter Meter : NO K
7013 04:44:13.770737 CBT Training : PASS
7014 04:44:13.774305 Write leveling : PASS
7015 04:44:13.774406 RX DQS gating : PASS
7016 04:44:13.777206 RX DQ/DQS(RDDQC) : PASS
7017 04:44:13.780535 TX DQ/DQS : PASS
7018 04:44:13.780611 RX DATLAT : PASS
7019 04:44:13.783788 RX DQ/DQS(Engine): PASS
7020 04:44:13.787535 TX OE : NO K
7021 04:44:13.787619 All Pass.
7022 04:44:13.787684
7023 04:44:13.787746 CH 0, Rank 1
7024 04:44:13.790508 SW Impedance : PASS
7025 04:44:13.794322 DUTY Scan : NO K
7026 04:44:13.794413 ZQ Calibration : PASS
7027 04:44:13.797429 Jitter Meter : NO K
7028 04:44:13.800577 CBT Training : PASS
7029 04:44:13.800663 Write leveling : NO K
7030 04:44:13.803930 RX DQS gating : PASS
7031 04:44:13.807197 RX DQ/DQS(RDDQC) : PASS
7032 04:44:13.807314 TX DQ/DQS : PASS
7033 04:44:13.810477 RX DATLAT : PASS
7034 04:44:13.814055 RX DQ/DQS(Engine): PASS
7035 04:44:13.814145 TX OE : NO K
7036 04:44:13.816827 All Pass.
7037 04:44:13.816911
7038 04:44:13.816976 CH 1, Rank 0
7039 04:44:13.820330 SW Impedance : PASS
7040 04:44:13.820415 DUTY Scan : NO K
7041 04:44:13.823702 ZQ Calibration : PASS
7042 04:44:13.827174 Jitter Meter : NO K
7043 04:44:13.827290 CBT Training : PASS
7044 04:44:13.830053 Write leveling : PASS
7045 04:44:13.833403 RX DQS gating : PASS
7046 04:44:13.833519 RX DQ/DQS(RDDQC) : PASS
7047 04:44:13.836804 TX DQ/DQS : PASS
7048 04:44:13.836915 RX DATLAT : PASS
7049 04:44:13.840143 RX DQ/DQS(Engine): PASS
7050 04:44:13.843685 TX OE : NO K
7051 04:44:13.843793 All Pass.
7052 04:44:13.843892
7053 04:44:13.843985 CH 1, Rank 1
7054 04:44:13.847197 SW Impedance : PASS
7055 04:44:13.850692 DUTY Scan : NO K
7056 04:44:13.850808 ZQ Calibration : PASS
7057 04:44:13.853408 Jitter Meter : NO K
7058 04:44:13.856837 CBT Training : PASS
7059 04:44:13.856948 Write leveling : NO K
7060 04:44:13.860297 RX DQS gating : PASS
7061 04:44:13.863894 RX DQ/DQS(RDDQC) : PASS
7062 04:44:13.864014 TX DQ/DQS : PASS
7063 04:44:13.866674 RX DATLAT : PASS
7064 04:44:13.870101 RX DQ/DQS(Engine): PASS
7065 04:44:13.870219 TX OE : NO K
7066 04:44:13.873612 All Pass.
7067 04:44:13.873734
7068 04:44:13.873838 DramC Write-DBI off
7069 04:44:13.877101 PER_BANK_REFRESH: Hybrid Mode
7070 04:44:13.877218 TX_TRACKING: ON
7071 04:44:13.904170 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7072 04:44:13.904339 [FAST_K] Save calibration result to emmc
7073 04:44:13.904449 dramc_set_vcore_voltage set vcore to 725000
7074 04:44:13.904546 Read voltage for 1600, 0
7075 04:44:13.904641 Vio18 = 0
7076 04:44:13.904737 Vcore = 725000
7077 04:44:13.904828 Vdram = 0
7078 04:44:13.904920 Vddq = 0
7079 04:44:13.905014 Vmddr = 0
7080 04:44:13.906536 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7081 04:44:13.913343 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7082 04:44:13.913500 MEM_TYPE=3, freq_sel=13
7083 04:44:13.916765 sv_algorithm_assistance_LP4_3733
7084 04:44:13.922950 ============ PULL DRAM RESETB DOWN ============
7085 04:44:13.926253 ========== PULL DRAM RESETB DOWN end =========
7086 04:44:13.929691 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7087 04:44:13.933281 ===================================
7088 04:44:13.936572 LPDDR4 DRAM CONFIGURATION
7089 04:44:13.939919 ===================================
7090 04:44:13.940087 EX_ROW_EN[0] = 0x0
7091 04:44:13.942573 EX_ROW_EN[1] = 0x0
7092 04:44:13.946625 LP4Y_EN = 0x0
7093 04:44:13.946732 WORK_FSP = 0x1
7094 04:44:13.949448 WL = 0x5
7095 04:44:13.949559 RL = 0x5
7096 04:44:13.952996 BL = 0x2
7097 04:44:13.953099 RPST = 0x0
7098 04:44:13.956077 RD_PRE = 0x0
7099 04:44:13.956183 WR_PRE = 0x1
7100 04:44:13.959605 WR_PST = 0x1
7101 04:44:13.959710 DBI_WR = 0x0
7102 04:44:13.963096 DBI_RD = 0x0
7103 04:44:13.963209 OTF = 0x1
7104 04:44:13.966058 ===================================
7105 04:44:13.969542 ===================================
7106 04:44:13.972275 ANA top config
7107 04:44:13.975672 ===================================
7108 04:44:13.979078 DLL_ASYNC_EN = 0
7109 04:44:13.979186 ALL_SLAVE_EN = 0
7110 04:44:13.982403 NEW_RANK_MODE = 1
7111 04:44:13.985966 DLL_IDLE_MODE = 1
7112 04:44:13.989408 LP45_APHY_COMB_EN = 1
7113 04:44:13.989492 TX_ODT_DIS = 0
7114 04:44:13.992748 NEW_8X_MODE = 1
7115 04:44:13.995517 ===================================
7116 04:44:13.999124 ===================================
7117 04:44:14.002513 data_rate = 3200
7118 04:44:14.005997 CKR = 1
7119 04:44:14.008821 DQ_P2S_RATIO = 8
7120 04:44:14.012403 ===================================
7121 04:44:14.015906 CA_P2S_RATIO = 8
7122 04:44:14.015994 DQ_CA_OPEN = 0
7123 04:44:14.018646 DQ_SEMI_OPEN = 0
7124 04:44:14.021979 CA_SEMI_OPEN = 0
7125 04:44:14.025298 CA_FULL_RATE = 0
7126 04:44:14.028663 DQ_CKDIV4_EN = 0
7127 04:44:14.031844 CA_CKDIV4_EN = 0
7128 04:44:14.031929 CA_PREDIV_EN = 0
7129 04:44:14.035633 PH8_DLY = 12
7130 04:44:14.038542 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7131 04:44:14.042067 DQ_AAMCK_DIV = 4
7132 04:44:14.045221 CA_AAMCK_DIV = 4
7133 04:44:14.049297 CA_ADMCK_DIV = 4
7134 04:44:14.049478 DQ_TRACK_CA_EN = 0
7135 04:44:14.051942 CA_PICK = 1600
7136 04:44:14.055452 CA_MCKIO = 1600
7137 04:44:14.058593 MCKIO_SEMI = 0
7138 04:44:14.061862 PLL_FREQ = 3068
7139 04:44:14.065162 DQ_UI_PI_RATIO = 32
7140 04:44:14.068363 CA_UI_PI_RATIO = 0
7141 04:44:14.071973 ===================================
7142 04:44:14.075357 ===================================
7143 04:44:14.075443 memory_type:LPDDR4
7144 04:44:14.078268 GP_NUM : 10
7145 04:44:14.081729 SRAM_EN : 1
7146 04:44:14.081810 MD32_EN : 0
7147 04:44:14.085243 ===================================
7148 04:44:14.088809 [ANA_INIT] >>>>>>>>>>>>>>
7149 04:44:14.091590 <<<<<< [CONFIGURE PHASE]: ANA_TX
7150 04:44:14.095058 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7151 04:44:14.098429 ===================================
7152 04:44:14.101335 data_rate = 3200,PCW = 0X7600
7153 04:44:14.104875 ===================================
7154 04:44:14.108489 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7155 04:44:14.111870 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7156 04:44:14.118213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7157 04:44:14.121695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7158 04:44:14.127845 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7159 04:44:14.131150 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7160 04:44:14.131237 [ANA_INIT] flow start
7161 04:44:14.134631 [ANA_INIT] PLL >>>>>>>>
7162 04:44:14.138111 [ANA_INIT] PLL <<<<<<<<
7163 04:44:14.138196 [ANA_INIT] MIDPI >>>>>>>>
7164 04:44:14.141514 [ANA_INIT] MIDPI <<<<<<<<
7165 04:44:14.145085 [ANA_INIT] DLL >>>>>>>>
7166 04:44:14.145170 [ANA_INIT] DLL <<<<<<<<
7167 04:44:14.148187 [ANA_INIT] flow end
7168 04:44:14.151686 ============ LP4 DIFF to SE enter ============
7169 04:44:14.154335 ============ LP4 DIFF to SE exit ============
7170 04:44:14.157974 [ANA_INIT] <<<<<<<<<<<<<
7171 04:44:14.161400 [Flow] Enable top DCM control >>>>>
7172 04:44:14.164641 [Flow] Enable top DCM control <<<<<
7173 04:44:14.167816 Enable DLL master slave shuffle
7174 04:44:14.174865 ==============================================================
7175 04:44:14.174958 Gating Mode config
7176 04:44:14.181213 ==============================================================
7177 04:44:14.181299 Config description:
7178 04:44:14.191035 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7179 04:44:14.197682 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7180 04:44:14.204489 SELPH_MODE 0: By rank 1: By Phase
7181 04:44:14.207650 ==============================================================
7182 04:44:14.211410 GAT_TRACK_EN = 1
7183 04:44:14.214148 RX_GATING_MODE = 2
7184 04:44:14.217615 RX_GATING_TRACK_MODE = 2
7185 04:44:14.221023 SELPH_MODE = 1
7186 04:44:14.224666 PICG_EARLY_EN = 1
7187 04:44:14.227521 VALID_LAT_VALUE = 1
7188 04:44:14.234370 ==============================================================
7189 04:44:14.237780 Enter into Gating configuration >>>>
7190 04:44:14.240999 Exit from Gating configuration <<<<
7191 04:44:14.241112 Enter into DVFS_PRE_config >>>>>
7192 04:44:14.254469 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7193 04:44:14.257309 Exit from DVFS_PRE_config <<<<<
7194 04:44:14.260789 Enter into PICG configuration >>>>
7195 04:44:14.264262 Exit from PICG configuration <<<<
7196 04:44:14.264367 [RX_INPUT] configuration >>>>>
7197 04:44:14.267845 [RX_INPUT] configuration <<<<<
7198 04:44:14.274046 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7199 04:44:14.277441 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7200 04:44:14.284450 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7201 04:44:14.290657 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7202 04:44:14.297620 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7203 04:44:14.304206 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7204 04:44:14.307345 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7205 04:44:14.310551 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7206 04:44:14.317288 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7207 04:44:14.320591 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7208 04:44:14.323799 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7209 04:44:14.327034 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7210 04:44:14.330685 ===================================
7211 04:44:14.333719 LPDDR4 DRAM CONFIGURATION
7212 04:44:14.337313 ===================================
7213 04:44:14.340825 EX_ROW_EN[0] = 0x0
7214 04:44:14.340922 EX_ROW_EN[1] = 0x0
7215 04:44:14.343628 LP4Y_EN = 0x0
7216 04:44:14.343739 WORK_FSP = 0x1
7217 04:44:14.347148 WL = 0x5
7218 04:44:14.347256 RL = 0x5
7219 04:44:14.350365 BL = 0x2
7220 04:44:14.350470 RPST = 0x0
7221 04:44:14.353657 RD_PRE = 0x0
7222 04:44:14.353769 WR_PRE = 0x1
7223 04:44:14.356977 WR_PST = 0x1
7224 04:44:14.360261 DBI_WR = 0x0
7225 04:44:14.360398 DBI_RD = 0x0
7226 04:44:14.363767 OTF = 0x1
7227 04:44:14.363872 ===================================
7228 04:44:14.370644 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7229 04:44:14.374124 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7230 04:44:14.377533 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7231 04:44:14.380324 ===================================
7232 04:44:14.383778 LPDDR4 DRAM CONFIGURATION
7233 04:44:14.387240 ===================================
7234 04:44:14.390771 EX_ROW_EN[0] = 0x10
7235 04:44:14.390892 EX_ROW_EN[1] = 0x0
7236 04:44:14.394206 LP4Y_EN = 0x0
7237 04:44:14.394327 WORK_FSP = 0x1
7238 04:44:14.397101 WL = 0x5
7239 04:44:14.397201 RL = 0x5
7240 04:44:14.400658 BL = 0x2
7241 04:44:14.400758 RPST = 0x0
7242 04:44:14.403545 RD_PRE = 0x0
7243 04:44:14.403658 WR_PRE = 0x1
7244 04:44:14.407344 WR_PST = 0x1
7245 04:44:14.407443 DBI_WR = 0x0
7246 04:44:14.410793 DBI_RD = 0x0
7247 04:44:14.410919 OTF = 0x1
7248 04:44:14.413695 ===================================
7249 04:44:14.420687 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7250 04:44:14.420793 ==
7251 04:44:14.423912 Dram Type= 6, Freq= 0, CH_0, rank 0
7252 04:44:14.430560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7253 04:44:14.430668 ==
7254 04:44:14.430765 [Duty_Offset_Calibration]
7255 04:44:14.433580 B0:2 B1:1 CA:1
7256 04:44:14.433658
7257 04:44:14.437117 [DutyScan_Calibration_Flow] k_type=0
7258 04:44:14.446256
7259 04:44:14.446366 ==CLK 0==
7260 04:44:14.449517 Final CLK duty delay cell = 0
7261 04:44:14.452888 [0] MAX Duty = 5156%(X100), DQS PI = 22
7262 04:44:14.455838 [0] MIN Duty = 4907%(X100), DQS PI = 0
7263 04:44:14.455944 [0] AVG Duty = 5031%(X100)
7264 04:44:14.459438
7265 04:44:14.459544 CH0 CLK Duty spec in!! Max-Min= 249%
7266 04:44:14.466113 [DutyScan_Calibration_Flow] ====Done====
7267 04:44:14.466230
7268 04:44:14.469435 [DutyScan_Calibration_Flow] k_type=1
7269 04:44:14.484944
7270 04:44:14.485070 ==DQS 0 ==
7271 04:44:14.488508 Final DQS duty delay cell = -4
7272 04:44:14.491843 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7273 04:44:14.495389 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7274 04:44:14.498133 [-4] AVG Duty = 4891%(X100)
7275 04:44:14.498237
7276 04:44:14.498331 ==DQS 1 ==
7277 04:44:14.501604 Final DQS duty delay cell = 0
7278 04:44:14.505189 [0] MAX Duty = 5218%(X100), DQS PI = 22
7279 04:44:14.508606 [0] MIN Duty = 5062%(X100), DQS PI = 32
7280 04:44:14.512002 [0] AVG Duty = 5140%(X100)
7281 04:44:14.512103
7282 04:44:14.514871 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7283 04:44:14.514970
7284 04:44:14.518242 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7285 04:44:14.521836 [DutyScan_Calibration_Flow] ====Done====
7286 04:44:14.521935
7287 04:44:14.524689 [DutyScan_Calibration_Flow] k_type=3
7288 04:44:14.541965
7289 04:44:14.542078 ==DQM 0 ==
7290 04:44:14.545349 Final DQM duty delay cell = 0
7291 04:44:14.548583 [0] MAX Duty = 5218%(X100), DQS PI = 34
7292 04:44:14.551692 [0] MIN Duty = 4907%(X100), DQS PI = 56
7293 04:44:14.555197 [0] AVG Duty = 5062%(X100)
7294 04:44:14.555307
7295 04:44:14.555402 ==DQM 1 ==
7296 04:44:14.558566 Final DQM duty delay cell = -4
7297 04:44:14.561485 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7298 04:44:14.564817 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7299 04:44:14.568759 [-4] AVG Duty = 4906%(X100)
7300 04:44:14.568834
7301 04:44:14.572016 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7302 04:44:14.572128
7303 04:44:14.575093 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7304 04:44:14.578364 [DutyScan_Calibration_Flow] ====Done====
7305 04:44:14.578473
7306 04:44:14.581501 [DutyScan_Calibration_Flow] k_type=2
7307 04:44:14.599257
7308 04:44:14.599372 ==DQ 0 ==
7309 04:44:14.602667 Final DQ duty delay cell = 0
7310 04:44:14.606205 [0] MAX Duty = 5062%(X100), DQS PI = 24
7311 04:44:14.609302 [0] MIN Duty = 4907%(X100), DQS PI = 0
7312 04:44:14.609414 [0] AVG Duty = 4984%(X100)
7313 04:44:14.609488
7314 04:44:14.612685 ==DQ 1 ==
7315 04:44:14.615966 Final DQ duty delay cell = 0
7316 04:44:14.619505 [0] MAX Duty = 5125%(X100), DQS PI = 6
7317 04:44:14.623022 [0] MIN Duty = 4938%(X100), DQS PI = 34
7318 04:44:14.623125 [0] AVG Duty = 5031%(X100)
7319 04:44:14.623216
7320 04:44:14.625881 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7321 04:44:14.629299
7322 04:44:14.632797 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7323 04:44:14.635653 [DutyScan_Calibration_Flow] ====Done====
7324 04:44:14.635748 ==
7325 04:44:14.639078 Dram Type= 6, Freq= 0, CH_1, rank 0
7326 04:44:14.642594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7327 04:44:14.642692 ==
7328 04:44:14.646175 [Duty_Offset_Calibration]
7329 04:44:14.646277 B0:1 B1:0 CA:1
7330 04:44:14.646384
7331 04:44:14.648923 [DutyScan_Calibration_Flow] k_type=0
7332 04:44:14.658610
7333 04:44:14.658727 ==CLK 0==
7334 04:44:14.661876 Final CLK duty delay cell = -4
7335 04:44:14.665589 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7336 04:44:14.668901 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7337 04:44:14.672014 [-4] AVG Duty = 4922%(X100)
7338 04:44:14.672096
7339 04:44:14.675392 CH1 CLK Duty spec in!! Max-Min= 156%
7340 04:44:14.678705 [DutyScan_Calibration_Flow] ====Done====
7341 04:44:14.678808
7342 04:44:14.682218 [DutyScan_Calibration_Flow] k_type=1
7343 04:44:14.698652
7344 04:44:14.698762 ==DQS 0 ==
7345 04:44:14.702045 Final DQS duty delay cell = 0
7346 04:44:14.705641 [0] MAX Duty = 5094%(X100), DQS PI = 20
7347 04:44:14.708738 [0] MIN Duty = 4844%(X100), DQS PI = 48
7348 04:44:14.711976 [0] AVG Duty = 4969%(X100)
7349 04:44:14.712077
7350 04:44:14.712211 ==DQS 1 ==
7351 04:44:14.715776 Final DQS duty delay cell = 0
7352 04:44:14.718715 [0] MAX Duty = 5249%(X100), DQS PI = 18
7353 04:44:14.721734 [0] MIN Duty = 4938%(X100), DQS PI = 8
7354 04:44:14.725324 [0] AVG Duty = 5093%(X100)
7355 04:44:14.725429
7356 04:44:14.728776 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7357 04:44:14.728888
7358 04:44:14.732166 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7359 04:44:14.735337 [DutyScan_Calibration_Flow] ====Done====
7360 04:44:14.735439
7361 04:44:14.738757 [DutyScan_Calibration_Flow] k_type=3
7362 04:44:14.755400
7363 04:44:14.755517 ==DQM 0 ==
7364 04:44:14.759008 Final DQM duty delay cell = 0
7365 04:44:14.762371 [0] MAX Duty = 5187%(X100), DQS PI = 8
7366 04:44:14.765973 [0] MIN Duty = 4969%(X100), DQS PI = 48
7367 04:44:14.766079 [0] AVG Duty = 5078%(X100)
7368 04:44:14.768685
7369 04:44:14.768788 ==DQM 1 ==
7370 04:44:14.772015 Final DQM duty delay cell = 0
7371 04:44:14.775980 [0] MAX Duty = 5093%(X100), DQS PI = 16
7372 04:44:14.779239 [0] MIN Duty = 4876%(X100), DQS PI = 52
7373 04:44:14.779347 [0] AVG Duty = 4984%(X100)
7374 04:44:14.782162
7375 04:44:14.785908 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7376 04:44:14.786016
7377 04:44:14.789314 CH1 DQM 1 Duty spec in!! Max-Min= 217%
7378 04:44:14.792721 [DutyScan_Calibration_Flow] ====Done====
7379 04:44:14.792828
7380 04:44:14.795991 [DutyScan_Calibration_Flow] k_type=2
7381 04:44:14.811500
7382 04:44:14.811616 ==DQ 0 ==
7383 04:44:14.814746 Final DQ duty delay cell = -4
7384 04:44:14.818215 [-4] MAX Duty = 5031%(X100), DQS PI = 8
7385 04:44:14.821622 [-4] MIN Duty = 4875%(X100), DQS PI = 48
7386 04:44:14.825100 [-4] AVG Duty = 4953%(X100)
7387 04:44:14.825211
7388 04:44:14.825309 ==DQ 1 ==
7389 04:44:14.828225 Final DQ duty delay cell = 0
7390 04:44:14.831642 [0] MAX Duty = 5124%(X100), DQS PI = 18
7391 04:44:14.834889 [0] MIN Duty = 4938%(X100), DQS PI = 10
7392 04:44:14.838090 [0] AVG Duty = 5031%(X100)
7393 04:44:14.838193
7394 04:44:14.841849 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7395 04:44:14.841952
7396 04:44:14.844749 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7397 04:44:14.848424 [DutyScan_Calibration_Flow] ====Done====
7398 04:44:14.851409 nWR fixed to 30
7399 04:44:14.851515 [ModeRegInit_LP4] CH0 RK0
7400 04:44:14.855201 [ModeRegInit_LP4] CH0 RK1
7401 04:44:14.858000 [ModeRegInit_LP4] CH1 RK0
7402 04:44:14.861380 [ModeRegInit_LP4] CH1 RK1
7403 04:44:14.861471 match AC timing 5
7404 04:44:14.868457 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7405 04:44:14.871243 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7406 04:44:14.874767 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7407 04:44:14.881794 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7408 04:44:14.885068 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7409 04:44:14.885181 [MiockJmeterHQA]
7410 04:44:14.885276
7411 04:44:14.887815 [DramcMiockJmeter] u1RxGatingPI = 0
7412 04:44:14.891245 0 : 4257, 4029
7413 04:44:14.891362 4 : 4363, 4137
7414 04:44:14.894386 8 : 4258, 4029
7415 04:44:14.894494 12 : 4253, 4027
7416 04:44:14.894590 16 : 4252, 4026
7417 04:44:14.897945 20 : 4363, 4138
7418 04:44:14.898057 24 : 4252, 4027
7419 04:44:14.901013 28 : 4363, 4138
7420 04:44:14.901109 32 : 4252, 4027
7421 04:44:14.904389 36 : 4365, 4140
7422 04:44:14.904474 40 : 4252, 4027
7423 04:44:14.907720 44 : 4254, 4029
7424 04:44:14.907816 48 : 4363, 4138
7425 04:44:14.907887 52 : 4252, 4027
7426 04:44:14.911453 56 : 4363, 4138
7427 04:44:14.911535 60 : 4363, 4139
7428 04:44:14.914947 64 : 4250, 4027
7429 04:44:14.915052 68 : 4250, 4027
7430 04:44:14.917718 72 : 4360, 4138
7431 04:44:14.917848 76 : 4250, 4027
7432 04:44:14.921068 80 : 4252, 4029
7433 04:44:14.921171 84 : 4250, 4027
7434 04:44:14.921296 88 : 4250, 187
7435 04:44:14.924647 92 : 4361, 0
7436 04:44:14.924751 96 : 4252, 0
7437 04:44:14.924845 100 : 4360, 0
7438 04:44:14.928109 104 : 4250, 0
7439 04:44:14.928224 108 : 4252, 0
7440 04:44:14.931579 112 : 4252, 0
7441 04:44:14.931684 116 : 4363, 0
7442 04:44:14.931777 120 : 4257, 0
7443 04:44:14.934943 124 : 4253, 0
7444 04:44:14.935049 128 : 4363, 0
7445 04:44:14.937737 132 : 4250, 0
7446 04:44:14.937838 136 : 4253, 0
7447 04:44:14.937935 140 : 4250, 0
7448 04:44:14.941127 144 : 4253, 0
7449 04:44:14.941230 148 : 4363, 0
7450 04:44:14.944760 152 : 4252, 0
7451 04:44:14.944864 156 : 4250, 0
7452 04:44:14.944958 160 : 4257, 0
7453 04:44:14.948129 164 : 4360, 0
7454 04:44:14.948228 168 : 4250, 0
7455 04:44:14.948358 172 : 4250, 0
7456 04:44:14.951386 176 : 4253, 0
7457 04:44:14.951489 180 : 4361, 0
7458 04:44:14.954759 184 : 4250, 0
7459 04:44:14.954864 188 : 4253, 0
7460 04:44:14.954995 192 : 4250, 0
7461 04:44:14.957940 196 : 4255, 0
7462 04:44:14.958044 200 : 4361, 0
7463 04:44:14.961212 204 : 4252, 1456
7464 04:44:14.961340 208 : 4253, 3995
7465 04:44:14.964197 212 : 4255, 4032
7466 04:44:14.964327 216 : 4360, 4137
7467 04:44:14.967715 220 : 4250, 4027
7468 04:44:14.967820 224 : 4250, 4026
7469 04:44:14.967919 228 : 4250, 4027
7470 04:44:14.970847 232 : 4253, 4029
7471 04:44:14.970951 236 : 4250, 4026
7472 04:44:14.974344 240 : 4361, 4137
7473 04:44:14.974450 244 : 4249, 4027
7474 04:44:14.977981 248 : 4250, 4026
7475 04:44:14.978091 252 : 4250, 4027
7476 04:44:14.981276 256 : 4363, 4140
7477 04:44:14.981380 260 : 4363, 4140
7478 04:44:14.984090 264 : 4250, 4027
7479 04:44:14.984209 268 : 4252, 4029
7480 04:44:14.987491 272 : 4253, 4029
7481 04:44:14.987594 276 : 4250, 4027
7482 04:44:14.990982 280 : 4250, 4026
7483 04:44:14.991084 284 : 4249, 4027
7484 04:44:14.991178 288 : 4253, 4029
7485 04:44:14.994475 292 : 4363, 4139
7486 04:44:14.994589 296 : 4360, 4138
7487 04:44:14.997848 300 : 4249, 4027
7488 04:44:14.997948 304 : 4250, 4027
7489 04:44:15.001309 308 : 4363, 4082
7490 04:44:15.001387 312 : 4363, 2065
7491 04:44:15.001477
7492 04:44:15.003970 MIOCK jitter meter ch=0
7493 04:44:15.004065
7494 04:44:15.007959 1T = (312-88) = 224 dly cells
7495 04:44:15.014081 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7496 04:44:15.014184 ==
7497 04:44:15.017370 Dram Type= 6, Freq= 0, CH_0, rank 0
7498 04:44:15.020658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7499 04:44:15.020778 ==
7500 04:44:15.027095 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7501 04:44:15.030621 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7502 04:44:15.034016 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7503 04:44:15.040809 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7504 04:44:15.049193 [CA 0] Center 43 (13~74) winsize 62
7505 04:44:15.052782 [CA 1] Center 43 (13~74) winsize 62
7506 04:44:15.056145 [CA 2] Center 38 (9~68) winsize 60
7507 04:44:15.059570 [CA 3] Center 38 (8~68) winsize 61
7508 04:44:15.063076 [CA 4] Center 36 (7~66) winsize 60
7509 04:44:15.065862 [CA 5] Center 36 (7~65) winsize 59
7510 04:44:15.065947
7511 04:44:15.069295 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7512 04:44:15.069377
7513 04:44:15.072464 [CATrainingPosCal] consider 1 rank data
7514 04:44:15.076323 u2DelayCellTimex100 = 290/100 ps
7515 04:44:15.079370 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7516 04:44:15.086181 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7517 04:44:15.089272 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7518 04:44:15.092890 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7519 04:44:15.095770 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7520 04:44:15.099243 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7521 04:44:15.099352
7522 04:44:15.102743 CA PerBit enable=1, Macro0, CA PI delay=36
7523 04:44:15.102850
7524 04:44:15.105563 [CBTSetCACLKResult] CA Dly = 36
7525 04:44:15.108921 CS Dly: 9 (0~40)
7526 04:44:15.112538 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7527 04:44:15.115907 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7528 04:44:15.116013 ==
7529 04:44:15.119488 Dram Type= 6, Freq= 0, CH_0, rank 1
7530 04:44:15.122078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 04:44:15.122216 ==
7532 04:44:15.129085 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7533 04:44:15.132664 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7534 04:44:15.138985 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7535 04:44:15.142345 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7536 04:44:15.152590 [CA 0] Center 43 (13~73) winsize 61
7537 04:44:15.155730 [CA 1] Center 42 (12~73) winsize 62
7538 04:44:15.159193 [CA 2] Center 38 (8~68) winsize 61
7539 04:44:15.162581 [CA 3] Center 38 (8~68) winsize 61
7540 04:44:15.165476 [CA 4] Center 36 (6~66) winsize 61
7541 04:44:15.168819 [CA 5] Center 35 (6~65) winsize 60
7542 04:44:15.168892
7543 04:44:15.172301 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7544 04:44:15.172440
7545 04:44:15.178702 [CATrainingPosCal] consider 2 rank data
7546 04:44:15.178807 u2DelayCellTimex100 = 290/100 ps
7547 04:44:15.185356 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7548 04:44:15.188613 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7549 04:44:15.191851 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7550 04:44:15.195093 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7551 04:44:15.198375 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7552 04:44:15.202104 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7553 04:44:15.202204
7554 04:44:15.205247 CA PerBit enable=1, Macro0, CA PI delay=36
7555 04:44:15.205328
7556 04:44:15.208674 [CBTSetCACLKResult] CA Dly = 36
7557 04:44:15.212159 CS Dly: 10 (0~42)
7558 04:44:15.215698 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7559 04:44:15.218461 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7560 04:44:15.218564
7561 04:44:15.221991 ----->DramcWriteLeveling(PI) begin...
7562 04:44:15.222062 ==
7563 04:44:15.225614 Dram Type= 6, Freq= 0, CH_0, rank 0
7564 04:44:15.232321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 04:44:15.232438 ==
7566 04:44:15.235302 Write leveling (Byte 0): 37 => 37
7567 04:44:15.235401 Write leveling (Byte 1): 29 => 29
7568 04:44:15.238387 DramcWriteLeveling(PI) end<-----
7569 04:44:15.238493
7570 04:44:15.241734 ==
7571 04:44:15.241834 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 04:44:15.248800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 04:44:15.248904 ==
7574 04:44:15.251626 [Gating] SW mode calibration
7575 04:44:15.258297 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7576 04:44:15.261756 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7577 04:44:15.281595 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7578 04:44:15.281792 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7579 04:44:15.281893 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7580 04:44:15.282189 1 4 12 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
7581 04:44:15.284801 1 4 16 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
7582 04:44:15.288187 1 4 20 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7583 04:44:15.294870 1 4 24 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (1 1)
7584 04:44:15.298339 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
7585 04:44:15.301814 1 5 0 | B1->B0 | 3434 3938 | 1 1 | (1 1) (1 1)
7586 04:44:15.308542 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 04:44:15.311594 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
7588 04:44:15.314808 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
7589 04:44:15.321718 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7590 04:44:15.324571 1 5 20 | B1->B0 | 2b2b 2625 | 0 1 | (1 0) (0 0)
7591 04:44:15.328051 1 5 24 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7592 04:44:15.334870 1 5 28 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
7593 04:44:15.337736 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 04:44:15.341730 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 04:44:15.347989 1 6 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
7596 04:44:15.351394 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7597 04:44:15.354831 1 6 16 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
7598 04:44:15.357612 1 6 20 | B1->B0 | 4343 4645 | 0 1 | (0 0) (0 0)
7599 04:44:15.364658 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 04:44:15.367545 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 04:44:15.371101 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 04:44:15.377807 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 04:44:15.381229 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 04:44:15.384642 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7605 04:44:15.391189 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7606 04:44:15.394587 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7607 04:44:15.397995 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 04:44:15.404642 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 04:44:15.407801 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 04:44:15.411120 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 04:44:15.417657 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 04:44:15.420748 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 04:44:15.424680 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 04:44:15.430984 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 04:44:15.434466 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 04:44:15.437985 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 04:44:15.444188 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 04:44:15.447673 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 04:44:15.451192 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 04:44:15.457773 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7621 04:44:15.460915 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7622 04:44:15.463889 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 04:44:15.467842 Total UI for P1: 0, mck2ui 16
7624 04:44:15.470543 best dqsien dly found for B0: ( 1, 9, 14)
7625 04:44:15.474121 Total UI for P1: 0, mck2ui 16
7626 04:44:15.477527 best dqsien dly found for B1: ( 1, 9, 18)
7627 04:44:15.480963 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7628 04:44:15.484452 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7629 04:44:15.484572
7630 04:44:15.487153 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7631 04:44:15.494210 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7632 04:44:15.494308 [Gating] SW calibration Done
7633 04:44:15.497488 ==
7634 04:44:15.497571 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 04:44:15.504063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 04:44:15.504162 ==
7637 04:44:15.504230 RX Vref Scan: 0
7638 04:44:15.504302
7639 04:44:15.507352 RX Vref 0 -> 0, step: 1
7640 04:44:15.507435
7641 04:44:15.510511 RX Delay 0 -> 252, step: 8
7642 04:44:15.514644 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7643 04:44:15.517835 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7644 04:44:15.520859 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7645 04:44:15.527667 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7646 04:44:15.530921 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7647 04:44:15.534023 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7648 04:44:15.537556 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7649 04:44:15.541008 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7650 04:44:15.543858 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7651 04:44:15.550877 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7652 04:44:15.554292 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7653 04:44:15.557796 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7654 04:44:15.561312 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7655 04:44:15.564099 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7656 04:44:15.570590 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7657 04:44:15.574205 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7658 04:44:15.574280 ==
7659 04:44:15.577837 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 04:44:15.581193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 04:44:15.581300 ==
7662 04:44:15.584155 DQS Delay:
7663 04:44:15.584252 DQS0 = 0, DQS1 = 0
7664 04:44:15.584363 DQM Delay:
7665 04:44:15.587419 DQM0 = 137, DQM1 = 129
7666 04:44:15.587490 DQ Delay:
7667 04:44:15.590909 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7668 04:44:15.593924 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7669 04:44:15.597348 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7670 04:44:15.604420 DQ12 =131, DQ13 =139, DQ14 =139, DQ15 =135
7671 04:44:15.604519
7672 04:44:15.604617
7673 04:44:15.604704 ==
7674 04:44:15.607680 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 04:44:15.610463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 04:44:15.610565 ==
7677 04:44:15.610658
7678 04:44:15.610750
7679 04:44:15.614268 TX Vref Scan disable
7680 04:44:15.614371 == TX Byte 0 ==
7681 04:44:15.620551 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7682 04:44:15.623801 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7683 04:44:15.627114 == TX Byte 1 ==
7684 04:44:15.630362 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7685 04:44:15.633881 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7686 04:44:15.634004 ==
7687 04:44:15.636963 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 04:44:15.640507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 04:44:15.640607 ==
7690 04:44:15.655406
7691 04:44:15.658697 TX Vref early break, caculate TX vref
7692 04:44:15.662251 TX Vref=16, minBit 0, minWin=23, winSum=378
7693 04:44:15.665004 TX Vref=18, minBit 0, minWin=23, winSum=388
7694 04:44:15.668545 TX Vref=20, minBit 0, minWin=24, winSum=396
7695 04:44:15.672015 TX Vref=22, minBit 7, minWin=24, winSum=407
7696 04:44:15.675354 TX Vref=24, minBit 2, minWin=24, winSum=414
7697 04:44:15.682092 TX Vref=26, minBit 6, minWin=25, winSum=422
7698 04:44:15.685233 TX Vref=28, minBit 0, minWin=25, winSum=423
7699 04:44:15.688278 TX Vref=30, minBit 1, minWin=24, winSum=411
7700 04:44:15.691511 TX Vref=32, minBit 6, minWin=23, winSum=402
7701 04:44:15.695532 TX Vref=34, minBit 1, minWin=23, winSum=392
7702 04:44:15.701577 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
7703 04:44:15.701700
7704 04:44:15.705021 Final TX Range 0 Vref 28
7705 04:44:15.705125
7706 04:44:15.705222 ==
7707 04:44:15.708605 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 04:44:15.711972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 04:44:15.712108 ==
7710 04:44:15.712200
7711 04:44:15.712310
7712 04:44:15.715232 TX Vref Scan disable
7713 04:44:15.721532 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7714 04:44:15.721643 == TX Byte 0 ==
7715 04:44:15.724787 u2DelayCellOfst[0]=10 cells (3 PI)
7716 04:44:15.728222 u2DelayCellOfst[1]=13 cells (4 PI)
7717 04:44:15.731817 u2DelayCellOfst[2]=10 cells (3 PI)
7718 04:44:15.735200 u2DelayCellOfst[3]=10 cells (3 PI)
7719 04:44:15.738694 u2DelayCellOfst[4]=6 cells (2 PI)
7720 04:44:15.741402 u2DelayCellOfst[5]=0 cells (0 PI)
7721 04:44:15.744865 u2DelayCellOfst[6]=16 cells (5 PI)
7722 04:44:15.744971 u2DelayCellOfst[7]=13 cells (4 PI)
7723 04:44:15.751672 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7724 04:44:15.755163 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7725 04:44:15.755271 == TX Byte 1 ==
7726 04:44:15.758691 u2DelayCellOfst[8]=0 cells (0 PI)
7727 04:44:15.761760 u2DelayCellOfst[9]=0 cells (0 PI)
7728 04:44:15.764815 u2DelayCellOfst[10]=10 cells (3 PI)
7729 04:44:15.768094 u2DelayCellOfst[11]=6 cells (2 PI)
7730 04:44:15.771575 u2DelayCellOfst[12]=10 cells (3 PI)
7731 04:44:15.775149 u2DelayCellOfst[13]=10 cells (3 PI)
7732 04:44:15.778617 u2DelayCellOfst[14]=13 cells (4 PI)
7733 04:44:15.781363 u2DelayCellOfst[15]=10 cells (3 PI)
7734 04:44:15.784987 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7735 04:44:15.791887 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7736 04:44:15.792001 DramC Write-DBI on
7737 04:44:15.792099 ==
7738 04:44:15.794584 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 04:44:15.798080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 04:44:15.801444 ==
7741 04:44:15.801546
7742 04:44:15.801641
7743 04:44:15.801732 TX Vref Scan disable
7744 04:44:15.804706 == TX Byte 0 ==
7745 04:44:15.808466 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7746 04:44:15.811626 == TX Byte 1 ==
7747 04:44:15.814757 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7748 04:44:15.818219 DramC Write-DBI off
7749 04:44:15.818296
7750 04:44:15.818430 [DATLAT]
7751 04:44:15.818522 Freq=1600, CH0 RK0
7752 04:44:15.818664
7753 04:44:15.821688 DATLAT Default: 0xf
7754 04:44:15.824566 0, 0xFFFF, sum = 0
7755 04:44:15.824671 1, 0xFFFF, sum = 0
7756 04:44:15.827943 2, 0xFFFF, sum = 0
7757 04:44:15.828046 3, 0xFFFF, sum = 0
7758 04:44:15.831380 4, 0xFFFF, sum = 0
7759 04:44:15.831493 5, 0xFFFF, sum = 0
7760 04:44:15.834745 6, 0xFFFF, sum = 0
7761 04:44:15.834849 7, 0xFFFF, sum = 0
7762 04:44:15.838369 8, 0xFFFF, sum = 0
7763 04:44:15.838446 9, 0xFFFF, sum = 0
7764 04:44:15.841696 10, 0xFFFF, sum = 0
7765 04:44:15.841798 11, 0xFFFF, sum = 0
7766 04:44:15.844430 12, 0xFFFF, sum = 0
7767 04:44:15.844516 13, 0xFFFF, sum = 0
7768 04:44:15.848046 14, 0x0, sum = 1
7769 04:44:15.848149 15, 0x0, sum = 2
7770 04:44:15.851502 16, 0x0, sum = 3
7771 04:44:15.851609 17, 0x0, sum = 4
7772 04:44:15.854970 best_step = 15
7773 04:44:15.855093
7774 04:44:15.855202 ==
7775 04:44:15.857755 Dram Type= 6, Freq= 0, CH_0, rank 0
7776 04:44:15.861092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7777 04:44:15.861191 ==
7778 04:44:15.864178 RX Vref Scan: 1
7779 04:44:15.864346
7780 04:44:15.864499 Set Vref Range= 24 -> 127
7781 04:44:15.864590
7782 04:44:15.867916 RX Vref 24 -> 127, step: 1
7783 04:44:15.868017
7784 04:44:15.871021 RX Delay 19 -> 252, step: 4
7785 04:44:15.871119
7786 04:44:15.874384 Set Vref, RX VrefLevel [Byte0]: 24
7787 04:44:15.878061 [Byte1]: 24
7788 04:44:15.878165
7789 04:44:15.881012 Set Vref, RX VrefLevel [Byte0]: 25
7790 04:44:15.884422 [Byte1]: 25
7791 04:44:15.888002
7792 04:44:15.888103 Set Vref, RX VrefLevel [Byte0]: 26
7793 04:44:15.890738 [Byte1]: 26
7794 04:44:15.894957
7795 04:44:15.895056 Set Vref, RX VrefLevel [Byte0]: 27
7796 04:44:15.898459 [Byte1]: 27
7797 04:44:15.902740
7798 04:44:15.902820 Set Vref, RX VrefLevel [Byte0]: 28
7799 04:44:15.905984 [Byte1]: 28
7800 04:44:15.910263
7801 04:44:15.910378 Set Vref, RX VrefLevel [Byte0]: 29
7802 04:44:15.913641 [Byte1]: 29
7803 04:44:15.918046
7804 04:44:15.918122 Set Vref, RX VrefLevel [Byte0]: 30
7805 04:44:15.921262 [Byte1]: 30
7806 04:44:15.925917
7807 04:44:15.926008 Set Vref, RX VrefLevel [Byte0]: 31
7808 04:44:15.928835 [Byte1]: 31
7809 04:44:15.933210
7810 04:44:15.933429 Set Vref, RX VrefLevel [Byte0]: 32
7811 04:44:15.936626 [Byte1]: 32
7812 04:44:15.940760
7813 04:44:15.940960 Set Vref, RX VrefLevel [Byte0]: 33
7814 04:44:15.944096 [Byte1]: 33
7815 04:44:15.948365
7816 04:44:15.948508 Set Vref, RX VrefLevel [Byte0]: 34
7817 04:44:15.951909 [Byte1]: 34
7818 04:44:15.956023
7819 04:44:15.956131 Set Vref, RX VrefLevel [Byte0]: 35
7820 04:44:15.958802 [Byte1]: 35
7821 04:44:15.963744
7822 04:44:15.963853 Set Vref, RX VrefLevel [Byte0]: 36
7823 04:44:15.966397 [Byte1]: 36
7824 04:44:15.971076
7825 04:44:15.971198 Set Vref, RX VrefLevel [Byte0]: 37
7826 04:44:15.974318 [Byte1]: 37
7827 04:44:15.978766
7828 04:44:15.978893 Set Vref, RX VrefLevel [Byte0]: 38
7829 04:44:15.982012 [Byte1]: 38
7830 04:44:15.986406
7831 04:44:15.986534 Set Vref, RX VrefLevel [Byte0]: 39
7832 04:44:15.989603 [Byte1]: 39
7833 04:44:15.993857
7834 04:44:15.993992 Set Vref, RX VrefLevel [Byte0]: 40
7835 04:44:15.997284 [Byte1]: 40
7836 04:44:16.001236
7837 04:44:16.001355 Set Vref, RX VrefLevel [Byte0]: 41
7838 04:44:16.004756 [Byte1]: 41
7839 04:44:16.009003
7840 04:44:16.009116 Set Vref, RX VrefLevel [Byte0]: 42
7841 04:44:16.012240 [Byte1]: 42
7842 04:44:16.016477
7843 04:44:16.016599 Set Vref, RX VrefLevel [Byte0]: 43
7844 04:44:16.019952 [Byte1]: 43
7845 04:44:16.024405
7846 04:44:16.024527 Set Vref, RX VrefLevel [Byte0]: 44
7847 04:44:16.027122 [Byte1]: 44
7848 04:44:16.031491
7849 04:44:16.031595 Set Vref, RX VrefLevel [Byte0]: 45
7850 04:44:16.034990 [Byte1]: 45
7851 04:44:16.039064
7852 04:44:16.039165 Set Vref, RX VrefLevel [Byte0]: 46
7853 04:44:16.042229 [Byte1]: 46
7854 04:44:16.046764
7855 04:44:16.046872 Set Vref, RX VrefLevel [Byte0]: 47
7856 04:44:16.049798 [Byte1]: 47
7857 04:44:16.054028
7858 04:44:16.054133 Set Vref, RX VrefLevel [Byte0]: 48
7859 04:44:16.057778 [Byte1]: 48
7860 04:44:16.062174
7861 04:44:16.062279 Set Vref, RX VrefLevel [Byte0]: 49
7862 04:44:16.065046 [Byte1]: 49
7863 04:44:16.069129
7864 04:44:16.069228 Set Vref, RX VrefLevel [Byte0]: 50
7865 04:44:16.072603 [Byte1]: 50
7866 04:44:16.076705
7867 04:44:16.076781 Set Vref, RX VrefLevel [Byte0]: 51
7868 04:44:16.080040 [Byte1]: 51
7869 04:44:16.084640
7870 04:44:16.084715 Set Vref, RX VrefLevel [Byte0]: 52
7871 04:44:16.087847 [Byte1]: 52
7872 04:44:16.092253
7873 04:44:16.092364 Set Vref, RX VrefLevel [Byte0]: 53
7874 04:44:16.095626 [Byte1]: 53
7875 04:44:16.099512
7876 04:44:16.099615 Set Vref, RX VrefLevel [Byte0]: 54
7877 04:44:16.103146 [Byte1]: 54
7878 04:44:16.107139
7879 04:44:16.107261 Set Vref, RX VrefLevel [Byte0]: 55
7880 04:44:16.110460 [Byte1]: 55
7881 04:44:16.115096
7882 04:44:16.117833 Set Vref, RX VrefLevel [Byte0]: 56
7883 04:44:16.117938 [Byte1]: 56
7884 04:44:16.122724
7885 04:44:16.122842 Set Vref, RX VrefLevel [Byte0]: 57
7886 04:44:16.125544 [Byte1]: 57
7887 04:44:16.130161
7888 04:44:16.130275 Set Vref, RX VrefLevel [Byte0]: 58
7889 04:44:16.133524 [Byte1]: 58
7890 04:44:16.137669
7891 04:44:16.137765 Set Vref, RX VrefLevel [Byte0]: 59
7892 04:44:16.140598 [Byte1]: 59
7893 04:44:16.145411
7894 04:44:16.145527 Set Vref, RX VrefLevel [Byte0]: 60
7895 04:44:16.148162 [Byte1]: 60
7896 04:44:16.152896
7897 04:44:16.153000 Set Vref, RX VrefLevel [Byte0]: 61
7898 04:44:16.156338 [Byte1]: 61
7899 04:44:16.160300
7900 04:44:16.160416 Set Vref, RX VrefLevel [Byte0]: 62
7901 04:44:16.163756 [Byte1]: 62
7902 04:44:16.167665
7903 04:44:16.167739 Set Vref, RX VrefLevel [Byte0]: 63
7904 04:44:16.171369 [Byte1]: 63
7905 04:44:16.176021
7906 04:44:16.176140 Set Vref, RX VrefLevel [Byte0]: 64
7907 04:44:16.178618 [Byte1]: 64
7908 04:44:16.182678
7909 04:44:16.182796 Set Vref, RX VrefLevel [Byte0]: 65
7910 04:44:16.186128 [Byte1]: 65
7911 04:44:16.190250
7912 04:44:16.190364 Set Vref, RX VrefLevel [Byte0]: 66
7913 04:44:16.193770 [Byte1]: 66
7914 04:44:16.198347
7915 04:44:16.198443 Set Vref, RX VrefLevel [Byte0]: 67
7916 04:44:16.201138 [Byte1]: 67
7917 04:44:16.205921
7918 04:44:16.206042 Set Vref, RX VrefLevel [Byte0]: 68
7919 04:44:16.208800 [Byte1]: 68
7920 04:44:16.213314
7921 04:44:16.213393 Set Vref, RX VrefLevel [Byte0]: 69
7922 04:44:16.216453 [Byte1]: 69
7923 04:44:16.220785
7924 04:44:16.220888 Set Vref, RX VrefLevel [Byte0]: 70
7925 04:44:16.224106 [Byte1]: 70
7926 04:44:16.228677
7927 04:44:16.228758 Set Vref, RX VrefLevel [Byte0]: 71
7928 04:44:16.231965 [Byte1]: 71
7929 04:44:16.235846
7930 04:44:16.235945 Set Vref, RX VrefLevel [Byte0]: 72
7931 04:44:16.239156 [Byte1]: 72
7932 04:44:16.243341
7933 04:44:16.243414 Final RX Vref Byte 0 = 54 to rank0
7934 04:44:16.246820 Final RX Vref Byte 1 = 62 to rank0
7935 04:44:16.250369 Final RX Vref Byte 0 = 54 to rank1
7936 04:44:16.253161 Final RX Vref Byte 1 = 62 to rank1==
7937 04:44:16.256531 Dram Type= 6, Freq= 0, CH_0, rank 0
7938 04:44:16.263214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7939 04:44:16.263328 ==
7940 04:44:16.263424 DQS Delay:
7941 04:44:16.263514 DQS0 = 0, DQS1 = 0
7942 04:44:16.266519 DQM Delay:
7943 04:44:16.266629 DQM0 = 133, DQM1 = 128
7944 04:44:16.270136 DQ Delay:
7945 04:44:16.273595 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7946 04:44:16.276978 DQ4 =132, DQ5 =122, DQ6 =142, DQ7 =138
7947 04:44:16.280311 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
7948 04:44:16.283689 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7949 04:44:16.283787
7950 04:44:16.283879
7951 04:44:16.283966
7952 04:44:16.287091 [DramC_TX_OE_Calibration] TA2
7953 04:44:16.290363 Original DQ_B0 (3 6) =30, OEN = 27
7954 04:44:16.293555 Original DQ_B1 (3 6) =30, OEN = 27
7955 04:44:16.296732 24, 0x0, End_B0=24 End_B1=24
7956 04:44:16.296844 25, 0x0, End_B0=25 End_B1=25
7957 04:44:16.300068 26, 0x0, End_B0=26 End_B1=26
7958 04:44:16.303485 27, 0x0, End_B0=27 End_B1=27
7959 04:44:16.306945 28, 0x0, End_B0=28 End_B1=28
7960 04:44:16.307055 29, 0x0, End_B0=29 End_B1=29
7961 04:44:16.309784 30, 0x0, End_B0=30 End_B1=30
7962 04:44:16.313113 31, 0x4141, End_B0=30 End_B1=30
7963 04:44:16.316692 Byte0 end_step=30 best_step=27
7964 04:44:16.320159 Byte1 end_step=30 best_step=27
7965 04:44:16.323090 Byte0 TX OE(2T, 0.5T) = (3, 3)
7966 04:44:16.326366 Byte1 TX OE(2T, 0.5T) = (3, 3)
7967 04:44:16.326468
7968 04:44:16.326562
7969 04:44:16.333441 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7970 04:44:16.336639 CH0 RK0: MR19=303, MR18=2521
7971 04:44:16.343374 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
7972 04:44:16.343474
7973 04:44:16.346581 ----->DramcWriteLeveling(PI) begin...
7974 04:44:16.346687 ==
7975 04:44:16.350024 Dram Type= 6, Freq= 0, CH_0, rank 1
7976 04:44:16.353426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7977 04:44:16.353534 ==
7978 04:44:16.356183 Write leveling (Byte 0): 34 => 34
7979 04:44:16.359697 Write leveling (Byte 1): 26 => 26
7980 04:44:16.363330 DramcWriteLeveling(PI) end<-----
7981 04:44:16.363432
7982 04:44:16.363499 ==
7983 04:44:16.366861 Dram Type= 6, Freq= 0, CH_0, rank 1
7984 04:44:16.370159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7985 04:44:16.370260 ==
7986 04:44:16.373372 [Gating] SW mode calibration
7987 04:44:16.379542 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7988 04:44:16.386312 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7989 04:44:16.389791 1 4 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7990 04:44:16.393280 1 4 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7991 04:44:16.399587 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7992 04:44:16.402908 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7993 04:44:16.406151 1 4 16 | B1->B0 | 2d2d 3938 | 0 1 | (0 0) (0 0)
7994 04:44:16.413402 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7995 04:44:16.416382 1 4 24 | B1->B0 | 3434 3737 | 1 1 | (1 1) (0 0)
7996 04:44:16.419922 1 4 28 | B1->B0 | 3434 3838 | 1 0 | (1 1) (1 1)
7997 04:44:16.426664 1 5 0 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7998 04:44:16.430088 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7999 04:44:16.432825 1 5 8 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
8000 04:44:16.439696 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
8001 04:44:16.442844 1 5 16 | B1->B0 | 2d2d 302f | 0 1 | (0 1) (0 0)
8002 04:44:16.446622 1 5 20 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
8003 04:44:16.452971 1 5 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
8004 04:44:16.456671 1 5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8005 04:44:16.459960 1 6 0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
8006 04:44:16.466211 1 6 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8007 04:44:16.469679 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8008 04:44:16.473042 1 6 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8009 04:44:16.479627 1 6 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8010 04:44:16.483176 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8011 04:44:16.485953 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 04:44:16.489347 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 04:44:16.496179 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 04:44:16.499592 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 04:44:16.503146 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 04:44:16.509388 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8017 04:44:16.512941 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8018 04:44:16.516548 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8019 04:44:16.522683 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 04:44:16.526172 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 04:44:16.529352 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 04:44:16.536528 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 04:44:16.539653 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 04:44:16.542843 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 04:44:16.549345 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 04:44:16.552589 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 04:44:16.555891 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 04:44:16.562444 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 04:44:16.566129 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 04:44:16.569096 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 04:44:16.575853 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 04:44:16.579371 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8033 04:44:16.582501 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8034 04:44:16.589041 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 04:44:16.589144 Total UI for P1: 0, mck2ui 16
8036 04:44:16.595984 best dqsien dly found for B0: ( 1, 9, 14)
8037 04:44:16.596092 Total UI for P1: 0, mck2ui 16
8038 04:44:16.599338 best dqsien dly found for B1: ( 1, 9, 14)
8039 04:44:16.606070 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8040 04:44:16.608795 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8041 04:44:16.608898
8042 04:44:16.612165 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8043 04:44:16.615737 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8044 04:44:16.619320 [Gating] SW calibration Done
8045 04:44:16.619423 ==
8046 04:44:16.622064 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 04:44:16.625537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 04:44:16.625635 ==
8049 04:44:16.628927 RX Vref Scan: 0
8050 04:44:16.629023
8051 04:44:16.629115 RX Vref 0 -> 0, step: 1
8052 04:44:16.629204
8053 04:44:16.632484 RX Delay 0 -> 252, step: 8
8054 04:44:16.635257 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8055 04:44:16.642079 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8056 04:44:16.645457 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8057 04:44:16.649114 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8058 04:44:16.652169 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8059 04:44:16.656117 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8060 04:44:16.659083 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8061 04:44:16.665389 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8062 04:44:16.669004 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8063 04:44:16.672087 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8064 04:44:16.675383 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8065 04:44:16.679134 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8066 04:44:16.685843 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8067 04:44:16.689245 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8068 04:44:16.692075 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8069 04:44:16.695557 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8070 04:44:16.695658 ==
8071 04:44:16.698846 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 04:44:16.705801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 04:44:16.705898 ==
8074 04:44:16.705966 DQS Delay:
8075 04:44:16.709192 DQS0 = 0, DQS1 = 0
8076 04:44:16.709267 DQM Delay:
8077 04:44:16.712524 DQM0 = 136, DQM1 = 131
8078 04:44:16.712601 DQ Delay:
8079 04:44:16.715255 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8080 04:44:16.718689 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8081 04:44:16.722246 DQ8 =123, DQ9 =119, DQ10 =131, DQ11 =123
8082 04:44:16.725067 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8083 04:44:16.725142
8084 04:44:16.725205
8085 04:44:16.725263 ==
8086 04:44:16.728623 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 04:44:16.735567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 04:44:16.735674 ==
8089 04:44:16.735767
8090 04:44:16.735859
8091 04:44:16.735947 TX Vref Scan disable
8092 04:44:16.738952 == TX Byte 0 ==
8093 04:44:16.741702 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8094 04:44:16.748570 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8095 04:44:16.748680 == TX Byte 1 ==
8096 04:44:16.751988 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8097 04:44:16.758838 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8098 04:44:16.758946 ==
8099 04:44:16.761649 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 04:44:16.764948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 04:44:16.765061 ==
8102 04:44:16.778619
8103 04:44:16.782033 TX Vref early break, caculate TX vref
8104 04:44:16.785271 TX Vref=16, minBit 0, minWin=23, winSum=386
8105 04:44:16.788478 TX Vref=18, minBit 0, minWin=23, winSum=400
8106 04:44:16.791701 TX Vref=20, minBit 1, minWin=24, winSum=408
8107 04:44:16.794869 TX Vref=22, minBit 1, minWin=25, winSum=416
8108 04:44:16.798528 TX Vref=24, minBit 1, minWin=25, winSum=419
8109 04:44:16.804838 TX Vref=26, minBit 0, minWin=25, winSum=427
8110 04:44:16.808634 TX Vref=28, minBit 4, minWin=25, winSum=427
8111 04:44:16.811595 TX Vref=30, minBit 0, minWin=25, winSum=417
8112 04:44:16.814987 TX Vref=32, minBit 7, minWin=24, winSum=410
8113 04:44:16.818282 TX Vref=34, minBit 1, minWin=23, winSum=404
8114 04:44:16.825132 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 26
8115 04:44:16.825241
8116 04:44:16.828013 Final TX Range 0 Vref 26
8117 04:44:16.828112
8118 04:44:16.828211 ==
8119 04:44:16.831405 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 04:44:16.834742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 04:44:16.834846 ==
8122 04:44:16.834947
8123 04:44:16.835036
8124 04:44:16.838184 TX Vref Scan disable
8125 04:44:16.845272 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8126 04:44:16.845361 == TX Byte 0 ==
8127 04:44:16.847952 u2DelayCellOfst[0]=10 cells (3 PI)
8128 04:44:16.851322 u2DelayCellOfst[1]=13 cells (4 PI)
8129 04:44:16.854865 u2DelayCellOfst[2]=10 cells (3 PI)
8130 04:44:16.858381 u2DelayCellOfst[3]=10 cells (3 PI)
8131 04:44:16.861185 u2DelayCellOfst[4]=6 cells (2 PI)
8132 04:44:16.864567 u2DelayCellOfst[5]=0 cells (0 PI)
8133 04:44:16.867998 u2DelayCellOfst[6]=13 cells (4 PI)
8134 04:44:16.871541 u2DelayCellOfst[7]=16 cells (5 PI)
8135 04:44:16.874826 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8136 04:44:16.878084 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8137 04:44:16.881569 == TX Byte 1 ==
8138 04:44:16.881648 u2DelayCellOfst[8]=0 cells (0 PI)
8139 04:44:16.884901 u2DelayCellOfst[9]=0 cells (0 PI)
8140 04:44:16.888315 u2DelayCellOfst[10]=6 cells (2 PI)
8141 04:44:16.891077 u2DelayCellOfst[11]=6 cells (2 PI)
8142 04:44:16.894473 u2DelayCellOfst[12]=10 cells (3 PI)
8143 04:44:16.897852 u2DelayCellOfst[13]=10 cells (3 PI)
8144 04:44:16.901160 u2DelayCellOfst[14]=13 cells (4 PI)
8145 04:44:16.904283 u2DelayCellOfst[15]=10 cells (3 PI)
8146 04:44:16.907991 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8147 04:44:16.914695 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8148 04:44:16.914805 DramC Write-DBI on
8149 04:44:16.914968 ==
8150 04:44:16.917842 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 04:44:16.921306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 04:44:16.924834 ==
8153 04:44:16.925011
8154 04:44:16.925137
8155 04:44:16.925264 TX Vref Scan disable
8156 04:44:16.928155 == TX Byte 0 ==
8157 04:44:16.931786 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8158 04:44:16.934717 == TX Byte 1 ==
8159 04:44:16.938245 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8160 04:44:16.938368 DramC Write-DBI off
8161 04:44:16.941294
8162 04:44:16.941398 [DATLAT]
8163 04:44:16.941496 Freq=1600, CH0 RK1
8164 04:44:16.941600
8165 04:44:16.944931 DATLAT Default: 0xf
8166 04:44:16.945062 0, 0xFFFF, sum = 0
8167 04:44:16.947983 1, 0xFFFF, sum = 0
8168 04:44:16.948164 2, 0xFFFF, sum = 0
8169 04:44:16.951673 3, 0xFFFF, sum = 0
8170 04:44:16.955051 4, 0xFFFF, sum = 0
8171 04:44:16.955171 5, 0xFFFF, sum = 0
8172 04:44:16.957905 6, 0xFFFF, sum = 0
8173 04:44:16.958040 7, 0xFFFF, sum = 0
8174 04:44:16.961411 8, 0xFFFF, sum = 0
8175 04:44:16.961528 9, 0xFFFF, sum = 0
8176 04:44:16.964947 10, 0xFFFF, sum = 0
8177 04:44:16.965053 11, 0xFFFF, sum = 0
8178 04:44:16.968441 12, 0xFFFF, sum = 0
8179 04:44:16.968562 13, 0xFFFF, sum = 0
8180 04:44:16.971271 14, 0x0, sum = 1
8181 04:44:16.971431 15, 0x0, sum = 2
8182 04:44:16.974716 16, 0x0, sum = 3
8183 04:44:16.974827 17, 0x0, sum = 4
8184 04:44:16.978322 best_step = 15
8185 04:44:16.978445
8186 04:44:16.978535 ==
8187 04:44:16.981777 Dram Type= 6, Freq= 0, CH_0, rank 1
8188 04:44:16.985027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8189 04:44:16.985139 ==
8190 04:44:16.985239 RX Vref Scan: 0
8191 04:44:16.987771
8192 04:44:16.987881 RX Vref 0 -> 0, step: 1
8193 04:44:16.987975
8194 04:44:16.991794 RX Delay 19 -> 252, step: 4
8195 04:44:16.994789 iDelay=191, Bit 0, Center 132 (79 ~ 186) 108
8196 04:44:17.001308 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8197 04:44:17.004887 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8198 04:44:17.007622 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8199 04:44:17.011203 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8200 04:44:17.014881 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8201 04:44:17.021437 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8202 04:44:17.024709 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8203 04:44:17.027766 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8204 04:44:17.030956 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8205 04:44:17.034181 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8206 04:44:17.041228 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8207 04:44:17.044565 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8208 04:44:17.047824 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8209 04:44:17.050683 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8210 04:44:17.054224 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8211 04:44:17.057759 ==
8212 04:44:17.060763 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 04:44:17.064335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 04:44:17.064444 ==
8215 04:44:17.064545 DQS Delay:
8216 04:44:17.067197 DQS0 = 0, DQS1 = 0
8217 04:44:17.067308 DQM Delay:
8218 04:44:17.070839 DQM0 = 134, DQM1 = 127
8219 04:44:17.070946 DQ Delay:
8220 04:44:17.074323 DQ0 =132, DQ1 =138, DQ2 =130, DQ3 =134
8221 04:44:17.077153 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8222 04:44:17.080826 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8223 04:44:17.083785 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
8224 04:44:17.083896
8225 04:44:17.083996
8226 04:44:17.084108
8227 04:44:17.087261 [DramC_TX_OE_Calibration] TA2
8228 04:44:17.090897 Original DQ_B0 (3 6) =30, OEN = 27
8229 04:44:17.094272 Original DQ_B1 (3 6) =30, OEN = 27
8230 04:44:17.096978 24, 0x0, End_B0=24 End_B1=24
8231 04:44:17.100871 25, 0x0, End_B0=25 End_B1=25
8232 04:44:17.100977 26, 0x0, End_B0=26 End_B1=26
8233 04:44:17.104097 27, 0x0, End_B0=27 End_B1=27
8234 04:44:17.107593 28, 0x0, End_B0=28 End_B1=28
8235 04:44:17.110285 29, 0x0, End_B0=29 End_B1=29
8236 04:44:17.113641 30, 0x0, End_B0=30 End_B1=30
8237 04:44:17.113749 31, 0x4141, End_B0=30 End_B1=30
8238 04:44:17.117169 Byte0 end_step=30 best_step=27
8239 04:44:17.120642 Byte1 end_step=30 best_step=27
8240 04:44:17.124032 Byte0 TX OE(2T, 0.5T) = (3, 3)
8241 04:44:17.126989 Byte1 TX OE(2T, 0.5T) = (3, 3)
8242 04:44:17.127114
8243 04:44:17.127209
8244 04:44:17.133748 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8245 04:44:17.137017 CH0 RK1: MR19=303, MR18=1E06
8246 04:44:17.143718 CH0_RK1: MR19=0x303, MR18=0x1E06, DQSOSC=394, MR23=63, INC=23, DEC=15
8247 04:44:17.147128 [RxdqsGatingPostProcess] freq 1600
8248 04:44:17.153532 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8249 04:44:17.153640 best DQS0 dly(2T, 0.5T) = (1, 1)
8250 04:44:17.156890 best DQS1 dly(2T, 0.5T) = (1, 1)
8251 04:44:17.160315 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8252 04:44:17.163815 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8253 04:44:17.166930 best DQS0 dly(2T, 0.5T) = (1, 1)
8254 04:44:17.170675 best DQS1 dly(2T, 0.5T) = (1, 1)
8255 04:44:17.173979 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8256 04:44:17.176961 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8257 04:44:17.180591 Pre-setting of DQS Precalculation
8258 04:44:17.184011 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8259 04:44:17.184126 ==
8260 04:44:17.186824 Dram Type= 6, Freq= 0, CH_1, rank 0
8261 04:44:17.193881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 04:44:17.193986 ==
8263 04:44:17.196807 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8264 04:44:17.203672 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8265 04:44:17.206605 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8266 04:44:17.213798 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8267 04:44:17.221581 [CA 0] Center 41 (12~71) winsize 60
8268 04:44:17.224228 [CA 1] Center 41 (12~71) winsize 60
8269 04:44:17.227645 [CA 2] Center 38 (9~68) winsize 60
8270 04:44:17.230972 [CA 3] Center 37 (9~66) winsize 58
8271 04:44:17.234576 [CA 4] Center 37 (8~67) winsize 60
8272 04:44:17.238091 [CA 5] Center 36 (7~66) winsize 60
8273 04:44:17.238196
8274 04:44:17.240896 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8275 04:44:17.240975
8276 04:44:17.244443 [CATrainingPosCal] consider 1 rank data
8277 04:44:17.247889 u2DelayCellTimex100 = 290/100 ps
8278 04:44:17.251341 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8279 04:44:17.257895 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8280 04:44:17.260694 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8281 04:44:17.264108 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8282 04:44:17.267711 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8283 04:44:17.271256 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8284 04:44:17.271337
8285 04:44:17.274133 CA PerBit enable=1, Macro0, CA PI delay=36
8286 04:44:17.274210
8287 04:44:17.277968 [CBTSetCACLKResult] CA Dly = 36
8288 04:44:17.281110 CS Dly: 11 (0~42)
8289 04:44:17.284365 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8290 04:44:17.287661 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8291 04:44:17.287761 ==
8292 04:44:17.291068 Dram Type= 6, Freq= 0, CH_1, rank 1
8293 04:44:17.294335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 04:44:17.294461 ==
8295 04:44:17.300655 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8296 04:44:17.304086 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8297 04:44:17.310964 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8298 04:44:17.313750 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8299 04:44:17.324300 [CA 0] Center 42 (12~72) winsize 61
8300 04:44:17.327651 [CA 1] Center 41 (12~71) winsize 60
8301 04:44:17.330976 [CA 2] Center 38 (9~68) winsize 60
8302 04:44:17.334219 [CA 3] Center 38 (8~68) winsize 61
8303 04:44:17.337682 [CA 4] Center 38 (8~68) winsize 61
8304 04:44:17.341128 [CA 5] Center 37 (8~67) winsize 60
8305 04:44:17.341212
8306 04:44:17.344653 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8307 04:44:17.344736
8308 04:44:17.347425 [CATrainingPosCal] consider 2 rank data
8309 04:44:17.350882 u2DelayCellTimex100 = 290/100 ps
8310 04:44:17.354405 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8311 04:44:17.360546 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8312 04:44:17.363915 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8313 04:44:17.367682 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8314 04:44:17.370729 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8315 04:44:17.373840 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8316 04:44:17.373924
8317 04:44:17.377282 CA PerBit enable=1, Macro0, CA PI delay=37
8318 04:44:17.377365
8319 04:44:17.380741 [CBTSetCACLKResult] CA Dly = 37
8320 04:44:17.384277 CS Dly: 12 (0~45)
8321 04:44:17.387508 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8322 04:44:17.390729 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8323 04:44:17.390808
8324 04:44:17.394039 ----->DramcWriteLeveling(PI) begin...
8325 04:44:17.394115 ==
8326 04:44:17.397242 Dram Type= 6, Freq= 0, CH_1, rank 0
8327 04:44:17.403625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8328 04:44:17.403701 ==
8329 04:44:17.406960 Write leveling (Byte 0): 24 => 24
8330 04:44:17.407061 Write leveling (Byte 1): 26 => 26
8331 04:44:17.410276 DramcWriteLeveling(PI) end<-----
8332 04:44:17.410384
8333 04:44:17.410476 ==
8334 04:44:17.413743 Dram Type= 6, Freq= 0, CH_1, rank 0
8335 04:44:17.420707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 04:44:17.420819 ==
8337 04:44:17.423913 [Gating] SW mode calibration
8338 04:44:17.430041 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8339 04:44:17.433518 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8340 04:44:17.440415 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 04:44:17.443723 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 04:44:17.447026 1 4 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
8343 04:44:17.453326 1 4 12 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
8344 04:44:17.456871 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 04:44:17.460397 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 04:44:17.466678 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 04:44:17.470165 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 04:44:17.473519 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 04:44:17.476924 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 04:44:17.484010 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
8351 04:44:17.486875 1 5 12 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
8352 04:44:17.490516 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8353 04:44:17.496691 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 04:44:17.500150 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 04:44:17.503622 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 04:44:17.510477 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 04:44:17.513742 1 6 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
8358 04:44:17.516942 1 6 8 | B1->B0 | 2525 3a3a | 0 0 | (0 0) (0 0)
8359 04:44:17.523279 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8360 04:44:17.526704 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 04:44:17.530301 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 04:44:17.536839 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 04:44:17.540454 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 04:44:17.543258 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 04:44:17.550276 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 04:44:17.553531 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8367 04:44:17.557167 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8368 04:44:17.563508 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8369 04:44:17.566553 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 04:44:17.570310 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 04:44:17.577093 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 04:44:17.579968 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 04:44:17.583591 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 04:44:17.586932 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 04:44:17.593381 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 04:44:17.596804 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 04:44:17.599712 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 04:44:17.606575 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 04:44:17.610276 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 04:44:17.613103 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 04:44:17.620181 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 04:44:17.623465 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8383 04:44:17.626621 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8384 04:44:17.633327 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 04:44:17.636479 Total UI for P1: 0, mck2ui 16
8386 04:44:17.639592 best dqsien dly found for B0: ( 1, 9, 10)
8387 04:44:17.643529 Total UI for P1: 0, mck2ui 16
8388 04:44:17.646764 best dqsien dly found for B1: ( 1, 9, 12)
8389 04:44:17.649757 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8390 04:44:17.653486 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8391 04:44:17.653568
8392 04:44:17.656403 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8393 04:44:17.659810 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8394 04:44:17.663158 [Gating] SW calibration Done
8395 04:44:17.663243 ==
8396 04:44:17.666382 Dram Type= 6, Freq= 0, CH_1, rank 0
8397 04:44:17.669908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 04:44:17.669987 ==
8399 04:44:17.673363 RX Vref Scan: 0
8400 04:44:17.673443
8401 04:44:17.673507 RX Vref 0 -> 0, step: 1
8402 04:44:17.676277
8403 04:44:17.676365 RX Delay 0 -> 252, step: 8
8404 04:44:17.679854 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8405 04:44:17.686711 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8406 04:44:17.689623 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8407 04:44:17.693157 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8408 04:44:17.696589 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8409 04:44:17.699374 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8410 04:44:17.706064 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8411 04:44:17.709797 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8412 04:44:17.713112 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8413 04:44:17.716251 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8414 04:44:17.719644 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8415 04:44:17.726149 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8416 04:44:17.729570 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8417 04:44:17.732464 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8418 04:44:17.736053 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8419 04:44:17.742333 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8420 04:44:17.742412 ==
8421 04:44:17.746267 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 04:44:17.749516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 04:44:17.749594 ==
8424 04:44:17.749658 DQS Delay:
8425 04:44:17.752594 DQS0 = 0, DQS1 = 0
8426 04:44:17.752667 DQM Delay:
8427 04:44:17.755675 DQM0 = 136, DQM1 = 132
8428 04:44:17.755754 DQ Delay:
8429 04:44:17.759431 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8430 04:44:17.762319 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8431 04:44:17.765820 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8432 04:44:17.768717 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8433 04:44:17.768797
8434 04:44:17.768865
8435 04:44:17.772620 ==
8436 04:44:17.775657 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 04:44:17.779040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 04:44:17.779121 ==
8439 04:44:17.779187
8440 04:44:17.779247
8441 04:44:17.782618 TX Vref Scan disable
8442 04:44:17.782689 == TX Byte 0 ==
8443 04:44:17.785289 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8444 04:44:17.792229 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8445 04:44:17.792317 == TX Byte 1 ==
8446 04:44:17.798888 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8447 04:44:17.801771 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8448 04:44:17.801851 ==
8449 04:44:17.805360 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 04:44:17.808709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 04:44:17.808782 ==
8452 04:44:17.821572
8453 04:44:17.824842 TX Vref early break, caculate TX vref
8454 04:44:17.828356 TX Vref=16, minBit 0, minWin=22, winSum=374
8455 04:44:17.831658 TX Vref=18, minBit 0, minWin=22, winSum=383
8456 04:44:17.834964 TX Vref=20, minBit 0, minWin=23, winSum=394
8457 04:44:17.837920 TX Vref=22, minBit 1, minWin=23, winSum=404
8458 04:44:17.841560 TX Vref=24, minBit 0, minWin=25, winSum=417
8459 04:44:17.847976 TX Vref=26, minBit 0, minWin=24, winSum=422
8460 04:44:17.851615 TX Vref=28, minBit 1, minWin=25, winSum=429
8461 04:44:17.854591 TX Vref=30, minBit 2, minWin=24, winSum=424
8462 04:44:17.858158 TX Vref=32, minBit 0, minWin=24, winSum=410
8463 04:44:17.861642 TX Vref=34, minBit 6, minWin=23, winSum=401
8464 04:44:17.867604 [TxChooseVref] Worse bit 1, Min win 25, Win sum 429, Final Vref 28
8465 04:44:17.867711
8466 04:44:17.871333 Final TX Range 0 Vref 28
8467 04:44:17.871409
8468 04:44:17.871471 ==
8469 04:44:17.874302 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 04:44:17.877684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 04:44:17.877763 ==
8472 04:44:17.877826
8473 04:44:17.877922
8474 04:44:17.881362 TX Vref Scan disable
8475 04:44:17.887890 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8476 04:44:17.887971 == TX Byte 0 ==
8477 04:44:17.891200 u2DelayCellOfst[0]=16 cells (5 PI)
8478 04:44:17.893844 u2DelayCellOfst[1]=10 cells (3 PI)
8479 04:44:17.897842 u2DelayCellOfst[2]=0 cells (0 PI)
8480 04:44:17.900565 u2DelayCellOfst[3]=6 cells (2 PI)
8481 04:44:17.904081 u2DelayCellOfst[4]=10 cells (3 PI)
8482 04:44:17.907781 u2DelayCellOfst[5]=20 cells (6 PI)
8483 04:44:17.910594 u2DelayCellOfst[6]=20 cells (6 PI)
8484 04:44:17.914138 u2DelayCellOfst[7]=6 cells (2 PI)
8485 04:44:17.917641 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8486 04:44:17.920856 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8487 04:44:17.924144 == TX Byte 1 ==
8488 04:44:17.927702 u2DelayCellOfst[8]=0 cells (0 PI)
8489 04:44:17.927778 u2DelayCellOfst[9]=6 cells (2 PI)
8490 04:44:17.930400 u2DelayCellOfst[10]=13 cells (4 PI)
8491 04:44:17.933756 u2DelayCellOfst[11]=3 cells (1 PI)
8492 04:44:17.937686 u2DelayCellOfst[12]=13 cells (4 PI)
8493 04:44:17.940908 u2DelayCellOfst[13]=13 cells (4 PI)
8494 04:44:17.943936 u2DelayCellOfst[14]=16 cells (5 PI)
8495 04:44:17.947570 u2DelayCellOfst[15]=16 cells (5 PI)
8496 04:44:17.950973 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8497 04:44:17.957356 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8498 04:44:17.957441 DramC Write-DBI on
8499 04:44:17.957508 ==
8500 04:44:17.960836 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 04:44:17.967129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 04:44:17.967212 ==
8503 04:44:17.967278
8504 04:44:17.967338
8505 04:44:17.967396 TX Vref Scan disable
8506 04:44:17.971341 == TX Byte 0 ==
8507 04:44:17.974175 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8508 04:44:17.977683 == TX Byte 1 ==
8509 04:44:17.980997 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8510 04:44:17.984364 DramC Write-DBI off
8511 04:44:17.984448
8512 04:44:17.984559 [DATLAT]
8513 04:44:17.984648 Freq=1600, CH1 RK0
8514 04:44:17.984711
8515 04:44:17.987572 DATLAT Default: 0xf
8516 04:44:17.987654 0, 0xFFFF, sum = 0
8517 04:44:17.990904 1, 0xFFFF, sum = 0
8518 04:44:17.994144 2, 0xFFFF, sum = 0
8519 04:44:17.994227 3, 0xFFFF, sum = 0
8520 04:44:17.997440 4, 0xFFFF, sum = 0
8521 04:44:17.997533 5, 0xFFFF, sum = 0
8522 04:44:18.000695 6, 0xFFFF, sum = 0
8523 04:44:18.000777 7, 0xFFFF, sum = 0
8524 04:44:18.003963 8, 0xFFFF, sum = 0
8525 04:44:18.004045 9, 0xFFFF, sum = 0
8526 04:44:18.007906 10, 0xFFFF, sum = 0
8527 04:44:18.007984 11, 0xFFFF, sum = 0
8528 04:44:18.011119 12, 0xFFFF, sum = 0
8529 04:44:18.011200 13, 0xFFFF, sum = 0
8530 04:44:18.014510 14, 0x0, sum = 1
8531 04:44:18.014591 15, 0x0, sum = 2
8532 04:44:18.017267 16, 0x0, sum = 3
8533 04:44:18.017343 17, 0x0, sum = 4
8534 04:44:18.020768 best_step = 15
8535 04:44:18.020843
8536 04:44:18.020904 ==
8537 04:44:18.024234 Dram Type= 6, Freq= 0, CH_1, rank 0
8538 04:44:18.027548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8539 04:44:18.027627 ==
8540 04:44:18.027690 RX Vref Scan: 1
8541 04:44:18.030782
8542 04:44:18.030862 Set Vref Range= 24 -> 127
8543 04:44:18.030927
8544 04:44:18.034303 RX Vref 24 -> 127, step: 1
8545 04:44:18.034376
8546 04:44:18.037807 RX Delay 27 -> 252, step: 4
8547 04:44:18.037882
8548 04:44:18.040655 Set Vref, RX VrefLevel [Byte0]: 24
8549 04:44:18.044145 [Byte1]: 24
8550 04:44:18.044216
8551 04:44:18.047751 Set Vref, RX VrefLevel [Byte0]: 25
8552 04:44:18.051168 [Byte1]: 25
8553 04:44:18.051286
8554 04:44:18.054370 Set Vref, RX VrefLevel [Byte0]: 26
8555 04:44:18.057592 [Byte1]: 26
8556 04:44:18.060883
8557 04:44:18.060980 Set Vref, RX VrefLevel [Byte0]: 27
8558 04:44:18.064699 [Byte1]: 27
8559 04:44:18.068930
8560 04:44:18.069009 Set Vref, RX VrefLevel [Byte0]: 28
8561 04:44:18.072094 [Byte1]: 28
8562 04:44:18.076218
8563 04:44:18.076331 Set Vref, RX VrefLevel [Byte0]: 29
8564 04:44:18.079814 [Byte1]: 29
8565 04:44:18.083533
8566 04:44:18.083648 Set Vref, RX VrefLevel [Byte0]: 30
8567 04:44:18.086952 [Byte1]: 30
8568 04:44:18.091175
8569 04:44:18.091294 Set Vref, RX VrefLevel [Byte0]: 31
8570 04:44:18.094615 [Byte1]: 31
8571 04:44:18.098710
8572 04:44:18.098799 Set Vref, RX VrefLevel [Byte0]: 32
8573 04:44:18.102089 [Byte1]: 32
8574 04:44:18.106125
8575 04:44:18.106208 Set Vref, RX VrefLevel [Byte0]: 33
8576 04:44:18.109517 [Byte1]: 33
8577 04:44:18.113628
8578 04:44:18.113716 Set Vref, RX VrefLevel [Byte0]: 34
8579 04:44:18.117007 [Byte1]: 34
8580 04:44:18.121159
8581 04:44:18.121253 Set Vref, RX VrefLevel [Byte0]: 35
8582 04:44:18.125164 [Byte1]: 35
8583 04:44:18.128766
8584 04:44:18.128875 Set Vref, RX VrefLevel [Byte0]: 36
8585 04:44:18.132313 [Byte1]: 36
8586 04:44:18.136234
8587 04:44:18.136374 Set Vref, RX VrefLevel [Byte0]: 37
8588 04:44:18.139968 [Byte1]: 37
8589 04:44:18.144125
8590 04:44:18.144234 Set Vref, RX VrefLevel [Byte0]: 38
8591 04:44:18.147027 [Byte1]: 38
8592 04:44:18.151360
8593 04:44:18.151436 Set Vref, RX VrefLevel [Byte0]: 39
8594 04:44:18.154858 [Byte1]: 39
8595 04:44:18.159186
8596 04:44:18.159298 Set Vref, RX VrefLevel [Byte0]: 40
8597 04:44:18.162691 [Byte1]: 40
8598 04:44:18.166877
8599 04:44:18.166960 Set Vref, RX VrefLevel [Byte0]: 41
8600 04:44:18.169783 [Byte1]: 41
8601 04:44:18.174495
8602 04:44:18.174606 Set Vref, RX VrefLevel [Byte0]: 42
8603 04:44:18.177735 [Byte1]: 42
8604 04:44:18.181380
8605 04:44:18.181487 Set Vref, RX VrefLevel [Byte0]: 43
8606 04:44:18.185190 [Byte1]: 43
8607 04:44:18.189101
8608 04:44:18.189192 Set Vref, RX VrefLevel [Byte0]: 44
8609 04:44:18.192455 [Byte1]: 44
8610 04:44:18.196757
8611 04:44:18.196836 Set Vref, RX VrefLevel [Byte0]: 45
8612 04:44:18.200322 [Byte1]: 45
8613 04:44:18.204017
8614 04:44:18.204096 Set Vref, RX VrefLevel [Byte0]: 46
8615 04:44:18.207630 [Byte1]: 46
8616 04:44:18.211724
8617 04:44:18.211830 Set Vref, RX VrefLevel [Byte0]: 47
8618 04:44:18.215245 [Byte1]: 47
8619 04:44:18.219421
8620 04:44:18.219497 Set Vref, RX VrefLevel [Byte0]: 48
8621 04:44:18.222998 [Byte1]: 48
8622 04:44:18.226574
8623 04:44:18.226684 Set Vref, RX VrefLevel [Byte0]: 49
8624 04:44:18.229834 [Byte1]: 49
8625 04:44:18.234371
8626 04:44:18.234483 Set Vref, RX VrefLevel [Byte0]: 50
8627 04:44:18.238146 [Byte1]: 50
8628 04:44:18.241929
8629 04:44:18.242007 Set Vref, RX VrefLevel [Byte0]: 51
8630 04:44:18.244927 [Byte1]: 51
8631 04:44:18.249776
8632 04:44:18.249880 Set Vref, RX VrefLevel [Byte0]: 52
8633 04:44:18.252736 [Byte1]: 52
8634 04:44:18.256934
8635 04:44:18.257043 Set Vref, RX VrefLevel [Byte0]: 53
8636 04:44:18.260290 [Byte1]: 53
8637 04:44:18.264512
8638 04:44:18.264623 Set Vref, RX VrefLevel [Byte0]: 54
8639 04:44:18.268187 [Byte1]: 54
8640 04:44:18.272360
8641 04:44:18.272471 Set Vref, RX VrefLevel [Byte0]: 55
8642 04:44:18.275311 [Byte1]: 55
8643 04:44:18.279557
8644 04:44:18.279663 Set Vref, RX VrefLevel [Byte0]: 56
8645 04:44:18.283053 [Byte1]: 56
8646 04:44:18.287160
8647 04:44:18.287264 Set Vref, RX VrefLevel [Byte0]: 57
8648 04:44:18.290596 [Byte1]: 57
8649 04:44:18.294647
8650 04:44:18.294766 Set Vref, RX VrefLevel [Byte0]: 58
8651 04:44:18.298038 [Byte1]: 58
8652 04:44:18.301933
8653 04:44:18.302066 Set Vref, RX VrefLevel [Byte0]: 59
8654 04:44:18.305243 [Byte1]: 59
8655 04:44:18.309587
8656 04:44:18.309702 Set Vref, RX VrefLevel [Byte0]: 60
8657 04:44:18.312970 [Byte1]: 60
8658 04:44:18.317261
8659 04:44:18.317348 Set Vref, RX VrefLevel [Byte0]: 61
8660 04:44:18.320829 [Byte1]: 61
8661 04:44:18.325028
8662 04:44:18.325139 Set Vref, RX VrefLevel [Byte0]: 62
8663 04:44:18.328146 [Byte1]: 62
8664 04:44:18.332577
8665 04:44:18.332684 Set Vref, RX VrefLevel [Byte0]: 63
8666 04:44:18.336186 [Byte1]: 63
8667 04:44:18.340302
8668 04:44:18.340410 Set Vref, RX VrefLevel [Byte0]: 64
8669 04:44:18.343132 [Byte1]: 64
8670 04:44:18.347631
8671 04:44:18.347741 Set Vref, RX VrefLevel [Byte0]: 65
8672 04:44:18.350620 [Byte1]: 65
8673 04:44:18.354956
8674 04:44:18.355063 Set Vref, RX VrefLevel [Byte0]: 66
8675 04:44:18.358060 [Byte1]: 66
8676 04:44:18.362731
8677 04:44:18.362840 Set Vref, RX VrefLevel [Byte0]: 67
8678 04:44:18.365511 [Byte1]: 67
8679 04:44:18.369923
8680 04:44:18.370036 Set Vref, RX VrefLevel [Byte0]: 68
8681 04:44:18.373581 [Byte1]: 68
8682 04:44:18.377372
8683 04:44:18.377485 Set Vref, RX VrefLevel [Byte0]: 69
8684 04:44:18.381181 [Byte1]: 69
8685 04:44:18.385124
8686 04:44:18.385224 Set Vref, RX VrefLevel [Byte0]: 70
8687 04:44:18.388815 [Byte1]: 70
8688 04:44:18.392436
8689 04:44:18.392550 Set Vref, RX VrefLevel [Byte0]: 71
8690 04:44:18.396120 [Byte1]: 71
8691 04:44:18.400374
8692 04:44:18.400484 Set Vref, RX VrefLevel [Byte0]: 72
8693 04:44:18.403271 [Byte1]: 72
8694 04:44:18.407597
8695 04:44:18.407716 Set Vref, RX VrefLevel [Byte0]: 73
8696 04:44:18.411213 [Byte1]: 73
8697 04:44:18.415352
8698 04:44:18.415469 Set Vref, RX VrefLevel [Byte0]: 74
8699 04:44:18.418853 [Byte1]: 74
8700 04:44:18.422778
8701 04:44:18.422885 Set Vref, RX VrefLevel [Byte0]: 75
8702 04:44:18.426234 [Byte1]: 75
8703 04:44:18.430125
8704 04:44:18.430209 Set Vref, RX VrefLevel [Byte0]: 76
8705 04:44:18.433658 [Byte1]: 76
8706 04:44:18.437800
8707 04:44:18.437875 Final RX Vref Byte 0 = 58 to rank0
8708 04:44:18.441212 Final RX Vref Byte 1 = 53 to rank0
8709 04:44:18.444179 Final RX Vref Byte 0 = 58 to rank1
8710 04:44:18.447729 Final RX Vref Byte 1 = 53 to rank1==
8711 04:44:18.450812 Dram Type= 6, Freq= 0, CH_1, rank 0
8712 04:44:18.457950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8713 04:44:18.458042 ==
8714 04:44:18.458110 DQS Delay:
8715 04:44:18.458171 DQS0 = 0, DQS1 = 0
8716 04:44:18.461241 DQM Delay:
8717 04:44:18.461314 DQM0 = 134, DQM1 = 130
8718 04:44:18.464734 DQ Delay:
8719 04:44:18.467466 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8720 04:44:18.471030 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8721 04:44:18.474013 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8722 04:44:18.477705 DQ12 =138, DQ13 =136, DQ14 =140, DQ15 =140
8723 04:44:18.477803
8724 04:44:18.477882
8725 04:44:18.477955
8726 04:44:18.480691 [DramC_TX_OE_Calibration] TA2
8727 04:44:18.484300 Original DQ_B0 (3 6) =30, OEN = 27
8728 04:44:18.487279 Original DQ_B1 (3 6) =30, OEN = 27
8729 04:44:18.490815 24, 0x0, End_B0=24 End_B1=24
8730 04:44:18.490895 25, 0x0, End_B0=25 End_B1=25
8731 04:44:18.494326 26, 0x0, End_B0=26 End_B1=26
8732 04:44:18.497363 27, 0x0, End_B0=27 End_B1=27
8733 04:44:18.500964 28, 0x0, End_B0=28 End_B1=28
8734 04:44:18.503814 29, 0x0, End_B0=29 End_B1=29
8735 04:44:18.503923 30, 0x0, End_B0=30 End_B1=30
8736 04:44:18.507375 31, 0x4141, End_B0=30 End_B1=30
8737 04:44:18.510888 Byte0 end_step=30 best_step=27
8738 04:44:18.514362 Byte1 end_step=30 best_step=27
8739 04:44:18.517792 Byte0 TX OE(2T, 0.5T) = (3, 3)
8740 04:44:18.520678 Byte1 TX OE(2T, 0.5T) = (3, 3)
8741 04:44:18.520759
8742 04:44:18.520824
8743 04:44:18.527610 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8744 04:44:18.530318 CH1 RK0: MR19=303, MR18=1624
8745 04:44:18.536924 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8746 04:44:18.537006
8747 04:44:18.540439 ----->DramcWriteLeveling(PI) begin...
8748 04:44:18.540513 ==
8749 04:44:18.543622 Dram Type= 6, Freq= 0, CH_1, rank 1
8750 04:44:18.547093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 04:44:18.547171 ==
8752 04:44:18.550527 Write leveling (Byte 0): 27 => 27
8753 04:44:18.554159 Write leveling (Byte 1): 28 => 28
8754 04:44:18.556985 DramcWriteLeveling(PI) end<-----
8755 04:44:18.557079
8756 04:44:18.557184 ==
8757 04:44:18.560577 Dram Type= 6, Freq= 0, CH_1, rank 1
8758 04:44:18.563961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8759 04:44:18.564041 ==
8760 04:44:18.567251 [Gating] SW mode calibration
8761 04:44:18.573434 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8762 04:44:18.580642 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8763 04:44:18.583346 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 04:44:18.590266 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 04:44:18.593903 1 4 8 | B1->B0 | 3130 2323 | 1 0 | (1 1) (0 0)
8766 04:44:18.596735 1 4 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
8767 04:44:18.600059 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 04:44:18.607047 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 04:44:18.610337 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 04:44:18.613886 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 04:44:18.620160 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 04:44:18.623519 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 04:44:18.627134 1 5 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 0) (1 1)
8774 04:44:18.633352 1 5 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 0)
8775 04:44:18.636768 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 04:44:18.640175 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 04:44:18.646661 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 04:44:18.649980 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 04:44:18.653263 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 04:44:18.660056 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 04:44:18.663626 1 6 8 | B1->B0 | 4545 2424 | 0 0 | (0 0) (0 0)
8782 04:44:18.667050 1 6 12 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (1 1)
8783 04:44:18.673332 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 04:44:18.676744 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 04:44:18.680191 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 04:44:18.686488 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 04:44:18.690253 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 04:44:18.693362 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8789 04:44:18.699657 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8790 04:44:18.702985 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8791 04:44:18.706705 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8792 04:44:18.712836 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 04:44:18.716257 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 04:44:18.719911 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 04:44:18.726382 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 04:44:18.729912 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 04:44:18.733322 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 04:44:18.739593 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 04:44:18.743090 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 04:44:18.746441 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 04:44:18.752959 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 04:44:18.756098 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 04:44:18.759925 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 04:44:18.762611 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8805 04:44:18.769712 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8806 04:44:18.773254 Total UI for P1: 0, mck2ui 16
8807 04:44:18.776095 best dqsien dly found for B1: ( 1, 9, 4)
8808 04:44:18.779579 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8809 04:44:18.783075 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8810 04:44:18.789333 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 04:44:18.789412 Total UI for P1: 0, mck2ui 16
8812 04:44:18.796576 best dqsien dly found for B0: ( 1, 9, 12)
8813 04:44:18.799821 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8814 04:44:18.802509 best DQS1 dly(MCK, UI, PI) = (1, 9, 4)
8815 04:44:18.802628
8816 04:44:18.805891 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8817 04:44:18.809232 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 4)
8818 04:44:18.812587 [Gating] SW calibration Done
8819 04:44:18.812694 ==
8820 04:44:18.816229 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 04:44:18.819369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 04:44:18.819492 ==
8823 04:44:18.823014 RX Vref Scan: 0
8824 04:44:18.823112
8825 04:44:18.823213 RX Vref 0 -> 0, step: 1
8826 04:44:18.823304
8827 04:44:18.826070 RX Delay 0 -> 252, step: 8
8828 04:44:18.829656 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8829 04:44:18.836160 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8830 04:44:18.839098 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8831 04:44:18.842866 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8832 04:44:18.846532 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8833 04:44:18.849326 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8834 04:44:18.855830 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8835 04:44:18.859622 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8836 04:44:18.862475 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8837 04:44:18.865851 iDelay=208, Bit 9, Center 127 (72 ~ 183) 112
8838 04:44:18.869358 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8839 04:44:18.875956 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8840 04:44:18.879301 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8841 04:44:18.883153 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8842 04:44:18.886118 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8843 04:44:18.889701 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8844 04:44:18.892620 ==
8845 04:44:18.892697 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 04:44:18.899216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 04:44:18.899325 ==
8848 04:44:18.899418 DQS Delay:
8849 04:44:18.902921 DQS0 = 0, DQS1 = 0
8850 04:44:18.903012 DQM Delay:
8851 04:44:18.906537 DQM0 = 136, DQM1 = 134
8852 04:44:18.906622 DQ Delay:
8853 04:44:18.909733 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8854 04:44:18.913011 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8855 04:44:18.915842 DQ8 =119, DQ9 =127, DQ10 =135, DQ11 =127
8856 04:44:18.919203 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8857 04:44:18.919279
8858 04:44:18.919347
8859 04:44:18.919407 ==
8860 04:44:18.922853 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 04:44:18.929205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 04:44:18.929291 ==
8863 04:44:18.929358
8864 04:44:18.929418
8865 04:44:18.929477 TX Vref Scan disable
8866 04:44:18.932456 == TX Byte 0 ==
8867 04:44:18.936332 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8868 04:44:18.939245 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8869 04:44:18.943043 == TX Byte 1 ==
8870 04:44:18.945776 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8871 04:44:18.949181 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8872 04:44:18.952496 ==
8873 04:44:18.956638 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 04:44:18.959475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 04:44:18.959585 ==
8876 04:44:18.972564
8877 04:44:18.975976 TX Vref early break, caculate TX vref
8878 04:44:18.979392 TX Vref=16, minBit 2, minWin=22, winSum=381
8879 04:44:18.982786 TX Vref=18, minBit 2, minWin=22, winSum=390
8880 04:44:18.986122 TX Vref=20, minBit 0, minWin=23, winSum=398
8881 04:44:18.989055 TX Vref=22, minBit 2, minWin=24, winSum=407
8882 04:44:18.993004 TX Vref=24, minBit 1, minWin=25, winSum=415
8883 04:44:18.999657 TX Vref=26, minBit 2, minWin=25, winSum=423
8884 04:44:19.002411 TX Vref=28, minBit 0, minWin=25, winSum=427
8885 04:44:19.006050 TX Vref=30, minBit 0, minWin=25, winSum=424
8886 04:44:19.008981 TX Vref=32, minBit 0, minWin=25, winSum=414
8887 04:44:19.012464 TX Vref=34, minBit 0, minWin=24, winSum=407
8888 04:44:19.015952 TX Vref=36, minBit 0, minWin=24, winSum=400
8889 04:44:19.022545 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 28
8890 04:44:19.022642
8891 04:44:19.025930 Final TX Range 0 Vref 28
8892 04:44:19.026026
8893 04:44:19.026093 ==
8894 04:44:19.029521 Dram Type= 6, Freq= 0, CH_1, rank 1
8895 04:44:19.032235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8896 04:44:19.032346 ==
8897 04:44:19.032441
8898 04:44:19.032526
8899 04:44:19.035547 TX Vref Scan disable
8900 04:44:19.042324 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8901 04:44:19.042413 == TX Byte 0 ==
8902 04:44:19.045965 u2DelayCellOfst[0]=20 cells (6 PI)
8903 04:44:19.048743 u2DelayCellOfst[1]=13 cells (4 PI)
8904 04:44:19.052239 u2DelayCellOfst[2]=0 cells (0 PI)
8905 04:44:19.055611 u2DelayCellOfst[3]=10 cells (3 PI)
8906 04:44:19.059083 u2DelayCellOfst[4]=10 cells (3 PI)
8907 04:44:19.062378 u2DelayCellOfst[5]=20 cells (6 PI)
8908 04:44:19.065615 u2DelayCellOfst[6]=20 cells (6 PI)
8909 04:44:19.069007 u2DelayCellOfst[7]=6 cells (2 PI)
8910 04:44:19.071968 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8911 04:44:19.075581 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8912 04:44:19.079356 == TX Byte 1 ==
8913 04:44:19.082682 u2DelayCellOfst[8]=0 cells (0 PI)
8914 04:44:19.082762 u2DelayCellOfst[9]=0 cells (0 PI)
8915 04:44:19.085504 u2DelayCellOfst[10]=10 cells (3 PI)
8916 04:44:19.088986 u2DelayCellOfst[11]=0 cells (0 PI)
8917 04:44:19.092420 u2DelayCellOfst[12]=13 cells (4 PI)
8918 04:44:19.095855 u2DelayCellOfst[13]=13 cells (4 PI)
8919 04:44:19.099132 u2DelayCellOfst[14]=13 cells (4 PI)
8920 04:44:19.102351 u2DelayCellOfst[15]=16 cells (5 PI)
8921 04:44:19.105531 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8922 04:44:19.112841 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8923 04:44:19.112944 DramC Write-DBI on
8924 04:44:19.113012 ==
8925 04:44:19.115719 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 04:44:19.122401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 04:44:19.122488 ==
8928 04:44:19.122554
8929 04:44:19.122631
8930 04:44:19.122691 TX Vref Scan disable
8931 04:44:19.126044 == TX Byte 0 ==
8932 04:44:19.129497 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8933 04:44:19.132388 == TX Byte 1 ==
8934 04:44:19.135641 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8935 04:44:19.139137 DramC Write-DBI off
8936 04:44:19.139245
8937 04:44:19.139349 [DATLAT]
8938 04:44:19.139440 Freq=1600, CH1 RK1
8939 04:44:19.139539
8940 04:44:19.142613 DATLAT Default: 0xf
8941 04:44:19.142718 0, 0xFFFF, sum = 0
8942 04:44:19.145459 1, 0xFFFF, sum = 0
8943 04:44:19.149508 2, 0xFFFF, sum = 0
8944 04:44:19.149623 3, 0xFFFF, sum = 0
8945 04:44:19.152128 4, 0xFFFF, sum = 0
8946 04:44:19.152240 5, 0xFFFF, sum = 0
8947 04:44:19.155691 6, 0xFFFF, sum = 0
8948 04:44:19.155804 7, 0xFFFF, sum = 0
8949 04:44:19.159355 8, 0xFFFF, sum = 0
8950 04:44:19.159443 9, 0xFFFF, sum = 0
8951 04:44:19.162240 10, 0xFFFF, sum = 0
8952 04:44:19.162368 11, 0xFFFF, sum = 0
8953 04:44:19.165873 12, 0xFFFF, sum = 0
8954 04:44:19.165989 13, 0xFFFF, sum = 0
8955 04:44:19.169340 14, 0x0, sum = 1
8956 04:44:19.169426 15, 0x0, sum = 2
8957 04:44:19.172593 16, 0x0, sum = 3
8958 04:44:19.172700 17, 0x0, sum = 4
8959 04:44:19.175786 best_step = 15
8960 04:44:19.175898
8961 04:44:19.175991 ==
8962 04:44:19.178926 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 04:44:19.182381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 04:44:19.182496 ==
8965 04:44:19.182600 RX Vref Scan: 0
8966 04:44:19.182691
8967 04:44:19.185889 RX Vref 0 -> 0, step: 1
8968 04:44:19.185982
8969 04:44:19.189497 RX Delay 19 -> 252, step: 4
8970 04:44:19.192434 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8971 04:44:19.198994 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8972 04:44:19.202755 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8973 04:44:19.205623 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8974 04:44:19.209191 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8975 04:44:19.212456 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8976 04:44:19.215707 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8977 04:44:19.221961 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8978 04:44:19.225499 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8979 04:44:19.228965 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
8980 04:44:19.232406 iDelay=195, Bit 10, Center 134 (83 ~ 186) 104
8981 04:44:19.238733 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8982 04:44:19.242307 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8983 04:44:19.245208 iDelay=195, Bit 13, Center 136 (87 ~ 186) 100
8984 04:44:19.248590 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8985 04:44:19.251824 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8986 04:44:19.254936 ==
8987 04:44:19.258706 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 04:44:19.261970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 04:44:19.262056 ==
8990 04:44:19.262127 DQS Delay:
8991 04:44:19.265600 DQS0 = 0, DQS1 = 0
8992 04:44:19.265710 DQM Delay:
8993 04:44:19.268343 DQM0 = 134, DQM1 = 131
8994 04:44:19.268436 DQ Delay:
8995 04:44:19.271859 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
8996 04:44:19.275373 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8997 04:44:19.278109 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =126
8998 04:44:19.281699 DQ12 =140, DQ13 =136, DQ14 =136, DQ15 =140
8999 04:44:19.281811
9000 04:44:19.281903
9001 04:44:19.281998
9002 04:44:19.284934 [DramC_TX_OE_Calibration] TA2
9003 04:44:19.288226 Original DQ_B0 (3 6) =30, OEN = 27
9004 04:44:19.291731 Original DQ_B1 (3 6) =30, OEN = 27
9005 04:44:19.295009 24, 0x0, End_B0=24 End_B1=24
9006 04:44:19.298489 25, 0x0, End_B0=25 End_B1=25
9007 04:44:19.298612 26, 0x0, End_B0=26 End_B1=26
9008 04:44:19.301963 27, 0x0, End_B0=27 End_B1=27
9009 04:44:19.305381 28, 0x0, End_B0=28 End_B1=28
9010 04:44:19.308252 29, 0x0, End_B0=29 End_B1=29
9011 04:44:19.308366 30, 0x0, End_B0=30 End_B1=30
9012 04:44:19.311811 31, 0x4141, End_B0=30 End_B1=30
9013 04:44:19.314555 Byte0 end_step=30 best_step=27
9014 04:44:19.318111 Byte1 end_step=30 best_step=27
9015 04:44:19.321605 Byte0 TX OE(2T, 0.5T) = (3, 3)
9016 04:44:19.324913 Byte1 TX OE(2T, 0.5T) = (3, 3)
9017 04:44:19.325031
9018 04:44:19.325135
9019 04:44:19.331678 [DQSOSCAuto] RK1, (LSB)MR18= 0x2309, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9020 04:44:19.335068 CH1 RK1: MR19=303, MR18=2309
9021 04:44:19.341321 CH1_RK1: MR19=0x303, MR18=0x2309, DQSOSC=392, MR23=63, INC=24, DEC=16
9022 04:44:19.344996 [RxdqsGatingPostProcess] freq 1600
9023 04:44:19.351549 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9024 04:44:19.351679 best DQS0 dly(2T, 0.5T) = (1, 1)
9025 04:44:19.355005 best DQS1 dly(2T, 0.5T) = (1, 1)
9026 04:44:19.357740 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9027 04:44:19.361185 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9028 04:44:19.364641 best DQS0 dly(2T, 0.5T) = (1, 1)
9029 04:44:19.367767 best DQS1 dly(2T, 0.5T) = (1, 1)
9030 04:44:19.371565 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9031 04:44:19.374695 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9032 04:44:19.377582 Pre-setting of DQS Precalculation
9033 04:44:19.381135 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9034 04:44:19.391004 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9035 04:44:19.397637 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9036 04:44:19.397750
9037 04:44:19.397840
9038 04:44:19.400979 [Calibration Summary] 3200 Mbps
9039 04:44:19.401067 CH 0, Rank 0
9040 04:44:19.404580 SW Impedance : PASS
9041 04:44:19.404668 DUTY Scan : NO K
9042 04:44:19.408014 ZQ Calibration : PASS
9043 04:44:19.411421 Jitter Meter : NO K
9044 04:44:19.411510 CBT Training : PASS
9045 04:44:19.414261 Write leveling : PASS
9046 04:44:19.417807 RX DQS gating : PASS
9047 04:44:19.417889 RX DQ/DQS(RDDQC) : PASS
9048 04:44:19.421419 TX DQ/DQS : PASS
9049 04:44:19.421508 RX DATLAT : PASS
9050 04:44:19.424238 RX DQ/DQS(Engine): PASS
9051 04:44:19.427815 TX OE : PASS
9052 04:44:19.427901 All Pass.
9053 04:44:19.427965
9054 04:44:19.428031 CH 0, Rank 1
9055 04:44:19.431169 SW Impedance : PASS
9056 04:44:19.434268 DUTY Scan : NO K
9057 04:44:19.434380 ZQ Calibration : PASS
9058 04:44:19.437633 Jitter Meter : NO K
9059 04:44:19.440834 CBT Training : PASS
9060 04:44:19.440951 Write leveling : PASS
9061 04:44:19.444594 RX DQS gating : PASS
9062 04:44:19.447844 RX DQ/DQS(RDDQC) : PASS
9063 04:44:19.447926 TX DQ/DQS : PASS
9064 04:44:19.451291 RX DATLAT : PASS
9065 04:44:19.454301 RX DQ/DQS(Engine): PASS
9066 04:44:19.454434 TX OE : PASS
9067 04:44:19.457760 All Pass.
9068 04:44:19.457880
9069 04:44:19.457987 CH 1, Rank 0
9070 04:44:19.461190 SW Impedance : PASS
9071 04:44:19.461302 DUTY Scan : NO K
9072 04:44:19.464478 ZQ Calibration : PASS
9073 04:44:19.467880 Jitter Meter : NO K
9074 04:44:19.467985 CBT Training : PASS
9075 04:44:19.471343 Write leveling : PASS
9076 04:44:19.471418 RX DQS gating : PASS
9077 04:44:19.474189 RX DQ/DQS(RDDQC) : PASS
9078 04:44:19.478065 TX DQ/DQS : PASS
9079 04:44:19.478180 RX DATLAT : PASS
9080 04:44:19.481120 RX DQ/DQS(Engine): PASS
9081 04:44:19.484417 TX OE : PASS
9082 04:44:19.484548 All Pass.
9083 04:44:19.484658
9084 04:44:19.484782 CH 1, Rank 1
9085 04:44:19.487837 SW Impedance : PASS
9086 04:44:19.490646 DUTY Scan : NO K
9087 04:44:19.490754 ZQ Calibration : PASS
9088 04:44:19.494263 Jitter Meter : NO K
9089 04:44:19.497676 CBT Training : PASS
9090 04:44:19.497779 Write leveling : PASS
9091 04:44:19.500571 RX DQS gating : PASS
9092 04:44:19.504023 RX DQ/DQS(RDDQC) : PASS
9093 04:44:19.504138 TX DQ/DQS : PASS
9094 04:44:19.507362 RX DATLAT : PASS
9095 04:44:19.510803 RX DQ/DQS(Engine): PASS
9096 04:44:19.510912 TX OE : PASS
9097 04:44:19.511005 All Pass.
9098 04:44:19.514253
9099 04:44:19.514391 DramC Write-DBI on
9100 04:44:19.517552 PER_BANK_REFRESH: Hybrid Mode
9101 04:44:19.517633 TX_TRACKING: ON
9102 04:44:19.527503 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9103 04:44:19.533911 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9104 04:44:19.543923 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9105 04:44:19.547233 [FAST_K] Save calibration result to emmc
9106 04:44:19.550547 sync common calibartion params.
9107 04:44:19.550664 sync cbt_mode0:1, 1:1
9108 04:44:19.553744 dram_init: ddr_geometry: 2
9109 04:44:19.557508 dram_init: ddr_geometry: 2
9110 04:44:19.557640 dram_init: ddr_geometry: 2
9111 04:44:19.561029 0:dram_rank_size:100000000
9112 04:44:19.563869 1:dram_rank_size:100000000
9113 04:44:19.567330 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9114 04:44:19.570677 DFS_SHUFFLE_HW_MODE: ON
9115 04:44:19.574005 dramc_set_vcore_voltage set vcore to 725000
9116 04:44:19.577636 Read voltage for 1600, 0
9117 04:44:19.577755 Vio18 = 0
9118 04:44:19.580495 Vcore = 725000
9119 04:44:19.580582 Vdram = 0
9120 04:44:19.580648 Vddq = 0
9121 04:44:19.580708 Vmddr = 0
9122 04:44:19.583681 switch to 3200 Mbps bootup
9123 04:44:19.587369 [DramcRunTimeConfig]
9124 04:44:19.587442 PHYPLL
9125 04:44:19.590682 DPM_CONTROL_AFTERK: ON
9126 04:44:19.590767 PER_BANK_REFRESH: ON
9127 04:44:19.593808 REFRESH_OVERHEAD_REDUCTION: ON
9128 04:44:19.596853 CMD_PICG_NEW_MODE: OFF
9129 04:44:19.596932 XRTWTW_NEW_MODE: ON
9130 04:44:19.600432 XRTRTR_NEW_MODE: ON
9131 04:44:19.600509 TX_TRACKING: ON
9132 04:44:19.603996 RDSEL_TRACKING: OFF
9133 04:44:19.606934 DQS Precalculation for DVFS: ON
9134 04:44:19.607012 RX_TRACKING: OFF
9135 04:44:19.610306 HW_GATING DBG: ON
9136 04:44:19.610381 ZQCS_ENABLE_LP4: ON
9137 04:44:19.613655 RX_PICG_NEW_MODE: ON
9138 04:44:19.613732 TX_PICG_NEW_MODE: ON
9139 04:44:19.616960 ENABLE_RX_DCM_DPHY: ON
9140 04:44:19.620497 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9141 04:44:19.623912 DUMMY_READ_FOR_TRACKING: OFF
9142 04:44:19.624015 !!! SPM_CONTROL_AFTERK: OFF
9143 04:44:19.627147 !!! SPM could not control APHY
9144 04:44:19.630514 IMPEDANCE_TRACKING: ON
9145 04:44:19.630589 TEMP_SENSOR: ON
9146 04:44:19.633972 HW_SAVE_FOR_SR: OFF
9147 04:44:19.637398 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9148 04:44:19.640145 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9149 04:44:19.640260 Read ODT Tracking: ON
9150 04:44:19.643820 Refresh Rate DeBounce: ON
9151 04:44:19.646826 DFS_NO_QUEUE_FLUSH: ON
9152 04:44:19.650270 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9153 04:44:19.650347 ENABLE_DFS_RUNTIME_MRW: OFF
9154 04:44:19.653729 DDR_RESERVE_NEW_MODE: ON
9155 04:44:19.657122 MR_CBT_SWITCH_FREQ: ON
9156 04:44:19.657236 =========================
9157 04:44:19.676987 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9158 04:44:19.680258 dram_init: ddr_geometry: 2
9159 04:44:19.698322 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9160 04:44:19.701793 dram_init: dram init end (result: 0)
9161 04:44:19.708742 DRAM-K: Full calibration passed in 24472 msecs
9162 04:44:19.712293 MRC: failed to locate region type 0.
9163 04:44:19.712383 DRAM rank0 size:0x100000000,
9164 04:44:19.715199 DRAM rank1 size=0x100000000
9165 04:44:19.725152 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9166 04:44:19.732211 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9167 04:44:19.738362 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9168 04:44:19.745266 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9169 04:44:19.748749 DRAM rank0 size:0x100000000,
9170 04:44:19.751552 DRAM rank1 size=0x100000000
9171 04:44:19.751641 CBMEM:
9172 04:44:19.755048 IMD: root @ 0xfffff000 254 entries.
9173 04:44:19.758592 IMD: root @ 0xffffec00 62 entries.
9174 04:44:19.762138 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9175 04:44:19.765060 WARNING: RO_VPD is uninitialized or empty.
9176 04:44:19.771413 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9177 04:44:19.778580 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9178 04:44:19.791163 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9179 04:44:19.802814 BS: romstage times (exec / console): total (unknown) / 24002 ms
9180 04:44:19.802912
9181 04:44:19.803001
9182 04:44:19.812460 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9183 04:44:19.815663 ARM64: Exception handlers installed.
9184 04:44:19.818981 ARM64: Testing exception
9185 04:44:19.822537 ARM64: Done test exception
9186 04:44:19.822627 Enumerating buses...
9187 04:44:19.826139 Show all devs... Before device enumeration.
9188 04:44:19.828741 Root Device: enabled 1
9189 04:44:19.832681 CPU_CLUSTER: 0: enabled 1
9190 04:44:19.832798 CPU: 00: enabled 1
9191 04:44:19.835529 Compare with tree...
9192 04:44:19.835632 Root Device: enabled 1
9193 04:44:19.838923 CPU_CLUSTER: 0: enabled 1
9194 04:44:19.842392 CPU: 00: enabled 1
9195 04:44:19.842499 Root Device scanning...
9196 04:44:19.845731 scan_static_bus for Root Device
9197 04:44:19.848571 CPU_CLUSTER: 0 enabled
9198 04:44:19.851988 scan_static_bus for Root Device done
9199 04:44:19.856061 scan_bus: bus Root Device finished in 8 msecs
9200 04:44:19.856168 done
9201 04:44:19.862250 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9202 04:44:19.865158 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9203 04:44:19.872291 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9204 04:44:19.875120 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9205 04:44:19.878699 Allocating resources...
9206 04:44:19.882260 Reading resources...
9207 04:44:19.885615 Root Device read_resources bus 0 link: 0
9208 04:44:19.888983 DRAM rank0 size:0x100000000,
9209 04:44:19.889071 DRAM rank1 size=0x100000000
9210 04:44:19.891805 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9211 04:44:19.895348 CPU: 00 missing read_resources
9212 04:44:19.902274 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9213 04:44:19.904953 Root Device read_resources bus 0 link: 0 done
9214 04:44:19.905041 Done reading resources.
9215 04:44:19.911813 Show resources in subtree (Root Device)...After reading.
9216 04:44:19.915026 Root Device child on link 0 CPU_CLUSTER: 0
9217 04:44:19.918555 CPU_CLUSTER: 0 child on link 0 CPU: 00
9218 04:44:19.928585 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9219 04:44:19.928672 CPU: 00
9220 04:44:19.931966 Root Device assign_resources, bus 0 link: 0
9221 04:44:19.935660 CPU_CLUSTER: 0 missing set_resources
9222 04:44:19.941593 Root Device assign_resources, bus 0 link: 0 done
9223 04:44:19.941681 Done setting resources.
9224 04:44:19.948417 Show resources in subtree (Root Device)...After assigning values.
9225 04:44:19.951919 Root Device child on link 0 CPU_CLUSTER: 0
9226 04:44:19.955326 CPU_CLUSTER: 0 child on link 0 CPU: 00
9227 04:44:19.965243 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9228 04:44:19.965363 CPU: 00
9229 04:44:19.968712 Done allocating resources.
9230 04:44:19.974791 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9231 04:44:19.974903 Enabling resources...
9232 04:44:19.975006 done.
9233 04:44:19.981794 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9234 04:44:19.981878 Initializing devices...
9235 04:44:19.984648 Root Device init
9236 04:44:19.984754 init hardware done!
9237 04:44:19.987934 0x00000018: ctrlr->caps
9238 04:44:19.991452 52.000 MHz: ctrlr->f_max
9239 04:44:19.991561 0.400 MHz: ctrlr->f_min
9240 04:44:19.994670 0x40ff8080: ctrlr->voltages
9241 04:44:19.998247 sclk: 390625
9242 04:44:19.998328 Bus Width = 1
9243 04:44:19.998412 sclk: 390625
9244 04:44:20.001733 Bus Width = 1
9245 04:44:20.001813 Early init status = 3
9246 04:44:20.008128 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9247 04:44:20.011628 in-header: 03 fb 00 00 01 00 00 00
9248 04:44:20.011740 in-data: 01
9249 04:44:20.018408 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9250 04:44:20.021297 in-header: 03 fb 00 00 01 00 00 00
9251 04:44:20.024501 in-data: 01
9252 04:44:20.028363 [SSUSB] Setting up USB HOST controller...
9253 04:44:20.031582 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9254 04:44:20.031664 [SSUSB] phy power-on done.
9255 04:44:20.037755 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9256 04:44:20.041419 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9257 04:44:20.048235 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9258 04:44:20.055030 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9259 04:44:20.061323 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9260 04:44:20.067705 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9261 04:44:20.074796 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9262 04:44:20.077642 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9263 04:44:20.081206 SPM: binary array size = 0x9dc
9264 04:44:20.088302 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9265 04:44:20.094356 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9266 04:44:20.101192 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9267 04:44:20.104649 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9268 04:44:20.108128 configure_display: Starting display init
9269 04:44:20.144162 anx7625_power_on_init: Init interface.
9270 04:44:20.147621 anx7625_disable_pd_protocol: Disabled PD feature.
9271 04:44:20.150414 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9272 04:44:20.178373 anx7625_start_dp_work: Secure OCM version=00
9273 04:44:20.181739 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9274 04:44:20.196373 sp_tx_get_edid_block: EDID Block = 1
9275 04:44:20.299256 Extracted contents:
9276 04:44:20.302727 header: 00 ff ff ff ff ff ff 00
9277 04:44:20.305738 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9278 04:44:20.308855 version: 01 04
9279 04:44:20.312136 basic params: 95 1f 11 78 0a
9280 04:44:20.315458 chroma info: 76 90 94 55 54 90 27 21 50 54
9281 04:44:20.318874 established: 00 00 00
9282 04:44:20.325393 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9283 04:44:20.328934 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9284 04:44:20.335312 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9285 04:44:20.342351 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9286 04:44:20.348649 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9287 04:44:20.352179 extensions: 00
9288 04:44:20.352282 checksum: fb
9289 04:44:20.352361
9290 04:44:20.355580 Manufacturer: IVO Model 57d Serial Number 0
9291 04:44:20.359049 Made week 0 of 2020
9292 04:44:20.359156 EDID version: 1.4
9293 04:44:20.362339 Digital display
9294 04:44:20.365395 6 bits per primary color channel
9295 04:44:20.365478 DisplayPort interface
9296 04:44:20.368712 Maximum image size: 31 cm x 17 cm
9297 04:44:20.372080 Gamma: 220%
9298 04:44:20.372185 Check DPMS levels
9299 04:44:20.375500 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9300 04:44:20.379073 First detailed timing is preferred timing
9301 04:44:20.382423 Established timings supported:
9302 04:44:20.385209 Standard timings supported:
9303 04:44:20.388795 Detailed timings
9304 04:44:20.392181 Hex of detail: 383680a07038204018303c0035ae10000019
9305 04:44:20.395743 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9306 04:44:20.402050 0780 0798 07c8 0820 hborder 0
9307 04:44:20.405423 0438 043b 0447 0458 vborder 0
9308 04:44:20.408819 -hsync -vsync
9309 04:44:20.408935 Did detailed timing
9310 04:44:20.412004 Hex of detail: 000000000000000000000000000000000000
9311 04:44:20.416118 Manufacturer-specified data, tag 0
9312 04:44:20.422302 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9313 04:44:20.422388 ASCII string: InfoVision
9314 04:44:20.429153 Hex of detail: 000000fe00523134304e574635205248200a
9315 04:44:20.432441 ASCII string: R140NWF5 RH
9316 04:44:20.432549 Checksum
9317 04:44:20.432642 Checksum: 0xfb (valid)
9318 04:44:20.438731 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9319 04:44:20.441979 DSI data_rate: 832800000 bps
9320 04:44:20.445584 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9321 04:44:20.452188 anx7625_parse_edid: pixelclock(138800).
9322 04:44:20.455573 hactive(1920), hsync(48), hfp(24), hbp(88)
9323 04:44:20.458996 vactive(1080), vsync(12), vfp(3), vbp(17)
9324 04:44:20.461853 anx7625_dsi_config: config dsi.
9325 04:44:20.468150 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9326 04:44:20.481214 anx7625_dsi_config: success to config DSI
9327 04:44:20.484588 anx7625_dp_start: MIPI phy setup OK.
9328 04:44:20.487625 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9329 04:44:20.491071 mtk_ddp_mode_set invalid vrefresh 60
9330 04:44:20.494441 main_disp_path_setup
9331 04:44:20.494525 ovl_layer_smi_id_en
9332 04:44:20.498015 ovl_layer_smi_id_en
9333 04:44:20.498117 ccorr_config
9334 04:44:20.498208 aal_config
9335 04:44:20.500852 gamma_config
9336 04:44:20.500952 postmask_config
9337 04:44:20.504416 dither_config
9338 04:44:20.507979 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9339 04:44:20.514108 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9340 04:44:20.517336 Root Device init finished in 529 msecs
9341 04:44:20.521174 CPU_CLUSTER: 0 init
9342 04:44:20.527701 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9343 04:44:20.531182 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9344 04:44:20.533935 APU_MBOX 0x190000b0 = 0x10001
9345 04:44:20.537503 APU_MBOX 0x190001b0 = 0x10001
9346 04:44:20.540834 APU_MBOX 0x190005b0 = 0x10001
9347 04:44:20.544150 APU_MBOX 0x190006b0 = 0x10001
9348 04:44:20.547183 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9349 04:44:20.560387 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9350 04:44:20.572841 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9351 04:44:20.579059 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9352 04:44:20.591211 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9353 04:44:20.599773 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9354 04:44:20.603507 CPU_CLUSTER: 0 init finished in 81 msecs
9355 04:44:20.606852 Devices initialized
9356 04:44:20.610102 Show all devs... After init.
9357 04:44:20.610205 Root Device: enabled 1
9358 04:44:20.613622 CPU_CLUSTER: 0: enabled 1
9359 04:44:20.616356 CPU: 00: enabled 1
9360 04:44:20.619906 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9361 04:44:20.623399 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9362 04:44:20.626805 ELOG: NV offset 0x57f000 size 0x1000
9363 04:44:20.633087 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9364 04:44:20.639625 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9365 04:44:20.643025 ELOG: Event(17) added with size 13 at 2024-02-04 04:41:39 UTC
9366 04:44:20.649971 out: cmd=0x121: 03 db 21 01 00 00 00 00
9367 04:44:20.652656 in-header: 03 e5 00 00 2c 00 00 00
9368 04:44:20.662513 in-data: 7a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9369 04:44:20.669242 ELOG: Event(A1) added with size 10 at 2024-02-04 04:41:39 UTC
9370 04:44:20.676162 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9371 04:44:20.682265 ELOG: Event(A0) added with size 9 at 2024-02-04 04:41:39 UTC
9372 04:44:20.686366 elog_add_boot_reason: Logged dev mode boot
9373 04:44:20.692554 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9374 04:44:20.692652 Finalize devices...
9375 04:44:20.696002 Devices finalized
9376 04:44:20.698772 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9377 04:44:20.702257 Writing coreboot table at 0xffe64000
9378 04:44:20.705544 0. 000000000010a000-0000000000113fff: RAMSTAGE
9379 04:44:20.712303 1. 0000000040000000-00000000400fffff: RAM
9380 04:44:20.715567 2. 0000000040100000-000000004032afff: RAMSTAGE
9381 04:44:20.719003 3. 000000004032b000-00000000545fffff: RAM
9382 04:44:20.721746 4. 0000000054600000-000000005465ffff: BL31
9383 04:44:20.725362 5. 0000000054660000-00000000ffe63fff: RAM
9384 04:44:20.732012 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9385 04:44:20.735526 7. 0000000100000000-000000023fffffff: RAM
9386 04:44:20.738391 Passing 5 GPIOs to payload:
9387 04:44:20.741830 NAME | PORT | POLARITY | VALUE
9388 04:44:20.748772 EC in RW | 0x000000aa | low | undefined
9389 04:44:20.752201 EC interrupt | 0x00000005 | low | undefined
9390 04:44:20.755778 TPM interrupt | 0x000000ab | high | undefined
9391 04:44:20.761871 SD card detect | 0x00000011 | high | undefined
9392 04:44:20.765413 speaker enable | 0x00000093 | high | undefined
9393 04:44:20.768892 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9394 04:44:20.772324 in-header: 03 f9 00 00 02 00 00 00
9395 04:44:20.775190 in-data: 02 00
9396 04:44:20.778681 ADC[4]: Raw value=904726 ID=7
9397 04:44:20.778791 ADC[3]: Raw value=213441 ID=1
9398 04:44:20.782090 RAM Code: 0x71
9399 04:44:20.785356 ADC[6]: Raw value=75701 ID=0
9400 04:44:20.785459 ADC[5]: Raw value=213441 ID=1
9401 04:44:20.788625 SKU Code: 0x1
9402 04:44:20.792131 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b313
9403 04:44:20.795078 coreboot table: 964 bytes.
9404 04:44:20.798498 IMD ROOT 0. 0xfffff000 0x00001000
9405 04:44:20.801852 IMD SMALL 1. 0xffffe000 0x00001000
9406 04:44:20.805347 RO MCACHE 2. 0xffffc000 0x00001104
9407 04:44:20.808242 CONSOLE 3. 0xfff7c000 0x00080000
9408 04:44:20.811664 FMAP 4. 0xfff7b000 0x00000452
9409 04:44:20.814933 TIME STAMP 5. 0xfff7a000 0x00000910
9410 04:44:20.818101 VBOOT WORK 6. 0xfff66000 0x00014000
9411 04:44:20.822010 RAMOOPS 7. 0xffe66000 0x00100000
9412 04:44:20.824755 COREBOOT 8. 0xffe64000 0x00002000
9413 04:44:20.828604 IMD small region:
9414 04:44:20.831360 IMD ROOT 0. 0xffffec00 0x00000400
9415 04:44:20.834987 VPD 1. 0xffffeb80 0x0000006c
9416 04:44:20.838348 MMC STATUS 2. 0xffffeb60 0x00000004
9417 04:44:20.841753 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9418 04:44:20.844628 Probing TPM: done!
9419 04:44:20.848017 Connected to device vid:did:rid of 1ae0:0028:00
9420 04:44:20.859076 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9421 04:44:20.862562 Initialized TPM device CR50 revision 0
9422 04:44:20.865904 Checking cr50 for pending updates
9423 04:44:20.870058 Reading cr50 TPM mode
9424 04:44:20.878140 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9425 04:44:20.885148 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9426 04:44:20.925215 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9427 04:44:20.928567 Checking segment from ROM address 0x40100000
9428 04:44:20.931590 Checking segment from ROM address 0x4010001c
9429 04:44:20.938606 Loading segment from ROM address 0x40100000
9430 04:44:20.938713 code (compression=0)
9431 04:44:20.948177 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9432 04:44:20.955019 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9433 04:44:20.955138 it's not compressed!
9434 04:44:20.961939 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9435 04:44:20.965310 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9436 04:44:20.985931 Loading segment from ROM address 0x4010001c
9437 04:44:20.986054 Entry Point 0x80000000
9438 04:44:20.988712 Loaded segments
9439 04:44:20.992244 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9440 04:44:20.999234 Jumping to boot code at 0x80000000(0xffe64000)
9441 04:44:21.005667 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9442 04:44:21.011909 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9443 04:44:21.019702 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9444 04:44:21.023247 Checking segment from ROM address 0x40100000
9445 04:44:21.026822 Checking segment from ROM address 0x4010001c
9446 04:44:21.032920 Loading segment from ROM address 0x40100000
9447 04:44:21.033008 code (compression=1)
9448 04:44:21.040046 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9449 04:44:21.049618 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9450 04:44:21.049729 using LZMA
9451 04:44:21.058566 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9452 04:44:21.064973 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9453 04:44:21.068572 Loading segment from ROM address 0x4010001c
9454 04:44:21.068768 Entry Point 0x54601000
9455 04:44:21.071560 Loaded segments
9456 04:44:21.074816 NOTICE: MT8192 bl31_setup
9457 04:44:21.081796 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9458 04:44:21.085356 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9459 04:44:21.088436 WARNING: region 0:
9460 04:44:21.092424 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 04:44:21.092567 WARNING: region 1:
9462 04:44:21.098758 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9463 04:44:21.102356 WARNING: region 2:
9464 04:44:21.105837 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9465 04:44:21.108628 WARNING: region 3:
9466 04:44:21.112151 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9467 04:44:21.115743 WARNING: region 4:
9468 04:44:21.118666 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9469 04:44:21.122602 WARNING: region 5:
9470 04:44:21.125367 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 04:44:21.128892 WARNING: region 6:
9472 04:44:21.132296 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 04:44:21.132382 WARNING: region 7:
9474 04:44:21.139196 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 04:44:21.145583 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9476 04:44:21.148974 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9477 04:44:21.152075 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9478 04:44:21.159222 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9479 04:44:21.162691 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9480 04:44:21.166029 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9481 04:44:21.172307 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9482 04:44:21.175780 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9483 04:44:21.179216 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9484 04:44:21.185816 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9485 04:44:21.189022 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9486 04:44:21.192223 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9487 04:44:21.198984 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9488 04:44:21.202344 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9489 04:44:21.209624 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9490 04:44:21.212660 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9491 04:44:21.215716 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9492 04:44:21.222334 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9493 04:44:21.225926 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9494 04:44:21.229211 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9495 04:44:21.235646 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9496 04:44:21.238969 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9497 04:44:21.246049 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9498 04:44:21.249544 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9499 04:44:21.252968 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9500 04:44:21.259022 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9501 04:44:21.262376 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9502 04:44:21.269304 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9503 04:44:21.272426 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9504 04:44:21.275700 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9505 04:44:21.282656 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9506 04:44:21.286070 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9507 04:44:21.288812 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9508 04:44:21.295819 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9509 04:44:21.299053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9510 04:44:21.302454 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9511 04:44:21.305776 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9512 04:44:21.312194 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9513 04:44:21.315672 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9514 04:44:21.319068 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9515 04:44:21.322595 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9516 04:44:21.328870 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9517 04:44:21.332065 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9518 04:44:21.336166 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9519 04:44:21.338985 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9520 04:44:21.345522 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9521 04:44:21.348980 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9522 04:44:21.352389 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9523 04:44:21.358662 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9524 04:44:21.362136 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9525 04:44:21.365643 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9526 04:44:21.372367 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9527 04:44:21.375775 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9528 04:44:21.382346 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9529 04:44:21.385417 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9530 04:44:21.392619 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9531 04:44:21.396083 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9532 04:44:21.399479 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9533 04:44:21.405577 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9534 04:44:21.408807 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9535 04:44:21.415632 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9536 04:44:21.419011 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9537 04:44:21.425357 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9538 04:44:21.428880 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9539 04:44:21.435792 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9540 04:44:21.439105 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9541 04:44:21.442493 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9542 04:44:21.448680 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9543 04:44:21.452637 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9544 04:44:21.458873 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9545 04:44:21.461983 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9546 04:44:21.468679 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9547 04:44:21.472083 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9548 04:44:21.475465 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9549 04:44:21.482248 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9550 04:44:21.485722 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9551 04:44:21.491975 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9552 04:44:21.495893 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9553 04:44:21.502430 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9554 04:44:21.505328 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9555 04:44:21.509225 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9556 04:44:21.515307 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9557 04:44:21.519230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9558 04:44:21.525505 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9559 04:44:21.528964 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9560 04:44:21.535881 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9561 04:44:21.538632 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9562 04:44:21.541956 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9563 04:44:21.548778 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9564 04:44:21.552375 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9565 04:44:21.558621 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9566 04:44:21.562104 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9567 04:44:21.568736 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9568 04:44:21.571910 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9569 04:44:21.579058 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9570 04:44:21.582474 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9571 04:44:21.585716 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9572 04:44:21.588603 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9573 04:44:21.595549 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9574 04:44:21.599010 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9575 04:44:21.601843 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9576 04:44:21.608707 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9577 04:44:21.612029 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9578 04:44:21.615649 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9579 04:44:21.622073 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9580 04:44:21.625859 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9581 04:44:21.632411 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9582 04:44:21.635376 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9583 04:44:21.639189 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9584 04:44:21.646206 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9585 04:44:21.648834 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9586 04:44:21.655562 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9587 04:44:21.658964 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9588 04:44:21.662459 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9589 04:44:21.668753 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9590 04:44:21.672659 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9591 04:44:21.675344 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9592 04:44:21.682136 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9593 04:44:21.685365 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9594 04:44:21.689082 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9595 04:44:21.692256 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9596 04:44:21.698952 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9597 04:44:21.702501 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9598 04:44:21.705329 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9599 04:44:21.712416 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9600 04:44:21.715700 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9601 04:44:21.719187 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9602 04:44:21.725771 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9603 04:44:21.729078 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9604 04:44:21.732653 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9605 04:44:21.739214 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9606 04:44:21.742661 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9607 04:44:21.749149 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9608 04:44:21.752204 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9609 04:44:21.755517 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9610 04:44:21.762335 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9611 04:44:21.765569 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9612 04:44:21.772378 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9613 04:44:21.775708 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9614 04:44:21.779155 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9615 04:44:21.785523 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9616 04:44:21.788800 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9617 04:44:21.792856 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9618 04:44:21.798895 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9619 04:44:21.802548 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9620 04:44:21.809240 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9621 04:44:21.812861 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9622 04:44:21.815581 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9623 04:44:21.822527 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9624 04:44:21.825978 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9625 04:44:21.832646 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9626 04:44:21.836048 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9627 04:44:21.838903 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9628 04:44:21.845734 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9629 04:44:21.849036 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9630 04:44:21.852424 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9631 04:44:21.859022 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9632 04:44:21.862835 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9633 04:44:21.869047 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9634 04:44:21.872691 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9635 04:44:21.876002 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9636 04:44:21.882350 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9637 04:44:21.885752 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9638 04:44:21.892854 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9639 04:44:21.895621 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9640 04:44:21.899099 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9641 04:44:21.906177 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9642 04:44:21.909571 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9643 04:44:21.912436 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9644 04:44:21.919353 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9645 04:44:21.922264 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9646 04:44:21.929275 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9647 04:44:21.932737 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9648 04:44:21.935445 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9649 04:44:21.942579 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9650 04:44:21.945312 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9651 04:44:21.952245 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9652 04:44:21.955753 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9653 04:44:21.959058 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9654 04:44:21.965332 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9655 04:44:21.968720 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9656 04:44:21.975485 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9657 04:44:21.978741 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9658 04:44:21.981862 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9659 04:44:21.988585 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9660 04:44:21.991742 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9661 04:44:21.998536 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9662 04:44:22.001816 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9663 04:44:22.005238 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9664 04:44:22.011561 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9665 04:44:22.015104 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9666 04:44:22.022134 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9667 04:44:22.024918 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9668 04:44:22.028819 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9669 04:44:22.035261 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9670 04:44:22.038266 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9671 04:44:22.044698 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9672 04:44:22.048482 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9673 04:44:22.055013 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9674 04:44:22.057995 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9675 04:44:22.061245 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9676 04:44:22.068167 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9677 04:44:22.071698 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9678 04:44:22.078592 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9679 04:44:22.081374 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9680 04:44:22.088201 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9681 04:44:22.091445 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9682 04:44:22.094912 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9683 04:44:22.101136 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9684 04:44:22.105105 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9685 04:44:22.111429 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9686 04:44:22.114590 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9687 04:44:22.117818 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9688 04:44:22.124766 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9689 04:44:22.127669 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9690 04:44:22.134574 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9691 04:44:22.138067 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9692 04:44:22.144295 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9693 04:44:22.147883 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9694 04:44:22.151147 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9695 04:44:22.157920 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9696 04:44:22.160779 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9697 04:44:22.167924 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9698 04:44:22.171189 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9699 04:44:22.174425 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9700 04:44:22.181049 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9701 04:44:22.184365 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9702 04:44:22.191214 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9703 04:44:22.194029 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9704 04:44:22.197317 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9705 04:44:22.200968 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9706 04:44:22.207809 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9707 04:44:22.211332 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9708 04:44:22.214061 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9709 04:44:22.221182 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9710 04:44:22.224449 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9711 04:44:22.227679 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9712 04:44:22.234414 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9713 04:44:22.237205 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9714 04:44:22.240876 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9715 04:44:22.247843 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9716 04:44:22.250612 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9717 04:44:22.257538 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9718 04:44:22.260539 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9719 04:44:22.264371 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9720 04:44:22.270692 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9721 04:44:22.274325 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9722 04:44:22.277687 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9723 04:44:22.284237 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9724 04:44:22.287410 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9725 04:44:22.290990 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9726 04:44:22.297195 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9727 04:44:22.300515 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9728 04:44:22.303792 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9729 04:44:22.310572 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9730 04:44:22.314171 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9731 04:44:22.320304 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9732 04:44:22.323752 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9733 04:44:22.327111 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9734 04:44:22.333750 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9735 04:44:22.336951 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9736 04:44:22.340111 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9737 04:44:22.346885 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9738 04:44:22.350305 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9739 04:44:22.356731 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9740 04:44:22.360117 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9741 04:44:22.363546 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9742 04:44:22.369644 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9743 04:44:22.373572 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9744 04:44:22.376395 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9745 04:44:22.379918 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9746 04:44:22.386255 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9747 04:44:22.389694 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9748 04:44:22.393247 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9749 04:44:22.396113 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9750 04:44:22.403303 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9751 04:44:22.406675 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9752 04:44:22.409321 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9753 04:44:22.412775 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9754 04:44:22.419473 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9755 04:44:22.422636 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9756 04:44:22.425735 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9757 04:44:22.432555 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9758 04:44:22.435670 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9759 04:44:22.442624 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9760 04:44:22.445938 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9761 04:44:22.452607 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9762 04:44:22.455807 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9763 04:44:22.459204 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9764 04:44:22.465856 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9765 04:44:22.469310 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9766 04:44:22.475558 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9767 04:44:22.479007 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9768 04:44:22.482414 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9769 04:44:22.488629 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9770 04:44:22.492111 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9771 04:44:22.499133 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9772 04:44:22.502636 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9773 04:44:22.505305 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9774 04:44:22.512053 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9775 04:44:22.515565 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9776 04:44:22.521822 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9777 04:44:22.525300 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9778 04:44:22.532213 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9779 04:44:22.535072 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9780 04:44:22.538568 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9781 04:44:22.545215 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9782 04:44:22.549020 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9783 04:44:22.552378 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9784 04:44:22.558693 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9785 04:44:22.561655 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9786 04:44:22.568632 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9787 04:44:22.572050 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9788 04:44:22.575130 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9789 04:44:22.581725 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9790 04:44:22.585084 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9791 04:44:22.591846 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9792 04:44:22.595221 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9793 04:44:22.601908 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9794 04:44:22.605309 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9795 04:44:22.611643 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9796 04:44:22.615098 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9797 04:44:22.618600 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9798 04:44:22.624767 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9799 04:44:22.628227 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9800 04:44:22.631751 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9801 04:44:22.638074 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9802 04:44:22.641669 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9803 04:44:22.647988 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9804 04:44:22.651261 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9805 04:44:22.654766 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9806 04:44:22.661111 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9807 04:44:22.664688 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9808 04:44:22.670901 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9809 04:44:22.674353 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9810 04:44:22.680998 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9811 04:44:22.684344 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9812 04:44:22.687715 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9813 04:44:22.694150 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9814 04:44:22.697696 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9815 04:44:22.704034 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9816 04:44:22.707394 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9817 04:44:22.711037 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9818 04:44:22.717471 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9819 04:44:22.720761 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9820 04:44:22.727766 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9821 04:44:22.730672 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9822 04:44:22.734352 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9823 04:44:22.740585 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9824 04:44:22.744043 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9825 04:44:22.750945 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9826 04:44:22.754502 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9827 04:44:22.760870 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9828 04:44:22.764165 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9829 04:44:22.767378 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9830 04:44:22.773997 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9831 04:44:22.777587 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9832 04:44:22.783875 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9833 04:44:22.787340 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9834 04:44:22.794132 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9835 04:44:22.797876 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9836 04:44:22.800576 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9837 04:44:22.806895 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9838 04:44:22.810315 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9839 04:44:22.817150 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9840 04:44:22.820377 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9841 04:44:22.826961 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9842 04:44:22.830421 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9843 04:44:22.837338 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9844 04:44:22.840262 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9845 04:44:22.843816 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9846 04:44:22.850319 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9847 04:44:22.854035 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9848 04:44:22.860513 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9849 04:44:22.864054 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9850 04:44:22.870261 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9851 04:44:22.873646 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9852 04:44:22.877121 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9853 04:44:22.883454 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9854 04:44:22.886863 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9855 04:44:22.893813 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9856 04:44:22.897094 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9857 04:44:22.903622 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9858 04:44:22.907038 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9859 04:44:22.910604 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9860 04:44:22.916862 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9861 04:44:22.920281 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9862 04:44:22.927314 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9863 04:44:22.930080 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9864 04:44:22.937070 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9865 04:44:22.940268 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9866 04:44:22.943656 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9867 04:44:22.950371 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9868 04:44:22.953733 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9869 04:44:22.960112 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9870 04:44:22.963395 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9871 04:44:22.969960 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9872 04:44:22.973305 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9873 04:44:22.976872 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9874 04:44:22.983115 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9875 04:44:22.986808 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9876 04:44:22.993309 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9877 04:44:22.996547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9878 04:44:22.999815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9879 04:44:23.006786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9880 04:44:23.009678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9881 04:44:23.016592 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9882 04:44:23.020078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9883 04:44:23.026408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9884 04:44:23.029954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9885 04:44:23.036351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9886 04:44:23.039993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9887 04:44:23.046221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9888 04:44:23.049495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9889 04:44:23.056278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9890 04:44:23.059644 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9891 04:44:23.066482 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9892 04:44:23.069252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9893 04:44:23.076302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9894 04:44:23.079698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9895 04:44:23.086210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9896 04:44:23.089395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9897 04:44:23.096081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9898 04:44:23.099246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9899 04:44:23.106181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9900 04:44:23.109131 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9901 04:44:23.115712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9902 04:44:23.119545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9903 04:44:23.125968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9904 04:44:23.129530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9905 04:44:23.135770 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9906 04:44:23.139293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9907 04:44:23.145621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9908 04:44:23.149052 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9909 04:44:23.152538 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9910 04:44:23.156022 INFO: [APUAPC] vio 0
9911 04:44:23.162626 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9912 04:44:23.165623 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9913 04:44:23.169280 INFO: [APUAPC] D0_APC_0: 0x400510
9914 04:44:23.172013 INFO: [APUAPC] D0_APC_1: 0x0
9915 04:44:23.175463 INFO: [APUAPC] D0_APC_2: 0x1540
9916 04:44:23.178961 INFO: [APUAPC] D0_APC_3: 0x0
9917 04:44:23.182496 INFO: [APUAPC] D1_APC_0: 0xffffffff
9918 04:44:23.185325 INFO: [APUAPC] D1_APC_1: 0xffffffff
9919 04:44:23.188780 INFO: [APUAPC] D1_APC_2: 0x3fffff
9920 04:44:23.192164 INFO: [APUAPC] D1_APC_3: 0x0
9921 04:44:23.195579 INFO: [APUAPC] D2_APC_0: 0xffffffff
9922 04:44:23.198779 INFO: [APUAPC] D2_APC_1: 0xffffffff
9923 04:44:23.201898 INFO: [APUAPC] D2_APC_2: 0x3fffff
9924 04:44:23.205318 INFO: [APUAPC] D2_APC_3: 0x0
9925 04:44:23.208741 INFO: [APUAPC] D3_APC_0: 0xffffffff
9926 04:44:23.212079 INFO: [APUAPC] D3_APC_1: 0xffffffff
9927 04:44:23.215553 INFO: [APUAPC] D3_APC_2: 0x3fffff
9928 04:44:23.215642 INFO: [APUAPC] D3_APC_3: 0x0
9929 04:44:23.218998 INFO: [APUAPC] D4_APC_0: 0xffffffff
9930 04:44:23.225501 INFO: [APUAPC] D4_APC_1: 0xffffffff
9931 04:44:23.228634 INFO: [APUAPC] D4_APC_2: 0x3fffff
9932 04:44:23.228723 INFO: [APUAPC] D4_APC_3: 0x0
9933 04:44:23.231608 INFO: [APUAPC] D5_APC_0: 0xffffffff
9934 04:44:23.235183 INFO: [APUAPC] D5_APC_1: 0xffffffff
9935 04:44:23.238742 INFO: [APUAPC] D5_APC_2: 0x3fffff
9936 04:44:23.241463 INFO: [APUAPC] D5_APC_3: 0x0
9937 04:44:23.244804 INFO: [APUAPC] D6_APC_0: 0xffffffff
9938 04:44:23.248853 INFO: [APUAPC] D6_APC_1: 0xffffffff
9939 04:44:23.251696 INFO: [APUAPC] D6_APC_2: 0x3fffff
9940 04:44:23.255053 INFO: [APUAPC] D6_APC_3: 0x0
9941 04:44:23.258507 INFO: [APUAPC] D7_APC_0: 0xffffffff
9942 04:44:23.261917 INFO: [APUAPC] D7_APC_1: 0xffffffff
9943 04:44:23.265576 INFO: [APUAPC] D7_APC_2: 0x3fffff
9944 04:44:23.268350 INFO: [APUAPC] D7_APC_3: 0x0
9945 04:44:23.271590 INFO: [APUAPC] D8_APC_0: 0xffffffff
9946 04:44:23.274747 INFO: [APUAPC] D8_APC_1: 0xffffffff
9947 04:44:23.278013 INFO: [APUAPC] D8_APC_2: 0x3fffff
9948 04:44:23.281856 INFO: [APUAPC] D8_APC_3: 0x0
9949 04:44:23.284628 INFO: [APUAPC] D9_APC_0: 0xffffffff
9950 04:44:23.288045 INFO: [APUAPC] D9_APC_1: 0xffffffff
9951 04:44:23.291581 INFO: [APUAPC] D9_APC_2: 0x3fffff
9952 04:44:23.295012 INFO: [APUAPC] D9_APC_3: 0x0
9953 04:44:23.298558 INFO: [APUAPC] D10_APC_0: 0xffffffff
9954 04:44:23.301243 INFO: [APUAPC] D10_APC_1: 0xffffffff
9955 04:44:23.304554 INFO: [APUAPC] D10_APC_2: 0x3fffff
9956 04:44:23.308492 INFO: [APUAPC] D10_APC_3: 0x0
9957 04:44:23.311220 INFO: [APUAPC] D11_APC_0: 0xffffffff
9958 04:44:23.314590 INFO: [APUAPC] D11_APC_1: 0xffffffff
9959 04:44:23.317967 INFO: [APUAPC] D11_APC_2: 0x3fffff
9960 04:44:23.321607 INFO: [APUAPC] D11_APC_3: 0x0
9961 04:44:23.325049 INFO: [APUAPC] D12_APC_0: 0xffffffff
9962 04:44:23.327750 INFO: [APUAPC] D12_APC_1: 0xffffffff
9963 04:44:23.331226 INFO: [APUAPC] D12_APC_2: 0x3fffff
9964 04:44:23.334799 INFO: [APUAPC] D12_APC_3: 0x0
9965 04:44:23.338248 INFO: [APUAPC] D13_APC_0: 0xffffffff
9966 04:44:23.341613 INFO: [APUAPC] D13_APC_1: 0xffffffff
9967 04:44:23.344901 INFO: [APUAPC] D13_APC_2: 0x3fffff
9968 04:44:23.348336 INFO: [APUAPC] D13_APC_3: 0x0
9969 04:44:23.351440 INFO: [APUAPC] D14_APC_0: 0xffffffff
9970 04:44:23.354388 INFO: [APUAPC] D14_APC_1: 0xffffffff
9971 04:44:23.358150 INFO: [APUAPC] D14_APC_2: 0x3fffff
9972 04:44:23.361145 INFO: [APUAPC] D14_APC_3: 0x0
9973 04:44:23.364564 INFO: [APUAPC] D15_APC_0: 0xffffffff
9974 04:44:23.368122 INFO: [APUAPC] D15_APC_1: 0xffffffff
9975 04:44:23.371330 INFO: [APUAPC] D15_APC_2: 0x3fffff
9976 04:44:23.374582 INFO: [APUAPC] D15_APC_3: 0x0
9977 04:44:23.377895 INFO: [APUAPC] APC_CON: 0x4
9978 04:44:23.381272 INFO: [NOCDAPC] D0_APC_0: 0x0
9979 04:44:23.384722 INFO: [NOCDAPC] D0_APC_1: 0x0
9980 04:44:23.388036 INFO: [NOCDAPC] D1_APC_0: 0x0
9981 04:44:23.391186 INFO: [NOCDAPC] D1_APC_1: 0xfff
9982 04:44:23.391295 INFO: [NOCDAPC] D2_APC_0: 0x0
9983 04:44:23.394491 INFO: [NOCDAPC] D2_APC_1: 0xfff
9984 04:44:23.398036 INFO: [NOCDAPC] D3_APC_0: 0x0
9985 04:44:23.400884 INFO: [NOCDAPC] D3_APC_1: 0xfff
9986 04:44:23.404428 INFO: [NOCDAPC] D4_APC_0: 0x0
9987 04:44:23.407911 INFO: [NOCDAPC] D4_APC_1: 0xfff
9988 04:44:23.411511 INFO: [NOCDAPC] D5_APC_0: 0x0
9989 04:44:23.414034 INFO: [NOCDAPC] D5_APC_1: 0xfff
9990 04:44:23.417374 INFO: [NOCDAPC] D6_APC_0: 0x0
9991 04:44:23.421141 INFO: [NOCDAPC] D6_APC_1: 0xfff
9992 04:44:23.424336 INFO: [NOCDAPC] D7_APC_0: 0x0
9993 04:44:23.424432 INFO: [NOCDAPC] D7_APC_1: 0xfff
9994 04:44:23.427355 INFO: [NOCDAPC] D8_APC_0: 0x0
9995 04:44:23.431212 INFO: [NOCDAPC] D8_APC_1: 0xfff
9996 04:44:23.434679 INFO: [NOCDAPC] D9_APC_0: 0x0
9997 04:44:23.437527 INFO: [NOCDAPC] D9_APC_1: 0xfff
9998 04:44:23.441013 INFO: [NOCDAPC] D10_APC_0: 0x0
9999 04:44:23.444634 INFO: [NOCDAPC] D10_APC_1: 0xfff
10000 04:44:23.447967 INFO: [NOCDAPC] D11_APC_0: 0x0
10001 04:44:23.450790 INFO: [NOCDAPC] D11_APC_1: 0xfff
10002 04:44:23.454332 INFO: [NOCDAPC] D12_APC_0: 0x0
10003 04:44:23.457965 INFO: [NOCDAPC] D12_APC_1: 0xfff
10004 04:44:23.461312 INFO: [NOCDAPC] D13_APC_0: 0x0
10005 04:44:23.461423 INFO: [NOCDAPC] D13_APC_1: 0xfff
10006 04:44:23.464695 INFO: [NOCDAPC] D14_APC_0: 0x0
10007 04:44:23.467439 INFO: [NOCDAPC] D14_APC_1: 0xfff
10008 04:44:23.471313 INFO: [NOCDAPC] D15_APC_0: 0x0
10009 04:44:23.474540 INFO: [NOCDAPC] D15_APC_1: 0xfff
10010 04:44:23.477852 INFO: [NOCDAPC] APC_CON: 0x4
10011 04:44:23.481105 INFO: [APUAPC] set_apusys_apc done
10012 04:44:23.484276 INFO: [DEVAPC] devapc_init done
10013 04:44:23.487320 INFO: GICv3 without legacy support detected.
10014 04:44:23.494073 INFO: ARM GICv3 driver initialized in EL3
10015 04:44:23.497470 INFO: Maximum SPI INTID supported: 639
10016 04:44:23.500654 INFO: BL31: Initializing runtime services
10017 04:44:23.507151 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10018 04:44:23.507264 INFO: SPM: enable CPC mode
10019 04:44:23.513709 INFO: mcdi ready for mcusys-off-idle and system suspend
10020 04:44:23.517136 INFO: BL31: Preparing for EL3 exit to normal world
10021 04:44:23.524147 INFO: Entry point address = 0x80000000
10022 04:44:23.524254 INFO: SPSR = 0x8
10023 04:44:23.529697
10024 04:44:23.529774
10025 04:44:23.529838
10026 04:44:23.533046 Starting depthcharge on Spherion...
10027 04:44:23.533152
10028 04:44:23.533246 Wipe memory regions:
10029 04:44:23.533335
10030 04:44:23.534202 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10031 04:44:23.534336 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10032 04:44:23.534451 Setting prompt string to ['asurada:']
10033 04:44:23.534540 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10034 04:44:23.536836 [0x00000040000000, 0x00000054600000)
10035 04:44:23.659026
10036 04:44:23.659198 [0x00000054660000, 0x00000080000000)
10037 04:44:23.919619
10038 04:44:23.919794 [0x000000821a7280, 0x000000ffe64000)
10039 04:44:24.663904
10040 04:44:24.664080 [0x00000100000000, 0x00000240000000)
10041 04:44:26.553742
10042 04:44:26.556314 Initializing XHCI USB controller at 0x11200000.
10043 04:44:27.594435
10044 04:44:27.597952 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10045 04:44:27.598040
10046 04:44:27.598106
10047 04:44:27.598167
10048 04:44:27.598460 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10050 04:44:27.698775 asurada: tftpboot 192.168.201.1 12699833/tftp-deploy-7_8yyls4/kernel/image.itb 12699833/tftp-deploy-7_8yyls4/kernel/cmdline
10051 04:44:27.698962 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10052 04:44:27.699063 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10053 04:44:27.703918 tftpboot 192.168.201.1 12699833/tftp-deploy-7_8yyls4/kernel/image.itp-deploy-7_8yyls4/kernel/cmdline
10054 04:44:27.704005
10055 04:44:27.704071 Waiting for link
10056 04:44:27.864348
10057 04:44:27.864486 R8152: Initializing
10058 04:44:27.864557
10059 04:44:27.867742 Version 9 (ocp_data = 6010)
10060 04:44:27.867826
10061 04:44:27.870631 R8152: Done initializing
10062 04:44:27.870758
10063 04:44:27.870865 Adding net device
10064 04:44:29.816300
10065 04:44:29.816467 done.
10066 04:44:29.816539
10067 04:44:29.816602 MAC: 00:e0:4c:78:7a:aa
10068 04:44:29.816680
10069 04:44:29.819601 Sending DHCP discover... done.
10070 04:44:29.819713
10071 04:44:29.822814 Waiting for reply... done.
10072 04:44:29.822964
10073 04:44:29.826047 Sending DHCP request... done.
10074 04:44:29.826193
10075 04:44:29.826309 Waiting for reply... done.
10076 04:44:29.826403
10077 04:44:29.829645 My ip is 192.168.201.12
10078 04:44:29.829772
10079 04:44:29.833090 The DHCP server ip is 192.168.201.1
10080 04:44:29.833201
10081 04:44:29.836039 TFTP server IP predefined by user: 192.168.201.1
10082 04:44:29.836186
10083 04:44:29.842756 Bootfile predefined by user: 12699833/tftp-deploy-7_8yyls4/kernel/image.itb
10084 04:44:29.842906
10085 04:44:29.846059 Sending tftp read request... done.
10086 04:44:29.846148
10087 04:44:29.849728 Waiting for the transfer...
10088 04:44:29.849858
10089 04:44:30.105201 00000000 ################################################################
10090 04:44:30.105384
10091 04:44:30.357255 00080000 ################################################################
10092 04:44:30.357424
10093 04:44:30.604794 00100000 ################################################################
10094 04:44:30.604984
10095 04:44:30.850158 00180000 ################################################################
10096 04:44:30.850328
10097 04:44:31.096975 00200000 ################################################################
10098 04:44:31.097141
10099 04:44:31.345026 00280000 ################################################################
10100 04:44:31.345190
10101 04:44:31.595457 00300000 ################################################################
10102 04:44:31.595628
10103 04:44:31.844528 00380000 ################################################################
10104 04:44:31.844708
10105 04:44:32.094757 00400000 ################################################################
10106 04:44:32.094925
10107 04:44:32.349520 00480000 ################################################################
10108 04:44:32.349671
10109 04:44:32.608486 00500000 ################################################################
10110 04:44:32.608623
10111 04:44:32.870497 00580000 ################################################################
10112 04:44:32.870632
10113 04:44:33.130251 00600000 ################################################################
10114 04:44:33.130402
10115 04:44:33.386312 00680000 ################################################################
10116 04:44:33.386456
10117 04:44:33.638538 00700000 ################################################################
10118 04:44:33.638711
10119 04:44:33.891936 00780000 ################################################################
10120 04:44:33.892131
10121 04:44:34.149098 00800000 ################################################################
10122 04:44:34.149239
10123 04:44:34.404186 00880000 ################################################################
10124 04:44:34.404358
10125 04:44:34.656358 00900000 ################################################################
10126 04:44:34.656496
10127 04:44:34.907903 00980000 ################################################################
10128 04:44:34.908054
10129 04:44:35.159053 00a00000 ################################################################
10130 04:44:35.159197
10131 04:44:35.409363 00a80000 ################################################################
10132 04:44:35.409514
10133 04:44:35.662797 00b00000 ################################################################
10134 04:44:35.662947
10135 04:44:35.923867 00b80000 ################################################################
10136 04:44:35.924036
10137 04:44:36.182773 00c00000 ################################################################
10138 04:44:36.182905
10139 04:44:36.435848 00c80000 ################################################################
10140 04:44:36.436007
10141 04:44:36.689626 00d00000 ################################################################
10142 04:44:36.689762
10143 04:44:36.941873 00d80000 ################################################################
10144 04:44:36.942051
10145 04:44:37.196391 00e00000 ################################################################
10146 04:44:37.196561
10147 04:44:37.458792 00e80000 ################################################################
10148 04:44:37.458959
10149 04:44:37.715682 00f00000 ################################################################
10150 04:44:37.715859
10151 04:44:37.966723 00f80000 ################################################################
10152 04:44:37.966895
10153 04:44:38.216935 01000000 ################################################################
10154 04:44:38.217117
10155 04:44:38.469888 01080000 ################################################################
10156 04:44:38.470029
10157 04:44:38.719617 01100000 ################################################################
10158 04:44:38.719770
10159 04:44:38.970283 01180000 ################################################################
10160 04:44:38.970433
10161 04:44:39.215755 01200000 ################################################################
10162 04:44:39.215936
10163 04:44:39.473160 01280000 ################################################################
10164 04:44:39.473304
10165 04:44:39.721057 01300000 ################################################################
10166 04:44:39.721207
10167 04:44:39.983035 01380000 ################################################################
10168 04:44:39.983200
10169 04:44:40.237996 01400000 ################################################################
10170 04:44:40.238161
10171 04:44:40.491104 01480000 ################################################################
10172 04:44:40.491275
10173 04:44:40.745375 01500000 ################################################################
10174 04:44:40.745548
10175 04:44:40.993273 01580000 ################################################################
10176 04:44:40.993439
10177 04:44:41.250193 01600000 ################################################################
10178 04:44:41.250362
10179 04:44:41.496910 01680000 ################################################################
10180 04:44:41.497049
10181 04:44:41.749097 01700000 ################################################################
10182 04:44:41.749242
10183 04:44:41.998053 01780000 ################################################################
10184 04:44:41.998207
10185 04:44:42.250256 01800000 ################################################################
10186 04:44:42.250428
10187 04:44:42.500618 01880000 ################################################################
10188 04:44:42.500752
10189 04:44:42.751838 01900000 ################################################################
10190 04:44:42.752007
10191 04:44:43.006340 01980000 ################################################################
10192 04:44:43.006491
10193 04:44:43.280211 01a00000 ################################################################
10194 04:44:43.280404
10195 04:44:43.544138 01a80000 ################################################################
10196 04:44:43.544352
10197 04:44:43.798207 01b00000 ################################################################
10198 04:44:43.798380
10199 04:44:44.060598 01b80000 ################################################################
10200 04:44:44.060742
10201 04:44:44.313452 01c00000 ################################################################
10202 04:44:44.313584
10203 04:44:44.568614 01c80000 ################################################################
10204 04:44:44.568759
10205 04:44:44.826372 01d00000 ################################################################
10206 04:44:44.826513
10207 04:44:45.075270 01d80000 ################################################################
10208 04:44:45.075419
10209 04:44:45.326271 01e00000 ################################################################
10210 04:44:45.326406
10211 04:44:45.579082 01e80000 ################################################################
10212 04:44:45.579273
10213 04:44:45.836814 01f00000 ################################################################
10214 04:44:45.836963
10215 04:44:46.073957 01f80000 ########################################################### done.
10216 04:44:46.074087
10217 04:44:46.077619 The bootfile was 33508398 bytes long.
10218 04:44:46.077699
10219 04:44:46.080567 Sending tftp read request... done.
10220 04:44:46.080647
10221 04:44:46.084273 Waiting for the transfer...
10222 04:44:46.084375
10223 04:44:46.084442 00000000 # done.
10224 04:44:46.084506
10225 04:44:46.093911 Command line loaded dynamically from TFTP file: 12699833/tftp-deploy-7_8yyls4/kernel/cmdline
10226 04:44:46.093996
10227 04:44:46.107552 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10228 04:44:46.107668
10229 04:44:46.107764 Loading FIT.
10230 04:44:46.107854
10231 04:44:46.110668 Image ramdisk-1 has 21410577 bytes.
10232 04:44:46.110777
10233 04:44:46.114324 Image fdt-1 has 47278 bytes.
10234 04:44:46.114406
10235 04:44:46.117417 Image kernel-1 has 12048508 bytes.
10236 04:44:46.117524
10237 04:44:46.127138 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10238 04:44:46.127224
10239 04:44:46.143865 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10240 04:44:46.143978
10241 04:44:46.147378 Choosing best match conf-1 for compat google,spherion-rev2.
10242 04:44:46.153084
10243 04:44:46.157976 Connected to device vid:did:rid of 1ae0:0028:00
10244 04:44:46.165472
10245 04:44:46.168672 tpm_get_response: command 0x17b, return code 0x0
10246 04:44:46.168781
10247 04:44:46.171988 ec_init: CrosEC protocol v3 supported (256, 248)
10248 04:44:46.176208
10249 04:44:46.179630 tpm_cleanup: add release locality here.
10250 04:44:46.179792
10251 04:44:46.179888 Shutting down all USB controllers.
10252 04:44:46.183095
10253 04:44:46.183233 Removing current net device
10254 04:44:46.183342
10255 04:44:46.189594 Exiting depthcharge with code 4 at timestamp: 51928880
10256 04:44:46.189771
10257 04:44:46.192739 LZMA decompressing kernel-1 to 0x821a6718
10258 04:44:46.192890
10259 04:44:46.196281 LZMA decompressing kernel-1 to 0x40000000
10260 04:44:47.694885
10261 04:44:47.695047 jumping to kernel
10262 04:44:47.695576 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10263 04:44:47.695693 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10264 04:44:47.695802 Setting prompt string to ['Linux version [0-9]']
10265 04:44:47.695908 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10266 04:44:47.696004 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10267 04:44:47.776943
10268 04:44:47.780281 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10269 04:44:47.783801 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10270 04:44:47.783898 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10271 04:44:47.783969 Setting prompt string to []
10272 04:44:47.784048 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10273 04:44:47.784120 Using line separator: #'\n'#
10274 04:44:47.784179 No login prompt set.
10275 04:44:47.784240 Parsing kernel messages
10276 04:44:47.784324 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10277 04:44:47.784447 [login-action] Waiting for messages, (timeout 00:04:01)
10278 04:44:47.803608 [ 0.000000] Linux version 6.1.75-cip14-rt8 (KernelCI@build-j97480-arm64-gcc-10-defconfig-arm64-chromebook-6n26j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024
10279 04:44:47.806776 [ 0.000000] random: crng init done
10280 04:44:47.813197 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10281 04:44:47.817030 [ 0.000000] efi: UEFI not found.
10282 04:44:47.823229 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10283 04:44:47.829914 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10284 04:44:47.839669 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10285 04:44:47.849801 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10286 04:44:47.856029 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10287 04:44:47.862970 [ 0.000000] printk: bootconsole [mtk8250] enabled
10288 04:44:47.869932 [ 0.000000] NUMA: No NUMA configuration found
10289 04:44:47.876129 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10290 04:44:47.879530 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10291 04:44:47.882890 [ 0.000000] Zone ranges:
10292 04:44:47.889371 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10293 04:44:47.892849 [ 0.000000] DMA32 empty
10294 04:44:47.899553 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10295 04:44:47.902737 [ 0.000000] Movable zone start for each node
10296 04:44:47.905581 [ 0.000000] Early memory node ranges
10297 04:44:47.912559 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10298 04:44:47.919381 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10299 04:44:47.925876 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10300 04:44:47.932735 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10301 04:44:47.939349 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10302 04:44:47.945756 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10303 04:44:48.001566 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10304 04:44:48.008700 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10305 04:44:48.015027 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10306 04:44:48.018652 [ 0.000000] psci: probing for conduit method from DT.
10307 04:44:48.024879 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10308 04:44:48.028049 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10309 04:44:48.034769 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10310 04:44:48.038236 [ 0.000000] psci: SMC Calling Convention v1.2
10311 04:44:48.044768 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10312 04:44:48.048096 [ 0.000000] Detected VIPT I-cache on CPU0
10313 04:44:48.054975 [ 0.000000] CPU features: detected: GIC system register CPU interface
10314 04:44:48.061499 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10315 04:44:48.068259 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10316 04:44:48.074498 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10317 04:44:48.081285 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10318 04:44:48.088142 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10319 04:44:48.094525 [ 0.000000] alternatives: applying boot alternatives
10320 04:44:48.101390 [ 0.000000] Fallback order for Node 0: 0
10321 04:44:48.107768 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10322 04:44:48.111225 [ 0.000000] Policy zone: Normal
10323 04:44:48.124784 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10324 04:44:48.134639 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10325 04:44:48.145894 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10326 04:44:48.156040 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10327 04:44:48.162973 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10328 04:44:48.166264 <6>[ 0.000000] software IO TLB: area num 8.
10329 04:44:48.223013 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10330 04:44:48.372448 <6>[ 0.000000] Memory: 7946284K/8385536K available (18048K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 616K bss, 406484K reserved, 32768K cma-reserved)
10331 04:44:48.379053 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10332 04:44:48.385760 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10333 04:44:48.388888 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10334 04:44:48.395336 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10335 04:44:48.402197 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10336 04:44:48.405748 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10337 04:44:48.415433 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10338 04:44:48.422040 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10339 04:44:48.428834 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10340 04:44:48.435053 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10341 04:44:48.438618 <6>[ 0.000000] GICv3: 608 SPIs implemented
10342 04:44:48.442035 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10343 04:44:48.448239 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10344 04:44:48.451646 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10345 04:44:48.458342 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10346 04:44:48.471958 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10347 04:44:48.482026 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10348 04:44:48.491657 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10349 04:44:48.499062 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10350 04:44:48.512227 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10351 04:44:48.518623 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10352 04:44:48.524976 <6>[ 0.009179] Console: colour dummy device 80x25
10353 04:44:48.535578 <6>[ 0.013924] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10354 04:44:48.538536 <6>[ 0.024366] pid_max: default: 32768 minimum: 301
10355 04:44:48.545322 <6>[ 0.029238] LSM: Security Framework initializing
10356 04:44:48.551595 <6>[ 0.034176] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10357 04:44:48.561592 <6>[ 0.042038] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10358 04:44:48.568316 <6>[ 0.051455] cblist_init_generic: Setting adjustable number of callback queues.
10359 04:44:48.575083 <6>[ 0.058946] cblist_init_generic: Setting shift to 3 and lim to 1.
10360 04:44:48.585100 <6>[ 0.065323] cblist_init_generic: Setting adjustable number of callback queues.
10361 04:44:48.591244 <6>[ 0.072752] cblist_init_generic: Setting shift to 3 and lim to 1.
10362 04:44:48.594819 <6>[ 0.079192] rcu: Hierarchical SRCU implementation.
10363 04:44:48.601737 <6>[ 0.079194] rcu: Max phase no-delay instances is 1000.
10364 04:44:48.607943 <6>[ 0.079219] printk: bootconsole [mtk8250] printing thread started
10365 04:44:48.614728 <6>[ 0.097528] EFI services will not be available.
10366 04:44:48.618521 <6>[ 0.097730] smp: Bringing up secondary CPUs ...
10367 04:44:48.621636 <6>[ 0.098043] Detected VIPT I-cache on CPU1
10368 04:44:48.631856 <6>[ 0.098112] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10369 04:44:48.638050 <6>[ 0.098143] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10370 04:44:48.646833 <6>[ 0.126032] Detected VIPT I-cache on CPU2
10371 04:44:48.656614 <6>[ 0.126079] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10372 04:44:48.663796 <6>[ 0.126093] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10373 04:44:48.666626 <6>[ 0.126348] Detected VIPT I-cache on CPU3
10374 04:44:48.673877 <6>[ 0.126393] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10375 04:44:48.679808 <6>[ 0.126406] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10376 04:44:48.683195 <6>[ 0.126717] CPU features: detected: Spectre-v4
10377 04:44:48.689967 <6>[ 0.126723] CPU features: detected: Spectre-BHB
10378 04:44:48.693292 <6>[ 0.126729] Detected PIPT I-cache on CPU4
10379 04:44:48.699564 <6>[ 0.126787] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10380 04:44:48.706569 <6>[ 0.126803] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10381 04:44:48.712765 <6>[ 0.127091] Detected PIPT I-cache on CPU5
10382 04:44:48.719675 <6>[ 0.127151] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10383 04:44:48.726255 <6>[ 0.127167] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10384 04:44:48.729322 <6>[ 0.127438] Detected PIPT I-cache on CPU6
10385 04:44:48.736259 <6>[ 0.127502] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10386 04:44:48.742646 <6>[ 0.127518] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10387 04:44:48.752236 <6>[ 0.127806] Detected PIPT I-cache on CPU7
10388 04:44:48.758990 <6>[ 0.127871] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10389 04:44:48.765293 <6>[ 0.127887] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10390 04:44:48.768580 <6>[ 0.127933] smp: Brought up 1 node, 8 CPUs
10391 04:44:48.775173 <6>[ 0.127938] SMP: Total of 8 processors activated.
10392 04:44:48.778292 <6>[ 0.127940] CPU features: detected: 32-bit EL0 Support
10393 04:44:48.788728 <6>[ 0.127942] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10394 04:44:48.795217 <6>[ 0.127945] CPU features: detected: Common not Private translations
10395 04:44:48.801873 <6>[ 0.127946] CPU features: detected: CRC32 instructions
10396 04:44:48.805115 <6>[ 0.127949] CPU features: detected: RCpc load-acquire (LDAPR)
10397 04:44:48.811944 <6>[ 0.127950] CPU features: detected: LSE atomic instructions
10398 04:44:48.818003 <6>[ 0.127952] CPU features: detected: Privileged Access Never
10399 04:44:48.824905 <6>[ 0.127953] CPU features: detected: RAS Extension Support
10400 04:44:48.831701 <6>[ 0.127956] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10401 04:44:48.834944 <6>[ 0.128022] CPU: All CPU(s) started at EL2
10402 04:44:48.841674 <6>[ 0.128024] alternatives: applying system-wide alternatives
10403 04:44:48.845053 <6>[ 0.141099] devtmpfs: initialized
10404 04:44:48.854816 <6>[ 0.147335] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10405 04:44:48.861065 <6>[ 0.147350] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10406 04:44:48.886739 �'�ZY.'HL�LL�&$JKV�.'hN��1048576 bytes, linear)
10407 04:44:48.890115 <6>[ < 0.375092] printk: console [ttyS0] enabled
10408 04:44:48.899999 6>[ 0.247465] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10409 04:44:48.907407 <6>[ 0.375093] printk: console [ttyS0] printing thread started
10410 04:44:48.913975 <6>[ 0.375097] printk: bootconsole [mtk8250] disabled
10411 04:44:48.920782 <6>[ 0.388352] printk: bootconsole [mtk8250] printing thread stopped
10412 04:44:48.923872 <6>[ 0.389678] SuperH (H)SCI(F) driver initialized
10413 04:44:48.927262 <6>[ 0.390161] msm_serial: driver initialized
10414 04:44:48.937074 <6>[ 0.394823] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10415 04:44:48.947335 <6>[ 0.394852] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10416 04:44:48.957067 <6>[ 0.394881] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10417 04:44:48.968950 <6>[ 0.394910] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10418 04:44:48.975904 <6>[ 0.394931] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10419 04:44:48.991712 <6>[ 0.394959] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10420 04:44:48.992260 <6>[ 0.394987] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10421 04:44:48.996707 <6>[ 0.395117] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10422 04:44:49.006288 <6>[ 0.395147] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10423 04:44:49.014060 <6>[ 0.406204] loop: module loaded
10424 04:44:49.017251 <6>[ 0.408787] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10425 04:44:49.020459 <4>[ 0.425877] mtk-pmic-keys: Failed to locate of_node [id: -1]
10426 04:44:49.023718 <6>[ 0.426891] megasas: 07.719.03.00-rc1
10427 04:44:49.030513 <6>[ 0.436234] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10428 04:44:49.037171 <6>[ 0.438839] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10429 04:44:49.043717 <6>[ 0.450942] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10430 04:44:49.054016 <6>[ 0.504655] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10431 04:44:49.699709 <6>[ 1.180137] Freeing initrd memory: 20904K
10432 04:44:49.711153 <6>[ 1.191783] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10433 04:44:49.717923 <6>[ 1.196451] tun: Universal TUN/TAP device driver, 1.6
10434 04:44:49.721785 <6>[ 1.197230] thunder_xcv, ver 1.0
10435 04:44:49.725007 <6>[ 1.197247] thunder_bgx, ver 1.0
10436 04:44:49.728138 <6>[ 1.197260] nicpf, ver 1.0
10437 04:44:49.735276 <6>[ 1.198302] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10438 04:44:49.741570 <6>[ 1.198305] hns3: Copyright (c) 2017 Huawei Corporation.
10439 04:44:49.744975 <6>[ 1.198328] hclge is initializing
10440 04:44:49.748179 <6>[ 1.198343] e1000: Intel(R) PRO/1000 Network Driver
10441 04:44:49.754940 <6>[ 1.198345] e1000: Copyright (c) 1999-2006 Intel Corporation.
10442 04:44:49.763187 <6>[ 1.198365] e1000e: Intel(R) PRO/1000 Network Driver
10443 04:44:49.766154 <6>[ 1.198367] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10444 04:44:49.773211 <6>[ 1.198384] igb: Intel(R) Gigabit Ethernet Network Driver
10445 04:44:49.779906 <6>[ 1.198386] igb: Copyright (c) 2007-2014 Intel Corporation.
10446 04:44:49.783350 <6>[ 1.198400] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10447 04:44:49.790413 <6>[ 1.198402] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10448 04:44:49.793665 <6>[ 1.198691] sky2: driver version 1.30
10449 04:44:49.800034 <6>[ 1.199766] VFIO - User Level meta-driver version: 0.3
10450 04:44:49.806754 <6>[ 1.202575] usbcore: registered new interface driver usb-storage
10451 04:44:49.813329 <6>[ 1.202753] usbcore: registered new device driver onboard-usb-hub
10452 04:44:49.816750 <6>[ 1.205496] mt6397-rtc mt6359-rtc: registered as rtc0
10453 04:44:49.826496 <6>[ 1.205652] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-04T04:42:08 UTC (1707021728)
10454 04:44:49.833537 <6>[ 1.206261] i2c_dev: i2c /dev entries driver
10455 04:44:49.840095 <6>[ 1.213308] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10456 04:44:49.843556 <6>[ 1.228290] cpu cpu0: EM: created perf domain
10457 04:44:49.850030 <6>[ 1.228601] cpu cpu4: EM: created perf domain
10458 04:44:49.856628 <6>[ 1.230153] sdhci: Secure Digital Host Controller Interface driver
10459 04:44:49.859962 <6>[ 1.230154] sdhci: Copyright(c) Pierre Ossman
10460 04:44:49.866924 <6>[ 1.230513] Synopsys Designware Multimedia Card Interface Driver
10461 04:44:49.873366 <6>[ 1.230885] sdhci-pltfm: SDHCI platform and OF driver helper
10462 04:44:49.880228 <6>[ 1.233569] ledtrig-cpu: registered to indicate activity on CPUs
10463 04:44:49.882998 <6>[ 1.234165] mmc0: CQHCI version 5.10
10464 04:44:49.889592 <6>[ 1.234250] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10465 04:44:49.896159 <6>[ 1.234519] usbcore: registered new interface driver usbhid
10466 04:44:49.899678 <6>[ 1.234521] usbhid: USB HID core driver
10467 04:44:49.906164 <6>[ 1.234647] spi_master spi0: will run message pump with realtime priority
10468 04:44:49.919555 <6>[ 1.266196] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10469 04:44:49.932802 <6>[ 1.269126] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10470 04:44:49.936145 <6>[ 1.270049] cros-ec-spi spi0.0: Chrome EC device registered
10471 04:44:49.946084 <6>[ 1.287868] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10472 04:44:49.952762 <6>[ 1.291079] NET: Registered PF_PACKET protocol family
10473 04:44:49.956092 <6>[ 1.291207] 9pnet: Installing 9P2000 support
10474 04:44:49.962568 <5>[ 1.291250] Key type dns_resolver registered
10475 04:44:49.966278 <6>[ 1.291708] registered taskstats version 1
10476 04:44:49.969538 <5>[ 1.291730] Loading compiled-in X.509 certificates
10477 04:44:49.982693 <4>[ 1.315052] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10478 04:44:49.992584 <4>[ 1.315199] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10479 04:44:49.999508 <3>[ 1.315213] debugfs: File 'uA_load' in directory '/' already present!
10480 04:44:50.005687 <3>[ 1.315220] debugfs: File 'min_uV' in directory '/' already present!
10481 04:44:50.012425 <3>[ 1.315223] debugfs: File 'max_uV' in directory '/' already present!
10482 04:44:50.018982 <3>[ 1.315226] debugfs: File 'constraint_flags' in directory '/' already present!
10483 04:44:50.028887 <3>[ 1.317320] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10484 04:44:50.032131 <6>[ 1.324406] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10485 04:44:50.038979 <6>[ 1.325000] xhci-mtk 11200000.usb: xHCI Host Controller
10486 04:44:50.045397 <6>[ 1.325023] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10487 04:44:50.055527 <6>[ 1.325253] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10488 04:44:50.062305 <6>[ 1.325302] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10489 04:44:50.069163 <6>[ 1.325439] xhci-mtk 11200000.usb: xHCI Host Controller
10490 04:44:50.075992 <6>[ 1.325449] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10491 04:44:50.082408 <6>[ 1.325463] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10492 04:44:50.085963 <6>[ 1.325982] hub 1-0:1.0: USB hub found
10493 04:44:50.092200 <6>[ 1.326000] hub 1-0:1.0: 1 port detected
10494 04:44:50.099081 <6>[ 1.326183] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10495 04:44:50.102626 <6>[ 1.326404] hub 2-0:1.0: USB hub found
10496 04:44:50.108669 <6>[ 1.326418] hub 2-0:1.0: 1 port detected
10497 04:44:50.112045 <6>[ 1.329239] mtk-msdc 11f70000.mmc: Got CD GPIO
10498 04:44:50.115501 <6>[ 1.333604] mmc0: Command Queue Engine enabled
10499 04:44:50.122239 <6>[ 1.333626] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10500 04:44:50.128876 <6>[ 1.334352] mmcblk0: mmc0:0001 DA4128 116 GiB
10501 04:44:50.135243 <6>[ 1.338765] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10502 04:44:50.138756 <6>[ 1.339751] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10503 04:44:50.145282 <6>[ 1.340520] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10504 04:44:50.151668 <6>[ 1.341399] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10505 04:44:50.158727 <6>[ 1.345502] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10506 04:44:50.168423 <6>[ 1.345508] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10507 04:44:50.174997 <4>[ 1.345663] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10508 04:44:50.184888 <6>[ 1.346296] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10509 04:44:50.191770 <6>[ 1.346299] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10510 04:44:50.198216 <6>[ 1.346417] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10511 04:44:50.208085 <6>[ 1.346432] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10512 04:44:50.214927 <6>[ 1.346437] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10513 04:44:50.224584 <6>[ 1.346442] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10514 04:44:50.231569 <6>[ 1.348020] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10515 04:44:50.241468 <6>[ 1.348039] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10516 04:44:50.247732 <6>[ 1.348046] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10517 04:44:50.257984 <6>[ 1.348053] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10518 04:44:50.264262 <6>[ 1.348059] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10519 04:44:50.274329 <6>[ 1.348066] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10520 04:44:50.281232 <6>[ 1.348073] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10521 04:44:50.291125 <6>[ 1.348079] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10522 04:44:50.300955 <6>[ 1.348086] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10523 04:44:50.307822 <6>[ 1.348093] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10524 04:44:50.317397 <6>[ 1.348099] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10525 04:44:50.324113 <6>[ 1.348105] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10526 04:44:50.334343 <6>[ 1.348112] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10527 04:44:50.340767 <6>[ 1.348118] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10528 04:44:50.350617 <6>[ 1.348124] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10529 04:44:50.357582 <6>[ 1.348630] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10530 04:44:50.363798 <6>[ 1.349460] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10531 04:44:50.370518 <6>[ 1.350009] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10532 04:44:50.376875 <6>[ 1.350631] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10533 04:44:50.383547 <6>[ 1.351269] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10534 04:44:50.390280 <6>[ 1.351469] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10535 04:44:50.400018 <6>[ 1.351489] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10536 04:44:50.410216 <6>[ 1.351495] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10537 04:44:50.420107 <6>[ 1.351501] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10538 04:44:50.430284 <6>[ 1.351507] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10539 04:44:50.436934 <6>[ 1.351513] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10540 04:44:50.446581 <6>[ 1.351520] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10541 04:44:50.456587 <6>[ 1.351526] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10542 04:44:50.466289 <6>[ 1.351532] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10543 04:44:50.476765 <6>[ 1.351543] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10544 04:44:50.486591 <6>[ 1.351550] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10545 04:44:50.492974 <6>[ 1.352775] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10546 04:44:50.499823 <6>[ 1.707808] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10547 04:44:50.506084 <6>[ 1.734533] hub 2-1:1.0: USB hub found
10548 04:44:50.509542 <6>[ 1.734892] hub 2-1:1.0: 3 ports detected
10549 04:44:50.512874 <6>[ 1.737570] hub 2-1:1.0: USB hub found
10550 04:44:50.519606 <6>[ 1.737913] hub 2-1:1.0: 3 ports detected
10551 04:44:50.525663 <6>[ 1.855583] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10552 04:44:50.529073 <6>[ 2.008266] hub 1-1:1.0: USB hub found
10553 04:44:50.532619 <6>[ 2.008675] hub 1-1:1.0: 4 ports detected
10554 04:44:50.535967 <6>[ 2.012194] hub 1-1:1.0: USB hub found
10555 04:44:50.542711 <6>[ 2.012613] hub 1-1:1.0: 4 ports detected
10556 04:44:50.610692 <6>[ 2.088001] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10557 04:44:50.846643 <6>[ 2.323782] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10558 04:44:50.967381 <6>[ 2.451223] hub 1-1.4:1.0: USB hub found
10559 04:44:50.970652 <6>[ 2.451640] hub 1-1.4:1.0: 2 ports detected
10560 04:44:50.973793 <6>[ 2.455204] hub 1-1.4:1.0: USB hub found
10561 04:44:50.980231 <6>[ 2.455607] hub 1-1.4:1.0: 2 ports detected
10562 04:44:51.266604 <6>[ 2.743730] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10563 04:44:51.450983 <6>[ 2.927753] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10564 04:45:02.179417 <6>[ 13.664771] ALSA device list:
10565 04:45:02.185896 <6>[ 13.664793] No soundcards found.
10566 04:45:02.189631 <6>[ 13.669187] Freeing unused kernel memory: 8448K
10567 04:45:02.192864 <6>[ 13.669339] Run /init as init process
10568 04:45:02.211596 Starting syslogd: OK
10569 04:45:02.215586 Starting klogd: OK
10570 04:45:02.225263 Running sysctl: OK
10571 04:45:02.234738 Populating /dev using udev: <30>[ 13.718682] udevd[197]: starting version 3.2.9
10572 04:45:02.238234 <27>[ 13.721944] udevd[197]: specified user 'tss' unknown
10573 04:45:02.244934 <27>[ 13.721985] udevd[197]: specified group 'tss' unknown
10574 04:45:02.248261 <30>[ 13.722823] udevd[198]: starting eudev-3.2.9
10575 04:45:02.369775 <6>[ 13.849802] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10576 04:45:02.379721 <6>[ 13.849923] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10577 04:45:02.390184 <6>[ 13.849935] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10578 04:45:02.425602 <6>[ 13.906875] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10579 04:45:02.434478 <6>[ 13.919427] remoteproc remoteproc0: scp is available
10580 04:45:02.441457 <3>[ 13.920025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10581 04:45:02.451452 <3>[ 13.920034] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10582 04:45:02.457659 <3>[ 13.920039] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10583 04:45:02.464389 <6>[ 13.920143] remoteproc remoteproc0: powering up scp
10584 04:45:02.470786 <6>[ 13.920149] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10585 04:45:02.477402 <6>[ 13.920164] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10586 04:45:02.487916 <3>[ 13.920227] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10587 04:45:02.494503 <3>[ 13.920234] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10588 04:45:02.501115 <3>[ 13.920238] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10589 04:45:02.511072 <3>[ 13.920243] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10590 04:45:02.517544 <3>[ 13.920246] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10591 04:45:02.528180 <3>[ 13.920279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10592 04:45:02.534970 <3>[ 13.920306] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10593 04:45:02.542030 <3>[ 13.920309] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10594 04:45:02.552238 <3>[ 13.920312] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10595 04:45:02.558663 <3>[ 13.920338] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10596 04:45:02.568636 <3>[ 13.920341] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10597 04:45:02.575455 <3>[ 13.920343] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10598 04:45:02.581615 <3>[ 13.920346] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10599 04:45:02.591552 <3>[ 13.920348] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10600 04:45:02.598274 <3>[ 13.920372] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10601 04:45:02.608050 <4>[ 13.958175] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10602 04:45:02.615144 <4>[ 13.963155] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10603 04:45:02.621745 <6>[ 13.974080] usbcore: registered new device driver r8152-cfgselector
10604 04:45:02.627976 <6>[ 13.976852] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10605 04:45:02.631580 <6>[ 13.980906] mc: Linux media interface: v0.10
10606 04:45:02.638345 <6>[ 13.997760] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10607 04:45:02.644620 <6>[ 13.997770] pci_bus 0000:00: root bus resource [bus 00-ff]
10608 04:45:02.651328 <6>[ 13.997775] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10609 04:45:02.661693 <6>[ 13.997780] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10610 04:45:02.667783 <6>[ 13.997810] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10611 04:45:02.674831 <6>[ 13.997829] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10612 04:45:02.681014 <6>[ 13.997908] pci 0000:00:00.0: supports D1 D2
10613 04:45:02.687472 <6>[ 13.997911] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10614 04:45:02.694390 <6>[ 13.999618] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10615 04:45:02.701092 <6>[ 13.999843] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10616 04:45:02.711120 <6>[ 13.999877] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10617 04:45:02.717741 <6>[ 13.999898] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10618 04:45:02.724158 <6>[ 13.999916] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10619 04:45:02.727505 <6>[ 14.000038] pci 0000:01:00.0: supports D1 D2
10620 04:45:02.734224 <6>[ 14.000041] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10621 04:45:02.740589 <6>[ 14.001224] videodev: Linux video capture interface: v2.00
10622 04:45:02.750508 <4>[ 14.001371] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10623 04:45:02.753936 <4>[ 14.001371] Fallback method does not support PEC.
10624 04:45:02.760908 <6>[ 14.011581] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10625 04:45:02.770444 <6>[ 14.011641] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10626 04:45:02.777378 <6>[ 14.011645] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10627 04:45:02.787181 <6>[ 14.011655] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10628 04:45:02.793786 <6>[ 14.011669] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10629 04:45:02.803871 <6>[ 14.011682] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10630 04:45:02.807280 <6>[ 14.011696] pci 0000:00:00.0: PCI bridge to [bus 01]
10631 04:45:02.816722 <6>[ 14.011704] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10632 04:45:02.819994 <6>[ 14.011971] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10633 04:45:02.827081 <6>[ 14.012926] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10634 04:45:02.833411 <6>[ 14.014385] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10635 04:45:02.843262 <3>[ 14.018680] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10636 04:45:02.850119 <3>[ 14.041373] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10637 04:45:02.859665 <6>[ 14.045373] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10638 04:45:02.866305 <6>[ 14.045382] remoteproc remoteproc0: remote processor scp is now up
10639 04:45:02.872880 <6>[ 14.045387] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10640 04:45:02.883225 <6>[ 14.047946] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10641 04:45:02.892851 <6>[ 14.048280] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10642 04:45:02.899551 <6>[ 14.067831] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10643 04:45:02.909360 <6>[ 14.070994] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10644 04:45:02.919294 <4>[ 14.093405] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10645 04:45:02.925794 <4>[ 14.093430] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10646 04:45:02.936322 <5>[ 14.113393] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10647 04:45:02.942608 <6>[ 14.118440] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10648 04:45:02.945977 <6>[ 14.119644] Bluetooth: Core ver 2.22
10649 04:45:02.952499 <6>[ 14.119803] NET: Registered PF_BLUETOOTH protocol family
10650 04:45:02.958765 <6>[ 14.119808] Bluetooth: HCI device and connection manager initialized
10651 04:45:02.965591 <6>[ 14.119868] Bluetooth: HCI socket layer initialized
10652 04:45:02.968748 <6>[ 14.119893] Bluetooth: L2CAP socket layer initialized
10653 04:45:02.975587 <6>[ 14.119922] Bluetooth: SCO socket layer initialized
10654 04:45:02.982492 <6>[ 14.121891] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10655 04:45:02.989306 <6>[ 14.137087] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10656 04:45:02.995422 <5>[ 14.137904] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10657 04:45:03.005366 <5>[ 14.138143] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10658 04:45:03.015245 <4>[ 14.138212] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10659 04:45:03.018510 <6>[ 14.138227] cfg80211: failed to load regulatory.db
10660 04:45:03.032386 <6>[ 14.138399] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10661 04:45:03.038590 <6>[ 14.138567] usbcore: registered new interface driver uvcvideo
10662 04:45:03.041791 <6>[ 14.151609] r8152 2-1.3:1.0 eth0: v1.12.13
10663 04:45:03.048981 <6>[ 14.151740] usbcore: registered new interface driver r8152
10664 04:45:03.052034 <6>[ 14.178113] usbcore: registered new interface driver cdc_ether
10665 04:45:03.058184 <6>[ 14.178616] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10666 04:45:03.064880 <6>[ 14.179064] usbcore: registered new interface driver btusb
10667 04:45:03.075181 <4>[ 14.180130] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10668 04:45:03.081958 <3>[ 14.180140] Bluetooth: hci0: Failed to load firmware file (-2)
10669 04:45:03.088273 <3>[ 14.180145] Bluetooth: hci0: Failed to set up firmware (-2)
10670 04:45:03.098577 <4>[ 14.180149] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10671 04:45:03.105240 <6>[ 14.192398] usbcore: registered new interface driver r8153_ecm
10672 04:45:03.111780 <6>[ 14.233725] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10673 04:45:03.118822 <6>[ 14.233822] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10674 04:45:03.124791 <6>[ 14.251659] mt7921e 0000:01:00.0: ASIC revision: 79610010
10675 04:45:03.131476 <6>[ 14.346537] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10676 04:45:03.134809 <6>[ 14.346537]
10677 04:45:03.141383 <6>[ 14.606115] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10678 04:45:03.151040 done
10679 04:45:03.160735 Saving random seed: OK
10680 04:45:03.175266 Starting network: OK
10681 04:45:03.214375 Starting dropbear sshd: OK
10682 04:45:03.217557 <6>[ 14.700048] NET: Registered PF_INET6 protocol family
10683 04:45:03.225295 /bin/sh: can't a<6>[ 14.701382] Segment Routing with IPv6
10684 04:45:03.228694 <6>[ 14.701395] In-situ OAM (IOAM) with IPv6
10685 04:45:03.232078 ccess tty; job control turned off
10686 04:45:03.233253 Matched prompt #10: / #
10688 04:45:03.234459 Setting prompt string to ['/ #']
10689 04:45:03.234890 end: 2.2.5.1 login-action (duration 00:00:15) [common]
10691 04:45:03.235865 end: 2.2.5 auto-login-action (duration 00:00:16) [common]
10692 04:45:03.236342 start: 2.2.6 expect-shell-connection (timeout 00:03:46) [common]
10693 04:45:03.236717 Setting prompt string to ['/ #']
10694 04:45:03.237027 Forcing a shell prompt, looking for ['/ #']
10696 04:45:03.287829 / #
10697 04:45:03.288477 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10698 04:45:03.288905 Waiting using forced prompt support (timeout 00:02:30)
10699 04:45:03.294688
10700 04:45:03.295502 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10701 04:45:03.296037 start: 2.2.7 export-device-env (timeout 00:03:45) [common]
10702 04:45:03.296590 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10703 04:45:03.297067 end: 2.2 depthcharge-retry (duration 00:01:15) [common]
10704 04:45:03.297572 end: 2 depthcharge-action (duration 00:01:15) [common]
10705 04:45:03.298067 start: 3 lava-test-retry (timeout 00:01:00) [common]
10706 04:45:03.298515 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10707 04:45:03.298932 Using namespace: common
10709 04:45:03.400048 / # #
10710 04:45:03.400775 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10711 04:45:03.407023 #
10712 04:45:03.407824 Using /lava-12699833
10714 04:45:03.508921 / # export SHELL=/bin/sh
10715 04:45:03.515329 export SHELL=/bin/sh
10717 04:45:03.616931 / # . /lava-12699833/environment
10718 04:45:03.623288 . /lava-12699833/environment
10720 04:45:03.724835 / # /lava-12699833/bin/lava-test-runner /lava-12699833/0
10721 04:45:03.725332 Test shell timeout: 10s (minimum of the action and connection timeout)
10722 04:45:03.731716 /lava-12699833/bin/lava-test-runner /lava-12699833/0
10723 04:45:03.749286 + export 'TESTRUN_ID=0_dmesg'
10724 04:45:03.759879 + cd /lava-12699833/0/tests/0_dmesg<8>[ 15.240297] <LAVA_SIGNAL_STARTRUN 0_dmesg 12699833_1.5.2.3.1>
10725 04:45:03.760484
10726 04:45:03.760969 + cat uuid
10727 04:45:03.761756 Received signal: <STARTRUN> 0_dmesg 12699833_1.5.2.3.1
10728 04:45:03.762249 Starting test lava.0_dmesg (12699833_1.5.2.3.1)
10729 04:45:03.762766 Skipping test definition patterns.
10730 04:45:03.769609 + UUID=12699833_1.<8>[ 15.251398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10731 04:45:03.770460 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10733 04:45:03.779290 <8>[ 15.261160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10734 04:45:03.779879 5.2.3.1
10735 04:45:03.780664 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10737 04:45:03.782745 + set +x
10738 04:45:03.785994 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10739 04:45:03.786290 + set +x
10740 04:45:03.796135 <<8>[ 15.271769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10741 04:45:03.796677 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10743 04:45:03.799613 Received signal: <ENDRUN> 0_dmesg 12699833_1.5.2.3.1
10744 04:45:03.799931 Ending use of test pattern.
10745 04:45:03.800163 Ending test lava.0_dmesg (12699833_1.5.2.3.1), duration 0.04
10747 04:45:03.802610 <8>[ 15.272514] <LAVA_SIGNAL_ENDRUN 0_dmesg 12699833_1.5.2.3.1>
10748 04:45:03.802904 LAVA_TEST_RUNNER EXIT>
10749 04:45:03.966214 / # <6>[ 15.449299] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10750 04:45:32.543829 <6>[ 44.031991] vpu: disabling
10751 04:45:32.546848 <6>[ 44.032136] vproc2: disabling
10752 04:45:32.550538 <6>[ 44.032196] vproc1: disabling
10753 04:45:32.553702 <6>[ 44.032252] vaud18: disabling
10754 04:45:32.557347 <6>[ 44.032508] vsram_others: disabling
10755 04:45:32.560649 <6>[ 44.032695] va09: disabling
10756 04:45:32.563790 <6>[ 44.032774] vsram_md: disabling
10757 04:45:32.566927 <6>[ 44.032911] Vgpu: disabling
10759 04:46:03.298782 end: 3.1 lava-test-shell (duration 00:01:00) [common]
10761 04:46:03.299130 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
10763 04:46:03.299396 end: 3 lava-test-retry (duration 00:01:00) [common]
10765 04:46:03.299789 Cleaning after the job
10766 04:46:03.299936 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699833/tftp-deploy-7_8yyls4/ramdisk
10767 04:46:03.304214 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699833/tftp-deploy-7_8yyls4/kernel
10768 04:46:03.323036 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699833/tftp-deploy-7_8yyls4/dtb
10769 04:46:03.323342 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699833/tftp-deploy-7_8yyls4/modules
10770 04:46:03.333647 start: 5.1 power-off (timeout 00:00:30) [common]
10771 04:46:03.333965 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
10772 04:46:03.411942 >> Command sent successfully.
10773 04:46:03.414553 Returned 0 in 0 seconds
10774 04:46:03.514937 end: 5.1 power-off (duration 00:00:00) [common]
10776 04:46:03.515269 start: 5.2 read-feedback (timeout 00:10:00) [common]
10777 04:46:03.515543 Listened to connection for namespace 'common' for up to 1s
10778 04:46:04.516404 Finalising connection for namespace 'common'
10779 04:46:04.516685 Disconnecting from shell: Finalise
10780 04:46:04.617109 end: 5.2 read-feedback (duration 00:00:01) [common]
10781 04:46:04.617339 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12699833
10782 04:46:04.679700 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12699833
10783 04:46:04.679921 TestError: A test failed to run, look at the error message.