Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 13
- Kernel Errors: 30
1 04:44:15.233892 lava-dispatcher, installed at version: 2023.10
2 04:44:15.234108 start: 0 validate
3 04:44:15.234235 Start time: 2024-02-04 04:44:15.234227+00:00 (UTC)
4 04:44:15.234353 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:44:15.234482 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 04:44:15.503326 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:44:15.504084 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:44:15.773818 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:44:15.774663 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:44:16.043981 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:44:16.044759 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 04:44:16.313496 validate duration: 1.08
14 04:44:16.313779 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:44:16.313874 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:44:16.314001 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:44:16.314148 Not decompressing ramdisk as can be used compressed.
18 04:44:16.314233 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 04:44:16.314299 saving as /var/lib/lava/dispatcher/tmp/12699819/tftp-deploy-qmxjd096/ramdisk/rootfs.cpio.gz
20 04:44:16.314378 total size: 43284872 (41 MB)
21 04:44:16.315420 progress 0 % (0 MB)
22 04:44:16.326490 progress 5 % (2 MB)
23 04:44:16.337320 progress 10 % (4 MB)
24 04:44:16.348212 progress 15 % (6 MB)
25 04:44:16.359025 progress 20 % (8 MB)
26 04:44:16.369774 progress 25 % (10 MB)
27 04:44:16.380636 progress 30 % (12 MB)
28 04:44:16.391688 progress 35 % (14 MB)
29 04:44:16.402629 progress 40 % (16 MB)
30 04:44:16.413475 progress 45 % (18 MB)
31 04:44:16.424286 progress 50 % (20 MB)
32 04:44:16.435071 progress 55 % (22 MB)
33 04:44:16.445889 progress 60 % (24 MB)
34 04:44:16.456776 progress 65 % (26 MB)
35 04:44:16.467557 progress 70 % (28 MB)
36 04:44:16.478376 progress 75 % (30 MB)
37 04:44:16.489296 progress 80 % (33 MB)
38 04:44:16.500175 progress 85 % (35 MB)
39 04:44:16.511066 progress 90 % (37 MB)
40 04:44:16.521707 progress 95 % (39 MB)
41 04:44:16.532308 progress 100 % (41 MB)
42 04:44:16.532579 41 MB downloaded in 0.22 s (189.18 MB/s)
43 04:44:16.532740 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:44:16.532986 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:44:16.533074 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:44:16.533159 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:44:16.533299 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 04:44:16.533372 saving as /var/lib/lava/dispatcher/tmp/12699819/tftp-deploy-qmxjd096/kernel/Image
50 04:44:16.533434 total size: 51597824 (49 MB)
51 04:44:16.533496 No compression specified
52 04:44:16.534612 progress 0 % (0 MB)
53 04:44:16.547416 progress 5 % (2 MB)
54 04:44:16.560464 progress 10 % (4 MB)
55 04:44:16.573341 progress 15 % (7 MB)
56 04:44:16.586178 progress 20 % (9 MB)
57 04:44:16.599422 progress 25 % (12 MB)
58 04:44:16.612586 progress 30 % (14 MB)
59 04:44:16.625796 progress 35 % (17 MB)
60 04:44:16.638951 progress 40 % (19 MB)
61 04:44:16.652018 progress 45 % (22 MB)
62 04:44:16.665094 progress 50 % (24 MB)
63 04:44:16.678146 progress 55 % (27 MB)
64 04:44:16.691159 progress 60 % (29 MB)
65 04:44:16.704192 progress 65 % (32 MB)
66 04:44:16.717263 progress 70 % (34 MB)
67 04:44:16.730130 progress 75 % (36 MB)
68 04:44:16.743018 progress 80 % (39 MB)
69 04:44:16.755907 progress 85 % (41 MB)
70 04:44:16.768919 progress 90 % (44 MB)
71 04:44:16.781570 progress 95 % (46 MB)
72 04:44:16.794503 progress 100 % (49 MB)
73 04:44:16.794745 49 MB downloaded in 0.26 s (188.31 MB/s)
74 04:44:16.794904 end: 1.2.1 http-download (duration 00:00:00) [common]
76 04:44:16.795135 end: 1.2 download-retry (duration 00:00:00) [common]
77 04:44:16.795227 start: 1.3 download-retry (timeout 00:10:00) [common]
78 04:44:16.795314 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 04:44:16.795448 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 04:44:16.795519 saving as /var/lib/lava/dispatcher/tmp/12699819/tftp-deploy-qmxjd096/dtb/mt8192-asurada-spherion-r0.dtb
81 04:44:16.795580 total size: 47278 (0 MB)
82 04:44:16.795642 No compression specified
83 04:44:16.796733 progress 69 % (0 MB)
84 04:44:16.797001 progress 100 % (0 MB)
85 04:44:16.797155 0 MB downloaded in 0.00 s (28.67 MB/s)
86 04:44:16.797278 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:44:16.797502 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:44:16.797587 start: 1.4 download-retry (timeout 00:10:00) [common]
90 04:44:16.797670 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 04:44:16.797779 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 04:44:16.797850 saving as /var/lib/lava/dispatcher/tmp/12699819/tftp-deploy-qmxjd096/modules/modules.tar
93 04:44:16.797913 total size: 8633524 (8 MB)
94 04:44:16.798034 Using unxz to decompress xz
95 04:44:16.801699 progress 0 % (0 MB)
96 04:44:16.823338 progress 5 % (0 MB)
97 04:44:16.847654 progress 10 % (0 MB)
98 04:44:16.871777 progress 15 % (1 MB)
99 04:44:16.896312 progress 20 % (1 MB)
100 04:44:16.921472 progress 25 % (2 MB)
101 04:44:16.949600 progress 30 % (2 MB)
102 04:44:16.974466 progress 35 % (2 MB)
103 04:44:16.998636 progress 40 % (3 MB)
104 04:44:17.023533 progress 45 % (3 MB)
105 04:44:17.049374 progress 50 % (4 MB)
106 04:44:17.074508 progress 55 % (4 MB)
107 04:44:17.101998 progress 60 % (4 MB)
108 04:44:17.128263 progress 65 % (5 MB)
109 04:44:17.153786 progress 70 % (5 MB)
110 04:44:17.177775 progress 75 % (6 MB)
111 04:44:17.205696 progress 80 % (6 MB)
112 04:44:17.232061 progress 85 % (7 MB)
113 04:44:17.259536 progress 90 % (7 MB)
114 04:44:17.289906 progress 95 % (7 MB)
115 04:44:17.318484 progress 100 % (8 MB)
116 04:44:17.324121 8 MB downloaded in 0.53 s (15.65 MB/s)
117 04:44:17.324392 end: 1.4.1 http-download (duration 00:00:01) [common]
119 04:44:17.324686 end: 1.4 download-retry (duration 00:00:01) [common]
120 04:44:17.324798 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 04:44:17.324915 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 04:44:17.325010 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:44:17.325114 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 04:44:17.325393 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue
125 04:44:17.325565 makedir: /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin
126 04:44:17.325709 makedir: /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/tests
127 04:44:17.325847 makedir: /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/results
128 04:44:17.326010 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-add-keys
129 04:44:17.326175 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-add-sources
130 04:44:17.326320 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-background-process-start
131 04:44:17.326466 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-background-process-stop
132 04:44:17.326607 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-common-functions
133 04:44:17.326750 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-echo-ipv4
134 04:44:17.326918 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-install-packages
135 04:44:17.327085 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-installed-packages
136 04:44:17.327251 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-os-build
137 04:44:17.327419 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-probe-channel
138 04:44:17.327585 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-probe-ip
139 04:44:17.327747 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-target-ip
140 04:44:17.327891 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-target-mac
141 04:44:17.328058 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-target-storage
142 04:44:17.328229 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-test-case
143 04:44:17.328398 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-test-event
144 04:44:17.328564 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-test-feedback
145 04:44:17.328732 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-test-raise
146 04:44:17.328898 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-test-reference
147 04:44:17.329066 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-test-runner
148 04:44:17.329234 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-test-set
149 04:44:17.329402 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-test-shell
150 04:44:17.329569 Updating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-install-packages (oe)
151 04:44:17.329736 Updating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/bin/lava-installed-packages (oe)
152 04:44:17.329873 Creating /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/environment
153 04:44:17.330016 LAVA metadata
154 04:44:17.330125 - LAVA_JOB_ID=12699819
155 04:44:17.330231 - LAVA_DISPATCHER_IP=192.168.201.1
156 04:44:17.330387 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 04:44:17.330490 skipped lava-vland-overlay
158 04:44:17.330610 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 04:44:17.330734 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 04:44:17.330829 skipped lava-multinode-overlay
161 04:44:17.330952 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 04:44:17.331082 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 04:44:17.331173 Loading test definitions
164 04:44:17.331289 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 04:44:17.331403 Using /lava-12699819 at stage 0
166 04:44:17.331828 uuid=12699819_1.5.2.3.1 testdef=None
167 04:44:17.331954 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 04:44:17.332081 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 04:44:17.332804 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 04:44:17.333177 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 04:44:17.334036 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 04:44:17.334298 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 04:44:17.334918 runner path: /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/0/tests/0_igt-gpu-panfrost test_uuid 12699819_1.5.2.3.1
176 04:44:17.335087 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 04:44:17.335320 Creating lava-test-runner.conf files
179 04:44:17.335422 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12699819/lava-overlay-nm5nxuue/lava-12699819/0 for stage 0
180 04:44:17.335556 - 0_igt-gpu-panfrost
181 04:44:17.335693 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 04:44:17.335819 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 04:44:17.343305 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 04:44:17.343433 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 04:44:17.343538 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 04:44:17.343644 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 04:44:17.343749 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 04:44:18.634345 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 04:44:18.634730 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 04:44:18.634861 extracting modules file /var/lib/lava/dispatcher/tmp/12699819/tftp-deploy-qmxjd096/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699819/extract-overlay-ramdisk-2c7uiasp/ramdisk
191 04:44:18.845788 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 04:44:18.845967 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 04:44:18.846068 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699819/compress-overlay-p1nlq5fp/overlay-1.5.2.4.tar.gz to ramdisk
194 04:44:18.846139 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699819/compress-overlay-p1nlq5fp/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12699819/extract-overlay-ramdisk-2c7uiasp/ramdisk
195 04:44:18.852439 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 04:44:18.852553 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 04:44:18.852646 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 04:44:18.852736 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 04:44:18.852818 Building ramdisk /var/lib/lava/dispatcher/tmp/12699819/extract-overlay-ramdisk-2c7uiasp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12699819/extract-overlay-ramdisk-2c7uiasp/ramdisk
200 04:44:19.676645 >> 370014 blocks
201 04:44:25.380584 rename /var/lib/lava/dispatcher/tmp/12699819/extract-overlay-ramdisk-2c7uiasp/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12699819/tftp-deploy-qmxjd096/ramdisk/ramdisk.cpio.gz
202 04:44:25.381008 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 04:44:25.381121 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 04:44:25.381227 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 04:44:25.381336 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12699819/tftp-deploy-qmxjd096/kernel/Image'
206 04:44:37.842742 Returned 0 in 12 seconds
207 04:44:37.943396 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12699819/tftp-deploy-qmxjd096/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12699819/tftp-deploy-qmxjd096/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12699819/tftp-deploy-qmxjd096/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12699819/tftp-deploy-qmxjd096/kernel/image.itb
208 04:44:38.706052 output: FIT description: Kernel Image image with one or more FDT blobs
209 04:44:38.706431 output: Created: Sun Feb 4 04:44:38 2024
210 04:44:38.706510 output: Image 0 (kernel-1)
211 04:44:38.706577 output: Description:
212 04:44:38.706641 output: Created: Sun Feb 4 04:44:38 2024
213 04:44:38.706706 output: Type: Kernel Image
214 04:44:38.706766 output: Compression: lzma compressed
215 04:44:38.706826 output: Data Size: 12048508 Bytes = 11766.12 KiB = 11.49 MiB
216 04:44:38.706885 output: Architecture: AArch64
217 04:44:38.706942 output: OS: Linux
218 04:44:38.706997 output: Load Address: 0x00000000
219 04:44:38.707051 output: Entry Point: 0x00000000
220 04:44:38.707102 output: Hash algo: crc32
221 04:44:38.707157 output: Hash value: 3b31d50c
222 04:44:38.707212 output: Image 1 (fdt-1)
223 04:44:38.707266 output: Description: mt8192-asurada-spherion-r0
224 04:44:38.707319 output: Created: Sun Feb 4 04:44:38 2024
225 04:44:38.707372 output: Type: Flat Device Tree
226 04:44:38.707424 output: Compression: uncompressed
227 04:44:38.707476 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 04:44:38.707529 output: Architecture: AArch64
229 04:44:38.707582 output: Hash algo: crc32
230 04:44:38.707634 output: Hash value: cc4352de
231 04:44:38.707687 output: Image 2 (ramdisk-1)
232 04:44:38.707738 output: Description: unavailable
233 04:44:38.707791 output: Created: Sun Feb 4 04:44:38 2024
234 04:44:38.707843 output: Type: RAMDisk Image
235 04:44:38.707896 output: Compression: Unknown Compression
236 04:44:38.707948 output: Data Size: 56456229 Bytes = 55133.04 KiB = 53.84 MiB
237 04:44:38.708000 output: Architecture: AArch64
238 04:44:38.708052 output: OS: Linux
239 04:44:38.708104 output: Load Address: unavailable
240 04:44:38.708161 output: Entry Point: unavailable
241 04:44:38.708244 output: Hash algo: crc32
242 04:44:38.708326 output: Hash value: aca2e36e
243 04:44:38.708420 output: Default Configuration: 'conf-1'
244 04:44:38.708473 output: Configuration 0 (conf-1)
245 04:44:38.708526 output: Description: mt8192-asurada-spherion-r0
246 04:44:38.708578 output: Kernel: kernel-1
247 04:44:38.708630 output: Init Ramdisk: ramdisk-1
248 04:44:38.708682 output: FDT: fdt-1
249 04:44:38.708734 output: Loadables: kernel-1
250 04:44:38.708785 output:
251 04:44:38.708970 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 04:44:38.709065 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 04:44:38.709163 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 04:44:38.709252 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 04:44:38.709330 No LXC device requested
256 04:44:38.709407 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 04:44:38.709492 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 04:44:38.709568 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 04:44:38.709640 Checking files for TFTP limit of 4294967296 bytes.
260 04:44:38.710147 end: 1 tftp-deploy (duration 00:00:22) [common]
261 04:44:38.710296 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 04:44:38.710389 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 04:44:38.710510 substitutions:
264 04:44:38.710576 - {DTB}: 12699819/tftp-deploy-qmxjd096/dtb/mt8192-asurada-spherion-r0.dtb
265 04:44:38.710642 - {INITRD}: 12699819/tftp-deploy-qmxjd096/ramdisk/ramdisk.cpio.gz
266 04:44:38.710701 - {KERNEL}: 12699819/tftp-deploy-qmxjd096/kernel/Image
267 04:44:38.710758 - {LAVA_MAC}: None
268 04:44:38.710814 - {PRESEED_CONFIG}: None
269 04:44:38.710870 - {PRESEED_LOCAL}: None
270 04:44:38.710924 - {RAMDISK}: 12699819/tftp-deploy-qmxjd096/ramdisk/ramdisk.cpio.gz
271 04:44:38.710979 - {ROOT_PART}: None
272 04:44:38.711033 - {ROOT}: None
273 04:44:38.711087 - {SERVER_IP}: 192.168.201.1
274 04:44:38.711140 - {TEE}: None
275 04:44:38.711194 Parsed boot commands:
276 04:44:38.711247 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 04:44:38.711412 Parsed boot commands: tftpboot 192.168.201.1 12699819/tftp-deploy-qmxjd096/kernel/image.itb 12699819/tftp-deploy-qmxjd096/kernel/cmdline
278 04:44:38.711499 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 04:44:38.711582 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 04:44:38.711671 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 04:44:38.711758 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 04:44:38.711826 Not connected, no need to disconnect.
283 04:44:38.711899 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 04:44:38.711979 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 04:44:38.712043 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 04:44:38.715262 Setting prompt string to ['lava-test: # ']
287 04:44:38.715584 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 04:44:38.715689 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 04:44:38.715807 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 04:44:38.715926 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 04:44:38.716161 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 04:44:43.864009 >> Command sent successfully.
293 04:44:43.874633 Returned 0 in 5 seconds
294 04:44:43.975778 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 04:44:43.977288 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 04:44:43.977820 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 04:44:43.978347 Setting prompt string to 'Starting depthcharge on Spherion...'
299 04:44:43.978743 Changing prompt to 'Starting depthcharge on Spherion...'
300 04:44:43.979123 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 04:44:43.980435 [Enter `^Ec?' for help]
302 04:44:44.141114
303 04:44:44.141710
304 04:44:44.142188 F0: 102B 0000
305 04:44:44.142566
306 04:44:44.142903 F3: 1001 0000 [0200]
307 04:44:44.144434
308 04:44:44.145048 F3: 1001 0000
309 04:44:44.145446
310 04:44:44.145796 F7: 102D 0000
311 04:44:44.146200
312 04:44:44.147516 F1: 0000 0000
313 04:44:44.147997
314 04:44:44.148379 V0: 0000 0000 [0001]
315 04:44:44.148733
316 04:44:44.150827 00: 0007 8000
317 04:44:44.151326
318 04:44:44.151707 01: 0000 0000
319 04:44:44.152069
320 04:44:44.154023 BP: 0C00 0209 [0000]
321 04:44:44.154500
322 04:44:44.154877 G0: 1182 0000
323 04:44:44.155233
324 04:44:44.157720 EC: 0000 0021 [4000]
325 04:44:44.158234
326 04:44:44.158616 S7: 0000 0000 [0000]
327 04:44:44.158967
328 04:44:44.161185 CC: 0000 0000 [0001]
329 04:44:44.161886
330 04:44:44.162362 T0: 0000 0040 [010F]
331 04:44:44.162736
332 04:44:44.163084 Jump to BL
333 04:44:44.163420
334 04:44:44.187942
335 04:44:44.188475
336 04:44:44.188822
337 04:44:44.194862 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 04:44:44.198303 ARM64: Exception handlers installed.
339 04:44:44.202429 ARM64: Testing exception
340 04:44:44.205675 ARM64: Done test exception
341 04:44:44.212203 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 04:44:44.222500 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 04:44:44.229428 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 04:44:44.239366 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 04:44:44.246229 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 04:44:44.252926 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 04:44:44.264920 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 04:44:44.271159 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 04:44:44.290972 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 04:44:44.294034 WDT: Last reset was cold boot
351 04:44:44.297547 SPI1(PAD0) initialized at 2873684 Hz
352 04:44:44.300915 SPI5(PAD0) initialized at 992727 Hz
353 04:44:44.303969 VBOOT: Loading verstage.
354 04:44:44.310302 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 04:44:44.313900 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 04:44:44.317034 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 04:44:44.320285 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 04:44:44.328053 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 04:44:44.334178 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 04:44:44.345610 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 04:44:44.345725
362 04:44:44.345820
363 04:44:44.355818 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 04:44:44.359033 ARM64: Exception handlers installed.
365 04:44:44.362329 ARM64: Testing exception
366 04:44:44.362760 ARM64: Done test exception
367 04:44:44.369000 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 04:44:44.372732 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 04:44:44.386389 Probing TPM: . done!
370 04:44:44.386876 TPM ready after 0 ms
371 04:44:44.393391 Connected to device vid:did:rid of 1ae0:0028:00
372 04:44:44.400906 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 04:44:44.457326 Initialized TPM device CR50 revision 0
374 04:44:44.469592 tlcl_send_startup: Startup return code is 0
375 04:44:44.470124 TPM: setup succeeded
376 04:44:44.481166 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 04:44:44.489646 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 04:44:44.499830 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 04:44:44.509417 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 04:44:44.512519 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 04:44:44.520964 in-header: 03 07 00 00 08 00 00 00
382 04:44:44.524506 in-data: aa e4 47 04 13 02 00 00
383 04:44:44.528255 Chrome EC: UHEPI supported
384 04:44:44.535558 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 04:44:44.539239 in-header: 03 ad 00 00 08 00 00 00
386 04:44:44.542671 in-data: 00 20 20 08 00 00 00 00
387 04:44:44.543177 Phase 1
388 04:44:44.546470 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 04:44:44.553804 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 04:44:44.557806 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 04:44:44.561126 Recovery requested (1009000e)
392 04:44:44.569997 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 04:44:44.575638 tlcl_extend: response is 0
394 04:44:44.584989 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 04:44:44.590539 tlcl_extend: response is 0
396 04:44:44.597385 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 04:44:44.617981 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 04:44:44.624989 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 04:44:44.625442
400 04:44:44.625782
401 04:44:44.635083 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 04:44:44.638378 ARM64: Exception handlers installed.
403 04:44:44.638808 ARM64: Testing exception
404 04:44:44.641813 ARM64: Done test exception
405 04:44:44.663494 pmic_efuse_setting: Set efuses in 11 msecs
406 04:44:44.666844 pmwrap_interface_init: Select PMIF_VLD_RDY
407 04:44:44.673267 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 04:44:44.677379 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 04:44:44.680629 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 04:44:44.687253 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 04:44:44.691064 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 04:44:44.694790 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 04:44:44.701856 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 04:44:44.705926 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 04:44:44.709362 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 04:44:44.716623 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 04:44:44.720607 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 04:44:44.724089 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 04:44:44.727376 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 04:44:44.734277 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 04:44:44.741304 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 04:44:44.748539 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 04:44:44.752544 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 04:44:44.759260 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 04:44:44.763288 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 04:44:44.769759 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 04:44:44.773177 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 04:44:44.780466 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 04:44:44.787027 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 04:44:44.790598 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 04:44:44.797304 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 04:44:44.803431 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 04:44:44.807289 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 04:44:44.813658 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 04:44:44.817175 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 04:44:44.820527 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 04:44:44.827008 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 04:44:44.830349 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 04:44:44.836968 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 04:44:44.840455 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 04:44:44.847155 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 04:44:44.850409 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 04:44:44.857211 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 04:44:44.860767 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 04:44:44.867325 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 04:44:44.870783 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 04:44:44.874268 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 04:44:44.878455 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 04:44:44.884806 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 04:44:44.888214 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 04:44:44.891875 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 04:44:44.898470 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 04:44:44.901833 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 04:44:44.905130 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 04:44:44.908767 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 04:44:44.915377 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 04:44:44.918627 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 04:44:44.925122 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 04:44:44.935288 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 04:44:44.938670 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 04:44:44.948723 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 04:44:44.955640 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 04:44:44.958883 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 04:44:44.965470 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 04:44:44.968532 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 04:44:44.976000 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x18
467 04:44:44.982405 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 04:44:44.985591 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 04:44:44.989427 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 04:44:45.000009 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 04:44:45.009657 [RTC]rtc_get_frequency_meter,154: input=23, output=957
472 04:44:45.019017 [RTC]rtc_get_frequency_meter,154: input=19, output=865
473 04:44:45.028706 [RTC]rtc_get_frequency_meter,154: input=17, output=816
474 04:44:45.038574 [RTC]rtc_get_frequency_meter,154: input=16, output=795
475 04:44:45.041498 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 04:44:45.048618 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 04:44:45.051576 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 04:44:45.054916 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 04:44:45.058463 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 04:44:45.061741 ADC[4]: Raw value=903245 ID=7
481 04:44:45.064933 ADC[3]: Raw value=213179 ID=1
482 04:44:45.065507 RAM Code: 0x71
483 04:44:45.071751 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 04:44:45.075242 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 04:44:45.086116 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 04:44:45.093172 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 04:44:45.093720 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 04:44:45.097006 in-header: 03 07 00 00 08 00 00 00
489 04:44:45.100764 in-data: aa e4 47 04 13 02 00 00
490 04:44:45.104684 Chrome EC: UHEPI supported
491 04:44:45.111859 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 04:44:45.115428 in-header: 03 ed 00 00 08 00 00 00
493 04:44:45.119305 in-data: 80 20 60 08 00 00 00 00
494 04:44:45.119874 MRC: failed to locate region type 0.
495 04:44:45.126620 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 04:44:45.130719 DRAM-K: Running full calibration
497 04:44:45.138319 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 04:44:45.138894 header.status = 0x0
499 04:44:45.141124 header.version = 0x6 (expected: 0x6)
500 04:44:45.144735 header.size = 0xd00 (expected: 0xd00)
501 04:44:45.148210 header.flags = 0x0
502 04:44:45.151162 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 04:44:45.170487 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
504 04:44:45.177101 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 04:44:45.180615 dram_init: ddr_geometry: 2
506 04:44:45.183496 [EMI] MDL number = 2
507 04:44:45.183992 [EMI] Get MDL freq = 0
508 04:44:45.187119 dram_init: ddr_type: 0
509 04:44:45.187555 is_discrete_lpddr4: 1
510 04:44:45.190576 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 04:44:45.191009
512 04:44:45.191352
513 04:44:45.193879 [Bian_co] ETT version 0.0.0.1
514 04:44:45.201596 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 04:44:45.202160
516 04:44:45.202555 dramc_set_vcore_voltage set vcore to 650000
517 04:44:45.204916 Read voltage for 800, 4
518 04:44:45.205353 Vio18 = 0
519 04:44:45.208734 Vcore = 650000
520 04:44:45.209170 Vdram = 0
521 04:44:45.209518 Vddq = 0
522 04:44:45.209844 Vmddr = 0
523 04:44:45.212682 dram_init: config_dvfs: 1
524 04:44:45.216470 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 04:44:45.223428 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 04:44:45.226884 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 04:44:45.229851 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 04:44:45.233338 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 04:44:45.240278 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 04:44:45.240739 MEM_TYPE=3, freq_sel=18
531 04:44:45.243284 sv_algorithm_assistance_LP4_1600
532 04:44:45.246750 ============ PULL DRAM RESETB DOWN ============
533 04:44:45.253745 ========== PULL DRAM RESETB DOWN end =========
534 04:44:45.257209 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 04:44:45.260551 ===================================
536 04:44:45.263464 LPDDR4 DRAM CONFIGURATION
537 04:44:45.266956 ===================================
538 04:44:45.267568 EX_ROW_EN[0] = 0x0
539 04:44:45.270102 EX_ROW_EN[1] = 0x0
540 04:44:45.270582 LP4Y_EN = 0x0
541 04:44:45.273659 WORK_FSP = 0x0
542 04:44:45.274294 WL = 0x2
543 04:44:45.277232 RL = 0x2
544 04:44:45.277812 BL = 0x2
545 04:44:45.280012 RPST = 0x0
546 04:44:45.280504 RD_PRE = 0x0
547 04:44:45.283875 WR_PRE = 0x1
548 04:44:45.284353 WR_PST = 0x0
549 04:44:45.286740 DBI_WR = 0x0
550 04:44:45.290596 DBI_RD = 0x0
551 04:44:45.291176 OTF = 0x1
552 04:44:45.293739 ===================================
553 04:44:45.296726 ===================================
554 04:44:45.297206 ANA top config
555 04:44:45.300437 ===================================
556 04:44:45.303777 DLL_ASYNC_EN = 0
557 04:44:45.307176 ALL_SLAVE_EN = 1
558 04:44:45.310183 NEW_RANK_MODE = 1
559 04:44:45.310683 DLL_IDLE_MODE = 1
560 04:44:45.313717 LP45_APHY_COMB_EN = 1
561 04:44:45.316674 TX_ODT_DIS = 1
562 04:44:45.320307 NEW_8X_MODE = 1
563 04:44:45.323390 ===================================
564 04:44:45.327264 ===================================
565 04:44:45.330491 data_rate = 1600
566 04:44:45.331040 CKR = 1
567 04:44:45.333693 DQ_P2S_RATIO = 8
568 04:44:45.337272 ===================================
569 04:44:45.340268 CA_P2S_RATIO = 8
570 04:44:45.343720 DQ_CA_OPEN = 0
571 04:44:45.346702 DQ_SEMI_OPEN = 0
572 04:44:45.350026 CA_SEMI_OPEN = 0
573 04:44:45.350538 CA_FULL_RATE = 0
574 04:44:45.353644 DQ_CKDIV4_EN = 1
575 04:44:45.357032 CA_CKDIV4_EN = 1
576 04:44:45.360414 CA_PREDIV_EN = 0
577 04:44:45.363797 PH8_DLY = 0
578 04:44:45.367294 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 04:44:45.367732 DQ_AAMCK_DIV = 4
580 04:44:45.370258 CA_AAMCK_DIV = 4
581 04:44:45.373746 CA_ADMCK_DIV = 4
582 04:44:45.377028 DQ_TRACK_CA_EN = 0
583 04:44:45.380295 CA_PICK = 800
584 04:44:45.383708 CA_MCKIO = 800
585 04:44:45.384144 MCKIO_SEMI = 0
586 04:44:45.387163 PLL_FREQ = 3068
587 04:44:45.390612 DQ_UI_PI_RATIO = 32
588 04:44:45.394149 CA_UI_PI_RATIO = 0
589 04:44:45.397029 ===================================
590 04:44:45.400340 ===================================
591 04:44:45.403723 memory_type:LPDDR4
592 04:44:45.404242 GP_NUM : 10
593 04:44:45.407032 SRAM_EN : 1
594 04:44:45.407469 MD32_EN : 0
595 04:44:45.410660 ===================================
596 04:44:45.413983 [ANA_INIT] >>>>>>>>>>>>>>
597 04:44:45.417853 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 04:44:45.421243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 04:44:45.424534 ===================================
600 04:44:45.428459 data_rate = 1600,PCW = 0X7600
601 04:44:45.429033 ===================================
602 04:44:45.431833 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 04:44:45.439534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 04:44:45.443507 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 04:44:45.450823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 04:44:45.453892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 04:44:45.457525 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 04:44:45.458098 [ANA_INIT] flow start
609 04:44:45.461071 [ANA_INIT] PLL >>>>>>>>
610 04:44:45.464272 [ANA_INIT] PLL <<<<<<<<
611 04:44:45.464799 [ANA_INIT] MIDPI >>>>>>>>
612 04:44:45.467655 [ANA_INIT] MIDPI <<<<<<<<
613 04:44:45.470859 [ANA_INIT] DLL >>>>>>>>
614 04:44:45.471305 [ANA_INIT] flow end
615 04:44:45.474208 ============ LP4 DIFF to SE enter ============
616 04:44:45.480832 ============ LP4 DIFF to SE exit ============
617 04:44:45.481346 [ANA_INIT] <<<<<<<<<<<<<
618 04:44:45.484128 [Flow] Enable top DCM control >>>>>
619 04:44:45.487062 [Flow] Enable top DCM control <<<<<
620 04:44:45.490432 Enable DLL master slave shuffle
621 04:44:45.497352 ==============================================================
622 04:44:45.497798 Gating Mode config
623 04:44:45.504335 ==============================================================
624 04:44:45.507178 Config description:
625 04:44:45.517306 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 04:44:45.524175 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 04:44:45.527467 SELPH_MODE 0: By rank 1: By Phase
628 04:44:45.534404 ==============================================================
629 04:44:45.537311 GAT_TRACK_EN = 1
630 04:44:45.537783 RX_GATING_MODE = 2
631 04:44:45.540639 RX_GATING_TRACK_MODE = 2
632 04:44:45.543985 SELPH_MODE = 1
633 04:44:45.547449 PICG_EARLY_EN = 1
634 04:44:45.551029 VALID_LAT_VALUE = 1
635 04:44:45.557425 ==============================================================
636 04:44:45.560812 Enter into Gating configuration >>>>
637 04:44:45.564001 Exit from Gating configuration <<<<
638 04:44:45.567354 Enter into DVFS_PRE_config >>>>>
639 04:44:45.577505 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 04:44:45.580944 Exit from DVFS_PRE_config <<<<<
641 04:44:45.584534 Enter into PICG configuration >>>>
642 04:44:45.587465 Exit from PICG configuration <<<<
643 04:44:45.590681 [RX_INPUT] configuration >>>>>
644 04:44:45.591200 [RX_INPUT] configuration <<<<<
645 04:44:45.597529 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 04:44:45.604369 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 04:44:45.607549 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 04:44:45.614292 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 04:44:45.621143 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 04:44:45.627176 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 04:44:45.630719 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 04:44:45.634156 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 04:44:45.641367 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 04:44:45.644785 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 04:44:45.648000 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 04:44:45.651990 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 04:44:45.654629 ===================================
658 04:44:45.658039 LPDDR4 DRAM CONFIGURATION
659 04:44:45.661579 ===================================
660 04:44:45.664703 EX_ROW_EN[0] = 0x0
661 04:44:45.665137 EX_ROW_EN[1] = 0x0
662 04:44:45.668154 LP4Y_EN = 0x0
663 04:44:45.668593 WORK_FSP = 0x0
664 04:44:45.671861 WL = 0x2
665 04:44:45.672378 RL = 0x2
666 04:44:45.674660 BL = 0x2
667 04:44:45.675098 RPST = 0x0
668 04:44:45.678018 RD_PRE = 0x0
669 04:44:45.678455 WR_PRE = 0x1
670 04:44:45.681429 WR_PST = 0x0
671 04:44:45.681881 DBI_WR = 0x0
672 04:44:45.685181 DBI_RD = 0x0
673 04:44:45.685809 OTF = 0x1
674 04:44:45.688542 ===================================
675 04:44:45.691496 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 04:44:45.698058 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 04:44:45.701592 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 04:44:45.705019 ===================================
679 04:44:45.708207 LPDDR4 DRAM CONFIGURATION
680 04:44:45.711673 ===================================
681 04:44:45.712113 EX_ROW_EN[0] = 0x10
682 04:44:45.715154 EX_ROW_EN[1] = 0x0
683 04:44:45.718441 LP4Y_EN = 0x0
684 04:44:45.718930 WORK_FSP = 0x0
685 04:44:45.721697 WL = 0x2
686 04:44:45.722172 RL = 0x2
687 04:44:45.724954 BL = 0x2
688 04:44:45.725391 RPST = 0x0
689 04:44:45.728457 RD_PRE = 0x0
690 04:44:45.729012 WR_PRE = 0x1
691 04:44:45.731908 WR_PST = 0x0
692 04:44:45.732448 DBI_WR = 0x0
693 04:44:45.735354 DBI_RD = 0x0
694 04:44:45.735983 OTF = 0x1
695 04:44:45.738531 ===================================
696 04:44:45.745008 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 04:44:45.749185 nWR fixed to 40
698 04:44:45.752701 [ModeRegInit_LP4] CH0 RK0
699 04:44:45.753137 [ModeRegInit_LP4] CH0 RK1
700 04:44:45.756623 [ModeRegInit_LP4] CH1 RK0
701 04:44:45.757137 [ModeRegInit_LP4] CH1 RK1
702 04:44:45.759994 match AC timing 13
703 04:44:45.763744 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 04:44:45.767379 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 04:44:45.774645 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 04:44:45.778458 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 04:44:45.782199 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 04:44:45.782635 [EMI DOE] emi_dcm 0
709 04:44:45.789679 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 04:44:45.790221 ==
711 04:44:45.793698 Dram Type= 6, Freq= 0, CH_0, rank 0
712 04:44:45.796634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 04:44:45.797202 ==
714 04:44:45.800432 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 04:44:45.807475 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 04:44:45.816723 [CA 0] Center 38 (7~69) winsize 63
717 04:44:45.821072 [CA 1] Center 38 (7~69) winsize 63
718 04:44:45.824334 [CA 2] Center 35 (5~66) winsize 62
719 04:44:45.827828 [CA 3] Center 35 (4~66) winsize 63
720 04:44:45.831721 [CA 4] Center 34 (4~65) winsize 62
721 04:44:45.835374 [CA 5] Center 33 (3~64) winsize 62
722 04:44:45.835844
723 04:44:45.838991 [CmdBusTrainingLP45] Vref(ca) range 1: 34
724 04:44:45.839424
725 04:44:45.842936 [CATrainingPosCal] consider 1 rank data
726 04:44:45.843370 u2DelayCellTimex100 = 270/100 ps
727 04:44:45.846700 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
728 04:44:45.850032 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 04:44:45.853776 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 04:44:45.858052 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
731 04:44:45.861589 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
732 04:44:45.865468 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 04:44:45.866112
734 04:44:45.869201 CA PerBit enable=1, Macro0, CA PI delay=33
735 04:44:45.869639
736 04:44:45.872685 [CBTSetCACLKResult] CA Dly = 33
737 04:44:45.873322 CS Dly: 6 (0~37)
738 04:44:45.876707 ==
739 04:44:45.877226 Dram Type= 6, Freq= 0, CH_0, rank 1
740 04:44:45.880688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 04:44:45.884407 ==
742 04:44:45.887962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 04:44:45.895555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 04:44:45.903055 [CA 0] Center 38 (7~69) winsize 63
745 04:44:45.906875 [CA 1] Center 38 (7~69) winsize 63
746 04:44:45.910190 [CA 2] Center 36 (5~67) winsize 63
747 04:44:45.914106 [CA 3] Center 36 (5~67) winsize 63
748 04:44:45.917932 [CA 4] Center 35 (4~66) winsize 63
749 04:44:45.921187 [CA 5] Center 34 (4~65) winsize 62
750 04:44:45.921620
751 04:44:45.924701 [CmdBusTrainingLP45] Vref(ca) range 1: 34
752 04:44:45.925231
753 04:44:45.928570 [CATrainingPosCal] consider 2 rank data
754 04:44:45.932650 u2DelayCellTimex100 = 270/100 ps
755 04:44:45.935896 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 04:44:45.939821 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
757 04:44:45.940323 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
758 04:44:45.943796 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 04:44:45.947019 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 04:44:45.951003 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 04:44:45.951436
762 04:44:45.954708 CA PerBit enable=1, Macro0, CA PI delay=34
763 04:44:45.955273
764 04:44:45.958388 [CBTSetCACLKResult] CA Dly = 34
765 04:44:45.962017 CS Dly: 6 (0~38)
766 04:44:45.962604
767 04:44:45.966019 ----->DramcWriteLeveling(PI) begin...
768 04:44:45.966715 ==
769 04:44:45.969422 Dram Type= 6, Freq= 0, CH_0, rank 0
770 04:44:45.973360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 04:44:45.973805 ==
772 04:44:45.977034 Write leveling (Byte 0): 31 => 31
773 04:44:45.977476 Write leveling (Byte 1): 31 => 31
774 04:44:45.980485 DramcWriteLeveling(PI) end<-----
775 04:44:45.980917
776 04:44:45.981258 ==
777 04:44:45.984431 Dram Type= 6, Freq= 0, CH_0, rank 0
778 04:44:45.988118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 04:44:45.988558 ==
780 04:44:45.991438 [Gating] SW mode calibration
781 04:44:45.998831 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 04:44:46.006326 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 04:44:46.010026 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 04:44:46.013380 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 04:44:46.017642 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 04:44:46.021375 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 04:44:46.028225 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 04:44:46.032148 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 04:44:46.035930 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 04:44:46.039508 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 04:44:46.042877 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 04:44:46.046422 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 04:44:46.053716 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 04:44:46.057462 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 04:44:46.061376 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 04:44:46.065293 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 04:44:46.068890 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 04:44:46.076280 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 04:44:46.079169 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 04:44:46.082561 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
801 04:44:46.089414 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
802 04:44:46.092765 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 04:44:46.096050 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 04:44:46.099328 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 04:44:46.106248 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 04:44:46.109186 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 04:44:46.112720 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 04:44:46.119203 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
809 04:44:46.122484 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 04:44:46.125903 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
811 04:44:46.132375 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 04:44:46.135955 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 04:44:46.139129 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 04:44:46.145983 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 04:44:46.149131 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 04:44:46.152509 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
817 04:44:46.159451 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (0 0) (0 0)
818 04:44:46.162644 0 10 12 | B1->B0 | 2727 2323 | 1 0 | (0 0) (0 0)
819 04:44:46.165982 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 04:44:46.172601 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 04:44:46.175708 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 04:44:46.179203 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 04:44:46.185845 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 04:44:46.189335 0 11 4 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
825 04:44:46.192618 0 11 8 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
826 04:44:46.199016 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
827 04:44:46.202640 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 04:44:46.206272 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 04:44:46.209104 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 04:44:46.215990 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 04:44:46.219417 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 04:44:46.222599 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 04:44:46.229460 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 04:44:46.232769 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 04:44:46.235997 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 04:44:46.242889 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 04:44:46.246280 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 04:44:46.249354 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 04:44:46.256233 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 04:44:46.259587 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 04:44:46.262500 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 04:44:46.269505 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 04:44:46.272686 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 04:44:46.276199 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 04:44:46.282871 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 04:44:46.286006 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 04:44:46.289452 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
848 04:44:46.293028 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
849 04:44:46.299398 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
850 04:44:46.302916 Total UI for P1: 0, mck2ui 16
851 04:44:46.306008 best dqsien dly found for B0: ( 0, 14, 2)
852 04:44:46.309342 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 04:44:46.312794 Total UI for P1: 0, mck2ui 16
854 04:44:46.316251 best dqsien dly found for B1: ( 0, 14, 8)
855 04:44:46.319384 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
856 04:44:46.322688 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
857 04:44:46.323169
858 04:44:46.326257 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
859 04:44:46.329251 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
860 04:44:46.333022 [Gating] SW calibration Done
861 04:44:46.333629 ==
862 04:44:46.336226 Dram Type= 6, Freq= 0, CH_0, rank 0
863 04:44:46.339405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 04:44:46.342845 ==
865 04:44:46.343329 RX Vref Scan: 0
866 04:44:46.343706
867 04:44:46.346223 RX Vref 0 -> 0, step: 1
868 04:44:46.346795
869 04:44:46.349343 RX Delay -130 -> 252, step: 16
870 04:44:46.352686 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
871 04:44:46.356068 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
872 04:44:46.359862 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
873 04:44:46.362791 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
874 04:44:46.369597 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
875 04:44:46.372753 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 04:44:46.376328 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
877 04:44:46.379409 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 04:44:46.382765 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 04:44:46.389341 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
880 04:44:46.392807 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
881 04:44:46.395931 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
882 04:44:46.399361 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
883 04:44:46.402996 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
884 04:44:46.409469 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 04:44:46.412823 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
886 04:44:46.413502 ==
887 04:44:46.416200 Dram Type= 6, Freq= 0, CH_0, rank 0
888 04:44:46.419758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 04:44:46.420403 ==
890 04:44:46.422767 DQS Delay:
891 04:44:46.423231 DQS0 = 0, DQS1 = 0
892 04:44:46.423583 DQM Delay:
893 04:44:46.426128 DQM0 = 89, DQM1 = 80
894 04:44:46.426667 DQ Delay:
895 04:44:46.429449 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
896 04:44:46.432856 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
897 04:44:46.436200 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
898 04:44:46.439392 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
899 04:44:46.439919
900 04:44:46.440267
901 04:44:46.440591 ==
902 04:44:46.442905 Dram Type= 6, Freq= 0, CH_0, rank 0
903 04:44:46.449546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 04:44:46.450068 ==
905 04:44:46.450420
906 04:44:46.450739
907 04:44:46.451048 TX Vref Scan disable
908 04:44:46.452617 == TX Byte 0 ==
909 04:44:46.455999 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
910 04:44:46.459242 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
911 04:44:46.462756 == TX Byte 1 ==
912 04:44:46.465981 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 04:44:46.472827 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 04:44:46.473265 ==
915 04:44:46.476168 Dram Type= 6, Freq= 0, CH_0, rank 0
916 04:44:46.479120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 04:44:46.479550 ==
918 04:44:46.492172 TX Vref=22, minBit 6, minWin=27, winSum=439
919 04:44:46.495057 TX Vref=24, minBit 8, minWin=27, winSum=443
920 04:44:46.498433 TX Vref=26, minBit 8, minWin=27, winSum=447
921 04:44:46.501739 TX Vref=28, minBit 10, minWin=27, winSum=452
922 04:44:46.505112 TX Vref=30, minBit 8, minWin=28, winSum=456
923 04:44:46.508301 TX Vref=32, minBit 6, minWin=28, winSum=457
924 04:44:46.515238 [TxChooseVref] Worse bit 6, Min win 28, Win sum 457, Final Vref 32
925 04:44:46.515672
926 04:44:46.518786 Final TX Range 1 Vref 32
927 04:44:46.519348
928 04:44:46.519704 ==
929 04:44:46.522141 Dram Type= 6, Freq= 0, CH_0, rank 0
930 04:44:46.525182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 04:44:46.525750 ==
932 04:44:46.526144
933 04:44:46.528591
934 04:44:46.529186 TX Vref Scan disable
935 04:44:46.532091 == TX Byte 0 ==
936 04:44:46.535454 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
937 04:44:46.538747 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
938 04:44:46.542051 == TX Byte 1 ==
939 04:44:46.545311 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 04:44:46.548757 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 04:44:46.549346
942 04:44:46.552124 [DATLAT]
943 04:44:46.552732 Freq=800, CH0 RK0
944 04:44:46.553116
945 04:44:46.555452 DATLAT Default: 0xa
946 04:44:46.556043 0, 0xFFFF, sum = 0
947 04:44:46.558413 1, 0xFFFF, sum = 0
948 04:44:46.558898 2, 0xFFFF, sum = 0
949 04:44:46.562098 3, 0xFFFF, sum = 0
950 04:44:46.562692 4, 0xFFFF, sum = 0
951 04:44:46.565158 5, 0xFFFF, sum = 0
952 04:44:46.565645 6, 0xFFFF, sum = 0
953 04:44:46.568415 7, 0xFFFF, sum = 0
954 04:44:46.568898 8, 0xFFFF, sum = 0
955 04:44:46.572275 9, 0x0, sum = 1
956 04:44:46.572865 10, 0x0, sum = 2
957 04:44:46.575455 11, 0x0, sum = 3
958 04:44:46.575935 12, 0x0, sum = 4
959 04:44:46.578387 best_step = 10
960 04:44:46.578990
961 04:44:46.579532 ==
962 04:44:46.582131 Dram Type= 6, Freq= 0, CH_0, rank 0
963 04:44:46.585442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 04:44:46.586161 ==
965 04:44:46.588791 RX Vref Scan: 1
966 04:44:46.589500
967 04:44:46.590066 Set Vref Range= 32 -> 127
968 04:44:46.590410
969 04:44:46.591902 RX Vref 32 -> 127, step: 1
970 04:44:46.592332
971 04:44:46.595446 RX Delay -95 -> 252, step: 8
972 04:44:46.595874
973 04:44:46.598440 Set Vref, RX VrefLevel [Byte0]: 32
974 04:44:46.601876 [Byte1]: 32
975 04:44:46.602359
976 04:44:46.605398 Set Vref, RX VrefLevel [Byte0]: 33
977 04:44:46.608356 [Byte1]: 33
978 04:44:46.612053
979 04:44:46.612586 Set Vref, RX VrefLevel [Byte0]: 34
980 04:44:46.615494 [Byte1]: 34
981 04:44:46.619463
982 04:44:46.619965 Set Vref, RX VrefLevel [Byte0]: 35
983 04:44:46.622693 [Byte1]: 35
984 04:44:46.627233
985 04:44:46.627735 Set Vref, RX VrefLevel [Byte0]: 36
986 04:44:46.630666 [Byte1]: 36
987 04:44:46.634845
988 04:44:46.635280 Set Vref, RX VrefLevel [Byte0]: 37
989 04:44:46.637955 [Byte1]: 37
990 04:44:46.643204
991 04:44:46.643706 Set Vref, RX VrefLevel [Byte0]: 38
992 04:44:46.646048 [Byte1]: 38
993 04:44:46.649922
994 04:44:46.650382 Set Vref, RX VrefLevel [Byte0]: 39
995 04:44:46.653449 [Byte1]: 39
996 04:44:46.657438
997 04:44:46.657864 Set Vref, RX VrefLevel [Byte0]: 40
998 04:44:46.660735 [Byte1]: 40
999 04:44:46.665788
1000 04:44:46.666404 Set Vref, RX VrefLevel [Byte0]: 41
1001 04:44:46.668885 [Byte1]: 41
1002 04:44:46.673147
1003 04:44:46.673589 Set Vref, RX VrefLevel [Byte0]: 42
1004 04:44:46.676799 [Byte1]: 42
1005 04:44:46.680614
1006 04:44:46.681048 Set Vref, RX VrefLevel [Byte0]: 43
1007 04:44:46.683972 [Byte1]: 43
1008 04:44:46.688003
1009 04:44:46.688440 Set Vref, RX VrefLevel [Byte0]: 44
1010 04:44:46.691539 [Byte1]: 44
1011 04:44:46.696331
1012 04:44:46.696768 Set Vref, RX VrefLevel [Byte0]: 45
1013 04:44:46.699618 [Byte1]: 45
1014 04:44:46.703170
1015 04:44:46.703603 Set Vref, RX VrefLevel [Byte0]: 46
1016 04:44:46.706501 [Byte1]: 46
1017 04:44:46.710877
1018 04:44:46.711317 Set Vref, RX VrefLevel [Byte0]: 47
1019 04:44:46.713906 [Byte1]: 47
1020 04:44:46.718413
1021 04:44:46.718846 Set Vref, RX VrefLevel [Byte0]: 48
1022 04:44:46.721634 [Byte1]: 48
1023 04:44:46.725930
1024 04:44:46.726491 Set Vref, RX VrefLevel [Byte0]: 49
1025 04:44:46.729081 [Byte1]: 49
1026 04:44:46.733840
1027 04:44:46.734535 Set Vref, RX VrefLevel [Byte0]: 50
1028 04:44:46.737323 [Byte1]: 50
1029 04:44:46.740965
1030 04:44:46.741395 Set Vref, RX VrefLevel [Byte0]: 51
1031 04:44:46.744379 [Byte1]: 51
1032 04:44:46.748900
1033 04:44:46.749427 Set Vref, RX VrefLevel [Byte0]: 52
1034 04:44:46.752311 [Byte1]: 52
1035 04:44:46.756450
1036 04:44:46.756925 Set Vref, RX VrefLevel [Byte0]: 53
1037 04:44:46.759514 [Byte1]: 53
1038 04:44:46.763779
1039 04:44:46.764205 Set Vref, RX VrefLevel [Byte0]: 54
1040 04:44:46.767068 [Byte1]: 54
1041 04:44:46.771654
1042 04:44:46.772181 Set Vref, RX VrefLevel [Byte0]: 55
1043 04:44:46.775126 [Byte1]: 55
1044 04:44:46.778960
1045 04:44:46.779391 Set Vref, RX VrefLevel [Byte0]: 56
1046 04:44:46.782386 [Byte1]: 56
1047 04:44:46.786941
1048 04:44:46.787425 Set Vref, RX VrefLevel [Byte0]: 57
1049 04:44:46.790142 [Byte1]: 57
1050 04:44:46.794410
1051 04:44:46.794831 Set Vref, RX VrefLevel [Byte0]: 58
1052 04:44:46.797355 [Byte1]: 58
1053 04:44:46.802150
1054 04:44:46.802569 Set Vref, RX VrefLevel [Byte0]: 59
1055 04:44:46.805305 [Byte1]: 59
1056 04:44:46.809597
1057 04:44:46.810064 Set Vref, RX VrefLevel [Byte0]: 60
1058 04:44:46.813162 [Byte1]: 60
1059 04:44:46.817026
1060 04:44:46.817444 Set Vref, RX VrefLevel [Byte0]: 61
1061 04:44:46.820828 [Byte1]: 61
1062 04:44:46.824863
1063 04:44:46.825284 Set Vref, RX VrefLevel [Byte0]: 62
1064 04:44:46.827975 [Byte1]: 62
1065 04:44:46.832319
1066 04:44:46.832841 Set Vref, RX VrefLevel [Byte0]: 63
1067 04:44:46.835642 [Byte1]: 63
1068 04:44:46.840366
1069 04:44:46.840903 Set Vref, RX VrefLevel [Byte0]: 64
1070 04:44:46.842946 [Byte1]: 64
1071 04:44:46.847582
1072 04:44:46.848074 Set Vref, RX VrefLevel [Byte0]: 65
1073 04:44:46.851082 [Byte1]: 65
1074 04:44:46.855141
1075 04:44:46.855639 Set Vref, RX VrefLevel [Byte0]: 66
1076 04:44:46.858485 [Byte1]: 66
1077 04:44:46.862849
1078 04:44:46.863266 Set Vref, RX VrefLevel [Byte0]: 67
1079 04:44:46.866282 [Byte1]: 67
1080 04:44:46.870459
1081 04:44:46.870881 Set Vref, RX VrefLevel [Byte0]: 68
1082 04:44:46.873618 [Byte1]: 68
1083 04:44:46.877792
1084 04:44:46.878253 Set Vref, RX VrefLevel [Byte0]: 69
1085 04:44:46.881270 [Byte1]: 69
1086 04:44:46.885324
1087 04:44:46.885825 Set Vref, RX VrefLevel [Byte0]: 70
1088 04:44:46.888885 [Byte1]: 70
1089 04:44:46.893093
1090 04:44:46.893582 Set Vref, RX VrefLevel [Byte0]: 71
1091 04:44:46.896335 [Byte1]: 71
1092 04:44:46.900665
1093 04:44:46.901091 Set Vref, RX VrefLevel [Byte0]: 72
1094 04:44:46.904327 [Byte1]: 72
1095 04:44:46.908310
1096 04:44:46.908785 Set Vref, RX VrefLevel [Byte0]: 73
1097 04:44:46.911715 [Byte1]: 73
1098 04:44:46.915831
1099 04:44:46.916256 Set Vref, RX VrefLevel [Byte0]: 74
1100 04:44:46.919563 [Byte1]: 74
1101 04:44:46.923989
1102 04:44:46.924561 Set Vref, RX VrefLevel [Byte0]: 75
1103 04:44:46.926666 [Byte1]: 75
1104 04:44:46.931155
1105 04:44:46.931578 Final RX Vref Byte 0 = 61 to rank0
1106 04:44:46.934483 Final RX Vref Byte 1 = 58 to rank0
1107 04:44:46.938108 Final RX Vref Byte 0 = 61 to rank1
1108 04:44:46.941034 Final RX Vref Byte 1 = 58 to rank1==
1109 04:44:46.944354 Dram Type= 6, Freq= 0, CH_0, rank 0
1110 04:44:46.951384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1111 04:44:46.951926 ==
1112 04:44:46.952272 DQS Delay:
1113 04:44:46.952590 DQS0 = 0, DQS1 = 0
1114 04:44:46.954546 DQM Delay:
1115 04:44:46.954982 DQM0 = 93, DQM1 = 82
1116 04:44:46.957894 DQ Delay:
1117 04:44:46.960685 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1118 04:44:46.964088 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1119 04:44:46.967710 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1120 04:44:46.971084 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1121 04:44:46.971627
1122 04:44:46.971973
1123 04:44:46.977666 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1124 04:44:46.981157 CH0 RK0: MR19=606, MR18=3D38
1125 04:44:46.987608 CH0_RK0: MR19=0x606, MR18=0x3D38, DQSOSC=394, MR23=63, INC=95, DEC=63
1126 04:44:46.988075
1127 04:44:46.991221 ----->DramcWriteLeveling(PI) begin...
1128 04:44:46.991716 ==
1129 04:44:46.994222 Dram Type= 6, Freq= 0, CH_0, rank 1
1130 04:44:46.998103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1131 04:44:46.998673 ==
1132 04:44:47.001219 Write leveling (Byte 0): 32 => 32
1133 04:44:47.004440 Write leveling (Byte 1): 31 => 31
1134 04:44:47.007690 DramcWriteLeveling(PI) end<-----
1135 04:44:47.008136
1136 04:44:47.008582 ==
1137 04:44:47.010959 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 04:44:47.014744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 04:44:47.015301 ==
1140 04:44:47.017811 [Gating] SW mode calibration
1141 04:44:47.024783 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1142 04:44:47.031363 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1143 04:44:47.034238 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1144 04:44:47.037697 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1145 04:44:47.044280 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 04:44:47.047788 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 04:44:47.051342 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 04:44:47.057757 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 04:44:47.061106 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 04:44:47.064773 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 04:44:47.111799 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 04:44:47.112365 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 04:44:47.112775 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 04:44:47.113125 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 04:44:47.113808 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 04:44:47.114207 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 04:44:47.114634 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 04:44:47.114971 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 04:44:47.115291 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1160 04:44:47.115609 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1161 04:44:47.156516 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1162 04:44:47.157126 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 04:44:47.158140 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 04:44:47.158659 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 04:44:47.159020 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 04:44:47.159359 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 04:44:47.159684 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 04:44:47.160005 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 04:44:47.160318 0 9 8 | B1->B0 | 2c2c 3333 | 1 1 | (1 1) (1 1)
1170 04:44:47.160631 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 04:44:47.160998 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 04:44:47.186287 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 04:44:47.186988 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 04:44:47.187595 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 04:44:47.188535 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 04:44:47.188947 0 10 4 | B1->B0 | 3333 3030 | 1 1 | (1 0) (1 0)
1177 04:44:47.189341 0 10 8 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
1178 04:44:47.190042 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 04:44:47.193587 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 04:44:47.196451 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 04:44:47.199996 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 04:44:47.206953 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 04:44:47.210116 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 04:44:47.213434 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1185 04:44:47.220142 0 11 8 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
1186 04:44:47.223908 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 04:44:47.227307 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 04:44:47.233544 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 04:44:47.236721 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 04:44:47.239999 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 04:44:47.247071 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 04:44:47.250373 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1193 04:44:47.254338 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1194 04:44:47.257701 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 04:44:47.261711 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 04:44:47.268029 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 04:44:47.271765 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 04:44:47.275248 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 04:44:47.282504 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 04:44:47.285460 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 04:44:47.289004 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 04:44:47.292331 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 04:44:47.298875 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 04:44:47.302210 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 04:44:47.305491 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 04:44:47.312689 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 04:44:47.315783 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 04:44:47.318729 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1209 04:44:47.325765 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1210 04:44:47.326490 Total UI for P1: 0, mck2ui 16
1211 04:44:47.332447 best dqsien dly found for B0: ( 0, 14, 4)
1212 04:44:47.335875 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 04:44:47.339061 Total UI for P1: 0, mck2ui 16
1214 04:44:47.342481 best dqsien dly found for B1: ( 0, 14, 8)
1215 04:44:47.345496 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1216 04:44:47.349025 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1217 04:44:47.349542
1218 04:44:47.352397 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1219 04:44:47.355729 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1220 04:44:47.358949 [Gating] SW calibration Done
1221 04:44:47.359401 ==
1222 04:44:47.362425 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 04:44:47.366071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1224 04:44:47.366620 ==
1225 04:44:47.368981 RX Vref Scan: 0
1226 04:44:47.369516
1227 04:44:47.372365 RX Vref 0 -> 0, step: 1
1228 04:44:47.372899
1229 04:44:47.373294 RX Delay -130 -> 252, step: 16
1230 04:44:47.378763 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1231 04:44:47.382160 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1232 04:44:47.385817 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1233 04:44:47.388716 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1234 04:44:47.392305 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1235 04:44:47.398854 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1236 04:44:47.402320 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1237 04:44:47.405583 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1238 04:44:47.408943 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1239 04:44:47.412484 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1240 04:44:47.418872 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1241 04:44:47.422167 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1242 04:44:47.425772 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1243 04:44:47.429146 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1244 04:44:47.432629 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1245 04:44:47.439274 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1246 04:44:47.439799 ==
1247 04:44:47.442778 Dram Type= 6, Freq= 0, CH_0, rank 1
1248 04:44:47.446045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1249 04:44:47.446503 ==
1250 04:44:47.446849 DQS Delay:
1251 04:44:47.448967 DQS0 = 0, DQS1 = 0
1252 04:44:47.449397 DQM Delay:
1253 04:44:47.452637 DQM0 = 88, DQM1 = 81
1254 04:44:47.453161 DQ Delay:
1255 04:44:47.455748 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1256 04:44:47.459324 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1257 04:44:47.462508 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1258 04:44:47.466239 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1259 04:44:47.466669
1260 04:44:47.467011
1261 04:44:47.467331 ==
1262 04:44:47.469451 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 04:44:47.472971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 04:44:47.473548 ==
1265 04:44:47.474164
1266 04:44:47.475732
1267 04:44:47.476160 TX Vref Scan disable
1268 04:44:47.478904 == TX Byte 0 ==
1269 04:44:47.482442 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1270 04:44:47.485867 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1271 04:44:47.489334 == TX Byte 1 ==
1272 04:44:47.492498 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1273 04:44:47.495834 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1274 04:44:47.496414 ==
1275 04:44:47.499485 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 04:44:47.505840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 04:44:47.506384 ==
1278 04:44:47.518011 TX Vref=22, minBit 3, minWin=27, winSum=446
1279 04:44:47.521188 TX Vref=24, minBit 8, minWin=27, winSum=451
1280 04:44:47.524380 TX Vref=26, minBit 8, minWin=27, winSum=451
1281 04:44:47.528009 TX Vref=28, minBit 8, minWin=27, winSum=453
1282 04:44:47.531535 TX Vref=30, minBit 8, minWin=27, winSum=455
1283 04:44:47.534393 TX Vref=32, minBit 8, minWin=27, winSum=456
1284 04:44:47.541249 [TxChooseVref] Worse bit 8, Min win 27, Win sum 456, Final Vref 32
1285 04:44:47.541832
1286 04:44:47.544595 Final TX Range 1 Vref 32
1287 04:44:47.545150
1288 04:44:47.545539 ==
1289 04:44:47.547861 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 04:44:47.551474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 04:44:47.552114 ==
1292 04:44:47.552490
1293 04:44:47.554269
1294 04:44:47.554721 TX Vref Scan disable
1295 04:44:47.557611 == TX Byte 0 ==
1296 04:44:47.561078 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1297 04:44:47.564430 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1298 04:44:47.567624 == TX Byte 1 ==
1299 04:44:47.571054 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1300 04:44:47.574368 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1301 04:44:47.577697
1302 04:44:47.578046 [DATLAT]
1303 04:44:47.578388 Freq=800, CH0 RK1
1304 04:44:47.578644
1305 04:44:47.581018 DATLAT Default: 0xa
1306 04:44:47.581269 0, 0xFFFF, sum = 0
1307 04:44:47.584236 1, 0xFFFF, sum = 0
1308 04:44:47.584526 2, 0xFFFF, sum = 0
1309 04:44:47.587692 3, 0xFFFF, sum = 0
1310 04:44:47.587882 4, 0xFFFF, sum = 0
1311 04:44:47.590700 5, 0xFFFF, sum = 0
1312 04:44:47.590889 6, 0xFFFF, sum = 0
1313 04:44:47.594237 7, 0xFFFF, sum = 0
1314 04:44:47.597691 8, 0xFFFF, sum = 0
1315 04:44:47.597912 9, 0x0, sum = 1
1316 04:44:47.598123 10, 0x0, sum = 2
1317 04:44:47.600629 11, 0x0, sum = 3
1318 04:44:47.600817 12, 0x0, sum = 4
1319 04:44:47.604235 best_step = 10
1320 04:44:47.604422
1321 04:44:47.604570 ==
1322 04:44:47.607395 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 04:44:47.610724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 04:44:47.610932 ==
1325 04:44:47.614285 RX Vref Scan: 0
1326 04:44:47.614512
1327 04:44:47.614775 RX Vref 0 -> 0, step: 1
1328 04:44:47.615025
1329 04:44:47.617342 RX Delay -79 -> 252, step: 8
1330 04:44:47.624456 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1331 04:44:47.627984 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1332 04:44:47.631297 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1333 04:44:47.634641 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1334 04:44:47.638149 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1335 04:44:47.644377 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1336 04:44:47.648209 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1337 04:44:47.651723 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1338 04:44:47.654541 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1339 04:44:47.658320 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1340 04:44:47.664419 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1341 04:44:47.667822 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1342 04:44:47.671319 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1343 04:44:47.674410 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1344 04:44:47.678097 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1345 04:44:47.684927 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1346 04:44:47.685471 ==
1347 04:44:47.688098 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 04:44:47.691292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 04:44:47.691775 ==
1350 04:44:47.692162 DQS Delay:
1351 04:44:47.694722 DQS0 = 0, DQS1 = 0
1352 04:44:47.695173 DQM Delay:
1353 04:44:47.698265 DQM0 = 90, DQM1 = 81
1354 04:44:47.698716 DQ Delay:
1355 04:44:47.701056 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1356 04:44:47.704651 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1357 04:44:47.707730 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1358 04:44:47.711158 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =92
1359 04:44:47.711582
1360 04:44:47.711928
1361 04:44:47.717702 [DQSOSCAuto] RK1, (LSB)MR18= 0x411c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1362 04:44:47.721433 CH0 RK1: MR19=606, MR18=411C
1363 04:44:47.728090 CH0_RK1: MR19=0x606, MR18=0x411C, DQSOSC=393, MR23=63, INC=95, DEC=63
1364 04:44:47.731379 [RxdqsGatingPostProcess] freq 800
1365 04:44:47.738189 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1366 04:44:47.738603 Pre-setting of DQS Precalculation
1367 04:44:47.744594 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1368 04:44:47.745005 ==
1369 04:44:47.747992 Dram Type= 6, Freq= 0, CH_1, rank 0
1370 04:44:47.751612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 04:44:47.752027 ==
1372 04:44:47.758234 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1373 04:44:47.764627 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1374 04:44:47.772652 [CA 0] Center 36 (6~67) winsize 62
1375 04:44:47.776045 [CA 1] Center 36 (6~67) winsize 62
1376 04:44:47.779388 [CA 2] Center 34 (4~65) winsize 62
1377 04:44:47.782796 [CA 3] Center 34 (3~65) winsize 63
1378 04:44:47.786488 [CA 4] Center 34 (4~65) winsize 62
1379 04:44:47.789244 [CA 5] Center 33 (3~64) winsize 62
1380 04:44:47.789654
1381 04:44:47.792620 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1382 04:44:47.793044
1383 04:44:47.796620 [CATrainingPosCal] consider 1 rank data
1384 04:44:47.799312 u2DelayCellTimex100 = 270/100 ps
1385 04:44:47.802877 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1386 04:44:47.805867 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1387 04:44:47.812925 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1388 04:44:47.815983 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1389 04:44:47.819590 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1390 04:44:47.822656 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1391 04:44:47.823078
1392 04:44:47.826148 CA PerBit enable=1, Macro0, CA PI delay=33
1393 04:44:47.826568
1394 04:44:47.829764 [CBTSetCACLKResult] CA Dly = 33
1395 04:44:47.830338 CS Dly: 5 (0~36)
1396 04:44:47.830683 ==
1397 04:44:47.833409 Dram Type= 6, Freq= 0, CH_1, rank 1
1398 04:44:47.839445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 04:44:47.839872 ==
1400 04:44:47.842872 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1401 04:44:47.849878 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1402 04:44:47.858870 [CA 0] Center 36 (6~67) winsize 62
1403 04:44:47.862343 [CA 1] Center 37 (6~68) winsize 63
1404 04:44:47.865870 [CA 2] Center 35 (5~66) winsize 62
1405 04:44:47.868782 [CA 3] Center 34 (4~65) winsize 62
1406 04:44:47.872279 [CA 4] Center 34 (4~65) winsize 62
1407 04:44:47.875711 [CA 5] Center 34 (3~65) winsize 63
1408 04:44:47.876140
1409 04:44:47.879427 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1410 04:44:47.880167
1411 04:44:47.882599 [CATrainingPosCal] consider 2 rank data
1412 04:44:47.885863 u2DelayCellTimex100 = 270/100 ps
1413 04:44:47.888827 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1414 04:44:47.892275 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1415 04:44:47.899169 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1416 04:44:47.902395 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1417 04:44:47.906059 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1418 04:44:47.908923 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1419 04:44:47.909351
1420 04:44:47.912990 CA PerBit enable=1, Macro0, CA PI delay=33
1421 04:44:47.913422
1422 04:44:47.916994 [CBTSetCACLKResult] CA Dly = 33
1423 04:44:47.917425 CS Dly: 6 (0~38)
1424 04:44:47.917811
1425 04:44:47.920696 ----->DramcWriteLeveling(PI) begin...
1426 04:44:47.921269 ==
1427 04:44:47.924447 Dram Type= 6, Freq= 0, CH_1, rank 0
1428 04:44:47.928042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 04:44:47.928563 ==
1430 04:44:47.931572 Write leveling (Byte 0): 26 => 26
1431 04:44:47.935730 Write leveling (Byte 1): 30 => 30
1432 04:44:47.938973 DramcWriteLeveling(PI) end<-----
1433 04:44:47.939405
1434 04:44:47.939785 ==
1435 04:44:47.942877 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 04:44:47.946563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 04:44:47.947033 ==
1438 04:44:47.947481 [Gating] SW mode calibration
1439 04:44:47.957375 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1440 04:44:47.960369 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1441 04:44:47.963636 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1442 04:44:47.970210 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1443 04:44:47.973879 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 04:44:47.977198 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 04:44:47.983523 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 04:44:47.986721 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 04:44:47.990408 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 04:44:47.997148 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 04:44:48.000748 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 04:44:48.003797 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 04:44:48.010165 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 04:44:48.013931 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 04:44:48.017458 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 04:44:48.020218 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 04:44:48.027285 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 04:44:48.030662 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 04:44:48.033931 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 04:44:48.040367 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1459 04:44:48.043885 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 04:44:48.047371 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 04:44:48.053889 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 04:44:48.056885 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 04:44:48.060634 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 04:44:48.067029 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 04:44:48.070305 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 04:44:48.074114 0 9 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1467 04:44:48.080509 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 04:44:48.083965 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 04:44:48.086923 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 04:44:48.093853 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 04:44:48.097459 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 04:44:48.100275 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 04:44:48.103765 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1474 04:44:48.110205 0 10 4 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (0 1)
1475 04:44:48.114072 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 04:44:48.117025 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 04:44:48.123987 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 04:44:48.126979 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 04:44:48.130466 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 04:44:48.136921 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 04:44:48.140607 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 04:44:48.143964 0 11 4 | B1->B0 | 3030 3636 | 1 0 | (0 0) (0 0)
1483 04:44:48.150343 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 04:44:48.153818 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 04:44:48.156993 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 04:44:48.163739 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 04:44:48.166845 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 04:44:48.170073 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 04:44:48.176858 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 04:44:48.179990 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1491 04:44:48.183371 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 04:44:48.186897 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 04:44:48.193832 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 04:44:48.197145 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 04:44:48.200402 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 04:44:48.206874 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 04:44:48.210392 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 04:44:48.213693 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 04:44:48.220489 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 04:44:48.224172 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 04:44:48.227377 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 04:44:48.233922 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 04:44:48.237370 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 04:44:48.240487 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 04:44:48.247332 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 04:44:48.250890 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1507 04:44:48.254315 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 04:44:48.257296 Total UI for P1: 0, mck2ui 16
1509 04:44:48.260466 best dqsien dly found for B0: ( 0, 14, 4)
1510 04:44:48.264163 Total UI for P1: 0, mck2ui 16
1511 04:44:48.267273 best dqsien dly found for B1: ( 0, 14, 6)
1512 04:44:48.270727 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1513 04:44:48.273937 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1514 04:44:48.274157
1515 04:44:48.277031 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1516 04:44:48.280538 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1517 04:44:48.283845 [Gating] SW calibration Done
1518 04:44:48.283985 ==
1519 04:44:48.287131 Dram Type= 6, Freq= 0, CH_1, rank 0
1520 04:44:48.290446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1521 04:44:48.293944 ==
1522 04:44:48.294062 RX Vref Scan: 0
1523 04:44:48.294167
1524 04:44:48.297331 RX Vref 0 -> 0, step: 1
1525 04:44:48.297441
1526 04:44:48.300279 RX Delay -130 -> 252, step: 16
1527 04:44:48.304065 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1528 04:44:48.307144 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1529 04:44:48.310563 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1530 04:44:48.313676 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1531 04:44:48.320979 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1532 04:44:48.324380 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1533 04:44:48.327142 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1534 04:44:48.330681 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1535 04:44:48.334111 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1536 04:44:48.340940 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1537 04:44:48.344134 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1538 04:44:48.347381 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1539 04:44:48.350936 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1540 04:44:48.353986 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1541 04:44:48.360934 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1542 04:44:48.364359 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1543 04:44:48.364649 ==
1544 04:44:48.367507 Dram Type= 6, Freq= 0, CH_1, rank 0
1545 04:44:48.370455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1546 04:44:48.371014 ==
1547 04:44:48.374245 DQS Delay:
1548 04:44:48.374898 DQS0 = 0, DQS1 = 0
1549 04:44:48.375511 DQM Delay:
1550 04:44:48.377569 DQM0 = 88, DQM1 = 80
1551 04:44:48.378282 DQ Delay:
1552 04:44:48.380778 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1553 04:44:48.383982 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1554 04:44:48.387209 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1555 04:44:48.390666 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1556 04:44:48.391365
1557 04:44:48.392011
1558 04:44:48.392640 ==
1559 04:44:48.393819 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 04:44:48.400638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 04:44:48.401143 ==
1562 04:44:48.401608
1563 04:44:48.402069
1564 04:44:48.402522 TX Vref Scan disable
1565 04:44:48.403896 == TX Byte 0 ==
1566 04:44:48.407293 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1567 04:44:48.410704 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1568 04:44:48.414115 == TX Byte 1 ==
1569 04:44:48.417630 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1570 04:44:48.420575 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1571 04:44:48.423964 ==
1572 04:44:48.427301 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 04:44:48.430620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 04:44:48.430788 ==
1575 04:44:48.443608 TX Vref=22, minBit 10, minWin=27, winSum=451
1576 04:44:48.447006 TX Vref=24, minBit 15, minWin=27, winSum=454
1577 04:44:48.450234 TX Vref=26, minBit 15, minWin=27, winSum=456
1578 04:44:48.453665 TX Vref=28, minBit 0, minWin=28, winSum=457
1579 04:44:48.456514 TX Vref=30, minBit 15, minWin=27, winSum=458
1580 04:44:48.463643 TX Vref=32, minBit 12, minWin=27, winSum=456
1581 04:44:48.467301 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
1582 04:44:48.467586
1583 04:44:48.470678 Final TX Range 1 Vref 28
1584 04:44:48.470980
1585 04:44:48.471186 ==
1586 04:44:48.473494 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 04:44:48.477077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 04:44:48.477273 ==
1589 04:44:48.480037
1590 04:44:48.480265
1591 04:44:48.480443 TX Vref Scan disable
1592 04:44:48.483934 == TX Byte 0 ==
1593 04:44:48.487295 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1594 04:44:48.493826 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1595 04:44:48.494370 == TX Byte 1 ==
1596 04:44:48.498043 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1597 04:44:48.501385 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1598 04:44:48.501817
1599 04:44:48.504494 [DATLAT]
1600 04:44:48.505046 Freq=800, CH1 RK0
1601 04:44:48.505535
1602 04:44:48.508121 DATLAT Default: 0xa
1603 04:44:48.508543 0, 0xFFFF, sum = 0
1604 04:44:48.511450 1, 0xFFFF, sum = 0
1605 04:44:48.511880 2, 0xFFFF, sum = 0
1606 04:44:48.514899 3, 0xFFFF, sum = 0
1607 04:44:48.515330 4, 0xFFFF, sum = 0
1608 04:44:48.517884 5, 0xFFFF, sum = 0
1609 04:44:48.518344 6, 0xFFFF, sum = 0
1610 04:44:48.521386 7, 0xFFFF, sum = 0
1611 04:44:48.521815 8, 0xFFFF, sum = 0
1612 04:44:48.525031 9, 0x0, sum = 1
1613 04:44:48.525533 10, 0x0, sum = 2
1614 04:44:48.528385 11, 0x0, sum = 3
1615 04:44:48.528818 12, 0x0, sum = 4
1616 04:44:48.531684 best_step = 10
1617 04:44:48.532108
1618 04:44:48.532442 ==
1619 04:44:48.535030 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 04:44:48.537983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 04:44:48.538485 ==
1622 04:44:48.538824 RX Vref Scan: 1
1623 04:44:48.541537
1624 04:44:48.542063 Set Vref Range= 32 -> 127
1625 04:44:48.542406
1626 04:44:48.544919 RX Vref 32 -> 127, step: 1
1627 04:44:48.545417
1628 04:44:48.547811 RX Delay -95 -> 252, step: 8
1629 04:44:48.548236
1630 04:44:48.551269 Set Vref, RX VrefLevel [Byte0]: 32
1631 04:44:48.554382 [Byte1]: 32
1632 04:44:48.554806
1633 04:44:48.557922 Set Vref, RX VrefLevel [Byte0]: 33
1634 04:44:48.561490 [Byte1]: 33
1635 04:44:48.564505
1636 04:44:48.564928 Set Vref, RX VrefLevel [Byte0]: 34
1637 04:44:48.567855 [Byte1]: 34
1638 04:44:48.571943
1639 04:44:48.572360 Set Vref, RX VrefLevel [Byte0]: 35
1640 04:44:48.575385 [Byte1]: 35
1641 04:44:48.579679
1642 04:44:48.580145 Set Vref, RX VrefLevel [Byte0]: 36
1643 04:44:48.582784 [Byte1]: 36
1644 04:44:48.587052
1645 04:44:48.587601 Set Vref, RX VrefLevel [Byte0]: 37
1646 04:44:48.590376 [Byte1]: 37
1647 04:44:48.594982
1648 04:44:48.595409 Set Vref, RX VrefLevel [Byte0]: 38
1649 04:44:48.598053 [Byte1]: 38
1650 04:44:48.602333
1651 04:44:48.602808 Set Vref, RX VrefLevel [Byte0]: 39
1652 04:44:48.605498 [Byte1]: 39
1653 04:44:48.609989
1654 04:44:48.610461 Set Vref, RX VrefLevel [Byte0]: 40
1655 04:44:48.613116 [Byte1]: 40
1656 04:44:48.617598
1657 04:44:48.618088 Set Vref, RX VrefLevel [Byte0]: 41
1658 04:44:48.620680 [Byte1]: 41
1659 04:44:48.625156
1660 04:44:48.625584 Set Vref, RX VrefLevel [Byte0]: 42
1661 04:44:48.628827 [Byte1]: 42
1662 04:44:48.632820
1663 04:44:48.633358 Set Vref, RX VrefLevel [Byte0]: 43
1664 04:44:48.635775 [Byte1]: 43
1665 04:44:48.640496
1666 04:44:48.641026 Set Vref, RX VrefLevel [Byte0]: 44
1667 04:44:48.643722 [Byte1]: 44
1668 04:44:48.647632
1669 04:44:48.648024 Set Vref, RX VrefLevel [Byte0]: 45
1670 04:44:48.651024 [Byte1]: 45
1671 04:44:48.655627
1672 04:44:48.656053 Set Vref, RX VrefLevel [Byte0]: 46
1673 04:44:48.658745 [Byte1]: 46
1674 04:44:48.663039
1675 04:44:48.663346 Set Vref, RX VrefLevel [Byte0]: 47
1676 04:44:48.666526 [Byte1]: 47
1677 04:44:48.670385
1678 04:44:48.670572 Set Vref, RX VrefLevel [Byte0]: 48
1679 04:44:48.673770 [Byte1]: 48
1680 04:44:48.678322
1681 04:44:48.678482 Set Vref, RX VrefLevel [Byte0]: 49
1682 04:44:48.681260 [Byte1]: 49
1683 04:44:48.685563
1684 04:44:48.685691 Set Vref, RX VrefLevel [Byte0]: 50
1685 04:44:48.688759 [Byte1]: 50
1686 04:44:48.693076
1687 04:44:48.693189 Set Vref, RX VrefLevel [Byte0]: 51
1688 04:44:48.696197 [Byte1]: 51
1689 04:44:48.700602
1690 04:44:48.700687 Set Vref, RX VrefLevel [Byte0]: 52
1691 04:44:48.703984 [Byte1]: 52
1692 04:44:48.708139
1693 04:44:48.708224 Set Vref, RX VrefLevel [Byte0]: 53
1694 04:44:48.711523 [Byte1]: 53
1695 04:44:48.715909
1696 04:44:48.715993 Set Vref, RX VrefLevel [Byte0]: 54
1697 04:44:48.719598 [Byte1]: 54
1698 04:44:48.724040
1699 04:44:48.724470 Set Vref, RX VrefLevel [Byte0]: 55
1700 04:44:48.727038 [Byte1]: 55
1701 04:44:48.731433
1702 04:44:48.731928 Set Vref, RX VrefLevel [Byte0]: 56
1703 04:44:48.734853 [Byte1]: 56
1704 04:44:48.739077
1705 04:44:48.739505 Set Vref, RX VrefLevel [Byte0]: 57
1706 04:44:48.742385 [Byte1]: 57
1707 04:44:48.746844
1708 04:44:48.747333 Set Vref, RX VrefLevel [Byte0]: 58
1709 04:44:48.749847 [Byte1]: 58
1710 04:44:48.754409
1711 04:44:48.754838 Set Vref, RX VrefLevel [Byte0]: 59
1712 04:44:48.757531 [Byte1]: 59
1713 04:44:48.761863
1714 04:44:48.762326 Set Vref, RX VrefLevel [Byte0]: 60
1715 04:44:48.765107 [Byte1]: 60
1716 04:44:48.769598
1717 04:44:48.770226 Set Vref, RX VrefLevel [Byte0]: 61
1718 04:44:48.772476 [Byte1]: 61
1719 04:44:48.777004
1720 04:44:48.777550 Set Vref, RX VrefLevel [Byte0]: 62
1721 04:44:48.780470 [Byte1]: 62
1722 04:44:48.784469
1723 04:44:48.784896 Set Vref, RX VrefLevel [Byte0]: 63
1724 04:44:48.787627 [Byte1]: 63
1725 04:44:48.792193
1726 04:44:48.792621 Set Vref, RX VrefLevel [Byte0]: 64
1727 04:44:48.795663 [Byte1]: 64
1728 04:44:48.799607
1729 04:44:48.800044 Set Vref, RX VrefLevel [Byte0]: 65
1730 04:44:48.802960 [Byte1]: 65
1731 04:44:48.807184
1732 04:44:48.807612 Set Vref, RX VrefLevel [Byte0]: 66
1733 04:44:48.810951 [Byte1]: 66
1734 04:44:48.815131
1735 04:44:48.815561 Set Vref, RX VrefLevel [Byte0]: 67
1736 04:44:48.818143 [Byte1]: 67
1737 04:44:48.822629
1738 04:44:48.823062 Set Vref, RX VrefLevel [Byte0]: 68
1739 04:44:48.825779 [Byte1]: 68
1740 04:44:48.830111
1741 04:44:48.830541 Set Vref, RX VrefLevel [Byte0]: 69
1742 04:44:48.833698 [Byte1]: 69
1743 04:44:48.837608
1744 04:44:48.838065 Set Vref, RX VrefLevel [Byte0]: 70
1745 04:44:48.840947 [Byte1]: 70
1746 04:44:48.844983
1747 04:44:48.845210 Set Vref, RX VrefLevel [Byte0]: 71
1748 04:44:48.848527 [Byte1]: 71
1749 04:44:48.852887
1750 04:44:48.853082 Set Vref, RX VrefLevel [Byte0]: 72
1751 04:44:48.855853 [Byte1]: 72
1752 04:44:48.860322
1753 04:44:48.860459 Set Vref, RX VrefLevel [Byte0]: 73
1754 04:44:48.863873 [Byte1]: 73
1755 04:44:48.867942
1756 04:44:48.868069 Set Vref, RX VrefLevel [Byte0]: 74
1757 04:44:48.874417 [Byte1]: 74
1758 04:44:48.874524
1759 04:44:48.877886 Set Vref, RX VrefLevel [Byte0]: 75
1760 04:44:48.880869 [Byte1]: 75
1761 04:44:48.880956
1762 04:44:48.884410 Set Vref, RX VrefLevel [Byte0]: 76
1763 04:44:48.887669 [Byte1]: 76
1764 04:44:48.887756
1765 04:44:48.891305 Set Vref, RX VrefLevel [Byte0]: 77
1766 04:44:48.894666 [Byte1]: 77
1767 04:44:48.898391
1768 04:44:48.898475 Set Vref, RX VrefLevel [Byte0]: 78
1769 04:44:48.901498 [Byte1]: 78
1770 04:44:48.905839
1771 04:44:48.905924 Set Vref, RX VrefLevel [Byte0]: 79
1772 04:44:48.909308 [Byte1]: 79
1773 04:44:48.913416
1774 04:44:48.913499 Final RX Vref Byte 0 = 50 to rank0
1775 04:44:48.916733 Final RX Vref Byte 1 = 62 to rank0
1776 04:44:48.920336 Final RX Vref Byte 0 = 50 to rank1
1777 04:44:48.923231 Final RX Vref Byte 1 = 62 to rank1==
1778 04:44:48.926615 Dram Type= 6, Freq= 0, CH_1, rank 0
1779 04:44:48.933477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1780 04:44:48.933587 ==
1781 04:44:48.933657 DQS Delay:
1782 04:44:48.933719 DQS0 = 0, DQS1 = 0
1783 04:44:48.936909 DQM Delay:
1784 04:44:48.936994 DQM0 = 93, DQM1 = 81
1785 04:44:48.939975 DQ Delay:
1786 04:44:48.943524 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1787 04:44:48.943619 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1788 04:44:48.946972 DQ8 =72, DQ9 =68, DQ10 =88, DQ11 =76
1789 04:44:48.953756 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =84
1790 04:44:48.953840
1791 04:44:48.953906
1792 04:44:48.960096 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1793 04:44:48.963578 CH1 RK0: MR19=606, MR18=2C4A
1794 04:44:48.969972 CH1_RK0: MR19=0x606, MR18=0x2C4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1795 04:44:48.970061
1796 04:44:48.973354 ----->DramcWriteLeveling(PI) begin...
1797 04:44:48.973443 ==
1798 04:44:48.976765 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 04:44:48.980288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 04:44:48.980392 ==
1801 04:44:48.983411 Write leveling (Byte 0): 27 => 27
1802 04:44:48.986843 Write leveling (Byte 1): 30 => 30
1803 04:44:48.990298 DramcWriteLeveling(PI) end<-----
1804 04:44:48.990421
1805 04:44:48.990517 ==
1806 04:44:48.993669 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 04:44:48.996927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 04:44:48.997064 ==
1809 04:44:49.000243 [Gating] SW mode calibration
1810 04:44:49.006817 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1811 04:44:49.013449 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1812 04:44:49.017059 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1813 04:44:49.020400 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1814 04:44:49.027221 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 04:44:49.030052 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 04:44:49.033482 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 04:44:49.040391 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 04:44:49.043426 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 04:44:49.046969 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 04:44:49.053860 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 04:44:49.057090 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 04:44:49.060205 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 04:44:49.067131 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 04:44:49.070655 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 04:44:49.074167 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 04:44:49.077269 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 04:44:49.083969 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 04:44:49.087326 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1829 04:44:49.090283 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1830 04:44:49.097140 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 04:44:49.100652 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 04:44:49.103858 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 04:44:49.110354 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 04:44:49.114035 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 04:44:49.117155 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 04:44:49.124249 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 04:44:49.127128 0 9 4 | B1->B0 | 2525 2323 | 1 0 | (1 1) (0 0)
1838 04:44:49.130995 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1839 04:44:49.137536 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 04:44:49.141159 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 04:44:49.144046 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 04:44:49.150884 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 04:44:49.154032 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 04:44:49.157441 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 04:44:49.161159 0 10 4 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (0 0)
1846 04:44:49.167753 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1847 04:44:49.171312 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 04:44:49.174444 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 04:44:49.180663 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 04:44:49.184078 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 04:44:49.187503 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 04:44:49.193817 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 04:44:49.197369 0 11 4 | B1->B0 | 2e2e 2e2e | 0 0 | (0 0) (0 0)
1854 04:44:49.200770 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1855 04:44:49.207149 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 04:44:49.210630 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 04:44:49.214041 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 04:44:49.220437 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 04:44:49.224399 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 04:44:49.227520 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 04:44:49.233985 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1862 04:44:49.237617 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1863 04:44:49.240432 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 04:44:49.247103 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 04:44:49.250761 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 04:44:49.254165 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 04:44:49.257307 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 04:44:49.264062 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 04:44:49.267454 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 04:44:49.270870 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 04:44:49.277393 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 04:44:49.280891 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 04:44:49.284155 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 04:44:49.290836 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 04:44:49.294313 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 04:44:49.297911 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1877 04:44:49.304175 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1878 04:44:49.304659 Total UI for P1: 0, mck2ui 16
1879 04:44:49.310637 best dqsien dly found for B1: ( 0, 14, 2)
1880 04:44:49.314300 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 04:44:49.317644 Total UI for P1: 0, mck2ui 16
1882 04:44:49.321001 best dqsien dly found for B0: ( 0, 14, 2)
1883 04:44:49.324247 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1884 04:44:49.327915 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1885 04:44:49.328491
1886 04:44:49.331014 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1887 04:44:49.334161 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1888 04:44:49.337802 [Gating] SW calibration Done
1889 04:44:49.338306 ==
1890 04:44:49.340824 Dram Type= 6, Freq= 0, CH_1, rank 1
1891 04:44:49.344447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1892 04:44:49.344920 ==
1893 04:44:49.347514 RX Vref Scan: 0
1894 04:44:49.347998
1895 04:44:49.350859 RX Vref 0 -> 0, step: 1
1896 04:44:49.351330
1897 04:44:49.351704 RX Delay -130 -> 252, step: 16
1898 04:44:49.357703 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1899 04:44:49.360667 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1900 04:44:49.364072 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1901 04:44:49.367507 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1902 04:44:49.370854 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1903 04:44:49.377265 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1904 04:44:49.380670 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1905 04:44:49.384105 iDelay=222, Bit 7, Center 85 (-18 ~ 189) 208
1906 04:44:49.387620 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1907 04:44:49.390569 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1908 04:44:49.397842 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1909 04:44:49.400680 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1910 04:44:49.404154 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1911 04:44:49.407569 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1912 04:44:49.410979 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1913 04:44:49.417547 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1914 04:44:49.418108 ==
1915 04:44:49.421041 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 04:44:49.424503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1917 04:44:49.425037 ==
1918 04:44:49.425409 DQS Delay:
1919 04:44:49.428030 DQS0 = 0, DQS1 = 0
1920 04:44:49.428584 DQM Delay:
1921 04:44:49.431037 DQM0 = 91, DQM1 = 78
1922 04:44:49.431504 DQ Delay:
1923 04:44:49.433879 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1924 04:44:49.437388 DQ4 =85, DQ5 =109, DQ6 =93, DQ7 =85
1925 04:44:49.440923 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =69
1926 04:44:49.444005 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1927 04:44:49.444503
1928 04:44:49.444884
1929 04:44:49.445226 ==
1930 04:44:49.447784 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 04:44:49.450965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 04:44:49.451451 ==
1933 04:44:49.451822
1934 04:44:49.454191
1935 04:44:49.454804 TX Vref Scan disable
1936 04:44:49.457299 == TX Byte 0 ==
1937 04:44:49.460909 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1938 04:44:49.464430 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1939 04:44:49.467279 == TX Byte 1 ==
1940 04:44:49.470770 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1941 04:44:49.474073 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1942 04:44:49.474824 ==
1943 04:44:49.477628 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 04:44:49.484138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 04:44:49.484613 ==
1946 04:44:49.495848 TX Vref=22, minBit 13, minWin=27, winSum=452
1947 04:44:49.499007 TX Vref=24, minBit 13, minWin=27, winSum=453
1948 04:44:49.502794 TX Vref=26, minBit 13, minWin=27, winSum=455
1949 04:44:49.505817 TX Vref=28, minBit 8, minWin=28, winSum=460
1950 04:44:49.509290 TX Vref=30, minBit 9, minWin=27, winSum=458
1951 04:44:49.516098 TX Vref=32, minBit 8, minWin=28, winSum=459
1952 04:44:49.520021 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 28
1953 04:44:49.520602
1954 04:44:49.522648 Final TX Range 1 Vref 28
1955 04:44:49.523117
1956 04:44:49.523536 ==
1957 04:44:49.526572 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 04:44:49.529442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 04:44:49.530051 ==
1960 04:44:49.532632
1961 04:44:49.533093
1962 04:44:49.533460 TX Vref Scan disable
1963 04:44:49.536452 == TX Byte 0 ==
1964 04:44:49.539700 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1965 04:44:49.543155 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1966 04:44:49.546448 == TX Byte 1 ==
1967 04:44:49.549407 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1968 04:44:49.553296 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1969 04:44:49.556325
1970 04:44:49.556790 [DATLAT]
1971 04:44:49.557162 Freq=800, CH1 RK1
1972 04:44:49.557511
1973 04:44:49.559423 DATLAT Default: 0xa
1974 04:44:49.559886 0, 0xFFFF, sum = 0
1975 04:44:49.563096 1, 0xFFFF, sum = 0
1976 04:44:49.563570 2, 0xFFFF, sum = 0
1977 04:44:49.566250 3, 0xFFFF, sum = 0
1978 04:44:49.566719 4, 0xFFFF, sum = 0
1979 04:44:49.569485 5, 0xFFFF, sum = 0
1980 04:44:49.569910 6, 0xFFFF, sum = 0
1981 04:44:49.573083 7, 0xFFFF, sum = 0
1982 04:44:49.576641 8, 0xFFFF, sum = 0
1983 04:44:49.577176 9, 0x0, sum = 1
1984 04:44:49.577528 10, 0x0, sum = 2
1985 04:44:49.579617 11, 0x0, sum = 3
1986 04:44:49.580044 12, 0x0, sum = 4
1987 04:44:49.583336 best_step = 10
1988 04:44:49.583860
1989 04:44:49.584204 ==
1990 04:44:49.586044 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 04:44:49.589543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 04:44:49.590002 ==
1993 04:44:49.592942 RX Vref Scan: 0
1994 04:44:49.593360
1995 04:44:49.593695 RX Vref 0 -> 0, step: 1
1996 04:44:49.594051
1997 04:44:49.596432 RX Delay -95 -> 252, step: 8
1998 04:44:49.603093 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
1999 04:44:49.606512 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2000 04:44:49.609744 iDelay=209, Bit 2, Center 76 (-23 ~ 176) 200
2001 04:44:49.612935 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2002 04:44:49.616394 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2003 04:44:49.623367 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2004 04:44:49.626236 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2005 04:44:49.630017 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2006 04:44:49.633465 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2007 04:44:49.636823 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2008 04:44:49.639583 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2009 04:44:49.646264 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2010 04:44:49.649765 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2011 04:44:49.653382 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2012 04:44:49.656576 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2013 04:44:49.663015 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2014 04:44:49.663481 ==
2015 04:44:49.666236 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 04:44:49.669999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 04:44:49.670493 ==
2018 04:44:49.670866 DQS Delay:
2019 04:44:49.673054 DQS0 = 0, DQS1 = 0
2020 04:44:49.673520 DQM Delay:
2021 04:44:49.676251 DQM0 = 89, DQM1 = 84
2022 04:44:49.676721 DQ Delay:
2023 04:44:49.679779 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =88
2024 04:44:49.683155 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2025 04:44:49.686476 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2026 04:44:49.689999 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =96
2027 04:44:49.690471
2028 04:44:49.690841
2029 04:44:49.696746 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2030 04:44:49.700018 CH1 RK1: MR19=606, MR18=3D12
2031 04:44:49.706470 CH1_RK1: MR19=0x606, MR18=0x3D12, DQSOSC=394, MR23=63, INC=95, DEC=63
2032 04:44:49.709857 [RxdqsGatingPostProcess] freq 800
2033 04:44:49.716646 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2034 04:44:49.717121 Pre-setting of DQS Precalculation
2035 04:44:49.723474 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2036 04:44:49.730251 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2037 04:44:49.736748 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2038 04:44:49.737295
2039 04:44:49.737672
2040 04:44:49.740261 [Calibration Summary] 1600 Mbps
2041 04:44:49.743669 CH 0, Rank 0
2042 04:44:49.744143 SW Impedance : PASS
2043 04:44:49.746944 DUTY Scan : NO K
2044 04:44:49.747441 ZQ Calibration : PASS
2045 04:44:49.750156 Jitter Meter : NO K
2046 04:44:49.753710 CBT Training : PASS
2047 04:44:49.754339 Write leveling : PASS
2048 04:44:49.757208 RX DQS gating : PASS
2049 04:44:49.760497 RX DQ/DQS(RDDQC) : PASS
2050 04:44:49.760972 TX DQ/DQS : PASS
2051 04:44:49.763465 RX DATLAT : PASS
2052 04:44:49.767137 RX DQ/DQS(Engine): PASS
2053 04:44:49.767610 TX OE : NO K
2054 04:44:49.767985 All Pass.
2055 04:44:49.770237
2056 04:44:49.770708 CH 0, Rank 1
2057 04:44:49.773751 SW Impedance : PASS
2058 04:44:49.774262 DUTY Scan : NO K
2059 04:44:49.777133 ZQ Calibration : PASS
2060 04:44:49.777604 Jitter Meter : NO K
2061 04:44:49.780316 CBT Training : PASS
2062 04:44:49.783632 Write leveling : PASS
2063 04:44:49.784103 RX DQS gating : PASS
2064 04:44:49.786807 RX DQ/DQS(RDDQC) : PASS
2065 04:44:49.790393 TX DQ/DQS : PASS
2066 04:44:49.790867 RX DATLAT : PASS
2067 04:44:49.793974 RX DQ/DQS(Engine): PASS
2068 04:44:49.797439 TX OE : NO K
2069 04:44:49.798049 All Pass.
2070 04:44:49.798438
2071 04:44:49.798786 CH 1, Rank 0
2072 04:44:49.800319 SW Impedance : PASS
2073 04:44:49.803834 DUTY Scan : NO K
2074 04:44:49.804308 ZQ Calibration : PASS
2075 04:44:49.807255 Jitter Meter : NO K
2076 04:44:49.810444 CBT Training : PASS
2077 04:44:49.810906 Write leveling : PASS
2078 04:44:49.813685 RX DQS gating : PASS
2079 04:44:49.814245 RX DQ/DQS(RDDQC) : PASS
2080 04:44:49.816767 TX DQ/DQS : PASS
2081 04:44:49.820533 RX DATLAT : PASS
2082 04:44:49.821070 RX DQ/DQS(Engine): PASS
2083 04:44:49.823779 TX OE : NO K
2084 04:44:49.824246 All Pass.
2085 04:44:49.824613
2086 04:44:49.826790 CH 1, Rank 1
2087 04:44:49.827252 SW Impedance : PASS
2088 04:44:49.830288 DUTY Scan : NO K
2089 04:44:49.833877 ZQ Calibration : PASS
2090 04:44:49.834464 Jitter Meter : NO K
2091 04:44:49.836931 CBT Training : PASS
2092 04:44:49.840340 Write leveling : PASS
2093 04:44:49.840806 RX DQS gating : PASS
2094 04:44:49.843820 RX DQ/DQS(RDDQC) : PASS
2095 04:44:49.846864 TX DQ/DQS : PASS
2096 04:44:49.847334 RX DATLAT : PASS
2097 04:44:49.850221 RX DQ/DQS(Engine): PASS
2098 04:44:49.853797 TX OE : NO K
2099 04:44:49.854409 All Pass.
2100 04:44:49.854781
2101 04:44:49.855126 DramC Write-DBI off
2102 04:44:49.857225 PER_BANK_REFRESH: Hybrid Mode
2103 04:44:49.860720 TX_TRACKING: ON
2104 04:44:49.863485 [GetDramInforAfterCalByMRR] Vendor 6.
2105 04:44:49.867207 [GetDramInforAfterCalByMRR] Revision 606.
2106 04:44:49.870470 [GetDramInforAfterCalByMRR] Revision 2 0.
2107 04:44:49.870936 MR0 0x3b3b
2108 04:44:49.873757 MR8 0x5151
2109 04:44:49.877119 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2110 04:44:49.877679
2111 04:44:49.878101 MR0 0x3b3b
2112 04:44:49.878452 MR8 0x5151
2113 04:44:49.880283 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 04:44:49.880748
2115 04:44:49.890375 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2116 04:44:49.894098 [FAST_K] Save calibration result to emmc
2117 04:44:49.897318 [FAST_K] Save calibration result to emmc
2118 04:44:49.900782 dram_init: config_dvfs: 1
2119 04:44:49.903756 dramc_set_vcore_voltage set vcore to 662500
2120 04:44:49.907249 Read voltage for 1200, 2
2121 04:44:49.907715 Vio18 = 0
2122 04:44:49.908083 Vcore = 662500
2123 04:44:49.910681 Vdram = 0
2124 04:44:49.911143 Vddq = 0
2125 04:44:49.911509 Vmddr = 0
2126 04:44:49.917230 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2127 04:44:49.920826 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2128 04:44:49.924220 MEM_TYPE=3, freq_sel=15
2129 04:44:49.927427 sv_algorithm_assistance_LP4_1600
2130 04:44:49.930650 ============ PULL DRAM RESETB DOWN ============
2131 04:44:49.934358 ========== PULL DRAM RESETB DOWN end =========
2132 04:44:49.940943 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2133 04:44:49.944285 ===================================
2134 04:44:49.944819 LPDDR4 DRAM CONFIGURATION
2135 04:44:49.947367 ===================================
2136 04:44:49.950725 EX_ROW_EN[0] = 0x0
2137 04:44:49.954496 EX_ROW_EN[1] = 0x0
2138 04:44:49.955059 LP4Y_EN = 0x0
2139 04:44:49.957550 WORK_FSP = 0x0
2140 04:44:49.958151 WL = 0x4
2141 04:44:49.961090 RL = 0x4
2142 04:44:49.961652 BL = 0x2
2143 04:44:49.964092 RPST = 0x0
2144 04:44:49.964658 RD_PRE = 0x0
2145 04:44:49.967269 WR_PRE = 0x1
2146 04:44:49.967736 WR_PST = 0x0
2147 04:44:49.970841 DBI_WR = 0x0
2148 04:44:49.971400 DBI_RD = 0x0
2149 04:44:49.974283 OTF = 0x1
2150 04:44:49.977420 ===================================
2151 04:44:49.980666 ===================================
2152 04:44:49.981136 ANA top config
2153 04:44:49.984574 ===================================
2154 04:44:49.987581 DLL_ASYNC_EN = 0
2155 04:44:49.990691 ALL_SLAVE_EN = 0
2156 04:44:49.993846 NEW_RANK_MODE = 1
2157 04:44:49.994376 DLL_IDLE_MODE = 1
2158 04:44:49.997539 LP45_APHY_COMB_EN = 1
2159 04:44:50.000799 TX_ODT_DIS = 1
2160 04:44:50.004408 NEW_8X_MODE = 1
2161 04:44:50.007415 ===================================
2162 04:44:50.011157 ===================================
2163 04:44:50.011729 data_rate = 2400
2164 04:44:50.013874 CKR = 1
2165 04:44:50.017618 DQ_P2S_RATIO = 8
2166 04:44:50.021195 ===================================
2167 04:44:50.024041 CA_P2S_RATIO = 8
2168 04:44:50.027820 DQ_CA_OPEN = 0
2169 04:44:50.031210 DQ_SEMI_OPEN = 0
2170 04:44:50.031779 CA_SEMI_OPEN = 0
2171 04:44:50.034618 CA_FULL_RATE = 0
2172 04:44:50.037641 DQ_CKDIV4_EN = 0
2173 04:44:50.041248 CA_CKDIV4_EN = 0
2174 04:44:50.044767 CA_PREDIV_EN = 0
2175 04:44:50.047818 PH8_DLY = 17
2176 04:44:50.048290 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2177 04:44:50.050737 DQ_AAMCK_DIV = 4
2178 04:44:50.054322 CA_AAMCK_DIV = 4
2179 04:44:50.057872 CA_ADMCK_DIV = 4
2180 04:44:50.061329 DQ_TRACK_CA_EN = 0
2181 04:44:50.064462 CA_PICK = 1200
2182 04:44:50.064937 CA_MCKIO = 1200
2183 04:44:50.067714 MCKIO_SEMI = 0
2184 04:44:50.071058 PLL_FREQ = 2366
2185 04:44:50.074390 DQ_UI_PI_RATIO = 32
2186 04:44:50.077918 CA_UI_PI_RATIO = 0
2187 04:44:50.081085 ===================================
2188 04:44:50.084657 ===================================
2189 04:44:50.087603 memory_type:LPDDR4
2190 04:44:50.088146 GP_NUM : 10
2191 04:44:50.091294 SRAM_EN : 1
2192 04:44:50.091765 MD32_EN : 0
2193 04:44:50.094186 ===================================
2194 04:44:50.097635 [ANA_INIT] >>>>>>>>>>>>>>
2195 04:44:50.101130 <<<<<< [CONFIGURE PHASE]: ANA_TX
2196 04:44:50.104300 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2197 04:44:50.107511 ===================================
2198 04:44:50.110962 data_rate = 2400,PCW = 0X5b00
2199 04:44:50.114507 ===================================
2200 04:44:50.118175 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2201 04:44:50.121187 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 04:44:50.127931 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 04:44:50.134154 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2204 04:44:50.138027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2205 04:44:50.141427 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2206 04:44:50.142040 [ANA_INIT] flow start
2207 04:44:50.144402 [ANA_INIT] PLL >>>>>>>>
2208 04:44:50.147664 [ANA_INIT] PLL <<<<<<<<
2209 04:44:50.148134 [ANA_INIT] MIDPI >>>>>>>>
2210 04:44:50.150989 [ANA_INIT] MIDPI <<<<<<<<
2211 04:44:50.154635 [ANA_INIT] DLL >>>>>>>>
2212 04:44:50.155105 [ANA_INIT] DLL <<<<<<<<
2213 04:44:50.157712 [ANA_INIT] flow end
2214 04:44:50.161096 ============ LP4 DIFF to SE enter ============
2215 04:44:50.164634 ============ LP4 DIFF to SE exit ============
2216 04:44:50.167822 [ANA_INIT] <<<<<<<<<<<<<
2217 04:44:50.171016 [Flow] Enable top DCM control >>>>>
2218 04:44:50.174694 [Flow] Enable top DCM control <<<<<
2219 04:44:50.178230 Enable DLL master slave shuffle
2220 04:44:50.184463 ==============================================================
2221 04:44:50.185030 Gating Mode config
2222 04:44:50.190994 ==============================================================
2223 04:44:50.191502 Config description:
2224 04:44:50.201441 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2225 04:44:50.207383 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2226 04:44:50.214512 SELPH_MODE 0: By rank 1: By Phase
2227 04:44:50.217897 ==============================================================
2228 04:44:50.221290 GAT_TRACK_EN = 1
2229 04:44:50.224200 RX_GATING_MODE = 2
2230 04:44:50.227820 RX_GATING_TRACK_MODE = 2
2231 04:44:50.231194 SELPH_MODE = 1
2232 04:44:50.234556 PICG_EARLY_EN = 1
2233 04:44:50.238113 VALID_LAT_VALUE = 1
2234 04:44:50.241205 ==============================================================
2235 04:44:50.244737 Enter into Gating configuration >>>>
2236 04:44:50.248174 Exit from Gating configuration <<<<
2237 04:44:50.251672 Enter into DVFS_PRE_config >>>>>
2238 04:44:50.264663 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2239 04:44:50.268229 Exit from DVFS_PRE_config <<<<<
2240 04:44:50.268798 Enter into PICG configuration >>>>
2241 04:44:50.271513 Exit from PICG configuration <<<<
2242 04:44:50.274897 [RX_INPUT] configuration >>>>>
2243 04:44:50.278425 [RX_INPUT] configuration <<<<<
2244 04:44:50.284614 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2245 04:44:50.288321 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2246 04:44:50.294660 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 04:44:50.301106 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 04:44:50.307878 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 04:44:50.314764 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 04:44:50.317931 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2251 04:44:50.321239 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2252 04:44:50.324519 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2253 04:44:50.331604 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2254 04:44:50.334841 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2255 04:44:50.338508 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2256 04:44:50.341617 ===================================
2257 04:44:50.345271 LPDDR4 DRAM CONFIGURATION
2258 04:44:50.348190 ===================================
2259 04:44:50.348762 EX_ROW_EN[0] = 0x0
2260 04:44:50.351696 EX_ROW_EN[1] = 0x0
2261 04:44:50.352265 LP4Y_EN = 0x0
2262 04:44:50.354995 WORK_FSP = 0x0
2263 04:44:50.358274 WL = 0x4
2264 04:44:50.358845 RL = 0x4
2265 04:44:50.361433 BL = 0x2
2266 04:44:50.361898 RPST = 0x0
2267 04:44:50.365019 RD_PRE = 0x0
2268 04:44:50.365486 WR_PRE = 0x1
2269 04:44:50.368139 WR_PST = 0x0
2270 04:44:50.368705 DBI_WR = 0x0
2271 04:44:50.371411 DBI_RD = 0x0
2272 04:44:50.371876 OTF = 0x1
2273 04:44:50.374940 ===================================
2274 04:44:50.378042 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2275 04:44:50.385075 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2276 04:44:50.388196 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2277 04:44:50.391541 ===================================
2278 04:44:50.394832 LPDDR4 DRAM CONFIGURATION
2279 04:44:50.398141 ===================================
2280 04:44:50.398606 EX_ROW_EN[0] = 0x10
2281 04:44:50.401311 EX_ROW_EN[1] = 0x0
2282 04:44:50.401775 LP4Y_EN = 0x0
2283 04:44:50.404508 WORK_FSP = 0x0
2284 04:44:50.404972 WL = 0x4
2285 04:44:50.407967 RL = 0x4
2286 04:44:50.408430 BL = 0x2
2287 04:44:50.411684 RPST = 0x0
2288 04:44:50.412247 RD_PRE = 0x0
2289 04:44:50.414824 WR_PRE = 0x1
2290 04:44:50.415289 WR_PST = 0x0
2291 04:44:50.418305 DBI_WR = 0x0
2292 04:44:50.421490 DBI_RD = 0x0
2293 04:44:50.422033 OTF = 0x1
2294 04:44:50.424694 ===================================
2295 04:44:50.431618 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2296 04:44:50.432073 ==
2297 04:44:50.434991 Dram Type= 6, Freq= 0, CH_0, rank 0
2298 04:44:50.438388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2299 04:44:50.438845 ==
2300 04:44:50.441370 [Duty_Offset_Calibration]
2301 04:44:50.441823 B0:2 B1:0 CA:1
2302 04:44:50.442216
2303 04:44:50.444687 [DutyScan_Calibration_Flow] k_type=0
2304 04:44:50.454761
2305 04:44:50.455314 ==CLK 0==
2306 04:44:50.457998 Final CLK duty delay cell = -4
2307 04:44:50.461557 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2308 04:44:50.465025 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2309 04:44:50.468433 [-4] AVG Duty = 4953%(X100)
2310 04:44:50.468984
2311 04:44:50.471763 CH0 CLK Duty spec in!! Max-Min= 156%
2312 04:44:50.474962 [DutyScan_Calibration_Flow] ====Done====
2313 04:44:50.475513
2314 04:44:50.478406 [DutyScan_Calibration_Flow] k_type=1
2315 04:44:50.493734
2316 04:44:50.494352 ==DQS 0 ==
2317 04:44:50.496666 Final DQS duty delay cell = 0
2318 04:44:50.500156 [0] MAX Duty = 5187%(X100), DQS PI = 30
2319 04:44:50.503343 [0] MIN Duty = 4938%(X100), DQS PI = 0
2320 04:44:50.503859 [0] AVG Duty = 5062%(X100)
2321 04:44:50.507171
2322 04:44:50.507642 ==DQS 1 ==
2323 04:44:50.510229 Final DQS duty delay cell = -4
2324 04:44:50.513709 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2325 04:44:50.516867 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2326 04:44:50.520347 [-4] AVG Duty = 5031%(X100)
2327 04:44:50.520861
2328 04:44:50.523676 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2329 04:44:50.524132
2330 04:44:50.526917 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2331 04:44:50.530154 [DutyScan_Calibration_Flow] ====Done====
2332 04:44:50.530664
2333 04:44:50.533343 [DutyScan_Calibration_Flow] k_type=3
2334 04:44:50.550069
2335 04:44:50.550486 ==DQM 0 ==
2336 04:44:50.553382 Final DQM duty delay cell = 0
2337 04:44:50.557034 [0] MAX Duty = 5062%(X100), DQS PI = 24
2338 04:44:50.560359 [0] MIN Duty = 4813%(X100), DQS PI = 2
2339 04:44:50.560772 [0] AVG Duty = 4937%(X100)
2340 04:44:50.563786
2341 04:44:50.564197 ==DQM 1 ==
2342 04:44:50.566731 Final DQM duty delay cell = 0
2343 04:44:50.569914 [0] MAX Duty = 5187%(X100), DQS PI = 48
2344 04:44:50.573473 [0] MIN Duty = 5000%(X100), DQS PI = 22
2345 04:44:50.573579 [0] AVG Duty = 5093%(X100)
2346 04:44:50.576530
2347 04:44:50.579967 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2348 04:44:50.580048
2349 04:44:50.583397 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2350 04:44:50.586567 [DutyScan_Calibration_Flow] ====Done====
2351 04:44:50.586648
2352 04:44:50.590017 [DutyScan_Calibration_Flow] k_type=2
2353 04:44:50.606656
2354 04:44:50.606737 ==DQ 0 ==
2355 04:44:50.609891 Final DQ duty delay cell = -4
2356 04:44:50.613109 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2357 04:44:50.616377 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2358 04:44:50.619862 [-4] AVG Duty = 4968%(X100)
2359 04:44:50.619945
2360 04:44:50.620011 ==DQ 1 ==
2361 04:44:50.623246 Final DQ duty delay cell = 4
2362 04:44:50.626429 [4] MAX Duty = 5093%(X100), DQS PI = 4
2363 04:44:50.629775 [4] MIN Duty = 5031%(X100), DQS PI = 0
2364 04:44:50.629858 [4] AVG Duty = 5062%(X100)
2365 04:44:50.629924
2366 04:44:50.633521 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2367 04:44:50.633604
2368 04:44:50.636391 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2369 04:44:50.643212 [DutyScan_Calibration_Flow] ====Done====
2370 04:44:50.643295 ==
2371 04:44:50.646490 Dram Type= 6, Freq= 0, CH_1, rank 0
2372 04:44:50.649892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2373 04:44:50.650017 ==
2374 04:44:50.653366 [Duty_Offset_Calibration]
2375 04:44:50.653449 B0:0 B1:-1 CA:2
2376 04:44:50.653514
2377 04:44:50.656608 [DutyScan_Calibration_Flow] k_type=0
2378 04:44:50.666481
2379 04:44:50.666564 ==CLK 0==
2380 04:44:50.669925 Final CLK duty delay cell = 0
2381 04:44:50.673366 [0] MAX Duty = 5156%(X100), DQS PI = 10
2382 04:44:50.676492 [0] MIN Duty = 4938%(X100), DQS PI = 44
2383 04:44:50.676575 [0] AVG Duty = 5047%(X100)
2384 04:44:50.679910
2385 04:44:50.679993 CH1 CLK Duty spec in!! Max-Min= 218%
2386 04:44:50.686794 [DutyScan_Calibration_Flow] ====Done====
2387 04:44:50.686877
2388 04:44:50.689744 [DutyScan_Calibration_Flow] k_type=1
2389 04:44:50.706060
2390 04:44:50.706144 ==DQS 0 ==
2391 04:44:50.709336 Final DQS duty delay cell = 0
2392 04:44:50.712547 [0] MAX Duty = 5093%(X100), DQS PI = 24
2393 04:44:50.715913 [0] MIN Duty = 4969%(X100), DQS PI = 0
2394 04:44:50.715996 [0] AVG Duty = 5031%(X100)
2395 04:44:50.719202
2396 04:44:50.719283 ==DQS 1 ==
2397 04:44:50.722455 Final DQS duty delay cell = 0
2398 04:44:50.725895 [0] MAX Duty = 5156%(X100), DQS PI = 0
2399 04:44:50.729338 [0] MIN Duty = 4813%(X100), DQS PI = 36
2400 04:44:50.729421 [0] AVG Duty = 4984%(X100)
2401 04:44:50.732509
2402 04:44:50.736228 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2403 04:44:50.736311
2404 04:44:50.739399 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2405 04:44:50.742696 [DutyScan_Calibration_Flow] ====Done====
2406 04:44:50.742783
2407 04:44:50.745893 [DutyScan_Calibration_Flow] k_type=3
2408 04:44:50.763152
2409 04:44:50.763237 ==DQM 0 ==
2410 04:44:50.766557 Final DQM duty delay cell = 4
2411 04:44:50.769974 [4] MAX Duty = 5093%(X100), DQS PI = 6
2412 04:44:50.772942 [4] MIN Duty = 4938%(X100), DQS PI = 48
2413 04:44:50.776539 [4] AVG Duty = 5015%(X100)
2414 04:44:50.776625
2415 04:44:50.776711 ==DQM 1 ==
2416 04:44:50.779877 Final DQM duty delay cell = 0
2417 04:44:50.782819 [0] MAX Duty = 5249%(X100), DQS PI = 0
2418 04:44:50.786739 [0] MIN Duty = 4875%(X100), DQS PI = 38
2419 04:44:50.786825 [0] AVG Duty = 5062%(X100)
2420 04:44:50.789787
2421 04:44:50.793139 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2422 04:44:50.793240
2423 04:44:50.796515 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2424 04:44:50.800055 [DutyScan_Calibration_Flow] ====Done====
2425 04:44:50.800141
2426 04:44:50.803055 [DutyScan_Calibration_Flow] k_type=2
2427 04:44:50.819300
2428 04:44:50.819386 ==DQ 0 ==
2429 04:44:50.823054 Final DQ duty delay cell = 0
2430 04:44:50.826219 [0] MAX Duty = 5031%(X100), DQS PI = 18
2431 04:44:50.829682 [0] MIN Duty = 4938%(X100), DQS PI = 0
2432 04:44:50.829769 [0] AVG Duty = 4984%(X100)
2433 04:44:50.832593
2434 04:44:50.832679 ==DQ 1 ==
2435 04:44:50.836246 Final DQ duty delay cell = 0
2436 04:44:50.839585 [0] MAX Duty = 5031%(X100), DQS PI = 2
2437 04:44:50.842761 [0] MIN Duty = 4813%(X100), DQS PI = 36
2438 04:44:50.842847 [0] AVG Duty = 4922%(X100)
2439 04:44:50.842934
2440 04:44:50.846196 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2441 04:44:50.846283
2442 04:44:50.849353 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2443 04:44:50.856158 [DutyScan_Calibration_Flow] ====Done====
2444 04:44:50.859177 nWR fixed to 30
2445 04:44:50.859264 [ModeRegInit_LP4] CH0 RK0
2446 04:44:50.862534 [ModeRegInit_LP4] CH0 RK1
2447 04:44:50.865951 [ModeRegInit_LP4] CH1 RK0
2448 04:44:50.866038 [ModeRegInit_LP4] CH1 RK1
2449 04:44:50.869391 match AC timing 7
2450 04:44:50.872931 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2451 04:44:50.876392 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2452 04:44:50.882818 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2453 04:44:50.885700 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2454 04:44:50.892707 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2455 04:44:50.892793 ==
2456 04:44:50.896224 Dram Type= 6, Freq= 0, CH_0, rank 0
2457 04:44:50.899369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2458 04:44:50.899456 ==
2459 04:44:50.905952 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2460 04:44:50.909449 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2461 04:44:50.919471 [CA 0] Center 38 (7~69) winsize 63
2462 04:44:50.922668 [CA 1] Center 38 (8~69) winsize 62
2463 04:44:50.925937 [CA 2] Center 35 (4~66) winsize 63
2464 04:44:50.929367 [CA 3] Center 35 (4~66) winsize 63
2465 04:44:50.932594 [CA 4] Center 34 (4~65) winsize 62
2466 04:44:50.935978 [CA 5] Center 33 (3~63) winsize 61
2467 04:44:50.936063
2468 04:44:50.939660 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2469 04:44:50.939745
2470 04:44:50.942697 [CATrainingPosCal] consider 1 rank data
2471 04:44:50.945973 u2DelayCellTimex100 = 270/100 ps
2472 04:44:50.949409 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2473 04:44:50.952641 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2474 04:44:50.959196 CA2 delay=35 (4~66),Diff = 2 PI (9 cell)
2475 04:44:50.962762 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2476 04:44:50.966105 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2477 04:44:50.969196 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2478 04:44:50.969281
2479 04:44:50.972636 CA PerBit enable=1, Macro0, CA PI delay=33
2480 04:44:50.972720
2481 04:44:50.976212 [CBTSetCACLKResult] CA Dly = 33
2482 04:44:50.976297 CS Dly: 6 (0~37)
2483 04:44:50.976381 ==
2484 04:44:50.979184 Dram Type= 6, Freq= 0, CH_0, rank 1
2485 04:44:50.986231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2486 04:44:50.986345 ==
2487 04:44:50.989645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2488 04:44:50.996102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2489 04:44:51.004997 [CA 0] Center 39 (8~70) winsize 63
2490 04:44:51.008396 [CA 1] Center 38 (8~69) winsize 62
2491 04:44:51.011844 [CA 2] Center 35 (5~66) winsize 62
2492 04:44:51.014900 [CA 3] Center 35 (5~66) winsize 62
2493 04:44:51.017936 [CA 4] Center 34 (4~65) winsize 62
2494 04:44:51.021350 [CA 5] Center 34 (4~64) winsize 61
2495 04:44:51.021508
2496 04:44:51.024837 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2497 04:44:51.024922
2498 04:44:51.028210 [CATrainingPosCal] consider 2 rank data
2499 04:44:51.031410 u2DelayCellTimex100 = 270/100 ps
2500 04:44:51.034892 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2501 04:44:51.041920 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2502 04:44:51.045328 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2503 04:44:51.048136 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2504 04:44:51.051353 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2505 04:44:51.055065 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2506 04:44:51.055151
2507 04:44:51.058499 CA PerBit enable=1, Macro0, CA PI delay=33
2508 04:44:51.058586
2509 04:44:51.061742 [CBTSetCACLKResult] CA Dly = 33
2510 04:44:51.061828 CS Dly: 7 (0~39)
2511 04:44:51.061932
2512 04:44:51.064835 ----->DramcWriteLeveling(PI) begin...
2513 04:44:51.068313 ==
2514 04:44:51.071542 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 04:44:51.074842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 04:44:51.074928 ==
2517 04:44:51.078228 Write leveling (Byte 0): 34 => 34
2518 04:44:51.081735 Write leveling (Byte 1): 31 => 31
2519 04:44:51.084702 DramcWriteLeveling(PI) end<-----
2520 04:44:51.084787
2521 04:44:51.084873 ==
2522 04:44:51.088118 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 04:44:51.091589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 04:44:51.091675 ==
2525 04:44:51.095069 [Gating] SW mode calibration
2526 04:44:51.101545 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2527 04:44:51.105028 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2528 04:44:51.111836 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2529 04:44:51.114833 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2530 04:44:51.118271 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 04:44:51.125330 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 04:44:51.128319 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 04:44:51.131762 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 04:44:51.138430 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2535 04:44:51.141675 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2536 04:44:51.144957 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
2537 04:44:51.151686 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 04:44:51.154904 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 04:44:51.158536 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 04:44:51.165174 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 04:44:51.168183 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 04:44:51.171689 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2543 04:44:51.178330 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2544 04:44:51.181629 1 1 0 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
2545 04:44:51.185024 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2546 04:44:51.191545 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 04:44:51.195030 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 04:44:51.198603 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 04:44:51.201973 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 04:44:51.208508 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 04:44:51.211937 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2552 04:44:51.215327 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2553 04:44:51.221713 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 04:44:51.225205 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 04:44:51.228862 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 04:44:51.235267 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 04:44:51.238827 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 04:44:51.242182 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 04:44:51.248784 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 04:44:51.252075 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 04:44:51.255641 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 04:44:51.258964 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 04:44:51.265400 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 04:44:51.268890 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 04:44:51.272205 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 04:44:51.278936 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 04:44:51.281828 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2568 04:44:51.285611 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2569 04:44:51.288617 Total UI for P1: 0, mck2ui 16
2570 04:44:51.292111 best dqsien dly found for B0: ( 1, 3, 28)
2571 04:44:51.298541 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 04:44:51.298625 Total UI for P1: 0, mck2ui 16
2573 04:44:51.305074 best dqsien dly found for B1: ( 1, 3, 30)
2574 04:44:51.308500 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2575 04:44:51.312060 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2576 04:44:51.312142
2577 04:44:51.315397 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2578 04:44:51.318587 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2579 04:44:51.322067 [Gating] SW calibration Done
2580 04:44:51.322150 ==
2581 04:44:51.325528 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 04:44:51.328585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 04:44:51.328668 ==
2584 04:44:51.332021 RX Vref Scan: 0
2585 04:44:51.332103
2586 04:44:51.332168 RX Vref 0 -> 0, step: 1
2587 04:44:51.332227
2588 04:44:51.335298 RX Delay -40 -> 252, step: 8
2589 04:44:51.338773 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2590 04:44:51.345223 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2591 04:44:51.348580 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2592 04:44:51.352214 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2593 04:44:51.355315 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2594 04:44:51.358510 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2595 04:44:51.365190 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2596 04:44:51.368597 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2597 04:44:51.372143 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2598 04:44:51.375203 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2599 04:44:51.378730 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2600 04:44:51.385350 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2601 04:44:51.388526 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2602 04:44:51.392072 iDelay=200, Bit 13, Center 111 (48 ~ 175) 128
2603 04:44:51.395538 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2604 04:44:51.398511 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2605 04:44:51.398594 ==
2606 04:44:51.402171 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 04:44:51.408807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 04:44:51.408891 ==
2609 04:44:51.408956 DQS Delay:
2610 04:44:51.411825 DQS0 = 0, DQS1 = 0
2611 04:44:51.411908 DQM Delay:
2612 04:44:51.415379 DQM0 = 122, DQM1 = 110
2613 04:44:51.415461 DQ Delay:
2614 04:44:51.418765 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2615 04:44:51.422067 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2616 04:44:51.425504 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2617 04:44:51.428545 DQ12 =115, DQ13 =111, DQ14 =123, DQ15 =119
2618 04:44:51.428628
2619 04:44:51.428693
2620 04:44:51.428753 ==
2621 04:44:51.432079 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 04:44:51.435542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 04:44:51.438972 ==
2624 04:44:51.439054
2625 04:44:51.439120
2626 04:44:51.439180 TX Vref Scan disable
2627 04:44:51.442049 == TX Byte 0 ==
2628 04:44:51.445474 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2629 04:44:51.448989 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2630 04:44:51.452382 == TX Byte 1 ==
2631 04:44:51.455800 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2632 04:44:51.459164 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2633 04:44:51.459247 ==
2634 04:44:51.462358 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 04:44:51.468613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 04:44:51.468696 ==
2637 04:44:51.479636 TX Vref=22, minBit 7, minWin=22, winSum=399
2638 04:44:51.482739 TX Vref=24, minBit 0, minWin=24, winSum=411
2639 04:44:51.486201 TX Vref=26, minBit 1, minWin=24, winSum=414
2640 04:44:51.489743 TX Vref=28, minBit 0, minWin=24, winSum=418
2641 04:44:51.492726 TX Vref=30, minBit 7, minWin=24, winSum=417
2642 04:44:51.496496 TX Vref=32, minBit 1, minWin=25, winSum=416
2643 04:44:51.502939 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 32
2644 04:44:51.503023
2645 04:44:51.506514 Final TX Range 1 Vref 32
2646 04:44:51.506598
2647 04:44:51.506663 ==
2648 04:44:51.509433 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 04:44:51.512880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 04:44:51.512963 ==
2651 04:44:51.513029
2652 04:44:51.513088
2653 04:44:51.516385 TX Vref Scan disable
2654 04:44:51.519868 == TX Byte 0 ==
2655 04:44:51.522843 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2656 04:44:51.526424 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2657 04:44:51.529423 == TX Byte 1 ==
2658 04:44:51.532954 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2659 04:44:51.536537 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2660 04:44:51.536620
2661 04:44:51.539940 [DATLAT]
2662 04:44:51.540022 Freq=1200, CH0 RK0
2663 04:44:51.540089
2664 04:44:51.542922 DATLAT Default: 0xd
2665 04:44:51.543006 0, 0xFFFF, sum = 0
2666 04:44:51.546022 1, 0xFFFF, sum = 0
2667 04:44:51.546107 2, 0xFFFF, sum = 0
2668 04:44:51.549524 3, 0xFFFF, sum = 0
2669 04:44:51.549608 4, 0xFFFF, sum = 0
2670 04:44:51.553013 5, 0xFFFF, sum = 0
2671 04:44:51.553098 6, 0xFFFF, sum = 0
2672 04:44:51.555962 7, 0xFFFF, sum = 0
2673 04:44:51.556046 8, 0xFFFF, sum = 0
2674 04:44:51.559401 9, 0xFFFF, sum = 0
2675 04:44:51.562670 10, 0xFFFF, sum = 0
2676 04:44:51.562754 11, 0xFFFF, sum = 0
2677 04:44:51.565995 12, 0x0, sum = 1
2678 04:44:51.566078 13, 0x0, sum = 2
2679 04:44:51.566144 14, 0x0, sum = 3
2680 04:44:51.569514 15, 0x0, sum = 4
2681 04:44:51.569611 best_step = 13
2682 04:44:51.569715
2683 04:44:51.572682 ==
2684 04:44:51.572765 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 04:44:51.579246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 04:44:51.579330 ==
2687 04:44:51.579395 RX Vref Scan: 1
2688 04:44:51.579454
2689 04:44:51.582917 Set Vref Range= 32 -> 127
2690 04:44:51.582999
2691 04:44:51.586067 RX Vref 32 -> 127, step: 1
2692 04:44:51.586186
2693 04:44:51.589805 RX Delay -13 -> 252, step: 4
2694 04:44:51.589918
2695 04:44:51.592893 Set Vref, RX VrefLevel [Byte0]: 32
2696 04:44:51.596163 [Byte1]: 32
2697 04:44:51.596246
2698 04:44:51.599409 Set Vref, RX VrefLevel [Byte0]: 33
2699 04:44:51.602769 [Byte1]: 33
2700 04:44:51.602852
2701 04:44:51.606198 Set Vref, RX VrefLevel [Byte0]: 34
2702 04:44:51.609167 [Byte1]: 34
2703 04:44:51.613633
2704 04:44:51.613715 Set Vref, RX VrefLevel [Byte0]: 35
2705 04:44:51.617114 [Byte1]: 35
2706 04:44:51.621544
2707 04:44:51.621627 Set Vref, RX VrefLevel [Byte0]: 36
2708 04:44:51.625029 [Byte1]: 36
2709 04:44:51.629398
2710 04:44:51.629480 Set Vref, RX VrefLevel [Byte0]: 37
2711 04:44:51.632730 [Byte1]: 37
2712 04:44:51.637090
2713 04:44:51.637187 Set Vref, RX VrefLevel [Byte0]: 38
2714 04:44:51.640553 [Byte1]: 38
2715 04:44:51.645119
2716 04:44:51.645232 Set Vref, RX VrefLevel [Byte0]: 39
2717 04:44:51.648521 [Byte1]: 39
2718 04:44:51.653045
2719 04:44:51.653158 Set Vref, RX VrefLevel [Byte0]: 40
2720 04:44:51.656519 [Byte1]: 40
2721 04:44:51.660986
2722 04:44:51.661069 Set Vref, RX VrefLevel [Byte0]: 41
2723 04:44:51.663870 [Byte1]: 41
2724 04:44:51.668556
2725 04:44:51.668638 Set Vref, RX VrefLevel [Byte0]: 42
2726 04:44:51.671953 [Byte1]: 42
2727 04:44:51.676400
2728 04:44:51.676489 Set Vref, RX VrefLevel [Byte0]: 43
2729 04:44:51.679941 [Byte1]: 43
2730 04:44:51.684618
2731 04:44:51.684701 Set Vref, RX VrefLevel [Byte0]: 44
2732 04:44:51.687805 [Byte1]: 44
2733 04:44:51.692196
2734 04:44:51.692308 Set Vref, RX VrefLevel [Byte0]: 45
2735 04:44:51.695467 [Byte1]: 45
2736 04:44:51.700052
2737 04:44:51.700164 Set Vref, RX VrefLevel [Byte0]: 46
2738 04:44:51.703774 [Byte1]: 46
2739 04:44:51.708150
2740 04:44:51.708233 Set Vref, RX VrefLevel [Byte0]: 47
2741 04:44:51.714597 [Byte1]: 47
2742 04:44:51.714681
2743 04:44:51.718159 Set Vref, RX VrefLevel [Byte0]: 48
2744 04:44:51.721487 [Byte1]: 48
2745 04:44:51.721570
2746 04:44:51.724517 Set Vref, RX VrefLevel [Byte0]: 49
2747 04:44:51.728023 [Byte1]: 49
2748 04:44:51.731936
2749 04:44:51.732019 Set Vref, RX VrefLevel [Byte0]: 50
2750 04:44:51.735195 [Byte1]: 50
2751 04:44:51.739682
2752 04:44:51.739764 Set Vref, RX VrefLevel [Byte0]: 51
2753 04:44:51.743066 [Byte1]: 51
2754 04:44:51.747543
2755 04:44:51.747625 Set Vref, RX VrefLevel [Byte0]: 52
2756 04:44:51.751005 [Byte1]: 52
2757 04:44:51.755505
2758 04:44:51.755587 Set Vref, RX VrefLevel [Byte0]: 53
2759 04:44:51.759010 [Byte1]: 53
2760 04:44:51.763350
2761 04:44:51.763433 Set Vref, RX VrefLevel [Byte0]: 54
2762 04:44:51.766856 [Byte1]: 54
2763 04:44:51.771117
2764 04:44:51.771198 Set Vref, RX VrefLevel [Byte0]: 55
2765 04:44:51.774444 [Byte1]: 55
2766 04:44:51.779250
2767 04:44:51.779332 Set Vref, RX VrefLevel [Byte0]: 56
2768 04:44:51.782183 [Byte1]: 56
2769 04:44:51.786850
2770 04:44:51.786933 Set Vref, RX VrefLevel [Byte0]: 57
2771 04:44:51.790273 [Byte1]: 57
2772 04:44:51.794877
2773 04:44:51.794960 Set Vref, RX VrefLevel [Byte0]: 58
2774 04:44:51.798412 [Byte1]: 58
2775 04:44:51.802556
2776 04:44:51.802638 Set Vref, RX VrefLevel [Byte0]: 59
2777 04:44:51.806129 [Byte1]: 59
2778 04:44:51.810703
2779 04:44:51.810786 Set Vref, RX VrefLevel [Byte0]: 60
2780 04:44:51.813871 [Byte1]: 60
2781 04:44:51.818653
2782 04:44:51.818739 Set Vref, RX VrefLevel [Byte0]: 61
2783 04:44:51.822158 [Byte1]: 61
2784 04:44:51.826561
2785 04:44:51.826644 Set Vref, RX VrefLevel [Byte0]: 62
2786 04:44:51.830046 [Byte1]: 62
2787 04:44:51.834577
2788 04:44:51.834658 Set Vref, RX VrefLevel [Byte0]: 63
2789 04:44:51.837781 [Byte1]: 63
2790 04:44:51.842286
2791 04:44:51.842367 Set Vref, RX VrefLevel [Byte0]: 64
2792 04:44:51.845627 [Byte1]: 64
2793 04:44:51.850164
2794 04:44:51.850266 Set Vref, RX VrefLevel [Byte0]: 65
2795 04:44:51.853545 [Byte1]: 65
2796 04:44:51.858052
2797 04:44:51.858133 Set Vref, RX VrefLevel [Byte0]: 66
2798 04:44:51.861592 [Byte1]: 66
2799 04:44:51.865933
2800 04:44:51.866045 Set Vref, RX VrefLevel [Byte0]: 67
2801 04:44:51.869402 [Byte1]: 67
2802 04:44:51.873763
2803 04:44:51.873844 Set Vref, RX VrefLevel [Byte0]: 68
2804 04:44:51.876986 [Byte1]: 68
2805 04:44:51.881579
2806 04:44:51.881660 Set Vref, RX VrefLevel [Byte0]: 69
2807 04:44:51.884932 [Byte1]: 69
2808 04:44:51.889533
2809 04:44:51.889614 Set Vref, RX VrefLevel [Byte0]: 70
2810 04:44:51.892752 [Byte1]: 70
2811 04:44:51.897612
2812 04:44:51.897694 Final RX Vref Byte 0 = 57 to rank0
2813 04:44:51.900745 Final RX Vref Byte 1 = 49 to rank0
2814 04:44:51.904390 Final RX Vref Byte 0 = 57 to rank1
2815 04:44:51.907772 Final RX Vref Byte 1 = 49 to rank1==
2816 04:44:51.910839 Dram Type= 6, Freq= 0, CH_0, rank 0
2817 04:44:51.917702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2818 04:44:51.917785 ==
2819 04:44:51.917849 DQS Delay:
2820 04:44:51.917909 DQS0 = 0, DQS1 = 0
2821 04:44:51.920809 DQM Delay:
2822 04:44:51.920891 DQM0 = 122, DQM1 = 109
2823 04:44:51.924072 DQ Delay:
2824 04:44:51.927487 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =118
2825 04:44:51.931108 DQ4 =124, DQ5 =116, DQ6 =130, DQ7 =128
2826 04:44:51.933926 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =108
2827 04:44:51.937498 DQ12 =114, DQ13 =110, DQ14 =122, DQ15 =116
2828 04:44:51.937580
2829 04:44:51.937644
2830 04:44:51.944218 [DQSOSCAuto] RK0, (LSB)MR18= 0x906, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2831 04:44:51.947789 CH0 RK0: MR19=404, MR18=906
2832 04:44:51.954242 CH0_RK0: MR19=0x404, MR18=0x906, DQSOSC=406, MR23=63, INC=39, DEC=26
2833 04:44:51.954324
2834 04:44:51.957604 ----->DramcWriteLeveling(PI) begin...
2835 04:44:51.957687 ==
2836 04:44:51.960654 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 04:44:51.964120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2838 04:44:51.964202 ==
2839 04:44:51.967574 Write leveling (Byte 0): 34 => 34
2840 04:44:51.971050 Write leveling (Byte 1): 32 => 32
2841 04:44:51.974429 DramcWriteLeveling(PI) end<-----
2842 04:44:51.974511
2843 04:44:51.974604 ==
2844 04:44:51.977785 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 04:44:51.981129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 04:44:51.984611 ==
2847 04:44:51.984719 [Gating] SW mode calibration
2848 04:44:51.994184 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2849 04:44:51.997679 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2850 04:44:52.000975 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2851 04:44:52.008168 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 04:44:52.011319 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 04:44:52.014499 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 04:44:52.021488 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 04:44:52.024659 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 04:44:52.027784 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2857 04:44:52.034526 0 15 28 | B1->B0 | 3131 3131 | 1 0 | (1 0) (0 1)
2858 04:44:52.037955 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2859 04:44:52.040992 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 04:44:52.044299 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 04:44:52.051207 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 04:44:52.054686 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 04:44:52.057763 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 04:44:52.064728 1 0 24 | B1->B0 | 2625 2a2a | 1 1 | (0 0) (0 0)
2865 04:44:52.067783 1 0 28 | B1->B0 | 3737 3d3d | 0 1 | (0 0) (0 0)
2866 04:44:52.071107 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 04:44:52.077553 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 04:44:52.081484 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 04:44:52.084482 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 04:44:52.091100 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 04:44:52.094586 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 04:44:52.097995 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2873 04:44:52.104437 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2874 04:44:52.108010 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2875 04:44:52.111628 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 04:44:52.118151 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 04:44:52.121307 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 04:44:52.124943 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 04:44:52.127732 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 04:44:52.134655 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 04:44:52.138004 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 04:44:52.141494 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 04:44:52.147853 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 04:44:52.151160 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 04:44:52.154612 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 04:44:52.161554 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 04:44:52.164969 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 04:44:52.167934 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2889 04:44:52.174974 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2890 04:44:52.177859 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 04:44:52.181255 Total UI for P1: 0, mck2ui 16
2892 04:44:52.184715 best dqsien dly found for B0: ( 1, 3, 26)
2893 04:44:52.188171 Total UI for P1: 0, mck2ui 16
2894 04:44:52.191609 best dqsien dly found for B1: ( 1, 3, 28)
2895 04:44:52.194756 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2896 04:44:52.198222 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2897 04:44:52.198305
2898 04:44:52.201172 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2899 04:44:52.204629 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2900 04:44:52.208182 [Gating] SW calibration Done
2901 04:44:52.208265 ==
2902 04:44:52.211683 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 04:44:52.214861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 04:44:52.214945 ==
2905 04:44:52.218428 RX Vref Scan: 0
2906 04:44:52.218511
2907 04:44:52.221180 RX Vref 0 -> 0, step: 1
2908 04:44:52.221263
2909 04:44:52.221329 RX Delay -40 -> 252, step: 8
2910 04:44:52.228165 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2911 04:44:52.231359 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2912 04:44:52.234564 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2913 04:44:52.238110 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2914 04:44:52.241331 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2915 04:44:52.248302 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2916 04:44:52.251208 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2917 04:44:52.254649 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2918 04:44:52.258104 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2919 04:44:52.261175 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2920 04:44:52.268189 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2921 04:44:52.271692 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2922 04:44:52.274591 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2923 04:44:52.278063 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2924 04:44:52.281263 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2925 04:44:52.288151 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2926 04:44:52.288226 ==
2927 04:44:52.291262 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 04:44:52.294720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 04:44:52.294806 ==
2930 04:44:52.294869 DQS Delay:
2931 04:44:52.298241 DQS0 = 0, DQS1 = 0
2932 04:44:52.298323 DQM Delay:
2933 04:44:52.301279 DQM0 = 120, DQM1 = 108
2934 04:44:52.301376 DQ Delay:
2935 04:44:52.304712 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2936 04:44:52.308302 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2937 04:44:52.311200 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2938 04:44:52.314681 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2939 04:44:52.314764
2940 04:44:52.314828
2941 04:44:52.314887 ==
2942 04:44:52.318229 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 04:44:52.324879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 04:44:52.324961 ==
2945 04:44:52.325027
2946 04:44:52.325088
2947 04:44:52.325146 TX Vref Scan disable
2948 04:44:52.328827 == TX Byte 0 ==
2949 04:44:52.332162 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2950 04:44:52.336085 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2951 04:44:52.338584 == TX Byte 1 ==
2952 04:44:52.341828 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2953 04:44:52.348254 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2954 04:44:52.348337 ==
2955 04:44:52.351764 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 04:44:52.355199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 04:44:52.355288 ==
2958 04:44:52.366397 TX Vref=22, minBit 7, minWin=24, winSum=412
2959 04:44:52.369917 TX Vref=24, minBit 7, minWin=24, winSum=415
2960 04:44:52.373382 TX Vref=26, minBit 0, minWin=25, winSum=417
2961 04:44:52.376427 TX Vref=28, minBit 1, minWin=24, winSum=419
2962 04:44:52.379954 TX Vref=30, minBit 1, minWin=25, winSum=417
2963 04:44:52.383173 TX Vref=32, minBit 1, minWin=25, winSum=419
2964 04:44:52.389933 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 32
2965 04:44:52.390064
2966 04:44:52.393052 Final TX Range 1 Vref 32
2967 04:44:52.393136
2968 04:44:52.393203 ==
2969 04:44:52.396647 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 04:44:52.399958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 04:44:52.400046 ==
2972 04:44:52.400113
2973 04:44:52.400172
2974 04:44:52.403213 TX Vref Scan disable
2975 04:44:52.406731 == TX Byte 0 ==
2976 04:44:52.409770 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2977 04:44:52.413248 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2978 04:44:52.416568 == TX Byte 1 ==
2979 04:44:52.420110 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2980 04:44:52.423034 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2981 04:44:52.423118
2982 04:44:52.426382 [DATLAT]
2983 04:44:52.426465 Freq=1200, CH0 RK1
2984 04:44:52.426531
2985 04:44:52.429640 DATLAT Default: 0xd
2986 04:44:52.429724 0, 0xFFFF, sum = 0
2987 04:44:52.432996 1, 0xFFFF, sum = 0
2988 04:44:52.433082 2, 0xFFFF, sum = 0
2989 04:44:52.436425 3, 0xFFFF, sum = 0
2990 04:44:52.436510 4, 0xFFFF, sum = 0
2991 04:44:52.440127 5, 0xFFFF, sum = 0
2992 04:44:52.440212 6, 0xFFFF, sum = 0
2993 04:44:52.443494 7, 0xFFFF, sum = 0
2994 04:44:52.443580 8, 0xFFFF, sum = 0
2995 04:44:52.447026 9, 0xFFFF, sum = 0
2996 04:44:52.447112 10, 0xFFFF, sum = 0
2997 04:44:52.449727 11, 0xFFFF, sum = 0
2998 04:44:52.453234 12, 0x0, sum = 1
2999 04:44:52.453319 13, 0x0, sum = 2
3000 04:44:52.453386 14, 0x0, sum = 3
3001 04:44:52.456815 15, 0x0, sum = 4
3002 04:44:52.456899 best_step = 13
3003 04:44:52.456966
3004 04:44:52.457026 ==
3005 04:44:52.459834 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 04:44:52.466687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 04:44:52.466771 ==
3008 04:44:52.466838 RX Vref Scan: 0
3009 04:44:52.466898
3010 04:44:52.470033 RX Vref 0 -> 0, step: 1
3011 04:44:52.470116
3012 04:44:52.473168 RX Delay -21 -> 252, step: 4
3013 04:44:52.476604 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3014 04:44:52.480080 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3015 04:44:52.486918 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3016 04:44:52.490354 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3017 04:44:52.493274 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3018 04:44:52.496872 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3019 04:44:52.500234 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3020 04:44:52.506574 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3021 04:44:52.509971 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3022 04:44:52.513478 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3023 04:44:52.516866 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3024 04:44:52.520408 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3025 04:44:52.523404 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3026 04:44:52.530113 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3027 04:44:52.533491 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3028 04:44:52.537007 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3029 04:44:52.537091 ==
3030 04:44:52.540493 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 04:44:52.543627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 04:44:52.546938 ==
3033 04:44:52.547021 DQS Delay:
3034 04:44:52.547088 DQS0 = 0, DQS1 = 0
3035 04:44:52.550229 DQM Delay:
3036 04:44:52.550313 DQM0 = 119, DQM1 = 108
3037 04:44:52.553654 DQ Delay:
3038 04:44:52.556789 DQ0 =116, DQ1 =122, DQ2 =116, DQ3 =114
3039 04:44:52.560262 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3040 04:44:52.563597 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3041 04:44:52.566823 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =114
3042 04:44:52.566907
3043 04:44:52.566973
3044 04:44:52.573751 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 405 ps
3045 04:44:52.577125 CH0 RK1: MR19=403, MR18=DF5
3046 04:44:52.583460 CH0_RK1: MR19=0x403, MR18=0xDF5, DQSOSC=405, MR23=63, INC=39, DEC=26
3047 04:44:52.587263 [RxdqsGatingPostProcess] freq 1200
3048 04:44:52.590128 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3049 04:44:52.593654 best DQS0 dly(2T, 0.5T) = (0, 11)
3050 04:44:52.596678 best DQS1 dly(2T, 0.5T) = (0, 11)
3051 04:44:52.600171 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3052 04:44:52.603622 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3053 04:44:52.607062 best DQS0 dly(2T, 0.5T) = (0, 11)
3054 04:44:52.610547 best DQS1 dly(2T, 0.5T) = (0, 11)
3055 04:44:52.613859 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3056 04:44:52.616874 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3057 04:44:52.620318 Pre-setting of DQS Precalculation
3058 04:44:52.623765 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3059 04:44:52.623850 ==
3060 04:44:52.627234 Dram Type= 6, Freq= 0, CH_1, rank 0
3061 04:44:52.634196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 04:44:52.634307 ==
3063 04:44:52.637126 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3064 04:44:52.643710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3065 04:44:52.652224 [CA 0] Center 37 (7~68) winsize 62
3066 04:44:52.655740 [CA 1] Center 37 (7~68) winsize 62
3067 04:44:52.659218 [CA 2] Center 35 (5~65) winsize 61
3068 04:44:52.662427 [CA 3] Center 34 (4~65) winsize 62
3069 04:44:52.665821 [CA 4] Center 34 (4~64) winsize 61
3070 04:44:52.669092 [CA 5] Center 33 (3~64) winsize 62
3071 04:44:52.669183
3072 04:44:52.672377 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3073 04:44:52.672460
3074 04:44:52.675863 [CATrainingPosCal] consider 1 rank data
3075 04:44:52.679362 u2DelayCellTimex100 = 270/100 ps
3076 04:44:52.682303 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3077 04:44:52.685706 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3078 04:44:52.689269 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3079 04:44:52.696157 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3080 04:44:52.699084 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3081 04:44:52.702495 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3082 04:44:52.702581
3083 04:44:52.705917 CA PerBit enable=1, Macro0, CA PI delay=33
3084 04:44:52.706041
3085 04:44:52.709402 [CBTSetCACLKResult] CA Dly = 33
3086 04:44:52.709509 CS Dly: 5 (0~36)
3087 04:44:52.709577 ==
3088 04:44:52.712813 Dram Type= 6, Freq= 0, CH_1, rank 1
3089 04:44:52.719603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 04:44:52.719688 ==
3091 04:44:52.722601 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3092 04:44:52.729595 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3093 04:44:52.737915 [CA 0] Center 38 (8~68) winsize 61
3094 04:44:52.741313 [CA 1] Center 38 (7~69) winsize 63
3095 04:44:52.744889 [CA 2] Center 35 (5~66) winsize 62
3096 04:44:52.748413 [CA 3] Center 35 (5~65) winsize 61
3097 04:44:52.751282 [CA 4] Center 34 (4~64) winsize 61
3098 04:44:52.754552 [CA 5] Center 34 (4~64) winsize 61
3099 04:44:52.754658
3100 04:44:52.757908 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3101 04:44:52.758010
3102 04:44:52.761446 [CATrainingPosCal] consider 2 rank data
3103 04:44:52.764875 u2DelayCellTimex100 = 270/100 ps
3104 04:44:52.768161 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3105 04:44:52.771588 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3106 04:44:52.778092 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3107 04:44:52.781538 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3108 04:44:52.784986 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3109 04:44:52.787919 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3110 04:44:52.788018
3111 04:44:52.791364 CA PerBit enable=1, Macro0, CA PI delay=34
3112 04:44:52.791447
3113 04:44:52.794789 [CBTSetCACLKResult] CA Dly = 34
3114 04:44:52.794886 CS Dly: 6 (0~39)
3115 04:44:52.794986
3116 04:44:52.798235 ----->DramcWriteLeveling(PI) begin...
3117 04:44:52.798335 ==
3118 04:44:52.801287 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 04:44:52.808404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 04:44:52.808486 ==
3121 04:44:52.811513 Write leveling (Byte 0): 24 => 24
3122 04:44:52.815004 Write leveling (Byte 1): 27 => 27
3123 04:44:52.815087 DramcWriteLeveling(PI) end<-----
3124 04:44:52.818342
3125 04:44:52.818425 ==
3126 04:44:52.821665 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 04:44:52.825131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 04:44:52.825267 ==
3129 04:44:52.828593 [Gating] SW mode calibration
3130 04:44:52.834941 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3131 04:44:52.838380 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3132 04:44:52.844910 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 04:44:52.848180 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 04:44:52.851433 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 04:44:52.858260 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 04:44:52.861473 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 04:44:52.865101 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3138 04:44:52.871723 0 15 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (1 0)
3139 04:44:52.874880 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3140 04:44:52.878486 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 04:44:52.885198 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 04:44:52.888763 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 04:44:52.891589 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 04:44:52.894992 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 04:44:52.901516 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 04:44:52.904937 1 0 24 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
3147 04:44:52.908334 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 04:44:52.915265 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 04:44:52.918192 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 04:44:52.922089 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 04:44:52.928777 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 04:44:52.931823 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 04:44:52.935176 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3154 04:44:52.941610 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3155 04:44:52.944992 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 04:44:52.948432 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 04:44:52.955153 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 04:44:52.958581 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 04:44:52.961781 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 04:44:52.965490 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 04:44:52.971929 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 04:44:52.975380 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 04:44:52.978791 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 04:44:52.985571 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 04:44:52.988508 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 04:44:52.991795 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 04:44:52.998711 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 04:44:53.002179 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 04:44:53.005175 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3170 04:44:53.012162 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3171 04:44:53.015058 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3172 04:44:53.018619 Total UI for P1: 0, mck2ui 16
3173 04:44:53.021997 best dqsien dly found for B0: ( 1, 3, 22)
3174 04:44:53.025403 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 04:44:53.028520 Total UI for P1: 0, mck2ui 16
3176 04:44:53.031905 best dqsien dly found for B1: ( 1, 3, 26)
3177 04:44:53.035278 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3178 04:44:53.038753 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3179 04:44:53.038836
3180 04:44:53.042319 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3181 04:44:53.048533 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3182 04:44:53.048644 [Gating] SW calibration Done
3183 04:44:53.048738 ==
3184 04:44:53.051990 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 04:44:53.058845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 04:44:53.058969 ==
3187 04:44:53.059036 RX Vref Scan: 0
3188 04:44:53.059098
3189 04:44:53.062212 RX Vref 0 -> 0, step: 1
3190 04:44:53.062295
3191 04:44:53.065856 RX Delay -40 -> 252, step: 8
3192 04:44:53.068637 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3193 04:44:53.072104 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3194 04:44:53.075559 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3195 04:44:53.082073 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3196 04:44:53.085512 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3197 04:44:53.088608 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3198 04:44:53.092071 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3199 04:44:53.095323 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3200 04:44:53.098552 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3201 04:44:53.105424 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3202 04:44:53.108962 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3203 04:44:53.111972 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3204 04:44:53.115342 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3205 04:44:53.118891 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3206 04:44:53.125326 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3207 04:44:53.128722 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3208 04:44:53.128806 ==
3209 04:44:53.132033 Dram Type= 6, Freq= 0, CH_1, rank 0
3210 04:44:53.135800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3211 04:44:53.135885 ==
3212 04:44:53.138779 DQS Delay:
3213 04:44:53.138863 DQS0 = 0, DQS1 = 0
3214 04:44:53.138929 DQM Delay:
3215 04:44:53.142185 DQM0 = 119, DQM1 = 113
3216 04:44:53.142269 DQ Delay:
3217 04:44:53.145690 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3218 04:44:53.148654 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3219 04:44:53.152078 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3220 04:44:53.158768 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3221 04:44:53.158852
3222 04:44:53.158919
3223 04:44:53.158979 ==
3224 04:44:53.162207 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 04:44:53.165562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 04:44:53.165646 ==
3227 04:44:53.165712
3228 04:44:53.165772
3229 04:44:53.168794 TX Vref Scan disable
3230 04:44:53.168877 == TX Byte 0 ==
3231 04:44:53.175403 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3232 04:44:53.178781 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3233 04:44:53.178865 == TX Byte 1 ==
3234 04:44:53.185663 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3235 04:44:53.189159 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3236 04:44:53.189242 ==
3237 04:44:53.192472 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 04:44:53.195475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 04:44:53.195560 ==
3240 04:44:53.207990 TX Vref=22, minBit 10, minWin=24, winSum=406
3241 04:44:53.211498 TX Vref=24, minBit 3, minWin=24, winSum=409
3242 04:44:53.214989 TX Vref=26, minBit 9, minWin=25, winSum=417
3243 04:44:53.217825 TX Vref=28, minBit 10, minWin=25, winSum=421
3244 04:44:53.221300 TX Vref=30, minBit 10, minWin=25, winSum=424
3245 04:44:53.228273 TX Vref=32, minBit 9, minWin=25, winSum=420
3246 04:44:53.231693 [TxChooseVref] Worse bit 10, Min win 25, Win sum 424, Final Vref 30
3247 04:44:53.231777
3248 04:44:53.234594 Final TX Range 1 Vref 30
3249 04:44:53.234678
3250 04:44:53.234744 ==
3251 04:44:53.238365 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 04:44:53.241207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 04:44:53.241291 ==
3254 04:44:53.244646
3255 04:44:53.244747
3256 04:44:53.244814 TX Vref Scan disable
3257 04:44:53.248238 == TX Byte 0 ==
3258 04:44:53.251260 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3259 04:44:53.254608 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3260 04:44:53.258112 == TX Byte 1 ==
3261 04:44:53.261276 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3262 04:44:53.264509 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3263 04:44:53.268264
3264 04:44:53.268348 [DATLAT]
3265 04:44:53.268414 Freq=1200, CH1 RK0
3266 04:44:53.268475
3267 04:44:53.271574 DATLAT Default: 0xd
3268 04:44:53.271657 0, 0xFFFF, sum = 0
3269 04:44:53.274734 1, 0xFFFF, sum = 0
3270 04:44:53.274819 2, 0xFFFF, sum = 0
3271 04:44:53.277989 3, 0xFFFF, sum = 0
3272 04:44:53.278074 4, 0xFFFF, sum = 0
3273 04:44:53.281458 5, 0xFFFF, sum = 0
3274 04:44:53.284493 6, 0xFFFF, sum = 0
3275 04:44:53.284578 7, 0xFFFF, sum = 0
3276 04:44:53.287911 8, 0xFFFF, sum = 0
3277 04:44:53.287995 9, 0xFFFF, sum = 0
3278 04:44:53.291384 10, 0xFFFF, sum = 0
3279 04:44:53.291469 11, 0xFFFF, sum = 0
3280 04:44:53.294880 12, 0x0, sum = 1
3281 04:44:53.294964 13, 0x0, sum = 2
3282 04:44:53.298250 14, 0x0, sum = 3
3283 04:44:53.298335 15, 0x0, sum = 4
3284 04:44:53.298402 best_step = 13
3285 04:44:53.298462
3286 04:44:53.301559 ==
3287 04:44:53.301642 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 04:44:53.308421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 04:44:53.308505 ==
3290 04:44:53.308571 RX Vref Scan: 1
3291 04:44:53.308632
3292 04:44:53.311594 Set Vref Range= 32 -> 127
3293 04:44:53.311675
3294 04:44:53.314949 RX Vref 32 -> 127, step: 1
3295 04:44:53.315030
3296 04:44:53.318312 RX Delay -13 -> 252, step: 4
3297 04:44:53.318394
3298 04:44:53.321746 Set Vref, RX VrefLevel [Byte0]: 32
3299 04:44:53.325195 [Byte1]: 32
3300 04:44:53.325277
3301 04:44:53.328193 Set Vref, RX VrefLevel [Byte0]: 33
3302 04:44:53.331588 [Byte1]: 33
3303 04:44:53.331669
3304 04:44:53.335090 Set Vref, RX VrefLevel [Byte0]: 34
3305 04:44:53.338463 [Byte1]: 34
3306 04:44:53.342442
3307 04:44:53.342522 Set Vref, RX VrefLevel [Byte0]: 35
3308 04:44:53.345708 [Byte1]: 35
3309 04:44:53.350235
3310 04:44:53.350315 Set Vref, RX VrefLevel [Byte0]: 36
3311 04:44:53.353605 [Byte1]: 36
3312 04:44:53.358136
3313 04:44:53.358217 Set Vref, RX VrefLevel [Byte0]: 37
3314 04:44:53.361629 [Byte1]: 37
3315 04:44:53.366060
3316 04:44:53.366140 Set Vref, RX VrefLevel [Byte0]: 38
3317 04:44:53.369440 [Byte1]: 38
3318 04:44:53.373807
3319 04:44:53.373887 Set Vref, RX VrefLevel [Byte0]: 39
3320 04:44:53.377032 [Byte1]: 39
3321 04:44:53.381714
3322 04:44:53.381794 Set Vref, RX VrefLevel [Byte0]: 40
3323 04:44:53.385091 [Byte1]: 40
3324 04:44:53.389575
3325 04:44:53.389655 Set Vref, RX VrefLevel [Byte0]: 41
3326 04:44:53.393183 [Byte1]: 41
3327 04:44:53.397498
3328 04:44:53.397606 Set Vref, RX VrefLevel [Byte0]: 42
3329 04:44:53.400901 [Byte1]: 42
3330 04:44:53.405471
3331 04:44:53.405572 Set Vref, RX VrefLevel [Byte0]: 43
3332 04:44:53.408773 [Byte1]: 43
3333 04:44:53.413488
3334 04:44:53.413588 Set Vref, RX VrefLevel [Byte0]: 44
3335 04:44:53.416478 [Byte1]: 44
3336 04:44:53.421257
3337 04:44:53.421371 Set Vref, RX VrefLevel [Byte0]: 45
3338 04:44:53.424670 [Byte1]: 45
3339 04:44:53.429153
3340 04:44:53.429263 Set Vref, RX VrefLevel [Byte0]: 46
3341 04:44:53.432119 [Byte1]: 46
3342 04:44:53.437087
3343 04:44:53.437193 Set Vref, RX VrefLevel [Byte0]: 47
3344 04:44:53.440132 [Byte1]: 47
3345 04:44:53.444883
3346 04:44:53.444993 Set Vref, RX VrefLevel [Byte0]: 48
3347 04:44:53.448238 [Byte1]: 48
3348 04:44:53.452657
3349 04:44:53.452765 Set Vref, RX VrefLevel [Byte0]: 49
3350 04:44:53.455971 [Byte1]: 49
3351 04:44:53.460398
3352 04:44:53.460498 Set Vref, RX VrefLevel [Byte0]: 50
3353 04:44:53.463986 [Byte1]: 50
3354 04:44:53.468497
3355 04:44:53.468594 Set Vref, RX VrefLevel [Byte0]: 51
3356 04:44:53.471805 [Byte1]: 51
3357 04:44:53.476470
3358 04:44:53.476546 Set Vref, RX VrefLevel [Byte0]: 52
3359 04:44:53.479853 [Byte1]: 52
3360 04:44:53.484500
3361 04:44:53.484602 Set Vref, RX VrefLevel [Byte0]: 53
3362 04:44:53.487343 [Byte1]: 53
3363 04:44:53.492323
3364 04:44:53.492421 Set Vref, RX VrefLevel [Byte0]: 54
3365 04:44:53.495388 [Byte1]: 54
3366 04:44:53.499922
3367 04:44:53.500034 Set Vref, RX VrefLevel [Byte0]: 55
3368 04:44:53.503419 [Byte1]: 55
3369 04:44:53.507944
3370 04:44:53.508041 Set Vref, RX VrefLevel [Byte0]: 56
3371 04:44:53.511347 [Byte1]: 56
3372 04:44:53.515807
3373 04:44:53.515913 Set Vref, RX VrefLevel [Byte0]: 57
3374 04:44:53.519426 [Byte1]: 57
3375 04:44:53.523734
3376 04:44:53.523831 Set Vref, RX VrefLevel [Byte0]: 58
3377 04:44:53.526972 [Byte1]: 58
3378 04:44:53.531529
3379 04:44:53.531601 Set Vref, RX VrefLevel [Byte0]: 59
3380 04:44:53.534958 [Byte1]: 59
3381 04:44:53.539483
3382 04:44:53.539588 Set Vref, RX VrefLevel [Byte0]: 60
3383 04:44:53.542965 [Byte1]: 60
3384 04:44:53.547525
3385 04:44:53.547623 Set Vref, RX VrefLevel [Byte0]: 61
3386 04:44:53.550909 [Byte1]: 61
3387 04:44:53.555220
3388 04:44:53.555324 Set Vref, RX VrefLevel [Byte0]: 62
3389 04:44:53.558706 [Byte1]: 62
3390 04:44:53.563282
3391 04:44:53.563379 Set Vref, RX VrefLevel [Byte0]: 63
3392 04:44:53.566739 [Byte1]: 63
3393 04:44:53.571221
3394 04:44:53.571326 Set Vref, RX VrefLevel [Byte0]: 64
3395 04:44:53.574234 [Byte1]: 64
3396 04:44:53.578942
3397 04:44:53.579049 Set Vref, RX VrefLevel [Byte0]: 65
3398 04:44:53.582357 [Byte1]: 65
3399 04:44:53.587138
3400 04:44:53.587241 Set Vref, RX VrefLevel [Byte0]: 66
3401 04:44:53.589862 [Byte1]: 66
3402 04:44:53.594861
3403 04:44:53.594963 Set Vref, RX VrefLevel [Byte0]: 67
3404 04:44:53.598380 [Byte1]: 67
3405 04:44:53.602772
3406 04:44:53.602881 Final RX Vref Byte 0 = 54 to rank0
3407 04:44:53.606376 Final RX Vref Byte 1 = 48 to rank0
3408 04:44:53.609267 Final RX Vref Byte 0 = 54 to rank1
3409 04:44:53.612874 Final RX Vref Byte 1 = 48 to rank1==
3410 04:44:53.615921 Dram Type= 6, Freq= 0, CH_1, rank 0
3411 04:44:53.619247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3412 04:44:53.622939 ==
3413 04:44:53.623023 DQS Delay:
3414 04:44:53.623089 DQS0 = 0, DQS1 = 0
3415 04:44:53.626107 DQM Delay:
3416 04:44:53.626191 DQM0 = 119, DQM1 = 111
3417 04:44:53.629408 DQ Delay:
3418 04:44:53.632869 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =120
3419 04:44:53.635949 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =118
3420 04:44:53.639291 DQ8 =98, DQ9 =100, DQ10 =114, DQ11 =104
3421 04:44:53.642732 DQ12 =122, DQ13 =116, DQ14 =118, DQ15 =116
3422 04:44:53.642818
3423 04:44:53.642905
3424 04:44:53.649247 [DQSOSCAuto] RK0, (LSB)MR18= 0xff13, (MSB)MR19= 0x304, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3425 04:44:53.652661 CH1 RK0: MR19=304, MR18=FF13
3426 04:44:53.659554 CH1_RK0: MR19=0x304, MR18=0xFF13, DQSOSC=402, MR23=63, INC=40, DEC=27
3427 04:44:53.659641
3428 04:44:53.662423 ----->DramcWriteLeveling(PI) begin...
3429 04:44:53.662510 ==
3430 04:44:53.665932 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 04:44:53.669385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 04:44:53.672364 ==
3433 04:44:53.672451 Write leveling (Byte 0): 24 => 24
3434 04:44:53.675840 Write leveling (Byte 1): 30 => 30
3435 04:44:53.679252 DramcWriteLeveling(PI) end<-----
3436 04:44:53.679339
3437 04:44:53.679424 ==
3438 04:44:53.682663 Dram Type= 6, Freq= 0, CH_1, rank 1
3439 04:44:53.689226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3440 04:44:53.689313 ==
3441 04:44:53.689399 [Gating] SW mode calibration
3442 04:44:53.699440 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3443 04:44:53.702390 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3444 04:44:53.705820 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3445 04:44:53.712712 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 04:44:53.716019 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 04:44:53.719420 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 04:44:53.725801 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 04:44:53.729299 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 04:44:53.732913 0 15 24 | B1->B0 | 2727 3434 | 0 1 | (1 0) (1 0)
3451 04:44:53.739377 0 15 28 | B1->B0 | 2323 2c2c | 0 1 | (1 0) (0 0)
3452 04:44:53.742754 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 04:44:53.746315 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 04:44:53.752829 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 04:44:53.756429 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 04:44:53.759381 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 04:44:53.766118 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3458 04:44:53.769589 1 0 24 | B1->B0 | 4242 2929 | 0 0 | (1 1) (0 0)
3459 04:44:53.772922 1 0 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
3460 04:44:53.776444 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 04:44:53.782688 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 04:44:53.786158 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 04:44:53.789462 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 04:44:53.796009 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 04:44:53.799331 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 04:44:53.802814 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3467 04:44:53.809335 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3468 04:44:53.812890 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 04:44:53.815778 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 04:44:53.822555 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 04:44:53.825801 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 04:44:53.829453 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 04:44:53.836061 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 04:44:53.839055 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 04:44:53.842497 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 04:44:53.849392 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 04:44:53.852466 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 04:44:53.856023 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 04:44:53.862329 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 04:44:53.865557 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 04:44:53.868975 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 04:44:53.875876 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3483 04:44:53.879267 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3484 04:44:53.882270 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 04:44:53.885668 Total UI for P1: 0, mck2ui 16
3486 04:44:53.888953 best dqsien dly found for B0: ( 1, 3, 26)
3487 04:44:53.892172 Total UI for P1: 0, mck2ui 16
3488 04:44:53.895586 best dqsien dly found for B1: ( 1, 3, 26)
3489 04:44:53.898811 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3490 04:44:53.902087 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3491 04:44:53.902170
3492 04:44:53.908948 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3493 04:44:53.911904 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3494 04:44:53.911987 [Gating] SW calibration Done
3495 04:44:53.915511 ==
3496 04:44:53.919066 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 04:44:53.922052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3498 04:44:53.922135 ==
3499 04:44:53.922201 RX Vref Scan: 0
3500 04:44:53.922261
3501 04:44:53.925451 RX Vref 0 -> 0, step: 1
3502 04:44:53.925534
3503 04:44:53.928635 RX Delay -40 -> 252, step: 8
3504 04:44:53.931900 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3505 04:44:53.935156 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3506 04:44:53.938867 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3507 04:44:53.945181 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3508 04:44:53.948520 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3509 04:44:53.952002 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3510 04:44:53.955493 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3511 04:44:53.958577 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3512 04:44:53.965383 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3513 04:44:53.968818 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3514 04:44:53.972184 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3515 04:44:53.975058 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3516 04:44:53.978658 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3517 04:44:53.985423 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3518 04:44:53.988432 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3519 04:44:53.991895 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3520 04:44:53.992011 ==
3521 04:44:53.995223 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 04:44:53.998453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 04:44:54.001850 ==
3524 04:44:54.002002 DQS Delay:
3525 04:44:54.002070 DQS0 = 0, DQS1 = 0
3526 04:44:54.005006 DQM Delay:
3527 04:44:54.005104 DQM0 = 120, DQM1 = 112
3528 04:44:54.008265 DQ Delay:
3529 04:44:54.011857 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3530 04:44:54.014855 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =115
3531 04:44:54.018547 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =103
3532 04:44:54.021736 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =123
3533 04:44:54.021844
3534 04:44:54.021945
3535 04:44:54.022045 ==
3536 04:44:54.025204 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 04:44:54.028273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 04:44:54.028376 ==
3539 04:44:54.028472
3540 04:44:54.031534
3541 04:44:54.031612 TX Vref Scan disable
3542 04:44:54.034966 == TX Byte 0 ==
3543 04:44:54.038107 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3544 04:44:54.041689 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3545 04:44:54.045011 == TX Byte 1 ==
3546 04:44:54.048433 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3547 04:44:54.051502 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3548 04:44:54.051575 ==
3549 04:44:54.055014 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 04:44:54.061524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 04:44:54.061606 ==
3552 04:44:54.072418 TX Vref=22, minBit 1, minWin=25, winSum=417
3553 04:44:54.075622 TX Vref=24, minBit 1, minWin=25, winSum=418
3554 04:44:54.079134 TX Vref=26, minBit 3, minWin=25, winSum=424
3555 04:44:54.082112 TX Vref=28, minBit 7, minWin=26, winSum=429
3556 04:44:54.085592 TX Vref=30, minBit 1, minWin=26, winSum=429
3557 04:44:54.089150 TX Vref=32, minBit 1, minWin=26, winSum=426
3558 04:44:54.095523 [TxChooseVref] Worse bit 7, Min win 26, Win sum 429, Final Vref 28
3559 04:44:54.095598
3560 04:44:54.098738 Final TX Range 1 Vref 28
3561 04:44:54.098815
3562 04:44:54.098896 ==
3563 04:44:54.102108 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 04:44:54.105331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 04:44:54.105411 ==
3566 04:44:54.105474
3567 04:44:54.108681
3568 04:44:54.108752 TX Vref Scan disable
3569 04:44:54.112345 == TX Byte 0 ==
3570 04:44:54.115601 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3571 04:44:54.119063 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3572 04:44:54.122036 == TX Byte 1 ==
3573 04:44:54.125690 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3574 04:44:54.129109 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3575 04:44:54.129183
3576 04:44:54.132098 [DATLAT]
3577 04:44:54.132166 Freq=1200, CH1 RK1
3578 04:44:54.132234
3579 04:44:54.135383 DATLAT Default: 0xd
3580 04:44:54.135451 0, 0xFFFF, sum = 0
3581 04:44:54.138861 1, 0xFFFF, sum = 0
3582 04:44:54.138964 2, 0xFFFF, sum = 0
3583 04:44:54.142317 3, 0xFFFF, sum = 0
3584 04:44:54.142395 4, 0xFFFF, sum = 0
3585 04:44:54.145479 5, 0xFFFF, sum = 0
3586 04:44:54.145559 6, 0xFFFF, sum = 0
3587 04:44:54.148823 7, 0xFFFF, sum = 0
3588 04:44:54.152257 8, 0xFFFF, sum = 0
3589 04:44:54.152329 9, 0xFFFF, sum = 0
3590 04:44:54.155173 10, 0xFFFF, sum = 0
3591 04:44:54.155245 11, 0xFFFF, sum = 0
3592 04:44:54.158621 12, 0x0, sum = 1
3593 04:44:54.158700 13, 0x0, sum = 2
3594 04:44:54.162164 14, 0x0, sum = 3
3595 04:44:54.162234 15, 0x0, sum = 4
3596 04:44:54.162296 best_step = 13
3597 04:44:54.162361
3598 04:44:54.165104 ==
3599 04:44:54.168707 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 04:44:54.172236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 04:44:54.172311 ==
3602 04:44:54.172373 RX Vref Scan: 0
3603 04:44:54.172439
3604 04:44:54.175132 RX Vref 0 -> 0, step: 1
3605 04:44:54.175201
3606 04:44:54.178511 RX Delay -13 -> 252, step: 4
3607 04:44:54.182099 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3608 04:44:54.188451 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3609 04:44:54.191939 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3610 04:44:54.195495 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3611 04:44:54.198435 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3612 04:44:54.202153 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3613 04:44:54.205423 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3614 04:44:54.212198 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3615 04:44:54.215485 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3616 04:44:54.218865 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3617 04:44:54.221897 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3618 04:44:54.225178 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3619 04:44:54.232155 iDelay=195, Bit 12, Center 120 (55 ~ 186) 132
3620 04:44:54.235155 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3621 04:44:54.238600 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3622 04:44:54.241710 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3623 04:44:54.241779 ==
3624 04:44:54.245103 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 04:44:54.251693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 04:44:54.251771 ==
3627 04:44:54.251836 DQS Delay:
3628 04:44:54.255350 DQS0 = 0, DQS1 = 0
3629 04:44:54.255426 DQM Delay:
3630 04:44:54.258334 DQM0 = 119, DQM1 = 112
3631 04:44:54.258409 DQ Delay:
3632 04:44:54.261785 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3633 04:44:54.265247 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3634 04:44:54.268775 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3635 04:44:54.271748 DQ12 =120, DQ13 =118, DQ14 =120, DQ15 =120
3636 04:44:54.271819
3637 04:44:54.271886
3638 04:44:54.282138 [DQSOSCAuto] RK1, (LSB)MR18= 0x5ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 408 ps
3639 04:44:54.282232 CH1 RK1: MR19=403, MR18=5EA
3640 04:44:54.288554 CH1_RK1: MR19=0x403, MR18=0x5EA, DQSOSC=408, MR23=63, INC=39, DEC=26
3641 04:44:54.291950 [RxdqsGatingPostProcess] freq 1200
3642 04:44:54.298500 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3643 04:44:54.301502 best DQS0 dly(2T, 0.5T) = (0, 11)
3644 04:44:54.304802 best DQS1 dly(2T, 0.5T) = (0, 11)
3645 04:44:54.308260 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3646 04:44:54.311671 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3647 04:44:54.314855 best DQS0 dly(2T, 0.5T) = (0, 11)
3648 04:44:54.314947 best DQS1 dly(2T, 0.5T) = (0, 11)
3649 04:44:54.318153 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3650 04:44:54.321568 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3651 04:44:54.325100 Pre-setting of DQS Precalculation
3652 04:44:54.331528 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3653 04:44:54.338350 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3654 04:44:54.344778 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3655 04:44:54.344865
3656 04:44:54.344951
3657 04:44:54.348349 [Calibration Summary] 2400 Mbps
3658 04:44:54.348436 CH 0, Rank 0
3659 04:44:54.351612 SW Impedance : PASS
3660 04:44:54.354922 DUTY Scan : NO K
3661 04:44:54.355008 ZQ Calibration : PASS
3662 04:44:54.358094 Jitter Meter : NO K
3663 04:44:54.361512 CBT Training : PASS
3664 04:44:54.361596 Write leveling : PASS
3665 04:44:54.365054 RX DQS gating : PASS
3666 04:44:54.367991 RX DQ/DQS(RDDQC) : PASS
3667 04:44:54.368074 TX DQ/DQS : PASS
3668 04:44:54.371480 RX DATLAT : PASS
3669 04:44:54.375030 RX DQ/DQS(Engine): PASS
3670 04:44:54.375114 TX OE : NO K
3671 04:44:54.378443 All Pass.
3672 04:44:54.378528
3673 04:44:54.378614 CH 0, Rank 1
3674 04:44:54.381442 SW Impedance : PASS
3675 04:44:54.381528 DUTY Scan : NO K
3676 04:44:54.384957 ZQ Calibration : PASS
3677 04:44:54.388165 Jitter Meter : NO K
3678 04:44:54.388251 CBT Training : PASS
3679 04:44:54.391502 Write leveling : PASS
3680 04:44:54.391595 RX DQS gating : PASS
3681 04:44:54.395003 RX DQ/DQS(RDDQC) : PASS
3682 04:44:54.398574 TX DQ/DQS : PASS
3683 04:44:54.398660 RX DATLAT : PASS
3684 04:44:54.401494 RX DQ/DQS(Engine): PASS
3685 04:44:54.404983 TX OE : NO K
3686 04:44:54.405069 All Pass.
3687 04:44:54.405155
3688 04:44:54.405235 CH 1, Rank 0
3689 04:44:54.408348 SW Impedance : PASS
3690 04:44:54.411560 DUTY Scan : NO K
3691 04:44:54.411647 ZQ Calibration : PASS
3692 04:44:54.414934 Jitter Meter : NO K
3693 04:44:54.418338 CBT Training : PASS
3694 04:44:54.418424 Write leveling : PASS
3695 04:44:54.421706 RX DQS gating : PASS
3696 04:44:54.425063 RX DQ/DQS(RDDQC) : PASS
3697 04:44:54.425150 TX DQ/DQS : PASS
3698 04:44:54.428353 RX DATLAT : PASS
3699 04:44:54.428439 RX DQ/DQS(Engine): PASS
3700 04:44:54.431742 TX OE : NO K
3701 04:44:54.431828 All Pass.
3702 04:44:54.431914
3703 04:44:54.434717 CH 1, Rank 1
3704 04:44:54.434803 SW Impedance : PASS
3705 04:44:54.438314 DUTY Scan : NO K
3706 04:44:54.441690 ZQ Calibration : PASS
3707 04:44:54.441776 Jitter Meter : NO K
3708 04:44:54.444706 CBT Training : PASS
3709 04:44:54.448083 Write leveling : PASS
3710 04:44:54.448169 RX DQS gating : PASS
3711 04:44:54.451284 RX DQ/DQS(RDDQC) : PASS
3712 04:44:54.454637 TX DQ/DQS : PASS
3713 04:44:54.454724 RX DATLAT : PASS
3714 04:44:54.458315 RX DQ/DQS(Engine): PASS
3715 04:44:54.461534 TX OE : NO K
3716 04:44:54.461624 All Pass.
3717 04:44:54.461710
3718 04:44:54.464963 DramC Write-DBI off
3719 04:44:54.465049 PER_BANK_REFRESH: Hybrid Mode
3720 04:44:54.467912 TX_TRACKING: ON
3721 04:44:54.474713 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3722 04:44:54.481288 [FAST_K] Save calibration result to emmc
3723 04:44:54.484150 dramc_set_vcore_voltage set vcore to 650000
3724 04:44:54.484235 Read voltage for 600, 5
3725 04:44:54.487639 Vio18 = 0
3726 04:44:54.487725 Vcore = 650000
3727 04:44:54.487811 Vdram = 0
3728 04:44:54.491103 Vddq = 0
3729 04:44:54.491189 Vmddr = 0
3730 04:44:54.494408 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3731 04:44:54.500905 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3732 04:44:54.504529 MEM_TYPE=3, freq_sel=19
3733 04:44:54.507698 sv_algorithm_assistance_LP4_1600
3734 04:44:54.510905 ============ PULL DRAM RESETB DOWN ============
3735 04:44:54.514173 ========== PULL DRAM RESETB DOWN end =========
3736 04:44:54.520746 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3737 04:44:54.524053 ===================================
3738 04:44:54.524137 LPDDR4 DRAM CONFIGURATION
3739 04:44:54.527487 ===================================
3740 04:44:54.530422 EX_ROW_EN[0] = 0x0
3741 04:44:54.530505 EX_ROW_EN[1] = 0x0
3742 04:44:54.534196 LP4Y_EN = 0x0
3743 04:44:54.537179 WORK_FSP = 0x0
3744 04:44:54.537263 WL = 0x2
3745 04:44:54.540555 RL = 0x2
3746 04:44:54.540639 BL = 0x2
3747 04:44:54.543556 RPST = 0x0
3748 04:44:54.543639 RD_PRE = 0x0
3749 04:44:54.547021 WR_PRE = 0x1
3750 04:44:54.547104 WR_PST = 0x0
3751 04:44:54.550408 DBI_WR = 0x0
3752 04:44:54.550491 DBI_RD = 0x0
3753 04:44:54.553723 OTF = 0x1
3754 04:44:54.557261 ===================================
3755 04:44:54.560138 ===================================
3756 04:44:54.560222 ANA top config
3757 04:44:54.563738 ===================================
3758 04:44:54.567007 DLL_ASYNC_EN = 0
3759 04:44:54.570343 ALL_SLAVE_EN = 1
3760 04:44:54.573396 NEW_RANK_MODE = 1
3761 04:44:54.573481 DLL_IDLE_MODE = 1
3762 04:44:54.576942 LP45_APHY_COMB_EN = 1
3763 04:44:54.580433 TX_ODT_DIS = 1
3764 04:44:54.583264 NEW_8X_MODE = 1
3765 04:44:54.586792 ===================================
3766 04:44:54.590250 ===================================
3767 04:44:54.590351 data_rate = 1200
3768 04:44:54.593206 CKR = 1
3769 04:44:54.596589 DQ_P2S_RATIO = 8
3770 04:44:54.600260 ===================================
3771 04:44:54.603228 CA_P2S_RATIO = 8
3772 04:44:54.606855 DQ_CA_OPEN = 0
3773 04:44:54.610215 DQ_SEMI_OPEN = 0
3774 04:44:54.610299 CA_SEMI_OPEN = 0
3775 04:44:54.613317 CA_FULL_RATE = 0
3776 04:44:54.616614 DQ_CKDIV4_EN = 1
3777 04:44:54.619519 CA_CKDIV4_EN = 1
3778 04:44:54.623128 CA_PREDIV_EN = 0
3779 04:44:54.626491 PH8_DLY = 0
3780 04:44:54.629800 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3781 04:44:54.629884 DQ_AAMCK_DIV = 4
3782 04:44:54.633176 CA_AAMCK_DIV = 4
3783 04:44:54.636505 CA_ADMCK_DIV = 4
3784 04:44:54.639702 DQ_TRACK_CA_EN = 0
3785 04:44:54.643169 CA_PICK = 600
3786 04:44:54.646174 CA_MCKIO = 600
3787 04:44:54.646258 MCKIO_SEMI = 0
3788 04:44:54.649643 PLL_FREQ = 2288
3789 04:44:54.652602 DQ_UI_PI_RATIO = 32
3790 04:44:54.655960 CA_UI_PI_RATIO = 0
3791 04:44:54.659276 ===================================
3792 04:44:54.662854 ===================================
3793 04:44:54.665976 memory_type:LPDDR4
3794 04:44:54.666060 GP_NUM : 10
3795 04:44:54.669398 SRAM_EN : 1
3796 04:44:54.672675 MD32_EN : 0
3797 04:44:54.675941 ===================================
3798 04:44:54.676026 [ANA_INIT] >>>>>>>>>>>>>>
3799 04:44:54.679554 <<<<<< [CONFIGURE PHASE]: ANA_TX
3800 04:44:54.682497 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3801 04:44:54.686059 ===================================
3802 04:44:54.688931 data_rate = 1200,PCW = 0X5800
3803 04:44:54.692524 ===================================
3804 04:44:54.695993 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3805 04:44:54.702373 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3806 04:44:54.705868 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3807 04:44:54.712270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3808 04:44:54.715660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3809 04:44:54.719134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3810 04:44:54.722434 [ANA_INIT] flow start
3811 04:44:54.722518 [ANA_INIT] PLL >>>>>>>>
3812 04:44:54.725357 [ANA_INIT] PLL <<<<<<<<
3813 04:44:54.728775 [ANA_INIT] MIDPI >>>>>>>>
3814 04:44:54.728858 [ANA_INIT] MIDPI <<<<<<<<
3815 04:44:54.732522 [ANA_INIT] DLL >>>>>>>>
3816 04:44:54.735488 [ANA_INIT] flow end
3817 04:44:54.738877 ============ LP4 DIFF to SE enter ============
3818 04:44:54.742110 ============ LP4 DIFF to SE exit ============
3819 04:44:54.745451 [ANA_INIT] <<<<<<<<<<<<<
3820 04:44:54.748875 [Flow] Enable top DCM control >>>>>
3821 04:44:54.752265 [Flow] Enable top DCM control <<<<<
3822 04:44:54.755322 Enable DLL master slave shuffle
3823 04:44:54.759200 ==============================================================
3824 04:44:54.762445 Gating Mode config
3825 04:44:54.765804 ==============================================================
3826 04:44:54.768942 Config description:
3827 04:44:54.778610 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3828 04:44:54.785513 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3829 04:44:54.789044 SELPH_MODE 0: By rank 1: By Phase
3830 04:44:54.795584 ==============================================================
3831 04:44:54.798557 GAT_TRACK_EN = 1
3832 04:44:54.801980 RX_GATING_MODE = 2
3833 04:44:54.805469 RX_GATING_TRACK_MODE = 2
3834 04:44:54.808762 SELPH_MODE = 1
3835 04:44:54.812161 PICG_EARLY_EN = 1
3836 04:44:54.812245 VALID_LAT_VALUE = 1
3837 04:44:54.818790 ==============================================================
3838 04:44:54.822214 Enter into Gating configuration >>>>
3839 04:44:54.825179 Exit from Gating configuration <<<<
3840 04:44:54.828735 Enter into DVFS_PRE_config >>>>>
3841 04:44:54.838702 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3842 04:44:54.842250 Exit from DVFS_PRE_config <<<<<
3843 04:44:54.845097 Enter into PICG configuration >>>>
3844 04:44:54.848807 Exit from PICG configuration <<<<
3845 04:44:54.851803 [RX_INPUT] configuration >>>>>
3846 04:44:54.855187 [RX_INPUT] configuration <<<<<
3847 04:44:54.861634 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3848 04:44:54.865144 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3849 04:44:54.871556 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3850 04:44:54.878388 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3851 04:44:54.885232 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3852 04:44:54.891642 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3853 04:44:54.895021 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3854 04:44:54.898578 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3855 04:44:54.901632 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3856 04:44:54.908521 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3857 04:44:54.911764 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3858 04:44:54.915339 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3859 04:44:54.918304 ===================================
3860 04:44:54.921726 LPDDR4 DRAM CONFIGURATION
3861 04:44:54.925231 ===================================
3862 04:44:54.925314 EX_ROW_EN[0] = 0x0
3863 04:44:54.928763 EX_ROW_EN[1] = 0x0
3864 04:44:54.928845 LP4Y_EN = 0x0
3865 04:44:54.931843 WORK_FSP = 0x0
3866 04:44:54.931925 WL = 0x2
3867 04:44:54.935053 RL = 0x2
3868 04:44:54.938399 BL = 0x2
3869 04:44:54.938483 RPST = 0x0
3870 04:44:54.941738 RD_PRE = 0x0
3871 04:44:54.941821 WR_PRE = 0x1
3872 04:44:54.944944 WR_PST = 0x0
3873 04:44:54.945027 DBI_WR = 0x0
3874 04:44:54.948454 DBI_RD = 0x0
3875 04:44:54.948537 OTF = 0x1
3876 04:44:54.951808 ===================================
3877 04:44:54.954768 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3878 04:44:54.961687 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3879 04:44:54.964574 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3880 04:44:54.967991 ===================================
3881 04:44:54.971312 LPDDR4 DRAM CONFIGURATION
3882 04:44:54.975049 ===================================
3883 04:44:54.975134 EX_ROW_EN[0] = 0x10
3884 04:44:54.978384 EX_ROW_EN[1] = 0x0
3885 04:44:54.978468 LP4Y_EN = 0x0
3886 04:44:54.981442 WORK_FSP = 0x0
3887 04:44:54.981526 WL = 0x2
3888 04:44:54.984858 RL = 0x2
3889 04:44:54.984942 BL = 0x2
3890 04:44:54.988272 RPST = 0x0
3891 04:44:54.988366 RD_PRE = 0x0
3892 04:44:54.991676 WR_PRE = 0x1
3893 04:44:54.995163 WR_PST = 0x0
3894 04:44:54.995247 DBI_WR = 0x0
3895 04:44:54.998146 DBI_RD = 0x0
3896 04:44:54.998230 OTF = 0x1
3897 04:44:55.001518 ===================================
3898 04:44:55.007949 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3899 04:44:55.011469 nWR fixed to 30
3900 04:44:55.014839 [ModeRegInit_LP4] CH0 RK0
3901 04:44:55.014923 [ModeRegInit_LP4] CH0 RK1
3902 04:44:55.018327 [ModeRegInit_LP4] CH1 RK0
3903 04:44:55.021806 [ModeRegInit_LP4] CH1 RK1
3904 04:44:55.021889 match AC timing 17
3905 04:44:55.028264 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3906 04:44:55.031534 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3907 04:44:55.034950 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3908 04:44:55.041484 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3909 04:44:55.044954 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3910 04:44:55.045037 ==
3911 04:44:55.048148 Dram Type= 6, Freq= 0, CH_0, rank 0
3912 04:44:55.051489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3913 04:44:55.051573 ==
3914 04:44:55.058269 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3915 04:44:55.064703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3916 04:44:55.068331 [CA 0] Center 36 (6~67) winsize 62
3917 04:44:55.071700 [CA 1] Center 36 (6~67) winsize 62
3918 04:44:55.074898 [CA 2] Center 34 (4~65) winsize 62
3919 04:44:55.078308 [CA 3] Center 34 (4~65) winsize 62
3920 04:44:55.081553 [CA 4] Center 34 (3~65) winsize 63
3921 04:44:55.084854 [CA 5] Center 33 (3~64) winsize 62
3922 04:44:55.084937
3923 04:44:55.088444 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3924 04:44:55.088527
3925 04:44:55.091747 [CATrainingPosCal] consider 1 rank data
3926 04:44:55.095324 u2DelayCellTimex100 = 270/100 ps
3927 04:44:55.098142 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3928 04:44:55.101806 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3929 04:44:55.105203 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3930 04:44:55.108308 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3931 04:44:55.111635 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3932 04:44:55.115166 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3933 04:44:55.115248
3934 04:44:55.121734 CA PerBit enable=1, Macro0, CA PI delay=33
3935 04:44:55.121817
3936 04:44:55.121883 [CBTSetCACLKResult] CA Dly = 33
3937 04:44:55.124743 CS Dly: 4 (0~35)
3938 04:44:55.124826 ==
3939 04:44:55.128292 Dram Type= 6, Freq= 0, CH_0, rank 1
3940 04:44:55.131736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3941 04:44:55.131819 ==
3942 04:44:55.138139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3943 04:44:55.144734 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3944 04:44:55.148172 [CA 0] Center 36 (6~67) winsize 62
3945 04:44:55.151371 [CA 1] Center 37 (7~67) winsize 61
3946 04:44:55.154594 [CA 2] Center 35 (5~66) winsize 62
3947 04:44:55.158338 [CA 3] Center 34 (4~65) winsize 62
3948 04:44:55.161471 [CA 4] Center 34 (4~65) winsize 62
3949 04:44:55.164956 [CA 5] Center 34 (3~65) winsize 63
3950 04:44:55.165039
3951 04:44:55.167812 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3952 04:44:55.167896
3953 04:44:55.171359 [CATrainingPosCal] consider 2 rank data
3954 04:44:55.174743 u2DelayCellTimex100 = 270/100 ps
3955 04:44:55.178156 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3956 04:44:55.181443 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3957 04:44:55.184699 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3958 04:44:55.188014 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3959 04:44:55.191214 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3960 04:44:55.194936 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3961 04:44:55.198221
3962 04:44:55.201183 CA PerBit enable=1, Macro0, CA PI delay=33
3963 04:44:55.201267
3964 04:44:55.204634 [CBTSetCACLKResult] CA Dly = 33
3965 04:44:55.204721 CS Dly: 4 (0~36)
3966 04:44:55.204788
3967 04:44:55.208176 ----->DramcWriteLeveling(PI) begin...
3968 04:44:55.208250 ==
3969 04:44:55.211587 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 04:44:55.214602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 04:44:55.218124 ==
3972 04:44:55.218197 Write leveling (Byte 0): 35 => 35
3973 04:44:55.221439 Write leveling (Byte 1): 32 => 32
3974 04:44:55.224823 DramcWriteLeveling(PI) end<-----
3975 04:44:55.224894
3976 04:44:55.224955 ==
3977 04:44:55.228250 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 04:44:55.234648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 04:44:55.234727 ==
3980 04:44:55.234790 [Gating] SW mode calibration
3981 04:44:55.244326 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3982 04:44:55.247705 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3983 04:44:55.251313 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 04:44:55.257954 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 04:44:55.260957 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3986 04:44:55.264459 0 9 12 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
3987 04:44:55.271197 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
3988 04:44:55.274671 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 04:44:55.277724 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 04:44:55.284564 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 04:44:55.287896 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 04:44:55.291207 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 04:44:55.297924 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3994 04:44:55.301257 0 10 12 | B1->B0 | 2626 3d3d | 1 0 | (0 0) (0 0)
3995 04:44:55.304373 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3996 04:44:55.310893 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 04:44:55.314328 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 04:44:55.317812 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 04:44:55.324172 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 04:44:55.327624 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 04:44:55.330901 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 04:44:55.337842 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 04:44:55.340804 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 04:44:55.344680 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 04:44:55.351046 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 04:44:55.354585 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 04:44:55.357540 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 04:44:55.361265 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 04:44:55.367806 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 04:44:55.371031 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 04:44:55.374486 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 04:44:55.380850 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 04:44:55.384302 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 04:44:55.387502 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 04:44:55.394219 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 04:44:55.397503 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 04:44:55.400941 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 04:44:55.407679 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4019 04:44:55.410601 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4020 04:44:55.414129 Total UI for P1: 0, mck2ui 16
4021 04:44:55.417579 best dqsien dly found for B0: ( 0, 13, 12)
4022 04:44:55.420601 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 04:44:55.424192 Total UI for P1: 0, mck2ui 16
4024 04:44:55.427603 best dqsien dly found for B1: ( 0, 13, 14)
4025 04:44:55.430958 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4026 04:44:55.433866 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4027 04:44:55.433937
4028 04:44:55.440818 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4029 04:44:55.444285 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4030 04:44:55.447235 [Gating] SW calibration Done
4031 04:44:55.447311 ==
4032 04:44:55.450591 Dram Type= 6, Freq= 0, CH_0, rank 0
4033 04:44:55.454387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4034 04:44:55.454462 ==
4035 04:44:55.454525 RX Vref Scan: 0
4036 04:44:55.454584
4037 04:44:55.457270 RX Vref 0 -> 0, step: 1
4038 04:44:55.457339
4039 04:44:55.460576 RX Delay -230 -> 252, step: 16
4040 04:44:55.464066 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4041 04:44:55.467285 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4042 04:44:55.473722 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4043 04:44:55.477287 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4044 04:44:55.480711 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4045 04:44:55.483614 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4046 04:44:55.490674 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4047 04:44:55.493947 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4048 04:44:55.497162 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4049 04:44:55.500422 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4050 04:44:55.503741 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4051 04:44:55.510451 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4052 04:44:55.513517 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4053 04:44:55.517011 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4054 04:44:55.520501 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4055 04:44:55.526922 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4056 04:44:55.526995 ==
4057 04:44:55.530403 Dram Type= 6, Freq= 0, CH_0, rank 0
4058 04:44:55.533806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4059 04:44:55.533908 ==
4060 04:44:55.534022 DQS Delay:
4061 04:44:55.537089 DQS0 = 0, DQS1 = 0
4062 04:44:55.537169 DQM Delay:
4063 04:44:55.540094 DQM0 = 49, DQM1 = 39
4064 04:44:55.540162 DQ Delay:
4065 04:44:55.543694 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =41
4066 04:44:55.546603 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4067 04:44:55.550097 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4068 04:44:55.553518 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =41
4069 04:44:55.553586
4070 04:44:55.553643
4071 04:44:55.553707 ==
4072 04:44:55.556887 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 04:44:55.563298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 04:44:55.563380 ==
4075 04:44:55.563442
4076 04:44:55.563501
4077 04:44:55.563573 TX Vref Scan disable
4078 04:44:55.566892 == TX Byte 0 ==
4079 04:44:55.570207 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4080 04:44:55.573450 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4081 04:44:55.576715 == TX Byte 1 ==
4082 04:44:55.580147 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4083 04:44:55.583559 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4084 04:44:55.586644 ==
4085 04:44:55.589925 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 04:44:55.593444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 04:44:55.593526 ==
4088 04:44:55.593590
4089 04:44:55.593649
4090 04:44:55.596660 TX Vref Scan disable
4091 04:44:55.596742 == TX Byte 0 ==
4092 04:44:55.603180 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4093 04:44:55.606951 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4094 04:44:55.607033 == TX Byte 1 ==
4095 04:44:55.613609 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4096 04:44:55.617136 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4097 04:44:55.617218
4098 04:44:55.617283 [DATLAT]
4099 04:44:55.620105 Freq=600, CH0 RK0
4100 04:44:55.620187
4101 04:44:55.620252 DATLAT Default: 0x9
4102 04:44:55.623639 0, 0xFFFF, sum = 0
4103 04:44:55.623722 1, 0xFFFF, sum = 0
4104 04:44:55.626612 2, 0xFFFF, sum = 0
4105 04:44:55.626695 3, 0xFFFF, sum = 0
4106 04:44:55.630059 4, 0xFFFF, sum = 0
4107 04:44:55.633531 5, 0xFFFF, sum = 0
4108 04:44:55.633614 6, 0xFFFF, sum = 0
4109 04:44:55.636458 7, 0xFFFF, sum = 0
4110 04:44:55.636541 8, 0x0, sum = 1
4111 04:44:55.636608 9, 0x0, sum = 2
4112 04:44:55.639991 10, 0x0, sum = 3
4113 04:44:55.640100 11, 0x0, sum = 4
4114 04:44:55.643481 best_step = 9
4115 04:44:55.643563
4116 04:44:55.643627 ==
4117 04:44:55.646492 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 04:44:55.649936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 04:44:55.650055 ==
4120 04:44:55.653418 RX Vref Scan: 1
4121 04:44:55.653500
4122 04:44:55.653565 RX Vref 0 -> 0, step: 1
4123 04:44:55.653624
4124 04:44:55.656826 RX Delay -179 -> 252, step: 8
4125 04:44:55.656907
4126 04:44:55.659789 Set Vref, RX VrefLevel [Byte0]: 57
4127 04:44:55.663392 [Byte1]: 49
4128 04:44:55.667261
4129 04:44:55.667343 Final RX Vref Byte 0 = 57 to rank0
4130 04:44:55.670621 Final RX Vref Byte 1 = 49 to rank0
4131 04:44:55.673823 Final RX Vref Byte 0 = 57 to rank1
4132 04:44:55.677074 Final RX Vref Byte 1 = 49 to rank1==
4133 04:44:55.680337 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 04:44:55.687112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 04:44:55.687196 ==
4136 04:44:55.687261 DQS Delay:
4137 04:44:55.687321 DQS0 = 0, DQS1 = 0
4138 04:44:55.690557 DQM Delay:
4139 04:44:55.690640 DQM0 = 50, DQM1 = 39
4140 04:44:55.693601 DQ Delay:
4141 04:44:55.696995 DQ0 =48, DQ1 =52, DQ2 =48, DQ3 =44
4142 04:44:55.700306 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4143 04:44:55.703467 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =32
4144 04:44:55.706760 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4145 04:44:55.706844
4146 04:44:55.706909
4147 04:44:55.713936 [DQSOSCAuto] RK0, (LSB)MR18= 0x5650, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4148 04:44:55.716788 CH0 RK0: MR19=808, MR18=5650
4149 04:44:55.723719 CH0_RK0: MR19=0x808, MR18=0x5650, DQSOSC=393, MR23=63, INC=169, DEC=113
4150 04:44:55.723803
4151 04:44:55.726632 ----->DramcWriteLeveling(PI) begin...
4152 04:44:55.726716 ==
4153 04:44:55.730211 Dram Type= 6, Freq= 0, CH_0, rank 1
4154 04:44:55.733552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 04:44:55.733639 ==
4156 04:44:55.737021 Write leveling (Byte 0): 34 => 34
4157 04:44:55.740036 Write leveling (Byte 1): 34 => 34
4158 04:44:55.743414 DramcWriteLeveling(PI) end<-----
4159 04:44:55.743497
4160 04:44:55.743562 ==
4161 04:44:55.746647 Dram Type= 6, Freq= 0, CH_0, rank 1
4162 04:44:55.750270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4163 04:44:55.750355 ==
4164 04:44:55.753764 [Gating] SW mode calibration
4165 04:44:55.760129 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4166 04:44:55.766960 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4167 04:44:55.770291 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4168 04:44:55.773623 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4169 04:44:55.779976 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4170 04:44:55.783304 0 9 12 | B1->B0 | 3232 3030 | 1 0 | (1 0) (0 0)
4171 04:44:55.787006 0 9 16 | B1->B0 | 2b2b 2323 | 1 0 | (0 0) (1 0)
4172 04:44:55.793415 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 04:44:55.796918 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 04:44:55.799919 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 04:44:55.806893 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 04:44:55.809928 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 04:44:55.813199 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 04:44:55.820006 0 10 12 | B1->B0 | 2929 3232 | 1 0 | (0 0) (0 0)
4179 04:44:55.823297 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4180 04:44:55.826674 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 04:44:55.833107 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 04:44:55.836595 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 04:44:55.840189 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 04:44:55.846436 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 04:44:55.849730 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 04:44:55.853192 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4187 04:44:55.860052 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 04:44:55.863047 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 04:44:55.866548 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 04:44:55.873512 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 04:44:55.876440 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 04:44:55.879806 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 04:44:55.886328 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 04:44:55.889652 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 04:44:55.893035 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 04:44:55.899477 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 04:44:55.902942 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 04:44:55.906468 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 04:44:55.913031 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 04:44:55.916217 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 04:44:55.919551 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 04:44:55.922872 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 04:44:55.929427 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 04:44:55.932901 Total UI for P1: 0, mck2ui 16
4205 04:44:55.935799 best dqsien dly found for B0: ( 0, 13, 14)
4206 04:44:55.939405 Total UI for P1: 0, mck2ui 16
4207 04:44:55.942824 best dqsien dly found for B1: ( 0, 13, 14)
4208 04:44:55.945866 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4209 04:44:55.949346 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4210 04:44:55.949428
4211 04:44:55.952568 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4212 04:44:55.955990 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4213 04:44:55.959398 [Gating] SW calibration Done
4214 04:44:55.959481 ==
4215 04:44:55.962830 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 04:44:55.966305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 04:44:55.966389 ==
4218 04:44:55.969235 RX Vref Scan: 0
4219 04:44:55.969317
4220 04:44:55.972624 RX Vref 0 -> 0, step: 1
4221 04:44:55.972707
4222 04:44:55.972773 RX Delay -230 -> 252, step: 16
4223 04:44:55.979120 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4224 04:44:55.982740 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4225 04:44:55.985956 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4226 04:44:55.989442 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4227 04:44:55.995944 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4228 04:44:55.999115 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4229 04:44:56.002443 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4230 04:44:56.005967 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4231 04:44:56.009482 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4232 04:44:56.016082 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4233 04:44:56.019255 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4234 04:44:56.022460 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4235 04:44:56.025717 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4236 04:44:56.032481 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4237 04:44:56.035980 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4238 04:44:56.039048 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4239 04:44:56.039131 ==
4240 04:44:56.042463 Dram Type= 6, Freq= 0, CH_0, rank 1
4241 04:44:56.045958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4242 04:44:56.049010 ==
4243 04:44:56.049093 DQS Delay:
4244 04:44:56.049158 DQS0 = 0, DQS1 = 0
4245 04:44:56.052454 DQM Delay:
4246 04:44:56.052537 DQM0 = 46, DQM1 = 42
4247 04:44:56.055890 DQ Delay:
4248 04:44:56.055973 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4249 04:44:56.058805 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4250 04:44:56.062244 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4251 04:44:56.065618 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4252 04:44:56.065720
4253 04:44:56.069122
4254 04:44:56.069207 ==
4255 04:44:56.072615 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 04:44:56.075882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 04:44:56.075989 ==
4258 04:44:56.076086
4259 04:44:56.076151
4260 04:44:56.078916 TX Vref Scan disable
4261 04:44:56.078987 == TX Byte 0 ==
4262 04:44:56.085639 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4263 04:44:56.089105 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4264 04:44:56.089187 == TX Byte 1 ==
4265 04:44:56.096118 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4266 04:44:56.099188 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4267 04:44:56.099270 ==
4268 04:44:56.102200 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 04:44:56.105721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 04:44:56.105807 ==
4271 04:44:56.105910
4272 04:44:56.106029
4273 04:44:56.109152 TX Vref Scan disable
4274 04:44:56.112192 == TX Byte 0 ==
4275 04:44:56.115634 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4276 04:44:56.118994 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4277 04:44:56.122204 == TX Byte 1 ==
4278 04:44:56.125482 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4279 04:44:56.128855 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4280 04:44:56.128939
4281 04:44:56.132309 [DATLAT]
4282 04:44:56.132392 Freq=600, CH0 RK1
4283 04:44:56.132459
4284 04:44:56.135642 DATLAT Default: 0x9
4285 04:44:56.135725 0, 0xFFFF, sum = 0
4286 04:44:56.138573 1, 0xFFFF, sum = 0
4287 04:44:56.138657 2, 0xFFFF, sum = 0
4288 04:44:56.142060 3, 0xFFFF, sum = 0
4289 04:44:56.142145 4, 0xFFFF, sum = 0
4290 04:44:56.145582 5, 0xFFFF, sum = 0
4291 04:44:56.145667 6, 0xFFFF, sum = 0
4292 04:44:56.148947 7, 0xFFFF, sum = 0
4293 04:44:56.149030 8, 0x0, sum = 1
4294 04:44:56.152023 9, 0x0, sum = 2
4295 04:44:56.152106 10, 0x0, sum = 3
4296 04:44:56.155462 11, 0x0, sum = 4
4297 04:44:56.155545 best_step = 9
4298 04:44:56.155609
4299 04:44:56.155668 ==
4300 04:44:56.158996 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 04:44:56.162258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 04:44:56.165669 ==
4303 04:44:56.165750 RX Vref Scan: 0
4304 04:44:56.165814
4305 04:44:56.168650 RX Vref 0 -> 0, step: 1
4306 04:44:56.168732
4307 04:44:56.172203 RX Delay -179 -> 252, step: 8
4308 04:44:56.175567 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4309 04:44:56.179055 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4310 04:44:56.185450 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4311 04:44:56.189006 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4312 04:44:56.192300 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4313 04:44:56.195504 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4314 04:44:56.198735 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4315 04:44:56.205441 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4316 04:44:56.208894 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4317 04:44:56.211914 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4318 04:44:56.215266 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4319 04:44:56.222158 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4320 04:44:56.225013 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4321 04:44:56.228639 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4322 04:44:56.231872 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4323 04:44:56.235300 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4324 04:44:56.238167 ==
4325 04:44:56.241509 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 04:44:56.245020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 04:44:56.245102 ==
4328 04:44:56.245167 DQS Delay:
4329 04:44:56.248568 DQS0 = 0, DQS1 = 0
4330 04:44:56.248649 DQM Delay:
4331 04:44:56.251550 DQM0 = 47, DQM1 = 40
4332 04:44:56.251631 DQ Delay:
4333 04:44:56.255033 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4334 04:44:56.258476 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =52
4335 04:44:56.261456 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =36
4336 04:44:56.264750 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =44
4337 04:44:56.264831
4338 04:44:56.264896
4339 04:44:56.271406 [DQSOSCAuto] RK1, (LSB)MR18= 0x6330, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4340 04:44:56.274546 CH0 RK1: MR19=808, MR18=6330
4341 04:44:56.281332 CH0_RK1: MR19=0x808, MR18=0x6330, DQSOSC=391, MR23=63, INC=171, DEC=114
4342 04:44:56.284662 [RxdqsGatingPostProcess] freq 600
4343 04:44:56.291102 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4344 04:44:56.294377 Pre-setting of DQS Precalculation
4345 04:44:56.297711 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4346 04:44:56.297793 ==
4347 04:44:56.301094 Dram Type= 6, Freq= 0, CH_1, rank 0
4348 04:44:56.304302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 04:44:56.304384 ==
4350 04:44:56.310966 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4351 04:44:56.317846 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4352 04:44:56.321182 [CA 0] Center 35 (5~66) winsize 62
4353 04:44:56.324511 [CA 1] Center 35 (5~66) winsize 62
4354 04:44:56.327488 [CA 2] Center 34 (4~65) winsize 62
4355 04:44:56.331272 [CA 3] Center 33 (3~64) winsize 62
4356 04:44:56.334495 [CA 4] Center 33 (3~64) winsize 62
4357 04:44:56.337873 [CA 5] Center 33 (3~64) winsize 62
4358 04:44:56.337985
4359 04:44:56.341210 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4360 04:44:56.341293
4361 04:44:56.344286 [CATrainingPosCal] consider 1 rank data
4362 04:44:56.347735 u2DelayCellTimex100 = 270/100 ps
4363 04:44:56.350692 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4364 04:44:56.354307 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4365 04:44:56.357297 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4366 04:44:56.360739 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4367 04:44:56.364237 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4368 04:44:56.367649 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4369 04:44:56.370834
4370 04:44:56.374183 CA PerBit enable=1, Macro0, CA PI delay=33
4371 04:44:56.374267
4372 04:44:56.377754 [CBTSetCACLKResult] CA Dly = 33
4373 04:44:56.377837 CS Dly: 5 (0~36)
4374 04:44:56.377904 ==
4375 04:44:56.380782 Dram Type= 6, Freq= 0, CH_1, rank 1
4376 04:44:56.384171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 04:44:56.384256 ==
4378 04:44:56.390560 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4379 04:44:56.397610 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4380 04:44:56.400430 [CA 0] Center 35 (5~66) winsize 62
4381 04:44:56.404078 [CA 1] Center 35 (5~66) winsize 62
4382 04:44:56.407488 [CA 2] Center 34 (4~65) winsize 62
4383 04:44:56.410600 [CA 3] Center 34 (4~65) winsize 62
4384 04:44:56.414094 [CA 4] Center 34 (4~65) winsize 62
4385 04:44:56.417051 [CA 5] Center 34 (4~64) winsize 61
4386 04:44:56.417135
4387 04:44:56.420489 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4388 04:44:56.420573
4389 04:44:56.424011 [CATrainingPosCal] consider 2 rank data
4390 04:44:56.427535 u2DelayCellTimex100 = 270/100 ps
4391 04:44:56.430430 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4392 04:44:56.433835 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4393 04:44:56.436943 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4394 04:44:56.440377 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4395 04:44:56.443668 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4396 04:44:56.450714 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4397 04:44:56.450797
4398 04:44:56.453696 CA PerBit enable=1, Macro0, CA PI delay=34
4399 04:44:56.453778
4400 04:44:56.457245 [CBTSetCACLKResult] CA Dly = 34
4401 04:44:56.457328 CS Dly: 5 (0~37)
4402 04:44:56.457396
4403 04:44:56.460233 ----->DramcWriteLeveling(PI) begin...
4404 04:44:56.460317 ==
4405 04:44:56.463747 Dram Type= 6, Freq= 0, CH_1, rank 0
4406 04:44:56.470223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 04:44:56.470306 ==
4408 04:44:56.473605 Write leveling (Byte 0): 30 => 30
4409 04:44:56.473688 Write leveling (Byte 1): 31 => 31
4410 04:44:56.476941 DramcWriteLeveling(PI) end<-----
4411 04:44:56.477024
4412 04:44:56.477089 ==
4413 04:44:56.480489 Dram Type= 6, Freq= 0, CH_1, rank 0
4414 04:44:56.487417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 04:44:56.487501 ==
4416 04:44:56.490275 [Gating] SW mode calibration
4417 04:44:56.497342 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4418 04:44:56.500278 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4419 04:44:56.506966 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4420 04:44:56.510242 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4421 04:44:56.513575 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4422 04:44:56.520300 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (1 1)
4423 04:44:56.523731 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 04:44:56.526791 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 04:44:56.530185 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 04:44:56.537043 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 04:44:56.540198 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 04:44:56.543451 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 04:44:56.550332 0 10 8 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
4430 04:44:56.553759 0 10 12 | B1->B0 | 3838 4444 | 1 0 | (0 0) (0 0)
4431 04:44:56.557304 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 04:44:56.563668 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 04:44:56.567172 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 04:44:56.570582 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 04:44:56.576858 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 04:44:56.580646 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 04:44:56.583922 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4438 04:44:56.590322 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4439 04:44:56.593765 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 04:44:56.597159 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 04:44:56.603658 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 04:44:56.607004 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 04:44:56.610271 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 04:44:56.616840 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 04:44:56.620584 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 04:44:56.623507 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 04:44:56.626961 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 04:44:56.633372 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 04:44:56.636879 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 04:44:56.640541 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 04:44:56.646890 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 04:44:56.650206 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 04:44:56.653568 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 04:44:56.660382 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4455 04:44:56.663384 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 04:44:56.666920 Total UI for P1: 0, mck2ui 16
4457 04:44:56.669899 best dqsien dly found for B0: ( 0, 13, 12)
4458 04:44:56.673494 Total UI for P1: 0, mck2ui 16
4459 04:44:56.676820 best dqsien dly found for B1: ( 0, 13, 12)
4460 04:44:56.680167 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4461 04:44:56.683192 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4462 04:44:56.683274
4463 04:44:56.686843 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4464 04:44:56.690289 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4465 04:44:56.693323 [Gating] SW calibration Done
4466 04:44:56.693420 ==
4467 04:44:56.696722 Dram Type= 6, Freq= 0, CH_1, rank 0
4468 04:44:56.703821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 04:44:56.703904 ==
4470 04:44:56.703969 RX Vref Scan: 0
4471 04:44:56.704028
4472 04:44:56.706801 RX Vref 0 -> 0, step: 1
4473 04:44:56.706885
4474 04:44:56.709867 RX Delay -230 -> 252, step: 16
4475 04:44:56.713432 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4476 04:44:56.716748 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4477 04:44:56.720407 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4478 04:44:56.726579 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4479 04:44:56.729925 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4480 04:44:56.733423 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4481 04:44:56.736495 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4482 04:44:56.739943 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4483 04:44:56.746759 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4484 04:44:56.750146 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4485 04:44:56.753462 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4486 04:44:56.756836 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4487 04:44:56.763050 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4488 04:44:56.766570 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4489 04:44:56.769886 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4490 04:44:56.772927 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4491 04:44:56.773011 ==
4492 04:44:56.776400 Dram Type= 6, Freq= 0, CH_1, rank 0
4493 04:44:56.783231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4494 04:44:56.783316 ==
4495 04:44:56.783383 DQS Delay:
4496 04:44:56.786286 DQS0 = 0, DQS1 = 0
4497 04:44:56.786369 DQM Delay:
4498 04:44:56.786435 DQM0 = 51, DQM1 = 42
4499 04:44:56.789497 DQ Delay:
4500 04:44:56.793260 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4501 04:44:56.796244 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4502 04:44:56.799629 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =33
4503 04:44:56.802615 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4504 04:44:56.802698
4505 04:44:56.802765
4506 04:44:56.802827 ==
4507 04:44:56.806092 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 04:44:56.809552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 04:44:56.809630 ==
4510 04:44:56.809701
4511 04:44:56.809764
4512 04:44:56.812597 TX Vref Scan disable
4513 04:44:56.816317 == TX Byte 0 ==
4514 04:44:56.819571 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4515 04:44:56.822671 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4516 04:44:56.825977 == TX Byte 1 ==
4517 04:44:56.829120 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4518 04:44:56.832576 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4519 04:44:56.832660 ==
4520 04:44:56.836147 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 04:44:56.839088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 04:44:56.842571 ==
4523 04:44:56.842654
4524 04:44:56.842721
4525 04:44:56.842781 TX Vref Scan disable
4526 04:44:56.846568 == TX Byte 0 ==
4527 04:44:56.849562 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4528 04:44:56.856394 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4529 04:44:56.856479 == TX Byte 1 ==
4530 04:44:56.859749 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4531 04:44:56.866460 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4532 04:44:56.866544
4533 04:44:56.866610 [DATLAT]
4534 04:44:56.866671 Freq=600, CH1 RK0
4535 04:44:56.866730
4536 04:44:56.870064 DATLAT Default: 0x9
4537 04:44:56.870148 0, 0xFFFF, sum = 0
4538 04:44:56.872974 1, 0xFFFF, sum = 0
4539 04:44:56.873063 2, 0xFFFF, sum = 0
4540 04:44:56.876558 3, 0xFFFF, sum = 0
4541 04:44:56.879750 4, 0xFFFF, sum = 0
4542 04:44:56.879835 5, 0xFFFF, sum = 0
4543 04:44:56.883107 6, 0xFFFF, sum = 0
4544 04:44:56.883192 7, 0xFFFF, sum = 0
4545 04:44:56.886495 8, 0x0, sum = 1
4546 04:44:56.886580 9, 0x0, sum = 2
4547 04:44:56.886648 10, 0x0, sum = 3
4548 04:44:56.889470 11, 0x0, sum = 4
4549 04:44:56.889555 best_step = 9
4550 04:44:56.889625
4551 04:44:56.889688 ==
4552 04:44:56.892772 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 04:44:56.899449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 04:44:56.899533 ==
4555 04:44:56.899600 RX Vref Scan: 1
4556 04:44:56.899660
4557 04:44:56.902983 RX Vref 0 -> 0, step: 1
4558 04:44:56.903067
4559 04:44:56.906492 RX Delay -179 -> 252, step: 8
4560 04:44:56.906576
4561 04:44:56.909415 Set Vref, RX VrefLevel [Byte0]: 54
4562 04:44:56.912876 [Byte1]: 48
4563 04:44:56.912960
4564 04:44:56.916375 Final RX Vref Byte 0 = 54 to rank0
4565 04:44:56.919454 Final RX Vref Byte 1 = 48 to rank0
4566 04:44:56.922805 Final RX Vref Byte 0 = 54 to rank1
4567 04:44:56.926012 Final RX Vref Byte 1 = 48 to rank1==
4568 04:44:56.929295 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 04:44:56.932547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 04:44:56.932632 ==
4571 04:44:56.935944 DQS Delay:
4572 04:44:56.936028 DQS0 = 0, DQS1 = 0
4573 04:44:56.939464 DQM Delay:
4574 04:44:56.939548 DQM0 = 48, DQM1 = 40
4575 04:44:56.939615 DQ Delay:
4576 04:44:56.942790 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4577 04:44:56.945976 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4578 04:44:56.949409 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4579 04:44:56.952447 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4580 04:44:56.952531
4581 04:44:56.952598
4582 04:44:56.962946 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4583 04:44:56.965761 CH1 RK0: MR19=808, MR18=4C73
4584 04:44:56.969417 CH1_RK0: MR19=0x808, MR18=0x4C73, DQSOSC=388, MR23=63, INC=174, DEC=116
4585 04:44:56.972389
4586 04:44:56.975828 ----->DramcWriteLeveling(PI) begin...
4587 04:44:56.975913 ==
4588 04:44:56.979453 Dram Type= 6, Freq= 0, CH_1, rank 1
4589 04:44:56.982437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 04:44:56.982522 ==
4591 04:44:56.985851 Write leveling (Byte 0): 29 => 29
4592 04:44:56.989315 Write leveling (Byte 1): 28 => 28
4593 04:44:56.992365 DramcWriteLeveling(PI) end<-----
4594 04:44:56.992448
4595 04:44:56.992515 ==
4596 04:44:56.995676 Dram Type= 6, Freq= 0, CH_1, rank 1
4597 04:44:56.999038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 04:44:56.999122 ==
4599 04:44:57.002279 [Gating] SW mode calibration
4600 04:44:57.009138 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4601 04:44:57.015564 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4602 04:44:57.018996 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4603 04:44:57.022316 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4604 04:44:57.028915 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4605 04:44:57.032329 0 9 12 | B1->B0 | 2e2e 3131 | 0 0 | (1 0) (0 0)
4606 04:44:57.035970 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4607 04:44:57.042462 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 04:44:57.045497 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 04:44:57.049008 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 04:44:57.055530 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 04:44:57.058747 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 04:44:57.062024 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4613 04:44:57.065465 0 10 12 | B1->B0 | 4242 3131 | 0 0 | (0 0) (0 0)
4614 04:44:57.072213 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4615 04:44:57.075461 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 04:44:57.078441 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 04:44:57.085348 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 04:44:57.088887 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 04:44:57.091863 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 04:44:57.098627 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 04:44:57.101675 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 04:44:57.104998 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 04:44:57.111726 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 04:44:57.115216 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 04:44:57.118728 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 04:44:57.125087 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 04:44:57.128475 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 04:44:57.131731 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 04:44:57.138324 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 04:44:57.141711 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 04:44:57.144905 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 04:44:57.151965 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 04:44:57.154933 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 04:44:57.158402 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 04:44:57.164992 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 04:44:57.168245 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4637 04:44:57.171802 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4638 04:44:57.175291 Total UI for P1: 0, mck2ui 16
4639 04:44:57.178446 best dqsien dly found for B1: ( 0, 13, 8)
4640 04:44:57.185002 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 04:44:57.185086 Total UI for P1: 0, mck2ui 16
4642 04:44:57.188391 best dqsien dly found for B0: ( 0, 13, 10)
4643 04:44:57.194879 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4644 04:44:57.198171 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4645 04:44:57.198255
4646 04:44:57.201680 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4647 04:44:57.205121 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4648 04:44:57.208120 [Gating] SW calibration Done
4649 04:44:57.208218 ==
4650 04:44:57.211436 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 04:44:57.214786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 04:44:57.214872 ==
4653 04:44:57.218227 RX Vref Scan: 0
4654 04:44:57.218314
4655 04:44:57.218399 RX Vref 0 -> 0, step: 1
4656 04:44:57.218478
4657 04:44:57.221283 RX Delay -230 -> 252, step: 16
4658 04:44:57.224707 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4659 04:44:57.231435 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4660 04:44:57.234935 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4661 04:44:57.238267 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4662 04:44:57.241483 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4663 04:44:57.244943 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4664 04:44:57.251742 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4665 04:44:57.254693 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4666 04:44:57.258270 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4667 04:44:57.261752 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4668 04:44:57.268371 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4669 04:44:57.271589 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4670 04:44:57.275055 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4671 04:44:57.278387 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4672 04:44:57.281606 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4673 04:44:57.288126 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4674 04:44:57.288225 ==
4675 04:44:57.291630 Dram Type= 6, Freq= 0, CH_1, rank 1
4676 04:44:57.294984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 04:44:57.295072 ==
4678 04:44:57.295157 DQS Delay:
4679 04:44:57.298008 DQS0 = 0, DQS1 = 0
4680 04:44:57.298104 DQM Delay:
4681 04:44:57.301413 DQM0 = 52, DQM1 = 44
4682 04:44:57.301497 DQ Delay:
4683 04:44:57.304972 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4684 04:44:57.308288 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4685 04:44:57.311315 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4686 04:44:57.314780 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =57
4687 04:44:57.314864
4688 04:44:57.314947
4689 04:44:57.315026 ==
4690 04:44:57.318016 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 04:44:57.321571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 04:44:57.324587 ==
4693 04:44:57.324670
4694 04:44:57.324754
4695 04:44:57.324833 TX Vref Scan disable
4696 04:44:57.328119 == TX Byte 0 ==
4697 04:44:57.331112 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4698 04:44:57.334468 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4699 04:44:57.337775 == TX Byte 1 ==
4700 04:44:57.341197 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4701 04:44:57.344878 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4702 04:44:57.347934 ==
4703 04:44:57.351202 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 04:44:57.354516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 04:44:57.354602 ==
4706 04:44:57.354689
4707 04:44:57.354769
4708 04:44:57.357870 TX Vref Scan disable
4709 04:44:57.357977 == TX Byte 0 ==
4710 04:44:57.364365 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4711 04:44:57.367995 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4712 04:44:57.368081 == TX Byte 1 ==
4713 04:44:57.374515 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4714 04:44:57.377974 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4715 04:44:57.378059
4716 04:44:57.378144 [DATLAT]
4717 04:44:57.381210 Freq=600, CH1 RK1
4718 04:44:57.381309
4719 04:44:57.381389 DATLAT Default: 0x9
4720 04:44:57.384186 0, 0xFFFF, sum = 0
4721 04:44:57.384287 1, 0xFFFF, sum = 0
4722 04:44:57.387528 2, 0xFFFF, sum = 0
4723 04:44:57.387614 3, 0xFFFF, sum = 0
4724 04:44:57.390990 4, 0xFFFF, sum = 0
4725 04:44:57.394398 5, 0xFFFF, sum = 0
4726 04:44:57.394484 6, 0xFFFF, sum = 0
4727 04:44:57.397473 7, 0xFFFF, sum = 0
4728 04:44:57.397559 8, 0x0, sum = 1
4729 04:44:57.397645 9, 0x0, sum = 2
4730 04:44:57.401016 10, 0x0, sum = 3
4731 04:44:57.401103 11, 0x0, sum = 4
4732 04:44:57.403903 best_step = 9
4733 04:44:57.403989
4734 04:44:57.404073 ==
4735 04:44:57.407372 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 04:44:57.410765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 04:44:57.410851 ==
4738 04:44:57.414247 RX Vref Scan: 0
4739 04:44:57.414332
4740 04:44:57.414418 RX Vref 0 -> 0, step: 1
4741 04:44:57.414498
4742 04:44:57.417210 RX Delay -163 -> 252, step: 8
4743 04:44:57.424814 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4744 04:44:57.428390 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4745 04:44:57.431334 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4746 04:44:57.434846 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4747 04:44:57.441231 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4748 04:44:57.444479 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4749 04:44:57.447709 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4750 04:44:57.451045 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4751 04:44:57.454375 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4752 04:44:57.461043 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4753 04:44:57.464544 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4754 04:44:57.467497 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4755 04:44:57.470958 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4756 04:44:57.474295 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4757 04:44:57.481152 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4758 04:44:57.484453 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4759 04:44:57.484538 ==
4760 04:44:57.487333 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 04:44:57.490694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 04:44:57.490781 ==
4763 04:44:57.493927 DQS Delay:
4764 04:44:57.494049 DQS0 = 0, DQS1 = 0
4765 04:44:57.494134 DQM Delay:
4766 04:44:57.497479 DQM0 = 48, DQM1 = 43
4767 04:44:57.497564 DQ Delay:
4768 04:44:57.500972 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4769 04:44:57.503934 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4770 04:44:57.507429 DQ8 =28, DQ9 =36, DQ10 =44, DQ11 =36
4771 04:44:57.510780 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4772 04:44:57.510895
4773 04:44:57.510997
4774 04:44:57.520725 [DQSOSCAuto] RK1, (LSB)MR18= 0x531a, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
4775 04:44:57.524057 CH1 RK1: MR19=808, MR18=531A
4776 04:44:57.527462 CH1_RK1: MR19=0x808, MR18=0x531A, DQSOSC=394, MR23=63, INC=168, DEC=112
4777 04:44:57.530434 [RxdqsGatingPostProcess] freq 600
4778 04:44:57.537457 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4779 04:44:57.540961 Pre-setting of DQS Precalculation
4780 04:44:57.543962 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4781 04:44:57.554159 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4782 04:44:57.560330 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4783 04:44:57.560415
4784 04:44:57.560499
4785 04:44:57.563770 [Calibration Summary] 1200 Mbps
4786 04:44:57.563882 CH 0, Rank 0
4787 04:44:57.567199 SW Impedance : PASS
4788 04:44:57.567308 DUTY Scan : NO K
4789 04:44:57.570157 ZQ Calibration : PASS
4790 04:44:57.573675 Jitter Meter : NO K
4791 04:44:57.573785 CBT Training : PASS
4792 04:44:57.577102 Write leveling : PASS
4793 04:44:57.580444 RX DQS gating : PASS
4794 04:44:57.580529 RX DQ/DQS(RDDQC) : PASS
4795 04:44:57.583555 TX DQ/DQS : PASS
4796 04:44:57.586915 RX DATLAT : PASS
4797 04:44:57.587003 RX DQ/DQS(Engine): PASS
4798 04:44:57.590384 TX OE : NO K
4799 04:44:57.590494 All Pass.
4800 04:44:57.590579
4801 04:44:57.593551 CH 0, Rank 1
4802 04:44:57.593660 SW Impedance : PASS
4803 04:44:57.596856 DUTY Scan : NO K
4804 04:44:57.596941 ZQ Calibration : PASS
4805 04:44:57.600165 Jitter Meter : NO K
4806 04:44:57.603757 CBT Training : PASS
4807 04:44:57.603842 Write leveling : PASS
4808 04:44:57.607173 RX DQS gating : PASS
4809 04:44:57.610087 RX DQ/DQS(RDDQC) : PASS
4810 04:44:57.610172 TX DQ/DQS : PASS
4811 04:44:57.613598 RX DATLAT : PASS
4812 04:44:57.617222 RX DQ/DQS(Engine): PASS
4813 04:44:57.617307 TX OE : NO K
4814 04:44:57.620126 All Pass.
4815 04:44:57.620211
4816 04:44:57.620296 CH 1, Rank 0
4817 04:44:57.623612 SW Impedance : PASS
4818 04:44:57.623697 DUTY Scan : NO K
4819 04:44:57.627043 ZQ Calibration : PASS
4820 04:44:57.630344 Jitter Meter : NO K
4821 04:44:57.630430 CBT Training : PASS
4822 04:44:57.633319 Write leveling : PASS
4823 04:44:57.636837 RX DQS gating : PASS
4824 04:44:57.636920 RX DQ/DQS(RDDQC) : PASS
4825 04:44:57.640169 TX DQ/DQS : PASS
4826 04:44:57.643261 RX DATLAT : PASS
4827 04:44:57.643344 RX DQ/DQS(Engine): PASS
4828 04:44:57.646622 TX OE : NO K
4829 04:44:57.646706 All Pass.
4830 04:44:57.646789
4831 04:44:57.649884 CH 1, Rank 1
4832 04:44:57.649994 SW Impedance : PASS
4833 04:44:57.653548 DUTY Scan : NO K
4834 04:44:57.653632 ZQ Calibration : PASS
4835 04:44:57.656406 Jitter Meter : NO K
4836 04:44:57.660125 CBT Training : PASS
4837 04:44:57.660222 Write leveling : PASS
4838 04:44:57.663425 RX DQS gating : PASS
4839 04:44:57.666717 RX DQ/DQS(RDDQC) : PASS
4840 04:44:57.666825 TX DQ/DQS : PASS
4841 04:44:57.669661 RX DATLAT : PASS
4842 04:44:57.673259 RX DQ/DQS(Engine): PASS
4843 04:44:57.673346 TX OE : NO K
4844 04:44:57.676739 All Pass.
4845 04:44:57.676837
4846 04:44:57.676915 DramC Write-DBI off
4847 04:44:57.679660 PER_BANK_REFRESH: Hybrid Mode
4848 04:44:57.679733 TX_TRACKING: ON
4849 04:44:57.689944 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4850 04:44:57.692861 [FAST_K] Save calibration result to emmc
4851 04:44:57.696735 dramc_set_vcore_voltage set vcore to 662500
4852 04:44:57.700090 Read voltage for 933, 3
4853 04:44:57.700175 Vio18 = 0
4854 04:44:57.702803 Vcore = 662500
4855 04:44:57.702918 Vdram = 0
4856 04:44:57.703004 Vddq = 0
4857 04:44:57.706434 Vmddr = 0
4858 04:44:57.709437 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4859 04:44:57.716405 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4860 04:44:57.716490 MEM_TYPE=3, freq_sel=17
4861 04:44:57.719407 sv_algorithm_assistance_LP4_1600
4862 04:44:57.726378 ============ PULL DRAM RESETB DOWN ============
4863 04:44:57.729277 ========== PULL DRAM RESETB DOWN end =========
4864 04:44:57.733129 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4865 04:44:57.736057 ===================================
4866 04:44:57.739580 LPDDR4 DRAM CONFIGURATION
4867 04:44:57.743062 ===================================
4868 04:44:57.743148 EX_ROW_EN[0] = 0x0
4869 04:44:57.745929 EX_ROW_EN[1] = 0x0
4870 04:44:57.749472 LP4Y_EN = 0x0
4871 04:44:57.749558 WORK_FSP = 0x0
4872 04:44:57.752981 WL = 0x3
4873 04:44:57.753064 RL = 0x3
4874 04:44:57.756330 BL = 0x2
4875 04:44:57.756416 RPST = 0x0
4876 04:44:57.759690 RD_PRE = 0x0
4877 04:44:57.759775 WR_PRE = 0x1
4878 04:44:57.762627 WR_PST = 0x0
4879 04:44:57.762713 DBI_WR = 0x0
4880 04:44:57.766395 DBI_RD = 0x0
4881 04:44:57.766480 OTF = 0x1
4882 04:44:57.769661 ===================================
4883 04:44:57.772598 ===================================
4884 04:44:57.776095 ANA top config
4885 04:44:57.779513 ===================================
4886 04:44:57.779597 DLL_ASYNC_EN = 0
4887 04:44:57.782931 ALL_SLAVE_EN = 1
4888 04:44:57.785834 NEW_RANK_MODE = 1
4889 04:44:57.789556 DLL_IDLE_MODE = 1
4890 04:44:57.792738 LP45_APHY_COMB_EN = 1
4891 04:44:57.792821 TX_ODT_DIS = 1
4892 04:44:57.796086 NEW_8X_MODE = 1
4893 04:44:57.799469 ===================================
4894 04:44:57.802379 ===================================
4895 04:44:57.805740 data_rate = 1866
4896 04:44:57.809241 CKR = 1
4897 04:44:57.812575 DQ_P2S_RATIO = 8
4898 04:44:57.816030 ===================================
4899 04:44:57.816113 CA_P2S_RATIO = 8
4900 04:44:57.818923 DQ_CA_OPEN = 0
4901 04:44:57.822440 DQ_SEMI_OPEN = 0
4902 04:44:57.826011 CA_SEMI_OPEN = 0
4903 04:44:57.829018 CA_FULL_RATE = 0
4904 04:44:57.832467 DQ_CKDIV4_EN = 1
4905 04:44:57.832551 CA_CKDIV4_EN = 1
4906 04:44:57.835887 CA_PREDIV_EN = 0
4907 04:44:57.839201 PH8_DLY = 0
4908 04:44:57.842257 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4909 04:44:57.845754 DQ_AAMCK_DIV = 4
4910 04:44:57.849184 CA_AAMCK_DIV = 4
4911 04:44:57.849267 CA_ADMCK_DIV = 4
4912 04:44:57.852647 DQ_TRACK_CA_EN = 0
4913 04:44:57.855910 CA_PICK = 933
4914 04:44:57.859188 CA_MCKIO = 933
4915 04:44:57.862526 MCKIO_SEMI = 0
4916 04:44:57.865785 PLL_FREQ = 3732
4917 04:44:57.869157 DQ_UI_PI_RATIO = 32
4918 04:44:57.869240 CA_UI_PI_RATIO = 0
4919 04:44:57.872479 ===================================
4920 04:44:57.875677 ===================================
4921 04:44:57.879233 memory_type:LPDDR4
4922 04:44:57.882641 GP_NUM : 10
4923 04:44:57.882724 SRAM_EN : 1
4924 04:44:57.885591 MD32_EN : 0
4925 04:44:57.888681 ===================================
4926 04:44:57.892407 [ANA_INIT] >>>>>>>>>>>>>>
4927 04:44:57.895523 <<<<<< [CONFIGURE PHASE]: ANA_TX
4928 04:44:57.898906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4929 04:44:57.901918 ===================================
4930 04:44:57.902039 data_rate = 1866,PCW = 0X8f00
4931 04:44:57.905653 ===================================
4932 04:44:57.908580 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4933 04:44:57.915260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4934 04:44:57.922068 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4935 04:44:57.925627 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4936 04:44:57.928646 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4937 04:44:57.932165 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4938 04:44:57.935162 [ANA_INIT] flow start
4939 04:44:57.938597 [ANA_INIT] PLL >>>>>>>>
4940 04:44:57.938693 [ANA_INIT] PLL <<<<<<<<
4941 04:44:57.941917 [ANA_INIT] MIDPI >>>>>>>>
4942 04:44:57.945443 [ANA_INIT] MIDPI <<<<<<<<
4943 04:44:57.945539 [ANA_INIT] DLL >>>>>>>>
4944 04:44:57.948437 [ANA_INIT] flow end
4945 04:44:57.951390 ============ LP4 DIFF to SE enter ============
4946 04:44:57.954850 ============ LP4 DIFF to SE exit ============
4947 04:44:57.958269 [ANA_INIT] <<<<<<<<<<<<<
4948 04:44:57.961874 [Flow] Enable top DCM control >>>>>
4949 04:44:57.964699 [Flow] Enable top DCM control <<<<<
4950 04:44:57.968332 Enable DLL master slave shuffle
4951 04:44:57.974905 ==============================================================
4952 04:44:57.974989 Gating Mode config
4953 04:44:57.981756 ==============================================================
4954 04:44:57.981853 Config description:
4955 04:44:57.991228 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4956 04:44:57.998293 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4957 04:44:58.004827 SELPH_MODE 0: By rank 1: By Phase
4958 04:44:58.011453 ==============================================================
4959 04:44:58.011551 GAT_TRACK_EN = 1
4960 04:44:58.014755 RX_GATING_MODE = 2
4961 04:44:58.017668 RX_GATING_TRACK_MODE = 2
4962 04:44:58.021125 SELPH_MODE = 1
4963 04:44:58.024609 PICG_EARLY_EN = 1
4964 04:44:58.027633 VALID_LAT_VALUE = 1
4965 04:44:58.034534 ==============================================================
4966 04:44:58.037522 Enter into Gating configuration >>>>
4967 04:44:58.041031 Exit from Gating configuration <<<<
4968 04:44:58.044392 Enter into DVFS_PRE_config >>>>>
4969 04:44:58.054184 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4970 04:44:58.057670 Exit from DVFS_PRE_config <<<<<
4971 04:44:58.061120 Enter into PICG configuration >>>>
4972 04:44:58.063987 Exit from PICG configuration <<<<
4973 04:44:58.067730 [RX_INPUT] configuration >>>>>
4974 04:44:58.067812 [RX_INPUT] configuration <<<<<
4975 04:44:58.074441 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4976 04:44:58.080733 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4977 04:44:58.087340 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4978 04:44:58.090811 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4979 04:44:58.097315 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4980 04:44:58.103833 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4981 04:44:58.107079 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4982 04:44:58.110811 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4983 04:44:58.117423 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4984 04:44:58.120737 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4985 04:44:58.123973 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4986 04:44:58.130474 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4987 04:44:58.133843 ===================================
4988 04:44:58.133926 LPDDR4 DRAM CONFIGURATION
4989 04:44:58.136928 ===================================
4990 04:44:58.140432 EX_ROW_EN[0] = 0x0
4991 04:44:58.143835 EX_ROW_EN[1] = 0x0
4992 04:44:58.143917 LP4Y_EN = 0x0
4993 04:44:58.147124 WORK_FSP = 0x0
4994 04:44:58.147207 WL = 0x3
4995 04:44:58.150408 RL = 0x3
4996 04:44:58.150491 BL = 0x2
4997 04:44:58.153850 RPST = 0x0
4998 04:44:58.153933 RD_PRE = 0x0
4999 04:44:58.156859 WR_PRE = 0x1
5000 04:44:58.156942 WR_PST = 0x0
5001 04:44:58.160351 DBI_WR = 0x0
5002 04:44:58.160435 DBI_RD = 0x0
5003 04:44:58.163842 OTF = 0x1
5004 04:44:58.166841 ===================================
5005 04:44:58.170310 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5006 04:44:58.173461 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5007 04:44:58.180110 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5008 04:44:58.183473 ===================================
5009 04:44:58.183556 LPDDR4 DRAM CONFIGURATION
5010 04:44:58.187109 ===================================
5011 04:44:58.190467 EX_ROW_EN[0] = 0x10
5012 04:44:58.190550 EX_ROW_EN[1] = 0x0
5013 04:44:58.193456 LP4Y_EN = 0x0
5014 04:44:58.193538 WORK_FSP = 0x0
5015 04:44:58.196894 WL = 0x3
5016 04:44:58.196977 RL = 0x3
5017 04:44:58.200408 BL = 0x2
5018 04:44:58.203784 RPST = 0x0
5019 04:44:58.203867 RD_PRE = 0x0
5020 04:44:58.206913 WR_PRE = 0x1
5021 04:44:58.206996 WR_PST = 0x0
5022 04:44:58.210135 DBI_WR = 0x0
5023 04:44:58.210217 DBI_RD = 0x0
5024 04:44:58.213555 OTF = 0x1
5025 04:44:58.216879 ===================================
5026 04:44:58.220331 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5027 04:44:58.225787 nWR fixed to 30
5028 04:44:58.229139 [ModeRegInit_LP4] CH0 RK0
5029 04:44:58.229222 [ModeRegInit_LP4] CH0 RK1
5030 04:44:58.232129 [ModeRegInit_LP4] CH1 RK0
5031 04:44:58.235505 [ModeRegInit_LP4] CH1 RK1
5032 04:44:58.235588 match AC timing 9
5033 04:44:58.242618 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5034 04:44:58.245943 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5035 04:44:58.248945 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5036 04:44:58.255286 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5037 04:44:58.258761 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5038 04:44:58.258843 ==
5039 04:44:58.262213 Dram Type= 6, Freq= 0, CH_0, rank 0
5040 04:44:58.265607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5041 04:44:58.265690 ==
5042 04:44:58.271990 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5043 04:44:58.278730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5044 04:44:58.281950 [CA 0] Center 38 (7~69) winsize 63
5045 04:44:58.285308 [CA 1] Center 38 (8~69) winsize 62
5046 04:44:58.288830 [CA 2] Center 35 (5~66) winsize 62
5047 04:44:58.292238 [CA 3] Center 35 (5~65) winsize 61
5048 04:44:58.295496 [CA 4] Center 34 (4~65) winsize 62
5049 04:44:58.298409 [CA 5] Center 33 (3~64) winsize 62
5050 04:44:58.298490
5051 04:44:58.301890 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5052 04:44:58.302012
5053 04:44:58.305459 [CATrainingPosCal] consider 1 rank data
5054 04:44:58.308730 u2DelayCellTimex100 = 270/100 ps
5055 04:44:58.311841 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5056 04:44:58.315235 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5057 04:44:58.318706 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5058 04:44:58.322149 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5059 04:44:58.325086 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5060 04:44:58.332112 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5061 04:44:58.332194
5062 04:44:58.335108 CA PerBit enable=1, Macro0, CA PI delay=33
5063 04:44:58.335190
5064 04:44:58.338654 [CBTSetCACLKResult] CA Dly = 33
5065 04:44:58.338737 CS Dly: 6 (0~37)
5066 04:44:58.338803 ==
5067 04:44:58.342080 Dram Type= 6, Freq= 0, CH_0, rank 1
5068 04:44:58.345128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5069 04:44:58.348624 ==
5070 04:44:58.352127 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5071 04:44:58.358343 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5072 04:44:58.361888 [CA 0] Center 38 (8~69) winsize 62
5073 04:44:58.365321 [CA 1] Center 38 (8~69) winsize 62
5074 04:44:58.368303 [CA 2] Center 36 (6~66) winsize 61
5075 04:44:58.371876 [CA 3] Center 35 (5~66) winsize 62
5076 04:44:58.374860 [CA 4] Center 34 (4~65) winsize 62
5077 04:44:58.378570 [CA 5] Center 34 (4~65) winsize 62
5078 04:44:58.378652
5079 04:44:58.381446 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5080 04:44:58.381528
5081 04:44:58.385126 [CATrainingPosCal] consider 2 rank data
5082 04:44:58.388466 u2DelayCellTimex100 = 270/100 ps
5083 04:44:58.391759 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5084 04:44:58.394916 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5085 04:44:58.398104 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5086 04:44:58.401514 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5087 04:44:58.408155 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5088 04:44:58.411484 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5089 04:44:58.411566
5090 04:44:58.414862 CA PerBit enable=1, Macro0, CA PI delay=34
5091 04:44:58.414956
5092 04:44:58.418113 [CBTSetCACLKResult] CA Dly = 34
5093 04:44:58.418195 CS Dly: 7 (0~39)
5094 04:44:58.418259
5095 04:44:58.421398 ----->DramcWriteLeveling(PI) begin...
5096 04:44:58.421482 ==
5097 04:44:58.424943 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 04:44:58.431263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 04:44:58.431345 ==
5100 04:44:58.434786 Write leveling (Byte 0): 35 => 35
5101 04:44:58.438252 Write leveling (Byte 1): 29 => 29
5102 04:44:58.438333 DramcWriteLeveling(PI) end<-----
5103 04:44:58.438397
5104 04:44:58.441276 ==
5105 04:44:58.444580 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 04:44:58.448192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 04:44:58.448273 ==
5108 04:44:58.451154 [Gating] SW mode calibration
5109 04:44:58.458008 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5110 04:44:58.461437 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5111 04:44:58.468192 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5112 04:44:58.471190 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 04:44:58.474737 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 04:44:58.481110 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 04:44:58.484425 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 04:44:58.488127 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 04:44:58.494334 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5118 04:44:58.497590 0 14 28 | B1->B0 | 3131 2323 | 0 0 | (1 0) (0 0)
5119 04:44:58.500975 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5120 04:44:58.507929 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 04:44:58.510862 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 04:44:58.514236 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 04:44:58.520682 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 04:44:58.524330 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 04:44:58.527777 0 15 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5126 04:44:58.534056 0 15 28 | B1->B0 | 2727 4646 | 0 0 | (1 1) (0 0)
5127 04:44:58.537764 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5128 04:44:58.541033 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 04:44:58.547524 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 04:44:58.550944 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 04:44:58.553897 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 04:44:58.560439 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 04:44:58.563880 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5134 04:44:58.567561 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5135 04:44:58.573988 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5136 04:44:58.577461 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 04:44:58.580411 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 04:44:58.583912 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 04:44:58.590610 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 04:44:58.593793 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 04:44:58.597134 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 04:44:58.603683 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 04:44:58.607104 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 04:44:58.610537 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 04:44:58.617558 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 04:44:58.620704 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 04:44:58.623786 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 04:44:58.630526 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 04:44:58.633914 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5150 04:44:58.637199 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5151 04:44:58.643943 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 04:44:58.644026 Total UI for P1: 0, mck2ui 16
5153 04:44:58.650356 best dqsien dly found for B0: ( 1, 2, 26)
5154 04:44:58.650439 Total UI for P1: 0, mck2ui 16
5155 04:44:58.656908 best dqsien dly found for B1: ( 1, 2, 30)
5156 04:44:58.660429 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5157 04:44:58.663376 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5158 04:44:58.663458
5159 04:44:58.666842 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5160 04:44:58.670286 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5161 04:44:58.673576 [Gating] SW calibration Done
5162 04:44:58.673659 ==
5163 04:44:58.676987 Dram Type= 6, Freq= 0, CH_0, rank 0
5164 04:44:58.680121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 04:44:58.680205 ==
5166 04:44:58.683555 RX Vref Scan: 0
5167 04:44:58.683637
5168 04:44:58.683701 RX Vref 0 -> 0, step: 1
5169 04:44:58.683760
5170 04:44:58.686462 RX Delay -80 -> 252, step: 8
5171 04:44:58.693256 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5172 04:44:58.696795 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5173 04:44:58.699917 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5174 04:44:58.703372 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5175 04:44:58.706699 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5176 04:44:58.710049 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5177 04:44:58.716428 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5178 04:44:58.719909 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5179 04:44:58.723437 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5180 04:44:58.726732 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5181 04:44:58.729882 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5182 04:44:58.733233 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5183 04:44:58.740003 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5184 04:44:58.743454 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5185 04:44:58.746773 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5186 04:44:58.749666 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5187 04:44:58.749749 ==
5188 04:44:58.753192 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 04:44:58.756669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 04:44:58.756753 ==
5191 04:44:58.759694 DQS Delay:
5192 04:44:58.759790 DQS0 = 0, DQS1 = 0
5193 04:44:58.763206 DQM Delay:
5194 04:44:58.763304 DQM0 = 105, DQM1 = 90
5195 04:44:58.766201 DQ Delay:
5196 04:44:58.766373 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5197 04:44:58.772995 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5198 04:44:58.776137 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5199 04:44:58.779607 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5200 04:44:58.779689
5201 04:44:58.779755
5202 04:44:58.779814 ==
5203 04:44:58.782991 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 04:44:58.786436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 04:44:58.786519 ==
5206 04:44:58.786585
5207 04:44:58.786646
5208 04:44:58.789885 TX Vref Scan disable
5209 04:44:58.790353 == TX Byte 0 ==
5210 04:44:58.796855 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5211 04:44:58.800084 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5212 04:44:58.800556 == TX Byte 1 ==
5213 04:44:58.806685 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5214 04:44:58.810052 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5215 04:44:58.810531 ==
5216 04:44:58.812985 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 04:44:58.816822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 04:44:58.817253 ==
5219 04:44:58.817594
5220 04:44:58.817907
5221 04:44:58.819745 TX Vref Scan disable
5222 04:44:58.823338 == TX Byte 0 ==
5223 04:44:58.826205 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5224 04:44:58.829599 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5225 04:44:58.833213 == TX Byte 1 ==
5226 04:44:58.836282 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5227 04:44:58.839923 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5228 04:44:58.840395
5229 04:44:58.843124 [DATLAT]
5230 04:44:58.843554 Freq=933, CH0 RK0
5231 04:44:58.843918
5232 04:44:58.846380 DATLAT Default: 0xd
5233 04:44:58.846853 0, 0xFFFF, sum = 0
5234 04:44:58.849653 1, 0xFFFF, sum = 0
5235 04:44:58.850126 2, 0xFFFF, sum = 0
5236 04:44:58.852890 3, 0xFFFF, sum = 0
5237 04:44:58.853323 4, 0xFFFF, sum = 0
5238 04:44:58.856396 5, 0xFFFF, sum = 0
5239 04:44:58.856832 6, 0xFFFF, sum = 0
5240 04:44:58.859766 7, 0xFFFF, sum = 0
5241 04:44:58.860201 8, 0xFFFF, sum = 0
5242 04:44:58.863290 9, 0xFFFF, sum = 0
5243 04:44:58.863724 10, 0x0, sum = 1
5244 04:44:58.866373 11, 0x0, sum = 2
5245 04:44:58.866809 12, 0x0, sum = 3
5246 04:44:58.869762 13, 0x0, sum = 4
5247 04:44:58.870235 best_step = 11
5248 04:44:58.870578
5249 04:44:58.870896 ==
5250 04:44:58.873356 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 04:44:58.879843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 04:44:58.880276 ==
5253 04:44:58.880615 RX Vref Scan: 1
5254 04:44:58.880931
5255 04:44:58.883169 RX Vref 0 -> 0, step: 1
5256 04:44:58.883598
5257 04:44:58.886691 RX Delay -53 -> 252, step: 4
5258 04:44:58.887119
5259 04:44:58.889711 Set Vref, RX VrefLevel [Byte0]: 57
5260 04:44:58.892980 [Byte1]: 49
5261 04:44:58.893409
5262 04:44:58.896624 Final RX Vref Byte 0 = 57 to rank0
5263 04:44:58.899511 Final RX Vref Byte 1 = 49 to rank0
5264 04:44:58.903514 Final RX Vref Byte 0 = 57 to rank1
5265 04:44:58.906385 Final RX Vref Byte 1 = 49 to rank1==
5266 04:44:58.909542 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 04:44:58.912946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 04:44:58.913402 ==
5269 04:44:58.916101 DQS Delay:
5270 04:44:58.916626 DQS0 = 0, DQS1 = 0
5271 04:44:58.917085 DQM Delay:
5272 04:44:58.919289 DQM0 = 107, DQM1 = 91
5273 04:44:58.919673 DQ Delay:
5274 04:44:58.922744 DQ0 =106, DQ1 =108, DQ2 =102, DQ3 =106
5275 04:44:58.926249 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =116
5276 04:44:58.929142 DQ8 =88, DQ9 =76, DQ10 =92, DQ11 =90
5277 04:44:58.933024 DQ12 =94, DQ13 =92, DQ14 =102, DQ15 =100
5278 04:44:58.936351
5279 04:44:58.936742
5280 04:44:58.942502 [DQSOSCAuto] RK0, (LSB)MR18= 0x201c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5281 04:44:58.945890 CH0 RK0: MR19=505, MR18=201C
5282 04:44:58.952445 CH0_RK0: MR19=0x505, MR18=0x201C, DQSOSC=411, MR23=63, INC=64, DEC=42
5283 04:44:58.952848
5284 04:44:58.955866 ----->DramcWriteLeveling(PI) begin...
5285 04:44:58.956252 ==
5286 04:44:58.959198 Dram Type= 6, Freq= 0, CH_0, rank 1
5287 04:44:58.962749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 04:44:58.963154 ==
5289 04:44:58.966022 Write leveling (Byte 0): 32 => 32
5290 04:44:58.969517 Write leveling (Byte 1): 29 => 29
5291 04:44:58.972423 DramcWriteLeveling(PI) end<-----
5292 04:44:58.972938
5293 04:44:58.973391 ==
5294 04:44:58.975826 Dram Type= 6, Freq= 0, CH_0, rank 1
5295 04:44:58.979159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 04:44:58.979541 ==
5297 04:44:58.982652 [Gating] SW mode calibration
5298 04:44:58.989069 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5299 04:44:58.995946 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5300 04:44:58.999127 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 04:44:59.002467 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 04:44:59.008907 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 04:44:59.012545 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 04:44:59.015434 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 04:44:59.022414 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 04:44:59.025931 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5307 04:44:59.028863 0 14 28 | B1->B0 | 2e2e 2727 | 0 0 | (0 0) (0 0)
5308 04:44:59.035178 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 04:44:59.038736 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 04:44:59.042360 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 04:44:59.048848 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 04:44:59.052319 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 04:44:59.055123 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 04:44:59.061809 0 15 24 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
5315 04:44:59.065191 0 15 28 | B1->B0 | 3838 3d3c | 0 1 | (0 0) (0 0)
5316 04:44:59.068649 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 04:44:59.075032 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 04:44:59.078413 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 04:44:59.081998 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 04:44:59.088547 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 04:44:59.091701 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 04:44:59.095278 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 04:44:59.101824 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5324 04:44:59.105286 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5325 04:44:59.108665 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 04:44:59.115345 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 04:44:59.118732 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 04:44:59.122178 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 04:44:59.128726 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 04:44:59.131762 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 04:44:59.135181 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 04:44:59.141743 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 04:44:59.145132 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 04:44:59.148282 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 04:44:59.151565 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 04:44:59.158363 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 04:44:59.161593 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 04:44:59.164933 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 04:44:59.171895 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5340 04:44:59.174887 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 04:44:59.178379 Total UI for P1: 0, mck2ui 16
5342 04:44:59.181763 best dqsien dly found for B0: ( 1, 2, 28)
5343 04:44:59.185203 Total UI for P1: 0, mck2ui 16
5344 04:44:59.188177 best dqsien dly found for B1: ( 1, 2, 28)
5345 04:44:59.191648 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5346 04:44:59.194932 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5347 04:44:59.195319
5348 04:44:59.198427 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5349 04:44:59.201816 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5350 04:44:59.204890 [Gating] SW calibration Done
5351 04:44:59.205276 ==
5352 04:44:59.208314 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 04:44:59.214753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 04:44:59.215157 ==
5355 04:44:59.215512 RX Vref Scan: 0
5356 04:44:59.215843
5357 04:44:59.218174 RX Vref 0 -> 0, step: 1
5358 04:44:59.218540
5359 04:44:59.221542 RX Delay -80 -> 252, step: 8
5360 04:44:59.224926 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5361 04:44:59.228069 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5362 04:44:59.231443 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5363 04:44:59.234897 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5364 04:44:59.238220 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5365 04:44:59.244866 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5366 04:44:59.248220 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5367 04:44:59.251504 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5368 04:44:59.255032 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5369 04:44:59.258412 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5370 04:44:59.265072 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5371 04:44:59.267923 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5372 04:44:59.271161 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5373 04:44:59.274774 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5374 04:44:59.278154 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5375 04:44:59.281149 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5376 04:44:59.281523 ==
5377 04:44:59.284676 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 04:44:59.291521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 04:44:59.291914 ==
5380 04:44:59.292234 DQS Delay:
5381 04:44:59.294458 DQS0 = 0, DQS1 = 0
5382 04:44:59.294824 DQM Delay:
5383 04:44:59.297735 DQM0 = 104, DQM1 = 90
5384 04:44:59.298116 DQ Delay:
5385 04:44:59.301503 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5386 04:44:59.304604 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5387 04:44:59.307966 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5388 04:44:59.311470 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5389 04:44:59.311991
5390 04:44:59.312468
5391 04:44:59.312935 ==
5392 04:44:59.314379 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 04:44:59.317919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 04:44:59.318317 ==
5395 04:44:59.318649
5396 04:44:59.318950
5397 04:44:59.321203 TX Vref Scan disable
5398 04:44:59.324409 == TX Byte 0 ==
5399 04:44:59.327712 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5400 04:44:59.330999 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5401 04:44:59.334399 == TX Byte 1 ==
5402 04:44:59.337707 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5403 04:44:59.341102 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5404 04:44:59.341482 ==
5405 04:44:59.344584 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 04:44:59.350851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 04:44:59.351368 ==
5408 04:44:59.351838
5409 04:44:59.352318
5410 04:44:59.352663 TX Vref Scan disable
5411 04:44:59.355146 == TX Byte 0 ==
5412 04:44:59.358398 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5413 04:44:59.361684 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5414 04:44:59.365078 == TX Byte 1 ==
5415 04:44:59.367911 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5416 04:44:59.374716 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5417 04:44:59.375127
5418 04:44:59.375464 [DATLAT]
5419 04:44:59.375801 Freq=933, CH0 RK1
5420 04:44:59.376119
5421 04:44:59.378101 DATLAT Default: 0xb
5422 04:44:59.378595 0, 0xFFFF, sum = 0
5423 04:44:59.381727 1, 0xFFFF, sum = 0
5424 04:44:59.384644 2, 0xFFFF, sum = 0
5425 04:44:59.385102 3, 0xFFFF, sum = 0
5426 04:44:59.387962 4, 0xFFFF, sum = 0
5427 04:44:59.388468 5, 0xFFFF, sum = 0
5428 04:44:59.391427 6, 0xFFFF, sum = 0
5429 04:44:59.392021 7, 0xFFFF, sum = 0
5430 04:44:59.394334 8, 0xFFFF, sum = 0
5431 04:44:59.394792 9, 0xFFFF, sum = 0
5432 04:44:59.397652 10, 0x0, sum = 1
5433 04:44:59.398246 11, 0x0, sum = 2
5434 04:44:59.401108 12, 0x0, sum = 3
5435 04:44:59.401701 13, 0x0, sum = 4
5436 04:44:59.402251 best_step = 11
5437 04:44:59.402734
5438 04:44:59.404364 ==
5439 04:44:59.407749 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 04:44:59.411206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 04:44:59.411684 ==
5442 04:44:59.412047 RX Vref Scan: 0
5443 04:44:59.412367
5444 04:44:59.414648 RX Vref 0 -> 0, step: 1
5445 04:44:59.415076
5446 04:44:59.418091 RX Delay -53 -> 252, step: 4
5447 04:44:59.421427 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5448 04:44:59.427827 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5449 04:44:59.431103 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5450 04:44:59.434475 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5451 04:44:59.438173 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5452 04:44:59.441205 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5453 04:44:59.447525 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5454 04:44:59.450850 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5455 04:44:59.454246 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5456 04:44:59.457617 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5457 04:44:59.460685 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5458 04:44:59.464023 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5459 04:44:59.470897 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5460 04:44:59.473967 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5461 04:44:59.477360 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5462 04:44:59.480756 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5463 04:44:59.480830 ==
5464 04:44:59.484260 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 04:44:59.490628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 04:44:59.490804 ==
5467 04:44:59.490961 DQS Delay:
5468 04:44:59.494055 DQS0 = 0, DQS1 = 0
5469 04:44:59.494155 DQM Delay:
5470 04:44:59.494228 DQM0 = 104, DQM1 = 92
5471 04:44:59.497432 DQ Delay:
5472 04:44:59.500394 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5473 04:44:59.503955 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =112
5474 04:44:59.507264 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5475 04:44:59.510587 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =98
5476 04:44:59.510674
5477 04:44:59.510740
5478 04:44:59.517324 [DQSOSCAuto] RK1, (LSB)MR18= 0x2607, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5479 04:44:59.520313 CH0 RK1: MR19=505, MR18=2607
5480 04:44:59.526798 CH0_RK1: MR19=0x505, MR18=0x2607, DQSOSC=409, MR23=63, INC=64, DEC=43
5481 04:44:59.530277 [RxdqsGatingPostProcess] freq 933
5482 04:44:59.536830 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5483 04:44:59.540226 best DQS0 dly(2T, 0.5T) = (0, 10)
5484 04:44:59.540311 best DQS1 dly(2T, 0.5T) = (0, 10)
5485 04:44:59.543558 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5486 04:44:59.546943 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5487 04:44:59.550267 best DQS0 dly(2T, 0.5T) = (0, 10)
5488 04:44:59.553579 best DQS1 dly(2T, 0.5T) = (0, 10)
5489 04:44:59.556625 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5490 04:44:59.560099 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5491 04:44:59.563428 Pre-setting of DQS Precalculation
5492 04:44:59.570066 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5493 04:44:59.570177 ==
5494 04:44:59.572871 Dram Type= 6, Freq= 0, CH_1, rank 0
5495 04:44:59.576447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 04:44:59.576554 ==
5497 04:44:59.583340 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5498 04:44:59.586373 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5499 04:44:59.590797 [CA 0] Center 37 (7~68) winsize 62
5500 04:44:59.594111 [CA 1] Center 37 (7~68) winsize 62
5501 04:44:59.597669 [CA 2] Center 35 (5~66) winsize 62
5502 04:44:59.600671 [CA 3] Center 34 (4~65) winsize 62
5503 04:44:59.604121 [CA 4] Center 34 (4~65) winsize 62
5504 04:44:59.607606 [CA 5] Center 34 (4~65) winsize 62
5505 04:44:59.607712
5506 04:44:59.610538 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5507 04:44:59.610675
5508 04:44:59.613831 [CATrainingPosCal] consider 1 rank data
5509 04:44:59.617391 u2DelayCellTimex100 = 270/100 ps
5510 04:44:59.620794 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5511 04:44:59.623902 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5512 04:44:59.630924 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5513 04:44:59.633825 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5514 04:44:59.637222 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5515 04:44:59.640474 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5516 04:44:59.640608
5517 04:44:59.643764 CA PerBit enable=1, Macro0, CA PI delay=34
5518 04:44:59.643868
5519 04:44:59.647136 [CBTSetCACLKResult] CA Dly = 34
5520 04:44:59.647235 CS Dly: 6 (0~37)
5521 04:44:59.650400 ==
5522 04:44:59.650533 Dram Type= 6, Freq= 0, CH_1, rank 1
5523 04:44:59.657216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5524 04:44:59.657322 ==
5525 04:44:59.660645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5526 04:44:59.667051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5527 04:44:59.670612 [CA 0] Center 37 (7~68) winsize 62
5528 04:44:59.673978 [CA 1] Center 37 (7~68) winsize 62
5529 04:44:59.677330 [CA 2] Center 36 (6~66) winsize 61
5530 04:44:59.680460 [CA 3] Center 35 (5~65) winsize 61
5531 04:44:59.683729 [CA 4] Center 35 (6~65) winsize 60
5532 04:44:59.687528 [CA 5] Center 34 (5~64) winsize 60
5533 04:44:59.687646
5534 04:44:59.690379 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5535 04:44:59.690481
5536 04:44:59.693741 [CATrainingPosCal] consider 2 rank data
5537 04:44:59.697098 u2DelayCellTimex100 = 270/100 ps
5538 04:44:59.700271 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5539 04:44:59.707115 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5540 04:44:59.710613 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5541 04:44:59.713916 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5542 04:44:59.717306 CA4 delay=35 (6~65),Diff = 1 PI (6 cell)
5543 04:44:59.720266 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5544 04:44:59.720369
5545 04:44:59.723600 CA PerBit enable=1, Macro0, CA PI delay=34
5546 04:44:59.723702
5547 04:44:59.727145 [CBTSetCACLKResult] CA Dly = 34
5548 04:44:59.727247 CS Dly: 7 (0~39)
5549 04:44:59.730644
5550 04:44:59.733596 ----->DramcWriteLeveling(PI) begin...
5551 04:44:59.733700 ==
5552 04:44:59.737054 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 04:44:59.740185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 04:44:59.740293 ==
5555 04:44:59.743555 Write leveling (Byte 0): 25 => 25
5556 04:44:59.746876 Write leveling (Byte 1): 29 => 29
5557 04:44:59.750241 DramcWriteLeveling(PI) end<-----
5558 04:44:59.750317
5559 04:44:59.750398 ==
5560 04:44:59.753471 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 04:44:59.757255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 04:44:59.757370 ==
5563 04:44:59.760270 [Gating] SW mode calibration
5564 04:44:59.767136 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5565 04:44:59.773741 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5566 04:44:59.777177 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 04:44:59.780422 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 04:44:59.786986 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 04:44:59.790200 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 04:44:59.793403 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 04:44:59.800213 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 04:44:59.803725 0 14 24 | B1->B0 | 3131 3030 | 0 1 | (0 0) (1 0)
5573 04:44:59.806650 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
5574 04:44:59.810245 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 04:44:59.817082 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 04:44:59.819927 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 04:44:59.823685 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 04:44:59.830110 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 04:44:59.833577 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 04:44:59.836504 0 15 24 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (1 1)
5581 04:44:59.843485 0 15 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5582 04:44:59.846732 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 04:44:59.850124 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 04:44:59.856759 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 04:44:59.859902 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 04:44:59.863470 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 04:44:59.869838 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 04:44:59.873391 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5589 04:44:59.876632 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5590 04:44:59.883128 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 04:44:59.886616 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 04:44:59.889849 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 04:44:59.896386 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 04:44:59.899651 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 04:44:59.903119 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 04:44:59.909707 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 04:44:59.913168 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 04:44:59.916538 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 04:44:59.922901 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 04:44:59.926532 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 04:44:59.930030 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 04:44:59.936476 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 04:44:59.939571 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 04:44:59.943005 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5605 04:44:59.946440 Total UI for P1: 0, mck2ui 16
5606 04:44:59.949803 best dqsien dly found for B0: ( 1, 2, 22)
5607 04:44:59.956355 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 04:44:59.956439 Total UI for P1: 0, mck2ui 16
5609 04:44:59.959724 best dqsien dly found for B1: ( 1, 2, 24)
5610 04:44:59.965862 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5611 04:44:59.969316 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5612 04:44:59.969403
5613 04:44:59.972368 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5614 04:44:59.975755 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5615 04:44:59.979127 [Gating] SW calibration Done
5616 04:44:59.979215 ==
5617 04:44:59.982436 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 04:44:59.985540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 04:44:59.985626 ==
5620 04:44:59.988997 RX Vref Scan: 0
5621 04:44:59.989082
5622 04:44:59.989148 RX Vref 0 -> 0, step: 1
5623 04:44:59.989211
5624 04:44:59.992476 RX Delay -80 -> 252, step: 8
5625 04:44:59.995799 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5626 04:45:00.002294 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5627 04:45:00.005685 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5628 04:45:00.008730 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5629 04:45:00.012152 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5630 04:45:00.015613 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5631 04:45:00.019106 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5632 04:45:00.025417 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5633 04:45:00.028639 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5634 04:45:00.031948 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5635 04:45:00.035354 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5636 04:45:00.038354 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5637 04:45:00.041858 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5638 04:45:00.048385 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5639 04:45:00.051750 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5640 04:45:00.055118 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5641 04:45:00.055194 ==
5642 04:45:00.058238 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 04:45:00.061630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 04:45:00.061734 ==
5645 04:45:00.065160 DQS Delay:
5646 04:45:00.065234 DQS0 = 0, DQS1 = 0
5647 04:45:00.068063 DQM Delay:
5648 04:45:00.068158 DQM0 = 101, DQM1 = 95
5649 04:45:00.071415 DQ Delay:
5650 04:45:00.071498 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5651 04:45:00.074897 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5652 04:45:00.078325 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5653 04:45:00.084738 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5654 04:45:00.084823
5655 04:45:00.084890
5656 04:45:00.084977 ==
5657 04:45:00.088340 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 04:45:00.091608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 04:45:00.091681 ==
5660 04:45:00.091741
5661 04:45:00.091799
5662 04:45:00.095002 TX Vref Scan disable
5663 04:45:00.095082 == TX Byte 0 ==
5664 04:45:00.101656 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5665 04:45:00.105063 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5666 04:45:00.105157 == TX Byte 1 ==
5667 04:45:00.111278 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5668 04:45:00.114737 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5669 04:45:00.114840 ==
5670 04:45:00.118206 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 04:45:00.121260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 04:45:00.121357 ==
5673 04:45:00.121447
5674 04:45:00.121536
5675 04:45:00.124679 TX Vref Scan disable
5676 04:45:00.128071 == TX Byte 0 ==
5677 04:45:00.131347 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5678 04:45:00.134321 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5679 04:45:00.138071 == TX Byte 1 ==
5680 04:45:00.141067 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5681 04:45:00.144615 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5682 04:45:00.144686
5683 04:45:00.148152 [DATLAT]
5684 04:45:00.148246 Freq=933, CH1 RK0
5685 04:45:00.148336
5686 04:45:00.151105 DATLAT Default: 0xd
5687 04:45:00.151174 0, 0xFFFF, sum = 0
5688 04:45:00.154651 1, 0xFFFF, sum = 0
5689 04:45:00.154720 2, 0xFFFF, sum = 0
5690 04:45:00.158109 3, 0xFFFF, sum = 0
5691 04:45:00.158212 4, 0xFFFF, sum = 0
5692 04:45:00.161358 5, 0xFFFF, sum = 0
5693 04:45:00.161453 6, 0xFFFF, sum = 0
5694 04:45:00.164738 7, 0xFFFF, sum = 0
5695 04:45:00.164840 8, 0xFFFF, sum = 0
5696 04:45:00.168097 9, 0xFFFF, sum = 0
5697 04:45:00.168195 10, 0x0, sum = 1
5698 04:45:00.170899 11, 0x0, sum = 2
5699 04:45:00.170970 12, 0x0, sum = 3
5700 04:45:00.174769 13, 0x0, sum = 4
5701 04:45:00.174841 best_step = 11
5702 04:45:00.174902
5703 04:45:00.174959 ==
5704 04:45:00.177654 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 04:45:00.184221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 04:45:00.184324 ==
5707 04:45:00.184415 RX Vref Scan: 1
5708 04:45:00.184502
5709 04:45:00.187800 RX Vref 0 -> 0, step: 1
5710 04:45:00.187873
5711 04:45:00.191030 RX Delay -53 -> 252, step: 4
5712 04:45:00.191105
5713 04:45:00.194439 Set Vref, RX VrefLevel [Byte0]: 54
5714 04:45:00.197634 [Byte1]: 48
5715 04:45:00.197752
5716 04:45:00.201151 Final RX Vref Byte 0 = 54 to rank0
5717 04:45:00.204127 Final RX Vref Byte 1 = 48 to rank0
5718 04:45:00.207772 Final RX Vref Byte 0 = 54 to rank1
5719 04:45:00.210973 Final RX Vref Byte 1 = 48 to rank1==
5720 04:45:00.214121 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 04:45:00.217400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 04:45:00.217486 ==
5723 04:45:00.220875 DQS Delay:
5724 04:45:00.220984 DQS0 = 0, DQS1 = 0
5725 04:45:00.224403 DQM Delay:
5726 04:45:00.224512 DQM0 = 104, DQM1 = 96
5727 04:45:00.224613 DQ Delay:
5728 04:45:00.227395 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5729 04:45:00.230906 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5730 04:45:00.234309 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =90
5731 04:45:00.240854 DQ12 =106, DQ13 =100, DQ14 =104, DQ15 =102
5732 04:45:00.240960
5733 04:45:00.241052
5734 04:45:00.247494 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5735 04:45:00.250978 CH1 RK0: MR19=505, MR18=1C35
5736 04:45:00.257362 CH1_RK0: MR19=0x505, MR18=0x1C35, DQSOSC=405, MR23=63, INC=66, DEC=44
5737 04:45:00.257433
5738 04:45:00.260848 ----->DramcWriteLeveling(PI) begin...
5739 04:45:00.260948 ==
5740 04:45:00.263926 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 04:45:00.267709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 04:45:00.267787 ==
5743 04:45:00.270591 Write leveling (Byte 0): 27 => 27
5744 04:45:00.274277 Write leveling (Byte 1): 28 => 28
5745 04:45:00.277594 DramcWriteLeveling(PI) end<-----
5746 04:45:00.277664
5747 04:45:00.277725 ==
5748 04:45:00.280497 Dram Type= 6, Freq= 0, CH_1, rank 1
5749 04:45:00.283925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 04:45:00.283994 ==
5751 04:45:00.287442 [Gating] SW mode calibration
5752 04:45:00.293749 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5753 04:45:00.300595 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5754 04:45:00.304055 0 14 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5755 04:45:00.310648 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 04:45:00.313872 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 04:45:00.317372 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 04:45:00.320432 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 04:45:00.327216 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 04:45:00.330618 0 14 24 | B1->B0 | 3131 3333 | 1 1 | (1 0) (1 0)
5761 04:45:00.333923 0 14 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5762 04:45:00.340464 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5763 04:45:00.343787 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 04:45:00.347108 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 04:45:00.353563 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 04:45:00.357067 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 04:45:00.360609 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 04:45:00.367025 0 15 24 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
5769 04:45:00.370226 0 15 28 | B1->B0 | 4141 3a39 | 0 1 | (0 0) (0 0)
5770 04:45:00.373542 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 04:45:00.380403 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 04:45:00.383701 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 04:45:00.387218 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 04:45:00.393766 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 04:45:00.397157 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 04:45:00.400311 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5777 04:45:00.406756 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 04:45:00.410255 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 04:45:00.413527 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 04:45:00.420070 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 04:45:00.423443 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 04:45:00.426898 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 04:45:00.433441 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 04:45:00.436831 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 04:45:00.439882 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 04:45:00.446875 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 04:45:00.449825 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 04:45:00.453357 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 04:45:00.459908 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 04:45:00.463427 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 04:45:00.466899 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5792 04:45:00.473371 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5793 04:45:00.476637 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5794 04:45:00.479878 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 04:45:00.483184 Total UI for P1: 0, mck2ui 16
5796 04:45:00.486419 best dqsien dly found for B0: ( 1, 2, 26)
5797 04:45:00.489908 Total UI for P1: 0, mck2ui 16
5798 04:45:00.493420 best dqsien dly found for B1: ( 1, 2, 24)
5799 04:45:00.496797 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5800 04:45:00.499744 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5801 04:45:00.499828
5802 04:45:00.503406 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5803 04:45:00.506655 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5804 04:45:00.509876 [Gating] SW calibration Done
5805 04:45:00.509966 ==
5806 04:45:00.513170 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 04:45:00.519876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 04:45:00.519960 ==
5809 04:45:00.520025 RX Vref Scan: 0
5810 04:45:00.520086
5811 04:45:00.523211 RX Vref 0 -> 0, step: 1
5812 04:45:00.523294
5813 04:45:00.526669 RX Delay -80 -> 252, step: 8
5814 04:45:00.529719 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5815 04:45:00.533177 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5816 04:45:00.536666 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5817 04:45:00.539599 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5818 04:45:00.546128 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5819 04:45:00.549720 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5820 04:45:00.553068 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5821 04:45:00.556563 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5822 04:45:00.560105 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5823 04:45:00.563014 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5824 04:45:00.566472 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5825 04:45:00.573161 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5826 04:45:00.576460 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5827 04:45:00.579806 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5828 04:45:00.583188 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5829 04:45:00.586367 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5830 04:45:00.586468 ==
5831 04:45:00.589548 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 04:45:00.596267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 04:45:00.596365 ==
5834 04:45:00.596433 DQS Delay:
5835 04:45:00.599690 DQS0 = 0, DQS1 = 0
5836 04:45:00.599778 DQM Delay:
5837 04:45:00.602616 DQM0 = 101, DQM1 = 95
5838 04:45:00.602699 DQ Delay:
5839 04:45:00.606009 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5840 04:45:00.609755 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5841 04:45:00.612700 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5842 04:45:00.616220 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =107
5843 04:45:00.616303
5844 04:45:00.616369
5845 04:45:00.616428 ==
5846 04:45:00.619469 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 04:45:00.622772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 04:45:00.622857 ==
5849 04:45:00.622923
5850 04:45:00.622984
5851 04:45:00.625973 TX Vref Scan disable
5852 04:45:00.629537 == TX Byte 0 ==
5853 04:45:00.632464 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5854 04:45:00.635951 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5855 04:45:00.639491 == TX Byte 1 ==
5856 04:45:00.642423 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5857 04:45:00.645925 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5858 04:45:00.646048 ==
5859 04:45:00.649389 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 04:45:00.655715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 04:45:00.655799 ==
5862 04:45:00.655866
5863 04:45:00.655926
5864 04:45:00.655985 TX Vref Scan disable
5865 04:45:00.660125 == TX Byte 0 ==
5866 04:45:00.663123 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5867 04:45:00.670088 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5868 04:45:00.670172 == TX Byte 1 ==
5869 04:45:00.673073 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5870 04:45:00.679761 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5871 04:45:00.679850
5872 04:45:00.679916 [DATLAT]
5873 04:45:00.679977 Freq=933, CH1 RK1
5874 04:45:00.680037
5875 04:45:00.682945 DATLAT Default: 0xb
5876 04:45:00.683028 0, 0xFFFF, sum = 0
5877 04:45:00.686230 1, 0xFFFF, sum = 0
5878 04:45:00.686315 2, 0xFFFF, sum = 0
5879 04:45:00.689607 3, 0xFFFF, sum = 0
5880 04:45:00.689692 4, 0xFFFF, sum = 0
5881 04:45:00.693414 5, 0xFFFF, sum = 0
5882 04:45:00.696709 6, 0xFFFF, sum = 0
5883 04:45:00.696802 7, 0xFFFF, sum = 0
5884 04:45:00.699536 8, 0xFFFF, sum = 0
5885 04:45:00.699622 9, 0xFFFF, sum = 0
5886 04:45:00.703061 10, 0x0, sum = 1
5887 04:45:00.703146 11, 0x0, sum = 2
5888 04:45:00.703214 12, 0x0, sum = 3
5889 04:45:00.706443 13, 0x0, sum = 4
5890 04:45:00.706528 best_step = 11
5891 04:45:00.706594
5892 04:45:00.709965 ==
5893 04:45:00.710063 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 04:45:00.716556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 04:45:00.716641 ==
5896 04:45:00.716707 RX Vref Scan: 0
5897 04:45:00.716768
5898 04:45:00.719967 RX Vref 0 -> 0, step: 1
5899 04:45:00.720051
5900 04:45:00.723216 RX Delay -53 -> 252, step: 4
5901 04:45:00.726498 iDelay=199, Bit 0, Center 110 (31 ~ 190) 160
5902 04:45:00.733157 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5903 04:45:00.736569 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5904 04:45:00.739570 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5905 04:45:00.742932 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5906 04:45:00.746393 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5907 04:45:00.752874 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5908 04:45:00.756393 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5909 04:45:00.759675 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5910 04:45:00.763133 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5911 04:45:00.766109 iDelay=199, Bit 10, Center 100 (19 ~ 182) 164
5912 04:45:00.769584 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5913 04:45:00.776103 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5914 04:45:00.779488 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5915 04:45:00.782817 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5916 04:45:00.786214 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5917 04:45:00.786298 ==
5918 04:45:00.789477 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 04:45:00.796016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 04:45:00.796102 ==
5921 04:45:00.796169 DQS Delay:
5922 04:45:00.799710 DQS0 = 0, DQS1 = 0
5923 04:45:00.799794 DQM Delay:
5924 04:45:00.799860 DQM0 = 104, DQM1 = 97
5925 04:45:00.802985 DQ Delay:
5926 04:45:00.806390 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5927 04:45:00.809416 DQ4 =106, DQ5 =114, DQ6 =110, DQ7 =102
5928 04:45:00.812798 DQ8 =84, DQ9 =86, DQ10 =100, DQ11 =92
5929 04:45:00.816113 DQ12 =104, DQ13 =104, DQ14 =104, DQ15 =106
5930 04:45:00.816198
5931 04:45:00.816264
5932 04:45:00.822619 [DQSOSCAuto] RK1, (LSB)MR18= 0x2200, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
5933 04:45:00.826125 CH1 RK1: MR19=505, MR18=2200
5934 04:45:00.832825 CH1_RK1: MR19=0x505, MR18=0x2200, DQSOSC=411, MR23=63, INC=64, DEC=42
5935 04:45:00.836119 [RxdqsGatingPostProcess] freq 933
5936 04:45:00.842987 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5937 04:45:00.843072 best DQS0 dly(2T, 0.5T) = (0, 10)
5938 04:45:00.846431 best DQS1 dly(2T, 0.5T) = (0, 10)
5939 04:45:00.849373 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5940 04:45:00.852923 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5941 04:45:00.856425 best DQS0 dly(2T, 0.5T) = (0, 10)
5942 04:45:00.859870 best DQS1 dly(2T, 0.5T) = (0, 10)
5943 04:45:00.862924 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5944 04:45:00.866291 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5945 04:45:00.869743 Pre-setting of DQS Precalculation
5946 04:45:00.876137 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5947 04:45:00.883049 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5948 04:45:00.889660 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5949 04:45:00.889744
5950 04:45:00.889810
5951 04:45:00.893096 [Calibration Summary] 1866 Mbps
5952 04:45:00.893180 CH 0, Rank 0
5953 04:45:00.896370 SW Impedance : PASS
5954 04:45:00.899713 DUTY Scan : NO K
5955 04:45:00.899797 ZQ Calibration : PASS
5956 04:45:00.902557 Jitter Meter : NO K
5957 04:45:00.902640 CBT Training : PASS
5958 04:45:00.906248 Write leveling : PASS
5959 04:45:00.909520 RX DQS gating : PASS
5960 04:45:00.909625 RX DQ/DQS(RDDQC) : PASS
5961 04:45:00.912470 TX DQ/DQS : PASS
5962 04:45:00.915919 RX DATLAT : PASS
5963 04:45:00.916003 RX DQ/DQS(Engine): PASS
5964 04:45:00.919344 TX OE : NO K
5965 04:45:00.919428 All Pass.
5966 04:45:00.919495
5967 04:45:00.922545 CH 0, Rank 1
5968 04:45:00.922629 SW Impedance : PASS
5969 04:45:00.925764 DUTY Scan : NO K
5970 04:45:00.929182 ZQ Calibration : PASS
5971 04:45:00.929267 Jitter Meter : NO K
5972 04:45:00.932556 CBT Training : PASS
5973 04:45:00.935953 Write leveling : PASS
5974 04:45:00.936051 RX DQS gating : PASS
5975 04:45:00.939165 RX DQ/DQS(RDDQC) : PASS
5976 04:45:00.942455 TX DQ/DQS : PASS
5977 04:45:00.942540 RX DATLAT : PASS
5978 04:45:00.945967 RX DQ/DQS(Engine): PASS
5979 04:45:00.949090 TX OE : NO K
5980 04:45:00.949173 All Pass.
5981 04:45:00.949240
5982 04:45:00.949302 CH 1, Rank 0
5983 04:45:00.952559 SW Impedance : PASS
5984 04:45:00.955569 DUTY Scan : NO K
5985 04:45:00.955653 ZQ Calibration : PASS
5986 04:45:00.959173 Jitter Meter : NO K
5987 04:45:00.959257 CBT Training : PASS
5988 04:45:00.962535 Write leveling : PASS
5989 04:45:00.965490 RX DQS gating : PASS
5990 04:45:00.965573 RX DQ/DQS(RDDQC) : PASS
5991 04:45:00.968841 TX DQ/DQS : PASS
5992 04:45:00.972176 RX DATLAT : PASS
5993 04:45:00.972283 RX DQ/DQS(Engine): PASS
5994 04:45:00.975697 TX OE : NO K
5995 04:45:00.975781 All Pass.
5996 04:45:00.975847
5997 04:45:00.978735 CH 1, Rank 1
5998 04:45:00.978820 SW Impedance : PASS
5999 04:45:00.982155 DUTY Scan : NO K
6000 04:45:00.985623 ZQ Calibration : PASS
6001 04:45:00.985707 Jitter Meter : NO K
6002 04:45:00.989107 CBT Training : PASS
6003 04:45:00.992546 Write leveling : PASS
6004 04:45:00.992630 RX DQS gating : PASS
6005 04:45:00.995819 RX DQ/DQS(RDDQC) : PASS
6006 04:45:00.999181 TX DQ/DQS : PASS
6007 04:45:00.999265 RX DATLAT : PASS
6008 04:45:01.002149 RX DQ/DQS(Engine): PASS
6009 04:45:01.002233 TX OE : NO K
6010 04:45:01.005349 All Pass.
6011 04:45:01.005434
6012 04:45:01.005500 DramC Write-DBI off
6013 04:45:01.008995 PER_BANK_REFRESH: Hybrid Mode
6014 04:45:01.012226 TX_TRACKING: ON
6015 04:45:01.018677 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6016 04:45:01.022132 [FAST_K] Save calibration result to emmc
6017 04:45:01.028524 dramc_set_vcore_voltage set vcore to 650000
6018 04:45:01.028608 Read voltage for 400, 6
6019 04:45:01.031767 Vio18 = 0
6020 04:45:01.031850 Vcore = 650000
6021 04:45:01.031916 Vdram = 0
6022 04:45:01.031978 Vddq = 0
6023 04:45:01.035192 Vmddr = 0
6024 04:45:01.039045 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6025 04:45:01.045094 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6026 04:45:01.048505 MEM_TYPE=3, freq_sel=20
6027 04:45:01.048589 sv_algorithm_assistance_LP4_800
6028 04:45:01.055457 ============ PULL DRAM RESETB DOWN ============
6029 04:45:01.058434 ========== PULL DRAM RESETB DOWN end =========
6030 04:45:01.061796 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6031 04:45:01.065222 ===================================
6032 04:45:01.068184 LPDDR4 DRAM CONFIGURATION
6033 04:45:01.071615 ===================================
6034 04:45:01.074808 EX_ROW_EN[0] = 0x0
6035 04:45:01.074892 EX_ROW_EN[1] = 0x0
6036 04:45:01.078256 LP4Y_EN = 0x0
6037 04:45:01.078340 WORK_FSP = 0x0
6038 04:45:01.081778 WL = 0x2
6039 04:45:01.081862 RL = 0x2
6040 04:45:01.084706 BL = 0x2
6041 04:45:01.084790 RPST = 0x0
6042 04:45:01.088246 RD_PRE = 0x0
6043 04:45:01.088329 WR_PRE = 0x1
6044 04:45:01.091705 WR_PST = 0x0
6045 04:45:01.091789 DBI_WR = 0x0
6046 04:45:01.095142 DBI_RD = 0x0
6047 04:45:01.098246 OTF = 0x1
6048 04:45:01.098330 ===================================
6049 04:45:01.101385 ===================================
6050 04:45:01.104801 ANA top config
6051 04:45:01.108233 ===================================
6052 04:45:01.111519 DLL_ASYNC_EN = 0
6053 04:45:01.111603 ALL_SLAVE_EN = 1
6054 04:45:01.114812 NEW_RANK_MODE = 1
6055 04:45:01.118129 DLL_IDLE_MODE = 1
6056 04:45:01.121475 LP45_APHY_COMB_EN = 1
6057 04:45:01.124907 TX_ODT_DIS = 1
6058 04:45:01.124991 NEW_8X_MODE = 1
6059 04:45:01.127759 ===================================
6060 04:45:01.131546 ===================================
6061 04:45:01.134692 data_rate = 800
6062 04:45:01.138120 CKR = 1
6063 04:45:01.141402 DQ_P2S_RATIO = 4
6064 04:45:01.144835 ===================================
6065 04:45:01.148071 CA_P2S_RATIO = 4
6066 04:45:01.151439 DQ_CA_OPEN = 0
6067 04:45:01.151523 DQ_SEMI_OPEN = 1
6068 04:45:01.154394 CA_SEMI_OPEN = 1
6069 04:45:01.157885 CA_FULL_RATE = 0
6070 04:45:01.161368 DQ_CKDIV4_EN = 0
6071 04:45:01.164426 CA_CKDIV4_EN = 1
6072 04:45:01.167845 CA_PREDIV_EN = 0
6073 04:45:01.167929 PH8_DLY = 0
6074 04:45:01.170859 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6075 04:45:01.174388 DQ_AAMCK_DIV = 0
6076 04:45:01.177835 CA_AAMCK_DIV = 0
6077 04:45:01.181313 CA_ADMCK_DIV = 4
6078 04:45:01.184278 DQ_TRACK_CA_EN = 0
6079 04:45:01.184361 CA_PICK = 800
6080 04:45:01.187632 CA_MCKIO = 400
6081 04:45:01.191123 MCKIO_SEMI = 400
6082 04:45:01.194194 PLL_FREQ = 3016
6083 04:45:01.197589 DQ_UI_PI_RATIO = 32
6084 04:45:01.200512 CA_UI_PI_RATIO = 32
6085 04:45:01.204331 ===================================
6086 04:45:01.207402 ===================================
6087 04:45:01.210616 memory_type:LPDDR4
6088 04:45:01.210700 GP_NUM : 10
6089 04:45:01.214061 SRAM_EN : 1
6090 04:45:01.214146 MD32_EN : 0
6091 04:45:01.217444 ===================================
6092 04:45:01.220702 [ANA_INIT] >>>>>>>>>>>>>>
6093 04:45:01.223634 <<<<<< [CONFIGURE PHASE]: ANA_TX
6094 04:45:01.227188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6095 04:45:01.230621 ===================================
6096 04:45:01.233880 data_rate = 800,PCW = 0X7400
6097 04:45:01.237316 ===================================
6098 04:45:01.240462 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6099 04:45:01.243896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6100 04:45:01.257363 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6101 04:45:01.260427 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6102 04:45:01.263856 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6103 04:45:01.267431 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6104 04:45:01.270308 [ANA_INIT] flow start
6105 04:45:01.273804 [ANA_INIT] PLL >>>>>>>>
6106 04:45:01.273887 [ANA_INIT] PLL <<<<<<<<
6107 04:45:01.277399 [ANA_INIT] MIDPI >>>>>>>>
6108 04:45:01.280311 [ANA_INIT] MIDPI <<<<<<<<
6109 04:45:01.280395 [ANA_INIT] DLL >>>>>>>>
6110 04:45:01.283794 [ANA_INIT] flow end
6111 04:45:01.287291 ============ LP4 DIFF to SE enter ============
6112 04:45:01.293693 ============ LP4 DIFF to SE exit ============
6113 04:45:01.293778 [ANA_INIT] <<<<<<<<<<<<<
6114 04:45:01.297108 [Flow] Enable top DCM control >>>>>
6115 04:45:01.300551 [Flow] Enable top DCM control <<<<<
6116 04:45:01.303492 Enable DLL master slave shuffle
6117 04:45:01.310147 ==============================================================
6118 04:45:01.310261 Gating Mode config
6119 04:45:01.317105 ==============================================================
6120 04:45:01.320419 Config description:
6121 04:45:01.326676 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6122 04:45:01.333696 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6123 04:45:01.340115 SELPH_MODE 0: By rank 1: By Phase
6124 04:45:01.346650 ==============================================================
6125 04:45:01.346734 GAT_TRACK_EN = 0
6126 04:45:01.349979 RX_GATING_MODE = 2
6127 04:45:01.353233 RX_GATING_TRACK_MODE = 2
6128 04:45:01.356595 SELPH_MODE = 1
6129 04:45:01.360402 PICG_EARLY_EN = 1
6130 04:45:01.363381 VALID_LAT_VALUE = 1
6131 04:45:01.370422 ==============================================================
6132 04:45:01.373403 Enter into Gating configuration >>>>
6133 04:45:01.376923 Exit from Gating configuration <<<<
6134 04:45:01.379970 Enter into DVFS_PRE_config >>>>>
6135 04:45:01.390054 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6136 04:45:01.393110 Exit from DVFS_PRE_config <<<<<
6137 04:45:01.396586 Enter into PICG configuration >>>>
6138 04:45:01.400063 Exit from PICG configuration <<<<
6139 04:45:01.403468 [RX_INPUT] configuration >>>>>
6140 04:45:01.403547 [RX_INPUT] configuration <<<<<
6141 04:45:01.410114 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6142 04:45:01.416838 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6143 04:45:01.420079 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6144 04:45:01.426573 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6145 04:45:01.433421 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6146 04:45:01.439787 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6147 04:45:01.443247 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6148 04:45:01.446337 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6149 04:45:01.453325 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6150 04:45:01.456326 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6151 04:45:01.459665 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6152 04:45:01.466705 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6153 04:45:01.469783 ===================================
6154 04:45:01.469884 LPDDR4 DRAM CONFIGURATION
6155 04:45:01.472894 ===================================
6156 04:45:01.476334 EX_ROW_EN[0] = 0x0
6157 04:45:01.476411 EX_ROW_EN[1] = 0x0
6158 04:45:01.479803 LP4Y_EN = 0x0
6159 04:45:01.479875 WORK_FSP = 0x0
6160 04:45:01.483310 WL = 0x2
6161 04:45:01.483425 RL = 0x2
6162 04:45:01.486484 BL = 0x2
6163 04:45:01.486563 RPST = 0x0
6164 04:45:01.489780 RD_PRE = 0x0
6165 04:45:01.493080 WR_PRE = 0x1
6166 04:45:01.493152 WR_PST = 0x0
6167 04:45:01.496718 DBI_WR = 0x0
6168 04:45:01.496787 DBI_RD = 0x0
6169 04:45:01.499572 OTF = 0x1
6170 04:45:01.503057 ===================================
6171 04:45:01.506486 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6172 04:45:01.510056 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6173 04:45:01.513334 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6174 04:45:01.516558 ===================================
6175 04:45:01.519480 LPDDR4 DRAM CONFIGURATION
6176 04:45:01.522770 ===================================
6177 04:45:01.526166 EX_ROW_EN[0] = 0x10
6178 04:45:01.526239 EX_ROW_EN[1] = 0x0
6179 04:45:01.529796 LP4Y_EN = 0x0
6180 04:45:01.529902 WORK_FSP = 0x0
6181 04:45:01.533071 WL = 0x2
6182 04:45:01.533140 RL = 0x2
6183 04:45:01.536098 BL = 0x2
6184 04:45:01.536166 RPST = 0x0
6185 04:45:01.539560 RD_PRE = 0x0
6186 04:45:01.539637 WR_PRE = 0x1
6187 04:45:01.543050 WR_PST = 0x0
6188 04:45:01.546195 DBI_WR = 0x0
6189 04:45:01.546264 DBI_RD = 0x0
6190 04:45:01.549667 OTF = 0x1
6191 04:45:01.552928 ===================================
6192 04:45:01.556124 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6193 04:45:01.561363 nWR fixed to 30
6194 04:45:01.564729 [ModeRegInit_LP4] CH0 RK0
6195 04:45:01.564819 [ModeRegInit_LP4] CH0 RK1
6196 04:45:01.568018 [ModeRegInit_LP4] CH1 RK0
6197 04:45:01.571512 [ModeRegInit_LP4] CH1 RK1
6198 04:45:01.571581 match AC timing 19
6199 04:45:01.578071 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6200 04:45:01.581080 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6201 04:45:01.584460 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6202 04:45:01.591345 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6203 04:45:01.594580 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6204 04:45:01.594661 ==
6205 04:45:01.598054 Dram Type= 6, Freq= 0, CH_0, rank 0
6206 04:45:01.600975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6207 04:45:01.601050 ==
6208 04:45:01.607877 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6209 04:45:01.614327 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6210 04:45:01.617980 [CA 0] Center 36 (8~64) winsize 57
6211 04:45:01.621102 [CA 1] Center 36 (8~64) winsize 57
6212 04:45:01.624460 [CA 2] Center 36 (8~64) winsize 57
6213 04:45:01.624533 [CA 3] Center 36 (8~64) winsize 57
6214 04:45:01.627662 [CA 4] Center 36 (8~64) winsize 57
6215 04:45:01.630977 [CA 5] Center 36 (8~64) winsize 57
6216 04:45:01.631049
6217 04:45:01.634577 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6218 04:45:01.637864
6219 04:45:01.641460 [CATrainingPosCal] consider 1 rank data
6220 04:45:01.641532 u2DelayCellTimex100 = 270/100 ps
6221 04:45:01.647852 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 04:45:01.651124 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 04:45:01.654670 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 04:45:01.657969 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 04:45:01.661380 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 04:45:01.664736 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 04:45:01.664835
6228 04:45:01.667637 CA PerBit enable=1, Macro0, CA PI delay=36
6229 04:45:01.667712
6230 04:45:01.671361 [CBTSetCACLKResult] CA Dly = 36
6231 04:45:01.674284 CS Dly: 1 (0~32)
6232 04:45:01.674355 ==
6233 04:45:01.677674 Dram Type= 6, Freq= 0, CH_0, rank 1
6234 04:45:01.681203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6235 04:45:01.681279 ==
6236 04:45:01.687532 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6237 04:45:01.690963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6238 04:45:01.694478 [CA 0] Center 36 (8~64) winsize 57
6239 04:45:01.697809 [CA 1] Center 36 (8~64) winsize 57
6240 04:45:01.701166 [CA 2] Center 36 (8~64) winsize 57
6241 04:45:01.704558 [CA 3] Center 36 (8~64) winsize 57
6242 04:45:01.708069 [CA 4] Center 36 (8~64) winsize 57
6243 04:45:01.710989 [CA 5] Center 36 (8~64) winsize 57
6244 04:45:01.711063
6245 04:45:01.714467 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6246 04:45:01.714545
6247 04:45:01.717435 [CATrainingPosCal] consider 2 rank data
6248 04:45:01.720974 u2DelayCellTimex100 = 270/100 ps
6249 04:45:01.724185 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 04:45:01.727887 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 04:45:01.730593 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 04:45:01.737303 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 04:45:01.740521 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 04:45:01.743950 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 04:45:01.744027
6256 04:45:01.747363 CA PerBit enable=1, Macro0, CA PI delay=36
6257 04:45:01.747440
6258 04:45:01.750858 [CBTSetCACLKResult] CA Dly = 36
6259 04:45:01.750925 CS Dly: 1 (0~32)
6260 04:45:01.750992
6261 04:45:01.754180 ----->DramcWriteLeveling(PI) begin...
6262 04:45:01.754249 ==
6263 04:45:01.757404 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 04:45:01.764113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 04:45:01.764223 ==
6266 04:45:01.767682 Write leveling (Byte 0): 40 => 8
6267 04:45:01.770891 Write leveling (Byte 1): 32 => 0
6268 04:45:01.770965 DramcWriteLeveling(PI) end<-----
6269 04:45:01.771035
6270 04:45:01.774200 ==
6271 04:45:01.777573 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 04:45:01.780543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 04:45:01.780613 ==
6274 04:45:01.784101 [Gating] SW mode calibration
6275 04:45:01.790692 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6276 04:45:01.793911 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6277 04:45:01.800862 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6278 04:45:01.804128 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6279 04:45:01.807482 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 04:45:01.814342 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 04:45:01.817416 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 04:45:01.820968 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 04:45:01.827398 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 04:45:01.830771 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 04:45:01.834015 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 04:45:01.837460 Total UI for P1: 0, mck2ui 16
6287 04:45:01.840603 best dqsien dly found for B0: ( 0, 14, 24)
6288 04:45:01.843927 Total UI for P1: 0, mck2ui 16
6289 04:45:01.847428 best dqsien dly found for B1: ( 0, 14, 24)
6290 04:45:01.850733 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6291 04:45:01.854202 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6292 04:45:01.854303
6293 04:45:01.860325 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6294 04:45:01.863685 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6295 04:45:01.863766 [Gating] SW calibration Done
6296 04:45:01.866873 ==
6297 04:45:01.870566 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 04:45:01.873501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 04:45:01.873583 ==
6300 04:45:01.873646 RX Vref Scan: 0
6301 04:45:01.873706
6302 04:45:01.877297 RX Vref 0 -> 0, step: 1
6303 04:45:01.877378
6304 04:45:01.880088 RX Delay -410 -> 252, step: 16
6305 04:45:01.883557 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6306 04:45:01.887106 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6307 04:45:01.893596 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6308 04:45:01.896554 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6309 04:45:01.900195 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6310 04:45:01.906867 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6311 04:45:01.910236 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6312 04:45:01.913164 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6313 04:45:01.916723 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6314 04:45:01.920175 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6315 04:45:01.926647 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6316 04:45:01.929925 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6317 04:45:01.933529 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6318 04:45:01.939754 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6319 04:45:01.942987 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6320 04:45:01.946349 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6321 04:45:01.946430 ==
6322 04:45:01.949512 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 04:45:01.953105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 04:45:01.956638 ==
6325 04:45:01.956719 DQS Delay:
6326 04:45:01.956782 DQS0 = 27, DQS1 = 43
6327 04:45:01.959472 DQM Delay:
6328 04:45:01.959553 DQM0 = 12, DQM1 = 15
6329 04:45:01.962851 DQ Delay:
6330 04:45:01.966335 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6331 04:45:01.966416 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6332 04:45:01.969588 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6333 04:45:01.972786 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6334 04:45:01.972867
6335 04:45:01.972931
6336 04:45:01.976194 ==
6337 04:45:01.979560 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 04:45:01.982759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 04:45:01.982841 ==
6340 04:45:01.982905
6341 04:45:01.982963
6342 04:45:01.986186 TX Vref Scan disable
6343 04:45:01.986266 == TX Byte 0 ==
6344 04:45:01.989169 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6345 04:45:01.995729 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6346 04:45:01.995810 == TX Byte 1 ==
6347 04:45:01.999233 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6348 04:45:02.006055 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6349 04:45:02.006136 ==
6350 04:45:02.009120 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 04:45:02.012464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 04:45:02.012546 ==
6353 04:45:02.012609
6354 04:45:02.012668
6355 04:45:02.015873 TX Vref Scan disable
6356 04:45:02.015953 == TX Byte 0 ==
6357 04:45:02.022283 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6358 04:45:02.025756 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6359 04:45:02.025840 == TX Byte 1 ==
6360 04:45:02.032126 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6361 04:45:02.035468 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6362 04:45:02.035551
6363 04:45:02.035617 [DATLAT]
6364 04:45:02.039143 Freq=400, CH0 RK0
6365 04:45:02.039226
6366 04:45:02.039291 DATLAT Default: 0xf
6367 04:45:02.042280 0, 0xFFFF, sum = 0
6368 04:45:02.042364 1, 0xFFFF, sum = 0
6369 04:45:02.045480 2, 0xFFFF, sum = 0
6370 04:45:02.045563 3, 0xFFFF, sum = 0
6371 04:45:02.048678 4, 0xFFFF, sum = 0
6372 04:45:02.048762 5, 0xFFFF, sum = 0
6373 04:45:02.052109 6, 0xFFFF, sum = 0
6374 04:45:02.052194 7, 0xFFFF, sum = 0
6375 04:45:02.055354 8, 0xFFFF, sum = 0
6376 04:45:02.055439 9, 0xFFFF, sum = 0
6377 04:45:02.058489 10, 0xFFFF, sum = 0
6378 04:45:02.061883 11, 0xFFFF, sum = 0
6379 04:45:02.062001 12, 0xFFFF, sum = 0
6380 04:45:02.065412 13, 0x0, sum = 1
6381 04:45:02.065496 14, 0x0, sum = 2
6382 04:45:02.065562 15, 0x0, sum = 3
6383 04:45:02.068398 16, 0x0, sum = 4
6384 04:45:02.068481 best_step = 14
6385 04:45:02.068548
6386 04:45:02.072148 ==
6387 04:45:02.072232 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 04:45:02.078778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 04:45:02.078865 ==
6390 04:45:02.078931 RX Vref Scan: 1
6391 04:45:02.078992
6392 04:45:02.081758 RX Vref 0 -> 0, step: 1
6393 04:45:02.081841
6394 04:45:02.085047 RX Delay -327 -> 252, step: 8
6395 04:45:02.085131
6396 04:45:02.088709 Set Vref, RX VrefLevel [Byte0]: 57
6397 04:45:02.091650 [Byte1]: 49
6398 04:45:02.095187
6399 04:45:02.095270 Final RX Vref Byte 0 = 57 to rank0
6400 04:45:02.098625 Final RX Vref Byte 1 = 49 to rank0
6401 04:45:02.101651 Final RX Vref Byte 0 = 57 to rank1
6402 04:45:02.105211 Final RX Vref Byte 1 = 49 to rank1==
6403 04:45:02.108706 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 04:45:02.115076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 04:45:02.115207 ==
6406 04:45:02.115274 DQS Delay:
6407 04:45:02.118684 DQS0 = 28, DQS1 = 48
6408 04:45:02.118766 DQM Delay:
6409 04:45:02.118832 DQM0 = 12, DQM1 = 15
6410 04:45:02.121717 DQ Delay:
6411 04:45:02.125198 DQ0 =8, DQ1 =12, DQ2 =12, DQ3 =8
6412 04:45:02.125282 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6413 04:45:02.128771 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6414 04:45:02.131568 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6415 04:45:02.131651
6416 04:45:02.135126
6417 04:45:02.141556 [DQSOSCAuto] RK0, (LSB)MR18= 0xaba3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6418 04:45:02.144994 CH0 RK0: MR19=C0C, MR18=ABA3
6419 04:45:02.151574 CH0_RK0: MR19=0xC0C, MR18=0xABA3, DQSOSC=388, MR23=63, INC=392, DEC=261
6420 04:45:02.151658 ==
6421 04:45:02.154862 Dram Type= 6, Freq= 0, CH_0, rank 1
6422 04:45:02.158138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 04:45:02.158221 ==
6424 04:45:02.161698 [Gating] SW mode calibration
6425 04:45:02.168146 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6426 04:45:02.174833 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6427 04:45:02.178293 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6428 04:45:02.181690 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6429 04:45:02.187998 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 04:45:02.191687 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 04:45:02.194715 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 04:45:02.201562 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 04:45:02.204880 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 04:45:02.207867 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 04:45:02.211710 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 04:45:02.214643 Total UI for P1: 0, mck2ui 16
6437 04:45:02.218096 best dqsien dly found for B0: ( 0, 14, 24)
6438 04:45:02.221407 Total UI for P1: 0, mck2ui 16
6439 04:45:02.224668 best dqsien dly found for B1: ( 0, 14, 24)
6440 04:45:02.228094 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6441 04:45:02.234481 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6442 04:45:02.234565
6443 04:45:02.238257 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6444 04:45:02.241106 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6445 04:45:02.244636 [Gating] SW calibration Done
6446 04:45:02.244724 ==
6447 04:45:02.248107 Dram Type= 6, Freq= 0, CH_0, rank 1
6448 04:45:02.251299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 04:45:02.251396 ==
6450 04:45:02.254664 RX Vref Scan: 0
6451 04:45:02.254766
6452 04:45:02.254848 RX Vref 0 -> 0, step: 1
6453 04:45:02.254924
6454 04:45:02.257908 RX Delay -410 -> 252, step: 16
6455 04:45:02.261099 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6456 04:45:02.268159 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6457 04:45:02.271355 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6458 04:45:02.274694 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6459 04:45:02.278164 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6460 04:45:02.284677 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6461 04:45:02.288022 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6462 04:45:02.291344 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6463 04:45:02.294758 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6464 04:45:02.301736 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6465 04:45:02.304660 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6466 04:45:02.308238 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6467 04:45:02.311445 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6468 04:45:02.318052 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6469 04:45:02.321495 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6470 04:45:02.324785 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6471 04:45:02.325329 ==
6472 04:45:02.328086 Dram Type= 6, Freq= 0, CH_0, rank 1
6473 04:45:02.334564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 04:45:02.335128 ==
6475 04:45:02.335502 DQS Delay:
6476 04:45:02.337828 DQS0 = 27, DQS1 = 43
6477 04:45:02.338340 DQM Delay:
6478 04:45:02.338711 DQM0 = 9, DQM1 = 15
6479 04:45:02.341287 DQ Delay:
6480 04:45:02.344676 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6481 04:45:02.345253 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6482 04:45:02.348142 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6483 04:45:02.351272 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6484 04:45:02.351743
6485 04:45:02.354737
6486 04:45:02.355311 ==
6487 04:45:02.357666 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 04:45:02.361540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 04:45:02.362192 ==
6490 04:45:02.362574
6491 04:45:02.362921
6492 04:45:02.364466 TX Vref Scan disable
6493 04:45:02.364932 == TX Byte 0 ==
6494 04:45:02.368031 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6495 04:45:02.374710 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6496 04:45:02.375287 == TX Byte 1 ==
6497 04:45:02.378047 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6498 04:45:02.384716 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6499 04:45:02.385434 ==
6500 04:45:02.387942 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 04:45:02.391095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 04:45:02.391696 ==
6503 04:45:02.392079
6504 04:45:02.392425
6505 04:45:02.394457 TX Vref Scan disable
6506 04:45:02.395034 == TX Byte 0 ==
6507 04:45:02.397642 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6508 04:45:02.404614 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6509 04:45:02.405193 == TX Byte 1 ==
6510 04:45:02.407610 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6511 04:45:02.414299 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6512 04:45:02.414857
6513 04:45:02.415232 [DATLAT]
6514 04:45:02.415579 Freq=400, CH0 RK1
6515 04:45:02.416028
6516 04:45:02.417229 DATLAT Default: 0xe
6517 04:45:02.420947 0, 0xFFFF, sum = 0
6518 04:45:02.421593 1, 0xFFFF, sum = 0
6519 04:45:02.424258 2, 0xFFFF, sum = 0
6520 04:45:02.424736 3, 0xFFFF, sum = 0
6521 04:45:02.427579 4, 0xFFFF, sum = 0
6522 04:45:02.428059 5, 0xFFFF, sum = 0
6523 04:45:02.431123 6, 0xFFFF, sum = 0
6524 04:45:02.431715 7, 0xFFFF, sum = 0
6525 04:45:02.434337 8, 0xFFFF, sum = 0
6526 04:45:02.434821 9, 0xFFFF, sum = 0
6527 04:45:02.437574 10, 0xFFFF, sum = 0
6528 04:45:02.438197 11, 0xFFFF, sum = 0
6529 04:45:02.440857 12, 0xFFFF, sum = 0
6530 04:45:02.441431 13, 0x0, sum = 1
6531 04:45:02.444458 14, 0x0, sum = 2
6532 04:45:02.445040 15, 0x0, sum = 3
6533 04:45:02.447819 16, 0x0, sum = 4
6534 04:45:02.448393 best_step = 14
6535 04:45:02.448773
6536 04:45:02.449125 ==
6537 04:45:02.450634 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 04:45:02.454571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 04:45:02.457483 ==
6540 04:45:02.458076 RX Vref Scan: 0
6541 04:45:02.458461
6542 04:45:02.460913 RX Vref 0 -> 0, step: 1
6543 04:45:02.461488
6544 04:45:02.464109 RX Delay -327 -> 252, step: 8
6545 04:45:02.467322 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6546 04:45:02.474297 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6547 04:45:02.477422 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6548 04:45:02.480782 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6549 04:45:02.484092 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6550 04:45:02.490561 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6551 04:45:02.494167 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6552 04:45:02.497628 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6553 04:45:02.500746 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6554 04:45:02.507743 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6555 04:45:02.510620 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6556 04:45:02.513936 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6557 04:45:02.517380 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6558 04:45:02.523861 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6559 04:45:02.527325 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6560 04:45:02.530546 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6561 04:45:02.531114 ==
6562 04:45:02.534301 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 04:45:02.540335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 04:45:02.540894 ==
6565 04:45:02.541268 DQS Delay:
6566 04:45:02.544051 DQS0 = 28, DQS1 = 44
6567 04:45:02.544616 DQM Delay:
6568 04:45:02.544992 DQM0 = 10, DQM1 = 16
6569 04:45:02.547430 DQ Delay:
6570 04:45:02.550831 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6571 04:45:02.551399 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6572 04:45:02.553872 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6573 04:45:02.557339 DQ12 =20, DQ13 =24, DQ14 =28, DQ15 =20
6574 04:45:02.557901
6575 04:45:02.560628
6576 04:45:02.567233 [DQSOSCAuto] RK1, (LSB)MR18= 0xbb70, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6577 04:45:02.570442 CH0 RK1: MR19=C0C, MR18=BB70
6578 04:45:02.577362 CH0_RK1: MR19=0xC0C, MR18=0xBB70, DQSOSC=386, MR23=63, INC=396, DEC=264
6579 04:45:02.580858 [RxdqsGatingPostProcess] freq 400
6580 04:45:02.583818 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6581 04:45:02.587247 best DQS0 dly(2T, 0.5T) = (0, 10)
6582 04:45:02.590632 best DQS1 dly(2T, 0.5T) = (0, 10)
6583 04:45:02.594133 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6584 04:45:02.597282 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6585 04:45:02.600661 best DQS0 dly(2T, 0.5T) = (0, 10)
6586 04:45:02.603837 best DQS1 dly(2T, 0.5T) = (0, 10)
6587 04:45:02.607193 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6588 04:45:02.610445 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6589 04:45:02.613656 Pre-setting of DQS Precalculation
6590 04:45:02.617041 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6591 04:45:02.617517 ==
6592 04:45:02.620509 Dram Type= 6, Freq= 0, CH_1, rank 0
6593 04:45:02.623921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 04:45:02.627266 ==
6595 04:45:02.630588 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6596 04:45:02.637643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6597 04:45:02.640318 [CA 0] Center 36 (8~64) winsize 57
6598 04:45:02.644108 [CA 1] Center 36 (8~64) winsize 57
6599 04:45:02.647216 [CA 2] Center 36 (8~64) winsize 57
6600 04:45:02.650836 [CA 3] Center 36 (8~64) winsize 57
6601 04:45:02.654283 [CA 4] Center 36 (8~64) winsize 57
6602 04:45:02.657257 [CA 5] Center 36 (8~64) winsize 57
6603 04:45:02.657826
6604 04:45:02.660744 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6605 04:45:02.661316
6606 04:45:02.663793 [CATrainingPosCal] consider 1 rank data
6607 04:45:02.667209 u2DelayCellTimex100 = 270/100 ps
6608 04:45:02.670463 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 04:45:02.673867 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 04:45:02.677216 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 04:45:02.680349 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 04:45:02.683678 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 04:45:02.687363 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 04:45:02.687932
6615 04:45:02.690613 CA PerBit enable=1, Macro0, CA PI delay=36
6616 04:45:02.691188
6617 04:45:02.694047 [CBTSetCACLKResult] CA Dly = 36
6618 04:45:02.697317 CS Dly: 1 (0~32)
6619 04:45:02.697880 ==
6620 04:45:02.700400 Dram Type= 6, Freq= 0, CH_1, rank 1
6621 04:45:02.704005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 04:45:02.704577 ==
6623 04:45:02.710609 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6624 04:45:02.717020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6625 04:45:02.720399 [CA 0] Center 36 (8~64) winsize 57
6626 04:45:02.720875 [CA 1] Center 36 (8~64) winsize 57
6627 04:45:02.724172 [CA 2] Center 36 (8~64) winsize 57
6628 04:45:02.727078 [CA 3] Center 36 (8~64) winsize 57
6629 04:45:02.730390 [CA 4] Center 36 (8~64) winsize 57
6630 04:45:02.733804 [CA 5] Center 36 (8~64) winsize 57
6631 04:45:02.734332
6632 04:45:02.737646 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6633 04:45:02.738288
6634 04:45:02.740514 [CATrainingPosCal] consider 2 rank data
6635 04:45:02.744137 u2DelayCellTimex100 = 270/100 ps
6636 04:45:02.747460 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 04:45:02.750821 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 04:45:02.757343 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 04:45:02.760659 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 04:45:02.764091 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 04:45:02.767156 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 04:45:02.767721
6643 04:45:02.770310 CA PerBit enable=1, Macro0, CA PI delay=36
6644 04:45:02.770803
6645 04:45:02.773693 [CBTSetCACLKResult] CA Dly = 36
6646 04:45:02.774200 CS Dly: 1 (0~32)
6647 04:45:02.774579
6648 04:45:02.777080 ----->DramcWriteLeveling(PI) begin...
6649 04:45:02.780243 ==
6650 04:45:02.784053 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 04:45:02.786923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 04:45:02.787502 ==
6653 04:45:02.790806 Write leveling (Byte 0): 40 => 8
6654 04:45:02.793605 Write leveling (Byte 1): 32 => 0
6655 04:45:02.797013 DramcWriteLeveling(PI) end<-----
6656 04:45:02.797584
6657 04:45:02.798008 ==
6658 04:45:02.800525 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 04:45:02.803838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 04:45:02.804415 ==
6661 04:45:02.806971 [Gating] SW mode calibration
6662 04:45:02.813668 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6663 04:45:02.817154 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6664 04:45:02.823789 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6665 04:45:02.826651 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6666 04:45:02.830109 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 04:45:02.836789 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 04:45:02.840232 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 04:45:02.843615 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 04:45:02.850408 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 04:45:02.853431 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 04:45:02.856975 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 04:45:02.860189 Total UI for P1: 0, mck2ui 16
6674 04:45:02.863636 best dqsien dly found for B0: ( 0, 14, 24)
6675 04:45:02.866597 Total UI for P1: 0, mck2ui 16
6676 04:45:02.869912 best dqsien dly found for B1: ( 0, 14, 24)
6677 04:45:02.873362 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6678 04:45:02.876611 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6679 04:45:02.879998
6680 04:45:02.883157 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6681 04:45:02.886537 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6682 04:45:02.890189 [Gating] SW calibration Done
6683 04:45:02.890662 ==
6684 04:45:02.893510 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 04:45:02.896556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 04:45:02.897033 ==
6687 04:45:02.897408 RX Vref Scan: 0
6688 04:45:02.897758
6689 04:45:02.899944 RX Vref 0 -> 0, step: 1
6690 04:45:02.900412
6691 04:45:02.903531 RX Delay -410 -> 252, step: 16
6692 04:45:02.906988 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6693 04:45:02.913043 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6694 04:45:02.916207 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6695 04:45:02.919732 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6696 04:45:02.923005 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6697 04:45:02.929914 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6698 04:45:02.933153 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6699 04:45:02.936658 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6700 04:45:02.940214 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6701 04:45:02.946426 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6702 04:45:02.949934 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6703 04:45:02.953011 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6704 04:45:02.956535 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6705 04:45:02.963348 iDelay=230, Bit 13, Center -19 (-266 ~ 229) 496
6706 04:45:02.966316 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6707 04:45:02.969645 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6708 04:45:02.970137 ==
6709 04:45:02.973446 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 04:45:02.976913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 04:45:02.979714 ==
6712 04:45:02.980281 DQS Delay:
6713 04:45:02.980653 DQS0 = 27, DQS1 = 43
6714 04:45:02.982858 DQM Delay:
6715 04:45:02.983380 DQM0 = 5, DQM1 = 15
6716 04:45:02.986720 DQ Delay:
6717 04:45:02.987294 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6718 04:45:02.989629 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6719 04:45:02.993118 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6720 04:45:02.996338 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6721 04:45:02.996909
6722 04:45:02.997274
6723 04:45:02.997680 ==
6724 04:45:02.999984 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 04:45:03.006629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 04:45:03.007265 ==
6727 04:45:03.007641
6728 04:45:03.007976
6729 04:45:03.009361 TX Vref Scan disable
6730 04:45:03.009823 == TX Byte 0 ==
6731 04:45:03.012564 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6732 04:45:03.019628 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6733 04:45:03.020095 == TX Byte 1 ==
6734 04:45:03.022520 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6735 04:45:03.029423 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6736 04:45:03.030040 ==
6737 04:45:03.032723 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 04:45:03.036483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 04:45:03.037055 ==
6740 04:45:03.037424
6741 04:45:03.037767
6742 04:45:03.039280 TX Vref Scan disable
6743 04:45:03.039744 == TX Byte 0 ==
6744 04:45:03.042874 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6745 04:45:03.050106 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6746 04:45:03.050676 == TX Byte 1 ==
6747 04:45:03.052919 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6748 04:45:03.059906 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6749 04:45:03.060503
6750 04:45:03.060875 [DATLAT]
6751 04:45:03.061219 Freq=400, CH1 RK0
6752 04:45:03.061554
6753 04:45:03.062822 DATLAT Default: 0xf
6754 04:45:03.065907 0, 0xFFFF, sum = 0
6755 04:45:03.066419 1, 0xFFFF, sum = 0
6756 04:45:03.069637 2, 0xFFFF, sum = 0
6757 04:45:03.070250 3, 0xFFFF, sum = 0
6758 04:45:03.073072 4, 0xFFFF, sum = 0
6759 04:45:03.073645 5, 0xFFFF, sum = 0
6760 04:45:03.076252 6, 0xFFFF, sum = 0
6761 04:45:03.076727 7, 0xFFFF, sum = 0
6762 04:45:03.079220 8, 0xFFFF, sum = 0
6763 04:45:03.079695 9, 0xFFFF, sum = 0
6764 04:45:03.082736 10, 0xFFFF, sum = 0
6765 04:45:03.083330 11, 0xFFFF, sum = 0
6766 04:45:03.086186 12, 0xFFFF, sum = 0
6767 04:45:03.086833 13, 0x0, sum = 1
6768 04:45:03.089585 14, 0x0, sum = 2
6769 04:45:03.090196 15, 0x0, sum = 3
6770 04:45:03.092949 16, 0x0, sum = 4
6771 04:45:03.093534 best_step = 14
6772 04:45:03.093909
6773 04:45:03.094310 ==
6774 04:45:03.096030 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 04:45:03.099382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 04:45:03.102880 ==
6777 04:45:03.103460 RX Vref Scan: 1
6778 04:45:03.103833
6779 04:45:03.106386 RX Vref 0 -> 0, step: 1
6780 04:45:03.107145
6781 04:45:03.108928 RX Delay -327 -> 252, step: 8
6782 04:45:03.109392
6783 04:45:03.112349 Set Vref, RX VrefLevel [Byte0]: 54
6784 04:45:03.115799 [Byte1]: 48
6785 04:45:03.116335
6786 04:45:03.119024 Final RX Vref Byte 0 = 54 to rank0
6787 04:45:03.122556 Final RX Vref Byte 1 = 48 to rank0
6788 04:45:03.125763 Final RX Vref Byte 0 = 54 to rank1
6789 04:45:03.129158 Final RX Vref Byte 1 = 48 to rank1==
6790 04:45:03.132326 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 04:45:03.135827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 04:45:03.136396 ==
6793 04:45:03.139154 DQS Delay:
6794 04:45:03.139707 DQS0 = 28, DQS1 = 40
6795 04:45:03.142056 DQM Delay:
6796 04:45:03.142519 DQM0 = 8, DQM1 = 13
6797 04:45:03.142885 DQ Delay:
6798 04:45:03.145705 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6799 04:45:03.148963 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6800 04:45:03.152672 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6801 04:45:03.155647 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6802 04:45:03.156207
6803 04:45:03.156574
6804 04:45:03.165829 [DQSOSCAuto] RK0, (LSB)MR18= 0x95d1, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6805 04:45:03.166424 CH1 RK0: MR19=C0C, MR18=95D1
6806 04:45:03.172190 CH1_RK0: MR19=0xC0C, MR18=0x95D1, DQSOSC=384, MR23=63, INC=400, DEC=267
6807 04:45:03.172755 ==
6808 04:45:03.175512 Dram Type= 6, Freq= 0, CH_1, rank 1
6809 04:45:03.181917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 04:45:03.182539 ==
6811 04:45:03.185608 [Gating] SW mode calibration
6812 04:45:03.191810 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6813 04:45:03.195381 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6814 04:45:03.202177 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6815 04:45:03.205691 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6816 04:45:03.208902 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6817 04:45:03.215096 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 04:45:03.218514 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 04:45:03.222043 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 04:45:03.228741 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 04:45:03.231832 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 04:45:03.235261 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 04:45:03.238344 Total UI for P1: 0, mck2ui 16
6824 04:45:03.241826 best dqsien dly found for B0: ( 0, 14, 24)
6825 04:45:03.245373 Total UI for P1: 0, mck2ui 16
6826 04:45:03.248984 best dqsien dly found for B1: ( 0, 14, 24)
6827 04:45:03.252317 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6828 04:45:03.255283 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6829 04:45:03.255845
6830 04:45:03.258817 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6831 04:45:03.265293 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6832 04:45:03.265866 [Gating] SW calibration Done
6833 04:45:03.266276 ==
6834 04:45:03.268549 Dram Type= 6, Freq= 0, CH_1, rank 1
6835 04:45:03.275419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 04:45:03.275992 ==
6837 04:45:03.276366 RX Vref Scan: 0
6838 04:45:03.276709
6839 04:45:03.278150 RX Vref 0 -> 0, step: 1
6840 04:45:03.278610
6841 04:45:03.281766 RX Delay -410 -> 252, step: 16
6842 04:45:03.285166 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6843 04:45:03.288084 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6844 04:45:03.295076 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6845 04:45:03.298480 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6846 04:45:03.301659 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6847 04:45:03.305215 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6848 04:45:03.311551 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6849 04:45:03.314814 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6850 04:45:03.317826 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6851 04:45:03.321451 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6852 04:45:03.327968 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6853 04:45:03.331120 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6854 04:45:03.334557 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6855 04:45:03.338138 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6856 04:45:03.345046 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6857 04:45:03.348128 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6858 04:45:03.348601 ==
6859 04:45:03.351649 Dram Type= 6, Freq= 0, CH_1, rank 1
6860 04:45:03.354631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 04:45:03.355110 ==
6862 04:45:03.358064 DQS Delay:
6863 04:45:03.358539 DQS0 = 35, DQS1 = 35
6864 04:45:03.361158 DQM Delay:
6865 04:45:03.361699 DQM0 = 18, DQM1 = 13
6866 04:45:03.362111 DQ Delay:
6867 04:45:03.364703 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6868 04:45:03.367970 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6869 04:45:03.371429 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6870 04:45:03.374492 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6871 04:45:03.374968
6872 04:45:03.375341
6873 04:45:03.375684 ==
6874 04:45:03.377862 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 04:45:03.384403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 04:45:03.384941 ==
6877 04:45:03.385320
6878 04:45:03.385665
6879 04:45:03.386026 TX Vref Scan disable
6880 04:45:03.387748 == TX Byte 0 ==
6881 04:45:03.391211 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6882 04:45:03.394691 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6883 04:45:03.398212 == TX Byte 1 ==
6884 04:45:03.401481 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6885 04:45:03.404407 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6886 04:45:03.404953 ==
6887 04:45:03.407662 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 04:45:03.414665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 04:45:03.415203 ==
6890 04:45:03.415578
6891 04:45:03.415927
6892 04:45:03.416260 TX Vref Scan disable
6893 04:45:03.417631 == TX Byte 0 ==
6894 04:45:03.421065 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6895 04:45:03.424538 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6896 04:45:03.427966 == TX Byte 1 ==
6897 04:45:03.431312 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6898 04:45:03.434666 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6899 04:45:03.435141
6900 04:45:03.438034 [DATLAT]
6901 04:45:03.438613 Freq=400, CH1 RK1
6902 04:45:03.438965
6903 04:45:03.441304 DATLAT Default: 0xe
6904 04:45:03.441733 0, 0xFFFF, sum = 0
6905 04:45:03.444721 1, 0xFFFF, sum = 0
6906 04:45:03.445288 2, 0xFFFF, sum = 0
6907 04:45:03.447585 3, 0xFFFF, sum = 0
6908 04:45:03.448091 4, 0xFFFF, sum = 0
6909 04:45:03.451248 5, 0xFFFF, sum = 0
6910 04:45:03.451688 6, 0xFFFF, sum = 0
6911 04:45:03.454261 7, 0xFFFF, sum = 0
6912 04:45:03.454700 8, 0xFFFF, sum = 0
6913 04:45:03.457713 9, 0xFFFF, sum = 0
6914 04:45:03.458275 10, 0xFFFF, sum = 0
6915 04:45:03.461134 11, 0xFFFF, sum = 0
6916 04:45:03.464594 12, 0xFFFF, sum = 0
6917 04:45:03.465030 13, 0x0, sum = 1
6918 04:45:03.467512 14, 0x0, sum = 2
6919 04:45:03.467946 15, 0x0, sum = 3
6920 04:45:03.468293 16, 0x0, sum = 4
6921 04:45:03.470857 best_step = 14
6922 04:45:03.471283
6923 04:45:03.471620 ==
6924 04:45:03.474508 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 04:45:03.477394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 04:45:03.477923 ==
6927 04:45:03.480672 RX Vref Scan: 0
6928 04:45:03.481195
6929 04:45:03.483761 RX Vref 0 -> 0, step: 1
6930 04:45:03.484190
6931 04:45:03.484549 RX Delay -311 -> 252, step: 8
6932 04:45:03.492547 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6933 04:45:03.496185 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6934 04:45:03.499104 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6935 04:45:03.505855 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6936 04:45:03.509374 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6937 04:45:03.512321 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6938 04:45:03.515758 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6939 04:45:03.518884 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6940 04:45:03.525605 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6941 04:45:03.529106 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6942 04:45:03.532614 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6943 04:45:03.536117 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6944 04:45:03.542584 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6945 04:45:03.545517 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6946 04:45:03.549218 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6947 04:45:03.555790 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6948 04:45:03.556273 ==
6949 04:45:03.559482 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 04:45:03.562273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 04:45:03.562745 ==
6952 04:45:03.563117 DQS Delay:
6953 04:45:03.565695 DQS0 = 32, DQS1 = 36
6954 04:45:03.566204 DQM Delay:
6955 04:45:03.569071 DQM0 = 13, DQM1 = 12
6956 04:45:03.569537 DQ Delay:
6957 04:45:03.572247 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6958 04:45:03.575708 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =12
6959 04:45:03.579023 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6960 04:45:03.582039 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =24
6961 04:45:03.582464
6962 04:45:03.582848
6963 04:45:03.588639 [DQSOSCAuto] RK1, (LSB)MR18= 0xa852, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6964 04:45:03.592305 CH1 RK1: MR19=C0C, MR18=A852
6965 04:45:03.598645 CH1_RK1: MR19=0xC0C, MR18=0xA852, DQSOSC=388, MR23=63, INC=392, DEC=261
6966 04:45:03.602372 [RxdqsGatingPostProcess] freq 400
6967 04:45:03.608965 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6968 04:45:03.611734 best DQS0 dly(2T, 0.5T) = (0, 10)
6969 04:45:03.612160 best DQS1 dly(2T, 0.5T) = (0, 10)
6970 04:45:03.615147 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6971 04:45:03.618454 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6972 04:45:03.622353 best DQS0 dly(2T, 0.5T) = (0, 10)
6973 04:45:03.625107 best DQS1 dly(2T, 0.5T) = (0, 10)
6974 04:45:03.628473 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6975 04:45:03.631924 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6976 04:45:03.635320 Pre-setting of DQS Precalculation
6977 04:45:03.641995 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6978 04:45:03.648681 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6979 04:45:03.655248 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6980 04:45:03.655844
6981 04:45:03.656228
6982 04:45:03.658314 [Calibration Summary] 800 Mbps
6983 04:45:03.658785 CH 0, Rank 0
6984 04:45:03.661884 SW Impedance : PASS
6985 04:45:03.665244 DUTY Scan : NO K
6986 04:45:03.665837 ZQ Calibration : PASS
6987 04:45:03.668493 Jitter Meter : NO K
6988 04:45:03.672185 CBT Training : PASS
6989 04:45:03.672797 Write leveling : PASS
6990 04:45:03.675089 RX DQS gating : PASS
6991 04:45:03.675672 RX DQ/DQS(RDDQC) : PASS
6992 04:45:03.678446 TX DQ/DQS : PASS
6993 04:45:03.682303 RX DATLAT : PASS
6994 04:45:03.682891 RX DQ/DQS(Engine): PASS
6995 04:45:03.684969 TX OE : NO K
6996 04:45:03.685444 All Pass.
6997 04:45:03.685819
6998 04:45:03.688398 CH 0, Rank 1
6999 04:45:03.688869 SW Impedance : PASS
7000 04:45:03.691691 DUTY Scan : NO K
7001 04:45:03.694926 ZQ Calibration : PASS
7002 04:45:03.695348 Jitter Meter : NO K
7003 04:45:03.698638 CBT Training : PASS
7004 04:45:03.701657 Write leveling : NO K
7005 04:45:03.702225 RX DQS gating : PASS
7006 04:45:03.705238 RX DQ/DQS(RDDQC) : PASS
7007 04:45:03.708564 TX DQ/DQS : PASS
7008 04:45:03.709039 RX DATLAT : PASS
7009 04:45:03.711574 RX DQ/DQS(Engine): PASS
7010 04:45:03.714939 TX OE : NO K
7011 04:45:03.715412 All Pass.
7012 04:45:03.715805
7013 04:45:03.716223 CH 1, Rank 0
7014 04:45:03.718364 SW Impedance : PASS
7015 04:45:03.721631 DUTY Scan : NO K
7016 04:45:03.722178 ZQ Calibration : PASS
7017 04:45:03.724530 Jitter Meter : NO K
7018 04:45:03.724948 CBT Training : PASS
7019 04:45:03.727879 Write leveling : PASS
7020 04:45:03.731626 RX DQS gating : PASS
7021 04:45:03.732062 RX DQ/DQS(RDDQC) : PASS
7022 04:45:03.735093 TX DQ/DQS : PASS
7023 04:45:03.737904 RX DATLAT : PASS
7024 04:45:03.738371 RX DQ/DQS(Engine): PASS
7025 04:45:03.741379 TX OE : NO K
7026 04:45:03.741800 All Pass.
7027 04:45:03.742186
7028 04:45:03.745037 CH 1, Rank 1
7029 04:45:03.745619 SW Impedance : PASS
7030 04:45:03.748319 DUTY Scan : NO K
7031 04:45:03.751237 ZQ Calibration : PASS
7032 04:45:03.751766 Jitter Meter : NO K
7033 04:45:03.754352 CBT Training : PASS
7034 04:45:03.758148 Write leveling : NO K
7035 04:45:03.758678 RX DQS gating : PASS
7036 04:45:03.761296 RX DQ/DQS(RDDQC) : PASS
7037 04:45:03.764664 TX DQ/DQS : PASS
7038 04:45:03.765206 RX DATLAT : PASS
7039 04:45:03.767957 RX DQ/DQS(Engine): PASS
7040 04:45:03.771312 TX OE : NO K
7041 04:45:03.771736 All Pass.
7042 04:45:03.772070
7043 04:45:03.772401 DramC Write-DBI off
7044 04:45:03.774560 PER_BANK_REFRESH: Hybrid Mode
7045 04:45:03.777565 TX_TRACKING: ON
7046 04:45:03.784503 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7047 04:45:03.787632 [FAST_K] Save calibration result to emmc
7048 04:45:03.794208 dramc_set_vcore_voltage set vcore to 725000
7049 04:45:03.794739 Read voltage for 1600, 0
7050 04:45:03.797419 Vio18 = 0
7051 04:45:03.797881 Vcore = 725000
7052 04:45:03.798290 Vdram = 0
7053 04:45:03.801207 Vddq = 0
7054 04:45:03.801867 Vmddr = 0
7055 04:45:03.804465 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7056 04:45:03.811231 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7057 04:45:03.814472 MEM_TYPE=3, freq_sel=13
7058 04:45:03.817412 sv_algorithm_assistance_LP4_3733
7059 04:45:03.820818 ============ PULL DRAM RESETB DOWN ============
7060 04:45:03.824333 ========== PULL DRAM RESETB DOWN end =========
7061 04:45:03.827548 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7062 04:45:03.830981 ===================================
7063 04:45:03.834311 LPDDR4 DRAM CONFIGURATION
7064 04:45:03.837480 ===================================
7065 04:45:03.840986 EX_ROW_EN[0] = 0x0
7066 04:45:03.841412 EX_ROW_EN[1] = 0x0
7067 04:45:03.844815 LP4Y_EN = 0x0
7068 04:45:03.845347 WORK_FSP = 0x1
7069 04:45:03.847786 WL = 0x5
7070 04:45:03.848326 RL = 0x5
7071 04:45:03.850754 BL = 0x2
7072 04:45:03.851238 RPST = 0x0
7073 04:45:03.854305 RD_PRE = 0x0
7074 04:45:03.854768 WR_PRE = 0x1
7075 04:45:03.857515 WR_PST = 0x1
7076 04:45:03.857956 DBI_WR = 0x0
7077 04:45:03.860833 DBI_RD = 0x0
7078 04:45:03.864306 OTF = 0x1
7079 04:45:03.864732 ===================================
7080 04:45:03.867210 ===================================
7081 04:45:03.870994 ANA top config
7082 04:45:03.873905 ===================================
7083 04:45:03.877585 DLL_ASYNC_EN = 0
7084 04:45:03.878170 ALL_SLAVE_EN = 0
7085 04:45:03.880450 NEW_RANK_MODE = 1
7086 04:45:03.883826 DLL_IDLE_MODE = 1
7087 04:45:03.887542 LP45_APHY_COMB_EN = 1
7088 04:45:03.890856 TX_ODT_DIS = 0
7089 04:45:03.891371 NEW_8X_MODE = 1
7090 04:45:03.894341 ===================================
7091 04:45:03.897536 ===================================
7092 04:45:03.900678 data_rate = 3200
7093 04:45:03.903794 CKR = 1
7094 04:45:03.907260 DQ_P2S_RATIO = 8
7095 04:45:03.910670 ===================================
7096 04:45:03.914227 CA_P2S_RATIO = 8
7097 04:45:03.914866 DQ_CA_OPEN = 0
7098 04:45:03.917197 DQ_SEMI_OPEN = 0
7099 04:45:03.920693 CA_SEMI_OPEN = 0
7100 04:45:03.924210 CA_FULL_RATE = 0
7101 04:45:03.927733 DQ_CKDIV4_EN = 0
7102 04:45:03.930553 CA_CKDIV4_EN = 0
7103 04:45:03.930978 CA_PREDIV_EN = 0
7104 04:45:03.933726 PH8_DLY = 12
7105 04:45:03.937615 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7106 04:45:03.940846 DQ_AAMCK_DIV = 4
7107 04:45:03.944232 CA_AAMCK_DIV = 4
7108 04:45:03.947468 CA_ADMCK_DIV = 4
7109 04:45:03.947997 DQ_TRACK_CA_EN = 0
7110 04:45:03.950592 CA_PICK = 1600
7111 04:45:03.954122 CA_MCKIO = 1600
7112 04:45:03.957270 MCKIO_SEMI = 0
7113 04:45:03.960690 PLL_FREQ = 3068
7114 04:45:03.964290 DQ_UI_PI_RATIO = 32
7115 04:45:03.967195 CA_UI_PI_RATIO = 0
7116 04:45:03.970495 ===================================
7117 04:45:03.973704 ===================================
7118 04:45:03.974256 memory_type:LPDDR4
7119 04:45:03.976983 GP_NUM : 10
7120 04:45:03.980336 SRAM_EN : 1
7121 04:45:03.980772 MD32_EN : 0
7122 04:45:03.983863 ===================================
7123 04:45:03.987507 [ANA_INIT] >>>>>>>>>>>>>>
7124 04:45:03.990565 <<<<<< [CONFIGURE PHASE]: ANA_TX
7125 04:45:03.993768 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7126 04:45:03.997474 ===================================
7127 04:45:04.000337 data_rate = 3200,PCW = 0X7600
7128 04:45:04.004069 ===================================
7129 04:45:04.007457 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7130 04:45:04.010370 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7131 04:45:04.016839 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7132 04:45:04.020287 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7133 04:45:04.023870 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7134 04:45:04.026971 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7135 04:45:04.030218 [ANA_INIT] flow start
7136 04:45:04.033534 [ANA_INIT] PLL >>>>>>>>
7137 04:45:04.033982 [ANA_INIT] PLL <<<<<<<<
7138 04:45:04.036816 [ANA_INIT] MIDPI >>>>>>>>
7139 04:45:04.040233 [ANA_INIT] MIDPI <<<<<<<<
7140 04:45:04.043590 [ANA_INIT] DLL >>>>>>>>
7141 04:45:04.044022 [ANA_INIT] DLL <<<<<<<<
7142 04:45:04.046793 [ANA_INIT] flow end
7143 04:45:04.050362 ============ LP4 DIFF to SE enter ============
7144 04:45:04.053806 ============ LP4 DIFF to SE exit ============
7145 04:45:04.056737 [ANA_INIT] <<<<<<<<<<<<<
7146 04:45:04.059975 [Flow] Enable top DCM control >>>>>
7147 04:45:04.063421 [Flow] Enable top DCM control <<<<<
7148 04:45:04.067047 Enable DLL master slave shuffle
7149 04:45:04.073737 ==============================================================
7150 04:45:04.074308 Gating Mode config
7151 04:45:04.080510 ==============================================================
7152 04:45:04.081188 Config description:
7153 04:45:04.089833 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7154 04:45:04.096302 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7155 04:45:04.103210 SELPH_MODE 0: By rank 1: By Phase
7156 04:45:04.106611 ==============================================================
7157 04:45:04.109611 GAT_TRACK_EN = 1
7158 04:45:04.112966 RX_GATING_MODE = 2
7159 04:45:04.116344 RX_GATING_TRACK_MODE = 2
7160 04:45:04.119943 SELPH_MODE = 1
7161 04:45:04.123040 PICG_EARLY_EN = 1
7162 04:45:04.126486 VALID_LAT_VALUE = 1
7163 04:45:04.132854 ==============================================================
7164 04:45:04.136094 Enter into Gating configuration >>>>
7165 04:45:04.139688 Exit from Gating configuration <<<<
7166 04:45:04.140108 Enter into DVFS_PRE_config >>>>>
7167 04:45:04.153181 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7168 04:45:04.156099 Exit from DVFS_PRE_config <<<<<
7169 04:45:04.159588 Enter into PICG configuration >>>>
7170 04:45:04.162594 Exit from PICG configuration <<<<
7171 04:45:04.163115 [RX_INPUT] configuration >>>>>
7172 04:45:04.166150 [RX_INPUT] configuration <<<<<
7173 04:45:04.172700 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7174 04:45:04.176227 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7175 04:45:04.182914 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7176 04:45:04.189318 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7177 04:45:04.195772 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7178 04:45:04.202822 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7179 04:45:04.205816 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7180 04:45:04.209323 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7181 04:45:04.216073 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7182 04:45:04.219304 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7183 04:45:04.222839 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7184 04:45:04.225828 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7185 04:45:04.229275 ===================================
7186 04:45:04.232232 LPDDR4 DRAM CONFIGURATION
7187 04:45:04.235858 ===================================
7188 04:45:04.238997 EX_ROW_EN[0] = 0x0
7189 04:45:04.239438 EX_ROW_EN[1] = 0x0
7190 04:45:04.242405 LP4Y_EN = 0x0
7191 04:45:04.242846 WORK_FSP = 0x1
7192 04:45:04.246061 WL = 0x5
7193 04:45:04.246502 RL = 0x5
7194 04:45:04.249305 BL = 0x2
7195 04:45:04.249748 RPST = 0x0
7196 04:45:04.252617 RD_PRE = 0x0
7197 04:45:04.253056 WR_PRE = 0x1
7198 04:45:04.256053 WR_PST = 0x1
7199 04:45:04.256570 DBI_WR = 0x0
7200 04:45:04.259513 DBI_RD = 0x0
7201 04:45:04.259952 OTF = 0x1
7202 04:45:04.262450 ===================================
7203 04:45:04.269139 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7204 04:45:04.272419 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7205 04:45:04.275822 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7206 04:45:04.279120 ===================================
7207 04:45:04.282663 LPDDR4 DRAM CONFIGURATION
7208 04:45:04.285888 ===================================
7209 04:45:04.289194 EX_ROW_EN[0] = 0x10
7210 04:45:04.289635 EX_ROW_EN[1] = 0x0
7211 04:45:04.292231 LP4Y_EN = 0x0
7212 04:45:04.292671 WORK_FSP = 0x1
7213 04:45:04.295671 WL = 0x5
7214 04:45:04.296112 RL = 0x5
7215 04:45:04.299225 BL = 0x2
7216 04:45:04.299668 RPST = 0x0
7217 04:45:04.302738 RD_PRE = 0x0
7218 04:45:04.303279 WR_PRE = 0x1
7219 04:45:04.305683 WR_PST = 0x1
7220 04:45:04.306161 DBI_WR = 0x0
7221 04:45:04.309311 DBI_RD = 0x0
7222 04:45:04.309851 OTF = 0x1
7223 04:45:04.312720 ===================================
7224 04:45:04.318914 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7225 04:45:04.319359 ==
7226 04:45:04.322399 Dram Type= 6, Freq= 0, CH_0, rank 0
7227 04:45:04.325747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7228 04:45:04.329349 ==
7229 04:45:04.329865 [Duty_Offset_Calibration]
7230 04:45:04.332579 B0:2 B1:0 CA:1
7231 04:45:04.333123
7232 04:45:04.335915 [DutyScan_Calibration_Flow] k_type=0
7233 04:45:04.344027
7234 04:45:04.344526 ==CLK 0==
7235 04:45:04.347801 Final CLK duty delay cell = -4
7236 04:45:04.350452 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7237 04:45:04.353641 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7238 04:45:04.357541 [-4] AVG Duty = 4922%(X100)
7239 04:45:04.358008
7240 04:45:04.360824 CH0 CLK Duty spec in!! Max-Min= 218%
7241 04:45:04.363883 [DutyScan_Calibration_Flow] ====Done====
7242 04:45:04.364414
7243 04:45:04.367348 [DutyScan_Calibration_Flow] k_type=1
7244 04:45:04.383325
7245 04:45:04.383834 ==DQS 0 ==
7246 04:45:04.386744 Final DQS duty delay cell = 0
7247 04:45:04.390341 [0] MAX Duty = 5249%(X100), DQS PI = 32
7248 04:45:04.392997 [0] MIN Duty = 4969%(X100), DQS PI = 0
7249 04:45:04.397003 [0] AVG Duty = 5109%(X100)
7250 04:45:04.397558
7251 04:45:04.397969 ==DQS 1 ==
7252 04:45:04.399799 Final DQS duty delay cell = -4
7253 04:45:04.403358 [-4] MAX Duty = 5125%(X100), DQS PI = 44
7254 04:45:04.406535 [-4] MIN Duty = 4844%(X100), DQS PI = 6
7255 04:45:04.409822 [-4] AVG Duty = 4984%(X100)
7256 04:45:04.410431
7257 04:45:04.413461 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7258 04:45:04.414082
7259 04:45:04.416365 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7260 04:45:04.419926 [DutyScan_Calibration_Flow] ====Done====
7261 04:45:04.420401
7262 04:45:04.423207 [DutyScan_Calibration_Flow] k_type=3
7263 04:45:04.440991
7264 04:45:04.441533 ==DQM 0 ==
7265 04:45:04.444281 Final DQM duty delay cell = 0
7266 04:45:04.447609 [0] MAX Duty = 5124%(X100), DQS PI = 26
7267 04:45:04.450880 [0] MIN Duty = 4813%(X100), DQS PI = 50
7268 04:45:04.454211 [0] AVG Duty = 4968%(X100)
7269 04:45:04.454683
7270 04:45:04.455058 ==DQM 1 ==
7271 04:45:04.457367 Final DQM duty delay cell = 0
7272 04:45:04.460682 [0] MAX Duty = 5249%(X100), DQS PI = 30
7273 04:45:04.463926 [0] MIN Duty = 5000%(X100), DQS PI = 20
7274 04:45:04.467278 [0] AVG Duty = 5124%(X100)
7275 04:45:04.467746
7276 04:45:04.470802 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7277 04:45:04.471230
7278 04:45:04.474091 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7279 04:45:04.477410 [DutyScan_Calibration_Flow] ====Done====
7280 04:45:04.477936
7281 04:45:04.480552 [DutyScan_Calibration_Flow] k_type=2
7282 04:45:04.498168
7283 04:45:04.498713 ==DQ 0 ==
7284 04:45:04.501461 Final DQ duty delay cell = 0
7285 04:45:04.504705 [0] MAX Duty = 5124%(X100), DQS PI = 34
7286 04:45:04.508154 [0] MIN Duty = 5000%(X100), DQS PI = 0
7287 04:45:04.508688 [0] AVG Duty = 5062%(X100)
7288 04:45:04.511474
7289 04:45:04.511905 ==DQ 1 ==
7290 04:45:04.514442 Final DQ duty delay cell = 0
7291 04:45:04.518024 [0] MAX Duty = 4969%(X100), DQS PI = 44
7292 04:45:04.521331 [0] MIN Duty = 4875%(X100), DQS PI = 10
7293 04:45:04.521873 [0] AVG Duty = 4922%(X100)
7294 04:45:04.522393
7295 04:45:04.524340 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7296 04:45:04.527949
7297 04:45:04.531142 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7298 04:45:04.534356 [DutyScan_Calibration_Flow] ====Done====
7299 04:45:04.534849 ==
7300 04:45:04.537806 Dram Type= 6, Freq= 0, CH_1, rank 0
7301 04:45:04.541313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7302 04:45:04.541772 ==
7303 04:45:04.544572 [Duty_Offset_Calibration]
7304 04:45:04.544893 B0:0 B1:-1 CA:2
7305 04:45:04.545089
7306 04:45:04.547932 [DutyScan_Calibration_Flow] k_type=0
7307 04:45:04.557893
7308 04:45:04.558223 ==CLK 0==
7309 04:45:04.561076 Final CLK duty delay cell = 0
7310 04:45:04.564418 [0] MAX Duty = 5156%(X100), DQS PI = 10
7311 04:45:04.567789 [0] MIN Duty = 4906%(X100), DQS PI = 46
7312 04:45:04.568014 [0] AVG Duty = 5031%(X100)
7313 04:45:04.571106
7314 04:45:04.574590 CH1 CLK Duty spec in!! Max-Min= 250%
7315 04:45:04.578161 [DutyScan_Calibration_Flow] ====Done====
7316 04:45:04.578527
7317 04:45:04.581002 [DutyScan_Calibration_Flow] k_type=1
7318 04:45:04.598395
7319 04:45:04.598912 ==DQS 0 ==
7320 04:45:04.601344 Final DQS duty delay cell = 0
7321 04:45:04.604968 [0] MAX Duty = 5124%(X100), DQS PI = 26
7322 04:45:04.608028 [0] MIN Duty = 5000%(X100), DQS PI = 0
7323 04:45:04.610990 [0] AVG Duty = 5062%(X100)
7324 04:45:04.611515
7325 04:45:04.611877 ==DQS 1 ==
7326 04:45:04.614489 Final DQS duty delay cell = 0
7327 04:45:04.618085 [0] MAX Duty = 5187%(X100), DQS PI = 0
7328 04:45:04.620978 [0] MIN Duty = 4844%(X100), DQS PI = 32
7329 04:45:04.621431 [0] AVG Duty = 5015%(X100)
7330 04:45:04.624351
7331 04:45:04.627880 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7332 04:45:04.628337
7333 04:45:04.630838 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7334 04:45:04.634324 [DutyScan_Calibration_Flow] ====Done====
7335 04:45:04.634738
7336 04:45:04.637668 [DutyScan_Calibration_Flow] k_type=3
7337 04:45:04.655828
7338 04:45:04.656344 ==DQM 0 ==
7339 04:45:04.659242 Final DQM duty delay cell = 4
7340 04:45:04.662709 [4] MAX Duty = 5125%(X100), DQS PI = 8
7341 04:45:04.665727 [4] MIN Duty = 4938%(X100), DQS PI = 48
7342 04:45:04.666325 [4] AVG Duty = 5031%(X100)
7343 04:45:04.668858
7344 04:45:04.669315 ==DQM 1 ==
7345 04:45:04.672230 Final DQM duty delay cell = 0
7346 04:45:04.675802 [0] MAX Duty = 5281%(X100), DQS PI = 58
7347 04:45:04.679333 [0] MIN Duty = 4907%(X100), DQS PI = 34
7348 04:45:04.679887 [0] AVG Duty = 5094%(X100)
7349 04:45:04.682744
7350 04:45:04.685492 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7351 04:45:04.686150
7352 04:45:04.689046 CH1 DQM 1 Duty spec in!! Max-Min= 374%
7353 04:45:04.691961 [DutyScan_Calibration_Flow] ====Done====
7354 04:45:04.692511
7355 04:45:04.695773 [DutyScan_Calibration_Flow] k_type=2
7356 04:45:04.712673
7357 04:45:04.713253 ==DQ 0 ==
7358 04:45:04.715541 Final DQ duty delay cell = 0
7359 04:45:04.718983 [0] MAX Duty = 5093%(X100), DQS PI = 20
7360 04:45:04.722592 [0] MIN Duty = 4969%(X100), DQS PI = 46
7361 04:45:04.723299 [0] AVG Duty = 5031%(X100)
7362 04:45:04.725869
7363 04:45:04.726377 ==DQ 1 ==
7364 04:45:04.728901 Final DQ duty delay cell = 0
7365 04:45:04.732686 [0] MAX Duty = 5062%(X100), DQS PI = 0
7366 04:45:04.736244 [0] MIN Duty = 4813%(X100), DQS PI = 34
7367 04:45:04.736825 [0] AVG Duty = 4937%(X100)
7368 04:45:04.737202
7369 04:45:04.739361 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7370 04:45:04.739830
7371 04:45:04.745670 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7372 04:45:04.749213 [DutyScan_Calibration_Flow] ====Done====
7373 04:45:04.752550 nWR fixed to 30
7374 04:45:04.753034 [ModeRegInit_LP4] CH0 RK0
7375 04:45:04.755859 [ModeRegInit_LP4] CH0 RK1
7376 04:45:04.759097 [ModeRegInit_LP4] CH1 RK0
7377 04:45:04.759570 [ModeRegInit_LP4] CH1 RK1
7378 04:45:04.762780 match AC timing 5
7379 04:45:04.765314 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7380 04:45:04.768679 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7381 04:45:04.775693 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7382 04:45:04.778658 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7383 04:45:04.785603 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7384 04:45:04.786218 [MiockJmeterHQA]
7385 04:45:04.786612
7386 04:45:04.788955 [DramcMiockJmeter] u1RxGatingPI = 0
7387 04:45:04.792121 0 : 4253, 4026
7388 04:45:04.792575 4 : 4252, 4027
7389 04:45:04.792926 8 : 4253, 4026
7390 04:45:04.795525 12 : 4366, 4140
7391 04:45:04.795980 16 : 4257, 4030
7392 04:45:04.798681 20 : 4255, 4030
7393 04:45:04.799117 24 : 4252, 4027
7394 04:45:04.802335 28 : 4363, 4137
7395 04:45:04.802767 32 : 4253, 4026
7396 04:45:04.805444 36 : 4363, 4138
7397 04:45:04.805873 40 : 4253, 4027
7398 04:45:04.806241 44 : 4253, 4026
7399 04:45:04.809170 48 : 4252, 4027
7400 04:45:04.809704 52 : 4255, 4030
7401 04:45:04.811817 56 : 4252, 4027
7402 04:45:04.812245 60 : 4250, 4027
7403 04:45:04.815555 64 : 4363, 4140
7404 04:45:04.815982 68 : 4250, 4026
7405 04:45:04.816326 72 : 4253, 4030
7406 04:45:04.818606 76 : 4250, 4026
7407 04:45:04.819032 80 : 4361, 4137
7408 04:45:04.822109 84 : 4250, 4027
7409 04:45:04.822554 88 : 4361, 3839
7410 04:45:04.825015 92 : 4253, 0
7411 04:45:04.825459 96 : 4250, 0
7412 04:45:04.825827 100 : 4250, 0
7413 04:45:04.828639 104 : 4360, 0
7414 04:45:04.829063 108 : 4250, 0
7415 04:45:04.832402 112 : 4250, 0
7416 04:45:04.832942 116 : 4250, 0
7417 04:45:04.833287 120 : 4252, 0
7418 04:45:04.835184 124 : 4361, 0
7419 04:45:04.835613 128 : 4250, 0
7420 04:45:04.835956 132 : 4250, 0
7421 04:45:04.838674 136 : 4250, 0
7422 04:45:04.839103 140 : 4361, 0
7423 04:45:04.842005 144 : 4361, 0
7424 04:45:04.842436 148 : 4249, 0
7425 04:45:04.842777 152 : 4361, 0
7426 04:45:04.845849 156 : 4250, 0
7427 04:45:04.846422 160 : 4250, 0
7428 04:45:04.849018 164 : 4250, 0
7429 04:45:04.849551 168 : 4250, 0
7430 04:45:04.849894 172 : 4252, 0
7431 04:45:04.852453 176 : 4250, 0
7432 04:45:04.853007 180 : 4250, 0
7433 04:45:04.853357 184 : 4253, 0
7434 04:45:04.855905 188 : 4361, 0
7435 04:45:04.856449 192 : 4361, 0
7436 04:45:04.858849 196 : 4363, 0
7437 04:45:04.859383 200 : 4250, 2
7438 04:45:04.859733 204 : 4361, 2220
7439 04:45:04.862375 208 : 4363, 4140
7440 04:45:04.862908 212 : 4250, 4027
7441 04:45:04.865624 216 : 4250, 4027
7442 04:45:04.866078 220 : 4360, 4137
7443 04:45:04.868598 224 : 4363, 4137
7444 04:45:04.869022 228 : 4250, 4026
7445 04:45:04.872306 232 : 4363, 4140
7446 04:45:04.872757 236 : 4361, 4137
7447 04:45:04.875492 240 : 4250, 4026
7448 04:45:04.876036 244 : 4250, 4027
7449 04:45:04.878807 248 : 4252, 4030
7450 04:45:04.879339 252 : 4250, 4027
7451 04:45:04.882272 256 : 4250, 4027
7452 04:45:04.882697 260 : 4250, 4027
7453 04:45:04.883065 264 : 4252, 4029
7454 04:45:04.885325 268 : 4250, 4027
7455 04:45:04.885782 272 : 4360, 4137
7456 04:45:04.888769 276 : 4361, 4137
7457 04:45:04.889306 280 : 4250, 4026
7458 04:45:04.891908 284 : 4363, 4139
7459 04:45:04.892334 288 : 4250, 4027
7460 04:45:04.895346 292 : 4250, 4026
7461 04:45:04.895771 296 : 4250, 4027
7462 04:45:04.898390 300 : 4252, 4030
7463 04:45:04.898818 304 : 4250, 4027
7464 04:45:04.902024 308 : 4250, 4026
7465 04:45:04.902449 312 : 4250, 3998
7466 04:45:04.905249 316 : 4252, 2352
7467 04:45:04.905672 320 : 4250, 32
7468 04:45:04.906171
7469 04:45:04.908829 MIOCK jitter meter ch=0
7470 04:45:04.909525
7471 04:45:04.911840 1T = (320-92) = 228 dly cells
7472 04:45:04.915291 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7473 04:45:04.915829 ==
7474 04:45:04.918120 Dram Type= 6, Freq= 0, CH_0, rank 0
7475 04:45:04.925050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7476 04:45:04.925539 ==
7477 04:45:04.928561 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7478 04:45:04.934838 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7479 04:45:04.938224 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7480 04:45:04.944803 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7481 04:45:04.952342 [CA 0] Center 42 (12~72) winsize 61
7482 04:45:04.955717 [CA 1] Center 42 (12~72) winsize 61
7483 04:45:04.959619 [CA 2] Center 37 (7~67) winsize 61
7484 04:45:04.962335 [CA 3] Center 37 (7~67) winsize 61
7485 04:45:04.965870 [CA 4] Center 35 (5~66) winsize 62
7486 04:45:04.969341 [CA 5] Center 35 (5~65) winsize 61
7487 04:45:04.969772
7488 04:45:04.972804 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7489 04:45:04.973273
7490 04:45:04.976091 [CATrainingPosCal] consider 1 rank data
7491 04:45:04.979222 u2DelayCellTimex100 = 285/100 ps
7492 04:45:04.982419 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7493 04:45:04.989297 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7494 04:45:04.992299 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7495 04:45:04.995820 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7496 04:45:04.999136 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7497 04:45:05.002254 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7498 04:45:05.002687
7499 04:45:05.005515 CA PerBit enable=1, Macro0, CA PI delay=35
7500 04:45:05.005966
7501 04:45:05.009479 [CBTSetCACLKResult] CA Dly = 35
7502 04:45:05.012818 CS Dly: 9 (0~40)
7503 04:45:05.015838 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7504 04:45:05.018873 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7505 04:45:05.019304 ==
7506 04:45:05.022187 Dram Type= 6, Freq= 0, CH_0, rank 1
7507 04:45:05.025821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7508 04:45:05.026331 ==
7509 04:45:05.032398 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7510 04:45:05.035699 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7511 04:45:05.042606 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7512 04:45:05.045549 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7513 04:45:05.055744 [CA 0] Center 43 (13~73) winsize 61
7514 04:45:05.059084 [CA 1] Center 43 (13~73) winsize 61
7515 04:45:05.062596 [CA 2] Center 38 (8~68) winsize 61
7516 04:45:05.066015 [CA 3] Center 37 (8~67) winsize 60
7517 04:45:05.069191 [CA 4] Center 36 (6~66) winsize 61
7518 04:45:05.072204 [CA 5] Center 36 (6~66) winsize 61
7519 04:45:05.072677
7520 04:45:05.075891 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7521 04:45:05.076458
7522 04:45:05.079190 [CATrainingPosCal] consider 2 rank data
7523 04:45:05.082618 u2DelayCellTimex100 = 285/100 ps
7524 04:45:05.085601 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7525 04:45:05.092626 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7526 04:45:05.095580 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7527 04:45:05.099368 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7528 04:45:05.102452 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7529 04:45:05.105803 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7530 04:45:05.106324
7531 04:45:05.109087 CA PerBit enable=1, Macro0, CA PI delay=35
7532 04:45:05.109558
7533 04:45:05.112329 [CBTSetCACLKResult] CA Dly = 35
7534 04:45:05.116105 CS Dly: 10 (0~43)
7535 04:45:05.119156 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7536 04:45:05.122629 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7537 04:45:05.123112
7538 04:45:05.126056 ----->DramcWriteLeveling(PI) begin...
7539 04:45:05.126555 ==
7540 04:45:05.129207 Dram Type= 6, Freq= 0, CH_0, rank 0
7541 04:45:05.132552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7542 04:45:05.132983 ==
7543 04:45:05.135991 Write leveling (Byte 0): 36 => 36
7544 04:45:05.139026 Write leveling (Byte 1): 31 => 31
7545 04:45:05.142609 DramcWriteLeveling(PI) end<-----
7546 04:45:05.143126
7547 04:45:05.143468 ==
7548 04:45:05.146037 Dram Type= 6, Freq= 0, CH_0, rank 0
7549 04:45:05.152478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 04:45:05.153000 ==
7551 04:45:05.153346 [Gating] SW mode calibration
7552 04:45:05.162311 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7553 04:45:05.165590 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7554 04:45:05.169133 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 04:45:05.175632 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 04:45:05.179196 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7557 04:45:05.182162 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7558 04:45:05.188896 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7559 04:45:05.192538 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7560 04:45:05.195543 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 04:45:05.202163 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7562 04:45:05.205879 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7563 04:45:05.208942 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7564 04:45:05.215428 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
7565 04:45:05.218671 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7566 04:45:05.221841 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7567 04:45:05.228574 1 5 20 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
7568 04:45:05.231782 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 04:45:05.235198 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 04:45:05.241984 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 04:45:05.244880 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
7572 04:45:05.248380 1 6 8 | B1->B0 | 2323 3e3d | 0 1 | (0 0) (0 0)
7573 04:45:05.255007 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7574 04:45:05.258311 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7575 04:45:05.261596 1 6 20 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7576 04:45:05.268295 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 04:45:05.271825 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 04:45:05.275126 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 04:45:05.281249 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7580 04:45:05.285082 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7581 04:45:05.288538 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7582 04:45:05.294798 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7583 04:45:05.298277 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7584 04:45:05.301320 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7585 04:45:05.308200 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 04:45:05.311371 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 04:45:05.314770 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 04:45:05.321453 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 04:45:05.324753 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 04:45:05.327923 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 04:45:05.334702 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 04:45:05.337833 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 04:45:05.341299 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 04:45:05.348107 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 04:45:05.351573 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 04:45:05.354416 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 04:45:05.357865 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7598 04:45:05.364610 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7599 04:45:05.367838 Total UI for P1: 0, mck2ui 16
7600 04:45:05.371206 best dqsien dly found for B0: ( 1, 9, 12)
7601 04:45:05.374552 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7602 04:45:05.378202 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 04:45:05.380993 Total UI for P1: 0, mck2ui 16
7604 04:45:05.384537 best dqsien dly found for B1: ( 1, 9, 20)
7605 04:45:05.388020 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7606 04:45:05.391050 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7607 04:45:05.394399
7608 04:45:05.397477 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7609 04:45:05.400801 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7610 04:45:05.404616 [Gating] SW calibration Done
7611 04:45:05.405116 ==
7612 04:45:05.407676 Dram Type= 6, Freq= 0, CH_0, rank 0
7613 04:45:05.411319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7614 04:45:05.411798 ==
7615 04:45:05.412177 RX Vref Scan: 0
7616 04:45:05.414298
7617 04:45:05.414862 RX Vref 0 -> 0, step: 1
7618 04:45:05.415241
7619 04:45:05.417628 RX Delay 0 -> 252, step: 8
7620 04:45:05.421088 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7621 04:45:05.424652 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7622 04:45:05.431067 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7623 04:45:05.434355 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7624 04:45:05.437780 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7625 04:45:05.440981 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7626 04:45:05.444536 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7627 04:45:05.447808 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7628 04:45:05.454329 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7629 04:45:05.457922 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7630 04:45:05.460861 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7631 04:45:05.464303 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7632 04:45:05.467815 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7633 04:45:05.474222 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7634 04:45:05.477452 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7635 04:45:05.480850 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
7636 04:45:05.481364 ==
7637 04:45:05.484322 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 04:45:05.487390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 04:45:05.490915 ==
7640 04:45:05.491427 DQS Delay:
7641 04:45:05.491771 DQS0 = 0, DQS1 = 0
7642 04:45:05.494235 DQM Delay:
7643 04:45:05.494663 DQM0 = 137, DQM1 = 126
7644 04:45:05.497330 DQ Delay:
7645 04:45:05.500539 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7646 04:45:05.505158 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7647 04:45:05.507519 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7648 04:45:05.510792 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =131
7649 04:45:05.511331
7650 04:45:05.511679
7651 04:45:05.511993 ==
7652 04:45:05.514012 Dram Type= 6, Freq= 0, CH_0, rank 0
7653 04:45:05.517383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7654 04:45:05.517930 ==
7655 04:45:05.518328
7656 04:45:05.518644
7657 04:45:05.520707 TX Vref Scan disable
7658 04:45:05.523730 == TX Byte 0 ==
7659 04:45:05.527300 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7660 04:45:05.530713 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7661 04:45:05.533923 == TX Byte 1 ==
7662 04:45:05.537196 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7663 04:45:05.540789 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7664 04:45:05.541321 ==
7665 04:45:05.544360 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 04:45:05.550387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 04:45:05.550910 ==
7668 04:45:05.562361
7669 04:45:05.565873 TX Vref early break, caculate TX vref
7670 04:45:05.568880 TX Vref=16, minBit 7, minWin=22, winSum=375
7671 04:45:05.572227 TX Vref=18, minBit 12, minWin=23, winSum=389
7672 04:45:05.575848 TX Vref=20, minBit 7, minWin=23, winSum=393
7673 04:45:05.579076 TX Vref=22, minBit 6, minWin=24, winSum=407
7674 04:45:05.582488 TX Vref=24, minBit 2, minWin=25, winSum=420
7675 04:45:05.588901 TX Vref=26, minBit 2, minWin=25, winSum=425
7676 04:45:05.592305 TX Vref=28, minBit 2, minWin=25, winSum=432
7677 04:45:05.595759 TX Vref=30, minBit 0, minWin=26, winSum=420
7678 04:45:05.598882 TX Vref=32, minBit 0, minWin=25, winSum=414
7679 04:45:05.602274 TX Vref=34, minBit 0, minWin=25, winSum=407
7680 04:45:05.608927 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 30
7681 04:45:05.609420
7682 04:45:05.612301 Final TX Range 0 Vref 30
7683 04:45:05.612801
7684 04:45:05.613140 ==
7685 04:45:05.615546 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 04:45:05.618746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 04:45:05.619248 ==
7688 04:45:05.619588
7689 04:45:05.620056
7690 04:45:05.622101 TX Vref Scan disable
7691 04:45:05.628573 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7692 04:45:05.629181 == TX Byte 0 ==
7693 04:45:05.632113 u2DelayCellOfst[0]=13 cells (4 PI)
7694 04:45:05.635477 u2DelayCellOfst[1]=17 cells (5 PI)
7695 04:45:05.638824 u2DelayCellOfst[2]=10 cells (3 PI)
7696 04:45:05.641920 u2DelayCellOfst[3]=10 cells (3 PI)
7697 04:45:05.645501 u2DelayCellOfst[4]=6 cells (2 PI)
7698 04:45:05.648812 u2DelayCellOfst[5]=0 cells (0 PI)
7699 04:45:05.651735 u2DelayCellOfst[6]=17 cells (5 PI)
7700 04:45:05.654994 u2DelayCellOfst[7]=13 cells (4 PI)
7701 04:45:05.659047 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7702 04:45:05.661725 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7703 04:45:05.665404 == TX Byte 1 ==
7704 04:45:05.665935 u2DelayCellOfst[8]=3 cells (1 PI)
7705 04:45:05.668247 u2DelayCellOfst[9]=0 cells (0 PI)
7706 04:45:05.671633 u2DelayCellOfst[10]=6 cells (2 PI)
7707 04:45:05.675581 u2DelayCellOfst[11]=3 cells (1 PI)
7708 04:45:05.678777 u2DelayCellOfst[12]=13 cells (4 PI)
7709 04:45:05.681931 u2DelayCellOfst[13]=10 cells (3 PI)
7710 04:45:05.684826 u2DelayCellOfst[14]=17 cells (5 PI)
7711 04:45:05.688719 u2DelayCellOfst[15]=13 cells (4 PI)
7712 04:45:05.691868 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7713 04:45:05.698558 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7714 04:45:05.699081 DramC Write-DBI on
7715 04:45:05.699421 ==
7716 04:45:05.701465 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 04:45:05.708214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 04:45:05.708710 ==
7719 04:45:05.709052
7720 04:45:05.709409
7721 04:45:05.709716 TX Vref Scan disable
7722 04:45:05.712017 == TX Byte 0 ==
7723 04:45:05.715171 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7724 04:45:05.718150 == TX Byte 1 ==
7725 04:45:05.721625 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7726 04:45:05.724766 DramC Write-DBI off
7727 04:45:05.725203
7728 04:45:05.725541 [DATLAT]
7729 04:45:05.725856 Freq=1600, CH0 RK0
7730 04:45:05.726198
7731 04:45:05.728570 DATLAT Default: 0xf
7732 04:45:05.729001 0, 0xFFFF, sum = 0
7733 04:45:05.731642 1, 0xFFFF, sum = 0
7734 04:45:05.734889 2, 0xFFFF, sum = 0
7735 04:45:05.735321 3, 0xFFFF, sum = 0
7736 04:45:05.738557 4, 0xFFFF, sum = 0
7737 04:45:05.738986 5, 0xFFFF, sum = 0
7738 04:45:05.741799 6, 0xFFFF, sum = 0
7739 04:45:05.742255 7, 0xFFFF, sum = 0
7740 04:45:05.744710 8, 0xFFFF, sum = 0
7741 04:45:05.745142 9, 0xFFFF, sum = 0
7742 04:45:05.747972 10, 0xFFFF, sum = 0
7743 04:45:05.748401 11, 0xFFFF, sum = 0
7744 04:45:05.751469 12, 0xFFFF, sum = 0
7745 04:45:05.751902 13, 0xFFFF, sum = 0
7746 04:45:05.754886 14, 0x0, sum = 1
7747 04:45:05.755315 15, 0x0, sum = 2
7748 04:45:05.758046 16, 0x0, sum = 3
7749 04:45:05.758478 17, 0x0, sum = 4
7750 04:45:05.761453 best_step = 15
7751 04:45:05.761876
7752 04:45:05.762263 ==
7753 04:45:05.764713 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 04:45:05.768567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 04:45:05.769108 ==
7756 04:45:05.771800 RX Vref Scan: 1
7757 04:45:05.772230
7758 04:45:05.772564 Set Vref Range= 24 -> 127
7759 04:45:05.772906
7760 04:45:05.774720 RX Vref 24 -> 127, step: 1
7761 04:45:05.775144
7762 04:45:05.778279 RX Delay 19 -> 252, step: 4
7763 04:45:05.778705
7764 04:45:05.781822 Set Vref, RX VrefLevel [Byte0]: 24
7765 04:45:05.784864 [Byte1]: 24
7766 04:45:05.785289
7767 04:45:05.788328 Set Vref, RX VrefLevel [Byte0]: 25
7768 04:45:05.791651 [Byte1]: 25
7769 04:45:05.792075
7770 04:45:05.794881 Set Vref, RX VrefLevel [Byte0]: 26
7771 04:45:05.798232 [Byte1]: 26
7772 04:45:05.802665
7773 04:45:05.803212 Set Vref, RX VrefLevel [Byte0]: 27
7774 04:45:05.805561 [Byte1]: 27
7775 04:45:05.809822
7776 04:45:05.810292 Set Vref, RX VrefLevel [Byte0]: 28
7777 04:45:05.813130 [Byte1]: 28
7778 04:45:05.817133
7779 04:45:05.817635 Set Vref, RX VrefLevel [Byte0]: 29
7780 04:45:05.820326 [Byte1]: 29
7781 04:45:05.825078
7782 04:45:05.825500 Set Vref, RX VrefLevel [Byte0]: 30
7783 04:45:05.827976 [Byte1]: 30
7784 04:45:05.832475
7785 04:45:05.832901 Set Vref, RX VrefLevel [Byte0]: 31
7786 04:45:05.835489 [Byte1]: 31
7787 04:45:05.840004
7788 04:45:05.840509 Set Vref, RX VrefLevel [Byte0]: 32
7789 04:45:05.843471 [Byte1]: 32
7790 04:45:05.847416
7791 04:45:05.847843 Set Vref, RX VrefLevel [Byte0]: 33
7792 04:45:05.850682 [Byte1]: 33
7793 04:45:05.855090
7794 04:45:05.855607 Set Vref, RX VrefLevel [Byte0]: 34
7795 04:45:05.858580 [Byte1]: 34
7796 04:45:05.862858
7797 04:45:05.863282 Set Vref, RX VrefLevel [Byte0]: 35
7798 04:45:05.866256 [Byte1]: 35
7799 04:45:05.870420
7800 04:45:05.870850 Set Vref, RX VrefLevel [Byte0]: 36
7801 04:45:05.873355 [Byte1]: 36
7802 04:45:05.877932
7803 04:45:05.878466 Set Vref, RX VrefLevel [Byte0]: 37
7804 04:45:05.881437 [Byte1]: 37
7805 04:45:05.885379
7806 04:45:05.885803 Set Vref, RX VrefLevel [Byte0]: 38
7807 04:45:05.888898 [Byte1]: 38
7808 04:45:05.893061
7809 04:45:05.893678 Set Vref, RX VrefLevel [Byte0]: 39
7810 04:45:05.896502 [Byte1]: 39
7811 04:45:05.900582
7812 04:45:05.901086 Set Vref, RX VrefLevel [Byte0]: 40
7813 04:45:05.903958 [Byte1]: 40
7814 04:45:05.908185
7815 04:45:05.908711 Set Vref, RX VrefLevel [Byte0]: 41
7816 04:45:05.911476 [Byte1]: 41
7817 04:45:05.915770
7818 04:45:05.916212 Set Vref, RX VrefLevel [Byte0]: 42
7819 04:45:05.918856 [Byte1]: 42
7820 04:45:05.923070
7821 04:45:05.923512 Set Vref, RX VrefLevel [Byte0]: 43
7822 04:45:05.926469 [Byte1]: 43
7823 04:45:05.930630
7824 04:45:05.931056 Set Vref, RX VrefLevel [Byte0]: 44
7825 04:45:05.933895 [Byte1]: 44
7826 04:45:05.938310
7827 04:45:05.938806 Set Vref, RX VrefLevel [Byte0]: 45
7828 04:45:05.941572 [Byte1]: 45
7829 04:45:05.946385
7830 04:45:05.946907 Set Vref, RX VrefLevel [Byte0]: 46
7831 04:45:05.949556 [Byte1]: 46
7832 04:45:05.953618
7833 04:45:05.954073 Set Vref, RX VrefLevel [Byte0]: 47
7834 04:45:05.956869 [Byte1]: 47
7835 04:45:05.961389
7836 04:45:05.961891 Set Vref, RX VrefLevel [Byte0]: 48
7837 04:45:05.964291 [Byte1]: 48
7838 04:45:05.968642
7839 04:45:05.969071 Set Vref, RX VrefLevel [Byte0]: 49
7840 04:45:05.971803 [Byte1]: 49
7841 04:45:05.976269
7842 04:45:05.976697 Set Vref, RX VrefLevel [Byte0]: 50
7843 04:45:05.979313 [Byte1]: 50
7844 04:45:05.983756
7845 04:45:05.984199 Set Vref, RX VrefLevel [Byte0]: 51
7846 04:45:05.987138 [Byte1]: 51
7847 04:45:05.991339
7848 04:45:05.991765 Set Vref, RX VrefLevel [Byte0]: 52
7849 04:45:05.994761 [Byte1]: 52
7850 04:45:05.998894
7851 04:45:05.999411 Set Vref, RX VrefLevel [Byte0]: 53
7852 04:45:06.002352 [Byte1]: 53
7853 04:45:06.006531
7854 04:45:06.007068 Set Vref, RX VrefLevel [Byte0]: 54
7855 04:45:06.010053 [Byte1]: 54
7856 04:45:06.014070
7857 04:45:06.014555 Set Vref, RX VrefLevel [Byte0]: 55
7858 04:45:06.017693 [Byte1]: 55
7859 04:45:06.021503
7860 04:45:06.021930 Set Vref, RX VrefLevel [Byte0]: 56
7861 04:45:06.025188 [Byte1]: 56
7862 04:45:06.029076
7863 04:45:06.029507 Set Vref, RX VrefLevel [Byte0]: 57
7864 04:45:06.032745 [Byte1]: 57
7865 04:45:06.036919
7866 04:45:06.037345 Set Vref, RX VrefLevel [Byte0]: 58
7867 04:45:06.040271 [Byte1]: 58
7868 04:45:06.044874
7869 04:45:06.045401 Set Vref, RX VrefLevel [Byte0]: 59
7870 04:45:06.047567 [Byte1]: 59
7871 04:45:06.052378
7872 04:45:06.052910 Set Vref, RX VrefLevel [Byte0]: 60
7873 04:45:06.055417 [Byte1]: 60
7874 04:45:06.059605
7875 04:45:06.060143 Set Vref, RX VrefLevel [Byte0]: 61
7876 04:45:06.062808 [Byte1]: 61
7877 04:45:06.067346
7878 04:45:06.067772 Set Vref, RX VrefLevel [Byte0]: 62
7879 04:45:06.070254 [Byte1]: 62
7880 04:45:06.074544
7881 04:45:06.074972 Set Vref, RX VrefLevel [Byte0]: 63
7882 04:45:06.077970 [Byte1]: 63
7883 04:45:06.082810
7884 04:45:06.083334 Set Vref, RX VrefLevel [Byte0]: 64
7885 04:45:06.085584 [Byte1]: 64
7886 04:45:06.089820
7887 04:45:06.090306 Set Vref, RX VrefLevel [Byte0]: 65
7888 04:45:06.093370 [Byte1]: 65
7889 04:45:06.097335
7890 04:45:06.097826 Set Vref, RX VrefLevel [Byte0]: 66
7891 04:45:06.100754 [Byte1]: 66
7892 04:45:06.105065
7893 04:45:06.105608 Set Vref, RX VrefLevel [Byte0]: 67
7894 04:45:06.108762 [Byte1]: 67
7895 04:45:06.112589
7896 04:45:06.113114 Set Vref, RX VrefLevel [Byte0]: 68
7897 04:45:06.116115 [Byte1]: 68
7898 04:45:06.120082
7899 04:45:06.120508 Set Vref, RX VrefLevel [Byte0]: 69
7900 04:45:06.123454 [Byte1]: 69
7901 04:45:06.127765
7902 04:45:06.128194 Set Vref, RX VrefLevel [Byte0]: 70
7903 04:45:06.131174 [Byte1]: 70
7904 04:45:06.134990
7905 04:45:06.135480 Set Vref, RX VrefLevel [Byte0]: 71
7906 04:45:06.138702 [Byte1]: 71
7907 04:45:06.142921
7908 04:45:06.143346 Set Vref, RX VrefLevel [Byte0]: 72
7909 04:45:06.146050 [Byte1]: 72
7910 04:45:06.150546
7911 04:45:06.150974 Set Vref, RX VrefLevel [Byte0]: 73
7912 04:45:06.153474 [Byte1]: 73
7913 04:45:06.158016
7914 04:45:06.158505 Set Vref, RX VrefLevel [Byte0]: 74
7915 04:45:06.161289 [Byte1]: 74
7916 04:45:06.165610
7917 04:45:06.166169 Set Vref, RX VrefLevel [Byte0]: 75
7918 04:45:06.169038 [Byte1]: 75
7919 04:45:06.173190
7920 04:45:06.173620 Set Vref, RX VrefLevel [Byte0]: 76
7921 04:45:06.176466 [Byte1]: 76
7922 04:45:06.181044
7923 04:45:06.181612 Set Vref, RX VrefLevel [Byte0]: 77
7924 04:45:06.184330 [Byte1]: 77
7925 04:45:06.188508
7926 04:45:06.188940 Final RX Vref Byte 0 = 66 to rank0
7927 04:45:06.191787 Final RX Vref Byte 1 = 63 to rank0
7928 04:45:06.195372 Final RX Vref Byte 0 = 66 to rank1
7929 04:45:06.198277 Final RX Vref Byte 1 = 63 to rank1==
7930 04:45:06.201728 Dram Type= 6, Freq= 0, CH_0, rank 0
7931 04:45:06.205255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7932 04:45:06.208704 ==
7933 04:45:06.209228 DQS Delay:
7934 04:45:06.209575 DQS0 = 0, DQS1 = 0
7935 04:45:06.211915 DQM Delay:
7936 04:45:06.212446 DQM0 = 136, DQM1 = 124
7937 04:45:06.215231 DQ Delay:
7938 04:45:06.218628 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7939 04:45:06.221777 DQ4 =140, DQ5 =126, DQ6 =146, DQ7 =142
7940 04:45:06.225082 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7941 04:45:06.228285 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =132
7942 04:45:06.228741
7943 04:45:06.229161
7944 04:45:06.229505
7945 04:45:06.231655 [DramC_TX_OE_Calibration] TA2
7946 04:45:06.234648 Original DQ_B0 (3 6) =30, OEN = 27
7947 04:45:06.238025 Original DQ_B1 (3 6) =30, OEN = 27
7948 04:45:06.241379 24, 0x0, End_B0=24 End_B1=24
7949 04:45:06.241853 25, 0x0, End_B0=25 End_B1=25
7950 04:45:06.244806 26, 0x0, End_B0=26 End_B1=26
7951 04:45:06.248351 27, 0x0, End_B0=27 End_B1=27
7952 04:45:06.251893 28, 0x0, End_B0=28 End_B1=28
7953 04:45:06.252431 29, 0x0, End_B0=29 End_B1=29
7954 04:45:06.254570 30, 0x0, End_B0=30 End_B1=30
7955 04:45:06.258279 31, 0x4141, End_B0=30 End_B1=30
7956 04:45:06.261749 Byte0 end_step=30 best_step=27
7957 04:45:06.264677 Byte1 end_step=30 best_step=27
7958 04:45:06.268308 Byte0 TX OE(2T, 0.5T) = (3, 3)
7959 04:45:06.268846 Byte1 TX OE(2T, 0.5T) = (3, 3)
7960 04:45:06.271261
7961 04:45:06.271861
7962 04:45:06.278532 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7963 04:45:06.281503 CH0 RK0: MR19=303, MR18=1C1A
7964 04:45:06.288040 CH0_RK0: MR19=0x303, MR18=0x1C1A, DQSOSC=395, MR23=63, INC=23, DEC=15
7965 04:45:06.288563
7966 04:45:06.291557 ----->DramcWriteLeveling(PI) begin...
7967 04:45:06.292084 ==
7968 04:45:06.294439 Dram Type= 6, Freq= 0, CH_0, rank 1
7969 04:45:06.297814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7970 04:45:06.298298 ==
7971 04:45:06.301549 Write leveling (Byte 0): 38 => 38
7972 04:45:06.304311 Write leveling (Byte 1): 30 => 30
7973 04:45:06.307764 DramcWriteLeveling(PI) end<-----
7974 04:45:06.308215
7975 04:45:06.308585 ==
7976 04:45:06.311494 Dram Type= 6, Freq= 0, CH_0, rank 1
7977 04:45:06.315091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7978 04:45:06.315614 ==
7979 04:45:06.317638 [Gating] SW mode calibration
7980 04:45:06.324513 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7981 04:45:06.330942 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7982 04:45:06.334546 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7983 04:45:06.337679 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7984 04:45:06.344493 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7985 04:45:06.347624 1 4 12 | B1->B0 | 2424 2c2c | 0 1 | (1 1) (1 1)
7986 04:45:06.351068 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7987 04:45:06.357468 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7988 04:45:06.361234 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7989 04:45:06.364266 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7990 04:45:06.370765 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7991 04:45:06.374442 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7992 04:45:06.377775 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7993 04:45:06.384180 1 5 12 | B1->B0 | 3434 2828 | 0 0 | (0 1) (0 0)
7994 04:45:06.387523 1 5 16 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (1 0)
7995 04:45:06.390733 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 04:45:06.398042 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 04:45:06.400836 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7998 04:45:06.404089 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7999 04:45:06.410621 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 04:45:06.414052 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8001 04:45:06.417437 1 6 12 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8002 04:45:06.424228 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8003 04:45:06.427175 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 04:45:06.430687 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 04:45:06.437167 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 04:45:06.441060 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 04:45:06.444054 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 04:45:06.447179 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 04:45:06.453894 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8010 04:45:06.457065 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8011 04:45:06.460773 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 04:45:06.467290 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 04:45:06.470806 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 04:45:06.474050 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 04:45:06.480769 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 04:45:06.484110 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 04:45:06.487131 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 04:45:06.494489 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 04:45:06.497511 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 04:45:06.501256 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 04:45:06.507573 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 04:45:06.510633 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 04:45:06.514334 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 04:45:06.520883 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8025 04:45:06.523968 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8026 04:45:06.527212 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8027 04:45:06.530406 Total UI for P1: 0, mck2ui 16
8028 04:45:06.533853 best dqsien dly found for B0: ( 1, 9, 10)
8029 04:45:06.540816 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 04:45:06.541239 Total UI for P1: 0, mck2ui 16
8031 04:45:06.543844 best dqsien dly found for B1: ( 1, 9, 16)
8032 04:45:06.550300 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8033 04:45:06.553603 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8034 04:45:06.554050
8035 04:45:06.557226 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8036 04:45:06.560205 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8037 04:45:06.564006 [Gating] SW calibration Done
8038 04:45:06.564511 ==
8039 04:45:06.567195 Dram Type= 6, Freq= 0, CH_0, rank 1
8040 04:45:06.570744 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 04:45:06.571346 ==
8042 04:45:06.573720 RX Vref Scan: 0
8043 04:45:06.574244
8044 04:45:06.574626 RX Vref 0 -> 0, step: 1
8045 04:45:06.574955
8046 04:45:06.577253 RX Delay 0 -> 252, step: 8
8047 04:45:06.580470 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8048 04:45:06.587026 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8049 04:45:06.590179 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8050 04:45:06.593576 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8051 04:45:06.596949 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8052 04:45:06.600128 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
8053 04:45:06.603495 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8054 04:45:06.610363 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8055 04:45:06.613593 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8056 04:45:06.617056 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8057 04:45:06.620579 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8058 04:45:06.623540 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8059 04:45:06.630252 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8060 04:45:06.633858 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8061 04:45:06.637301 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8062 04:45:06.640342 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8063 04:45:06.640871 ==
8064 04:45:06.643830 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 04:45:06.650233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 04:45:06.650664 ==
8067 04:45:06.651000 DQS Delay:
8068 04:45:06.653685 DQS0 = 0, DQS1 = 0
8069 04:45:06.654132 DQM Delay:
8070 04:45:06.654475 DQM0 = 136, DQM1 = 125
8071 04:45:06.657345 DQ Delay:
8072 04:45:06.660330 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8073 04:45:06.663704 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
8074 04:45:06.666730 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8075 04:45:06.670507 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8076 04:45:06.670937
8077 04:45:06.671278
8078 04:45:06.671594 ==
8079 04:45:06.673699 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 04:45:06.677022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 04:45:06.680192 ==
8082 04:45:06.680630
8083 04:45:06.681062
8084 04:45:06.681471 TX Vref Scan disable
8085 04:45:06.683547 == TX Byte 0 ==
8086 04:45:06.686841 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8087 04:45:06.690486 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8088 04:45:06.693715 == TX Byte 1 ==
8089 04:45:06.697069 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8090 04:45:06.700541 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8091 04:45:06.703891 ==
8092 04:45:06.704327 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 04:45:06.710083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 04:45:06.710594 ==
8095 04:45:06.723045
8096 04:45:06.726608 TX Vref early break, caculate TX vref
8097 04:45:06.730104 TX Vref=16, minBit 0, minWin=23, winSum=389
8098 04:45:06.733363 TX Vref=18, minBit 0, minWin=24, winSum=398
8099 04:45:06.736702 TX Vref=20, minBit 8, minWin=24, winSum=409
8100 04:45:06.740095 TX Vref=22, minBit 0, minWin=25, winSum=417
8101 04:45:06.743133 TX Vref=24, minBit 0, minWin=25, winSum=424
8102 04:45:06.746560 TX Vref=26, minBit 0, minWin=26, winSum=435
8103 04:45:06.753622 TX Vref=28, minBit 0, minWin=26, winSum=434
8104 04:45:06.756474 TX Vref=30, minBit 0, minWin=26, winSum=427
8105 04:45:06.759973 TX Vref=32, minBit 0, minWin=25, winSum=419
8106 04:45:06.763476 TX Vref=34, minBit 0, minWin=25, winSum=411
8107 04:45:06.769641 [TxChooseVref] Worse bit 0, Min win 26, Win sum 435, Final Vref 26
8108 04:45:06.770198
8109 04:45:06.773340 Final TX Range 0 Vref 26
8110 04:45:06.773800
8111 04:45:06.774221 ==
8112 04:45:06.776450 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 04:45:06.779539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 04:45:06.780040 ==
8115 04:45:06.780415
8116 04:45:06.780754
8117 04:45:06.783201 TX Vref Scan disable
8118 04:45:06.789764 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8119 04:45:06.790275 == TX Byte 0 ==
8120 04:45:06.793053 u2DelayCellOfst[0]=13 cells (4 PI)
8121 04:45:06.796427 u2DelayCellOfst[1]=20 cells (6 PI)
8122 04:45:06.799630 u2DelayCellOfst[2]=13 cells (4 PI)
8123 04:45:06.803212 u2DelayCellOfst[3]=13 cells (4 PI)
8124 04:45:06.806161 u2DelayCellOfst[4]=10 cells (3 PI)
8125 04:45:06.809711 u2DelayCellOfst[5]=0 cells (0 PI)
8126 04:45:06.813384 u2DelayCellOfst[6]=20 cells (6 PI)
8127 04:45:06.813904 u2DelayCellOfst[7]=17 cells (5 PI)
8128 04:45:06.819921 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8129 04:45:06.823086 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8130 04:45:06.823618 == TX Byte 1 ==
8131 04:45:06.826517 u2DelayCellOfst[8]=0 cells (0 PI)
8132 04:45:06.829444 u2DelayCellOfst[9]=0 cells (0 PI)
8133 04:45:06.832804 u2DelayCellOfst[10]=6 cells (2 PI)
8134 04:45:06.835985 u2DelayCellOfst[11]=3 cells (1 PI)
8135 04:45:06.839394 u2DelayCellOfst[12]=13 cells (4 PI)
8136 04:45:06.842616 u2DelayCellOfst[13]=13 cells (4 PI)
8137 04:45:06.846090 u2DelayCellOfst[14]=17 cells (5 PI)
8138 04:45:06.849546 u2DelayCellOfst[15]=10 cells (3 PI)
8139 04:45:06.852714 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8140 04:45:06.859868 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8141 04:45:06.860380 DramC Write-DBI on
8142 04:45:06.860722 ==
8143 04:45:06.862611 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 04:45:06.866054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 04:45:06.869345 ==
8146 04:45:06.869885
8147 04:45:06.870256
8148 04:45:06.870565 TX Vref Scan disable
8149 04:45:06.873083 == TX Byte 0 ==
8150 04:45:06.876489 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8151 04:45:06.879658 == TX Byte 1 ==
8152 04:45:06.882492 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8153 04:45:06.886211 DramC Write-DBI off
8154 04:45:06.886738
8155 04:45:06.887079 [DATLAT]
8156 04:45:06.887394 Freq=1600, CH0 RK1
8157 04:45:06.887701
8158 04:45:06.889632 DATLAT Default: 0xf
8159 04:45:06.890200 0, 0xFFFF, sum = 0
8160 04:45:06.892741 1, 0xFFFF, sum = 0
8161 04:45:06.896362 2, 0xFFFF, sum = 0
8162 04:45:06.896941 3, 0xFFFF, sum = 0
8163 04:45:06.899177 4, 0xFFFF, sum = 0
8164 04:45:06.899657 5, 0xFFFF, sum = 0
8165 04:45:06.903082 6, 0xFFFF, sum = 0
8166 04:45:06.903660 7, 0xFFFF, sum = 0
8167 04:45:06.906178 8, 0xFFFF, sum = 0
8168 04:45:06.906656 9, 0xFFFF, sum = 0
8169 04:45:06.909557 10, 0xFFFF, sum = 0
8170 04:45:06.910173 11, 0xFFFF, sum = 0
8171 04:45:06.912781 12, 0xFFFF, sum = 0
8172 04:45:06.913359 13, 0xFFFF, sum = 0
8173 04:45:06.916144 14, 0x0, sum = 1
8174 04:45:06.916728 15, 0x0, sum = 2
8175 04:45:06.919407 16, 0x0, sum = 3
8176 04:45:06.919889 17, 0x0, sum = 4
8177 04:45:06.922809 best_step = 15
8178 04:45:06.923278
8179 04:45:06.923654 ==
8180 04:45:06.925833 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 04:45:06.929336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 04:45:06.929811 ==
8183 04:45:06.932497 RX Vref Scan: 0
8184 04:45:06.933065
8185 04:45:06.933441 RX Vref 0 -> 0, step: 1
8186 04:45:06.933794
8187 04:45:06.935888 RX Delay 11 -> 252, step: 4
8188 04:45:06.939405 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8189 04:45:06.945664 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8190 04:45:06.949221 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8191 04:45:06.952797 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8192 04:45:06.955739 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8193 04:45:06.959122 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8194 04:45:06.966090 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8195 04:45:06.969380 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8196 04:45:06.972848 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8197 04:45:06.975951 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8198 04:45:06.979089 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8199 04:45:06.985832 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8200 04:45:06.989202 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8201 04:45:06.992485 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8202 04:45:06.995871 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8203 04:45:06.998833 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8204 04:45:07.002077 ==
8205 04:45:07.005354 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 04:45:07.008682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 04:45:07.009154 ==
8208 04:45:07.009617 DQS Delay:
8209 04:45:07.012210 DQS0 = 0, DQS1 = 0
8210 04:45:07.012794 DQM Delay:
8211 04:45:07.015202 DQM0 = 133, DQM1 = 123
8212 04:45:07.015674 DQ Delay:
8213 04:45:07.018506 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8214 04:45:07.022270 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8215 04:45:07.025405 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8216 04:45:07.028909 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8217 04:45:07.029377
8218 04:45:07.029802
8219 04:45:07.030208
8220 04:45:07.031964 [DramC_TX_OE_Calibration] TA2
8221 04:45:07.035405 Original DQ_B0 (3 6) =30, OEN = 27
8222 04:45:07.038897 Original DQ_B1 (3 6) =30, OEN = 27
8223 04:45:07.042528 24, 0x0, End_B0=24 End_B1=24
8224 04:45:07.045670 25, 0x0, End_B0=25 End_B1=25
8225 04:45:07.046239 26, 0x0, End_B0=26 End_B1=26
8226 04:45:07.049258 27, 0x0, End_B0=27 End_B1=27
8227 04:45:07.052518 28, 0x0, End_B0=28 End_B1=28
8228 04:45:07.055769 29, 0x0, End_B0=29 End_B1=29
8229 04:45:07.058719 30, 0x0, End_B0=30 End_B1=30
8230 04:45:07.059151 31, 0x4545, End_B0=30 End_B1=30
8231 04:45:07.062201 Byte0 end_step=30 best_step=27
8232 04:45:07.065061 Byte1 end_step=30 best_step=27
8233 04:45:07.068932 Byte0 TX OE(2T, 0.5T) = (3, 3)
8234 04:45:07.072377 Byte1 TX OE(2T, 0.5T) = (3, 3)
8235 04:45:07.072919
8236 04:45:07.073265
8237 04:45:07.078577 [DQSOSCAuto] RK1, (LSB)MR18= 0x210f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8238 04:45:07.081966 CH0 RK1: MR19=303, MR18=210F
8239 04:45:07.089006 CH0_RK1: MR19=0x303, MR18=0x210F, DQSOSC=393, MR23=63, INC=23, DEC=15
8240 04:45:07.091749 [RxdqsGatingPostProcess] freq 1600
8241 04:45:07.098655 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8242 04:45:07.099206 best DQS0 dly(2T, 0.5T) = (1, 1)
8243 04:45:07.101815 best DQS1 dly(2T, 0.5T) = (1, 1)
8244 04:45:07.105384 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8245 04:45:07.108734 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8246 04:45:07.112239 best DQS0 dly(2T, 0.5T) = (1, 1)
8247 04:45:07.115350 best DQS1 dly(2T, 0.5T) = (1, 1)
8248 04:45:07.118677 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8249 04:45:07.122004 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8250 04:45:07.125242 Pre-setting of DQS Precalculation
8251 04:45:07.128928 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8252 04:45:07.129356 ==
8253 04:45:07.131870 Dram Type= 6, Freq= 0, CH_1, rank 0
8254 04:45:07.138361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 04:45:07.138789 ==
8256 04:45:07.141813 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8257 04:45:07.148614 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8258 04:45:07.151919 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8259 04:45:07.158453 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8260 04:45:07.165837 [CA 0] Center 40 (10~70) winsize 61
8261 04:45:07.169336 [CA 1] Center 41 (11~71) winsize 61
8262 04:45:07.172911 [CA 2] Center 37 (8~67) winsize 60
8263 04:45:07.175607 [CA 3] Center 36 (7~66) winsize 60
8264 04:45:07.179167 [CA 4] Center 36 (7~66) winsize 60
8265 04:45:07.182574 [CA 5] Center 36 (6~66) winsize 61
8266 04:45:07.183042
8267 04:45:07.186008 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8268 04:45:07.186537
8269 04:45:07.189492 [CATrainingPosCal] consider 1 rank data
8270 04:45:07.192866 u2DelayCellTimex100 = 285/100 ps
8271 04:45:07.195684 CA0 delay=40 (10~70),Diff = 4 PI (13 cell)
8272 04:45:07.202514 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8273 04:45:07.205917 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8274 04:45:07.209030 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8275 04:45:07.212624 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8276 04:45:07.216168 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8277 04:45:07.216734
8278 04:45:07.219203 CA PerBit enable=1, Macro0, CA PI delay=36
8279 04:45:07.219677
8280 04:45:07.222635 [CBTSetCACLKResult] CA Dly = 36
8281 04:45:07.226007 CS Dly: 8 (0~39)
8282 04:45:07.229200 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8283 04:45:07.232395 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8284 04:45:07.232866 ==
8285 04:45:07.235584 Dram Type= 6, Freq= 0, CH_1, rank 1
8286 04:45:07.239133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 04:45:07.239608 ==
8288 04:45:07.245880 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8289 04:45:07.249439 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8290 04:45:07.255876 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8291 04:45:07.258921 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8292 04:45:07.269193 [CA 0] Center 42 (13~71) winsize 59
8293 04:45:07.272582 [CA 1] Center 41 (12~71) winsize 60
8294 04:45:07.275481 [CA 2] Center 38 (9~67) winsize 59
8295 04:45:07.278928 [CA 3] Center 37 (8~67) winsize 60
8296 04:45:07.282348 [CA 4] Center 38 (9~67) winsize 59
8297 04:45:07.285635 [CA 5] Center 37 (7~67) winsize 61
8298 04:45:07.286195
8299 04:45:07.289160 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8300 04:45:07.289671
8301 04:45:07.292567 [CATrainingPosCal] consider 2 rank data
8302 04:45:07.295586 u2DelayCellTimex100 = 285/100 ps
8303 04:45:07.299166 CA0 delay=41 (13~70),Diff = 5 PI (17 cell)
8304 04:45:07.305621 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8305 04:45:07.308751 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8306 04:45:07.312175 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8307 04:45:07.315299 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8308 04:45:07.318946 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8309 04:45:07.319404
8310 04:45:07.322300 CA PerBit enable=1, Macro0, CA PI delay=36
8311 04:45:07.322732
8312 04:45:07.325135 [CBTSetCACLKResult] CA Dly = 36
8313 04:45:07.329020 CS Dly: 9 (0~41)
8314 04:45:07.332038 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8315 04:45:07.335302 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8316 04:45:07.335755
8317 04:45:07.338576 ----->DramcWriteLeveling(PI) begin...
8318 04:45:07.339038 ==
8319 04:45:07.342019 Dram Type= 6, Freq= 0, CH_1, rank 0
8320 04:45:07.345510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 04:45:07.349042 ==
8322 04:45:07.349550 Write leveling (Byte 0): 25 => 25
8323 04:45:07.351765 Write leveling (Byte 1): 27 => 27
8324 04:45:07.355479 DramcWriteLeveling(PI) end<-----
8325 04:45:07.355994
8326 04:45:07.356321 ==
8327 04:45:07.358808 Dram Type= 6, Freq= 0, CH_1, rank 0
8328 04:45:07.365691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 04:45:07.366296 ==
8330 04:45:07.366632 [Gating] SW mode calibration
8331 04:45:07.375470 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8332 04:45:07.378708 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8333 04:45:07.385477 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 04:45:07.388937 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 04:45:07.392273 1 4 8 | B1->B0 | 3131 3434 | 1 0 | (1 1) (0 0)
8336 04:45:07.395221 1 4 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
8337 04:45:07.402091 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 04:45:07.405680 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 04:45:07.408640 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 04:45:07.415505 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8341 04:45:07.418648 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8342 04:45:07.421795 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8343 04:45:07.428146 1 5 8 | B1->B0 | 2626 2525 | 0 0 | (0 0) (1 0)
8344 04:45:07.431544 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8345 04:45:07.435274 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 04:45:07.441694 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 04:45:07.445165 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 04:45:07.448329 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 04:45:07.455111 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 04:45:07.458321 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 04:45:07.461828 1 6 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8352 04:45:07.468460 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 04:45:07.471694 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 04:45:07.474613 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 04:45:07.481717 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 04:45:07.485234 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 04:45:07.488253 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 04:45:07.494860 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 04:45:07.498552 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8360 04:45:07.501397 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8361 04:45:07.508182 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 04:45:07.511641 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 04:45:07.515135 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 04:45:07.521428 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 04:45:07.524870 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 04:45:07.527941 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 04:45:07.534908 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 04:45:07.538132 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 04:45:07.541355 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 04:45:07.544930 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 04:45:07.551626 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 04:45:07.554704 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 04:45:07.558382 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 04:45:07.564910 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 04:45:07.568426 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8376 04:45:07.571737 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8377 04:45:07.574880 Total UI for P1: 0, mck2ui 16
8378 04:45:07.577880 best dqsien dly found for B0: ( 1, 9, 8)
8379 04:45:07.584731 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 04:45:07.585300 Total UI for P1: 0, mck2ui 16
8381 04:45:07.591463 best dqsien dly found for B1: ( 1, 9, 12)
8382 04:45:07.595091 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8383 04:45:07.598178 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8384 04:45:07.598743
8385 04:45:07.601579 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8386 04:45:07.605016 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8387 04:45:07.608035 [Gating] SW calibration Done
8388 04:45:07.608601 ==
8389 04:45:07.611188 Dram Type= 6, Freq= 0, CH_1, rank 0
8390 04:45:07.614800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8391 04:45:07.615371 ==
8392 04:45:07.617867 RX Vref Scan: 0
8393 04:45:07.618478
8394 04:45:07.618849 RX Vref 0 -> 0, step: 1
8395 04:45:07.619199
8396 04:45:07.620949 RX Delay 0 -> 252, step: 8
8397 04:45:07.624576 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8398 04:45:07.630989 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8399 04:45:07.634744 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8400 04:45:07.638056 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8401 04:45:07.641269 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8402 04:45:07.644979 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8403 04:45:07.648136 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8404 04:45:07.654457 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8405 04:45:07.657722 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8406 04:45:07.661209 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8407 04:45:07.664527 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8408 04:45:07.668087 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8409 04:45:07.674490 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8410 04:45:07.677798 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8411 04:45:07.681328 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8412 04:45:07.684368 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8413 04:45:07.684936 ==
8414 04:45:07.687853 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 04:45:07.694625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 04:45:07.695195 ==
8417 04:45:07.695569 DQS Delay:
8418 04:45:07.697643 DQS0 = 0, DQS1 = 0
8419 04:45:07.698246 DQM Delay:
8420 04:45:07.701067 DQM0 = 136, DQM1 = 130
8421 04:45:07.701629 DQ Delay:
8422 04:45:07.704638 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8423 04:45:07.707613 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8424 04:45:07.710890 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8425 04:45:07.714533 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8426 04:45:07.715102
8427 04:45:07.715473
8428 04:45:07.715815 ==
8429 04:45:07.718160 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 04:45:07.724398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 04:45:07.724991 ==
8432 04:45:07.725367
8433 04:45:07.725711
8434 04:45:07.726080 TX Vref Scan disable
8435 04:45:07.727650 == TX Byte 0 ==
8436 04:45:07.730489 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8437 04:45:07.734115 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8438 04:45:07.737259 == TX Byte 1 ==
8439 04:45:07.740912 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8440 04:45:07.747688 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8441 04:45:07.748263 ==
8442 04:45:07.750744 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 04:45:07.754318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 04:45:07.754882 ==
8445 04:45:07.766011
8446 04:45:07.769728 TX Vref early break, caculate TX vref
8447 04:45:07.772726 TX Vref=16, minBit 9, minWin=22, winSum=371
8448 04:45:07.776164 TX Vref=18, minBit 10, minWin=22, winSum=383
8449 04:45:07.779474 TX Vref=20, minBit 10, minWin=23, winSum=393
8450 04:45:07.782673 TX Vref=22, minBit 10, minWin=24, winSum=404
8451 04:45:07.786109 TX Vref=24, minBit 10, minWin=24, winSum=412
8452 04:45:07.792869 TX Vref=26, minBit 6, minWin=25, winSum=420
8453 04:45:07.796294 TX Vref=28, minBit 14, minWin=25, winSum=425
8454 04:45:07.799726 TX Vref=30, minBit 10, minWin=25, winSum=420
8455 04:45:07.802699 TX Vref=32, minBit 13, minWin=24, winSum=411
8456 04:45:07.806095 TX Vref=34, minBit 9, minWin=24, winSum=401
8457 04:45:07.812902 [TxChooseVref] Worse bit 14, Min win 25, Win sum 425, Final Vref 28
8458 04:45:07.813479
8459 04:45:07.816210 Final TX Range 0 Vref 28
8460 04:45:07.816782
8461 04:45:07.817158 ==
8462 04:45:07.818977 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 04:45:07.822584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 04:45:07.823179 ==
8465 04:45:07.823563
8466 04:45:07.823908
8467 04:45:07.825936 TX Vref Scan disable
8468 04:45:07.832628 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8469 04:45:07.833205 == TX Byte 0 ==
8470 04:45:07.835746 u2DelayCellOfst[0]=17 cells (5 PI)
8471 04:45:07.839172 u2DelayCellOfst[1]=10 cells (3 PI)
8472 04:45:07.842460 u2DelayCellOfst[2]=0 cells (0 PI)
8473 04:45:07.845742 u2DelayCellOfst[3]=6 cells (2 PI)
8474 04:45:07.849283 u2DelayCellOfst[4]=6 cells (2 PI)
8475 04:45:07.852462 u2DelayCellOfst[5]=17 cells (5 PI)
8476 04:45:07.855900 u2DelayCellOfst[6]=17 cells (5 PI)
8477 04:45:07.859218 u2DelayCellOfst[7]=3 cells (1 PI)
8478 04:45:07.861920 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8479 04:45:07.865858 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8480 04:45:07.869226 == TX Byte 1 ==
8481 04:45:07.872628 u2DelayCellOfst[8]=0 cells (0 PI)
8482 04:45:07.875580 u2DelayCellOfst[9]=3 cells (1 PI)
8483 04:45:07.876074 u2DelayCellOfst[10]=6 cells (2 PI)
8484 04:45:07.878511 u2DelayCellOfst[11]=3 cells (1 PI)
8485 04:45:07.882107 u2DelayCellOfst[12]=13 cells (4 PI)
8486 04:45:07.885305 u2DelayCellOfst[13]=20 cells (6 PI)
8487 04:45:07.888658 u2DelayCellOfst[14]=20 cells (6 PI)
8488 04:45:07.891835 u2DelayCellOfst[15]=17 cells (5 PI)
8489 04:45:07.898867 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8490 04:45:07.901913 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8491 04:45:07.902519 DramC Write-DBI on
8492 04:45:07.902894 ==
8493 04:45:07.905237 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 04:45:07.911801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 04:45:07.912383 ==
8496 04:45:07.912757
8497 04:45:07.913101
8498 04:45:07.913427 TX Vref Scan disable
8499 04:45:07.916372 == TX Byte 0 ==
8500 04:45:07.919370 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8501 04:45:07.922420 == TX Byte 1 ==
8502 04:45:07.925988 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8503 04:45:07.929176 DramC Write-DBI off
8504 04:45:07.929654
8505 04:45:07.930060 [DATLAT]
8506 04:45:07.930417 Freq=1600, CH1 RK0
8507 04:45:07.930753
8508 04:45:07.932589 DATLAT Default: 0xf
8509 04:45:07.933058 0, 0xFFFF, sum = 0
8510 04:45:07.935833 1, 0xFFFF, sum = 0
8511 04:45:07.936318 2, 0xFFFF, sum = 0
8512 04:45:07.939070 3, 0xFFFF, sum = 0
8513 04:45:07.942361 4, 0xFFFF, sum = 0
8514 04:45:07.942839 5, 0xFFFF, sum = 0
8515 04:45:07.945736 6, 0xFFFF, sum = 0
8516 04:45:07.946374 7, 0xFFFF, sum = 0
8517 04:45:07.949173 8, 0xFFFF, sum = 0
8518 04:45:07.949756 9, 0xFFFF, sum = 0
8519 04:45:07.952638 10, 0xFFFF, sum = 0
8520 04:45:07.953256 11, 0xFFFF, sum = 0
8521 04:45:07.955681 12, 0xFFFF, sum = 0
8522 04:45:07.956269 13, 0xFFFF, sum = 0
8523 04:45:07.959021 14, 0x0, sum = 1
8524 04:45:07.959609 15, 0x0, sum = 2
8525 04:45:07.962754 16, 0x0, sum = 3
8526 04:45:07.963344 17, 0x0, sum = 4
8527 04:45:07.965841 best_step = 15
8528 04:45:07.966447
8529 04:45:07.966823 ==
8530 04:45:07.969304 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 04:45:07.972881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 04:45:07.973462 ==
8533 04:45:07.973842 RX Vref Scan: 1
8534 04:45:07.975976
8535 04:45:07.976445 Set Vref Range= 24 -> 127
8536 04:45:07.976815
8537 04:45:07.979153 RX Vref 24 -> 127, step: 1
8538 04:45:07.979725
8539 04:45:07.982295 RX Delay 19 -> 252, step: 4
8540 04:45:07.982767
8541 04:45:07.986096 Set Vref, RX VrefLevel [Byte0]: 24
8542 04:45:07.989117 [Byte1]: 24
8543 04:45:07.989863
8544 04:45:07.992219 Set Vref, RX VrefLevel [Byte0]: 25
8545 04:45:07.995913 [Byte1]: 25
8546 04:45:07.996483
8547 04:45:07.998780 Set Vref, RX VrefLevel [Byte0]: 26
8548 04:45:08.002341 [Byte1]: 26
8549 04:45:08.006140
8550 04:45:08.006701 Set Vref, RX VrefLevel [Byte0]: 27
8551 04:45:08.009629 [Byte1]: 27
8552 04:45:08.014035
8553 04:45:08.014591 Set Vref, RX VrefLevel [Byte0]: 28
8554 04:45:08.016949 [Byte1]: 28
8555 04:45:08.021241
8556 04:45:08.021782 Set Vref, RX VrefLevel [Byte0]: 29
8557 04:45:08.024789 [Byte1]: 29
8558 04:45:08.029013
8559 04:45:08.029786 Set Vref, RX VrefLevel [Byte0]: 30
8560 04:45:08.032020 [Byte1]: 30
8561 04:45:08.036283
8562 04:45:08.037010 Set Vref, RX VrefLevel [Byte0]: 31
8563 04:45:08.039708 [Byte1]: 31
8564 04:45:08.043739
8565 04:45:08.044364 Set Vref, RX VrefLevel [Byte0]: 32
8566 04:45:08.047152 [Byte1]: 32
8567 04:45:08.051549
8568 04:45:08.052013 Set Vref, RX VrefLevel [Byte0]: 33
8569 04:45:08.054978 [Byte1]: 33
8570 04:45:08.059335
8571 04:45:08.059912 Set Vref, RX VrefLevel [Byte0]: 34
8572 04:45:08.062533 [Byte1]: 34
8573 04:45:08.066630
8574 04:45:08.067193 Set Vref, RX VrefLevel [Byte0]: 35
8575 04:45:08.070184 [Byte1]: 35
8576 04:45:08.074391
8577 04:45:08.074958 Set Vref, RX VrefLevel [Byte0]: 36
8578 04:45:08.077801 [Byte1]: 36
8579 04:45:08.081839
8580 04:45:08.082448 Set Vref, RX VrefLevel [Byte0]: 37
8581 04:45:08.085136 [Byte1]: 37
8582 04:45:08.089473
8583 04:45:08.090068 Set Vref, RX VrefLevel [Byte0]: 38
8584 04:45:08.092810 [Byte1]: 38
8585 04:45:08.097193
8586 04:45:08.097757 Set Vref, RX VrefLevel [Byte0]: 39
8587 04:45:08.100372 [Byte1]: 39
8588 04:45:08.104785
8589 04:45:08.105351 Set Vref, RX VrefLevel [Byte0]: 40
8590 04:45:08.107793 [Byte1]: 40
8591 04:45:08.112495
8592 04:45:08.113060 Set Vref, RX VrefLevel [Byte0]: 41
8593 04:45:08.115372 [Byte1]: 41
8594 04:45:08.119778
8595 04:45:08.123179 Set Vref, RX VrefLevel [Byte0]: 42
8596 04:45:08.123746 [Byte1]: 42
8597 04:45:08.127158
8598 04:45:08.127721 Set Vref, RX VrefLevel [Byte0]: 43
8599 04:45:08.130756 [Byte1]: 43
8600 04:45:08.134951
8601 04:45:08.135507 Set Vref, RX VrefLevel [Byte0]: 44
8602 04:45:08.137967 [Byte1]: 44
8603 04:45:08.142294
8604 04:45:08.142766 Set Vref, RX VrefLevel [Byte0]: 45
8605 04:45:08.145618 [Byte1]: 45
8606 04:45:08.150107
8607 04:45:08.150679 Set Vref, RX VrefLevel [Byte0]: 46
8608 04:45:08.153824 [Byte1]: 46
8609 04:45:08.157806
8610 04:45:08.158424 Set Vref, RX VrefLevel [Byte0]: 47
8611 04:45:08.160924 [Byte1]: 47
8612 04:45:08.165103
8613 04:45:08.165675 Set Vref, RX VrefLevel [Byte0]: 48
8614 04:45:08.168643 [Byte1]: 48
8615 04:45:08.172982
8616 04:45:08.173547 Set Vref, RX VrefLevel [Byte0]: 49
8617 04:45:08.176164 [Byte1]: 49
8618 04:45:08.180299
8619 04:45:08.180866 Set Vref, RX VrefLevel [Byte0]: 50
8620 04:45:08.183884 [Byte1]: 50
8621 04:45:08.187910
8622 04:45:08.188500 Set Vref, RX VrefLevel [Byte0]: 51
8623 04:45:08.191098 [Byte1]: 51
8624 04:45:08.195261
8625 04:45:08.195808 Set Vref, RX VrefLevel [Byte0]: 52
8626 04:45:08.198537 [Byte1]: 52
8627 04:45:08.203291
8628 04:45:08.203854 Set Vref, RX VrefLevel [Byte0]: 53
8629 04:45:08.206098 [Byte1]: 53
8630 04:45:08.210847
8631 04:45:08.211411 Set Vref, RX VrefLevel [Byte0]: 54
8632 04:45:08.213823 [Byte1]: 54
8633 04:45:08.218377
8634 04:45:08.218949 Set Vref, RX VrefLevel [Byte0]: 55
8635 04:45:08.221645 [Byte1]: 55
8636 04:45:08.225521
8637 04:45:08.226035 Set Vref, RX VrefLevel [Byte0]: 56
8638 04:45:08.228929 [Byte1]: 56
8639 04:45:08.233603
8640 04:45:08.234212 Set Vref, RX VrefLevel [Byte0]: 57
8641 04:45:08.236942 [Byte1]: 57
8642 04:45:08.240750
8643 04:45:08.241213 Set Vref, RX VrefLevel [Byte0]: 58
8644 04:45:08.244168 [Byte1]: 58
8645 04:45:08.248721
8646 04:45:08.249285 Set Vref, RX VrefLevel [Byte0]: 59
8647 04:45:08.251853 [Byte1]: 59
8648 04:45:08.256190
8649 04:45:08.256806 Set Vref, RX VrefLevel [Byte0]: 60
8650 04:45:08.259312 [Byte1]: 60
8651 04:45:08.264143
8652 04:45:08.264705 Set Vref, RX VrefLevel [Byte0]: 61
8653 04:45:08.266652 [Byte1]: 61
8654 04:45:08.271110
8655 04:45:08.271674 Set Vref, RX VrefLevel [Byte0]: 62
8656 04:45:08.274744 [Byte1]: 62
8657 04:45:08.279044
8658 04:45:08.279608 Set Vref, RX VrefLevel [Byte0]: 63
8659 04:45:08.282003 [Byte1]: 63
8660 04:45:08.286603
8661 04:45:08.287172 Set Vref, RX VrefLevel [Byte0]: 64
8662 04:45:08.290181 [Byte1]: 64
8663 04:45:08.294213
8664 04:45:08.294806 Set Vref, RX VrefLevel [Byte0]: 65
8665 04:45:08.297458 [Byte1]: 65
8666 04:45:08.301608
8667 04:45:08.302214 Set Vref, RX VrefLevel [Byte0]: 66
8668 04:45:08.304717 [Byte1]: 66
8669 04:45:08.308822
8670 04:45:08.309335 Set Vref, RX VrefLevel [Byte0]: 67
8671 04:45:08.312355 [Byte1]: 67
8672 04:45:08.316780
8673 04:45:08.317346 Set Vref, RX VrefLevel [Byte0]: 68
8674 04:45:08.320351 [Byte1]: 68
8675 04:45:08.323898
8676 04:45:08.324362 Set Vref, RX VrefLevel [Byte0]: 69
8677 04:45:08.327180 [Byte1]: 69
8678 04:45:08.331690
8679 04:45:08.332194 Set Vref, RX VrefLevel [Byte0]: 70
8680 04:45:08.334855 [Byte1]: 70
8681 04:45:08.339302
8682 04:45:08.339869 Set Vref, RX VrefLevel [Byte0]: 71
8683 04:45:08.342503 [Byte1]: 71
8684 04:45:08.346882
8685 04:45:08.347343 Set Vref, RX VrefLevel [Byte0]: 72
8686 04:45:08.349915 [Byte1]: 72
8687 04:45:08.354421
8688 04:45:08.355010 Set Vref, RX VrefLevel [Byte0]: 73
8689 04:45:08.357471 [Byte1]: 73
8690 04:45:08.362300
8691 04:45:08.362866 Set Vref, RX VrefLevel [Byte0]: 74
8692 04:45:08.365247 [Byte1]: 74
8693 04:45:08.369672
8694 04:45:08.370320 Set Vref, RX VrefLevel [Byte0]: 75
8695 04:45:08.372952 [Byte1]: 75
8696 04:45:08.376958
8697 04:45:08.377430 Final RX Vref Byte 0 = 58 to rank0
8698 04:45:08.380461 Final RX Vref Byte 1 = 62 to rank0
8699 04:45:08.383587 Final RX Vref Byte 0 = 58 to rank1
8700 04:45:08.387013 Final RX Vref Byte 1 = 62 to rank1==
8701 04:45:08.390756 Dram Type= 6, Freq= 0, CH_1, rank 0
8702 04:45:08.397232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8703 04:45:08.397830 ==
8704 04:45:08.398266 DQS Delay:
8705 04:45:08.398623 DQS0 = 0, DQS1 = 0
8706 04:45:08.400374 DQM Delay:
8707 04:45:08.400843 DQM0 = 133, DQM1 = 129
8708 04:45:08.403839 DQ Delay:
8709 04:45:08.407141 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8710 04:45:08.410365 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
8711 04:45:08.413471 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8712 04:45:08.417041 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8713 04:45:08.417604
8714 04:45:08.418027
8715 04:45:08.418391
8716 04:45:08.420409 [DramC_TX_OE_Calibration] TA2
8717 04:45:08.423738 Original DQ_B0 (3 6) =30, OEN = 27
8718 04:45:08.427127 Original DQ_B1 (3 6) =30, OEN = 27
8719 04:45:08.430488 24, 0x0, End_B0=24 End_B1=24
8720 04:45:08.430976 25, 0x0, End_B0=25 End_B1=25
8721 04:45:08.433912 26, 0x0, End_B0=26 End_B1=26
8722 04:45:08.437000 27, 0x0, End_B0=27 End_B1=27
8723 04:45:08.440489 28, 0x0, End_B0=28 End_B1=28
8724 04:45:08.441020 29, 0x0, End_B0=29 End_B1=29
8725 04:45:08.443982 30, 0x0, End_B0=30 End_B1=30
8726 04:45:08.446945 31, 0x4141, End_B0=30 End_B1=30
8727 04:45:08.450975 Byte0 end_step=30 best_step=27
8728 04:45:08.453810 Byte1 end_step=30 best_step=27
8729 04:45:08.457234 Byte0 TX OE(2T, 0.5T) = (3, 3)
8730 04:45:08.457703 Byte1 TX OE(2T, 0.5T) = (3, 3)
8731 04:45:08.458151
8732 04:45:08.460600
8733 04:45:08.467516 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8734 04:45:08.470109 CH1 RK0: MR19=303, MR18=1826
8735 04:45:08.476960 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8736 04:45:08.477548
8737 04:45:08.480348 ----->DramcWriteLeveling(PI) begin...
8738 04:45:08.480822 ==
8739 04:45:08.483759 Dram Type= 6, Freq= 0, CH_1, rank 1
8740 04:45:08.487207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 04:45:08.487679 ==
8742 04:45:08.490482 Write leveling (Byte 0): 23 => 23
8743 04:45:08.493838 Write leveling (Byte 1): 29 => 29
8744 04:45:08.497005 DramcWriteLeveling(PI) end<-----
8745 04:45:08.497573
8746 04:45:08.497976 ==
8747 04:45:08.500440 Dram Type= 6, Freq= 0, CH_1, rank 1
8748 04:45:08.503498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 04:45:08.504067 ==
8750 04:45:08.506811 [Gating] SW mode calibration
8751 04:45:08.513588 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8752 04:45:08.520177 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8753 04:45:08.523560 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 04:45:08.526837 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 04:45:08.533998 1 4 8 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8756 04:45:08.536954 1 4 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
8757 04:45:08.540148 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 04:45:08.547295 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 04:45:08.550098 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 04:45:08.553764 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 04:45:08.560585 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 04:45:08.563441 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8763 04:45:08.567196 1 5 8 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 0)
8764 04:45:08.573518 1 5 12 | B1->B0 | 2323 2c2c | 0 0 | (1 0) (0 1)
8765 04:45:08.576888 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 04:45:08.580235 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 04:45:08.586958 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 04:45:08.590426 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 04:45:08.593554 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 04:45:08.597250 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 04:45:08.603723 1 6 8 | B1->B0 | 4242 2323 | 0 0 | (0 0) (0 0)
8772 04:45:08.606986 1 6 12 | B1->B0 | 4646 3636 | 0 0 | (0 0) (1 1)
8773 04:45:08.609998 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 04:45:08.616582 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 04:45:08.620108 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 04:45:08.623392 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 04:45:08.629972 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 04:45:08.633413 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8779 04:45:08.637083 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8780 04:45:08.643446 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8781 04:45:08.646376 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 04:45:08.650104 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 04:45:08.656526 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 04:45:08.659966 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 04:45:08.663373 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 04:45:08.669724 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 04:45:08.672907 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 04:45:08.676339 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 04:45:08.683148 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 04:45:08.686484 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 04:45:08.689887 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 04:45:08.696566 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 04:45:08.700107 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 04:45:08.703037 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 04:45:08.709865 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8796 04:45:08.713289 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8797 04:45:08.716177 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 04:45:08.720376 Total UI for P1: 0, mck2ui 16
8799 04:45:08.723075 best dqsien dly found for B0: ( 1, 9, 10)
8800 04:45:08.726425 Total UI for P1: 0, mck2ui 16
8801 04:45:08.729607 best dqsien dly found for B1: ( 1, 9, 10)
8802 04:45:08.732761 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8803 04:45:08.736149 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8804 04:45:08.736622
8805 04:45:08.739473 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8806 04:45:08.745997 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8807 04:45:08.746471 [Gating] SW calibration Done
8808 04:45:08.746847 ==
8809 04:45:08.749429 Dram Type= 6, Freq= 0, CH_1, rank 1
8810 04:45:08.756244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 04:45:08.756819 ==
8812 04:45:08.757200 RX Vref Scan: 0
8813 04:45:08.757546
8814 04:45:08.759707 RX Vref 0 -> 0, step: 1
8815 04:45:08.760286
8816 04:45:08.763128 RX Delay 0 -> 252, step: 8
8817 04:45:08.766262 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8818 04:45:08.769509 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8819 04:45:08.772820 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8820 04:45:08.779142 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8821 04:45:08.782533 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8822 04:45:08.785983 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8823 04:45:08.789135 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8824 04:45:08.793129 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8825 04:45:08.795730 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8826 04:45:08.803028 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8827 04:45:08.806161 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8828 04:45:08.809238 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8829 04:45:08.813011 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8830 04:45:08.819319 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8831 04:45:08.822674 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8832 04:45:08.826159 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8833 04:45:08.826775 ==
8834 04:45:08.829356 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 04:45:08.832351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 04:45:08.832878 ==
8837 04:45:08.835775 DQS Delay:
8838 04:45:08.836249 DQS0 = 0, DQS1 = 0
8839 04:45:08.839073 DQM Delay:
8840 04:45:08.839542 DQM0 = 137, DQM1 = 132
8841 04:45:08.839920 DQ Delay:
8842 04:45:08.842340 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8843 04:45:08.846276 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8844 04:45:08.852853 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8845 04:45:08.855885 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8846 04:45:08.856361
8847 04:45:08.856731
8848 04:45:08.857073 ==
8849 04:45:08.859241 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 04:45:08.862829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 04:45:08.863306 ==
8852 04:45:08.863681
8853 04:45:08.864027
8854 04:45:08.866044 TX Vref Scan disable
8855 04:45:08.869494 == TX Byte 0 ==
8856 04:45:08.872733 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8857 04:45:08.876049 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8858 04:45:08.879022 == TX Byte 1 ==
8859 04:45:08.882644 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8860 04:45:08.886007 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8861 04:45:08.886585 ==
8862 04:45:08.889220 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 04:45:08.892256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 04:45:08.895934 ==
8865 04:45:08.908547
8866 04:45:08.911536 TX Vref early break, caculate TX vref
8867 04:45:08.914804 TX Vref=16, minBit 9, minWin=21, winSum=374
8868 04:45:08.918123 TX Vref=18, minBit 10, minWin=22, winSum=385
8869 04:45:08.921548 TX Vref=20, minBit 8, minWin=23, winSum=395
8870 04:45:08.924975 TX Vref=22, minBit 9, minWin=23, winSum=400
8871 04:45:08.927718 TX Vref=24, minBit 12, minWin=24, winSum=413
8872 04:45:08.934279 TX Vref=26, minBit 11, minWin=24, winSum=417
8873 04:45:08.937988 TX Vref=28, minBit 8, minWin=24, winSum=418
8874 04:45:08.941126 TX Vref=30, minBit 8, minWin=24, winSum=408
8875 04:45:08.944130 TX Vref=32, minBit 8, minWin=24, winSum=403
8876 04:45:08.947531 TX Vref=34, minBit 8, minWin=24, winSum=399
8877 04:45:08.954360 TX Vref=36, minBit 8, minWin=23, winSum=390
8878 04:45:08.957877 [TxChooseVref] Worse bit 8, Min win 24, Win sum 418, Final Vref 28
8879 04:45:08.958500
8880 04:45:08.960891 Final TX Range 0 Vref 28
8881 04:45:08.961462
8882 04:45:08.961843 ==
8883 04:45:08.964274 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 04:45:08.967745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 04:45:08.970835 ==
8886 04:45:08.971409
8887 04:45:08.971786
8888 04:45:08.972133 TX Vref Scan disable
8889 04:45:08.978129 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8890 04:45:08.978701 == TX Byte 0 ==
8891 04:45:08.980765 u2DelayCellOfst[0]=13 cells (4 PI)
8892 04:45:08.984455 u2DelayCellOfst[1]=10 cells (3 PI)
8893 04:45:08.987951 u2DelayCellOfst[2]=0 cells (0 PI)
8894 04:45:08.991276 u2DelayCellOfst[3]=3 cells (1 PI)
8895 04:45:08.994488 u2DelayCellOfst[4]=6 cells (2 PI)
8896 04:45:08.997675 u2DelayCellOfst[5]=17 cells (5 PI)
8897 04:45:09.001178 u2DelayCellOfst[6]=17 cells (5 PI)
8898 04:45:09.004361 u2DelayCellOfst[7]=6 cells (2 PI)
8899 04:45:09.007296 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8900 04:45:09.011280 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8901 04:45:09.014355 == TX Byte 1 ==
8902 04:45:09.017766 u2DelayCellOfst[8]=0 cells (0 PI)
8903 04:45:09.021220 u2DelayCellOfst[9]=3 cells (1 PI)
8904 04:45:09.021801 u2DelayCellOfst[10]=10 cells (3 PI)
8905 04:45:09.024566 u2DelayCellOfst[11]=3 cells (1 PI)
8906 04:45:09.028036 u2DelayCellOfst[12]=13 cells (4 PI)
8907 04:45:09.030737 u2DelayCellOfst[13]=17 cells (5 PI)
8908 04:45:09.034219 u2DelayCellOfst[14]=17 cells (5 PI)
8909 04:45:09.037642 u2DelayCellOfst[15]=17 cells (5 PI)
8910 04:45:09.043927 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8911 04:45:09.047694 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8912 04:45:09.048275 DramC Write-DBI on
8913 04:45:09.048779 ==
8914 04:45:09.050768 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 04:45:09.057100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 04:45:09.057783 ==
8917 04:45:09.058310
8918 04:45:09.058711
8919 04:45:09.059058 TX Vref Scan disable
8920 04:45:09.061611 == TX Byte 0 ==
8921 04:45:09.065192 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8922 04:45:09.068046 == TX Byte 1 ==
8923 04:45:09.071486 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8924 04:45:09.074668 DramC Write-DBI off
8925 04:45:09.075167
8926 04:45:09.075794 [DATLAT]
8927 04:45:09.076431 Freq=1600, CH1 RK1
8928 04:45:09.077003
8929 04:45:09.077877 DATLAT Default: 0xf
8930 04:45:09.078459 0, 0xFFFF, sum = 0
8931 04:45:09.081321 1, 0xFFFF, sum = 0
8932 04:45:09.084810 2, 0xFFFF, sum = 0
8933 04:45:09.085324 3, 0xFFFF, sum = 0
8934 04:45:09.088115 4, 0xFFFF, sum = 0
8935 04:45:09.088690 5, 0xFFFF, sum = 0
8936 04:45:09.091744 6, 0xFFFF, sum = 0
8937 04:45:09.092316 7, 0xFFFF, sum = 0
8938 04:45:09.094849 8, 0xFFFF, sum = 0
8939 04:45:09.095424 9, 0xFFFF, sum = 0
8940 04:45:09.098311 10, 0xFFFF, sum = 0
8941 04:45:09.098887 11, 0xFFFF, sum = 0
8942 04:45:09.101510 12, 0xFFFF, sum = 0
8943 04:45:09.102135 13, 0xFFFF, sum = 0
8944 04:45:09.105076 14, 0x0, sum = 1
8945 04:45:09.105649 15, 0x0, sum = 2
8946 04:45:09.108245 16, 0x0, sum = 3
8947 04:45:09.108724 17, 0x0, sum = 4
8948 04:45:09.112096 best_step = 15
8949 04:45:09.112663
8950 04:45:09.113042 ==
8951 04:45:09.114562 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 04:45:09.118432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 04:45:09.119023 ==
8954 04:45:09.119398 RX Vref Scan: 0
8955 04:45:09.119749
8956 04:45:09.121686 RX Vref 0 -> 0, step: 1
8957 04:45:09.122362
8958 04:45:09.124886 RX Delay 19 -> 252, step: 4
8959 04:45:09.128284 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8960 04:45:09.134707 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8961 04:45:09.138428 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8962 04:45:09.141471 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8963 04:45:09.144680 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8964 04:45:09.147764 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8965 04:45:09.151326 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8966 04:45:09.157975 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8967 04:45:09.161491 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8968 04:45:09.164966 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8969 04:45:09.167935 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8970 04:45:09.171312 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8971 04:45:09.177757 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8972 04:45:09.181212 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8973 04:45:09.184694 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8974 04:45:09.187797 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8975 04:45:09.188274 ==
8976 04:45:09.191332 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 04:45:09.197823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 04:45:09.198457 ==
8979 04:45:09.198837 DQS Delay:
8980 04:45:09.201319 DQS0 = 0, DQS1 = 0
8981 04:45:09.201887 DQM Delay:
8982 04:45:09.202319 DQM0 = 133, DQM1 = 130
8983 04:45:09.204469 DQ Delay:
8984 04:45:09.207735 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8985 04:45:09.211217 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
8986 04:45:09.214671 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
8987 04:45:09.217758 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8988 04:45:09.218371
8989 04:45:09.218852
8990 04:45:09.219370
8991 04:45:09.221354 [DramC_TX_OE_Calibration] TA2
8992 04:45:09.224229 Original DQ_B0 (3 6) =30, OEN = 27
8993 04:45:09.227760 Original DQ_B1 (3 6) =30, OEN = 27
8994 04:45:09.231242 24, 0x0, End_B0=24 End_B1=24
8995 04:45:09.231719 25, 0x0, End_B0=25 End_B1=25
8996 04:45:09.234206 26, 0x0, End_B0=26 End_B1=26
8997 04:45:09.237844 27, 0x0, End_B0=27 End_B1=27
8998 04:45:09.241259 28, 0x0, End_B0=28 End_B1=28
8999 04:45:09.244585 29, 0x0, End_B0=29 End_B1=29
9000 04:45:09.245066 30, 0x0, End_B0=30 End_B1=30
9001 04:45:09.247746 31, 0x4141, End_B0=30 End_B1=30
9002 04:45:09.250856 Byte0 end_step=30 best_step=27
9003 04:45:09.254615 Byte1 end_step=30 best_step=27
9004 04:45:09.257884 Byte0 TX OE(2T, 0.5T) = (3, 3)
9005 04:45:09.260852 Byte1 TX OE(2T, 0.5T) = (3, 3)
9006 04:45:09.261440
9007 04:45:09.262010
9008 04:45:09.267755 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9009 04:45:09.271122 CH1 RK1: MR19=303, MR18=1E09
9010 04:45:09.277616 CH1_RK1: MR19=0x303, MR18=0x1E09, DQSOSC=394, MR23=63, INC=23, DEC=15
9011 04:45:09.281065 [RxdqsGatingPostProcess] freq 1600
9012 04:45:09.284144 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9013 04:45:09.287936 best DQS0 dly(2T, 0.5T) = (1, 1)
9014 04:45:09.291024 best DQS1 dly(2T, 0.5T) = (1, 1)
9015 04:45:09.294544 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9016 04:45:09.297672 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9017 04:45:09.301010 best DQS0 dly(2T, 0.5T) = (1, 1)
9018 04:45:09.304305 best DQS1 dly(2T, 0.5T) = (1, 1)
9019 04:45:09.307026 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9020 04:45:09.310908 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9021 04:45:09.314069 Pre-setting of DQS Precalculation
9022 04:45:09.317143 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9023 04:45:09.323823 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9024 04:45:09.333764 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9025 04:45:09.334509
9026 04:45:09.334904
9027 04:45:09.335252 [Calibration Summary] 3200 Mbps
9028 04:45:09.337418 CH 0, Rank 0
9029 04:45:09.338148 SW Impedance : PASS
9030 04:45:09.340576 DUTY Scan : NO K
9031 04:45:09.343530 ZQ Calibration : PASS
9032 04:45:09.344033 Jitter Meter : NO K
9033 04:45:09.347140 CBT Training : PASS
9034 04:45:09.350285 Write leveling : PASS
9035 04:45:09.350879 RX DQS gating : PASS
9036 04:45:09.353589 RX DQ/DQS(RDDQC) : PASS
9037 04:45:09.356852 TX DQ/DQS : PASS
9038 04:45:09.357354 RX DATLAT : PASS
9039 04:45:09.360184 RX DQ/DQS(Engine): PASS
9040 04:45:09.363880 TX OE : PASS
9041 04:45:09.364472 All Pass.
9042 04:45:09.364845
9043 04:45:09.365184 CH 0, Rank 1
9044 04:45:09.366767 SW Impedance : PASS
9045 04:45:09.370231 DUTY Scan : NO K
9046 04:45:09.370730 ZQ Calibration : PASS
9047 04:45:09.373428 Jitter Meter : NO K
9048 04:45:09.376850 CBT Training : PASS
9049 04:45:09.377437 Write leveling : PASS
9050 04:45:09.380138 RX DQS gating : PASS
9051 04:45:09.383823 RX DQ/DQS(RDDQC) : PASS
9052 04:45:09.384415 TX DQ/DQS : PASS
9053 04:45:09.386650 RX DATLAT : PASS
9054 04:45:09.387150 RX DQ/DQS(Engine): PASS
9055 04:45:09.390095 TX OE : PASS
9056 04:45:09.390561 All Pass.
9057 04:45:09.390926
9058 04:45:09.393699 CH 1, Rank 0
9059 04:45:09.394356 SW Impedance : PASS
9060 04:45:09.396809 DUTY Scan : NO K
9061 04:45:09.400210 ZQ Calibration : PASS
9062 04:45:09.400673 Jitter Meter : NO K
9063 04:45:09.403194 CBT Training : PASS
9064 04:45:09.406804 Write leveling : PASS
9065 04:45:09.407389 RX DQS gating : PASS
9066 04:45:09.409883 RX DQ/DQS(RDDQC) : PASS
9067 04:45:09.413424 TX DQ/DQS : PASS
9068 04:45:09.414018 RX DATLAT : PASS
9069 04:45:09.416526 RX DQ/DQS(Engine): PASS
9070 04:45:09.420130 TX OE : PASS
9071 04:45:09.420696 All Pass.
9072 04:45:09.421119
9073 04:45:09.421461 CH 1, Rank 1
9074 04:45:09.423693 SW Impedance : PASS
9075 04:45:09.426909 DUTY Scan : NO K
9076 04:45:09.427374 ZQ Calibration : PASS
9077 04:45:09.430150 Jitter Meter : NO K
9078 04:45:09.433419 CBT Training : PASS
9079 04:45:09.433935 Write leveling : PASS
9080 04:45:09.437209 RX DQS gating : PASS
9081 04:45:09.437779 RX DQ/DQS(RDDQC) : PASS
9082 04:45:09.439839 TX DQ/DQS : PASS
9083 04:45:09.443476 RX DATLAT : PASS
9084 04:45:09.444043 RX DQ/DQS(Engine): PASS
9085 04:45:09.446892 TX OE : PASS
9086 04:45:09.447507 All Pass.
9087 04:45:09.447876
9088 04:45:09.449808 DramC Write-DBI on
9089 04:45:09.453327 PER_BANK_REFRESH: Hybrid Mode
9090 04:45:09.453896 TX_TRACKING: ON
9091 04:45:09.463564 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9092 04:45:09.470309 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9093 04:45:09.476539 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9094 04:45:09.480190 [FAST_K] Save calibration result to emmc
9095 04:45:09.483722 sync common calibartion params.
9096 04:45:09.486840 sync cbt_mode0:1, 1:1
9097 04:45:09.490221 dram_init: ddr_geometry: 2
9098 04:45:09.490793 dram_init: ddr_geometry: 2
9099 04:45:09.493522 dram_init: ddr_geometry: 2
9100 04:45:09.497266 0:dram_rank_size:100000000
9101 04:45:09.500506 1:dram_rank_size:100000000
9102 04:45:09.503473 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9103 04:45:09.506899 DFS_SHUFFLE_HW_MODE: ON
9104 04:45:09.510099 dramc_set_vcore_voltage set vcore to 725000
9105 04:45:09.513110 Read voltage for 1600, 0
9106 04:45:09.513685 Vio18 = 0
9107 04:45:09.514096 Vcore = 725000
9108 04:45:09.517130 Vdram = 0
9109 04:45:09.517705 Vddq = 0
9110 04:45:09.518123 Vmddr = 0
9111 04:45:09.519907 switch to 3200 Mbps bootup
9112 04:45:09.523195 [DramcRunTimeConfig]
9113 04:45:09.523781 PHYPLL
9114 04:45:09.524185 DPM_CONTROL_AFTERK: ON
9115 04:45:09.526451 PER_BANK_REFRESH: ON
9116 04:45:09.529747 REFRESH_OVERHEAD_REDUCTION: ON
9117 04:45:09.530261 CMD_PICG_NEW_MODE: OFF
9118 04:45:09.533096 XRTWTW_NEW_MODE: ON
9119 04:45:09.536761 XRTRTR_NEW_MODE: ON
9120 04:45:09.537374 TX_TRACKING: ON
9121 04:45:09.537756 RDSEL_TRACKING: OFF
9122 04:45:09.539642 DQS Precalculation for DVFS: ON
9123 04:45:09.543196 RX_TRACKING: OFF
9124 04:45:09.543774 HW_GATING DBG: ON
9125 04:45:09.546715 ZQCS_ENABLE_LP4: ON
9126 04:45:09.547470 RX_PICG_NEW_MODE: ON
9127 04:45:09.549719 TX_PICG_NEW_MODE: ON
9128 04:45:09.553264 ENABLE_RX_DCM_DPHY: ON
9129 04:45:09.556557 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9130 04:45:09.557134 DUMMY_READ_FOR_TRACKING: OFF
9131 04:45:09.559784 !!! SPM_CONTROL_AFTERK: OFF
9132 04:45:09.563154 !!! SPM could not control APHY
9133 04:45:09.566331 IMPEDANCE_TRACKING: ON
9134 04:45:09.566907 TEMP_SENSOR: ON
9135 04:45:09.569609 HW_SAVE_FOR_SR: OFF
9136 04:45:09.570119 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9137 04:45:09.576338 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9138 04:45:09.576922 Read ODT Tracking: ON
9139 04:45:09.579641 Refresh Rate DeBounce: ON
9140 04:45:09.580124 DFS_NO_QUEUE_FLUSH: ON
9141 04:45:09.583018 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9142 04:45:09.586866 ENABLE_DFS_RUNTIME_MRW: OFF
9143 04:45:09.589837 DDR_RESERVE_NEW_MODE: ON
9144 04:45:09.590451 MR_CBT_SWITCH_FREQ: ON
9145 04:45:09.593150 =========================
9146 04:45:09.612445 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9147 04:45:09.615570 dram_init: ddr_geometry: 2
9148 04:45:09.633935 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9149 04:45:09.637525 dram_init: dram init end (result: 0)
9150 04:45:09.643720 DRAM-K: Full calibration passed in 24501 msecs
9151 04:45:09.647407 MRC: failed to locate region type 0.
9152 04:45:09.648129 DRAM rank0 size:0x100000000,
9153 04:45:09.650491 DRAM rank1 size=0x100000000
9154 04:45:09.660784 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9155 04:45:09.666990 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9156 04:45:09.673638 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9157 04:45:09.680116 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9158 04:45:09.683429 DRAM rank0 size:0x100000000,
9159 04:45:09.687141 DRAM rank1 size=0x100000000
9160 04:45:09.687713 CBMEM:
9161 04:45:09.690545 IMD: root @ 0xfffff000 254 entries.
9162 04:45:09.693519 IMD: root @ 0xffffec00 62 entries.
9163 04:45:09.697078 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9164 04:45:09.703435 WARNING: RO_VPD is uninitialized or empty.
9165 04:45:09.706911 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9166 04:45:09.714490 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9167 04:45:09.726832 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9168 04:45:09.738115 BS: romstage times (exec / console): total (unknown) / 24000 ms
9169 04:45:09.738685
9170 04:45:09.739056
9171 04:45:09.748055 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9172 04:45:09.751470 ARM64: Exception handlers installed.
9173 04:45:09.754482 ARM64: Testing exception
9174 04:45:09.758143 ARM64: Done test exception
9175 04:45:09.758715 Enumerating buses...
9176 04:45:09.761345 Show all devs... Before device enumeration.
9177 04:45:09.765063 Root Device: enabled 1
9178 04:45:09.768384 CPU_CLUSTER: 0: enabled 1
9179 04:45:09.768958 CPU: 00: enabled 1
9180 04:45:09.771026 Compare with tree...
9181 04:45:09.771496 Root Device: enabled 1
9182 04:45:09.774940 CPU_CLUSTER: 0: enabled 1
9183 04:45:09.777714 CPU: 00: enabled 1
9184 04:45:09.778235 Root Device scanning...
9185 04:45:09.781330 scan_static_bus for Root Device
9186 04:45:09.784384 CPU_CLUSTER: 0 enabled
9187 04:45:09.787992 scan_static_bus for Root Device done
9188 04:45:09.791144 scan_bus: bus Root Device finished in 8 msecs
9189 04:45:09.791714 done
9190 04:45:09.798275 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9191 04:45:09.801406 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9192 04:45:09.808065 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9193 04:45:09.811394 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9194 04:45:09.814817 Allocating resources...
9195 04:45:09.817815 Reading resources...
9196 04:45:09.821208 Root Device read_resources bus 0 link: 0
9197 04:45:09.821799 DRAM rank0 size:0x100000000,
9198 04:45:09.824322 DRAM rank1 size=0x100000000
9199 04:45:09.827564 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9200 04:45:09.831144 CPU: 00 missing read_resources
9201 04:45:09.834321 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9202 04:45:09.840988 Root Device read_resources bus 0 link: 0 done
9203 04:45:09.841552 Done reading resources.
9204 04:45:09.848224 Show resources in subtree (Root Device)...After reading.
9205 04:45:09.850810 Root Device child on link 0 CPU_CLUSTER: 0
9206 04:45:09.854206 CPU_CLUSTER: 0 child on link 0 CPU: 00
9207 04:45:09.864482 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9208 04:45:09.865054 CPU: 00
9209 04:45:09.867794 Root Device assign_resources, bus 0 link: 0
9210 04:45:09.870910 CPU_CLUSTER: 0 missing set_resources
9211 04:45:09.877499 Root Device assign_resources, bus 0 link: 0 done
9212 04:45:09.878113 Done setting resources.
9213 04:45:09.884504 Show resources in subtree (Root Device)...After assigning values.
9214 04:45:09.887533 Root Device child on link 0 CPU_CLUSTER: 0
9215 04:45:09.891012 CPU_CLUSTER: 0 child on link 0 CPU: 00
9216 04:45:09.900870 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9217 04:45:09.901442 CPU: 00
9218 04:45:09.904291 Done allocating resources.
9219 04:45:09.907792 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9220 04:45:09.910763 Enabling resources...
9221 04:45:09.911330 done.
9222 04:45:09.917577 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9223 04:45:09.918190 Initializing devices...
9224 04:45:09.921123 Root Device init
9225 04:45:09.921689 init hardware done!
9226 04:45:09.924285 0x00000018: ctrlr->caps
9227 04:45:09.927560 52.000 MHz: ctrlr->f_max
9228 04:45:09.928039 0.400 MHz: ctrlr->f_min
9229 04:45:09.930937 0x40ff8080: ctrlr->voltages
9230 04:45:09.931531 sclk: 390625
9231 04:45:09.934276 Bus Width = 1
9232 04:45:09.934740 sclk: 390625
9233 04:45:09.937852 Bus Width = 1
9234 04:45:09.938446 Early init status = 3
9235 04:45:09.944257 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9236 04:45:09.947701 in-header: 03 fc 00 00 01 00 00 00
9237 04:45:09.948301 in-data: 00
9238 04:45:09.953669 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9239 04:45:09.957774 in-header: 03 fd 00 00 00 00 00 00
9240 04:45:09.960815 in-data:
9241 04:45:09.964259 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9242 04:45:09.967668 in-header: 03 fc 00 00 01 00 00 00
9243 04:45:09.970316 in-data: 00
9244 04:45:09.974074 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9245 04:45:09.978652 in-header: 03 fd 00 00 00 00 00 00
9246 04:45:09.981249 in-data:
9247 04:45:09.984930 [SSUSB] Setting up USB HOST controller...
9248 04:45:09.987866 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9249 04:45:09.991703 [SSUSB] phy power-on done.
9250 04:45:09.995148 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9251 04:45:10.001316 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9252 04:45:10.004998 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9253 04:45:10.011458 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9254 04:45:10.018300 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9255 04:45:10.024469 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9256 04:45:10.031020 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9257 04:45:10.037785 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9258 04:45:10.041288 SPM: binary array size = 0x9dc
9259 04:45:10.044406 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9260 04:45:10.050864 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9261 04:45:10.058205 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9262 04:45:10.061226 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9263 04:45:10.067690 configure_display: Starting display init
9264 04:45:10.101461 anx7625_power_on_init: Init interface.
9265 04:45:10.104808 anx7625_disable_pd_protocol: Disabled PD feature.
9266 04:45:10.108148 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9267 04:45:10.135477 anx7625_start_dp_work: Secure OCM version=00
9268 04:45:10.138936 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9269 04:45:10.153912 sp_tx_get_edid_block: EDID Block = 1
9270 04:45:10.256775 Extracted contents:
9271 04:45:10.259993 header: 00 ff ff ff ff ff ff 00
9272 04:45:10.263090 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9273 04:45:10.266638 version: 01 04
9274 04:45:10.270057 basic params: 95 1f 11 78 0a
9275 04:45:10.273164 chroma info: 76 90 94 55 54 90 27 21 50 54
9276 04:45:10.276709 established: 00 00 00
9277 04:45:10.282942 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9278 04:45:10.286681 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9279 04:45:10.293114 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9280 04:45:10.299948 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9281 04:45:10.306328 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9282 04:45:10.309425 extensions: 00
9283 04:45:10.310064 checksum: fb
9284 04:45:10.310448
9285 04:45:10.312800 Manufacturer: IVO Model 57d Serial Number 0
9286 04:45:10.316287 Made week 0 of 2020
9287 04:45:10.316759 EDID version: 1.4
9288 04:45:10.319388 Digital display
9289 04:45:10.322923 6 bits per primary color channel
9290 04:45:10.323495 DisplayPort interface
9291 04:45:10.326540 Maximum image size: 31 cm x 17 cm
9292 04:45:10.329902 Gamma: 220%
9293 04:45:10.330404 Check DPMS levels
9294 04:45:10.332789 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9295 04:45:10.336223 First detailed timing is preferred timing
9296 04:45:10.339632 Established timings supported:
9297 04:45:10.342951 Standard timings supported:
9298 04:45:10.343406 Detailed timings
9299 04:45:10.349484 Hex of detail: 383680a07038204018303c0035ae10000019
9300 04:45:10.352891 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9301 04:45:10.359671 0780 0798 07c8 0820 hborder 0
9302 04:45:10.362824 0438 043b 0447 0458 vborder 0
9303 04:45:10.366515 -hsync -vsync
9304 04:45:10.366971 Did detailed timing
9305 04:45:10.369509 Hex of detail: 000000000000000000000000000000000000
9306 04:45:10.372786 Manufacturer-specified data, tag 0
9307 04:45:10.379419 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9308 04:45:10.379876 ASCII string: InfoVision
9309 04:45:10.386088 Hex of detail: 000000fe00523134304e574635205248200a
9310 04:45:10.389602 ASCII string: R140NWF5 RH
9311 04:45:10.390213 Checksum
9312 04:45:10.390587 Checksum: 0xfb (valid)
9313 04:45:10.396432 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9314 04:45:10.399730 DSI data_rate: 832800000 bps
9315 04:45:10.402683 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9316 04:45:10.405987 anx7625_parse_edid: pixelclock(138800).
9317 04:45:10.412086 hactive(1920), hsync(48), hfp(24), hbp(88)
9318 04:45:10.415888 vactive(1080), vsync(12), vfp(3), vbp(17)
9319 04:45:10.419114 anx7625_dsi_config: config dsi.
9320 04:45:10.426120 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9321 04:45:10.438303 anx7625_dsi_config: success to config DSI
9322 04:45:10.441699 anx7625_dp_start: MIPI phy setup OK.
9323 04:45:10.445218 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9324 04:45:10.448392 mtk_ddp_mode_set invalid vrefresh 60
9325 04:45:10.451608 main_disp_path_setup
9326 04:45:10.452065 ovl_layer_smi_id_en
9327 04:45:10.454782 ovl_layer_smi_id_en
9328 04:45:10.455218 ccorr_config
9329 04:45:10.455544 aal_config
9330 04:45:10.458390 gamma_config
9331 04:45:10.458806 postmask_config
9332 04:45:10.461283 dither_config
9333 04:45:10.464528 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9334 04:45:10.470960 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9335 04:45:10.474397 Root Device init finished in 551 msecs
9336 04:45:10.477781 CPU_CLUSTER: 0 init
9337 04:45:10.484499 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9338 04:45:10.487953 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9339 04:45:10.490983 APU_MBOX 0x190000b0 = 0x10001
9340 04:45:10.494483 APU_MBOX 0x190001b0 = 0x10001
9341 04:45:10.497958 APU_MBOX 0x190005b0 = 0x10001
9342 04:45:10.500918 APU_MBOX 0x190006b0 = 0x10001
9343 04:45:10.515493 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9344 04:45:10.516844 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9345 04:45:10.529889 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9346 04:45:10.536235 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9347 04:45:10.548189 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9348 04:45:10.556913 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9349 04:45:10.561035 CPU_CLUSTER: 0 init finished in 81 msecs
9350 04:45:10.563855 Devices initialized
9351 04:45:10.567360 Show all devs... After init.
9352 04:45:10.567927 Root Device: enabled 1
9353 04:45:10.570538 CPU_CLUSTER: 0: enabled 1
9354 04:45:10.574127 CPU: 00: enabled 1
9355 04:45:10.577055 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9356 04:45:10.580354 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9357 04:45:10.583501 ELOG: NV offset 0x57f000 size 0x1000
9358 04:45:10.590837 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9359 04:45:10.597202 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9360 04:45:10.600745 ELOG: Event(17) added with size 13 at 2024-02-04 04:44:33 UTC
9361 04:45:10.603711 out: cmd=0x121: 03 db 21 01 00 00 00 00
9362 04:45:10.608861 in-header: 03 33 00 00 2c 00 00 00
9363 04:45:10.621816 in-data: 2c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9364 04:45:10.628540 ELOG: Event(A1) added with size 10 at 2024-02-04 04:44:33 UTC
9365 04:45:10.634964 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9366 04:45:10.641688 ELOG: Event(A0) added with size 9 at 2024-02-04 04:44:33 UTC
9367 04:45:10.645180 elog_add_boot_reason: Logged dev mode boot
9368 04:45:10.648681 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9369 04:45:10.652202 Finalize devices...
9370 04:45:10.652943 Devices finalized
9371 04:45:10.658163 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9372 04:45:10.661554 Writing coreboot table at 0xffe64000
9373 04:45:10.664981 0. 000000000010a000-0000000000113fff: RAMSTAGE
9374 04:45:10.668084 1. 0000000040000000-00000000400fffff: RAM
9375 04:45:10.674827 2. 0000000040100000-000000004032afff: RAMSTAGE
9376 04:45:10.677923 3. 000000004032b000-00000000545fffff: RAM
9377 04:45:10.681459 4. 0000000054600000-000000005465ffff: BL31
9378 04:45:10.684530 5. 0000000054660000-00000000ffe63fff: RAM
9379 04:45:10.691381 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9380 04:45:10.694859 7. 0000000100000000-000000023fffffff: RAM
9381 04:45:10.695427 Passing 5 GPIOs to payload:
9382 04:45:10.701753 NAME | PORT | POLARITY | VALUE
9383 04:45:10.705243 EC in RW | 0x000000aa | low | undefined
9384 04:45:10.711804 EC interrupt | 0x00000005 | low | undefined
9385 04:45:10.714618 TPM interrupt | 0x000000ab | high | undefined
9386 04:45:10.718296 SD card detect | 0x00000011 | high | undefined
9387 04:45:10.724856 speaker enable | 0x00000093 | high | undefined
9388 04:45:10.727795 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9389 04:45:10.731600 in-header: 03 f9 00 00 02 00 00 00
9390 04:45:10.732174 in-data: 02 00
9391 04:45:10.734898 ADC[4]: Raw value=901770 ID=7
9392 04:45:10.738093 ADC[3]: Raw value=213179 ID=1
9393 04:45:10.738655 RAM Code: 0x71
9394 04:45:10.741550 ADC[6]: Raw value=74502 ID=0
9395 04:45:10.744994 ADC[5]: Raw value=212072 ID=1
9396 04:45:10.745563 SKU Code: 0x1
9397 04:45:10.751532 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3234
9398 04:45:10.754800 coreboot table: 964 bytes.
9399 04:45:10.758255 IMD ROOT 0. 0xfffff000 0x00001000
9400 04:45:10.761142 IMD SMALL 1. 0xffffe000 0x00001000
9401 04:45:10.764805 RO MCACHE 2. 0xffffc000 0x00001104
9402 04:45:10.767911 CONSOLE 3. 0xfff7c000 0x00080000
9403 04:45:10.771296 FMAP 4. 0xfff7b000 0x00000452
9404 04:45:10.774513 TIME STAMP 5. 0xfff7a000 0x00000910
9405 04:45:10.778153 VBOOT WORK 6. 0xfff66000 0x00014000
9406 04:45:10.781235 RAMOOPS 7. 0xffe66000 0x00100000
9407 04:45:10.784491 COREBOOT 8. 0xffe64000 0x00002000
9408 04:45:10.785063 IMD small region:
9409 04:45:10.787858 IMD ROOT 0. 0xffffec00 0x00000400
9410 04:45:10.790937 VPD 1. 0xffffeb80 0x0000006c
9411 04:45:10.794355 MMC STATUS 2. 0xffffeb60 0x00000004
9412 04:45:10.801219 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9413 04:45:10.804361 Probing TPM: done!
9414 04:45:10.807744 Connected to device vid:did:rid of 1ae0:0028:00
9415 04:45:10.817707 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9416 04:45:10.820995 Initialized TPM device CR50 revision 0
9417 04:45:10.824676 Checking cr50 for pending updates
9418 04:45:10.828089 Reading cr50 TPM mode
9419 04:45:10.836318 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9420 04:45:10.843324 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9421 04:45:10.883021 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9422 04:45:10.886800 Checking segment from ROM address 0x40100000
9423 04:45:10.890196 Checking segment from ROM address 0x4010001c
9424 04:45:10.896700 Loading segment from ROM address 0x40100000
9425 04:45:10.897337 code (compression=0)
9426 04:45:10.906711 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9427 04:45:10.913293 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9428 04:45:10.913862 it's not compressed!
9429 04:45:10.920133 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9430 04:45:10.923225 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9431 04:45:10.943950 Loading segment from ROM address 0x4010001c
9432 04:45:10.944512 Entry Point 0x80000000
9433 04:45:10.946846 Loaded segments
9434 04:45:10.950347 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9435 04:45:10.957041 Jumping to boot code at 0x80000000(0xffe64000)
9436 04:45:10.963968 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9437 04:45:10.970064 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9438 04:45:10.977866 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9439 04:45:10.981460 Checking segment from ROM address 0x40100000
9440 04:45:10.984883 Checking segment from ROM address 0x4010001c
9441 04:45:10.991340 Loading segment from ROM address 0x40100000
9442 04:45:10.991813 code (compression=1)
9443 04:45:10.998053 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9444 04:45:11.008160 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9445 04:45:11.008751 using LZMA
9446 04:45:11.016465 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9447 04:45:11.023474 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9448 04:45:11.026471 Loading segment from ROM address 0x4010001c
9449 04:45:11.027043 Entry Point 0x54601000
9450 04:45:11.029759 Loaded segments
9451 04:45:11.033390 NOTICE: MT8192 bl31_setup
9452 04:45:11.040091 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9453 04:45:11.043505 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9454 04:45:11.046493 WARNING: region 0:
9455 04:45:11.049871 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 04:45:11.050384 WARNING: region 1:
9457 04:45:11.056797 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9458 04:45:11.059768 WARNING: region 2:
9459 04:45:11.063263 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9460 04:45:11.066705 WARNING: region 3:
9461 04:45:11.070059 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9462 04:45:11.073417 WARNING: region 4:
9463 04:45:11.076776 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9464 04:45:11.080104 WARNING: region 5:
9465 04:45:11.083424 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 04:45:11.086535 WARNING: region 6:
9467 04:45:11.090098 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 04:45:11.090651 WARNING: region 7:
9469 04:45:11.096712 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 04:45:11.103487 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9471 04:45:11.107004 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9472 04:45:11.110321 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9473 04:45:11.117278 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9474 04:45:11.120367 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9475 04:45:11.123606 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9476 04:45:11.129904 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9477 04:45:11.133386 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9478 04:45:11.140169 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9479 04:45:11.143587 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9480 04:45:11.146851 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9481 04:45:11.153445 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9482 04:45:11.156437 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9483 04:45:11.159809 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9484 04:45:11.166823 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9485 04:45:11.169697 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9486 04:45:11.176451 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9487 04:45:11.179774 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9488 04:45:11.183178 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9489 04:45:11.189766 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9490 04:45:11.193103 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9491 04:45:11.196616 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9492 04:45:11.203251 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9493 04:45:11.206593 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9494 04:45:11.213022 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9495 04:45:11.216786 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9496 04:45:11.220140 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9497 04:45:11.226844 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9498 04:45:11.229833 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9499 04:45:11.236608 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9500 04:45:11.240060 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9501 04:45:11.243651 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9502 04:45:11.250348 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9503 04:45:11.253415 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9504 04:45:11.256489 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9505 04:45:11.260060 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9506 04:45:11.263929 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9507 04:45:11.270387 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9508 04:45:11.273772 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9509 04:45:11.276552 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9510 04:45:11.280309 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9511 04:45:11.286615 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9512 04:45:11.290343 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9513 04:45:11.293444 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9514 04:45:11.296793 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9515 04:45:11.303678 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9516 04:45:11.306802 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9517 04:45:11.310230 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9518 04:45:11.317077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9519 04:45:11.320301 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9520 04:45:11.326850 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9521 04:45:11.330199 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9522 04:45:11.333759 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9523 04:45:11.340320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9524 04:45:11.343693 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9525 04:45:11.350179 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9526 04:45:11.353647 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9527 04:45:11.356671 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9528 04:45:11.363529 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9529 04:45:11.366782 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9530 04:45:11.373478 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9531 04:45:11.376837 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9532 04:45:11.383573 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9533 04:45:11.387166 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9534 04:45:11.393561 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9535 04:45:11.396972 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9536 04:45:11.400040 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9537 04:45:11.406804 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9538 04:45:11.410374 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9539 04:45:11.416929 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9540 04:45:11.420759 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9541 04:45:11.426976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9542 04:45:11.430201 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9543 04:45:11.433802 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9544 04:45:11.440575 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9545 04:45:11.444003 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9546 04:45:11.450589 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9547 04:45:11.454070 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9548 04:45:11.460380 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9549 04:45:11.463819 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9550 04:45:11.466961 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9551 04:45:11.473289 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9552 04:45:11.476910 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9553 04:45:11.483728 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9554 04:45:11.486842 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9555 04:45:11.493636 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9556 04:45:11.497198 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9557 04:45:11.500551 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9558 04:45:11.506927 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9559 04:45:11.510349 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9560 04:45:11.517224 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9561 04:45:11.520879 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9562 04:45:11.527237 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9563 04:45:11.530547 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9564 04:45:11.533893 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9565 04:45:11.540337 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9566 04:45:11.543697 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9567 04:45:11.547307 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9568 04:45:11.553801 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9569 04:45:11.557158 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9570 04:45:11.560597 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9571 04:45:11.563812 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9572 04:45:11.570279 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9573 04:45:11.573641 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9574 04:45:11.580100 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9575 04:45:11.583477 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9576 04:45:11.586819 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9577 04:45:11.593351 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9578 04:45:11.596710 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9579 04:45:11.603348 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9580 04:45:11.606603 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9581 04:45:11.609879 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9582 04:45:11.616858 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9583 04:45:11.620182 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9584 04:45:11.626699 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9585 04:45:11.630080 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9586 04:45:11.633342 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9587 04:45:11.640058 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9588 04:45:11.643461 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9589 04:45:11.646973 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9590 04:45:11.649893 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9591 04:45:11.657071 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9592 04:45:11.660095 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9593 04:45:11.663476 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9594 04:45:11.666797 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9595 04:45:11.673244 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9596 04:45:11.676771 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9597 04:45:11.683607 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9598 04:45:11.686578 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9599 04:45:11.690094 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9600 04:45:11.697162 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9601 04:45:11.700570 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9602 04:45:11.707174 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9603 04:45:11.710362 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9604 04:45:11.713565 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9605 04:45:11.720590 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9606 04:45:11.723539 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9607 04:45:11.727468 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9608 04:45:11.734044 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9609 04:45:11.737294 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9610 04:45:11.744046 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9611 04:45:11.747197 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9612 04:45:11.750517 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9613 04:45:11.756948 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9614 04:45:11.760597 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9615 04:45:11.767437 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9616 04:45:11.770787 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9617 04:45:11.774016 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9618 04:45:11.780678 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9619 04:45:11.784116 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9620 04:45:11.787137 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9621 04:45:11.794047 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9622 04:45:11.797426 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9623 04:45:11.804014 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9624 04:45:11.807240 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9625 04:45:11.810570 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9626 04:45:11.817176 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9627 04:45:11.820340 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9628 04:45:11.823846 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9629 04:45:11.830626 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9630 04:45:11.833928 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9631 04:45:11.840540 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9632 04:45:11.843860 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9633 04:45:11.847157 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9634 04:45:11.853573 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9635 04:45:11.857225 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9636 04:45:11.863693 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9637 04:45:11.867105 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9638 04:45:11.870612 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9639 04:45:11.876880 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9640 04:45:11.880174 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9641 04:45:11.886746 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9642 04:45:11.890049 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9643 04:45:11.893578 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9644 04:45:11.899957 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9645 04:45:11.903431 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9646 04:45:11.909901 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9647 04:45:11.913257 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9648 04:45:11.916510 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9649 04:45:11.923174 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9650 04:45:11.926418 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9651 04:45:11.933346 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9652 04:45:11.936745 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9653 04:45:11.939898 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9654 04:45:11.946485 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9655 04:45:11.949673 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9656 04:45:11.956511 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9657 04:45:11.959561 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9658 04:45:11.963042 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9659 04:45:11.969533 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9660 04:45:11.973062 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9661 04:45:11.979798 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9662 04:45:11.983125 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9663 04:45:11.986536 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9664 04:45:11.992891 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9665 04:45:11.996402 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9666 04:45:12.002806 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9667 04:45:12.006337 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9668 04:45:12.012744 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9669 04:45:12.016138 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9670 04:45:12.019453 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9671 04:45:12.025996 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9672 04:45:12.029669 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9673 04:45:12.036290 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9674 04:45:12.039285 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9675 04:45:12.042659 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9676 04:45:12.049538 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9677 04:45:12.053009 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9678 04:45:12.059733 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9679 04:45:12.062665 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9680 04:45:12.069573 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9681 04:45:12.072563 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9682 04:45:12.076015 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9683 04:45:12.082646 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9684 04:45:12.086113 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9685 04:45:12.092928 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9686 04:45:12.096179 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9687 04:45:12.099205 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9688 04:45:12.106095 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9689 04:45:12.109525 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9690 04:45:12.116006 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9691 04:45:12.119433 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9692 04:45:12.122841 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9693 04:45:12.128973 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9694 04:45:12.132648 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9695 04:45:12.139321 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9696 04:45:12.142267 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9697 04:45:12.148979 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9698 04:45:12.152320 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9699 04:45:12.155575 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9700 04:45:12.158742 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9701 04:45:12.165347 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9702 04:45:12.168723 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9703 04:45:12.172298 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9704 04:45:12.175740 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9705 04:45:12.182094 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9706 04:45:12.185436 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9707 04:45:12.192196 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9708 04:45:12.195501 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9709 04:45:12.198756 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9710 04:45:12.205193 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9711 04:45:12.208736 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9712 04:45:12.215656 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9713 04:45:12.218612 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9714 04:45:12.221917 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9715 04:45:12.228690 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9716 04:45:12.231991 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9717 04:45:12.235210 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9718 04:45:12.241815 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9719 04:45:12.245318 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9720 04:45:12.248773 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9721 04:45:12.255461 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9722 04:45:12.258654 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9723 04:45:12.262096 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9724 04:45:12.268583 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9725 04:45:12.271553 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9726 04:45:12.278439 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9727 04:45:12.281493 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9728 04:45:12.284826 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9729 04:45:12.291806 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9730 04:45:12.295107 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9731 04:45:12.298513 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9732 04:45:12.305297 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9733 04:45:12.308614 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9734 04:45:12.311494 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9735 04:45:12.318446 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9736 04:45:12.321821 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9737 04:45:12.328556 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9738 04:45:12.331680 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9739 04:45:12.335515 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9740 04:45:12.338443 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9741 04:45:12.345210 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9742 04:45:12.348611 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9743 04:45:12.351517 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9744 04:45:12.354895 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9745 04:45:12.358197 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9746 04:45:12.365473 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9747 04:45:12.368204 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9748 04:45:12.372098 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9749 04:45:12.374981 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9750 04:45:12.381895 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9751 04:45:12.384805 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9752 04:45:12.388288 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9753 04:45:12.395005 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9754 04:45:12.398413 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9755 04:45:12.404768 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9756 04:45:12.408199 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9757 04:45:12.414662 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9758 04:45:12.418152 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9759 04:45:12.421624 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9760 04:45:12.428110 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9761 04:45:12.431006 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9762 04:45:12.437843 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9763 04:45:12.441546 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9764 04:45:12.447318 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9765 04:45:12.450898 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9766 04:45:12.454261 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9767 04:45:12.460583 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9768 04:45:12.464024 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9769 04:45:12.471058 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9770 04:45:12.473877 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9771 04:45:12.477220 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9772 04:45:12.484066 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9773 04:45:12.487104 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9774 04:45:12.494045 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9775 04:45:12.497399 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9776 04:45:12.500763 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9777 04:45:12.507556 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9778 04:45:12.510392 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9779 04:45:12.517026 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9780 04:45:12.520459 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9781 04:45:12.526959 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9782 04:45:12.530580 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9783 04:45:12.534073 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9784 04:45:12.540416 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9785 04:45:12.543847 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9786 04:45:12.550678 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9787 04:45:12.553861 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9788 04:45:12.557017 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9789 04:45:12.563445 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9790 04:45:12.567132 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9791 04:45:12.573717 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9792 04:45:12.576997 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9793 04:45:12.580322 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9794 04:45:12.586854 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9795 04:45:12.589891 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9796 04:45:12.596866 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9797 04:45:12.599968 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9798 04:45:12.606762 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9799 04:45:12.609816 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9800 04:45:12.613264 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9801 04:45:12.619933 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9802 04:45:12.623372 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9803 04:45:12.629771 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9804 04:45:12.633261 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9805 04:45:12.636228 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9806 04:45:12.643107 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9807 04:45:12.646636 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9808 04:45:12.653133 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9809 04:45:12.656510 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9810 04:45:12.659669 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9811 04:45:12.666601 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9812 04:45:12.669761 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9813 04:45:12.676138 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9814 04:45:12.679455 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9815 04:45:12.682644 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9816 04:45:12.689766 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9817 04:45:12.692757 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9818 04:45:12.699362 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9819 04:45:12.702754 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9820 04:45:12.709731 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9821 04:45:12.712994 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9822 04:45:12.716100 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9823 04:45:12.722962 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9824 04:45:12.726077 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9825 04:45:12.732974 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9826 04:45:12.736467 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9827 04:45:12.739368 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9828 04:45:12.746378 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9829 04:45:12.749658 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9830 04:45:12.756166 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9831 04:45:12.759572 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9832 04:45:12.763047 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9833 04:45:12.769487 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9834 04:45:12.773027 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9835 04:45:12.779347 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9836 04:45:12.782930 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9837 04:45:12.789449 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9838 04:45:12.792443 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9839 04:45:12.799583 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9840 04:45:12.802474 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9841 04:45:12.805910 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9842 04:45:12.812779 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9843 04:45:12.815733 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9844 04:45:12.822591 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9845 04:45:12.826013 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9846 04:45:12.832607 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9847 04:45:12.836050 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9848 04:45:12.839263 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9849 04:45:12.846231 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9850 04:45:12.849033 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9851 04:45:12.855733 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9852 04:45:12.859441 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9853 04:45:12.865778 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9854 04:45:12.869166 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9855 04:45:12.872202 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9856 04:45:12.879111 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9857 04:45:12.882186 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9858 04:45:12.889073 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9859 04:45:12.892239 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9860 04:45:12.898713 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9861 04:45:12.902152 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9862 04:45:12.908685 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9863 04:45:12.912020 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9864 04:45:12.915467 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9865 04:45:12.922169 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9866 04:45:12.925408 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9867 04:45:12.932156 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9868 04:45:12.935379 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9869 04:45:12.942156 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9870 04:45:12.945788 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9871 04:45:12.948905 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9872 04:45:12.955371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9873 04:45:12.958832 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9874 04:45:12.965290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9875 04:45:12.968639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9876 04:45:12.975607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9877 04:45:12.978895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9878 04:45:12.982076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9879 04:45:12.988764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9880 04:45:12.992328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9881 04:45:12.998642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9882 04:45:13.002520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9883 04:45:13.009029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9884 04:45:13.012646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9885 04:45:13.019159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9886 04:45:13.021892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9887 04:45:13.028765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9888 04:45:13.032007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9889 04:45:13.038499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9890 04:45:13.041677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9891 04:45:13.048348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9892 04:45:13.051793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9893 04:45:13.058535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9894 04:45:13.061477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9895 04:45:13.068312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9896 04:45:13.071870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9897 04:45:13.078570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9898 04:45:13.081541 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9899 04:45:13.088318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9900 04:45:13.091399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9901 04:45:13.098133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9902 04:45:13.101531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9903 04:45:13.108165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9904 04:45:13.111157 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9905 04:45:13.114754 INFO: [APUAPC] vio 0
9906 04:45:13.118246 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9907 04:45:13.124706 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9908 04:45:13.127946 INFO: [APUAPC] D0_APC_0: 0x400510
9909 04:45:13.128440 INFO: [APUAPC] D0_APC_1: 0x0
9910 04:45:13.131175 INFO: [APUAPC] D0_APC_2: 0x1540
9911 04:45:13.134527 INFO: [APUAPC] D0_APC_3: 0x0
9912 04:45:13.137910 INFO: [APUAPC] D1_APC_0: 0xffffffff
9913 04:45:13.141152 INFO: [APUAPC] D1_APC_1: 0xffffffff
9914 04:45:13.144419 INFO: [APUAPC] D1_APC_2: 0x3fffff
9915 04:45:13.147727 INFO: [APUAPC] D1_APC_3: 0x0
9916 04:45:13.151221 INFO: [APUAPC] D2_APC_0: 0xffffffff
9917 04:45:13.154634 INFO: [APUAPC] D2_APC_1: 0xffffffff
9918 04:45:13.158127 INFO: [APUAPC] D2_APC_2: 0x3fffff
9919 04:45:13.160982 INFO: [APUAPC] D2_APC_3: 0x0
9920 04:45:13.164482 INFO: [APUAPC] D3_APC_0: 0xffffffff
9921 04:45:13.167887 INFO: [APUAPC] D3_APC_1: 0xffffffff
9922 04:45:13.170930 INFO: [APUAPC] D3_APC_2: 0x3fffff
9923 04:45:13.174450 INFO: [APUAPC] D3_APC_3: 0x0
9924 04:45:13.177760 INFO: [APUAPC] D4_APC_0: 0xffffffff
9925 04:45:13.181161 INFO: [APUAPC] D4_APC_1: 0xffffffff
9926 04:45:13.184275 INFO: [APUAPC] D4_APC_2: 0x3fffff
9927 04:45:13.187806 INFO: [APUAPC] D4_APC_3: 0x0
9928 04:45:13.191263 INFO: [APUAPC] D5_APC_0: 0xffffffff
9929 04:45:13.194160 INFO: [APUAPC] D5_APC_1: 0xffffffff
9930 04:45:13.197624 INFO: [APUAPC] D5_APC_2: 0x3fffff
9931 04:45:13.200750 INFO: [APUAPC] D5_APC_3: 0x0
9932 04:45:13.204526 INFO: [APUAPC] D6_APC_0: 0xffffffff
9933 04:45:13.207487 INFO: [APUAPC] D6_APC_1: 0xffffffff
9934 04:45:13.210724 INFO: [APUAPC] D6_APC_2: 0x3fffff
9935 04:45:13.214089 INFO: [APUAPC] D6_APC_3: 0x0
9936 04:45:13.217552 INFO: [APUAPC] D7_APC_0: 0xffffffff
9937 04:45:13.220848 INFO: [APUAPC] D7_APC_1: 0xffffffff
9938 04:45:13.224385 INFO: [APUAPC] D7_APC_2: 0x3fffff
9939 04:45:13.227195 INFO: [APUAPC] D7_APC_3: 0x0
9940 04:45:13.230651 INFO: [APUAPC] D8_APC_0: 0xffffffff
9941 04:45:13.234177 INFO: [APUAPC] D8_APC_1: 0xffffffff
9942 04:45:13.237533 INFO: [APUAPC] D8_APC_2: 0x3fffff
9943 04:45:13.240964 INFO: [APUAPC] D8_APC_3: 0x0
9944 04:45:13.244371 INFO: [APUAPC] D9_APC_0: 0xffffffff
9945 04:45:13.247616 INFO: [APUAPC] D9_APC_1: 0xffffffff
9946 04:45:13.250415 INFO: [APUAPC] D9_APC_2: 0x3fffff
9947 04:45:13.253697 INFO: [APUAPC] D9_APC_3: 0x0
9948 04:45:13.257134 INFO: [APUAPC] D10_APC_0: 0xffffffff
9949 04:45:13.260554 INFO: [APUAPC] D10_APC_1: 0xffffffff
9950 04:45:13.264050 INFO: [APUAPC] D10_APC_2: 0x3fffff
9951 04:45:13.267398 INFO: [APUAPC] D10_APC_3: 0x0
9952 04:45:13.270401 INFO: [APUAPC] D11_APC_0: 0xffffffff
9953 04:45:13.273787 INFO: [APUAPC] D11_APC_1: 0xffffffff
9954 04:45:13.276833 INFO: [APUAPC] D11_APC_2: 0x3fffff
9955 04:45:13.280370 INFO: [APUAPC] D11_APC_3: 0x0
9956 04:45:13.283718 INFO: [APUAPC] D12_APC_0: 0xffffffff
9957 04:45:13.287173 INFO: [APUAPC] D12_APC_1: 0xffffffff
9958 04:45:13.290627 INFO: [APUAPC] D12_APC_2: 0x3fffff
9959 04:45:13.293657 INFO: [APUAPC] D12_APC_3: 0x0
9960 04:45:13.297203 INFO: [APUAPC] D13_APC_0: 0xffffffff
9961 04:45:13.300553 INFO: [APUAPC] D13_APC_1: 0xffffffff
9962 04:45:13.303600 INFO: [APUAPC] D13_APC_2: 0x3fffff
9963 04:45:13.306817 INFO: [APUAPC] D13_APC_3: 0x0
9964 04:45:13.310095 INFO: [APUAPC] D14_APC_0: 0xffffffff
9965 04:45:13.313516 INFO: [APUAPC] D14_APC_1: 0xffffffff
9966 04:45:13.316722 INFO: [APUAPC] D14_APC_2: 0x3fffff
9967 04:45:13.320301 INFO: [APUAPC] D14_APC_3: 0x0
9968 04:45:13.323694 INFO: [APUAPC] D15_APC_0: 0xffffffff
9969 04:45:13.326732 INFO: [APUAPC] D15_APC_1: 0xffffffff
9970 04:45:13.330062 INFO: [APUAPC] D15_APC_2: 0x3fffff
9971 04:45:13.333569 INFO: [APUAPC] D15_APC_3: 0x0
9972 04:45:13.337076 INFO: [APUAPC] APC_CON: 0x4
9973 04:45:13.337544 INFO: [NOCDAPC] D0_APC_0: 0x0
9974 04:45:13.339977 INFO: [NOCDAPC] D0_APC_1: 0x0
9975 04:45:13.343618 INFO: [NOCDAPC] D1_APC_0: 0x0
9976 04:45:13.347076 INFO: [NOCDAPC] D1_APC_1: 0xfff
9977 04:45:13.350189 INFO: [NOCDAPC] D2_APC_0: 0x0
9978 04:45:13.353516 INFO: [NOCDAPC] D2_APC_1: 0xfff
9979 04:45:13.356840 INFO: [NOCDAPC] D3_APC_0: 0x0
9980 04:45:13.359904 INFO: [NOCDAPC] D3_APC_1: 0xfff
9981 04:45:13.363423 INFO: [NOCDAPC] D4_APC_0: 0x0
9982 04:45:13.366711 INFO: [NOCDAPC] D4_APC_1: 0xfff
9983 04:45:13.369567 INFO: [NOCDAPC] D5_APC_0: 0x0
9984 04:45:13.373574 INFO: [NOCDAPC] D5_APC_1: 0xfff
9985 04:45:13.374188 INFO: [NOCDAPC] D6_APC_0: 0x0
9986 04:45:13.376795 INFO: [NOCDAPC] D6_APC_1: 0xfff
9987 04:45:13.380062 INFO: [NOCDAPC] D7_APC_0: 0x0
9988 04:45:13.383322 INFO: [NOCDAPC] D7_APC_1: 0xfff
9989 04:45:13.386300 INFO: [NOCDAPC] D8_APC_0: 0x0
9990 04:45:13.389806 INFO: [NOCDAPC] D8_APC_1: 0xfff
9991 04:45:13.393249 INFO: [NOCDAPC] D9_APC_0: 0x0
9992 04:45:13.396807 INFO: [NOCDAPC] D9_APC_1: 0xfff
9993 04:45:13.399918 INFO: [NOCDAPC] D10_APC_0: 0x0
9994 04:45:13.403231 INFO: [NOCDAPC] D10_APC_1: 0xfff
9995 04:45:13.406652 INFO: [NOCDAPC] D11_APC_0: 0x0
9996 04:45:13.409752 INFO: [NOCDAPC] D11_APC_1: 0xfff
9997 04:45:13.410281 INFO: [NOCDAPC] D12_APC_0: 0x0
9998 04:45:13.413041 INFO: [NOCDAPC] D12_APC_1: 0xfff
9999 04:45:13.416113 INFO: [NOCDAPC] D13_APC_0: 0x0
10000 04:45:13.419907 INFO: [NOCDAPC] D13_APC_1: 0xfff
10001 04:45:13.422967 INFO: [NOCDAPC] D14_APC_0: 0x0
10002 04:45:13.426577 INFO: [NOCDAPC] D14_APC_1: 0xfff
10003 04:45:13.429514 INFO: [NOCDAPC] D15_APC_0: 0x0
10004 04:45:13.432800 INFO: [NOCDAPC] D15_APC_1: 0xfff
10005 04:45:13.436458 INFO: [NOCDAPC] APC_CON: 0x4
10006 04:45:13.439842 INFO: [APUAPC] set_apusys_apc done
10007 04:45:13.442791 INFO: [DEVAPC] devapc_init done
10008 04:45:13.446583 INFO: GICv3 without legacy support detected.
10009 04:45:13.449532 INFO: ARM GICv3 driver initialized in EL3
10010 04:45:13.453231 INFO: Maximum SPI INTID supported: 639
10011 04:45:13.459799 INFO: BL31: Initializing runtime services
10012 04:45:13.462837 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10013 04:45:13.466087 INFO: SPM: enable CPC mode
10014 04:45:13.473088 INFO: mcdi ready for mcusys-off-idle and system suspend
10015 04:45:13.476860 INFO: BL31: Preparing for EL3 exit to normal world
10016 04:45:13.479620 INFO: Entry point address = 0x80000000
10017 04:45:13.482970 INFO: SPSR = 0x8
10018 04:45:13.487873
10019 04:45:13.488332
10020 04:45:13.488698
10021 04:45:13.490928 Starting depthcharge on Spherion...
10022 04:45:13.491446
10023 04:45:13.491815 Wipe memory regions:
10024 04:45:13.492157
10025 04:45:13.494895 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10026 04:45:13.495493 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10027 04:45:13.496095 Setting prompt string to ['asurada:']
10028 04:45:13.496563 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10029 04:45:13.497283 [0x00000040000000, 0x00000054600000)
10030 04:45:13.616839
10031 04:45:13.617393 [0x00000054660000, 0x00000080000000)
10032 04:45:13.877299
10033 04:45:13.877870 [0x000000821a7280, 0x000000ffe64000)
10034 04:45:14.621872
10035 04:45:14.622041 [0x00000100000000, 0x00000240000000)
10036 04:45:16.511901
10037 04:45:16.515314 Initializing XHCI USB controller at 0x11200000.
10038 04:45:17.552962
10039 04:45:17.556268 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10040 04:45:17.556343
10041 04:45:17.556405
10042 04:45:17.556464
10043 04:45:17.556736 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10045 04:45:17.657226 asurada: tftpboot 192.168.201.1 12699819/tftp-deploy-qmxjd096/kernel/image.itb 12699819/tftp-deploy-qmxjd096/kernel/cmdline
10046 04:45:17.657972 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10047 04:45:17.658459 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10048 04:45:17.663116 tftpboot 192.168.201.1 12699819/tftp-deploy-qmxjd096/kernel/image.itbtp-deploy-qmxjd096/kernel/cmdline
10049 04:45:17.663632
10050 04:45:17.664090 Waiting for link
10051 04:45:17.823202
10052 04:45:17.823350 R8152: Initializing
10053 04:45:17.823422
10054 04:45:17.826562 Version 9 (ocp_data = 6010)
10055 04:45:17.826670
10056 04:45:17.829457 R8152: Done initializing
10057 04:45:17.829565
10058 04:45:17.829663 Adding net device
10059 04:45:19.701164
10060 04:45:19.701302 done.
10061 04:45:19.701369
10062 04:45:19.701430 MAC: 00:e0:4c:72:2d:d6
10063 04:45:19.701488
10064 04:45:19.704476 Sending DHCP discover... done.
10065 04:45:19.704549
10066 04:45:30.831305 Waiting for reply... R8152: Bulk read error 0xffffffbf
10067 04:45:30.831873
10068 04:45:30.834761 Receive failed.
10069 04:45:30.835279
10070 04:45:30.835644 done.
10071 04:45:30.836130
10072 04:45:30.838192 Sending DHCP request... done.
10073 04:45:30.838647
10074 04:45:30.841535 Waiting for reply... done.
10075 04:45:30.842016
10076 04:45:30.842377 My ip is 192.168.201.21
10077 04:45:30.842710
10078 04:45:30.844513 The DHCP server ip is 192.168.201.1
10079 04:45:30.844969
10080 04:45:30.851472 TFTP server IP predefined by user: 192.168.201.1
10081 04:45:30.852020
10082 04:45:30.858314 Bootfile predefined by user: 12699819/tftp-deploy-qmxjd096/kernel/image.itb
10083 04:45:30.858875
10084 04:45:30.861341 Sending tftp read request... done.
10085 04:45:30.861823
10086 04:45:30.865911 Waiting for the transfer...
10087 04:45:30.866444
10088 04:45:31.183530 00000000 ################################################################
10089 04:45:31.183683
10090 04:45:31.451064 00080000 ################################################################
10091 04:45:31.451212
10092 04:45:31.695645 00100000 ################################################################
10093 04:45:31.695827
10094 04:45:31.938243 00180000 ################################################################
10095 04:45:31.938410
10096 04:45:32.181429 00200000 ################################################################
10097 04:45:32.181573
10098 04:45:32.425343 00280000 ################################################################
10099 04:45:32.425495
10100 04:45:32.668828 00300000 ################################################################
10101 04:45:32.668977
10102 04:45:32.912677 00380000 ################################################################
10103 04:45:32.912830
10104 04:45:33.156325 00400000 ################################################################
10105 04:45:33.156509
10106 04:45:33.400859 00480000 ################################################################
10107 04:45:33.401033
10108 04:45:33.644930 00500000 ################################################################
10109 04:45:33.645083
10110 04:45:33.888380 00580000 ################################################################
10111 04:45:33.888553
10112 04:45:34.133210 00600000 ################################################################
10113 04:45:34.133383
10114 04:45:34.376677 00680000 ################################################################
10115 04:45:34.376851
10116 04:45:34.641493 00700000 ################################################################
10117 04:45:34.641633
10118 04:45:34.937373 00780000 ################################################################
10119 04:45:34.937535
10120 04:45:35.194080 00800000 ################################################################
10121 04:45:35.194231
10122 04:45:35.438775 00880000 ################################################################
10123 04:45:35.439007
10124 04:45:35.682967 00900000 ################################################################
10125 04:45:35.683117
10126 04:45:35.927867 00980000 ################################################################
10127 04:45:35.928014
10128 04:45:36.172955 00a00000 ################################################################
10129 04:45:36.173131
10130 04:45:36.416839 00a80000 ################################################################
10131 04:45:36.416989
10132 04:45:36.660896 00b00000 ################################################################
10133 04:45:36.661046
10134 04:45:36.904144 00b80000 ################################################################
10135 04:45:36.904295
10136 04:45:37.148664 00c00000 ################################################################
10137 04:45:37.148842
10138 04:45:37.392309 00c80000 ################################################################
10139 04:45:37.392459
10140 04:45:37.636968 00d00000 ################################################################
10141 04:45:37.637150
10142 04:45:37.880981 00d80000 ################################################################
10143 04:45:37.881161
10144 04:45:38.125127 00e00000 ################################################################
10145 04:45:38.125283
10146 04:45:38.369828 00e80000 ################################################################
10147 04:45:38.370021
10148 04:45:38.616891 00f00000 ################################################################
10149 04:45:38.617032
10150 04:45:38.866236 00f80000 ################################################################
10151 04:45:38.866362
10152 04:45:39.115217 01000000 ################################################################
10153 04:45:39.115351
10154 04:45:39.361910 01080000 ################################################################
10155 04:45:39.362065
10156 04:45:39.607485 01100000 ################################################################
10157 04:45:39.607632
10158 04:45:39.855160 01180000 ################################################################
10159 04:45:39.855349
10160 04:45:40.099197 01200000 ################################################################
10161 04:45:40.099391
10162 04:45:40.343339 01280000 ################################################################
10163 04:45:40.343516
10164 04:45:40.586560 01300000 ################################################################
10165 04:45:40.586740
10166 04:45:40.853021 01380000 ################################################################
10167 04:45:40.853178
10168 04:45:41.109502 01400000 ################################################################
10169 04:45:41.109687
10170 04:45:41.355935 01480000 ################################################################
10171 04:45:41.356070
10172 04:45:41.619603 01500000 ################################################################
10173 04:45:41.619751
10174 04:45:41.866913 01580000 ################################################################
10175 04:45:41.867066
10176 04:45:42.114574 01600000 ################################################################
10177 04:45:42.114705
10178 04:45:42.383807 01680000 ################################################################
10179 04:45:42.383962
10180 04:45:42.635707 01700000 ################################################################
10181 04:45:42.635886
10182 04:45:42.911435 01780000 ################################################################
10183 04:45:42.911610
10184 04:45:43.180058 01800000 ################################################################
10185 04:45:43.180220
10186 04:45:43.442128 01880000 ################################################################
10187 04:45:43.442283
10188 04:45:43.686747 01900000 ################################################################
10189 04:45:43.686921
10190 04:45:43.931608 01980000 ################################################################
10191 04:45:43.931802
10192 04:45:44.196175 01a00000 ################################################################
10193 04:45:44.196348
10194 04:45:44.441422 01a80000 ################################################################
10195 04:45:44.441591
10196 04:45:44.685282 01b00000 ################################################################
10197 04:45:44.685439
10198 04:45:44.928809 01b80000 ################################################################
10199 04:45:44.928987
10200 04:45:45.174541 01c00000 ################################################################
10201 04:45:45.174685
10202 04:45:45.426799 01c80000 ################################################################
10203 04:45:45.426967
10204 04:45:45.690404 01d00000 ################################################################
10205 04:45:45.690549
10206 04:45:45.970709 01d80000 ################################################################
10207 04:45:45.970859
10208 04:45:46.238408 01e00000 ################################################################
10209 04:45:46.238559
10210 04:45:46.496757 01e80000 ################################################################
10211 04:45:46.496923
10212 04:45:46.740178 01f00000 ################################################################
10213 04:45:46.740359
10214 04:45:46.984916 01f80000 ################################################################
10215 04:45:46.985090
10216 04:45:47.230130 02000000 ################################################################
10217 04:45:47.230305
10218 04:45:47.475597 02080000 ################################################################
10219 04:45:47.475766
10220 04:45:47.720464 02100000 ################################################################
10221 04:45:47.720637
10222 04:45:47.964266 02180000 ################################################################
10223 04:45:47.964440
10224 04:45:48.208901 02200000 ################################################################
10225 04:45:48.209048
10226 04:45:48.453396 02280000 ################################################################
10227 04:45:48.453541
10228 04:45:48.697587 02300000 ################################################################
10229 04:45:48.697767
10230 04:45:48.942028 02380000 ################################################################
10231 04:45:48.942163
10232 04:45:49.188886 02400000 ################################################################
10233 04:45:49.189041
10234 04:45:49.433068 02480000 ################################################################
10235 04:45:49.433217
10236 04:45:49.678999 02500000 ################################################################
10237 04:45:49.679164
10238 04:45:49.924148 02580000 ################################################################
10239 04:45:49.924343
10240 04:45:50.183133 02600000 ################################################################
10241 04:45:50.183286
10242 04:45:50.458381 02680000 ################################################################
10243 04:45:50.458522
10244 04:45:50.727234 02700000 ################################################################
10245 04:45:50.727383
10246 04:45:50.987559 02780000 ################################################################
10247 04:45:50.987707
10248 04:45:51.283374 02800000 ################################################################
10249 04:45:51.283521
10250 04:45:51.575473 02880000 ################################################################
10251 04:45:51.575609
10252 04:45:51.871148 02900000 ################################################################
10253 04:45:51.871301
10254 04:45:52.167721 02980000 ################################################################
10255 04:45:52.167877
10256 04:45:52.451010 02a00000 ################################################################
10257 04:45:52.451145
10258 04:45:52.716531 02a80000 ################################################################
10259 04:45:52.716688
10260 04:45:52.960313 02b00000 ################################################################
10261 04:45:52.960465
10262 04:45:53.203882 02b80000 ################################################################
10263 04:45:53.204033
10264 04:45:53.447057 02c00000 ################################################################
10265 04:45:53.447211
10266 04:45:53.691137 02c80000 ################################################################
10267 04:45:53.691278
10268 04:45:53.935631 02d00000 ################################################################
10269 04:45:53.935773
10270 04:45:54.178979 02d80000 ################################################################
10271 04:45:54.179163
10272 04:45:54.423519 02e00000 ################################################################
10273 04:45:54.423660
10274 04:45:54.668010 02e80000 ################################################################
10275 04:45:54.668169
10276 04:45:54.910933 02f00000 ################################################################
10277 04:45:54.911082
10278 04:45:55.154999 02f80000 ################################################################
10279 04:45:55.155207
10280 04:45:55.398615 03000000 ################################################################
10281 04:45:55.398760
10282 04:45:55.642078 03080000 ################################################################
10283 04:45:55.642224
10284 04:45:55.885455 03100000 ################################################################
10285 04:45:55.885595
10286 04:45:56.128469 03180000 ################################################################
10287 04:45:56.128622
10288 04:45:56.371615 03200000 ################################################################
10289 04:45:56.371767
10290 04:45:56.615519 03280000 ################################################################
10291 04:45:56.615660
10292 04:45:56.859382 03300000 ################################################################
10293 04:45:56.859531
10294 04:45:57.103530 03380000 ################################################################
10295 04:45:57.103685
10296 04:45:57.348016 03400000 ################################################################
10297 04:45:57.348165
10298 04:45:57.591733 03480000 ################################################################
10299 04:45:57.591880
10300 04:45:57.835818 03500000 ################################################################
10301 04:45:57.835969
10302 04:45:58.081342 03580000 ################################################################
10303 04:45:58.081495
10304 04:45:58.329450 03600000 ################################################################
10305 04:45:58.329588
10306 04:45:58.574573 03680000 ################################################################
10307 04:45:58.574725
10308 04:45:58.819066 03700000 ################################################################
10309 04:45:58.819213
10310 04:45:59.064444 03780000 ################################################################
10311 04:45:59.064587
10312 04:45:59.309853 03800000 ################################################################
10313 04:45:59.310025
10314 04:45:59.554425 03880000 ################################################################
10315 04:45:59.554568
10316 04:45:59.810312 03900000 ################################################################
10317 04:45:59.810455
10318 04:46:00.077013 03980000 ################################################################
10319 04:46:00.077149
10320 04:46:00.342928 03a00000 ################################################################
10321 04:46:00.343072
10322 04:46:00.592392 03a80000 ################################################################
10323 04:46:00.592568
10324 04:46:00.837678 03b00000 ################################################################
10325 04:46:00.837860
10326 04:46:01.091570 03b80000 ################################################################
10327 04:46:01.091720
10328 04:46:01.337270 03c00000 ################################################################
10329 04:46:01.337445
10330 04:46:01.585384 03c80000 ################################################################
10331 04:46:01.585517
10332 04:46:01.838885 03d00000 ################################################################
10333 04:46:01.839032
10334 04:46:02.087122 03d80000 ################################################################
10335 04:46:02.087290
10336 04:46:02.340665 03e00000 ################################################################
10337 04:46:02.340810
10338 04:46:02.592155 03e80000 ################################################################
10339 04:46:02.592315
10340 04:46:02.844029 03f00000 ################################################################
10341 04:46:02.844195
10342 04:46:03.089656 03f80000 ################################################################
10343 04:46:03.089802
10344 04:46:03.334994 04000000 ################################################################
10345 04:46:03.335147
10346 04:46:03.579314 04080000 ################################################################
10347 04:46:03.579448
10348 04:46:03.762658 04100000 ################################################# done.
10349 04:46:03.762824
10350 04:46:03.765861 The bootfile was 68554050 bytes long.
10351 04:46:03.766012
10352 04:46:03.769115 Sending tftp read request... done.
10353 04:46:03.769234
10354 04:46:03.772368 Waiting for the transfer...
10355 04:46:03.772486
10356 04:46:03.772557 00000000 # done.
10357 04:46:03.772623
10358 04:46:03.782276 Command line loaded dynamically from TFTP file: 12699819/tftp-deploy-qmxjd096/kernel/cmdline
10359 04:46:03.782408
10360 04:46:03.796018 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10361 04:46:03.796150
10362 04:46:03.796224 Loading FIT.
10363 04:46:03.796286
10364 04:46:03.799344 Image ramdisk-1 has 56456229 bytes.
10365 04:46:03.799430
10366 04:46:03.802551 Image fdt-1 has 47278 bytes.
10367 04:46:03.802638
10368 04:46:03.806036 Image kernel-1 has 12048508 bytes.
10369 04:46:03.806121
10370 04:46:03.812310 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10371 04:46:03.815834
10372 04:46:03.832256 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10373 04:46:03.832372
10374 04:46:03.835925 Choosing best match conf-1 for compat google,spherion-rev2.
10375 04:46:03.840939
10376 04:46:03.845787 Connected to device vid:did:rid of 1ae0:0028:00
10377 04:46:03.852890
10378 04:46:03.855853 tpm_get_response: command 0x17b, return code 0x0
10379 04:46:03.855939
10380 04:46:03.859284 ec_init: CrosEC protocol v3 supported (256, 248)
10381 04:46:03.864654
10382 04:46:03.867832 tpm_cleanup: add release locality here.
10383 04:46:03.867918
10384 04:46:03.867985 Shutting down all USB controllers.
10385 04:46:03.871122
10386 04:46:03.871208 Removing current net device
10387 04:46:03.871277
10388 04:46:03.878142 Exiting depthcharge with code 4 at timestamp: 79687024
10389 04:46:03.878232
10390 04:46:03.881234 LZMA decompressing kernel-1 to 0x821a6718
10391 04:46:03.881327
10392 04:46:03.884682 LZMA decompressing kernel-1 to 0x40000000
10393 04:46:05.382842
10394 04:46:05.383002 jumping to kernel
10395 04:46:05.383535 end: 2.2.4 bootloader-commands (duration 00:00:52) [common]
10396 04:46:05.383634 start: 2.2.5 auto-login-action (timeout 00:03:33) [common]
10397 04:46:05.383713 Setting prompt string to ['Linux version [0-9]']
10398 04:46:05.383783 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10399 04:46:05.383851 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10400 04:46:05.464760
10401 04:46:05.468141 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10402 04:46:05.471727 start: 2.2.5.1 login-action (timeout 00:03:33) [common]
10403 04:46:05.471820 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10404 04:46:05.471894 Setting prompt string to []
10405 04:46:05.471973 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10406 04:46:05.472048 Using line separator: #'\n'#
10407 04:46:05.472107 No login prompt set.
10408 04:46:05.472170 Parsing kernel messages
10409 04:46:05.472226 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10410 04:46:05.472325 [login-action] Waiting for messages, (timeout 00:03:33)
10411 04:46:05.491605 [ 0.000000] Linux version 6.1.75-cip14-rt8 (KernelCI@build-j97480-arm64-gcc-10-defconfig-arm64-chromebook-6n26j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024
10412 04:46:05.494682 [ 0.000000] random: crng init done
10413 04:46:05.501434 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10414 04:46:05.504637 [ 0.000000] efi: UEFI not found.
10415 04:46:05.511146 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10416 04:46:05.517559 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10417 04:46:05.527729 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10418 04:46:05.537850 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10419 04:46:05.544043 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10420 04:46:05.550837 [ 0.000000] printk: bootconsole [mtk8250] enabled
10421 04:46:05.557284 [ 0.000000] NUMA: No NUMA configuration found
10422 04:46:05.563942 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10423 04:46:05.567162 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10424 04:46:05.570617 [ 0.000000] Zone ranges:
10425 04:46:05.577271 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10426 04:46:05.580715 [ 0.000000] DMA32 empty
10427 04:46:05.587189 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10428 04:46:05.590763 [ 0.000000] Movable zone start for each node
10429 04:46:05.593720 [ 0.000000] Early memory node ranges
10430 04:46:05.600573 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10431 04:46:05.606816 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10432 04:46:05.613799 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10433 04:46:05.619985 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10434 04:46:05.626773 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10435 04:46:05.633631 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10436 04:46:05.689516 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10437 04:46:05.696034 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10438 04:46:05.702793 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10439 04:46:05.706047 [ 0.000000] psci: probing for conduit method from DT.
10440 04:46:05.712867 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10441 04:46:05.715976 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10442 04:46:05.722714 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10443 04:46:05.725969 [ 0.000000] psci: SMC Calling Convention v1.2
10444 04:46:05.732453 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10445 04:46:05.735821 [ 0.000000] Detected VIPT I-cache on CPU0
10446 04:46:05.742621 [ 0.000000] CPU features: detected: GIC system register CPU interface
10447 04:46:05.749095 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10448 04:46:05.755837 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10449 04:46:05.762391 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10450 04:46:05.768935 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10451 04:46:05.778867 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10452 04:46:05.782313 [ 0.000000] alternatives: applying boot alternatives
10453 04:46:05.789135 [ 0.000000] Fallback order for Node 0: 0
10454 04:46:05.795821 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10455 04:46:05.798880 [ 0.000000] Policy zone: Normal
10456 04:46:05.811926 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10457 04:46:05.821918 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10458 04:46:05.833812 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10459 04:46:05.843721 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10460 04:46:05.850470 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10461 04:46:05.853937 <6>[ 0.000000] software IO TLB: area num 8.
10462 04:46:05.910378 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10463 04:46:06.059244 <6>[ 0.000000] Memory: 7912060K/8385536K available (18048K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 616K bss, 440708K reserved, 32768K cma-reserved)
10464 04:46:06.065839 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10465 04:46:06.072437 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10466 04:46:06.076188 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10467 04:46:06.082423 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10468 04:46:06.089007 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10469 04:46:06.092329 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10470 04:46:06.102575 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10471 04:46:06.109243 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10472 04:46:06.115550 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10473 04:46:06.122812 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10474 04:46:06.125584 <6>[ 0.000000] GICv3: 608 SPIs implemented
10475 04:46:06.128995 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10476 04:46:06.135597 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10477 04:46:06.138696 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10478 04:46:06.145988 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10479 04:46:06.158588 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10480 04:46:06.168752 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10481 04:46:06.178908 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10482 04:46:06.185771 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10483 04:46:06.198961 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10484 04:46:06.205929 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10485 04:46:06.212457 <6>[ 0.009181] Console: colour dummy device 80x25
10486 04:46:06.222522 <6>[ 0.013903] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10487 04:46:06.228736 <6>[ 0.024346] pid_max: default: 32768 minimum: 301
10488 04:46:06.232609 <6>[ 0.029218] LSM: Security Framework initializing
10489 04:46:06.238976 <6>[ 0.034117] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10490 04:46:06.248925 <6>[ 0.041930] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10491 04:46:06.255619 <6>[ 0.051232] cblist_init_generic: Setting adjustable number of callback queues.
10492 04:46:06.262473 <6>[ 0.058723] cblist_init_generic: Setting shift to 3 and lim to 1.
10493 04:46:06.272264 <6>[ 0.065100] cblist_init_generic: Setting adjustable number of callback queues.
10494 04:46:06.275446 <6>[ 0.072527] cblist_init_generic: Setting shift to 3 and lim to 1.
10495 04:46:06.282422 <6>[ 0.079005] rcu: Hierarchical SRCU implementation.
10496 04:46:06.288856 <6>[ 0.079007] rcu: Max phase no-delay instances is 1000.
10497 04:46:06.292582 <6>[ 0.079032] printk: bootconsole [mtk8250] printing thread started
10498 04:46:06.300880 <6>[ 0.097373] EFI services will not be available.
10499 04:46:06.304157 <6>[ 0.097571] smp: Bringing up secondary CPUs ...
10500 04:46:06.311095 <6>[ 0.097884] Detected VIPT I-cache on CPU1
10501 04:46:06.317698 <6>[ 0.097955] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10502 04:46:06.324251 <6>[ 0.097989] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10503 04:46:06.334271 <6>[ 0.125828] Detected VIPT I-cache on CPU2
10504 04:46:06.340464 <6>[ 0.125875] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10505 04:46:06.350358 <6>[ 0.125890] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10506 04:46:06.354003 <6>[ 0.126147] Detected VIPT I-cache on CPU3
10507 04:46:06.360642 <6>[ 0.126193] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10508 04:46:06.366877 <6>[ 0.126207] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10509 04:46:06.370594 <6>[ 0.126514] CPU features: detected: Spectre-v4
10510 04:46:06.377210 <6>[ 0.126520] CPU features: detected: Spectre-BHB
10511 04:46:06.380583 <6>[ 0.126526] Detected PIPT I-cache on CPU4
10512 04:46:06.387083 <6>[ 0.126584] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10513 04:46:06.393475 <6>[ 0.126600] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10514 04:46:06.400334 <6>[ 0.126888] Detected PIPT I-cache on CPU5
10515 04:46:06.406809 <6>[ 0.126948] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10516 04:46:06.413183 <6>[ 0.126964] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10517 04:46:06.416666 <6>[ 0.127237] Detected PIPT I-cache on CPU6
10518 04:46:06.423297 <6>[ 0.127301] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10519 04:46:06.430137 <6>[ 0.127317] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10520 04:46:06.438742 <6>[ 0.127604] Detected PIPT I-cache on CPU7
10521 04:46:06.445286 <6>[ 0.127668] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10522 04:46:06.451525 <6>[ 0.127684] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10523 04:46:06.455155 <6>[ 0.127730] smp: Brought up 1 node, 8 CPUs
10524 04:46:06.461522 <6>[ 0.127735] SMP: Total of 8 processors activated.
10525 04:46:06.465171 <6>[ 0.127737] CPU features: detected: 32-bit EL0 Support
10526 04:46:06.474753 <6>[ 0.127739] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10527 04:46:06.481376 <6>[ 0.127742] CPU features: detected: Common not Private translations
10528 04:46:06.488060 <6>[ 0.127743] CPU features: detected: CRC32 instructions
10529 04:46:06.491351 <6>[ 0.127746] CPU features: detected: RCpc load-acquire (LDAPR)
10530 04:46:06.498103 <6>[ 0.127747] CPU features: detected: LSE atomic instructions
10531 04:46:06.504936 <6>[ 0.127749] CPU features: detected: Privileged Access Never
10532 04:46:06.511173 <6>[ 0.127750] CPU features: detected: RAS Extension Support
10533 04:46:06.517998 <6>[ 0.127753] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10534 04:46:06.521270 <6>[ 0.127825] CPU: All CPU(s) started at EL2
10535 04:46:06.528433 <6>[ 0.127827] alternatives: applying system-wide alternatives
10536 04:46:06.531251 <6>[ 0.140901] devtmpfs: initialized
10537 04:46:06.541301 <6>[ 0.147161] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10538 04:46:06.548069 <6>[ 0.147175] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10539 04:46:06.579926 ���ځ��r����������ɱ���ɕ�J��ѥ���镑������ɱ��Չ���ѕ�5)�<6>[ 0.375806] printk: console [ttyS0<] printing thread started
10540 04:46:06.583107 6><6>[ 0.375839] printk: console [ttyS0] enabled
10541 04:46:06.590039 [ 0.149221] DMI not present or invalid.
10542 04:46:06.593207 <6>[ 0.375842] printk: bootconsole [mtk8250] disabled
10543 04:46:06.599885 <6>[ 0.390169] printk: bootconsole [mtk8250] printing thread stopped
10544 04:46:06.606317 <6>[ 0.391525] SuperH (H)SCI(F) driver initialized
10545 04:46:06.609664 <6>[ 0.392014] msm_serial: driver initialized
10546 04:46:06.619948 <6>[ 0.396654] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10547 04:46:06.626368 <6>[ 0.396682] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10548 04:46:06.635970 <6>[ 0.396711] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10549 04:46:06.642727 <6>[ 0.396741] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10550 04:46:06.652044 <6>[ 0.396761] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10551 04:46:06.662966 <6>[ 0.396789] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10552 04:46:06.675859 <6>[ 0.396816] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10553 04:46:06.687126 <6>[ 0.396947] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10554 04:46:06.692052 <6>[ 0.396976] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10555 04:46:06.692140 <6>[ 0.406176] loop: module loaded
10556 04:46:06.700903 <6>[ 0.408792] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10557 04:46:06.706955 <4>[ 0.433507] mtk-pmic-keys: Failed to locate of_node [id: -1]
10558 04:46:06.707041 <6>[ 0.434602] megasas: 07.719.03.00-rc1
10559 04:46:06.713960 <6>[ 0.446612] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10560 04:46:06.717434 <6>[ 0.447429] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10561 04:46:06.724168 <6>[ 0.458811] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10562 04:46:06.737084 <6>[ 0.512106] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10563 04:46:08.861986 <6>[ 2.655226] Freeing initrd memory: 55128K
10564 04:46:08.868864 <6>[ 2.661268] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10565 04:46:08.872054 <6>[ 2.665938] tun: Universal TUN/TAP device driver, 1.6
10566 04:46:08.875408 <6>[ 2.666703] thunder_xcv, ver 1.0
10567 04:46:08.878657 <6>[ 2.666722] thunder_bgx, ver 1.0
10568 04:46:08.881934 <6>[ 2.666735] nicpf, ver 1.0
10569 04:46:08.891742 <6>[ 2.667820] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10570 04:46:08.895118 <6>[ 2.667823] hns3: Copyright (c) 2017 Huawei Corporation.
10571 04:46:08.898584 <6>[ 2.667853] hclge is initializing
10572 04:46:08.905247 <6>[ 2.667867] e1000: Intel(R) PRO/1000 Network Driver
10573 04:46:08.911703 <6>[ 2.667869] e1000: Copyright (c) 1999-2006 Intel Corporation.
10574 04:46:08.915149 <6>[ 2.667885] e1000e: Intel(R) PRO/1000 Network Driver
10575 04:46:08.922646 <6>[ 2.667886] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10576 04:46:08.925984 <6>[ 2.667905] igb: Intel(R) Gigabit Ethernet Network Driver
10577 04:46:08.932916 <6>[ 2.667907] igb: Copyright (c) 2007-2014 Intel Corporation.
10578 04:46:08.939553 <6>[ 2.667920] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10579 04:46:08.946255 <6>[ 2.667922] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10580 04:46:08.950191 <6>[ 2.668213] sky2: driver version 1.30
10581 04:46:08.956762 <6>[ 2.669290] VFIO - User Level meta-driver version: 0.3
10582 04:46:08.960018 <6>[ 2.672129] usbcore: registered new interface driver usb-storage
10583 04:46:08.966785 <6>[ 2.672309] usbcore: registered new device driver onboard-usb-hub
10584 04:46:08.973169 <6>[ 2.675115] mt6397-rtc mt6359-rtc: registered as rtc0
10585 04:46:08.983326 <6>[ 2.675264] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-04T04:45:31 UTC (1707021931)
10586 04:46:08.986636 <6>[ 2.675883] i2c_dev: i2c /dev entries driver
10587 04:46:08.993028 <6>[ 2.683049] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10588 04:46:08.999738 <6>[ 2.698053] cpu cpu0: EM: created perf domain
10589 04:46:09.003124 <6>[ 2.698367] cpu cpu4: EM: created perf domain
10590 04:46:09.009490 <6>[ 2.701651] sdhci: Secure Digital Host Controller Interface driver
10591 04:46:09.016010 <6>[ 2.701653] sdhci: Copyright(c) Pierre Ossman
10592 04:46:09.019422 <6>[ 2.702010] Synopsys Designware Multimedia Card Interface Driver
10593 04:46:09.025904 <6>[ 2.702394] sdhci-pltfm: SDHCI platform and OF driver helper
10594 04:46:09.029370 <6>[ 2.707082] mmc0: CQHCI version 5.10
10595 04:46:09.036091 <6>[ 2.712738] ledtrig-cpu: registered to indicate activity on CPUs
10596 04:46:09.042498 <6>[ 2.713530] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10597 04:46:09.049072 <6>[ 2.713809] usbcore: registered new interface driver usbhid
10598 04:46:09.052711 <6>[ 2.713811] usbhid: USB HID core driver
10599 04:46:09.062252 <6>[ 2.713946] spi_master spi0: will run message pump with realtime priority
10600 04:46:09.072673 <6>[ 2.744022] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10601 04:46:09.085555 <6>[ 2.746643] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10602 04:46:09.092283 <6>[ 2.747759] cros-ec-spi spi0.0: Chrome EC device registered
10603 04:46:09.102217 <6>[ 2.761887] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10604 04:46:09.108609 <6>[ 2.762823] NET: Registered PF_PACKET protocol family
10605 04:46:09.112069 <6>[ 2.762898] 9pnet: Installing 9P2000 support
10606 04:46:09.115521 <5>[ 2.762940] Key type dns_resolver registered
10607 04:46:09.121934 <6>[ 2.763473] registered taskstats version 1
10608 04:46:09.125519 <5>[ 2.763494] Loading compiled-in X.509 certificates
10609 04:46:09.135298 <4>[ 2.778391] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 04:46:09.145033 <4>[ 2.778491] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 04:46:09.154926 <3>[ 2.778495] debugfs: File 'uA_load' in directory '/' already present!
10612 04:46:09.161823 <3>[ 2.778500] debugfs: File 'min_uV' in directory '/' already present!
10613 04:46:09.167953 <3>[ 2.778501] debugfs: File 'max_uV' in directory '/' already present!
10614 04:46:09.174625 <3>[ 2.778503] debugfs: File 'constraint_flags' in directory '/' already present!
10615 04:46:09.181493 <3>[ 2.779790] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10616 04:46:09.187992 <6>[ 2.783072] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10617 04:46:09.194645 <6>[ 2.783709] xhci-mtk 11200000.usb: xHCI Host Controller
10618 04:46:09.201359 <6>[ 2.783727] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10619 04:46:09.211154 <6>[ 2.783943] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10620 04:46:09.217688 <6>[ 2.783994] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10621 04:46:09.224585 <6>[ 2.784110] xhci-mtk 11200000.usb: xHCI Host Controller
10622 04:46:09.231027 <6>[ 2.784117] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10623 04:46:09.237442 <6>[ 2.784125] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10624 04:46:09.240886 <6>[ 2.784561] hub 1-0:1.0: USB hub found
10625 04:46:09.247239 <6>[ 2.784579] hub 1-0:1.0: 1 port detected
10626 04:46:09.254068 <6>[ 2.784736] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10627 04:46:09.257279 <6>[ 2.785100] hub 2-0:1.0: USB hub found
10628 04:46:09.264081 <6>[ 2.785108] hub 2-0:1.0: 1 port detected
10629 04:46:09.267515 <6>[ 2.788075] mtk-msdc 11f70000.mmc: Got CD GPIO
10630 04:46:09.273691 <6>[ 2.796295] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10631 04:46:09.283590 <6>[ 2.796301] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10632 04:46:09.290617 <4>[ 2.796384] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10633 04:46:09.300053 <6>[ 2.796890] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10634 04:46:09.306596 <6>[ 2.796892] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10635 04:46:09.316836 <6>[ 2.797170] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10636 04:46:09.323427 <6>[ 2.797178] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10637 04:46:09.330173 <6>[ 2.797180] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10638 04:46:09.339903 <6>[ 2.797183] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10639 04:46:09.349857 <6>[ 2.798306] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10640 04:46:09.356687 <6>[ 2.798322] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10641 04:46:09.366791 <6>[ 2.798325] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10642 04:46:09.372998 <6>[ 2.798330] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10643 04:46:09.383412 <6>[ 2.798333] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10644 04:46:09.389815 <6>[ 2.798337] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10645 04:46:09.399820 <6>[ 2.798341] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10646 04:46:09.406575 <6>[ 2.798344] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10647 04:46:09.416347 <6>[ 2.798348] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10648 04:46:09.422703 <6>[ 2.798352] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10649 04:46:09.432874 <6>[ 2.798355] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10650 04:46:09.439470 <6>[ 2.798359] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10651 04:46:09.449412 <6>[ 2.798363] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10652 04:46:09.456370 <6>[ 2.798366] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10653 04:46:09.466038 <6>[ 2.798371] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10654 04:46:09.472865 <6>[ 2.798675] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10655 04:46:09.479057 <6>[ 2.799174] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10656 04:46:09.486173 <6>[ 2.799386] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10657 04:46:09.492357 <6>[ 2.799644] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10658 04:46:09.499143 <6>[ 2.799881] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10659 04:46:09.509264 <6>[ 2.800033] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10660 04:46:09.515981 <6>[ 2.800043] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10661 04:46:09.525612 <6>[ 2.800046] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10662 04:46:09.535450 <6>[ 2.800049] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10663 04:46:09.545227 <6>[ 2.800053] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10664 04:46:09.555166 <6>[ 2.800056] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10665 04:46:09.562022 <6>[ 2.800059] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10666 04:46:09.571987 <6>[ 2.800062] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10667 04:46:09.582096 <6>[ 2.800064] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10668 04:46:09.592025 <6>[ 2.800068] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10669 04:46:09.601751 <6>[ 2.800071] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10670 04:46:09.612041 <6>[ 2.801105] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10671 04:46:09.615298 <6>[ 2.812605] mmc0: Command Queue Engine enabled
10672 04:46:09.621748 <6>[ 2.812614] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10673 04:46:09.625246 <6>[ 2.813115] mmcblk0: mmc0:0001 DA4128 116 GiB
10674 04:46:09.631783 <6>[ 2.816146] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10675 04:46:09.638539 <6>[ 2.817047] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10676 04:46:09.641575 <6>[ 2.817682] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10677 04:46:09.648572 <6>[ 2.818193] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10678 04:46:09.655082 <6>[ 3.167576] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10679 04:46:09.661741 <6>[ 3.194034] hub 2-1:1.0: USB hub found
10680 04:46:09.665174 <6>[ 3.194326] hub 2-1:1.0: 3 ports detected
10681 04:46:09.668091 <6>[ 3.195846] hub 2-1:1.0: USB hub found
10682 04:46:09.671774 <6>[ 3.196130] hub 2-1:1.0: 3 ports detected
10683 04:46:09.678184 <6>[ 3.315327] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10684 04:46:09.684840 <6>[ 3.468168] hub 1-1:1.0: USB hub found
10685 04:46:09.688272 <6>[ 3.468576] hub 1-1:1.0: 4 ports detected
10686 04:46:09.691648 <6>[ 3.472130] hub 1-1:1.0: USB hub found
10687 04:46:09.694970 <6>[ 3.472542] hub 1-1:1.0: 4 ports detected
10688 04:46:09.757488 <6>[ 3.547713] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10689 04:46:09.993370 <6>[ 3.783469] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10690 04:46:10.113852 <6>[ 3.910202] hub 1-1.4:1.0: USB hub found
10691 04:46:10.117605 <6>[ 3.910492] hub 1-1.4:1.0: 2 ports detected
10692 04:46:10.120615 <6>[ 3.912820] hub 1-1.4:1.0: USB hub found
10693 04:46:10.127506 <6>[ 3.913136] hub 1-1.4:1.0: 2 ports detected
10694 04:46:10.409196 <6>[ 4.199457] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10695 04:46:10.593573 <6>[ 4.383429] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10696 04:46:21.305499 <6>[ 15.104520] ALSA device list:
10697 04:46:21.312250 <6>[ 15.104541] No soundcards found.
10698 04:46:21.315628 <6>[ 15.108990] Freeing unused kernel memory: 8448K
10699 04:46:21.318731 <6>[ 15.109139] Run /init as init process
10700 04:46:21.352750 <6>[ 15.148432] NET: Registered PF_INET6 protocol family
10701 04:46:21.355940 <6>[ 15.149415] Segment Routing with IPv6
10702 04:46:21.362692 <6>[ 15.149432] In-situ OAM (IOAM) with IPv6
10703 04:46:21.362777
10704 04:46:21.389114 Welcome to [1mDebian GNU/Linu<30>[ 15.164944] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10705 04:46:21.392403 <30>[ 15.165567] systemd[1]: Detected architecture arm64.
10706 04:46:21.395706 x 11 (bullseye)[0m!
10707 04:46:21.395791
10708 04:46:21.412582 <30>[ 15.207401] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10709 04:46:21.508027 <30>[ 15.302062] systemd[1]: Queued start job for default target Graphical Interface.
10710 04:46:21.533314 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 15.328253] systemd[1]: Created slice system-getty.slice.
10711 04:46:21.536288 m-getty.slice[0m.
10712 04:46:21.560341 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 15.352029] systemd[1]: Created slice system-modprobe.slice.
10713 04:46:21.560428 m-modprobe.slice[0m.
10714 04:46:21.584454 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 15.376296] systemd[1]: Created slice system-serial\x2dgetty.slice.
10715 04:46:21.587833 m-serial\x2dgetty.slice[0m.
10716 04:46:21.605473 [[0;32m OK [0m] Created slic<30>[ 15.400527] systemd[1]: Created slice User and Session Slice.
10717 04:46:21.608945 e [0;1;39mUser and Session Slice[0m.
10718 04:46:21.632764 [[0;32m OK [0m] Started [0;<30>[ 15.424253] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10719 04:46:21.635914 1;39mDispatch Password …ts to Console Directory Watch[0m.
10720 04:46:21.660551 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 15.452203] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10721 04:46:21.663709 sword R…uests to Wall Directory Watch[0m.
10722 04:46:21.691597 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 15.479977] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10723 04:46:21.698626 <30>[ 15.480245] systemd[1]: Reached target Local Encrypted Volumes.
10724 04:46:21.701518 l Encrypted Volumes[0m.
10725 04:46:21.720995 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 15.515943] systemd[1]: Reached target Paths.
10726 04:46:21.721086 s[0m.
10727 04:46:21.740865 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 15.535876] systemd[1]: Reached target Remote File Systems.
10728 04:46:21.744149 te File Systems[0m.
10729 04:46:21.764694 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 15.559818] systemd[1]: Reached target Slices.
10730 04:46:21.764780 es[0m.
10731 04:46:21.784280 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 15.579528] systemd[1]: Reached target Swap.
10732 04:46:21.784367 [0m.
10733 04:46:21.805573 [[0;32m OK [0m] Listening on<30>[ 15.600463] systemd[1]: Listening on initctl Compatibility Named Pipe.
10734 04:46:21.812060 [0;1;39minitctl Compatibility Named Pipe[0m.
10735 04:46:21.821843 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 15.615884] systemd[1]: Listening on Journal Audit Socket.
10736 04:46:21.824874 l Audit Socket[0m.
10737 04:46:21.847939 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 15.640095] systemd[1]: Listening on Journal Socket (/dev/log).
10738 04:46:21.848052 l Socket (/dev/log)[0m.
10739 04:46:21.869670 [[0;32m OK [0m] Listening on<30>[ 15.664683] systemd[1]: Listening on Journal Socket.
10740 04:46:21.872586 [0;1;39mJournal Socket[0m.
10741 04:46:21.889116 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 15.684133] systemd[1]: Listening on udev Control Socket.
10742 04:46:21.892362 ontrol Socket[0m.
10743 04:46:21.913183 [[0;32m OK [0m] Listening on<30>[ 15.708477] systemd[1]: Listening on udev Kernel Socket.
10744 04:46:21.916871 [0;1;39mudev Kernel Socket[0m.
10745 04:46:21.975860 Mounting [0;1;39mHuge Pages File Syste<30>[ 15.767795] systemd[1]: Mounting Huge Pages File System...
10746 04:46:21.975966 m[0m...
10747 04:46:21.999568 Mounting [0;1;39mPOSIX Message Queue F<30>[ 15.791444] systemd[1]: Mounting POSIX Message Queue File System...
10748 04:46:21.999715 ile System[0m...
10749 04:46:22.027758 Mounting [0;1;39mKernel Debug File Sys<30>[ 15.819509] systemd[1]: Mounting Kernel Debug File System...
10750 04:46:22.027858 tem[0m...
10751 04:46:22.048049 <30>[ 15.839898] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10752 04:46:22.061321 Starting [0;1;39mCreate list of st…o<30>[ 15.844039] systemd[1]: Starting Create list of static device nodes for the current kernel...
10753 04:46:22.064573 des for the current kernel[0m...
10754 04:46:22.091892 Starting [0;1;39mLoad Kernel Module co<30>[ 15.883685] systemd[1]: Starting Load Kernel Module configfs...
10755 04:46:22.091985 nfigfs[0m...
10756 04:46:22.112601 Starting [0;1;39mLoad Kernel Module dr<30>[ 15.907410] systemd[1]: Starting Load Kernel Module drm...
10757 04:46:22.115414 m[0m...
10758 04:46:22.136173 <30>[ 15.927662] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10759 04:46:22.142584 <30>[ 15.933264] systemd[1]: Starting Journal Service...
10760 04:46:22.146004 Starting [0;1;39mJournal Service[0m...
10761 04:46:22.166712 Startin<30>[ 15.962051] systemd[1]: Starting Load Kernel Modules...
10762 04:46:22.169828 g [0;1;39mLoad Kernel Modules[0m...
10763 04:46:22.195798 Startin<30>[ 15.989823] systemd[1]: Starting Remount Root and Kernel File Systems...
10764 04:46:22.202184 g [0;1;39mRemount Root and Kernel File Systems[0m...
10765 04:46:22.222698 Startin<30>[ 16.017898] systemd[1]: Starting Coldplug All udev Devices...
10766 04:46:22.226147 g [0;1;39mColdplug All udev Devices[0m...
10767 04:46:22.244200 [[0;32m OK [<30>[ 16.042575] systemd[1]: Started Journal Service.
10768 04:46:22.250607 0m] Started [0;1;39mJournal Service[0m.
10769 04:46:22.267390 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10770 04:46:22.286239 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10771 04:46:22.301830 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10772 04:46:22.322351 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10773 04:46:22.338841 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10774 04:46:22.354593 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10775 04:46:22.373699 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10776 04:46:22.397242 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10777 04:46:22.416902 See 'systemctl status systemd-remount-fs.service' for details.
10778 04:46:22.464206 Mounting [0;1;39mKernel Configuration File System[0m...
10779 04:46:22.490368 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10780 04:46:22.512075 <46>[ 16.305887] systemd-journald[190]: Received client request to flush runtime journal.
10781 04:46:22.515171 Starting [0;1;39mLoad/Save Random Seed[0m...
10782 04:46:22.536505 Starting [0;1;39mApply Kernel Variables[0m...
10783 04:46:22.560965 Starting [0;1;39mCreate System Users[0m...
10784 04:46:22.583616 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10785 04:46:22.601816 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10786 04:46:22.621846 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10787 04:46:22.634737 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10788 04:46:22.650839 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10789 04:46:22.666302 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10790 04:46:22.710054 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10791 04:46:22.728931 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10792 04:46:22.741140 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10793 04:46:22.760940 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10794 04:46:22.793486 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10795 04:46:22.824811 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10796 04:46:22.848430 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10797 04:46:22.867392 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10798 04:46:22.919480 Starting [0;1;39mNetwork Time Synchronization[0m...
10799 04:46:22.938187 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10800 04:46:22.987815 [[0;32m OK [<6>[ 16.781073] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10801 04:46:22.997785 0m] Started [0;<6>[ 16.781116] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10802 04:46:23.007423 1;39mNetwork Tim<6>[ 16.781122] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10803 04:46:23.010824 e Synchronization[0m.
10804 04:46:23.033862 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10805 04:46:23.055749 <4>[ 16.848595] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10806 04:46:23.062482 <3>[ 16.849043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10807 04:46:23.072298 <3>[ 16.849051] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10808 04:46:23.078817 <3>[ 16.849055] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10809 04:46:23.085754 <4>[ 16.868970] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10810 04:46:23.095402 <3>[ 16.877192] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10811 04:46:23.101852 <3>[ 16.877224] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10812 04:46:23.112171 <3>[ 16.877228] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10813 04:46:23.118437 <3>[ 16.877235] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10814 04:46:23.128519 <3>[ 16.877239] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10815 04:46:23.134925 <3>[ 16.885930] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10816 04:46:23.141499 <3>[ 16.895576] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10817 04:46:23.151561 [[0;32m OK [<3>[ 16.895594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10818 04:46:23.161360 <3>[ 16.895598] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10819 04:46:23.168342 <3>[ 16.904013] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10820 04:46:23.175468 <3>[ 16.904033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10821 04:46:23.185328 <3>[ 16.904037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10822 04:46:23.191723 <3>[ 16.904043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10823 04:46:23.202543 0m] Finished [0<3>[ 16.904046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10824 04:46:23.209443 <6>[ 16.905649] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10825 04:46:23.219178 ;1;39mUpdate UTM<3>[ 16.905751] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10826 04:46:23.226002 <6>[ 16.935800] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10827 04:46:23.232427 P about System B<6>[ 16.935820] pci_bus 0000:00: root bus resource [bus 00-ff]
10828 04:46:23.239039 <6>[ 16.935828] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10829 04:46:23.249467 <6>[ 16.935833] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10830 04:46:23.256749 <6>[ 16.935890] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10831 04:46:23.263065 <6>[ 16.935916] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10832 04:46:23.270130 <6>[ 16.936012] pci 0000:00:00.0: supports D1 D2
10833 04:46:23.276323 oot/Shutdown[0m<6>[ 16.936015] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10834 04:46:23.286308 <4>[ 16.951943] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10835 04:46:23.289798 <4>[ 16.951943] Fallback method does not support PEC.
10836 04:46:23.299700 <6>[ 16.955326] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10837 04:46:23.299822 .
10838 04:46:23.309993 <6>[ 16.959533] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10839 04:46:23.316680 <6>[ 16.959968] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10840 04:46:23.323575 <6>[ 16.959996] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10841 04:46:23.329958 <6>[ 16.960013] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10842 04:46:23.336802 <6>[ 16.960028] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10843 04:46:23.343641 <6>[ 16.960139] pci 0000:01:00.0: supports D1 D2
10844 04:46:23.350716 <6>[ 16.960140] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10845 04:46:23.353995 <6>[ 16.960337] mc: Linux media interface: v0.10
10846 04:46:23.364266 <6>[ 16.965420] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10847 04:46:23.371381 <3>[ 16.975617] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10848 04:46:23.377781 <6>[ 16.980018] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10849 04:46:23.387550 <6>[ 16.980092] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10850 04:46:23.394941 <6>[ 16.980100] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10851 04:46:23.401840 <6>[ 16.980117] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10852 04:46:23.411860 <6>[ 16.980135] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10853 04:46:23.418592 <6>[ 16.980167] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10854 04:46:23.425448 <6>[ 16.980185] pci 0000:00:00.0: PCI bridge to [bus 01]
10855 04:46:23.431788 <6>[ 16.980196] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10856 04:46:23.439245 [[0;32m OK [<6>[ 16.982547] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10857 04:46:23.446686 <6>[ 16.984215] usbcore: registered new device driver r8152-cfgselector
10858 04:46:23.456982 0m] Created slic<6>[ 16.985152] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10859 04:46:23.463786 <6>[ 17.007248] pcieport 0000:00:00.0: PME: Signaling with IRQ 281
10860 04:46:23.470652 e [0;1;39msyste<6>[ 17.009235] videodev: Linux video capture interface: v2.00
10861 04:46:23.477301 <3>[ 17.010696] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10862 04:46:23.488238 m-systemd\x2dbac<6>[ 17.012858] pcieport 0000:00:00.0: AER: enabled with IRQ 281
10863 04:46:23.494639 <6>[ 17.027861] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10864 04:46:23.504524 klight.slice[0m<3>[ 17.056595] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10865 04:46:23.504613 .
10866 04:46:23.507901 <6>[ 17.063311] remoteproc remoteproc0: scp is available
10867 04:46:23.514875 <6>[ 17.063400] remoteproc remoteproc0: powering up scp
10868 04:46:23.521419 <6>[ 17.063409] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10869 04:46:23.528104 [[0;32m OK [<6>[ 17.063433] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10870 04:46:23.535151 <6>[ 17.074321] Bluetooth: Core ver 2.22
10871 04:46:23.542393 0m] Reached targ<6>[ 17.074399] NET: Registered PF_BLUETOOTH protocol family
10872 04:46:23.549321 et [0;1;39mSyst<6>[ 17.074401] Bluetooth: HCI device and connection manager initialized
10873 04:46:23.552232 <6>[ 17.074426] Bluetooth: HCI socket layer initialized
10874 04:46:23.559548 <6>[ 17.074434] Bluetooth: L2CAP socket layer initialized
10875 04:46:23.563008 <6>[ 17.074453] Bluetooth: SCO socket layer initialized
10876 04:46:23.573063 em Time Set[0m.<3>[ 17.112777] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10877 04:46:23.582966 <6>[ 17.124853] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10878 04:46:23.592928 <6>[ 17.139753] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10879 04:46:23.599248 <6>[ 17.140070] usbcore: registered new interface driver uvcvideo
10880 04:46:23.609276 <3>[ 17.145554] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 04:46:23.615752 <3>[ 17.168994] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 04:46:23.622373 <6>[ 17.174441] usbcore: registered new interface driver btusb
10883 04:46:23.632657 <4>[ 17.174918] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10884 04:46:23.639046 <3>[ 17.174929] Bluetooth: hci0: Failed to load firmware file (-2)
10885 04:46:23.645821 <3>[ 17.174933] Bluetooth: hci0: Failed to set up firmware (-2)
10886 04:46:23.655698 <4>[ 17.174937] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10887 04:46:23.662082 <6>[ 17.177435] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10888 04:46:23.672163 <6>[ 17.188836] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10889 04:46:23.678996 <6>[ 17.188838] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10890 04:46:23.685317 <6>[ 17.188858] remoteproc remoteproc0: remote processor scp is now up
10891 04:46:23.691984 <6>[ 17.200987] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10892 04:46:23.702016 <3>[ 17.205807] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 04:46:23.708738 <6>[ 17.217063] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10894 04:46:23.718481 <5>[ 17.217573] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10895 04:46:23.725032 <6>[ 17.218299] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10896 04:46:23.735073 <4>[ 17.223928] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10897 04:46:23.741607 <4>[ 17.223942] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10898 04:46:23.748289 <5>[ 17.228756] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10899 04:46:23.758336 <5>[ 17.229203] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10900 04:46:23.768150 <4>[ 17.229268] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10901 04:46:23.771353 <6>[ 17.229274] cfg80211: failed to load regulatory.db
10902 04:46:23.781386 <3>[ 17.256173] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 04:46:23.790960 <3>[ 17.257022] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10904 04:46:23.797590 <3>[ 17.269422] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 04:46:23.801237 <6>[ 17.307356] r8152 2-1.3:1.0 eth0: v1.12.13
10906 04:46:23.807422 <6>[ 17.307412] usbcore: registered new interface driver r8152
10907 04:46:23.814424 <6>[ 17.327144] usbcore: registered new interface driver cdc_ether
10908 04:46:23.820847 <6>[ 17.338054] usbcore: registered new interface driver r8153_ecm
10909 04:46:23.827756 <6>[ 17.341624] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10910 04:46:23.834099 <6>[ 17.341741] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10911 04:46:23.840899 <6>[ 17.359217] mt7921e 0000:01:00.0: ASIC revision: 79610010
10912 04:46:23.847428 <6>[ 17.362648] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10913 04:46:23.853888 <6>[ 17.456094] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10914 04:46:23.857374 <6>[ 17.456094]
10915 04:46:23.857458
10916 04:46:23.873134 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10917 04:46:23.919979 <6>[ 17.713082] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10918 04:46:23.926354 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10919 04:46:23.950483 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10920 04:46:24.049199 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10921 04:46:24.064788 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10922 04:46:24.081418 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10923 04:46:24.099882 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10924 04:46:24.112390 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10925 04:46:24.132077 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10926 04:46:24.144523 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10927 04:46:24.160673 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10928 04:46:24.180369 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10929 04:46:24.217319 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10930 04:46:24.249475 Starting [0;1;39mUser Login Management[0m...
10931 04:46:24.269626 Starting [0;1;39mPermit User Sessions[0m...
10932 04:46:24.288355 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10933 04:46:24.334185 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10934 04:46:24.350937 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10935 04:46:24.368489 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10936 04:46:24.391684 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10937 04:46:24.413539 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10938 04:46:24.433215 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10939 04:46:24.450353 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10940 04:46:24.465319 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10941 04:46:24.508977 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10942 04:46:24.536490 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10943 04:46:24.573307
10944 04:46:24.573398
10945 04:46:24.576721 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10946 04:46:24.576802
10947 04:46:24.580110 debian-bullseye-arm64 login: root (automatic login)
10948 04:46:24.580188
10949 04:46:24.580273
10950 04:46:24.598736 Linux debian-bullseye-arm64 6.1.75-cip14-rt8 #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024 aarch64
10951 04:46:24.598829
10952 04:46:24.605307 The programs included with the Debian GNU/Linux system are free software;
10953 04:46:24.611916 the exact distribution terms for each program are described in the
10954 04:46:24.615070 individual files in /usr/share/doc/*/copyright.
10955 04:46:24.615151
10956 04:46:24.621934 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10957 04:46:24.625318 permitted by applicable law.
10958 04:46:24.625718 Matched prompt #10: / #
10960 04:46:24.626030 Setting prompt string to ['/ #']
10961 04:46:24.626168 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10963 04:46:24.626476 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10964 04:46:24.626586 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
10965 04:46:24.626666 Setting prompt string to ['/ #']
10966 04:46:24.626769 Forcing a shell prompt, looking for ['/ #']
10968 04:46:24.677012 / #
10969 04:46:24.677133 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10970 04:46:24.677229 Waiting using forced prompt support (timeout 00:02:30)
10971 04:46:24.682030
10972 04:46:24.682305 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10973 04:46:24.682413 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
10974 04:46:24.682521 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10975 04:46:24.682625 end: 2.2 depthcharge-retry (duration 00:01:46) [common]
10976 04:46:24.682729 end: 2 depthcharge-action (duration 00:01:46) [common]
10977 04:46:24.682831 start: 3 lava-test-retry (timeout 00:07:52) [common]
10978 04:46:24.682959 start: 3.1 lava-test-shell (timeout 00:07:52) [common]
10979 04:46:24.683047 Using namespace: common
10981 04:46:24.783399 / # #
10982 04:46:24.783549 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10983 04:46:24.783689 #<6>[ 18.555936] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10984 04:46:24.788174
10985 04:46:24.788462 Using /lava-12699819
10987 04:46:24.888770 / # export SHELL=/bin/sh
10988 04:46:24.894352 export SHELL=/bin/sh
10990 04:46:24.994815 / # . /lava-12699819/environment
10991 04:46:24.999770 . /lava-12699819/environment
10993 04:46:25.100254 / # /lava-12699819/bin/lava-test-runner /lava-12699819/0
10994 04:46:25.100395 Test shell timeout: 10s (minimum of the action and connection timeout)
10995 04:46:25.105394 /lava-12699819/bin/lava-test-runner /lava-12699819/0
10996 04:46:25.130902 + export TESTRUN_ID=0_igt-gpu-panfrost
10997 04:46:25.137558 + cd /lava-12699819/0/te<8>[ 18.931383] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 12699819_1.5.2.3.1>
10998 04:46:25.137825 Received signal: <STARTRUN> 0_igt-gpu-panfrost 12699819_1.5.2.3.1
10999 04:46:25.137908 Starting test lava.0_igt-gpu-panfrost (12699819_1.5.2.3.1)
11000 04:46:25.138035 Skipping test definition patterns.
11001 04:46:25.140984 sts/0_igt-gpu-panfrost
11002 04:46:25.141059 + cat uuid
11003 04:46:25.143927 + UUID=12699819_1.5.2.3.1
11004 04:46:25.143999 + set +x
11005 04:46:25.153902 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11006 04:46:25.160731 <8>[ 18.958657] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11007 04:46:25.160979 Received signal: <TESTSET> START panfrost_gem_new
11008 04:46:25.161052 Starting test_set panfrost_gem_new
11009 04:46:25.184206 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 18.980050] [IGT] panfrost_gem_new: executing
11010 04:46:25.187769 .1.75-cip14-rt8 aarch64)
11011 04:46:25.194342 Test r<14>[ 18.989144] [IGT] panfrost_gem_new: exiting, ret=77
11012 04:46:25.200690 equirement not m<8>[ 18.993958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11013 04:46:25.200947 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11015 04:46:25.207315 et in function drm_open_driver, file ../lib/drmtest.c:621:
11016 04:46:25.207396 Test requirement: !(fd<0)
11017 04:46:25.214291 No known gpu found for chipset flags 0x32 (panfrost)
11018 04:46:25.220731 Last errno: 2, No such file or dire<14>[ 19.018487] [IGT] panfrost_gem_new: executing
11019 04:46:25.220816 ctory
11020 04:46:25.230906 [1mSubtest gem-new-4096:<14>[ 19.025616] [IGT] panfrost_gem_new: exiting, ret=77
11021 04:46:25.237204 SKIP (0.000s)[<8>[ 19.031132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11022 04:46:25.237290 0m
11023 04:46:25.237528 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11025 04:46:25.244083 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11026 04:46:25.253772 Test requirement not met in function drm_open_driv<14>[ 19.050942] [IGT] panfrost_gem_new: executing
11027 04:46:25.257122 er, file ../lib/drmtest.c:621:
11028 04:46:25.260610 <14>[ 19.057413] [IGT] panfrost_gem_new: exiting, ret=77
11029 04:46:25.270589 Test requirement<8>[ 19.063152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11030 04:46:25.270846 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11032 04:46:25.274005 <8>[ 19.064901] <LAVA_SIGNAL_TESTSET STOP>
11033 04:46:25.274104 : !(fd<0)
11034 04:46:25.274342 Received signal: <TESTSET> STOP
11035 04:46:25.274415 Closing test_set panfrost_gem_new
11036 04:46:25.280451 No known gpu found for chipset flags 0x32 (panfrost)
11037 04:46:25.283701 Last errno: 2, No such file or directory
11038 04:46:25.287087 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11039 04:46:25.293763 IGT-Version<8>[ 19.091135] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11040 04:46:25.294025 Received signal: <TESTSET> START panfrost_get_param
11041 04:46:25.294098 Starting test_set panfrost_get_param
11042 04:46:25.300337 : 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11043 04:46:25.310053 Test requirement not met in function drm_open_driver, file ../lib<14>[ 19.103365] [IGT] panfrost_get_param: executing
11044 04:46:25.313489 <14>[ 19.105426] [IGT] panfrost_get_param: exiting, ret=77
11045 04:46:25.319800 <8>[ 19.109641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11046 04:46:25.320084 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11048 04:46:25.323387 /drmtest.c:621:
11049 04:46:25.326905 Test requirement: !(fd<0)
11050 04:46:25.329796 No known gpu found for chipset flags 0x32 (panfrost)
11051 04:46:25.336465 Last errno: 2,<14>[ 19.131678] [IGT] panfrost_get_param: executing
11052 04:46:25.340176 No such file or directory
11053 04:46:25.346422 [1mSubtest gem-new-<14>[ 19.140527] [IGT] panfrost_get_param: exiting, ret=77
11054 04:46:25.353234 <8>[ 19.145887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11055 04:46:25.353516 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11057 04:46:25.356750 zeroed: SKIP (0.000s)[0m
11058 04:46:25.363576 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11059 04:46:25.373376 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c<14>[ 19.167922] [IGT] panfrost_get_param: executing
11060 04:46:25.373491 :621:
11061 04:46:25.379902 Test requirement: !(fd<0)<14>[ 19.177361] [IGT] panfrost_get_param: exiting, ret=77
11062 04:46:25.389884 <8>[ 19.182773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11063 04:46:25.390202 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11065 04:46:25.393210 <8>[ 19.184507] <LAVA_SIGNAL_TESTSET STOP>
11066 04:46:25.393317
11067 04:46:25.393581 Received signal: <TESTSET> STOP
11068 04:46:25.393684 Closing test_set panfrost_get_param
11069 04:46:25.396239 No known gpu found for chipset flags 0x32 (panfrost)
11070 04:46:25.406218 Last errno: 2, No such f<8>[ 19.200782] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11071 04:46:25.406303 ile or directory
11072 04:46:25.406550 Received signal: <TESTSET> START panfrost_prime
11073 04:46:25.406620 Starting test_set panfrost_prime
11074 04:46:25.409583 [1mSubtest base-params: SKIP (0.000s)[0m
11075 04:46:25.416090 IGT-Version: 1.27.<14>[ 19.213243] [IGT] panfrost_prime: executing
11076 04:46:25.426067 1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aa<14>[ 19.220694] [IGT] panfrost_prime: exiting, ret=77
11077 04:46:25.432842 <8>[ 19.226373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11078 04:46:25.433126 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11080 04:46:25.436230 <8>[ 19.227590] <LAVA_SIGNAL_TESTSET STOP>
11081 04:46:25.436510 Received signal: <TESTSET> STOP
11082 04:46:25.436607 Closing test_set panfrost_prime
11083 04:46:25.439485 rch64)
11084 04:46:25.445924 Test requirement not met<8>[ 19.242035] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11085 04:46:25.446222 Received signal: <TESTSET> START panfrost_submit
11086 04:46:25.446298 Starting test_set panfrost_submit
11087 04:46:25.449244 in function drm_open_driver, file ../lib/drmtest.c:621:
11088 04:46:25.456127 Test requirement: !(fd<14>[ 19.253807] [IGT] panfrost_submit: executing
11089 04:46:25.456229 <0)
11090 04:46:25.466065 No known gpu found for chip<14>[ 19.261173] [IGT] panfrost_submit: exiting, ret=77
11091 04:46:25.472470 <8>[ 19.265878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11092 04:46:25.472550 set flags 0x32 (panfrost)
11093 04:46:25.472832 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11095 04:46:25.479474 Last errno: 2, No suc<14>[ 19.277597] [IGT] panfrost_submit: executing
11096 04:46:25.482382 h file or directory
11097 04:46:25.488976 [1mSubtest get-bad-param: <14>[ 19.284933] [IGT] panfrost_submit: exiting, ret=77
11098 04:46:25.498812 <8>[ 19.289444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11099 04:46:25.498932 SKIP (0.000s)[0m
11100 04:46:25.499172 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11102 04:46:25.505652 IGT-Version: <14>[ 19.301931] [IGT] panfrost_submit: executing
11103 04:46:25.512327 1.27.1-g621c2d3 (aarch64) (Linux<14>[ 19.309580] [IGT] panfrost_submit: exiting, ret=77
11104 04:46:25.522102 <8>[ 19.313948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11105 04:46:25.522357 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11107 04:46:25.525420 : 6.1.75-cip14-rt8 aarch64)
11108 04:46:25.531846 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11109 04:46:25.535426 T<14>[ 19.334778] [IGT] panfrost_submit: executing
11110 04:46:25.538907 est requirement: !(fd<0)
11111 04:46:25.545292 No known gpu found for<14>[ 19.340267] [IGT] panfrost_submit: exiting, ret=77
11112 04:46:25.555361 <8>[ 19.345633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11113 04:46:25.555644 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11115 04:46:25.558812 chipset flags 0<14>[ 19.358073] [IGT] panfrost_submit: executing
11116 04:46:25.561800 x32 (panfrost)
11117 04:46:25.568504 Last errno: 2, No such file or d<14>[ 19.364108] [IGT] panfrost_submit: exiting, ret=77
11118 04:46:25.578727 <8>[ 19.368471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11119 04:46:25.578806 irectory
11120 04:46:25.579091 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11122 04:46:25.585255 [1mSu<14>[ 19.382227] [IGT] panfrost_submit: executing
11123 04:46:25.588260 btest get-bad-padding: SKIP (0.000s)[0m
11124 04:46:25.591732 IGT-Ve<14>[ 19.388287] [IGT] panfrost_submit: exiting, ret=77
11125 04:46:25.601762 <8>[ 19.392650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11126 04:46:25.602039 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11128 04:46:25.608316 rsion: 1.27.1-g621c2d3 (aarch64)<14>[ 19.406003] [IGT] panfrost_submit: executing
11129 04:46:25.618153 (Linux: 6.1.75-cip14-rt8 aarch6<14>[ 19.413445] [IGT] panfrost_submit: exiting, ret=77
11130 04:46:25.624937 <8>[ 19.417613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11131 04:46:25.625039 4)
11132 04:46:25.625319 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11134 04:46:25.631317 Test requirement not met in function drm_ope<14>[ 19.429408] [IGT] panfrost_submit: executing
11135 04:46:25.641200 n_driver, file ../lib/drmtest.c:<14>[ 19.436948] [IGT] panfrost_submit: exiting, ret=77
11136 04:46:25.648130 <8>[ 19.441695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11137 04:46:25.648232 621:
11138 04:46:25.648471 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11140 04:46:25.651550 Test requirement: !(fd<0)
11141 04:46:25.658086 No known gpu fo<14>[ 19.453632] [IGT] panfrost_submit: executing
11142 04:46:25.664450 und for chipset <14>[ 19.461416] [IGT] panfrost_submit: exiting, ret=77
11143 04:46:25.664557 flags 0x32 (panfrost)
11144 04:46:25.667783 Last errno: 2, No such file or directory
11145 04:46:25.681297 [1mSubtest gem-prime-import: S<8>[ 19.472322] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11146 04:46:25.681569 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11148 04:46:25.684333 <8>[ 19.473624] <LAVA_SIGNAL_TESTSET STOP>
11149 04:46:25.684607 Received signal: <TESTSET> STOP
11150 04:46:25.684709 Closing test_set panfrost_submit
11151 04:46:25.691369 <8>[ 19.474295] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 12699819_1.5.2.3.1>
11152 04:46:25.691488 KIP (0.000s)[0m
11153 04:46:25.691762 Received signal: <ENDRUN> 0_igt-gpu-panfrost 12699819_1.5.2.3.1
11154 04:46:25.691873 Ending use of test pattern.
11155 04:46:25.691970 Ending test lava.0_igt-gpu-panfrost (12699819_1.5.2.3.1), duration 0.55
11157 04:46:25.697854 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11158 04:46:25.704325 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11159 04:46:25.707748 Test requirement: !(fd<0)
11160 04:46:25.714218 No known gpu found for chipset flags 0x32 (panfrost)
11161 04:46:25.717848 Last errno: 2, No such file or directory
11162 04:46:25.721189 [1mSubtest pan-submit: SKIP (0.000s)[0m
11163 04:46:25.727822 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11164 04:46:25.734204 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11165 04:46:25.737714 Test requirement: !(fd<0)
11166 04:46:25.740709 No known gpu found for chipset flags 0x32 (panfrost)
11167 04:46:25.744178 Last errno: 2, No such file or directory
11168 04:46:25.750816 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11169 04:46:25.754148 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11170 04:46:25.763911 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11171 04:46:25.764016 Test requirement: !(fd<0)
11172 04:46:25.770846 No known gpu found for chipset flags 0x32 (panfrost)
11173 04:46:25.774218 Last errno: 2, No such file or directory
11174 04:46:25.777589 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11175 04:46:25.783832 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11176 04:46:25.793765 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11177 04:46:25.793878 Test requirement: !(fd<0)
11178 04:46:25.800661 No known gpu found for chipset flags 0x32 (panfrost)
11179 04:46:25.803522 Last errno: 2, No such file or directory
11180 04:46:25.810285 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11181 04:46:25.813548 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11182 04:46:25.823487 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11183 04:46:25.823607 Test requirement: !(fd<0)
11184 04:46:25.830356 No known gpu found for chipset flags 0x32 (panfrost)
11185 04:46:25.833743 Last errno: 2, No such file or directory
11186 04:46:25.840144 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11187 04:46:25.843611 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11188 04:46:25.853318 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11189 04:46:25.853428 Test requirement: !(fd<0)
11190 04:46:25.860075 No known gpu found for chipset flags 0x32 (panfrost)
11191 04:46:25.863297 Last errno: 2, No such file or directory
11192 04:46:25.870223 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11193 04:46:25.873139 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11194 04:46:25.883041 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11195 04:46:25.883149 Test requirement: !(fd<0)
11196 04:46:25.889868 No known gpu found for chipset flags 0x32 (panfrost)
11197 04:46:25.893292 Last errno: 2, No such file or directory
11198 04:46:25.896265 [1mSubtest pan-reset: SKIP (0.000s)[0m
11199 04:46:25.903171 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11200 04:46:25.909571 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11201 04:46:25.912921 Test requirement: !(fd<0)
11202 04:46:25.916483 No known gpu found for chipset flags 0x32 (panfrost)
11203 04:46:25.919651 Last errno: 2, No such file or directory
11204 04:46:25.926277 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11205 04:46:25.933099 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11206 04:46:25.939424 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11207 04:46:25.939509 Test requirement: !(fd<0)
11208 04:46:25.945956 No known gpu found for chipset flags 0x32 (panfrost)
11209 04:46:25.949514 Last errno: 2, No such file or directory
11210 04:46:25.952480 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11211 04:46:25.955869 + set +x
11212 04:46:25.955972 <LAVA_TEST_RUNNER EXIT>
11213 04:46:25.956263 ok: lava_test_shell seems to have completed
11214 04:46:25.956942 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11215 04:46:25.957097 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11216 04:46:25.957228 end: 3 lava-test-retry (duration 00:00:01) [common]
11217 04:46:25.957352 start: 4 finalize (timeout 00:07:50) [common]
11218 04:46:25.957488 start: 4.1 power-off (timeout 00:00:30) [common]
11219 04:46:25.957801 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11220 04:46:26.032577 >> Command sent successfully.
11221 04:46:26.035049 Returned 0 in 0 seconds
11222 04:46:26.135443 end: 4.1 power-off (duration 00:00:00) [common]
11224 04:46:26.135845 start: 4.2 read-feedback (timeout 00:07:50) [common]
11225 04:46:26.136129 Listened to connection for namespace 'common' for up to 1s
11226 04:46:27.137054 Finalising connection for namespace 'common'
11227 04:46:27.137216 Disconnecting from shell: Finalise
11228 04:46:27.137306 / #
11229 04:46:27.237623 end: 4.2 read-feedback (duration 00:00:01) [common]
11230 04:46:27.237837 end: 4 finalize (duration 00:00:01) [common]
11231 04:46:27.238035 Cleaning after the job
11232 04:46:27.238147 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699819/tftp-deploy-qmxjd096/ramdisk
11233 04:46:27.244672 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699819/tftp-deploy-qmxjd096/kernel
11234 04:46:27.252203 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699819/tftp-deploy-qmxjd096/dtb
11235 04:46:27.252451 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699819/tftp-deploy-qmxjd096/modules
11236 04:46:27.258391 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12699819
11237 04:46:27.363266 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12699819
11238 04:46:27.363441 Job finished correctly