Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 12
- Kernel Errors: 30
1 04:40:55.048601 lava-dispatcher, installed at version: 2023.10
2 04:40:55.048812 start: 0 validate
3 04:40:55.048940 Start time: 2024-02-04 04:40:55.048933+00:00 (UTC)
4 04:40:55.049065 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:40:55.049201 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 04:40:55.318524 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:40:55.319290 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:41:32.643755 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:41:32.644527 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:41:32.913255 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:41:32.914034 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 04:41:36.694183 validate duration: 41.65
14 04:41:36.694454 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:41:36.694552 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:41:36.694641 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:41:36.694763 Not decompressing ramdisk as can be used compressed.
18 04:41:36.694850 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 04:41:36.694917 saving as /var/lib/lava/dispatcher/tmp/12699799/tftp-deploy-s8jh0h48/ramdisk/rootfs.cpio.gz
20 04:41:36.694983 total size: 43284872 (41 MB)
21 04:41:36.960797 progress 0 % (0 MB)
22 04:41:36.972101 progress 5 % (2 MB)
23 04:41:36.983248 progress 10 % (4 MB)
24 04:41:36.994551 progress 15 % (6 MB)
25 04:41:37.005128 progress 20 % (8 MB)
26 04:41:37.015796 progress 25 % (10 MB)
27 04:41:37.026445 progress 30 % (12 MB)
28 04:41:37.037534 progress 35 % (14 MB)
29 04:41:37.048513 progress 40 % (16 MB)
30 04:41:37.059432 progress 45 % (18 MB)
31 04:41:37.070294 progress 50 % (20 MB)
32 04:41:37.081170 progress 55 % (22 MB)
33 04:41:37.092135 progress 60 % (24 MB)
34 04:41:37.102959 progress 65 % (26 MB)
35 04:41:37.113909 progress 70 % (28 MB)
36 04:41:37.124906 progress 75 % (30 MB)
37 04:41:37.136067 progress 80 % (33 MB)
38 04:41:37.147009 progress 85 % (35 MB)
39 04:41:37.157930 progress 90 % (37 MB)
40 04:41:37.168750 progress 95 % (39 MB)
41 04:41:37.179602 progress 100 % (41 MB)
42 04:41:37.179889 41 MB downloaded in 0.48 s (85.13 MB/s)
43 04:41:37.180056 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:41:37.180302 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:41:37.180393 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:41:37.180480 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:41:37.180619 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 04:41:37.180691 saving as /var/lib/lava/dispatcher/tmp/12699799/tftp-deploy-s8jh0h48/kernel/Image
50 04:41:37.180755 total size: 51597824 (49 MB)
51 04:41:37.180818 No compression specified
52 04:41:37.181982 progress 0 % (0 MB)
53 04:41:37.195074 progress 5 % (2 MB)
54 04:41:37.208104 progress 10 % (4 MB)
55 04:41:37.221260 progress 15 % (7 MB)
56 04:41:37.234294 progress 20 % (9 MB)
57 04:41:37.247596 progress 25 % (12 MB)
58 04:41:37.260734 progress 30 % (14 MB)
59 04:41:37.273820 progress 35 % (17 MB)
60 04:41:37.286975 progress 40 % (19 MB)
61 04:41:37.301572 progress 45 % (22 MB)
62 04:41:37.315865 progress 50 % (24 MB)
63 04:41:37.329776 progress 55 % (27 MB)
64 04:41:37.343520 progress 60 % (29 MB)
65 04:41:37.357517 progress 65 % (32 MB)
66 04:41:37.371293 progress 70 % (34 MB)
67 04:41:37.385200 progress 75 % (36 MB)
68 04:41:37.399605 progress 80 % (39 MB)
69 04:41:37.413588 progress 85 % (41 MB)
70 04:41:37.427754 progress 90 % (44 MB)
71 04:41:37.440940 progress 95 % (46 MB)
72 04:41:37.453924 progress 100 % (49 MB)
73 04:41:37.454217 49 MB downloaded in 0.27 s (179.95 MB/s)
74 04:41:37.454378 end: 1.2.1 http-download (duration 00:00:00) [common]
76 04:41:37.454614 end: 1.2 download-retry (duration 00:00:00) [common]
77 04:41:37.454709 start: 1.3 download-retry (timeout 00:09:59) [common]
78 04:41:37.454801 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 04:41:37.454935 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 04:41:37.455007 saving as /var/lib/lava/dispatcher/tmp/12699799/tftp-deploy-s8jh0h48/dtb/mt8192-asurada-spherion-r0.dtb
81 04:41:37.455070 total size: 47278 (0 MB)
82 04:41:37.455134 No compression specified
83 04:41:37.456272 progress 69 % (0 MB)
84 04:41:37.456551 progress 100 % (0 MB)
85 04:41:37.456708 0 MB downloaded in 0.00 s (27.57 MB/s)
86 04:41:37.456835 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:41:37.457062 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:41:37.457148 start: 1.4 download-retry (timeout 00:09:59) [common]
90 04:41:37.457233 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 04:41:37.457348 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 04:41:37.457419 saving as /var/lib/lava/dispatcher/tmp/12699799/tftp-deploy-s8jh0h48/modules/modules.tar
93 04:41:37.457484 total size: 8633524 (8 MB)
94 04:41:37.457549 Using unxz to decompress xz
95 04:41:37.461255 progress 0 % (0 MB)
96 04:41:37.482549 progress 5 % (0 MB)
97 04:41:37.506343 progress 10 % (0 MB)
98 04:41:37.529746 progress 15 % (1 MB)
99 04:41:37.553877 progress 20 % (1 MB)
100 04:41:37.577950 progress 25 % (2 MB)
101 04:41:37.605419 progress 30 % (2 MB)
102 04:41:37.630104 progress 35 % (2 MB)
103 04:41:37.653738 progress 40 % (3 MB)
104 04:41:37.677749 progress 45 % (3 MB)
105 04:41:37.702734 progress 50 % (4 MB)
106 04:41:37.727122 progress 55 % (4 MB)
107 04:41:37.753987 progress 60 % (4 MB)
108 04:41:37.779484 progress 65 % (5 MB)
109 04:41:37.804454 progress 70 % (5 MB)
110 04:41:37.827947 progress 75 % (6 MB)
111 04:41:37.855243 progress 80 % (6 MB)
112 04:41:37.880773 progress 85 % (7 MB)
113 04:41:37.907154 progress 90 % (7 MB)
114 04:41:37.936842 progress 95 % (7 MB)
115 04:41:37.964445 progress 100 % (8 MB)
116 04:41:37.970016 8 MB downloaded in 0.51 s (16.06 MB/s)
117 04:41:37.970262 end: 1.4.1 http-download (duration 00:00:01) [common]
119 04:41:37.970527 end: 1.4 download-retry (duration 00:00:01) [common]
120 04:41:37.970623 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 04:41:37.970721 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 04:41:37.970805 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:41:37.970894 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 04:41:37.971151 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux
125 04:41:37.971283 makedir: /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin
126 04:41:37.971390 makedir: /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/tests
127 04:41:37.971490 makedir: /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/results
128 04:41:37.971611 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-add-keys
129 04:41:37.971758 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-add-sources
130 04:41:37.971888 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-background-process-start
131 04:41:37.972016 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-background-process-stop
132 04:41:37.972141 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-common-functions
133 04:41:37.972264 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-echo-ipv4
134 04:41:37.972432 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-install-packages
135 04:41:37.972555 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-installed-packages
136 04:41:37.972676 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-os-build
137 04:41:37.972800 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-probe-channel
138 04:41:37.972925 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-probe-ip
139 04:41:37.973046 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-target-ip
140 04:41:37.973168 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-target-mac
141 04:41:37.973288 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-target-storage
142 04:41:37.973414 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-test-case
143 04:41:37.973537 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-test-event
144 04:41:37.973658 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-test-feedback
145 04:41:37.973778 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-test-raise
146 04:41:37.973901 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-test-reference
147 04:41:37.974057 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-test-runner
148 04:41:37.974180 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-test-set
149 04:41:37.974302 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-test-shell
150 04:41:37.974428 Updating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-install-packages (oe)
151 04:41:37.974581 Updating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/bin/lava-installed-packages (oe)
152 04:41:37.974711 Creating /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/environment
153 04:41:37.974812 LAVA metadata
154 04:41:37.974926 - LAVA_JOB_ID=12699799
155 04:41:37.974994 - LAVA_DISPATCHER_IP=192.168.201.1
156 04:41:37.975099 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 04:41:37.975169 skipped lava-vland-overlay
158 04:41:37.975246 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 04:41:37.975331 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 04:41:37.975400 skipped lava-multinode-overlay
161 04:41:37.975475 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 04:41:37.975559 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 04:41:37.975639 Loading test definitions
164 04:41:37.975735 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 04:41:37.975811 Using /lava-12699799 at stage 0
166 04:41:37.976109 uuid=12699799_1.5.2.3.1 testdef=None
167 04:41:37.976200 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 04:41:37.976290 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 04:41:37.976812 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 04:41:37.977043 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 04:41:37.977670 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 04:41:37.977905 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 04:41:37.978536 runner path: /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/0/tests/0_igt-kms-mediatek test_uuid 12699799_1.5.2.3.1
176 04:41:37.978692 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 04:41:37.978904 Creating lava-test-runner.conf files
179 04:41:37.978969 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12699799/lava-overlay-09ihq1ux/lava-12699799/0 for stage 0
180 04:41:37.979061 - 0_igt-kms-mediatek
181 04:41:37.979160 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 04:41:37.979246 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 04:41:37.985766 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 04:41:37.985881 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 04:41:37.986014 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 04:41:37.986103 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 04:41:37.986195 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 04:41:39.293569 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 04:41:39.293957 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 04:41:39.294168 extracting modules file /var/lib/lava/dispatcher/tmp/12699799/tftp-deploy-s8jh0h48/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699799/extract-overlay-ramdisk-kjng2r3d/ramdisk
191 04:41:39.514349 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 04:41:39.514525 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 04:41:39.514623 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699799/compress-overlay-xemumdwc/overlay-1.5.2.4.tar.gz to ramdisk
194 04:41:39.514697 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699799/compress-overlay-xemumdwc/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12699799/extract-overlay-ramdisk-kjng2r3d/ramdisk
195 04:41:39.521005 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 04:41:39.521123 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 04:41:39.521216 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 04:41:39.521309 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 04:41:39.521394 Building ramdisk /var/lib/lava/dispatcher/tmp/12699799/extract-overlay-ramdisk-kjng2r3d/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12699799/extract-overlay-ramdisk-kjng2r3d/ramdisk
200 04:41:40.470465 >> 370015 blocks
201 04:41:46.406124 rename /var/lib/lava/dispatcher/tmp/12699799/extract-overlay-ramdisk-kjng2r3d/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12699799/tftp-deploy-s8jh0h48/ramdisk/ramdisk.cpio.gz
202 04:41:46.406561 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 04:41:46.406684 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 04:41:46.406793 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 04:41:46.406904 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12699799/tftp-deploy-s8jh0h48/kernel/Image'
206 04:41:59.467904 Returned 0 in 13 seconds
207 04:41:59.568600 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12699799/tftp-deploy-s8jh0h48/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12699799/tftp-deploy-s8jh0h48/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12699799/tftp-deploy-s8jh0h48/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12699799/tftp-deploy-s8jh0h48/kernel/image.itb
208 04:42:00.356018 output: FIT description: Kernel Image image with one or more FDT blobs
209 04:42:00.356446 output: Created: Sun Feb 4 04:42:00 2024
210 04:42:00.356556 output: Image 0 (kernel-1)
211 04:42:00.356655 output: Description:
212 04:42:00.356752 output: Created: Sun Feb 4 04:42:00 2024
213 04:42:00.356848 output: Type: Kernel Image
214 04:42:00.356944 output: Compression: lzma compressed
215 04:42:00.357042 output: Data Size: 12048508 Bytes = 11766.12 KiB = 11.49 MiB
216 04:42:00.357138 output: Architecture: AArch64
217 04:42:00.357238 output: OS: Linux
218 04:42:00.357333 output: Load Address: 0x00000000
219 04:42:00.357429 output: Entry Point: 0x00000000
220 04:42:00.357523 output: Hash algo: crc32
221 04:42:00.357613 output: Hash value: 3b31d50c
222 04:42:00.357702 output: Image 1 (fdt-1)
223 04:42:00.357791 output: Description: mt8192-asurada-spherion-r0
224 04:42:00.357881 output: Created: Sun Feb 4 04:42:00 2024
225 04:42:00.357978 output: Type: Flat Device Tree
226 04:42:00.358069 output: Compression: uncompressed
227 04:42:00.358158 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 04:42:00.358247 output: Architecture: AArch64
229 04:42:00.358335 output: Hash algo: crc32
230 04:42:00.358423 output: Hash value: cc4352de
231 04:42:00.358511 output: Image 2 (ramdisk-1)
232 04:42:00.358597 output: Description: unavailable
233 04:42:00.358685 output: Created: Sun Feb 4 04:42:00 2024
234 04:42:00.358773 output: Type: RAMDisk Image
235 04:42:00.358860 output: Compression: Unknown Compression
236 04:42:00.358949 output: Data Size: 56453557 Bytes = 55130.43 KiB = 53.84 MiB
237 04:42:00.359038 output: Architecture: AArch64
238 04:42:00.359126 output: OS: Linux
239 04:42:00.359214 output: Load Address: unavailable
240 04:42:00.359302 output: Entry Point: unavailable
241 04:42:00.359391 output: Hash algo: crc32
242 04:42:00.359479 output: Hash value: a361472a
243 04:42:00.359567 output: Default Configuration: 'conf-1'
244 04:42:00.359654 output: Configuration 0 (conf-1)
245 04:42:00.359742 output: Description: mt8192-asurada-spherion-r0
246 04:42:00.359831 output: Kernel: kernel-1
247 04:42:00.359919 output: Init Ramdisk: ramdisk-1
248 04:42:00.360007 output: FDT: fdt-1
249 04:42:00.360094 output: Loadables: kernel-1
250 04:42:00.360182 output:
251 04:42:00.360434 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 04:42:00.360580 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 04:42:00.360731 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 04:42:00.360867 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 04:42:00.360989 No LXC device requested
256 04:42:00.361111 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 04:42:00.361237 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 04:42:00.361356 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 04:42:00.361468 Checking files for TFTP limit of 4294967296 bytes.
260 04:42:00.362179 end: 1 tftp-deploy (duration 00:00:24) [common]
261 04:42:00.362322 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 04:42:00.362456 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 04:42:00.362630 substitutions:
264 04:42:00.362731 - {DTB}: 12699799/tftp-deploy-s8jh0h48/dtb/mt8192-asurada-spherion-r0.dtb
265 04:42:00.362831 - {INITRD}: 12699799/tftp-deploy-s8jh0h48/ramdisk/ramdisk.cpio.gz
266 04:42:00.362924 - {KERNEL}: 12699799/tftp-deploy-s8jh0h48/kernel/Image
267 04:42:00.363016 - {LAVA_MAC}: None
268 04:42:00.363106 - {PRESEED_CONFIG}: None
269 04:42:00.363197 - {PRESEED_LOCAL}: None
270 04:42:00.363286 - {RAMDISK}: 12699799/tftp-deploy-s8jh0h48/ramdisk/ramdisk.cpio.gz
271 04:42:00.363377 - {ROOT_PART}: None
272 04:42:00.363467 - {ROOT}: None
273 04:42:00.363558 - {SERVER_IP}: 192.168.201.1
274 04:42:00.363647 - {TEE}: None
275 04:42:00.363738 Parsed boot commands:
276 04:42:00.363826 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 04:42:00.364068 Parsed boot commands: tftpboot 192.168.201.1 12699799/tftp-deploy-s8jh0h48/kernel/image.itb 12699799/tftp-deploy-s8jh0h48/kernel/cmdline
278 04:42:00.364203 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 04:42:00.364336 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 04:42:00.364474 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 04:42:00.364600 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 04:42:00.364708 Not connected, no need to disconnect.
283 04:42:00.364823 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 04:42:00.364941 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 04:42:00.365045 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 04:42:00.369029 Setting prompt string to ['lava-test: # ']
287 04:42:00.369443 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 04:42:00.369592 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 04:42:00.369730 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 04:42:00.369864 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 04:42:00.370224 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 04:42:05.501139 >> Command sent successfully.
293 04:42:05.503714 Returned 0 in 5 seconds
294 04:42:05.604113 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 04:42:05.604446 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 04:42:05.604545 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 04:42:05.604640 Setting prompt string to 'Starting depthcharge on Spherion...'
299 04:42:05.604708 Changing prompt to 'Starting depthcharge on Spherion...'
300 04:42:05.604776 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 04:42:05.605037 [Enter `^Ec?' for help]
302 04:42:05.777760
303 04:42:05.777918
304 04:42:05.778029 F0: 102B 0000
305 04:42:05.778094
306 04:42:05.778153 F3: 1001 0000 [0200]
307 04:42:05.778212
308 04:42:05.781669 F3: 1001 0000
309 04:42:05.781757
310 04:42:05.781822 F7: 102D 0000
311 04:42:05.781885
312 04:42:05.781950 F1: 0000 0000
313 04:42:05.782042
314 04:42:05.785407 V0: 0000 0000 [0001]
315 04:42:05.785493
316 04:42:05.785558 00: 0007 8000
317 04:42:05.785620
318 04:42:05.788792 01: 0000 0000
319 04:42:05.788879
320 04:42:05.788948 BP: 0C00 0209 [0000]
321 04:42:05.789009
322 04:42:05.789068 G0: 1182 0000
323 04:42:05.792531
324 04:42:05.792650 EC: 0000 0021 [4000]
325 04:42:05.792744
326 04:42:05.796255 S7: 0000 0000 [0000]
327 04:42:05.796345
328 04:42:05.796411 CC: 0000 0000 [0001]
329 04:42:05.796473
330 04:42:05.799667 T0: 0000 0040 [010F]
331 04:42:05.799756
332 04:42:05.799821 Jump to BL
333 04:42:05.799883
334 04:42:05.824443
335 04:42:05.824650
336 04:42:05.824741
337 04:42:05.831983 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 04:42:05.835154 ARM64: Exception handlers installed.
339 04:42:05.839132 ARM64: Testing exception
340 04:42:05.842645 ARM64: Done test exception
341 04:42:05.850032 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 04:42:05.857226 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 04:42:05.864428 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 04:42:05.874972 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 04:42:05.881696 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 04:42:05.891890 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 04:42:05.902626 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 04:42:05.909287 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 04:42:05.927128 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 04:42:05.930496 WDT: Last reset was cold boot
351 04:42:05.933830 SPI1(PAD0) initialized at 2873684 Hz
352 04:42:05.937199 SPI5(PAD0) initialized at 992727 Hz
353 04:42:05.940441 VBOOT: Loading verstage.
354 04:42:05.947113 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 04:42:05.950355 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 04:42:05.953971 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 04:42:05.956911 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 04:42:05.964822 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 04:42:05.971402 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 04:42:05.981891 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 04:42:05.982031
362 04:42:05.982101
363 04:42:05.992047 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 04:42:05.995579 ARM64: Exception handlers installed.
365 04:42:05.998981 ARM64: Testing exception
366 04:42:05.999079 ARM64: Done test exception
367 04:42:06.005578 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 04:42:06.009007 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 04:42:06.023252 Probing TPM: . done!
370 04:42:06.023403 TPM ready after 0 ms
371 04:42:06.030024 Connected to device vid:did:rid of 1ae0:0028:00
372 04:42:06.036716 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 04:42:06.095157 Initialized TPM device CR50 revision 0
374 04:42:06.104758 tlcl_send_startup: Startup return code is 0
375 04:42:06.104923 TPM: setup succeeded
376 04:42:06.116168 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 04:42:06.125444 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 04:42:06.135602 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 04:42:06.144623 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 04:42:06.147756 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 04:42:06.158007 in-header: 03 07 00 00 08 00 00 00
382 04:42:06.161857 in-data: aa e4 47 04 13 02 00 00
383 04:42:06.165514 Chrome EC: UHEPI supported
384 04:42:06.172959 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 04:42:06.176721 in-header: 03 ad 00 00 08 00 00 00
386 04:42:06.180511 in-data: 00 20 20 08 00 00 00 00
387 04:42:06.180611 Phase 1
388 04:42:06.183823 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 04:42:06.191509 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 04:42:06.195393 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 04:42:06.199069 Recovery requested (1009000e)
392 04:42:06.207335 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 04:42:06.212566 tlcl_extend: response is 0
394 04:42:06.222299 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 04:42:06.227734 tlcl_extend: response is 0
396 04:42:06.234646 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 04:42:06.254682 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 04:42:06.261937 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 04:42:06.262099
400 04:42:06.262168
401 04:42:06.271927 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 04:42:06.275476 ARM64: Exception handlers installed.
403 04:42:06.275575 ARM64: Testing exception
404 04:42:06.278411 ARM64: Done test exception
405 04:42:06.300324 pmic_efuse_setting: Set efuses in 11 msecs
406 04:42:06.303845 pmwrap_interface_init: Select PMIF_VLD_RDY
407 04:42:06.310519 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 04:42:06.314569 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 04:42:06.317830 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 04:42:06.324263 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 04:42:06.327607 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 04:42:06.335179 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 04:42:06.339036 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 04:42:06.342817 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 04:42:06.346670 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 04:42:06.354410 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 04:42:06.357581 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 04:42:06.361523 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 04:42:06.364619 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 04:42:06.371940 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 04:42:06.378300 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 04:42:06.385553 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 04:42:06.389270 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 04:42:06.396323 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 04:42:06.400712 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 04:42:06.406890 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 04:42:06.410325 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 04:42:06.417606 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 04:42:06.424343 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 04:42:06.427736 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 04:42:06.434620 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 04:42:06.441086 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 04:42:06.444451 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 04:42:06.447912 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 04:42:06.454342 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 04:42:06.457789 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 04:42:06.464563 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 04:42:06.468023 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 04:42:06.474697 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 04:42:06.477929 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 04:42:06.484883 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 04:42:06.487932 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 04:42:06.494463 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 04:42:06.498265 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 04:42:06.504820 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 04:42:06.508338 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 04:42:06.511383 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 04:42:06.518081 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 04:42:06.521401 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 04:42:06.525118 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 04:42:06.529113 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 04:42:06.532436 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 04:42:06.539137 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 04:42:06.542611 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 04:42:06.545989 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 04:42:06.549462 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 04:42:06.555787 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 04:42:06.562728 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 04:42:06.572583 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 04:42:06.575992 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 04:42:06.582602 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 04:42:06.592705 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 04:42:06.595976 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 04:42:06.602799 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 04:42:06.606078 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 04:42:06.612601 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x18
467 04:42:06.619573 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 04:42:06.622494 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 04:42:06.625849 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 04:42:06.638047 [RTC]rtc_get_frequency_meter,154: input=15, output=773
471 04:42:06.646702 [RTC]rtc_get_frequency_meter,154: input=23, output=956
472 04:42:06.656111 [RTC]rtc_get_frequency_meter,154: input=19, output=864
473 04:42:06.665516 [RTC]rtc_get_frequency_meter,154: input=17, output=819
474 04:42:06.675033 [RTC]rtc_get_frequency_meter,154: input=16, output=794
475 04:42:06.678599 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 04:42:06.685245 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 04:42:06.688959 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 04:42:06.692070 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 04:42:06.695296 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 04:42:06.698974 ADC[4]: Raw value=902876 ID=7
481 04:42:06.701885 ADC[3]: Raw value=213179 ID=1
482 04:42:06.702018 RAM Code: 0x71
483 04:42:06.709089 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 04:42:06.711863 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 04:42:06.722225 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 04:42:06.728997 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 04:42:06.732186 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 04:42:06.735445 in-header: 03 07 00 00 08 00 00 00
489 04:42:06.738867 in-data: aa e4 47 04 13 02 00 00
490 04:42:06.742104 Chrome EC: UHEPI supported
491 04:42:06.748563 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 04:42:06.751980 in-header: 03 ed 00 00 08 00 00 00
493 04:42:06.755364 in-data: 80 20 60 08 00 00 00 00
494 04:42:06.758840 MRC: failed to locate region type 0.
495 04:42:06.765178 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 04:42:06.765286 DRAM-K: Running full calibration
497 04:42:06.772089 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 04:42:06.775127 header.status = 0x0
499 04:42:06.778467 header.version = 0x6 (expected: 0x6)
500 04:42:06.781834 header.size = 0xd00 (expected: 0xd00)
501 04:42:06.781950 header.flags = 0x0
502 04:42:06.788794 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 04:42:06.807254 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
504 04:42:06.813704 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 04:42:06.817403 dram_init: ddr_geometry: 2
506 04:42:06.820793 [EMI] MDL number = 2
507 04:42:06.820889 [EMI] Get MDL freq = 0
508 04:42:06.823763 dram_init: ddr_type: 0
509 04:42:06.823850 is_discrete_lpddr4: 1
510 04:42:06.827213 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 04:42:06.827302
512 04:42:06.827385
513 04:42:06.830718 [Bian_co] ETT version 0.0.0.1
514 04:42:06.837205 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 04:42:06.837315
516 04:42:06.840676 dramc_set_vcore_voltage set vcore to 650000
517 04:42:06.840769 Read voltage for 800, 4
518 04:42:06.843977 Vio18 = 0
519 04:42:06.844065 Vcore = 650000
520 04:42:06.844132 Vdram = 0
521 04:42:06.847417 Vddq = 0
522 04:42:06.847504 Vmddr = 0
523 04:42:06.850858 dram_init: config_dvfs: 1
524 04:42:06.853688 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 04:42:06.860598 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 04:42:06.864082 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=10
527 04:42:06.867513 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=10
528 04:42:06.870903 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 04:42:06.874369 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 04:42:06.877355 MEM_TYPE=3, freq_sel=18
531 04:42:06.881551 sv_algorithm_assistance_LP4_1600
532 04:42:06.884971 ============ PULL DRAM RESETB DOWN ============
533 04:42:06.888461 ========== PULL DRAM RESETB DOWN end =========
534 04:42:06.891917 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 04:42:06.895734 ===================================
536 04:42:06.899507 LPDDR4 DRAM CONFIGURATION
537 04:42:06.902999 ===================================
538 04:42:06.903159 EX_ROW_EN[0] = 0x0
539 04:42:06.906781 EX_ROW_EN[1] = 0x0
540 04:42:06.906874 LP4Y_EN = 0x0
541 04:42:06.910374 WORK_FSP = 0x0
542 04:42:06.910470 WL = 0x2
543 04:42:06.914330 RL = 0x2
544 04:42:06.914503 BL = 0x2
545 04:42:06.917910 RPST = 0x0
546 04:42:06.918042 RD_PRE = 0x0
547 04:42:06.921777 WR_PRE = 0x1
548 04:42:06.921868 WR_PST = 0x0
549 04:42:06.925330 DBI_WR = 0x0
550 04:42:06.925479 DBI_RD = 0x0
551 04:42:06.929216 OTF = 0x1
552 04:42:06.929298 ===================================
553 04:42:06.933197 ===================================
554 04:42:06.937058 ANA top config
555 04:42:06.937156 ===================================
556 04:42:06.940348 DLL_ASYNC_EN = 0
557 04:42:06.943663 ALL_SLAVE_EN = 1
558 04:42:06.947140 NEW_RANK_MODE = 1
559 04:42:06.950107 DLL_IDLE_MODE = 1
560 04:42:06.950198 LP45_APHY_COMB_EN = 1
561 04:42:06.953789 TX_ODT_DIS = 1
562 04:42:06.956806 NEW_8X_MODE = 1
563 04:42:06.960333 ===================================
564 04:42:06.963570 ===================================
565 04:42:06.967097 data_rate = 1600
566 04:42:06.970516 CKR = 1
567 04:42:06.970610 DQ_P2S_RATIO = 8
568 04:42:06.973905 ===================================
569 04:42:06.976777 CA_P2S_RATIO = 8
570 04:42:06.980313 DQ_CA_OPEN = 0
571 04:42:06.983578 DQ_SEMI_OPEN = 0
572 04:42:06.987201 CA_SEMI_OPEN = 0
573 04:42:06.987293 CA_FULL_RATE = 0
574 04:42:06.990753 DQ_CKDIV4_EN = 1
575 04:42:06.994212 CA_CKDIV4_EN = 1
576 04:42:06.997721 CA_PREDIV_EN = 0
577 04:42:07.001129 PH8_DLY = 0
578 04:42:07.001231 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 04:42:07.004726 DQ_AAMCK_DIV = 4
580 04:42:07.008457 CA_AAMCK_DIV = 4
581 04:42:07.012711 CA_ADMCK_DIV = 4
582 04:42:07.012816 DQ_TRACK_CA_EN = 0
583 04:42:07.016154 CA_PICK = 800
584 04:42:07.019843 CA_MCKIO = 800
585 04:42:07.023338 MCKIO_SEMI = 0
586 04:42:07.026518 PLL_FREQ = 3068
587 04:42:07.026619 DQ_UI_PI_RATIO = 32
588 04:42:07.029890 CA_UI_PI_RATIO = 0
589 04:42:07.033376 ===================================
590 04:42:07.036818 ===================================
591 04:42:07.040128 memory_type:LPDDR4
592 04:42:07.043393 GP_NUM : 10
593 04:42:07.043487 SRAM_EN : 1
594 04:42:07.046842 MD32_EN : 0
595 04:42:07.050250 ===================================
596 04:42:07.050344 [ANA_INIT] >>>>>>>>>>>>>>
597 04:42:07.054083 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 04:42:07.057630 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 04:42:07.061026 ===================================
600 04:42:07.064883 data_rate = 1600,PCW = 0X7600
601 04:42:07.068365 ===================================
602 04:42:07.072260 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 04:42:07.075772 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 04:42:07.083005 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 04:42:07.086829 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 04:42:07.090151 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 04:42:07.093585 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 04:42:07.093688 [ANA_INIT] flow start
609 04:42:07.096652 [ANA_INIT] PLL >>>>>>>>
610 04:42:07.100063 [ANA_INIT] PLL <<<<<<<<
611 04:42:07.103706 [ANA_INIT] MIDPI >>>>>>>>
612 04:42:07.103806 [ANA_INIT] MIDPI <<<<<<<<
613 04:42:07.106738 [ANA_INIT] DLL >>>>>>>>
614 04:42:07.106831 [ANA_INIT] flow end
615 04:42:07.113525 ============ LP4 DIFF to SE enter ============
616 04:42:07.116843 ============ LP4 DIFF to SE exit ============
617 04:42:07.120348 [ANA_INIT] <<<<<<<<<<<<<
618 04:42:07.123365 [Flow] Enable top DCM control >>>>>
619 04:42:07.126896 [Flow] Enable top DCM control <<<<<
620 04:42:07.126996 Enable DLL master slave shuffle
621 04:42:07.133694 ==============================================================
622 04:42:07.136921 Gating Mode config
623 04:42:07.140422 ==============================================================
624 04:42:07.143795 Config description:
625 04:42:07.153433 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 04:42:07.160361 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 04:42:07.163837 SELPH_MODE 0: By rank 1: By Phase
628 04:42:07.170557 ==============================================================
629 04:42:07.173549 GAT_TRACK_EN = 1
630 04:42:07.176929 RX_GATING_MODE = 2
631 04:42:07.180182 RX_GATING_TRACK_MODE = 2
632 04:42:07.180280 SELPH_MODE = 1
633 04:42:07.183615 PICG_EARLY_EN = 1
634 04:42:07.187058 VALID_LAT_VALUE = 1
635 04:42:07.193592 ==============================================================
636 04:42:07.196944 Enter into Gating configuration >>>>
637 04:42:07.200253 Exit from Gating configuration <<<<
638 04:42:07.204217 Enter into DVFS_PRE_config >>>>>
639 04:42:07.213737 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 04:42:07.217187 Exit from DVFS_PRE_config <<<<<
641 04:42:07.220683 Enter into PICG configuration >>>>
642 04:42:07.223976 Exit from PICG configuration <<<<
643 04:42:07.227383 [RX_INPUT] configuration >>>>>
644 04:42:07.230606 [RX_INPUT] configuration <<<<<
645 04:42:07.234119 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 04:42:07.240462 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 04:42:07.247263 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 04:42:07.250681 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 04:42:07.257315 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 04:42:07.264198 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 04:42:07.267158 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 04:42:07.270557 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 04:42:07.277306 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 04:42:07.281371 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 04:42:07.284587 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 04:42:07.288125 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 04:42:07.291129 ===================================
658 04:42:07.294404 LPDDR4 DRAM CONFIGURATION
659 04:42:07.298306 ===================================
660 04:42:07.301806 EX_ROW_EN[0] = 0x0
661 04:42:07.301902 EX_ROW_EN[1] = 0x0
662 04:42:07.305033 LP4Y_EN = 0x0
663 04:42:07.305121 WORK_FSP = 0x0
664 04:42:07.308318 WL = 0x2
665 04:42:07.308408 RL = 0x2
666 04:42:07.311696 BL = 0x2
667 04:42:07.311786 RPST = 0x0
668 04:42:07.314838 RD_PRE = 0x0
669 04:42:07.314927 WR_PRE = 0x1
670 04:42:07.318084 WR_PST = 0x0
671 04:42:07.318173 DBI_WR = 0x0
672 04:42:07.321578 DBI_RD = 0x0
673 04:42:07.321672 OTF = 0x1
674 04:42:07.324837 ===================================
675 04:42:07.331629 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 04:42:07.334951 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 04:42:07.338204 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 04:42:07.341879 ===================================
679 04:42:07.345059 LPDDR4 DRAM CONFIGURATION
680 04:42:07.348356 ===================================
681 04:42:07.348449 EX_ROW_EN[0] = 0x10
682 04:42:07.351648 EX_ROW_EN[1] = 0x0
683 04:42:07.354907 LP4Y_EN = 0x0
684 04:42:07.354995 WORK_FSP = 0x0
685 04:42:07.358604 WL = 0x2
686 04:42:07.358692 RL = 0x2
687 04:42:07.361604 BL = 0x2
688 04:42:07.361691 RPST = 0x0
689 04:42:07.364984 RD_PRE = 0x0
690 04:42:07.365071 WR_PRE = 0x1
691 04:42:07.368312 WR_PST = 0x0
692 04:42:07.368399 DBI_WR = 0x0
693 04:42:07.371779 DBI_RD = 0x0
694 04:42:07.371866 OTF = 0x1
695 04:42:07.375209 ===================================
696 04:42:07.381553 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 04:42:07.385824 nWR fixed to 40
698 04:42:07.389129 [ModeRegInit_LP4] CH0 RK0
699 04:42:07.389221 [ModeRegInit_LP4] CH0 RK1
700 04:42:07.392479 [ModeRegInit_LP4] CH1 RK0
701 04:42:07.396041 [ModeRegInit_LP4] CH1 RK1
702 04:42:07.396132 match AC timing 13
703 04:42:07.402477 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 04:42:07.406164 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 04:42:07.409564 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 04:42:07.416240 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 04:42:07.419145 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 04:42:07.419251 [EMI DOE] emi_dcm 0
709 04:42:07.425705 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 04:42:07.425804 ==
711 04:42:07.429513 Dram Type= 6, Freq= 0, CH_0, rank 0
712 04:42:07.433228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 04:42:07.433322 ==
714 04:42:07.436920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 04:42:07.443901 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 04:42:07.453596 [CA 0] Center 38 (7~69) winsize 63
717 04:42:07.457788 [CA 1] Center 38 (7~69) winsize 63
718 04:42:07.461079 [CA 2] Center 35 (5~66) winsize 62
719 04:42:07.464490 [CA 3] Center 35 (5~66) winsize 62
720 04:42:07.467896 [CA 4] Center 34 (4~65) winsize 62
721 04:42:07.471308 [CA 5] Center 33 (3~64) winsize 62
722 04:42:07.471403
723 04:42:07.475218 [CmdBusTrainingLP45] Vref(ca) range 1: 34
724 04:42:07.475308
725 04:42:07.478631 [CATrainingPosCal] consider 1 rank data
726 04:42:07.482324 u2DelayCellTimex100 = 270/100 ps
727 04:42:07.486223 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
728 04:42:07.489740 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 04:42:07.493335 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 04:42:07.497232 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
731 04:42:07.501015 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
732 04:42:07.504328 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 04:42:07.504427
734 04:42:07.508309 CA PerBit enable=1, Macro0, CA PI delay=33
735 04:42:07.508402
736 04:42:07.508469 [CBTSetCACLKResult] CA Dly = 33
737 04:42:07.512043 CS Dly: 6 (0~37)
738 04:42:07.512132 ==
739 04:42:07.515499 Dram Type= 6, Freq= 0, CH_0, rank 1
740 04:42:07.519261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 04:42:07.519357 ==
742 04:42:07.523137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 04:42:07.530017 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 04:42:07.540319 [CA 0] Center 38 (7~69) winsize 63
745 04:42:07.544254 [CA 1] Center 38 (7~69) winsize 63
746 04:42:07.547961 [CA 2] Center 36 (6~67) winsize 62
747 04:42:07.551564 [CA 3] Center 36 (5~67) winsize 63
748 04:42:07.555875 [CA 4] Center 35 (4~66) winsize 63
749 04:42:07.555980 [CA 5] Center 34 (4~65) winsize 62
750 04:42:07.556049
751 04:42:07.558855 [CmdBusTrainingLP45] Vref(ca) range 1: 34
752 04:42:07.563034
753 04:42:07.563129 [CATrainingPosCal] consider 2 rank data
754 04:42:07.566707 u2DelayCellTimex100 = 270/100 ps
755 04:42:07.570585 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 04:42:07.573957 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
757 04:42:07.577911 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 04:42:07.581745 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 04:42:07.585069 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 04:42:07.588930 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 04:42:07.589030
762 04:42:07.592789 CA PerBit enable=1, Macro0, CA PI delay=34
763 04:42:07.592883
764 04:42:07.596668 [CBTSetCACLKResult] CA Dly = 34
765 04:42:07.596769 CS Dly: 6 (0~38)
766 04:42:07.600073
767 04:42:07.600165 ----->DramcWriteLeveling(PI) begin...
768 04:42:07.603991 ==
769 04:42:07.604085 Dram Type= 6, Freq= 0, CH_0, rank 0
770 04:42:07.607406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 04:42:07.611248 ==
772 04:42:07.611346 Write leveling (Byte 0): 31 => 31
773 04:42:07.615029 Write leveling (Byte 1): 30 => 30
774 04:42:07.619031 DramcWriteLeveling(PI) end<-----
775 04:42:07.619131
776 04:42:07.619222 ==
777 04:42:07.622432 Dram Type= 6, Freq= 0, CH_0, rank 0
778 04:42:07.626301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 04:42:07.626399 ==
780 04:42:07.629827 [Gating] SW mode calibration
781 04:42:07.637266 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 04:42:07.640855 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 04:42:07.644743 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 04:42:07.652205 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
785 04:42:07.656246 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 04:42:07.659343 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 04:42:07.663818 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 04:42:07.666764 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 04:42:07.670711 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 04:42:07.677631 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 04:42:07.681385 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 04:42:07.685355 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 04:42:07.689240 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 04:42:07.692731 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 04:42:07.700672 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 04:42:07.704180 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 04:42:07.708021 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 04:42:07.711625 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 04:42:07.715183 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 04:42:07.719232 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
801 04:42:07.725983 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
802 04:42:07.729961 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 04:42:07.733963 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 04:42:07.737653 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 04:42:07.741028 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 04:42:07.748221 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 04:42:07.752460 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 04:42:07.755874 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 04:42:07.759637 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 04:42:07.763153 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
811 04:42:07.769779 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 04:42:07.772906 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 04:42:07.776389 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 04:42:07.782964 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 04:42:07.786395 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 04:42:07.789690 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
817 04:42:07.796482 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (1 1) (0 0)
818 04:42:07.800029 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 04:42:07.802896 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 04:42:07.809819 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 04:42:07.813180 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 04:42:07.816408 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 04:42:07.822875 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 04:42:07.826343 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
825 04:42:07.829685 0 11 8 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
826 04:42:07.833245 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
827 04:42:07.839689 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 04:42:07.843061 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 04:42:07.846310 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 04:42:07.853112 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 04:42:07.856576 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
832 04:42:07.859728 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 04:42:07.866658 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 04:42:07.869546 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 04:42:07.873405 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 04:42:07.879705 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 04:42:07.883149 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 04:42:07.886393 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 04:42:07.893074 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 04:42:07.896535 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 04:42:07.899975 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 04:42:07.906705 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 04:42:07.910209 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 04:42:07.913145 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 04:42:07.916525 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 04:42:07.923243 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 04:42:07.926683 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 04:42:07.930108 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
849 04:42:07.933521 Total UI for P1: 0, mck2ui 16
850 04:42:07.936515 best dqsien dly found for B0: ( 0, 14, 2)
851 04:42:07.943162 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 04:42:07.946614 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 04:42:07.949969 Total UI for P1: 0, mck2ui 16
854 04:42:07.953413 best dqsien dly found for B1: ( 0, 14, 6)
855 04:42:07.956705 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
856 04:42:07.960147 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
857 04:42:07.960239
858 04:42:07.963557 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
859 04:42:07.966636 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
860 04:42:07.970283 [Gating] SW calibration Done
861 04:42:07.970383 ==
862 04:42:07.973385 Dram Type= 6, Freq= 0, CH_0, rank 0
863 04:42:07.976538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 04:42:07.976667 ==
865 04:42:07.979936 RX Vref Scan: 0
866 04:42:07.980054
867 04:42:07.983480 RX Vref 0 -> 0, step: 1
868 04:42:07.983572
869 04:42:07.983660 RX Delay -130 -> 252, step: 16
870 04:42:07.990436 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
871 04:42:07.993614 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
872 04:42:07.996802 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
873 04:42:08.000196 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
874 04:42:08.003756 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
875 04:42:08.009934 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 04:42:08.013477 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
877 04:42:08.016984 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 04:42:08.019943 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 04:42:08.023324 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
880 04:42:08.029917 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
881 04:42:08.033565 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
882 04:42:08.037041 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
883 04:42:08.040275 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
884 04:42:08.043661 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 04:42:08.050181 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
886 04:42:08.050290 ==
887 04:42:08.053519 Dram Type= 6, Freq= 0, CH_0, rank 0
888 04:42:08.056498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 04:42:08.056592 ==
890 04:42:08.056659 DQS Delay:
891 04:42:08.060059 DQS0 = 0, DQS1 = 0
892 04:42:08.060147 DQM Delay:
893 04:42:08.063280 DQM0 = 90, DQM1 = 80
894 04:42:08.063361 DQ Delay:
895 04:42:08.066953 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
896 04:42:08.070487 DQ4 =85, DQ5 =77, DQ6 =109, DQ7 =101
897 04:42:08.073620 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
898 04:42:08.076668 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
899 04:42:08.076802
900 04:42:08.076899
901 04:42:08.077005 ==
902 04:42:08.080404 Dram Type= 6, Freq= 0, CH_0, rank 0
903 04:42:08.083693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 04:42:08.083781 ==
905 04:42:08.086848
906 04:42:08.086937
907 04:42:08.087004 TX Vref Scan disable
908 04:42:08.090346 == TX Byte 0 ==
909 04:42:08.093540 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
910 04:42:08.096960 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
911 04:42:08.099915 == TX Byte 1 ==
912 04:42:08.103640 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
913 04:42:08.106780 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
914 04:42:08.106890 ==
915 04:42:08.110376 Dram Type= 6, Freq= 0, CH_0, rank 0
916 04:42:08.116782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 04:42:08.116890 ==
918 04:42:08.128681 TX Vref=22, minBit 6, minWin=27, winSum=442
919 04:42:08.132070 TX Vref=24, minBit 11, minWin=26, winSum=444
920 04:42:08.135401 TX Vref=26, minBit 8, minWin=27, winSum=446
921 04:42:08.138957 TX Vref=28, minBit 10, minWin=27, winSum=454
922 04:42:08.142417 TX Vref=30, minBit 6, minWin=28, winSum=455
923 04:42:08.148587 TX Vref=32, minBit 12, minWin=27, winSum=451
924 04:42:08.152071 [TxChooseVref] Worse bit 6, Min win 28, Win sum 455, Final Vref 30
925 04:42:08.152172
926 04:42:08.155520 Final TX Range 1 Vref 30
927 04:42:08.155612
928 04:42:08.155681 ==
929 04:42:08.158456 Dram Type= 6, Freq= 0, CH_0, rank 0
930 04:42:08.162266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 04:42:08.162362 ==
932 04:42:08.165549
933 04:42:08.165640
934 04:42:08.165708 TX Vref Scan disable
935 04:42:08.168762 == TX Byte 0 ==
936 04:42:08.172340 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
937 04:42:08.175684 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
938 04:42:08.179241 == TX Byte 1 ==
939 04:42:08.182211 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
940 04:42:08.185862 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
941 04:42:08.188712
942 04:42:08.188807 [DATLAT]
943 04:42:08.188879 Freq=800, CH0 RK0
944 04:42:08.188945
945 04:42:08.192269 DATLAT Default: 0xa
946 04:42:08.192384 0, 0xFFFF, sum = 0
947 04:42:08.195403 1, 0xFFFF, sum = 0
948 04:42:08.195498 2, 0xFFFF, sum = 0
949 04:42:08.199008 3, 0xFFFF, sum = 0
950 04:42:08.199110 4, 0xFFFF, sum = 0
951 04:42:08.202301 5, 0xFFFF, sum = 0
952 04:42:08.202392 6, 0xFFFF, sum = 0
953 04:42:08.205854 7, 0xFFFF, sum = 0
954 04:42:08.209142 8, 0xFFFF, sum = 0
955 04:42:08.209235 9, 0x0, sum = 1
956 04:42:08.209312 10, 0x0, sum = 2
957 04:42:08.212487 11, 0x0, sum = 3
958 04:42:08.212577 12, 0x0, sum = 4
959 04:42:08.215917 best_step = 10
960 04:42:08.216007
961 04:42:08.216077 ==
962 04:42:08.218851 Dram Type= 6, Freq= 0, CH_0, rank 0
963 04:42:08.222317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 04:42:08.222408 ==
965 04:42:08.225892 RX Vref Scan: 1
966 04:42:08.225996
967 04:42:08.226068 Set Vref Range= 32 -> 127
968 04:42:08.226134
969 04:42:08.228982 RX Vref 32 -> 127, step: 1
970 04:42:08.229072
971 04:42:08.232253 RX Delay -79 -> 252, step: 8
972 04:42:08.232344
973 04:42:08.235617 Set Vref, RX VrefLevel [Byte0]: 32
974 04:42:08.239055 [Byte1]: 32
975 04:42:08.239146
976 04:42:08.242499 Set Vref, RX VrefLevel [Byte0]: 33
977 04:42:08.245499 [Byte1]: 33
978 04:42:08.249085
979 04:42:08.249174 Set Vref, RX VrefLevel [Byte0]: 34
980 04:42:08.252469 [Byte1]: 34
981 04:42:08.256925
982 04:42:08.257013 Set Vref, RX VrefLevel [Byte0]: 35
983 04:42:08.259898 [Byte1]: 35
984 04:42:08.264104
985 04:42:08.264196 Set Vref, RX VrefLevel [Byte0]: 36
986 04:42:08.267362 [Byte1]: 36
987 04:42:08.272067
988 04:42:08.272172 Set Vref, RX VrefLevel [Byte0]: 37
989 04:42:08.275510 [Byte1]: 37
990 04:42:08.279400
991 04:42:08.279500 Set Vref, RX VrefLevel [Byte0]: 38
992 04:42:08.282572 [Byte1]: 38
993 04:42:08.286761
994 04:42:08.286875 Set Vref, RX VrefLevel [Byte0]: 39
995 04:42:08.290135 [Byte1]: 39
996 04:42:08.294097
997 04:42:08.294232 Set Vref, RX VrefLevel [Byte0]: 40
998 04:42:08.297707 [Byte1]: 40
999 04:42:08.302166
1000 04:42:08.302269 Set Vref, RX VrefLevel [Byte0]: 41
1001 04:42:08.305440 [Byte1]: 41
1002 04:42:08.310150
1003 04:42:08.310248 Set Vref, RX VrefLevel [Byte0]: 42
1004 04:42:08.313280 [Byte1]: 42
1005 04:42:08.317354
1006 04:42:08.317447 Set Vref, RX VrefLevel [Byte0]: 43
1007 04:42:08.320855 [Byte1]: 43
1008 04:42:08.325094
1009 04:42:08.325190 Set Vref, RX VrefLevel [Byte0]: 44
1010 04:42:08.327933 [Byte1]: 44
1011 04:42:08.332766
1012 04:42:08.332866 Set Vref, RX VrefLevel [Byte0]: 45
1013 04:42:08.335795 [Byte1]: 45
1014 04:42:08.339691
1015 04:42:08.339788 Set Vref, RX VrefLevel [Byte0]: 46
1016 04:42:08.343054 [Byte1]: 46
1017 04:42:08.347501
1018 04:42:08.347592 Set Vref, RX VrefLevel [Byte0]: 47
1019 04:42:08.350741 [Byte1]: 47
1020 04:42:08.354714
1021 04:42:08.354806 Set Vref, RX VrefLevel [Byte0]: 48
1022 04:42:08.358096 [Byte1]: 48
1023 04:42:08.362155
1024 04:42:08.362246 Set Vref, RX VrefLevel [Byte0]: 49
1025 04:42:08.365595 [Byte1]: 49
1026 04:42:08.370067
1027 04:42:08.370158 Set Vref, RX VrefLevel [Byte0]: 50
1028 04:42:08.373343 [Byte1]: 50
1029 04:42:08.377819
1030 04:42:08.377910 Set Vref, RX VrefLevel [Byte0]: 51
1031 04:42:08.383955 [Byte1]: 51
1032 04:42:08.384049
1033 04:42:08.387282 Set Vref, RX VrefLevel [Byte0]: 52
1034 04:42:08.390399 [Byte1]: 52
1035 04:42:08.390490
1036 04:42:08.393795 Set Vref, RX VrefLevel [Byte0]: 53
1037 04:42:08.397143 [Byte1]: 53
1038 04:42:08.397239
1039 04:42:08.400597 Set Vref, RX VrefLevel [Byte0]: 54
1040 04:42:08.403856 [Byte1]: 54
1041 04:42:08.407824
1042 04:42:08.407918 Set Vref, RX VrefLevel [Byte0]: 55
1043 04:42:08.410855 [Byte1]: 55
1044 04:42:08.415118
1045 04:42:08.415211 Set Vref, RX VrefLevel [Byte0]: 56
1046 04:42:08.418344 [Byte1]: 56
1047 04:42:08.422683
1048 04:42:08.422777 Set Vref, RX VrefLevel [Byte0]: 57
1049 04:42:08.426193 [Byte1]: 57
1050 04:42:08.430431
1051 04:42:08.430523 Set Vref, RX VrefLevel [Byte0]: 58
1052 04:42:08.433409 [Byte1]: 58
1053 04:42:08.437821
1054 04:42:08.437935 Set Vref, RX VrefLevel [Byte0]: 59
1055 04:42:08.441211 [Byte1]: 59
1056 04:42:08.445481
1057 04:42:08.445603 Set Vref, RX VrefLevel [Byte0]: 60
1058 04:42:08.448650 [Byte1]: 60
1059 04:42:08.452920
1060 04:42:08.453011 Set Vref, RX VrefLevel [Byte0]: 61
1061 04:42:08.456380 [Byte1]: 61
1062 04:42:08.460773
1063 04:42:08.460862 Set Vref, RX VrefLevel [Byte0]: 62
1064 04:42:08.463699 [Byte1]: 62
1065 04:42:08.468171
1066 04:42:08.468259 Set Vref, RX VrefLevel [Byte0]: 63
1067 04:42:08.471234 [Byte1]: 63
1068 04:42:08.475690
1069 04:42:08.475775 Set Vref, RX VrefLevel [Byte0]: 64
1070 04:42:08.479118 [Byte1]: 64
1071 04:42:08.482923
1072 04:42:08.483011 Set Vref, RX VrefLevel [Byte0]: 65
1073 04:42:08.486733 [Byte1]: 65
1074 04:42:08.490598
1075 04:42:08.490687 Set Vref, RX VrefLevel [Byte0]: 66
1076 04:42:08.493799 [Byte1]: 66
1077 04:42:08.498002
1078 04:42:08.498116 Set Vref, RX VrefLevel [Byte0]: 67
1079 04:42:08.501447 [Byte1]: 67
1080 04:42:08.505821
1081 04:42:08.505958 Set Vref, RX VrefLevel [Byte0]: 68
1082 04:42:08.509086 [Byte1]: 68
1083 04:42:08.512987
1084 04:42:08.513107 Set Vref, RX VrefLevel [Byte0]: 69
1085 04:42:08.516370 [Byte1]: 69
1086 04:42:08.520943
1087 04:42:08.521039 Set Vref, RX VrefLevel [Byte0]: 70
1088 04:42:08.524089 [Byte1]: 70
1089 04:42:08.528287
1090 04:42:08.528402 Set Vref, RX VrefLevel [Byte0]: 71
1091 04:42:08.531852 [Byte1]: 71
1092 04:42:08.536168
1093 04:42:08.536265 Set Vref, RX VrefLevel [Byte0]: 72
1094 04:42:08.539245 [Byte1]: 72
1095 04:42:08.543526
1096 04:42:08.543647 Set Vref, RX VrefLevel [Byte0]: 73
1097 04:42:08.546940 [Byte1]: 73
1098 04:42:08.550791
1099 04:42:08.550882 Set Vref, RX VrefLevel [Byte0]: 74
1100 04:42:08.554257 [Byte1]: 74
1101 04:42:08.558341
1102 04:42:08.558436 Set Vref, RX VrefLevel [Byte0]: 75
1103 04:42:08.561784 [Byte1]: 75
1104 04:42:08.565937
1105 04:42:08.566037 Set Vref, RX VrefLevel [Byte0]: 76
1106 04:42:08.569409 [Byte1]: 76
1107 04:42:08.573672
1108 04:42:08.573768 Set Vref, RX VrefLevel [Byte0]: 77
1109 04:42:08.576895 [Byte1]: 77
1110 04:42:08.581163
1111 04:42:08.581284 Final RX Vref Byte 0 = 62 to rank0
1112 04:42:08.584419 Final RX Vref Byte 1 = 61 to rank0
1113 04:42:08.588085 Final RX Vref Byte 0 = 62 to rank1
1114 04:42:08.591482 Final RX Vref Byte 1 = 61 to rank1==
1115 04:42:08.595207 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 04:42:08.597843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 04:42:08.601090 ==
1118 04:42:08.601196 DQS Delay:
1119 04:42:08.601298 DQS0 = 0, DQS1 = 0
1120 04:42:08.604718 DQM Delay:
1121 04:42:08.604823 DQM0 = 93, DQM1 = 82
1122 04:42:08.607658 DQ Delay:
1123 04:42:08.611320 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1124 04:42:08.614708 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1125 04:42:08.614805 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1126 04:42:08.621261 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =92
1127 04:42:08.621367
1128 04:42:08.621437
1129 04:42:08.627905 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 393 ps
1130 04:42:08.631315 CH0 RK0: MR19=606, MR18=3F3A
1131 04:42:08.638040 CH0_RK0: MR19=0x606, MR18=0x3F3A, DQSOSC=393, MR23=63, INC=95, DEC=63
1132 04:42:08.638169
1133 04:42:08.641355 ----->DramcWriteLeveling(PI) begin...
1134 04:42:08.641447 ==
1135 04:42:08.644773 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 04:42:08.648278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 04:42:08.648374 ==
1138 04:42:08.651248 Write leveling (Byte 0): 32 => 32
1139 04:42:08.654840 Write leveling (Byte 1): 28 => 28
1140 04:42:08.657891 DramcWriteLeveling(PI) end<-----
1141 04:42:08.658023
1142 04:42:08.658091 ==
1143 04:42:08.661406 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 04:42:08.664915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 04:42:08.665006 ==
1146 04:42:08.667919 [Gating] SW mode calibration
1147 04:42:08.674821 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 04:42:08.681304 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 04:42:08.684616 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 04:42:08.687861 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1151 04:42:08.694864 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 04:42:08.698218 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 04:42:08.701232 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 04:42:08.748727 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 04:42:08.748886 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 04:42:08.748955 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 04:42:08.749210 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 04:42:08.749277 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 04:42:08.749349 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 04:42:08.749411 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 04:42:08.749666 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 04:42:08.749769 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 04:42:08.749872 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 04:42:08.792828 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 04:42:08.792990 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1166 04:42:08.793257 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1167 04:42:08.793330 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 04:42:08.793456 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 04:42:08.794070 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 04:42:08.794155 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 04:42:08.794222 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 04:42:08.794634 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 04:42:08.794907 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 04:42:08.794979 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 04:42:08.823214 0 9 8 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (0 0)
1176 04:42:08.823392 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 04:42:08.823657 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 04:42:08.823728 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 04:42:08.823792 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 04:42:08.823851 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 04:42:08.827229 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1182 04:42:08.830153 0 10 4 | B1->B0 | 3333 2f2f | 1 1 | (1 0) (0 0)
1183 04:42:08.833832 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1184 04:42:08.836858 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 04:42:08.844195 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 04:42:08.847100 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 04:42:08.850692 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 04:42:08.857335 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 04:42:08.860658 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 04:42:08.863542 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1191 04:42:08.870527 0 11 8 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
1192 04:42:08.873694 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 04:42:08.877206 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 04:42:08.883918 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 04:42:08.888504 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 04:42:08.892105 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 04:42:08.896131 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 04:42:08.899454 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1199 04:42:08.906059 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1200 04:42:08.909174 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 04:42:08.913712 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 04:42:08.916688 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 04:42:08.923384 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 04:42:08.926879 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 04:42:08.930138 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 04:42:08.936683 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 04:42:08.940026 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 04:42:08.943609 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 04:42:08.949855 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 04:42:08.953390 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 04:42:08.956741 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 04:42:08.959975 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 04:42:08.966824 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 04:42:08.970170 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1215 04:42:08.973630 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1216 04:42:08.980052 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 04:42:08.983375 Total UI for P1: 0, mck2ui 16
1218 04:42:08.986886 best dqsien dly found for B0: ( 0, 14, 6)
1219 04:42:08.986976 Total UI for P1: 0, mck2ui 16
1220 04:42:08.993264 best dqsien dly found for B1: ( 0, 14, 8)
1221 04:42:08.996970 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1222 04:42:09.000230 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1223 04:42:09.000327
1224 04:42:09.003686 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1225 04:42:09.006557 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1226 04:42:09.009891 [Gating] SW calibration Done
1227 04:42:09.010035 ==
1228 04:42:09.013546 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 04:42:09.016757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 04:42:09.016874 ==
1231 04:42:09.019937 RX Vref Scan: 0
1232 04:42:09.020027
1233 04:42:09.020095 RX Vref 0 -> 0, step: 1
1234 04:42:09.020156
1235 04:42:09.023358 RX Delay -130 -> 252, step: 16
1236 04:42:09.026751 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1237 04:42:09.033257 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1238 04:42:09.037110 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1239 04:42:09.040071 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1240 04:42:09.043463 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1241 04:42:09.046604 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1242 04:42:09.053415 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1243 04:42:09.057025 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1244 04:42:09.059977 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1245 04:42:09.063517 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1246 04:42:09.066675 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1247 04:42:09.070593 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1248 04:42:09.077138 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1249 04:42:09.080085 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1250 04:42:09.083555 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1251 04:42:09.086995 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1252 04:42:09.087146 ==
1253 04:42:09.090122 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 04:42:09.097010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 04:42:09.097146 ==
1256 04:42:09.097243 DQS Delay:
1257 04:42:09.100380 DQS0 = 0, DQS1 = 0
1258 04:42:09.100471 DQM Delay:
1259 04:42:09.100537 DQM0 = 88, DQM1 = 82
1260 04:42:09.103761 DQ Delay:
1261 04:42:09.106903 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1262 04:42:09.110779 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1263 04:42:09.113897 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1264 04:42:09.117259 DQ12 =77, DQ13 =93, DQ14 =93, DQ15 =93
1265 04:42:09.117354
1266 04:42:09.117422
1267 04:42:09.117484 ==
1268 04:42:09.120539 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 04:42:09.124015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 04:42:09.124107 ==
1271 04:42:09.124175
1272 04:42:09.124256
1273 04:42:09.127550 TX Vref Scan disable
1274 04:42:09.127638 == TX Byte 0 ==
1275 04:42:09.133611 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1276 04:42:09.137159 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1277 04:42:09.137289 == TX Byte 1 ==
1278 04:42:09.144006 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1279 04:42:09.147140 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1280 04:42:09.147235 ==
1281 04:42:09.150858 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 04:42:09.153873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 04:42:09.154005 ==
1284 04:42:09.168409 TX Vref=22, minBit 3, minWin=27, winSum=446
1285 04:42:09.171796 TX Vref=24, minBit 8, minWin=27, winSum=449
1286 04:42:09.175163 TX Vref=26, minBit 8, minWin=27, winSum=451
1287 04:42:09.178120 TX Vref=28, minBit 8, minWin=27, winSum=455
1288 04:42:09.181623 TX Vref=30, minBit 8, minWin=27, winSum=456
1289 04:42:09.184740 TX Vref=32, minBit 4, minWin=28, winSum=458
1290 04:42:09.191599 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 32
1291 04:42:09.191709
1292 04:42:09.194988 Final TX Range 1 Vref 32
1293 04:42:09.195087
1294 04:42:09.195154 ==
1295 04:42:09.198068 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 04:42:09.201610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 04:42:09.201740 ==
1298 04:42:09.201835
1299 04:42:09.204586
1300 04:42:09.204696 TX Vref Scan disable
1301 04:42:09.208047 == TX Byte 0 ==
1302 04:42:09.211611 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1303 04:42:09.214794 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1304 04:42:09.218685 == TX Byte 1 ==
1305 04:42:09.221381 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1306 04:42:09.225175 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1307 04:42:09.228231
1308 04:42:09.228356 [DATLAT]
1309 04:42:09.228457 Freq=800, CH0 RK1
1310 04:42:09.228556
1311 04:42:09.231643 DATLAT Default: 0xa
1312 04:42:09.231756 0, 0xFFFF, sum = 0
1313 04:42:09.235124 1, 0xFFFF, sum = 0
1314 04:42:09.235241 2, 0xFFFF, sum = 0
1315 04:42:09.238343 3, 0xFFFF, sum = 0
1316 04:42:09.238451 4, 0xFFFF, sum = 0
1317 04:42:09.241582 5, 0xFFFF, sum = 0
1318 04:42:09.241672 6, 0xFFFF, sum = 0
1319 04:42:09.245083 7, 0xFFFF, sum = 0
1320 04:42:09.245172 8, 0xFFFF, sum = 0
1321 04:42:09.248626 9, 0x0, sum = 1
1322 04:42:09.248717 10, 0x0, sum = 2
1323 04:42:09.251811 11, 0x0, sum = 3
1324 04:42:09.251900 12, 0x0, sum = 4
1325 04:42:09.255256 best_step = 10
1326 04:42:09.255345
1327 04:42:09.255412 ==
1328 04:42:09.258631 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 04:42:09.261836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 04:42:09.261927 ==
1331 04:42:09.265038 RX Vref Scan: 0
1332 04:42:09.265126
1333 04:42:09.265193 RX Vref 0 -> 0, step: 1
1334 04:42:09.265254
1335 04:42:09.268534 RX Delay -79 -> 252, step: 8
1336 04:42:09.275477 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1337 04:42:09.278852 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1338 04:42:09.282177 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1339 04:42:09.285125 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1340 04:42:09.288559 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1341 04:42:09.292220 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1342 04:42:09.298772 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1343 04:42:09.302146 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1344 04:42:09.305735 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1345 04:42:09.308947 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1346 04:42:09.312304 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1347 04:42:09.318695 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1348 04:42:09.321989 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1349 04:42:09.325509 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1350 04:42:09.328744 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1351 04:42:09.331957 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1352 04:42:09.335317 ==
1353 04:42:09.338873 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 04:42:09.342490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 04:42:09.342586 ==
1356 04:42:09.342653 DQS Delay:
1357 04:42:09.345490 DQS0 = 0, DQS1 = 0
1358 04:42:09.345574 DQM Delay:
1359 04:42:09.348945 DQM0 = 90, DQM1 = 81
1360 04:42:09.349029 DQ Delay:
1361 04:42:09.352373 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1362 04:42:09.355371 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1363 04:42:09.358791 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1364 04:42:09.362155 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1365 04:42:09.362249
1366 04:42:09.362317
1367 04:42:09.368919 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1368 04:42:09.372086 CH0 RK1: MR19=606, MR18=3F19
1369 04:42:09.379108 CH0_RK1: MR19=0x606, MR18=0x3F19, DQSOSC=393, MR23=63, INC=95, DEC=63
1370 04:42:09.382117 [RxdqsGatingPostProcess] freq 800
1371 04:42:09.385553 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 04:42:09.388594 Pre-setting of DQS Precalculation
1373 04:42:09.395217 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 04:42:09.395323 ==
1375 04:42:09.399014 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 04:42:09.402225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 04:42:09.402316 ==
1378 04:42:09.409215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 04:42:09.415454 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 04:42:09.423316 [CA 0] Center 36 (6~67) winsize 62
1381 04:42:09.426811 [CA 1] Center 36 (6~67) winsize 62
1382 04:42:09.429889 [CA 2] Center 35 (5~65) winsize 61
1383 04:42:09.433207 [CA 3] Center 34 (4~65) winsize 62
1384 04:42:09.436650 [CA 4] Center 34 (4~65) winsize 62
1385 04:42:09.439978 [CA 5] Center 33 (3~64) winsize 62
1386 04:42:09.440066
1387 04:42:09.443123 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1388 04:42:09.443215
1389 04:42:09.446777 [CATrainingPosCal] consider 1 rank data
1390 04:42:09.449755 u2DelayCellTimex100 = 270/100 ps
1391 04:42:09.453001 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1392 04:42:09.459977 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1393 04:42:09.462986 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1394 04:42:09.466437 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1395 04:42:09.469799 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 04:42:09.473378 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 04:42:09.473471
1398 04:42:09.476468 CA PerBit enable=1, Macro0, CA PI delay=33
1399 04:42:09.476566
1400 04:42:09.479837 [CBTSetCACLKResult] CA Dly = 33
1401 04:42:09.479924 CS Dly: 4 (0~35)
1402 04:42:09.482754 ==
1403 04:42:09.486228 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 04:42:09.489705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 04:42:09.489794 ==
1406 04:42:09.493150 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 04:42:09.499549 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 04:42:09.509869 [CA 0] Center 37 (6~68) winsize 63
1409 04:42:09.513186 [CA 1] Center 37 (6~68) winsize 63
1410 04:42:09.516109 [CA 2] Center 35 (5~66) winsize 62
1411 04:42:09.519391 [CA 3] Center 34 (4~65) winsize 62
1412 04:42:09.522831 [CA 4] Center 34 (4~65) winsize 62
1413 04:42:09.526085 [CA 5] Center 34 (4~64) winsize 61
1414 04:42:09.526178
1415 04:42:09.529669 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1416 04:42:09.529765
1417 04:42:09.532632 [CATrainingPosCal] consider 2 rank data
1418 04:42:09.536173 u2DelayCellTimex100 = 270/100 ps
1419 04:42:09.540020 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1420 04:42:09.543197 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1421 04:42:09.546659 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1422 04:42:09.553379 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1423 04:42:09.557081 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 04:42:09.557183 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1425 04:42:09.561089
1426 04:42:09.564489 CA PerBit enable=1, Macro0, CA PI delay=34
1427 04:42:09.564582
1428 04:42:09.564652 [CBTSetCACLKResult] CA Dly = 34
1429 04:42:09.568476 CS Dly: 5 (0~37)
1430 04:42:09.568567
1431 04:42:09.572009 ----->DramcWriteLeveling(PI) begin...
1432 04:42:09.572101 ==
1433 04:42:09.575955 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 04:42:09.579596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 04:42:09.579692 ==
1436 04:42:09.583774 Write leveling (Byte 0): 25 => 25
1437 04:42:09.583868 Write leveling (Byte 1): 30 => 30
1438 04:42:09.586972 DramcWriteLeveling(PI) end<-----
1439 04:42:09.587081
1440 04:42:09.587151 ==
1441 04:42:09.590307 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 04:42:09.597115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 04:42:09.597216 ==
1444 04:42:09.600475 [Gating] SW mode calibration
1445 04:42:09.606825 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 04:42:09.610327 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 04:42:09.617186 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 04:42:09.620540 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1449 04:42:09.623801 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 04:42:09.626826 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 04:42:09.633934 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 04:42:09.637032 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 04:42:09.640218 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 04:42:09.646985 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 04:42:09.650391 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 04:42:09.653651 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 04:42:09.660452 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 04:42:09.663848 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 04:42:09.667088 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 04:42:09.673735 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 04:42:09.676989 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 04:42:09.680221 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 04:42:09.687180 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1464 04:42:09.690267 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1465 04:42:09.693999 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 04:42:09.700464 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 04:42:09.703426 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 04:42:09.707173 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 04:42:09.713585 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 04:42:09.717079 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 04:42:09.720346 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 04:42:09.723721 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1473 04:42:09.730147 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1474 04:42:09.733481 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 04:42:09.737112 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 04:42:09.743527 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 04:42:09.747096 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 04:42:09.750392 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 04:42:09.756920 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1480 04:42:09.760350 0 10 4 | B1->B0 | 2f2f 2f2f | 0 0 | (1 0) (0 0)
1481 04:42:09.763744 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1482 04:42:09.770395 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 04:42:09.773853 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 04:42:09.776981 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 04:42:09.783723 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 04:42:09.786901 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 04:42:09.790549 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 04:42:09.797025 0 11 4 | B1->B0 | 3232 3535 | 1 0 | (0 0) (0 0)
1489 04:42:09.800715 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1490 04:42:09.803601 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 04:42:09.807037 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 04:42:09.813921 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 04:42:09.817396 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 04:42:09.820726 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 04:42:09.827372 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1496 04:42:09.830557 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1497 04:42:09.833758 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 04:42:09.840566 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 04:42:09.843933 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 04:42:09.847285 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 04:42:09.853891 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 04:42:09.857387 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 04:42:09.860849 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 04:42:09.867810 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 04:42:09.871112 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 04:42:09.874207 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 04:42:09.877212 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 04:42:09.884360 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 04:42:09.887228 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 04:42:09.890895 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 04:42:09.897598 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1512 04:42:09.900899 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1513 04:42:09.904413 Total UI for P1: 0, mck2ui 16
1514 04:42:09.907503 best dqsien dly found for B0: ( 0, 14, 0)
1515 04:42:09.910997 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 04:42:09.914074 Total UI for P1: 0, mck2ui 16
1517 04:42:09.917567 best dqsien dly found for B1: ( 0, 14, 4)
1518 04:42:09.921034 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1519 04:42:09.924310 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1520 04:42:09.924389
1521 04:42:09.927931 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1522 04:42:09.934246 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1523 04:42:09.934326 [Gating] SW calibration Done
1524 04:42:09.934392 ==
1525 04:42:09.937811 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 04:42:09.944244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 04:42:09.944360 ==
1528 04:42:09.944431 RX Vref Scan: 0
1529 04:42:09.944496
1530 04:42:09.947735 RX Vref 0 -> 0, step: 1
1531 04:42:09.947843
1532 04:42:09.950928 RX Delay -130 -> 252, step: 16
1533 04:42:09.954497 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1534 04:42:09.957847 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1535 04:42:09.960953 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1536 04:42:09.967660 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1537 04:42:09.970703 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1538 04:42:09.974407 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1539 04:42:09.977470 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1540 04:42:09.981004 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1541 04:42:09.984381 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1542 04:42:09.990884 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1543 04:42:09.994225 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1544 04:42:09.997446 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1545 04:42:10.001421 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1546 04:42:10.007766 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1547 04:42:10.011050 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1548 04:42:10.014316 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1549 04:42:10.014421 ==
1550 04:42:10.017614 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 04:42:10.021187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1552 04:42:10.021273 ==
1553 04:42:10.024292 DQS Delay:
1554 04:42:10.024403 DQS0 = 0, DQS1 = 0
1555 04:42:10.024500 DQM Delay:
1556 04:42:10.027666 DQM0 = 90, DQM1 = 82
1557 04:42:10.027787 DQ Delay:
1558 04:42:10.031048 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1559 04:42:10.034635 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =93
1560 04:42:10.037570 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1561 04:42:10.041054 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1562 04:42:10.041139
1563 04:42:10.041206
1564 04:42:10.041273 ==
1565 04:42:10.044822 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 04:42:10.051285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 04:42:10.051371 ==
1568 04:42:10.051438
1569 04:42:10.051502
1570 04:42:10.051561 TX Vref Scan disable
1571 04:42:10.055016 == TX Byte 0 ==
1572 04:42:10.058398 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1573 04:42:10.061528 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1574 04:42:10.064658 == TX Byte 1 ==
1575 04:42:10.068222 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1576 04:42:10.071496 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1577 04:42:10.075235 ==
1578 04:42:10.078256 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 04:42:10.081658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 04:42:10.081742 ==
1581 04:42:10.094147 TX Vref=22, minBit 8, minWin=27, winSum=445
1582 04:42:10.097507 TX Vref=24, minBit 8, minWin=27, winSum=448
1583 04:42:10.100891 TX Vref=26, minBit 8, minWin=27, winSum=450
1584 04:42:10.104603 TX Vref=28, minBit 8, minWin=27, winSum=453
1585 04:42:10.107376 TX Vref=30, minBit 8, minWin=27, winSum=457
1586 04:42:10.111035 TX Vref=32, minBit 8, minWin=27, winSum=456
1587 04:42:10.117652 [TxChooseVref] Worse bit 8, Min win 27, Win sum 457, Final Vref 30
1588 04:42:10.117767
1589 04:42:10.121279 Final TX Range 1 Vref 30
1590 04:42:10.121415
1591 04:42:10.121508 ==
1592 04:42:10.124324 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 04:42:10.127628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 04:42:10.127712 ==
1595 04:42:10.127778
1596 04:42:10.127839
1597 04:42:10.131354 TX Vref Scan disable
1598 04:42:10.135161 == TX Byte 0 ==
1599 04:42:10.138448 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1600 04:42:10.141886 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1601 04:42:10.145287 == TX Byte 1 ==
1602 04:42:10.148689 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1603 04:42:10.151686 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1604 04:42:10.151773
1605 04:42:10.155082 [DATLAT]
1606 04:42:10.155167 Freq=800, CH1 RK0
1607 04:42:10.155252
1608 04:42:10.158270 DATLAT Default: 0xa
1609 04:42:10.158357 0, 0xFFFF, sum = 0
1610 04:42:10.161690 1, 0xFFFF, sum = 0
1611 04:42:10.161777 2, 0xFFFF, sum = 0
1612 04:42:10.164971 3, 0xFFFF, sum = 0
1613 04:42:10.165059 4, 0xFFFF, sum = 0
1614 04:42:10.168312 5, 0xFFFF, sum = 0
1615 04:42:10.168400 6, 0xFFFF, sum = 0
1616 04:42:10.171706 7, 0xFFFF, sum = 0
1617 04:42:10.171807 8, 0xFFFF, sum = 0
1618 04:42:10.175451 9, 0x0, sum = 1
1619 04:42:10.175562 10, 0x0, sum = 2
1620 04:42:10.178311 11, 0x0, sum = 3
1621 04:42:10.178397 12, 0x0, sum = 4
1622 04:42:10.178464 best_step = 10
1623 04:42:10.181824
1624 04:42:10.181907 ==
1625 04:42:10.185237 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 04:42:10.188730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 04:42:10.188815 ==
1628 04:42:10.188883 RX Vref Scan: 1
1629 04:42:10.188946
1630 04:42:10.192035 Set Vref Range= 32 -> 127
1631 04:42:10.192120
1632 04:42:10.195367 RX Vref 32 -> 127, step: 1
1633 04:42:10.195451
1634 04:42:10.198854 RX Delay -95 -> 252, step: 8
1635 04:42:10.198939
1636 04:42:10.201971 Set Vref, RX VrefLevel [Byte0]: 32
1637 04:42:10.205415 [Byte1]: 32
1638 04:42:10.205499
1639 04:42:10.208459 Set Vref, RX VrefLevel [Byte0]: 33
1640 04:42:10.211909 [Byte1]: 33
1641 04:42:10.211994
1642 04:42:10.215259 Set Vref, RX VrefLevel [Byte0]: 34
1643 04:42:10.218374 [Byte1]: 34
1644 04:42:10.222296
1645 04:42:10.222395 Set Vref, RX VrefLevel [Byte0]: 35
1646 04:42:10.225392 [Byte1]: 35
1647 04:42:10.229410
1648 04:42:10.229487 Set Vref, RX VrefLevel [Byte0]: 36
1649 04:42:10.233106 [Byte1]: 36
1650 04:42:10.237027
1651 04:42:10.237112 Set Vref, RX VrefLevel [Byte0]: 37
1652 04:42:10.240663 [Byte1]: 37
1653 04:42:10.245000
1654 04:42:10.245084 Set Vref, RX VrefLevel [Byte0]: 38
1655 04:42:10.248400 [Byte1]: 38
1656 04:42:10.252446
1657 04:42:10.252547 Set Vref, RX VrefLevel [Byte0]: 39
1658 04:42:10.256053 [Byte1]: 39
1659 04:42:10.260036
1660 04:42:10.260121 Set Vref, RX VrefLevel [Byte0]: 40
1661 04:42:10.263732 [Byte1]: 40
1662 04:42:10.267485
1663 04:42:10.267574 Set Vref, RX VrefLevel [Byte0]: 41
1664 04:42:10.271095 [Byte1]: 41
1665 04:42:10.275420
1666 04:42:10.275505 Set Vref, RX VrefLevel [Byte0]: 42
1667 04:42:10.278508 [Byte1]: 42
1668 04:42:10.282581
1669 04:42:10.282667 Set Vref, RX VrefLevel [Byte0]: 43
1670 04:42:10.286128 [Byte1]: 43
1671 04:42:10.290203
1672 04:42:10.290288 Set Vref, RX VrefLevel [Byte0]: 44
1673 04:42:10.293676 [Byte1]: 44
1674 04:42:10.298493
1675 04:42:10.298577 Set Vref, RX VrefLevel [Byte0]: 45
1676 04:42:10.301530 [Byte1]: 45
1677 04:42:10.305817
1678 04:42:10.305902 Set Vref, RX VrefLevel [Byte0]: 46
1679 04:42:10.308847 [Byte1]: 46
1680 04:42:10.313242
1681 04:42:10.313328 Set Vref, RX VrefLevel [Byte0]: 47
1682 04:42:10.316688 [Byte1]: 47
1683 04:42:10.321055
1684 04:42:10.321140 Set Vref, RX VrefLevel [Byte0]: 48
1685 04:42:10.324050 [Byte1]: 48
1686 04:42:10.328630
1687 04:42:10.328714 Set Vref, RX VrefLevel [Byte0]: 49
1688 04:42:10.331687 [Byte1]: 49
1689 04:42:10.336066
1690 04:42:10.336148 Set Vref, RX VrefLevel [Byte0]: 50
1691 04:42:10.339385 [Byte1]: 50
1692 04:42:10.343851
1693 04:42:10.343945 Set Vref, RX VrefLevel [Byte0]: 51
1694 04:42:10.346859 [Byte1]: 51
1695 04:42:10.351075
1696 04:42:10.351188 Set Vref, RX VrefLevel [Byte0]: 52
1697 04:42:10.354420 [Byte1]: 52
1698 04:42:10.358983
1699 04:42:10.359065 Set Vref, RX VrefLevel [Byte0]: 53
1700 04:42:10.362344 [Byte1]: 53
1701 04:42:10.366391
1702 04:42:10.366473 Set Vref, RX VrefLevel [Byte0]: 54
1703 04:42:10.369787 [Byte1]: 54
1704 04:42:10.373831
1705 04:42:10.373968 Set Vref, RX VrefLevel [Byte0]: 55
1706 04:42:10.377269 [Byte1]: 55
1707 04:42:10.381569
1708 04:42:10.381652 Set Vref, RX VrefLevel [Byte0]: 56
1709 04:42:10.384920 [Byte1]: 56
1710 04:42:10.389467
1711 04:42:10.389550 Set Vref, RX VrefLevel [Byte0]: 57
1712 04:42:10.392382 [Byte1]: 57
1713 04:42:10.396798
1714 04:42:10.396880 Set Vref, RX VrefLevel [Byte0]: 58
1715 04:42:10.399993 [Byte1]: 58
1716 04:42:10.404666
1717 04:42:10.404748 Set Vref, RX VrefLevel [Byte0]: 59
1718 04:42:10.407574 [Byte1]: 59
1719 04:42:10.411888
1720 04:42:10.411972 Set Vref, RX VrefLevel [Byte0]: 60
1721 04:42:10.415698 [Byte1]: 60
1722 04:42:10.419981
1723 04:42:10.420064 Set Vref, RX VrefLevel [Byte0]: 61
1724 04:42:10.422800 [Byte1]: 61
1725 04:42:10.427080
1726 04:42:10.427167 Set Vref, RX VrefLevel [Byte0]: 62
1727 04:42:10.430544 [Byte1]: 62
1728 04:42:10.434587
1729 04:42:10.434675 Set Vref, RX VrefLevel [Byte0]: 63
1730 04:42:10.438271 [Byte1]: 63
1731 04:42:10.442761
1732 04:42:10.442843 Set Vref, RX VrefLevel [Byte0]: 64
1733 04:42:10.445662 [Byte1]: 64
1734 04:42:10.449968
1735 04:42:10.450056 Set Vref, RX VrefLevel [Byte0]: 65
1736 04:42:10.453363 [Byte1]: 65
1737 04:42:10.457511
1738 04:42:10.457594 Set Vref, RX VrefLevel [Byte0]: 66
1739 04:42:10.460739 [Byte1]: 66
1740 04:42:10.465340
1741 04:42:10.465423 Set Vref, RX VrefLevel [Byte0]: 67
1742 04:42:10.468643 [Byte1]: 67
1743 04:42:10.472757
1744 04:42:10.472844 Set Vref, RX VrefLevel [Byte0]: 68
1745 04:42:10.476032 [Byte1]: 68
1746 04:42:10.480270
1747 04:42:10.480354 Set Vref, RX VrefLevel [Byte0]: 69
1748 04:42:10.483710 [Byte1]: 69
1749 04:42:10.487842
1750 04:42:10.487925 Set Vref, RX VrefLevel [Byte0]: 70
1751 04:42:10.491533 [Byte1]: 70
1752 04:42:10.495891
1753 04:42:10.495975 Set Vref, RX VrefLevel [Byte0]: 71
1754 04:42:10.498830 [Byte1]: 71
1755 04:42:10.503191
1756 04:42:10.503277 Set Vref, RX VrefLevel [Byte0]: 72
1757 04:42:10.506448 [Byte1]: 72
1758 04:42:10.511004
1759 04:42:10.511089 Set Vref, RX VrefLevel [Byte0]: 73
1760 04:42:10.514251 [Byte1]: 73
1761 04:42:10.518654
1762 04:42:10.518738 Final RX Vref Byte 0 = 52 to rank0
1763 04:42:10.521817 Final RX Vref Byte 1 = 62 to rank0
1764 04:42:10.524923 Final RX Vref Byte 0 = 52 to rank1
1765 04:42:10.528403 Final RX Vref Byte 1 = 62 to rank1==
1766 04:42:10.531853 Dram Type= 6, Freq= 0, CH_1, rank 0
1767 04:42:10.538592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1768 04:42:10.538679 ==
1769 04:42:10.538746 DQS Delay:
1770 04:42:10.538807 DQS0 = 0, DQS1 = 0
1771 04:42:10.541623 DQM Delay:
1772 04:42:10.541706 DQM0 = 93, DQM1 = 83
1773 04:42:10.545092 DQ Delay:
1774 04:42:10.548512 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1775 04:42:10.551955 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1776 04:42:10.552038 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1777 04:42:10.558632 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1778 04:42:10.558718
1779 04:42:10.558783
1780 04:42:10.565022 [DQSOSCAuto] RK0, (LSB)MR18= 0x3351, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1781 04:42:10.568461 CH1 RK0: MR19=606, MR18=3351
1782 04:42:10.575169 CH1_RK0: MR19=0x606, MR18=0x3351, DQSOSC=389, MR23=63, INC=97, DEC=65
1783 04:42:10.575255
1784 04:42:10.578543 ----->DramcWriteLeveling(PI) begin...
1785 04:42:10.578629 ==
1786 04:42:10.582212 Dram Type= 6, Freq= 0, CH_1, rank 1
1787 04:42:10.585377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 04:42:10.585462 ==
1789 04:42:10.588709 Write leveling (Byte 0): 28 => 28
1790 04:42:10.592152 Write leveling (Byte 1): 30 => 30
1791 04:42:10.595445 DramcWriteLeveling(PI) end<-----
1792 04:42:10.595529
1793 04:42:10.595595 ==
1794 04:42:10.598731 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 04:42:10.601689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 04:42:10.601776 ==
1797 04:42:10.605048 [Gating] SW mode calibration
1798 04:42:10.612073 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1799 04:42:10.618616 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1800 04:42:10.621892 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1801 04:42:10.625291 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1802 04:42:10.631825 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 04:42:10.635258 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 04:42:10.638678 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 04:42:10.645625 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 04:42:10.649020 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 04:42:10.652421 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 04:42:10.655738 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 04:42:10.661889 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 04:42:10.665621 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 04:42:10.669211 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 04:42:10.675303 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 04:42:10.679003 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 04:42:10.682391 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 04:42:10.688972 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 04:42:10.692532 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1817 04:42:10.695333 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1818 04:42:10.701997 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 04:42:10.705539 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 04:42:10.708765 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 04:42:10.715480 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 04:42:10.719290 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 04:42:10.722176 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 04:42:10.728811 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 04:42:10.732415 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1826 04:42:10.735698 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1827 04:42:10.742407 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 04:42:10.745314 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 04:42:10.748787 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 04:42:10.752090 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 04:42:10.758979 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 04:42:10.762318 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 04:42:10.765644 0 10 4 | B1->B0 | 3030 3333 | 1 0 | (1 0) (0 1)
1834 04:42:10.772126 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1835 04:42:10.775409 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 04:42:10.778725 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 04:42:10.785601 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 04:42:10.788762 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 04:42:10.792091 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 04:42:10.799079 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 04:42:10.802507 0 11 4 | B1->B0 | 3232 2d2d | 0 1 | (0 0) (0 0)
1842 04:42:10.805740 0 11 8 | B1->B0 | 4646 3c3c | 0 0 | (0 0) (0 0)
1843 04:42:10.812086 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 04:42:10.815466 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 04:42:10.818742 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 04:42:10.825773 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 04:42:10.829175 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 04:42:10.832328 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1849 04:42:10.835618 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1850 04:42:10.842323 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 04:42:10.845703 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 04:42:10.849047 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 04:42:10.855752 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 04:42:10.859234 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 04:42:10.862548 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 04:42:10.869076 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 04:42:10.872391 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 04:42:10.875897 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 04:42:10.882502 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 04:42:10.885698 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 04:42:10.889049 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 04:42:10.895514 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 04:42:10.899009 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 04:42:10.902339 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1865 04:42:10.909048 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1866 04:42:10.909138 Total UI for P1: 0, mck2ui 16
1867 04:42:10.912526 best dqsien dly found for B1: ( 0, 14, 0)
1868 04:42:10.918847 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 04:42:10.922249 Total UI for P1: 0, mck2ui 16
1870 04:42:10.925829 best dqsien dly found for B0: ( 0, 14, 4)
1871 04:42:10.929157 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1872 04:42:10.932473 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1873 04:42:10.932580
1874 04:42:10.935760 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1875 04:42:10.939078 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1876 04:42:10.942728 [Gating] SW calibration Done
1877 04:42:10.942812 ==
1878 04:42:10.946134 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 04:42:10.949071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 04:42:10.949155 ==
1881 04:42:10.952520 RX Vref Scan: 0
1882 04:42:10.952603
1883 04:42:10.952668 RX Vref 0 -> 0, step: 1
1884 04:42:10.952729
1885 04:42:10.955818 RX Delay -130 -> 252, step: 16
1886 04:42:10.959294 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1887 04:42:10.966132 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1888 04:42:10.969066 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1889 04:42:10.972557 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1890 04:42:10.975864 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1891 04:42:10.979042 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1892 04:42:10.986071 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1893 04:42:10.989399 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1894 04:42:10.992773 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1895 04:42:10.995911 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1896 04:42:10.999564 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1897 04:42:11.006400 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1898 04:42:11.009293 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1899 04:42:11.012545 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1900 04:42:11.016104 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1901 04:42:11.019547 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1902 04:42:11.022976 ==
1903 04:42:11.023060 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 04:42:11.029406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1905 04:42:11.029557 ==
1906 04:42:11.029667 DQS Delay:
1907 04:42:11.032635 DQS0 = 0, DQS1 = 0
1908 04:42:11.032719 DQM Delay:
1909 04:42:11.036012 DQM0 = 90, DQM1 = 83
1910 04:42:11.036095 DQ Delay:
1911 04:42:11.039389 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1912 04:42:11.042753 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1913 04:42:11.045931 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1914 04:42:11.049576 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1915 04:42:11.049660
1916 04:42:11.049726
1917 04:42:11.049786 ==
1918 04:42:11.052900 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 04:42:11.056058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 04:42:11.056142 ==
1921 04:42:11.056209
1922 04:42:11.056269
1923 04:42:11.059682 TX Vref Scan disable
1924 04:42:11.062918 == TX Byte 0 ==
1925 04:42:11.065930 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1926 04:42:11.069250 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1927 04:42:11.072608 == TX Byte 1 ==
1928 04:42:11.076169 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1929 04:42:11.079490 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1930 04:42:11.079575 ==
1931 04:42:11.082777 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 04:42:11.086211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 04:42:11.086294 ==
1934 04:42:11.100363 TX Vref=22, minBit 10, minWin=27, winSum=450
1935 04:42:11.103778 TX Vref=24, minBit 13, minWin=27, winSum=457
1936 04:42:11.107458 TX Vref=26, minBit 1, minWin=28, winSum=455
1937 04:42:11.110497 TX Vref=28, minBit 8, minWin=28, winSum=459
1938 04:42:11.113852 TX Vref=30, minBit 8, minWin=28, winSum=462
1939 04:42:11.120683 TX Vref=32, minBit 1, minWin=28, winSum=458
1940 04:42:11.123596 [TxChooseVref] Worse bit 8, Min win 28, Win sum 462, Final Vref 30
1941 04:42:11.123682
1942 04:42:11.127017 Final TX Range 1 Vref 30
1943 04:42:11.127101
1944 04:42:11.127166 ==
1945 04:42:11.130447 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 04:42:11.133860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 04:42:11.133968 ==
1948 04:42:11.134049
1949 04:42:11.137262
1950 04:42:11.137357 TX Vref Scan disable
1951 04:42:11.140526 == TX Byte 0 ==
1952 04:42:11.143685 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1953 04:42:11.147022 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1954 04:42:11.150471 == TX Byte 1 ==
1955 04:42:11.153748 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1956 04:42:11.157194 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1957 04:42:11.160428
1958 04:42:11.160510 [DATLAT]
1959 04:42:11.160575 Freq=800, CH1 RK1
1960 04:42:11.160634
1961 04:42:11.163934 DATLAT Default: 0xa
1962 04:42:11.164015 0, 0xFFFF, sum = 0
1963 04:42:11.167362 1, 0xFFFF, sum = 0
1964 04:42:11.167446 2, 0xFFFF, sum = 0
1965 04:42:11.170834 3, 0xFFFF, sum = 0
1966 04:42:11.170917 4, 0xFFFF, sum = 0
1967 04:42:11.174295 5, 0xFFFF, sum = 0
1968 04:42:11.174378 6, 0xFFFF, sum = 0
1969 04:42:11.177205 7, 0xFFFF, sum = 0
1970 04:42:11.177287 8, 0xFFFF, sum = 0
1971 04:42:11.180971 9, 0x0, sum = 1
1972 04:42:11.181054 10, 0x0, sum = 2
1973 04:42:11.183870 11, 0x0, sum = 3
1974 04:42:11.183953 12, 0x0, sum = 4
1975 04:42:11.187440 best_step = 10
1976 04:42:11.187522
1977 04:42:11.187587 ==
1978 04:42:11.190820 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 04:42:11.194177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 04:42:11.194260 ==
1981 04:42:11.197532 RX Vref Scan: 0
1982 04:42:11.197614
1983 04:42:11.197680 RX Vref 0 -> 0, step: 1
1984 04:42:11.197740
1985 04:42:11.200744 RX Delay -95 -> 252, step: 8
1986 04:42:11.207562 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
1987 04:42:11.210805 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
1988 04:42:11.214154 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
1989 04:42:11.217462 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1990 04:42:11.220826 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
1991 04:42:11.224067 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1992 04:42:11.230984 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1993 04:42:11.234339 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
1994 04:42:11.237387 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1995 04:42:11.240792 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1996 04:42:11.244431 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
1997 04:42:11.251029 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
1998 04:42:11.254334 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1999 04:42:11.257665 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2000 04:42:11.261087 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2001 04:42:11.264357 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2002 04:42:11.267791 ==
2003 04:42:11.267875 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 04:42:11.274140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 04:42:11.274227 ==
2006 04:42:11.274294 DQS Delay:
2007 04:42:11.277597 DQS0 = 0, DQS1 = 0
2008 04:42:11.277690 DQM Delay:
2009 04:42:11.281091 DQM0 = 92, DQM1 = 85
2010 04:42:11.281178 DQ Delay:
2011 04:42:11.284465 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2012 04:42:11.287784 DQ4 =96, DQ5 =108, DQ6 =96, DQ7 =88
2013 04:42:11.290987 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2014 04:42:11.294217 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =96
2015 04:42:11.294302
2016 04:42:11.294369
2017 04:42:11.301175 [DQSOSCAuto] RK1, (LSB)MR18= 0x380d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2018 04:42:11.304556 CH1 RK1: MR19=606, MR18=380D
2019 04:42:11.310916 CH1_RK1: MR19=0x606, MR18=0x380D, DQSOSC=395, MR23=63, INC=94, DEC=63
2020 04:42:11.314372 [RxdqsGatingPostProcess] freq 800
2021 04:42:11.317493 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2022 04:42:11.321447 Pre-setting of DQS Precalculation
2023 04:42:11.327592 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2024 04:42:11.334484 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2025 04:42:11.341139 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2026 04:42:11.341224
2027 04:42:11.341290
2028 04:42:11.344422 [Calibration Summary] 1600 Mbps
2029 04:42:11.344520 CH 0, Rank 0
2030 04:42:11.347666 SW Impedance : PASS
2031 04:42:11.351018 DUTY Scan : NO K
2032 04:42:11.351102 ZQ Calibration : PASS
2033 04:42:11.354139 Jitter Meter : NO K
2034 04:42:11.357432 CBT Training : PASS
2035 04:42:11.357515 Write leveling : PASS
2036 04:42:11.360846 RX DQS gating : PASS
2037 04:42:11.364297 RX DQ/DQS(RDDQC) : PASS
2038 04:42:11.364381 TX DQ/DQS : PASS
2039 04:42:11.367616 RX DATLAT : PASS
2040 04:42:11.371140 RX DQ/DQS(Engine): PASS
2041 04:42:11.371224 TX OE : NO K
2042 04:42:11.371292 All Pass.
2043 04:42:11.374604
2044 04:42:11.374688 CH 0, Rank 1
2045 04:42:11.377597 SW Impedance : PASS
2046 04:42:11.377680 DUTY Scan : NO K
2047 04:42:11.381244 ZQ Calibration : PASS
2048 04:42:11.381328 Jitter Meter : NO K
2049 04:42:11.384655 CBT Training : PASS
2050 04:42:11.387778 Write leveling : PASS
2051 04:42:11.387861 RX DQS gating : PASS
2052 04:42:11.391162 RX DQ/DQS(RDDQC) : PASS
2053 04:42:11.394373 TX DQ/DQS : PASS
2054 04:42:11.394457 RX DATLAT : PASS
2055 04:42:11.397571 RX DQ/DQS(Engine): PASS
2056 04:42:11.401262 TX OE : NO K
2057 04:42:11.401347 All Pass.
2058 04:42:11.401414
2059 04:42:11.401476 CH 1, Rank 0
2060 04:42:11.404715 SW Impedance : PASS
2061 04:42:11.407847 DUTY Scan : NO K
2062 04:42:11.407930 ZQ Calibration : PASS
2063 04:42:11.411343 Jitter Meter : NO K
2064 04:42:11.414908 CBT Training : PASS
2065 04:42:11.414991 Write leveling : PASS
2066 04:42:11.417717 RX DQS gating : PASS
2067 04:42:11.417800 RX DQ/DQS(RDDQC) : PASS
2068 04:42:11.421437 TX DQ/DQS : PASS
2069 04:42:11.425026 RX DATLAT : PASS
2070 04:42:11.425109 RX DQ/DQS(Engine): PASS
2071 04:42:11.427933 TX OE : NO K
2072 04:42:11.428017 All Pass.
2073 04:42:11.428083
2074 04:42:11.431189 CH 1, Rank 1
2075 04:42:11.431272 SW Impedance : PASS
2076 04:42:11.434692 DUTY Scan : NO K
2077 04:42:11.438101 ZQ Calibration : PASS
2078 04:42:11.438210 Jitter Meter : NO K
2079 04:42:11.441068 CBT Training : PASS
2080 04:42:11.444556 Write leveling : PASS
2081 04:42:11.444639 RX DQS gating : PASS
2082 04:42:11.448206 RX DQ/DQS(RDDQC) : PASS
2083 04:42:11.451471 TX DQ/DQS : PASS
2084 04:42:11.451554 RX DATLAT : PASS
2085 04:42:11.454823 RX DQ/DQS(Engine): PASS
2086 04:42:11.454906 TX OE : NO K
2087 04:42:11.458052 All Pass.
2088 04:42:11.458135
2089 04:42:11.458202 DramC Write-DBI off
2090 04:42:11.461520 PER_BANK_REFRESH: Hybrid Mode
2091 04:42:11.464789 TX_TRACKING: ON
2092 04:42:11.468096 [GetDramInforAfterCalByMRR] Vendor 6.
2093 04:42:11.471500 [GetDramInforAfterCalByMRR] Revision 606.
2094 04:42:11.474830 [GetDramInforAfterCalByMRR] Revision 2 0.
2095 04:42:11.474913 MR0 0x3b3b
2096 04:42:11.474979 MR8 0x5151
2097 04:42:11.481225 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 04:42:11.481309
2099 04:42:11.481374 MR0 0x3b3b
2100 04:42:11.481434 MR8 0x5151
2101 04:42:11.484667 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2102 04:42:11.484750
2103 04:42:11.494837 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2104 04:42:11.497919 [FAST_K] Save calibration result to emmc
2105 04:42:11.501244 [FAST_K] Save calibration result to emmc
2106 04:42:11.504843 dram_init: config_dvfs: 1
2107 04:42:11.508170 dramc_set_vcore_voltage set vcore to 662500
2108 04:42:11.511616 Read voltage for 1200, 2
2109 04:42:11.511702 Vio18 = 0
2110 04:42:11.511768 Vcore = 662500
2111 04:42:11.514776 Vdram = 0
2112 04:42:11.514859 Vddq = 0
2113 04:42:11.514924 Vmddr = 0
2114 04:42:11.521373 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2115 04:42:11.524721 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2116 04:42:11.528417 MEM_TYPE=3, freq_sel=15
2117 04:42:11.531843 sv_algorithm_assistance_LP4_1600
2118 04:42:11.535030 ============ PULL DRAM RESETB DOWN ============
2119 04:42:11.538392 ========== PULL DRAM RESETB DOWN end =========
2120 04:42:11.545145 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2121 04:42:11.548163 ===================================
2122 04:42:11.548248 LPDDR4 DRAM CONFIGURATION
2123 04:42:11.551856 ===================================
2124 04:42:11.555015 EX_ROW_EN[0] = 0x0
2125 04:42:11.558371 EX_ROW_EN[1] = 0x0
2126 04:42:11.558455 LP4Y_EN = 0x0
2127 04:42:11.561627 WORK_FSP = 0x0
2128 04:42:11.561723 WL = 0x4
2129 04:42:11.564807 RL = 0x4
2130 04:42:11.564890 BL = 0x2
2131 04:42:11.568165 RPST = 0x0
2132 04:42:11.568249 RD_PRE = 0x0
2133 04:42:11.571722 WR_PRE = 0x1
2134 04:42:11.571806 WR_PST = 0x0
2135 04:42:11.574924 DBI_WR = 0x0
2136 04:42:11.575008 DBI_RD = 0x0
2137 04:42:11.578355 OTF = 0x1
2138 04:42:11.581782 ===================================
2139 04:42:11.585228 ===================================
2140 04:42:11.585312 ANA top config
2141 04:42:11.588501 ===================================
2142 04:42:11.591834 DLL_ASYNC_EN = 0
2143 04:42:11.595321 ALL_SLAVE_EN = 0
2144 04:42:11.595404 NEW_RANK_MODE = 1
2145 04:42:11.598701 DLL_IDLE_MODE = 1
2146 04:42:11.601837 LP45_APHY_COMB_EN = 1
2147 04:42:11.605145 TX_ODT_DIS = 1
2148 04:42:11.608524 NEW_8X_MODE = 1
2149 04:42:11.611886 ===================================
2150 04:42:11.611970 ===================================
2151 04:42:11.615190 data_rate = 2400
2152 04:42:11.618371 CKR = 1
2153 04:42:11.621891 DQ_P2S_RATIO = 8
2154 04:42:11.625256 ===================================
2155 04:42:11.628568 CA_P2S_RATIO = 8
2156 04:42:11.631803 DQ_CA_OPEN = 0
2157 04:42:11.631932 DQ_SEMI_OPEN = 0
2158 04:42:11.635227 CA_SEMI_OPEN = 0
2159 04:42:11.638554 CA_FULL_RATE = 0
2160 04:42:11.642340 DQ_CKDIV4_EN = 0
2161 04:42:11.645651 CA_CKDIV4_EN = 0
2162 04:42:11.649123 CA_PREDIV_EN = 0
2163 04:42:11.649206 PH8_DLY = 17
2164 04:42:11.652078 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2165 04:42:11.655339 DQ_AAMCK_DIV = 4
2166 04:42:11.659097 CA_AAMCK_DIV = 4
2167 04:42:11.662449 CA_ADMCK_DIV = 4
2168 04:42:11.665723 DQ_TRACK_CA_EN = 0
2169 04:42:11.665836 CA_PICK = 1200
2170 04:42:11.668988 CA_MCKIO = 1200
2171 04:42:11.672181 MCKIO_SEMI = 0
2172 04:42:11.675564 PLL_FREQ = 2366
2173 04:42:11.679112 DQ_UI_PI_RATIO = 32
2174 04:42:11.682464 CA_UI_PI_RATIO = 0
2175 04:42:11.685885 ===================================
2176 04:42:11.689176 ===================================
2177 04:42:11.689259 memory_type:LPDDR4
2178 04:42:11.692668 GP_NUM : 10
2179 04:42:11.695682 SRAM_EN : 1
2180 04:42:11.695763 MD32_EN : 0
2181 04:42:11.699154 ===================================
2182 04:42:11.702546 [ANA_INIT] >>>>>>>>>>>>>>
2183 04:42:11.705830 <<<<<< [CONFIGURE PHASE]: ANA_TX
2184 04:42:11.709088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2185 04:42:11.712678 ===================================
2186 04:42:11.715624 data_rate = 2400,PCW = 0X5b00
2187 04:42:11.718979 ===================================
2188 04:42:11.722212 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2189 04:42:11.725551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2190 04:42:11.732448 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2191 04:42:11.735678 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2192 04:42:11.739076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2193 04:42:11.742309 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2194 04:42:11.745672 [ANA_INIT] flow start
2195 04:42:11.749151 [ANA_INIT] PLL >>>>>>>>
2196 04:42:11.749236 [ANA_INIT] PLL <<<<<<<<
2197 04:42:11.752600 [ANA_INIT] MIDPI >>>>>>>>
2198 04:42:11.755524 [ANA_INIT] MIDPI <<<<<<<<
2199 04:42:11.755607 [ANA_INIT] DLL >>>>>>>>
2200 04:42:11.758989 [ANA_INIT] DLL <<<<<<<<
2201 04:42:11.762581 [ANA_INIT] flow end
2202 04:42:11.765932 ============ LP4 DIFF to SE enter ============
2203 04:42:11.768945 ============ LP4 DIFF to SE exit ============
2204 04:42:11.772170 [ANA_INIT] <<<<<<<<<<<<<
2205 04:42:11.775753 [Flow] Enable top DCM control >>>>>
2206 04:42:11.779198 [Flow] Enable top DCM control <<<<<
2207 04:42:11.782205 Enable DLL master slave shuffle
2208 04:42:11.785666 ==============================================================
2209 04:42:11.789117 Gating Mode config
2210 04:42:11.795744 ==============================================================
2211 04:42:11.795833 Config description:
2212 04:42:11.806105 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2213 04:42:11.812738 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2214 04:42:11.815946 SELPH_MODE 0: By rank 1: By Phase
2215 04:42:11.822558 ==============================================================
2216 04:42:11.825985 GAT_TRACK_EN = 1
2217 04:42:11.829403 RX_GATING_MODE = 2
2218 04:42:11.832490 RX_GATING_TRACK_MODE = 2
2219 04:42:11.836139 SELPH_MODE = 1
2220 04:42:11.839378 PICG_EARLY_EN = 1
2221 04:42:11.842670 VALID_LAT_VALUE = 1
2222 04:42:11.845935 ==============================================================
2223 04:42:11.849304 Enter into Gating configuration >>>>
2224 04:42:11.852735 Exit from Gating configuration <<<<
2225 04:42:11.856293 Enter into DVFS_PRE_config >>>>>
2226 04:42:11.866096 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2227 04:42:11.869289 Exit from DVFS_PRE_config <<<<<
2228 04:42:11.872677 Enter into PICG configuration >>>>
2229 04:42:11.875796 Exit from PICG configuration <<<<
2230 04:42:11.879001 [RX_INPUT] configuration >>>>>
2231 04:42:11.882674 [RX_INPUT] configuration <<<<<
2232 04:42:11.889021 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2233 04:42:11.892361 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2234 04:42:11.898881 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2235 04:42:11.905688 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2236 04:42:11.912556 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 04:42:11.918954 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 04:42:11.922538 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2239 04:42:11.925827 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2240 04:42:11.929064 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2241 04:42:11.932316 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2242 04:42:11.939052 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2243 04:42:11.942346 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2244 04:42:11.945653 ===================================
2245 04:42:11.949029 LPDDR4 DRAM CONFIGURATION
2246 04:42:11.952196 ===================================
2247 04:42:11.952284 EX_ROW_EN[0] = 0x0
2248 04:42:11.955620 EX_ROW_EN[1] = 0x0
2249 04:42:11.955705 LP4Y_EN = 0x0
2250 04:42:11.959003 WORK_FSP = 0x0
2251 04:42:11.959087 WL = 0x4
2252 04:42:11.962348 RL = 0x4
2253 04:42:11.962431 BL = 0x2
2254 04:42:11.965792 RPST = 0x0
2255 04:42:11.965875 RD_PRE = 0x0
2256 04:42:11.969126 WR_PRE = 0x1
2257 04:42:11.972318 WR_PST = 0x0
2258 04:42:11.972403 DBI_WR = 0x0
2259 04:42:11.975568 DBI_RD = 0x0
2260 04:42:11.975651 OTF = 0x1
2261 04:42:11.978904 ===================================
2262 04:42:11.982307 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2263 04:42:11.985433 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2264 04:42:11.992442 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 04:42:11.995812 ===================================
2266 04:42:11.999154 LPDDR4 DRAM CONFIGURATION
2267 04:42:12.002565 ===================================
2268 04:42:12.002667 EX_ROW_EN[0] = 0x10
2269 04:42:12.005574 EX_ROW_EN[1] = 0x0
2270 04:42:12.005659 LP4Y_EN = 0x0
2271 04:42:12.008963 WORK_FSP = 0x0
2272 04:42:12.009047 WL = 0x4
2273 04:42:12.012419 RL = 0x4
2274 04:42:12.012502 BL = 0x2
2275 04:42:12.015784 RPST = 0x0
2276 04:42:12.015892 RD_PRE = 0x0
2277 04:42:12.019094 WR_PRE = 0x1
2278 04:42:12.019177 WR_PST = 0x0
2279 04:42:12.022334 DBI_WR = 0x0
2280 04:42:12.022418 DBI_RD = 0x0
2281 04:42:12.025779 OTF = 0x1
2282 04:42:12.029145 ===================================
2283 04:42:12.035662 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2284 04:42:12.035748 ==
2285 04:42:12.039524 Dram Type= 6, Freq= 0, CH_0, rank 0
2286 04:42:12.042625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2287 04:42:12.042711 ==
2288 04:42:12.045583 [Duty_Offset_Calibration]
2289 04:42:12.045668 B0:2 B1:0 CA:1
2290 04:42:12.045734
2291 04:42:12.049391 [DutyScan_Calibration_Flow] k_type=0
2292 04:42:12.058946
2293 04:42:12.059055 ==CLK 0==
2294 04:42:12.062342 Final CLK duty delay cell = -4
2295 04:42:12.065302 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2296 04:42:12.068652 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2297 04:42:12.071866 [-4] AVG Duty = 4953%(X100)
2298 04:42:12.071951
2299 04:42:12.075487 CH0 CLK Duty spec in!! Max-Min= 156%
2300 04:42:12.078766 [DutyScan_Calibration_Flow] ====Done====
2301 04:42:12.078849
2302 04:42:12.082029 [DutyScan_Calibration_Flow] k_type=1
2303 04:42:12.097620
2304 04:42:12.097732 ==DQS 0 ==
2305 04:42:12.100994 Final DQS duty delay cell = 0
2306 04:42:12.104381 [0] MAX Duty = 5187%(X100), DQS PI = 30
2307 04:42:12.107624 [0] MIN Duty = 4938%(X100), DQS PI = 0
2308 04:42:12.107708 [0] AVG Duty = 5062%(X100)
2309 04:42:12.107774
2310 04:42:12.111057 ==DQS 1 ==
2311 04:42:12.114446 Final DQS duty delay cell = -4
2312 04:42:12.117808 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2313 04:42:12.121084 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2314 04:42:12.121218 [-4] AVG Duty = 5031%(X100)
2315 04:42:12.124340
2316 04:42:12.127736 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2317 04:42:12.127825
2318 04:42:12.131021 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2319 04:42:12.134266 [DutyScan_Calibration_Flow] ====Done====
2320 04:42:12.134352
2321 04:42:12.137740 [DutyScan_Calibration_Flow] k_type=3
2322 04:42:12.154687
2323 04:42:12.154810 ==DQM 0 ==
2324 04:42:12.157648 Final DQM duty delay cell = 0
2325 04:42:12.160834 [0] MAX Duty = 5062%(X100), DQS PI = 24
2326 04:42:12.164303 [0] MIN Duty = 4813%(X100), DQS PI = 2
2327 04:42:12.164387 [0] AVG Duty = 4937%(X100)
2328 04:42:12.167641
2329 04:42:12.167719 ==DQM 1 ==
2330 04:42:12.171049 Final DQM duty delay cell = 0
2331 04:42:12.174465 [0] MAX Duty = 5187%(X100), DQS PI = 46
2332 04:42:12.177818 [0] MIN Duty = 5000%(X100), DQS PI = 22
2333 04:42:12.177922 [0] AVG Duty = 5093%(X100)
2334 04:42:12.181084
2335 04:42:12.184517 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2336 04:42:12.184605
2337 04:42:12.187767 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2338 04:42:12.191048 [DutyScan_Calibration_Flow] ====Done====
2339 04:42:12.191124
2340 04:42:12.194298 [DutyScan_Calibration_Flow] k_type=2
2341 04:42:12.210289
2342 04:42:12.210395 ==DQ 0 ==
2343 04:42:12.213222 Final DQ duty delay cell = -4
2344 04:42:12.216667 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2345 04:42:12.220093 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2346 04:42:12.223543 [-4] AVG Duty = 4968%(X100)
2347 04:42:12.223618
2348 04:42:12.223681 ==DQ 1 ==
2349 04:42:12.226936 Final DQ duty delay cell = 0
2350 04:42:12.230263 [0] MAX Duty = 4969%(X100), DQS PI = 8
2351 04:42:12.233365 [0] MIN Duty = 4907%(X100), DQS PI = 0
2352 04:42:12.233464 [0] AVG Duty = 4938%(X100)
2353 04:42:12.233554
2354 04:42:12.237082 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2355 04:42:12.240097
2356 04:42:12.243636 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2357 04:42:12.246714 [DutyScan_Calibration_Flow] ====Done====
2358 04:42:12.246794 ==
2359 04:42:12.250027 Dram Type= 6, Freq= 0, CH_1, rank 0
2360 04:42:12.253759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2361 04:42:12.253859 ==
2362 04:42:12.257045 [Duty_Offset_Calibration]
2363 04:42:12.257141 B0:0 B1:-1 CA:2
2364 04:42:12.257233
2365 04:42:12.260016 [DutyScan_Calibration_Flow] k_type=0
2366 04:42:12.269958
2367 04:42:12.270063 ==CLK 0==
2368 04:42:12.273442 Final CLK duty delay cell = 0
2369 04:42:12.276827 [0] MAX Duty = 5156%(X100), DQS PI = 16
2370 04:42:12.280171 [0] MIN Duty = 4938%(X100), DQS PI = 44
2371 04:42:12.280273 [0] AVG Duty = 5047%(X100)
2372 04:42:12.283524
2373 04:42:12.287126 CH1 CLK Duty spec in!! Max-Min= 218%
2374 04:42:12.290097 [DutyScan_Calibration_Flow] ====Done====
2375 04:42:12.290175
2376 04:42:12.293385 [DutyScan_Calibration_Flow] k_type=1
2377 04:42:12.309545
2378 04:42:12.309683 ==DQS 0 ==
2379 04:42:12.312968 Final DQS duty delay cell = 0
2380 04:42:12.316456 [0] MAX Duty = 5093%(X100), DQS PI = 24
2381 04:42:12.319880 [0] MIN Duty = 4969%(X100), DQS PI = 0
2382 04:42:12.319979 [0] AVG Duty = 5031%(X100)
2383 04:42:12.322857
2384 04:42:12.322934 ==DQS 1 ==
2385 04:42:12.326215 Final DQS duty delay cell = 0
2386 04:42:12.329631 [0] MAX Duty = 5156%(X100), DQS PI = 0
2387 04:42:12.333290 [0] MIN Duty = 4844%(X100), DQS PI = 36
2388 04:42:12.333377 [0] AVG Duty = 5000%(X100)
2389 04:42:12.336602
2390 04:42:12.339600 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2391 04:42:12.339680
2392 04:42:12.342976 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2393 04:42:12.346427 [DutyScan_Calibration_Flow] ====Done====
2394 04:42:12.346508
2395 04:42:12.349767 [DutyScan_Calibration_Flow] k_type=3
2396 04:42:12.366265
2397 04:42:12.366363 ==DQM 0 ==
2398 04:42:12.369472 Final DQM duty delay cell = 4
2399 04:42:12.372886 [4] MAX Duty = 5093%(X100), DQS PI = 20
2400 04:42:12.376354 [4] MIN Duty = 4969%(X100), DQS PI = 28
2401 04:42:12.379246 [4] AVG Duty = 5031%(X100)
2402 04:42:12.379331
2403 04:42:12.379417 ==DQM 1 ==
2404 04:42:12.382526 Final DQM duty delay cell = -4
2405 04:42:12.386304 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2406 04:42:12.389296 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2407 04:42:12.392814 [-4] AVG Duty = 4875%(X100)
2408 04:42:12.392892
2409 04:42:12.395980 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2410 04:42:12.396055
2411 04:42:12.399753 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2412 04:42:12.403013 [DutyScan_Calibration_Flow] ====Done====
2413 04:42:12.403119
2414 04:42:12.405973 [DutyScan_Calibration_Flow] k_type=2
2415 04:42:12.423241
2416 04:42:12.423386 ==DQ 0 ==
2417 04:42:12.426245 Final DQ duty delay cell = 0
2418 04:42:12.429504 [0] MAX Duty = 5062%(X100), DQS PI = 20
2419 04:42:12.432956 [0] MIN Duty = 4938%(X100), DQS PI = 0
2420 04:42:12.433067 [0] AVG Duty = 5000%(X100)
2421 04:42:12.433168
2422 04:42:12.436179 ==DQ 1 ==
2423 04:42:12.439704 Final DQ duty delay cell = 0
2424 04:42:12.443157 [0] MAX Duty = 5031%(X100), DQS PI = 2
2425 04:42:12.446592 [0] MIN Duty = 4813%(X100), DQS PI = 34
2426 04:42:12.446672 [0] AVG Duty = 4922%(X100)
2427 04:42:12.446756
2428 04:42:12.449926 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2429 04:42:12.450045
2430 04:42:12.453311 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2431 04:42:12.456456 [DutyScan_Calibration_Flow] ====Done====
2432 04:42:12.461918 nWR fixed to 30
2433 04:42:12.465227 [ModeRegInit_LP4] CH0 RK0
2434 04:42:12.465312 [ModeRegInit_LP4] CH0 RK1
2435 04:42:12.468899 [ModeRegInit_LP4] CH1 RK0
2436 04:42:12.471685 [ModeRegInit_LP4] CH1 RK1
2437 04:42:12.471769 match AC timing 7
2438 04:42:12.478476 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2439 04:42:12.481947 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2440 04:42:12.485408 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2441 04:42:12.492016 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2442 04:42:12.495319 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2443 04:42:12.495411 ==
2444 04:42:12.498529 Dram Type= 6, Freq= 0, CH_0, rank 0
2445 04:42:12.502013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2446 04:42:12.502098 ==
2447 04:42:12.508951 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2448 04:42:12.515379 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2449 04:42:12.522653 [CA 0] Center 38 (7~69) winsize 63
2450 04:42:12.526066 [CA 1] Center 38 (8~69) winsize 62
2451 04:42:12.529104 [CA 2] Center 35 (5~66) winsize 62
2452 04:42:12.532449 [CA 3] Center 35 (4~66) winsize 63
2453 04:42:12.535996 [CA 4] Center 34 (4~65) winsize 62
2454 04:42:12.539290 [CA 5] Center 33 (3~63) winsize 61
2455 04:42:12.539376
2456 04:42:12.542688 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2457 04:42:12.542790
2458 04:42:12.546113 [CATrainingPosCal] consider 1 rank data
2459 04:42:12.549047 u2DelayCellTimex100 = 270/100 ps
2460 04:42:12.552416 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2461 04:42:12.559192 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2462 04:42:12.562479 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2463 04:42:12.565976 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2464 04:42:12.569241 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2465 04:42:12.572848 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2466 04:42:12.572938
2467 04:42:12.575931 CA PerBit enable=1, Macro0, CA PI delay=33
2468 04:42:12.576017
2469 04:42:12.579394 [CBTSetCACLKResult] CA Dly = 33
2470 04:42:12.579480 CS Dly: 6 (0~37)
2471 04:42:12.582750 ==
2472 04:42:12.582836 Dram Type= 6, Freq= 0, CH_0, rank 1
2473 04:42:12.589209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2474 04:42:12.589299 ==
2475 04:42:12.592566 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2476 04:42:12.599233 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2477 04:42:12.608363 [CA 0] Center 39 (8~70) winsize 63
2478 04:42:12.611857 [CA 1] Center 38 (8~69) winsize 62
2479 04:42:12.615215 [CA 2] Center 35 (5~66) winsize 62
2480 04:42:12.618641 [CA 3] Center 35 (5~66) winsize 62
2481 04:42:12.621557 [CA 4] Center 34 (4~65) winsize 62
2482 04:42:12.625100 [CA 5] Center 34 (4~64) winsize 61
2483 04:42:12.625187
2484 04:42:12.628306 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2485 04:42:12.628391
2486 04:42:12.631702 [CATrainingPosCal] consider 2 rank data
2487 04:42:12.635125 u2DelayCellTimex100 = 270/100 ps
2488 04:42:12.638550 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2489 04:42:12.641887 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2490 04:42:12.648942 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2491 04:42:12.651950 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2492 04:42:12.655390 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2493 04:42:12.658755 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2494 04:42:12.658843
2495 04:42:12.662106 CA PerBit enable=1, Macro0, CA PI delay=33
2496 04:42:12.662190
2497 04:42:12.665615 [CBTSetCACLKResult] CA Dly = 33
2498 04:42:12.665701 CS Dly: 7 (0~39)
2499 04:42:12.665766
2500 04:42:12.668457 ----->DramcWriteLeveling(PI) begin...
2501 04:42:12.668542 ==
2502 04:42:12.672010 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 04:42:12.678839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2504 04:42:12.678935 ==
2505 04:42:12.681794 Write leveling (Byte 0): 33 => 33
2506 04:42:12.685150 Write leveling (Byte 1): 30 => 30
2507 04:42:12.685241 DramcWriteLeveling(PI) end<-----
2508 04:42:12.688603
2509 04:42:12.688687 ==
2510 04:42:12.692007 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 04:42:12.695672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 04:42:12.695760 ==
2513 04:42:12.698805 [Gating] SW mode calibration
2514 04:42:12.705317 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2515 04:42:12.708675 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2516 04:42:12.715584 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2517 04:42:12.718894 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2518 04:42:12.722452 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 04:42:12.728805 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 04:42:12.732140 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 04:42:12.735585 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 04:42:12.742092 0 15 24 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
2523 04:42:12.745463 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2524 04:42:12.748725 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2525 04:42:12.752333 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 04:42:12.758986 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 04:42:12.762229 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 04:42:12.765637 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 04:42:12.772514 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 04:42:12.775470 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2531 04:42:12.779002 1 0 28 | B1->B0 | 2424 4646 | 1 0 | (0 0) (0 0)
2532 04:42:12.785518 1 1 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
2533 04:42:12.789000 1 1 4 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
2534 04:42:12.792267 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 04:42:12.798947 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 04:42:12.802347 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 04:42:12.805894 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 04:42:12.812471 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 04:42:12.815733 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2540 04:42:12.818952 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2541 04:42:12.826022 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 04:42:12.829449 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 04:42:12.832431 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 04:42:12.835865 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 04:42:12.842603 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 04:42:12.846083 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 04:42:12.849042 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 04:42:12.856089 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 04:42:12.859347 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 04:42:12.862811 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 04:42:12.869120 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 04:42:12.872492 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 04:42:12.876013 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 04:42:12.882680 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2555 04:42:12.886204 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2556 04:42:12.889122 Total UI for P1: 0, mck2ui 16
2557 04:42:12.892713 best dqsien dly found for B0: ( 1, 3, 24)
2558 04:42:12.895718 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2559 04:42:12.902339 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 04:42:12.902425 Total UI for P1: 0, mck2ui 16
2561 04:42:12.905778 best dqsien dly found for B1: ( 1, 3, 30)
2562 04:42:12.909311 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2563 04:42:12.916062 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2564 04:42:12.916152
2565 04:42:12.919659 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2566 04:42:12.922799 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2567 04:42:12.925931 [Gating] SW calibration Done
2568 04:42:12.926054 ==
2569 04:42:12.929509 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 04:42:12.932890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 04:42:12.932975 ==
2572 04:42:12.933042 RX Vref Scan: 0
2573 04:42:12.935816
2574 04:42:12.935898 RX Vref 0 -> 0, step: 1
2575 04:42:12.935964
2576 04:42:12.939681 RX Delay -40 -> 252, step: 8
2577 04:42:12.942702 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2578 04:42:12.946086 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2579 04:42:12.952947 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2580 04:42:12.956236 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2581 04:42:12.959159 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2582 04:42:12.962681 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2583 04:42:12.965922 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2584 04:42:12.972556 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2585 04:42:12.976254 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2586 04:42:12.979164 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2587 04:42:12.982896 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2588 04:42:12.986275 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2589 04:42:12.992485 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2590 04:42:12.996033 iDelay=208, Bit 13, Center 111 (48 ~ 175) 128
2591 04:42:12.999129 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2592 04:42:13.002776 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2593 04:42:13.002862 ==
2594 04:42:13.006016 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 04:42:13.009590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 04:42:13.012739 ==
2597 04:42:13.012827 DQS Delay:
2598 04:42:13.012893 DQS0 = 0, DQS1 = 0
2599 04:42:13.016376 DQM Delay:
2600 04:42:13.016461 DQM0 = 123, DQM1 = 109
2601 04:42:13.019307 DQ Delay:
2602 04:42:13.022751 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2603 04:42:13.026001 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2604 04:42:13.029292 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2605 04:42:13.033022 DQ12 =115, DQ13 =111, DQ14 =123, DQ15 =115
2606 04:42:13.033106
2607 04:42:13.033173
2608 04:42:13.033234 ==
2609 04:42:13.036063 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 04:42:13.039517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 04:42:13.039602 ==
2612 04:42:13.039669
2613 04:42:13.039730
2614 04:42:13.042972 TX Vref Scan disable
2615 04:42:13.046356 == TX Byte 0 ==
2616 04:42:13.049695 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2617 04:42:13.053022 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2618 04:42:13.056412 == TX Byte 1 ==
2619 04:42:13.059756 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2620 04:42:13.062885 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2621 04:42:13.062969 ==
2622 04:42:13.066600 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 04:42:13.069464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 04:42:13.073016 ==
2625 04:42:13.083117 TX Vref=22, minBit 7, minWin=23, winSum=404
2626 04:42:13.086077 TX Vref=24, minBit 1, minWin=24, winSum=407
2627 04:42:13.089548 TX Vref=26, minBit 1, minWin=24, winSum=415
2628 04:42:13.093341 TX Vref=28, minBit 7, minWin=24, winSum=418
2629 04:42:13.096224 TX Vref=30, minBit 3, minWin=25, winSum=422
2630 04:42:13.099848 TX Vref=32, minBit 1, minWin=25, winSum=419
2631 04:42:13.106595 [TxChooseVref] Worse bit 3, Min win 25, Win sum 422, Final Vref 30
2632 04:42:13.106684
2633 04:42:13.109595 Final TX Range 1 Vref 30
2634 04:42:13.109703
2635 04:42:13.109801 ==
2636 04:42:13.113276 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 04:42:13.116463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 04:42:13.116564 ==
2639 04:42:13.116631
2640 04:42:13.119618
2641 04:42:13.119700 TX Vref Scan disable
2642 04:42:13.122805 == TX Byte 0 ==
2643 04:42:13.126647 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2644 04:42:13.129825 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2645 04:42:13.133257 == TX Byte 1 ==
2646 04:42:13.136547 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2647 04:42:13.139576 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2648 04:42:13.139659
2649 04:42:13.142943 [DATLAT]
2650 04:42:13.143026 Freq=1200, CH0 RK0
2651 04:42:13.143092
2652 04:42:13.146416 DATLAT Default: 0xd
2653 04:42:13.146499 0, 0xFFFF, sum = 0
2654 04:42:13.149862 1, 0xFFFF, sum = 0
2655 04:42:13.149963 2, 0xFFFF, sum = 0
2656 04:42:13.152888 3, 0xFFFF, sum = 0
2657 04:42:13.152972 4, 0xFFFF, sum = 0
2658 04:42:13.156349 5, 0xFFFF, sum = 0
2659 04:42:13.156433 6, 0xFFFF, sum = 0
2660 04:42:13.159518 7, 0xFFFF, sum = 0
2661 04:42:13.159603 8, 0xFFFF, sum = 0
2662 04:42:13.163004 9, 0xFFFF, sum = 0
2663 04:42:13.166320 10, 0xFFFF, sum = 0
2664 04:42:13.166404 11, 0xFFFF, sum = 0
2665 04:42:13.169570 12, 0x0, sum = 1
2666 04:42:13.169654 13, 0x0, sum = 2
2667 04:42:13.169739 14, 0x0, sum = 3
2668 04:42:13.173058 15, 0x0, sum = 4
2669 04:42:13.173185 best_step = 13
2670 04:42:13.173255
2671 04:42:13.173328 ==
2672 04:42:13.176476 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 04:42:13.183799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 04:42:13.183887 ==
2675 04:42:13.183995 RX Vref Scan: 1
2676 04:42:13.184058
2677 04:42:13.186438 Set Vref Range= 32 -> 127
2678 04:42:13.186523
2679 04:42:13.189828 RX Vref 32 -> 127, step: 1
2680 04:42:13.189948
2681 04:42:13.193333 RX Delay -13 -> 252, step: 4
2682 04:42:13.193417
2683 04:42:13.196728 Set Vref, RX VrefLevel [Byte0]: 32
2684 04:42:13.199560 [Byte1]: 32
2685 04:42:13.199644
2686 04:42:13.202940 Set Vref, RX VrefLevel [Byte0]: 33
2687 04:42:13.206637 [Byte1]: 33
2688 04:42:13.206724
2689 04:42:13.209724 Set Vref, RX VrefLevel [Byte0]: 34
2690 04:42:13.213264 [Byte1]: 34
2691 04:42:13.216903
2692 04:42:13.220094 Set Vref, RX VrefLevel [Byte0]: 35
2693 04:42:13.223319 [Byte1]: 35
2694 04:42:13.223403
2695 04:42:13.226830 Set Vref, RX VrefLevel [Byte0]: 36
2696 04:42:13.230234 [Byte1]: 36
2697 04:42:13.230318
2698 04:42:13.233452 Set Vref, RX VrefLevel [Byte0]: 37
2699 04:42:13.236904 [Byte1]: 37
2700 04:42:13.240681
2701 04:42:13.240766 Set Vref, RX VrefLevel [Byte0]: 38
2702 04:42:13.243997 [Byte1]: 38
2703 04:42:13.248478
2704 04:42:13.248563 Set Vref, RX VrefLevel [Byte0]: 39
2705 04:42:13.251941 [Byte1]: 39
2706 04:42:13.256258
2707 04:42:13.256342 Set Vref, RX VrefLevel [Byte0]: 40
2708 04:42:13.259735 [Byte1]: 40
2709 04:42:13.264511
2710 04:42:13.264595 Set Vref, RX VrefLevel [Byte0]: 41
2711 04:42:13.267817 [Byte1]: 41
2712 04:42:13.272245
2713 04:42:13.272329 Set Vref, RX VrefLevel [Byte0]: 42
2714 04:42:13.275386 [Byte1]: 42
2715 04:42:13.280117
2716 04:42:13.280201 Set Vref, RX VrefLevel [Byte0]: 43
2717 04:42:13.286826 [Byte1]: 43
2718 04:42:13.286911
2719 04:42:13.290056 Set Vref, RX VrefLevel [Byte0]: 44
2720 04:42:13.293556 [Byte1]: 44
2721 04:42:13.293640
2722 04:42:13.296456 Set Vref, RX VrefLevel [Byte0]: 45
2723 04:42:13.299812 [Byte1]: 45
2724 04:42:13.303932
2725 04:42:13.304015 Set Vref, RX VrefLevel [Byte0]: 46
2726 04:42:13.307155 [Byte1]: 46
2727 04:42:13.311590
2728 04:42:13.311709 Set Vref, RX VrefLevel [Byte0]: 47
2729 04:42:13.315288 [Byte1]: 47
2730 04:42:13.319695
2731 04:42:13.319779 Set Vref, RX VrefLevel [Byte0]: 48
2732 04:42:13.322781 [Byte1]: 48
2733 04:42:13.327571
2734 04:42:13.327655 Set Vref, RX VrefLevel [Byte0]: 49
2735 04:42:13.330988 [Byte1]: 49
2736 04:42:13.335410
2737 04:42:13.335493 Set Vref, RX VrefLevel [Byte0]: 50
2738 04:42:13.338570 [Byte1]: 50
2739 04:42:13.343252
2740 04:42:13.343328 Set Vref, RX VrefLevel [Byte0]: 51
2741 04:42:13.346282 [Byte1]: 51
2742 04:42:13.351219
2743 04:42:13.351293 Set Vref, RX VrefLevel [Byte0]: 52
2744 04:42:13.354567 [Byte1]: 52
2745 04:42:13.358951
2746 04:42:13.359027 Set Vref, RX VrefLevel [Byte0]: 53
2747 04:42:13.362523 [Byte1]: 53
2748 04:42:13.367180
2749 04:42:13.367254 Set Vref, RX VrefLevel [Byte0]: 54
2750 04:42:13.370386 [Byte1]: 54
2751 04:42:13.374767
2752 04:42:13.374839 Set Vref, RX VrefLevel [Byte0]: 55
2753 04:42:13.378056 [Byte1]: 55
2754 04:42:13.382715
2755 04:42:13.382791 Set Vref, RX VrefLevel [Byte0]: 56
2756 04:42:13.386162 [Byte1]: 56
2757 04:42:13.390824
2758 04:42:13.390897 Set Vref, RX VrefLevel [Byte0]: 57
2759 04:42:13.394215 [Byte1]: 57
2760 04:42:13.398546
2761 04:42:13.398624 Set Vref, RX VrefLevel [Byte0]: 58
2762 04:42:13.401502 [Byte1]: 58
2763 04:42:13.406447
2764 04:42:13.406534 Set Vref, RX VrefLevel [Byte0]: 59
2765 04:42:13.409815 [Byte1]: 59
2766 04:42:13.414498
2767 04:42:13.414580 Set Vref, RX VrefLevel [Byte0]: 60
2768 04:42:13.417294 [Byte1]: 60
2769 04:42:13.421919
2770 04:42:13.422048 Set Vref, RX VrefLevel [Byte0]: 61
2771 04:42:13.425494 [Byte1]: 61
2772 04:42:13.429891
2773 04:42:13.430016 Set Vref, RX VrefLevel [Byte0]: 62
2774 04:42:13.433316 [Byte1]: 62
2775 04:42:13.437887
2776 04:42:13.438020 Set Vref, RX VrefLevel [Byte0]: 63
2777 04:42:13.441104 [Byte1]: 63
2778 04:42:13.446129
2779 04:42:13.446288 Set Vref, RX VrefLevel [Byte0]: 64
2780 04:42:13.448998 [Byte1]: 64
2781 04:42:13.453521
2782 04:42:13.453606 Set Vref, RX VrefLevel [Byte0]: 65
2783 04:42:13.456916 [Byte1]: 65
2784 04:42:13.461908
2785 04:42:13.462002 Set Vref, RX VrefLevel [Byte0]: 66
2786 04:42:13.464890 [Byte1]: 66
2787 04:42:13.469601
2788 04:42:13.469684 Set Vref, RX VrefLevel [Byte0]: 67
2789 04:42:13.473064 [Byte1]: 67
2790 04:42:13.477393
2791 04:42:13.477476 Set Vref, RX VrefLevel [Byte0]: 68
2792 04:42:13.480701 [Byte1]: 68
2793 04:42:13.485203
2794 04:42:13.485286 Set Vref, RX VrefLevel [Byte0]: 69
2795 04:42:13.488593 [Byte1]: 69
2796 04:42:13.493034
2797 04:42:13.493118 Set Vref, RX VrefLevel [Byte0]: 70
2798 04:42:13.496371 [Byte1]: 70
2799 04:42:13.501212
2800 04:42:13.501296 Final RX Vref Byte 0 = 59 to rank0
2801 04:42:13.504509 Final RX Vref Byte 1 = 48 to rank0
2802 04:42:13.507572 Final RX Vref Byte 0 = 59 to rank1
2803 04:42:13.511029 Final RX Vref Byte 1 = 48 to rank1==
2804 04:42:13.514443 Dram Type= 6, Freq= 0, CH_0, rank 0
2805 04:42:13.521067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2806 04:42:13.521151 ==
2807 04:42:13.521234 DQS Delay:
2808 04:42:13.521311 DQS0 = 0, DQS1 = 0
2809 04:42:13.524361 DQM Delay:
2810 04:42:13.524481 DQM0 = 122, DQM1 = 108
2811 04:42:13.527814 DQ Delay:
2812 04:42:13.531045 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2813 04:42:13.534520 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2814 04:42:13.537581 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2815 04:42:13.541053 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =116
2816 04:42:13.541134
2817 04:42:13.541215
2818 04:42:13.550512 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2819 04:42:13.550611 CH0 RK0: MR19=404, MR18=D0A
2820 04:42:13.557187 CH0_RK0: MR19=0x404, MR18=0xD0A, DQSOSC=405, MR23=63, INC=39, DEC=26
2821 04:42:13.557293
2822 04:42:13.560931 ----->DramcWriteLeveling(PI) begin...
2823 04:42:13.561031 ==
2824 04:42:13.563908 Dram Type= 6, Freq= 0, CH_0, rank 1
2825 04:42:13.567252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 04:42:13.570613 ==
2827 04:42:13.570687 Write leveling (Byte 0): 34 => 34
2828 04:42:13.573879 Write leveling (Byte 1): 30 => 30
2829 04:42:13.577358 DramcWriteLeveling(PI) end<-----
2830 04:42:13.577442
2831 04:42:13.577507 ==
2832 04:42:13.580794 Dram Type= 6, Freq= 0, CH_0, rank 1
2833 04:42:13.587449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2834 04:42:13.587533 ==
2835 04:42:13.587596 [Gating] SW mode calibration
2836 04:42:13.597423 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2837 04:42:13.601224 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2838 04:42:13.604107 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2839 04:42:13.611000 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 04:42:13.614468 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 04:42:13.617373 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 04:42:13.624203 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 04:42:13.627907 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 04:42:13.631053 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 04:42:13.637844 0 15 28 | B1->B0 | 3131 3030 | 1 0 | (1 0) (1 0)
2846 04:42:13.641022 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 04:42:13.644702 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 04:42:13.648389 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 04:42:13.654479 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 04:42:13.657963 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 04:42:13.661515 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 04:42:13.667832 1 0 24 | B1->B0 | 2525 2d2d | 0 1 | (0 0) (1 1)
2853 04:42:13.671288 1 0 28 | B1->B0 | 3535 3d3d | 0 0 | (0 0) (0 0)
2854 04:42:13.674502 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 04:42:13.681501 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 04:42:13.684793 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 04:42:13.688285 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 04:42:13.694835 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 04:42:13.698261 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 04:42:13.701502 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 04:42:13.708257 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2862 04:42:13.711655 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 04:42:13.714944 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 04:42:13.721705 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 04:42:13.724697 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 04:42:13.728048 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 04:42:13.731644 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 04:42:13.738319 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 04:42:13.741698 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 04:42:13.745252 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 04:42:13.751905 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 04:42:13.754988 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 04:42:13.758336 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 04:42:13.765140 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 04:42:13.768323 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 04:42:13.771756 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2877 04:42:13.778674 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2878 04:42:13.782142 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 04:42:13.785075 Total UI for P1: 0, mck2ui 16
2880 04:42:13.788610 best dqsien dly found for B0: ( 1, 3, 26)
2881 04:42:13.791912 Total UI for P1: 0, mck2ui 16
2882 04:42:13.795304 best dqsien dly found for B1: ( 1, 3, 28)
2883 04:42:13.798601 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2884 04:42:13.802059 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2885 04:42:13.802143
2886 04:42:13.805049 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2887 04:42:13.808476 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2888 04:42:13.811758 [Gating] SW calibration Done
2889 04:42:13.811842 ==
2890 04:42:13.815227 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 04:42:13.818532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 04:42:13.818616 ==
2893 04:42:13.821455 RX Vref Scan: 0
2894 04:42:13.821538
2895 04:42:13.824873 RX Vref 0 -> 0, step: 1
2896 04:42:13.824955
2897 04:42:13.825022 RX Delay -40 -> 252, step: 8
2898 04:42:13.831711 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2899 04:42:13.834913 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2900 04:42:13.838619 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2901 04:42:13.841759 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2902 04:42:13.845034 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2903 04:42:13.851832 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2904 04:42:13.855249 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2905 04:42:13.858393 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2906 04:42:13.861622 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2907 04:42:13.865261 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2908 04:42:13.868715 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2909 04:42:13.875298 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2910 04:42:13.878453 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2911 04:42:13.881868 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2912 04:42:13.885246 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2913 04:42:13.888775 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2914 04:42:13.892101 ==
2915 04:42:13.895136 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 04:42:13.898496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 04:42:13.898598 ==
2918 04:42:13.898681 DQS Delay:
2919 04:42:13.902076 DQS0 = 0, DQS1 = 0
2920 04:42:13.902160 DQM Delay:
2921 04:42:13.905568 DQM0 = 120, DQM1 = 108
2922 04:42:13.905652 DQ Delay:
2923 04:42:13.908563 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2924 04:42:13.912194 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2925 04:42:13.915511 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2926 04:42:13.918916 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2927 04:42:13.919001
2928 04:42:13.919068
2929 04:42:13.919130 ==
2930 04:42:13.921971 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 04:42:13.928872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 04:42:13.928958 ==
2933 04:42:13.929026
2934 04:42:13.929089
2935 04:42:13.929149 TX Vref Scan disable
2936 04:42:13.932299 == TX Byte 0 ==
2937 04:42:13.935571 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2938 04:42:13.939020 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2939 04:42:13.942188 == TX Byte 1 ==
2940 04:42:13.945278 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2941 04:42:13.948571 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2942 04:42:13.952447 ==
2943 04:42:13.955328 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 04:42:13.958884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 04:42:13.958971 ==
2946 04:42:13.970115 TX Vref=22, minBit 0, minWin=24, winSum=410
2947 04:42:13.973665 TX Vref=24, minBit 7, minWin=24, winSum=414
2948 04:42:13.977031 TX Vref=26, minBit 0, minWin=25, winSum=414
2949 04:42:13.980304 TX Vref=28, minBit 0, minWin=25, winSum=419
2950 04:42:13.983243 TX Vref=30, minBit 3, minWin=25, winSum=418
2951 04:42:13.989916 TX Vref=32, minBit 1, minWin=25, winSum=417
2952 04:42:13.993458 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
2953 04:42:13.993544
2954 04:42:13.996727 Final TX Range 1 Vref 28
2955 04:42:13.996813
2956 04:42:13.996880 ==
2957 04:42:14.000046 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 04:42:14.003426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 04:42:14.003512 ==
2960 04:42:14.003580
2961 04:42:14.006810
2962 04:42:14.006896 TX Vref Scan disable
2963 04:42:14.010291 == TX Byte 0 ==
2964 04:42:14.013574 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2965 04:42:14.016621 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2966 04:42:14.020101 == TX Byte 1 ==
2967 04:42:14.023531 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2968 04:42:14.026578 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2969 04:42:14.029984
2970 04:42:14.030084 [DATLAT]
2971 04:42:14.030152 Freq=1200, CH0 RK1
2972 04:42:14.030215
2973 04:42:14.033418 DATLAT Default: 0xd
2974 04:42:14.033502 0, 0xFFFF, sum = 0
2975 04:42:14.036841 1, 0xFFFF, sum = 0
2976 04:42:14.036927 2, 0xFFFF, sum = 0
2977 04:42:14.040369 3, 0xFFFF, sum = 0
2978 04:42:14.040456 4, 0xFFFF, sum = 0
2979 04:42:14.043402 5, 0xFFFF, sum = 0
2980 04:42:14.043489 6, 0xFFFF, sum = 0
2981 04:42:14.046705 7, 0xFFFF, sum = 0
2982 04:42:14.049911 8, 0xFFFF, sum = 0
2983 04:42:14.050010 9, 0xFFFF, sum = 0
2984 04:42:14.053525 10, 0xFFFF, sum = 0
2985 04:42:14.053610 11, 0xFFFF, sum = 0
2986 04:42:14.056780 12, 0x0, sum = 1
2987 04:42:14.056865 13, 0x0, sum = 2
2988 04:42:14.060174 14, 0x0, sum = 3
2989 04:42:14.060259 15, 0x0, sum = 4
2990 04:42:14.060327 best_step = 13
2991 04:42:14.060394
2992 04:42:14.063337 ==
2993 04:42:14.063422 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 04:42:14.069935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 04:42:14.070060 ==
2996 04:42:14.070127 RX Vref Scan: 0
2997 04:42:14.070188
2998 04:42:14.073694 RX Vref 0 -> 0, step: 1
2999 04:42:14.073778
3000 04:42:14.077001 RX Delay -21 -> 252, step: 4
3001 04:42:14.080056 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3002 04:42:14.083478 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3003 04:42:14.090130 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3004 04:42:14.093508 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3005 04:42:14.097070 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3006 04:42:14.100575 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3007 04:42:14.103571 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3008 04:42:14.110483 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3009 04:42:14.113961 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3010 04:42:14.116993 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3011 04:42:14.120174 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3012 04:42:14.123472 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3013 04:42:14.130440 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3014 04:42:14.133827 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3015 04:42:14.136872 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3016 04:42:14.140275 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3017 04:42:14.140359 ==
3018 04:42:14.143584 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 04:42:14.146979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 04:42:14.150674 ==
3021 04:42:14.150758 DQS Delay:
3022 04:42:14.150826 DQS0 = 0, DQS1 = 0
3023 04:42:14.153816 DQM Delay:
3024 04:42:14.153900 DQM0 = 119, DQM1 = 108
3025 04:42:14.157181 DQ Delay:
3026 04:42:14.160565 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3027 04:42:14.163978 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3028 04:42:14.167383 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3029 04:42:14.170619 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3030 04:42:14.170704
3031 04:42:14.170770
3032 04:42:14.177068 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 405 ps
3033 04:42:14.180397 CH0 RK1: MR19=403, MR18=DF5
3034 04:42:14.187352 CH0_RK1: MR19=0x403, MR18=0xDF5, DQSOSC=405, MR23=63, INC=39, DEC=26
3035 04:42:14.190455 [RxdqsGatingPostProcess] freq 1200
3036 04:42:14.193976 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3037 04:42:14.196996 best DQS0 dly(2T, 0.5T) = (0, 11)
3038 04:42:14.200349 best DQS1 dly(2T, 0.5T) = (0, 11)
3039 04:42:14.203790 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3040 04:42:14.207262 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3041 04:42:14.210677 best DQS0 dly(2T, 0.5T) = (0, 11)
3042 04:42:14.213778 best DQS1 dly(2T, 0.5T) = (0, 11)
3043 04:42:14.217220 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3044 04:42:14.220640 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3045 04:42:14.223944 Pre-setting of DQS Precalculation
3046 04:42:14.226970 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3047 04:42:14.230666 ==
3048 04:42:14.230752 Dram Type= 6, Freq= 0, CH_1, rank 0
3049 04:42:14.237085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 04:42:14.237171 ==
3051 04:42:14.240505 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3052 04:42:14.247221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3053 04:42:14.256294 [CA 0] Center 37 (7~68) winsize 62
3054 04:42:14.260104 [CA 1] Center 37 (7~68) winsize 62
3055 04:42:14.262991 [CA 2] Center 35 (5~65) winsize 61
3056 04:42:14.266007 [CA 3] Center 34 (4~65) winsize 62
3057 04:42:14.269423 [CA 4] Center 34 (4~64) winsize 61
3058 04:42:14.272866 [CA 5] Center 33 (3~64) winsize 62
3059 04:42:14.272962
3060 04:42:14.276255 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3061 04:42:14.276340
3062 04:42:14.279815 [CATrainingPosCal] consider 1 rank data
3063 04:42:14.282796 u2DelayCellTimex100 = 270/100 ps
3064 04:42:14.286080 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3065 04:42:14.289303 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3066 04:42:14.296096 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3067 04:42:14.299465 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3068 04:42:14.302798 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3069 04:42:14.306416 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3070 04:42:14.306502
3071 04:42:14.309856 CA PerBit enable=1, Macro0, CA PI delay=33
3072 04:42:14.309964
3073 04:42:14.312746 [CBTSetCACLKResult] CA Dly = 33
3074 04:42:14.312831 CS Dly: 5 (0~36)
3075 04:42:14.312897 ==
3076 04:42:14.316504 Dram Type= 6, Freq= 0, CH_1, rank 1
3077 04:42:14.322840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 04:42:14.322932 ==
3079 04:42:14.326240 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3080 04:42:14.332803 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3081 04:42:14.341688 [CA 0] Center 38 (8~68) winsize 61
3082 04:42:14.345108 [CA 1] Center 38 (8~69) winsize 62
3083 04:42:14.348501 [CA 2] Center 35 (5~66) winsize 62
3084 04:42:14.351753 [CA 3] Center 35 (5~65) winsize 61
3085 04:42:14.355169 [CA 4] Center 35 (5~65) winsize 61
3086 04:42:14.358398 [CA 5] Center 34 (4~64) winsize 61
3087 04:42:14.358481
3088 04:42:14.361777 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3089 04:42:14.361853
3090 04:42:14.365185 [CATrainingPosCal] consider 2 rank data
3091 04:42:14.368558 u2DelayCellTimex100 = 270/100 ps
3092 04:42:14.371971 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3093 04:42:14.375342 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3094 04:42:14.382144 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3095 04:42:14.385039 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3096 04:42:14.388743 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3097 04:42:14.391992 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3098 04:42:14.392068
3099 04:42:14.395161 CA PerBit enable=1, Macro0, CA PI delay=34
3100 04:42:14.395237
3101 04:42:14.398493 [CBTSetCACLKResult] CA Dly = 34
3102 04:42:14.398575 CS Dly: 6 (0~39)
3103 04:42:14.398654
3104 04:42:14.401931 ----->DramcWriteLeveling(PI) begin...
3105 04:42:14.402050 ==
3106 04:42:14.405141 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 04:42:14.411965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 04:42:14.412059 ==
3109 04:42:14.415478 Write leveling (Byte 0): 23 => 23
3110 04:42:14.418896 Write leveling (Byte 1): 28 => 28
3111 04:42:14.418972 DramcWriteLeveling(PI) end<-----
3112 04:42:14.422076
3113 04:42:14.422157 ==
3114 04:42:14.425489 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 04:42:14.428373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 04:42:14.428455 ==
3117 04:42:14.431900 [Gating] SW mode calibration
3118 04:42:14.438528 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3119 04:42:14.441936 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3120 04:42:14.448669 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 04:42:14.451884 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 04:42:14.455443 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 04:42:14.462167 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 04:42:14.465346 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 04:42:14.468649 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 04:42:14.475228 0 15 24 | B1->B0 | 2b2b 2727 | 0 0 | (0 1) (1 1)
3127 04:42:14.478621 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3128 04:42:14.482065 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 04:42:14.488679 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 04:42:14.492085 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 04:42:14.495201 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 04:42:14.501884 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 04:42:14.505258 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3134 04:42:14.508911 1 0 24 | B1->B0 | 3939 4444 | 1 0 | (0 0) (0 0)
3135 04:42:14.512171 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 04:42:14.518482 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 04:42:14.521744 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 04:42:14.525570 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 04:42:14.531885 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 04:42:14.535212 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 04:42:14.538565 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3142 04:42:14.545361 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3143 04:42:14.548862 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3144 04:42:14.552016 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 04:42:14.558483 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 04:42:14.561858 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 04:42:14.565202 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 04:42:14.571918 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 04:42:14.575316 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 04:42:14.578649 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 04:42:14.585467 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 04:42:14.588813 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 04:42:14.592257 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 04:42:14.598813 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 04:42:14.601863 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 04:42:14.605319 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 04:42:14.608837 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 04:42:14.615603 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3159 04:42:14.618961 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3160 04:42:14.621907 Total UI for P1: 0, mck2ui 16
3161 04:42:14.625446 best dqsien dly found for B0: ( 1, 3, 24)
3162 04:42:14.628657 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 04:42:14.631835 Total UI for P1: 0, mck2ui 16
3164 04:42:14.635366 best dqsien dly found for B1: ( 1, 3, 26)
3165 04:42:14.638580 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3166 04:42:14.642312 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3167 04:42:14.642400
3168 04:42:14.648625 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3169 04:42:14.652060 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3170 04:42:14.652145 [Gating] SW calibration Done
3171 04:42:14.655244 ==
3172 04:42:14.658640 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 04:42:14.662142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 04:42:14.662228 ==
3175 04:42:14.662296 RX Vref Scan: 0
3176 04:42:14.662359
3177 04:42:14.665419 RX Vref 0 -> 0, step: 1
3178 04:42:14.665504
3179 04:42:14.668873 RX Delay -40 -> 252, step: 8
3180 04:42:14.672101 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3181 04:42:14.675676 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3182 04:42:14.678989 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3183 04:42:14.685776 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3184 04:42:14.688800 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3185 04:42:14.692131 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3186 04:42:14.695624 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3187 04:42:14.698881 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3188 04:42:14.705634 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3189 04:42:14.708990 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3190 04:42:14.712189 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3191 04:42:14.715909 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3192 04:42:14.719125 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3193 04:42:14.725486 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3194 04:42:14.728869 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3195 04:42:14.732222 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3196 04:42:14.732307 ==
3197 04:42:14.735564 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 04:42:14.738962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 04:42:14.739048 ==
3200 04:42:14.742400 DQS Delay:
3201 04:42:14.742485 DQS0 = 0, DQS1 = 0
3202 04:42:14.745478 DQM Delay:
3203 04:42:14.745564 DQM0 = 119, DQM1 = 112
3204 04:42:14.745630 DQ Delay:
3205 04:42:14.749148 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3206 04:42:14.752601 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3207 04:42:14.759250 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3208 04:42:14.762272 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3209 04:42:14.762357
3210 04:42:14.762424
3211 04:42:14.762487 ==
3212 04:42:14.765681 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 04:42:14.769155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 04:42:14.769241 ==
3215 04:42:14.769307
3216 04:42:14.769369
3217 04:42:14.772588 TX Vref Scan disable
3218 04:42:14.772672 == TX Byte 0 ==
3219 04:42:14.779115 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3220 04:42:14.782593 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3221 04:42:14.782679 == TX Byte 1 ==
3222 04:42:14.789110 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3223 04:42:14.792572 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3224 04:42:14.792656 ==
3225 04:42:14.796049 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 04:42:14.799521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 04:42:14.799607 ==
3228 04:42:14.812095 TX Vref=22, minBit 11, minWin=24, winSum=408
3229 04:42:14.815373 TX Vref=24, minBit 8, minWin=25, winSum=416
3230 04:42:14.818493 TX Vref=26, minBit 8, minWin=25, winSum=415
3231 04:42:14.822105 TX Vref=28, minBit 9, minWin=25, winSum=420
3232 04:42:14.825240 TX Vref=30, minBit 10, minWin=25, winSum=422
3233 04:42:14.832004 TX Vref=32, minBit 9, minWin=24, winSum=419
3234 04:42:14.835400 [TxChooseVref] Worse bit 10, Min win 25, Win sum 422, Final Vref 30
3235 04:42:14.835488
3236 04:42:14.838700 Final TX Range 1 Vref 30
3237 04:42:14.838798
3238 04:42:14.838898 ==
3239 04:42:14.842093 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 04:42:14.845394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 04:42:14.845492 ==
3242 04:42:14.848717
3243 04:42:14.848799
3244 04:42:14.848862 TX Vref Scan disable
3245 04:42:14.852228 == TX Byte 0 ==
3246 04:42:14.855295 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3247 04:42:14.858626 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3248 04:42:14.861929 == TX Byte 1 ==
3249 04:42:14.865533 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3250 04:42:14.871934 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3251 04:42:14.872018
3252 04:42:14.872110 [DATLAT]
3253 04:42:14.872199 Freq=1200, CH1 RK0
3254 04:42:14.872291
3255 04:42:14.875443 DATLAT Default: 0xd
3256 04:42:14.875511 0, 0xFFFF, sum = 0
3257 04:42:14.878775 1, 0xFFFF, sum = 0
3258 04:42:14.878852 2, 0xFFFF, sum = 0
3259 04:42:14.881810 3, 0xFFFF, sum = 0
3260 04:42:14.884989 4, 0xFFFF, sum = 0
3261 04:42:14.885091 5, 0xFFFF, sum = 0
3262 04:42:14.888611 6, 0xFFFF, sum = 0
3263 04:42:14.888688 7, 0xFFFF, sum = 0
3264 04:42:14.891995 8, 0xFFFF, sum = 0
3265 04:42:14.892067 9, 0xFFFF, sum = 0
3266 04:42:14.894966 10, 0xFFFF, sum = 0
3267 04:42:14.895042 11, 0xFFFF, sum = 0
3268 04:42:14.898331 12, 0x0, sum = 1
3269 04:42:14.898402 13, 0x0, sum = 2
3270 04:42:14.901771 14, 0x0, sum = 3
3271 04:42:14.901869 15, 0x0, sum = 4
3272 04:42:14.901963 best_step = 13
3273 04:42:14.902024
3274 04:42:14.905197 ==
3275 04:42:14.908664 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 04:42:14.911764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 04:42:14.911865 ==
3278 04:42:14.911960 RX Vref Scan: 1
3279 04:42:14.912049
3280 04:42:14.915454 Set Vref Range= 32 -> 127
3281 04:42:14.915549
3282 04:42:14.918558 RX Vref 32 -> 127, step: 1
3283 04:42:14.918628
3284 04:42:14.921800 RX Delay -13 -> 252, step: 4
3285 04:42:14.921893
3286 04:42:14.925173 Set Vref, RX VrefLevel [Byte0]: 32
3287 04:42:14.928360 [Byte1]: 32
3288 04:42:14.928431
3289 04:42:14.932180 Set Vref, RX VrefLevel [Byte0]: 33
3290 04:42:14.935151 [Byte1]: 33
3291 04:42:14.935224
3292 04:42:14.938531 Set Vref, RX VrefLevel [Byte0]: 34
3293 04:42:14.941864 [Byte1]: 34
3294 04:42:14.946229
3295 04:42:14.946303 Set Vref, RX VrefLevel [Byte0]: 35
3296 04:42:14.949546 [Byte1]: 35
3297 04:42:14.954107
3298 04:42:14.954203 Set Vref, RX VrefLevel [Byte0]: 36
3299 04:42:14.957473 [Byte1]: 36
3300 04:42:14.961798
3301 04:42:14.961896 Set Vref, RX VrefLevel [Byte0]: 37
3302 04:42:14.965163 [Byte1]: 37
3303 04:42:14.969745
3304 04:42:14.969844 Set Vref, RX VrefLevel [Byte0]: 38
3305 04:42:14.973110 [Byte1]: 38
3306 04:42:14.978066
3307 04:42:14.978143 Set Vref, RX VrefLevel [Byte0]: 39
3308 04:42:14.980956 [Byte1]: 39
3309 04:42:14.985765
3310 04:42:14.985864 Set Vref, RX VrefLevel [Byte0]: 40
3311 04:42:14.988969 [Byte1]: 40
3312 04:42:14.993695
3313 04:42:14.993767 Set Vref, RX VrefLevel [Byte0]: 41
3314 04:42:14.996895 [Byte1]: 41
3315 04:42:15.001374
3316 04:42:15.001470 Set Vref, RX VrefLevel [Byte0]: 42
3317 04:42:15.004775 [Byte1]: 42
3318 04:42:15.009166
3319 04:42:15.009244 Set Vref, RX VrefLevel [Byte0]: 43
3320 04:42:15.012583 [Byte1]: 43
3321 04:42:15.017081
3322 04:42:15.017179 Set Vref, RX VrefLevel [Byte0]: 44
3323 04:42:15.020663 [Byte1]: 44
3324 04:42:15.025250
3325 04:42:15.025333 Set Vref, RX VrefLevel [Byte0]: 45
3326 04:42:15.028154 [Byte1]: 45
3327 04:42:15.033360
3328 04:42:15.033458 Set Vref, RX VrefLevel [Byte0]: 46
3329 04:42:15.036146 [Byte1]: 46
3330 04:42:15.040779
3331 04:42:15.040850 Set Vref, RX VrefLevel [Byte0]: 47
3332 04:42:15.044037 [Byte1]: 47
3333 04:42:15.048679
3334 04:42:15.048786 Set Vref, RX VrefLevel [Byte0]: 48
3335 04:42:15.052077 [Byte1]: 48
3336 04:42:15.056458
3337 04:42:15.056534 Set Vref, RX VrefLevel [Byte0]: 49
3338 04:42:15.060249 [Byte1]: 49
3339 04:42:15.064471
3340 04:42:15.064567 Set Vref, RX VrefLevel [Byte0]: 50
3341 04:42:15.067923 [Byte1]: 50
3342 04:42:15.072206
3343 04:42:15.072304 Set Vref, RX VrefLevel [Byte0]: 51
3344 04:42:15.075724 [Byte1]: 51
3345 04:42:15.080692
3346 04:42:15.080796 Set Vref, RX VrefLevel [Byte0]: 52
3347 04:42:15.083564 [Byte1]: 52
3348 04:42:15.088235
3349 04:42:15.088322 Set Vref, RX VrefLevel [Byte0]: 53
3350 04:42:15.091526 [Byte1]: 53
3351 04:42:15.096070
3352 04:42:15.096172 Set Vref, RX VrefLevel [Byte0]: 54
3353 04:42:15.099729 [Byte1]: 54
3354 04:42:15.104160
3355 04:42:15.104256 Set Vref, RX VrefLevel [Byte0]: 55
3356 04:42:15.107155 [Byte1]: 55
3357 04:42:15.111971
3358 04:42:15.112083 Set Vref, RX VrefLevel [Byte0]: 56
3359 04:42:15.115430 [Byte1]: 56
3360 04:42:15.119846
3361 04:42:15.119950 Set Vref, RX VrefLevel [Byte0]: 57
3362 04:42:15.123145 [Byte1]: 57
3363 04:42:15.127671
3364 04:42:15.127781 Set Vref, RX VrefLevel [Byte0]: 58
3365 04:42:15.130840 [Byte1]: 58
3366 04:42:15.135645
3367 04:42:15.135717 Set Vref, RX VrefLevel [Byte0]: 59
3368 04:42:15.138942 [Byte1]: 59
3369 04:42:15.143174
3370 04:42:15.143274 Set Vref, RX VrefLevel [Byte0]: 60
3371 04:42:15.146951 [Byte1]: 60
3372 04:42:15.151232
3373 04:42:15.151306 Set Vref, RX VrefLevel [Byte0]: 61
3374 04:42:15.154623 [Byte1]: 61
3375 04:42:15.159497
3376 04:42:15.159568 Set Vref, RX VrefLevel [Byte0]: 62
3377 04:42:15.162379 [Byte1]: 62
3378 04:42:15.166866
3379 04:42:15.166939 Set Vref, RX VrefLevel [Byte0]: 63
3380 04:42:15.170191 [Byte1]: 63
3381 04:42:15.175135
3382 04:42:15.175242 Set Vref, RX VrefLevel [Byte0]: 64
3383 04:42:15.178136 [Byte1]: 64
3384 04:42:15.182564
3385 04:42:15.182638 Set Vref, RX VrefLevel [Byte0]: 65
3386 04:42:15.185949 [Byte1]: 65
3387 04:42:15.190654
3388 04:42:15.190755 Set Vref, RX VrefLevel [Byte0]: 66
3389 04:42:15.193935 [Byte1]: 66
3390 04:42:15.198547
3391 04:42:15.198621 Final RX Vref Byte 0 = 53 to rank0
3392 04:42:15.201924 Final RX Vref Byte 1 = 53 to rank0
3393 04:42:15.205305 Final RX Vref Byte 0 = 53 to rank1
3394 04:42:15.208566 Final RX Vref Byte 1 = 53 to rank1==
3395 04:42:15.212043 Dram Type= 6, Freq= 0, CH_1, rank 0
3396 04:42:15.215499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3397 04:42:15.218889 ==
3398 04:42:15.218960 DQS Delay:
3399 04:42:15.219022 DQS0 = 0, DQS1 = 0
3400 04:42:15.222150 DQM Delay:
3401 04:42:15.222217 DQM0 = 119, DQM1 = 112
3402 04:42:15.225406 DQ Delay:
3403 04:42:15.228673 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3404 04:42:15.232243 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3405 04:42:15.235466 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3406 04:42:15.238820 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =118
3407 04:42:15.238891
3408 04:42:15.238953
3409 04:42:15.245243 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3410 04:42:15.249019 CH1 RK0: MR19=404, MR18=13
3411 04:42:15.255353 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3412 04:42:15.255434
3413 04:42:15.258756 ----->DramcWriteLeveling(PI) begin...
3414 04:42:15.258828 ==
3415 04:42:15.262231 Dram Type= 6, Freq= 0, CH_1, rank 1
3416 04:42:15.265560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3417 04:42:15.265659 ==
3418 04:42:15.268878 Write leveling (Byte 0): 23 => 23
3419 04:42:15.272221 Write leveling (Byte 1): 29 => 29
3420 04:42:15.275640 DramcWriteLeveling(PI) end<-----
3421 04:42:15.275710
3422 04:42:15.275775 ==
3423 04:42:15.278983 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 04:42:15.282380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 04:42:15.282449 ==
3426 04:42:15.285754 [Gating] SW mode calibration
3427 04:42:15.292496 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3428 04:42:15.299226 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3429 04:42:15.302694 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 04:42:15.309136 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3431 04:42:15.312505 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 04:42:15.315961 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3433 04:42:15.318830 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 04:42:15.325729 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 04:42:15.329056 0 15 24 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 1)
3436 04:42:15.332327 0 15 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 1)
3437 04:42:15.339315 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3438 04:42:15.342255 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 04:42:15.345937 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 04:42:15.352340 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 04:42:15.355682 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 04:42:15.358942 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3443 04:42:15.365829 1 0 24 | B1->B0 | 3f3f 2e2e | 1 1 | (0 0) (0 0)
3444 04:42:15.369092 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3445 04:42:15.372568 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 04:42:15.379290 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 04:42:15.382787 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 04:42:15.385704 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 04:42:15.392443 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 04:42:15.395940 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 04:42:15.399096 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3452 04:42:15.402526 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3453 04:42:15.409189 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 04:42:15.412587 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 04:42:15.416143 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 04:42:15.422429 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 04:42:15.425842 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 04:42:15.429253 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 04:42:15.435815 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 04:42:15.439023 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 04:42:15.442217 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 04:42:15.449338 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 04:42:15.452349 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 04:42:15.456044 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 04:42:15.462389 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 04:42:15.465707 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3467 04:42:15.469203 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3468 04:42:15.476042 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 04:42:15.476151 Total UI for P1: 0, mck2ui 16
3470 04:42:15.482585 best dqsien dly found for B0: ( 1, 3, 24)
3471 04:42:15.482660 Total UI for P1: 0, mck2ui 16
3472 04:42:15.486018 best dqsien dly found for B1: ( 1, 3, 22)
3473 04:42:15.492315 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3474 04:42:15.495897 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3475 04:42:15.495988
3476 04:42:15.499274 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3477 04:42:15.502503 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3478 04:42:15.505811 [Gating] SW calibration Done
3479 04:42:15.505908 ==
3480 04:42:15.509152 Dram Type= 6, Freq= 0, CH_1, rank 1
3481 04:42:15.512551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 04:42:15.512664 ==
3483 04:42:15.515832 RX Vref Scan: 0
3484 04:42:15.515932
3485 04:42:15.516025 RX Vref 0 -> 0, step: 1
3486 04:42:15.516113
3487 04:42:15.519293 RX Delay -40 -> 252, step: 8
3488 04:42:15.522290 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3489 04:42:15.525832 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3490 04:42:15.532334 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3491 04:42:15.535673 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3492 04:42:15.538888 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3493 04:42:15.542072 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3494 04:42:15.545837 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3495 04:42:15.552244 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3496 04:42:15.555673 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3497 04:42:15.559097 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3498 04:42:15.562032 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3499 04:42:15.565473 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3500 04:42:15.572223 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3501 04:42:15.575556 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3502 04:42:15.578943 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3503 04:42:15.582064 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3504 04:42:15.582147 ==
3505 04:42:15.585527 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 04:42:15.592370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 04:42:15.592454 ==
3508 04:42:15.592521 DQS Delay:
3509 04:42:15.595413 DQS0 = 0, DQS1 = 0
3510 04:42:15.595495 DQM Delay:
3511 04:42:15.598711 DQM0 = 120, DQM1 = 113
3512 04:42:15.598793 DQ Delay:
3513 04:42:15.602058 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3514 04:42:15.605367 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3515 04:42:15.608823 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3516 04:42:15.612144 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =123
3517 04:42:15.612230
3518 04:42:15.612297
3519 04:42:15.612393 ==
3520 04:42:15.615235 Dram Type= 6, Freq= 0, CH_1, rank 1
3521 04:42:15.618591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3522 04:42:15.622080 ==
3523 04:42:15.622157
3524 04:42:15.622229
3525 04:42:15.622291 TX Vref Scan disable
3526 04:42:15.625552 == TX Byte 0 ==
3527 04:42:15.628801 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3528 04:42:15.632160 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3529 04:42:15.635610 == TX Byte 1 ==
3530 04:42:15.638540 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3531 04:42:15.642227 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3532 04:42:15.642308 ==
3533 04:42:15.645414 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 04:42:15.651890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 04:42:15.651966 ==
3536 04:42:15.663247 TX Vref=22, minBit 1, minWin=25, winSum=418
3537 04:42:15.666350 TX Vref=24, minBit 1, minWin=25, winSum=419
3538 04:42:15.670155 TX Vref=26, minBit 0, minWin=26, winSum=425
3539 04:42:15.673488 TX Vref=28, minBit 1, minWin=26, winSum=427
3540 04:42:15.676298 TX Vref=30, minBit 1, minWin=26, winSum=427
3541 04:42:15.679623 TX Vref=32, minBit 9, minWin=25, winSum=425
3542 04:42:15.686518 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
3543 04:42:15.686598
3544 04:42:15.689861 Final TX Range 1 Vref 28
3545 04:42:15.689955
3546 04:42:15.690031 ==
3547 04:42:15.692926 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 04:42:15.696690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 04:42:15.696760 ==
3550 04:42:15.696827
3551 04:42:15.699651
3552 04:42:15.699723 TX Vref Scan disable
3553 04:42:15.702987 == TX Byte 0 ==
3554 04:42:15.706597 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3555 04:42:15.709876 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3556 04:42:15.713087 == TX Byte 1 ==
3557 04:42:15.716565 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3558 04:42:15.719976 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3559 04:42:15.723285
3560 04:42:15.723353 [DATLAT]
3561 04:42:15.723420 Freq=1200, CH1 RK1
3562 04:42:15.723479
3563 04:42:15.726175 DATLAT Default: 0xd
3564 04:42:15.726245 0, 0xFFFF, sum = 0
3565 04:42:15.729460 1, 0xFFFF, sum = 0
3566 04:42:15.729534 2, 0xFFFF, sum = 0
3567 04:42:15.732801 3, 0xFFFF, sum = 0
3568 04:42:15.736237 4, 0xFFFF, sum = 0
3569 04:42:15.736312 5, 0xFFFF, sum = 0
3570 04:42:15.739688 6, 0xFFFF, sum = 0
3571 04:42:15.739756 7, 0xFFFF, sum = 0
3572 04:42:15.742688 8, 0xFFFF, sum = 0
3573 04:42:15.742765 9, 0xFFFF, sum = 0
3574 04:42:15.746262 10, 0xFFFF, sum = 0
3575 04:42:15.746330 11, 0xFFFF, sum = 0
3576 04:42:15.749419 12, 0x0, sum = 1
3577 04:42:15.749491 13, 0x0, sum = 2
3578 04:42:15.752645 14, 0x0, sum = 3
3579 04:42:15.752712 15, 0x0, sum = 4
3580 04:42:15.752773 best_step = 13
3581 04:42:15.756040
3582 04:42:15.756111 ==
3583 04:42:15.759221 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 04:42:15.762499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 04:42:15.762567 ==
3586 04:42:15.762634 RX Vref Scan: 0
3587 04:42:15.762691
3588 04:42:15.766289 RX Vref 0 -> 0, step: 1
3589 04:42:15.766354
3590 04:42:15.769551 RX Delay -13 -> 252, step: 4
3591 04:42:15.772796 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3592 04:42:15.779540 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3593 04:42:15.782603 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3594 04:42:15.785886 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3595 04:42:15.789358 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3596 04:42:15.792484 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3597 04:42:15.799364 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3598 04:42:15.802747 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3599 04:42:15.805797 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3600 04:42:15.809276 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3601 04:42:15.812662 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3602 04:42:15.819272 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3603 04:42:15.822716 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3604 04:42:15.826254 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3605 04:42:15.829504 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3606 04:42:15.832993 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3607 04:42:15.833078 ==
3608 04:42:15.835972 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 04:42:15.842920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 04:42:15.843013 ==
3611 04:42:15.843078 DQS Delay:
3612 04:42:15.845915 DQS0 = 0, DQS1 = 0
3613 04:42:15.846043 DQM Delay:
3614 04:42:15.849200 DQM0 = 119, DQM1 = 113
3615 04:42:15.849287 DQ Delay:
3616 04:42:15.852873 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3617 04:42:15.856002 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3618 04:42:15.859198 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =108
3619 04:42:15.862587 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3620 04:42:15.862672
3621 04:42:15.862739
3622 04:42:15.872687 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 405 ps
3623 04:42:15.872771 CH1 RK1: MR19=403, MR18=CF1
3624 04:42:15.879171 CH1_RK1: MR19=0x403, MR18=0xCF1, DQSOSC=405, MR23=63, INC=39, DEC=26
3625 04:42:15.882546 [RxdqsGatingPostProcess] freq 1200
3626 04:42:15.889029 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3627 04:42:15.892727 best DQS0 dly(2T, 0.5T) = (0, 11)
3628 04:42:15.895961 best DQS1 dly(2T, 0.5T) = (0, 11)
3629 04:42:15.898985 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3630 04:42:15.902439 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3631 04:42:15.902509 best DQS0 dly(2T, 0.5T) = (0, 11)
3632 04:42:15.905923 best DQS1 dly(2T, 0.5T) = (0, 11)
3633 04:42:15.909376 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3634 04:42:15.912661 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3635 04:42:15.915795 Pre-setting of DQS Precalculation
3636 04:42:15.922424 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3637 04:42:15.928937 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3638 04:42:15.935672 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3639 04:42:15.935771
3640 04:42:15.935836
3641 04:42:15.939026 [Calibration Summary] 2400 Mbps
3642 04:42:15.939108 CH 0, Rank 0
3643 04:42:15.942996 SW Impedance : PASS
3644 04:42:15.945926 DUTY Scan : NO K
3645 04:42:15.946019 ZQ Calibration : PASS
3646 04:42:15.948934 Jitter Meter : NO K
3647 04:42:15.952230 CBT Training : PASS
3648 04:42:15.952314 Write leveling : PASS
3649 04:42:15.955942 RX DQS gating : PASS
3650 04:42:15.958949 RX DQ/DQS(RDDQC) : PASS
3651 04:42:15.959024 TX DQ/DQS : PASS
3652 04:42:15.962256 RX DATLAT : PASS
3653 04:42:15.965711 RX DQ/DQS(Engine): PASS
3654 04:42:15.965778 TX OE : NO K
3655 04:42:15.968924 All Pass.
3656 04:42:15.969001
3657 04:42:15.969063 CH 0, Rank 1
3658 04:42:15.972420 SW Impedance : PASS
3659 04:42:15.972495 DUTY Scan : NO K
3660 04:42:15.975487 ZQ Calibration : PASS
3661 04:42:15.978789 Jitter Meter : NO K
3662 04:42:15.978866 CBT Training : PASS
3663 04:42:15.982025 Write leveling : PASS
3664 04:42:15.985612 RX DQS gating : PASS
3665 04:42:15.985702 RX DQ/DQS(RDDQC) : PASS
3666 04:42:15.988498 TX DQ/DQS : PASS
3667 04:42:15.988566 RX DATLAT : PASS
3668 04:42:15.991974 RX DQ/DQS(Engine): PASS
3669 04:42:15.995394 TX OE : NO K
3670 04:42:15.995468 All Pass.
3671 04:42:15.995530
3672 04:42:15.995617 CH 1, Rank 0
3673 04:42:15.998466 SW Impedance : PASS
3674 04:42:16.001858 DUTY Scan : NO K
3675 04:42:16.001925 ZQ Calibration : PASS
3676 04:42:16.005371 Jitter Meter : NO K
3677 04:42:16.008786 CBT Training : PASS
3678 04:42:16.008854 Write leveling : PASS
3679 04:42:16.012242 RX DQS gating : PASS
3680 04:42:16.015616 RX DQ/DQS(RDDQC) : PASS
3681 04:42:16.015688 TX DQ/DQS : PASS
3682 04:42:16.018541 RX DATLAT : PASS
3683 04:42:16.021923 RX DQ/DQS(Engine): PASS
3684 04:42:16.022039 TX OE : NO K
3685 04:42:16.025378 All Pass.
3686 04:42:16.025459
3687 04:42:16.025520 CH 1, Rank 1
3688 04:42:16.028499 SW Impedance : PASS
3689 04:42:16.028573 DUTY Scan : NO K
3690 04:42:16.032235 ZQ Calibration : PASS
3691 04:42:16.035059 Jitter Meter : NO K
3692 04:42:16.035159 CBT Training : PASS
3693 04:42:16.038555 Write leveling : PASS
3694 04:42:16.042088 RX DQS gating : PASS
3695 04:42:16.042159 RX DQ/DQS(RDDQC) : PASS
3696 04:42:16.044952 TX DQ/DQS : PASS
3697 04:42:16.045023 RX DATLAT : PASS
3698 04:42:16.048493 RX DQ/DQS(Engine): PASS
3699 04:42:16.051990 TX OE : NO K
3700 04:42:16.052062 All Pass.
3701 04:42:16.052124
3702 04:42:16.055416 DramC Write-DBI off
3703 04:42:16.055484 PER_BANK_REFRESH: Hybrid Mode
3704 04:42:16.058285 TX_TRACKING: ON
3705 04:42:16.068475 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3706 04:42:16.071761 [FAST_K] Save calibration result to emmc
3707 04:42:16.074944 dramc_set_vcore_voltage set vcore to 650000
3708 04:42:16.075016 Read voltage for 600, 5
3709 04:42:16.078292 Vio18 = 0
3710 04:42:16.078368 Vcore = 650000
3711 04:42:16.078429 Vdram = 0
3712 04:42:16.081550 Vddq = 0
3713 04:42:16.081624 Vmddr = 0
3714 04:42:16.085154 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3715 04:42:16.091390 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3716 04:42:16.094850 MEM_TYPE=3, freq_sel=19
3717 04:42:16.098188 sv_algorithm_assistance_LP4_1600
3718 04:42:16.101408 ============ PULL DRAM RESETB DOWN ============
3719 04:42:16.104822 ========== PULL DRAM RESETB DOWN end =========
3720 04:42:16.111782 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3721 04:42:16.115229 ===================================
3722 04:42:16.115306 LPDDR4 DRAM CONFIGURATION
3723 04:42:16.118567 ===================================
3724 04:42:16.121508 EX_ROW_EN[0] = 0x0
3725 04:42:16.121577 EX_ROW_EN[1] = 0x0
3726 04:42:16.125281 LP4Y_EN = 0x0
3727 04:42:16.125366 WORK_FSP = 0x0
3728 04:42:16.128126 WL = 0x2
3729 04:42:16.131850 RL = 0x2
3730 04:42:16.131919 BL = 0x2
3731 04:42:16.135028 RPST = 0x0
3732 04:42:16.135100 RD_PRE = 0x0
3733 04:42:16.138566 WR_PRE = 0x1
3734 04:42:16.138636 WR_PST = 0x0
3735 04:42:16.141533 DBI_WR = 0x0
3736 04:42:16.141607 DBI_RD = 0x0
3737 04:42:16.145031 OTF = 0x1
3738 04:42:16.148427 ===================================
3739 04:42:16.151472 ===================================
3740 04:42:16.151551 ANA top config
3741 04:42:16.154848 ===================================
3742 04:42:16.158453 DLL_ASYNC_EN = 0
3743 04:42:16.161640 ALL_SLAVE_EN = 1
3744 04:42:16.161738 NEW_RANK_MODE = 1
3745 04:42:16.164830 DLL_IDLE_MODE = 1
3746 04:42:16.168516 LP45_APHY_COMB_EN = 1
3747 04:42:16.171694 TX_ODT_DIS = 1
3748 04:42:16.171787 NEW_8X_MODE = 1
3749 04:42:16.175163 ===================================
3750 04:42:16.178525 ===================================
3751 04:42:16.181439 data_rate = 1200
3752 04:42:16.184740 CKR = 1
3753 04:42:16.188556 DQ_P2S_RATIO = 8
3754 04:42:16.191479 ===================================
3755 04:42:16.195024 CA_P2S_RATIO = 8
3756 04:42:16.198600 DQ_CA_OPEN = 0
3757 04:42:16.198682 DQ_SEMI_OPEN = 0
3758 04:42:16.201555 CA_SEMI_OPEN = 0
3759 04:42:16.204875 CA_FULL_RATE = 0
3760 04:42:16.208057 DQ_CKDIV4_EN = 1
3761 04:42:16.211537 CA_CKDIV4_EN = 1
3762 04:42:16.214934 CA_PREDIV_EN = 0
3763 04:42:16.215031 PH8_DLY = 0
3764 04:42:16.218364 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3765 04:42:16.221718 DQ_AAMCK_DIV = 4
3766 04:42:16.224686 CA_AAMCK_DIV = 4
3767 04:42:16.228251 CA_ADMCK_DIV = 4
3768 04:42:16.231219 DQ_TRACK_CA_EN = 0
3769 04:42:16.231301 CA_PICK = 600
3770 04:42:16.234941 CA_MCKIO = 600
3771 04:42:16.238321 MCKIO_SEMI = 0
3772 04:42:16.241098 PLL_FREQ = 2288
3773 04:42:16.244658 DQ_UI_PI_RATIO = 32
3774 04:42:16.248131 CA_UI_PI_RATIO = 0
3775 04:42:16.251117 ===================================
3776 04:42:16.254663 ===================================
3777 04:42:16.257628 memory_type:LPDDR4
3778 04:42:16.257710 GP_NUM : 10
3779 04:42:16.261071 SRAM_EN : 1
3780 04:42:16.261153 MD32_EN : 0
3781 04:42:16.264519 ===================================
3782 04:42:16.267674 [ANA_INIT] >>>>>>>>>>>>>>
3783 04:42:16.270930 <<<<<< [CONFIGURE PHASE]: ANA_TX
3784 04:42:16.274277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3785 04:42:16.277657 ===================================
3786 04:42:16.280965 data_rate = 1200,PCW = 0X5800
3787 04:42:16.284452 ===================================
3788 04:42:16.287537 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3789 04:42:16.290848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3790 04:42:16.297600 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3791 04:42:16.304516 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3792 04:42:16.307478 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3793 04:42:16.310912 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3794 04:42:16.310996 [ANA_INIT] flow start
3795 04:42:16.314504 [ANA_INIT] PLL >>>>>>>>
3796 04:42:16.317413 [ANA_INIT] PLL <<<<<<<<
3797 04:42:16.317495 [ANA_INIT] MIDPI >>>>>>>>
3798 04:42:16.320990 [ANA_INIT] MIDPI <<<<<<<<
3799 04:42:16.324431 [ANA_INIT] DLL >>>>>>>>
3800 04:42:16.324514 [ANA_INIT] flow end
3801 04:42:16.330778 ============ LP4 DIFF to SE enter ============
3802 04:42:16.334160 ============ LP4 DIFF to SE exit ============
3803 04:42:16.334243 [ANA_INIT] <<<<<<<<<<<<<
3804 04:42:16.337668 [Flow] Enable top DCM control >>>>>
3805 04:42:16.340940 [Flow] Enable top DCM control <<<<<
3806 04:42:16.344117 Enable DLL master slave shuffle
3807 04:42:16.351102 ==============================================================
3808 04:42:16.353952 Gating Mode config
3809 04:42:16.357497 ==============================================================
3810 04:42:16.360542 Config description:
3811 04:42:16.370918 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3812 04:42:16.377528 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3813 04:42:16.380742 SELPH_MODE 0: By rank 1: By Phase
3814 04:42:16.387481 ==============================================================
3815 04:42:16.390590 GAT_TRACK_EN = 1
3816 04:42:16.393991 RX_GATING_MODE = 2
3817 04:42:16.394076 RX_GATING_TRACK_MODE = 2
3818 04:42:16.397544 SELPH_MODE = 1
3819 04:42:16.400843 PICG_EARLY_EN = 1
3820 04:42:16.403936 VALID_LAT_VALUE = 1
3821 04:42:16.410840 ==============================================================
3822 04:42:16.414153 Enter into Gating configuration >>>>
3823 04:42:16.417416 Exit from Gating configuration <<<<
3824 04:42:16.420985 Enter into DVFS_PRE_config >>>>>
3825 04:42:16.431002 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3826 04:42:16.433996 Exit from DVFS_PRE_config <<<<<
3827 04:42:16.437542 Enter into PICG configuration >>>>
3828 04:42:16.440933 Exit from PICG configuration <<<<
3829 04:42:16.444236 [RX_INPUT] configuration >>>>>
3830 04:42:16.447631 [RX_INPUT] configuration <<<<<
3831 04:42:16.450754 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3832 04:42:16.457515 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3833 04:42:16.464031 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3834 04:42:16.467615 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3835 04:42:16.473932 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3836 04:42:16.480836 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3837 04:42:16.484198 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3838 04:42:16.490621 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3839 04:42:16.493993 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3840 04:42:16.497366 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3841 04:42:16.500827 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3842 04:42:16.507102 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3843 04:42:16.510585 ===================================
3844 04:42:16.510669 LPDDR4 DRAM CONFIGURATION
3845 04:42:16.514011 ===================================
3846 04:42:16.516990 EX_ROW_EN[0] = 0x0
3847 04:42:16.520452 EX_ROW_EN[1] = 0x0
3848 04:42:16.520536 LP4Y_EN = 0x0
3849 04:42:16.524044 WORK_FSP = 0x0
3850 04:42:16.524127 WL = 0x2
3851 04:42:16.527517 RL = 0x2
3852 04:42:16.527601 BL = 0x2
3853 04:42:16.530450 RPST = 0x0
3854 04:42:16.530534 RD_PRE = 0x0
3855 04:42:16.534113 WR_PRE = 0x1
3856 04:42:16.534196 WR_PST = 0x0
3857 04:42:16.537539 DBI_WR = 0x0
3858 04:42:16.537622 DBI_RD = 0x0
3859 04:42:16.540531 OTF = 0x1
3860 04:42:16.544079 ===================================
3861 04:42:16.547364 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3862 04:42:16.550751 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3863 04:42:16.557068 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3864 04:42:16.560342 ===================================
3865 04:42:16.560425 LPDDR4 DRAM CONFIGURATION
3866 04:42:16.563845 ===================================
3867 04:42:16.567265 EX_ROW_EN[0] = 0x10
3868 04:42:16.567348 EX_ROW_EN[1] = 0x0
3869 04:42:16.570646 LP4Y_EN = 0x0
3870 04:42:16.570729 WORK_FSP = 0x0
3871 04:42:16.573708 WL = 0x2
3872 04:42:16.573782 RL = 0x2
3873 04:42:16.577077 BL = 0x2
3874 04:42:16.580375 RPST = 0x0
3875 04:42:16.580448 RD_PRE = 0x0
3876 04:42:16.583530 WR_PRE = 0x1
3877 04:42:16.583611 WR_PST = 0x0
3878 04:42:16.587257 DBI_WR = 0x0
3879 04:42:16.587337 DBI_RD = 0x0
3880 04:42:16.590630 OTF = 0x1
3881 04:42:16.593914 ===================================
3882 04:42:16.597280 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3883 04:42:16.602399 nWR fixed to 30
3884 04:42:16.605618 [ModeRegInit_LP4] CH0 RK0
3885 04:42:16.605696 [ModeRegInit_LP4] CH0 RK1
3886 04:42:16.609481 [ModeRegInit_LP4] CH1 RK0
3887 04:42:16.612431 [ModeRegInit_LP4] CH1 RK1
3888 04:42:16.612509 match AC timing 17
3889 04:42:16.618977 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3890 04:42:16.622260 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3891 04:42:16.625769 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3892 04:42:16.632258 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3893 04:42:16.635380 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3894 04:42:16.635460 ==
3895 04:42:16.638792 Dram Type= 6, Freq= 0, CH_0, rank 0
3896 04:42:16.642274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3897 04:42:16.642354 ==
3898 04:42:16.648682 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3899 04:42:16.655178 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3900 04:42:16.658671 [CA 0] Center 36 (5~67) winsize 63
3901 04:42:16.661977 [CA 1] Center 36 (6~67) winsize 62
3902 04:42:16.665392 [CA 2] Center 34 (4~65) winsize 62
3903 04:42:16.668488 [CA 3] Center 34 (3~65) winsize 63
3904 04:42:16.671966 [CA 4] Center 33 (3~64) winsize 62
3905 04:42:16.675412 [CA 5] Center 33 (3~64) winsize 62
3906 04:42:16.675486
3907 04:42:16.678526 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3908 04:42:16.678600
3909 04:42:16.681908 [CATrainingPosCal] consider 1 rank data
3910 04:42:16.685259 u2DelayCellTimex100 = 270/100 ps
3911 04:42:16.688526 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3912 04:42:16.691832 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3913 04:42:16.695294 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3914 04:42:16.698506 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3915 04:42:16.705255 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3916 04:42:16.708420 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3917 04:42:16.708502
3918 04:42:16.711747 CA PerBit enable=1, Macro0, CA PI delay=33
3919 04:42:16.711827
3920 04:42:16.715206 [CBTSetCACLKResult] CA Dly = 33
3921 04:42:16.715281 CS Dly: 6 (0~37)
3922 04:42:16.715352 ==
3923 04:42:16.718206 Dram Type= 6, Freq= 0, CH_0, rank 1
3924 04:42:16.724998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3925 04:42:16.725075 ==
3926 04:42:16.728071 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3927 04:42:16.734943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3928 04:42:16.738069 [CA 0] Center 36 (6~67) winsize 62
3929 04:42:16.741531 [CA 1] Center 36 (6~67) winsize 62
3930 04:42:16.745012 [CA 2] Center 35 (5~66) winsize 62
3931 04:42:16.747938 [CA 3] Center 34 (4~65) winsize 62
3932 04:42:16.751425 [CA 4] Center 34 (3~65) winsize 63
3933 04:42:16.754765 [CA 5] Center 34 (4~65) winsize 62
3934 04:42:16.754838
3935 04:42:16.758143 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3936 04:42:16.758217
3937 04:42:16.761398 [CATrainingPosCal] consider 2 rank data
3938 04:42:16.764639 u2DelayCellTimex100 = 270/100 ps
3939 04:42:16.768014 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3940 04:42:16.771098 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3941 04:42:16.778121 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3942 04:42:16.781125 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3943 04:42:16.784499 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3944 04:42:16.787795 CA5 delay=34 (4~64),Diff = 1 PI (9 cell)
3945 04:42:16.787894
3946 04:42:16.791158 CA PerBit enable=1, Macro0, CA PI delay=33
3947 04:42:16.791232
3948 04:42:16.794353 [CBTSetCACLKResult] CA Dly = 33
3949 04:42:16.794425 CS Dly: 6 (0~37)
3950 04:42:16.794485
3951 04:42:16.798076 ----->DramcWriteLeveling(PI) begin...
3952 04:42:16.800926 ==
3953 04:42:16.804263 Dram Type= 6, Freq= 0, CH_0, rank 0
3954 04:42:16.807569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 04:42:16.807640 ==
3956 04:42:16.811143 Write leveling (Byte 0): 33 => 33
3957 04:42:16.814562 Write leveling (Byte 1): 29 => 29
3958 04:42:16.817348 DramcWriteLeveling(PI) end<-----
3959 04:42:16.817449
3960 04:42:16.817540 ==
3961 04:42:16.820883 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 04:42:16.824280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 04:42:16.824354 ==
3964 04:42:16.827754 [Gating] SW mode calibration
3965 04:42:16.834107 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3966 04:42:16.840972 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3967 04:42:16.844448 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3968 04:42:16.847465 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3969 04:42:16.854253 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3970 04:42:16.857158 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
3971 04:42:16.860660 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
3972 04:42:16.867189 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 04:42:16.870733 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 04:42:16.874116 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 04:42:16.880551 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 04:42:16.884033 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 04:42:16.887066 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3978 04:42:16.890332 0 10 12 | B1->B0 | 2929 3e3e | 0 1 | (0 0) (0 0)
3979 04:42:16.897337 0 10 16 | B1->B0 | 3f3e 4646 | 1 0 | (1 1) (0 0)
3980 04:42:16.900566 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 04:42:16.904036 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 04:42:16.910360 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 04:42:16.914148 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 04:42:16.917226 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 04:42:16.923881 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 04:42:16.926981 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3987 04:42:16.930397 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3988 04:42:16.937266 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 04:42:16.940141 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 04:42:16.943618 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 04:42:16.950009 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 04:42:16.953575 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 04:42:16.957054 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 04:42:16.963476 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 04:42:16.966799 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 04:42:16.970088 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 04:42:16.976940 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 04:42:16.980037 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 04:42:16.983506 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 04:42:16.990376 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 04:42:16.993732 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 04:42:16.996999 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4003 04:42:17.003380 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4004 04:42:17.003463 Total UI for P1: 0, mck2ui 16
4005 04:42:17.010136 best dqsien dly found for B0: ( 0, 13, 12)
4006 04:42:17.013519 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 04:42:17.016714 Total UI for P1: 0, mck2ui 16
4008 04:42:17.020059 best dqsien dly found for B1: ( 0, 13, 16)
4009 04:42:17.023476 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4010 04:42:17.026776 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4011 04:42:17.026859
4012 04:42:17.029863 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4013 04:42:17.033295 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4014 04:42:17.036748 [Gating] SW calibration Done
4015 04:42:17.036830 ==
4016 04:42:17.040172 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 04:42:17.043523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 04:42:17.043638 ==
4019 04:42:17.046507 RX Vref Scan: 0
4020 04:42:17.046590
4021 04:42:17.049947 RX Vref 0 -> 0, step: 1
4022 04:42:17.050044
4023 04:42:17.050127 RX Delay -230 -> 252, step: 16
4024 04:42:17.056884 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4025 04:42:17.060278 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4026 04:42:17.063364 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4027 04:42:17.066794 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4028 04:42:17.073579 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4029 04:42:17.076879 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4030 04:42:17.080259 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4031 04:42:17.083227 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4032 04:42:17.086707 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4033 04:42:17.093201 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4034 04:42:17.096618 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4035 04:42:17.099940 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4036 04:42:17.103251 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4037 04:42:17.109884 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4038 04:42:17.113269 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4039 04:42:17.116476 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4040 04:42:17.116561 ==
4041 04:42:17.119988 Dram Type= 6, Freq= 0, CH_0, rank 0
4042 04:42:17.123268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4043 04:42:17.126648 ==
4044 04:42:17.126740 DQS Delay:
4045 04:42:17.126807 DQS0 = 0, DQS1 = 0
4046 04:42:17.129879 DQM Delay:
4047 04:42:17.129993 DQM0 = 51, DQM1 = 42
4048 04:42:17.133413 DQ Delay:
4049 04:42:17.136477 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4050 04:42:17.136558 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4051 04:42:17.140080 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4052 04:42:17.142967 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4053 04:42:17.146467
4054 04:42:17.146544
4055 04:42:17.146606 ==
4056 04:42:17.149455 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 04:42:17.153017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 04:42:17.153091 ==
4059 04:42:17.153152
4060 04:42:17.153218
4061 04:42:17.156443 TX Vref Scan disable
4062 04:42:17.156513 == TX Byte 0 ==
4063 04:42:17.162807 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4064 04:42:17.166170 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4065 04:42:17.166245 == TX Byte 1 ==
4066 04:42:17.173035 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4067 04:42:17.176392 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4068 04:42:17.176466 ==
4069 04:42:17.179684 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 04:42:17.182996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 04:42:17.183070 ==
4072 04:42:17.183133
4073 04:42:17.183191
4074 04:42:17.186417 TX Vref Scan disable
4075 04:42:17.189897 == TX Byte 0 ==
4076 04:42:17.192838 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4077 04:42:17.196375 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4078 04:42:17.199521 == TX Byte 1 ==
4079 04:42:17.202827 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4080 04:42:17.206168 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4081 04:42:17.209472
4082 04:42:17.209545 [DATLAT]
4083 04:42:17.209614 Freq=600, CH0 RK0
4084 04:42:17.209675
4085 04:42:17.212779 DATLAT Default: 0x9
4086 04:42:17.212861 0, 0xFFFF, sum = 0
4087 04:42:17.216007 1, 0xFFFF, sum = 0
4088 04:42:17.216080 2, 0xFFFF, sum = 0
4089 04:42:17.219383 3, 0xFFFF, sum = 0
4090 04:42:17.219456 4, 0xFFFF, sum = 0
4091 04:42:17.222937 5, 0xFFFF, sum = 0
4092 04:42:17.223011 6, 0xFFFF, sum = 0
4093 04:42:17.226004 7, 0xFFFF, sum = 0
4094 04:42:17.226077 8, 0x0, sum = 1
4095 04:42:17.229431 9, 0x0, sum = 2
4096 04:42:17.229505 10, 0x0, sum = 3
4097 04:42:17.232613 11, 0x0, sum = 4
4098 04:42:17.232699 best_step = 9
4099 04:42:17.232766
4100 04:42:17.232825 ==
4101 04:42:17.235932 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 04:42:17.243073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 04:42:17.243160 ==
4104 04:42:17.243226 RX Vref Scan: 1
4105 04:42:17.243286
4106 04:42:17.245821 RX Vref 0 -> 0, step: 1
4107 04:42:17.245903
4108 04:42:17.249525 RX Delay -163 -> 252, step: 8
4109 04:42:17.249608
4110 04:42:17.252528 Set Vref, RX VrefLevel [Byte0]: 59
4111 04:42:17.255988 [Byte1]: 48
4112 04:42:17.256073
4113 04:42:17.259505 Final RX Vref Byte 0 = 59 to rank0
4114 04:42:17.263001 Final RX Vref Byte 1 = 48 to rank0
4115 04:42:17.266337 Final RX Vref Byte 0 = 59 to rank1
4116 04:42:17.269242 Final RX Vref Byte 1 = 48 to rank1==
4117 04:42:17.272828 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 04:42:17.276237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 04:42:17.276320 ==
4120 04:42:17.279554 DQS Delay:
4121 04:42:17.279636 DQS0 = 0, DQS1 = 0
4122 04:42:17.279701 DQM Delay:
4123 04:42:17.282877 DQM0 = 48, DQM1 = 39
4124 04:42:17.282959 DQ Delay:
4125 04:42:17.286202 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4126 04:42:17.289523 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4127 04:42:17.292943 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4128 04:42:17.295987 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4129 04:42:17.296072
4130 04:42:17.296136
4131 04:42:17.305979 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e57, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4132 04:42:17.306063 CH0 RK0: MR19=808, MR18=5E57
4133 04:42:17.312900 CH0_RK0: MR19=0x808, MR18=0x5E57, DQSOSC=392, MR23=63, INC=170, DEC=113
4134 04:42:17.312983
4135 04:42:17.316158 ----->DramcWriteLeveling(PI) begin...
4136 04:42:17.316241 ==
4137 04:42:17.319311 Dram Type= 6, Freq= 0, CH_0, rank 1
4138 04:42:17.325904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 04:42:17.326025 ==
4140 04:42:17.329277 Write leveling (Byte 0): 35 => 35
4141 04:42:17.332749 Write leveling (Byte 1): 31 => 31
4142 04:42:17.332831 DramcWriteLeveling(PI) end<-----
4143 04:42:17.332896
4144 04:42:17.335927 ==
4145 04:42:17.339308 Dram Type= 6, Freq= 0, CH_0, rank 1
4146 04:42:17.342697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 04:42:17.342780 ==
4148 04:42:17.346118 [Gating] SW mode calibration
4149 04:42:17.352642 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4150 04:42:17.356028 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4151 04:42:17.362534 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4152 04:42:17.365985 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4153 04:42:17.369036 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4154 04:42:17.375554 0 9 12 | B1->B0 | 3030 3131 | 0 0 | (0 0) (0 0)
4155 04:42:17.378994 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
4156 04:42:17.382238 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 04:42:17.388976 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 04:42:17.392199 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 04:42:17.395620 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 04:42:17.402221 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 04:42:17.405568 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 04:42:17.409207 0 10 12 | B1->B0 | 3030 2f2f | 0 1 | (0 0) (0 0)
4163 04:42:17.415800 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4164 04:42:17.418591 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 04:42:17.422190 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 04:42:17.428870 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 04:42:17.432123 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 04:42:17.435373 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 04:42:17.442007 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 04:42:17.445425 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4171 04:42:17.448461 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 04:42:17.455160 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 04:42:17.458556 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 04:42:17.462034 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 04:42:17.468557 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 04:42:17.471909 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 04:42:17.474971 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 04:42:17.481997 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 04:42:17.485435 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 04:42:17.488738 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 04:42:17.491712 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 04:42:17.498423 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 04:42:17.501930 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 04:42:17.505471 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 04:42:17.511776 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 04:42:17.515190 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 04:42:17.518386 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 04:42:17.522152 Total UI for P1: 0, mck2ui 16
4189 04:42:17.525417 best dqsien dly found for B0: ( 0, 13, 14)
4190 04:42:17.528600 Total UI for P1: 0, mck2ui 16
4191 04:42:17.532043 best dqsien dly found for B1: ( 0, 13, 14)
4192 04:42:17.535012 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4193 04:42:17.538764 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4194 04:42:17.538854
4195 04:42:17.545409 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4196 04:42:17.548826 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4197 04:42:17.551834 [Gating] SW calibration Done
4198 04:42:17.551918 ==
4199 04:42:17.555347 Dram Type= 6, Freq= 0, CH_0, rank 1
4200 04:42:17.558748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 04:42:17.558831 ==
4202 04:42:17.558896 RX Vref Scan: 0
4203 04:42:17.558956
4204 04:42:17.562299 RX Vref 0 -> 0, step: 1
4205 04:42:17.562382
4206 04:42:17.565250 RX Delay -230 -> 252, step: 16
4207 04:42:17.568836 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4208 04:42:17.571733 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4209 04:42:17.578580 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4210 04:42:17.582092 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4211 04:42:17.585046 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4212 04:42:17.588539 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4213 04:42:17.591864 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4214 04:42:17.598438 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4215 04:42:17.601779 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4216 04:42:17.605283 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4217 04:42:17.608669 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4218 04:42:17.615067 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4219 04:42:17.618403 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4220 04:42:17.621791 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4221 04:42:17.624912 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4222 04:42:17.631476 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4223 04:42:17.631575 ==
4224 04:42:17.635108 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 04:42:17.638581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 04:42:17.638671 ==
4227 04:42:17.638739 DQS Delay:
4228 04:42:17.641836 DQS0 = 0, DQS1 = 0
4229 04:42:17.641919 DQM Delay:
4230 04:42:17.645132 DQM0 = 47, DQM1 = 41
4231 04:42:17.645219 DQ Delay:
4232 04:42:17.648316 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4233 04:42:17.651644 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =57
4234 04:42:17.654625 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4235 04:42:17.658135 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4236 04:42:17.658223
4237 04:42:17.658290
4238 04:42:17.658350 ==
4239 04:42:17.661659 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 04:42:17.664582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 04:42:17.664667 ==
4242 04:42:17.667989
4243 04:42:17.668072
4244 04:42:17.668138 TX Vref Scan disable
4245 04:42:17.671467 == TX Byte 0 ==
4246 04:42:17.674955 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4247 04:42:17.677944 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4248 04:42:17.681484 == TX Byte 1 ==
4249 04:42:17.684937 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4250 04:42:17.687921 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4251 04:42:17.691490 ==
4252 04:42:17.691574 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 04:42:17.698225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 04:42:17.698310 ==
4255 04:42:17.698377
4256 04:42:17.698437
4257 04:42:17.698543 TX Vref Scan disable
4258 04:42:17.702927 == TX Byte 0 ==
4259 04:42:17.706261 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4260 04:42:17.712667 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4261 04:42:17.712769 == TX Byte 1 ==
4262 04:42:17.716159 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4263 04:42:17.722608 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4264 04:42:17.722691
4265 04:42:17.722757 [DATLAT]
4266 04:42:17.722817 Freq=600, CH0 RK1
4267 04:42:17.722877
4268 04:42:17.725860 DATLAT Default: 0x9
4269 04:42:17.725965 0, 0xFFFF, sum = 0
4270 04:42:17.729184 1, 0xFFFF, sum = 0
4271 04:42:17.732510 2, 0xFFFF, sum = 0
4272 04:42:17.732610 3, 0xFFFF, sum = 0
4273 04:42:17.735852 4, 0xFFFF, sum = 0
4274 04:42:17.735964 5, 0xFFFF, sum = 0
4275 04:42:17.739093 6, 0xFFFF, sum = 0
4276 04:42:17.739184 7, 0xFFFF, sum = 0
4277 04:42:17.742493 8, 0x0, sum = 1
4278 04:42:17.742578 9, 0x0, sum = 2
4279 04:42:17.742644 10, 0x0, sum = 3
4280 04:42:17.745715 11, 0x0, sum = 4
4281 04:42:17.745799 best_step = 9
4282 04:42:17.745865
4283 04:42:17.745926 ==
4284 04:42:17.749234 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 04:42:17.755623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 04:42:17.755724 ==
4287 04:42:17.755792 RX Vref Scan: 0
4288 04:42:17.755855
4289 04:42:17.759031 RX Vref 0 -> 0, step: 1
4290 04:42:17.759119
4291 04:42:17.762462 RX Delay -179 -> 252, step: 8
4292 04:42:17.765770 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4293 04:42:17.772303 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4294 04:42:17.775740 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4295 04:42:17.778693 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4296 04:42:17.782201 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4297 04:42:17.785635 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4298 04:42:17.792178 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4299 04:42:17.795507 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4300 04:42:17.798842 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4301 04:42:17.802285 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4302 04:42:17.808458 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4303 04:42:17.811931 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4304 04:42:17.815408 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4305 04:42:17.818484 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4306 04:42:17.821843 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4307 04:42:17.828702 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4308 04:42:17.828785 ==
4309 04:42:17.831971 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 04:42:17.835175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 04:42:17.835257 ==
4312 04:42:17.835321 DQS Delay:
4313 04:42:17.838572 DQS0 = 0, DQS1 = 0
4314 04:42:17.838653 DQM Delay:
4315 04:42:17.841739 DQM0 = 47, DQM1 = 40
4316 04:42:17.841819 DQ Delay:
4317 04:42:17.845265 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4318 04:42:17.848510 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =52
4319 04:42:17.851901 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32
4320 04:42:17.855056 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4321 04:42:17.855138
4322 04:42:17.855202
4323 04:42:17.865229 [DQSOSCAuto] RK1, (LSB)MR18= 0x6432, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4324 04:42:17.865312 CH0 RK1: MR19=808, MR18=6432
4325 04:42:17.871741 CH0_RK1: MR19=0x808, MR18=0x6432, DQSOSC=391, MR23=63, INC=171, DEC=114
4326 04:42:17.874989 [RxdqsGatingPostProcess] freq 600
4327 04:42:17.881769 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4328 04:42:17.885211 Pre-setting of DQS Precalculation
4329 04:42:17.888234 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4330 04:42:17.888325 ==
4331 04:42:17.891836 Dram Type= 6, Freq= 0, CH_1, rank 0
4332 04:42:17.894821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 04:42:17.898269 ==
4334 04:42:17.901664 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4335 04:42:17.908268 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4336 04:42:17.911688 [CA 0] Center 35 (5~66) winsize 62
4337 04:42:17.915019 [CA 1] Center 35 (5~66) winsize 62
4338 04:42:17.917967 [CA 2] Center 34 (4~64) winsize 61
4339 04:42:17.921408 [CA 3] Center 33 (3~64) winsize 62
4340 04:42:17.924944 [CA 4] Center 34 (3~65) winsize 63
4341 04:42:17.928424 [CA 5] Center 33 (3~64) winsize 62
4342 04:42:17.928521
4343 04:42:17.931395 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4344 04:42:17.931476
4345 04:42:17.935009 [CATrainingPosCal] consider 1 rank data
4346 04:42:17.938382 u2DelayCellTimex100 = 270/100 ps
4347 04:42:17.941558 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4348 04:42:17.944850 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4349 04:42:17.948236 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4350 04:42:17.951722 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4351 04:42:17.957988 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4352 04:42:17.961611 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4353 04:42:17.961720
4354 04:42:17.964526 CA PerBit enable=1, Macro0, CA PI delay=33
4355 04:42:17.964614
4356 04:42:17.967899 [CBTSetCACLKResult] CA Dly = 33
4357 04:42:17.968040 CS Dly: 4 (0~35)
4358 04:42:17.968164 ==
4359 04:42:17.971522 Dram Type= 6, Freq= 0, CH_1, rank 1
4360 04:42:17.974994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 04:42:17.978022 ==
4362 04:42:17.981303 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4363 04:42:17.987809 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4364 04:42:17.991292 [CA 0] Center 35 (5~66) winsize 62
4365 04:42:17.994783 [CA 1] Center 35 (5~66) winsize 62
4366 04:42:17.998248 [CA 2] Center 34 (4~65) winsize 62
4367 04:42:18.001277 [CA 3] Center 34 (4~65) winsize 62
4368 04:42:18.004775 [CA 4] Center 34 (4~64) winsize 61
4369 04:42:18.008021 [CA 5] Center 33 (3~64) winsize 62
4370 04:42:18.008102
4371 04:42:18.011380 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4372 04:42:18.011462
4373 04:42:18.014758 [CATrainingPosCal] consider 2 rank data
4374 04:42:18.018069 u2DelayCellTimex100 = 270/100 ps
4375 04:42:18.021035 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4376 04:42:18.024560 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4377 04:42:18.028128 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4378 04:42:18.034539 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4379 04:42:18.037831 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4380 04:42:18.041232 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4381 04:42:18.041315
4382 04:42:18.044446 CA PerBit enable=1, Macro0, CA PI delay=33
4383 04:42:18.044529
4384 04:42:18.047755 [CBTSetCACLKResult] CA Dly = 33
4385 04:42:18.047838 CS Dly: 5 (0~37)
4386 04:42:18.047904
4387 04:42:18.050979 ----->DramcWriteLeveling(PI) begin...
4388 04:42:18.051063 ==
4389 04:42:18.054358 Dram Type= 6, Freq= 0, CH_1, rank 0
4390 04:42:18.060989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 04:42:18.061073 ==
4392 04:42:18.064243 Write leveling (Byte 0): 29 => 29
4393 04:42:18.067564 Write leveling (Byte 1): 29 => 29
4394 04:42:18.067647 DramcWriteLeveling(PI) end<-----
4395 04:42:18.071024
4396 04:42:18.071107 ==
4397 04:42:18.074445 Dram Type= 6, Freq= 0, CH_1, rank 0
4398 04:42:18.077498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 04:42:18.077581 ==
4400 04:42:18.080903 [Gating] SW mode calibration
4401 04:42:18.087676 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4402 04:42:18.090687 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4403 04:42:18.097657 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4404 04:42:18.100655 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4405 04:42:18.104168 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4406 04:42:18.110571 0 9 12 | B1->B0 | 2d2d 2b2b | 1 1 | (1 0) (1 0)
4407 04:42:18.113908 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 04:42:18.117712 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 04:42:18.123944 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 04:42:18.127573 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 04:42:18.130993 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 04:42:18.137480 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 04:42:18.140833 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4414 04:42:18.144156 0 10 12 | B1->B0 | 3939 4545 | 0 0 | (1 1) (0 0)
4415 04:42:18.150639 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 04:42:18.154352 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 04:42:18.157432 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 04:42:18.164075 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 04:42:18.167641 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 04:42:18.170859 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 04:42:18.177614 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4422 04:42:18.180634 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4423 04:42:18.184243 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 04:42:18.187428 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 04:42:18.194284 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 04:42:18.197203 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 04:42:18.200632 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 04:42:18.207545 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 04:42:18.210563 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 04:42:18.214092 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 04:42:18.220687 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 04:42:18.224073 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 04:42:18.227341 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 04:42:18.234170 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 04:42:18.237253 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 04:42:18.240568 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 04:42:18.247287 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 04:42:18.250640 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 04:42:18.253859 Total UI for P1: 0, mck2ui 16
4440 04:42:18.257235 best dqsien dly found for B0: ( 0, 13, 10)
4441 04:42:18.260518 Total UI for P1: 0, mck2ui 16
4442 04:42:18.263915 best dqsien dly found for B1: ( 0, 13, 10)
4443 04:42:18.267125 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4444 04:42:18.270506 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4445 04:42:18.270590
4446 04:42:18.273684 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4447 04:42:18.277476 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4448 04:42:18.280798 [Gating] SW calibration Done
4449 04:42:18.280881 ==
4450 04:42:18.283801 Dram Type= 6, Freq= 0, CH_1, rank 0
4451 04:42:18.287292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 04:42:18.290739 ==
4453 04:42:18.290822 RX Vref Scan: 0
4454 04:42:18.290887
4455 04:42:18.294227 RX Vref 0 -> 0, step: 1
4456 04:42:18.294310
4457 04:42:18.296999 RX Delay -230 -> 252, step: 16
4458 04:42:18.300571 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4459 04:42:18.303576 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4460 04:42:18.306951 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4461 04:42:18.313455 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4462 04:42:18.316921 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4463 04:42:18.320247 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4464 04:42:18.323511 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4465 04:42:18.326925 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4466 04:42:18.333620 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4467 04:42:18.336981 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4468 04:42:18.340472 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4469 04:42:18.343891 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4470 04:42:18.350452 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4471 04:42:18.353674 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4472 04:42:18.357041 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4473 04:42:18.360282 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4474 04:42:18.360365 ==
4475 04:42:18.363598 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 04:42:18.370229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 04:42:18.370312 ==
4478 04:42:18.370379 DQS Delay:
4479 04:42:18.373296 DQS0 = 0, DQS1 = 0
4480 04:42:18.373378 DQM Delay:
4481 04:42:18.373443 DQM0 = 49, DQM1 = 44
4482 04:42:18.376972 DQ Delay:
4483 04:42:18.380276 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4484 04:42:18.383523 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =49
4485 04:42:18.386955 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4486 04:42:18.389916 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =49
4487 04:42:18.390009
4488 04:42:18.390075
4489 04:42:18.390136 ==
4490 04:42:18.393434 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 04:42:18.396860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 04:42:18.396943 ==
4493 04:42:18.397009
4494 04:42:18.397068
4495 04:42:18.400229 TX Vref Scan disable
4496 04:42:18.400311 == TX Byte 0 ==
4497 04:42:18.406765 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4498 04:42:18.409784 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4499 04:42:18.409868 == TX Byte 1 ==
4500 04:42:18.416678 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4501 04:42:18.420265 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4502 04:42:18.420348 ==
4503 04:42:18.423483 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 04:42:18.426821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 04:42:18.426905 ==
4506 04:42:18.426970
4507 04:42:18.430091
4508 04:42:18.430173 TX Vref Scan disable
4509 04:42:18.433502 == TX Byte 0 ==
4510 04:42:18.436463 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4511 04:42:18.443503 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4512 04:42:18.443594 == TX Byte 1 ==
4513 04:42:18.446796 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4514 04:42:18.453154 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4515 04:42:18.453238
4516 04:42:18.453303 [DATLAT]
4517 04:42:18.453365 Freq=600, CH1 RK0
4518 04:42:18.453426
4519 04:42:18.456499 DATLAT Default: 0x9
4520 04:42:18.456582 0, 0xFFFF, sum = 0
4521 04:42:18.459867 1, 0xFFFF, sum = 0
4522 04:42:18.459952 2, 0xFFFF, sum = 0
4523 04:42:18.463130 3, 0xFFFF, sum = 0
4524 04:42:18.463214 4, 0xFFFF, sum = 0
4525 04:42:18.466394 5, 0xFFFF, sum = 0
4526 04:42:18.469888 6, 0xFFFF, sum = 0
4527 04:42:18.469999 7, 0xFFFF, sum = 0
4528 04:42:18.470069 8, 0x0, sum = 1
4529 04:42:18.473148 9, 0x0, sum = 2
4530 04:42:18.473232 10, 0x0, sum = 3
4531 04:42:18.476610 11, 0x0, sum = 4
4532 04:42:18.476695 best_step = 9
4533 04:42:18.476762
4534 04:42:18.476823 ==
4535 04:42:18.480096 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 04:42:18.486530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 04:42:18.486614 ==
4538 04:42:18.486681 RX Vref Scan: 1
4539 04:42:18.486742
4540 04:42:18.489917 RX Vref 0 -> 0, step: 1
4541 04:42:18.490041
4542 04:42:18.493347 RX Delay -179 -> 252, step: 8
4543 04:42:18.493431
4544 04:42:18.496829 Set Vref, RX VrefLevel [Byte0]: 53
4545 04:42:18.499875 [Byte1]: 53
4546 04:42:18.499959
4547 04:42:18.503260 Final RX Vref Byte 0 = 53 to rank0
4548 04:42:18.506691 Final RX Vref Byte 1 = 53 to rank0
4549 04:42:18.510228 Final RX Vref Byte 0 = 53 to rank1
4550 04:42:18.513104 Final RX Vref Byte 1 = 53 to rank1==
4551 04:42:18.516586 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 04:42:18.520055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 04:42:18.520140 ==
4554 04:42:18.523573 DQS Delay:
4555 04:42:18.523656 DQS0 = 0, DQS1 = 0
4556 04:42:18.523723 DQM Delay:
4557 04:42:18.526846 DQM0 = 47, DQM1 = 40
4558 04:42:18.526929 DQ Delay:
4559 04:42:18.530087 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4560 04:42:18.533483 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4561 04:42:18.536720 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4562 04:42:18.540061 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =48
4563 04:42:18.540145
4564 04:42:18.540210
4565 04:42:18.550219 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f77, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4566 04:42:18.550304 CH1 RK0: MR19=808, MR18=4F77
4567 04:42:18.556621 CH1_RK0: MR19=0x808, MR18=0x4F77, DQSOSC=387, MR23=63, INC=175, DEC=116
4568 04:42:18.556706
4569 04:42:18.560015 ----->DramcWriteLeveling(PI) begin...
4570 04:42:18.560100 ==
4571 04:42:18.563228 Dram Type= 6, Freq= 0, CH_1, rank 1
4572 04:42:18.569894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 04:42:18.569999 ==
4574 04:42:18.573249 Write leveling (Byte 0): 28 => 28
4575 04:42:18.576656 Write leveling (Byte 1): 29 => 29
4576 04:42:18.576740 DramcWriteLeveling(PI) end<-----
4577 04:42:18.579956
4578 04:42:18.580040 ==
4579 04:42:18.583488 Dram Type= 6, Freq= 0, CH_1, rank 1
4580 04:42:18.586714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 04:42:18.586798 ==
4582 04:42:18.589833 [Gating] SW mode calibration
4583 04:42:18.596595 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4584 04:42:18.600077 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4585 04:42:18.606504 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4586 04:42:18.610212 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4587 04:42:18.613451 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4588 04:42:18.620047 0 9 12 | B1->B0 | 2626 2f2f | 0 1 | (1 0) (1 0)
4589 04:42:18.622966 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 04:42:18.626529 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 04:42:18.633299 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 04:42:18.636578 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 04:42:18.639934 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 04:42:18.646246 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 04:42:18.649623 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 04:42:18.653100 0 10 12 | B1->B0 | 3f3f 3333 | 1 0 | (0 0) (0 0)
4597 04:42:18.659675 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 04:42:18.662980 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 04:42:18.666243 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 04:42:18.672830 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 04:42:18.676319 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 04:42:18.679741 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 04:42:18.686487 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 04:42:18.689851 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4605 04:42:18.693037 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 04:42:18.696402 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 04:42:18.702841 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 04:42:18.706361 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 04:42:18.709762 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 04:42:18.716685 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 04:42:18.719666 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 04:42:18.723285 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 04:42:18.729535 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 04:42:18.733150 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 04:42:18.736295 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 04:42:18.743222 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 04:42:18.746232 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 04:42:18.749340 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 04:42:18.756256 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 04:42:18.759547 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 04:42:18.762637 Total UI for P1: 0, mck2ui 16
4622 04:42:18.766058 best dqsien dly found for B0: ( 0, 13, 10)
4623 04:42:18.769347 Total UI for P1: 0, mck2ui 16
4624 04:42:18.772676 best dqsien dly found for B1: ( 0, 13, 10)
4625 04:42:18.775970 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4626 04:42:18.779144 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4627 04:42:18.779227
4628 04:42:18.782707 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4629 04:42:18.786040 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4630 04:42:18.789414 [Gating] SW calibration Done
4631 04:42:18.789498 ==
4632 04:42:18.792845 Dram Type= 6, Freq= 0, CH_1, rank 1
4633 04:42:18.796137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 04:42:18.799280 ==
4635 04:42:18.799364 RX Vref Scan: 0
4636 04:42:18.799431
4637 04:42:18.802640 RX Vref 0 -> 0, step: 1
4638 04:42:18.802723
4639 04:42:18.806192 RX Delay -230 -> 252, step: 16
4640 04:42:18.809139 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4641 04:42:18.812521 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4642 04:42:18.815974 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4643 04:42:18.822533 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4644 04:42:18.826051 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4645 04:42:18.828933 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4646 04:42:18.832374 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4647 04:42:18.835494 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4648 04:42:18.842589 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4649 04:42:18.845462 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4650 04:42:18.848843 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4651 04:42:18.852193 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4652 04:42:18.858836 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4653 04:42:18.862527 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4654 04:42:18.865906 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4655 04:42:18.868973 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4656 04:42:18.869057 ==
4657 04:42:18.872290 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 04:42:18.878857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 04:42:18.878942 ==
4660 04:42:18.879008 DQS Delay:
4661 04:42:18.879069 DQS0 = 0, DQS1 = 0
4662 04:42:18.882658 DQM Delay:
4663 04:42:18.882741 DQM0 = 51, DQM1 = 46
4664 04:42:18.886046 DQ Delay:
4665 04:42:18.889251 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4666 04:42:18.889340 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4667 04:42:18.892459 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4668 04:42:18.898825 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4669 04:42:18.898908
4670 04:42:18.898975
4671 04:42:18.899036 ==
4672 04:42:18.902182 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 04:42:18.905464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 04:42:18.905549 ==
4675 04:42:18.905616
4676 04:42:18.905678
4677 04:42:18.908915 TX Vref Scan disable
4678 04:42:18.908999 == TX Byte 0 ==
4679 04:42:18.915500 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4680 04:42:18.918876 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4681 04:42:18.918960 == TX Byte 1 ==
4682 04:42:18.925265 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4683 04:42:18.928715 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4684 04:42:18.928799 ==
4685 04:42:18.931733 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 04:42:18.935203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 04:42:18.935287 ==
4688 04:42:18.938770
4689 04:42:18.938857
4690 04:42:18.938923 TX Vref Scan disable
4691 04:42:18.942161 == TX Byte 0 ==
4692 04:42:18.945464 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4693 04:42:18.951815 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4694 04:42:18.951899 == TX Byte 1 ==
4695 04:42:18.955198 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4696 04:42:18.961981 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4697 04:42:18.962065
4698 04:42:18.962132 [DATLAT]
4699 04:42:18.962193 Freq=600, CH1 RK1
4700 04:42:18.962254
4701 04:42:18.964966 DATLAT Default: 0x9
4702 04:42:18.965049 0, 0xFFFF, sum = 0
4703 04:42:18.968398 1, 0xFFFF, sum = 0
4704 04:42:18.968484 2, 0xFFFF, sum = 0
4705 04:42:18.971988 3, 0xFFFF, sum = 0
4706 04:42:18.974928 4, 0xFFFF, sum = 0
4707 04:42:18.975013 5, 0xFFFF, sum = 0
4708 04:42:18.978666 6, 0xFFFF, sum = 0
4709 04:42:18.978751 7, 0xFFFF, sum = 0
4710 04:42:18.981851 8, 0x0, sum = 1
4711 04:42:18.981937 9, 0x0, sum = 2
4712 04:42:18.982014 10, 0x0, sum = 3
4713 04:42:18.985229 11, 0x0, sum = 4
4714 04:42:18.985315 best_step = 9
4715 04:42:18.985382
4716 04:42:18.985443 ==
4717 04:42:18.988539 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 04:42:18.994903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 04:42:18.994988 ==
4720 04:42:18.995055 RX Vref Scan: 0
4721 04:42:18.995117
4722 04:42:18.998257 RX Vref 0 -> 0, step: 1
4723 04:42:18.998341
4724 04:42:19.001599 RX Delay -163 -> 252, step: 8
4725 04:42:19.004876 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4726 04:42:19.011923 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4727 04:42:19.014988 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4728 04:42:19.018679 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4729 04:42:19.021666 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4730 04:42:19.024992 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4731 04:42:19.031604 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4732 04:42:19.035091 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4733 04:42:19.038600 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4734 04:42:19.041613 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4735 04:42:19.045088 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4736 04:42:19.051874 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4737 04:42:19.054822 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4738 04:42:19.058256 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4739 04:42:19.061641 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4740 04:42:19.068480 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4741 04:42:19.068567 ==
4742 04:42:19.071406 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 04:42:19.074981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 04:42:19.075065 ==
4745 04:42:19.075132 DQS Delay:
4746 04:42:19.078057 DQS0 = 0, DQS1 = 0
4747 04:42:19.078169 DQM Delay:
4748 04:42:19.081381 DQM0 = 48, DQM1 = 43
4749 04:42:19.081465 DQ Delay:
4750 04:42:19.084667 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4751 04:42:19.088362 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4752 04:42:19.091697 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4753 04:42:19.094604 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4754 04:42:19.094688
4755 04:42:19.094754
4756 04:42:19.101287 [DQSOSCAuto] RK1, (LSB)MR18= 0x5920, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
4757 04:42:19.104649 CH1 RK1: MR19=808, MR18=5920
4758 04:42:19.111219 CH1_RK1: MR19=0x808, MR18=0x5920, DQSOSC=393, MR23=63, INC=169, DEC=113
4759 04:42:19.114538 [RxdqsGatingPostProcess] freq 600
4760 04:42:19.121030 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4761 04:42:19.124569 Pre-setting of DQS Precalculation
4762 04:42:19.128012 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4763 04:42:19.134832 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4764 04:42:19.141291 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4765 04:42:19.141376
4766 04:42:19.141442
4767 04:42:19.144779 [Calibration Summary] 1200 Mbps
4768 04:42:19.147897 CH 0, Rank 0
4769 04:42:19.147982 SW Impedance : PASS
4770 04:42:19.151228 DUTY Scan : NO K
4771 04:42:19.154471 ZQ Calibration : PASS
4772 04:42:19.154554 Jitter Meter : NO K
4773 04:42:19.157867 CBT Training : PASS
4774 04:42:19.161049 Write leveling : PASS
4775 04:42:19.161147 RX DQS gating : PASS
4776 04:42:19.164348 RX DQ/DQS(RDDQC) : PASS
4777 04:42:19.164418 TX DQ/DQS : PASS
4778 04:42:19.168080 RX DATLAT : PASS
4779 04:42:19.171025 RX DQ/DQS(Engine): PASS
4780 04:42:19.171125 TX OE : NO K
4781 04:42:19.174473 All Pass.
4782 04:42:19.174545
4783 04:42:19.174607 CH 0, Rank 1
4784 04:42:19.177884 SW Impedance : PASS
4785 04:42:19.177986 DUTY Scan : NO K
4786 04:42:19.181271 ZQ Calibration : PASS
4787 04:42:19.184804 Jitter Meter : NO K
4788 04:42:19.184904 CBT Training : PASS
4789 04:42:19.187997 Write leveling : PASS
4790 04:42:19.191274 RX DQS gating : PASS
4791 04:42:19.191345 RX DQ/DQS(RDDQC) : PASS
4792 04:42:19.194498 TX DQ/DQS : PASS
4793 04:42:19.198102 RX DATLAT : PASS
4794 04:42:19.198175 RX DQ/DQS(Engine): PASS
4795 04:42:19.201189 TX OE : NO K
4796 04:42:19.201283 All Pass.
4797 04:42:19.201375
4798 04:42:19.204295 CH 1, Rank 0
4799 04:42:19.204388 SW Impedance : PASS
4800 04:42:19.207737 DUTY Scan : NO K
4801 04:42:19.207832 ZQ Calibration : PASS
4802 04:42:19.210976 Jitter Meter : NO K
4803 04:42:19.214694 CBT Training : PASS
4804 04:42:19.214800 Write leveling : PASS
4805 04:42:19.217913 RX DQS gating : PASS
4806 04:42:19.221233 RX DQ/DQS(RDDQC) : PASS
4807 04:42:19.221335 TX DQ/DQS : PASS
4808 04:42:19.224362 RX DATLAT : PASS
4809 04:42:19.227799 RX DQ/DQS(Engine): PASS
4810 04:42:19.227898 TX OE : NO K
4811 04:42:19.230792 All Pass.
4812 04:42:19.230866
4813 04:42:19.230929 CH 1, Rank 1
4814 04:42:19.234053 SW Impedance : PASS
4815 04:42:19.234157 DUTY Scan : NO K
4816 04:42:19.237511 ZQ Calibration : PASS
4817 04:42:19.240945 Jitter Meter : NO K
4818 04:42:19.241051 CBT Training : PASS
4819 04:42:19.244524 Write leveling : PASS
4820 04:42:19.247540 RX DQS gating : PASS
4821 04:42:19.247645 RX DQ/DQS(RDDQC) : PASS
4822 04:42:19.251069 TX DQ/DQS : PASS
4823 04:42:19.251169 RX DATLAT : PASS
4824 04:42:19.254551 RX DQ/DQS(Engine): PASS
4825 04:42:19.257806 TX OE : NO K
4826 04:42:19.257910 All Pass.
4827 04:42:19.258024
4828 04:42:19.261146 DramC Write-DBI off
4829 04:42:19.261254 PER_BANK_REFRESH: Hybrid Mode
4830 04:42:19.264312 TX_TRACKING: ON
4831 04:42:19.274480 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4832 04:42:19.277416 [FAST_K] Save calibration result to emmc
4833 04:42:19.281040 dramc_set_vcore_voltage set vcore to 662500
4834 04:42:19.281150 Read voltage for 933, 3
4835 04:42:19.284479 Vio18 = 0
4836 04:42:19.284554 Vcore = 662500
4837 04:42:19.284617 Vdram = 0
4838 04:42:19.287410 Vddq = 0
4839 04:42:19.287507 Vmddr = 0
4840 04:42:19.294351 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4841 04:42:19.297561 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4842 04:42:19.300702 MEM_TYPE=3, freq_sel=17
4843 04:42:19.304211 sv_algorithm_assistance_LP4_1600
4844 04:42:19.307522 ============ PULL DRAM RESETB DOWN ============
4845 04:42:19.310753 ========== PULL DRAM RESETB DOWN end =========
4846 04:42:19.317354 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4847 04:42:19.320595 ===================================
4848 04:42:19.320698 LPDDR4 DRAM CONFIGURATION
4849 04:42:19.323977 ===================================
4850 04:42:19.327479 EX_ROW_EN[0] = 0x0
4851 04:42:19.327578 EX_ROW_EN[1] = 0x0
4852 04:42:19.330958 LP4Y_EN = 0x0
4853 04:42:19.333933 WORK_FSP = 0x0
4854 04:42:19.334074 WL = 0x3
4855 04:42:19.337436 RL = 0x3
4856 04:42:19.337533 BL = 0x2
4857 04:42:19.340900 RPST = 0x0
4858 04:42:19.340999 RD_PRE = 0x0
4859 04:42:19.344297 WR_PRE = 0x1
4860 04:42:19.344394 WR_PST = 0x0
4861 04:42:19.347255 DBI_WR = 0x0
4862 04:42:19.347351 DBI_RD = 0x0
4863 04:42:19.350728 OTF = 0x1
4864 04:42:19.354200 ===================================
4865 04:42:19.357261 ===================================
4866 04:42:19.357358 ANA top config
4867 04:42:19.360530 ===================================
4868 04:42:19.363901 DLL_ASYNC_EN = 0
4869 04:42:19.367195 ALL_SLAVE_EN = 1
4870 04:42:19.367281 NEW_RANK_MODE = 1
4871 04:42:19.370515 DLL_IDLE_MODE = 1
4872 04:42:19.373846 LP45_APHY_COMB_EN = 1
4873 04:42:19.377179 TX_ODT_DIS = 1
4874 04:42:19.380635 NEW_8X_MODE = 1
4875 04:42:19.380731 ===================================
4876 04:42:19.384072 ===================================
4877 04:42:19.387049 data_rate = 1866
4878 04:42:19.390540 CKR = 1
4879 04:42:19.393827 DQ_P2S_RATIO = 8
4880 04:42:19.397177 ===================================
4881 04:42:19.400396 CA_P2S_RATIO = 8
4882 04:42:19.403715 DQ_CA_OPEN = 0
4883 04:42:19.407099 DQ_SEMI_OPEN = 0
4884 04:42:19.407201 CA_SEMI_OPEN = 0
4885 04:42:19.410629 CA_FULL_RATE = 0
4886 04:42:19.413823 DQ_CKDIV4_EN = 1
4887 04:42:19.417291 CA_CKDIV4_EN = 1
4888 04:42:19.420157 CA_PREDIV_EN = 0
4889 04:42:19.423844 PH8_DLY = 0
4890 04:42:19.423953 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4891 04:42:19.427114 DQ_AAMCK_DIV = 4
4892 04:42:19.430542 CA_AAMCK_DIV = 4
4893 04:42:19.433540 CA_ADMCK_DIV = 4
4894 04:42:19.437029 DQ_TRACK_CA_EN = 0
4895 04:42:19.440476 CA_PICK = 933
4896 04:42:19.440550 CA_MCKIO = 933
4897 04:42:19.443751 MCKIO_SEMI = 0
4898 04:42:19.447283 PLL_FREQ = 3732
4899 04:42:19.450167 DQ_UI_PI_RATIO = 32
4900 04:42:19.453605 CA_UI_PI_RATIO = 0
4901 04:42:19.457183 ===================================
4902 04:42:19.460684 ===================================
4903 04:42:19.463678 memory_type:LPDDR4
4904 04:42:19.463782 GP_NUM : 10
4905 04:42:19.467313 SRAM_EN : 1
4906 04:42:19.467398 MD32_EN : 0
4907 04:42:19.470260 ===================================
4908 04:42:19.473630 [ANA_INIT] >>>>>>>>>>>>>>
4909 04:42:19.476884 <<<<<< [CONFIGURE PHASE]: ANA_TX
4910 04:42:19.480625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4911 04:42:19.483565 ===================================
4912 04:42:19.487232 data_rate = 1866,PCW = 0X8f00
4913 04:42:19.490565 ===================================
4914 04:42:19.493710 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4915 04:42:19.496737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4916 04:42:19.503257 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4917 04:42:19.507031 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4918 04:42:19.513361 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4919 04:42:19.517051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4920 04:42:19.517155 [ANA_INIT] flow start
4921 04:42:19.520314 [ANA_INIT] PLL >>>>>>>>
4922 04:42:19.523773 [ANA_INIT] PLL <<<<<<<<
4923 04:42:19.523872 [ANA_INIT] MIDPI >>>>>>>>
4924 04:42:19.527003 [ANA_INIT] MIDPI <<<<<<<<
4925 04:42:19.530507 [ANA_INIT] DLL >>>>>>>>
4926 04:42:19.530608 [ANA_INIT] flow end
4927 04:42:19.533475 ============ LP4 DIFF to SE enter ============
4928 04:42:19.540361 ============ LP4 DIFF to SE exit ============
4929 04:42:19.540469 [ANA_INIT] <<<<<<<<<<<<<
4930 04:42:19.543830 [Flow] Enable top DCM control >>>>>
4931 04:42:19.547021 [Flow] Enable top DCM control <<<<<
4932 04:42:19.550117 Enable DLL master slave shuffle
4933 04:42:19.556587 ==============================================================
4934 04:42:19.556688 Gating Mode config
4935 04:42:19.563490 ==============================================================
4936 04:42:19.567064 Config description:
4937 04:42:19.576971 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4938 04:42:19.583292 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4939 04:42:19.586647 SELPH_MODE 0: By rank 1: By Phase
4940 04:42:19.593696 ==============================================================
4941 04:42:19.596554 GAT_TRACK_EN = 1
4942 04:42:19.599999 RX_GATING_MODE = 2
4943 04:42:19.600083 RX_GATING_TRACK_MODE = 2
4944 04:42:19.603194 SELPH_MODE = 1
4945 04:42:19.606409 PICG_EARLY_EN = 1
4946 04:42:19.609746 VALID_LAT_VALUE = 1
4947 04:42:19.616855 ==============================================================
4948 04:42:19.620156 Enter into Gating configuration >>>>
4949 04:42:19.623442 Exit from Gating configuration <<<<
4950 04:42:19.626771 Enter into DVFS_PRE_config >>>>>
4951 04:42:19.636890 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4952 04:42:19.639700 Exit from DVFS_PRE_config <<<<<
4953 04:42:19.643180 Enter into PICG configuration >>>>
4954 04:42:19.646624 Exit from PICG configuration <<<<
4955 04:42:19.649982 [RX_INPUT] configuration >>>>>
4956 04:42:19.652991 [RX_INPUT] configuration <<<<<
4957 04:42:19.656553 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4958 04:42:19.663047 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4959 04:42:19.669523 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4960 04:42:19.676388 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4961 04:42:19.679700 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4962 04:42:19.686164 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4963 04:42:19.689477 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4964 04:42:19.696394 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4965 04:42:19.699339 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4966 04:42:19.702748 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4967 04:42:19.706048 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4968 04:42:19.712680 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4969 04:42:19.715964 ===================================
4970 04:42:19.716048 LPDDR4 DRAM CONFIGURATION
4971 04:42:19.719315 ===================================
4972 04:42:19.722809 EX_ROW_EN[0] = 0x0
4973 04:42:19.726005 EX_ROW_EN[1] = 0x0
4974 04:42:19.726088 LP4Y_EN = 0x0
4975 04:42:19.729656 WORK_FSP = 0x0
4976 04:42:19.729739 WL = 0x3
4977 04:42:19.732938 RL = 0x3
4978 04:42:19.733022 BL = 0x2
4979 04:42:19.736246 RPST = 0x0
4980 04:42:19.736329 RD_PRE = 0x0
4981 04:42:19.739625 WR_PRE = 0x1
4982 04:42:19.739709 WR_PST = 0x0
4983 04:42:19.743072 DBI_WR = 0x0
4984 04:42:19.743155 DBI_RD = 0x0
4985 04:42:19.746142 OTF = 0x1
4986 04:42:19.749564 ===================================
4987 04:42:19.752870 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4988 04:42:19.756249 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4989 04:42:19.762605 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4990 04:42:19.765726 ===================================
4991 04:42:19.765813 LPDDR4 DRAM CONFIGURATION
4992 04:42:19.769159 ===================================
4993 04:42:19.772724 EX_ROW_EN[0] = 0x10
4994 04:42:19.776245 EX_ROW_EN[1] = 0x0
4995 04:42:19.776329 LP4Y_EN = 0x0
4996 04:42:19.779571 WORK_FSP = 0x0
4997 04:42:19.779655 WL = 0x3
4998 04:42:19.782480 RL = 0x3
4999 04:42:19.782563 BL = 0x2
5000 04:42:19.785753 RPST = 0x0
5001 04:42:19.785837 RD_PRE = 0x0
5002 04:42:19.789374 WR_PRE = 0x1
5003 04:42:19.789458 WR_PST = 0x0
5004 04:42:19.792682 DBI_WR = 0x0
5005 04:42:19.792766 DBI_RD = 0x0
5006 04:42:19.795724 OTF = 0x1
5007 04:42:19.799118 ===================================
5008 04:42:19.805656 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5009 04:42:19.808930 nWR fixed to 30
5010 04:42:19.809015 [ModeRegInit_LP4] CH0 RK0
5011 04:42:19.812239 [ModeRegInit_LP4] CH0 RK1
5012 04:42:19.815583 [ModeRegInit_LP4] CH1 RK0
5013 04:42:19.818878 [ModeRegInit_LP4] CH1 RK1
5014 04:42:19.818962 match AC timing 9
5015 04:42:19.822571 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5016 04:42:19.825465 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5017 04:42:19.832116 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5018 04:42:19.835681 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5019 04:42:19.842376 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5020 04:42:19.842461 ==
5021 04:42:19.845770 Dram Type= 6, Freq= 0, CH_0, rank 0
5022 04:42:19.848733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5023 04:42:19.848818 ==
5024 04:42:19.855791 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5025 04:42:19.859196 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5026 04:42:19.863600 [CA 0] Center 38 (7~69) winsize 63
5027 04:42:19.867084 [CA 1] Center 38 (8~69) winsize 62
5028 04:42:19.870035 [CA 2] Center 35 (5~66) winsize 62
5029 04:42:19.873513 [CA 3] Center 35 (4~66) winsize 63
5030 04:42:19.876993 [CA 4] Center 34 (4~65) winsize 62
5031 04:42:19.880485 [CA 5] Center 33 (3~64) winsize 62
5032 04:42:19.880570
5033 04:42:19.883739 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5034 04:42:19.883823
5035 04:42:19.886991 [CATrainingPosCal] consider 1 rank data
5036 04:42:19.889982 u2DelayCellTimex100 = 270/100 ps
5037 04:42:19.893728 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5038 04:42:19.897161 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5039 04:42:19.903596 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5040 04:42:19.907035 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5041 04:42:19.910070 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5042 04:42:19.913558 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5043 04:42:19.913646
5044 04:42:19.916808 CA PerBit enable=1, Macro0, CA PI delay=33
5045 04:42:19.916893
5046 04:42:19.920059 [CBTSetCACLKResult] CA Dly = 33
5047 04:42:19.920143 CS Dly: 7 (0~38)
5048 04:42:19.923389 ==
5049 04:42:19.926370 Dram Type= 6, Freq= 0, CH_0, rank 1
5050 04:42:19.929744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5051 04:42:19.929829 ==
5052 04:42:19.933139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5053 04:42:19.939799 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5054 04:42:19.943460 [CA 0] Center 38 (8~69) winsize 62
5055 04:42:19.946875 [CA 1] Center 38 (8~69) winsize 62
5056 04:42:19.950255 [CA 2] Center 36 (6~66) winsize 61
5057 04:42:19.953879 [CA 3] Center 35 (5~66) winsize 62
5058 04:42:19.956803 [CA 4] Center 34 (4~65) winsize 62
5059 04:42:19.960301 [CA 5] Center 34 (4~65) winsize 62
5060 04:42:19.960385
5061 04:42:19.963861 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5062 04:42:19.963946
5063 04:42:19.966679 [CATrainingPosCal] consider 2 rank data
5064 04:42:19.970286 u2DelayCellTimex100 = 270/100 ps
5065 04:42:19.973717 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5066 04:42:19.976661 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5067 04:42:19.983707 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5068 04:42:19.987081 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5069 04:42:19.990352 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5070 04:42:19.993557 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5071 04:42:19.993641
5072 04:42:19.996996 CA PerBit enable=1, Macro0, CA PI delay=34
5073 04:42:19.997081
5074 04:42:20.000414 [CBTSetCACLKResult] CA Dly = 34
5075 04:42:20.000498 CS Dly: 7 (0~39)
5076 04:42:20.000565
5077 04:42:20.003779 ----->DramcWriteLeveling(PI) begin...
5078 04:42:20.006670 ==
5079 04:42:20.010194 Dram Type= 6, Freq= 0, CH_0, rank 0
5080 04:42:20.013701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5081 04:42:20.013784 ==
5082 04:42:20.016650 Write leveling (Byte 0): 33 => 33
5083 04:42:20.020001 Write leveling (Byte 1): 27 => 27
5084 04:42:20.023379 DramcWriteLeveling(PI) end<-----
5085 04:42:20.023464
5086 04:42:20.023528 ==
5087 04:42:20.027017 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 04:42:20.030342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 04:42:20.030445 ==
5090 04:42:20.033579 [Gating] SW mode calibration
5091 04:42:20.040182 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5092 04:42:20.046956 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5093 04:42:20.049875 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
5094 04:42:20.053542 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 04:42:20.056560 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 04:42:20.063426 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 04:42:20.066867 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 04:42:20.070063 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 04:42:20.076498 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 0)
5100 04:42:20.080053 0 14 28 | B1->B0 | 3131 2424 | 0 0 | (1 0) (0 0)
5101 04:42:20.083495 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5102 04:42:20.089914 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 04:42:20.093345 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 04:42:20.096681 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 04:42:20.103319 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 04:42:20.106776 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 04:42:20.110232 0 15 24 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
5108 04:42:20.116719 0 15 28 | B1->B0 | 2f2f 4545 | 0 0 | (0 0) (0 0)
5109 04:42:20.120115 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5110 04:42:20.123526 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 04:42:20.130066 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 04:42:20.133360 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 04:42:20.136428 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 04:42:20.143339 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 04:42:20.146691 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5116 04:42:20.149981 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5117 04:42:20.156629 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 04:42:20.159645 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 04:42:20.163314 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 04:42:20.166414 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 04:42:20.173193 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 04:42:20.176663 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 04:42:20.180120 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 04:42:20.186471 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 04:42:20.190014 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 04:42:20.193026 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 04:42:20.199802 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 04:42:20.202980 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 04:42:20.206400 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 04:42:20.213108 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 04:42:20.216614 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5132 04:42:20.219563 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5133 04:42:20.223003 Total UI for P1: 0, mck2ui 16
5134 04:42:20.226418 best dqsien dly found for B0: ( 1, 2, 24)
5135 04:42:20.233091 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 04:42:20.233174 Total UI for P1: 0, mck2ui 16
5137 04:42:20.239441 best dqsien dly found for B1: ( 1, 2, 28)
5138 04:42:20.242850 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5139 04:42:20.246158 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5140 04:42:20.246241
5141 04:42:20.249658 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5142 04:42:20.252910 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5143 04:42:20.256212 [Gating] SW calibration Done
5144 04:42:20.256295 ==
5145 04:42:20.260019 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 04:42:20.262960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 04:42:20.263043 ==
5148 04:42:20.266504 RX Vref Scan: 0
5149 04:42:20.266586
5150 04:42:20.266651 RX Vref 0 -> 0, step: 1
5151 04:42:20.266711
5152 04:42:20.269532 RX Delay -80 -> 252, step: 8
5153 04:42:20.272892 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5154 04:42:20.279694 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5155 04:42:20.282742 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5156 04:42:20.286210 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5157 04:42:20.289623 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5158 04:42:20.292657 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5159 04:42:20.296244 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5160 04:42:20.302910 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5161 04:42:20.306287 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5162 04:42:20.309667 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5163 04:42:20.312836 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5164 04:42:20.316367 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5165 04:42:20.319733 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5166 04:42:20.326171 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5167 04:42:20.329573 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5168 04:42:20.332972 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5169 04:42:20.333055 ==
5170 04:42:20.335913 Dram Type= 6, Freq= 0, CH_0, rank 0
5171 04:42:20.339470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5172 04:42:20.339554 ==
5173 04:42:20.342746 DQS Delay:
5174 04:42:20.342828 DQS0 = 0, DQS1 = 0
5175 04:42:20.342894 DQM Delay:
5176 04:42:20.346048 DQM0 = 105, DQM1 = 90
5177 04:42:20.346130 DQ Delay:
5178 04:42:20.349596 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5179 04:42:20.352880 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5180 04:42:20.356280 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5181 04:42:20.359664 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5182 04:42:20.359747
5183 04:42:20.359813
5184 04:42:20.363008 ==
5185 04:42:20.366326 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 04:42:20.369279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 04:42:20.369362 ==
5188 04:42:20.369427
5189 04:42:20.369508
5190 04:42:20.372795 TX Vref Scan disable
5191 04:42:20.372877 == TX Byte 0 ==
5192 04:42:20.379687 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5193 04:42:20.382589 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5194 04:42:20.382671 == TX Byte 1 ==
5195 04:42:20.389582 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5196 04:42:20.392499 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5197 04:42:20.392583 ==
5198 04:42:20.396000 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 04:42:20.399453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 04:42:20.399535 ==
5201 04:42:20.399601
5202 04:42:20.399664
5203 04:42:20.402577 TX Vref Scan disable
5204 04:42:20.405836 == TX Byte 0 ==
5205 04:42:20.409550 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5206 04:42:20.412576 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5207 04:42:20.415901 == TX Byte 1 ==
5208 04:42:20.419204 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5209 04:42:20.422710 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5210 04:42:20.422792
5211 04:42:20.425710 [DATLAT]
5212 04:42:20.425792 Freq=933, CH0 RK0
5213 04:42:20.425858
5214 04:42:20.429293 DATLAT Default: 0xd
5215 04:42:20.429376 0, 0xFFFF, sum = 0
5216 04:42:20.432318 1, 0xFFFF, sum = 0
5217 04:42:20.432402 2, 0xFFFF, sum = 0
5218 04:42:20.435707 3, 0xFFFF, sum = 0
5219 04:42:20.435791 4, 0xFFFF, sum = 0
5220 04:42:20.439515 5, 0xFFFF, sum = 0
5221 04:42:20.439600 6, 0xFFFF, sum = 0
5222 04:42:20.442289 7, 0xFFFF, sum = 0
5223 04:42:20.442374 8, 0xFFFF, sum = 0
5224 04:42:20.446063 9, 0xFFFF, sum = 0
5225 04:42:20.446148 10, 0x0, sum = 1
5226 04:42:20.449336 11, 0x0, sum = 2
5227 04:42:20.449420 12, 0x0, sum = 3
5228 04:42:20.452779 13, 0x0, sum = 4
5229 04:42:20.452862 best_step = 11
5230 04:42:20.452927
5231 04:42:20.452986 ==
5232 04:42:20.455985 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 04:42:20.458977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 04:42:20.462583 ==
5235 04:42:20.462665 RX Vref Scan: 1
5236 04:42:20.462731
5237 04:42:20.465900 RX Vref 0 -> 0, step: 1
5238 04:42:20.466000
5239 04:42:20.469266 RX Delay -53 -> 252, step: 4
5240 04:42:20.469348
5241 04:42:20.472363 Set Vref, RX VrefLevel [Byte0]: 59
5242 04:42:20.472448 [Byte1]: 48
5243 04:42:20.477306
5244 04:42:20.477388 Final RX Vref Byte 0 = 59 to rank0
5245 04:42:20.480736 Final RX Vref Byte 1 = 48 to rank0
5246 04:42:20.484021 Final RX Vref Byte 0 = 59 to rank1
5247 04:42:20.487471 Final RX Vref Byte 1 = 48 to rank1==
5248 04:42:20.490951 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 04:42:20.497517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 04:42:20.497600 ==
5251 04:42:20.497665 DQS Delay:
5252 04:42:20.497726 DQS0 = 0, DQS1 = 0
5253 04:42:20.500866 DQM Delay:
5254 04:42:20.500949 DQM0 = 107, DQM1 = 92
5255 04:42:20.504404 DQ Delay:
5256 04:42:20.507382 DQ0 =106, DQ1 =108, DQ2 =102, DQ3 =106
5257 04:42:20.510607 DQ4 =108, DQ5 =98, DQ6 =118, DQ7 =116
5258 04:42:20.513930 DQ8 =88, DQ9 =78, DQ10 =90, DQ11 =90
5259 04:42:20.517137 DQ12 =94, DQ13 =94, DQ14 =102, DQ15 =100
5260 04:42:20.517211
5261 04:42:20.517273
5262 04:42:20.524035 [DQSOSCAuto] RK0, (LSB)MR18= 0x2925, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
5263 04:42:20.527435 CH0 RK0: MR19=505, MR18=2925
5264 04:42:20.534148 CH0_RK0: MR19=0x505, MR18=0x2925, DQSOSC=408, MR23=63, INC=65, DEC=43
5265 04:42:20.534231
5266 04:42:20.537087 ----->DramcWriteLeveling(PI) begin...
5267 04:42:20.537171 ==
5268 04:42:20.540532 Dram Type= 6, Freq= 0, CH_0, rank 1
5269 04:42:20.543775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 04:42:20.543858 ==
5271 04:42:20.547404 Write leveling (Byte 0): 33 => 33
5272 04:42:20.550256 Write leveling (Byte 1): 30 => 30
5273 04:42:20.554089 DramcWriteLeveling(PI) end<-----
5274 04:42:20.554172
5275 04:42:20.554237 ==
5276 04:42:20.557025 Dram Type= 6, Freq= 0, CH_0, rank 1
5277 04:42:20.563588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 04:42:20.563672 ==
5279 04:42:20.563737 [Gating] SW mode calibration
5280 04:42:20.573521 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5281 04:42:20.576959 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5282 04:42:20.580533 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5283 04:42:20.587066 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 04:42:20.590287 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 04:42:20.593794 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 04:42:20.600144 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 04:42:20.603715 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 04:42:20.606568 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5289 04:42:20.613534 0 14 28 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
5290 04:42:20.616473 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5291 04:42:20.620224 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 04:42:20.626391 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 04:42:20.629735 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 04:42:20.633222 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 04:42:20.639838 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 04:42:20.643363 0 15 24 | B1->B0 | 2929 2727 | 0 0 | (0 0) (0 0)
5297 04:42:20.646519 0 15 28 | B1->B0 | 3736 3d3d | 1 0 | (0 0) (0 0)
5298 04:42:20.653027 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 04:42:20.656341 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 04:42:20.660201 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 04:42:20.666462 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 04:42:20.669814 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 04:42:20.673137 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 04:42:20.679884 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 04:42:20.683518 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 04:42:20.686468 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 04:42:20.693388 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 04:42:20.696620 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 04:42:20.700026 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 04:42:20.702967 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 04:42:20.709967 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 04:42:20.712997 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 04:42:20.716413 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 04:42:20.722943 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 04:42:20.726335 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 04:42:20.730012 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 04:42:20.736349 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 04:42:20.739739 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 04:42:20.743164 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 04:42:20.749849 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 04:42:20.753158 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5322 04:42:20.756471 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5323 04:42:20.759701 Total UI for P1: 0, mck2ui 16
5324 04:42:20.763122 best dqsien dly found for B1: ( 1, 2, 28)
5325 04:42:20.769901 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 04:42:20.769988 Total UI for P1: 0, mck2ui 16
5327 04:42:20.776702 best dqsien dly found for B0: ( 1, 2, 30)
5328 04:42:20.779529 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5329 04:42:20.782971 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5330 04:42:20.783051
5331 04:42:20.786420 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5332 04:42:20.789851 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5333 04:42:20.792984 [Gating] SW calibration Done
5334 04:42:20.793065 ==
5335 04:42:20.796284 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 04:42:20.799832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 04:42:20.799913 ==
5338 04:42:20.802801 RX Vref Scan: 0
5339 04:42:20.802882
5340 04:42:20.802945 RX Vref 0 -> 0, step: 1
5341 04:42:20.803004
5342 04:42:20.806256 RX Delay -80 -> 252, step: 8
5343 04:42:20.809815 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5344 04:42:20.816351 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5345 04:42:20.819719 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5346 04:42:20.822891 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5347 04:42:20.826241 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5348 04:42:20.829584 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5349 04:42:20.832944 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5350 04:42:20.839868 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5351 04:42:20.842888 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5352 04:42:20.846370 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5353 04:42:20.849975 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5354 04:42:20.852885 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5355 04:42:20.856241 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5356 04:42:20.862810 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5357 04:42:20.866581 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5358 04:42:20.869873 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5359 04:42:20.869961 ==
5360 04:42:20.873095 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 04:42:20.876061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 04:42:20.876143 ==
5363 04:42:20.879721 DQS Delay:
5364 04:42:20.879801 DQS0 = 0, DQS1 = 0
5365 04:42:20.879866 DQM Delay:
5366 04:42:20.883134 DQM0 = 105, DQM1 = 89
5367 04:42:20.883216 DQ Delay:
5368 04:42:20.886524 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5369 04:42:20.889513 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5370 04:42:20.893071 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5371 04:42:20.895958 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5372 04:42:20.896065
5373 04:42:20.896158
5374 04:42:20.899511 ==
5375 04:42:20.902708 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 04:42:20.906143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 04:42:20.906226 ==
5378 04:42:20.906292
5379 04:42:20.906353
5380 04:42:20.909216 TX Vref Scan disable
5381 04:42:20.909298 == TX Byte 0 ==
5382 04:42:20.916112 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5383 04:42:20.919536 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5384 04:42:20.919640 == TX Byte 1 ==
5385 04:42:20.925880 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5386 04:42:20.929140 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5387 04:42:20.929223 ==
5388 04:42:20.932592 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 04:42:20.935776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 04:42:20.935858 ==
5391 04:42:20.935923
5392 04:42:20.935983
5393 04:42:20.939304 TX Vref Scan disable
5394 04:42:20.942303 == TX Byte 0 ==
5395 04:42:20.945769 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5396 04:42:20.949339 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5397 04:42:20.952303 == TX Byte 1 ==
5398 04:42:20.955641 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5399 04:42:20.958993 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5400 04:42:20.959075
5401 04:42:20.962370 [DATLAT]
5402 04:42:20.962452 Freq=933, CH0 RK1
5403 04:42:20.962518
5404 04:42:20.965683 DATLAT Default: 0xb
5405 04:42:20.965765 0, 0xFFFF, sum = 0
5406 04:42:20.969517 1, 0xFFFF, sum = 0
5407 04:42:20.969600 2, 0xFFFF, sum = 0
5408 04:42:20.972338 3, 0xFFFF, sum = 0
5409 04:42:20.972422 4, 0xFFFF, sum = 0
5410 04:42:20.976000 5, 0xFFFF, sum = 0
5411 04:42:20.976084 6, 0xFFFF, sum = 0
5412 04:42:20.978995 7, 0xFFFF, sum = 0
5413 04:42:20.979080 8, 0xFFFF, sum = 0
5414 04:42:20.982354 9, 0xFFFF, sum = 0
5415 04:42:20.982437 10, 0x0, sum = 1
5416 04:42:20.985696 11, 0x0, sum = 2
5417 04:42:20.985779 12, 0x0, sum = 3
5418 04:42:20.989077 13, 0x0, sum = 4
5419 04:42:20.989161 best_step = 11
5420 04:42:20.989226
5421 04:42:20.989286 ==
5422 04:42:20.992433 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 04:42:20.996005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 04:42:20.999469 ==
5425 04:42:20.999551 RX Vref Scan: 0
5426 04:42:20.999616
5427 04:42:21.002665 RX Vref 0 -> 0, step: 1
5428 04:42:21.002748
5429 04:42:21.005762 RX Delay -53 -> 252, step: 4
5430 04:42:21.009037 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5431 04:42:21.012478 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5432 04:42:21.018994 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5433 04:42:21.022492 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5434 04:42:21.025422 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5435 04:42:21.028847 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5436 04:42:21.032211 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5437 04:42:21.035534 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5438 04:42:21.042205 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5439 04:42:21.045537 iDelay=199, Bit 9, Center 78 (-5 ~ 162) 168
5440 04:42:21.049014 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5441 04:42:21.052477 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5442 04:42:21.055523 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5443 04:42:21.062821 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5444 04:42:21.065716 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5445 04:42:21.068897 iDelay=199, Bit 15, Center 96 (11 ~ 182) 172
5446 04:42:21.068980 ==
5447 04:42:21.072441 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 04:42:21.075738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 04:42:21.075821 ==
5450 04:42:21.078952 DQS Delay:
5451 04:42:21.079035 DQS0 = 0, DQS1 = 0
5452 04:42:21.082212 DQM Delay:
5453 04:42:21.082294 DQM0 = 103, DQM1 = 91
5454 04:42:21.082360 DQ Delay:
5455 04:42:21.085583 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5456 04:42:21.088850 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5457 04:42:21.092237 DQ8 =84, DQ9 =78, DQ10 =94, DQ11 =92
5458 04:42:21.095676 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =96
5459 04:42:21.098542
5460 04:42:21.098624
5461 04:42:21.105535 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5462 04:42:21.108965 CH0 RK1: MR19=505, MR18=2C0D
5463 04:42:21.115198 CH0_RK1: MR19=0x505, MR18=0x2C0D, DQSOSC=408, MR23=63, INC=65, DEC=43
5464 04:42:21.118741 [RxdqsGatingPostProcess] freq 933
5465 04:42:21.121660 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5466 04:42:21.125269 best DQS0 dly(2T, 0.5T) = (0, 10)
5467 04:42:21.128225 best DQS1 dly(2T, 0.5T) = (0, 10)
5468 04:42:21.131656 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5469 04:42:21.135064 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5470 04:42:21.138327 best DQS0 dly(2T, 0.5T) = (0, 10)
5471 04:42:21.141638 best DQS1 dly(2T, 0.5T) = (0, 10)
5472 04:42:21.145083 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5473 04:42:21.147982 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5474 04:42:21.151395 Pre-setting of DQS Precalculation
5475 04:42:21.154984 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5476 04:42:21.155068 ==
5477 04:42:21.158368 Dram Type= 6, Freq= 0, CH_1, rank 0
5478 04:42:21.164917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 04:42:21.165001 ==
5480 04:42:21.168170 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5481 04:42:21.174817 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5482 04:42:21.178102 [CA 0] Center 37 (7~68) winsize 62
5483 04:42:21.181714 [CA 1] Center 37 (7~68) winsize 62
5484 04:42:21.184940 [CA 2] Center 35 (5~65) winsize 61
5485 04:42:21.188269 [CA 3] Center 35 (5~65) winsize 61
5486 04:42:21.191583 [CA 4] Center 35 (5~65) winsize 61
5487 04:42:21.195015 [CA 5] Center 34 (4~65) winsize 62
5488 04:42:21.195099
5489 04:42:21.198174 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5490 04:42:21.198258
5491 04:42:21.202060 [CATrainingPosCal] consider 1 rank data
5492 04:42:21.205086 u2DelayCellTimex100 = 270/100 ps
5493 04:42:21.208029 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5494 04:42:21.211588 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5495 04:42:21.218136 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5496 04:42:21.221398 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5497 04:42:21.224366 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5498 04:42:21.227955 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5499 04:42:21.228039
5500 04:42:21.231396 CA PerBit enable=1, Macro0, CA PI delay=34
5501 04:42:21.231480
5502 04:42:21.234385 [CBTSetCACLKResult] CA Dly = 34
5503 04:42:21.234469 CS Dly: 6 (0~37)
5504 04:42:21.234535 ==
5505 04:42:21.237769 Dram Type= 6, Freq= 0, CH_1, rank 1
5506 04:42:21.244525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 04:42:21.244618 ==
5508 04:42:21.247411 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5509 04:42:21.254157 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5510 04:42:21.257658 [CA 0] Center 38 (8~68) winsize 61
5511 04:42:21.261068 [CA 1] Center 38 (8~69) winsize 62
5512 04:42:21.264590 [CA 2] Center 36 (6~66) winsize 61
5513 04:42:21.268090 [CA 3] Center 35 (5~65) winsize 61
5514 04:42:21.271091 [CA 4] Center 35 (5~65) winsize 61
5515 04:42:21.274168 [CA 5] Center 34 (5~64) winsize 60
5516 04:42:21.274252
5517 04:42:21.277867 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5518 04:42:21.278014
5519 04:42:21.281148 [CATrainingPosCal] consider 2 rank data
5520 04:42:21.284314 u2DelayCellTimex100 = 270/100 ps
5521 04:42:21.287725 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5522 04:42:21.294396 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5523 04:42:21.297752 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5524 04:42:21.301192 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5525 04:42:21.304468 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5526 04:42:21.307494 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5527 04:42:21.307579
5528 04:42:21.310970 CA PerBit enable=1, Macro0, CA PI delay=34
5529 04:42:21.311054
5530 04:42:21.314572 [CBTSetCACLKResult] CA Dly = 34
5531 04:42:21.314656 CS Dly: 7 (0~39)
5532 04:42:21.317428
5533 04:42:21.320885 ----->DramcWriteLeveling(PI) begin...
5534 04:42:21.320970 ==
5535 04:42:21.324257 Dram Type= 6, Freq= 0, CH_1, rank 0
5536 04:42:21.327741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 04:42:21.327826 ==
5538 04:42:21.330786 Write leveling (Byte 0): 27 => 27
5539 04:42:21.334247 Write leveling (Byte 1): 28 => 28
5540 04:42:21.337188 DramcWriteLeveling(PI) end<-----
5541 04:42:21.337272
5542 04:42:21.337338 ==
5543 04:42:21.340639 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 04:42:21.343994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 04:42:21.344079 ==
5546 04:42:21.347433 [Gating] SW mode calibration
5547 04:42:21.353930 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5548 04:42:21.360504 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5549 04:42:21.363980 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 04:42:21.367478 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 04:42:21.373899 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 04:42:21.377703 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 04:42:21.380963 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 04:42:21.387276 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5555 04:42:21.390804 0 14 24 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (1 0)
5556 04:42:21.394288 0 14 28 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
5557 04:42:21.397246 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 04:42:21.403978 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 04:42:21.407222 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 04:42:21.410640 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 04:42:21.417353 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 04:42:21.420429 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 04:42:21.424337 0 15 24 | B1->B0 | 2828 2929 | 0 0 | (0 0) (0 0)
5564 04:42:21.430645 0 15 28 | B1->B0 | 3e3e 4242 | 1 0 | (0 0) (0 0)
5565 04:42:21.433813 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 04:42:21.436978 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 04:42:21.443744 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 04:42:21.447150 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 04:42:21.450342 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 04:42:21.457023 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5571 04:42:21.460546 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5572 04:42:21.463390 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 04:42:21.470320 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 04:42:21.473886 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 04:42:21.476921 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 04:42:21.483565 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 04:42:21.486792 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 04:42:21.490241 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 04:42:21.496687 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 04:42:21.500096 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 04:42:21.503405 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 04:42:21.510182 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 04:42:21.513596 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 04:42:21.517039 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 04:42:21.523507 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 04:42:21.526998 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 04:42:21.530084 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5588 04:42:21.533398 Total UI for P1: 0, mck2ui 16
5589 04:42:21.536615 best dqsien dly found for B0: ( 1, 2, 22)
5590 04:42:21.539913 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 04:42:21.543357 Total UI for P1: 0, mck2ui 16
5592 04:42:21.546987 best dqsien dly found for B1: ( 1, 2, 24)
5593 04:42:21.550443 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5594 04:42:21.553283 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5595 04:42:21.556699
5596 04:42:21.560200 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5597 04:42:21.563411 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5598 04:42:21.566696 [Gating] SW calibration Done
5599 04:42:21.566795 ==
5600 04:42:21.570240 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 04:42:21.573209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 04:42:21.573293 ==
5603 04:42:21.573359 RX Vref Scan: 0
5604 04:42:21.576756
5605 04:42:21.576838 RX Vref 0 -> 0, step: 1
5606 04:42:21.576904
5607 04:42:21.580232 RX Delay -80 -> 252, step: 8
5608 04:42:21.583173 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5609 04:42:21.586505 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5610 04:42:21.593548 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5611 04:42:21.596846 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5612 04:42:21.600047 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5613 04:42:21.603431 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5614 04:42:21.606746 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5615 04:42:21.613609 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5616 04:42:21.616937 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5617 04:42:21.619953 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5618 04:42:21.623412 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5619 04:42:21.626898 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5620 04:42:21.629868 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5621 04:42:21.636823 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5622 04:42:21.640199 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5623 04:42:21.643315 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5624 04:42:21.643416 ==
5625 04:42:21.646727 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 04:42:21.650183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 04:42:21.650283 ==
5628 04:42:21.653176 DQS Delay:
5629 04:42:21.653274 DQS0 = 0, DQS1 = 0
5630 04:42:21.653373 DQM Delay:
5631 04:42:21.656439 DQM0 = 103, DQM1 = 96
5632 04:42:21.656535 DQ Delay:
5633 04:42:21.659831 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =103
5634 04:42:21.663196 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5635 04:42:21.666519 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5636 04:42:21.670197 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =103
5637 04:42:21.673656
5638 04:42:21.673732
5639 04:42:21.673795 ==
5640 04:42:21.676579 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 04:42:21.680064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 04:42:21.680163 ==
5643 04:42:21.680261
5644 04:42:21.680349
5645 04:42:21.683065 TX Vref Scan disable
5646 04:42:21.683148 == TX Byte 0 ==
5647 04:42:21.689748 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5648 04:42:21.693566 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5649 04:42:21.693644 == TX Byte 1 ==
5650 04:42:21.700144 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5651 04:42:21.703106 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5652 04:42:21.703186 ==
5653 04:42:21.706448 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 04:42:21.709717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 04:42:21.709805 ==
5656 04:42:21.709891
5657 04:42:21.710025
5658 04:42:21.713098 TX Vref Scan disable
5659 04:42:21.716626 == TX Byte 0 ==
5660 04:42:21.720023 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5661 04:42:21.723231 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5662 04:42:21.726285 == TX Byte 1 ==
5663 04:42:21.729791 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5664 04:42:21.733233 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5665 04:42:21.733319
5666 04:42:21.736215 [DATLAT]
5667 04:42:21.736301 Freq=933, CH1 RK0
5668 04:42:21.736387
5669 04:42:21.739701 DATLAT Default: 0xd
5670 04:42:21.739809 0, 0xFFFF, sum = 0
5671 04:42:21.742691 1, 0xFFFF, sum = 0
5672 04:42:21.742778 2, 0xFFFF, sum = 0
5673 04:42:21.746074 3, 0xFFFF, sum = 0
5674 04:42:21.746162 4, 0xFFFF, sum = 0
5675 04:42:21.749365 5, 0xFFFF, sum = 0
5676 04:42:21.749453 6, 0xFFFF, sum = 0
5677 04:42:21.752625 7, 0xFFFF, sum = 0
5678 04:42:21.752712 8, 0xFFFF, sum = 0
5679 04:42:21.756134 9, 0xFFFF, sum = 0
5680 04:42:21.756219 10, 0x0, sum = 1
5681 04:42:21.759207 11, 0x0, sum = 2
5682 04:42:21.759308 12, 0x0, sum = 3
5683 04:42:21.762563 13, 0x0, sum = 4
5684 04:42:21.762638 best_step = 11
5685 04:42:21.762701
5686 04:42:21.762759 ==
5687 04:42:21.765966 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 04:42:21.772649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 04:42:21.772732 ==
5690 04:42:21.772798 RX Vref Scan: 1
5691 04:42:21.772857
5692 04:42:21.775620 RX Vref 0 -> 0, step: 1
5693 04:42:21.775702
5694 04:42:21.779110 RX Delay -53 -> 252, step: 4
5695 04:42:21.779193
5696 04:42:21.782597 Set Vref, RX VrefLevel [Byte0]: 53
5697 04:42:21.785987 [Byte1]: 53
5698 04:42:21.786070
5699 04:42:21.789385 Final RX Vref Byte 0 = 53 to rank0
5700 04:42:21.792763 Final RX Vref Byte 1 = 53 to rank0
5701 04:42:21.796081 Final RX Vref Byte 0 = 53 to rank1
5702 04:42:21.799352 Final RX Vref Byte 1 = 53 to rank1==
5703 04:42:21.802690 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 04:42:21.806184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 04:42:21.806268 ==
5706 04:42:21.808994 DQS Delay:
5707 04:42:21.809076 DQS0 = 0, DQS1 = 0
5708 04:42:21.809142 DQM Delay:
5709 04:42:21.812379 DQM0 = 104, DQM1 = 96
5710 04:42:21.812461 DQ Delay:
5711 04:42:21.815687 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5712 04:42:21.819001 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =100
5713 04:42:21.822475 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =90
5714 04:42:21.829265 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =102
5715 04:42:21.829348
5716 04:42:21.829414
5717 04:42:21.835650 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5718 04:42:21.839012 CH1 RK0: MR19=505, MR18=1C35
5719 04:42:21.845487 CH1_RK0: MR19=0x505, MR18=0x1C35, DQSOSC=405, MR23=63, INC=66, DEC=44
5720 04:42:21.845571
5721 04:42:21.849078 ----->DramcWriteLeveling(PI) begin...
5722 04:42:21.849164 ==
5723 04:42:21.852087 Dram Type= 6, Freq= 0, CH_1, rank 1
5724 04:42:21.855533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 04:42:21.855617 ==
5726 04:42:21.858980 Write leveling (Byte 0): 25 => 25
5727 04:42:21.862530 Write leveling (Byte 1): 26 => 26
5728 04:42:21.865252 DramcWriteLeveling(PI) end<-----
5729 04:42:21.865335
5730 04:42:21.865401 ==
5731 04:42:21.869014 Dram Type= 6, Freq= 0, CH_1, rank 1
5732 04:42:21.871945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 04:42:21.872029 ==
5734 04:42:21.875206 [Gating] SW mode calibration
5735 04:42:21.882008 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5736 04:42:21.889143 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5737 04:42:21.891896 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5738 04:42:21.898719 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 04:42:21.901924 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 04:42:21.905351 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 04:42:21.908680 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 04:42:21.915287 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 04:42:21.918726 0 14 24 | B1->B0 | 2f2f 3131 | 0 1 | (0 0) (1 0)
5744 04:42:21.921801 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5745 04:42:21.928410 0 15 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
5746 04:42:21.931648 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 04:42:21.935273 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 04:42:21.941678 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 04:42:21.945273 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 04:42:21.948280 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 04:42:21.955046 0 15 24 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
5752 04:42:21.958523 0 15 28 | B1->B0 | 3a3a 3939 | 0 0 | (0 0) (1 1)
5753 04:42:21.961806 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 04:42:21.968284 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 04:42:21.971617 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 04:42:21.975013 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 04:42:21.981681 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 04:42:21.985143 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 04:42:21.988151 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5760 04:42:21.994829 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 04:42:21.998388 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 04:42:22.001632 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 04:42:22.008099 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 04:42:22.011578 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 04:42:22.015041 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 04:42:22.021481 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 04:42:22.024904 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 04:42:22.028331 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 04:42:22.034636 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 04:42:22.038098 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 04:42:22.041537 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 04:42:22.048067 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 04:42:22.051615 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 04:42:22.054571 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 04:42:22.061428 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5776 04:42:22.064749 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5777 04:42:22.067848 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 04:42:22.071182 Total UI for P1: 0, mck2ui 16
5779 04:42:22.074529 best dqsien dly found for B0: ( 1, 2, 26)
5780 04:42:22.077976 Total UI for P1: 0, mck2ui 16
5781 04:42:22.081322 best dqsien dly found for B1: ( 1, 2, 26)
5782 04:42:22.084274 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5783 04:42:22.088116 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5784 04:42:22.088201
5785 04:42:22.090997 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5786 04:42:22.097976 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5787 04:42:22.098060 [Gating] SW calibration Done
5788 04:42:22.098128 ==
5789 04:42:22.101007 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 04:42:22.107670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 04:42:22.107754 ==
5792 04:42:22.107821 RX Vref Scan: 0
5793 04:42:22.107884
5794 04:42:22.110926 RX Vref 0 -> 0, step: 1
5795 04:42:22.111010
5796 04:42:22.114465 RX Delay -80 -> 252, step: 8
5797 04:42:22.117722 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5798 04:42:22.121104 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5799 04:42:22.124427 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5800 04:42:22.127864 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5801 04:42:22.135271 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5802 04:42:22.137523 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5803 04:42:22.140901 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5804 04:42:22.144409 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5805 04:42:22.147911 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5806 04:42:22.150858 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5807 04:42:22.157474 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5808 04:42:22.160920 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5809 04:42:22.163970 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5810 04:42:22.167359 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5811 04:42:22.170929 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5812 04:42:22.177718 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5813 04:42:22.177804 ==
5814 04:42:22.181001 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 04:42:22.184338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 04:42:22.184422 ==
5817 04:42:22.184489 DQS Delay:
5818 04:42:22.187270 DQS0 = 0, DQS1 = 0
5819 04:42:22.187381 DQM Delay:
5820 04:42:22.190962 DQM0 = 101, DQM1 = 96
5821 04:42:22.191046 DQ Delay:
5822 04:42:22.194311 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5823 04:42:22.197228 DQ4 =103, DQ5 =115, DQ6 =107, DQ7 =99
5824 04:42:22.200698 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5825 04:42:22.204271 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5826 04:42:22.204355
5827 04:42:22.204422
5828 04:42:22.204483 ==
5829 04:42:22.207727 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 04:42:22.210617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 04:42:22.214379 ==
5832 04:42:22.214463
5833 04:42:22.214530
5834 04:42:22.214591 TX Vref Scan disable
5835 04:42:22.217179 == TX Byte 0 ==
5836 04:42:22.220874 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5837 04:42:22.223777 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5838 04:42:22.227186 == TX Byte 1 ==
5839 04:42:22.230464 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5840 04:42:22.233903 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5841 04:42:22.237135 ==
5842 04:42:22.240528 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 04:42:22.243844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 04:42:22.243944 ==
5845 04:42:22.244035
5846 04:42:22.244132
5847 04:42:22.247302 TX Vref Scan disable
5848 04:42:22.247399 == TX Byte 0 ==
5849 04:42:22.253785 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5850 04:42:22.257289 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5851 04:42:22.257390 == TX Byte 1 ==
5852 04:42:22.263637 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5853 04:42:22.267166 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5854 04:42:22.267242
5855 04:42:22.267305 [DATLAT]
5856 04:42:22.270500 Freq=933, CH1 RK1
5857 04:42:22.270584
5858 04:42:22.270673 DATLAT Default: 0xb
5859 04:42:22.274220 0, 0xFFFF, sum = 0
5860 04:42:22.274297 1, 0xFFFF, sum = 0
5861 04:42:22.277163 2, 0xFFFF, sum = 0
5862 04:42:22.277262 3, 0xFFFF, sum = 0
5863 04:42:22.280479 4, 0xFFFF, sum = 0
5864 04:42:22.280577 5, 0xFFFF, sum = 0
5865 04:42:22.283826 6, 0xFFFF, sum = 0
5866 04:42:22.283924 7, 0xFFFF, sum = 0
5867 04:42:22.287222 8, 0xFFFF, sum = 0
5868 04:42:22.287297 9, 0xFFFF, sum = 0
5869 04:42:22.290437 10, 0x0, sum = 1
5870 04:42:22.290534 11, 0x0, sum = 2
5871 04:42:22.293790 12, 0x0, sum = 3
5872 04:42:22.293887 13, 0x0, sum = 4
5873 04:42:22.297234 best_step = 11
5874 04:42:22.297330
5875 04:42:22.297425 ==
5876 04:42:22.300208 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 04:42:22.303730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 04:42:22.303835 ==
5879 04:42:22.307186 RX Vref Scan: 0
5880 04:42:22.307269
5881 04:42:22.307333 RX Vref 0 -> 0, step: 1
5882 04:42:22.307392
5883 04:42:22.310276 RX Delay -53 -> 252, step: 4
5884 04:42:22.317351 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5885 04:42:22.320921 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5886 04:42:22.324204 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5887 04:42:22.327566 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5888 04:42:22.330517 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5889 04:42:22.337223 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5890 04:42:22.340999 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5891 04:42:22.344244 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5892 04:42:22.347673 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5893 04:42:22.350697 iDelay=199, Bit 9, Center 90 (7 ~ 174) 168
5894 04:42:22.354096 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5895 04:42:22.360514 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5896 04:42:22.364068 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5897 04:42:22.367565 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5898 04:42:22.370522 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5899 04:42:22.377494 iDelay=199, Bit 15, Center 104 (15 ~ 194) 180
5900 04:42:22.377626 ==
5901 04:42:22.380563 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 04:42:22.383961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 04:42:22.384041 ==
5904 04:42:22.384118 DQS Delay:
5905 04:42:22.387231 DQS0 = 0, DQS1 = 0
5906 04:42:22.387308 DQM Delay:
5907 04:42:22.390724 DQM0 = 104, DQM1 = 97
5908 04:42:22.390797 DQ Delay:
5909 04:42:22.393908 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5910 04:42:22.397448 DQ4 =106, DQ5 =116, DQ6 =110, DQ7 =102
5911 04:42:22.400805 DQ8 =84, DQ9 =90, DQ10 =98, DQ11 =92
5912 04:42:22.403752 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =104
5913 04:42:22.403835
5914 04:42:22.403899
5915 04:42:22.413735 [DQSOSCAuto] RK1, (LSB)MR18= 0x2401, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
5916 04:42:22.413819 CH1 RK1: MR19=505, MR18=2401
5917 04:42:22.420880 CH1_RK1: MR19=0x505, MR18=0x2401, DQSOSC=410, MR23=63, INC=64, DEC=42
5918 04:42:22.424178 [RxdqsGatingPostProcess] freq 933
5919 04:42:22.430770 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5920 04:42:22.433741 best DQS0 dly(2T, 0.5T) = (0, 10)
5921 04:42:22.436916 best DQS1 dly(2T, 0.5T) = (0, 10)
5922 04:42:22.440786 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5923 04:42:22.444018 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5924 04:42:22.447052 best DQS0 dly(2T, 0.5T) = (0, 10)
5925 04:42:22.447135 best DQS1 dly(2T, 0.5T) = (0, 10)
5926 04:42:22.450381 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5927 04:42:22.453847 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5928 04:42:22.457004 Pre-setting of DQS Precalculation
5929 04:42:22.463818 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5930 04:42:22.470281 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5931 04:42:22.477254 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5932 04:42:22.477353
5933 04:42:22.477433
5934 04:42:22.480281 [Calibration Summary] 1866 Mbps
5935 04:42:22.480372 CH 0, Rank 0
5936 04:42:22.483574 SW Impedance : PASS
5937 04:42:22.487014 DUTY Scan : NO K
5938 04:42:22.487097 ZQ Calibration : PASS
5939 04:42:22.490469 Jitter Meter : NO K
5940 04:42:22.493544 CBT Training : PASS
5941 04:42:22.493635 Write leveling : PASS
5942 04:42:22.496907 RX DQS gating : PASS
5943 04:42:22.500293 RX DQ/DQS(RDDQC) : PASS
5944 04:42:22.500367 TX DQ/DQS : PASS
5945 04:42:22.503759 RX DATLAT : PASS
5946 04:42:22.507171 RX DQ/DQS(Engine): PASS
5947 04:42:22.507251 TX OE : NO K
5948 04:42:22.507322 All Pass.
5949 04:42:22.510652
5950 04:42:22.510736 CH 0, Rank 1
5951 04:42:22.513595 SW Impedance : PASS
5952 04:42:22.513693 DUTY Scan : NO K
5953 04:42:22.517220 ZQ Calibration : PASS
5954 04:42:22.517290 Jitter Meter : NO K
5955 04:42:22.520485 CBT Training : PASS
5956 04:42:22.523676 Write leveling : PASS
5957 04:42:22.523758 RX DQS gating : PASS
5958 04:42:22.527430 RX DQ/DQS(RDDQC) : PASS
5959 04:42:22.530266 TX DQ/DQS : PASS
5960 04:42:22.530341 RX DATLAT : PASS
5961 04:42:22.533996 RX DQ/DQS(Engine): PASS
5962 04:42:22.537373 TX OE : NO K
5963 04:42:22.537474 All Pass.
5964 04:42:22.537564
5965 04:42:22.537659 CH 1, Rank 0
5966 04:42:22.540190 SW Impedance : PASS
5967 04:42:22.543551 DUTY Scan : NO K
5968 04:42:22.543624 ZQ Calibration : PASS
5969 04:42:22.547185 Jitter Meter : NO K
5970 04:42:22.550185 CBT Training : PASS
5971 04:42:22.550270 Write leveling : PASS
5972 04:42:22.553592 RX DQS gating : PASS
5973 04:42:22.556829 RX DQ/DQS(RDDQC) : PASS
5974 04:42:22.556936 TX DQ/DQS : PASS
5975 04:42:22.560338 RX DATLAT : PASS
5976 04:42:22.560412 RX DQ/DQS(Engine): PASS
5977 04:42:22.563868 TX OE : NO K
5978 04:42:22.563969 All Pass.
5979 04:42:22.564066
5980 04:42:22.566913 CH 1, Rank 1
5981 04:42:22.566991 SW Impedance : PASS
5982 04:42:22.570277 DUTY Scan : NO K
5983 04:42:22.573268 ZQ Calibration : PASS
5984 04:42:22.573339 Jitter Meter : NO K
5985 04:42:22.576876 CBT Training : PASS
5986 04:42:22.580291 Write leveling : PASS
5987 04:42:22.580388 RX DQS gating : PASS
5988 04:42:22.583355 RX DQ/DQS(RDDQC) : PASS
5989 04:42:22.586745 TX DQ/DQS : PASS
5990 04:42:22.586849 RX DATLAT : PASS
5991 04:42:22.590344 RX DQ/DQS(Engine): PASS
5992 04:42:22.593578 TX OE : NO K
5993 04:42:22.593675 All Pass.
5994 04:42:22.593771
5995 04:42:22.596805 DramC Write-DBI off
5996 04:42:22.596913 PER_BANK_REFRESH: Hybrid Mode
5997 04:42:22.600093 TX_TRACKING: ON
5998 04:42:22.606412 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5999 04:42:22.613273 [FAST_K] Save calibration result to emmc
6000 04:42:22.616375 dramc_set_vcore_voltage set vcore to 650000
6001 04:42:22.616448 Read voltage for 400, 6
6002 04:42:22.619825 Vio18 = 0
6003 04:42:22.619902 Vcore = 650000
6004 04:42:22.619988 Vdram = 0
6005 04:42:22.623265 Vddq = 0
6006 04:42:22.623339 Vmddr = 0
6007 04:42:22.626566 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6008 04:42:22.633111 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6009 04:42:22.636578 MEM_TYPE=3, freq_sel=20
6010 04:42:22.639804 sv_algorithm_assistance_LP4_800
6011 04:42:22.643296 ============ PULL DRAM RESETB DOWN ============
6012 04:42:22.646629 ========== PULL DRAM RESETB DOWN end =========
6013 04:42:22.649890 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6014 04:42:22.653201 ===================================
6015 04:42:22.656630 LPDDR4 DRAM CONFIGURATION
6016 04:42:22.659950 ===================================
6017 04:42:22.662966 EX_ROW_EN[0] = 0x0
6018 04:42:22.663038 EX_ROW_EN[1] = 0x0
6019 04:42:22.666466 LP4Y_EN = 0x0
6020 04:42:22.666537 WORK_FSP = 0x0
6021 04:42:22.669655 WL = 0x2
6022 04:42:22.669726 RL = 0x2
6023 04:42:22.672996 BL = 0x2
6024 04:42:22.673092 RPST = 0x0
6025 04:42:22.676521 RD_PRE = 0x0
6026 04:42:22.679579 WR_PRE = 0x1
6027 04:42:22.679651 WR_PST = 0x0
6028 04:42:22.683049 DBI_WR = 0x0
6029 04:42:22.683119 DBI_RD = 0x0
6030 04:42:22.686508 OTF = 0x1
6031 04:42:22.689813 ===================================
6032 04:42:22.692811 ===================================
6033 04:42:22.692907 ANA top config
6034 04:42:22.696304 ===================================
6035 04:42:22.699434 DLL_ASYNC_EN = 0
6036 04:42:22.703310 ALL_SLAVE_EN = 1
6037 04:42:22.703385 NEW_RANK_MODE = 1
6038 04:42:22.706422 DLL_IDLE_MODE = 1
6039 04:42:22.709474 LP45_APHY_COMB_EN = 1
6040 04:42:22.712708 TX_ODT_DIS = 1
6041 04:42:22.712813 NEW_8X_MODE = 1
6042 04:42:22.716217 ===================================
6043 04:42:22.719740 ===================================
6044 04:42:22.722619 data_rate = 800
6045 04:42:22.725893 CKR = 1
6046 04:42:22.729560 DQ_P2S_RATIO = 4
6047 04:42:22.732824 ===================================
6048 04:42:22.736090 CA_P2S_RATIO = 4
6049 04:42:22.739289 DQ_CA_OPEN = 0
6050 04:42:22.739373 DQ_SEMI_OPEN = 1
6051 04:42:22.742528 CA_SEMI_OPEN = 1
6052 04:42:22.745908 CA_FULL_RATE = 0
6053 04:42:22.749404 DQ_CKDIV4_EN = 0
6054 04:42:22.752546 CA_CKDIV4_EN = 1
6055 04:42:22.755881 CA_PREDIV_EN = 0
6056 04:42:22.756011 PH8_DLY = 0
6057 04:42:22.759378 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6058 04:42:22.762665 DQ_AAMCK_DIV = 0
6059 04:42:22.765946 CA_AAMCK_DIV = 0
6060 04:42:22.769387 CA_ADMCK_DIV = 4
6061 04:42:22.772408 DQ_TRACK_CA_EN = 0
6062 04:42:22.772482 CA_PICK = 800
6063 04:42:22.775934 CA_MCKIO = 400
6064 04:42:22.779413 MCKIO_SEMI = 400
6065 04:42:22.782355 PLL_FREQ = 3016
6066 04:42:22.785920 DQ_UI_PI_RATIO = 32
6067 04:42:22.789410 CA_UI_PI_RATIO = 32
6068 04:42:22.792352 ===================================
6069 04:42:22.795989 ===================================
6070 04:42:22.799365 memory_type:LPDDR4
6071 04:42:22.799434 GP_NUM : 10
6072 04:42:22.802232 SRAM_EN : 1
6073 04:42:22.802300 MD32_EN : 0
6074 04:42:22.806048 ===================================
6075 04:42:22.809300 [ANA_INIT] >>>>>>>>>>>>>>
6076 04:42:22.812285 <<<<<< [CONFIGURE PHASE]: ANA_TX
6077 04:42:22.815703 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6078 04:42:22.819082 ===================================
6079 04:42:22.822596 data_rate = 800,PCW = 0X7400
6080 04:42:22.825604 ===================================
6081 04:42:22.829059 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6082 04:42:22.832524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6083 04:42:22.845664 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6084 04:42:22.849106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6085 04:42:22.852098 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6086 04:42:22.855413 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6087 04:42:22.858635 [ANA_INIT] flow start
6088 04:42:22.862479 [ANA_INIT] PLL >>>>>>>>
6089 04:42:22.862585 [ANA_INIT] PLL <<<<<<<<
6090 04:42:22.865415 [ANA_INIT] MIDPI >>>>>>>>
6091 04:42:22.868831 [ANA_INIT] MIDPI <<<<<<<<
6092 04:42:22.868908 [ANA_INIT] DLL >>>>>>>>
6093 04:42:22.872276 [ANA_INIT] flow end
6094 04:42:22.875664 ============ LP4 DIFF to SE enter ============
6095 04:42:22.882204 ============ LP4 DIFF to SE exit ============
6096 04:42:22.882307 [ANA_INIT] <<<<<<<<<<<<<
6097 04:42:22.885778 [Flow] Enable top DCM control >>>>>
6098 04:42:22.888688 [Flow] Enable top DCM control <<<<<
6099 04:42:22.892188 Enable DLL master slave shuffle
6100 04:42:22.898682 ==============================================================
6101 04:42:22.898790 Gating Mode config
6102 04:42:22.905261 ==============================================================
6103 04:42:22.908560 Config description:
6104 04:42:22.915200 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6105 04:42:22.921925 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6106 04:42:22.928523 SELPH_MODE 0: By rank 1: By Phase
6107 04:42:22.935089 ==============================================================
6108 04:42:22.935167 GAT_TRACK_EN = 0
6109 04:42:22.938560 RX_GATING_MODE = 2
6110 04:42:22.941850 RX_GATING_TRACK_MODE = 2
6111 04:42:22.945125 SELPH_MODE = 1
6112 04:42:22.948835 PICG_EARLY_EN = 1
6113 04:42:22.952077 VALID_LAT_VALUE = 1
6114 04:42:22.958771 ==============================================================
6115 04:42:22.962149 Enter into Gating configuration >>>>
6116 04:42:22.965320 Exit from Gating configuration <<<<
6117 04:42:22.968287 Enter into DVFS_PRE_config >>>>>
6118 04:42:22.978842 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6119 04:42:22.981696 Exit from DVFS_PRE_config <<<<<
6120 04:42:22.985199 Enter into PICG configuration >>>>
6121 04:42:22.988300 Exit from PICG configuration <<<<
6122 04:42:22.991783 [RX_INPUT] configuration >>>>>
6123 04:42:22.991856 [RX_INPUT] configuration <<<<<
6124 04:42:22.998309 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6125 04:42:23.005224 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6126 04:42:23.008199 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6127 04:42:23.015265 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6128 04:42:23.021742 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6129 04:42:23.028414 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6130 04:42:23.031518 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6131 04:42:23.034963 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6132 04:42:23.041461 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6133 04:42:23.044793 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6134 04:42:23.048092 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6135 04:42:23.054655 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6136 04:42:23.058211 ===================================
6137 04:42:23.058289 LPDDR4 DRAM CONFIGURATION
6138 04:42:23.061497 ===================================
6139 04:42:23.064597 EX_ROW_EN[0] = 0x0
6140 04:42:23.064672 EX_ROW_EN[1] = 0x0
6141 04:42:23.067966 LP4Y_EN = 0x0
6142 04:42:23.068038 WORK_FSP = 0x0
6143 04:42:23.071241 WL = 0x2
6144 04:42:23.074607 RL = 0x2
6145 04:42:23.074690 BL = 0x2
6146 04:42:23.077925 RPST = 0x0
6147 04:42:23.078044 RD_PRE = 0x0
6148 04:42:23.081535 WR_PRE = 0x1
6149 04:42:23.081617 WR_PST = 0x0
6150 04:42:23.084512 DBI_WR = 0x0
6151 04:42:23.084594 DBI_RD = 0x0
6152 04:42:23.088062 OTF = 0x1
6153 04:42:23.091571 ===================================
6154 04:42:23.094626 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6155 04:42:23.098037 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6156 04:42:23.101570 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6157 04:42:23.104570 ===================================
6158 04:42:23.108242 LPDDR4 DRAM CONFIGURATION
6159 04:42:23.111157 ===================================
6160 04:42:23.114621 EX_ROW_EN[0] = 0x10
6161 04:42:23.114703 EX_ROW_EN[1] = 0x0
6162 04:42:23.117821 LP4Y_EN = 0x0
6163 04:42:23.117903 WORK_FSP = 0x0
6164 04:42:23.121167 WL = 0x2
6165 04:42:23.121250 RL = 0x2
6166 04:42:23.124593 BL = 0x2
6167 04:42:23.124675 RPST = 0x0
6168 04:42:23.128065 RD_PRE = 0x0
6169 04:42:23.131394 WR_PRE = 0x1
6170 04:42:23.131476 WR_PST = 0x0
6171 04:42:23.134308 DBI_WR = 0x0
6172 04:42:23.134390 DBI_RD = 0x0
6173 04:42:23.137766 OTF = 0x1
6174 04:42:23.141172 ===================================
6175 04:42:23.144176 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6176 04:42:23.149706 nWR fixed to 30
6177 04:42:23.152899 [ModeRegInit_LP4] CH0 RK0
6178 04:42:23.152981 [ModeRegInit_LP4] CH0 RK1
6179 04:42:23.156566 [ModeRegInit_LP4] CH1 RK0
6180 04:42:23.159734 [ModeRegInit_LP4] CH1 RK1
6181 04:42:23.159816 match AC timing 19
6182 04:42:23.166457 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6183 04:42:23.169861 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6184 04:42:23.172793 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6185 04:42:23.179745 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6186 04:42:23.182826 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6187 04:42:23.182909 ==
6188 04:42:23.186327 Dram Type= 6, Freq= 0, CH_0, rank 0
6189 04:42:23.189282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6190 04:42:23.189365 ==
6191 04:42:23.195812 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6192 04:42:23.202718 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6193 04:42:23.205740 [CA 0] Center 36 (8~64) winsize 57
6194 04:42:23.209192 [CA 1] Center 36 (8~64) winsize 57
6195 04:42:23.212554 [CA 2] Center 36 (8~64) winsize 57
6196 04:42:23.215798 [CA 3] Center 36 (8~64) winsize 57
6197 04:42:23.219222 [CA 4] Center 36 (8~64) winsize 57
6198 04:42:23.219305 [CA 5] Center 36 (8~64) winsize 57
6199 04:42:23.222476
6200 04:42:23.225841 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6201 04:42:23.225924
6202 04:42:23.229335 [CATrainingPosCal] consider 1 rank data
6203 04:42:23.232184 u2DelayCellTimex100 = 270/100 ps
6204 04:42:23.235496 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 04:42:23.239016 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 04:42:23.242554 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 04:42:23.245514 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 04:42:23.248954 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 04:42:23.252407 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 04:42:23.252501
6211 04:42:23.255582 CA PerBit enable=1, Macro0, CA PI delay=36
6212 04:42:23.255667
6213 04:42:23.258875 [CBTSetCACLKResult] CA Dly = 36
6214 04:42:23.262162 CS Dly: 1 (0~32)
6215 04:42:23.262302 ==
6216 04:42:23.265539 Dram Type= 6, Freq= 0, CH_0, rank 1
6217 04:42:23.268915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6218 04:42:23.269007 ==
6219 04:42:23.275542 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6220 04:42:23.282018 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6221 04:42:23.285429 [CA 0] Center 36 (8~64) winsize 57
6222 04:42:23.285568 [CA 1] Center 36 (8~64) winsize 57
6223 04:42:23.288847 [CA 2] Center 36 (8~64) winsize 57
6224 04:42:23.292293 [CA 3] Center 36 (8~64) winsize 57
6225 04:42:23.295971 [CA 4] Center 36 (8~64) winsize 57
6226 04:42:23.298814 [CA 5] Center 36 (8~64) winsize 57
6227 04:42:23.298988
6228 04:42:23.302245 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6229 04:42:23.302421
6230 04:42:23.305705 [CATrainingPosCal] consider 2 rank data
6231 04:42:23.308653 u2DelayCellTimex100 = 270/100 ps
6232 04:42:23.312005 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 04:42:23.318512 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 04:42:23.322259 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 04:42:23.325624 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 04:42:23.328470 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 04:42:23.331822 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 04:42:23.331906
6239 04:42:23.335230 CA PerBit enable=1, Macro0, CA PI delay=36
6240 04:42:23.335314
6241 04:42:23.338490 [CBTSetCACLKResult] CA Dly = 36
6242 04:42:23.338574 CS Dly: 1 (0~32)
6243 04:42:23.342038
6244 04:42:23.345517 ----->DramcWriteLeveling(PI) begin...
6245 04:42:23.345638 ==
6246 04:42:23.348392 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 04:42:23.352077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 04:42:23.352240 ==
6249 04:42:23.355545 Write leveling (Byte 0): 40 => 8
6250 04:42:23.358388 Write leveling (Byte 1): 32 => 0
6251 04:42:23.361704 DramcWriteLeveling(PI) end<-----
6252 04:42:23.361788
6253 04:42:23.361854 ==
6254 04:42:23.365042 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 04:42:23.368292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 04:42:23.368376 ==
6257 04:42:23.371704 [Gating] SW mode calibration
6258 04:42:23.378469 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6259 04:42:23.385028 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6260 04:42:23.388394 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6261 04:42:23.391818 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6262 04:42:23.398167 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6263 04:42:23.401576 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6264 04:42:23.405087 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 04:42:23.411674 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 04:42:23.415058 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6267 04:42:23.418148 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 04:42:23.421543 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6269 04:42:23.425078 Total UI for P1: 0, mck2ui 16
6270 04:42:23.428302 best dqsien dly found for B0: ( 0, 14, 24)
6271 04:42:23.431324 Total UI for P1: 0, mck2ui 16
6272 04:42:23.434985 best dqsien dly found for B1: ( 0, 14, 24)
6273 04:42:23.437917 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6274 04:42:23.444888 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6275 04:42:23.444973
6276 04:42:23.447906 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6277 04:42:23.451366 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6278 04:42:23.454872 [Gating] SW calibration Done
6279 04:42:23.454955 ==
6280 04:42:23.457864 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 04:42:23.461303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 04:42:23.461413 ==
6283 04:42:23.464433 RX Vref Scan: 0
6284 04:42:23.464516
6285 04:42:23.464581 RX Vref 0 -> 0, step: 1
6286 04:42:23.464642
6287 04:42:23.467815 RX Delay -410 -> 252, step: 16
6288 04:42:23.471612 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6289 04:42:23.478108 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6290 04:42:23.481078 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6291 04:42:23.484562 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6292 04:42:23.487855 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6293 04:42:23.494434 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6294 04:42:23.497918 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6295 04:42:23.500951 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6296 04:42:23.504376 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6297 04:42:23.510780 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6298 04:42:23.514196 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6299 04:42:23.517822 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6300 04:42:23.520932 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6301 04:42:23.527347 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6302 04:42:23.530884 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6303 04:42:23.534291 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6304 04:42:23.534375 ==
6305 04:42:23.537705 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 04:42:23.544412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 04:42:23.544518 ==
6308 04:42:23.544596 DQS Delay:
6309 04:42:23.547746 DQS0 = 27, DQS1 = 43
6310 04:42:23.547827 DQM Delay:
6311 04:42:23.547906 DQM0 = 13, DQM1 = 12
6312 04:42:23.550858 DQ Delay:
6313 04:42:23.554267 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6314 04:42:23.554349 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6315 04:42:23.557738 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6316 04:42:23.561181 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6317 04:42:23.561263
6318 04:42:23.564231
6319 04:42:23.564311 ==
6320 04:42:23.567536 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 04:42:23.570768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 04:42:23.570851 ==
6323 04:42:23.570915
6324 04:42:23.570974
6325 04:42:23.574219 TX Vref Scan disable
6326 04:42:23.574303 == TX Byte 0 ==
6327 04:42:23.577371 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6328 04:42:23.584048 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6329 04:42:23.584144 == TX Byte 1 ==
6330 04:42:23.587489 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6331 04:42:23.593995 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6332 04:42:23.594105 ==
6333 04:42:23.597307 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 04:42:23.600767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 04:42:23.600886 ==
6336 04:42:23.600980
6337 04:42:23.601075
6338 04:42:23.604175 TX Vref Scan disable
6339 04:42:23.604256 == TX Byte 0 ==
6340 04:42:23.610671 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 04:42:23.614131 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 04:42:23.614213 == TX Byte 1 ==
6343 04:42:23.617291 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6344 04:42:23.624129 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6345 04:42:23.624211
6346 04:42:23.624275 [DATLAT]
6347 04:42:23.627587 Freq=400, CH0 RK0
6348 04:42:23.627670
6349 04:42:23.627734 DATLAT Default: 0xf
6350 04:42:23.630512 0, 0xFFFF, sum = 0
6351 04:42:23.630597 1, 0xFFFF, sum = 0
6352 04:42:23.634120 2, 0xFFFF, sum = 0
6353 04:42:23.634220 3, 0xFFFF, sum = 0
6354 04:42:23.637470 4, 0xFFFF, sum = 0
6355 04:42:23.637553 5, 0xFFFF, sum = 0
6356 04:42:23.640451 6, 0xFFFF, sum = 0
6357 04:42:23.640576 7, 0xFFFF, sum = 0
6358 04:42:23.643806 8, 0xFFFF, sum = 0
6359 04:42:23.643889 9, 0xFFFF, sum = 0
6360 04:42:23.647221 10, 0xFFFF, sum = 0
6361 04:42:23.647303 11, 0xFFFF, sum = 0
6362 04:42:23.650802 12, 0xFFFF, sum = 0
6363 04:42:23.650885 13, 0x0, sum = 1
6364 04:42:23.653709 14, 0x0, sum = 2
6365 04:42:23.653791 15, 0x0, sum = 3
6366 04:42:23.656955 16, 0x0, sum = 4
6367 04:42:23.657085 best_step = 14
6368 04:42:23.657150
6369 04:42:23.657210 ==
6370 04:42:23.660343 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 04:42:23.666999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 04:42:23.667085 ==
6373 04:42:23.667152 RX Vref Scan: 1
6374 04:42:23.667214
6375 04:42:23.670341 RX Vref 0 -> 0, step: 1
6376 04:42:23.670424
6377 04:42:23.673692 RX Delay -327 -> 252, step: 8
6378 04:42:23.673807
6379 04:42:23.676808 Set Vref, RX VrefLevel [Byte0]: 59
6380 04:42:23.680126 [Byte1]: 48
6381 04:42:23.680210
6382 04:42:23.683639 Final RX Vref Byte 0 = 59 to rank0
6383 04:42:23.687276 Final RX Vref Byte 1 = 48 to rank0
6384 04:42:23.690215 Final RX Vref Byte 0 = 59 to rank1
6385 04:42:23.693660 Final RX Vref Byte 1 = 48 to rank1==
6386 04:42:23.696893 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 04:42:23.700277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 04:42:23.703620 ==
6389 04:42:23.703722 DQS Delay:
6390 04:42:23.703788 DQS0 = 28, DQS1 = 48
6391 04:42:23.706640 DQM Delay:
6392 04:42:23.706724 DQM0 = 11, DQM1 = 15
6393 04:42:23.709976 DQ Delay:
6394 04:42:23.710074 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6395 04:42:23.713396 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6396 04:42:23.716844 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6397 04:42:23.720282 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6398 04:42:23.720381
6399 04:42:23.720474
6400 04:42:23.730083 [DQSOSCAuto] RK0, (LSB)MR18= 0xb2aa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6401 04:42:23.733534 CH0 RK0: MR19=C0C, MR18=B2AA
6402 04:42:23.739903 CH0_RK0: MR19=0xC0C, MR18=0xB2AA, DQSOSC=387, MR23=63, INC=394, DEC=262
6403 04:42:23.740029 ==
6404 04:42:23.743381 Dram Type= 6, Freq= 0, CH_0, rank 1
6405 04:42:23.746872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 04:42:23.746973 ==
6407 04:42:23.750107 [Gating] SW mode calibration
6408 04:42:23.756975 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6409 04:42:23.760241 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6410 04:42:23.767005 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6411 04:42:23.770140 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6412 04:42:23.773515 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6413 04:42:23.780017 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6414 04:42:23.783711 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 04:42:23.786971 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6416 04:42:23.793763 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6417 04:42:23.796725 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6418 04:42:23.800401 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6419 04:42:23.803696 Total UI for P1: 0, mck2ui 16
6420 04:42:23.806969 best dqsien dly found for B0: ( 0, 14, 24)
6421 04:42:23.810012 Total UI for P1: 0, mck2ui 16
6422 04:42:23.813501 best dqsien dly found for B1: ( 0, 14, 24)
6423 04:42:23.817038 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6424 04:42:23.820085 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6425 04:42:23.820168
6426 04:42:23.826949 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6427 04:42:23.830036 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6428 04:42:23.830120 [Gating] SW calibration Done
6429 04:42:23.833555 ==
6430 04:42:23.836968 Dram Type= 6, Freq= 0, CH_0, rank 1
6431 04:42:23.839970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 04:42:23.840054 ==
6433 04:42:23.840121 RX Vref Scan: 0
6434 04:42:23.840183
6435 04:42:23.843345 RX Vref 0 -> 0, step: 1
6436 04:42:23.843428
6437 04:42:23.846843 RX Delay -410 -> 252, step: 16
6438 04:42:23.850259 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6439 04:42:23.853446 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6440 04:42:23.860118 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6441 04:42:23.863558 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6442 04:42:23.866903 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6443 04:42:23.870241 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6444 04:42:23.876762 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6445 04:42:23.880046 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6446 04:42:23.883322 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6447 04:42:23.886634 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6448 04:42:23.893337 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6449 04:42:23.896738 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6450 04:42:23.899672 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6451 04:42:23.906404 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6452 04:42:23.909645 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6453 04:42:23.913315 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6454 04:42:23.913398 ==
6455 04:42:23.916241 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 04:42:23.919669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 04:42:23.923287 ==
6458 04:42:23.923372 DQS Delay:
6459 04:42:23.923437 DQS0 = 27, DQS1 = 43
6460 04:42:23.926606 DQM Delay:
6461 04:42:23.926688 DQM0 = 9, DQM1 = 16
6462 04:42:23.929567 DQ Delay:
6463 04:42:23.929650 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6464 04:42:23.933117 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6465 04:42:23.936501 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6466 04:42:23.939591 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6467 04:42:23.939673
6468 04:42:23.939739
6469 04:42:23.939799 ==
6470 04:42:23.942954 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 04:42:23.949914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 04:42:23.950036 ==
6473 04:42:23.950100
6474 04:42:23.950160
6475 04:42:23.950218 TX Vref Scan disable
6476 04:42:23.952963 == TX Byte 0 ==
6477 04:42:23.956299 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6478 04:42:23.959596 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6479 04:42:23.963147 == TX Byte 1 ==
6480 04:42:23.966671 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6481 04:42:23.969878 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6482 04:42:23.970014 ==
6483 04:42:23.972958 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 04:42:23.979848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 04:42:23.979959 ==
6486 04:42:23.980027
6487 04:42:23.980088
6488 04:42:23.980146 TX Vref Scan disable
6489 04:42:23.983316 == TX Byte 0 ==
6490 04:42:23.986294 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6491 04:42:23.989449 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6492 04:42:23.993127 == TX Byte 1 ==
6493 04:42:23.996427 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6494 04:42:23.999505 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6495 04:42:23.999608
6496 04:42:24.002836 [DATLAT]
6497 04:42:24.002917 Freq=400, CH0 RK1
6498 04:42:24.002984
6499 04:42:24.006447 DATLAT Default: 0xe
6500 04:42:24.006527 0, 0xFFFF, sum = 0
6501 04:42:24.009770 1, 0xFFFF, sum = 0
6502 04:42:24.009843 2, 0xFFFF, sum = 0
6503 04:42:24.013012 3, 0xFFFF, sum = 0
6504 04:42:24.013096 4, 0xFFFF, sum = 0
6505 04:42:24.016485 5, 0xFFFF, sum = 0
6506 04:42:24.016570 6, 0xFFFF, sum = 0
6507 04:42:24.019433 7, 0xFFFF, sum = 0
6508 04:42:24.019547 8, 0xFFFF, sum = 0
6509 04:42:24.022943 9, 0xFFFF, sum = 0
6510 04:42:24.023028 10, 0xFFFF, sum = 0
6511 04:42:24.025867 11, 0xFFFF, sum = 0
6512 04:42:24.029314 12, 0xFFFF, sum = 0
6513 04:42:24.029398 13, 0x0, sum = 1
6514 04:42:24.029466 14, 0x0, sum = 2
6515 04:42:24.032788 15, 0x0, sum = 3
6516 04:42:24.032872 16, 0x0, sum = 4
6517 04:42:24.036179 best_step = 14
6518 04:42:24.036262
6519 04:42:24.036326 ==
6520 04:42:24.039163 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 04:42:24.042691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 04:42:24.042775 ==
6523 04:42:24.046165 RX Vref Scan: 0
6524 04:42:24.046247
6525 04:42:24.046313 RX Vref 0 -> 0, step: 1
6526 04:42:24.046374
6527 04:42:24.049142 RX Delay -327 -> 252, step: 8
6528 04:42:24.057715 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6529 04:42:24.060999 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6530 04:42:24.064195 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6531 04:42:24.067673 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6532 04:42:24.074202 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6533 04:42:24.077878 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6534 04:42:24.080811 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6535 04:42:24.084293 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6536 04:42:24.091051 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6537 04:42:24.094366 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6538 04:42:24.097282 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6539 04:42:24.100844 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6540 04:42:24.107630 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6541 04:42:24.110857 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6542 04:42:24.114141 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6543 04:42:24.120761 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6544 04:42:24.120848 ==
6545 04:42:24.123761 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 04:42:24.127250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 04:42:24.127334 ==
6548 04:42:24.127419 DQS Delay:
6549 04:42:24.130763 DQS0 = 28, DQS1 = 40
6550 04:42:24.130849 DQM Delay:
6551 04:42:24.133721 DQM0 = 11, DQM1 = 12
6552 04:42:24.133818 DQ Delay:
6553 04:42:24.137160 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6554 04:42:24.140576 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6555 04:42:24.143545 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6556 04:42:24.147047 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6557 04:42:24.147150
6558 04:42:24.147216
6559 04:42:24.153445 [DQSOSCAuto] RK1, (LSB)MR18= 0xbb6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6560 04:42:24.156961 CH0 RK1: MR19=C0C, MR18=BB6F
6561 04:42:24.163433 CH0_RK1: MR19=0xC0C, MR18=0xBB6F, DQSOSC=386, MR23=63, INC=396, DEC=264
6562 04:42:24.166805 [RxdqsGatingPostProcess] freq 400
6563 04:42:24.173640 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6564 04:42:24.176693 best DQS0 dly(2T, 0.5T) = (0, 10)
6565 04:42:24.176768 best DQS1 dly(2T, 0.5T) = (0, 10)
6566 04:42:24.180132 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6567 04:42:24.183388 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6568 04:42:24.186924 best DQS0 dly(2T, 0.5T) = (0, 10)
6569 04:42:24.189919 best DQS1 dly(2T, 0.5T) = (0, 10)
6570 04:42:24.193299 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6571 04:42:24.196722 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6572 04:42:24.199861 Pre-setting of DQS Precalculation
6573 04:42:24.206668 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6574 04:42:24.206752 ==
6575 04:42:24.209819 Dram Type= 6, Freq= 0, CH_1, rank 0
6576 04:42:24.213408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 04:42:24.213492 ==
6578 04:42:24.219813 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6579 04:42:24.223512 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6580 04:42:24.226454 [CA 0] Center 36 (8~64) winsize 57
6581 04:42:24.230098 [CA 1] Center 36 (8~64) winsize 57
6582 04:42:24.233507 [CA 2] Center 36 (8~64) winsize 57
6583 04:42:24.236484 [CA 3] Center 36 (8~64) winsize 57
6584 04:42:24.239877 [CA 4] Center 36 (8~64) winsize 57
6585 04:42:24.243437 [CA 5] Center 36 (8~64) winsize 57
6586 04:42:24.243520
6587 04:42:24.246428 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6588 04:42:24.246512
6589 04:42:24.249841 [CATrainingPosCal] consider 1 rank data
6590 04:42:24.252870 u2DelayCellTimex100 = 270/100 ps
6591 04:42:24.256364 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 04:42:24.259892 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 04:42:24.266491 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 04:42:24.269873 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 04:42:24.272784 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 04:42:24.276284 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 04:42:24.276367
6598 04:42:24.279386 CA PerBit enable=1, Macro0, CA PI delay=36
6599 04:42:24.279468
6600 04:42:24.283138 [CBTSetCACLKResult] CA Dly = 36
6601 04:42:24.283222 CS Dly: 1 (0~32)
6602 04:42:24.283288 ==
6603 04:42:24.286124 Dram Type= 6, Freq= 0, CH_1, rank 1
6604 04:42:24.292720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 04:42:24.292803 ==
6606 04:42:24.296222 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6607 04:42:24.302833 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6608 04:42:24.306217 [CA 0] Center 36 (8~64) winsize 57
6609 04:42:24.309162 [CA 1] Center 36 (8~64) winsize 57
6610 04:42:24.312809 [CA 2] Center 36 (8~64) winsize 57
6611 04:42:24.315938 [CA 3] Center 36 (8~64) winsize 57
6612 04:42:24.319185 [CA 4] Center 36 (8~64) winsize 57
6613 04:42:24.322725 [CA 5] Center 36 (8~64) winsize 57
6614 04:42:24.322810
6615 04:42:24.325845 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6616 04:42:24.325929
6617 04:42:24.329492 [CATrainingPosCal] consider 2 rank data
6618 04:42:24.332761 u2DelayCellTimex100 = 270/100 ps
6619 04:42:24.335814 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 04:42:24.339451 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 04:42:24.342854 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 04:42:24.345885 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 04:42:24.349154 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 04:42:24.356302 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 04:42:24.356385
6626 04:42:24.359379 CA PerBit enable=1, Macro0, CA PI delay=36
6627 04:42:24.359463
6628 04:42:24.362788 [CBTSetCACLKResult] CA Dly = 36
6629 04:42:24.362871 CS Dly: 1 (0~32)
6630 04:42:24.362937
6631 04:42:24.365853 ----->DramcWriteLeveling(PI) begin...
6632 04:42:24.365943 ==
6633 04:42:24.369310 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 04:42:24.372698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 04:42:24.376187 ==
6636 04:42:24.376269 Write leveling (Byte 0): 40 => 8
6637 04:42:24.379615 Write leveling (Byte 1): 32 => 0
6638 04:42:24.382543 DramcWriteLeveling(PI) end<-----
6639 04:42:24.382627
6640 04:42:24.382693 ==
6641 04:42:24.386196 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 04:42:24.392490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 04:42:24.392575 ==
6644 04:42:24.392642 [Gating] SW mode calibration
6645 04:42:24.402632 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6646 04:42:24.405771 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6647 04:42:24.409157 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6648 04:42:24.416008 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6649 04:42:24.418916 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6650 04:42:24.422728 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6651 04:42:24.429199 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 04:42:24.432288 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 04:42:24.435888 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 04:42:24.442547 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 04:42:24.445675 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6656 04:42:24.449154 Total UI for P1: 0, mck2ui 16
6657 04:42:24.452242 best dqsien dly found for B0: ( 0, 14, 24)
6658 04:42:24.455669 Total UI for P1: 0, mck2ui 16
6659 04:42:24.459181 best dqsien dly found for B1: ( 0, 14, 24)
6660 04:42:24.462293 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6661 04:42:24.465712 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6662 04:42:24.465796
6663 04:42:24.469248 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6664 04:42:24.472288 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6665 04:42:24.475813 [Gating] SW calibration Done
6666 04:42:24.475894 ==
6667 04:42:24.478988 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 04:42:24.482385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 04:42:24.485836 ==
6670 04:42:24.485966 RX Vref Scan: 0
6671 04:42:24.486049
6672 04:42:24.489200 RX Vref 0 -> 0, step: 1
6673 04:42:24.489282
6674 04:42:24.492146 RX Delay -410 -> 252, step: 16
6675 04:42:24.495569 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6676 04:42:24.499037 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6677 04:42:24.502462 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6678 04:42:24.508742 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6679 04:42:24.512357 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6680 04:42:24.515369 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6681 04:42:24.518700 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6682 04:42:24.525559 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6683 04:42:24.528971 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6684 04:42:24.531988 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6685 04:42:24.535209 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6686 04:42:24.542199 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6687 04:42:24.545447 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6688 04:42:24.548813 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6689 04:42:24.552283 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6690 04:42:24.558807 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6691 04:42:24.558893 ==
6692 04:42:24.562195 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 04:42:24.565165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 04:42:24.565248 ==
6695 04:42:24.565313 DQS Delay:
6696 04:42:24.568588 DQS0 = 27, DQS1 = 35
6697 04:42:24.568669 DQM Delay:
6698 04:42:24.572111 DQM0 = 6, DQM1 = 9
6699 04:42:24.572194 DQ Delay:
6700 04:42:24.575542 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6701 04:42:24.578472 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6702 04:42:24.581883 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6703 04:42:24.585186 DQ12 =24, DQ13 =8, DQ14 =8, DQ15 =16
6704 04:42:24.585268
6705 04:42:24.585333
6706 04:42:24.585392 ==
6707 04:42:24.588633 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 04:42:24.592215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 04:42:24.592298 ==
6710 04:42:24.592363
6711 04:42:24.592424
6712 04:42:24.595460 TX Vref Scan disable
6713 04:42:24.595542 == TX Byte 0 ==
6714 04:42:24.601874 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6715 04:42:24.605344 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6716 04:42:24.605428 == TX Byte 1 ==
6717 04:42:24.612125 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6718 04:42:24.615471 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6719 04:42:24.615617 ==
6720 04:42:24.618430 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 04:42:24.621976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 04:42:24.622110 ==
6723 04:42:24.622190
6724 04:42:24.622255
6725 04:42:24.624891 TX Vref Scan disable
6726 04:42:24.628578 == TX Byte 0 ==
6727 04:42:24.631753 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 04:42:24.635272 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 04:42:24.638240 == TX Byte 1 ==
6730 04:42:24.642002 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6731 04:42:24.645082 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6732 04:42:24.645168
6733 04:42:24.645234 [DATLAT]
6734 04:42:24.648525 Freq=400, CH1 RK0
6735 04:42:24.648608
6736 04:42:24.648673 DATLAT Default: 0xf
6737 04:42:24.651768 0, 0xFFFF, sum = 0
6738 04:42:24.655126 1, 0xFFFF, sum = 0
6739 04:42:24.655210 2, 0xFFFF, sum = 0
6740 04:42:24.658123 3, 0xFFFF, sum = 0
6741 04:42:24.658207 4, 0xFFFF, sum = 0
6742 04:42:24.661572 5, 0xFFFF, sum = 0
6743 04:42:24.661656 6, 0xFFFF, sum = 0
6744 04:42:24.664955 7, 0xFFFF, sum = 0
6745 04:42:24.665039 8, 0xFFFF, sum = 0
6746 04:42:24.668486 9, 0xFFFF, sum = 0
6747 04:42:24.668570 10, 0xFFFF, sum = 0
6748 04:42:24.671471 11, 0xFFFF, sum = 0
6749 04:42:24.671555 12, 0xFFFF, sum = 0
6750 04:42:24.674881 13, 0x0, sum = 1
6751 04:42:24.674965 14, 0x0, sum = 2
6752 04:42:24.678320 15, 0x0, sum = 3
6753 04:42:24.678432 16, 0x0, sum = 4
6754 04:42:24.681427 best_step = 14
6755 04:42:24.681508
6756 04:42:24.681573 ==
6757 04:42:24.684854 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 04:42:24.688054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 04:42:24.688138 ==
6760 04:42:24.691526 RX Vref Scan: 1
6761 04:42:24.691608
6762 04:42:24.691674 RX Vref 0 -> 0, step: 1
6763 04:42:24.691734
6764 04:42:24.694931 RX Delay -311 -> 252, step: 8
6765 04:42:24.695013
6766 04:42:24.698054 Set Vref, RX VrefLevel [Byte0]: 53
6767 04:42:24.701445 [Byte1]: 53
6768 04:42:24.705465
6769 04:42:24.705578 Final RX Vref Byte 0 = 53 to rank0
6770 04:42:24.708987 Final RX Vref Byte 1 = 53 to rank0
6771 04:42:24.711855 Final RX Vref Byte 0 = 53 to rank1
6772 04:42:24.715737 Final RX Vref Byte 1 = 53 to rank1==
6773 04:42:24.718725 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 04:42:24.725192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 04:42:24.725276 ==
6776 04:42:24.725342 DQS Delay:
6777 04:42:24.728579 DQS0 = 28, DQS1 = 40
6778 04:42:24.728662 DQM Delay:
6779 04:42:24.728727 DQM0 = 9, DQM1 = 12
6780 04:42:24.731998 DQ Delay:
6781 04:42:24.735145 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6782 04:42:24.735228 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =4
6783 04:42:24.738631 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6784 04:42:24.742178 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =16
6785 04:42:24.742265
6786 04:42:24.742331
6787 04:42:24.752041 [DQSOSCAuto] RK0, (LSB)MR18= 0x96d2, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 391 ps
6788 04:42:24.755756 CH1 RK0: MR19=C0C, MR18=96D2
6789 04:42:24.761771 CH1_RK0: MR19=0xC0C, MR18=0x96D2, DQSOSC=383, MR23=63, INC=402, DEC=268
6790 04:42:24.761880 ==
6791 04:42:24.765333 Dram Type= 6, Freq= 0, CH_1, rank 1
6792 04:42:24.768892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 04:42:24.768977 ==
6794 04:42:24.771825 [Gating] SW mode calibration
6795 04:42:24.778758 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6796 04:42:24.785309 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6797 04:42:24.788304 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6798 04:42:24.791933 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6799 04:42:24.795426 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6800 04:42:24.801739 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6801 04:42:24.805196 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 04:42:24.808308 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6803 04:42:24.815298 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6804 04:42:24.818515 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6805 04:42:24.821703 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6806 04:42:24.824962 Total UI for P1: 0, mck2ui 16
6807 04:42:24.828464 best dqsien dly found for B0: ( 0, 14, 24)
6808 04:42:24.831887 Total UI for P1: 0, mck2ui 16
6809 04:42:24.835207 best dqsien dly found for B1: ( 0, 14, 24)
6810 04:42:24.838592 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6811 04:42:24.841529 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6812 04:42:24.844990
6813 04:42:24.848503 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6814 04:42:24.851723 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6815 04:42:24.855139 [Gating] SW calibration Done
6816 04:42:24.855229 ==
6817 04:42:24.858347 Dram Type= 6, Freq= 0, CH_1, rank 1
6818 04:42:24.861696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 04:42:24.861799 ==
6820 04:42:24.861905 RX Vref Scan: 0
6821 04:42:24.864736
6822 04:42:24.864845 RX Vref 0 -> 0, step: 1
6823 04:42:24.864935
6824 04:42:24.868301 RX Delay -410 -> 252, step: 16
6825 04:42:24.871786 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6826 04:42:24.878138 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6827 04:42:24.881713 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6828 04:42:24.884683 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6829 04:42:24.888261 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6830 04:42:24.895137 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6831 04:42:24.898429 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6832 04:42:24.901469 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6833 04:42:24.905006 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6834 04:42:24.911785 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6835 04:42:24.914755 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6836 04:42:24.918096 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6837 04:42:24.921479 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6838 04:42:24.927894 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6839 04:42:24.931667 iDelay=230, Bit 14, Center -19 (-266 ~ 229) 496
6840 04:42:24.934667 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6841 04:42:24.934746 ==
6842 04:42:24.937911 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 04:42:24.941219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 04:42:24.944907 ==
6845 04:42:24.944983 DQS Delay:
6846 04:42:24.945064 DQS0 = 35, DQS1 = 43
6847 04:42:24.947907 DQM Delay:
6848 04:42:24.947981 DQM0 = 18, DQM1 = 19
6849 04:42:24.951374 DQ Delay:
6850 04:42:24.951448 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6851 04:42:24.954824 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6852 04:42:24.958074 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6853 04:42:24.961191 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6854 04:42:24.961292
6855 04:42:24.964628
6856 04:42:24.964703 ==
6857 04:42:24.967771 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 04:42:24.971297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 04:42:24.971381 ==
6860 04:42:24.971464
6861 04:42:24.971542
6862 04:42:24.974747 TX Vref Scan disable
6863 04:42:24.974820 == TX Byte 0 ==
6864 04:42:24.978254 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6865 04:42:24.984612 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6866 04:42:24.984689 == TX Byte 1 ==
6867 04:42:24.988152 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6868 04:42:24.994446 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6869 04:42:24.994527 ==
6870 04:42:24.997954 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 04:42:25.001222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 04:42:25.001307 ==
6873 04:42:25.001374
6874 04:42:25.001435
6875 04:42:25.004652 TX Vref Scan disable
6876 04:42:25.004724 == TX Byte 0 ==
6877 04:42:25.008086 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6878 04:42:25.014952 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6879 04:42:25.015030 == TX Byte 1 ==
6880 04:42:25.018004 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6881 04:42:25.024616 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6882 04:42:25.024722
6883 04:42:25.024821 [DATLAT]
6884 04:42:25.024912 Freq=400, CH1 RK1
6885 04:42:25.024999
6886 04:42:25.028065 DATLAT Default: 0xe
6887 04:42:25.028163 0, 0xFFFF, sum = 0
6888 04:42:25.031375 1, 0xFFFF, sum = 0
6889 04:42:25.031448 2, 0xFFFF, sum = 0
6890 04:42:25.034718 3, 0xFFFF, sum = 0
6891 04:42:25.037742 4, 0xFFFF, sum = 0
6892 04:42:25.037826 5, 0xFFFF, sum = 0
6893 04:42:25.041111 6, 0xFFFF, sum = 0
6894 04:42:25.041196 7, 0xFFFF, sum = 0
6895 04:42:25.044428 8, 0xFFFF, sum = 0
6896 04:42:25.044512 9, 0xFFFF, sum = 0
6897 04:42:25.048040 10, 0xFFFF, sum = 0
6898 04:42:25.048123 11, 0xFFFF, sum = 0
6899 04:42:25.051021 12, 0xFFFF, sum = 0
6900 04:42:25.051105 13, 0x0, sum = 1
6901 04:42:25.054532 14, 0x0, sum = 2
6902 04:42:25.054616 15, 0x0, sum = 3
6903 04:42:25.057904 16, 0x0, sum = 4
6904 04:42:25.057993 best_step = 14
6905 04:42:25.058059
6906 04:42:25.058120 ==
6907 04:42:25.061120 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 04:42:25.064599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 04:42:25.064683 ==
6910 04:42:25.067666 RX Vref Scan: 0
6911 04:42:25.067749
6912 04:42:25.071012 RX Vref 0 -> 0, step: 1
6913 04:42:25.071096
6914 04:42:25.071161 RX Delay -327 -> 252, step: 8
6915 04:42:25.079816 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6916 04:42:25.083279 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6917 04:42:25.086728 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6918 04:42:25.089619 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6919 04:42:25.096793 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6920 04:42:25.099735 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6921 04:42:25.103118 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6922 04:42:25.106374 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6923 04:42:25.113046 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6924 04:42:25.116411 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6925 04:42:25.119839 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6926 04:42:25.126246 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6927 04:42:25.129929 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6928 04:42:25.133000 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6929 04:42:25.136520 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6930 04:42:25.142895 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6931 04:42:25.142978 ==
6932 04:42:25.146193 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 04:42:25.150004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 04:42:25.150088 ==
6935 04:42:25.150154 DQS Delay:
6936 04:42:25.153189 DQS0 = 28, DQS1 = 36
6937 04:42:25.153273 DQM Delay:
6938 04:42:25.156159 DQM0 = 10, DQM1 = 11
6939 04:42:25.156242 DQ Delay:
6940 04:42:25.159705 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6941 04:42:25.163194 DQ4 =12, DQ5 =16, DQ6 =12, DQ7 =8
6942 04:42:25.166443 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6943 04:42:25.169528 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6944 04:42:25.169612
6945 04:42:25.169677
6946 04:42:25.176447 [DQSOSCAuto] RK1, (LSB)MR18= 0xa74f, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
6947 04:42:25.179732 CH1 RK1: MR19=C0C, MR18=A74F
6948 04:42:25.186289 CH1_RK1: MR19=0xC0C, MR18=0xA74F, DQSOSC=389, MR23=63, INC=390, DEC=260
6949 04:42:25.189723 [RxdqsGatingPostProcess] freq 400
6950 04:42:25.196161 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6951 04:42:25.196245 best DQS0 dly(2T, 0.5T) = (0, 10)
6952 04:42:25.199612 best DQS1 dly(2T, 0.5T) = (0, 10)
6953 04:42:25.203048 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6954 04:42:25.206042 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6955 04:42:25.209334 best DQS0 dly(2T, 0.5T) = (0, 10)
6956 04:42:25.212654 best DQS1 dly(2T, 0.5T) = (0, 10)
6957 04:42:25.216245 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6958 04:42:25.219247 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6959 04:42:25.222645 Pre-setting of DQS Precalculation
6960 04:42:25.229489 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6961 04:42:25.235839 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6962 04:42:25.242461 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6963 04:42:25.242544
6964 04:42:25.242610
6965 04:42:25.245915 [Calibration Summary] 800 Mbps
6966 04:42:25.246040 CH 0, Rank 0
6967 04:42:25.249270 SW Impedance : PASS
6968 04:42:25.249354 DUTY Scan : NO K
6969 04:42:25.252460 ZQ Calibration : PASS
6970 04:42:25.256169 Jitter Meter : NO K
6971 04:42:25.256252 CBT Training : PASS
6972 04:42:25.259528 Write leveling : PASS
6973 04:42:25.262482 RX DQS gating : PASS
6974 04:42:25.262566 RX DQ/DQS(RDDQC) : PASS
6975 04:42:25.265997 TX DQ/DQS : PASS
6976 04:42:25.269081 RX DATLAT : PASS
6977 04:42:25.269164 RX DQ/DQS(Engine): PASS
6978 04:42:25.272427 TX OE : NO K
6979 04:42:25.272510 All Pass.
6980 04:42:25.272577
6981 04:42:25.275845 CH 0, Rank 1
6982 04:42:25.275928 SW Impedance : PASS
6983 04:42:25.279301 DUTY Scan : NO K
6984 04:42:25.282776 ZQ Calibration : PASS
6985 04:42:25.282860 Jitter Meter : NO K
6986 04:42:25.285971 CBT Training : PASS
6987 04:42:25.289072 Write leveling : NO K
6988 04:42:25.289155 RX DQS gating : PASS
6989 04:42:25.292473 RX DQ/DQS(RDDQC) : PASS
6990 04:42:25.292556 TX DQ/DQS : PASS
6991 04:42:25.295952 RX DATLAT : PASS
6992 04:42:25.299461 RX DQ/DQS(Engine): PASS
6993 04:42:25.299544 TX OE : NO K
6994 04:42:25.302511 All Pass.
6995 04:42:25.302594
6996 04:42:25.302659 CH 1, Rank 0
6997 04:42:25.305631 SW Impedance : PASS
6998 04:42:25.305715 DUTY Scan : NO K
6999 04:42:25.309128 ZQ Calibration : PASS
7000 04:42:25.312400 Jitter Meter : NO K
7001 04:42:25.312483 CBT Training : PASS
7002 04:42:25.315749 Write leveling : PASS
7003 04:42:25.319155 RX DQS gating : PASS
7004 04:42:25.319239 RX DQ/DQS(RDDQC) : PASS
7005 04:42:25.322562 TX DQ/DQS : PASS
7006 04:42:25.325879 RX DATLAT : PASS
7007 04:42:25.325985 RX DQ/DQS(Engine): PASS
7008 04:42:25.329362 TX OE : NO K
7009 04:42:25.329445 All Pass.
7010 04:42:25.329511
7011 04:42:25.332376 CH 1, Rank 1
7012 04:42:25.332459 SW Impedance : PASS
7013 04:42:25.335765 DUTY Scan : NO K
7014 04:42:25.339200 ZQ Calibration : PASS
7015 04:42:25.339283 Jitter Meter : NO K
7016 04:42:25.342582 CBT Training : PASS
7017 04:42:25.342665 Write leveling : NO K
7018 04:42:25.345823 RX DQS gating : PASS
7019 04:42:25.349323 RX DQ/DQS(RDDQC) : PASS
7020 04:42:25.349406 TX DQ/DQS : PASS
7021 04:42:25.352894 RX DATLAT : PASS
7022 04:42:25.356114 RX DQ/DQS(Engine): PASS
7023 04:42:25.356197 TX OE : NO K
7024 04:42:25.359404 All Pass.
7025 04:42:25.359487
7026 04:42:25.359552 DramC Write-DBI off
7027 04:42:25.362580 PER_BANK_REFRESH: Hybrid Mode
7028 04:42:25.362663 TX_TRACKING: ON
7029 04:42:25.372579 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7030 04:42:25.375784 [FAST_K] Save calibration result to emmc
7031 04:42:25.379257 dramc_set_vcore_voltage set vcore to 725000
7032 04:42:25.382362 Read voltage for 1600, 0
7033 04:42:25.382444 Vio18 = 0
7034 04:42:25.385730 Vcore = 725000
7035 04:42:25.385814 Vdram = 0
7036 04:42:25.385880 Vddq = 0
7037 04:42:25.389366 Vmddr = 0
7038 04:42:25.392545 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7039 04:42:25.399008 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7040 04:42:25.399092 MEM_TYPE=3, freq_sel=13
7041 04:42:25.402345 sv_algorithm_assistance_LP4_3733
7042 04:42:25.408859 ============ PULL DRAM RESETB DOWN ============
7043 04:42:25.412360 ========== PULL DRAM RESETB DOWN end =========
7044 04:42:25.415817 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7045 04:42:25.419110 ===================================
7046 04:42:25.422156 LPDDR4 DRAM CONFIGURATION
7047 04:42:25.425655 ===================================
7048 04:42:25.428971 EX_ROW_EN[0] = 0x0
7049 04:42:25.429055 EX_ROW_EN[1] = 0x0
7050 04:42:25.432073 LP4Y_EN = 0x0
7051 04:42:25.432155 WORK_FSP = 0x1
7052 04:42:25.435573 WL = 0x5
7053 04:42:25.435657 RL = 0x5
7054 04:42:25.438457 BL = 0x2
7055 04:42:25.438540 RPST = 0x0
7056 04:42:25.441889 RD_PRE = 0x0
7057 04:42:25.442023 WR_PRE = 0x1
7058 04:42:25.445289 WR_PST = 0x1
7059 04:42:25.445372 DBI_WR = 0x0
7060 04:42:25.448695 DBI_RD = 0x0
7061 04:42:25.448779 OTF = 0x1
7062 04:42:25.451683 ===================================
7063 04:42:25.455196 ===================================
7064 04:42:25.458620 ANA top config
7065 04:42:25.461735 ===================================
7066 04:42:25.465142 DLL_ASYNC_EN = 0
7067 04:42:25.465229 ALL_SLAVE_EN = 0
7068 04:42:25.468585 NEW_RANK_MODE = 1
7069 04:42:25.471619 DLL_IDLE_MODE = 1
7070 04:42:25.475062 LP45_APHY_COMB_EN = 1
7071 04:42:25.475144 TX_ODT_DIS = 0
7072 04:42:25.478332 NEW_8X_MODE = 1
7073 04:42:25.481651 ===================================
7074 04:42:25.485174 ===================================
7075 04:42:25.488565 data_rate = 3200
7076 04:42:25.491555 CKR = 1
7077 04:42:25.494991 DQ_P2S_RATIO = 8
7078 04:42:25.498297 ===================================
7079 04:42:25.501647 CA_P2S_RATIO = 8
7080 04:42:25.501730 DQ_CA_OPEN = 0
7081 04:42:25.504985 DQ_SEMI_OPEN = 0
7082 04:42:25.508401 CA_SEMI_OPEN = 0
7083 04:42:25.511433 CA_FULL_RATE = 0
7084 04:42:25.514942 DQ_CKDIV4_EN = 0
7085 04:42:25.518438 CA_CKDIV4_EN = 0
7086 04:42:25.518521 CA_PREDIV_EN = 0
7087 04:42:25.521612 PH8_DLY = 12
7088 04:42:25.524996 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7089 04:42:25.528516 DQ_AAMCK_DIV = 4
7090 04:42:25.531587 CA_AAMCK_DIV = 4
7091 04:42:25.534874 CA_ADMCK_DIV = 4
7092 04:42:25.534957 DQ_TRACK_CA_EN = 0
7093 04:42:25.537842 CA_PICK = 1600
7094 04:42:25.541366 CA_MCKIO = 1600
7095 04:42:25.544617 MCKIO_SEMI = 0
7096 04:42:25.548032 PLL_FREQ = 3068
7097 04:42:25.551264 DQ_UI_PI_RATIO = 32
7098 04:42:25.554431 CA_UI_PI_RATIO = 0
7099 04:42:25.558065 ===================================
7100 04:42:25.561297 ===================================
7101 04:42:25.561380 memory_type:LPDDR4
7102 04:42:25.564492 GP_NUM : 10
7103 04:42:25.568116 SRAM_EN : 1
7104 04:42:25.568198 MD32_EN : 0
7105 04:42:25.571386 ===================================
7106 04:42:25.574378 [ANA_INIT] >>>>>>>>>>>>>>
7107 04:42:25.577787 <<<<<< [CONFIGURE PHASE]: ANA_TX
7108 04:42:25.581229 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7109 04:42:25.584441 ===================================
7110 04:42:25.587920 data_rate = 3200,PCW = 0X7600
7111 04:42:25.591383 ===================================
7112 04:42:25.594358 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7113 04:42:25.597856 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7114 04:42:25.604301 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7115 04:42:25.607725 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7116 04:42:25.611266 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7117 04:42:25.614587 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7118 04:42:25.617898 [ANA_INIT] flow start
7119 04:42:25.621060 [ANA_INIT] PLL >>>>>>>>
7120 04:42:25.621143 [ANA_INIT] PLL <<<<<<<<
7121 04:42:25.624434 [ANA_INIT] MIDPI >>>>>>>>
7122 04:42:25.627571 [ANA_INIT] MIDPI <<<<<<<<
7123 04:42:25.631150 [ANA_INIT] DLL >>>>>>>>
7124 04:42:25.631233 [ANA_INIT] DLL <<<<<<<<
7125 04:42:25.634692 [ANA_INIT] flow end
7126 04:42:25.638067 ============ LP4 DIFF to SE enter ============
7127 04:42:25.641043 ============ LP4 DIFF to SE exit ============
7128 04:42:25.644118 [ANA_INIT] <<<<<<<<<<<<<
7129 04:42:25.647450 [Flow] Enable top DCM control >>>>>
7130 04:42:25.651241 [Flow] Enable top DCM control <<<<<
7131 04:42:25.654110 Enable DLL master slave shuffle
7132 04:42:25.660859 ==============================================================
7133 04:42:25.660959 Gating Mode config
7134 04:42:25.667318 ==============================================================
7135 04:42:25.667401 Config description:
7136 04:42:25.677498 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7137 04:42:25.684411 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7138 04:42:25.691119 SELPH_MODE 0: By rank 1: By Phase
7139 04:42:25.694000 ==============================================================
7140 04:42:25.697526 GAT_TRACK_EN = 1
7141 04:42:25.700944 RX_GATING_MODE = 2
7142 04:42:25.704407 RX_GATING_TRACK_MODE = 2
7143 04:42:25.707391 SELPH_MODE = 1
7144 04:42:25.710600 PICG_EARLY_EN = 1
7145 04:42:25.714056 VALID_LAT_VALUE = 1
7146 04:42:25.717751 ==============================================================
7147 04:42:25.720601 Enter into Gating configuration >>>>
7148 04:42:25.724332 Exit from Gating configuration <<<<
7149 04:42:25.727702 Enter into DVFS_PRE_config >>>>>
7150 04:42:25.740887 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7151 04:42:25.744228 Exit from DVFS_PRE_config <<<<<
7152 04:42:25.744311 Enter into PICG configuration >>>>
7153 04:42:25.747722 Exit from PICG configuration <<<<
7154 04:42:25.750767 [RX_INPUT] configuration >>>>>
7155 04:42:25.754208 [RX_INPUT] configuration <<<<<
7156 04:42:25.760912 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7157 04:42:25.764195 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7158 04:42:25.770970 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7159 04:42:25.777439 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7160 04:42:25.784200 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7161 04:42:25.791015 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7162 04:42:25.793864 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7163 04:42:25.797368 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7164 04:42:25.800825 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7165 04:42:25.807411 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7166 04:42:25.810445 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7167 04:42:25.813800 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7168 04:42:25.817092 ===================================
7169 04:42:25.820233 LPDDR4 DRAM CONFIGURATION
7170 04:42:25.823755 ===================================
7171 04:42:25.827152 EX_ROW_EN[0] = 0x0
7172 04:42:25.827235 EX_ROW_EN[1] = 0x0
7173 04:42:25.830172 LP4Y_EN = 0x0
7174 04:42:25.830255 WORK_FSP = 0x1
7175 04:42:25.833675 WL = 0x5
7176 04:42:25.833783 RL = 0x5
7177 04:42:25.836951 BL = 0x2
7178 04:42:25.837034 RPST = 0x0
7179 04:42:25.840506 RD_PRE = 0x0
7180 04:42:25.840589 WR_PRE = 0x1
7181 04:42:25.843461 WR_PST = 0x1
7182 04:42:25.843544 DBI_WR = 0x0
7183 04:42:25.846879 DBI_RD = 0x0
7184 04:42:25.846961 OTF = 0x1
7185 04:42:25.850440 ===================================
7186 04:42:25.853755 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7187 04:42:25.860486 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7188 04:42:25.863747 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7189 04:42:25.866988 ===================================
7190 04:42:25.870455 LPDDR4 DRAM CONFIGURATION
7191 04:42:25.873519 ===================================
7192 04:42:25.873602 EX_ROW_EN[0] = 0x10
7193 04:42:25.876797 EX_ROW_EN[1] = 0x0
7194 04:42:25.880477 LP4Y_EN = 0x0
7195 04:42:25.880560 WORK_FSP = 0x1
7196 04:42:25.883396 WL = 0x5
7197 04:42:25.883478 RL = 0x5
7198 04:42:25.887019 BL = 0x2
7199 04:42:25.887102 RPST = 0x0
7200 04:42:25.890522 RD_PRE = 0x0
7201 04:42:25.890605 WR_PRE = 0x1
7202 04:42:25.893442 WR_PST = 0x1
7203 04:42:25.893525 DBI_WR = 0x0
7204 04:42:25.896662 DBI_RD = 0x0
7205 04:42:25.896745 OTF = 0x1
7206 04:42:25.900044 ===================================
7207 04:42:25.906991 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7208 04:42:25.907075 ==
7209 04:42:25.910456 Dram Type= 6, Freq= 0, CH_0, rank 0
7210 04:42:25.913418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7211 04:42:25.916959 ==
7212 04:42:25.917042 [Duty_Offset_Calibration]
7213 04:42:25.920389 B0:2 B1:0 CA:1
7214 04:42:25.920472
7215 04:42:25.923572 [DutyScan_Calibration_Flow] k_type=0
7216 04:42:25.931249
7217 04:42:25.931332 ==CLK 0==
7218 04:42:25.934695 Final CLK duty delay cell = -4
7219 04:42:25.938049 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7220 04:42:25.941361 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7221 04:42:25.944874 [-4] AVG Duty = 4937%(X100)
7222 04:42:25.944957
7223 04:42:25.947800 CH0 CLK Duty spec in!! Max-Min= 187%
7224 04:42:25.951198 [DutyScan_Calibration_Flow] ====Done====
7225 04:42:25.951280
7226 04:42:25.954659 [DutyScan_Calibration_Flow] k_type=1
7227 04:42:25.970863
7228 04:42:25.970949 ==DQS 0 ==
7229 04:42:25.974346 Final DQS duty delay cell = 0
7230 04:42:25.977173 [0] MAX Duty = 5249%(X100), DQS PI = 32
7231 04:42:25.980625 [0] MIN Duty = 4969%(X100), DQS PI = 0
7232 04:42:25.980708 [0] AVG Duty = 5109%(X100)
7233 04:42:25.983870
7234 04:42:25.983952 ==DQS 1 ==
7235 04:42:25.987127 Final DQS duty delay cell = -4
7236 04:42:25.990456 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7237 04:42:25.993974 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7238 04:42:25.997290 [-4] AVG Duty = 4984%(X100)
7239 04:42:25.997374
7240 04:42:26.000437 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7241 04:42:26.000521
7242 04:42:26.003898 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7243 04:42:26.007424 [DutyScan_Calibration_Flow] ====Done====
7244 04:42:26.007508
7245 04:42:26.010387 [DutyScan_Calibration_Flow] k_type=3
7246 04:42:26.028193
7247 04:42:26.028277 ==DQM 0 ==
7248 04:42:26.031470 Final DQM duty delay cell = 0
7249 04:42:26.034800 [0] MAX Duty = 5093%(X100), DQS PI = 26
7250 04:42:26.037833 [0] MIN Duty = 4844%(X100), DQS PI = 0
7251 04:42:26.041148 [0] AVG Duty = 4968%(X100)
7252 04:42:26.041257
7253 04:42:26.041352 ==DQM 1 ==
7254 04:42:26.044526 Final DQM duty delay cell = 0
7255 04:42:26.047985 [0] MAX Duty = 5280%(X100), DQS PI = 46
7256 04:42:26.051486 [0] MIN Duty = 5031%(X100), DQS PI = 10
7257 04:42:26.054304 [0] AVG Duty = 5155%(X100)
7258 04:42:26.054387
7259 04:42:26.057656 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7260 04:42:26.057765
7261 04:42:26.061225 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7262 04:42:26.064692 [DutyScan_Calibration_Flow] ====Done====
7263 04:42:26.064777
7264 04:42:26.067869 [DutyScan_Calibration_Flow] k_type=2
7265 04:42:26.085489
7266 04:42:26.085572 ==DQ 0 ==
7267 04:42:26.088437 Final DQ duty delay cell = 0
7268 04:42:26.091647 [0] MAX Duty = 5124%(X100), DQS PI = 34
7269 04:42:26.095030 [0] MIN Duty = 5000%(X100), DQS PI = 16
7270 04:42:26.095114 [0] AVG Duty = 5062%(X100)
7271 04:42:26.098645
7272 04:42:26.098728 ==DQ 1 ==
7273 04:42:26.101533 Final DQ duty delay cell = 0
7274 04:42:26.104879 [0] MAX Duty = 4969%(X100), DQS PI = 42
7275 04:42:26.108215 [0] MIN Duty = 4875%(X100), DQS PI = 10
7276 04:42:26.108299 [0] AVG Duty = 4922%(X100)
7277 04:42:26.111745
7278 04:42:26.115113 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7279 04:42:26.115197
7280 04:42:26.118513 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7281 04:42:26.121588 [DutyScan_Calibration_Flow] ====Done====
7282 04:42:26.121674 ==
7283 04:42:26.125121 Dram Type= 6, Freq= 0, CH_1, rank 0
7284 04:42:26.128414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7285 04:42:26.128502 ==
7286 04:42:26.132111 [Duty_Offset_Calibration]
7287 04:42:26.132194 B0:0 B1:-1 CA:2
7288 04:42:26.132261
7289 04:42:26.135326 [DutyScan_Calibration_Flow] k_type=0
7290 04:42:26.145477
7291 04:42:26.145560 ==CLK 0==
7292 04:42:26.148782 Final CLK duty delay cell = 0
7293 04:42:26.152266 [0] MAX Duty = 5156%(X100), DQS PI = 40
7294 04:42:26.155266 [0] MIN Duty = 4906%(X100), DQS PI = 14
7295 04:42:26.158554 [0] AVG Duty = 5031%(X100)
7296 04:42:26.158635
7297 04:42:26.161917 CH1 CLK Duty spec in!! Max-Min= 250%
7298 04:42:26.165550 [DutyScan_Calibration_Flow] ====Done====
7299 04:42:26.165631
7300 04:42:26.168448 [DutyScan_Calibration_Flow] k_type=1
7301 04:42:26.185198
7302 04:42:26.185280 ==DQS 0 ==
7303 04:42:26.188473 Final DQS duty delay cell = 0
7304 04:42:26.192301 [0] MAX Duty = 5062%(X100), DQS PI = 8
7305 04:42:26.195189 [0] MIN Duty = 4969%(X100), DQS PI = 50
7306 04:42:26.195271 [0] AVG Duty = 5015%(X100)
7307 04:42:26.195336
7308 04:42:26.198616 ==DQS 1 ==
7309 04:42:26.202085 Final DQS duty delay cell = 0
7310 04:42:26.205475 [0] MAX Duty = 5187%(X100), DQS PI = 28
7311 04:42:26.208804 [0] MIN Duty = 4844%(X100), DQS PI = 2
7312 04:42:26.208886 [0] AVG Duty = 5015%(X100)
7313 04:42:26.208951
7314 04:42:26.215459 CH1 DQS 0 Duty spec in!! Max-Min= 93%
7315 04:42:26.215541
7316 04:42:26.218568 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7317 04:42:26.221887 [DutyScan_Calibration_Flow] ====Done====
7318 04:42:26.222010
7319 04:42:26.225493 [DutyScan_Calibration_Flow] k_type=3
7320 04:42:26.242724
7321 04:42:26.242806 ==DQM 0 ==
7322 04:42:26.245831 Final DQM duty delay cell = 4
7323 04:42:26.249269 [4] MAX Duty = 5156%(X100), DQS PI = 24
7324 04:42:26.253006 [4] MIN Duty = 4969%(X100), DQS PI = 2
7325 04:42:26.253088 [4] AVG Duty = 5062%(X100)
7326 04:42:26.256053
7327 04:42:26.256134 ==DQM 1 ==
7328 04:42:26.259557 Final DQM duty delay cell = 0
7329 04:42:26.262823 [0] MAX Duty = 5312%(X100), DQS PI = 26
7330 04:42:26.266242 [0] MIN Duty = 4907%(X100), DQS PI = 2
7331 04:42:26.266324 [0] AVG Duty = 5109%(X100)
7332 04:42:26.269175
7333 04:42:26.272554 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7334 04:42:26.272636
7335 04:42:26.275935 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7336 04:42:26.279254 [DutyScan_Calibration_Flow] ====Done====
7337 04:42:26.279362
7338 04:42:26.282680 [DutyScan_Calibration_Flow] k_type=2
7339 04:42:26.299712
7340 04:42:26.299793 ==DQ 0 ==
7341 04:42:26.303102 Final DQ duty delay cell = 0
7342 04:42:26.305946 [0] MAX Duty = 5093%(X100), DQS PI = 22
7343 04:42:26.309531 [0] MIN Duty = 4969%(X100), DQS PI = 0
7344 04:42:26.309613 [0] AVG Duty = 5031%(X100)
7345 04:42:26.309677
7346 04:42:26.312875 ==DQ 1 ==
7347 04:42:26.316236 Final DQ duty delay cell = 0
7348 04:42:26.319734 [0] MAX Duty = 5094%(X100), DQS PI = 32
7349 04:42:26.322658 [0] MIN Duty = 4813%(X100), DQS PI = 2
7350 04:42:26.322740 [0] AVG Duty = 4953%(X100)
7351 04:42:26.322805
7352 04:42:26.326005 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7353 04:42:26.326090
7354 04:42:26.329509 CH1 DQ 1 Duty spec in!! Max-Min= 281%
7355 04:42:26.335871 [DutyScan_Calibration_Flow] ====Done====
7356 04:42:26.339474 nWR fixed to 30
7357 04:42:26.339561 [ModeRegInit_LP4] CH0 RK0
7358 04:42:26.342534 [ModeRegInit_LP4] CH0 RK1
7359 04:42:26.345844 [ModeRegInit_LP4] CH1 RK0
7360 04:42:26.345925 [ModeRegInit_LP4] CH1 RK1
7361 04:42:26.349376 match AC timing 5
7362 04:42:26.352374 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7363 04:42:26.359047 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7364 04:42:26.362586 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7365 04:42:26.368950 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7366 04:42:26.372442 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7367 04:42:26.372524 [MiockJmeterHQA]
7368 04:42:26.372589
7369 04:42:26.375898 [DramcMiockJmeter] u1RxGatingPI = 0
7370 04:42:26.379160 0 : 4252, 4027
7371 04:42:26.379272 4 : 4252, 4027
7372 04:42:26.379366 8 : 4255, 4029
7373 04:42:26.382570 12 : 4252, 4027
7374 04:42:26.382653 16 : 4252, 4027
7375 04:42:26.385662 20 : 4363, 4138
7376 04:42:26.385744 24 : 4253, 4026
7377 04:42:26.389052 28 : 4363, 4137
7378 04:42:26.389134 32 : 4253, 4026
7379 04:42:26.392571 36 : 4253, 4027
7380 04:42:26.392653 40 : 4252, 4027
7381 04:42:26.392718 44 : 4252, 4027
7382 04:42:26.395918 48 : 4366, 4140
7383 04:42:26.396001 52 : 4365, 4140
7384 04:42:26.399124 56 : 4255, 4029
7385 04:42:26.399207 60 : 4254, 4029
7386 04:42:26.402446 64 : 4361, 4138
7387 04:42:26.402528 68 : 4250, 4027
7388 04:42:26.405673 72 : 4363, 4140
7389 04:42:26.405755 76 : 4250, 4027
7390 04:42:26.405821 80 : 4250, 4027
7391 04:42:26.409193 84 : 4250, 4026
7392 04:42:26.409276 88 : 4252, 3669
7393 04:42:26.412202 92 : 4361, 0
7394 04:42:26.412314 96 : 4363, 0
7395 04:42:26.412406 100 : 4250, 0
7396 04:42:26.415672 104 : 4363, 0
7397 04:42:26.415755 108 : 4361, 0
7398 04:42:26.418927 112 : 4250, 0
7399 04:42:26.419012 116 : 4250, 0
7400 04:42:26.419081 120 : 4250, 0
7401 04:42:26.422497 124 : 4361, 0
7402 04:42:26.422582 128 : 4250, 0
7403 04:42:26.422650 132 : 4251, 0
7404 04:42:26.425860 136 : 4249, 0
7405 04:42:26.425968 140 : 4253, 0
7406 04:42:26.429001 144 : 4250, 0
7407 04:42:26.429086 148 : 4250, 0
7408 04:42:26.429154 152 : 4255, 0
7409 04:42:26.432438 156 : 4360, 0
7410 04:42:26.432523 160 : 4361, 0
7411 04:42:26.435884 164 : 4250, 0
7412 04:42:26.435969 168 : 4250, 0
7413 04:42:26.436037 172 : 4250, 0
7414 04:42:26.439317 176 : 4363, 0
7415 04:42:26.439402 180 : 4255, 0
7416 04:42:26.439470 184 : 4250, 0
7417 04:42:26.442551 188 : 4361, 0
7418 04:42:26.442636 192 : 4250, 0
7419 04:42:26.445641 196 : 4250, 0
7420 04:42:26.445726 200 : 4250, 1
7421 04:42:26.445794 204 : 4253, 2040
7422 04:42:26.449051 208 : 4250, 4027
7423 04:42:26.449136 212 : 4250, 4027
7424 04:42:26.452518 216 : 4360, 4137
7425 04:42:26.452603 220 : 4250, 4027
7426 04:42:26.455901 224 : 4361, 4137
7427 04:42:26.455986 228 : 4360, 4137
7428 04:42:26.459385 232 : 4250, 4027
7429 04:42:26.459470 236 : 4250, 4027
7430 04:42:26.462226 240 : 4363, 4138
7431 04:42:26.462310 244 : 4250, 4027
7432 04:42:26.465837 248 : 4250, 4026
7433 04:42:26.465921 252 : 4252, 4029
7434 04:42:26.469206 256 : 4252, 4029
7435 04:42:26.469290 260 : 4253, 4029
7436 04:42:26.472435 264 : 4361, 4138
7437 04:42:26.472520 268 : 4255, 4029
7438 04:42:26.472588 272 : 4250, 4027
7439 04:42:26.475509 276 : 4255, 4030
7440 04:42:26.475594 280 : 4363, 4140
7441 04:42:26.478938 284 : 4363, 4138
7442 04:42:26.479023 288 : 4250, 4027
7443 04:42:26.482721 292 : 4363, 4140
7444 04:42:26.482806 296 : 4250, 4027
7445 04:42:26.485987 300 : 4250, 4027
7446 04:42:26.486072 304 : 4252, 4029
7447 04:42:26.488902 308 : 4252, 4030
7448 04:42:26.488988 312 : 4253, 4005
7449 04:42:26.492242 316 : 4361, 2344
7450 04:42:26.492327 320 : 4255, 40
7451 04:42:26.492394
7452 04:42:26.495568 MIOCK jitter meter ch=0
7453 04:42:26.495652
7454 04:42:26.498963 1T = (320-92) = 228 dly cells
7455 04:42:26.502254 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7456 04:42:26.502339 ==
7457 04:42:26.506107 Dram Type= 6, Freq= 0, CH_0, rank 0
7458 04:42:26.512408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7459 04:42:26.512492 ==
7460 04:42:26.515788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7461 04:42:26.519440 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7462 04:42:26.526082 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7463 04:42:26.532099 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7464 04:42:26.539499 [CA 0] Center 42 (12~72) winsize 61
7465 04:42:26.542964 [CA 1] Center 42 (12~72) winsize 61
7466 04:42:26.546201 [CA 2] Center 37 (7~67) winsize 61
7467 04:42:26.549521 [CA 3] Center 37 (7~67) winsize 61
7468 04:42:26.553175 [CA 4] Center 36 (6~66) winsize 61
7469 04:42:26.556081 [CA 5] Center 35 (5~65) winsize 61
7470 04:42:26.556165
7471 04:42:26.559571 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7472 04:42:26.559655
7473 04:42:26.562943 [CATrainingPosCal] consider 1 rank data
7474 04:42:26.566283 u2DelayCellTimex100 = 285/100 ps
7475 04:42:26.569692 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7476 04:42:26.576229 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7477 04:42:26.579728 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7478 04:42:26.583193 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7479 04:42:26.586069 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7480 04:42:26.589898 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7481 04:42:26.590005
7482 04:42:26.593210 CA PerBit enable=1, Macro0, CA PI delay=35
7483 04:42:26.593294
7484 04:42:26.596276 [CBTSetCACLKResult] CA Dly = 35
7485 04:42:26.596399 CS Dly: 9 (0~40)
7486 04:42:26.603063 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7487 04:42:26.606431 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7488 04:42:26.606534 ==
7489 04:42:26.609427 Dram Type= 6, Freq= 0, CH_0, rank 1
7490 04:42:26.613189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7491 04:42:26.613274 ==
7492 04:42:26.619564 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7493 04:42:26.623039 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7494 04:42:26.629651 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7495 04:42:26.632646 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7496 04:42:26.643051 [CA 0] Center 43 (13~73) winsize 61
7497 04:42:26.646090 [CA 1] Center 43 (13~73) winsize 61
7498 04:42:26.649399 [CA 2] Center 37 (8~67) winsize 60
7499 04:42:26.652783 [CA 3] Center 38 (8~68) winsize 61
7500 04:42:26.656410 [CA 4] Center 36 (6~67) winsize 62
7501 04:42:26.659410 [CA 5] Center 36 (7~66) winsize 60
7502 04:42:26.659495
7503 04:42:26.662993 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7504 04:42:26.663077
7505 04:42:26.666365 [CATrainingPosCal] consider 2 rank data
7506 04:42:26.669201 u2DelayCellTimex100 = 285/100 ps
7507 04:42:26.672637 CA0 delay=42 (13~72),Diff = 6 PI (20 cell)
7508 04:42:26.679479 CA1 delay=42 (13~72),Diff = 6 PI (20 cell)
7509 04:42:26.682433 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
7510 04:42:26.685889 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
7511 04:42:26.689680 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7512 04:42:26.692624 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7513 04:42:26.692775
7514 04:42:26.695991 CA PerBit enable=1, Macro0, CA PI delay=36
7515 04:42:26.696075
7516 04:42:26.699042 [CBTSetCACLKResult] CA Dly = 36
7517 04:42:26.702345 CS Dly: 10 (0~43)
7518 04:42:26.705633 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7519 04:42:26.709174 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7520 04:42:26.709258
7521 04:42:26.712542 ----->DramcWriteLeveling(PI) begin...
7522 04:42:26.712627 ==
7523 04:42:26.715927 Dram Type= 6, Freq= 0, CH_0, rank 0
7524 04:42:26.722703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7525 04:42:26.722788 ==
7526 04:42:26.726269 Write leveling (Byte 0): 37 => 37
7527 04:42:26.726353 Write leveling (Byte 1): 29 => 29
7528 04:42:26.729434 DramcWriteLeveling(PI) end<-----
7529 04:42:26.729517
7530 04:42:26.729583 ==
7531 04:42:26.732335 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 04:42:26.739337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 04:42:26.739422 ==
7534 04:42:26.742795 [Gating] SW mode calibration
7535 04:42:26.749171 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7536 04:42:26.752608 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7537 04:42:26.759203 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7538 04:42:26.762496 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7539 04:42:26.765963 1 4 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
7540 04:42:26.772293 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7541 04:42:26.775754 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7542 04:42:26.778788 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7543 04:42:26.785452 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7544 04:42:26.788974 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7545 04:42:26.792079 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7546 04:42:26.795502 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7547 04:42:26.802090 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
7548 04:42:26.805330 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7549 04:42:26.808687 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7550 04:42:26.815306 1 5 20 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
7551 04:42:26.818696 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7552 04:42:26.821902 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7553 04:42:26.828321 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 04:42:26.831941 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7555 04:42:26.835155 1 6 8 | B1->B0 | 2323 4140 | 0 1 | (0 0) (0 0)
7556 04:42:26.841705 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7557 04:42:26.845267 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7558 04:42:26.848676 1 6 20 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
7559 04:42:26.855065 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7560 04:42:26.858477 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7561 04:42:26.861686 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7562 04:42:26.868438 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 04:42:26.871480 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7564 04:42:26.874887 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7565 04:42:26.881635 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7566 04:42:26.884689 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7567 04:42:26.888229 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 04:42:26.895125 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 04:42:26.898106 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 04:42:26.901414 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 04:42:26.907836 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 04:42:26.911269 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 04:42:26.914756 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 04:42:26.921337 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 04:42:26.924616 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 04:42:26.927991 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 04:42:26.934488 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 04:42:26.937793 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 04:42:26.941101 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7580 04:42:26.947657 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7581 04:42:26.951225 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7582 04:42:26.954502 Total UI for P1: 0, mck2ui 16
7583 04:42:26.957785 best dqsien dly found for B0: ( 1, 9, 10)
7584 04:42:26.961229 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7585 04:42:26.964558 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 04:42:26.967835 Total UI for P1: 0, mck2ui 16
7587 04:42:26.971097 best dqsien dly found for B1: ( 1, 9, 20)
7588 04:42:26.974617 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7589 04:42:26.981368 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7590 04:42:26.981466
7591 04:42:26.984806 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7592 04:42:26.987781 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7593 04:42:26.991302 [Gating] SW calibration Done
7594 04:42:26.991406 ==
7595 04:42:26.994641 Dram Type= 6, Freq= 0, CH_0, rank 0
7596 04:42:26.997746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 04:42:26.997850 ==
7598 04:42:27.001119 RX Vref Scan: 0
7599 04:42:27.001203
7600 04:42:27.001265 RX Vref 0 -> 0, step: 1
7601 04:42:27.001323
7602 04:42:27.004575 RX Delay 0 -> 252, step: 8
7603 04:42:27.007775 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7604 04:42:27.011171 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7605 04:42:27.017879 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7606 04:42:27.020829 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7607 04:42:27.024562 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7608 04:42:27.027827 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7609 04:42:27.031146 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7610 04:42:27.037698 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7611 04:42:27.041193 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7612 04:42:27.044506 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7613 04:42:27.047474 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7614 04:42:27.050956 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7615 04:42:27.057862 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7616 04:42:27.060740 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7617 04:42:27.064168 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7618 04:42:27.067711 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7619 04:42:27.067807 ==
7620 04:42:27.070811 Dram Type= 6, Freq= 0, CH_0, rank 0
7621 04:42:27.077698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 04:42:27.077799 ==
7623 04:42:27.077895 DQS Delay:
7624 04:42:27.077994 DQS0 = 0, DQS1 = 0
7625 04:42:27.080699 DQM Delay:
7626 04:42:27.080796 DQM0 = 138, DQM1 = 126
7627 04:42:27.084143 DQ Delay:
7628 04:42:27.087468 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7629 04:42:27.090951 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7630 04:42:27.093971 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7631 04:42:27.097382 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7632 04:42:27.097483
7633 04:42:27.097573
7634 04:42:27.097668 ==
7635 04:42:27.100521 Dram Type= 6, Freq= 0, CH_0, rank 0
7636 04:42:27.103844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7637 04:42:27.107434 ==
7638 04:42:27.107517
7639 04:42:27.107583
7640 04:42:27.107643 TX Vref Scan disable
7641 04:42:27.110776 == TX Byte 0 ==
7642 04:42:27.114250 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7643 04:42:27.117080 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7644 04:42:27.120522 == TX Byte 1 ==
7645 04:42:27.123761 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7646 04:42:27.127209 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7647 04:42:27.127317 ==
7648 04:42:27.132220 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 04:42:27.137158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 04:42:27.137262 ==
7651 04:42:27.151001
7652 04:42:27.154097 TX Vref early break, caculate TX vref
7653 04:42:27.157698 TX Vref=16, minBit 12, minWin=22, winSum=381
7654 04:42:27.160824 TX Vref=18, minBit 12, minWin=22, winSum=388
7655 04:42:27.164309 TX Vref=20, minBit 7, minWin=23, winSum=393
7656 04:42:27.167382 TX Vref=22, minBit 12, minWin=23, winSum=402
7657 04:42:27.170893 TX Vref=24, minBit 0, minWin=25, winSum=417
7658 04:42:27.177698 TX Vref=26, minBit 4, minWin=25, winSum=424
7659 04:42:27.181090 TX Vref=28, minBit 2, minWin=25, winSum=430
7660 04:42:27.184194 TX Vref=30, minBit 0, minWin=26, winSum=426
7661 04:42:27.187358 TX Vref=32, minBit 0, minWin=25, winSum=414
7662 04:42:27.190600 TX Vref=34, minBit 2, minWin=24, winSum=408
7663 04:42:27.197842 TX Vref=36, minBit 0, minWin=24, winSum=396
7664 04:42:27.201250 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 30
7665 04:42:27.201694
7666 04:42:27.204955 Final TX Range 0 Vref 30
7667 04:42:27.205523
7668 04:42:27.205899 ==
7669 04:42:27.207880 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 04:42:27.211376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 04:42:27.211948 ==
7672 04:42:27.214462
7673 04:42:27.215049
7674 04:42:27.215421 TX Vref Scan disable
7675 04:42:27.221016 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7676 04:42:27.221584 == TX Byte 0 ==
7677 04:42:27.224282 u2DelayCellOfst[0]=10 cells (3 PI)
7678 04:42:27.227609 u2DelayCellOfst[1]=17 cells (5 PI)
7679 04:42:27.231112 u2DelayCellOfst[2]=10 cells (3 PI)
7680 04:42:27.234325 u2DelayCellOfst[3]=10 cells (3 PI)
7681 04:42:27.237896 u2DelayCellOfst[4]=6 cells (2 PI)
7682 04:42:27.240904 u2DelayCellOfst[5]=0 cells (0 PI)
7683 04:42:27.244743 u2DelayCellOfst[6]=17 cells (5 PI)
7684 04:42:27.247514 u2DelayCellOfst[7]=13 cells (4 PI)
7685 04:42:27.250855 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7686 04:42:27.254394 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7687 04:42:27.257761 == TX Byte 1 ==
7688 04:42:27.261140 u2DelayCellOfst[8]=0 cells (0 PI)
7689 04:42:27.264673 u2DelayCellOfst[9]=0 cells (0 PI)
7690 04:42:27.267237 u2DelayCellOfst[10]=6 cells (2 PI)
7691 04:42:27.270898 u2DelayCellOfst[11]=3 cells (1 PI)
7692 04:42:27.271472 u2DelayCellOfst[12]=13 cells (4 PI)
7693 04:42:27.274435 u2DelayCellOfst[13]=13 cells (4 PI)
7694 04:42:27.277814 u2DelayCellOfst[14]=13 cells (4 PI)
7695 04:42:27.280958 u2DelayCellOfst[15]=10 cells (3 PI)
7696 04:42:27.287710 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7697 04:42:27.291186 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7698 04:42:27.291764 DramC Write-DBI on
7699 04:42:27.294295 ==
7700 04:42:27.294761 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 04:42:27.301060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 04:42:27.301528 ==
7703 04:42:27.301898
7704 04:42:27.302293
7705 04:42:27.302628 TX Vref Scan disable
7706 04:42:27.305037 == TX Byte 0 ==
7707 04:42:27.308959 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7708 04:42:27.311990 == TX Byte 1 ==
7709 04:42:27.315357 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7710 04:42:27.318617 DramC Write-DBI off
7711 04:42:27.319116
7712 04:42:27.319672 [DATLAT]
7713 04:42:27.320043 Freq=1600, CH0 RK0
7714 04:42:27.320380
7715 04:42:27.321870 DATLAT Default: 0xf
7716 04:42:27.322372 0, 0xFFFF, sum = 0
7717 04:42:27.325320 1, 0xFFFF, sum = 0
7718 04:42:27.328265 2, 0xFFFF, sum = 0
7719 04:42:27.328743 3, 0xFFFF, sum = 0
7720 04:42:27.331636 4, 0xFFFF, sum = 0
7721 04:42:27.332144 5, 0xFFFF, sum = 0
7722 04:42:27.335294 6, 0xFFFF, sum = 0
7723 04:42:27.335868 7, 0xFFFF, sum = 0
7724 04:42:27.338362 8, 0xFFFF, sum = 0
7725 04:42:27.338835 9, 0xFFFF, sum = 0
7726 04:42:27.341766 10, 0xFFFF, sum = 0
7727 04:42:27.342401 11, 0xFFFF, sum = 0
7728 04:42:27.345139 12, 0xFFFF, sum = 0
7729 04:42:27.345718 13, 0xFFFF, sum = 0
7730 04:42:27.348301 14, 0x0, sum = 1
7731 04:42:27.348773 15, 0x0, sum = 2
7732 04:42:27.351644 16, 0x0, sum = 3
7733 04:42:27.352221 17, 0x0, sum = 4
7734 04:42:27.354750 best_step = 15
7735 04:42:27.355235
7736 04:42:27.355599 ==
7737 04:42:27.357973 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 04:42:27.361379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 04:42:27.361851 ==
7740 04:42:27.364918 RX Vref Scan: 1
7741 04:42:27.365380
7742 04:42:27.365752 Set Vref Range= 24 -> 127
7743 04:42:27.366142
7744 04:42:27.367812 RX Vref 24 -> 127, step: 1
7745 04:42:27.368278
7746 04:42:27.371580 RX Delay 19 -> 252, step: 4
7747 04:42:27.372142
7748 04:42:27.375092 Set Vref, RX VrefLevel [Byte0]: 24
7749 04:42:27.378152 [Byte1]: 24
7750 04:42:27.378747
7751 04:42:27.381471 Set Vref, RX VrefLevel [Byte0]: 25
7752 04:42:27.385096 [Byte1]: 25
7753 04:42:27.385664
7754 04:42:27.387996 Set Vref, RX VrefLevel [Byte0]: 26
7755 04:42:27.391314 [Byte1]: 26
7756 04:42:27.395465
7757 04:42:27.395933 Set Vref, RX VrefLevel [Byte0]: 27
7758 04:42:27.398992 [Byte1]: 27
7759 04:42:27.403304
7760 04:42:27.403860 Set Vref, RX VrefLevel [Byte0]: 28
7761 04:42:27.406327 [Byte1]: 28
7762 04:42:27.410798
7763 04:42:27.411379 Set Vref, RX VrefLevel [Byte0]: 29
7764 04:42:27.414001 [Byte1]: 29
7765 04:42:27.418525
7766 04:42:27.419088 Set Vref, RX VrefLevel [Byte0]: 30
7767 04:42:27.421175 [Byte1]: 30
7768 04:42:27.425904
7769 04:42:27.426408 Set Vref, RX VrefLevel [Byte0]: 31
7770 04:42:27.429075 [Byte1]: 31
7771 04:42:27.433467
7772 04:42:27.434076 Set Vref, RX VrefLevel [Byte0]: 32
7773 04:42:27.436636 [Byte1]: 32
7774 04:42:27.440886
7775 04:42:27.441632 Set Vref, RX VrefLevel [Byte0]: 33
7776 04:42:27.444053 [Byte1]: 33
7777 04:42:27.448213
7778 04:42:27.448777 Set Vref, RX VrefLevel [Byte0]: 34
7779 04:42:27.451897 [Byte1]: 34
7780 04:42:27.455675
7781 04:42:27.456140 Set Vref, RX VrefLevel [Byte0]: 35
7782 04:42:27.459056 [Byte1]: 35
7783 04:42:27.463314
7784 04:42:27.463777 Set Vref, RX VrefLevel [Byte0]: 36
7785 04:42:27.466886 [Byte1]: 36
7786 04:42:27.471375
7787 04:42:27.471944 Set Vref, RX VrefLevel [Byte0]: 37
7788 04:42:27.474366 [Byte1]: 37
7789 04:42:27.478845
7790 04:42:27.479415 Set Vref, RX VrefLevel [Byte0]: 38
7791 04:42:27.481981 [Byte1]: 38
7792 04:42:27.486337
7793 04:42:27.486907 Set Vref, RX VrefLevel [Byte0]: 39
7794 04:42:27.490019 [Byte1]: 39
7795 04:42:27.493892
7796 04:42:27.494391 Set Vref, RX VrefLevel [Byte0]: 40
7797 04:42:27.496830 [Byte1]: 40
7798 04:42:27.501358
7799 04:42:27.501823 Set Vref, RX VrefLevel [Byte0]: 41
7800 04:42:27.504856 [Byte1]: 41
7801 04:42:27.509158
7802 04:42:27.509737 Set Vref, RX VrefLevel [Byte0]: 42
7803 04:42:27.512435 [Byte1]: 42
7804 04:42:27.516819
7805 04:42:27.517382 Set Vref, RX VrefLevel [Byte0]: 43
7806 04:42:27.519585 [Byte1]: 43
7807 04:42:27.524187
7808 04:42:27.524776 Set Vref, RX VrefLevel [Byte0]: 44
7809 04:42:27.527273 [Byte1]: 44
7810 04:42:27.531736
7811 04:42:27.532195 Set Vref, RX VrefLevel [Byte0]: 45
7812 04:42:27.535200 [Byte1]: 45
7813 04:42:27.539469
7814 04:42:27.540040 Set Vref, RX VrefLevel [Byte0]: 46
7815 04:42:27.542838 [Byte1]: 46
7816 04:42:27.546988
7817 04:42:27.547553 Set Vref, RX VrefLevel [Byte0]: 47
7818 04:42:27.550139 [Byte1]: 47
7819 04:42:27.554473
7820 04:42:27.554935 Set Vref, RX VrefLevel [Byte0]: 48
7821 04:42:27.557553 [Byte1]: 48
7822 04:42:27.562089
7823 04:42:27.562656 Set Vref, RX VrefLevel [Byte0]: 49
7824 04:42:27.565388 [Byte1]: 49
7825 04:42:27.569565
7826 04:42:27.570163 Set Vref, RX VrefLevel [Byte0]: 50
7827 04:42:27.572856 [Byte1]: 50
7828 04:42:27.577396
7829 04:42:27.577994 Set Vref, RX VrefLevel [Byte0]: 51
7830 04:42:27.580482 [Byte1]: 51
7831 04:42:27.584949
7832 04:42:27.585519 Set Vref, RX VrefLevel [Byte0]: 52
7833 04:42:27.587867 [Byte1]: 52
7834 04:42:27.592316
7835 04:42:27.592974 Set Vref, RX VrefLevel [Byte0]: 53
7836 04:42:27.595251 [Byte1]: 53
7837 04:42:27.599983
7838 04:42:27.600550 Set Vref, RX VrefLevel [Byte0]: 54
7839 04:42:27.603532 [Byte1]: 54
7840 04:42:27.607494
7841 04:42:27.608098 Set Vref, RX VrefLevel [Byte0]: 55
7842 04:42:27.610729 [Byte1]: 55
7843 04:42:27.615129
7844 04:42:27.615696 Set Vref, RX VrefLevel [Byte0]: 56
7845 04:42:27.618613 [Byte1]: 56
7846 04:42:27.622563
7847 04:42:27.623182 Set Vref, RX VrefLevel [Byte0]: 57
7848 04:42:27.625765 [Byte1]: 57
7849 04:42:27.630130
7850 04:42:27.630601 Set Vref, RX VrefLevel [Byte0]: 58
7851 04:42:27.633638 [Byte1]: 58
7852 04:42:27.637977
7853 04:42:27.638564 Set Vref, RX VrefLevel [Byte0]: 59
7854 04:42:27.640886 [Byte1]: 59
7855 04:42:27.645505
7856 04:42:27.646113 Set Vref, RX VrefLevel [Byte0]: 60
7857 04:42:27.648860 [Byte1]: 60
7858 04:42:27.653119
7859 04:42:27.653688 Set Vref, RX VrefLevel [Byte0]: 61
7860 04:42:27.656229 [Byte1]: 61
7861 04:42:27.660134
7862 04:42:27.660623 Set Vref, RX VrefLevel [Byte0]: 62
7863 04:42:27.663636 [Byte1]: 62
7864 04:42:27.668145
7865 04:42:27.668722 Set Vref, RX VrefLevel [Byte0]: 63
7866 04:42:27.671431 [Byte1]: 63
7867 04:42:27.675956
7868 04:42:27.676527 Set Vref, RX VrefLevel [Byte0]: 64
7869 04:42:27.678673 [Byte1]: 64
7870 04:42:27.683450
7871 04:42:27.684022 Set Vref, RX VrefLevel [Byte0]: 65
7872 04:42:27.686513 [Byte1]: 65
7873 04:42:27.690863
7874 04:42:27.691430 Set Vref, RX VrefLevel [Byte0]: 66
7875 04:42:27.694145 [Byte1]: 66
7876 04:42:27.698057
7877 04:42:27.698521 Set Vref, RX VrefLevel [Byte0]: 67
7878 04:42:27.701279 [Byte1]: 67
7879 04:42:27.705826
7880 04:42:27.706443 Set Vref, RX VrefLevel [Byte0]: 68
7881 04:42:27.709043 [Byte1]: 68
7882 04:42:27.713352
7883 04:42:27.713815 Set Vref, RX VrefLevel [Byte0]: 69
7884 04:42:27.716432 [Byte1]: 69
7885 04:42:27.720829
7886 04:42:27.721291 Set Vref, RX VrefLevel [Byte0]: 70
7887 04:42:27.724391 [Byte1]: 70
7888 04:42:27.728296
7889 04:42:27.728762 Set Vref, RX VrefLevel [Byte0]: 71
7890 04:42:27.731594 [Byte1]: 71
7891 04:42:27.736307
7892 04:42:27.736866 Set Vref, RX VrefLevel [Byte0]: 72
7893 04:42:27.739356 [Byte1]: 72
7894 04:42:27.743863
7895 04:42:27.744513 Set Vref, RX VrefLevel [Byte0]: 73
7896 04:42:27.746948 [Byte1]: 73
7897 04:42:27.751342
7898 04:42:27.751808 Set Vref, RX VrefLevel [Byte0]: 74
7899 04:42:27.754265 [Byte1]: 74
7900 04:42:27.759082
7901 04:42:27.759644 Set Vref, RX VrefLevel [Byte0]: 75
7902 04:42:27.762185 [Byte1]: 75
7903 04:42:27.766732
7904 04:42:27.767299 Set Vref, RX VrefLevel [Byte0]: 76
7905 04:42:27.769592 [Byte1]: 76
7906 04:42:27.774073
7907 04:42:27.774634 Set Vref, RX VrefLevel [Byte0]: 77
7908 04:42:27.777356 [Byte1]: 77
7909 04:42:27.781902
7910 04:42:27.782500 Final RX Vref Byte 0 = 57 to rank0
7911 04:42:27.784944 Final RX Vref Byte 1 = 60 to rank0
7912 04:42:27.788382 Final RX Vref Byte 0 = 57 to rank1
7913 04:42:27.791816 Final RX Vref Byte 1 = 60 to rank1==
7914 04:42:27.794530 Dram Type= 6, Freq= 0, CH_0, rank 0
7915 04:42:27.801671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7916 04:42:27.802270 ==
7917 04:42:27.802646 DQS Delay:
7918 04:42:27.802992 DQS0 = 0, DQS1 = 0
7919 04:42:27.804750 DQM Delay:
7920 04:42:27.805317 DQM0 = 135, DQM1 = 124
7921 04:42:27.808093 DQ Delay:
7922 04:42:27.811420 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7923 04:42:27.814591 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =144
7924 04:42:27.818149 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7925 04:42:27.821210 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
7926 04:42:27.821793
7927 04:42:27.822198
7928 04:42:27.822545
7929 04:42:27.824695 [DramC_TX_OE_Calibration] TA2
7930 04:42:27.827622 Original DQ_B0 (3 6) =30, OEN = 27
7931 04:42:27.831148 Original DQ_B1 (3 6) =30, OEN = 27
7932 04:42:27.834698 24, 0x0, End_B0=24 End_B1=24
7933 04:42:27.835394 25, 0x0, End_B0=25 End_B1=25
7934 04:42:27.837718 26, 0x0, End_B0=26 End_B1=26
7935 04:42:27.841787 27, 0x0, End_B0=27 End_B1=27
7936 04:42:27.844976 28, 0x0, End_B0=28 End_B1=28
7937 04:42:27.845450 29, 0x0, End_B0=29 End_B1=29
7938 04:42:27.848192 30, 0x0, End_B0=30 End_B1=30
7939 04:42:27.851598 31, 0x4141, End_B0=30 End_B1=30
7940 04:42:27.854684 Byte0 end_step=30 best_step=27
7941 04:42:27.858044 Byte1 end_step=30 best_step=27
7942 04:42:27.861360 Byte0 TX OE(2T, 0.5T) = (3, 3)
7943 04:42:27.861859 Byte1 TX OE(2T, 0.5T) = (3, 3)
7944 04:42:27.864871
7945 04:42:27.865436
7946 04:42:27.871694 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
7947 04:42:27.874815 CH0 RK0: MR19=303, MR18=1B19
7948 04:42:27.881638 CH0_RK0: MR19=0x303, MR18=0x1B19, DQSOSC=396, MR23=63, INC=23, DEC=15
7949 04:42:27.882341
7950 04:42:27.884689 ----->DramcWriteLeveling(PI) begin...
7951 04:42:27.885269 ==
7952 04:42:27.888006 Dram Type= 6, Freq= 0, CH_0, rank 1
7953 04:42:27.891472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 04:42:27.892044 ==
7955 04:42:27.894720 Write leveling (Byte 0): 38 => 38
7956 04:42:27.897759 Write leveling (Byte 1): 29 => 29
7957 04:42:27.901521 DramcWriteLeveling(PI) end<-----
7958 04:42:27.902125
7959 04:42:27.902500 ==
7960 04:42:27.904930 Dram Type= 6, Freq= 0, CH_0, rank 1
7961 04:42:27.907903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7962 04:42:27.908477 ==
7963 04:42:27.911693 [Gating] SW mode calibration
7964 04:42:27.917990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7965 04:42:27.924631 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7966 04:42:27.928019 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7967 04:42:27.931293 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7968 04:42:27.937923 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7969 04:42:27.940976 1 4 12 | B1->B0 | 2423 3232 | 1 0 | (0 0) (0 0)
7970 04:42:27.944596 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7971 04:42:27.951592 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7972 04:42:27.954443 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7973 04:42:27.958138 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7974 04:42:27.964291 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7975 04:42:27.967739 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7976 04:42:27.970946 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7977 04:42:27.978030 1 5 12 | B1->B0 | 3434 2727 | 0 0 | (0 1) (0 0)
7978 04:42:27.981194 1 5 16 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
7979 04:42:27.984942 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7980 04:42:27.991317 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7981 04:42:27.994457 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 04:42:27.998022 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7983 04:42:28.001289 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7984 04:42:28.007972 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7985 04:42:28.011432 1 6 12 | B1->B0 | 3131 4545 | 0 1 | (1 1) (0 0)
7986 04:42:28.014716 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 04:42:28.021348 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 04:42:28.024367 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 04:42:28.027824 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 04:42:28.034635 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 04:42:28.038034 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 04:42:28.041050 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 04:42:28.047661 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7994 04:42:28.051102 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7995 04:42:28.054690 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 04:42:28.060932 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 04:42:28.064637 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 04:42:28.067757 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 04:42:28.074346 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 04:42:28.077699 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 04:42:28.081257 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 04:42:28.088050 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 04:42:28.090730 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 04:42:28.094052 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 04:42:28.101172 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 04:42:28.104695 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 04:42:28.107733 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 04:42:28.114287 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8009 04:42:28.117380 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8010 04:42:28.120627 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8011 04:42:28.127353 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 04:42:28.127931 Total UI for P1: 0, mck2ui 16
8013 04:42:28.130553 best dqsien dly found for B0: ( 1, 9, 12)
8014 04:42:28.134040 Total UI for P1: 0, mck2ui 16
8015 04:42:28.137362 best dqsien dly found for B1: ( 1, 9, 14)
8016 04:42:28.140621 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8017 04:42:28.147328 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8018 04:42:28.147901
8019 04:42:28.150526 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8020 04:42:28.154245 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8021 04:42:28.157378 [Gating] SW calibration Done
8022 04:42:28.157986 ==
8023 04:42:28.160531 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 04:42:28.163771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 04:42:28.164273 ==
8026 04:42:28.167365 RX Vref Scan: 0
8027 04:42:28.168000
8028 04:42:28.168384 RX Vref 0 -> 0, step: 1
8029 04:42:28.168788
8030 04:42:28.170631 RX Delay 0 -> 252, step: 8
8031 04:42:28.174196 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8032 04:42:28.177585 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8033 04:42:28.183953 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8034 04:42:28.187049 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8035 04:42:28.190600 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8036 04:42:28.193805 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8037 04:42:28.197104 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8038 04:42:28.203964 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8039 04:42:28.207517 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8040 04:42:28.210597 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8041 04:42:28.214223 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8042 04:42:28.217266 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8043 04:42:28.223947 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8044 04:42:28.227065 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8045 04:42:28.230412 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8046 04:42:28.233595 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8047 04:42:28.234087 ==
8048 04:42:28.237315 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 04:42:28.243882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 04:42:28.244460 ==
8051 04:42:28.244834 DQS Delay:
8052 04:42:28.247428 DQS0 = 0, DQS1 = 0
8053 04:42:28.248006 DQM Delay:
8054 04:42:28.248377 DQM0 = 136, DQM1 = 125
8055 04:42:28.250218 DQ Delay:
8056 04:42:28.254005 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8057 04:42:28.257268 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8058 04:42:28.260578 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8059 04:42:28.263681 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8060 04:42:28.264151
8061 04:42:28.264579
8062 04:42:28.264944 ==
8063 04:42:28.267045 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 04:42:28.270447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 04:42:28.273816 ==
8066 04:42:28.274419
8067 04:42:28.274864
8068 04:42:28.275217 TX Vref Scan disable
8069 04:42:28.277176 == TX Byte 0 ==
8070 04:42:28.280390 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8071 04:42:28.283611 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8072 04:42:28.286893 == TX Byte 1 ==
8073 04:42:28.290555 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8074 04:42:28.293519 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8075 04:42:28.296701 ==
8076 04:42:28.300153 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 04:42:28.303450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 04:42:28.304035 ==
8079 04:42:28.317897
8080 04:42:28.321315 TX Vref early break, caculate TX vref
8081 04:42:28.324779 TX Vref=16, minBit 8, minWin=22, winSum=391
8082 04:42:28.328245 TX Vref=18, minBit 1, minWin=24, winSum=400
8083 04:42:28.331195 TX Vref=20, minBit 8, minWin=24, winSum=409
8084 04:42:28.334518 TX Vref=22, minBit 0, minWin=25, winSum=414
8085 04:42:28.337890 TX Vref=24, minBit 2, minWin=25, winSum=419
8086 04:42:28.344619 TX Vref=26, minBit 0, minWin=26, winSum=428
8087 04:42:28.348013 TX Vref=28, minBit 0, minWin=26, winSum=430
8088 04:42:28.351472 TX Vref=30, minBit 8, minWin=25, winSum=427
8089 04:42:28.354232 TX Vref=32, minBit 1, minWin=25, winSum=420
8090 04:42:28.357751 TX Vref=34, minBit 2, minWin=24, winSum=409
8091 04:42:28.361245 TX Vref=36, minBit 2, minWin=24, winSum=399
8092 04:42:28.367740 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8093 04:42:28.368322
8094 04:42:28.371221 Final TX Range 0 Vref 28
8095 04:42:28.371804
8096 04:42:28.372178 ==
8097 04:42:28.374564 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 04:42:28.377595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 04:42:28.378099 ==
8100 04:42:28.378481
8101 04:42:28.378828
8102 04:42:28.381179 TX Vref Scan disable
8103 04:42:28.387792 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8104 04:42:28.388369 == TX Byte 0 ==
8105 04:42:28.391474 u2DelayCellOfst[0]=13 cells (4 PI)
8106 04:42:28.394355 u2DelayCellOfst[1]=20 cells (6 PI)
8107 04:42:28.397562 u2DelayCellOfst[2]=13 cells (4 PI)
8108 04:42:28.401177 u2DelayCellOfst[3]=13 cells (4 PI)
8109 04:42:28.403966 u2DelayCellOfst[4]=10 cells (3 PI)
8110 04:42:28.407458 u2DelayCellOfst[5]=0 cells (0 PI)
8111 04:42:28.411254 u2DelayCellOfst[6]=20 cells (6 PI)
8112 04:42:28.414824 u2DelayCellOfst[7]=20 cells (6 PI)
8113 04:42:28.417684 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8114 04:42:28.421180 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8115 04:42:28.424564 == TX Byte 1 ==
8116 04:42:28.428098 u2DelayCellOfst[8]=3 cells (1 PI)
8117 04:42:28.428681 u2DelayCellOfst[9]=0 cells (0 PI)
8118 04:42:28.430717 u2DelayCellOfst[10]=6 cells (2 PI)
8119 04:42:28.434371 u2DelayCellOfst[11]=3 cells (1 PI)
8120 04:42:28.437983 u2DelayCellOfst[12]=13 cells (4 PI)
8121 04:42:28.440958 u2DelayCellOfst[13]=13 cells (4 PI)
8122 04:42:28.444170 u2DelayCellOfst[14]=13 cells (4 PI)
8123 04:42:28.447321 u2DelayCellOfst[15]=10 cells (3 PI)
8124 04:42:28.450702 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8125 04:42:28.457773 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8126 04:42:28.458387 DramC Write-DBI on
8127 04:42:28.458768 ==
8128 04:42:28.461243 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 04:42:28.467549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 04:42:28.468203 ==
8131 04:42:28.468628
8132 04:42:28.469060
8133 04:42:28.469406 TX Vref Scan disable
8134 04:42:28.471228 == TX Byte 0 ==
8135 04:42:28.475205 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8136 04:42:28.477984 == TX Byte 1 ==
8137 04:42:28.481383 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8138 04:42:28.484775 DramC Write-DBI off
8139 04:42:28.485354
8140 04:42:28.485729 [DATLAT]
8141 04:42:28.486115 Freq=1600, CH0 RK1
8142 04:42:28.486497
8143 04:42:28.487816 DATLAT Default: 0xf
8144 04:42:28.488287 0, 0xFFFF, sum = 0
8145 04:42:28.491783 1, 0xFFFF, sum = 0
8146 04:42:28.494666 2, 0xFFFF, sum = 0
8147 04:42:28.495156 3, 0xFFFF, sum = 0
8148 04:42:28.497907 4, 0xFFFF, sum = 0
8149 04:42:28.498576 5, 0xFFFF, sum = 0
8150 04:42:28.501653 6, 0xFFFF, sum = 0
8151 04:42:28.502281 7, 0xFFFF, sum = 0
8152 04:42:28.504982 8, 0xFFFF, sum = 0
8153 04:42:28.505567 9, 0xFFFF, sum = 0
8154 04:42:28.508037 10, 0xFFFF, sum = 0
8155 04:42:28.508626 11, 0xFFFF, sum = 0
8156 04:42:28.511330 12, 0xFFFF, sum = 0
8157 04:42:28.511914 13, 0xFFFF, sum = 0
8158 04:42:28.514716 14, 0x0, sum = 1
8159 04:42:28.515313 15, 0x0, sum = 2
8160 04:42:28.518146 16, 0x0, sum = 3
8161 04:42:28.518733 17, 0x0, sum = 4
8162 04:42:28.521789 best_step = 15
8163 04:42:28.522400
8164 04:42:28.522781 ==
8165 04:42:28.524690 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 04:42:28.528095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 04:42:28.528678 ==
8168 04:42:28.529067 RX Vref Scan: 0
8169 04:42:28.531381
8170 04:42:28.531852 RX Vref 0 -> 0, step: 1
8171 04:42:28.532228
8172 04:42:28.534399 RX Delay 11 -> 252, step: 4
8173 04:42:28.537766 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8174 04:42:28.544875 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8175 04:42:28.548226 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8176 04:42:28.550782 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8177 04:42:28.554106 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8178 04:42:28.557635 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8179 04:42:28.561410 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8180 04:42:28.567947 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8181 04:42:28.570993 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8182 04:42:28.574559 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8183 04:42:28.577700 iDelay=191, Bit 10, Center 126 (79 ~ 174) 96
8184 04:42:28.584762 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8185 04:42:28.588282 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8186 04:42:28.591083 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8187 04:42:28.594602 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8188 04:42:28.598061 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8189 04:42:28.598659 ==
8190 04:42:28.601093 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 04:42:28.607975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 04:42:28.608548 ==
8193 04:42:28.608927 DQS Delay:
8194 04:42:28.611414 DQS0 = 0, DQS1 = 0
8195 04:42:28.611988 DQM Delay:
8196 04:42:28.614688 DQM0 = 133, DQM1 = 123
8197 04:42:28.615164 DQ Delay:
8198 04:42:28.618131 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8199 04:42:28.621478 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8200 04:42:28.624423 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
8201 04:42:28.627742 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8202 04:42:28.628219
8203 04:42:28.628595
8204 04:42:28.628939
8205 04:42:28.631165 [DramC_TX_OE_Calibration] TA2
8206 04:42:28.634013 Original DQ_B0 (3 6) =30, OEN = 27
8207 04:42:28.637867 Original DQ_B1 (3 6) =30, OEN = 27
8208 04:42:28.641127 24, 0x0, End_B0=24 End_B1=24
8209 04:42:28.644354 25, 0x0, End_B0=25 End_B1=25
8210 04:42:28.645085 26, 0x0, End_B0=26 End_B1=26
8211 04:42:28.647541 27, 0x0, End_B0=27 End_B1=27
8212 04:42:28.650833 28, 0x0, End_B0=28 End_B1=28
8213 04:42:28.654550 29, 0x0, End_B0=29 End_B1=29
8214 04:42:28.655128 30, 0x0, End_B0=30 End_B1=30
8215 04:42:28.657745 31, 0x4141, End_B0=30 End_B1=30
8216 04:42:28.661123 Byte0 end_step=30 best_step=27
8217 04:42:28.664210 Byte1 end_step=30 best_step=27
8218 04:42:28.667666 Byte0 TX OE(2T, 0.5T) = (3, 3)
8219 04:42:28.671137 Byte1 TX OE(2T, 0.5T) = (3, 3)
8220 04:42:28.671707
8221 04:42:28.672085
8222 04:42:28.677637 [DQSOSCAuto] RK1, (LSB)MR18= 0x210f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8223 04:42:28.680897 CH0 RK1: MR19=303, MR18=210F
8224 04:42:28.687626 CH0_RK1: MR19=0x303, MR18=0x210F, DQSOSC=393, MR23=63, INC=23, DEC=15
8225 04:42:28.691089 [RxdqsGatingPostProcess] freq 1600
8226 04:42:28.694019 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8227 04:42:28.697363 best DQS0 dly(2T, 0.5T) = (1, 1)
8228 04:42:28.701308 best DQS1 dly(2T, 0.5T) = (1, 1)
8229 04:42:28.704418 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8230 04:42:28.707578 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8231 04:42:28.710830 best DQS0 dly(2T, 0.5T) = (1, 1)
8232 04:42:28.714610 best DQS1 dly(2T, 0.5T) = (1, 1)
8233 04:42:28.717532 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8234 04:42:28.720918 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8235 04:42:28.723916 Pre-setting of DQS Precalculation
8236 04:42:28.727046 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8237 04:42:28.727631 ==
8238 04:42:28.730706 Dram Type= 6, Freq= 0, CH_1, rank 0
8239 04:42:28.733966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8240 04:42:28.737635 ==
8241 04:42:28.740540 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8242 04:42:28.743761 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8243 04:42:28.750630 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8244 04:42:28.757612 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8245 04:42:28.764501 [CA 0] Center 40 (11~70) winsize 60
8246 04:42:28.767935 [CA 1] Center 41 (11~71) winsize 61
8247 04:42:28.770727 [CA 2] Center 37 (8~67) winsize 60
8248 04:42:28.774361 [CA 3] Center 36 (7~66) winsize 60
8249 04:42:28.777866 [CA 4] Center 36 (6~67) winsize 62
8250 04:42:28.781202 [CA 5] Center 36 (6~66) winsize 61
8251 04:42:28.781772
8252 04:42:28.784430 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8253 04:42:28.785003
8254 04:42:28.787836 [CATrainingPosCal] consider 1 rank data
8255 04:42:28.790998 u2DelayCellTimex100 = 285/100 ps
8256 04:42:28.794419 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8257 04:42:28.800984 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8258 04:42:28.803947 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8259 04:42:28.807289 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8260 04:42:28.811065 CA4 delay=36 (6~67),Diff = 0 PI (0 cell)
8261 04:42:28.814285 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8262 04:42:28.814858
8263 04:42:28.817391 CA PerBit enable=1, Macro0, CA PI delay=36
8264 04:42:28.817990
8265 04:42:28.820825 [CBTSetCACLKResult] CA Dly = 36
8266 04:42:28.824024 CS Dly: 8 (0~39)
8267 04:42:28.827115 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8268 04:42:28.830865 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8269 04:42:28.831436 ==
8270 04:42:28.833714 Dram Type= 6, Freq= 0, CH_1, rank 1
8271 04:42:28.837172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8272 04:42:28.837643 ==
8273 04:42:28.843972 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8274 04:42:28.847278 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8275 04:42:28.853671 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8276 04:42:28.859962 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8277 04:42:28.867313 [CA 0] Center 42 (13~72) winsize 60
8278 04:42:28.870644 [CA 1] Center 41 (11~71) winsize 61
8279 04:42:28.874311 [CA 2] Center 37 (8~67) winsize 60
8280 04:42:28.877177 [CA 3] Center 37 (8~66) winsize 59
8281 04:42:28.880725 [CA 4] Center 37 (8~67) winsize 60
8282 04:42:28.884043 [CA 5] Center 36 (7~66) winsize 60
8283 04:42:28.884619
8284 04:42:28.887434 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8285 04:42:28.888016
8286 04:42:28.890614 [CATrainingPosCal] consider 2 rank data
8287 04:42:28.894043 u2DelayCellTimex100 = 285/100 ps
8288 04:42:28.897242 CA0 delay=41 (13~70),Diff = 5 PI (17 cell)
8289 04:42:28.904056 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8290 04:42:28.907370 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8291 04:42:28.910447 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8292 04:42:28.913652 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8293 04:42:28.916854 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8294 04:42:28.917313
8295 04:42:28.920349 CA PerBit enable=1, Macro0, CA PI delay=36
8296 04:42:28.920806
8297 04:42:28.923803 [CBTSetCACLKResult] CA Dly = 36
8298 04:42:28.926843 CS Dly: 9 (0~42)
8299 04:42:28.930385 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8300 04:42:28.933639 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8301 04:42:28.934293
8302 04:42:28.936870 ----->DramcWriteLeveling(PI) begin...
8303 04:42:28.937339 ==
8304 04:42:28.939883 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 04:42:28.946895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 04:42:28.947440 ==
8307 04:42:28.950216 Write leveling (Byte 0): 23 => 23
8308 04:42:28.950681 Write leveling (Byte 1): 27 => 27
8309 04:42:28.953269 DramcWriteLeveling(PI) end<-----
8310 04:42:28.953833
8311 04:42:28.954225 ==
8312 04:42:28.956627 Dram Type= 6, Freq= 0, CH_1, rank 0
8313 04:42:28.963528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 04:42:28.964090 ==
8315 04:42:28.966990 [Gating] SW mode calibration
8316 04:42:28.973203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8317 04:42:28.976535 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8318 04:42:28.983245 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 04:42:28.986610 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 04:42:28.990052 1 4 8 | B1->B0 | 2f2f 3333 | 1 1 | (1 1) (1 1)
8321 04:42:28.996245 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 04:42:28.999798 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 04:42:29.003306 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 04:42:29.009987 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 04:42:29.013134 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 04:42:29.016872 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 04:42:29.020286 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8328 04:42:29.026608 1 5 8 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (1 0)
8329 04:42:29.029793 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8330 04:42:29.033480 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 04:42:29.039910 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 04:42:29.043218 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 04:42:29.046446 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 04:42:29.052865 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 04:42:29.056465 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8336 04:42:29.059653 1 6 8 | B1->B0 | 3939 3f3f | 0 1 | (0 0) (0 0)
8337 04:42:29.066439 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 04:42:29.069469 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 04:42:29.073296 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 04:42:29.079940 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 04:42:29.082812 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 04:42:29.086351 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 04:42:29.092780 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 04:42:29.096089 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8345 04:42:29.099345 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8346 04:42:29.105930 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 04:42:29.109488 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 04:42:29.112979 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 04:42:29.119348 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 04:42:29.122943 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 04:42:29.126436 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 04:42:29.132864 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 04:42:29.136118 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 04:42:29.139063 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 04:42:29.146377 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 04:42:29.149455 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 04:42:29.152931 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 04:42:29.159315 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 04:42:29.162851 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8360 04:42:29.166343 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8361 04:42:29.172880 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8362 04:42:29.173472 Total UI for P1: 0, mck2ui 16
8363 04:42:29.176313 best dqsien dly found for B0: ( 1, 9, 6)
8364 04:42:29.182557 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 04:42:29.185742 Total UI for P1: 0, mck2ui 16
8366 04:42:29.189496 best dqsien dly found for B1: ( 1, 9, 10)
8367 04:42:29.192527 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8368 04:42:29.195645 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8369 04:42:29.196124
8370 04:42:29.199008 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8371 04:42:29.202584 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8372 04:42:29.205830 [Gating] SW calibration Done
8373 04:42:29.206502 ==
8374 04:42:29.209331 Dram Type= 6, Freq= 0, CH_1, rank 0
8375 04:42:29.212326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8376 04:42:29.212946 ==
8377 04:42:29.215744 RX Vref Scan: 0
8378 04:42:29.216310
8379 04:42:29.218874 RX Vref 0 -> 0, step: 1
8380 04:42:29.219352
8381 04:42:29.219718 RX Delay 0 -> 252, step: 8
8382 04:42:29.226012 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8383 04:42:29.229091 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8384 04:42:29.232010 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8385 04:42:29.235455 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8386 04:42:29.238926 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8387 04:42:29.241847 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8388 04:42:29.248719 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8389 04:42:29.252156 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8390 04:42:29.255240 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8391 04:42:29.258514 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8392 04:42:29.262035 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8393 04:42:29.269011 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8394 04:42:29.271856 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8395 04:42:29.275740 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8396 04:42:29.278757 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8397 04:42:29.282382 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8398 04:42:29.285389 ==
8399 04:42:29.288566 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 04:42:29.292221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 04:42:29.292789 ==
8402 04:42:29.293168 DQS Delay:
8403 04:42:29.295617 DQS0 = 0, DQS1 = 0
8404 04:42:29.296086 DQM Delay:
8405 04:42:29.298576 DQM0 = 137, DQM1 = 130
8406 04:42:29.299045 DQ Delay:
8407 04:42:29.301861 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8408 04:42:29.305537 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8409 04:42:29.308607 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8410 04:42:29.311577 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8411 04:42:29.312047
8412 04:42:29.312418
8413 04:42:29.312763 ==
8414 04:42:29.315122 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 04:42:29.321981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 04:42:29.322546 ==
8417 04:42:29.322922
8418 04:42:29.323271
8419 04:42:29.323654 TX Vref Scan disable
8420 04:42:29.325806 == TX Byte 0 ==
8421 04:42:29.328581 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8422 04:42:29.335681 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8423 04:42:29.336308 == TX Byte 1 ==
8424 04:42:29.338821 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8425 04:42:29.345469 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8426 04:42:29.345985 ==
8427 04:42:29.348588 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 04:42:29.351913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 04:42:29.352399 ==
8430 04:42:29.363980
8431 04:42:29.367734 TX Vref early break, caculate TX vref
8432 04:42:29.370739 TX Vref=16, minBit 10, minWin=22, winSum=372
8433 04:42:29.374455 TX Vref=18, minBit 1, minWin=23, winSum=388
8434 04:42:29.377490 TX Vref=20, minBit 10, minWin=23, winSum=393
8435 04:42:29.380823 TX Vref=22, minBit 10, minWin=24, winSum=406
8436 04:42:29.387281 TX Vref=24, minBit 15, minWin=23, winSum=412
8437 04:42:29.390480 TX Vref=26, minBit 15, minWin=25, winSum=424
8438 04:42:29.394442 TX Vref=28, minBit 12, minWin=25, winSum=424
8439 04:42:29.397384 TX Vref=30, minBit 8, minWin=25, winSum=416
8440 04:42:29.400901 TX Vref=32, minBit 13, minWin=24, winSum=410
8441 04:42:29.404027 TX Vref=34, minBit 11, minWin=23, winSum=395
8442 04:42:29.410432 [TxChooseVref] Worse bit 15, Min win 25, Win sum 424, Final Vref 26
8443 04:42:29.410878
8444 04:42:29.414244 Final TX Range 0 Vref 26
8445 04:42:29.414688
8446 04:42:29.415150 ==
8447 04:42:29.417408 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 04:42:29.420708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 04:42:29.421152 ==
8450 04:42:29.421592
8451 04:42:29.422036
8452 04:42:29.423830 TX Vref Scan disable
8453 04:42:29.430592 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8454 04:42:29.431034 == TX Byte 0 ==
8455 04:42:29.433761 u2DelayCellOfst[0]=17 cells (5 PI)
8456 04:42:29.437024 u2DelayCellOfst[1]=6 cells (2 PI)
8457 04:42:29.440644 u2DelayCellOfst[2]=0 cells (0 PI)
8458 04:42:29.444039 u2DelayCellOfst[3]=3 cells (1 PI)
8459 04:42:29.447054 u2DelayCellOfst[4]=6 cells (2 PI)
8460 04:42:29.450863 u2DelayCellOfst[5]=17 cells (5 PI)
8461 04:42:29.453810 u2DelayCellOfst[6]=17 cells (5 PI)
8462 04:42:29.457247 u2DelayCellOfst[7]=3 cells (1 PI)
8463 04:42:29.460578 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8464 04:42:29.464125 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8465 04:42:29.467141 == TX Byte 1 ==
8466 04:42:29.470506 u2DelayCellOfst[8]=0 cells (0 PI)
8467 04:42:29.470931 u2DelayCellOfst[9]=3 cells (1 PI)
8468 04:42:29.473935 u2DelayCellOfst[10]=10 cells (3 PI)
8469 04:42:29.477354 u2DelayCellOfst[11]=3 cells (1 PI)
8470 04:42:29.480670 u2DelayCellOfst[12]=13 cells (4 PI)
8471 04:42:29.483774 u2DelayCellOfst[13]=17 cells (5 PI)
8472 04:42:29.487179 u2DelayCellOfst[14]=17 cells (5 PI)
8473 04:42:29.490146 u2DelayCellOfst[15]=17 cells (5 PI)
8474 04:42:29.493861 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8475 04:42:29.500715 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8476 04:42:29.501299 DramC Write-DBI on
8477 04:42:29.501649 ==
8478 04:42:29.503810 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 04:42:29.507455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 04:42:29.510491 ==
8481 04:42:29.510914
8482 04:42:29.511261
8483 04:42:29.511578 TX Vref Scan disable
8484 04:42:29.513974 == TX Byte 0 ==
8485 04:42:29.517461 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8486 04:42:29.520327 == TX Byte 1 ==
8487 04:42:29.523804 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8488 04:42:29.526860 DramC Write-DBI off
8489 04:42:29.526943
8490 04:42:29.527008 [DATLAT]
8491 04:42:29.527069 Freq=1600, CH1 RK0
8492 04:42:29.527129
8493 04:42:29.530463 DATLAT Default: 0xf
8494 04:42:29.530574 0, 0xFFFF, sum = 0
8495 04:42:29.533386 1, 0xFFFF, sum = 0
8496 04:42:29.536796 2, 0xFFFF, sum = 0
8497 04:42:29.536907 3, 0xFFFF, sum = 0
8498 04:42:29.540476 4, 0xFFFF, sum = 0
8499 04:42:29.540586 5, 0xFFFF, sum = 0
8500 04:42:29.543827 6, 0xFFFF, sum = 0
8501 04:42:29.543918 7, 0xFFFF, sum = 0
8502 04:42:29.546807 8, 0xFFFF, sum = 0
8503 04:42:29.546897 9, 0xFFFF, sum = 0
8504 04:42:29.550454 10, 0xFFFF, sum = 0
8505 04:42:29.550582 11, 0xFFFF, sum = 0
8506 04:42:29.553575 12, 0xFFFF, sum = 0
8507 04:42:29.553712 13, 0xFFFF, sum = 0
8508 04:42:29.556944 14, 0x0, sum = 1
8509 04:42:29.557081 15, 0x0, sum = 2
8510 04:42:29.560568 16, 0x0, sum = 3
8511 04:42:29.560721 17, 0x0, sum = 4
8512 04:42:29.563923 best_step = 15
8513 04:42:29.564087
8514 04:42:29.564235 ==
8515 04:42:29.566864 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 04:42:29.569887 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 04:42:29.570080 ==
8518 04:42:29.573632 RX Vref Scan: 1
8519 04:42:29.573839
8520 04:42:29.574015 Set Vref Range= 24 -> 127
8521 04:42:29.574193
8522 04:42:29.576877 RX Vref 24 -> 127, step: 1
8523 04:42:29.577085
8524 04:42:29.579899 RX Delay 19 -> 252, step: 4
8525 04:42:29.580133
8526 04:42:29.583203 Set Vref, RX VrefLevel [Byte0]: 24
8527 04:42:29.587015 [Byte1]: 24
8528 04:42:29.587222
8529 04:42:29.589910 Set Vref, RX VrefLevel [Byte0]: 25
8530 04:42:29.593504 [Byte1]: 25
8531 04:42:29.593744
8532 04:42:29.596629 Set Vref, RX VrefLevel [Byte0]: 26
8533 04:42:29.599917 [Byte1]: 26
8534 04:42:29.604204
8535 04:42:29.604287 Set Vref, RX VrefLevel [Byte0]: 27
8536 04:42:29.607096 [Byte1]: 27
8537 04:42:29.611668
8538 04:42:29.611751 Set Vref, RX VrefLevel [Byte0]: 28
8539 04:42:29.614689 [Byte1]: 28
8540 04:42:29.619426
8541 04:42:29.619508 Set Vref, RX VrefLevel [Byte0]: 29
8542 04:42:29.622363 [Byte1]: 29
8543 04:42:29.626458
8544 04:42:29.626558 Set Vref, RX VrefLevel [Byte0]: 30
8545 04:42:29.629999 [Byte1]: 30
8546 04:42:29.634554
8547 04:42:29.634637 Set Vref, RX VrefLevel [Byte0]: 31
8548 04:42:29.637605 [Byte1]: 31
8549 04:42:29.641837
8550 04:42:29.641926 Set Vref, RX VrefLevel [Byte0]: 32
8551 04:42:29.645289 [Byte1]: 32
8552 04:42:29.649784
8553 04:42:29.649980 Set Vref, RX VrefLevel [Byte0]: 33
8554 04:42:29.652525 [Byte1]: 33
8555 04:42:29.657101
8556 04:42:29.657252 Set Vref, RX VrefLevel [Byte0]: 34
8557 04:42:29.660150 [Byte1]: 34
8558 04:42:29.664508
8559 04:42:29.664646 Set Vref, RX VrefLevel [Byte0]: 35
8560 04:42:29.668279 [Byte1]: 35
8561 04:42:29.672274
8562 04:42:29.672450 Set Vref, RX VrefLevel [Byte0]: 36
8563 04:42:29.676043 [Byte1]: 36
8564 04:42:29.679857
8565 04:42:29.680109 Set Vref, RX VrefLevel [Byte0]: 37
8566 04:42:29.683358 [Byte1]: 37
8567 04:42:29.688007
8568 04:42:29.688414 Set Vref, RX VrefLevel [Byte0]: 38
8569 04:42:29.691192 [Byte1]: 38
8570 04:42:29.695507
8571 04:42:29.696118 Set Vref, RX VrefLevel [Byte0]: 39
8572 04:42:29.698778 [Byte1]: 39
8573 04:42:29.702438
8574 04:42:29.702911 Set Vref, RX VrefLevel [Byte0]: 40
8575 04:42:29.706068 [Byte1]: 40
8576 04:42:29.710145
8577 04:42:29.710617 Set Vref, RX VrefLevel [Byte0]: 41
8578 04:42:29.713759 [Byte1]: 41
8579 04:42:29.717700
8580 04:42:29.718221 Set Vref, RX VrefLevel [Byte0]: 42
8581 04:42:29.721235 [Byte1]: 42
8582 04:42:29.725584
8583 04:42:29.726087 Set Vref, RX VrefLevel [Byte0]: 43
8584 04:42:29.728571 [Byte1]: 43
8585 04:42:29.733040
8586 04:42:29.733511 Set Vref, RX VrefLevel [Byte0]: 44
8587 04:42:29.736149 [Byte1]: 44
8588 04:42:29.740619
8589 04:42:29.741310 Set Vref, RX VrefLevel [Byte0]: 45
8590 04:42:29.744235 [Byte1]: 45
8591 04:42:29.748049
8592 04:42:29.748543 Set Vref, RX VrefLevel [Byte0]: 46
8593 04:42:29.751158 [Byte1]: 46
8594 04:42:29.755785
8595 04:42:29.756259 Set Vref, RX VrefLevel [Byte0]: 47
8596 04:42:29.759281 [Byte1]: 47
8597 04:42:29.763070
8598 04:42:29.763706 Set Vref, RX VrefLevel [Byte0]: 48
8599 04:42:29.766265 [Byte1]: 48
8600 04:42:29.770975
8601 04:42:29.771573 Set Vref, RX VrefLevel [Byte0]: 49
8602 04:42:29.774151 [Byte1]: 49
8603 04:42:29.778261
8604 04:42:29.778697 Set Vref, RX VrefLevel [Byte0]: 50
8605 04:42:29.781379 [Byte1]: 50
8606 04:42:29.785909
8607 04:42:29.786257 Set Vref, RX VrefLevel [Byte0]: 51
8608 04:42:29.789123 [Byte1]: 51
8609 04:42:29.793560
8610 04:42:29.793791 Set Vref, RX VrefLevel [Byte0]: 52
8611 04:42:29.796717 [Byte1]: 52
8612 04:42:29.801013
8613 04:42:29.801245 Set Vref, RX VrefLevel [Byte0]: 53
8614 04:42:29.804695 [Byte1]: 53
8615 04:42:29.808995
8616 04:42:29.809312 Set Vref, RX VrefLevel [Byte0]: 54
8617 04:42:29.812486 [Byte1]: 54
8618 04:42:29.816459
8619 04:42:29.816780 Set Vref, RX VrefLevel [Byte0]: 55
8620 04:42:29.819863 [Byte1]: 55
8621 04:42:29.823720
8622 04:42:29.823987 Set Vref, RX VrefLevel [Byte0]: 56
8623 04:42:29.827195 [Byte1]: 56
8624 04:42:29.831549
8625 04:42:29.831779 Set Vref, RX VrefLevel [Byte0]: 57
8626 04:42:29.834544 [Byte1]: 57
8627 04:42:29.838751
8628 04:42:29.838985 Set Vref, RX VrefLevel [Byte0]: 58
8629 04:42:29.842354 [Byte1]: 58
8630 04:42:29.846666
8631 04:42:29.846957 Set Vref, RX VrefLevel [Byte0]: 59
8632 04:42:29.849518 [Byte1]: 59
8633 04:42:29.854095
8634 04:42:29.854330 Set Vref, RX VrefLevel [Byte0]: 60
8635 04:42:29.857339 [Byte1]: 60
8636 04:42:29.861510
8637 04:42:29.861812 Set Vref, RX VrefLevel [Byte0]: 61
8638 04:42:29.864855 [Byte1]: 61
8639 04:42:29.868905
8640 04:42:29.869198 Set Vref, RX VrefLevel [Byte0]: 62
8641 04:42:29.872485 [Byte1]: 62
8642 04:42:29.876855
8643 04:42:29.877067 Set Vref, RX VrefLevel [Byte0]: 63
8644 04:42:29.880000 [Byte1]: 63
8645 04:42:29.884437
8646 04:42:29.884740 Set Vref, RX VrefLevel [Byte0]: 64
8647 04:42:29.887609 [Byte1]: 64
8648 04:42:29.891831
8649 04:42:29.892135 Set Vref, RX VrefLevel [Byte0]: 65
8650 04:42:29.894902 [Byte1]: 65
8651 04:42:29.899398
8652 04:42:29.899675 Set Vref, RX VrefLevel [Byte0]: 66
8653 04:42:29.902724 [Byte1]: 66
8654 04:42:29.907219
8655 04:42:29.907444 Set Vref, RX VrefLevel [Byte0]: 67
8656 04:42:29.910363 [Byte1]: 67
8657 04:42:29.914546
8658 04:42:29.914772 Set Vref, RX VrefLevel [Byte0]: 68
8659 04:42:29.917887 [Byte1]: 68
8660 04:42:29.922006
8661 04:42:29.922230 Set Vref, RX VrefLevel [Byte0]: 69
8662 04:42:29.925114 [Byte1]: 69
8663 04:42:29.929529
8664 04:42:29.929612 Set Vref, RX VrefLevel [Byte0]: 70
8665 04:42:29.933173 [Byte1]: 70
8666 04:42:29.937377
8667 04:42:29.937485 Set Vref, RX VrefLevel [Byte0]: 71
8668 04:42:29.940627 [Byte1]: 71
8669 04:42:29.944464
8670 04:42:29.944546 Set Vref, RX VrefLevel [Byte0]: 72
8671 04:42:29.948073 [Byte1]: 72
8672 04:42:29.952238
8673 04:42:29.952374 Set Vref, RX VrefLevel [Byte0]: 73
8674 04:42:29.955484 [Byte1]: 73
8675 04:42:29.959680
8676 04:42:29.959798 Set Vref, RX VrefLevel [Byte0]: 74
8677 04:42:29.963425 [Byte1]: 74
8678 04:42:29.967415
8679 04:42:29.967560 Set Vref, RX VrefLevel [Byte0]: 75
8680 04:42:29.970847 [Byte1]: 75
8681 04:42:29.975240
8682 04:42:29.975362 Set Vref, RX VrefLevel [Byte0]: 76
8683 04:42:29.978516 [Byte1]: 76
8684 04:42:29.982768
8685 04:42:29.982850 Set Vref, RX VrefLevel [Byte0]: 77
8686 04:42:29.985813 [Byte1]: 77
8687 04:42:29.990477
8688 04:42:29.990563 Final RX Vref Byte 0 = 57 to rank0
8689 04:42:29.993206 Final RX Vref Byte 1 = 61 to rank0
8690 04:42:29.996799 Final RX Vref Byte 0 = 57 to rank1
8691 04:42:30.000321 Final RX Vref Byte 1 = 61 to rank1==
8692 04:42:30.003177 Dram Type= 6, Freq= 0, CH_1, rank 0
8693 04:42:30.010109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8694 04:42:30.010195 ==
8695 04:42:30.010262 DQS Delay:
8696 04:42:30.010325 DQS0 = 0, DQS1 = 0
8697 04:42:30.013316 DQM Delay:
8698 04:42:30.013399 DQM0 = 134, DQM1 = 129
8699 04:42:30.016738 DQ Delay:
8700 04:42:30.020398 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
8701 04:42:30.023507 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8702 04:42:30.027096 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =122
8703 04:42:30.030148 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8704 04:42:30.030232
8705 04:42:30.030298
8706 04:42:30.030359
8707 04:42:30.033483 [DramC_TX_OE_Calibration] TA2
8708 04:42:30.036637 Original DQ_B0 (3 6) =30, OEN = 27
8709 04:42:30.040225 Original DQ_B1 (3 6) =30, OEN = 27
8710 04:42:30.043428 24, 0x0, End_B0=24 End_B1=24
8711 04:42:30.043513 25, 0x0, End_B0=25 End_B1=25
8712 04:42:30.046476 26, 0x0, End_B0=26 End_B1=26
8713 04:42:30.050202 27, 0x0, End_B0=27 End_B1=27
8714 04:42:30.053183 28, 0x0, End_B0=28 End_B1=28
8715 04:42:30.053287 29, 0x0, End_B0=29 End_B1=29
8716 04:42:30.056732 30, 0x0, End_B0=30 End_B1=30
8717 04:42:30.059668 31, 0x5151, End_B0=30 End_B1=30
8718 04:42:30.063224 Byte0 end_step=30 best_step=27
8719 04:42:30.066788 Byte1 end_step=30 best_step=27
8720 04:42:30.069895 Byte0 TX OE(2T, 0.5T) = (3, 3)
8721 04:42:30.070051 Byte1 TX OE(2T, 0.5T) = (3, 3)
8722 04:42:30.073516
8723 04:42:30.073602
8724 04:42:30.079839 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8725 04:42:30.083058 CH1 RK0: MR19=303, MR18=1A28
8726 04:42:30.089795 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8727 04:42:30.089897
8728 04:42:30.093140 ----->DramcWriteLeveling(PI) begin...
8729 04:42:30.093218 ==
8730 04:42:30.096360 Dram Type= 6, Freq= 0, CH_1, rank 1
8731 04:42:30.099893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8732 04:42:30.099998 ==
8733 04:42:30.103008 Write leveling (Byte 0): 25 => 25
8734 04:42:30.106459 Write leveling (Byte 1): 27 => 27
8735 04:42:30.109530 DramcWriteLeveling(PI) end<-----
8736 04:42:30.109629
8737 04:42:30.109719 ==
8738 04:42:30.113120 Dram Type= 6, Freq= 0, CH_1, rank 1
8739 04:42:30.116089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8740 04:42:30.116164 ==
8741 04:42:30.119541 [Gating] SW mode calibration
8742 04:42:30.126170 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8743 04:42:30.133005 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8744 04:42:30.135883 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 04:42:30.142468 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 04:42:30.145979 1 4 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8747 04:42:30.149487 1 4 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
8748 04:42:30.155644 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 04:42:30.159219 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 04:42:30.162689 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 04:42:30.165730 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 04:42:30.172531 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 04:42:30.176095 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 04:42:30.178924 1 5 8 | B1->B0 | 2323 3434 | 0 1 | (1 0) (1 0)
8755 04:42:30.185827 1 5 12 | B1->B0 | 2323 2f2f | 0 0 | (1 0) (0 1)
8756 04:42:30.189174 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 04:42:30.192688 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 04:42:30.199081 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 04:42:30.202275 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 04:42:30.205837 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 04:42:30.212300 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8762 04:42:30.215852 1 6 8 | B1->B0 | 4242 2323 | 0 0 | (0 0) (0 0)
8763 04:42:30.219338 1 6 12 | B1->B0 | 4646 3939 | 0 0 | (0 0) (0 0)
8764 04:42:30.225677 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 04:42:30.229288 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 04:42:30.232434 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 04:42:30.239264 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 04:42:30.242602 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 04:42:30.245894 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 04:42:30.252344 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8771 04:42:30.255760 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8772 04:42:30.259308 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 04:42:30.265754 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 04:42:30.268795 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 04:42:30.272351 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 04:42:30.278790 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 04:42:30.282384 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 04:42:30.285750 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 04:42:30.288894 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 04:42:30.295409 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 04:42:30.298728 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 04:42:30.302132 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 04:42:30.308713 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 04:42:30.312439 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 04:42:30.315455 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8786 04:42:30.322205 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8787 04:42:30.325192 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8788 04:42:30.328799 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 04:42:30.331701 Total UI for P1: 0, mck2ui 16
8790 04:42:30.334888 best dqsien dly found for B0: ( 1, 9, 10)
8791 04:42:30.338375 Total UI for P1: 0, mck2ui 16
8792 04:42:30.342047 best dqsien dly found for B1: ( 1, 9, 8)
8793 04:42:30.344987 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8794 04:42:30.348507 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8795 04:42:30.351795
8796 04:42:30.355252 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8797 04:42:30.358951 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8798 04:42:30.362384 [Gating] SW calibration Done
8799 04:42:30.362852 ==
8800 04:42:30.365317 Dram Type= 6, Freq= 0, CH_1, rank 1
8801 04:42:30.368771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8802 04:42:30.369305 ==
8803 04:42:30.369686 RX Vref Scan: 0
8804 04:42:30.370075
8805 04:42:30.372143 RX Vref 0 -> 0, step: 1
8806 04:42:30.372732
8807 04:42:30.375571 RX Delay 0 -> 252, step: 8
8808 04:42:30.378954 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8809 04:42:30.382608 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8810 04:42:30.388776 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8811 04:42:30.392239 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8812 04:42:30.395217 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8813 04:42:30.398821 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8814 04:42:30.402189 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8815 04:42:30.408746 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8816 04:42:30.412213 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8817 04:42:30.415647 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8818 04:42:30.418961 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8819 04:42:30.422294 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8820 04:42:30.425591 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8821 04:42:30.432423 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8822 04:42:30.435723 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8823 04:42:30.438913 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8824 04:42:30.439425 ==
8825 04:42:30.441934 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 04:42:30.445492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 04:42:30.448883 ==
8828 04:42:30.449371 DQS Delay:
8829 04:42:30.449866 DQS0 = 0, DQS1 = 0
8830 04:42:30.451854 DQM Delay:
8831 04:42:30.452439 DQM0 = 136, DQM1 = 131
8832 04:42:30.455157 DQ Delay:
8833 04:42:30.458621 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8834 04:42:30.461864 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8835 04:42:30.465437 DQ8 =111, DQ9 =119, DQ10 =135, DQ11 =127
8836 04:42:30.468906 DQ12 =143, DQ13 =139, DQ14 =135, DQ15 =143
8837 04:42:30.469492
8838 04:42:30.470007
8839 04:42:30.470462 ==
8840 04:42:30.471670 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 04:42:30.475278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 04:42:30.478203 ==
8843 04:42:30.478689
8844 04:42:30.479169
8845 04:42:30.479619 TX Vref Scan disable
8846 04:42:30.481802 == TX Byte 0 ==
8847 04:42:30.485494 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8848 04:42:30.488302 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8849 04:42:30.491633 == TX Byte 1 ==
8850 04:42:30.495269 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8851 04:42:30.498142 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8852 04:42:30.498629 ==
8853 04:42:30.501329 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 04:42:30.508482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 04:42:30.509080 ==
8856 04:42:30.520172
8857 04:42:30.523351 TX Vref early break, caculate TX vref
8858 04:42:30.526662 TX Vref=16, minBit 9, minWin=22, winSum=387
8859 04:42:30.530054 TX Vref=18, minBit 12, minWin=23, winSum=395
8860 04:42:30.533442 TX Vref=20, minBit 1, minWin=25, winSum=408
8861 04:42:30.536915 TX Vref=22, minBit 11, minWin=24, winSum=411
8862 04:42:30.539952 TX Vref=24, minBit 12, minWin=25, winSum=422
8863 04:42:30.546777 TX Vref=26, minBit 14, minWin=25, winSum=423
8864 04:42:30.549892 TX Vref=28, minBit 12, minWin=25, winSum=425
8865 04:42:30.553350 TX Vref=30, minBit 12, minWin=25, winSum=421
8866 04:42:30.556547 TX Vref=32, minBit 0, minWin=25, winSum=410
8867 04:42:30.560366 TX Vref=34, minBit 10, minWin=23, winSum=400
8868 04:42:30.566686 [TxChooseVref] Worse bit 12, Min win 25, Win sum 425, Final Vref 28
8869 04:42:30.567166
8870 04:42:30.569734 Final TX Range 0 Vref 28
8871 04:42:30.570258
8872 04:42:30.570637 ==
8873 04:42:30.573323 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 04:42:30.576913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 04:42:30.577488 ==
8876 04:42:30.577866
8877 04:42:30.578264
8878 04:42:30.580360 TX Vref Scan disable
8879 04:42:30.586883 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8880 04:42:30.587453 == TX Byte 0 ==
8881 04:42:30.589982 u2DelayCellOfst[0]=13 cells (4 PI)
8882 04:42:30.593227 u2DelayCellOfst[1]=10 cells (3 PI)
8883 04:42:30.596863 u2DelayCellOfst[2]=0 cells (0 PI)
8884 04:42:30.599955 u2DelayCellOfst[3]=3 cells (1 PI)
8885 04:42:30.603266 u2DelayCellOfst[4]=6 cells (2 PI)
8886 04:42:30.606613 u2DelayCellOfst[5]=17 cells (5 PI)
8887 04:42:30.609930 u2DelayCellOfst[6]=17 cells (5 PI)
8888 04:42:30.613234 u2DelayCellOfst[7]=3 cells (1 PI)
8889 04:42:30.616453 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8890 04:42:30.620094 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8891 04:42:30.623150 == TX Byte 1 ==
8892 04:42:30.626601 u2DelayCellOfst[8]=0 cells (0 PI)
8893 04:42:30.627171 u2DelayCellOfst[9]=3 cells (1 PI)
8894 04:42:30.630223 u2DelayCellOfst[10]=10 cells (3 PI)
8895 04:42:30.633170 u2DelayCellOfst[11]=3 cells (1 PI)
8896 04:42:30.636375 u2DelayCellOfst[12]=13 cells (4 PI)
8897 04:42:30.640233 u2DelayCellOfst[13]=17 cells (5 PI)
8898 04:42:30.642875 u2DelayCellOfst[14]=20 cells (6 PI)
8899 04:42:30.646091 u2DelayCellOfst[15]=17 cells (5 PI)
8900 04:42:30.649704 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8901 04:42:30.656533 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8902 04:42:30.657089 DramC Write-DBI on
8903 04:42:30.657469 ==
8904 04:42:30.660115 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 04:42:30.666509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 04:42:30.667083 ==
8907 04:42:30.667464
8908 04:42:30.667819
8909 04:42:30.668156 TX Vref Scan disable
8910 04:42:30.669770 == TX Byte 0 ==
8911 04:42:30.673225 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8912 04:42:30.676855 == TX Byte 1 ==
8913 04:42:30.680263 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8914 04:42:30.680833 DramC Write-DBI off
8915 04:42:30.683670
8916 04:42:30.684235 [DATLAT]
8917 04:42:30.684611 Freq=1600, CH1 RK1
8918 04:42:30.684969
8919 04:42:30.686739 DATLAT Default: 0xf
8920 04:42:30.687213 0, 0xFFFF, sum = 0
8921 04:42:30.689645 1, 0xFFFF, sum = 0
8922 04:42:30.693267 2, 0xFFFF, sum = 0
8923 04:42:30.693841 3, 0xFFFF, sum = 0
8924 04:42:30.696579 4, 0xFFFF, sum = 0
8925 04:42:30.697154 5, 0xFFFF, sum = 0
8926 04:42:30.699828 6, 0xFFFF, sum = 0
8927 04:42:30.700311 7, 0xFFFF, sum = 0
8928 04:42:30.702879 8, 0xFFFF, sum = 0
8929 04:42:30.703360 9, 0xFFFF, sum = 0
8930 04:42:30.706388 10, 0xFFFF, sum = 0
8931 04:42:30.706868 11, 0xFFFF, sum = 0
8932 04:42:30.710097 12, 0xFFFF, sum = 0
8933 04:42:30.710673 13, 0xFFFF, sum = 0
8934 04:42:30.713218 14, 0x0, sum = 1
8935 04:42:30.713789 15, 0x0, sum = 2
8936 04:42:30.716597 16, 0x0, sum = 3
8937 04:42:30.717182 17, 0x0, sum = 4
8938 04:42:30.719663 best_step = 15
8939 04:42:30.720235
8940 04:42:30.720610 ==
8941 04:42:30.722955 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 04:42:30.726581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 04:42:30.727155 ==
8944 04:42:30.729313 RX Vref Scan: 0
8945 04:42:30.729781
8946 04:42:30.730193 RX Vref 0 -> 0, step: 1
8947 04:42:30.730540
8948 04:42:30.732930 RX Delay 11 -> 252, step: 4
8949 04:42:30.736175 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8950 04:42:30.742732 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8951 04:42:30.745966 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8952 04:42:30.749396 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8953 04:42:30.752916 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8954 04:42:30.755950 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8955 04:42:30.759627 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8956 04:42:30.766077 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8957 04:42:30.769688 iDelay=195, Bit 8, Center 114 (67 ~ 162) 96
8958 04:42:30.772634 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
8959 04:42:30.776011 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8960 04:42:30.779081 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8961 04:42:30.786050 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8962 04:42:30.789069 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8963 04:42:30.792340 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8964 04:42:30.795842 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
8965 04:42:30.796209 ==
8966 04:42:30.798790 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 04:42:30.805405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 04:42:30.805664 ==
8969 04:42:30.805877 DQS Delay:
8970 04:42:30.808763 DQS0 = 0, DQS1 = 0
8971 04:42:30.808972 DQM Delay:
8972 04:42:30.811974 DQM0 = 133, DQM1 = 130
8973 04:42:30.812130 DQ Delay:
8974 04:42:30.815298 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8975 04:42:30.818783 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8976 04:42:30.821616 DQ8 =114, DQ9 =120, DQ10 =130, DQ11 =124
8977 04:42:30.825018 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =142
8978 04:42:30.825123
8979 04:42:30.825205
8980 04:42:30.825280
8981 04:42:30.828607 [DramC_TX_OE_Calibration] TA2
8982 04:42:30.832186 Original DQ_B0 (3 6) =30, OEN = 27
8983 04:42:30.835317 Original DQ_B1 (3 6) =30, OEN = 27
8984 04:42:30.838331 24, 0x0, End_B0=24 End_B1=24
8985 04:42:30.841764 25, 0x0, End_B0=25 End_B1=25
8986 04:42:30.841902 26, 0x0, End_B0=26 End_B1=26
8987 04:42:30.845194 27, 0x0, End_B0=27 End_B1=27
8988 04:42:30.848725 28, 0x0, End_B0=28 End_B1=28
8989 04:42:30.851762 29, 0x0, End_B0=29 End_B1=29
8990 04:42:30.851866 30, 0x0, End_B0=30 End_B1=30
8991 04:42:30.854789 31, 0x4545, End_B0=30 End_B1=30
8992 04:42:30.858366 Byte0 end_step=30 best_step=27
8993 04:42:30.861554 Byte1 end_step=30 best_step=27
8994 04:42:30.864956 Byte0 TX OE(2T, 0.5T) = (3, 3)
8995 04:42:30.868050 Byte1 TX OE(2T, 0.5T) = (3, 3)
8996 04:42:30.868151
8997 04:42:30.868235
8998 04:42:30.875082 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
8999 04:42:30.878287 CH1 RK1: MR19=303, MR18=1E09
9000 04:42:30.884997 CH1_RK1: MR19=0x303, MR18=0x1E09, DQSOSC=394, MR23=63, INC=23, DEC=15
9001 04:42:30.887979 [RxdqsGatingPostProcess] freq 1600
9002 04:42:30.895106 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9003 04:42:30.895370 best DQS0 dly(2T, 0.5T) = (1, 1)
9004 04:42:30.898162 best DQS1 dly(2T, 0.5T) = (1, 1)
9005 04:42:30.901650 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9006 04:42:30.904753 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9007 04:42:30.908411 best DQS0 dly(2T, 0.5T) = (1, 1)
9008 04:42:30.911337 best DQS1 dly(2T, 0.5T) = (1, 1)
9009 04:42:30.915308 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9010 04:42:30.918095 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9011 04:42:30.921772 Pre-setting of DQS Precalculation
9012 04:42:30.924669 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9013 04:42:30.935154 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9014 04:42:30.941602 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9015 04:42:30.942227
9016 04:42:30.942578
9017 04:42:30.944995 [Calibration Summary] 3200 Mbps
9018 04:42:30.945280 CH 0, Rank 0
9019 04:42:30.947760 SW Impedance : PASS
9020 04:42:30.947991 DUTY Scan : NO K
9021 04:42:30.951472 ZQ Calibration : PASS
9022 04:42:30.954539 Jitter Meter : NO K
9023 04:42:30.954769 CBT Training : PASS
9024 04:42:30.958104 Write leveling : PASS
9025 04:42:30.960912 RX DQS gating : PASS
9026 04:42:30.961193 RX DQ/DQS(RDDQC) : PASS
9027 04:42:30.964619 TX DQ/DQS : PASS
9028 04:42:30.967639 RX DATLAT : PASS
9029 04:42:30.967856 RX DQ/DQS(Engine): PASS
9030 04:42:30.971437 TX OE : PASS
9031 04:42:30.971717 All Pass.
9032 04:42:30.971967
9033 04:42:30.974226 CH 0, Rank 1
9034 04:42:30.974417 SW Impedance : PASS
9035 04:42:30.977888 DUTY Scan : NO K
9036 04:42:30.978138 ZQ Calibration : PASS
9037 04:42:30.980852 Jitter Meter : NO K
9038 04:42:30.984333 CBT Training : PASS
9039 04:42:30.984614 Write leveling : PASS
9040 04:42:30.987432 RX DQS gating : PASS
9041 04:42:30.991126 RX DQ/DQS(RDDQC) : PASS
9042 04:42:30.991395 TX DQ/DQS : PASS
9043 04:42:30.994389 RX DATLAT : PASS
9044 04:42:30.997798 RX DQ/DQS(Engine): PASS
9045 04:42:30.998105 TX OE : PASS
9046 04:42:31.000755 All Pass.
9047 04:42:31.001030
9048 04:42:31.001273 CH 1, Rank 0
9049 04:42:31.004144 SW Impedance : PASS
9050 04:42:31.004417 DUTY Scan : NO K
9051 04:42:31.007544 ZQ Calibration : PASS
9052 04:42:31.010804 Jitter Meter : NO K
9053 04:42:31.011000 CBT Training : PASS
9054 04:42:31.014442 Write leveling : PASS
9055 04:42:31.017711 RX DQS gating : PASS
9056 04:42:31.017924 RX DQ/DQS(RDDQC) : PASS
9057 04:42:31.021091 TX DQ/DQS : PASS
9058 04:42:31.021344 RX DATLAT : PASS
9059 04:42:31.024048 RX DQ/DQS(Engine): PASS
9060 04:42:31.027644 TX OE : PASS
9061 04:42:31.027918 All Pass.
9062 04:42:31.028159
9063 04:42:31.028384 CH 1, Rank 1
9064 04:42:31.030903 SW Impedance : PASS
9065 04:42:31.034294 DUTY Scan : NO K
9066 04:42:31.034423 ZQ Calibration : PASS
9067 04:42:31.037293 Jitter Meter : NO K
9068 04:42:31.040897 CBT Training : PASS
9069 04:42:31.040993 Write leveling : PASS
9070 04:42:31.044072 RX DQS gating : PASS
9071 04:42:31.047480 RX DQ/DQS(RDDQC) : PASS
9072 04:42:31.047578 TX DQ/DQS : PASS
9073 04:42:31.050469 RX DATLAT : PASS
9074 04:42:31.053867 RX DQ/DQS(Engine): PASS
9075 04:42:31.053986 TX OE : PASS
9076 04:42:31.057778 All Pass.
9077 04:42:31.058229
9078 04:42:31.058549 DramC Write-DBI on
9079 04:42:31.060966 PER_BANK_REFRESH: Hybrid Mode
9080 04:42:31.061384 TX_TRACKING: ON
9081 04:42:31.071193 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9082 04:42:31.078194 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9083 04:42:31.087862 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9084 04:42:31.091196 [FAST_K] Save calibration result to emmc
9085 04:42:31.094601 sync common calibartion params.
9086 04:42:31.095173 sync cbt_mode0:1, 1:1
9087 04:42:31.098124 dram_init: ddr_geometry: 2
9088 04:42:31.101084 dram_init: ddr_geometry: 2
9089 04:42:31.101592 dram_init: ddr_geometry: 2
9090 04:42:31.104145 0:dram_rank_size:100000000
9091 04:42:31.107535 1:dram_rank_size:100000000
9092 04:42:31.110967 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9093 04:42:31.114181 DFS_SHUFFLE_HW_MODE: ON
9094 04:42:31.117578 dramc_set_vcore_voltage set vcore to 725000
9095 04:42:31.120946 Read voltage for 1600, 0
9096 04:42:31.121472 Vio18 = 0
9097 04:42:31.124355 Vcore = 725000
9098 04:42:31.124817 Vdram = 0
9099 04:42:31.125291 Vddq = 0
9100 04:42:31.125642 Vmddr = 0
9101 04:42:31.127708 switch to 3200 Mbps bootup
9102 04:42:31.131313 [DramcRunTimeConfig]
9103 04:42:31.131915 PHYPLL
9104 04:42:31.134442 DPM_CONTROL_AFTERK: ON
9105 04:42:31.134908 PER_BANK_REFRESH: ON
9106 04:42:31.137695 REFRESH_OVERHEAD_REDUCTION: ON
9107 04:42:31.141271 CMD_PICG_NEW_MODE: OFF
9108 04:42:31.141839 XRTWTW_NEW_MODE: ON
9109 04:42:31.144412 XRTRTR_NEW_MODE: ON
9110 04:42:31.144876 TX_TRACKING: ON
9111 04:42:31.147353 RDSEL_TRACKING: OFF
9112 04:42:31.150873 DQS Precalculation for DVFS: ON
9113 04:42:31.151343 RX_TRACKING: OFF
9114 04:42:31.154059 HW_GATING DBG: ON
9115 04:42:31.154544 ZQCS_ENABLE_LP4: ON
9116 04:42:31.157775 RX_PICG_NEW_MODE: ON
9117 04:42:31.158390 TX_PICG_NEW_MODE: ON
9118 04:42:31.160838 ENABLE_RX_DCM_DPHY: ON
9119 04:42:31.164328 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9120 04:42:31.167547 DUMMY_READ_FOR_TRACKING: OFF
9121 04:42:31.168059 !!! SPM_CONTROL_AFTERK: OFF
9122 04:42:31.170694 !!! SPM could not control APHY
9123 04:42:31.174380 IMPEDANCE_TRACKING: ON
9124 04:42:31.174948 TEMP_SENSOR: ON
9125 04:42:31.177474 HW_SAVE_FOR_SR: OFF
9126 04:42:31.180672 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9127 04:42:31.184502 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9128 04:42:31.185081 Read ODT Tracking: ON
9129 04:42:31.187524 Refresh Rate DeBounce: ON
9130 04:42:31.191009 DFS_NO_QUEUE_FLUSH: ON
9131 04:42:31.194304 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9132 04:42:31.194871 ENABLE_DFS_RUNTIME_MRW: OFF
9133 04:42:31.197763 DDR_RESERVE_NEW_MODE: ON
9134 04:42:31.200795 MR_CBT_SWITCH_FREQ: ON
9135 04:42:31.201294 =========================
9136 04:42:31.221159 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9137 04:42:31.223977 dram_init: ddr_geometry: 2
9138 04:42:31.242818 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9139 04:42:31.246002 dram_init: dram init end (result: 0)
9140 04:42:31.252587 DRAM-K: Full calibration passed in 24473 msecs
9141 04:42:31.255420 MRC: failed to locate region type 0.
9142 04:42:31.255994 DRAM rank0 size:0x100000000,
9143 04:42:31.259115 DRAM rank1 size=0x100000000
9144 04:42:31.269267 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9145 04:42:31.275592 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9146 04:42:31.282140 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9147 04:42:31.289039 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9148 04:42:31.291974 DRAM rank0 size:0x100000000,
9149 04:42:31.295287 DRAM rank1 size=0x100000000
9150 04:42:31.295855 CBMEM:
9151 04:42:31.298426 IMD: root @ 0xfffff000 254 entries.
9152 04:42:31.301905 IMD: root @ 0xffffec00 62 entries.
9153 04:42:31.305352 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9154 04:42:31.311822 WARNING: RO_VPD is uninitialized or empty.
9155 04:42:31.315183 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9156 04:42:31.322489 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9157 04:42:31.335146 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9158 04:42:31.346327 BS: romstage times (exec / console): total (unknown) / 23977 ms
9159 04:42:31.346439
9160 04:42:31.346534
9161 04:42:31.356205 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9162 04:42:31.359801 ARM64: Exception handlers installed.
9163 04:42:31.363167 ARM64: Testing exception
9164 04:42:31.366475 ARM64: Done test exception
9165 04:42:31.366947 Enumerating buses...
9166 04:42:31.369560 Show all devs... Before device enumeration.
9167 04:42:31.373225 Root Device: enabled 1
9168 04:42:31.376254 CPU_CLUSTER: 0: enabled 1
9169 04:42:31.376729 CPU: 00: enabled 1
9170 04:42:31.379789 Compare with tree...
9171 04:42:31.380359 Root Device: enabled 1
9172 04:42:31.382723 CPU_CLUSTER: 0: enabled 1
9173 04:42:31.386382 CPU: 00: enabled 1
9174 04:42:31.386950 Root Device scanning...
9175 04:42:31.389868 scan_static_bus for Root Device
9176 04:42:31.393108 CPU_CLUSTER: 0 enabled
9177 04:42:31.396221 scan_static_bus for Root Device done
9178 04:42:31.399740 scan_bus: bus Root Device finished in 8 msecs
9179 04:42:31.400212 done
9180 04:42:31.406360 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9181 04:42:31.409587 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9182 04:42:31.416334 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9183 04:42:31.419248 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9184 04:42:31.422653 Allocating resources...
9185 04:42:31.426179 Reading resources...
9186 04:42:31.429234 Root Device read_resources bus 0 link: 0
9187 04:42:31.429706 DRAM rank0 size:0x100000000,
9188 04:42:31.432792 DRAM rank1 size=0x100000000
9189 04:42:31.435816 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9190 04:42:31.438730 CPU: 00 missing read_resources
9191 04:42:31.442684 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9192 04:42:31.448875 Root Device read_resources bus 0 link: 0 done
9193 04:42:31.448961 Done reading resources.
9194 04:42:31.455506 Show resources in subtree (Root Device)...After reading.
9195 04:42:31.459183 Root Device child on link 0 CPU_CLUSTER: 0
9196 04:42:31.462150 CPU_CLUSTER: 0 child on link 0 CPU: 00
9197 04:42:31.471953 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9198 04:42:31.472039 CPU: 00
9199 04:42:31.475649 Root Device assign_resources, bus 0 link: 0
9200 04:42:31.478753 CPU_CLUSTER: 0 missing set_resources
9201 04:42:31.485569 Root Device assign_resources, bus 0 link: 0 done
9202 04:42:31.485668 Done setting resources.
9203 04:42:31.492212 Show resources in subtree (Root Device)...After assigning values.
9204 04:42:31.495441 Root Device child on link 0 CPU_CLUSTER: 0
9205 04:42:31.498703 CPU_CLUSTER: 0 child on link 0 CPU: 00
9206 04:42:31.508603 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9207 04:42:31.508688 CPU: 00
9208 04:42:31.512445 Done allocating resources.
9209 04:42:31.515285 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9210 04:42:31.519083 Enabling resources...
9211 04:42:31.519183 done.
9212 04:42:31.525706 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9213 04:42:31.525805 Initializing devices...
9214 04:42:31.528614 Root Device init
9215 04:42:31.528697 init hardware done!
9216 04:42:31.532122 0x00000018: ctrlr->caps
9217 04:42:31.535245 52.000 MHz: ctrlr->f_max
9218 04:42:31.535330 0.400 MHz: ctrlr->f_min
9219 04:42:31.538946 0x40ff8080: ctrlr->voltages
9220 04:42:31.539030 sclk: 390625
9221 04:42:31.542132 Bus Width = 1
9222 04:42:31.542247 sclk: 390625
9223 04:42:31.542345 Bus Width = 1
9224 04:42:31.545857 Early init status = 3
9225 04:42:31.552339 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9226 04:42:31.555593 in-header: 03 fc 00 00 01 00 00 00
9227 04:42:31.558753 in-data: 00
9228 04:42:31.561838 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9229 04:42:31.567411 in-header: 03 fd 00 00 00 00 00 00
9230 04:42:31.570923 in-data:
9231 04:42:31.574367 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9232 04:42:31.577843 in-header: 03 fc 00 00 01 00 00 00
9233 04:42:31.580977 in-data: 00
9234 04:42:31.584446 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9235 04:42:31.589106 in-header: 03 fd 00 00 00 00 00 00
9236 04:42:31.592124 in-data:
9237 04:42:31.595218 [SSUSB] Setting up USB HOST controller...
9238 04:42:31.598806 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9239 04:42:31.602028 [SSUSB] phy power-on done.
9240 04:42:31.605488 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9241 04:42:31.612150 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9242 04:42:31.615371 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9243 04:42:31.621810 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9244 04:42:31.628622 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9245 04:42:31.635135 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9246 04:42:31.641746 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9247 04:42:31.648406 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9248 04:42:31.651897 SPM: binary array size = 0x9dc
9249 04:42:31.655161 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9250 04:42:31.662103 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9251 04:42:31.668736 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9252 04:42:31.671718 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9253 04:42:31.678439 configure_display: Starting display init
9254 04:42:31.712359 anx7625_power_on_init: Init interface.
9255 04:42:31.715088 anx7625_disable_pd_protocol: Disabled PD feature.
9256 04:42:31.718754 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9257 04:42:31.746628 anx7625_start_dp_work: Secure OCM version=00
9258 04:42:31.749816 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9259 04:42:31.764428 sp_tx_get_edid_block: EDID Block = 1
9260 04:42:31.867263 Extracted contents:
9261 04:42:31.870715 header: 00 ff ff ff ff ff ff 00
9262 04:42:31.873743 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9263 04:42:31.876984 version: 01 04
9264 04:42:31.880491 basic params: 95 1f 11 78 0a
9265 04:42:31.883724 chroma info: 76 90 94 55 54 90 27 21 50 54
9266 04:42:31.887144 established: 00 00 00
9267 04:42:31.893902 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9268 04:42:31.897540 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9269 04:42:31.904228 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9270 04:42:31.910693 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9271 04:42:31.917034 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9272 04:42:31.920624 extensions: 00
9273 04:42:31.920886 checksum: fb
9274 04:42:31.921034
9275 04:42:31.924139 Manufacturer: IVO Model 57d Serial Number 0
9276 04:42:31.927370 Made week 0 of 2020
9277 04:42:31.927671 EDID version: 1.4
9278 04:42:31.930388 Digital display
9279 04:42:31.933896 6 bits per primary color channel
9280 04:42:31.934412 DisplayPort interface
9281 04:42:31.937136 Maximum image size: 31 cm x 17 cm
9282 04:42:31.940687 Gamma: 220%
9283 04:42:31.941320 Check DPMS levels
9284 04:42:31.944094 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9285 04:42:31.947173 First detailed timing is preferred timing
9286 04:42:31.950226 Established timings supported:
9287 04:42:31.953468 Standard timings supported:
9288 04:42:31.957319 Detailed timings
9289 04:42:31.960681 Hex of detail: 383680a07038204018303c0035ae10000019
9290 04:42:31.963898 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9291 04:42:31.970541 0780 0798 07c8 0820 hborder 0
9292 04:42:31.973827 0438 043b 0447 0458 vborder 0
9293 04:42:31.977264 -hsync -vsync
9294 04:42:31.977729 Did detailed timing
9295 04:42:31.980310 Hex of detail: 000000000000000000000000000000000000
9296 04:42:31.984003 Manufacturer-specified data, tag 0
9297 04:42:31.990634 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9298 04:42:31.991054 ASCII string: InfoVision
9299 04:42:31.997118 Hex of detail: 000000fe00523134304e574635205248200a
9300 04:42:32.000679 ASCII string: R140NWF5 RH
9301 04:42:32.001097 Checksum
9302 04:42:32.001430 Checksum: 0xfb (valid)
9303 04:42:32.006996 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9304 04:42:32.010498 DSI data_rate: 832800000 bps
9305 04:42:32.014198 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9306 04:42:32.020660 anx7625_parse_edid: pixelclock(138800).
9307 04:42:32.023994 hactive(1920), hsync(48), hfp(24), hbp(88)
9308 04:42:32.027181 vactive(1080), vsync(12), vfp(3), vbp(17)
9309 04:42:32.030270 anx7625_dsi_config: config dsi.
9310 04:42:32.037284 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9311 04:42:32.049721 anx7625_dsi_config: success to config DSI
9312 04:42:32.053259 anx7625_dp_start: MIPI phy setup OK.
9313 04:42:32.056781 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9314 04:42:32.059752 mtk_ddp_mode_set invalid vrefresh 60
9315 04:42:32.063010 main_disp_path_setup
9316 04:42:32.063471 ovl_layer_smi_id_en
9317 04:42:32.066100 ovl_layer_smi_id_en
9318 04:42:32.066565 ccorr_config
9319 04:42:32.066930 aal_config
9320 04:42:32.069440 gamma_config
9321 04:42:32.069900 postmask_config
9322 04:42:32.073000 dither_config
9323 04:42:32.076431 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9324 04:42:32.083348 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9325 04:42:32.086355 Root Device init finished in 554 msecs
9326 04:42:32.086909 CPU_CLUSTER: 0 init
9327 04:42:32.095916 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9328 04:42:32.099494 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9329 04:42:32.102741 APU_MBOX 0x190000b0 = 0x10001
9330 04:42:32.106306 APU_MBOX 0x190001b0 = 0x10001
9331 04:42:32.109894 APU_MBOX 0x190005b0 = 0x10001
9332 04:42:32.113079 APU_MBOX 0x190006b0 = 0x10001
9333 04:42:32.116084 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9334 04:42:32.128562 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9335 04:42:32.141185 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9336 04:42:32.147631 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9337 04:42:32.159327 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9338 04:42:32.168421 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9339 04:42:32.171853 CPU_CLUSTER: 0 init finished in 81 msecs
9340 04:42:32.175394 Devices initialized
9341 04:42:32.178613 Show all devs... After init.
9342 04:42:32.179076 Root Device: enabled 1
9343 04:42:32.181631 CPU_CLUSTER: 0: enabled 1
9344 04:42:32.185358 CPU: 00: enabled 1
9345 04:42:32.188850 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9346 04:42:32.192022 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9347 04:42:32.195220 ELOG: NV offset 0x57f000 size 0x1000
9348 04:42:32.201925 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9349 04:42:32.208736 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9350 04:42:32.212109 ELOG: Event(17) added with size 13 at 2024-02-04 04:41:55 UTC
9351 04:42:32.215021 out: cmd=0x121: 03 db 21 01 00 00 00 00
9352 04:42:32.218900 in-header: 03 51 00 00 2c 00 00 00
9353 04:42:32.231901 in-data: 0e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9354 04:42:32.238915 ELOG: Event(A1) added with size 10 at 2024-02-04 04:41:55 UTC
9355 04:42:32.245621 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9356 04:42:32.251848 ELOG: Event(A0) added with size 9 at 2024-02-04 04:41:55 UTC
9357 04:42:32.255538 elog_add_boot_reason: Logged dev mode boot
9358 04:42:32.258591 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9359 04:42:32.262219 Finalize devices...
9360 04:42:32.262790 Devices finalized
9361 04:42:32.268629 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9362 04:42:32.271824 Writing coreboot table at 0xffe64000
9363 04:42:32.275152 0. 000000000010a000-0000000000113fff: RAMSTAGE
9364 04:42:32.278381 1. 0000000040000000-00000000400fffff: RAM
9365 04:42:32.284785 2. 0000000040100000-000000004032afff: RAMSTAGE
9366 04:42:32.288662 3. 000000004032b000-00000000545fffff: RAM
9367 04:42:32.291629 4. 0000000054600000-000000005465ffff: BL31
9368 04:42:32.295076 5. 0000000054660000-00000000ffe63fff: RAM
9369 04:42:32.301203 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9370 04:42:32.305138 7. 0000000100000000-000000023fffffff: RAM
9371 04:42:32.308358 Passing 5 GPIOs to payload:
9372 04:42:32.311662 NAME | PORT | POLARITY | VALUE
9373 04:42:32.315185 EC in RW | 0x000000aa | low | undefined
9374 04:42:32.322005 EC interrupt | 0x00000005 | low | undefined
9375 04:42:32.325111 TPM interrupt | 0x000000ab | high | undefined
9376 04:42:32.328245 SD card detect | 0x00000011 | high | undefined
9377 04:42:32.335138 speaker enable | 0x00000093 | high | undefined
9378 04:42:32.338330 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9379 04:42:32.341460 in-header: 03 f9 00 00 02 00 00 00
9380 04:42:32.342091 in-data: 02 00
9381 04:42:32.344825 ADC[4]: Raw value=900663 ID=7
9382 04:42:32.347872 ADC[3]: Raw value=212810 ID=1
9383 04:42:32.348342 RAM Code: 0x71
9384 04:42:32.351411 ADC[6]: Raw value=74502 ID=0
9385 04:42:32.354627 ADC[5]: Raw value=212072 ID=1
9386 04:42:32.355096 SKU Code: 0x1
9387 04:42:32.361506 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3234
9388 04:42:32.364855 coreboot table: 964 bytes.
9389 04:42:32.368287 IMD ROOT 0. 0xfffff000 0x00001000
9390 04:42:32.371320 IMD SMALL 1. 0xffffe000 0x00001000
9391 04:42:32.374468 RO MCACHE 2. 0xffffc000 0x00001104
9392 04:42:32.377857 CONSOLE 3. 0xfff7c000 0x00080000
9393 04:42:32.381332 FMAP 4. 0xfff7b000 0x00000452
9394 04:42:32.384729 TIME STAMP 5. 0xfff7a000 0x00000910
9395 04:42:32.387727 VBOOT WORK 6. 0xfff66000 0x00014000
9396 04:42:32.391129 RAMOOPS 7. 0xffe66000 0x00100000
9397 04:42:32.394621 COREBOOT 8. 0xffe64000 0x00002000
9398 04:42:32.395197 IMD small region:
9399 04:42:32.398032 IMD ROOT 0. 0xffffec00 0x00000400
9400 04:42:32.401196 VPD 1. 0xffffeb80 0x0000006c
9401 04:42:32.404499 MMC STATUS 2. 0xffffeb60 0x00000004
9402 04:42:32.411102 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9403 04:42:32.414311 Probing TPM: done!
9404 04:42:32.418155 Connected to device vid:did:rid of 1ae0:0028:00
9405 04:42:32.427852 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9406 04:42:32.431207 Initialized TPM device CR50 revision 0
9407 04:42:32.435094 Checking cr50 for pending updates
9408 04:42:32.438599 Reading cr50 TPM mode
9409 04:42:32.446830 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9410 04:42:32.453613 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9411 04:42:32.493740 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9412 04:42:32.497302 Checking segment from ROM address 0x40100000
9413 04:42:32.500476 Checking segment from ROM address 0x4010001c
9414 04:42:32.507054 Loading segment from ROM address 0x40100000
9415 04:42:32.507626 code (compression=0)
9416 04:42:32.517101 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9417 04:42:32.523813 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9418 04:42:32.524391 it's not compressed!
9419 04:42:32.530489 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9420 04:42:32.533895 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9421 04:42:32.554134 Loading segment from ROM address 0x4010001c
9422 04:42:32.554687 Entry Point 0x80000000
9423 04:42:32.557672 Loaded segments
9424 04:42:32.560781 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9425 04:42:32.567497 Jumping to boot code at 0x80000000(0xffe64000)
9426 04:42:32.574184 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9427 04:42:32.580966 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9428 04:42:32.588574 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9429 04:42:32.591732 Checking segment from ROM address 0x40100000
9430 04:42:32.595174 Checking segment from ROM address 0x4010001c
9431 04:42:32.602042 Loading segment from ROM address 0x40100000
9432 04:42:32.602598 code (compression=1)
9433 04:42:32.608416 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9434 04:42:32.618645 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9435 04:42:32.619267 using LZMA
9436 04:42:32.626857 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9437 04:42:32.633559 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9438 04:42:32.636853 Loading segment from ROM address 0x4010001c
9439 04:42:32.637413 Entry Point 0x54601000
9440 04:42:32.640438 Loaded segments
9441 04:42:32.643674 NOTICE: MT8192 bl31_setup
9442 04:42:32.650370 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9443 04:42:32.653929 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9444 04:42:32.657325 WARNING: region 0:
9445 04:42:32.660742 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9446 04:42:32.661309 WARNING: region 1:
9447 04:42:32.667212 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9448 04:42:32.670613 WARNING: region 2:
9449 04:42:32.673811 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9450 04:42:32.677268 WARNING: region 3:
9451 04:42:32.680390 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9452 04:42:32.683655 WARNING: region 4:
9453 04:42:32.687276 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9454 04:42:32.689819 WARNING: region 5:
9455 04:42:32.693113 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 04:42:32.696517 WARNING: region 6:
9457 04:42:32.700004 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 04:42:32.700108 WARNING: region 7:
9459 04:42:32.706504 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 04:42:32.713646 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9461 04:42:32.717225 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9462 04:42:32.720293 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9463 04:42:32.726990 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9464 04:42:32.730237 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9465 04:42:32.733855 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9466 04:42:32.740406 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9467 04:42:32.743959 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9468 04:42:32.747295 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9469 04:42:32.753840 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9470 04:42:32.757312 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9471 04:42:32.760438 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9472 04:42:32.767258 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9473 04:42:32.770859 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9474 04:42:32.777511 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9475 04:42:32.780976 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9476 04:42:32.784394 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9477 04:42:32.790776 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9478 04:42:32.794261 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9479 04:42:32.797358 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9480 04:42:32.804032 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9481 04:42:32.807310 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9482 04:42:32.814166 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9483 04:42:32.817728 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9484 04:42:32.820962 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9485 04:42:32.828062 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9486 04:42:32.830871 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9487 04:42:32.838003 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9488 04:42:32.840964 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9489 04:42:32.844437 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9490 04:42:32.850561 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9491 04:42:32.854002 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9492 04:42:32.857628 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9493 04:42:32.864296 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9494 04:42:32.867677 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9495 04:42:32.871098 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9496 04:42:32.874502 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9497 04:42:32.881423 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9498 04:42:32.884759 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9499 04:42:32.888016 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9500 04:42:32.891409 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9501 04:42:32.897884 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9502 04:42:32.900790 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9503 04:42:32.904186 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9504 04:42:32.908093 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9505 04:42:32.914563 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9506 04:42:32.918016 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9507 04:42:32.921430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9508 04:42:32.927719 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9509 04:42:32.931104 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9510 04:42:32.934555 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9511 04:42:32.941532 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9512 04:42:32.944925 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9513 04:42:32.951231 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9514 04:42:32.954618 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9515 04:42:32.958282 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9516 04:42:32.964594 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9517 04:42:32.967645 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9518 04:42:32.974478 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9519 04:42:32.978129 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9520 04:42:32.985141 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9521 04:42:32.987836 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9522 04:42:32.991323 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9523 04:42:32.998401 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9524 04:42:33.001719 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9525 04:42:33.008104 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9526 04:42:33.011279 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9527 04:42:33.018300 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9528 04:42:33.021681 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9529 04:42:33.025183 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9530 04:42:33.031520 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9531 04:42:33.034758 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9532 04:42:33.041315 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9533 04:42:33.044816 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9534 04:42:33.051350 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9535 04:42:33.054787 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9536 04:42:33.057915 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9537 04:42:33.064835 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9538 04:42:33.067636 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9539 04:42:33.074417 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9540 04:42:33.077869 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9541 04:42:33.084440 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9542 04:42:33.087593 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9543 04:42:33.094459 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9544 04:42:33.097970 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9545 04:42:33.101294 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9546 04:42:33.108350 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9547 04:42:33.111661 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9548 04:42:33.118093 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9549 04:42:33.121528 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9550 04:42:33.124805 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9551 04:42:33.131264 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9552 04:42:33.134881 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9553 04:42:33.141882 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9554 04:42:33.145209 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9555 04:42:33.151504 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9556 04:42:33.154598 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9557 04:42:33.158095 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9558 04:42:33.161311 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9559 04:42:33.168026 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9560 04:42:33.171578 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9561 04:42:33.174942 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9562 04:42:33.181540 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9563 04:42:33.185034 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9564 04:42:33.191186 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9565 04:42:33.194911 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9566 04:42:33.198328 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9567 04:42:33.204824 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9568 04:42:33.208484 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9569 04:42:33.215195 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9570 04:42:33.218516 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9571 04:42:33.221842 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9572 04:42:33.228122 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9573 04:42:33.231425 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9574 04:42:33.238610 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9575 04:42:33.242061 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9576 04:42:33.245394 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9577 04:42:33.248654 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9578 04:42:33.255014 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9579 04:42:33.258633 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9580 04:42:33.262147 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9581 04:42:33.265084 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9582 04:42:33.268770 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9583 04:42:33.275365 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9584 04:42:33.278877 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9585 04:42:33.285567 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9586 04:42:33.288744 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9587 04:42:33.292323 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9588 04:42:33.298567 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9589 04:42:33.301936 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9590 04:42:33.308819 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9591 04:42:33.312195 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9592 04:42:33.314996 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9593 04:42:33.322024 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9594 04:42:33.325641 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9595 04:42:33.328946 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9596 04:42:33.335562 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9597 04:42:33.339137 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9598 04:42:33.345544 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9599 04:42:33.348887 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9600 04:42:33.352268 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9601 04:42:33.358703 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9602 04:42:33.362235 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9603 04:42:33.365573 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9604 04:42:33.372443 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9605 04:42:33.375689 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9606 04:42:33.382584 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9607 04:42:33.385775 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9608 04:42:33.389582 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9609 04:42:33.395764 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9610 04:42:33.399218 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9611 04:42:33.402715 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9612 04:42:33.409017 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9613 04:42:33.412698 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9614 04:42:33.419240 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9615 04:42:33.422782 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9616 04:42:33.425897 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9617 04:42:33.432576 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9618 04:42:33.435776 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9619 04:42:33.442510 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9620 04:42:33.445881 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9621 04:42:33.448982 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9622 04:42:33.455467 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9623 04:42:33.458867 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9624 04:42:33.465861 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9625 04:42:33.469301 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9626 04:42:33.472211 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9627 04:42:33.478814 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9628 04:42:33.482388 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9629 04:42:33.485756 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9630 04:42:33.492254 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9631 04:42:33.495363 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9632 04:42:33.502125 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9633 04:42:33.505614 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9634 04:42:33.508675 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9635 04:42:33.515402 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9636 04:42:33.518775 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9637 04:42:33.525493 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9638 04:42:33.528661 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9639 04:42:33.531846 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9640 04:42:33.538730 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9641 04:42:33.542120 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9642 04:42:33.548840 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9643 04:42:33.552158 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9644 04:42:33.555457 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9645 04:42:33.562054 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9646 04:42:33.565320 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9647 04:42:33.568447 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9648 04:42:33.575341 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9649 04:42:33.578588 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9650 04:42:33.585116 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9651 04:42:33.588673 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9652 04:42:33.595153 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9653 04:42:33.598472 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9654 04:42:33.601982 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9655 04:42:33.608574 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9656 04:42:33.611652 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9657 04:42:33.618459 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9658 04:42:33.621801 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9659 04:42:33.628855 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9660 04:42:33.631821 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9661 04:42:33.635119 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9662 04:42:33.641845 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9663 04:42:33.645185 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9664 04:42:33.651862 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9665 04:42:33.654680 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9666 04:42:33.658489 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9667 04:42:33.664783 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9668 04:42:33.668321 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9669 04:42:33.674611 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9670 04:42:33.678522 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9671 04:42:33.681284 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9672 04:42:33.688261 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9673 04:42:33.691453 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9674 04:42:33.698225 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9675 04:42:33.701875 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9676 04:42:33.708100 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9677 04:42:33.711644 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9678 04:42:33.715138 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9679 04:42:33.721706 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9680 04:42:33.724929 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9681 04:42:33.731688 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9682 04:42:33.734774 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9683 04:42:33.738014 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9684 04:42:33.744620 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9685 04:42:33.747714 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9686 04:42:33.754826 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9687 04:42:33.757983 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9688 04:42:33.761386 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9689 04:42:33.768277 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9690 04:42:33.771347 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9691 04:42:33.774552 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9692 04:42:33.778200 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9693 04:42:33.785108 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9694 04:42:33.788040 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9695 04:42:33.791257 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9696 04:42:33.798291 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9697 04:42:33.801754 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9698 04:42:33.804428 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9699 04:42:33.811220 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9700 04:42:33.814715 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9701 04:42:33.821793 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9702 04:42:33.824397 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9703 04:42:33.827899 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9704 04:42:33.834542 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9705 04:42:33.838149 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9706 04:42:33.841087 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9707 04:42:33.848029 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9708 04:42:33.851102 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9709 04:42:33.854636 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9710 04:42:33.861347 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9711 04:42:33.864532 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9712 04:42:33.871054 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9713 04:42:33.874397 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9714 04:42:33.877871 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9715 04:42:33.884164 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9716 04:42:33.887409 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9717 04:42:33.890888 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9718 04:42:33.897557 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9719 04:42:33.901031 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9720 04:42:33.904000 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9721 04:42:33.910928 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9722 04:42:33.914181 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9723 04:42:33.921010 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9724 04:42:33.924389 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9725 04:42:33.927366 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9726 04:42:33.934078 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9727 04:42:33.937508 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9728 04:42:33.940911 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9729 04:42:33.947782 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9730 04:42:33.950656 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9731 04:42:33.954513 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9732 04:42:33.957348 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9733 04:42:33.960828 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9734 04:42:33.967286 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9735 04:42:33.970638 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9736 04:42:33.973668 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9737 04:42:33.977176 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9738 04:42:33.983993 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9739 04:42:33.987166 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9740 04:42:33.990287 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9741 04:42:33.997133 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9742 04:42:34.000458 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9743 04:42:34.003805 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9744 04:42:34.010379 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9745 04:42:34.013898 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9746 04:42:34.020467 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9747 04:42:34.024090 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9748 04:42:34.030360 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9749 04:42:34.033798 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9750 04:42:34.036848 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9751 04:42:34.043536 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9752 04:42:34.046922 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9753 04:42:34.050381 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9754 04:42:34.057148 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9755 04:42:34.060473 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9756 04:42:34.066627 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9757 04:42:34.070008 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9758 04:42:34.073095 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9759 04:42:34.080125 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9760 04:42:34.083028 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9761 04:42:34.089837 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9762 04:42:34.093032 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9763 04:42:34.100289 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9764 04:42:34.103189 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9765 04:42:34.106478 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9766 04:42:34.113008 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9767 04:42:34.116533 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9768 04:42:34.123298 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9769 04:42:34.126530 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9770 04:42:34.129506 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9771 04:42:34.136514 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9772 04:42:34.139818 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9773 04:42:34.146468 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9774 04:42:34.149907 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9775 04:42:34.153382 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9776 04:42:34.159885 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9777 04:42:34.163087 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9778 04:42:34.169646 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9779 04:42:34.173073 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9780 04:42:34.179387 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9781 04:42:34.183033 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9782 04:42:34.186537 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9783 04:42:34.193172 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9784 04:42:34.196628 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9785 04:42:34.199792 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9786 04:42:34.206325 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9787 04:42:34.209684 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9788 04:42:34.216397 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9789 04:42:34.219434 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9790 04:42:34.222854 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9791 04:42:34.229825 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9792 04:42:34.233051 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9793 04:42:34.239570 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9794 04:42:34.243125 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9795 04:42:34.249594 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9796 04:42:34.253236 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9797 04:42:34.256118 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9798 04:42:34.263321 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9799 04:42:34.266316 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9800 04:42:34.273354 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9801 04:42:34.276742 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9802 04:42:34.279916 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9803 04:42:34.286450 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9804 04:42:34.289600 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9805 04:42:34.296430 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9806 04:42:34.299945 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9807 04:42:34.302991 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9808 04:42:34.309713 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9809 04:42:34.313059 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9810 04:42:34.319706 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9811 04:42:34.323111 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9812 04:42:34.326558 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9813 04:42:34.333115 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9814 04:42:34.336405 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9815 04:42:34.343220 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9816 04:42:34.346209 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9817 04:42:34.352532 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9818 04:42:34.355990 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9819 04:42:34.359802 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9820 04:42:34.366206 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9821 04:42:34.369972 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9822 04:42:34.376372 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9823 04:42:34.379102 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9824 04:42:34.386159 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9825 04:42:34.389342 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9826 04:42:34.395965 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9827 04:42:34.399226 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9828 04:42:34.402732 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9829 04:42:34.409092 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9830 04:42:34.412637 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9831 04:42:34.419534 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9832 04:42:34.422614 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9833 04:42:34.429355 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9834 04:42:34.432684 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9835 04:42:34.438842 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9836 04:42:34.442310 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9837 04:42:34.445862 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9838 04:42:34.452014 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9839 04:42:34.455309 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9840 04:42:34.462209 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9841 04:42:34.465776 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9842 04:42:34.472028 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9843 04:42:34.475434 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9844 04:42:34.478370 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9845 04:42:34.485532 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9846 04:42:34.488609 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9847 04:42:34.495171 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9848 04:42:34.498548 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9849 04:42:34.505209 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9850 04:42:34.508780 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9851 04:42:34.515291 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9852 04:42:34.518788 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9853 04:42:34.521568 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9854 04:42:34.528026 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9855 04:42:34.531379 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9856 04:42:34.538588 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9857 04:42:34.541617 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9858 04:42:34.548077 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9859 04:42:34.551246 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9860 04:42:34.558129 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9861 04:42:34.561508 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9862 04:42:34.564286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9863 04:42:34.571318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9864 04:42:34.574959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9865 04:42:34.581319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9866 04:42:34.584747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9867 04:42:34.587558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9868 04:42:34.594323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9869 04:42:34.598185 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9870 04:42:34.604239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9871 04:42:34.607621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9872 04:42:34.614620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9873 04:42:34.617828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9874 04:42:34.624675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9875 04:42:34.627888 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9876 04:42:34.634443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9877 04:42:34.637373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9878 04:42:34.644281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9879 04:42:34.647404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9880 04:42:34.654251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9881 04:42:34.657688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9882 04:42:34.664557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9883 04:42:34.667239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9884 04:42:34.674264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9885 04:42:34.677749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9886 04:42:34.684200 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9887 04:42:34.687668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9888 04:42:34.694354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9889 04:42:34.697277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9890 04:42:34.704114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9891 04:42:34.707205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9892 04:42:34.713764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9893 04:42:34.717289 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9894 04:42:34.723860 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9895 04:42:34.724441 INFO: [APUAPC] vio 0
9896 04:42:34.730363 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9897 04:42:34.733649 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9898 04:42:34.736819 INFO: [APUAPC] D0_APC_0: 0x400510
9899 04:42:34.740347 INFO: [APUAPC] D0_APC_1: 0x0
9900 04:42:34.743546 INFO: [APUAPC] D0_APC_2: 0x1540
9901 04:42:34.746801 INFO: [APUAPC] D0_APC_3: 0x0
9902 04:42:34.750376 INFO: [APUAPC] D1_APC_0: 0xffffffff
9903 04:42:34.753571 INFO: [APUAPC] D1_APC_1: 0xffffffff
9904 04:42:34.757302 INFO: [APUAPC] D1_APC_2: 0x3fffff
9905 04:42:34.759986 INFO: [APUAPC] D1_APC_3: 0x0
9906 04:42:34.763442 INFO: [APUAPC] D2_APC_0: 0xffffffff
9907 04:42:34.767035 INFO: [APUAPC] D2_APC_1: 0xffffffff
9908 04:42:34.770156 INFO: [APUAPC] D2_APC_2: 0x3fffff
9909 04:42:34.773637 INFO: [APUAPC] D2_APC_3: 0x0
9910 04:42:34.776749 INFO: [APUAPC] D3_APC_0: 0xffffffff
9911 04:42:34.780326 INFO: [APUAPC] D3_APC_1: 0xffffffff
9912 04:42:34.783240 INFO: [APUAPC] D3_APC_2: 0x3fffff
9913 04:42:34.786844 INFO: [APUAPC] D3_APC_3: 0x0
9914 04:42:34.790391 INFO: [APUAPC] D4_APC_0: 0xffffffff
9915 04:42:34.793336 INFO: [APUAPC] D4_APC_1: 0xffffffff
9916 04:42:34.796587 INFO: [APUAPC] D4_APC_2: 0x3fffff
9917 04:42:34.797159 INFO: [APUAPC] D4_APC_3: 0x0
9918 04:42:34.803188 INFO: [APUAPC] D5_APC_0: 0xffffffff
9919 04:42:34.806436 INFO: [APUAPC] D5_APC_1: 0xffffffff
9920 04:42:34.809925 INFO: [APUAPC] D5_APC_2: 0x3fffff
9921 04:42:34.810470 INFO: [APUAPC] D5_APC_3: 0x0
9922 04:42:34.812903 INFO: [APUAPC] D6_APC_0: 0xffffffff
9923 04:42:34.816498 INFO: [APUAPC] D6_APC_1: 0xffffffff
9924 04:42:34.819870 INFO: [APUAPC] D6_APC_2: 0x3fffff
9925 04:42:34.823290 INFO: [APUAPC] D6_APC_3: 0x0
9926 04:42:34.826408 INFO: [APUAPC] D7_APC_0: 0xffffffff
9927 04:42:34.829749 INFO: [APUAPC] D7_APC_1: 0xffffffff
9928 04:42:34.832828 INFO: [APUAPC] D7_APC_2: 0x3fffff
9929 04:42:34.836325 INFO: [APUAPC] D7_APC_3: 0x0
9930 04:42:34.839221 INFO: [APUAPC] D8_APC_0: 0xffffffff
9931 04:42:34.843861 INFO: [APUAPC] D8_APC_1: 0xffffffff
9932 04:42:34.846306 INFO: [APUAPC] D8_APC_2: 0x3fffff
9933 04:42:34.849448 INFO: [APUAPC] D8_APC_3: 0x0
9934 04:42:34.852690 INFO: [APUAPC] D9_APC_0: 0xffffffff
9935 04:42:34.856170 INFO: [APUAPC] D9_APC_1: 0xffffffff
9936 04:42:34.859466 INFO: [APUAPC] D9_APC_2: 0x3fffff
9937 04:42:34.862945 INFO: [APUAPC] D9_APC_3: 0x0
9938 04:42:34.866322 INFO: [APUAPC] D10_APC_0: 0xffffffff
9939 04:42:34.869254 INFO: [APUAPC] D10_APC_1: 0xffffffff
9940 04:42:34.872809 INFO: [APUAPC] D10_APC_2: 0x3fffff
9941 04:42:34.876187 INFO: [APUAPC] D10_APC_3: 0x0
9942 04:42:34.879544 INFO: [APUAPC] D11_APC_0: 0xffffffff
9943 04:42:34.882992 INFO: [APUAPC] D11_APC_1: 0xffffffff
9944 04:42:34.886085 INFO: [APUAPC] D11_APC_2: 0x3fffff
9945 04:42:34.889501 INFO: [APUAPC] D11_APC_3: 0x0
9946 04:42:34.892902 INFO: [APUAPC] D12_APC_0: 0xffffffff
9947 04:42:34.896319 INFO: [APUAPC] D12_APC_1: 0xffffffff
9948 04:42:34.899267 INFO: [APUAPC] D12_APC_2: 0x3fffff
9949 04:42:34.902517 INFO: [APUAPC] D12_APC_3: 0x0
9950 04:42:34.906010 INFO: [APUAPC] D13_APC_0: 0xffffffff
9951 04:42:34.909346 INFO: [APUAPC] D13_APC_1: 0xffffffff
9952 04:42:34.912554 INFO: [APUAPC] D13_APC_2: 0x3fffff
9953 04:42:34.915888 INFO: [APUAPC] D13_APC_3: 0x0
9954 04:42:34.919198 INFO: [APUAPC] D14_APC_0: 0xffffffff
9955 04:42:34.922433 INFO: [APUAPC] D14_APC_1: 0xffffffff
9956 04:42:34.926018 INFO: [APUAPC] D14_APC_2: 0x3fffff
9957 04:42:34.929210 INFO: [APUAPC] D14_APC_3: 0x0
9958 04:42:34.932390 INFO: [APUAPC] D15_APC_0: 0xffffffff
9959 04:42:34.935468 INFO: [APUAPC] D15_APC_1: 0xffffffff
9960 04:42:34.938590 INFO: [APUAPC] D15_APC_2: 0x3fffff
9961 04:42:34.942103 INFO: [APUAPC] D15_APC_3: 0x0
9962 04:42:34.945327 INFO: [APUAPC] APC_CON: 0x4
9963 04:42:34.948584 INFO: [NOCDAPC] D0_APC_0: 0x0
9964 04:42:34.952115 INFO: [NOCDAPC] D0_APC_1: 0x0
9965 04:42:34.955144 INFO: [NOCDAPC] D1_APC_0: 0x0
9966 04:42:34.958512 INFO: [NOCDAPC] D1_APC_1: 0xfff
9967 04:42:34.961770 INFO: [NOCDAPC] D2_APC_0: 0x0
9968 04:42:34.961855 INFO: [NOCDAPC] D2_APC_1: 0xfff
9969 04:42:34.965123 INFO: [NOCDAPC] D3_APC_0: 0x0
9970 04:42:34.968592 INFO: [NOCDAPC] D3_APC_1: 0xfff
9971 04:42:34.972124 INFO: [NOCDAPC] D4_APC_0: 0x0
9972 04:42:34.975068 INFO: [NOCDAPC] D4_APC_1: 0xfff
9973 04:42:34.978494 INFO: [NOCDAPC] D5_APC_0: 0x0
9974 04:42:34.981781 INFO: [NOCDAPC] D5_APC_1: 0xfff
9975 04:42:34.984811 INFO: [NOCDAPC] D6_APC_0: 0x0
9976 04:42:34.988300 INFO: [NOCDAPC] D6_APC_1: 0xfff
9977 04:42:34.991873 INFO: [NOCDAPC] D7_APC_0: 0x0
9978 04:42:34.994813 INFO: [NOCDAPC] D7_APC_1: 0xfff
9979 04:42:34.994886 INFO: [NOCDAPC] D8_APC_0: 0x0
9980 04:42:34.998306 INFO: [NOCDAPC] D8_APC_1: 0xfff
9981 04:42:35.001846 INFO: [NOCDAPC] D9_APC_0: 0x0
9982 04:42:35.004741 INFO: [NOCDAPC] D9_APC_1: 0xfff
9983 04:42:35.008195 INFO: [NOCDAPC] D10_APC_0: 0x0
9984 04:42:35.011580 INFO: [NOCDAPC] D10_APC_1: 0xfff
9985 04:42:35.014833 INFO: [NOCDAPC] D11_APC_0: 0x0
9986 04:42:35.018102 INFO: [NOCDAPC] D11_APC_1: 0xfff
9987 04:42:35.021467 INFO: [NOCDAPC] D12_APC_0: 0x0
9988 04:42:35.024851 INFO: [NOCDAPC] D12_APC_1: 0xfff
9989 04:42:35.028360 INFO: [NOCDAPC] D13_APC_0: 0x0
9990 04:42:35.031324 INFO: [NOCDAPC] D13_APC_1: 0xfff
9991 04:42:35.034599 INFO: [NOCDAPC] D14_APC_0: 0x0
9992 04:42:35.037993 INFO: [NOCDAPC] D14_APC_1: 0xfff
9993 04:42:35.041334 INFO: [NOCDAPC] D15_APC_0: 0x0
9994 04:42:35.041417 INFO: [NOCDAPC] D15_APC_1: 0xfff
9995 04:42:35.044711 INFO: [NOCDAPC] APC_CON: 0x4
9996 04:42:35.048187 INFO: [APUAPC] set_apusys_apc done
9997 04:42:35.051516 INFO: [DEVAPC] devapc_init done
9998 04:42:35.057993 INFO: GICv3 without legacy support detected.
9999 04:42:35.061353 INFO: ARM GICv3 driver initialized in EL3
10000 04:42:35.064852 INFO: Maximum SPI INTID supported: 639
10001 04:42:35.067744 INFO: BL31: Initializing runtime services
10002 04:42:35.074542 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10003 04:42:35.078071 INFO: SPM: enable CPC mode
10004 04:42:35.081068 INFO: mcdi ready for mcusys-off-idle and system suspend
10005 04:42:35.087757 INFO: BL31: Preparing for EL3 exit to normal world
10006 04:42:35.090898 INFO: Entry point address = 0x80000000
10007 04:42:35.090982 INFO: SPSR = 0x8
10008 04:42:35.097805
10009 04:42:35.097887
10010 04:42:35.097961
10011 04:42:35.101453 Starting depthcharge on Spherion...
10012 04:42:35.101536
10013 04:42:35.101602 Wipe memory regions:
10014 04:42:35.101662
10015 04:42:35.102325 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10016 04:42:35.102427 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10017 04:42:35.102509 Setting prompt string to ['asurada:']
10018 04:42:35.102587 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10019 04:42:35.104261 [0x00000040000000, 0x00000054600000)
10020 04:42:35.227060
10021 04:42:35.227171 [0x00000054660000, 0x00000080000000)
10022 04:42:35.487342
10023 04:42:35.487497 [0x000000821a7280, 0x000000ffe64000)
10024 04:42:36.232131
10025 04:42:36.232270 [0x00000100000000, 0x00000240000000)
10026 04:42:38.122106
10027 04:42:38.125528 Initializing XHCI USB controller at 0x11200000.
10028 04:42:39.163490
10029 04:42:39.166929 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10030 04:42:39.167016
10031 04:42:39.167082
10032 04:42:39.167145
10033 04:42:39.167425 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10035 04:42:39.267764 asurada: tftpboot 192.168.201.1 12699799/tftp-deploy-s8jh0h48/kernel/image.itb 12699799/tftp-deploy-s8jh0h48/kernel/cmdline
10036 04:42:39.267910 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10037 04:42:39.268025 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10038 04:42:39.272198 tftpboot 192.168.201.1 12699799/tftp-deploy-s8jh0h48/kernel/image.ittp-deploy-s8jh0h48/kernel/cmdline
10039 04:42:39.272284
10040 04:42:39.272350 Waiting for link
10041 04:42:39.432267
10042 04:42:39.432371 R8152: Initializing
10043 04:42:39.432439
10044 04:42:39.435553 Version 9 (ocp_data = 6010)
10045 04:42:39.435636
10046 04:42:39.438972 R8152: Done initializing
10047 04:42:39.439056
10048 04:42:39.439121 Adding net device
10049 04:42:41.384927
10050 04:42:41.385082 done.
10051 04:42:41.385150
10052 04:42:41.385240 MAC: 00:e0:4c:72:2d:d6
10053 04:42:41.385329
10054 04:42:41.387935 Sending DHCP discover... done.
10055 04:42:41.388019
10056 04:42:41.391490 Waiting for reply... done.
10057 04:42:41.391574
10058 04:42:41.395191 Sending DHCP request... done.
10059 04:42:41.395289
10060 04:42:41.395383 Waiting for reply... done.
10061 04:42:41.395449
10062 04:42:41.397914 My ip is 192.168.201.21
10063 04:42:41.398045
10064 04:42:41.401461 The DHCP server ip is 192.168.201.1
10065 04:42:41.401543
10066 04:42:41.404863 TFTP server IP predefined by user: 192.168.201.1
10067 04:42:41.404947
10068 04:42:41.411320 Bootfile predefined by user: 12699799/tftp-deploy-s8jh0h48/kernel/image.itb
10069 04:42:41.411443
10070 04:42:41.414824 Sending tftp read request... done.
10071 04:42:41.414920
10072 04:42:41.417847 Waiting for the transfer...
10073 04:42:41.417934
10074 04:42:41.675497 00000000 ################################################################
10075 04:42:41.675638
10076 04:42:41.931996 00080000 ################################################################
10077 04:42:41.932132
10078 04:42:42.186495 00100000 ################################################################
10079 04:42:42.186634
10080 04:42:42.445485 00180000 ################################################################
10081 04:42:42.445628
10082 04:42:42.701308 00200000 ################################################################
10083 04:42:42.701443
10084 04:42:42.957727 00280000 ################################################################
10085 04:42:42.957857
10086 04:42:43.212920 00300000 ################################################################
10087 04:42:43.213065
10088 04:42:43.467680 00380000 ################################################################
10089 04:42:43.467816
10090 04:42:43.724016 00400000 ################################################################
10091 04:42:43.724145
10092 04:42:43.978760 00480000 ################################################################
10093 04:42:43.978888
10094 04:42:44.232962 00500000 ################################################################
10095 04:42:44.233132
10096 04:42:44.489091 00580000 ################################################################
10097 04:42:44.489222
10098 04:42:44.745231 00600000 ################################################################
10099 04:42:44.745364
10100 04:42:45.001129 00680000 ################################################################
10101 04:42:45.001264
10102 04:42:45.254643 00700000 ################################################################
10103 04:42:45.254792
10104 04:42:45.510699 00780000 ################################################################
10105 04:42:45.510858
10106 04:42:45.766840 00800000 ################################################################
10107 04:42:45.766982
10108 04:42:46.023059 00880000 ################################################################
10109 04:42:46.023197
10110 04:42:46.278766 00900000 ################################################################
10111 04:42:46.278911
10112 04:42:46.535328 00980000 ################################################################
10113 04:42:46.535467
10114 04:42:46.791338 00a00000 ################################################################
10115 04:42:46.791477
10116 04:42:47.048001 00a80000 ################################################################
10117 04:42:47.048135
10118 04:42:47.301487 00b00000 ################################################################
10119 04:42:47.301615
10120 04:42:47.556649 00b80000 ################################################################
10121 04:42:47.556780
10122 04:42:47.812856 00c00000 ################################################################
10123 04:42:47.812983
10124 04:42:48.068795 00c80000 ################################################################
10125 04:42:48.068921
10126 04:42:48.323429 00d00000 ################################################################
10127 04:42:48.323572
10128 04:42:48.579679 00d80000 ################################################################
10129 04:42:48.579833
10130 04:42:48.842660 00e00000 ################################################################
10131 04:42:48.842826
10132 04:42:49.109807 00e80000 ################################################################
10133 04:42:49.110007
10134 04:42:49.381272 00f00000 ################################################################
10135 04:42:49.381420
10136 04:42:49.643945 00f80000 ################################################################
10137 04:42:49.644081
10138 04:42:49.898884 01000000 ################################################################
10139 04:42:49.899022
10140 04:42:50.153534 01080000 ################################################################
10141 04:42:50.153681
10142 04:42:50.402826 01100000 ################################################################
10143 04:42:50.402967
10144 04:42:50.651801 01180000 ################################################################
10145 04:42:50.651937
10146 04:42:50.900442 01200000 ################################################################
10147 04:42:50.900579
10148 04:42:51.148763 01280000 ################################################################
10149 04:42:51.148922
10150 04:42:51.401410 01300000 ################################################################
10151 04:42:51.401583
10152 04:42:51.654402 01380000 ################################################################
10153 04:42:51.654532
10154 04:42:51.910535 01400000 ################################################################
10155 04:42:51.910671
10156 04:42:52.160295 01480000 ################################################################
10157 04:42:52.160465
10158 04:42:52.408938 01500000 ################################################################
10159 04:42:52.409080
10160 04:42:52.658840 01580000 ################################################################
10161 04:42:52.659004
10162 04:42:52.910225 01600000 ################################################################
10163 04:42:52.910422
10164 04:42:53.164341 01680000 ################################################################
10165 04:42:53.164492
10166 04:42:53.412639 01700000 ################################################################
10167 04:42:53.412861
10168 04:42:53.662137 01780000 ################################################################
10169 04:42:53.662268
10170 04:42:53.911707 01800000 ################################################################
10171 04:42:53.911860
10172 04:42:54.162455 01880000 ################################################################
10173 04:42:54.162589
10174 04:42:54.418762 01900000 ################################################################
10175 04:42:54.418897
10176 04:42:54.676452 01980000 ################################################################
10177 04:42:54.676589
10178 04:42:54.932222 01a00000 ################################################################
10179 04:42:54.932359
10180 04:42:55.184702 01a80000 ################################################################
10181 04:42:55.184835
10182 04:42:55.442389 01b00000 ################################################################
10183 04:42:55.442523
10184 04:42:55.703603 01b80000 ################################################################
10185 04:42:55.703747
10186 04:42:55.958232 01c00000 ################################################################
10187 04:42:55.958368
10188 04:42:56.207793 01c80000 ################################################################
10189 04:42:56.207922
10190 04:42:56.459897 01d00000 ################################################################
10191 04:42:56.460060
10192 04:42:56.710373 01d80000 ################################################################
10193 04:42:56.710506
10194 04:42:56.959475 01e00000 ################################################################
10195 04:42:56.959603
10196 04:42:57.211800 01e80000 ################################################################
10197 04:42:57.211926
10198 04:42:57.568880 01f00000 ################################################################
10199 04:42:57.569484
10200 04:42:57.842056 01f80000 ################################################################
10201 04:42:57.842189
10202 04:42:58.090785 02000000 ################################################################
10203 04:42:58.090918
10204 04:42:58.339097 02080000 ################################################################
10205 04:42:58.339236
10206 04:42:58.588552 02100000 ################################################################
10207 04:42:58.588690
10208 04:42:58.836388 02180000 ################################################################
10209 04:42:58.836558
10210 04:42:59.085245 02200000 ################################################################
10211 04:42:59.085379
10212 04:42:59.333508 02280000 ################################################################
10213 04:42:59.333641
10214 04:42:59.581364 02300000 ################################################################
10215 04:42:59.581498
10216 04:42:59.829485 02380000 ################################################################
10217 04:42:59.829621
10218 04:43:00.157672 02400000 ################################################################
10219 04:43:00.158223
10220 04:43:00.488090 02480000 ################################################################
10221 04:43:00.488220
10222 04:43:00.766806 02500000 ################################################################
10223 04:43:00.766958
10224 04:43:01.049972 02580000 ################################################################
10225 04:43:01.050102
10226 04:43:01.333158 02600000 ################################################################
10227 04:43:01.333338
10228 04:43:01.627618 02680000 ################################################################
10229 04:43:01.627764
10230 04:43:01.881428 02700000 ################################################################
10231 04:43:01.881567
10232 04:43:02.131055 02780000 ################################################################
10233 04:43:02.131185
10234 04:43:02.381045 02800000 ################################################################
10235 04:43:02.381165
10236 04:43:02.630091 02880000 ################################################################
10237 04:43:02.630247
10238 04:43:02.879497 02900000 ################################################################
10239 04:43:02.879627
10240 04:43:03.153543 02980000 ################################################################
10241 04:43:03.153721
10242 04:43:03.431978 02a00000 ################################################################
10243 04:43:03.432118
10244 04:43:03.710541 02a80000 ################################################################
10245 04:43:03.710669
10246 04:43:03.959569 02b00000 ################################################################
10247 04:43:03.959697
10248 04:43:04.209062 02b80000 ################################################################
10249 04:43:04.209186
10250 04:43:04.458261 02c00000 ################################################################
10251 04:43:04.458385
10252 04:43:04.707054 02c80000 ################################################################
10253 04:43:04.707178
10254 04:43:04.955367 02d00000 ################################################################
10255 04:43:04.955514
10256 04:43:05.204263 02d80000 ################################################################
10257 04:43:05.204390
10258 04:43:05.452533 02e00000 ################################################################
10259 04:43:05.452655
10260 04:43:05.701453 02e80000 ################################################################
10261 04:43:05.701579
10262 04:43:05.949584 02f00000 ################################################################
10263 04:43:05.949727
10264 04:43:06.198326 02f80000 ################################################################
10265 04:43:06.198442
10266 04:43:06.446798 03000000 ################################################################
10267 04:43:06.446924
10268 04:43:06.695933 03080000 ################################################################
10269 04:43:06.696060
10270 04:43:06.943929 03100000 ################################################################
10271 04:43:06.944058
10272 04:43:07.193342 03180000 ################################################################
10273 04:43:07.193472
10274 04:43:07.442091 03200000 ################################################################
10275 04:43:07.442220
10276 04:43:07.691247 03280000 ################################################################
10277 04:43:07.691365
10278 04:43:07.939740 03300000 ################################################################
10279 04:43:07.939876
10280 04:43:08.189190 03380000 ################################################################
10281 04:43:08.189313
10282 04:43:08.438665 03400000 ################################################################
10283 04:43:08.438784
10284 04:43:08.687458 03480000 ################################################################
10285 04:43:08.687574
10286 04:43:08.935528 03500000 ################################################################
10287 04:43:08.935662
10288 04:43:09.184657 03580000 ################################################################
10289 04:43:09.184779
10290 04:43:09.434409 03600000 ################################################################
10291 04:43:09.434530
10292 04:43:09.683334 03680000 ################################################################
10293 04:43:09.683469
10294 04:43:09.931002 03700000 ################################################################
10295 04:43:09.931149
10296 04:43:10.179347 03780000 ################################################################
10297 04:43:10.179482
10298 04:43:10.430014 03800000 ################################################################
10299 04:43:10.430147
10300 04:43:10.681248 03880000 ################################################################
10301 04:43:10.681386
10302 04:43:10.932435 03900000 ################################################################
10303 04:43:10.932600
10304 04:43:11.183022 03980000 ################################################################
10305 04:43:11.183149
10306 04:43:11.432702 03a00000 ################################################################
10307 04:43:11.432874
10308 04:43:11.681691 03a80000 ################################################################
10309 04:43:11.681830
10310 04:43:11.928800 03b00000 ################################################################
10311 04:43:11.928971
10312 04:43:12.175520 03b80000 ################################################################
10313 04:43:12.175685
10314 04:43:12.425076 03c00000 ################################################################
10315 04:43:12.425230
10316 04:43:12.706046 03c80000 ################################################################
10317 04:43:12.706183
10318 04:43:12.953629 03d00000 ################################################################
10319 04:43:12.953784
10320 04:43:13.203765 03d80000 ################################################################
10321 04:43:13.203925
10322 04:43:13.451024 03e00000 ################################################################
10323 04:43:13.451176
10324 04:43:13.697377 03e80000 ################################################################
10325 04:43:13.697538
10326 04:43:13.941856 03f00000 ################################################################
10327 04:43:13.942037
10328 04:43:14.185856 03f80000 ################################################################
10329 04:43:14.186040
10330 04:43:14.429375 04000000 ################################################################
10331 04:43:14.429522
10332 04:43:14.673506 04080000 ################################################################
10333 04:43:14.673675
10334 04:43:14.856951 04100000 ################################################# done.
10335 04:43:14.857093
10336 04:43:14.859963 The bootfile was 68551378 bytes long.
10337 04:43:14.860056
10338 04:43:14.863736 Sending tftp read request... done.
10339 04:43:14.863863
10340 04:43:14.863957 Waiting for the transfer...
10341 04:43:14.866612
10342 04:43:14.866697 00000000 # done.
10343 04:43:14.866766
10344 04:43:14.873559 Command line loaded dynamically from TFTP file: 12699799/tftp-deploy-s8jh0h48/kernel/cmdline
10345 04:43:14.873681
10346 04:43:14.886706 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10347 04:43:14.886842
10348 04:43:14.890150 Loading FIT.
10349 04:43:14.890231
10350 04:43:14.893633 Image ramdisk-1 has 56453557 bytes.
10351 04:43:14.893736
10352 04:43:14.896614 Image fdt-1 has 47278 bytes.
10353 04:43:14.896715
10354 04:43:14.896806 Image kernel-1 has 12048508 bytes.
10355 04:43:14.900046
10356 04:43:14.906924 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10357 04:43:14.907071
10358 04:43:14.926216 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10359 04:43:14.926367
10360 04:43:14.929743 Choosing best match conf-1 for compat google,spherion-rev2.
10361 04:43:14.934168
10362 04:43:14.938981 Connected to device vid:did:rid of 1ae0:0028:00
10363 04:43:14.947179
10364 04:43:14.950120 tpm_get_response: command 0x17b, return code 0x0
10365 04:43:14.950211
10366 04:43:14.953595 ec_init: CrosEC protocol v3 supported (256, 248)
10367 04:43:14.957478
10368 04:43:14.960833 tpm_cleanup: add release locality here.
10369 04:43:14.960926
10370 04:43:14.960994 Shutting down all USB controllers.
10371 04:43:14.964117
10372 04:43:14.964203 Removing current net device
10373 04:43:14.964271
10374 04:43:14.970879 Exiting depthcharge with code 4 at timestamp: 69143210
10375 04:43:14.971014
10376 04:43:14.974380 LZMA decompressing kernel-1 to 0x821a6718
10377 04:43:14.974470
10378 04:43:14.977389 LZMA decompressing kernel-1 to 0x40000000
10379 04:43:16.477274
10380 04:43:16.477844 jumping to kernel
10381 04:43:16.480259 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10382 04:43:16.480854 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10383 04:43:16.481287 Setting prompt string to ['Linux version [0-9]']
10384 04:43:16.481679 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10385 04:43:16.482121 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10386 04:43:16.558936
10387 04:43:16.562255 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10388 04:43:16.566050 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10389 04:43:16.566672 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10390 04:43:16.567155 Setting prompt string to []
10391 04:43:16.567589 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10392 04:43:16.568003 Using line separator: #'\n'#
10393 04:43:16.568350 No login prompt set.
10394 04:43:16.568714 Parsing kernel messages
10395 04:43:16.569037 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10396 04:43:16.569611 [login-action] Waiting for messages, (timeout 00:03:44)
10397 04:43:16.585210 [ 0.000000] Linux version 6.1.75-cip14-rt8 (KernelCI@build-j97480-arm64-gcc-10-defconfig-arm64-chromebook-6n26j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024
10398 04:43:16.588528 [ 0.000000] random: crng init done
10399 04:43:16.595332 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10400 04:43:16.598378 [ 0.000000] efi: UEFI not found.
10401 04:43:16.605179 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10402 04:43:16.614872 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10403 04:43:16.624908 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10404 04:43:16.631561 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10405 04:43:16.638427 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10406 04:43:16.644558 [ 0.000000] printk: bootconsole [mtk8250] enabled
10407 04:43:16.651094 [ 0.000000] NUMA: No NUMA configuration found
10408 04:43:16.658105 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10409 04:43:16.664511 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10410 04:43:16.664850 [ 0.000000] Zone ranges:
10411 04:43:16.671183 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10412 04:43:16.674525 [ 0.000000] DMA32 empty
10413 04:43:16.681309 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10414 04:43:16.684260 [ 0.000000] Movable zone start for each node
10415 04:43:16.687508 [ 0.000000] Early memory node ranges
10416 04:43:16.694765 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10417 04:43:16.700796 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10418 04:43:16.707208 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10419 04:43:16.713968 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10420 04:43:16.720578 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10421 04:43:16.727377 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10422 04:43:16.783798 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10423 04:43:16.790513 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10424 04:43:16.797209 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10425 04:43:16.800559 [ 0.000000] psci: probing for conduit method from DT.
10426 04:43:16.806984 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10427 04:43:16.810407 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10428 04:43:16.816822 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10429 04:43:16.820215 [ 0.000000] psci: SMC Calling Convention v1.2
10430 04:43:16.826592 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10431 04:43:16.830026 [ 0.000000] Detected VIPT I-cache on CPU0
10432 04:43:16.836843 [ 0.000000] CPU features: detected: GIC system register CPU interface
10433 04:43:16.843467 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10434 04:43:16.850179 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10435 04:43:16.856550 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10436 04:43:16.863292 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10437 04:43:16.872802 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10438 04:43:16.876602 [ 0.000000] alternatives: applying boot alternatives
10439 04:43:16.883072 [ 0.000000] Fallback order for Node 0: 0
10440 04:43:16.889817 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10441 04:43:16.892845 [ 0.000000] Policy zone: Normal
10442 04:43:16.906441 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10443 04:43:16.916024 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10444 04:43:16.927032 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10445 04:43:16.936836 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10446 04:43:16.943656 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10447 04:43:16.946846 <6>[ 0.000000] software IO TLB: area num 8.
10448 04:43:17.003141 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10449 04:43:17.152689 <6>[ 0.000000] Memory: 7912064K/8385536K available (18048K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 616K bss, 440704K reserved, 32768K cma-reserved)
10450 04:43:17.159003 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10451 04:43:17.165755 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10452 04:43:17.169097 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10453 04:43:17.175424 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10454 04:43:17.182299 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10455 04:43:17.185741 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10456 04:43:17.195383 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10457 04:43:17.201894 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10458 04:43:17.208689 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10459 04:43:17.215329 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10460 04:43:17.218861 <6>[ 0.000000] GICv3: 608 SPIs implemented
10461 04:43:17.221830 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10462 04:43:17.228717 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10463 04:43:17.232095 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10464 04:43:17.238598 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10465 04:43:17.251759 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10466 04:43:17.261799 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10467 04:43:17.272037 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10468 04:43:17.279125 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10469 04:43:17.292286 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10470 04:43:17.298907 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10471 04:43:17.305690 <6>[ 0.009185] Console: colour dummy device 80x25
10472 04:43:17.315614 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10473 04:43:17.321902 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10474 04:43:17.325489 <6>[ 0.029221] LSM: Security Framework initializing
10475 04:43:17.332125 <6>[ 0.034159] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10476 04:43:17.341966 <6>[ 0.042023] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10477 04:43:17.348400 <6>[ 0.051487] cblist_init_generic: Setting adjustable number of callback queues.
10478 04:43:17.355095 <6>[ 0.058930] cblist_init_generic: Setting shift to 3 and lim to 1.
10479 04:43:17.365341 <6>[ 0.065308] cblist_init_generic: Setting adjustable number of callback queues.
10480 04:43:17.368711 <6>[ 0.072734] cblist_init_generic: Setting shift to 3 and lim to 1.
10481 04:43:17.375528 <6>[ 0.079165] rcu: Hierarchical SRCU implementation.
10482 04:43:17.381861 <6>[ 0.079167] rcu: Max phase no-delay instances is 1000.
10483 04:43:17.388568 <6>[ 0.079190] printk: bootconsole [mtk8250] printing thread started
10484 04:43:17.395267 <6>[ 0.097493] EFI services will not be available.
10485 04:43:17.398575 <6>[ 0.097694] smp: Bringing up secondary CPUs ...
10486 04:43:17.401850 <6>[ 0.098002] Detected VIPT I-cache on CPU1
10487 04:43:17.411605 <6>[ 0.098072] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10488 04:43:17.417958 <6>[ 0.098104] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10489 04:43:17.426993 <6>[ 0.125979] Detected VIPT I-cache on CPU2
10490 04:43:17.434031 <6>[ 0.126026] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10491 04:43:17.443989 <6>[ 0.126042] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10492 04:43:17.446885 <6>[ 0.126294] Detected VIPT I-cache on CPU3
10493 04:43:17.453746 <6>[ 0.126340] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10494 04:43:17.460196 <6>[ 0.126354] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10495 04:43:17.463781 <6>[ 0.126660] CPU features: detected: Spectre-v4
10496 04:43:17.470322 <6>[ 0.126667] CPU features: detected: Spectre-BHB
10497 04:43:17.473814 <6>[ 0.126672] Detected PIPT I-cache on CPU4
10498 04:43:17.480033 <6>[ 0.126730] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10499 04:43:17.486649 <6>[ 0.126747] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10500 04:43:17.493452 <6>[ 0.127035] Detected PIPT I-cache on CPU5
10501 04:43:17.500417 <6>[ 0.127096] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10502 04:43:17.506593 <6>[ 0.127113] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10503 04:43:17.509884 <6>[ 0.127385] Detected PIPT I-cache on CPU6
10504 04:43:17.516723 <6>[ 0.127449] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10505 04:43:17.523322 <6>[ 0.127465] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10506 04:43:17.529848 <6>[ 0.127754] Detected PIPT I-cache on CPU7
10507 04:43:17.536653 <6>[ 0.127818] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10508 04:43:17.543223 <6>[ 0.127834] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10509 04:43:17.546430 <6>[ 0.127880] smp: Brought up 1 node, 8 CPUs
10510 04:43:17.553051 <6>[ 0.127885] SMP: Total of 8 processors activated.
10511 04:43:17.556279 <6>[ 0.127887] CPU features: detected: 32-bit EL0 Support
10512 04:43:17.566514 <6>[ 0.127889] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10513 04:43:17.573106 <6>[ 0.127892] CPU features: detected: Common not Private translations
10514 04:43:17.579497 <6>[ 0.127894] CPU features: detected: CRC32 instructions
10515 04:43:17.583005 <6>[ 0.127896] CPU features: detected: RCpc load-acquire (LDAPR)
10516 04:43:17.589197 <6>[ 0.127898] CPU features: detected: LSE atomic instructions
10517 04:43:17.595966 <6>[ 0.127899] CPU features: detected: Privileged Access Never
10518 04:43:17.602687 <6>[ 0.127901] CPU features: detected: RAS Extension Support
10519 04:43:17.609586 <6>[ 0.127904] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10520 04:43:17.612837 <6>[ 0.127974] CPU: All CPU(s) started at EL2
10521 04:43:17.619031 <6>[ 0.127976] alternatives: applying system-wide alternatives
10522 04:43:17.622451 <6>[ 0.141085] devtmpfs: initialized
10523 04:43:17.651025 � ������͡�ㅉ������ɥ��郪��Bzɑ�Ɂ�b��ʲ�ѕͥ5R�<6>[ 0.355868] pr<intk: console [ttyS0] enabled
10524 04:43:17.654339 6>[ 0.225706] pnp: PnP ACPI: disabled
10525 04:43:17.661856 <6>[ 0.355867] printk: console [ttyS0] printing thread started
10526 04:43:17.668357 <6>[ 0.355871] printk: bootconsole [mtk8250] disabled
10527 04:43:17.675043 <6>[ 0.364063] printk: bootconsole [mtk8250] printing thread stopped
10528 04:43:17.678239 <6>[ 0.365326] SuperH (H)SCI(F) driver initialized
10529 04:43:17.681604 <6>[ 0.365857] msm_serial: driver initialized
10530 04:43:17.691500 <6>[ 0.370562] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10531 04:43:17.701526 <6>[ 0.370593] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10532 04:43:17.716161 <6>[ 0.370622] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10533 04:43:17.721161 <6>[ 0.370651] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10534 04:43:17.729958 <6>[ 0.370674] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10535 04:43:17.745490 <6>[ 0.370704] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10536 04:43:17.749074 <6>[ 0.370732] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10537 04:43:17.752992 <6>[ 0.370840] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10538 04:43:17.763778 <6>[ 0.370870] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10539 04:43:17.763878 <6>[ 0.380232] loop: module loaded
10540 04:43:17.771176 <6>[ 0.382557] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10541 04:43:17.774644 <4>[ 0.399660] mtk-pmic-keys: Failed to locate of_node [id: -1]
10542 04:43:17.781117 <6>[ 0.400730] megasas: 07.719.03.00-rc1
10543 04:43:17.784466 <6>[ 0.410255] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10544 04:43:17.791186 <6>[ 0.412842] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10545 04:43:17.798042 <6>[ 0.424697] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10546 04:43:17.807845 <6>[ 0.478325] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10547 04:43:19.921181 <6>[ 2.624016] Freeing initrd memory: 55124K
10548 04:43:19.929564 <6>[ 2.630115] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10549 04:43:19.936115 <6>[ 2.634852] tun: Universal TUN/TAP device driver, 1.6
10550 04:43:19.939312 <6>[ 2.635606] thunder_xcv, ver 1.0
10551 04:43:19.942856 <6>[ 2.635625] thunder_bgx, ver 1.0
10552 04:43:19.946297 <6>[ 2.635639] nicpf, ver 1.0
10553 04:43:19.953041 <6>[ 2.636713] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10554 04:43:19.959168 <6>[ 2.636717] hns3: Copyright (c) 2017 Huawei Corporation.
10555 04:43:19.962620 <6>[ 2.636740] hclge is initializing
10556 04:43:19.969411 <6>[ 2.636755] e1000: Intel(R) PRO/1000 Network Driver
10557 04:43:19.972331 <6>[ 2.636756] e1000: Copyright (c) 1999-2006 Intel Corporation.
10558 04:43:19.979942 <6>[ 2.636772] e1000e: Intel(R) PRO/1000 Network Driver
10559 04:43:19.983768 <6>[ 2.636774] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10560 04:43:19.990698 <6>[ 2.636789] igb: Intel(R) Gigabit Ethernet Network Driver
10561 04:43:19.997279 <6>[ 2.636791] igb: Copyright (c) 2007-2014 Intel Corporation.
10562 04:43:20.003897 <6>[ 2.636808] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10563 04:43:20.011025 <6>[ 2.636810] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10564 04:43:20.014276 <6>[ 2.637099] sky2: driver version 1.30
10565 04:43:20.017847 <6>[ 2.638169] VFIO - User Level meta-driver version: 0.3
10566 04:43:20.024390 <6>[ 2.640956] usbcore: registered new interface driver usb-storage
10567 04:43:20.030849 <6>[ 2.641144] usbcore: registered new device driver onboard-usb-hub
10568 04:43:20.037652 <6>[ 2.643932] mt6397-rtc mt6359-rtc: registered as rtc0
10569 04:43:20.044400 <6>[ 2.644085] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-04T04:42:42 UTC (1707021762)
10570 04:43:20.050698 <6>[ 2.644695] i2c_dev: i2c /dev entries driver
10571 04:43:20.057237 <6>[ 2.651837] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10572 04:43:20.060701 <6>[ 2.666833] cpu cpu0: EM: created perf domain
10573 04:43:20.067296 <6>[ 2.667164] cpu cpu4: EM: created perf domain
10574 04:43:20.073993 <6>[ 2.668166] sdhci: Secure Digital Host Controller Interface driver
10575 04:43:20.077430 <6>[ 2.668167] sdhci: Copyright(c) Pierre Ossman
10576 04:43:20.083897 <6>[ 2.668525] Synopsys Designware Multimedia Card Interface Driver
10577 04:43:20.090720 <6>[ 2.668894] sdhci-pltfm: SDHCI platform and OF driver helper
10578 04:43:20.093541 <6>[ 2.671929] mmc0: CQHCI version 5.10
10579 04:43:20.100352 <6>[ 2.676871] ledtrig-cpu: registered to indicate activity on CPUs
10580 04:43:20.107113 <6>[ 2.679514] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10581 04:43:20.113617 <6>[ 2.681075] usbcore: registered new interface driver usbhid
10582 04:43:20.116961 <6>[ 2.681081] usbhid: USB HID core driver
10583 04:43:20.123504 <6>[ 2.681408] spi_master spi0: will run message pump with realtime priority
10584 04:43:20.136834 <6>[ 2.713902] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10585 04:43:20.150284 <6>[ 2.715784] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10586 04:43:20.156494 <6>[ 2.716946] cros-ec-spi spi0.0: Chrome EC device registered
10587 04:43:20.166914 <6>[ 2.735469] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10588 04:43:20.169996 <6>[ 2.739098] NET: Registered PF_PACKET protocol family
10589 04:43:20.173152 <6>[ 2.739229] 9pnet: Installing 9P2000 support
10590 04:43:20.179924 <5>[ 2.739290] Key type dns_resolver registered
10591 04:43:20.183553 <6>[ 2.739756] registered taskstats version 1
10592 04:43:20.189714 <5>[ 2.739776] Loading compiled-in X.509 certificates
10593 04:43:20.199949 <4>[ 2.755475] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 04:43:20.209597 <4>[ 2.755647] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10595 04:43:20.216220 <3>[ 2.755657] debugfs: File 'uA_load' in directory '/' already present!
10596 04:43:20.223099 <3>[ 2.755664] debugfs: File 'min_uV' in directory '/' already present!
10597 04:43:20.229853 <3>[ 2.755667] debugfs: File 'max_uV' in directory '/' already present!
10598 04:43:20.236491 <3>[ 2.755670] debugfs: File 'constraint_flags' in directory '/' already present!
10599 04:43:20.246092 <3>[ 2.757808] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10600 04:43:20.252854 <6>[ 2.764532] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10601 04:43:20.256227 <6>[ 2.765138] xhci-mtk 11200000.usb: xHCI Host Controller
10602 04:43:20.266064 <6>[ 2.765157] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10603 04:43:20.275773 <6>[ 2.765374] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10604 04:43:20.279168 <6>[ 2.765422] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10605 04:43:20.285876 <6>[ 2.765557] xhci-mtk 11200000.usb: xHCI Host Controller
10606 04:43:20.292538 <6>[ 2.765567] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10607 04:43:20.302204 <6>[ 2.765585] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10608 04:43:20.305682 <6>[ 2.766261] hub 1-0:1.0: USB hub found
10609 04:43:20.308941 <6>[ 2.766287] hub 1-0:1.0: 1 port detected
10610 04:43:20.319115 <6>[ 2.766516] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10611 04:43:20.322144 <6>[ 2.766920] hub 2-0:1.0: USB hub found
10612 04:43:20.325658 <6>[ 2.766941] hub 2-0:1.0: 1 port detected
10613 04:43:20.328824 <6>[ 2.770160] mtk-msdc 11f70000.mmc: Got CD GPIO
10614 04:43:20.335476 <6>[ 2.771530] mmc0: Command Queue Engine enabled
10615 04:43:20.342056 <6>[ 2.771540] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10616 04:43:20.345435 <6>[ 2.772633] mmcblk0: mmc0:0001 DA4128 116 GiB
10617 04:43:20.352142 <6>[ 2.775847] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10618 04:43:20.358652 <6>[ 2.776852] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10619 04:43:20.362050 <6>[ 2.777498] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10620 04:43:20.368723 <6>[ 2.778120] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10621 04:43:20.378433 <6>[ 2.790476] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10622 04:43:20.385256 <6>[ 2.790484] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10623 04:43:20.395251 <4>[ 2.790638] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10624 04:43:20.402107 <6>[ 2.791269] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10625 04:43:20.408646 <6>[ 2.791272] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10626 04:43:20.418515 <6>[ 2.791401] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10627 04:43:20.425190 <6>[ 2.791413] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10628 04:43:20.434931 <6>[ 2.791417] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10629 04:43:20.441658 <6>[ 2.791426] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10630 04:43:20.451347 <6>[ 2.792836] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10631 04:43:20.457920 <6>[ 2.792857] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10632 04:43:20.468086 <6>[ 2.792863] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10633 04:43:20.474426 <6>[ 2.792870] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10634 04:43:20.484670 <6>[ 2.792877] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10635 04:43:20.491527 <6>[ 2.792883] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10636 04:43:20.501055 <6>[ 2.792889] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10637 04:43:20.507960 <6>[ 2.792896] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10638 04:43:20.517641 <6>[ 2.792903] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10639 04:43:20.524340 <6>[ 2.792909] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10640 04:43:20.534191 <6>[ 2.792916] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10641 04:43:20.540835 <6>[ 2.792922] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10642 04:43:20.550900 <6>[ 2.792929] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10643 04:43:20.557829 <6>[ 2.792935] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10644 04:43:20.567355 <6>[ 2.792942] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10645 04:43:20.574170 <6>[ 2.793463] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10646 04:43:20.580858 <6>[ 2.794624] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10647 04:43:20.587157 <6>[ 2.795290] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10648 04:43:20.593838 <6>[ 2.795935] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10649 04:43:20.600387 <6>[ 2.796596] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10650 04:43:20.610476 <6>[ 2.796792] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10651 04:43:20.617082 <6>[ 2.796808] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10652 04:43:20.626719 <6>[ 2.796813] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10653 04:43:20.636805 <6>[ 2.796823] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10654 04:43:20.646654 <6>[ 2.796829] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10655 04:43:20.656561 <6>[ 2.796835] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10656 04:43:20.666886 <6>[ 2.796840] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10657 04:43:20.673461 <6>[ 2.796846] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10658 04:43:20.683263 <6>[ 2.796851] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10659 04:43:20.693168 <6>[ 2.796857] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10660 04:43:20.703092 <6>[ 2.796862] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10661 04:43:20.713294 <6>[ 2.797350] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10662 04:43:20.719888 <6>[ 3.185627] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10663 04:43:20.723134 <6>[ 3.337259] hub 1-1:1.0: USB hub found
10664 04:43:20.726081 <6>[ 3.337596] hub 1-1:1.0: 4 ports detected
10665 04:43:20.733066 <6>[ 3.341009] hub 1-1:1.0: USB hub found
10666 04:43:20.736004 <6>[ 3.341263] hub 1-1:1.0: 4 ports detected
10667 04:43:20.764301 <6>[ 3.461847] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10668 04:43:20.785271 <6>[ 3.487032] hub 2-1:1.0: USB hub found
10669 04:43:20.788656 <6>[ 3.487469] hub 2-1:1.0: 3 ports detected
10670 04:43:20.792152 <6>[ 3.490984] hub 2-1:1.0: USB hub found
10671 04:43:20.795092 <6>[ 3.491351] hub 2-1:1.0: 3 ports detected
10672 04:43:20.956802 <6>[ 3.653764] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10673 04:43:21.077367 <6>[ 3.781004] hub 1-1.4:1.0: USB hub found
10674 04:43:21.081035 <6>[ 3.781382] hub 1-1.4:1.0: 2 ports detected
10675 04:43:21.084216 <6>[ 3.784787] hub 1-1.4:1.0: USB hub found
10676 04:43:21.090532 <6>[ 3.785104] hub 1-1.4:1.0: 2 ports detected
10677 04:43:21.164660 <6>[ 3.861812] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10678 04:43:21.376727 <6>[ 4.073755] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10679 04:43:21.560440 <6>[ 4.257766] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10680 04:43:32.401110 <6>[ 15.106828] ALSA device list:
10681 04:43:32.407491 <6>[ 15.106850] No soundcards found.
10682 04:43:32.410962 <6>[ 15.111428] Freeing unused kernel memory: 8448K
10683 04:43:32.413850 <6>[ 15.111613] Run /init as init process
10684 04:43:32.459942 <6>[ 15.162540] NET: Registered PF_INET6 protocol family
10685 04:43:32.463276 <6>[ 15.163549] Segment Routing with IPv6
10686 04:43:32.467179
10687 04:43:32.473526 Welcome to [1mDebian GNU/Linu<6>[ 15.163562] In-situ OAM (IOAM) with IPv6
10688 04:43:32.496691 x 11 (bullseye)<30>[ 15.174950] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10689 04:43:32.496832 [0m!
10690 04:43:32.496902
10691 04:43:32.503504 <30>[ 15.175530] systemd[1]: Detected architecture arm64.
10692 04:43:32.512087 <30>[ 15.213638] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10693 04:43:32.671662 <30>[ 15.371575] systemd[1]: Queued start job for default target Graphical Interface.
10694 04:43:32.704519 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 15.406593] systemd[1]: Created slice system-getty.slice.
10695 04:43:32.708051 m-getty.slice[0m.
10696 04:43:32.731537 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 15.430383] systemd[1]: Created slice system-modprobe.slice.
10697 04:43:32.731682 m-modprobe.slice[0m.
10698 04:43:32.756471 [[0;32m OK [0m] Created slic<30>[ 15.458746] systemd[1]: Created slice system-serial\x2dgetty.slice.
10699 04:43:32.763212 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10700 04:43:32.780954 [[0;32m OK [0m] Created slic<30>[ 15.483055] systemd[1]: Created slice User and Session Slice.
10701 04:43:32.784572 e [0;1;39mUser and Session Slice[0m.
10702 04:43:32.807104 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 15.505939] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10703 04:43:32.810443 ssword …ts to Console Directory Watch[0m.
10704 04:43:32.831256 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 15.529986] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10705 04:43:32.834460 sword R…uests to Wall Directory Watch[0m.
10706 04:43:32.858545 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 15.553832] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10707 04:43:32.865196 <30>[ 15.554080] systemd[1]: Reached target Local Encrypted Volumes.
10708 04:43:32.868686 l Encrypted Volumes[0m.
10709 04:43:32.887680 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 15.589831] systemd[1]: Reached target Paths.
10710 04:43:32.887810 s[0m.
10711 04:43:32.911048 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 15.609764] systemd[1]: Reached target Remote File Systems.
10712 04:43:32.911204 te File Systems[0m.
10713 04:43:32.932413 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 15.634154] systemd[1]: Reached target Slices.
10714 04:43:32.932538 es[0m.
10715 04:43:32.951765 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 15.653795] systemd[1]: Reached target Swap.
10716 04:43:32.951896 [0m.
10717 04:43:32.975771 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 15.674311] systemd[1]: Listening on initctl Compatibility Named Pipe.
10718 04:43:32.978786 l Compatibility Named Pipe[0m.
10719 04:43:32.988851 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 15.689691] systemd[1]: Listening on Journal Audit Socket.
10720 04:43:32.992126 l Audit Socket[0m.
10721 04:43:33.011486 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 15.710310] systemd[1]: Listening on Journal Socket (/dev/log).
10722 04:43:33.011605 l Socket (/dev/log)[0m.
10723 04:43:33.032901 [[0;32m OK [0m] Listening on<30>[ 15.735060] systemd[1]: Listening on Journal Socket.
10724 04:43:33.036201 [0;1;39mJournal Socket[0m.
10725 04:43:33.052644 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 15.754423] systemd[1]: Listening on udev Control Socket.
10726 04:43:33.055387 ontrol Socket[0m.
10727 04:43:33.077066 [[0;32m OK [0m] Listening on<30>[ 15.778860] systemd[1]: Listening on udev Kernel Socket.
10728 04:43:33.080068 [0;1;39mudev Kernel Socket[0m.
10729 04:43:33.126941 Mounting [0;1;39mHuge Pages File Syste<30>[ 15.825818] systemd[1]: Mounting Huge Pages File System...
10730 04:43:33.127090 m[0m...
10731 04:43:33.151459 Mounting [0;1;39mPOSIX Message Queue F<30>[ 15.850230] systemd[1]: Mounting POSIX Message Queue File System...
10732 04:43:33.151600 ile System[0m...
10733 04:43:33.179393 Mounting [0;1;39mKernel Debug File Sys<30>[ 15.878131] systemd[1]: Mounting Kernel Debug File System...
10734 04:43:33.179502 tem[0m...
10735 04:43:33.199264 <30>[ 15.898302] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10736 04:43:33.209378 <30>[ 15.903272] systemd[1]: Starting Create list of static device nodes for the current kernel...
10737 04:43:33.215931 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10738 04:43:33.271029 Starting [0;1;39mLoad Kernel Module co<30>[ 15.969984] systemd[1]: Starting Load Kernel Module configfs...
10739 04:43:33.271165 nfigfs[0m...
10740 04:43:33.291995 Starting [0;1;39mLoad Kernel Module dr<30>[ 15.993780] systemd[1]: Starting Load Kernel Module drm...
10741 04:43:33.295028 m[0m...
10742 04:43:33.314917 <30>[ 16.013834] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10743 04:43:33.343907 Starting [0;1;39mJournal Service[0m..<30>[ 16.046073] systemd[1]: Starting Journal Service...
10744 04:43:33.344005 .
10745 04:43:33.366645 Startin<30>[ 16.068823] systemd[1]: Starting Load Kernel Modules...
10746 04:43:33.370108 g [0;1;39mLoad Kernel Modules[0m...
10747 04:43:33.390235 Startin<30>[ 16.092240] systemd[1]: Starting Remount Root and Kernel File Systems...
10748 04:43:33.396704 g [0;1;39mRemount Root and Kernel File Systems[0m...
10749 04:43:33.418592 Starting [0;1;39mColdplug All udev Dev<30>[ 16.117574] systemd[1]: Starting Coldplug All udev Devices...
10750 04:43:33.418735 ices[0m...
10751 04:43:33.435591 [[0;32m OK [<30>[ 16.140904] systemd[1]: Started Journal Service.
10752 04:43:33.441838 0m] Started [0;1;39mJournal Service[0m.
10753 04:43:33.460294 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10754 04:43:33.477184 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10755 04:43:33.492873 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10756 04:43:33.512727 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10757 04:43:33.530424 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10758 04:43:33.549393 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10759 04:43:33.570388 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10760 04:43:33.590845 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10761 04:43:33.608034 See 'systemctl status systemd-remount-fs.service' for details.
10762 04:43:33.665021 Mounting [0;1;39mKernel Configuration File System[0m...
10763 04:43:33.685509 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10764 04:43:33.699387 <46>[ 16.401279] systemd-journald[190]: Received client request to flush runtime journal.
10765 04:43:33.710590 Starting [0;1;39mLoad/Save Random Seed[0m...
10766 04:43:33.729663 Starting [0;1;39mApply Kernel Variables[0m...
10767 04:43:33.750179 Starting [0;1;39mCreate System Users[0m...
10768 04:43:33.768471 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10769 04:43:33.785436 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10770 04:43:33.805621 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10771 04:43:33.818160 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10772 04:43:33.834251 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10773 04:43:33.849901 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10774 04:43:33.889042 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10775 04:43:33.914309 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10776 04:43:33.933103 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10777 04:43:33.952499 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10778 04:43:34.001471 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10779 04:43:34.031926 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10780 04:43:34.048917 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10781 04:43:34.068498 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10782 04:43:34.133602 Starting [0;1;39mNetwork Time Synchronization[0m...
10783 04:43:34.162769 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10784 04:43:34.203947 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10785 04:43:34.218951 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10786 04:43:34.247374 <6>[ 16.946488] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10787 04:43:34.253901 <6>[ 16.946530] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10788 04:43:34.264503 <6>[ 16.946540] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10789 04:43:34.270831 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10790 04:43:34.288242 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10791 04:43:34.294777 <6>[ 16.995223] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10792 04:43:34.304473 [[0;32m OK [0m] Reached target [0;1;39mSyst<6>[ 17.007429] remoteproc remoteproc0: scp is available
10793 04:43:34.311185 em Time Set[0m.<6>[ 17.007496] remoteproc remoteproc0: powering up scp
10794 04:43:34.321373 <6>[ 17.007500] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10795 04:43:34.321481
10796 04:43:34.327770 <6>[ 17.007517] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10797 04:43:34.334501 [[0;32m OK [0m] Reached target [0;1;39mSyst<6>[ 17.038318] mc: Linux media interface: v0.10
10798 04:43:34.340996 <6>[ 17.038409] usbcore: registered new device driver r8152-cfgselector
10799 04:43:34.351203 em Time Synchron<4>[ 17.048772] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10800 04:43:34.351314 ized[0m.
10801 04:43:34.360825 <3>[ 17.049822] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10802 04:43:34.367590 <3>[ 17.049847] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10803 04:43:34.377448 <3>[ 17.049856] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10804 04:43:34.384270 <4>[ 17.050290] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10805 04:43:34.390481 <3>[ 17.062715] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10806 04:43:34.400446 <3>[ 17.062744] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10807 04:43:34.407185 <3>[ 17.062752] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10808 04:43:34.417591 <3>[ 17.062763] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10809 04:43:34.424430 [[0;32m OK [<3>[ 17.062770] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10810 04:43:34.434643 <3>[ 17.066089] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10811 04:43:34.441564 0m] Started [0;<3>[ 17.069993] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10812 04:43:34.451401 1;39mDiscard unu<3>[ 17.070018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10813 04:43:34.461607 sed blocks once <3>[ 17.070026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10814 04:43:34.472086 <3>[ 17.070113] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10815 04:43:34.472223 a week[0m.
10816 04:43:34.478866 <3>[ 17.070121] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10817 04:43:34.488695 <3>[ 17.070128] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10818 04:43:34.495533 <3>[ 17.070140] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10819 04:43:34.509094 [[0;32m OK [0m] Reached target [0;1;39mTime<3>[ 17.070146] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10820 04:43:34.509232 rs[0m.
10821 04:43:34.515411 <6>[ 17.070409] videodev: Linux video capture interface: v2.00
10822 04:43:34.522348 <3>[ 17.075012] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10823 04:43:34.529219 <6>[ 17.090641] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10824 04:43:34.535535 <6>[ 17.090664] pci_bus 0000:00: root bus resource [bus 00-ff]
10825 04:43:34.545354 [[0;32m OK [0m] Listening on [0;1;39mD-Bus <6>[ 17.090672] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10826 04:43:34.558604 System Message B<6>[ 17.090677] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10827 04:43:34.558736 us Socket[0m.
10828 04:43:34.565732 <6>[ 17.090720] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10829 04:43:34.572007 <6>[ 17.090740] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10830 04:43:34.579150 <6>[ 17.090820] pci 0000:00:00.0: supports D1 D2
10831 04:43:34.586095 <6>[ 17.090823] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10832 04:43:34.592820 <6>[ 17.096090] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10833 04:43:34.599677 <6>[ 17.106693] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10834 04:43:34.609792 [[0;32m OK [0m] Reached targ<6>[ 17.107326] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10835 04:43:34.620040 et [0;1;39mSock<6>[ 17.107356] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10836 04:43:34.620149 ets[0m.
10837 04:43:34.627485 <6>[ 17.107373] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10838 04:43:34.633826 <6>[ 17.107388] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10839 04:43:34.640592 <6>[ 17.107503] pci 0000:01:00.0: supports D1 D2
10840 04:43:34.644522 <6>[ 17.107505] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10841 04:43:34.651214 <6>[ 17.121576] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10842 04:43:34.664959 [[0;32m OK [0m] Reached targ<6>[ 17.121644] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10843 04:43:34.671749 et [0;1;39mBasi<6>[ 17.121651] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10844 04:43:34.675030 c System[0m.
10845 04:43:34.682167 <6>[ 17.121665] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10846 04:43:34.688904 <6>[ 17.121681] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10847 04:43:34.698830 <6>[ 17.121698] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10848 04:43:34.702288 <6>[ 17.121715] pci 0000:00:00.0: PCI bridge to [bus 01]
10849 04:43:34.713013 <6>[ 17.121724] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10850 04:43:34.719748 <6>[ 17.122079] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10851 04:43:34.726522 <4>[ 17.122764] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10852 04:43:34.730080 <4>[ 17.122764] Fallback method does not support PEC.
10853 04:43:34.736947 <6>[ 17.123633] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10854 04:43:34.743913 <6>[ 17.123847] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10855 04:43:34.753926 <6>[ 17.134078] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10856 04:43:34.763811 <6>[ 17.134706] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10857 04:43:34.771026 <6>[ 17.138602] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10858 04:43:34.777925 <3>[ 17.140111] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10859 04:43:34.787850 <6>[ 17.144239] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10860 04:43:34.794448 <6>[ 17.144269] remoteproc remoteproc0: remote processor scp is now up
10861 04:43:34.800985 <6>[ 17.161798] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10862 04:43:34.810837 <6>[ 17.166130] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10863 04:43:34.820644 <4>[ 17.188626] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10864 04:43:34.827357 <4>[ 17.188634] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10865 04:43:34.837068 <5>[ 17.200326] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10866 04:43:34.843876 <6>[ 17.205748] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10867 04:43:34.854120 <6>[ 17.215989] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10868 04:43:34.860283 <5>[ 17.224384] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10869 04:43:34.867200 <5>[ 17.224839] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10870 04:43:34.877077 <4>[ 17.224915] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10871 04:43:34.880099 <6>[ 17.224924] cfg80211: failed to load regulatory.db
10872 04:43:34.887022 <6>[ 17.226880] Bluetooth: Core ver 2.22
10873 04:43:34.890190 <6>[ 17.226962] NET: Registered PF_BLUETOOTH protocol family
10874 04:43:34.896973 <6>[ 17.226965] Bluetooth: HCI device and connection manager initialized
10875 04:43:34.903528 <6>[ 17.226985] Bluetooth: HCI socket layer initialized
10876 04:43:34.906770 <6>[ 17.226992] Bluetooth: L2CAP socket layer initialized
10877 04:43:34.913585 <6>[ 17.227002] Bluetooth: SCO socket layer initialized
10878 04:43:34.920003 <6>[ 17.228078] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10879 04:43:34.933330 <6>[ 17.231115] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10880 04:43:34.939628 <6>[ 17.231338] usbcore: registered new interface driver uvcvideo
10881 04:43:34.942969 <6>[ 17.241643] r8152 2-1.3:1.0 eth0: v1.12.13
10882 04:43:34.949910 <6>[ 17.241767] usbcore: registered new interface driver r8152
10883 04:43:34.956485 <3>[ 17.248273] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 04:43:34.963071 <6>[ 17.248548] usbcore: registered new interface driver cdc_ether
10885 04:43:34.972959 <3>[ 17.249041] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10886 04:43:34.979538 <6>[ 17.249193] usbcore: registered new interface driver r8153_ecm
10887 04:43:34.986315 <6>[ 17.250972] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10888 04:43:34.989286 <6>[ 17.270081] usbcore: registered new interface driver btusb
10889 04:43:35.002513 <4>[ 17.272149] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10890 04:43:35.006193 <3>[ 17.272179] Bluetooth: hci0: Failed to load firmware file (-2)
10891 04:43:35.012470 <3>[ 17.272183] Bluetooth: hci0: Failed to set up firmware (-2)
10892 04:43:35.022575 <4>[ 17.272189] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10893 04:43:35.029297 <6>[ 17.273064] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10894 04:43:35.039156 <3>[ 17.303972] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 04:43:35.045546 <3>[ 17.304826] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10896 04:43:35.055756 <3>[ 17.311990] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 04:43:35.062309 <6>[ 17.315730] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10898 04:43:35.068620 <6>[ 17.315830] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10899 04:43:35.075442 <6>[ 17.333575] mt7921e 0000:01:00.0: ASIC revision: 79610010
10900 04:43:35.085485 <3>[ 17.334026] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 04:43:35.091890 <3>[ 17.356960] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 04:43:35.101961 <3>[ 17.377169] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 04:43:35.108667 <3>[ 17.399419] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 04:43:35.118490 <6>[ 17.431919] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10905 04:43:35.118576 <6>[ 17.431919]
10906 04:43:35.128559 <6>[ 17.690178] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10907 04:43:35.135183 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10908 04:43:35.157846 Starting [0;1;39mUser Login Management[0m...
10909 04:43:35.174513 Starting [0;1;39mPermit User Sessions[0m...
10910 04:43:35.190002 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10911 04:43:35.208488 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10912 04:43:35.320351 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10913 04:43:35.330266 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10914 04:43:35.344166 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10915 04:43:35.363790 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10916 04:43:35.414037 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10917 04:43:35.433473 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10918 04:43:35.453588 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10919 04:43:35.468990 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10920 04:43:35.489135 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10921 04:43:35.549317 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10922 04:43:35.573438 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10923 04:43:35.599627 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10924 04:43:35.666135 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10925 04:43:35.680805 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10926 04:43:35.709827 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10927 04:43:35.752415
10928 04:43:35.752546
10929 04:43:35.755642 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10930 04:43:35.755725
10931 04:43:35.758876 debian-bullseye-arm64 login: root (automatic login)
10932 04:43:35.758978
10933 04:43:35.759058
10934 04:43:35.774245 Linux debian-bullseye-arm64 6.1.75-cip14-rt8 #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024 aarch64
10935 04:43:35.774346
10936 04:43:35.780491 The programs included with the Debian GNU/Linux system are free software;
10937 04:43:35.787064 the exact distribution terms for each program are described in the
10938 04:43:35.790396 individual files in /usr/share/doc/*/copyright.
10939 04:43:35.790479
10940 04:43:35.797423 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10941 04:43:35.800471 permitted by applicable law.
10942 04:43:35.800853 Matched prompt #10: / #
10944 04:43:35.801062 Setting prompt string to ['/ #']
10945 04:43:35.801155 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10947 04:43:35.801343 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10948 04:43:35.801431 start: 2.2.6 expect-shell-connection (timeout 00:03:25) [common]
10949 04:43:35.801504 Setting prompt string to ['/ #']
10950 04:43:35.801565 Forcing a shell prompt, looking for ['/ #']
10952 04:43:35.851805 / #
10953 04:43:35.851996 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10954 04:43:35.852111 Waiting using forced prompt support (timeout 00:02:30)
10955 04:43:35.852230 <6>[ 18.529919] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10956 04:43:35.856906
10957 04:43:35.857200 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10958 04:43:35.857308 start: 2.2.7 export-device-env (timeout 00:03:25) [common]
10959 04:43:35.857445 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10960 04:43:35.857544 end: 2.2 depthcharge-retry (duration 00:01:35) [common]
10961 04:43:35.857642 end: 2 depthcharge-action (duration 00:01:35) [common]
10962 04:43:35.857746 start: 3 lava-test-retry (timeout 00:08:01) [common]
10963 04:43:35.857843 start: 3.1 lava-test-shell (timeout 00:08:01) [common]
10964 04:43:35.857984 Using namespace: common
10966 04:43:35.958469 / # #
10967 04:43:35.958708 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10968 04:43:35.963715 #
10969 04:43:35.963985 Using /lava-12699799
10971 04:43:36.064378 / # export SHELL=/bin/sh
10972 04:43:36.069583 export SHELL=/bin/sh
10974 04:43:36.170147 / # . /lava-12699799/environment
10975 04:43:36.175424 . /lava-12699799/environment
10977 04:43:36.276016 / # /lava-12699799/bin/lava-test-runner /lava-12699799/0
10978 04:43:36.276198 Test shell timeout: 10s (minimum of the action and connection timeout)
10979 04:43:36.281531 /lava-12699799/bin/lava-test-runner /lava-12699799/0
10980 04:43:36.308070 + export TESTRUN_ID=0_igt-kms-medi<8>[ 19.012237] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 12699799_1.5.2.3.1>
10981 04:43:36.308377 Received signal: <STARTRUN> 0_igt-kms-mediatek 12699799_1.5.2.3.1
10982 04:43:36.308464 Starting test lava.0_igt-kms-mediatek (12699799_1.5.2.3.1)
10983 04:43:36.308573 Skipping test definition patterns.
10984 04:43:36.311453 atek
10985 04:43:36.314707 + cd /lava-12699799/0/tests/0_igt-kms-mediatek
10986 04:43:36.314791 + cat uuid
10987 04:43:36.317936 + UUID=12699799_1.5.2.3.1
10988 04:43:36.318038 + set +x
10989 04:43:36.324542 + IGT_FOR<8>[ 19.028674] <LAVA_SIGNAL_TESTSET START core_auth>
10990 04:43:36.324819 Received signal: <TESTSET> START core_auth
10991 04:43:36.324924 Starting test_set core_auth
10992 04:43:36.334492 CE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats<14>[ 19.040981] [IGT] core_auth: executing
10993 04:43:36.341166 <14>[ 19.041213] [IGT] core_auth: starting subtest getclient-simple
10994 04:43:36.351312 core_getversion<14>[ 19.041348] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
10995 04:43:36.354676 <14>[ 19.041418] [IGT] core_auth: exiting, ret=0
10996 04:43:36.361275 <8>[ 19.050626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
10997 04:43:36.361580 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
10999 04:43:36.364568 <14>[ 19.065675] [IGT] core_auth: executing
11000 04:43:36.374449 core_setmaster_<14>[ 19.077147] [IGT] core_auth: starting subtest getclient-master-drop
11001 04:43:36.384201 vs_auth drm_read<14>[ 19.077284] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11002 04:43:36.387850 <14>[ 19.077344] [IGT] core_auth: exiting, ret=0
11003 04:43:36.394126 <8>[ 19.081521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11004 04:43:36.394414 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11006 04:43:36.400959 <14>[ 19.093922] [IGT] core_auth: executing
11007 04:43:36.410706 kms_addfb_basic kms_atomic kms_flip_event_leak <14>[ 19.110428] [IGT] core_auth: starting subtest basic-auth
11008 04:43:36.417423 kms_prop_blob km<14>[ 19.110522] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11009 04:43:36.421000 <14>[ 19.110559] [IGT] core_auth: exiting, ret=0
11010 04:43:36.427161 <8>[ 19.114594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11011 04:43:36.427451 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11013 04:43:36.433671 <14>[ 19.128041] [IGT] core_auth: executing
11014 04:43:36.440707 s_setmode kms_vb<14>[ 19.143414] [IGT] core_auth: starting subtest many-magics
11015 04:43:36.440820 lank
11016 04:43:36.450268 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Li<14>[ 19.152647] [IGT] core_auth: finished subtest many-magics, SUCCESS
11017 04:43:36.454140 <14>[ 19.152701] [IGT] core_auth: exiting, ret=0
11018 04:43:36.460510 <8>[ 19.157585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11019 04:43:36.460809 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11021 04:43:36.467120 <8>[ 19.160719] <LAVA_SIGNAL_TESTSET STOP>
11022 04:43:36.467232 nux: 6.1.75-cip14-rt8 aarch64)
11023 04:43:36.467504 Received signal: <TESTSET> STOP
11024 04:43:36.467608 Closing test_set core_auth
11025 04:43:36.470411 Starting subtest: getclient-simple
11026 04:43:36.473804 Opened device: /dev/dri/card0
11027 04:43:36.480146 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11028 04:43:36.486920 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11029 04:43:36.493231 Starting subtest: getclient-mas<14>[ 19.196731] [IGT] core_getclient: executing
11030 04:43:36.496656 <14>[ 19.197007] [IGT] core_getclient: exiting, ret=0
11031 04:43:36.503415 <8>[ 19.205018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11032 04:43:36.503707 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11034 04:43:36.506401 ter-drop
11035 04:43:36.509831 Opened device: /dev/dri/card0
11036 04:43:36.512929 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11037 04:43:36.519784 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11038 04:43:36.523171 Opened device: /dev/dri/card0
11039 04:43:36.529641 Starting subtest: bas<14>[ 19.230027] [IGT] core_getstats: executing
11040 04:43:36.532942 <14>[ 19.230374] [IGT] core_getstats: exiting, ret=0
11041 04:43:36.539801 <8>[ 19.235363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11042 04:43:36.539913 ic-auth
11043 04:43:36.540188 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11045 04:43:36.546272 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11046 04:43:36.552984 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11047 04:43:36.553098 Opened device: /dev/dri/card0
11048 04:43:36.556108 Starting subtest: many-magics
11049 04:43:36.559498 Reopening device failed after 1020 opens
11050 04:43:36.565926 [1mSubtest many-magics<14>[ 19.272042] [IGT] core_getversion: executing
11051 04:43:36.572518 <14>[ 19.272339] [IGT] core_getversion: exiting, ret=0
11052 04:43:36.579241 <8>[ 19.276857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11053 04:43:36.579537 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11055 04:43:36.582680 : SUCCESS (0.009s)[0m
11056 04:43:36.589119 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11057 04:43:36.589230 Opened device: /dev/dri/card0
11058 04:43:36.592480 SUCCESS (0.000s)
11059 04:43:36.599065 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11060 04:43:36.602586 Opened device: /dev/dri/card0
11061 04:43:36.602696 SUCCESS (0.000s)
11062 04:43:36.609018 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11063 04:43:36.615472 Opened device: /dev/dri/<14>[ 19.318817] [IGT] core_setmaster_vs_auth: executing
11064 04:43:36.622257 <14>[ 19.319150] [IGT] core_setmaster_vs_auth: exiting, ret=0
11065 04:43:36.628964 <8>[ 19.323881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11066 04:43:36.629258 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11068 04:43:36.635365 <8>[ 19.338830] <LAVA_SIGNAL_TESTSET START drm_read>
11069 04:43:36.635474 card0
11070 04:43:36.635743 Received signal: <TESTSET> START drm_read
11071 04:43:36.635843 Starting test_set drm_read
11072 04:43:36.638891 SUCCESS (0.000s)
11073 04:43:36.648616 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64<14>[ 19.350747] [IGT] drm_read: executing
11074 04:43:36.652254 <14>[ 19.351178] [IGT] drm_read: exiting, ret=77
11075 04:43:36.658480 <8>[ 19.356281] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11076 04:43:36.658606 )
11077 04:43:36.658920 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11079 04:43:36.661840 Opened device: /dev/dri/card0
11080 04:43:36.668651 SUCCESS (0.000<14>[ 19.370271] [IGT] drm_read: executing
11081 04:43:36.671919 <14>[ 19.370698] [IGT] drm_read: exiting, ret=77
11082 04:43:36.678227 <8>[ 19.376489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11083 04:43:36.678337 s)
11084 04:43:36.678609 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11086 04:43:36.688393 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linu<14>[ 19.390007] [IGT] drm_read: executing
11087 04:43:36.691397 <14>[ 19.390428] [IGT] drm_read: exiting, ret=77
11088 04:43:36.697931 <8>[ 19.394785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11089 04:43:36.698254 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11091 04:43:36.701255 x: 6.1.75-cip14-rt8 aarch64)
11092 04:43:36.704694 Opened device: /dev/dri/card0
11093 04:43:36.708115 No KMS driver or no outputs, pipes: 8, outputs: 0
11094 04:43:36.714448 [1mSubtest invalid-buffer: SKIP<14>[ 19.418763] [IGT] drm_read: executing
11095 04:43:36.717956 <14>[ 19.419338] [IGT] drm_read: exiting, ret=77
11096 04:43:36.727789 <8>[ 19.424964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11097 04:43:36.727899 (0.000s)[0m
11098 04:43:36.728172 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11100 04:43:36.734627 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11101 04:43:36.737982 Opened <14>[ 19.443987] [IGT] drm_read: executing
11102 04:43:36.744425 <14>[ 19.444549] [IGT] drm_read: exiting, ret=77
11103 04:43:36.751084 <8>[ 19.449955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11104 04:43:36.751371 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11106 04:43:36.754550 device: /dev/dri/card0
11107 04:43:36.757783 No KMS driver or no outputs, pipes: 8, outputs: 0
11108 04:43:36.760835 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11109 04:43:36.767649 IGT-Version: 1.27.1-g621<14>[ 19.470231] [IGT] drm_read: executing
11110 04:43:36.771174 <14>[ 19.470784] [IGT] drm_read: exiting, ret=77
11111 04:43:36.780948 <8>[ 19.475894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11112 04:43:36.781242 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11114 04:43:36.784096 c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11115 04:43:36.787477 Opened device: /dev/dri/card0
11116 04:43:36.790669 <14>[ 19.496216] [IGT] drm_read: executing
11117 04:43:36.794107 <14>[ 19.496815] [IGT] drm_read: exiting, ret=77
11118 04:43:36.804060 <8>[ 19.502173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11119 04:43:36.804349 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11121 04:43:36.807326 <8>[ 19.503522] <LAVA_SIGNAL_TESTSET STOP>
11122 04:43:36.807432
11123 04:43:36.807697 Received signal: <TESTSET> STOP
11124 04:43:36.807792 Closing test_set drm_read
11125 04:43:36.810619 No KMS driver or no outputs, pipes: 8, outputs: 0
11126 04:43:36.813956 [1mSubtest empty-block: SKIP (0.000s)[0m
11127 04:43:36.820936 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11128 04:43:36.830784 Opened device: /dev/dr<8>[ 19.529517] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11129 04:43:36.830893 i/card0
11130 04:43:36.831161 Received signal: <TESTSET> START kms_addfb_basic
11131 04:43:36.831261 Starting test_set kms_addfb_basic
11132 04:43:36.837426 No KMS driver or no out<14>[ 19.541525] [IGT] kms_addfb_basic: executing
11133 04:43:36.840415 puts, pipes: 8, outputs: 0
11134 04:43:36.843983 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11135 04:43:36.850737 IGT-V<14>[ 19.551846] [IGT] kms_addfb_basic: starting subtest unused-handle
11136 04:43:36.857173 <14>[ 19.551929] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11137 04:43:36.863965 ersion: 1.27.1-g<14>[ 19.568573] [IGT] kms_addfb_basic: exiting, ret=0
11138 04:43:36.870422 <8>[ 19.573100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11139 04:43:36.870731 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11141 04:43:36.877116 621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11142 04:43:36.877231 Opened device: /dev/dri/card0
11143 04:43:36.883654 No KMS driver or no outputs, pipes: 8, outputs: 0
11144 04:43:36.886662 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11145 04:43:36.893293 IGT-Ve<14>[ 19.595453] [IGT] kms_addfb_basic: executing
11146 04:43:36.900074 <14>[ 19.599972] [IGT] kms_addfb_basic: starting subtest unused-pitches
11147 04:43:36.910156 rsion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-<14>[ 19.609967] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11148 04:43:36.913460 cip14-rt8 aarch64)
11149 04:43:36.913574 Opened device: /dev/dri/card0
11150 04:43:36.919895 No KMS driver<14>[ 19.621489] [IGT] kms_addfb_basic: exiting, ret=0
11151 04:43:36.926727 <8>[ 19.626634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11152 04:43:36.927021 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11154 04:43:36.936477 or no outputs, pipes: 8, output<14>[ 19.639107] [IGT] kms_addfb_basic: executing
11155 04:43:36.943154 <14>[ 19.643541] [IGT] kms_addfb_basic: starting subtest unused-offsets
11156 04:43:36.943265 s: 0
11157 04:43:36.949496 [1mSubtes<14>[ 19.653206] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11158 04:43:36.952913 t short-buffer-nonblock: SKIP (0.000s)[0m
11159 04:43:36.959956 IGT-<14>[ 19.662025] [IGT] kms_addfb_basic: exiting, ret=0
11160 04:43:36.966195 <8>[ 19.666743] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11161 04:43:36.966495 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11163 04:43:36.976445 Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.7<14>[ 19.678269] [IGT] kms_addfb_basic: executing
11164 04:43:36.982740 <14>[ 19.682638] [IGT] kms_addfb_basic: starting subtest unused-modifier
11165 04:43:36.986180 5-cip14-rt8 aarch64)
11166 04:43:36.992737 Opened device: /dev/dri/ca<14>[ 19.693729] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11167 04:43:36.996126 rd0
11168 04:43:36.999644 No KMS driver or no outputs, pipes: 8, outputs: 0
11169 04:43:37.006042 [1mSubt<14>[ 19.705616] [IGT] kms_addfb_basic: exiting, ret=0
11170 04:43:37.012485 <8>[ 19.710395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11171 04:43:37.012780 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11173 04:43:37.019356 est short-buffer-wakeup: SKIP (0<14>[ 19.723264] [IGT] kms_addfb_basic: executing
11174 04:43:37.026148 <14>[ 19.727621] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11175 04:43:37.029007 .000s)[0m
11176 04:43:37.038988 IGT-Version: 1.27.1-g621c2d3 (aarch6<14>[ 19.737676] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11177 04:43:37.042560 4) (Linux: 6.1.75-cip14-rt8 aarch64)
11178 04:43:37.049280 Opened device: /dev/dri/ca<14>[ 19.749720] [IGT] kms_addfb_basic: exiting, ret=77
11179 04:43:37.055771 <8>[ 19.754470] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11180 04:43:37.055883 rd0
11181 04:43:37.056157 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11183 04:43:37.065455 Starting subtest: unused-ha<14>[ 19.767748] [IGT] kms_addfb_basic: executing
11184 04:43:37.072204 <14>[ 19.772008] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11185 04:43:37.072315 ndle
11186 04:43:37.085336 [1mSubtest unused-handle: SUCCESS (0.000s<14>[ 19.782860] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11187 04:43:37.085444 )[0m
11188 04:43:37.091977 Test requirement not met <14>[ 19.795560] [IGT] kms_addfb_basic: exiting, ret=77
11189 04:43:37.098996 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11191 04:43:37.101842 <8>[ 19.800112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11192 04:43:37.105030 in function igt_require_i915, file ../lib/drmtest.c:720:
11193 04:43:37.108593 Test requirement: is_i915_device(fd)
11194 04:43:37.121723 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720<14>[ 19.822456] [IGT] kms_addfb_basic: executing
11195 04:43:37.128530 <14>[ 19.827043] [IGT] kms_addfb_basic: starting subtest legacy-format
11196 04:43:37.128637 :
11197 04:43:37.131877 Test requirement: is_i915_device(fd)
11198 04:43:37.135318 No KMS driver or no outputs, pipes: 8, outputs: 0
11199 04:43:37.141606 IGT-<14>[ 19.844093] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11200 04:43:37.151877 Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarc<14>[ 19.853630] [IGT] kms_addfb_basic: exiting, ret=0
11201 04:43:37.158424 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11203 04:43:37.161627 <8>[ 19.858299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11204 04:43:37.161730 h64)
11205 04:43:37.161820 Opened device: /dev/dri/card0
11206 04:43:37.164899 Starting subtest: unused-pitches
11207 04:43:37.171582 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11208 04:43:37.181421 Test requirement not met in function igt_require_i915, <14>[ 19.884078] [IGT] kms_addfb_basic: executing
11209 04:43:37.181530 file ../lib/drmtest.c:720:
11210 04:43:37.188224 Test<14>[ 19.891337] [IGT] kms_addfb_basic: starting subtest no-handle
11211 04:43:37.194638 <14>[ 19.891416] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11212 04:43:37.197966 requirement: is_i915_device(fd)
11213 04:43:37.204840 Test requireme<14>[ 19.907009] [IGT] kms_addfb_basic: exiting, ret=0
11214 04:43:37.211057 <8>[ 19.911899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11215 04:43:37.211338 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11217 04:43:37.221157 nt not met in function igt_require_i915, file ..<14>[ 19.922832] [IGT] kms_addfb_basic: executing
11218 04:43:37.227867 <14>[ 19.929274] [IGT] kms_addfb_basic: starting subtest basic
11219 04:43:37.227973 /lib/drmtest.c:720:
11220 04:43:37.230893 Test requirement: is_i915_device(fd)
11221 04:43:37.237890 No KM<14>[ 19.937532] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11222 04:43:37.240982 S driver or no outputs, pipes: 8, outputs: 0
11223 04:43:37.247647 IGT-Version: 1.27.<14>[ 19.949739] [IGT] kms_addfb_basic: exiting, ret=0
11224 04:43:37.254488 <8>[ 19.954342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11225 04:43:37.254771 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11227 04:43:37.264323 1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aa<14>[ 19.966668] [IGT] kms_addfb_basic: executing
11228 04:43:37.270905 <14>[ 19.973153] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11229 04:43:37.271013 rch64)
11230 04:43:37.273857 Opened device: /dev/dri/card0
11231 04:43:37.280724 Starting <14>[ 19.981799] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11232 04:43:37.287507 subtest: unused-<14>[ 19.993360] [IGT] kms_addfb_basic: exiting, ret=0
11233 04:43:37.293908 <8>[ 19.998093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11234 04:43:37.294236 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11236 04:43:37.297203 offsets
11237 04:43:37.304086 [1mSubtest unused-offsets: SUCCESS (0.<14>[ 20.009088] [IGT] kms_addfb_basic: executing
11238 04:43:37.304190 000s)[0m
11239 04:43:37.313696 Test requirement not <14>[ 20.015417] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11240 04:43:37.317255 met in function igt_require_i915, file ../lib/drmtest.c:720:
11241 04:43:37.320494 Test requirement: is_i915_device(fd)
11242 04:43:37.330586 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11243 04:43:37.333591 Test requirement: is_i915_device(fd)
11244 04:43:37.337061 No KMS driver or no outputs, pipes: 8, outputs: 0
11245 04:43:37.343553 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11246 04:43:37.347288 Opened device: /dev/dri/card0
11247 04:43:37.350202 Starting subtest: unused-modifier
11248 04:43:37.353538 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11249 04:43:37.360444 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11250 04:43:37.363834 Test requirement: is_i915_device(fd)
11251 04:43:37.370180 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11252 04:43:37.373397 Test requirement: is_i915_device(fd)
11253 04:43:37.380275 No KMS driver or no outputs, pipes: 8, outputs: 0
11254 04:43:37.387137 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11255 04:43:37.387245 Opened device: /dev/dri/card0
11256 04:43:37.390071 Starting subtest: clobberred-modifier
11257 04:43:37.400013 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11258 04:43:37.403496 Test requirement: is_i915_device(fd)
11259 04:43:37.406788 [1mSubtest clobberred-modifier: SKIP (0.000s)[0m
11260 04:43:37.413121 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11261 04:43:37.416451 Test requirement: is_i915_device(fd)
11262 04:43:37.423148 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11263 04:43:37.426191 Test requirement: is_i915_device(fd)
11264 04:43:37.433222 No KMS driver or no outputs, pipes: 8, outputs: 0
11265 04:43:37.439544 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11266 04:43:37.439646 Opened device: /dev/dri/card0
11267 04:43:37.446533 Starting subtest: invalid-smem-bo-on-discrete
11268 04:43:37.452948 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:715:
11269 04:43:37.456453 Test requirement: is_intel_device(fd)
11270 04:43:37.462929 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11271 04:43:37.469330 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11272 04:43:37.472872 Test requirement: is_i915_device(fd)
11273 04:43:37.479358 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11274 04:43:37.482756 Test requirement: is_i915_device(fd)
11275 04:43:37.486201 No KMS driver or no outputs, pipes: 8, outputs: 0
11276 04:43:37.492569 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11277 04:43:37.496069 Opened device: /dev/dri/card0
11278 04:43:37.499807 Starting subtest: legacy-format
11279 04:43:37.503295 Successfully fuzzed 10000 {bpp, depth} variations
11280 04:43:37.506605 [1mSubtest legacy-format: SUCCESS (0.006s)[0m
11281 04:43:37.516518 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11282 04:43:37.516681 Test requirement: is_i915_device(fd)
11283 04:43:37.526445 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11284 04:43:37.529457 Test requirement: is_i915_device(fd)
11285 04:43:37.532851 No KMS driver or no outputs, pipes: 8, outputs: 0
11286 04:43:37.539675 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11287 04:43:37.543134 Opened device: /dev/dri/card0
11288 04:43:37.546300 Starting subtest: no-handle
11289 04:43:37.549531 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11290 04:43:37.556277 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11291 04:43:37.559529 Test requirement: is_i915_device(fd)
11292 04:43:37.566557 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11293 04:43:37.570065 Test requirement: is_i915_device(fd)
11294 04:43:37.572801 No KMS driver or no outputs, pipes: 8, outputs: 0
11295 04:43:37.579905 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11296 04:43:37.583022 Opened device: /dev/dri/card0
11297 04:43:37.586347 Starting subtest: basic
11298 04:43:37.589681 [1mSubtest basic: SUCCESS (0.000s)[0m
11299 04:43:37.596112 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11300 04:43:37.599477 Test requirement: is_i915_device(fd)
11301 04:43:37.606244 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11302 04:43:37.609114 Test requirement: is_i915_device(fd)
11303 04:43:37.612351 No KMS driver or no outputs, pipes: 8, outputs: 0
11304 04:43:37.619167 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11305 04:43:37.622138 Opened device: /dev/dri/card0
11306 04:43:37.625378 Starting subtest: bad-pitch-0
11307 04:43:37.628862 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11308 04:43:37.638811 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11309 04:43:37.642116 Test requirement: is_i915_device(fd)
11310 04:43:37.655457 Test requirement not met in function igt_require_i915, file ../lib/drmtest.<14>[ 20.355363] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11311 04:43:37.655601 c:720:
11312 04:43:37.661987 Test req<14>[ 20.365341] [IGT] kms_addfb_basic: exiting, ret=0
11313 04:43:37.668938 uirement: is_i91<8>[ 20.370094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11314 04:43:37.669176 5_device(fd)
11315 04:43:37.669595 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11317 04:43:37.675197 No KMS driver or no outputs, pipes: 8, outputs: 0
11318 04:43:37.681699 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11319 04:43:37.688347 Opened device: /dev/d<14>[ 20.393135] [IGT] kms_addfb_basic: executing
11320 04:43:37.688592 ri/card0
11321 04:43:37.691838 Starting subtest: bad-pitch-32
11322 04:43:37.695002 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11323 04:43:37.701476 Test r<14>[ 20.405017] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11324 04:43:37.708349 <14>[ 20.405152] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11325 04:43:37.714594 equirement not m<14>[ 20.420345] [IGT] kms_addfb_basic: exiting, ret=0
11326 04:43:37.721042 <8>[ 20.425590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11327 04:43:37.721315 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11329 04:43:37.727830 et in function igt_require_i915, file ../lib/drmtest.c:720:
11330 04:43:37.734620 Test requirement: is_i915_device(fd<14>[ 20.438179] [IGT] kms_addfb_basic: executing
11331 04:43:37.741419 <14>[ 20.444730] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11332 04:43:37.741504 )
11333 04:43:37.751071 Test requirem<14>[ 20.453236] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11334 04:43:37.761007 ent not met in function igt_require_i915, file .<14>[ 20.462105] [IGT] kms_addfb_basic: exiting, ret=0
11335 04:43:37.767487 <8>[ 20.466550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11336 04:43:37.767579 ./lib/drmtest.c:720:
11337 04:43:37.767820 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11339 04:43:37.777720 Test requirement: is_i915_<14>[ 20.478240] [IGT] kms_addfb_basic: executing
11340 04:43:37.780758 <14>[ 20.484955] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11341 04:43:37.784128 device(fd)
11342 04:43:37.794218 No KMS driver or no outputs, pipes: <14>[ 20.493516] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11343 04:43:37.794305 8, outputs: 0
11344 04:43:37.801001 I<14>[ 20.505140] [IGT] kms_addfb_basic: exiting, ret=0
11345 04:43:37.807483 <8>[ 20.509662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11346 04:43:37.807741 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11348 04:43:37.816936 GT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.<14>[ 20.521298] [IGT] kms_addfb_basic: executing
11349 04:43:37.817022 1.75-cip14-rt8 aarch64)
11350 04:43:37.820216 Opened device: /dev/dri/card0
11351 04:43:37.824017 Starting subtest: bad-pitch-63
11352 04:43:37.833483 [1mSubtest bad-pitch-63: SUCCESS (0.000<14>[ 20.533736] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11353 04:43:37.840245 <14>[ 20.533841] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11354 04:43:37.843520 s)[0m
11355 04:43:37.846847 Test req<14>[ 20.552460] [IGT] kms_addfb_basic: exiting, ret=0
11356 04:43:37.853425 <8>[ 20.556791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11357 04:43:37.853681 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11359 04:43:37.860112 uirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11360 04:43:37.863323 Test requirement: is_i915_device(fd)
11361 04:43:37.876398 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:72<14>[ 20.579144] [IGT] kms_addfb_basic: executing
11362 04:43:37.883002 <14>[ 20.586395] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11363 04:43:37.889928 <14>[ 20.593794] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11364 04:43:37.890049 0:
11365 04:43:37.896546 Test require<14>[ 20.601277] [IGT] kms_addfb_basic: exiting, ret=0
11366 04:43:37.902997 <8>[ 20.606210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11367 04:43:37.903252 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11369 04:43:37.906463 ment: is_i915_device(fd)
11370 04:43:37.912918 No KMS driver or no ou<14>[ 20.617237] [IGT] kms_addfb_basic: executing
11371 04:43:37.916342 tputs, pipes: 8, outputs: 0
11372 04:43:37.922667 IGT<14>[ 20.623839] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11373 04:43:37.929633 <14>[ 20.623932] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11374 04:43:37.935862 -Version: 1.27.1<14>[ 20.640462] [IGT] kms_addfb_basic: exiting, ret=0
11375 04:43:37.942608 <8>[ 20.644804] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11376 04:43:37.942862 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11378 04:43:37.946059 -g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11379 04:43:37.949394 Opened device: /dev/dri/card0
11380 04:43:37.952496 Starting subtest: bad-pitch-128
11381 04:43:37.955746 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11382 04:43:37.962707 Test requirement not met<14>[ 20.666917] [IGT] kms_addfb_basic: executing
11383 04:43:37.972684 in function igt_require_i915, f<14>[ 20.676028] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11384 04:43:37.982617 <14>[ 20.676098] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11385 04:43:37.989102 ile ../lib/drmte<14>[ 20.693280] [IGT] kms_addfb_basic: exiting, ret=0
11386 04:43:37.995982 <8>[ 20.697999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11387 04:43:37.996128 st.c:720:
11388 04:43:37.996401 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11390 04:43:38.002568 Test requirement: is_<14>[ 20.709036] [IGT] kms_addfb_basic: executing
11391 04:43:38.005499 i915_device(fd)
11392 04:43:38.015527 Test requirement not met in fun<14>[ 20.717388] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11393 04:43:38.022725 <14>[ 20.717596] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11394 04:43:38.029152 ction igt_requir<14>[ 20.733304] [IGT] kms_addfb_basic: exiting, ret=0
11395 04:43:38.036069 <8>[ 20.737744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11396 04:43:38.036432 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11398 04:43:38.042427 e_i915, file ../lib/drmtest.c:72<14>[ 20.748147] [IGT] kms_addfb_basic: executing
11399 04:43:38.042619 0:
11400 04:43:38.048626 Test requirement: is_i915_device(fd)
11401 04:43:38.055582 No KMS<14>[ 20.756367] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11402 04:43:38.062144 <14>[ 20.756478] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11403 04:43:38.065534 driver or no outputs, pipes: 8, outputs: 0
11404 04:43:38.072094 IGT-Version: 1.27.1<14>[ 20.773792] [IGT] kms_addfb_basic: exiting, ret=0
11405 04:43:38.081846 <8>[ 20.778170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11406 04:43:38.082597 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11408 04:43:38.085574 -g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11409 04:43:38.088777 Opened device: /dev/dri/card0
11410 04:43:38.091836 Starting subtest: bad-pitch-256
11411 04:43:38.095491 [1mSubte<14>[ 20.800237] [IGT] kms_addfb_basic: executing
11412 04:43:38.105424 st bad-pitch-256: SUCCESS (0.000<14>[ 20.809325] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11413 04:43:38.115605 <14>[ 20.809402] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11414 04:43:38.116160 s)[0m
11415 04:43:38.122170 Test req<14>[ 20.824762] [IGT] kms_addfb_basic: exiting, ret=0
11416 04:43:38.132027 uirement not met in function igt<8>[ 20.831558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11417 04:43:38.132852 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11419 04:43:38.134978 _require_i915, file ../lib/drmtest.c:720:
11420 04:43:38.142079 Test requirement: is_<14>[ 20.841959] [IGT] kms_addfb_basic: executing
11421 04:43:38.142630 i915_device(fd)
11422 04:43:38.148606 Test requiremen<14>[ 20.852017] [IGT] kms_addfb_basic: starting subtest master-rmfb
11423 04:43:38.158798 <14>[ 20.852126] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11424 04:43:38.165647 t not met in function igt_requir<14>[ 20.867886] [IGT] kms_addfb_basic: exiting, ret=0
11425 04:43:38.172143 <8>[ 20.874990] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11426 04:43:38.173008 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11428 04:43:38.175344 e_i915, file ../lib/drmtest.c:720:
11429 04:43:38.178443 Test requirement: is_i915_device(fd)
11430 04:43:38.181659 No KMS driver or no outputs, pipes: 8, outputs: 0
11431 04:43:38.191392 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.<14>[ 20.896814] [IGT] kms_addfb_basic: executing
11432 04:43:38.194946 75-cip14-rt8 aarch64)
11433 04:43:38.195491 Opened device: /dev/dri/card0
11434 04:43:38.198296 Starting subtest: bad-pitch-1024
11435 04:43:38.208318 [1mSubt<14>[ 20.909408] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11436 04:43:38.215006 <14>[ 20.909629] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11437 04:43:38.218255 est bad-pitch-1024: SUCCESS (0.000s)[0m
11438 04:43:38.228591 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11439 04:43:38.231249 Test requirement: is_i915_device(fd)
11440 04:43:38.238086 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11441 04:43:38.241520 Test requirement: is_i915_device(fd)
11442 04:43:38.244947 No KMS driver or no outputs, pipes: 8, outputs: 0
11443 04:43:38.251376 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11444 04:43:38.254480 Opened device: /dev/dri/card0
11445 04:43:38.258055 Starting subtest: bad-pitch-999
11446 04:43:38.261476 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11447 04:43:38.267776 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11448 04:43:38.271036 Test requirement: is_i915_device(fd)
11449 04:43:38.277997 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11450 04:43:38.281380 Test requirement: is_i915_device(fd)
11451 04:43:38.287753 No KMS driver or no outputs, pipes: 8, outputs: 0
11452 04:43:38.294533 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11453 04:43:38.295086 Opened device: /dev/dri/card0
11454 04:43:38.297548 Starting subtest: bad-pitch-65536
11455 04:43:38.304352 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11456 04:43:38.311309 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11457 04:43:38.314282 Test requirement: is_i915_device(fd)
11458 04:43:38.321190 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11459 04:43:38.324239 Test requirement: is_i915_device(fd)
11460 04:43:38.327616 No KMS driver or no outputs, pipes: 8, outputs: 0
11461 04:43:38.334447 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11462 04:43:38.337515 Opened device: /dev/dri/card0
11463 04:43:38.340894 Starting subtest: invalid-get-prop-any
11464 04:43:38.347363 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11465 04:43:38.354355 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11466 04:43:38.357501 Test requirement: is_i915_device(fd)
11467 04:43:38.363642 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11468 04:43:38.367131 Test requirement: is_i915_device(fd)
11469 04:43:38.370739 No KMS driver or no outputs, pipes: 8, outputs: 0
11470 04:43:38.377173 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11471 04:43:38.380374 Opened device: /dev/dri/card0
11472 04:43:38.383957 Starting subtest: invalid-get-prop
11473 04:43:38.387205 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11474 04:43:38.393415 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11475 04:43:38.397315 Test requirement: is_i915_device(fd)
11476 04:43:38.406959 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11477 04:43:38.409859 Test requirement: is_i915_device(fd)
11478 04:43:38.413665 No KMS driver or no outputs, pipes: 8, outputs: 0
11479 04:43:38.419895 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11480 04:43:38.423498 Opened device: /dev/dri/card0
11481 04:43:38.426727 Starting subtest: invalid-set-prop-any
11482 04:43:38.430664 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11483 04:43:38.436658 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11484 04:43:38.440169 Test requirement: is_i915_device(fd)
11485 04:43:38.449676 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11486 04:43:38.453119 Test requirement: is_i915_device(fd)
11487 04:43:38.456613 No KMS driver or no outputs, pipes: 8, outputs: 0
11488 04:43:38.463400 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11489 04:43:38.466116 Opened device: /dev/dri/card0
11490 04:43:38.469890 Starting subtest: invalid-set-prop
11491 04:43:38.473332 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11492 04:43:38.479746 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11493 04:43:38.482903 Test requirement: is_i915_device(fd)
11494 04:43:38.489439 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11495 04:43:38.493061 Test requirement: is_i915_device(fd)
11496 04:43:38.499526 No KMS driver or no outputs, pipes: 8, outputs: 0
11497 04:43:38.506174 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11498 04:43:38.506710 Opened device: /dev/dri/card0
11499 04:43:38.509366 Starting subtest: master-rmfb
11500 04:43:38.516029 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11501 04:43:38.522589 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11502 04:43:38.526395 Test requirement: is_i915_device(fd)
11503 04:43:38.532544 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11504 04:43:38.536022 Test requirement: is_i915_device(fd)
11505 04:43:38.539318 No KMS driver or no outputs, pipes: 8, outputs: 0
11506 04:43:38.545838 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11507 04:43:38.549039 Opened device: /dev/dri/card0
11508 04:43:38.555557 Starting subtest: addfb25-modifi<14>[ 21.258759] [IGT] kms_addfb_basic: exiting, ret=0
11509 04:43:38.565335 <8>[ 21.263913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11510 04:43:38.566071 er-no-flag
11511 04:43:38.566718 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11513 04:43:38.572460 [1mSubtest addfb25-<14>[ 21.275925] [IGT] kms_addfb_basic: executing
11514 04:43:38.575531 modifier-no-flag: SUCCESS (0.000s)[0m
11515 04:43:38.585362 Test requirement not met in function igt<14>[ 21.288025] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11516 04:43:38.588903 _require_i915, file ../lib/drmtest.c:720:
11517 04:43:38.598498 Test requirement: is_<14>[ 21.299512] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11518 04:43:38.605226 <14>[ 21.299770] [IGT] kms_addfb_basic: exiting, ret=98
11519 04:43:38.612272 <8>[ 21.307083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11520 04:43:38.613082 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11522 04:43:38.615354 i915_device(fd)
11523 04:43:38.621846 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11524 04:43:38.628645 Test requirement: is_i915_de<14>[ 21.330015] [IGT] kms_addfb_basic: executing
11525 04:43:38.629177 vice(fd)
11526 04:43:38.635448 No KMS driver or no outputs, pipes: 8, outputs: 0
11527 04:43:38.641638 IGT-Version: 1.27.1<14>[ 21.343759] [IGT] kms_addfb_basic: exiting, ret=77
11528 04:43:38.648403 <8>[ 21.349357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11529 04:43:38.649199 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11531 04:43:38.655275 -g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11532 04:43:38.661633 Opened device: /dev/dri/c<14>[ 21.362769] [IGT] kms_addfb_basic: executing
11533 04:43:38.662195 ard0
11534 04:43:38.664969 Starting subtest: addfb25-bad-modifier
11535 04:43:38.671632 (kms_addfb_basic:442) CRITICAL: Te<14>[ 21.375462] [IGT] kms_addfb_basic: exiting, ret=77
11536 04:43:38.681743 <8>[ 21.380259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11537 04:43:38.682586 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11539 04:43:38.688245 st assertion failure function ad<14>[ 21.391398] [IGT] kms_addfb_basic: executing
11540 04:43:38.691601 dfb25_tests, file ../tests/kms_addfb_basic.c:662:
11541 04:43:38.701654 (kms_addfb_basic:442) CRITICA<14>[ 21.404173] [IGT] kms_addfb_basic: exiting, ret=77
11542 04:43:38.708231 <8>[ 21.408750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11543 04:43:38.709112 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11545 04:43:38.724730 L: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11546 04:43:38.728114 <14>[ 21.431696] [IGT] kms_addfb_basic: executing
11547 04:43:38.728649
11548 04:43:38.734648 (kms_addfb_basic:442) CRITICAL: error: 0 != -1
11549 04:43:38.735177 Stack trace:
11550 04:43:38.740983 #0 ../lib/igt_c<14>[ 21.445405] [IGT] kms_addfb_basic: exiting, ret=77
11551 04:43:38.744406 ore.c:1971 __igt_fail_assert()
11552 04:43:38.747850 #1 [<unknown>+0xe17947e0]
11553 04:43:38.754654 #2 [<unknown>+0xe<8>[ 21.457161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11554 04:43:38.755451 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11556 04:43:38.758025 1796278]
11557 04:43:38.758463 #3 [<unknown>+0xe179167c]
11558 04:43:38.761446 #4 [__libc_start_main+0xe8]
11559 04:43:38.767740 #5 [<unknown>+0xe17916b4<14>[ 21.470235] [IGT] kms_addfb_basic: executing
11560 04:43:38.768224 ]
11561 04:43:38.771385 #6 [<unknown>+0xe17916b4]
11562 04:43:38.774262 Subtest addfb25-bad-modifier failed.
11563 04:43:38.781208 **** DEBUG<14>[ 21.482977] [IGT] kms_addfb_basic: exiting, ret=77
11564 04:43:38.787405 <8>[ 21.487680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11565 04:43:38.788209 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11567 04:43:38.790782 ****
11568 04:43:38.797611 (kms_addfb_basic:442) ioc<14>[ 21.500017] [IGT] kms_addfb_basic: executing
11569 04:43:38.804531 tl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11570 04:43:38.807418 (kms_addfb<14>[ 21.512886] [IGT] kms_addfb_basic: exiting, ret=77
11571 04:43:38.817128 <8>[ 21.517571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11572 04:43:38.817894 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11574 04:43:38.823991 _basic:442) CRITICAL: Test asser<14>[ 21.528751] [IGT] kms_addfb_basic: executing
11575 04:43:38.830505 tion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11576 04:43:38.847277 (kms_addfb_basic:442) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11577 04:43:38.853643 (kms_addfb_basic:442) CRITICAL: error: 0 != -1
11578 04:43:38.857127 (kms_addfb_basic:442) igt_core-INFO: Stack trace:
11579 04:43:38.864063 (kms_addfb_basic:442) igt_core-INFO: #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11580 04:43:38.870216 (kms_addfb_basic:442) igt_core-INFO: #1 [<unknown>+0xe17947e0]
11581 04:43:38.876865 (kms_addfb_basic:442) igt_core-INFO: #2 [<unknown>+0xe1796278]
11582 04:43:38.880364 (kms_addfb_basic:442) igt_core-INFO: #3 [<unknown>+0xe179167c]
11583 04:43:38.886851 (kms_addfb_basic:442) igt_core-INFO: #4 [__libc_start_main+0xe8]
11584 04:43:38.893682 (kms_addfb_basic:442) igt_core-INFO: #5 [<unknown>+0xe17916b4]
11585 04:43:38.900060 (kms_addfb_basic:442) igt_core-INFO: #6 [<unknown>+0xe17916b4]
11586 04:43:38.900589 **** END ****
11587 04:43:38.903770 [1mSubtest addfb25-bad-modifier: FAIL (0.011s)[0m
11588 04:43:38.913683 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11589 04:43:38.916956 Test requirement: is_i915_device(fd)
11590 04:43:38.923655 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11591 04:43:38.927037 Test requirement: is_i915_device(fd)
11592 04:43:38.930321 No KMS driver or no outputs, pipes: 8, outputs: 0
11593 04:43:38.936696 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11594 04:43:38.940055 Opened device: /dev/dri/card0
11595 04:43:38.946487 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11596 04:43:38.949657 Test requirement: is_i915_device(fd)
11597 04:43:38.956386 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11598 04:43:38.963052 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11599 04:43:38.966483 Test requirement: is_i915_device(fd)
11600 04:43:38.970092 No KMS driver or no outputs, pipes: 8, outputs: 0
11601 04:43:38.976789 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11602 04:43:38.979715 Opened device: /dev/dri/card0
11603 04:43:38.986399 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11604 04:43:38.989612 Test requirement: is_i915_device(fd)
11605 04:43:38.996166 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11606 04:43:39.003165 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11607 04:43:39.006833 Test requirement: is_i915_device(fd)
11608 04:43:39.009677 No KMS driver or no outputs, pipes: 8, outputs: 0
11609 04:43:39.016156 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11610 04:43:39.019732 Opened device: /dev/dri/card0
11611 04:43:39.026446 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11612 04:43:39.029808 Test requirement: is_i915_device(fd)
11613 04:43:39.036023 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11614 04:43:39.042819 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11615 04:43:39.045773 Test requirement: is_i915_device(fd)
11616 04:43:39.049180 No KMS driver or no outputs, pipes: 8, outputs: 0
11617 04:43:39.055623 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11618 04:43:39.058926 Opened device: /dev/dri/card0
11619 04:43:39.065592 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11620 04:43:39.068651 Test requirement: is_i915_device(fd)
11621 04:43:39.075594 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11622 04:43:39.079164 Test requirement: is_i915_device(fd)
11623 04:43:39.085531 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11624 04:43:39.088996 No KMS driver or no outputs, pipes: 8, outputs: 0
11625 04:43:39.095099 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11626 04:43:39.098596 Opened device: /dev/dri/card0
11627 04:43:39.105517 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11628 04:43:39.108853 Test requirement: is_i915_device(fd)
11629 04:43:39.115716 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11630 04:43:39.118603 Test requirement: is_i915_device(fd)
11631 04:43:39.125253 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11632 04:43:39.128242 No KMS driver or no outputs, pipes: 8, outputs: 0
11633 04:43:39.135342 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11634 04:43:39.138864 Opened device: /dev/dri/card0
11635 04:43:39.145489 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11636 04:43:39.148279 Test requirement: is_i915_device(fd)
11637 04:43:39.155337 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11638 04:43:39.158379 Test requirement: is_i915_device(fd)
11639 04:43:39.164926 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11640 04:43:39.168033 No KMS driver or no outputs, pipes: 8, outputs: 0
11641 04:43:39.174550 IGT-V<14>[ 21.873974] [IGT] kms_addfb_basic: exiting, ret=77
11642 04:43:39.184988 ersion: 1.27.1-g621c2d3 (aarch64<8>[ 21.884486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11643 04:43:39.185824 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11645 04:43:39.188548 ) (Linux: 6.1.75-cip14-rt8 aarch64)
11646 04:43:39.191798 Opened devi<14>[ 21.896474] [IGT] kms_addfb_basic: executing
11647 04:43:39.194878 ce: /dev/dri/card0
11648 04:43:39.205172 Test requirement not met in function igt_require_i915, file <14>[ 21.909184] [IGT] kms_addfb_basic: exiting, ret=77
11649 04:43:39.211634 <8>[ 21.913893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11650 04:43:39.212441 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11652 04:43:39.215075 ../lib/drmtest.c:720:
11653 04:43:39.221670 Test requirement: is_i915<14>[ 21.925133] [IGT] kms_addfb_basic: executing
11654 04:43:39.222266 _device(fd)
11655 04:43:39.227817 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11656 04:43:39.238063 Test requirement: is_i915_device<14>[ 21.937740] [IGT] kms_addfb_basic: exiting, ret=77
11657 04:43:39.244697 <8>[ 21.944340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11658 04:43:39.245236 (fd)
11659 04:43:39.245841 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11661 04:43:39.251368 [1mSubtest basic-y-tiled-legacy: SKIP (0.<14>[ 21.956608] [IGT] kms_addfb_basic: executing
11662 04:43:39.254778 000s)[0m
11663 04:43:39.258043 No KMS driver or no outputs, pipes: 8, outputs: 0
11664 04:43:39.264476 IGT-Version: 1.27.<14>[ 21.969265] [IGT] kms_addfb_basic: exiting, ret=77
11665 04:43:39.271032 <8>[ 21.974073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11666 04:43:39.271719 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11668 04:43:39.274549 1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11669 04:43:39.277814 Opened device: /dev/dri/card0
11670 04:43:39.284883 Test requ<14>[ 21.986260] [IGT] kms_addfb_basic: executing
11671 04:43:39.291222 irement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11672 04:43:39.297917 Test r<14>[ 21.998974] [IGT] kms_addfb_basic: exiting, ret=77
11673 04:43:39.304623 <8>[ 22.003706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11674 04:43:39.305160 equirement: is_i915_device(fd)
11675 04:43:39.305760 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11677 04:43:39.314488 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11678 04:43:39.318009 Test requirement: is_i915_device(fd)
11679 04:43:39.324435 No KMS driver or no outputs, pipes: 8, <14>[ 22.026229] [IGT] kms_addfb_basic: executing
11680 04:43:39.324980 outputs: 0
11681 04:43:39.328107 [1mSubtest size-max: SKIP (0.000s)[0m
11682 04:43:39.337359 IGT-Version: 1.27.1-g621c2d<14>[ 22.040131] [IGT] kms_addfb_basic: exiting, ret=77
11683 04:43:39.344358 <8>[ 22.045933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11684 04:43:39.345224 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11686 04:43:39.347797 3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11687 04:43:39.351265 Opened device: /dev/dri/card0
11688 04:43:39.357773 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11689 04:43:39.360785 Test requirement: is_i915_device(fd)
11690 04:43:39.367279 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11691 04:43:39.374073 Test r<14>[ 22.074124] [IGT] kms_addfb_basic: executing
11692 04:43:39.377707 equirement: is_i915_device(fd)
11693 04:43:39.383948 No KMS driver or no outputs, pipes: 8, outputs: <14>[ 22.088009] [IGT] kms_addfb_basic: exiting, ret=77
11694 04:43:39.394013 <8>[ 22.092959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11695 04:43:39.394542 0
11696 04:43:39.395166 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11698 04:43:39.397262 [1mSubtest too-wide: SKIP (0.000s)[0m
11699 04:43:39.403973 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11700 04:43:39.407048 Opened device: /dev/dri/card0
11701 04:43:39.417230 Test requirement not met in function igt_require_i915, file<14>[ 22.120475] [IGT] kms_addfb_basic: executing
11702 04:43:39.417771 ../lib/drmtest.c:720:
11703 04:43:39.420766 Test requirement: is_i915_device(fd)
11704 04:43:39.433606 Test requirement not met in function igt_require_i915, file ../lib<14>[ 22.134407] [IGT] kms_addfb_basic: exiting, ret=77
11705 04:43:39.440208 <8>[ 22.140286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11706 04:43:39.440790 /drmtest.c:720:
11707 04:43:39.441507 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11709 04:43:39.446869 Test requiremen<14>[ 22.153337] [IGT] kms_addfb_basic: executing
11710 04:43:39.450462 t: is_i915_device(fd)
11711 04:43:39.453893 No KMS driver or no outputs, pipes: 8, outputs: 0
11712 04:43:39.457000 [1mSubtest too-high: SKIP (0.000s)[0m
11713 04:43:39.463190 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11714 04:43:39.469921 Ope<14>[ 22.170909] [IGT] kms_addfb_basic: exiting, ret=77
11715 04:43:39.476754 <8>[ 22.175538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11716 04:43:39.477599 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11718 04:43:39.479758 ned device: /dev/dri/card0
11719 04:43:39.483356 Test<14>[ 22.188272] [IGT] kms_addfb_basic: executing
11720 04:43:39.493266 requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11721 04:43:39.496550 T<14>[ 22.201165] [IGT] kms_addfb_basic: exiting, ret=77
11722 04:43:39.506651 <8>[ 22.205830] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11723 04:43:39.507424 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11725 04:43:39.510011 est requirement: is_i915_device(fd)
11726 04:43:39.516941 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11727 04:43:39.519680 Test requirement: is_i915_device(fd)
11728 04:43:39.523376 No<14>[ 22.228055] [IGT] kms_addfb_basic: executing
11729 04:43:39.529845 KMS driver or no outputs, pipes: 8, outputs: 0
11730 04:43:39.533174 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11731 04:43:39.543396 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1<14>[ 22.241912] [IGT] kms_addfb_basic: exiting, ret=77
11732 04:43:39.550079 <8>[ 22.247567] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11733 04:43:39.550872 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11735 04:43:39.553212 <8>[ 22.250801] <LAVA_SIGNAL_TESTSET STOP>
11736 04:43:39.553889 Received signal: <TESTSET> STOP
11737 04:43:39.554280 Closing test_set kms_addfb_basic
11738 04:43:39.556503 .75-cip14-rt8 aarch64)
11739 04:43:39.557039 Opened device: /dev/dri/card0
11740 04:43:39.566524 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11741 04:43:39.569581 Test requirement: is_i915_device(fd)
11742 04:43:39.576326 Test requirement not met in function igt_require<8>[ 22.277837] <LAVA_SIGNAL_TESTSET START kms_atomic>
11743 04:43:39.577183 Received signal: <TESTSET> START kms_atomic
11744 04:43:39.577577 Starting test_set kms_atomic
11745 04:43:39.579615 _i915, file ../lib/drmtest.c:720:
11746 04:43:39.586492 Test requirement: is_i915_dev<14>[ 22.291816] [IGT] kms_atomic: executing
11747 04:43:39.592803 <14>[ 22.292248] [IGT] kms_atomic: exiting, ret=77
11748 04:43:39.599020 <8>[ 22.297015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11749 04:43:39.599473 ice(fd)
11750 04:43:39.600343 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11752 04:43:39.605570 No KMS driver or no outputs, pipes: 8, outputs: 0
11753 04:43:39.609235 [1mSubtest small-bo: SKIP (0.000s)[0m
11754 04:43:39.615528 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11755 04:43:39.619171 Opened device: /d<14>[ 22.322236] [IGT] kms_atomic: executing
11756 04:43:39.625785 <14>[ 22.322797] [IGT] kms_atomic: exiting, ret=77
11757 04:43:39.632192 <8>[ 22.328550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11758 04:43:39.632614 ev/dri/card0
11759 04:43:39.633201 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11761 04:43:39.638831 Test requirement n<14>[ 22.343664] [IGT] kms_atomic: executing
11762 04:43:39.645930 <14>[ 22.344088] [IGT] kms_atomic: exiting, ret=77
11763 04:43:39.652469 <8>[ 22.348538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11764 04:43:39.653331 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11766 04:43:39.658791 ot met in function igt_require_i<14>[ 22.364254] [IGT] kms_atomic: executing
11767 04:43:39.665369 <14>[ 22.364690] [IGT] kms_atomic: exiting, ret=77
11768 04:43:39.672178 <8>[ 22.371147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11769 04:43:39.672947 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11771 04:43:39.675116 915, file ../lib/drmtest.c:720:
11772 04:43:39.678858 <14>[ 22.383628] [IGT] kms_atomic: executing
11773 04:43:39.685497 <14>[ 22.384039] [IGT] kms_atomic: exiting, ret=77
11774 04:43:39.691892 <8>[ 22.388863] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11775 04:43:39.692419
11776 04:43:39.693020 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11778 04:43:39.695154 Test requirement: is_i915_device(fd)
11779 04:43:39.702038 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11780 04:43:39.708631 Test requirement: is_i<14>[ 22.413077] [IGT] kms_atomic: executing
11781 04:43:39.709207 915_device(fd)
11782 04:43:39.715440 No KMS driver or no outputs, pip<14>[ 22.419018] [IGT] kms_atomic: exiting, ret=77
11783 04:43:39.725518 <8>[ 22.423234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11784 04:43:39.726095 es: 8, outputs: 0
11785 04:43:39.726713 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11787 04:43:39.732046 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11788 04:43:39.738292 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1<14>[ 22.443702] [IGT] kms_atomic: executing
11789 04:43:39.744978 <14>[ 22.444214] [IGT] kms_atomic: exiting, ret=77
11790 04:43:39.751655 <8>[ 22.449228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11791 04:43:39.752504 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11793 04:43:39.754936 .75-cip14-rt8 aarch64)
11794 04:43:39.762075 Opened device: /dev/dri/<14>[ 22.462943] [IGT] kms_atomic: executing
11795 04:43:39.765148 <14>[ 22.463370] [IGT] kms_atomic: exiting, ret=77
11796 04:43:39.774813 <8>[ 22.467794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11797 04:43:39.775402 card0
11798 04:43:39.776049 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11800 04:43:39.781835 Test requirement not met <14>[ 22.484229] [IGT] kms_atomic: executing
11801 04:43:39.784634 <14>[ 22.484617] [IGT] kms_atomic: exiting, ret=77
11802 04:43:39.791329 <8>[ 22.491380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11803 04:43:39.792187 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11805 04:43:39.800960 in function igt_require_i915, fi<14>[ 22.503504] [IGT] kms_atomic: executing
11806 04:43:39.804788 <14>[ 22.503860] [IGT] kms_atomic: exiting, ret=77
11807 04:43:39.810827 <8>[ 22.511149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11808 04:43:39.811541 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11810 04:43:39.814502 le ../lib/drmtest.c:720:
11811 04:43:39.820788 Test r<14>[ 22.523318] [IGT] kms_atomic: executing
11812 04:43:39.824185 <14>[ 22.523695] [IGT] kms_atomic: exiting, ret=77
11813 04:43:39.831090 <8>[ 22.527648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11814 04:43:39.831881 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11816 04:43:39.834411 equirement: is_i915_device(fd)
11817 04:43:39.841035 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11818 04:43:39.844588 Test requirement: is_i915_device(fd)
11819 04:43:39.850844 No KMS driver or no out<14>[ 22.553803] [IGT] kms_atomic: executing
11820 04:43:39.857476 <14>[ 22.554302] [IGT] kms_atomic: exiting, ret=77
11821 04:43:39.863842 <8>[ 22.559392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
11822 04:43:39.864574 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
11824 04:43:39.867792 <8>[ 22.560672] <LAVA_SIGNAL_TESTSET STOP>
11825 04:43:39.868580 Received signal: <TESTSET> STOP
11826 04:43:39.868943 Closing test_set kms_atomic
11827 04:43:39.870470 puts, pipes: 8, outputs: 0
11828 04:43:39.873902 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11829 04:43:39.880710 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11830 04:43:39.884334 Opened device: /dev/dri/card0
11831 04:43:39.890717 Test<8>[ 22.591035] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
11832 04:43:39.891599 Received signal: <TESTSET> START kms_flip_event_leak
11833 04:43:39.891967 Starting test_set kms_flip_event_leak
11834 04:43:39.897450 requirement not<14>[ 22.601290] [IGT] kms_flip_event_leak: executing
11835 04:43:39.903762 met in function igt_require_i91<14>[ 22.607553] [IGT] kms_flip_event_leak: exiting, ret=77
11836 04:43:39.910306 <8>[ 22.612258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
11837 04:43:39.911107 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11839 04:43:39.913492 <8>[ 22.613723] <LAVA_SIGNAL_TESTSET STOP>
11840 04:43:39.914374 Received signal: <TESTSET> STOP
11841 04:43:39.914822 Closing test_set kms_flip_event_leak
11842 04:43:39.917294 5, file ../lib/drmtest.c:720:
11843 04:43:39.920372 Test requirement: is_i915_device(fd)
11844 04:43:39.926844 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11845 04:43:39.930297 Test requirement: is_i915_device(fd)
11846 04:43:39.936562 No<8>[ 22.639027] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
11847 04:43:39.937303 Received signal: <TESTSET> START kms_prop_blob
11848 04:43:39.937679 Starting test_set kms_prop_blob
11849 04:43:39.940032 KMS driver or no outputs, pipes: 8, outputs: 0
11850 04:43:39.950365 [1mSubtest addfb25-yf-tiled-le<14>[ 22.651015] [IGT] kms_prop_blob: executing
11851 04:43:39.953456 <14>[ 22.651304] [IGT] kms_prop_blob: starting subtest basic
11852 04:43:39.960093 <14>[ 22.651355] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
11853 04:43:39.966711 <14>[ 22.651397] [IGT] kms_prop_blob: exiting, ret=0
11854 04:43:39.970363 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11856 04:43:39.973609 <8>[ 22.658659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11857 04:43:39.974128 gacy: SKIP (0.000s)[0m
11858 04:43:39.980356 IGT-Version: 1.27.1-g62<14>[ 22.682808] [IGT] kms_prop_blob: executing
11859 04:43:39.986641 <14>[ 22.683254] [IGT] kms_prop_blob: starting subtest blob-prop-core
11860 04:43:39.993141 <14>[ 22.683356] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
11861 04:43:40.001055 <14>[ 22.683448] [IGT] kms_prop_blob: exiting, ret=0
11862 04:43:40.006156 <8>[ 22.688636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
11863 04:43:40.006849 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
11865 04:43:40.009906 <14>[ 22.704901] [IGT] kms_prop_blob: executing
11866 04:43:40.016480 1c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11867 04:43:40.024159 Opened device<14>[ 22.721478] [IGT] kms_prop_blob: starting subtest blob-prop-validate
11868 04:43:40.024590 : /dev/dri/card0
11869 04:43:40.032797 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11870 04:43:40.035867 Test requirement: is_i915_device(fd)
11871 04:43:40.042605 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11872 04:43:40.046139 Test requirement: is_i915_device(fd)
11873 04:43:40.049642 No KMS driver or no outputs, pipes: 8, outputs: 0
11874 04:43:40.056371 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
11875 04:43:40.062763 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11876 04:43:40.063296 Opened device: /dev/dri/card0
11877 04:43:40.072194 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11878 04:43:40.075706 Test requirement: is_i915_device(fd)
11879 04:43:40.082898 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11880 04:43:40.086345 Test requirement: is_i915_device(fd)
11881 04:43:40.089143 No KMS driver or no outputs, pipes: 8, outputs: 0
11882 04:43:40.092453 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
11883 04:43:40.099484 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11884 04:43:40.102535 Opened device: /dev/dri/card0
11885 04:43:40.106150 No KMS driver or no outputs, pipes: 8, outputs: 0
11886 04:43:40.112826 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
11887 04:43:40.118897 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11888 04:43:40.122432 Opened device: /dev/dri/card0
11889 04:43:40.125762 No KMS driver or no outputs, pipes: 8, outputs: 0
11890 04:43:40.128977 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
11891 04:43:40.135483 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11892 04:43:40.139163 Opened device: /dev/dri/card0
11893 04:43:40.142466 No KMS driver or no outputs, pipes: 8, outputs: 0
11894 04:43:40.148565 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
11895 04:43:40.155386 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11896 04:43:40.158687 Opened device: /dev/dri/card0
11897 04:43:40.162241 No KMS driver or no outputs, pipes: 8, outputs: 0
11898 04:43:40.168854 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
11899 04:43:40.175211 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11900 04:43:40.175727 Opened device: /dev/dri/card0
11901 04:43:40.181880 No KMS driver or no outputs, pipes: 8, outputs: 0
11902 04:43:40.185392 [1mSubtest test-only: SKIP (0.000s)[0m
11903 04:43:40.191602 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11904 04:43:40.195012 Opened device: /dev/dri/card0
11905 04:43:40.198464 No KMS driver or no outputs, pipes: 8, outputs: 0
11906 04:43:40.201644 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
11907 04:43:40.208248 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11908 04:43:40.211533 Opened device: /dev/dri/card0
11909 04:43:40.214908 No KMS driver or no outputs, pipes: 8, outputs: 0
11910 04:43:40.221584 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
11911 04:43:40.228539 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11912 04:43:40.231800 Opened device: /dev/dri/card0
11913 04:43:40.234670 No KMS driver or no outputs, pipes: 8, outputs: 0
11914 04:43:40.238366 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
11915 04:43:40.245102 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11916 04:43:40.248172 Opened device: /dev/dri/card0
11917 04:43:40.251329 No KMS driver or no outputs, pipes: 8, outputs: 0
11918 04:43:40.258002 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
11919 04:43:40.264513 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11920 04:43:40.268157 Opened device: /dev/dri/card0
11921 04:43:40.271483 No KMS driver or no outputs, pipes: 8, outputs: 0
11922 04:43:40.274908 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
11923 04:43:40.281708 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11924 04:43:40.284333 Opened device: /dev/dri/card0
11925 04:43:40.291490 No KMS driver or no outputs, pipes: 8, outputs: 0
11926 04:43:40.294523 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
11927 04:43:40.301435 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11928 04:43:40.304363 Opened device: /dev/dri/card0
11929 04:43:40.307894 No KMS driver or no outputs, pipes: 8, outputs: 0
11930 04:43:40.311322 [1mSubtest atomic_plane_damage: SKIP (0.000s)[0m
11931 04:43:40.317617 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11932 04:43:40.321160 Opened device: /dev/dri/card0
11933 04:43:40.327781 No KMS driver or no outputs, pipes: 8, outputs: 0
11934 04:43:40.331400 [1mSubtest basic: SKIP (0.000s)[0m
11935 04:43:40.334089 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11936 04:43:40.337654 Opened device: /dev/dri/card0
11937 04:43:40.340899 Starting subtest: basic
11938 04:43:40.344125 [1mSubtest basic: SUCCESS (0.000s)[0m
11939 04:43:40.350603 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11940 04:43:40.354045 Opened device: /dev/dri/card0
11941 04:43:40.364259 Starting subtest: blob-prop-core<14>[ 23.061682] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
11942 04:43:40.367448 <14>[ 23.061801] [IGT] kms_prop_blob: exiting, ret=0
11943 04:43:40.377588 <8>[ 23.066276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
11944 04:43:40.378503 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
11946 04:43:40.380338 <14>[ 23.079584] [IGT] kms_prop_blob: executing
11947 04:43:40.380821
11948 04:43:40.390470 [1mSubtest blob-prop-core: SU<14>[ 23.091644] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
11949 04:43:40.397235 <14>[ 23.091717] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
11950 04:43:40.403699 <14>[ 23.091747] [IGT] kms_prop_blob: exiting, ret=0
11951 04:43:40.410699 <8>[ 23.096933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
11952 04:43:40.411540 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
11954 04:43:40.414126 <14>[ 23.113378] [IGT] kms_prop_blob: executing
11955 04:43:40.420453 CCESS (0.000s)[<14>[ 23.125437] [IGT] kms_prop_blob: starting subtest blob-multiple
11956 04:43:40.423979 0m
11957 04:43:40.430523 IGT-Version:<14>[ 23.133069] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
11958 04:43:40.437543 <14>[ 23.133111] [IGT] kms_prop_blob: exiting, ret=0
11959 04:43:40.443982 <8>[ 23.137372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
11960 04:43:40.444831 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
11962 04:43:40.447151 1.27.1-g621c2d3<14>[ 23.153439] [IGT] kms_prop_blob: executing
11963 04:43:40.457443 (aarch64) (Linux: 6.1.75-cip14-<14>[ 23.159507] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
11964 04:43:40.467089 <14>[ 23.159562] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
11965 04:43:40.470242 <14>[ 23.159610] [IGT] kms_prop_blob: exiting, ret=0
11966 04:43:40.476800 <8>[ 23.163785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11967 04:43:40.477833 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11969 04:43:40.479565 rt8 aarch64)
11970 04:43:40.483400 Op<14>[ 23.189219] [IGT] kms_prop_blob: executing
11971 04:43:40.489777 <14>[ 23.189736] [IGT] kms_prop_blob: starting subtest invalid-get-prop
11972 04:43:40.493279 ened device: /dev/dri/card0
11973 04:43:40.503521 Starting subtest: blob-prop-validat<14>[ 23.201725] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
11974 04:43:40.510123 <14>[ 23.201785] [IGT] kms_prop_blob: exiting, ret=0
11975 04:43:40.516665 <8>[ 23.206761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11976 04:43:40.517527 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11978 04:43:40.520025 <14>[ 23.219355] [IGT] kms_prop_blob: executing
11979 04:43:40.520604 e
11980 04:43:40.530054 [1mSubtest blob-prop-validat<14>[ 23.231261] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
11981 04:43:40.535866 <14>[ 23.231308] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
11982 04:43:40.542884 <14>[ 23.231343] [IGT] kms_prop_blob: exiting, ret=0
11983 04:43:40.549400 <8>[ 23.235384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11984 04:43:40.550301 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11986 04:43:40.555820 e: SUCCESS (0.00<14>[ 23.261016] [IGT] kms_prop_blob: executing
11987 04:43:40.562603 <14>[ 23.261422] [IGT] kms_prop_blob: starting subtest invalid-set-prop
11988 04:43:40.563186 0s)[0m
11989 04:43:40.572340 IGT-Ver<14>[ 23.261621] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
11990 04:43:40.575644 sion: 1.27.1-g62<14>[ 23.261788] [IGT] kms_prop_blob: exiting, ret=0
11991 04:43:40.585438 <8>[ 23.277504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11992 04:43:40.586202 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11994 04:43:40.589409 <8>[ 23.278681] <LAVA_SIGNAL_TESTSET STOP>
11995 04:43:40.590231 Received signal: <TESTSET> STOP
11996 04:43:40.590590 Closing test_set kms_prop_blob
11997 04:43:40.592536 1c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
11998 04:43:40.595991 Opened device: /dev/dri/card0
11999 04:43:40.599264 Starting subtest: blob-prop-lifetime
12000 04:43:40.605799 [1mSubt<8>[ 23.307298] <LAVA_SIGNAL_TESTSET START kms_setmode>
12001 04:43:40.606639 Received signal: <TESTSET> START kms_setmode
12002 04:43:40.607057 Starting test_set kms_setmode
12003 04:43:40.612724 est blob-prop-lifetime: SUCCESS <14>[ 23.317417] [IGT] kms_setmode: executing
12004 04:43:40.613303 (0.000s)[0m
12005 04:43:40.622108 IGT-Version: 1.27.1-g621c2d3 (aarc<14>[ 23.323162] [IGT] kms_setmode: starting subtest basic
12006 04:43:40.629225 <14>[ 23.323214] [IGT] kms_setmode: finished subtest basic, SKIP
12007 04:43:40.632204 <14>[ 23.323253] [IGT] kms_setmode: exiting, ret=77
12008 04:43:40.638734 <8>[ 23.330563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12009 04:43:40.639529 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12011 04:43:40.642134 <14>[ 23.343397] [IGT] kms_setmode: executing
12012 04:43:40.645312 h64) (Linux: 6.1.75-cip14-rt8 aarch64)
12013 04:43:40.655398 Opened d<14>[ 23.354236] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12014 04:43:40.661796 evice: /dev/dri/<14>[ 23.354287] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12015 04:43:40.668328 <14>[ 23.354328] [IGT] kms_setmode: exiting, ret=77
12016 04:43:40.675128 <8>[ 23.359972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12017 04:43:40.675554 card0
12018 04:43:40.676140 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12020 04:43:40.678484 Starting subtest: blob-multiple
12021 04:43:40.685414 [1mSubt<14>[ 23.386801] [IGT] kms_setmode: executing
12022 04:43:40.691332 <14>[ 23.387258] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12023 04:43:40.698233 <14>[ 23.387337] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12024 04:43:40.705012 <14>[ 23.387400] [IGT] kms_setmode: exiting, ret=77
12025 04:43:40.711835 <8>[ 23.393324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12026 04:43:40.712642 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12028 04:43:40.715030 est blob-multiple: SUCCESS (0.000s)[0m
12029 04:43:40.721981 IGT-Ver<14>[ 23.423010] [IGT] kms_setmode: executing
12030 04:43:40.728376 <14>[ 23.423358] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12031 04:43:40.734817 <14>[ 23.423407] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12032 04:43:40.741615 <14>[ 23.423452] [IGT] kms_setmode: exiting, ret=77
12033 04:43:40.748385 <8>[ 23.428374] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12034 04:43:40.749247 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12036 04:43:40.754853 sion: 1.27.1-g621c2d3 (aarch64) <14>[ 23.459845] [IGT] kms_setmode: executing
12037 04:43:40.764648 (Linux: 6.1.75-c<14>[ 23.460163] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12038 04:43:40.771395 <14>[ 23.460208] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12039 04:43:40.774482 <14>[ 23.460242] [IGT] kms_setmode: exiting, ret=77
12040 04:43:40.784131 <8>[ 23.465238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12041 04:43:40.784703 ip14-rt8 aarch64)
12042 04:43:40.785360 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12044 04:43:40.790950 Opened device: /dev/dri/card0<14>[ 23.494685] [IGT] kms_setmode: executing
12045 04:43:40.800831 <14>[ 23.494986] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12046 04:43:40.807397 <14>[ 23.495028] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12047 04:43:40.814220 <14>[ 23.495064] [IGT] kms_setmode: exiting, ret=77
12048 04:43:40.820772 <8>[ 23.500077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12049 04:43:40.821627 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12051 04:43:40.827284 <8>[ 23.501978] <LAVA_SIGNAL_TESTSET STOP>
12052 04:43:40.828128 Received signal: <TESTSET> STOP
12053 04:43:40.828520 Closing test_set kms_setmode
12054 04:43:40.830404 <8>[ 23.514520] <LAVA_SIGNAL_TESTSET START kms_vblank>
12055 04:43:40.830881
12056 04:43:40.831519 Received signal: <TESTSET> START kms_vblank
12057 04:43:40.831915 Starting test_set kms_vblank
12058 04:43:40.834154 Starting subtest: invalid-get-prop-any
12059 04:43:40.843980 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m<14>[ 23.546917] [IGT] kms_vblank: executing
12060 04:43:40.844558
12061 04:43:40.850410 IGT-Version: 1<14>[ 23.547700] [IGT] kms_vblank: exiting, ret=77
12062 04:43:40.857464 <8>[ 23.553495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12063 04:43:40.858351 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12065 04:43:40.860188 .27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12066 04:43:40.863859 Opened device: /dev/dri/card0
12067 04:43:40.867234 Starting subtest: invalid-get-prop
12068 04:43:40.876852 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0<14>[ 23.579324] [IGT] kms_vblank: executing
12069 04:43:40.877471 m
12070 04:43:40.880335 IGT-Version: <14>[ 23.580039] [IGT] kms_vblank: exiting, ret=77
12071 04:43:40.886910 <8>[ 23.585879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12072 04:43:40.887592 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12074 04:43:40.893245 1.27.1-g621c2d3 (aarch64) (Linux<14>[ 23.599150] [IGT] kms_vblank: executing
12075 04:43:40.900167 : 6.1.75-cip14-r<14>[ 23.599644] [IGT] kms_vblank: exiting, ret=77
12076 04:43:40.910123 <8>[ 23.606750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
12077 04:43:40.910655 t8 aarch64)
12078 04:43:40.911260 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12080 04:43:40.916459 Opened device: /dev<14>[ 23.619909] [IGT] kms_vblank: executing
12081 04:43:40.916915 /dri/card0
12082 04:43:40.923252 Star<14>[ 23.620382] [IGT] kms_vblank: exiting, ret=77
12083 04:43:40.930268 <8>[ 23.624478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
12084 04:43:40.931099 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12086 04:43:40.932949 ting subtest: invalid-set-prop-any
12087 04:43:40.936691 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12088 04:43:40.946709 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarc<14>[ 23.650135] [IGT] kms_vblank: executing
12089 04:43:40.953001 <14>[ 23.650913] [IGT] kms_vblank: exiting, ret=77
12090 04:43:40.959801 <8>[ 23.655917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
12091 04:43:40.960379 h64)
12092 04:43:40.961032 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12094 04:43:40.966111 Opened device: /dev/dri/ca<14>[ 23.670958] [IGT] kms_vblank: executing
12095 04:43:40.972764 <14>[ 23.671430] [IGT] kms_vblank: exiting, ret=77
12096 04:43:40.979673 <8>[ 23.675550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
12097 04:43:40.980247 rd0
12098 04:43:40.980888 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12100 04:43:40.982422 Starting subtest: invalid-set-prop
12101 04:43:40.986004 [1mSub<14>[ 23.690253] [IGT] kms_vblank: executing
12102 04:43:40.992904 <14>[ 23.690725] [IGT] kms_vblank: exiting, ret=77
12103 04:43:40.999389 <8>[ 23.696142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
12104 04:43:41.000131 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12106 04:43:41.006127 test invalid-set-prop: SUCCESS (<14>[ 23.711355] [IGT] kms_vblank: executing
12107 04:43:41.012346 <14>[ 23.711823] [IGT] kms_vblank: exiting, ret=77
12108 04:43:41.019128 <8>[ 23.716017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
12109 04:43:41.019670 0.000s)[0m
12110 04:43:41.020342 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12112 04:43:41.029369 IGT-Version: 1.27.1-g621c2d3 (aarch<14>[ 23.730476] [IGT] kms_vblank: executing
12113 04:43:41.032318 64) (Linux: 6.1.<14>[ 23.730955] [IGT] kms_vblank: exiting, ret=77
12114 04:43:41.042616 <8>[ 23.735123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
12115 04:43:41.043199 75-cip14-rt8 aarch64)
12116 04:43:41.043854 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12118 04:43:41.045418 Opened device: /dev/dri/card0
12119 04:43:41.052210 Starting s<14>[ 23.757364] [IGT] kms_vblank: executing
12120 04:43:41.052747 ubtest: basic
12121 04:43:41.055478 No dynamic tests executed.
12122 04:43:41.058853 [1mS<14>[ 23.762860] [IGT] kms_vblank: exiting, ret=77
12123 04:43:41.068805 ubtest basic: SK<8>[ 23.767169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
12124 04:43:41.069658 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12126 04:43:41.071624 IP (0.000s)[0m
12127 04:43:41.078518 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12128 04:43:41.085277 Opened device: /dev/d<14>[ 23.787491] [IGT] kms_vblank: executing
12129 04:43:41.088612 <14>[ 23.788241] [IGT] kms_vblank: exiting, ret=77
12130 04:43:41.089197 ri/card0
12131 04:43:41.098192 Starti<8>[ 23.793940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
12132 04:43:41.099048 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12134 04:43:41.105327 ng subtest: basi<14>[ 23.809230] [IGT] kms_vblank: executing
12135 04:43:41.105856 c-clone-single-crtc
12136 04:43:41.108453 No dynamic tests executed.
12137 04:43:41.111680 <14>[ 23.815040] [IGT] kms_vblank: exiting, ret=77
12138 04:43:41.118741 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12140 04:43:41.121681 <8>[ 23.821619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
12141 04:43:41.122147
12142 04:43:41.128119 [1mSubtest basic-clone-single-<14>[ 23.832077] [IGT] kms_vblank: executing
12143 04:43:41.131820 crtc: SKIP (0.00<14>[ 23.832548] [IGT] kms_vblank: exiting, ret=77
12144 04:43:41.141606 <8>[ 23.839645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12145 04:43:41.142218 0s)[0m
12146 04:43:41.142869 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12148 04:43:41.148160 IGT-Version: 1.27.1-g62<14>[ 23.851941] [IGT] kms_vblank: executing
12149 04:43:41.154980 1c2d3 (aarch64) <14>[ 23.852415] [IGT] kms_vblank: exiting, ret=77
12150 04:43:41.161532 <8>[ 23.856446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12151 04:43:41.162454 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12153 04:43:41.164586 (Linux: 6.1.75-cip14-rt8 aarch64)
12154 04:43:41.168144 Opened device: /dev/dri/card0
12155 04:43:41.171185 Starting subtest: invalid-clone-single-crtc
12156 04:43:41.174785 N<14>[ 23.879003] [IGT] kms_vblank: executing
12157 04:43:41.180980 <14>[ 23.879842] [IGT] kms_vblank: exiting, ret=77
12158 04:43:41.187532 <8>[ 23.884949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12159 04:43:41.188367 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12161 04:43:41.190831 o dynamic tests executed.
12162 04:43:41.194117 [1mS<14>[ 23.899019] [IGT] kms_vblank: executing
12163 04:43:41.201416 ubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12164 04:43:41.207747 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12165 04:43:41.208326 Opened device: /dev/dri/card0
12166 04:43:41.214478 Starting subtest: invalid-clone-exclusive-crtc
12167 04:43:41.215009 No dynamic tests executed.
12168 04:43:41.220869 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12169 04:43:41.227419 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12170 04:43:41.230976 Opened device: /dev/dri/card0
12171 04:43:41.234359 Starting subtest: clone-exclusive-crtc
12172 04:43:41.234906 No dynamic tests executed.
12173 04:43:41.240684 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12174 04:43:41.247405 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12175 04:43:41.250804 Opened device: /dev/dri/card0
12176 04:43:41.254357 Starting subtest: invalid-clone-single-crtc-stealing
12177 04:43:41.257461 No dynamic tests executed.
12178 04:43:41.260753 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12179 04:43:41.267286 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12180 04:43:41.270523 Opened device: /dev/dri/card0
12181 04:43:41.277484 No KMS driver or no outputs, pipes: 8, outputs: 0
12182 04:43:41.280640 [1mSubtest invalid: SKIP (0.000s)[0m
12183 04:43:41.287467 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12184 04:43:41.288006 Opened device: /dev/dri/card0
12185 04:43:41.294136 No KMS driver or no outputs, pipes: 8, outputs: 0
12186 04:43:41.297538 [1mSubtest crtc-id: SKIP (0.000s)[0m
12187 04:43:41.303750 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12188 04:43:41.307489 Opened device: /dev/dri/card0
12189 04:43:41.310663 No KMS driver or no outputs, pipes: 8, outputs: 0
12190 04:43:41.313852 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
12191 04:43:41.320418 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12192 04:43:41.324215 Opened device: /dev/dri/card0
12193 04:43:41.327215 No KMS driver or no outputs, pipes: 8, outputs: 0
12194 04:43:41.334132 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
12195 04:43:41.340068 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12196 04:43:41.340547 Opened device: /dev/dri/card0
12197 04:43:41.347211 No KMS driver or no outputs, pipes: 8, outputs: 0
12198 04:43:41.350477 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
12199 04:43:41.357374 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12200 04:43:41.360216 Opened device: /dev/dri/card0
12201 04:43:41.363461 No KMS driver or no outputs, pipes: 8, outputs: 0
12202 04:43:41.370180 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
12203 04:43:41.376590 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12204 04:43:41.377062 Opened device: /dev/dri/card0
12205 04:43:41.383451 No KMS driver or no outputs, pipes: 8, outputs: 0
12206 04:43:41.386919 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
12207 04:43:41.393008 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12208 04:43:41.396499 Opened device: /dev/dri/card0
12209 04:43:41.399532 No KMS driver or no outputs, pipes: 8, outputs: 0
12210 04:43:41.406391 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
12211 04:43:41.413338 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12212 04:43:41.413916 Opened device: /dev/dri/card0
12213 04:43:41.420228 No KMS driver or no outputs, pipes: 8, outputs: 0
12214 04:43:41.422906 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
12215 04:43:41.429730 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12216 04:43:41.433398 Opened device: /dev/dri/card0
12217 04:43:41.436292 No KMS driver or no outputs, pipes: 8, outputs: 0
12218 04:43:41.442861 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
12219 04:43:41.449286 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12220 04:43:41.452983 Opened device: /dev/dri/card0
12221 04:43:41.455880 No KMS driver or no outputs, pipes: 8, outputs: 0
12222 04:43:41.459279 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
12223 04:43:41.466090 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12224 04:43:41.469568 Opened device: /dev/dri/card0
12225 04:43:41.475877 No KMS driver or no outputs, pipes: 8, outputs: 0
12226 04:43:41.479472 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
12227 04:43:41.486166 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12228 04:43:41.488867 Opened device: /dev/dri/card0
12229 04:43:41.492655 No KMS driver or no outputs, pipes: 8, outputs: 0
12230 04:43:41.495973 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12231 04:43:41.502775 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12232 04:43:41.506191 Opened device: /dev/dri/card0
12233 04:43:41.509133 No KMS driver or no outputs, pipes: 8, outputs: 0
12234 04:43:41.515917 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12235 04:43:41.522485 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12236 04:43:41.526014 Opened device: /dev/dri/card0
12237 04:43:41.532353 No KMS driver or no outputs, pipes:<14>[ 24.237118] [IGT] kms_vblank: exiting, ret=77
12238 04:43:41.532925 8, outputs: 0
12239 04:43:41.538630 <8>[ 24.241950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12240 04:43:41.539414 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12242 04:43:41.545503 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12243 04:43:41.551551 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12244 04:43:41.555072 Opened device: /dev/dri/card0
12245 04:43:41.558909 No KMS driver o<14>[ 24.263928] [IGT] kms_vblank: executing
12246 04:43:41.565382 <14>[ 24.264771] [IGT] kms_vblank: exiting, ret=77
12247 04:43:41.572015 <8>[ 24.269718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12248 04:43:41.572838 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12250 04:43:41.578395 r no outputs, pipes: 8, outputs:<14>[ 24.283393] [IGT] kms_vblank: executing
12251 04:43:41.578979 0
12252 04:43:41.584473 [1mSubtest <14>[ 24.283872] [IGT] kms_vblank: exiting, ret=77
12253 04:43:41.594771 <8>[ 24.291071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12254 04:43:41.595626 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12256 04:43:41.598063 pipe-A-wait-busy<14>[ 24.304420] [IGT] kms_vblank: executing
12257 04:43:41.604771 : SKIP (0.000s)<14>[ 24.304891] [IGT] kms_vblank: exiting, ret=77
12258 04:43:41.614765 <8>[ 24.309383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12259 04:43:41.615348 [0m
12260 04:43:41.615992 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12262 04:43:41.620929 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12263 04:43:41.624379 Opened device: /dev/dri/card0
12264 04:43:41.627923 No KMS driver or no outputs, pipes: 8, outputs: 0
12265 04:43:41.630821 <14>[ 24.335782] [IGT] kms_vblank: executing
12266 04:43:41.637728 <14>[ 24.336596] [IGT] kms_vblank: exiting, ret=77
12267 04:43:41.644036 <8>[ 24.341803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12268 04:43:41.644461
12269 04:43:41.645044 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12271 04:43:41.650821 [1mSubtest pipe-A-wait-busy-ha<14>[ 24.355501] [IGT] kms_vblank: executing
12272 04:43:41.657402 ng: SKIP (0.000s<14>[ 24.356020] [IGT] kms_vblank: exiting, ret=77
12273 04:43:41.667669 <8>[ 24.362191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12274 04:43:41.668243 )[0m
12275 04:43:41.668888 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12277 04:43:41.670863 IGT-Versi<14>[ 24.377297] [IGT] kms_vblank: executing
12278 04:43:41.680557 on: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip<14>[ 24.383154] [IGT] kms_vblank: exiting, ret=77
12279 04:43:41.690182 <8>[ 24.387694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12280 04:43:41.690607 14-rt8 aarch64)
12281 04:43:41.691191 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12283 04:43:41.693615 <14>[ 24.400449] [IGT] kms_vblank: executing
12284 04:43:41.694061
12285 04:43:41.700599 Opened device: <14>[ 24.400951] [IGT] kms_vblank: exiting, ret=77
12286 04:43:41.710381 <8>[ 24.407757] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12287 04:43:41.710907 /dev/dri/card0
12288 04:43:41.711502 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12290 04:43:41.717286 <14>[ 24.421116] [IGT] kms_vblank: executing
12291 04:43:41.723454 No KMS driver or no outputs, pipes: 8, outputs: <14>[ 24.421603] [IGT] kms_vblank: exiting, ret=77
12292 04:43:41.723996 0
12293 04:43:41.733480 [1mSubtest p<8>[ 24.431045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12294 04:43:41.734366 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12296 04:43:41.736848 ipe-A-wait-forked-busy: SKIP (0.000s)[0m
12297 04:43:41.746830 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75<14>[ 24.453229] [IGT] kms_vblank: executing
12298 04:43:41.749785 -cip14-rt8 aarch64)
12299 04:43:41.756858 Opened device: /dev/dri/car<14>[ 24.458450] [IGT] kms_vblank: exiting, ret=77
12300 04:43:41.763385 <8>[ 24.462641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12301 04:43:41.764050 d0
12302 04:43:41.764821 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12304 04:43:41.769604 No KMS driver or no outputs,<14>[ 24.475471] [IGT] kms_vblank: executing
12305 04:43:41.776485 pipes: 8, outpu<14>[ 24.475958] [IGT] kms_vblank: exiting, ret=77
12306 04:43:41.786505 <8>[ 24.480023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12307 04:43:41.787043 ts: 0
12308 04:43:41.787718 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12310 04:43:41.793120 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12311 04:43:41.799618 IGT-Version: 1.27.1-g621c2d3<14>[ 24.502446] [IGT] kms_vblank: executing
12312 04:43:41.803109 <14>[ 24.503221] [IGT] kms_vblank: exiting, ret=77
12313 04:43:41.813110 <8>[ 24.508259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12314 04:43:41.813778 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12316 04:43:41.819462 (aarch64) (Linux: 6.1.75-cip14-<14>[ 24.523573] [IGT] kms_vblank: executing
12317 04:43:41.822882 <14>[ 24.524031] [IGT] kms_vblank: exiting, ret=77
12318 04:43:41.832947 <8>[ 24.530624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12319 04:43:41.833470 rt8 aarch64)
12320 04:43:41.834065 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12322 04:43:41.839390 Opened device: /de<14>[ 24.542929] [IGT] kms_vblank: executing
12323 04:43:41.842399 <14>[ 24.543417] [IGT] kms_vblank: exiting, ret=77
12324 04:43:41.848943 <8>[ 24.549574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12325 04:43:41.849608 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12327 04:43:41.852344 v/dri/card0
12328 04:43:41.855743 No KMS driver or no outputs, pipes: 8, outputs: 0
12329 04:43:41.862509 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12330 04:43:41.872414 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarc<14>[ 24.573798] [IGT] kms_vblank: executing
12331 04:43:41.876004 <14>[ 24.574682] [IGT] kms_vblank: exiting, ret=77
12332 04:43:41.882740 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12334 04:43:41.885436 <8>[ 24.580130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12335 04:43:41.885992 h64)
12336 04:43:41.892532 Opened device: /dev/dri/ca<14>[ 24.595511] [IGT] kms_vblank: executing
12337 04:43:41.896032 <14>[ 24.595948] [IGT] kms_vblank: exiting, ret=77
12338 04:43:41.902602 <8>[ 24.600725] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12339 04:43:41.903021 rd0
12340 04:43:41.903594 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12342 04:43:41.912452 No KMS driver or no outputs, pipes: 8, outp<14>[ 24.614806] [IGT] kms_vblank: executing
12343 04:43:41.915660 <14>[ 24.615292] [IGT] kms_vblank: exiting, ret=77
12344 04:43:41.925304 <8>[ 24.621377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12345 04:43:41.925821 uts: 0
12346 04:43:41.926475 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12348 04:43:41.932304 [1mSubtest pipe-A-ts-co<14>[ 24.635929] [IGT] kms_vblank: executing
12349 04:43:41.935820 <14>[ 24.636412] [IGT] kms_vblank: exiting, ret=77
12350 04:43:41.942052 <8>[ 24.645846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12351 04:43:41.942763 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12353 04:43:41.951911 ntinuation-idle-hang: SKIP (0.00<14>[ 24.656272] [IGT] kms_vblank: executing
12354 04:43:41.955399 <14>[ 24.656738] [IGT] kms_vblank: exiting, ret=77
12355 04:43:41.962234 <8>[ 24.662878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12356 04:43:41.962917 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12358 04:43:41.965078 0s)[0m
12359 04:43:41.971988 IGT-Version: 1.27.1-g621c2d3 (aarch64) <14>[ 24.674562] [IGT] kms_vblank: executing
12360 04:43:41.975451 <14>[ 24.675040] [IGT] kms_vblank: exiting, ret=77
12361 04:43:41.985367 <8>[ 24.681119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12362 04:43:41.986054 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12364 04:43:41.991494 (Linux: 6.1.75-cip14-rt8 aarch64<14>[ 24.695676] [IGT] kms_vblank: executing
12365 04:43:41.995058 <14>[ 24.696161] [IGT] kms_vblank: exiting, ret=77
12366 04:43:42.005170 <8>[ 24.702186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12367 04:43:42.005650 )
12368 04:43:42.006425 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12370 04:43:42.011637 Opened device: /dev/dri/card0<14>[ 24.715849] [IGT] kms_vblank: executing
12371 04:43:42.014909 <14>[ 24.716323] [IGT] kms_vblank: exiting, ret=77
12372 04:43:42.025005 <8>[ 24.722473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12373 04:43:42.025435
12374 04:43:42.026143 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12376 04:43:42.027913 No KMS driver or no outputs, pipes: 8, outputs: 0
12377 04:43:42.034779 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12378 04:43:42.044845 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14<14>[ 24.748352] [IGT] kms_vblank: executing
12379 04:43:42.047796 <14>[ 24.749197] [IGT] kms_vblank: exiting, ret=77
12380 04:43:42.054727 <8>[ 24.754323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12381 04:43:42.055402 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12383 04:43:42.058095 -rt8 aarch64)
12384 04:43:42.058588 Opened device: /dev/dri/card0
12385 04:43:42.068073 No KMS driver or no outputs, pipes<14>[ 24.772746] [IGT] kms_vblank: executing
12386 04:43:42.068606 : 8, outputs: 0
12387 04:43:42.070959 <14>[ 24.773831] [IGT] kms_vblank: exiting, ret=77
12388 04:43:42.074589
12389 04:43:42.077883 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12390 04:43:42.087704 IGT-Version<8>[ 24.788388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12391 04:43:42.088405 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12393 04:43:42.094539 : 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14<14>[ 24.798748] [IGT] kms_vblank: executing
12394 04:43:42.100758 <14>[ 24.799209] [IGT] kms_vblank: exiting, ret=77
12395 04:43:42.107370 <8>[ 24.808298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12396 04:43:42.108126 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12398 04:43:42.110685 -rt8 aarch64)
12399 04:43:42.114030 Opened device: /d<14>[ 24.819556] [IGT] kms_vblank: executing
12400 04:43:42.120696 <14>[ 24.820031] [IGT] kms_vblank: exiting, ret=77
12401 04:43:42.127242 <8>[ 24.824960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12402 04:43:42.127671 ev/dri/card0
12403 04:43:42.128314 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12405 04:43:42.137381 No KMS driver or no outputs, pipes<14>[ 24.838604] [IGT] kms_vblank: executing
12406 04:43:42.140816 <14>[ 24.839081] [IGT] kms_vblank: exiting, ret=77
12407 04:43:42.147263 <8>[ 24.846507] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12408 04:43:42.147958 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12410 04:43:42.150669 : 8, outputs: 0
12411 04:43:42.153757 [1mSubtest pip<14>[ 24.859467] [IGT] kms_vblank: executing
12412 04:43:42.160317 <14>[ 24.859940] [IGT] kms_vblank: exiting, ret=77
12413 04:43:42.167300 <8>[ 24.863994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12414 04:43:42.167990 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12416 04:43:42.170346 e-A-ts-continuation-suspend: SKIP (0.000s)[0m
12417 04:43:42.177287 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12418 04:43:42.180730 Opened device: /dev/dri/card0
12419 04:43:42.187184 No KMS driver or no out<14>[ 24.890600] [IGT] kms_vblank: executing
12420 04:43:42.190061 puts, pipes: 8, outputs: 0
12421 04:43:42.193557 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12422 04:43:42.200429 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12423 04:43:42.203497 Opened device: /dev/dri/card0
12424 04:43:42.210407 No KMS driver or no outputs, pipes: 8, outputs: 0
12425 04:43:42.213673 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12426 04:43:42.219949 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12427 04:43:42.223620 Opened device: /dev/dri/card0
12428 04:43:42.226736 No KMS driver or no outputs, pipes: 8, outputs: 0
12429 04:43:42.233605 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12430 04:43:42.240249 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12431 04:43:42.243470 Opened device: /dev/dri/card0
12432 04:43:42.247176 No KMS driver or no outputs, pipes: 8, outputs: 0
12433 04:43:42.253610 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12434 04:43:42.259934 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12435 04:43:42.260383 Opened device: /dev/dri/card0
12436 04:43:42.266476 No KMS driver or no outputs, pipes: 8, outputs: 0
12437 04:43:42.269973 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12438 04:43:42.276345 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12439 04:43:42.279917 Opened device: /dev/dri/card0
12440 04:43:42.282902 No KMS driver or no outputs, pipes: 8, outputs: 0
12441 04:43:42.289560 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12442 04:43:42.296414 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12443 04:43:42.296924 Opened device: /dev/dri/card0
12444 04:43:42.303183 No KMS driver or no outputs, pipes: 8, outputs: 0
12445 04:43:42.306203 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12446 04:43:42.312981 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12447 04:43:42.316228 Opened device: /dev/dri/card0
12448 04:43:42.319352 No KMS driver or no outputs, pipes: 8, outputs: 0
12449 04:43:42.325780 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12450 04:43:42.332977 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12451 04:43:42.333493 Opened device: /dev/dri/card0
12452 04:43:42.339493 No KMS driver or no outputs, pipes: 8, outputs: 0
12453 04:43:42.342943 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12454 04:43:42.349487 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12455 04:43:42.352501 Opened device: /dev/dri/card0
12456 04:43:42.355944 No KMS driver or no outputs, pipes: 8, outputs: 0
12457 04:43:42.362780 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12458 04:43:42.365871 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12459 04:43:42.369142 Opened device: /dev/dri/card0
12460 04:43:42.375615 No KMS driver or no outputs, pipes: 8, outputs: 0
12461 04:43:42.379170 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12462 04:43:42.386015 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12463 04:43:42.388992 Opened device: /dev/dri/card0
12464 04:43:42.392665 No KMS driver or no outputs, pipes: 8, outputs: 0
12465 04:43:42.399356 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)[0m
12466 04:43:42.406085 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12467 04:43:42.409139 Opened device: /dev/dri/card0
12468 04:43:42.412647 No KMS driver or no outputs, pipes: 8, outputs: 0
12469 04:43:42.415564 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12470 04:43:42.422298 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12471 04:43:42.425550 Opened device: /dev/dri/card0
12472 04:43:42.428905 No KMS driver or no outputs, pipes: 8, outputs: 0
12473 04:43:42.435476 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12474 04:43:42.441934 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12475 04:43:42.445488 Opened device: /dev/dri/card0
12476 04:43:42.448913 No KMS driver or no outputs, pipes: 8, outputs: 0
12477 04:43:42.452208 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12478 04:43:42.458637 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12479 04:43:42.462141 Opened device: /dev/dri/card0
12480 04:43:42.465595 No KMS driver or no outputs, pipes: 8, outputs: 0
12481 04:43:42.471779 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12482 04:43:42.478273 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12483 04:43:42.481667 Opened device: /dev/dri/card0
12484 04:43:42.485200 No KMS driver or no outputs, pipes: 8, outputs: 0
12485 04:43:42.488463 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12486 04:43:42.495275 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12487 04:43:42.498092 Opened device: /dev/dri/card0
12488 04:43:42.501644 No KMS driver or no outputs, pipes: 8, outputs: 0
12489 04:43:42.508268 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12490 04:43:42.515159 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12491 04:43:42.515713 Opened device: /dev/dri/card0
12492 04:43:42.524773 No KMS driver or no outputs, pipes: 8<14>[ 25.228311] [IGT] kms_vblank: exiting, ret=77
12493 04:43:42.531284 <8>[ 25.233544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12494 04:43:42.532230 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12496 04:43:42.534709 , outputs: 0
12497 04:43:42.537926 [1mSubtest pipe-B<14>[ 25.243624] [IGT] kms_vblank: executing
12498 04:43:42.544529 -wait-forked-bus<14>[ 25.244093] [IGT] kms_vblank: exiting, ret=77
12499 04:43:42.554855 <8>[ 25.250013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12500 04:43:42.555422 y: SKIP (0.000s)[0m
12501 04:43:42.556060 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12503 04:43:42.561311 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12504 04:43:42.564801 Opened device: /dev/dri/card0
12505 04:43:42.571185 No KMS driver or no outputs, pipe<14>[ 25.276953] [IGT] kms_vblank: executing
12506 04:43:42.574641 s: 8, outputs: 0
12507 04:43:42.578283 [1mSubtest pi<14>[ 25.283384] [IGT] kms_vblank: exiting, ret=77
12508 04:43:42.584839 pe-B-wait-forked-busy-hang: SKIP (0.000s)[0m
12509 04:43:42.591194 I<8>[ 25.293434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12510 04:43:42.592033 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12512 04:43:42.598077 GT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12513 04:43:42.604153 Opened <14>[ 25.307104] [IGT] kms_vblank: executing
12514 04:43:42.607841 <14>[ 25.307663] [IGT] kms_vblank: exiting, ret=77
12515 04:43:42.617859 <8>[ 25.317327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12516 04:43:42.618463 device: /dev/dri/card0
12517 04:43:42.619104 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12519 04:43:42.624283 No KMS driver or no outputs, pipes: 8, outputs: 0
12520 04:43:42.627426 [1mS<14>[ 25.329972] [IGT] kms_vblank: executing
12521 04:43:42.634279 <14>[ 25.330519] [IGT] kms_vblank: exiting, ret=77
12522 04:43:42.640638 <8>[ 25.337086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12523 04:43:42.641500 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12525 04:43:42.647451 ubtest pipe-B-ts<14>[ 25.352838] [IGT] kms_vblank: executing
12526 04:43:42.650408 <14>[ 25.353382] [IGT] kms_vblank: exiting, ret=77
12527 04:43:42.660613 <8>[ 25.359817] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12528 04:43:42.661492 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12530 04:43:42.667233 -continuation-idle: SKIP (0.000s<14>[ 25.372025] [IGT] kms_vblank: executing
12531 04:43:42.673877 <14>[ 25.372580] [IGT] kms_vblank: exiting, ret=77
12532 04:43:42.680306 <8>[ 25.379390] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12533 04:43:42.680873 )[0m
12534 04:43:42.681506 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12536 04:43:42.687142 IGT-Version: 1.27.1-g621c<14>[ 25.391914] [IGT] kms_vblank: executing
12537 04:43:42.693351 <14>[ 25.392432] [IGT] kms_vblank: exiting, ret=77
12538 04:43:42.700451 <8>[ 25.399338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12539 04:43:42.701256 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12541 04:43:42.706694 2d3 (aarch64) (L<14>[ 25.412572] [IGT] kms_vblank: executing
12542 04:43:42.709967 <14>[ 25.413087] [IGT] kms_vblank: exiting, ret=77
12543 04:43:42.720223 <8>[ 25.419402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12544 04:43:42.721024 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12546 04:43:42.723531 inux: 6.1.75-cip14-rt8 aarch64)
12547 04:43:42.727101 <14>[ 25.431757] [IGT] kms_vblank: executing
12548 04:43:42.733208 <14>[ 25.432232] [IGT] kms_vblank: exiting, ret=77
12549 04:43:42.739951 <8>[ 25.436914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12550 04:43:42.740436
12551 04:43:42.741065 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12553 04:43:42.743168 Opened device: /dev/dri/card0
12554 04:43:42.746832 No KMS driver or no outputs, pipes: 8, outputs: 0
12555 04:43:42.753147 [1mSubtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)[0m
12556 04:43:42.759780 IGT-Version: 1.27.1-g621c2d3<14>[ 25.464526] [IGT] kms_vblank: executing
12557 04:43:42.763421 <14>[ 25.465309] [IGT] kms_vblank: exiting, ret=77
12558 04:43:42.766618 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12559 04:43:42.769848 Opened device: /dev/dri/card0
12560 04:43:42.776564 No KMS driver or no outputs, pipes: 8, outputs: 0
12561 04:43:42.782841 <8>[ 25.484895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12562 04:43:42.783683 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12564 04:43:42.789593 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKI<14>[ 25.495644] [IGT] kms_vblank: executing
12565 04:43:42.796491 <14>[ 25.496123] [IGT] kms_vblank: exiting, ret=77
12566 04:43:42.802770 <8>[ 25.501972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12567 04:43:42.803614 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12569 04:43:42.806429 P (0.000s)[0m
12570 04:43:42.813215 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 25.514781] [IGT] kms_vblank: executing
12571 04:43:42.816653 <14>[ 25.515285] [IGT] kms_vblank: exiting, ret=77
12572 04:43:42.823076 <8>[ 25.520366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12573 04:43:42.823938 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12575 04:43:42.829696 rch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12576 04:43:42.830294 Opened device: /dev/dri/card0
12577 04:43:42.836493 No KMS driver or no outputs, pipes: 8, outputs: 0
12578 04:43:42.839349 [1m<14>[ 25.542949] [IGT] kms_vblank: executing
12579 04:43:42.842612 <14>[ 25.543736] [IGT] kms_vblank: exiting, ret=77
12580 04:43:42.852506 <8>[ 25.548905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12581 04:43:42.853345 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12583 04:43:42.859139 Subtest pipe-B-ts-continuation-d<14>[ 25.563470] [IGT] kms_vblank: executing
12584 04:43:42.862395 <14>[ 25.563952] [IGT] kms_vblank: exiting, ret=77
12585 04:43:42.872411 <8>[ 25.570247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12586 04:43:42.873354 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12588 04:43:42.875596 pms-suspend: SKIP (0.000s)[0m
12589 04:43:42.879022 IGT-Version: 1.2<14>[ 25.582582] [IGT] kms_vblank: executing
12590 04:43:42.886111 <14>[ 25.583065] [IGT] kms_vblank: exiting, ret=77
12591 04:43:42.892556 <8>[ 25.587792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12592 04:43:42.893387 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12594 04:43:42.895617 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12595 04:43:42.898920 Opened device: /dev/dri/card0
12596 04:43:42.906077 No KMS driver or no outputs, pipes: 8, outputs: 0
12597 04:43:42.912368 [1mSubtest pipe-B-ts-continuation-s<14>[ 25.615677] [IGT] kms_vblank: executing
12598 04:43:42.915891 <14>[ 25.616461] [IGT] kms_vblank: exiting, ret=77
12599 04:43:42.925665 <8>[ 25.621867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12600 04:43:42.926289 uspend: SKIP (0.000s)[0m
12601 04:43:42.926929 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12603 04:43:42.932384 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12604 04:43:42.938811 Opened device: /dev/dri/car<14>[ 25.642089] [IGT] kms_vblank: executing
12605 04:43:42.945387 <14>[ 25.642879] [IGT] kms_vblank: exiting, ret=77
12606 04:43:42.952185 <8>[ 25.648055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12607 04:43:42.952756 d0
12608 04:43:42.953393 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12610 04:43:42.958616 No KMS driver or no outputs, pipes: 8, outputs: 0
12611 04:43:42.965264 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)<14>[ 25.670301] [IGT] kms_vblank: executing
12612 04:43:42.971924 <14>[ 25.671140] [IGT] kms_vblank: exiting, ret=77
12613 04:43:42.978675 <8>[ 25.676492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12614 04:43:42.979217 [0m
12615 04:43:42.979850 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12617 04:43:42.985063 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12618 04:43:42.991562 Opened device: /<14>[ 25.695914] [IGT] kms_vblank: executing
12619 04:43:42.995066 <14>[ 25.696785] [IGT] kms_vblank: exiting, ret=77
12620 04:43:43.004484 <8>[ 25.702112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12621 04:43:43.004659 dev/dri/card0
12622 04:43:43.004927 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12624 04:43:43.011391 No KMS driver or <14>[ 25.715028] [IGT] kms_vblank: executing
12625 04:43:43.014810 <14>[ 25.715472] [IGT] kms_vblank: exiting, ret=77
12626 04:43:43.021189 <8>[ 25.721765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12627 04:43:43.021606 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12629 04:43:43.024333 no outputs, pipes: 8, outputs: 0
12630 04:43:43.030971 [1mSubtest pi<14>[ 25.734290] [IGT] kms_vblank: executing
12631 04:43:43.034479 <14>[ 25.734736] [IGT] kms_vblank: exiting, ret=77
12632 04:43:43.044271 <8>[ 25.741324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12633 04:43:43.044901 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12635 04:43:43.047618 pe-B-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12636 04:43:43.054321 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12637 04:43:43.057753 Opened device: /dev/dri/card0
12638 04:43:43.064153 No KMS driver or <14>[ 25.765913] [IGT] kms_vblank: executing
12639 04:43:43.067622 <14>[ 25.766776] [IGT] kms_vblank: exiting, ret=77
12640 04:43:43.074483 <8>[ 25.772675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12641 04:43:43.074841 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12643 04:43:43.077622 no outputs, pipes: 8, outputs: 0
12644 04:43:43.084253 [1mSubtest pi<14>[ 25.786834] [IGT] kms_vblank: executing
12645 04:43:43.087508 <14>[ 25.787307] [IGT] kms_vblank: exiting, ret=77
12646 04:43:43.097425 <8>[ 25.793182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12647 04:43:43.097937 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12649 04:43:43.103659 pe-B-ts-continuation-modeset-rpm<14>[ 25.807659] [IGT] kms_vblank: executing
12650 04:43:43.107123 <14>[ 25.808093] [IGT] kms_vblank: exiting, ret=77
12651 04:43:43.113660 <8>[ 25.814392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12652 04:43:43.113945 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12654 04:43:43.117175 : SKIP (0.000s)[0m
12655 04:43:43.124054 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12656 04:43:43.127030 Opened device: /dev/dri/card0
12657 04:43:43.130584 No<14>[ 25.836606] [IGT] kms_vblank: executing
12658 04:43:43.136762 <14>[ 25.837515] [IGT] kms_vblank: exiting, ret=77
12659 04:43:43.140318 KMS driver or no outputs, pipes: 8, outputs: 0
12660 04:43:43.150535 [1mSubtest pipe-C-accuracy-idl<8>[ 25.851749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12661 04:43:43.150823 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12663 04:43:43.153602 e: SKIP (0.000s)[0m
12664 04:43:43.160153 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12665 04:43:43.163749 Opened device: /dev/dri/card0
12666 04:43:43.167096 No KMS driver or no outputs, pipes: 8, outputs: 0
12667 04:43:43.173929 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[<14>[ 25.878711] [IGT] kms_vblank: executing
12668 04:43:43.180165 <14>[ 25.879514] [IGT] kms_vblank: exiting, ret=77
12669 04:43:43.186971 <8>[ 25.885317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12670 04:43:43.187401 0m
12671 04:43:43.188046 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12673 04:43:43.193626 IGT-Version: 1.27.1-g621c2d3<14>[ 25.899306] [IGT] kms_vblank: executing
12674 04:43:43.200123 <14>[ 25.899789] [IGT] kms_vblank: exiting, ret=77
12675 04:43:43.206937 <8>[ 25.909073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12676 04:43:43.207609 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12678 04:43:43.217174 (aarch64) (Linux: 6.1.75-cip14-<14>[ 25.919732] [IGT] kms_vblank: executing
12679 04:43:43.217710 rt8 aarch64)
12680 04:43:43.220696 Op<14>[ 25.920166] [IGT] kms_vblank: exiting, ret=77
12681 04:43:43.230452 <8>[ 25.926353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12682 04:43:43.231291 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12684 04:43:43.237182 ened device: /de<14>[ 25.941409] [IGT] kms_vblank: executing
12685 04:43:43.237759 v/dri/card0
12686 04:43:43.243546 No KMS driver or no<14>[ 25.947264] [IGT] kms_vblank: exiting, ret=77
12687 04:43:43.253509 <8>[ 25.953654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12688 04:43:43.254126 outputs, pipes: 8, outputs: 0
12689 04:43:43.254772 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12691 04:43:43.259916 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12692 04:43:43.266695 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12693 04:43:43.273084 Opened device: <14>[ 25.975650] [IGT] kms_vblank: executing
12694 04:43:43.276560 <14>[ 25.976435] [IGT] kms_vblank: exiting, ret=77
12695 04:43:43.283513 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12697 04:43:43.286283 <8>[ 25.981520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12698 04:43:43.286761 /dev/dri/card0
12699 04:43:43.289589 No KMS driver or no outputs, pipes: 8, outputs: 0
12700 04:43:43.299709 [1mSubtest pipe-C-query-forked: SKIP (0.000s<14>[ 26.001730] [IGT] kms_vblank: executing
12701 04:43:43.300289 )[0m
12702 04:43:43.305848 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12703 04:43:43.309418 Opened device: /dev/dri/card0
12704 04:43:43.312871 No KMS driver or no outputs, pipes: 8, outputs: 0
12705 04:43:43.319673 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12706 04:43:43.323335 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12707 04:43:43.326218 Opened device: /dev/dri/card0
12708 04:43:43.332681 No KMS driver or no outputs, pipes: 8, outputs: 0
12709 04:43:43.336388 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12710 04:43:43.342620 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12711 04:43:43.345689 Opened device: /dev/dri/card0
12712 04:43:43.349020 No KMS driver or no outputs, pipes: 8, outputs: 0
12713 04:43:43.352471 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12714 04:43:43.359087 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12715 04:43:43.362338 Opened device: /dev/dri/card0
12716 04:43:43.368812 No KMS driver or no outputs, pipes: 8, outputs: 0
12717 04:43:43.372281 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12718 04:43:43.378653 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12719 04:43:43.382223 Opened device: /dev/dri/card0
12720 04:43:43.385790 No KMS driver or no outputs, pipes: 8, outputs: 0
12721 04:43:43.392205 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12722 04:43:43.398951 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12723 04:43:43.402019 Opened device: /dev/dri/card0
12724 04:43:43.405338 No KMS driver or no outputs, pipes: 8, outputs: 0
12725 04:43:43.409063 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12726 04:43:43.415918 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12727 04:43:43.419321 Opened device: /dev/dri/card0
12728 04:43:43.422458 No KMS driver or no outputs, pipes: 8, outputs: 0
12729 04:43:43.428893 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12730 04:43:43.435844 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12731 04:43:43.436421 Opened device: /dev/dri/card0
12732 04:43:43.442099 No KMS driver or no outputs, pipes: 8, outputs: 0
12733 04:43:43.445173 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12734 04:43:43.451920 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12735 04:43:43.455300 Opened device: /dev/dri/card0
12736 04:43:43.458514 No KMS driver or no outputs, pipes: 8, outputs: 0
12737 04:43:43.465249 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12738 04:43:43.471632 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12739 04:43:43.472105 Opened device: /dev/dri/card0
12740 04:43:43.478664 No KMS driver or no outputs, pipes: 8, outputs: 0
12741 04:43:43.481747 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12742 04:43:43.488375 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12743 04:43:43.491424 Opened device: /dev/dri/card0
12744 04:43:43.494981 No KMS driver or no outputs, pipes: 8, outputs: 0
12745 04:43:43.501419 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12746 04:43:43.504934 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12747 04:43:43.508374 Opened device: /dev/dri/card0
12748 04:43:43.515091 No KMS driver or no outputs, pipes: 8, outputs: 0
12749 04:43:43.517960 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12750 04:43:43.524565 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12751 04:43:43.527927 Opened device: /dev/dri/card0
12752 04:43:43.531456 No KMS driver or no outputs, pipes: 8, outputs: 0
12753 04:43:43.538410 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[0m
12754 04:43:43.544903 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12755 04:43:43.547928 Opened device: /dev/dri/card0
12756 04:43:43.551611 No KMS driver or no outputs, pipes: 8, outputs: 0
12757 04:43:43.554956 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12758 04:43:43.561562 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12759 04:43:43.564625 Opened device: /dev/dri/card0
12760 04:43:43.571300 No KMS driver or no outputs, pipes: 8, outputs: 0
12761 04:43:43.574532 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12762 04:43:43.580858 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12763 04:43:43.584497 Opened device: /dev/dri/card0
12764 04:43:43.587425 No KMS driver or no outputs, pipes: 8, outputs: 0
12765 04:43:43.594015 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12766 04:43:43.600662 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12767 04:43:43.604008 Opened device: /dev/dri/card0
12768 04:43:43.607484 No KMS driver or no outputs, pipes: 8, outputs: 0
12769 04:43:43.613992 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12770 04:43:43.620516 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12771 04:43:43.624345 Opened device: /dev/dri/card0
12772 04:43:43.627131 No KMS driver or no outputs, pipes: 8, outputs: 0
12773 04:43:43.633865 [1mSubtest pipe-C-ts-continuation-suspen<14>[ 26.340049] [IGT] kms_vblank: exiting, ret=77
12774 04:43:43.643590 <8>[ 26.345895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12775 04:43:43.644381 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12777 04:43:43.647288 d: SKIP (0.000s)[0m
12778 04:43:43.650213 IGT-Versio<14>[ 26.355849] [IGT] kms_vblank: executing
12779 04:43:43.657013 <14>[ 26.356339] [IGT] kms_vblank: exiting, ret=77
12780 04:43:43.663530 <8>[ 26.362523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12781 04:43:43.664214 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12783 04:43:43.670021 n: 1.27.1-g621c2d3 (aarch64) (Li<14>[ 26.376069] [IGT] kms_vblank: executing
12784 04:43:43.676726 <14>[ 26.376544] [IGT] kms_vblank: exiting, ret=77
12785 04:43:43.683605 <8>[ 26.384545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12786 04:43:43.684290 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12788 04:43:43.690081 nux: 6.1.75-cip1<14>[ 26.396646] [IGT] kms_vblank: executing
12789 04:43:43.696623 <14>[ 26.397165] [IGT] kms_vblank: exiting, ret=77
12790 04:43:43.703275 <8>[ 26.406634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12791 04:43:43.703785 4-rt8 aarch64)
12792 04:43:43.704561 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12794 04:43:43.706776 Opened device: /dev/dri/card0
12795 04:43:43.716630 No KMS driver or no outputs, pipes: 8, outputs: 0<14>[ 26.418207] [IGT] kms_vblank: executing
12796 04:43:43.719971 <14>[ 26.418747] [IGT] kms_vblank: exiting, ret=77
12797 04:43:43.726658 <8>[ 26.428281] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12798 04:43:43.727096
12799 04:43:43.727694 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12801 04:43:43.733036 [1mSubtest pipe-C-ts-continua<14>[ 26.439761] [IGT] kms_vblank: executing
12802 04:43:43.740075 <14>[ 26.440292] [IGT] kms_vblank: exiting, ret=77
12803 04:43:43.746082 <8>[ 26.449927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12804 04:43:43.746891 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12806 04:43:43.749822 tion-modeset: SKIP (0.000s)[0m
12807 04:43:43.756421 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12808 04:43:43.759527 Opened device: /dev/dri/card0
12809 04:43:43.763040 No KMS driver or no outputs, pipes: 8, outputs: 0
12810 04:43:43.769259 [1mSubtest pipe-C-ts-continuation-<14>[ 26.474284] [IGT] kms_vblank: executing
12811 04:43:43.776317 <14>[ 26.475149] [IGT] kms_vblank: exiting, ret=77
12812 04:43:43.782758 <8>[ 26.480943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12813 04:43:43.783455 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12815 04:43:43.786111 modeset-hang: SKIP (0.000s)[0m
12816 04:43:43.792825 IGT-Version: 1.<14>[ 26.494776] [IGT] kms_vblank: executing
12817 04:43:43.796237 <14>[ 26.495288] [IGT] kms_vblank: exiting, ret=77
12818 04:43:43.802980 <8>[ 26.504673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
12819 04:43:43.803753 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
12821 04:43:43.813000 27.1-g621c2d3 (aarch64) (Linux: <14>[ 26.515879] [IGT] kms_vblank: executing
12822 04:43:43.815938 <14>[ 26.516431] [IGT] kms_vblank: exiting, ret=77
12823 04:43:43.822666 <8>[ 26.522972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
12824 04:43:43.823419 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
12826 04:43:43.826254 6.1.75-cip14-rt8 aarch64)
12827 04:43:43.829569 Opene<14>[ 26.534998] [IGT] kms_vblank: executing
12828 04:43:43.836151 d device: /dev/d<14>[ 26.535501] [IGT] kms_vblank: exiting, ret=77
12829 04:43:43.846151 <8>[ 26.541590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
12830 04:43:43.846687 ri/card0
12831 04:43:43.847283 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
12833 04:43:43.852543 No KMS driver or no ou<14>[ 26.555912] [IGT] kms_vblank: executing
12834 04:43:43.855871 <14>[ 26.556397] [IGT] kms_vblank: exiting, ret=77
12835 04:43:43.862761 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
12837 04:43:43.866175 <8>[ 26.565368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
12838 04:43:43.866757 tputs, pipes: 8, outputs: 0
12839 04:43:43.872352 [1<14>[ 26.575856] [IGT] kms_vblank: executing
12840 04:43:43.875753 <14>[ 26.576339] [IGT] kms_vblank: exiting, ret=77
12841 04:43:43.885286 <8>[ 26.585762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
12842 04:43:43.886127 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
12844 04:43:43.892356 mSubtest pipe-C-ts-continuation-<14>[ 26.596201] [IGT] kms_vblank: executing
12845 04:43:43.895589 <14>[ 26.596619] [IGT] kms_vblank: exiting, ret=77
12846 04:43:43.902188 <8>[ 26.602903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
12847 04:43:43.903030 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
12849 04:43:43.905486 modeset-rpm: SKIP (0.000s)[0m
12850 04:43:43.912477 IGT-Version: 1.2<14>[ 26.614841] [IGT] kms_vblank: executing
12851 04:43:43.915664 <14>[ 26.615316] [IGT] kms_vblank: exiting, ret=77
12852 04:43:43.924955 <8>[ 26.624319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
12853 04:43:43.925712 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
12855 04:43:43.931925 7.1-g621c2d3 (aarch64) (Linux: 6<14>[ 26.635744] [IGT] kms_vblank: executing
12856 04:43:43.935322 <14>[ 26.636222] [IGT] kms_vblank: exiting, ret=77
12857 04:43:43.941630 <8>[ 26.645473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
12858 04:43:43.942494 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
12860 04:43:43.945232 .1.75-cip14-rt8 aarch64)
12861 04:43:43.952531 Opened device: /dev/dr<14>[ 26.655890] [IGT] kms_vblank: executing
12862 04:43:43.954784 <14>[ 26.656364] [IGT] kms_vblank: exiting, ret=77
12863 04:43:43.965009 <8>[ 26.662548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
12864 04:43:43.965504 i/card0
12865 04:43:43.966322 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
12867 04:43:43.971565 No KMS driver or no out<14>[ 26.675956] [IGT] kms_vblank: executing
12868 04:43:43.975105 <14>[ 26.676422] [IGT] kms_vblank: exiting, ret=77
12869 04:43:43.985222 <8>[ 26.682907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
12870 04:43:43.985748 puts, pipes: 8, outputs: 0
12871 04:43:43.986399 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
12873 04:43:43.991379 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12874 04:43:43.997992 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: <14>[ 26.705383] [IGT] kms_vblank: executing
12875 04:43:44.001610 6.1.75-cip14-rt8 aarch64)
12876 04:43:44.008016 Opened device: /dev/d<14>[ 26.710806] [IGT] kms_vblank: exiting, ret=77
12877 04:43:44.014780 <8>[ 26.715468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
12878 04:43:44.015213 ri/card0
12879 04:43:44.015803 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
12881 04:43:44.021411 No KMS driver or no outputs, pipes: 8, outputs: 0
12882 04:43:44.024815 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12883 04:43:44.031539 IGT-Version: 1.27<14>[ 26.735804] [IGT] kms_vblank: executing
12884 04:43:44.038323 .1-g621c2d3 (aar<14>[ 26.736616] [IGT] kms_vblank: exiting, ret=77
12885 04:43:44.044732 <8>[ 26.741905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
12886 04:43:44.045490 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
12888 04:43:44.048324 ch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12889 04:43:44.051316 Opened device: /dev/dri/card0
12890 04:43:44.058320 No KMS driver or no outputs, pipes: 8, o<14>[ 26.762500] [IGT] kms_vblank: executing
12891 04:43:44.064828 <14>[ 26.763283] [IGT] kms_vblank: exiting, ret=77
12892 04:43:44.071103 <8>[ 26.768608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
12893 04:43:44.071954 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
12895 04:43:44.074523 utputs: 0
12896 04:43:44.078278 [1mSubtest pipe-D-qu<14>[ 26.783277] [IGT] kms_vblank: executing
12897 04:43:44.084635 <14>[ 26.783752] [IGT] kms_vblank: exiting, ret=77
12898 04:43:44.091188 <8>[ 26.791041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
12899 04:43:44.092033 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
12901 04:43:44.097407 ery-idle-hang: SKIP (0.000s)[0m<14>[ 26.803441] [IGT] kms_vblank: executing
12902 04:43:44.104242 <14>[ 26.803934] [IGT] kms_vblank: exiting, ret=77
12903 04:43:44.111151 <8>[ 26.813120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
12904 04:43:44.111993 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
12906 04:43:44.113887
12907 04:43:44.117669 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12908 04:43:44.120392 Opened device: /dev/dri/card0
12909 04:43:44.127248 No KMS driver or no outputs, pipes: 8, outputs: 0
12910 04:43:44.130818 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
12911 04:43:44.136984 IGT-Version: 1<14>[ 26.837648] [IGT] kms_vblank: executing
12912 04:43:44.140672 <14>[ 26.838545] [IGT] kms_vblank: exiting, ret=77
12913 04:43:44.150131 <8>[ 26.848426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
12914 04:43:44.151140 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
12916 04:43:44.153648 .27.1-g621c2d3 (<14>[ 26.860620] [IGT] kms_vblank: executing
12917 04:43:44.160502 <14>[ 26.861089] [IGT] kms_vblank: exiting, ret=77
12918 04:43:44.166795 <8>[ 26.866334] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
12919 04:43:44.167741 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
12921 04:43:44.177227 aarch64) (Linux: 6.1.75-cip14-rt<14>[ 26.879935] [IGT] kms_vblank: executing
12922 04:43:44.180480 <14>[ 26.880423] [IGT] kms_vblank: exiting, ret=77
12923 04:43:44.190033 <8>[ 26.886946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
12924 04:43:44.190694 8 aarch64)
12925 04:43:44.191467 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
12927 04:43:44.193719 Opened device: /dev/dri/card0
12928 04:43:44.196783 No KMS driver or no outputs, pipes: 8, outputs: 0
12929 04:43:44.203664 [1mSubtest pipe-D<14>[ 26.909267] [IGT] kms_vblank: executing
12930 04:43:44.206877 -query-forked-hang: SKIP (0.000s)[0m
12931 04:43:44.210043 IGT-Versi<14>[ 26.914511] [IGT] kms_vblank: exiting, ret=77
12932 04:43:44.219905 <8>[ 26.919183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
12933 04:43:44.220785 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
12935 04:43:44.226596 on: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12936 04:43:44.229923 Opened device: /dev/dri/card0
12937 04:43:44.236128 No KMS driver or no outputs, pip<14>[ 26.941512] [IGT] kms_vblank: executing
12938 04:43:44.236765 es: 8, outputs: 0
12939 04:43:44.243034 [1mSubtest pipe-D-query-busy<14>[ 26.947537] [IGT] kms_vblank: exiting, ret=77
12940 04:43:44.252996 : SKIP (0.000s)<8>[ 26.952472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
12941 04:43:44.253687 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
12943 04:43:44.256239 [0m
12944 04:43:44.263014 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Lin<14>[ 26.966156] [IGT] kms_vblank: executing
12945 04:43:44.266244 <14>[ 26.966652] [IGT] kms_vblank: exiting, ret=77
12946 04:43:44.276171 <8>[ 26.970975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
12947 04:43:44.276987 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
12949 04:43:44.279488 ux: 6.1.75-cip14-rt8 aarch64)
12950 04:43:44.282470 O<14>[ 26.988145] [IGT] kms_vblank: executing
12951 04:43:44.286063 pened device: /dev/dri/card0
12952 04:43:44.289093 No KMS driver or no outputs, pipes: 8, outputs: 0
12953 04:43:44.295777 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
12954 04:43:44.302537 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12955 04:43:44.305633 Opened device: /dev/dri/card0
12956 04:43:44.309064 No KMS driver or no outputs, pipes: 8, outputs: 0
12957 04:43:44.312192 [1mSubtest pipe-D-query-forked-busy: SKIP (0.000s)[0m
12958 04:43:44.318636 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12959 04:43:44.322217 Opened device: /dev/dri/card0
12960 04:43:44.328970 No KMS driver or no outputs, pipes: 8, outputs: 0
12961 04:43:44.332418 [1mSubtest pipe-D-query-forked-busy-hang: SKIP (0.000s)[0m
12962 04:43:44.338824 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12963 04:43:44.342209 Opened device: /dev/dri/card0
12964 04:43:44.345322 No KMS driver or no outputs, pipes: 8, outputs: 0
12965 04:43:44.352113 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
12966 04:43:44.355592 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12967 04:43:44.359099 Opened device: /dev/dri/card0
12968 04:43:44.365673 No KMS driver or no outputs, pipes: 8, outputs: 0
12969 04:43:44.368951 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
12970 04:43:44.375084 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12971 04:43:44.378750 Opened device: /dev/dri/card0
12972 04:43:44.381658 No KMS driver or no outputs, pipes: 8, outputs: 0
12973 04:43:44.385299 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
12974 04:43:44.391902 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12975 04:43:44.395014 Opened device: /dev/dri/card0
12976 04:43:44.401611 No KMS driver or no outputs, pipes: 8, outputs: 0
12977 04:43:44.405537 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
12978 04:43:44.411560 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12979 04:43:44.414767 Opened device: /dev/dri/card0
12980 04:43:44.418551 No KMS driver or no outputs, pipes: 8, outputs: 0
12981 04:43:44.421734 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
12982 04:43:44.428019 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12983 04:43:44.431496 Opened device: /dev/dri/card0
12984 04:43:44.434974 No KMS driver or no outputs, pipes: 8, outputs: 0
12985 04:43:44.441417 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
12986 04:43:44.447869 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12987 04:43:44.451579 Opened device: /dev/dri/card0
12988 04:43:44.454420 No KMS driver or no outputs, pipes: 8, outputs: 0
12989 04:43:44.458044 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
12990 04:43:44.464379 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12991 04:43:44.467480 Opened device: /dev/dri/card0
12992 04:43:44.474303 No KMS driver or no outputs, pipes: 8, outputs: 0
12993 04:43:44.477544 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
12994 04:43:44.483943 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12995 04:43:44.487455 Opened device: /dev/dri/card0
12996 04:43:44.490791 No KMS driver or no outputs, pipes: 8, outputs: 0
12997 04:43:44.497502 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0m
12998 04:43:44.504238 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
12999 04:43:44.507426 Opened device: /dev/dri/card0
13000 04:43:44.510668 No KMS driver or no outputs, pipes: 8, outputs: 0
13001 04:43:44.517042 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
13002 04:43:44.523649 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13003 04:43:44.523733 Opened device: /dev/dri/card0
13004 04:43:44.530209 No KMS driver or no outputs, pipes: 8, outputs: 0
13005 04:43:44.533802 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13006 04:43:44.540292 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13007 04:43:44.543582 Opened device: /dev/dri/card0
13008 04:43:44.550581 No KMS driver or no outputs, pipes: 8, outputs: 0
13009 04:43:44.553663 [1mSubtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13010 04:43:44.560176 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13011 04:43:44.563568 Opened device: /dev/dri/card0
13012 04:43:44.566718 No KMS driver or no outputs, pipes: 8, outputs: 0
13013 04:43:44.573809 [1mSubtest pipe-D-ts-continuation-suspend: SKIP (0.000s)[0m
13014 04:43:44.580257 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13015 04:43:44.583667 Opened device: /dev/dri/card0
13016 04:43:44.587013 No KMS driver or no outputs, pipes: 8, outputs: 0
13017 04:43:44.593329 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s)[0m
13018 04:43:44.600195 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13019 04:43:44.603958 Opened device: /dev/dri/card0
13020 04:43:44.606755 No KMS driver or no outputs, pipes: 8, outputs: 0
13021 04:43:44.613895 [1mSubtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13022 04:43:44.623753 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarc<14>[ 27.326475] [IGT] kms_vblank: exiting, ret=77
13023 04:43:44.630565 <8>[ 27.332853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
13024 04:43:44.631151 h64)
13025 04:43:44.631827 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13027 04:43:44.633368 Opened device: /dev/dri/card0
13028 04:43:44.637160 No KMS driver or no outputs, pipes: 8, outputs: 0
13029 04:43:44.644102 [1mSubtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13030 04:43:44.650614 IGT-Version: 1.27.1-g621c2d3 (aarch64<14>[ 27.355227] [IGT] kms_vblank: executing
13031 04:43:44.657315 <14>[ 27.355998] [IGT] kms_vblank: exiting, ret=77
13032 04:43:44.663505 <8>[ 27.361080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
13033 04:43:44.664386 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13035 04:43:44.670291 ) (Linux: 6.1.75-cip14-rt8 aarch<14>[ 27.375269] [IGT] kms_vblank: executing
13036 04:43:44.676521 <14>[ 27.375741] [IGT] kms_vblank: exiting, ret=77
13037 04:43:44.683295 <8>[ 27.381930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
13038 04:43:44.683860 64)
13039 04:43:44.684512 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13041 04:43:44.686566 Opened device: /dev/dri/card0
13042 04:43:44.693218 No KMS drive<14>[ 27.394873] [IGT] kms_vblank: executing
13043 04:43:44.696389 <14>[ 27.395422] [IGT] kms_vblank: exiting, ret=77
13044 04:43:44.703089 <8>[ 27.402425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
13045 04:43:44.703821 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13047 04:43:44.710135 r or no outputs, pipes: 8, outpu<14>[ 27.415519] [IGT] kms_vblank: executing
13048 04:43:44.716600 <14>[ 27.416080] [IGT] kms_vblank: exiting, ret=77
13049 04:43:44.723557 <8>[ 27.420688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
13050 04:43:44.724132 ts: 0
13051 04:43:44.724776 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13053 04:43:44.729620 [1mSubtest pipe-E-accuracy-idle: SKIP (0.000s)[0m
13054 04:43:44.739824 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarc<14>[ 27.443850] [IGT] kms_vblank: executing
13055 04:43:44.740459 h64)
13056 04:43:44.746161 Opened dev<14>[ 27.444691] [IGT] kms_vblank: exiting, ret=77
13057 04:43:44.752603 <8>[ 27.450203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
13058 04:43:44.753201 ice: /dev/dri/card0
13059 04:43:44.753839 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13061 04:43:44.759326 No KMS driver or no outputs, pipes: 8, outputs: 0
13062 04:43:44.766010 [1mSubtest pipe-E-query-idle: SKIP (0.0<14>[ 27.470244] [IGT] kms_vblank: executing
13063 04:43:44.772711 <14>[ 27.471021] [IGT] kms_vblank: exiting, ret=77
13064 04:43:44.779368 <8>[ 27.476366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
13065 04:43:44.779856 00s)[0m
13066 04:43:44.780607 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13068 04:43:44.786243 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13069 04:43:44.792713 Opened devic<14>[ 27.496811] [IGT] kms_vblank: executing
13070 04:43:44.793381 e: /dev/dri/card0
13071 04:43:44.799173 No KMS driver<14>[ 27.503325] [IGT] kms_vblank: exiting, ret=77
13072 04:43:44.806076 <8>[ 27.508332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
13073 04:43:44.806938 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13075 04:43:44.809140 or no outputs, pipes: 8, outputs: 0
13076 04:43:44.815971 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
13077 04:43:44.822323 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13078 04:43:44.825800 Opened device: /dev/dri/card0
13079 04:43:44.832322 No KMS driver or no output<14>[ 27.536057] [IGT] kms_vblank: executing
13080 04:43:44.835902 <14>[ 27.536908] [IGT] kms_vblank: exiting, ret=77
13081 04:43:44.842578 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13083 04:43:44.845679 <8>[ 27.543119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
13084 04:43:44.846312 s, pipes: 8, outputs: 0
13085 04:43:44.851945 [1mSub<14>[ 27.555715] [IGT] kms_vblank: executing
13086 04:43:44.855637 <14>[ 27.556281] [IGT] kms_vblank: exiting, ret=77
13087 04:43:44.862117 <8>[ 27.566212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
13088 04:43:44.862980 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13090 04:43:44.865099 test pipe-E-query-forked: SKIP (0.000s)[0m
13091 04:43:44.875052 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.<14>[ 27.578446] [IGT] kms_vblank: executing
13092 04:43:44.878430 <14>[ 27.579010] [IGT] kms_vblank: exiting, ret=77
13093 04:43:44.888400 <8>[ 27.585826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
13094 04:43:44.889037 75-cip14-rt8 aarch64)
13095 04:43:44.889703 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13097 04:43:44.895100 Opened de<14>[ 27.599440] [IGT] kms_vblank: executing
13098 04:43:44.898371 <14>[ 27.600002] [IGT] kms_vblank: exiting, ret=77
13099 04:43:44.908159 <8>[ 27.606792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
13100 04:43:44.908824 vice: /dev/dri/card0
13101 04:43:44.909718 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13103 04:43:44.914650 No KMS driver or no outputs, pipes: 8, outputs: 0
13104 04:43:44.918031 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
13105 04:43:44.927844 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux:<14>[ 27.632945] [IGT] kms_vblank: executing
13106 04:43:44.928487 6.1.75-cip14-rt8 aarch64)
13107 04:43:44.934756 Opened device: /dev/<14>[ 27.638414] [IGT] kms_vblank: exiting, ret=77
13108 04:43:44.944757 <8>[ 27.643825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
13109 04:43:44.945396 dri/card0
13110 04:43:44.946205 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13112 04:43:44.948013 No KMS driver or no outputs, pipes: 8, outputs: 0
13113 04:43:44.954656 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
13114 04:43:44.957688 IGT-Version: 1.2<14>[ 27.664679] [IGT] kms_vblank: executing
13115 04:43:44.964606 <14>[ 27.665442] [IGT] kms_vblank: exiting, ret=77
13116 04:43:44.967544 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13117 04:43:44.977439 Opened device: /dev/dr<8>[ 27.679853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
13118 04:43:44.978011 i/card0
13119 04:43:44.978613 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13121 04:43:44.984458 No KMS driver or no outputs, pipes: 8, outputs: 0
13122 04:43:44.987392 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
13123 04:43:44.994166 IGT-Version: 1.27.1-g621c2d3 <14>[ 27.700569] [IGT] kms_vblank: executing
13124 04:43:44.997785 <14>[ 27.701367] [IGT] kms_vblank: exiting, ret=77
13125 04:43:45.004053 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13126 04:43:45.004546 Opened device: /dev/dri/card0
13127 04:43:45.014221 No KMS driver or no <8>[ 27.716047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
13128 04:43:45.014916 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13130 04:43:45.017547 outputs, pipes: 8, outputs: 0
13131 04:43:45.024184 [1mSubtest pipe-<14>[ 27.728741] [IGT] kms_vblank: executing
13132 04:43:45.027250 <14>[ 27.729321] [IGT] kms_vblank: exiting, ret=77
13133 04:43:45.037074 <8>[ 27.734641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
13134 04:43:45.037767 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13136 04:43:45.043741 E-query-forked-busy: SKIP (0.000<14>[ 27.747840] [IGT] kms_vblank: executing
13137 04:43:45.047394 <14>[ 27.748418] [IGT] kms_vblank: exiting, ret=77
13138 04:43:45.057445 <8>[ 27.755569] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
13139 04:43:45.057870 s)[0m
13140 04:43:45.058447 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13142 04:43:45.063956 IGT-Version: 1.27.1-g621<14>[ 27.768264] [IGT] kms_vblank: executing
13143 04:43:45.066932 <14>[ 27.768801] [IGT] kms_vblank: exiting, ret=77
13144 04:43:45.076721 <8>[ 27.775652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
13145 04:43:45.077007 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13147 04:43:45.083338 c2d3 (aarch64) (Linux: 6.1.75-ci<14>[ 27.788069] [IGT] kms_vblank: executing
13148 04:43:45.086652 <14>[ 27.788634] [IGT] kms_vblank: exiting, ret=77
13149 04:43:45.096908 <8>[ 27.795742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
13150 04:43:45.097219 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13152 04:43:45.103214 p14-rt8 aarch64)<14>[ 27.808286] [IGT] kms_vblank: executing
13153 04:43:45.106777 <14>[ 27.808827] [IGT] kms_vblank: exiting, ret=77
13154 04:43:45.116583 <8>[ 27.815594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
13155 04:43:45.116781
13156 04:43:45.116920 Opened device: /dev/dri/card0
13157 04:43:45.117211 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13159 04:43:45.123058 No KMS driver or no outputs, pipes: 8, outputs: 0
13160 04:43:45.126690 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
13161 04:43:45.133018 IGT-Version: 1.27.1-g621c2d3 (<14>[ 27.838613] [IGT] kms_vblank: executing
13162 04:43:45.139863 <14>[ 27.839493] [IGT] kms_vblank: exiting, ret=77
13163 04:43:45.146697 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13165 04:43:45.149986 <8>[ 27.845055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
13166 04:43:45.153256 aarch64) (Linux:<14>[ 27.860373] [IGT] kms_vblank: executing
13167 04:43:45.159758 <14>[ 27.860875] [IGT] kms_vblank: exiting, ret=77
13168 04:43:45.159992 6.1.75-cip14-rt8 aarch64)
13169 04:43:45.170000 Opened device: /dev/<8>[ 27.870658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13170 04:43:45.170540 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13172 04:43:45.173500 dri/card0
13173 04:43:45.180035 No KMS driver or no o<14>[ 27.883429] [IGT] kms_vblank: executing
13174 04:43:45.183112 <14>[ 27.883970] [IGT] kms_vblank: exiting, ret=77
13175 04:43:45.193059 <8>[ 27.890603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13176 04:43:45.193488 utputs, pipes: 8, outputs: 0
13177 04:43:45.194056 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13179 04:43:45.199827 [<14>[ 27.903653] [IGT] kms_vblank: executing
13180 04:43:45.203332 <14>[ 27.904165] [IGT] kms_vblank: exiting, ret=77
13181 04:43:45.213014 <8>[ 27.910484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13182 04:43:45.213691 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13184 04:43:45.216559 1mSubtest pipe-E<14>[ 27.924323] [IGT] kms_vblank: executing
13185 04:43:45.223148 <14>[ 27.924795] [IGT] kms_vblank: exiting, ret=77
13186 04:43:45.230501 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13188 04:43:45.233150 <8>[ 27.930241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13189 04:43:45.233586 -wait-idle: SKIP (0.000s)[0m
13190 04:43:45.239664 I<14>[ 27.943529] [IGT] kms_vblank: executing
13191 04:43:45.242724 <14>[ 27.944011] [IGT] kms_vblank: exiting, ret=77
13192 04:43:45.249736 <8>[ 27.948208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13193 04:43:45.249974 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13195 04:43:45.256315 GT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13196 04:43:45.259817 Opened device: /dev/dri/card0
13197 04:43:45.266174 No KMS driver or no outp<14>[ 27.971006] [IGT] kms_vblank: executing
13198 04:43:45.269998 <14>[ 27.971877] [IGT] kms_vblank: exiting, ret=77
13199 04:43:45.280069 <8>[ 27.977190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13200 04:43:45.280266 uts, pipes: 8, outputs: 0
13201 04:43:45.280552 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13203 04:43:45.286479 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
13204 04:43:45.289829 IGT-Version: 1.<14>[ 27.996246] [IGT] kms_vblank: executing
13205 04:43:45.295897 27.1-g621c2d3 (a<14>[ 27.997118] [IGT] kms_vblank: exiting, ret=77
13206 04:43:45.306363 <8>[ 28.002493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13207 04:43:45.306872 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13209 04:43:45.309403 arch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13210 04:43:45.312457 Opened device: /dev/dri/card0
13211 04:43:45.319362 No KMS driver or no outputs, pipes: 8,<14>[ 28.022315] [IGT] kms_vblank: executing
13212 04:43:45.322849 <14>[ 28.023091] [IGT] kms_vblank: exiting, ret=77
13213 04:43:45.332855 <8>[ 28.028076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13214 04:43:45.333443 outputs: 0
13215 04:43:45.334185 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13217 04:43:45.335858 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
13218 04:43:45.342471 IGT-Version: 1.2<14>[ 28.048890] [IGT] kms_vblank: executing
13219 04:43:45.352681 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 <14>[ 28.054298] [IGT] kms_vblank: exiting, ret=77
13220 04:43:45.359004 <8>[ 28.059426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13221 04:43:45.359451 aarch64)
13222 04:43:45.360044 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13224 04:43:45.362434 Opened device: /dev/dri/card0
13225 04:43:45.369328 No KMS <14>[ 28.070995] [IGT] kms_vblank: executing
13226 04:43:45.372407 <14>[ 28.071475] [IGT] kms_vblank: exiting, ret=77
13227 04:43:45.381933 driver or no out<8>[ 28.078568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13228 04:43:45.382660 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13230 04:43:45.385054 puts, pipes: 8, <14>[ 28.092955] [IGT] kms_vblank: executing
13231 04:43:45.388618 outputs: 0
13232 04:43:45.391650 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
13233 04:43:45.398555 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13234 04:43:45.401750 Opened device: /dev/dri/card0
13235 04:43:45.405260 No KMS driver or no outputs, pipes: 8, outputs: 0
13236 04:43:45.411775 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
13237 04:43:45.418304 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13238 04:43:45.418409 Opened device: /dev/dri/card0
13239 04:43:45.425226 No KMS driver or no outputs, pipes: 8, outputs: 0
13240 04:43:45.428214 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
13241 04:43:45.434917 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13242 04:43:45.438662 Opened device: /dev/dri/card0
13243 04:43:45.441646 No KMS driver or no outputs, pipes: 8, outputs: 0
13244 04:43:45.448219 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
13245 04:43:45.454677 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13246 04:43:45.454988 Opened device: /dev/dri/card0
13247 04:43:45.461596 No KMS driver or no outputs, pipes: 8, outputs: 0
13248 04:43:45.465097 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
13249 04:43:45.471642 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13250 04:43:45.475092 Opened device: /dev/dri/card0
13251 04:43:45.478622 No KMS driver or no outputs, pipes: 8, outputs: 0
13252 04:43:45.485127 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0m
13253 04:43:45.491766 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13254 04:43:45.495131 Opened device: /dev/dri/card0
13255 04:43:45.498039 No KMS driver or no outputs, pipes: 8, outputs: 0
13256 04:43:45.504602 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
13257 04:43:45.511184 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13258 04:43:45.514512 Opened device: /dev/dri/card0
13259 04:43:45.517725 No KMS driver or no outputs, pipes: 8, outputs: 0
13260 04:43:45.524189 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13261 04:43:45.531158 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13262 04:43:45.531614 Opened device: /dev/dri/card0
13263 04:43:45.537682 No KMS driver or no outputs, pipes: 8, outputs: 0
13264 04:43:45.544496 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13265 04:43:45.547422 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13266 04:43:45.551185 Opened device: /dev/dri/card0
13267 04:43:45.557278 No KMS driver or no outputs, pipes: 8, outputs: 0
13268 04:43:45.560695 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13269 04:43:45.567336 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13270 04:43:45.570821 Opened device: /dev/dri/card0
13271 04:43:45.573655 No KMS driver or no outputs, pipes: 8, outputs: 0
13272 04:43:45.580870 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13273 04:43:45.587484 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13274 04:43:45.590901 Opened device: /dev/dri/card0
13275 04:43:45.594023 No KMS driver or no outputs, pipes: 8, outputs: 0
13276 04:43:45.600616 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13277 04:43:45.607176 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13278 04:43:45.610311 Opened device: /dev/dri/card0
13279 04:43:45.613746 No KMS driver or no outputs, pipes: 8, outputs: 0
13280 04:43:45.620582 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13281 04:43:45.627131 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13282 04:43:45.627688 Opened device: /dev/dri/card0
13283 04:43:45.633902 No KMS driver or no outputs, pipes: 8, outputs: 0
13284 04:43:45.637335 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13285 04:43:45.643589 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13286 04:43:45.647103 Opened device: /dev/dri/card0
13287 04:43:45.650196 No KMS driver or no outputs, pipes: 8, outputs: 0
13288 04:43:45.656786 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13289 04:43:45.663657 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13290 04:43:45.664227 Opened device: /dev/dri/card0
13291 04:43:45.669977 No KMS driver or no outputs, pipes: 8, outputs: 0
13292 04:43:45.673378 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13293 04:43:45.680144 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13294 04:43:45.683060 Opened device: /dev/dri/card0
13295 04:43:45.686552 No KMS driver or no outputs, pipes: 8, outputs: 0
13296 04:43:45.693400 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13297 04:43:45.699871 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13298 04:43:45.700456 Opened device: /dev/dri/card0
13299 04:43:45.706342 No KMS driver or no outputs, pipes: 8, outputs: 0
13300 04:43:45.709388 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13301 04:43:45.716511 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13302 04:43:45.719535 Opened device: /dev/dri/card0
13303 04:43:45.729824 No KMS driver or no outputs, pipes: 8, out<14>[ 28.430803] [IGT] kms_vblank: exiting, ret=77
13304 04:43:45.736205 <8>[ 28.437524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13305 04:43:45.736773 puts: 0
13306 04:43:45.737442 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13308 04:43:45.739305 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13309 04:43:45.746165 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13310 04:43:45.749504 Opened device: /dev/dri/card0
13311 04:43:45.755830 No KMS drive<14>[ 28.459469] [IGT] kms_vblank: executing
13312 04:43:45.759102 <14>[ 28.460286] [IGT] kms_vblank: exiting, ret=77
13313 04:43:45.769025 <8>[ 28.465830] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13314 04:43:45.769882 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13316 04:43:45.772222 r or no outputs, pipes: 8, outputs: 0
13317 04:43:45.775487 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13318 04:43:45.782338 IGT-Version: 1.27.1-g621c2d3 (aarc<14>[ 28.486236] [IGT] kms_vblank: executing
13319 04:43:45.788761 <14>[ 28.487078] [IGT] kms_vblank: exiting, ret=77
13320 04:43:45.795874 <8>[ 28.492766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13321 04:43:45.796719 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13323 04:43:45.798595 h64) (Linux: 6.1.75-cip14-rt8 aarch64)
13324 04:43:45.802426 Opened device: /dev/dri/card0
13325 04:43:45.809047 No KMS driver or no outputs, pipes: 8, ou<14>[ 28.515215] [IGT] kms_vblank: executing
13326 04:43:45.811940 tputs: 0
13327 04:43:45.815648 [1mSu<14>[ 28.516087] [IGT] kms_vblank: exiting, ret=77
13328 04:43:45.822179 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13330 04:43:45.825116 <8>[ 28.521556] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13331 04:43:45.828735 btest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13332 04:43:45.835620 IGT-Version: 1.27.1-g621c2d3 <14>[ 28.541330] [IGT] kms_vblank: executing
13333 04:43:45.838667 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13334 04:43:45.845167 Ope<14>[ 28.547013] [IGT] kms_vblank: exiting, ret=77
13335 04:43:45.852124 <8>[ 28.551729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13336 04:43:45.852973 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13338 04:43:45.855525 ned device: /dev/dri/card0
13339 04:43:45.858544 No K<14>[ 28.563871] [IGT] kms_vblank: executing
13340 04:43:45.861892 <14>[ 28.564425] [IGT] kms_vblank: exiting, ret=77
13341 04:43:45.871936 <8>[ 28.569784] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13342 04:43:45.872803 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13344 04:43:45.874602 MS driver or no outputs, pipes: 8, outputs: 0
13345 04:43:45.877837 <14>[ 28.582337] [IGT] kms_vblank: executing
13346 04:43:45.884941 <14>[ 28.582880] [IGT] kms_vblank: exiting, ret=77
13347 04:43:45.891550 <8>[ 28.589199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13348 04:43:45.892394 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13350 04:43:45.898400 [1mSubtest pipe-F-query-forked-b<14>[ 28.603406] [IGT] kms_vblank: executing
13351 04:43:45.904988 <14>[ 28.603917] [IGT] kms_vblank: exiting, ret=77
13352 04:43:45.911726 <8>[ 28.610940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13353 04:43:45.912749 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13355 04:43:45.915059 usy-hang: SKIP (0.000s)[0m
13356 04:43:45.921531 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13357 04:43:45.922146 Opened device: /dev/dri/card0
13358 04:43:45.927810 No KMS driver or no outputs, pipes: 8, outputs: 0
13359 04:43:45.931484 [1mSub<14>[ 28.636777] [IGT] kms_vblank: executing
13360 04:43:45.938205 <14>[ 28.637721] [IGT] kms_vblank: exiting, ret=77
13361 04:43:45.941658 test pipe-F-wait-idle: SKIP (0.000s)[0m
13362 04:43:45.951622 IGT-Version: 1.27.1-g621c2d3 (aarch64)<8>[ 28.653203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13363 04:43:45.952480 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13365 04:43:45.954283 (Linux: 6.1.75-cip14-rt8 aarch64)
13366 04:43:45.958149 Opened device: /dev/dri/card0
13367 04:43:45.961599 No KMS driver or no outputs, pipes: 8, outputs: 0
13368 04:43:45.964506 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13369 04:43:45.970866 IGT-<14>[ 28.675902] [IGT] kms_vblank: executing
13370 04:43:45.974510 <14>[ 28.676786] [IGT] kms_vblank: exiting, ret=77
13371 04:43:45.984444 <8>[ 28.682269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13372 04:43:45.985282 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13374 04:43:45.990796 Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13375 04:43:45.991258 Opened device: /dev/dri/card0
13376 04:43:45.997891 No KMS driver or no outputs<14>[ 28.702592] [IGT] kms_vblank: executing
13377 04:43:46.004270 <14>[ 28.703359] [IGT] kms_vblank: exiting, ret=77
13378 04:43:46.010743 <8>[ 28.708643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13379 04:43:46.011483 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13381 04:43:46.014060 , pipes: 8, outputs: 0
13382 04:43:46.017310 [1mSubtest pipe-F-wait-forked: SKIP (0.000s)[0m
13383 04:43:46.024554 IGT-V<14>[ 28.729336] [IGT] kms_vblank: executing
13384 04:43:46.030764 ersion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75<14>[ 28.734946] [IGT] kms_vblank: exiting, ret=77
13385 04:43:46.040633 <8>[ 28.741527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13386 04:43:46.041262 -cip14-rt8 aarch64)
13387 04:43:46.041913 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13389 04:43:46.047687 Opened devi<14>[ 28.752129] [IGT] kms_vblank: executing
13390 04:43:46.050376 <14>[ 28.752664] [IGT] kms_vblank: exiting, ret=77
13391 04:43:46.060819 <8>[ 28.759637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13392 04:43:46.061387 ce: /dev/dri/card0
13393 04:43:46.062039 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13395 04:43:46.067424 No KMS drive<14>[ 28.772027] [IGT] kms_vblank: executing
13396 04:43:46.070157 <14>[ 28.772553] [IGT] kms_vblank: exiting, ret=77
13397 04:43:46.080172 <8>[ 28.779515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13398 04:43:46.081019 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13400 04:43:46.086850 r or no outputs,<14>[ 28.792307] [IGT] kms_vblank: executing
13401 04:43:46.090125 <14>[ 28.792814] [IGT] kms_vblank: exiting, ret=77
13402 04:43:46.099886 <8>[ 28.799603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13403 04:43:46.100744 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13405 04:43:46.103284 pipes: 8, outputs: 0
13406 04:43:46.106740 [1mSubtest pipe-F-wait-forked-hang: SKIP (0.000s)[0m
13407 04:43:46.113397 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13408 04:43:46.120086 Opened device: /dev/dri<14>[ 28.825003] [IGT] kms_vblank: executing
13409 04:43:46.120659 /card0
13410 04:43:46.126737 No KMS driver or no outp<14>[ 28.831210] [IGT] kms_vblank: exiting, ret=77
13411 04:43:46.136918 <8>[ 28.837010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13412 04:43:46.137485 uts, pipes: 8, outputs: 0
13413 04:43:46.138123 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13415 04:43:46.143228 [1mS<14>[ 28.847926] [IGT] kms_vblank: executing
13416 04:43:46.146768 <14>[ 28.848419] [IGT] kms_vblank: exiting, ret=77
13417 04:43:46.156571 <8>[ 28.853437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13418 04:43:46.157417 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13420 04:43:46.163197 ubtest pipe-F-wait-busy: SKIP (0<14>[ 28.867340] [IGT] kms_vblank: executing
13421 04:43:46.166576 <14>[ 28.867867] [IGT] kms_vblank: exiting, ret=77
13422 04:43:46.176742 <8>[ 28.872995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13423 04:43:46.177307 .000s)[0m
13424 04:43:46.178027 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13426 04:43:46.183032 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13427 04:43:46.190032 Opened device: /dev/dri/ca<14>[ 28.895438] [IGT] kms_vblank: executing
13428 04:43:46.196387 <14>[ 28.896240] [IGT] kms_vblank: exiting, ret=77
13429 04:43:46.203124 <8>[ 28.901662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13430 04:43:46.203594 rd0
13431 04:43:46.204224 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13433 04:43:46.209531 No KMS driver or no outputs, pipes: 8, outputs: 0
13434 04:43:46.213121 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13435 04:43:46.219675 IGT-Version: 1.27.<14>[ 28.921914] [IGT] kms_vblank: executing
13436 04:43:46.222663 <14>[ 28.922701] [IGT] kms_vblank: exiting, ret=77
13437 04:43:46.233360 <8>[ 28.927638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13438 04:43:46.234197 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13440 04:43:46.235917 1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13441 04:43:46.239525 Opened device: /dev/dri/card0
13442 04:43:46.242981 No KMS driver or no outputs, pipes: 8, outputs: 0
13443 04:43:46.249669 [1mSubtest pipe-F-wait-forked-busy: S<14>[ 28.956185] [IGT] kms_vblank: executing
13444 04:43:46.255846 <14>[ 28.956987] [IGT] kms_vblank: exiting, ret=77
13445 04:43:46.262787 <8>[ 28.962640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13446 04:43:46.263651 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13448 04:43:46.266003 KIP (0.000s)[0m
13449 04:43:46.272538 IGT-Version: 1.27.1-g621c2d3 (<14>[ 28.974744] [IGT] kms_vblank: executing
13450 04:43:46.275790 <14>[ 28.975191] [IGT] kms_vblank: exiting, ret=77
13451 04:43:46.282537 <8>[ 28.979515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13452 04:43:46.283371 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13454 04:43:46.288814 aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13455 04:43:46.289380 Opened device: /dev/dri/card0
13456 04:43:46.295695 No KMS driver or no outputs, pipes: 8, outputs: 0
13457 04:43:46.302489 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.<14>[ 29.006739] [IGT] kms_vblank: executing
13458 04:43:46.308824 <14>[ 29.007527] [IGT] kms_vblank: exiting, ret=77
13459 04:43:46.315668 <8>[ 29.013405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13460 04:43:46.316237 000s)[0m
13461 04:43:46.316888 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13463 04:43:46.322465 IGT-Version: 1.27.1-g<14>[ 29.027418] [IGT] kms_vblank: executing
13464 04:43:46.329210 <14>[ 29.027901] [IGT] kms_vblank: exiting, ret=77
13465 04:43:46.335409 <8>[ 29.037249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13466 04:43:46.336244 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13468 04:43:46.342350 621c2d3 (aarch64) (Linux: 6.1.75<14>[ 29.047614] [IGT] kms_vblank: executing
13469 04:43:46.348625 <14>[ 29.048084] [IGT] kms_vblank: exiting, ret=77
13470 04:43:46.355301 <8>[ 29.057930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13471 04:43:46.355951 -cip14-rt8 aarch64)
13472 04:43:46.356758 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13474 04:43:46.361599 Opened device: /dev/dri/car<14>[ 29.068335] [IGT] kms_vblank: executing
13475 04:43:46.368260 <14>[ 29.068776] [IGT] kms_vblank: exiting, ret=77
13476 04:43:46.375071 <8>[ 29.074228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13477 04:43:46.375634 d0
13478 04:43:46.376267 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13480 04:43:46.382084 No KMS driver or no outputs,<14>[ 29.087168] [IGT] kms_vblank: executing
13481 04:43:46.388246 <14>[ 29.087658] [IGT] kms_vblank: exiting, ret=77
13482 04:43:46.394955 <8>[ 29.094278] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13483 04:43:46.395802 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13485 04:43:46.398483 pipes: 8, outputs: 0
13486 04:43:46.401753 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13487 04:43:46.408124 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13488 04:43:46.411503 Opened device: /dev/dri/card0
13489 04:43:46.418021 No KMS driver or no outputs, pipes: <14>[ 29.121742] [IGT] kms_vblank: executing
13490 04:43:46.424325 <14>[ 29.122611] [IGT] kms_vblank: exiting, ret=77
13491 04:43:46.431382 <8>[ 29.128291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13492 04:43:46.432136 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13494 04:43:46.434574 8, outputs: 0
13495 04:43:46.437851 [1mSubtest pipe-<14>[ 29.143664] [IGT] kms_vblank: executing
13496 04:43:46.444745 <14>[ 29.144155] [IGT] kms_vblank: exiting, ret=77
13497 04:43:46.451017 <8>[ 29.153715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13498 04:43:46.451747 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13500 04:43:46.454384 F-ts-continuation-idle-hang: SKIP (0.000s)[0m
13501 04:43:46.458253 <14>[ 29.163734] [IGT] kms_vblank: executing
13502 04:43:46.464993 IGT-Version: 1.2<14>[ 29.164210] [IGT] kms_vblank: exiting, ret=77
13503 04:43:46.471980 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13505 04:43:46.474683 <8>[ 29.170463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13506 04:43:46.478357 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13507 04:43:46.481668 Opened device: /dev/dri/card0
13508 04:43:46.485023 No KMS driver or no outputs, pipes: 8, outputs: 0
13509 04:43:46.491438 [1mSubtest pipe-F-t<14>[ 29.196241] [IGT] kms_vblank: executing
13510 04:43:46.494908 <14>[ 29.197064] [IGT] kms_vblank: exiting, ret=77
13511 04:43:46.504483 <8>[ 29.202394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13512 04:43:46.505329 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13514 04:43:46.507936 s-continuation-dpms-rpm: SKIP (0.000s)[0m
13515 04:43:46.514472 IGT-Version: 1.27.1-g621c2d3 (aarch6<14>[ 29.220948] [IGT] kms_vblank: executing
13516 04:43:46.518115 4) (Linux: 6.1.75-cip14-rt8 aarch64)
13517 04:43:46.524691 Opened dev<14>[ 29.226493] [IGT] kms_vblank: exiting, ret=77
13518 04:43:46.530848 <8>[ 29.231031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13519 04:43:46.531691 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13521 04:43:46.534394 ice: /dev/dri/card0
13522 04:43:46.537798 No KMS driv<14>[ 29.243119] [IGT] kms_vblank: executing
13523 04:43:46.544560 <14>[ 29.243594] [IGT] kms_vblank: exiting, ret=77
13524 04:43:46.551100 <8>[ 29.247775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13525 04:43:46.551930 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13527 04:43:46.554495 er or no outputs, pipes: 8, outputs: 0
13528 04:43:46.558104 [1mSubt<14>[ 29.262151] [IGT] kms_vblank: executing
13529 04:43:46.564392 est pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13530 04:43:46.571077 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13531 04:43:46.574568 Opened device: /dev/dri/card0
13532 04:43:46.577469 No KMS driver or no outputs, pipes: 8, outputs: 0
13533 04:43:46.584572 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13534 04:43:46.590999 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13535 04:43:46.591567 Opened device: /dev/dri/card0
13536 04:43:46.597575 No KMS driver or no outputs, pipes: 8, outputs: 0
13537 04:43:46.601090 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13538 04:43:46.607608 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13539 04:43:46.610778 Opened device: /dev/dri/card0
13540 04:43:46.614402 No KMS driver or no outputs, pipes: 8, outputs: 0
13541 04:43:46.620693 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13542 04:43:46.627726 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13543 04:43:46.631005 Opened device: /dev/dri/card0
13544 04:43:46.634205 No KMS driver or no outputs, pipes: 8, outputs: 0
13545 04:43:46.641007 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13546 04:43:46.647623 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13547 04:43:46.650763 Opened device: /dev/dri/card0
13548 04:43:46.653996 No KMS driver or no outputs, pipes: 8, outputs: 0
13549 04:43:46.660584 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13550 04:43:46.667263 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13551 04:43:46.667822 Opened device: /dev/dri/card0
13552 04:43:46.674062 No KMS driver or no outputs, pipes: 8, outputs: 0
13553 04:43:46.677486 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13554 04:43:46.684071 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13555 04:43:46.687314 Opened device: /dev/dri/card0
13556 04:43:46.690627 No KMS driver or no outputs, pipes: 8, outputs: 0
13557 04:43:46.697025 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13558 04:43:46.700615 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13559 04:43:46.703809 Opened device: /dev/dri/card0
13560 04:43:46.710400 No KMS driver or no outputs, pipes: 8, outputs: 0
13561 04:43:46.713890 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13562 04:43:46.720382 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13563 04:43:46.723919 Opened device: /dev/dri/card0
13564 04:43:46.726575 No KMS driver or no outputs, pipes: 8, outputs: 0
13565 04:43:46.733676 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13566 04:43:46.737161 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13567 04:43:46.740226 Opened device: /dev/dri/card0
13568 04:43:46.746698 No KMS driver or no outputs, pipes: 8, outputs: 0
13569 04:43:46.749883 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13570 04:43:46.756641 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13571 04:43:46.759908 Opened device: /dev/dri/card0
13572 04:43:46.763266 No KMS driver or no outputs, pipes: 8, outputs: 0
13573 04:43:46.769598 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13574 04:43:46.773094 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13575 04:43:46.776131 Opened device: /dev/dri/card0
13576 04:43:46.783285 No KMS driver or no outputs, pipes: 8, outputs: 0
13577 04:43:46.786554 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13578 04:43:46.793057 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13579 04:43:46.796141 Opened device: /dev/dri/card0
13580 04:43:46.799579 No KMS driver or no outputs, pipes: 8, outputs: 0
13581 04:43:46.806005 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13582 04:43:46.812579 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13583 04:43:46.816113 Opened device: /dev/dri/card0
13584 04:43:46.819390 No KMS driver or no outputs, pipes: 8, outputs: 0
13585 04:43:46.822607 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13586 04:43:46.829363 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13587 04:43:46.832585 Opened device: /dev/dri/card0
13588 04:43:46.836004 No KMS driver or no outputs, pipes: 8, outputs: 0
13589 04:43:46.842829 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13590 04:43:46.849553 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13591 04:43:46.850226 Opened device: /dev/dri/card0
13592 04:43:46.856065 No KMS driver or no outputs, pipes: 8, outputs: 0
13593 04:43:46.859315 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13594 04:43:46.865833 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13595 04:43:46.869224 Opened device: /dev/dri/card0
13596 04:43:46.872054 No KMS driver or no outputs, pipes: 8, outputs: 0
13597 04:43:46.879003 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13598 04:43:46.885621 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13599 04:43:46.886253 Opened device: /dev/dri/card0
13600 04:43:46.895330 No KMS driver or no outputs, pipes: 8, output<14>[ 29.600033] [IGT] kms_vblank: exiting, ret=77
13601 04:43:46.902041 <8>[ 29.606601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13602 04:43:46.902917 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13604 04:43:46.905281 s: 0
13605 04:43:46.908906 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13606 04:43:46.915155 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13607 04:43:46.918452 Opened device: /dev/dri/card0
13608 04:43:46.922004 No KMS driver or<14>[ 29.628512] [IGT] kms_vblank: executing
13609 04:43:46.928629 <14>[ 29.629290] [IGT] kms_vblank: exiting, ret=77
13610 04:43:46.935334 <8>[ 29.634477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13611 04:43:46.936195 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13613 04:43:46.938357 no outputs, pipes: 8, outputs: 0
13614 04:43:46.942115 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13615 04:43:46.952041 IGT-Version: 1.27.1-g621c2d3 (aarch64) <14>[ 29.656228] [IGT] kms_vblank: executing
13616 04:43:46.955270 <14>[ 29.657074] [IGT] kms_vblank: exiting, ret=77
13617 04:43:46.965042 <8>[ 29.662954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13618 04:43:46.965905 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13620 04:43:46.968449 (Linux: 6.1.75-cip14-rt8 aarch64)
13621 04:43:46.969031 Opened device: /dev/dri/card0
13622 04:43:46.975155 No KMS driver <14>[ 29.681436] [IGT] kms_vblank: executing
13623 04:43:46.978217 or no outputs, pipes: 8, outputs: 0
13624 04:43:46.984973 [1mSubtest<14>[ 29.687467] [IGT] kms_vblank: exiting, ret=77
13625 04:43:46.991698 <8>[ 29.692334] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13626 04:43:46.992546 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13628 04:43:46.998904 pipe-G-wait-forked-busy: SKIP (<14>[ 29.704933] [IGT] kms_vblank: executing
13629 04:43:47.001437 0.000s)[0m
13630 04:43:47.008466 IGT-Version: 1.27.1-g621c2d3 (aarch<14>[ 29.705552] [IGT] kms_vblank: exiting, ret=77
13631 04:43:47.018133 <8>[ 29.716871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13632 04:43:47.018995 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13634 04:43:47.021257 64) (Linux: 6.1.<14>[ 29.729213] [IGT] kms_vblank: executing
13635 04:43:47.024953 75-cip14-rt8 aarch64)
13636 04:43:47.031209 Opened device: /dev/dri/c<14>[ 29.734348] [IGT] kms_vblank: exiting, ret=77
13637 04:43:47.040959 <8>[ 29.740904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13638 04:43:47.041444 ard0
13639 04:43:47.042070 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13641 04:43:47.048101 No KMS driver or no output<14>[ 29.753049] [IGT] kms_vblank: executing
13642 04:43:47.048686 s, pipes: 8, outputs: 0
13643 04:43:47.054617 [1mSubtest pipe-G-wait<14>[ 29.758752] [IGT] kms_vblank: exiting, ret=77
13644 04:43:47.064542 <8>[ 29.766663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13645 04:43:47.065393 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13647 04:43:47.067933 -forked-busy-hang: SKIP (0.000s)[0m
13648 04:43:47.074864 IGT-Version: 1.27.1-g621c2<14>[ 29.778683] [IGT] kms_vblank: executing
13649 04:43:47.081012 d3 (aarch64) (Li<14>[ 29.779235] [IGT] kms_vblank: exiting, ret=77
13650 04:43:47.087983 <8>[ 29.786019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13651 04:43:47.088830 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13653 04:43:47.094875 nux: 6.1.75-cip1<14>[ 29.801048] [IGT] kms_vblank: executing
13654 04:43:47.097549 4-rt8 aarch64)
13655 04:43:47.098122 Opened device: /dev/dri/card0
13656 04:43:47.104481 N<14>[ 29.806628] [IGT] kms_vblank: exiting, ret=77
13657 04:43:47.111037 <8>[ 29.814825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13658 04:43:47.111784 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13660 04:43:47.117796 o KMS driver or no outputs, pipes: 8, outputs: 0
13661 04:43:47.124200 [1mSubtest pipe-G-ts-continua<14>[ 29.826038] [IGT] kms_vblank: executing
13662 04:43:47.127688 <14>[ 29.826572] [IGT] kms_vblank: exiting, ret=77
13663 04:43:47.137525 <8>[ 29.833289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13664 04:43:47.138450 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13666 04:43:47.144097 tion-idle: SKIP <14>[ 29.848977] [IGT] kms_vblank: executing
13667 04:43:47.144686 (0.000s)[0m
13668 04:43:47.150772 IGT-Version: 1.27.1-g621c2d3 (aarc<14>[ 29.849537] [IGT] kms_vblank: exiting, ret=77
13669 04:43:47.160525 <8>[ 29.862611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13670 04:43:47.161277 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13672 04:43:47.166986 h64) (Linux: 6.1<14>[ 29.873416] [IGT] kms_vblank: executing
13673 04:43:47.167582 .75-cip14-rt8 aarch64)
13674 04:43:47.174224 Opened device: /dev/dri/<14>[ 29.878300] [IGT] kms_vblank: exiting, ret=77
13675 04:43:47.183747 <8>[ 29.884876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13676 04:43:47.184343 card0
13677 04:43:47.185003 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13679 04:43:47.190321 No KMS driver or no outputs, pipes: 8, ou<14>[ 29.895729] [IGT] kms_vblank: executing
13680 04:43:47.197145 <14>[ 29.896193] [IGT] kms_vblank: exiting, ret=77
13681 04:43:47.203361 <8>[ 29.902913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13682 04:43:47.203905 tputs: 0
13683 04:43:47.204551 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13685 04:43:47.210082 [1mSubtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13686 04:43:47.216726 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13687 04:43:47.220433 Opened device: /dev/dri/card0
13688 04:43:47.226676 No KMS driver or no outputs, pipes: 8, outpu<14>[ 29.929707] [IGT] kms_vblank: executing
13689 04:43:47.233680 <14>[ 29.930483] [IGT] kms_vblank: exiting, ret=77
13690 04:43:47.240194 <8>[ 29.935780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13691 04:43:47.240794 ts: 0
13692 04:43:47.241468 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13694 04:43:47.246650 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13695 04:43:47.256471 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip<14>[ 29.958154] [IGT] kms_vblank: executing
13696 04:43:47.259925 <14>[ 29.958998] [IGT] kms_vblank: exiting, ret=77
13697 04:43:47.266236 <8>[ 29.964546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13698 04:43:47.267103 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13700 04:43:47.269763 14-rt8 aarch64)
13701 04:43:47.272883 Opened device: /dev/dri/card0
13702 04:43:47.276290 <14>[ 29.978928] [IGT] kms_vblank: executing
13703 04:43:47.279735 <14>[ 29.979371] [IGT] kms_vblank: exiting, ret=77
13704 04:43:47.289465 <8>[ 29.983911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13705 04:43:47.290350 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13707 04:43:47.292870 No KMS driver or no outputs, pipes: 8, outputs: 0
13708 04:43:47.299327 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13709 04:43:47.305822 IGT-Version: 1.27.1-g621c2d3 (aarch64) (L<14>[ 30.010371] [IGT] kms_vblank: executing
13710 04:43:47.312765 <14>[ 30.011118] [IGT] kms_vblank: exiting, ret=77
13711 04:43:47.319566 <8>[ 30.016465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13712 04:43:47.320429 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13714 04:43:47.322586 inux: 6.1.75-cip14-rt8 aarch64)
13715 04:43:47.325920 Opened device: <14>[ 30.030273] [IGT] kms_vblank: executing
13716 04:43:47.332769 <14>[ 30.030720] [IGT] kms_vblank: exiting, ret=77
13717 04:43:47.339338 <8>[ 30.035311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13718 04:43:47.339930 /dev/dri/card0
13719 04:43:47.340586 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13721 04:43:47.345766 No KMS driver or no outputs, pipes: 8, outputs: 0
13722 04:43:47.356161 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[0m<14>[ 30.060893] [IGT] kms_vblank: executing
13723 04:43:47.356756
13724 04:43:47.362667 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux:<14>[ 30.066515] [IGT] kms_vblank: exiting, ret=77
13725 04:43:47.372537 <8>[ 30.072047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13726 04:43:47.373129 6.1.75-cip14-rt8 aarch64)
13727 04:43:47.373795 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13729 04:43:47.378861 Open<14>[ 30.083411] [IGT] kms_vblank: executing
13730 04:43:47.382278 <14>[ 30.083881] [IGT] kms_vblank: exiting, ret=77
13731 04:43:47.392430 <8>[ 30.087875] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13732 04:43:47.393327 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13734 04:43:47.395581 ed device: /dev/dri/card0
13735 04:43:47.398948 No KMS driver or no outputs, pipes: 8, outputs: 0
13736 04:43:47.405723 [1mSubtest pipe-G-ts-continuation-modeset: SKIP (0.000s)[0m
13737 04:43:47.412128 IGT-Version: 1.27.1-g621c2d3 (aarch<14>[ 30.116546] [IGT] kms_vblank: executing
13738 04:43:47.419505 64) (Linux: 6.1.<14>[ 30.117352] [IGT] kms_vblank: exiting, ret=77
13739 04:43:47.425587 <8>[ 30.122636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13740 04:43:47.426223 75-cip14-rt8 aarch64)
13741 04:43:47.426903 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13743 04:43:47.428625 Opened device: /dev/dri/card0
13744 04:43:47.435232 No KMS driver or no outputs, pipes: 8, outputs: 0
13745 04:43:47.438872 [1mSub<14>[ 30.144256] [IGT] kms_vblank: executing
13746 04:43:47.442276 <14>[ 30.145090] [IGT] kms_vblank: exiting, ret=77
13747 04:43:47.451654 <8>[ 30.150595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13748 04:43:47.452505 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13750 04:43:47.454755 test pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13751 04:43:47.461736 IGT-Version: 1.27.1<14>[ 30.168953] [IGT] kms_vblank: executing
13752 04:43:47.471693 -g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aar<14>[ 30.173957] [IGT] kms_vblank: exiting, ret=77
13753 04:43:47.478750 <8>[ 30.179055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13754 04:43:47.479339 ch64)
13755 04:43:47.479994 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13757 04:43:47.481718 Opened device: /dev/dri/card0
13758 04:43:47.485370 No KMS driver or no outputs, pipes: 8, outputs: 0
13759 04:43:47.494832 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0<14>[ 30.199176] [IGT] kms_vblank: executing
13760 04:43:47.501309 <14>[ 30.199979] [IGT] kms_vblank: exiting, ret=77
13761 04:43:47.507753 <8>[ 30.205967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13762 04:43:47.508248 .000s)[0m
13763 04:43:47.508897 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13765 04:43:47.514571 IGT-Version: 1.27.1-<14>[ 30.219658] [IGT] kms_vblank: executing
13766 04:43:47.518128 <14>[ 30.220137] [IGT] kms_vblank: exiting, ret=77
13767 04:43:47.528040 <8>[ 30.226320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13768 04:43:47.528909 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13770 04:43:47.534589 g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarc<14>[ 30.238703] [IGT] kms_vblank: executing
13771 04:43:47.541338 <14>[ 30.239141] [IGT] kms_vblank: exiting, ret=77
13772 04:43:47.547721 <8>[ 30.244494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13773 04:43:47.548321 h64)
13774 04:43:47.548985 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13776 04:43:47.554579 Opened device: /dev/dri/ca<14>[ 30.259588] [IGT] kms_vblank: executing
13777 04:43:47.561114 <14>[ 30.260038] [IGT] kms_vblank: exiting, ret=77
13778 04:43:47.567477 <8>[ 30.266583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
13779 04:43:47.568052 rd0
13780 04:43:47.568703 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
13782 04:43:47.570894 No KMS driver or no outputs, pipes: 8, outputs: 0
13783 04:43:47.577716 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13784 04:43:47.583925 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13785 04:43:47.587088 Opened device: /dev/dri/card0
13786 04:43:47.590616 No KMS driver or no outputs, pipes: 8, outputs: 0
13787 04:43:47.594024 [1mSub<14>[ 30.300960] [IGT] kms_vblank: executing
13788 04:43:47.603686 test pipe-H-query-idle: SKIP (0.<14>[ 30.307221] [IGT] kms_vblank: exiting, ret=77
13789 04:43:47.610106 <8>[ 30.312758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
13790 04:43:47.611088 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
13792 04:43:47.613469 000s)[0m
13793 04:43:47.617053 IGT-Version: 1.27.1-g<14>[ 30.322976] [IGT] kms_vblank: executing
13794 04:43:47.623584 621c2d3 (aarch64<14>[ 30.323421] [IGT] kms_vblank: exiting, ret=77
13795 04:43:47.633519 <8>[ 30.332971] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
13796 04:43:47.634402 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
13798 04:43:47.636898 ) (Linux: 6.1.75-cip14-rt8 aarch64)
13799 04:43:47.637381 Opened device: /dev/dri/card0
13800 04:43:47.643506 No KMS driver or no outputs, pipes: 8, outputs: 0
13801 04:43:47.646641 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13802 04:43:47.653225 IGT-Version: 1.27.1-g621c2d3 (aarc<14>[ 30.357656] [IGT] kms_vblank: executing
13803 04:43:47.659854 <14>[ 30.358465] [IGT] kms_vblank: exiting, ret=77
13804 04:43:47.666569 <8>[ 30.363882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
13805 04:43:47.667396 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
13807 04:43:47.673384 h64) (Linux: 6.1.75-cip14-rt8 aarch64)
13808 04:43:47.673985 Opened device: /dev/dri/card0
13809 04:43:47.679853 No KMS dr<14>[ 30.382937] [IGT] kms_vblank: executing
13810 04:43:47.683322 <14>[ 30.383739] [IGT] kms_vblank: exiting, ret=77
13811 04:43:47.693045 <8>[ 30.388877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
13812 04:43:47.693881 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
13814 04:43:47.699608 iver or no outpu<14>[ 30.404462] [IGT] kms_vblank: executing
13815 04:43:47.702810 <14>[ 30.404921] [IGT] kms_vblank: exiting, ret=77
13816 04:43:47.712865 <8>[ 30.409418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
13817 04:43:47.713426 ts, pipes: 8, outputs: 0
13818 04:43:47.714070 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
13820 04:43:47.719615 [1mSu<14>[ 30.423744] [IGT] kms_vblank: executing
13821 04:43:47.723006 <14>[ 30.424227] [IGT] kms_vblank: exiting, ret=77
13822 04:43:47.732529 <8>[ 30.431238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
13823 04:43:47.733387 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
13825 04:43:47.739258 btest pipe-H-query-forked: SKIP <14>[ 30.443987] [IGT] kms_vblank: executing
13826 04:43:47.742675 <14>[ 30.444477] [IGT] kms_vblank: exiting, ret=77
13827 04:43:47.752595 <8>[ 30.451663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
13828 04:43:47.753169 (0.000s)[0m
13829 04:43:47.753810 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
13831 04:43:47.759002 IGT-Version: 1.27.<14>[ 30.464228] [IGT] kms_vblank: executing
13832 04:43:47.766083 1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13833 04:43:47.766664 Opened device: /dev/dri/card0
13834 04:43:47.772286 No KMS driver or no outputs, pipes: 8, outputs: 0
13835 04:43:47.775453 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13836 04:43:47.782394 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13837 04:43:47.786040 Opened device: /dev/dri/card0
13838 04:43:47.789440 No KMS driver or no outputs, pipes: 8, outputs: 0
13839 04:43:47.795994 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13840 04:43:47.798778 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13841 04:43:47.802485 Opened device: /dev/dri/card0
13842 04:43:47.808708 No KMS driver or no outputs, pipes: 8, outputs: 0
13843 04:43:47.812069 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13844 04:43:47.819094 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13845 04:43:47.822081 Opened device: /dev/dri/card0
13846 04:43:47.825610 No KMS driver or no outputs, pipes: 8, outputs: 0
13847 04:43:47.832070 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13848 04:43:47.838387 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13849 04:43:47.839015 Opened device: /dev/dri/card0
13850 04:43:47.845245 No KMS driver or no outputs, pipes: 8, outputs: 0
13851 04:43:47.848462 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13852 04:43:47.855608 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13853 04:43:47.858278 Opened device: /dev/dri/card0
13854 04:43:47.865476 No KMS driver or no outputs, pipes: 8, outputs: 0
13855 04:43:47.868342 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13856 04:43:47.875286 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13857 04:43:47.878062 Opened device: /dev/dri/card0
13858 04:43:47.881303 No KMS driver or no outputs, pipes: 8, outputs: 0
13859 04:43:47.885315 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13860 04:43:47.891724 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13861 04:43:47.895040 Opened device: /dev/dri/card0
13862 04:43:47.898141 No KMS driver or no outputs, pipes: 8, outputs: 0
13863 04:43:47.904765 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13864 04:43:47.911199 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13865 04:43:47.911674 Opened device: /dev/dri/card0
13866 04:43:47.918208 No KMS driver or no outputs, pipes: 8, outputs: 0
13867 04:43:47.921381 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13868 04:43:47.927942 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13869 04:43:47.931436 Opened device: /dev/dri/card0
13870 04:43:47.934608 No KMS driver or no outputs, pipes: 8, outputs: 0
13871 04:43:47.941225 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13872 04:43:47.947517 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13873 04:43:47.948079 Opened device: /dev/dri/card0
13874 04:43:47.954054 No KMS driver or no outputs, pipes: 8, outputs: 0
13875 04:43:47.957754 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
13876 04:43:47.963968 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13877 04:43:47.967618 Opened device: /dev/dri/card0
13878 04:43:47.971084 No KMS driver or no outputs, pipes: 8, outputs: 0
13879 04:43:47.977474 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
13880 04:43:47.983957 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13881 04:43:47.987519 Opened device: /dev/dri/card0
13882 04:43:47.990941 No KMS driver or no outputs, pipes: 8, outputs: 0
13883 04:43:47.997367 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
13884 04:43:48.000876 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13885 04:43:48.004148 Opened device: /dev/dri/card0
13886 04:43:48.010526 No KMS driver or no outputs, pipes: 8, outputs: 0
13887 04:43:48.013427 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
13888 04:43:48.020488 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13889 04:43:48.024009 Opened device: /dev/dri/card0
13890 04:43:48.026633 No KMS driver or no outputs, pipes: 8, outputs: 0
13891 04:43:48.033639 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
13892 04:43:48.040714 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13893 04:43:48.043280 Opened device: /dev/dri/card0
13894 04:43:48.047323 No KMS driver or no outputs, pipes: 8, outputs: 0
13895 04:43:48.053799 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13896 04:43:48.060593 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13897 04:43:48.061172 Opened device: /dev/dri/card0
13898 04:43:48.066849 No KMS driver or no outputs, pipes: 8, outputs: 0
13899 04:43:48.073179 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13900 04:43:48.080284 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13901 04:43:48.080871 Opened device: /dev/dri/card0
13902 04:43:48.086914 No KMS driver or no outputs, pipes: 8, outputs: 0
13903 04:43:48.090173 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
13904 04:43:48.099946 IGT-Version: 1.27.1-g621c2d3 (aarch<14>[ 30.802688] [IGT] kms_vblank: exiting, ret=77
13905 04:43:48.106382 <8>[ 30.807317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
13906 04:43:48.107189 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
13908 04:43:48.112967 64) (Linux: 6.1.75-cip14-rt8 aar<14>[ 30.819609] [IGT] kms_vblank: executing
13909 04:43:48.120154 <14>[ 30.820051] [IGT] kms_vblank: exiting, ret=77
13910 04:43:48.129868 <8>[ 30.824215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
13911 04:43:48.130748 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
13913 04:43:48.132979 <8>[ 30.826499] <LAVA_SIGNAL_TESTSET STOP>
13914 04:43:48.133454 ch64)
13915 04:43:48.134064 Received signal: <TESTSET> STOP
13916 04:43:48.134448 Closing test_set kms_vblank
13917 04:43:48.142732 Opened device: /dev/dri/c<8>[ 30.844216] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 12699799_1.5.2.3.1>
13918 04:43:48.143300 ard0
13919 04:43:48.143945 Received signal: <ENDRUN> 0_igt-kms-mediatek 12699799_1.5.2.3.1
13920 04:43:48.144396 Ending use of test pattern.
13921 04:43:48.144748 Ending test lava.0_igt-kms-mediatek (12699799_1.5.2.3.1), duration 11.84
13923 04:43:48.146405 No KMS driver or no outputs, pipes: 8, outputs: 0
13924 04:43:48.152789 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
13925 04:43:48.159416 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13926 04:43:48.162653 Opened device: /dev/dri/card0
13927 04:43:48.166485 No KMS driver or no outputs, pipes: 8, outputs: 0
13928 04:43:48.172825 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13929 04:43:48.179306 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14-rt8 aarch64)
13930 04:43:48.179739 Opened device: /dev/dri/card0
13931 04:43:48.185711 No KMS driver or no outputs, pipes: 8, outputs: 0
13932 04:43:48.192494 [1mSubtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13933 04:43:48.192924 + set +x
13934 04:43:48.193271 <LAVA_TEST_RUNNER EXIT>
13935 04:43:48.193841 ok: lava_test_shell seems to have completed
13936 04:43:48.214263 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
13937 04:43:48.215489 end: 3.1 lava-test-shell (duration 00:00:12) [common]
13938 04:43:48.215940 end: 3 lava-test-retry (duration 00:00:12) [common]
13939 04:43:48.216393 start: 4 finalize (timeout 00:07:48) [common]
13940 04:43:48.216844 start: 4.1 power-off (timeout 00:00:30) [common]
13941 04:43:48.217579 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
13942 04:43:48.324964 >> Command sent successfully.
13943 04:43:48.329091 Returned 0 in 0 seconds
13944 04:43:48.429894 end: 4.1 power-off (duration 00:00:00) [common]
13946 04:43:48.431382 start: 4.2 read-feedback (timeout 00:07:48) [common]
13947 04:43:48.432529 Listened to connection for namespace 'common' for up to 1s
13948 04:43:49.433229 Finalising connection for namespace 'common'
13949 04:43:49.433922 Disconnecting from shell: Finalise
13950 04:43:49.434358 / #
13951 04:43:49.535350 end: 4.2 read-feedback (duration 00:00:01) [common]
13952 04:43:49.536129 end: 4 finalize (duration 00:00:01) [common]
13953 04:43:49.536779 Cleaning after the job
13954 04:43:49.537318 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699799/tftp-deploy-s8jh0h48/ramdisk
13955 04:43:49.565927 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699799/tftp-deploy-s8jh0h48/kernel
13956 04:43:49.582293 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699799/tftp-deploy-s8jh0h48/dtb
13957 04:43:49.582589 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699799/tftp-deploy-s8jh0h48/modules
13958 04:43:49.591157 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12699799
13959 04:43:49.687334 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12699799
13960 04:43:49.687516 Job finished correctly