Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 14
- Kernel Errors: 31
1 04:46:52.197890 lava-dispatcher, installed at version: 2023.10
2 04:46:52.198113 start: 0 validate
3 04:46:52.198252 Start time: 2024-02-04 04:46:52.198245+00:00 (UTC)
4 04:46:52.198371 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:46:52.198505 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 04:46:52.461776 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:46:52.461958 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:46:52.719143 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:46:52.719323 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:46:52.976226 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:46:52.976484 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 04:46:53.240937 Using caching service: 'http://localhost/cache/?uri=%s'
13 04:46:53.241127 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 04:46:53.507338 validate duration: 1.31
16 04:46:53.507615 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:46:53.507745 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:46:53.507879 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:46:53.508033 Not decompressing ramdisk as can be used compressed.
20 04:46:53.508159 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 04:46:53.508254 saving as /var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/ramdisk/initrd.cpio.gz
22 04:46:53.508387 total size: 4665395 (4 MB)
23 04:46:53.509504 progress 0 % (0 MB)
24 04:46:53.511141 progress 5 % (0 MB)
25 04:46:53.512541 progress 10 % (0 MB)
26 04:46:53.513826 progress 15 % (0 MB)
27 04:46:53.515176 progress 20 % (0 MB)
28 04:46:53.516547 progress 25 % (1 MB)
29 04:46:53.517863 progress 30 % (1 MB)
30 04:46:53.519207 progress 35 % (1 MB)
31 04:46:53.520583 progress 40 % (1 MB)
32 04:46:53.522056 progress 45 % (2 MB)
33 04:46:53.523443 progress 50 % (2 MB)
34 04:46:53.524839 progress 55 % (2 MB)
35 04:46:53.526125 progress 60 % (2 MB)
36 04:46:53.527436 progress 65 % (2 MB)
37 04:46:53.528831 progress 70 % (3 MB)
38 04:46:53.530176 progress 75 % (3 MB)
39 04:46:53.531511 progress 80 % (3 MB)
40 04:46:53.533121 progress 85 % (3 MB)
41 04:46:53.534466 progress 90 % (4 MB)
42 04:46:53.535806 progress 95 % (4 MB)
43 04:46:53.537209 progress 100 % (4 MB)
44 04:46:53.537372 4 MB downloaded in 0.03 s (153.49 MB/s)
45 04:46:53.537518 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:46:53.537766 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:46:53.537849 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:46:53.537930 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:46:53.538079 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 04:46:53.538164 saving as /var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/kernel/Image
52 04:46:53.538223 total size: 51597824 (49 MB)
53 04:46:53.538282 No compression specified
54 04:46:53.539951 progress 0 % (0 MB)
55 04:46:53.553996 progress 5 % (2 MB)
56 04:46:53.567722 progress 10 % (4 MB)
57 04:46:53.581756 progress 15 % (7 MB)
58 04:46:53.596081 progress 20 % (9 MB)
59 04:46:53.610942 progress 25 % (12 MB)
60 04:46:53.625057 progress 30 % (14 MB)
61 04:46:53.639540 progress 35 % (17 MB)
62 04:46:53.653977 progress 40 % (19 MB)
63 04:46:53.667845 progress 45 % (22 MB)
64 04:46:53.681555 progress 50 % (24 MB)
65 04:46:53.695357 progress 55 % (27 MB)
66 04:46:53.708999 progress 60 % (29 MB)
67 04:46:53.722911 progress 65 % (32 MB)
68 04:46:53.736558 progress 70 % (34 MB)
69 04:46:53.750040 progress 75 % (36 MB)
70 04:46:53.763886 progress 80 % (39 MB)
71 04:46:53.777559 progress 85 % (41 MB)
72 04:46:53.791909 progress 90 % (44 MB)
73 04:46:53.805555 progress 95 % (46 MB)
74 04:46:53.819145 progress 100 % (49 MB)
75 04:46:53.819364 49 MB downloaded in 0.28 s (175.03 MB/s)
76 04:46:53.819510 end: 1.2.1 http-download (duration 00:00:00) [common]
78 04:46:53.819774 end: 1.2 download-retry (duration 00:00:00) [common]
79 04:46:53.819858 start: 1.3 download-retry (timeout 00:10:00) [common]
80 04:46:53.819944 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 04:46:53.820077 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 04:46:53.820143 saving as /var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/dtb/mt8192-asurada-spherion-r0.dtb
83 04:46:53.820202 total size: 47278 (0 MB)
84 04:46:53.820263 No compression specified
85 04:46:53.821503 progress 69 % (0 MB)
86 04:46:53.821839 progress 100 % (0 MB)
87 04:46:53.821992 0 MB downloaded in 0.00 s (25.23 MB/s)
88 04:46:53.822111 end: 1.3.1 http-download (duration 00:00:00) [common]
90 04:46:53.822329 end: 1.3 download-retry (duration 00:00:00) [common]
91 04:46:53.822415 start: 1.4 download-retry (timeout 00:10:00) [common]
92 04:46:53.822495 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 04:46:53.822607 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 04:46:53.822672 saving as /var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/nfsrootfs/full.rootfs.tar
95 04:46:53.822731 total size: 200813988 (191 MB)
96 04:46:53.822791 Using unxz to decompress xz
97 04:46:53.827151 progress 0 % (0 MB)
98 04:46:54.366626 progress 5 % (9 MB)
99 04:46:54.887257 progress 10 % (19 MB)
100 04:46:55.485935 progress 15 % (28 MB)
101 04:46:55.866125 progress 20 % (38 MB)
102 04:46:56.194886 progress 25 % (47 MB)
103 04:46:56.793110 progress 30 % (57 MB)
104 04:46:57.349565 progress 35 % (67 MB)
105 04:46:57.951920 progress 40 % (76 MB)
106 04:46:58.529321 progress 45 % (86 MB)
107 04:46:59.145527 progress 50 % (95 MB)
108 04:46:59.809030 progress 55 % (105 MB)
109 04:47:00.507935 progress 60 % (114 MB)
110 04:47:00.640962 progress 65 % (124 MB)
111 04:47:00.793666 progress 70 % (134 MB)
112 04:47:00.894893 progress 75 % (143 MB)
113 04:47:00.973683 progress 80 % (153 MB)
114 04:47:01.050346 progress 85 % (162 MB)
115 04:47:01.161694 progress 90 % (172 MB)
116 04:47:01.450819 progress 95 % (181 MB)
117 04:47:02.024667 progress 100 % (191 MB)
118 04:47:02.029807 191 MB downloaded in 8.21 s (23.33 MB/s)
119 04:47:02.030086 end: 1.4.1 http-download (duration 00:00:08) [common]
121 04:47:02.030380 end: 1.4 download-retry (duration 00:00:08) [common]
122 04:47:02.030509 start: 1.5 download-retry (timeout 00:09:51) [common]
123 04:47:02.030643 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 04:47:02.030855 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 04:47:02.030958 saving as /var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/modules/modules.tar
126 04:47:02.031058 total size: 8633524 (8 MB)
127 04:47:02.031153 Using unxz to decompress xz
128 04:47:02.035631 progress 0 % (0 MB)
129 04:47:02.056640 progress 5 % (0 MB)
130 04:47:02.081387 progress 10 % (0 MB)
131 04:47:02.105867 progress 15 % (1 MB)
132 04:47:02.130556 progress 20 % (1 MB)
133 04:47:02.155210 progress 25 % (2 MB)
134 04:47:02.182834 progress 30 % (2 MB)
135 04:47:02.207102 progress 35 % (2 MB)
136 04:47:02.230378 progress 40 % (3 MB)
137 04:47:02.254367 progress 45 % (3 MB)
138 04:47:02.279397 progress 50 % (4 MB)
139 04:47:02.303533 progress 55 % (4 MB)
140 04:47:02.330152 progress 60 % (4 MB)
141 04:47:02.355420 progress 65 % (5 MB)
142 04:47:02.380077 progress 70 % (5 MB)
143 04:47:02.403469 progress 75 % (6 MB)
144 04:47:02.430792 progress 80 % (6 MB)
145 04:47:02.456386 progress 85 % (7 MB)
146 04:47:02.482847 progress 90 % (7 MB)
147 04:47:02.512549 progress 95 % (7 MB)
148 04:47:02.540485 progress 100 % (8 MB)
149 04:47:02.545934 8 MB downloaded in 0.51 s (15.99 MB/s)
150 04:47:02.546184 end: 1.5.1 http-download (duration 00:00:01) [common]
152 04:47:02.546451 end: 1.5 download-retry (duration 00:00:01) [common]
153 04:47:02.546543 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 04:47:02.546640 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 04:47:06.138050 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12699821/extract-nfsrootfs-a_4q7roz
156 04:47:06.138233 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 04:47:06.138331 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 04:47:06.138511 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko
159 04:47:06.138644 makedir: /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin
160 04:47:06.138748 makedir: /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/tests
161 04:47:06.138847 makedir: /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/results
162 04:47:06.138950 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-add-keys
163 04:47:06.139097 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-add-sources
164 04:47:06.139228 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-background-process-start
165 04:47:06.139357 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-background-process-stop
166 04:47:06.139484 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-common-functions
167 04:47:06.139610 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-echo-ipv4
168 04:47:06.139736 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-install-packages
169 04:47:06.139860 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-installed-packages
170 04:47:06.139983 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-os-build
171 04:47:06.140108 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-probe-channel
172 04:47:06.140232 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-probe-ip
173 04:47:06.140424 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-target-ip
174 04:47:06.140640 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-target-mac
175 04:47:06.140770 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-target-storage
176 04:47:06.140901 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-test-case
177 04:47:06.141030 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-test-event
178 04:47:06.141156 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-test-feedback
179 04:47:06.141281 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-test-raise
180 04:47:06.141405 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-test-reference
181 04:47:06.141529 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-test-runner
182 04:47:06.141655 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-test-set
183 04:47:06.141781 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-test-shell
184 04:47:06.141910 Updating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-add-keys (debian)
185 04:47:06.142070 Updating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-add-sources (debian)
186 04:47:06.142213 Updating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-install-packages (debian)
187 04:47:06.142354 Updating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-installed-packages (debian)
188 04:47:06.142496 Updating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/bin/lava-os-build (debian)
189 04:47:06.142620 Creating /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/environment
190 04:47:06.142721 LAVA metadata
191 04:47:06.142793 - LAVA_JOB_ID=12699821
192 04:47:06.142895 - LAVA_DISPATCHER_IP=192.168.201.1
193 04:47:06.143008 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 04:47:06.143077 skipped lava-vland-overlay
195 04:47:06.143152 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 04:47:06.143232 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 04:47:06.143293 skipped lava-multinode-overlay
198 04:47:06.143366 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 04:47:06.143444 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 04:47:06.143516 Loading test definitions
201 04:47:06.143605 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 04:47:06.143675 Using /lava-12699821 at stage 0
203 04:47:06.143964 uuid=12699821_1.6.2.3.1 testdef=None
204 04:47:06.144053 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 04:47:06.144137 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 04:47:06.144633 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 04:47:06.144856 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 04:47:06.145427 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 04:47:06.145657 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 04:47:06.146201 runner path: /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/0/tests/0_timesync-off test_uuid 12699821_1.6.2.3.1
213 04:47:06.146355 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 04:47:06.146580 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 04:47:06.146650 Using /lava-12699821 at stage 0
217 04:47:06.146748 Fetching tests from https://github.com/kernelci/test-definitions.git
218 04:47:06.146825 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/0/tests/1_kselftest-arm64'
219 04:47:09.383305 Running '/usr/bin/git checkout kernelci.org
220 04:47:09.530824 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 04:47:09.531653 uuid=12699821_1.6.2.3.5 testdef=None
222 04:47:09.531813 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 04:47:09.532066 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 04:47:09.532953 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 04:47:09.533177 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 04:47:09.534146 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 04:47:09.534378 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 04:47:09.535310 runner path: /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/0/tests/1_kselftest-arm64 test_uuid 12699821_1.6.2.3.5
232 04:47:09.535403 BOARD='mt8192-asurada-spherion-r0'
233 04:47:09.535467 BRANCH='cip-gitlab'
234 04:47:09.535526 SKIPFILE='/dev/null'
235 04:47:09.535583 SKIP_INSTALL='True'
236 04:47:09.535638 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 04:47:09.535697 TST_CASENAME=''
238 04:47:09.535752 TST_CMDFILES='arm64'
239 04:47:09.535893 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 04:47:09.536092 Creating lava-test-runner.conf files
242 04:47:09.536154 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12699821/lava-overlay-x77kzsko/lava-12699821/0 for stage 0
243 04:47:09.536246 - 0_timesync-off
244 04:47:09.536350 - 1_kselftest-arm64
245 04:47:09.536461 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 04:47:09.536548 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 04:47:17.005429 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 04:47:17.005586 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 04:47:17.005682 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 04:47:17.005810 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 04:47:17.005930 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 04:47:17.127969 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 04:47:17.128404 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 04:47:17.128514 extracting modules file /var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699821/extract-nfsrootfs-a_4q7roz
255 04:47:17.354813 extracting modules file /var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699821/extract-overlay-ramdisk-up0epqmk/ramdisk
256 04:47:17.592672 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 04:47:17.592837 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 04:47:17.592935 [common] Applying overlay to NFS
259 04:47:17.593008 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699821/compress-overlay-pw_697wz/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12699821/extract-nfsrootfs-a_4q7roz
260 04:47:18.533411 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 04:47:18.533574 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 04:47:18.533666 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 04:47:18.533750 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 04:47:18.533828 Building ramdisk /var/lib/lava/dispatcher/tmp/12699821/extract-overlay-ramdisk-up0epqmk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12699821/extract-overlay-ramdisk-up0epqmk/ramdisk
265 04:47:18.874004 >> 119436 blocks
266 04:47:20.807579 rename /var/lib/lava/dispatcher/tmp/12699821/extract-overlay-ramdisk-up0epqmk/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/ramdisk/ramdisk.cpio.gz
267 04:47:20.808079 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 04:47:20.808236 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 04:47:20.808398 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 04:47:20.808523 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/kernel/Image'
271 04:47:33.787537 Returned 0 in 12 seconds
272 04:47:33.888162 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/kernel/image.itb
273 04:47:34.251604 output: FIT description: Kernel Image image with one or more FDT blobs
274 04:47:34.252007 output: Created: Sun Feb 4 04:47:34 2024
275 04:47:34.252089 output: Image 0 (kernel-1)
276 04:47:34.252155 output: Description:
277 04:47:34.252220 output: Created: Sun Feb 4 04:47:34 2024
278 04:47:34.252282 output: Type: Kernel Image
279 04:47:34.252352 output: Compression: lzma compressed
280 04:47:34.252411 output: Data Size: 12048508 Bytes = 11766.12 KiB = 11.49 MiB
281 04:47:34.252470 output: Architecture: AArch64
282 04:47:34.252528 output: OS: Linux
283 04:47:34.252585 output: Load Address: 0x00000000
284 04:47:34.252642 output: Entry Point: 0x00000000
285 04:47:34.252700 output: Hash algo: crc32
286 04:47:34.252756 output: Hash value: 3b31d50c
287 04:47:34.252816 output: Image 1 (fdt-1)
288 04:47:34.252870 output: Description: mt8192-asurada-spherion-r0
289 04:47:34.252925 output: Created: Sun Feb 4 04:47:34 2024
290 04:47:34.252979 output: Type: Flat Device Tree
291 04:47:34.253033 output: Compression: uncompressed
292 04:47:34.253087 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 04:47:34.253141 output: Architecture: AArch64
294 04:47:34.253195 output: Hash algo: crc32
295 04:47:34.253248 output: Hash value: cc4352de
296 04:47:34.253302 output: Image 2 (ramdisk-1)
297 04:47:34.253355 output: Description: unavailable
298 04:47:34.253409 output: Created: Sun Feb 4 04:47:34 2024
299 04:47:34.253463 output: Type: RAMDisk Image
300 04:47:34.253517 output: Compression: Unknown Compression
301 04:47:34.253570 output: Data Size: 17798584 Bytes = 17381.43 KiB = 16.97 MiB
302 04:47:34.253624 output: Architecture: AArch64
303 04:47:34.253678 output: OS: Linux
304 04:47:34.253732 output: Load Address: unavailable
305 04:47:34.253785 output: Entry Point: unavailable
306 04:47:34.253839 output: Hash algo: crc32
307 04:47:34.253892 output: Hash value: 40866f4d
308 04:47:34.253947 output: Default Configuration: 'conf-1'
309 04:47:34.254001 output: Configuration 0 (conf-1)
310 04:47:34.254054 output: Description: mt8192-asurada-spherion-r0
311 04:47:34.254108 output: Kernel: kernel-1
312 04:47:34.254162 output: Init Ramdisk: ramdisk-1
313 04:47:34.254215 output: FDT: fdt-1
314 04:47:34.254269 output: Loadables: kernel-1
315 04:47:34.254322 output:
316 04:47:34.254525 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 04:47:34.254626 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 04:47:34.254738 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 04:47:34.254832 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 04:47:34.254916 No LXC device requested
321 04:47:34.254999 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 04:47:34.255089 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 04:47:34.255169 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 04:47:34.255237 Checking files for TFTP limit of 4294967296 bytes.
325 04:47:34.255755 end: 1 tftp-deploy (duration 00:00:41) [common]
326 04:47:34.255859 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 04:47:34.255955 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 04:47:34.256084 substitutions:
329 04:47:34.256151 - {DTB}: 12699821/tftp-deploy-ystyxgkl/dtb/mt8192-asurada-spherion-r0.dtb
330 04:47:34.256216 - {INITRD}: 12699821/tftp-deploy-ystyxgkl/ramdisk/ramdisk.cpio.gz
331 04:47:34.256276 - {KERNEL}: 12699821/tftp-deploy-ystyxgkl/kernel/Image
332 04:47:34.256343 - {LAVA_MAC}: None
333 04:47:34.256401 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12699821/extract-nfsrootfs-a_4q7roz
334 04:47:34.256458 - {NFS_SERVER_IP}: 192.168.201.1
335 04:47:34.256537 - {PRESEED_CONFIG}: None
336 04:47:34.256614 - {PRESEED_LOCAL}: None
337 04:47:34.256672 - {RAMDISK}: 12699821/tftp-deploy-ystyxgkl/ramdisk/ramdisk.cpio.gz
338 04:47:34.256728 - {ROOT_PART}: None
339 04:47:34.256783 - {ROOT}: None
340 04:47:34.256837 - {SERVER_IP}: 192.168.201.1
341 04:47:34.256892 - {TEE}: None
342 04:47:34.256948 Parsed boot commands:
343 04:47:34.257003 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 04:47:34.257189 Parsed boot commands: tftpboot 192.168.201.1 12699821/tftp-deploy-ystyxgkl/kernel/image.itb 12699821/tftp-deploy-ystyxgkl/kernel/cmdline
345 04:47:34.257281 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 04:47:34.257367 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 04:47:34.257461 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 04:47:34.257547 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 04:47:34.257620 Not connected, no need to disconnect.
350 04:47:34.257694 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 04:47:34.257781 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 04:47:34.257852 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 04:47:34.261993 Setting prompt string to ['lava-test: # ']
354 04:47:34.262405 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 04:47:34.262538 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 04:47:34.262642 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 04:47:34.262736 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 04:47:34.262936 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 04:47:39.389081 >> Command sent successfully.
360 04:47:39.391642 Returned 0 in 5 seconds
361 04:47:39.492069 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 04:47:39.492503 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 04:47:39.492634 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 04:47:39.492735 Setting prompt string to 'Starting depthcharge on Spherion...'
366 04:47:39.492837 Changing prompt to 'Starting depthcharge on Spherion...'
367 04:47:39.492944 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 04:47:39.493231 [Enter `^Ec?' for help]
369 04:47:39.666406
370 04:47:39.666548
371 04:47:39.666617 F0: 102B 0000
372 04:47:39.666681
373 04:47:39.666738 F3: 1001 0000 [0200]
374 04:47:39.666795
375 04:47:39.669814 F3: 1001 0000
376 04:47:39.669895
377 04:47:39.669958 F7: 102D 0000
378 04:47:39.670018
379 04:47:39.670075 F1: 0000 0000
380 04:47:39.670132
381 04:47:39.673295 V0: 0000 0000 [0001]
382 04:47:39.673376
383 04:47:39.673440 00: 0007 8000
384 04:47:39.673518
385 04:47:39.677420 01: 0000 0000
386 04:47:39.677508
387 04:47:39.677581 BP: 0C00 0209 [0000]
388 04:47:39.677658
389 04:47:39.677731 G0: 1182 0000
390 04:47:39.680831
391 04:47:39.680922 EC: 0000 0021 [4000]
392 04:47:39.680996
393 04:47:39.684799 S7: 0000 0000 [0000]
394 04:47:39.684901
395 04:47:39.684980 CC: 0000 0000 [0001]
396 04:47:39.685055
397 04:47:39.688024 T0: 0000 0040 [010F]
398 04:47:39.688167
399 04:47:39.688294 Jump to BL
400 04:47:39.688381
401 04:47:39.712725
402 04:47:39.712906
403 04:47:39.713047
404 04:47:39.720167 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 04:47:39.723481 ARM64: Exception handlers installed.
406 04:47:39.727840 ARM64: Testing exception
407 04:47:39.731845 ARM64: Done test exception
408 04:47:39.738867 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 04:47:39.745816 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 04:47:39.753269 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 04:47:39.764213 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 04:47:39.770307 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 04:47:39.780732 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 04:47:39.791388 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 04:47:39.798109 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 04:47:39.815981 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 04:47:39.818830 WDT: Last reset was cold boot
418 04:47:39.822218 SPI1(PAD0) initialized at 2873684 Hz
419 04:47:39.825759 SPI5(PAD0) initialized at 992727 Hz
420 04:47:39.829228 VBOOT: Loading verstage.
421 04:47:39.835659 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 04:47:39.840184 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 04:47:39.843176 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 04:47:39.846978 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 04:47:39.853626 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 04:47:39.860002 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 04:47:39.870767 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 04:47:39.870849
429 04:47:39.870914
430 04:47:39.881544 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 04:47:39.885197 ARM64: Exception handlers installed.
432 04:47:39.885288 ARM64: Testing exception
433 04:47:39.888004 ARM64: Done test exception
434 04:47:39.891443 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 04:47:39.898474 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 04:47:39.911820 Probing TPM: . done!
437 04:47:39.912002 TPM ready after 0 ms
438 04:47:39.920092 Connected to device vid:did:rid of 1ae0:0028:00
439 04:47:39.926521 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 04:47:39.985860 Initialized TPM device CR50 revision 0
441 04:47:39.996852 tlcl_send_startup: Startup return code is 0
442 04:47:39.997282 TPM: setup succeeded
443 04:47:40.008581 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 04:47:40.017630 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 04:47:40.029897 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 04:47:40.038912 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 04:47:40.042365 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 04:47:40.045748 in-header: 03 07 00 00 08 00 00 00
449 04:47:40.049177 in-data: aa e4 47 04 13 02 00 00
450 04:47:40.052473 Chrome EC: UHEPI supported
451 04:47:40.060348 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 04:47:40.064168 in-header: 03 95 00 00 08 00 00 00
453 04:47:40.064771 in-data: 18 20 20 08 00 00 00 00
454 04:47:40.067532 Phase 1
455 04:47:40.071620 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 04:47:40.075076 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 04:47:40.083458 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 04:47:40.083888 Recovery requested (1009000e)
459 04:47:40.094426 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 04:47:40.099328 tlcl_extend: response is 0
461 04:47:40.111272 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 04:47:40.114853 tlcl_extend: response is 0
463 04:47:40.121898 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 04:47:40.140987 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 04:47:40.147891 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 04:47:40.148358
467 04:47:40.148723
468 04:47:40.157517 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 04:47:40.161024 ARM64: Exception handlers installed.
470 04:47:40.164321 ARM64: Testing exception
471 04:47:40.164750 ARM64: Done test exception
472 04:47:40.186501 pmic_efuse_setting: Set efuses in 11 msecs
473 04:47:40.189987 pmwrap_interface_init: Select PMIF_VLD_RDY
474 04:47:40.196724 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 04:47:40.200099 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 04:47:40.207644 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 04:47:40.211049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 04:47:40.215225 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 04:47:40.219306 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 04:47:40.226575 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 04:47:40.230335 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 04:47:40.234043 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 04:47:40.237319 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 04:47:40.244790 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 04:47:40.248922 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 04:47:40.252775 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 04:47:40.259506 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 04:47:40.263965 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 04:47:40.270746 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 04:47:40.274346 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 04:47:40.281836 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 04:47:40.288924 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 04:47:40.293078 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 04:47:40.296443 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 04:47:40.303825 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 04:47:40.311214 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 04:47:40.314608 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 04:47:40.322049 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 04:47:40.325667 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 04:47:40.329638 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 04:47:40.337066 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 04:47:40.341026 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 04:47:40.344219 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 04:47:40.351656 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 04:47:40.355319 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 04:47:40.358636 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 04:47:40.365877 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 04:47:40.369472 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 04:47:40.377276 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 04:47:40.381192 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 04:47:40.384946 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 04:47:40.388923 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 04:47:40.395657 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 04:47:40.400107 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 04:47:40.403660 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 04:47:40.407455 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 04:47:40.411123 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 04:47:40.414969 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 04:47:40.422727 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 04:47:40.426229 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 04:47:40.429344 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 04:47:40.433555 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 04:47:40.437159 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 04:47:40.440464 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 04:47:40.447909 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 04:47:40.459022 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 04:47:40.462717 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 04:47:40.469900 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 04:47:40.477102 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 04:47:40.485364 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 04:47:40.488743 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 04:47:40.491873 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 04:47:40.500016 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x34
534 04:47:40.503473 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 04:47:40.511591 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 04:47:40.514417 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 04:47:40.523821 [RTC]rtc_get_frequency_meter,154: input=15, output=758
538 04:47:40.533411 [RTC]rtc_get_frequency_meter,154: input=23, output=941
539 04:47:40.543052 [RTC]rtc_get_frequency_meter,154: input=19, output=850
540 04:47:40.552546 [RTC]rtc_get_frequency_meter,154: input=17, output=804
541 04:47:40.562139 [RTC]rtc_get_frequency_meter,154: input=16, output=781
542 04:47:40.571420 [RTC]rtc_get_frequency_meter,154: input=16, output=781
543 04:47:40.581297 [RTC]rtc_get_frequency_meter,154: input=17, output=805
544 04:47:40.584743 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 04:47:40.588178 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 04:47:40.595801 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 04:47:40.600144 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 04:47:40.603558 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 04:47:40.607406 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 04:47:40.610913 ADC[4]: Raw value=905834 ID=7
551 04:47:40.611044 ADC[3]: Raw value=213441 ID=1
552 04:47:40.614433 RAM Code: 0x71
553 04:47:40.618583 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 04:47:40.621993 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 04:47:40.633576 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 04:47:40.637457 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 04:47:40.640541 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 04:47:40.644518 in-header: 03 07 00 00 08 00 00 00
559 04:47:40.648263 in-data: aa e4 47 04 13 02 00 00
560 04:47:40.651948 Chrome EC: UHEPI supported
561 04:47:40.659546 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 04:47:40.662822 in-header: 03 95 00 00 08 00 00 00
563 04:47:40.662920 in-data: 18 20 20 08 00 00 00 00
564 04:47:40.666301 MRC: failed to locate region type 0.
565 04:47:40.673841 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 04:47:40.677970 DRAM-K: Running full calibration
567 04:47:40.684726 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 04:47:40.684824 header.status = 0x0
569 04:47:40.689203 header.version = 0x6 (expected: 0x6)
570 04:47:40.692443 header.size = 0xd00 (expected: 0xd00)
571 04:47:40.692529 header.flags = 0x0
572 04:47:40.699829 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 04:47:40.717968 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
574 04:47:40.725752 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 04:47:40.725851 dram_init: ddr_geometry: 2
576 04:47:40.729812 [EMI] MDL number = 2
577 04:47:40.729929 [EMI] Get MDL freq = 0
578 04:47:40.733117 dram_init: ddr_type: 0
579 04:47:40.737359 is_discrete_lpddr4: 1
580 04:47:40.737446 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 04:47:40.737512
582 04:47:40.737572
583 04:47:40.741166 [Bian_co] ETT version 0.0.0.1
584 04:47:40.744699 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 04:47:40.744783
586 04:47:40.748719 dramc_set_vcore_voltage set vcore to 650000
587 04:47:40.752085 Read voltage for 800, 4
588 04:47:40.752171 Vio18 = 0
589 04:47:40.755455 Vcore = 650000
590 04:47:40.755540 Vdram = 0
591 04:47:40.755616 Vddq = 0
592 04:47:40.759296 Vmddr = 0
593 04:47:40.759376 dram_init: config_dvfs: 1
594 04:47:40.763388 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 04:47:40.770202 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 04:47:40.774436 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 04:47:40.777889 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 04:47:40.781319 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 04:47:40.784827 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 04:47:40.788426 MEM_TYPE=3, freq_sel=18
601 04:47:40.791715 sv_algorithm_assistance_LP4_1600
602 04:47:40.794926 ============ PULL DRAM RESETB DOWN ============
603 04:47:40.798301 ========== PULL DRAM RESETB DOWN end =========
604 04:47:40.802350 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 04:47:40.805747 ===================================
606 04:47:40.809171 LPDDR4 DRAM CONFIGURATION
607 04:47:40.812246 ===================================
608 04:47:40.816174 EX_ROW_EN[0] = 0x0
609 04:47:40.816259 EX_ROW_EN[1] = 0x0
610 04:47:40.820102 LP4Y_EN = 0x0
611 04:47:40.820186 WORK_FSP = 0x0
612 04:47:40.820253 WL = 0x2
613 04:47:40.824077 RL = 0x2
614 04:47:40.824161 BL = 0x2
615 04:47:40.827171 RPST = 0x0
616 04:47:40.827255 RD_PRE = 0x0
617 04:47:40.830248 WR_PRE = 0x1
618 04:47:40.833974 WR_PST = 0x0
619 04:47:40.834087 DBI_WR = 0x0
620 04:47:40.837012 DBI_RD = 0x0
621 04:47:40.837115 OTF = 0x1
622 04:47:40.840123 ===================================
623 04:47:40.843722 ===================================
624 04:47:40.843807 ANA top config
625 04:47:40.847248 ===================================
626 04:47:40.851363 DLL_ASYNC_EN = 0
627 04:47:40.854081 ALL_SLAVE_EN = 1
628 04:47:40.857524 NEW_RANK_MODE = 1
629 04:47:40.857611 DLL_IDLE_MODE = 1
630 04:47:40.860926 LP45_APHY_COMB_EN = 1
631 04:47:40.864257 TX_ODT_DIS = 1
632 04:47:40.867441 NEW_8X_MODE = 1
633 04:47:40.871519 ===================================
634 04:47:40.871604 ===================================
635 04:47:40.874694 data_rate = 1600
636 04:47:40.878763 CKR = 1
637 04:47:40.881990 DQ_P2S_RATIO = 8
638 04:47:40.885172 ===================================
639 04:47:40.888305 CA_P2S_RATIO = 8
640 04:47:40.891576 DQ_CA_OPEN = 0
641 04:47:40.891702 DQ_SEMI_OPEN = 0
642 04:47:40.895002 CA_SEMI_OPEN = 0
643 04:47:40.898196 CA_FULL_RATE = 0
644 04:47:40.901535 DQ_CKDIV4_EN = 1
645 04:47:40.905366 CA_CKDIV4_EN = 1
646 04:47:40.908847 CA_PREDIV_EN = 0
647 04:47:40.908931 PH8_DLY = 0
648 04:47:40.911640 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 04:47:40.915562 DQ_AAMCK_DIV = 4
650 04:47:40.918862 CA_AAMCK_DIV = 4
651 04:47:40.921942 CA_ADMCK_DIV = 4
652 04:47:40.922023 DQ_TRACK_CA_EN = 0
653 04:47:40.924992 CA_PICK = 800
654 04:47:40.928579 CA_MCKIO = 800
655 04:47:40.932305 MCKIO_SEMI = 0
656 04:47:40.935496 PLL_FREQ = 3068
657 04:47:40.939421 DQ_UI_PI_RATIO = 32
658 04:47:40.939515 CA_UI_PI_RATIO = 0
659 04:47:40.943398 ===================================
660 04:47:40.946580 ===================================
661 04:47:40.950836 memory_type:LPDDR4
662 04:47:40.950961 GP_NUM : 10
663 04:47:40.954213 SRAM_EN : 1
664 04:47:40.954296 MD32_EN : 0
665 04:47:40.958290 ===================================
666 04:47:40.961647 [ANA_INIT] >>>>>>>>>>>>>>
667 04:47:40.965704 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 04:47:40.969095 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 04:47:40.972466 ===================================
670 04:47:40.972545 data_rate = 1600,PCW = 0X7600
671 04:47:40.975799 ===================================
672 04:47:40.979022 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 04:47:40.985823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 04:47:40.992576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 04:47:40.995875 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 04:47:40.999214 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 04:47:41.002355 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 04:47:41.006228 [ANA_INIT] flow start
679 04:47:41.006310 [ANA_INIT] PLL >>>>>>>>
680 04:47:41.009504 [ANA_INIT] PLL <<<<<<<<
681 04:47:41.012477 [ANA_INIT] MIDPI >>>>>>>>
682 04:47:41.012559 [ANA_INIT] MIDPI <<<<<<<<
683 04:47:41.016173 [ANA_INIT] DLL >>>>>>>>
684 04:47:41.019121 [ANA_INIT] flow end
685 04:47:41.022553 ============ LP4 DIFF to SE enter ============
686 04:47:41.025800 ============ LP4 DIFF to SE exit ============
687 04:47:41.029408 [ANA_INIT] <<<<<<<<<<<<<
688 04:47:41.032628 [Flow] Enable top DCM control >>>>>
689 04:47:41.036493 [Flow] Enable top DCM control <<<<<
690 04:47:41.039474 Enable DLL master slave shuffle
691 04:47:41.042938 ==============================================================
692 04:47:41.045965 Gating Mode config
693 04:47:41.052628 ==============================================================
694 04:47:41.052713 Config description:
695 04:47:41.062863 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 04:47:41.069563 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 04:47:41.072776 SELPH_MODE 0: By rank 1: By Phase
698 04:47:41.079417 ==============================================================
699 04:47:41.082664 GAT_TRACK_EN = 1
700 04:47:41.086026 RX_GATING_MODE = 2
701 04:47:41.089539 RX_GATING_TRACK_MODE = 2
702 04:47:41.093127 SELPH_MODE = 1
703 04:47:41.096190 PICG_EARLY_EN = 1
704 04:47:41.099562 VALID_LAT_VALUE = 1
705 04:47:41.102983 ==============================================================
706 04:47:41.106315 Enter into Gating configuration >>>>
707 04:47:41.109702 Exit from Gating configuration <<<<
708 04:47:41.112470 Enter into DVFS_PRE_config >>>>>
709 04:47:41.123161 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 04:47:41.126168 Exit from DVFS_PRE_config <<<<<
711 04:47:41.129407 Enter into PICG configuration >>>>
712 04:47:41.132593 Exit from PICG configuration <<<<
713 04:47:41.136456 [RX_INPUT] configuration >>>>>
714 04:47:41.139897 [RX_INPUT] configuration <<<<<
715 04:47:41.146027 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 04:47:41.149946 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 04:47:41.156643 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 04:47:41.163265 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 04:47:41.169688 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 04:47:41.172925 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 04:47:41.180222 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 04:47:41.183412 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 04:47:41.186612 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 04:47:41.189843 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 04:47:41.196757 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 04:47:41.200136 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 04:47:41.203665 ===================================
728 04:47:41.207027 LPDDR4 DRAM CONFIGURATION
729 04:47:41.209799 ===================================
730 04:47:41.209882 EX_ROW_EN[0] = 0x0
731 04:47:41.213209 EX_ROW_EN[1] = 0x0
732 04:47:41.213291 LP4Y_EN = 0x0
733 04:47:41.216511 WORK_FSP = 0x0
734 04:47:41.216593 WL = 0x2
735 04:47:41.219801 RL = 0x2
736 04:47:41.219883 BL = 0x2
737 04:47:41.224100 RPST = 0x0
738 04:47:41.224536 RD_PRE = 0x0
739 04:47:41.226702 WR_PRE = 0x1
740 04:47:41.227091 WR_PST = 0x0
741 04:47:41.230125 DBI_WR = 0x0
742 04:47:41.230515 DBI_RD = 0x0
743 04:47:41.233548 OTF = 0x1
744 04:47:41.236841 ===================================
745 04:47:41.240085 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 04:47:41.243851 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 04:47:41.250548 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 04:47:41.253828 ===================================
749 04:47:41.254221 LPDDR4 DRAM CONFIGURATION
750 04:47:41.257156 ===================================
751 04:47:41.259990 EX_ROW_EN[0] = 0x10
752 04:47:41.263353 EX_ROW_EN[1] = 0x0
753 04:47:41.263742 LP4Y_EN = 0x0
754 04:47:41.267069 WORK_FSP = 0x0
755 04:47:41.267482 WL = 0x2
756 04:47:41.270091 RL = 0x2
757 04:47:41.270479 BL = 0x2
758 04:47:41.273620 RPST = 0x0
759 04:47:41.274101 RD_PRE = 0x0
760 04:47:41.277220 WR_PRE = 0x1
761 04:47:41.277609 WR_PST = 0x0
762 04:47:41.280279 DBI_WR = 0x0
763 04:47:41.280707 DBI_RD = 0x0
764 04:47:41.283389 OTF = 0x1
765 04:47:41.287100 ===================================
766 04:47:41.293356 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 04:47:41.296821 nWR fixed to 40
768 04:47:41.297213 [ModeRegInit_LP4] CH0 RK0
769 04:47:41.300328 [ModeRegInit_LP4] CH0 RK1
770 04:47:41.303811 [ModeRegInit_LP4] CH1 RK0
771 04:47:41.307034 [ModeRegInit_LP4] CH1 RK1
772 04:47:41.307426 match AC timing 13
773 04:47:41.310317 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 04:47:41.317127 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 04:47:41.320034 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 04:47:41.324018 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 04:47:41.330109 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 04:47:41.330604 [EMI DOE] emi_dcm 0
779 04:47:41.337270 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 04:47:41.337696 ==
781 04:47:41.340641 Dram Type= 6, Freq= 0, CH_0, rank 0
782 04:47:41.343372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 04:47:41.343762 ==
784 04:47:41.350271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 04:47:41.353593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 04:47:41.363501 [CA 0] Center 36 (6~67) winsize 62
787 04:47:41.366698 [CA 1] Center 36 (6~67) winsize 62
788 04:47:41.370195 [CA 2] Center 34 (4~65) winsize 62
789 04:47:41.373484 [CA 3] Center 34 (4~64) winsize 61
790 04:47:41.376793 [CA 4] Center 33 (3~64) winsize 62
791 04:47:41.380668 [CA 5] Center 32 (2~62) winsize 61
792 04:47:41.381058
793 04:47:41.383670 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 04:47:41.384061
795 04:47:41.387127 [CATrainingPosCal] consider 1 rank data
796 04:47:41.390288 u2DelayCellTimex100 = 270/100 ps
797 04:47:41.393375 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 04:47:41.396784 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 04:47:41.404150 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 04:47:41.407142 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
801 04:47:41.410361 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
802 04:47:41.413598 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 04:47:41.414025
804 04:47:41.416971 CA PerBit enable=1, Macro0, CA PI delay=32
805 04:47:41.417504
806 04:47:41.420679 [CBTSetCACLKResult] CA Dly = 32
807 04:47:41.421295 CS Dly: 5 (0~36)
808 04:47:41.421648 ==
809 04:47:41.423669 Dram Type= 6, Freq= 0, CH_0, rank 1
810 04:47:41.430418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 04:47:41.430811 ==
812 04:47:41.434283 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 04:47:41.440668 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 04:47:41.450083 [CA 0] Center 36 (6~67) winsize 62
815 04:47:41.453414 [CA 1] Center 36 (6~67) winsize 62
816 04:47:41.456784 [CA 2] Center 34 (4~65) winsize 62
817 04:47:41.460163 [CA 3] Center 33 (3~64) winsize 62
818 04:47:41.463546 [CA 4] Center 32 (2~63) winsize 62
819 04:47:41.466876 [CA 5] Center 32 (2~63) winsize 62
820 04:47:41.467441
821 04:47:41.469930 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 04:47:41.470423
823 04:47:41.473812 [CATrainingPosCal] consider 2 rank data
824 04:47:41.476813 u2DelayCellTimex100 = 270/100 ps
825 04:47:41.480271 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 04:47:41.483743 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 04:47:41.490347 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 04:47:41.493566 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
829 04:47:41.496633 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 04:47:41.500009 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 04:47:41.500585
832 04:47:41.503503 CA PerBit enable=1, Macro0, CA PI delay=32
833 04:47:41.504021
834 04:47:41.506887 [CBTSetCACLKResult] CA Dly = 32
835 04:47:41.507423 CS Dly: 5 (0~36)
836 04:47:41.507770
837 04:47:41.510883 ----->DramcWriteLeveling(PI) begin...
838 04:47:41.514403 ==
839 04:47:41.514926 Dram Type= 6, Freq= 0, CH_0, rank 0
840 04:47:41.521409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 04:47:41.521984 ==
842 04:47:41.522323 Write leveling (Byte 0): 34 => 34
843 04:47:41.525003 Write leveling (Byte 1): 30 => 30
844 04:47:41.528629 DramcWriteLeveling(PI) end<-----
845 04:47:41.529095
846 04:47:41.529562 ==
847 04:47:41.532158 Dram Type= 6, Freq= 0, CH_0, rank 0
848 04:47:41.535362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 04:47:41.535824 ==
850 04:47:41.538619 [Gating] SW mode calibration
851 04:47:41.546135 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 04:47:41.552440 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 04:47:41.556397 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 04:47:41.559243 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 04:47:41.566295 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 04:47:41.569108 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 04:47:41.572474 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 04:47:41.576420 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 04:47:50.036381 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 04:47:50.036508 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 04:47:50.036576 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 04:47:50.036638 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 04:47:50.036698 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 04:47:50.036756 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 04:47:50.036813 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 04:47:50.036868 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 04:47:50.036923 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 04:47:50.036978 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 04:47:50.037032 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 04:47:50.037087 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
871 04:47:50.037141 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 04:47:50.037196 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 04:47:50.037249 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 04:47:50.037303 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 04:47:50.037357 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 04:47:50.037410 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 04:47:50.037463 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 04:47:50.037517 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 04:47:50.037577 0 9 8 | B1->B0 | 2323 2e2e | 1 1 | (1 1) (1 1)
880 04:47:50.037640 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
881 04:47:50.037694 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 04:47:50.037747 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 04:47:50.037800 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 04:47:50.037853 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 04:47:50.037907 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 04:47:50.037960 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
887 04:47:50.038014 0 10 8 | B1->B0 | 3030 2828 | 1 0 | (1 1) (1 0)
888 04:47:50.038067 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 04:47:50.038120 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 04:47:50.038174 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 04:47:50.038227 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 04:47:50.038280 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 04:47:50.038333 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 04:47:50.038387 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
895 04:47:50.038441 0 11 8 | B1->B0 | 2b2b 4040 | 0 0 | (0 0) (0 0)
896 04:47:50.038494 0 11 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
897 04:47:50.038547 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 04:47:50.038600 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 04:47:50.038653 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 04:47:50.038706 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 04:47:50.038759 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 04:47:50.038813 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 04:47:50.038866 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 04:47:50.038920 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 04:47:50.038974 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 04:47:50.039027 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 04:47:50.039081 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 04:47:50.039135 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 04:47:50.039188 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 04:47:50.039242 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 04:47:50.039295 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 04:47:50.039350 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 04:47:50.039404 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 04:47:50.039457 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 04:47:50.039510 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 04:47:50.039564 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 04:47:50.039617 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 04:47:50.039670 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 04:47:50.039724 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 04:47:50.039777 Total UI for P1: 0, mck2ui 16
921 04:47:50.039832 best dqsien dly found for B0: ( 0, 14, 4)
922 04:47:50.039885 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 04:47:50.039939 Total UI for P1: 0, mck2ui 16
924 04:47:50.039993 best dqsien dly found for B1: ( 0, 14, 8)
925 04:47:50.040046 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 04:47:50.040099 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 04:47:50.040152
928 04:47:50.040205 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 04:47:50.040259 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 04:47:50.040342 [Gating] SW calibration Done
931 04:47:50.040410 ==
932 04:47:50.040464 Dram Type= 6, Freq= 0, CH_0, rank 0
933 04:47:50.040518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 04:47:50.040573 ==
935 04:47:50.040626 RX Vref Scan: 0
936 04:47:50.040679
937 04:47:50.040731 RX Vref 0 -> 0, step: 1
938 04:47:50.040784
939 04:47:50.040836 RX Delay -130 -> 252, step: 16
940 04:47:50.040889 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
941 04:47:50.040943 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
942 04:47:50.040996 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
943 04:47:50.041049 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
944 04:47:50.041103 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
945 04:47:50.041156 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
946 04:47:50.041209 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
947 04:47:50.041262 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
948 04:47:50.041524 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
949 04:47:50.041585 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
950 04:47:50.041648 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
951 04:47:50.041771 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
952 04:47:50.041828 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
953 04:47:50.041883 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
954 04:47:50.041938 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
955 04:47:50.042024 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
956 04:47:50.042113 ==
957 04:47:50.042183 Dram Type= 6, Freq= 0, CH_0, rank 0
958 04:47:50.042256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 04:47:50.042343 ==
960 04:47:50.042397 DQS Delay:
961 04:47:50.042452 DQS0 = 0, DQS1 = 0
962 04:47:50.042506 DQM Delay:
963 04:47:50.042561 DQM0 = 91, DQM1 = 85
964 04:47:50.042616 DQ Delay:
965 04:47:50.042671 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
966 04:47:50.042726 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
967 04:47:50.042781 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
968 04:47:50.042836 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
969 04:47:50.042890
970 04:47:50.042945
971 04:47:50.043000 ==
972 04:47:50.043055 Dram Type= 6, Freq= 0, CH_0, rank 0
973 04:47:50.043110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 04:47:50.043165 ==
975 04:47:50.043219
976 04:47:50.043273
977 04:47:50.043327 TX Vref Scan disable
978 04:47:50.043382 == TX Byte 0 ==
979 04:47:50.043438 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
980 04:47:50.043493 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
981 04:47:50.043548 == TX Byte 1 ==
982 04:47:50.043603 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 04:47:50.043658 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 04:47:50.043713 ==
985 04:47:50.043768 Dram Type= 6, Freq= 0, CH_0, rank 0
986 04:47:50.043823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 04:47:50.043878 ==
988 04:47:50.043933 TX Vref=22, minBit 8, minWin=27, winSum=448
989 04:47:50.043988 TX Vref=24, minBit 8, minWin=27, winSum=450
990 04:47:50.044044 TX Vref=26, minBit 4, minWin=28, winSum=453
991 04:47:50.044098 TX Vref=28, minBit 0, minWin=28, winSum=455
992 04:47:50.044153 TX Vref=30, minBit 5, minWin=28, winSum=457
993 04:47:50.044208 TX Vref=32, minBit 10, minWin=27, winSum=454
994 04:47:50.044263 [TxChooseVref] Worse bit 5, Min win 28, Win sum 457, Final Vref 30
995 04:47:50.044330
996 04:47:50.044386 Final TX Range 1 Vref 30
997 04:47:50.044442
998 04:47:50.044496 ==
999 04:47:50.044551 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 04:47:50.044607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 04:47:50.044662 ==
1002 04:47:50.044717
1003 04:47:50.044771
1004 04:47:50.044826 TX Vref Scan disable
1005 04:47:50.044881 == TX Byte 0 ==
1006 04:47:50.044936 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1007 04:47:50.044991 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1008 04:47:50.045046 == TX Byte 1 ==
1009 04:47:50.045100 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 04:47:50.045155 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 04:47:50.045211
1012 04:47:50.045269 [DATLAT]
1013 04:47:50.045324 Freq=800, CH0 RK0
1014 04:47:50.045380
1015 04:47:50.045434 DATLAT Default: 0xa
1016 04:47:50.045489 0, 0xFFFF, sum = 0
1017 04:47:50.045545 1, 0xFFFF, sum = 0
1018 04:47:50.045604 2, 0xFFFF, sum = 0
1019 04:47:50.045674 3, 0xFFFF, sum = 0
1020 04:47:50.045729 4, 0xFFFF, sum = 0
1021 04:47:50.045852 5, 0xFFFF, sum = 0
1022 04:47:50.045946 6, 0xFFFF, sum = 0
1023 04:47:50.046006 7, 0xFFFF, sum = 0
1024 04:47:50.046062 8, 0xFFFF, sum = 0
1025 04:47:50.046127 9, 0x0, sum = 1
1026 04:47:50.046186 10, 0x0, sum = 2
1027 04:47:50.046242 11, 0x0, sum = 3
1028 04:47:50.046297 12, 0x0, sum = 4
1029 04:47:50.046352 best_step = 10
1030 04:47:50.046405
1031 04:47:50.046458 ==
1032 04:47:50.046511 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 04:47:50.046565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 04:47:50.046618 ==
1035 04:47:50.046672 RX Vref Scan: 1
1036 04:47:50.046725
1037 04:47:50.046778 Set Vref Range= 32 -> 127
1038 04:47:50.046831
1039 04:47:50.046884 RX Vref 32 -> 127, step: 1
1040 04:47:50.046938
1041 04:47:50.046990 RX Delay -95 -> 252, step: 8
1042 04:47:50.047044
1043 04:47:50.047096 Set Vref, RX VrefLevel [Byte0]: 32
1044 04:47:50.047150 [Byte1]: 32
1045 04:47:50.047203
1046 04:47:50.047256 Set Vref, RX VrefLevel [Byte0]: 33
1047 04:47:50.047309 [Byte1]: 33
1048 04:47:50.047362
1049 04:47:50.047415 Set Vref, RX VrefLevel [Byte0]: 34
1050 04:47:50.047486 [Byte1]: 34
1051 04:47:50.047554
1052 04:47:50.047606 Set Vref, RX VrefLevel [Byte0]: 35
1053 04:47:50.047660 [Byte1]: 35
1054 04:47:50.047713
1055 04:47:50.047765 Set Vref, RX VrefLevel [Byte0]: 36
1056 04:47:50.047818 [Byte1]: 36
1057 04:47:50.047871
1058 04:47:50.047924 Set Vref, RX VrefLevel [Byte0]: 37
1059 04:47:50.047997 [Byte1]: 37
1060 04:47:50.048065
1061 04:47:50.048117 Set Vref, RX VrefLevel [Byte0]: 38
1062 04:47:50.048171 [Byte1]: 38
1063 04:47:50.048223
1064 04:47:50.048276 Set Vref, RX VrefLevel [Byte0]: 39
1065 04:47:50.048367 [Byte1]: 39
1066 04:47:50.048421
1067 04:47:50.048473 Set Vref, RX VrefLevel [Byte0]: 40
1068 04:47:50.048526 [Byte1]: 40
1069 04:47:50.048579
1070 04:47:50.048631 Set Vref, RX VrefLevel [Byte0]: 41
1071 04:47:50.048685 [Byte1]: 41
1072 04:47:50.048738
1073 04:47:50.048791 Set Vref, RX VrefLevel [Byte0]: 42
1074 04:47:50.048844 [Byte1]: 42
1075 04:47:50.048897
1076 04:47:50.048950 Set Vref, RX VrefLevel [Byte0]: 43
1077 04:47:50.049003 [Byte1]: 43
1078 04:47:50.049056
1079 04:47:50.049109 Set Vref, RX VrefLevel [Byte0]: 44
1080 04:47:50.049162 [Byte1]: 44
1081 04:47:50.049215
1082 04:47:50.049268 Set Vref, RX VrefLevel [Byte0]: 45
1083 04:47:50.049321 [Byte1]: 45
1084 04:47:50.049374
1085 04:47:50.049426 Set Vref, RX VrefLevel [Byte0]: 46
1086 04:47:50.049479 [Byte1]: 46
1087 04:47:50.049532
1088 04:47:50.049585 Set Vref, RX VrefLevel [Byte0]: 47
1089 04:47:50.049638 [Byte1]: 47
1090 04:47:50.049691
1091 04:47:50.049743 Set Vref, RX VrefLevel [Byte0]: 48
1092 04:47:50.049816 [Byte1]: 48
1093 04:47:50.049901
1094 04:47:50.049969 Set Vref, RX VrefLevel [Byte0]: 49
1095 04:47:50.050021 [Byte1]: 49
1096 04:47:50.050074
1097 04:47:50.050127 Set Vref, RX VrefLevel [Byte0]: 50
1098 04:47:50.050180 [Byte1]: 50
1099 04:47:50.050232
1100 04:47:50.050285 Set Vref, RX VrefLevel [Byte0]: 51
1101 04:47:50.050338 [Byte1]: 51
1102 04:47:50.050391
1103 04:47:50.050444 Set Vref, RX VrefLevel [Byte0]: 52
1104 04:47:50.050496 [Byte1]: 52
1105 04:47:50.050549
1106 04:47:50.050602 Set Vref, RX VrefLevel [Byte0]: 53
1107 04:47:50.050655 [Byte1]: 53
1108 04:47:50.050708
1109 04:47:50.050760 Set Vref, RX VrefLevel [Byte0]: 54
1110 04:47:50.051007 [Byte1]: 54
1111 04:47:50.051105
1112 04:47:50.051159 Set Vref, RX VrefLevel [Byte0]: 55
1113 04:47:50.051214 [Byte1]: 55
1114 04:47:50.051267
1115 04:47:50.051320 Set Vref, RX VrefLevel [Byte0]: 56
1116 04:47:50.051372 [Byte1]: 56
1117 04:47:50.051425
1118 04:47:50.051478 Set Vref, RX VrefLevel [Byte0]: 57
1119 04:47:50.051531 [Byte1]: 57
1120 04:47:50.051584
1121 04:47:50.051637 Set Vref, RX VrefLevel [Byte0]: 58
1122 04:47:50.051690 [Byte1]: 58
1123 04:47:50.051743
1124 04:47:50.051795 Set Vref, RX VrefLevel [Byte0]: 59
1125 04:47:50.051848 [Byte1]: 59
1126 04:47:50.051900
1127 04:47:50.051953 Set Vref, RX VrefLevel [Byte0]: 60
1128 04:47:50.052005 [Byte1]: 60
1129 04:47:50.052058
1130 04:47:50.052110 Set Vref, RX VrefLevel [Byte0]: 61
1131 04:47:50.052164 [Byte1]: 61
1132 04:47:50.052217
1133 04:47:50.052269 Set Vref, RX VrefLevel [Byte0]: 62
1134 04:47:50.052365 [Byte1]: 62
1135 04:47:50.052419
1136 04:47:50.052472 Set Vref, RX VrefLevel [Byte0]: 63
1137 04:47:50.052525 [Byte1]: 63
1138 04:47:50.052578
1139 04:47:50.052631 Set Vref, RX VrefLevel [Byte0]: 64
1140 04:47:50.052684 [Byte1]: 64
1141 04:47:50.052737
1142 04:47:50.052807 Set Vref, RX VrefLevel [Byte0]: 65
1143 04:47:50.052877 [Byte1]: 65
1144 04:47:50.052930
1145 04:47:50.052982 Set Vref, RX VrefLevel [Byte0]: 66
1146 04:47:50.053036 [Byte1]: 66
1147 04:47:50.053089
1148 04:47:50.053141 Set Vref, RX VrefLevel [Byte0]: 67
1149 04:47:50.053194 [Byte1]: 67
1150 04:47:50.053247
1151 04:47:50.053299 Set Vref, RX VrefLevel [Byte0]: 68
1152 04:47:50.053352 [Byte1]: 68
1153 04:47:50.053405
1154 04:47:50.053457 Set Vref, RX VrefLevel [Byte0]: 69
1155 04:47:50.053509 [Byte1]: 69
1156 04:47:50.053562
1157 04:47:50.053615 Set Vref, RX VrefLevel [Byte0]: 70
1158 04:47:50.053668 [Byte1]: 70
1159 04:47:50.053720
1160 04:47:50.053773 Set Vref, RX VrefLevel [Byte0]: 71
1161 04:47:50.053827 [Byte1]: 71
1162 04:47:50.053879
1163 04:47:50.053932 Set Vref, RX VrefLevel [Byte0]: 72
1164 04:47:50.053985 [Byte1]: 72
1165 04:47:50.054038
1166 04:47:50.054090 Set Vref, RX VrefLevel [Byte0]: 73
1167 04:47:50.054143 [Byte1]: 73
1168 04:47:50.054196
1169 04:47:50.054248 Set Vref, RX VrefLevel [Byte0]: 74
1170 04:47:50.054302 [Byte1]: 74
1171 04:47:50.054354
1172 04:47:50.054407 Set Vref, RX VrefLevel [Byte0]: 75
1173 04:47:50.054477 [Byte1]: 75
1174 04:47:50.054546
1175 04:47:50.054598 Set Vref, RX VrefLevel [Byte0]: 76
1176 04:47:50.054651 [Byte1]: 76
1177 04:47:50.054704
1178 04:47:50.054757 Set Vref, RX VrefLevel [Byte0]: 77
1179 04:47:50.054810 [Byte1]: 77
1180 04:47:50.054863
1181 04:47:50.054914 Set Vref, RX VrefLevel [Byte0]: 78
1182 04:47:50.054967 [Byte1]: 78
1183 04:47:50.055020
1184 04:47:50.055072 Final RX Vref Byte 0 = 52 to rank0
1185 04:47:50.055125 Final RX Vref Byte 1 = 60 to rank0
1186 04:47:50.055179 Final RX Vref Byte 0 = 52 to rank1
1187 04:47:50.055232 Final RX Vref Byte 1 = 60 to rank1==
1188 04:47:50.055304 Dram Type= 6, Freq= 0, CH_0, rank 0
1189 04:47:50.055371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1190 04:47:50.055425 ==
1191 04:47:50.055478 DQS Delay:
1192 04:47:50.055530 DQS0 = 0, DQS1 = 0
1193 04:47:50.055583 DQM Delay:
1194 04:47:50.055635 DQM0 = 91, DQM1 = 86
1195 04:47:50.055688 DQ Delay:
1196 04:47:50.055741 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1197 04:47:50.055826 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1198 04:47:50.055880 DQ8 =76, DQ9 =80, DQ10 =84, DQ11 =80
1199 04:47:50.055933 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1200 04:47:50.055986
1201 04:47:50.056038
1202 04:47:50.056090 [DQSOSCAuto] RK0, (LSB)MR18= 0x483e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 391 ps
1203 04:47:50.056146 CH0 RK0: MR19=606, MR18=483E
1204 04:47:50.056200 CH0_RK0: MR19=0x606, MR18=0x483E, DQSOSC=391, MR23=63, INC=96, DEC=64
1205 04:47:50.056253
1206 04:47:50.056332 ----->DramcWriteLeveling(PI) begin...
1207 04:47:50.056418 ==
1208 04:47:50.056473 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 04:47:50.056540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1210 04:47:50.056594 ==
1211 04:47:50.056647 Write leveling (Byte 0): 33 => 33
1212 04:47:50.056701 Write leveling (Byte 1): 30 => 30
1213 04:47:50.056753 DramcWriteLeveling(PI) end<-----
1214 04:47:50.056806
1215 04:47:50.056859 ==
1216 04:47:50.056912 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 04:47:50.056982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1218 04:47:50.057050 ==
1219 04:47:50.057103 [Gating] SW mode calibration
1220 04:47:50.057156 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1221 04:47:50.057210 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1222 04:47:50.057263 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 04:47:50.057317 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1224 04:47:50.057370 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1225 04:47:50.057423 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 04:47:50.057476 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 04:47:50.057529 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 04:47:50.057582 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 04:47:50.057635 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 04:47:50.057688 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 04:47:50.057741 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 04:47:50.057794 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 04:47:50.057848 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 04:47:50.057900 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 04:47:50.057953 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 04:47:50.058006 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 04:47:50.058059 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 04:47:50.058112 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 04:47:50.058165 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1240 04:47:50.058218 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1241 04:47:50.058271 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 04:47:50.058324 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 04:47:50.058567 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 04:47:50.058660 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 04:47:50.058715 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 04:47:50.058769 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 04:47:50.058822 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 04:47:50.058875 0 9 8 | B1->B0 | 2e2e 2929 | 0 1 | (0 0) (0 0)
1249 04:47:50.058929 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 04:47:50.058982 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 04:47:50.059036 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 04:47:50.059089 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 04:47:50.059142 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 04:47:50.059213 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 04:47:50.059281 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1256 04:47:50.059334 0 10 8 | B1->B0 | 2a2a 2828 | 0 0 | (1 0) (0 0)
1257 04:47:50.059387 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 04:47:50.059441 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 04:47:50.059494 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 04:47:50.059548 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 04:47:50.059601 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 04:47:50.059655 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 04:47:50.059708 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
1264 04:47:50.059761 0 11 8 | B1->B0 | 3d3d 3f3f | 1 0 | (0 0) (0 0)
1265 04:47:50.059814 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 04:47:50.059868 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 04:47:50.059921 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 04:47:50.059974 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 04:47:50.060028 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 04:47:50.060080 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 04:47:50.060133 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 04:47:50.060186 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1273 04:47:50.060240 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 04:47:50.060299 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 04:47:50.060387 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 04:47:50.060439 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 04:47:50.060495 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 04:47:50.060548 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 04:47:50.060601 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 04:47:50.060654 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 04:47:50.060706 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 04:47:50.060759 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 04:47:50.060811 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 04:47:50.060863 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 04:47:50.060916 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 04:47:50.060969 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 04:47:50.061022 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 04:47:50.061074 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1289 04:47:50.061127 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1290 04:47:50.061180 Total UI for P1: 0, mck2ui 16
1291 04:47:50.061233 best dqsien dly found for B0: ( 0, 14, 8)
1292 04:47:50.061287 Total UI for P1: 0, mck2ui 16
1293 04:47:50.061339 best dqsien dly found for B1: ( 0, 14, 8)
1294 04:47:50.061392 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1295 04:47:50.061445 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1296 04:47:50.061497
1297 04:47:50.061550 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1298 04:47:50.061603 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1299 04:47:50.061656 [Gating] SW calibration Done
1300 04:47:50.061709 ==
1301 04:47:50.061761 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 04:47:50.061814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 04:47:50.061868 ==
1304 04:47:50.061920 RX Vref Scan: 0
1305 04:47:50.061973
1306 04:47:50.062024 RX Vref 0 -> 0, step: 1
1307 04:47:50.062077
1308 04:47:50.062129 RX Delay -130 -> 252, step: 16
1309 04:47:50.062182 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1310 04:47:50.062234 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1311 04:47:50.062289 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1312 04:47:50.062341 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1313 04:47:50.062394 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1314 04:47:50.062446 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1315 04:47:50.062498 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1316 04:47:50.062550 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1317 04:47:50.062603 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1318 04:47:50.062655 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1319 04:47:50.062707 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1320 04:47:50.062759 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1321 04:47:50.062812 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1322 04:47:50.062864 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1323 04:47:50.062916 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1324 04:47:50.062968 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1325 04:47:50.063020 ==
1326 04:47:50.063073 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 04:47:50.063125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 04:47:50.063178 ==
1329 04:47:50.063231 DQS Delay:
1330 04:47:50.063283 DQS0 = 0, DQS1 = 0
1331 04:47:50.063335 DQM Delay:
1332 04:47:50.063387 DQM0 = 88, DQM1 = 81
1333 04:47:50.063440 DQ Delay:
1334 04:47:50.063492 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1335 04:47:50.063545 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1336 04:47:50.063598 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1337 04:47:50.063650 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1338 04:47:50.063703
1339 04:47:50.063755
1340 04:47:50.063807 ==
1341 04:47:50.063859 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 04:47:50.063911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 04:47:50.063964 ==
1344 04:47:50.064017
1345 04:47:50.064069
1346 04:47:50.064120 TX Vref Scan disable
1347 04:47:50.064349 == TX Byte 0 ==
1348 04:47:50.064422 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1349 04:47:50.064477 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1350 04:47:50.064553 == TX Byte 1 ==
1351 04:47:50.064621 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1352 04:47:50.064675 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1353 04:47:50.064727 ==
1354 04:47:50.064779 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 04:47:50.064832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 04:47:50.064886 ==
1357 04:47:50.064938 TX Vref=22, minBit 8, minWin=27, winSum=447
1358 04:47:50.064992 TX Vref=24, minBit 12, minWin=27, winSum=450
1359 04:47:50.065045 TX Vref=26, minBit 11, minWin=27, winSum=454
1360 04:47:50.065098 TX Vref=28, minBit 7, minWin=28, winSum=460
1361 04:47:50.065152 TX Vref=30, minBit 4, minWin=28, winSum=458
1362 04:47:50.065205 TX Vref=32, minBit 4, minWin=28, winSum=456
1363 04:47:50.065258 [TxChooseVref] Worse bit 7, Min win 28, Win sum 460, Final Vref 28
1364 04:47:50.065311
1365 04:47:50.065363 Final TX Range 1 Vref 28
1366 04:47:50.065416
1367 04:47:50.065468 ==
1368 04:47:50.065521 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 04:47:50.065573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 04:47:50.065626 ==
1371 04:47:50.065678
1372 04:47:50.065731
1373 04:47:50.065783 TX Vref Scan disable
1374 04:47:50.065835 == TX Byte 0 ==
1375 04:47:50.065887 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1376 04:47:50.065940 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1377 04:47:50.065992 == TX Byte 1 ==
1378 04:47:50.066045 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1379 04:47:50.066097 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1380 04:47:50.066151
1381 04:47:50.066203 [DATLAT]
1382 04:47:50.066255 Freq=800, CH0 RK1
1383 04:47:50.066307
1384 04:47:50.066359 DATLAT Default: 0xa
1385 04:47:50.066411 0, 0xFFFF, sum = 0
1386 04:47:50.066465 1, 0xFFFF, sum = 0
1387 04:47:50.066519 2, 0xFFFF, sum = 0
1388 04:47:50.066589 3, 0xFFFF, sum = 0
1389 04:47:50.066689 4, 0xFFFF, sum = 0
1390 04:47:50.066742 5, 0xFFFF, sum = 0
1391 04:47:50.066795 6, 0xFFFF, sum = 0
1392 04:47:50.066849 7, 0xFFFF, sum = 0
1393 04:47:50.066903 8, 0xFFFF, sum = 0
1394 04:47:50.066957 9, 0x0, sum = 1
1395 04:47:50.067010 10, 0x0, sum = 2
1396 04:47:50.067073 11, 0x0, sum = 3
1397 04:47:50.067132 12, 0x0, sum = 4
1398 04:47:50.067186 best_step = 10
1399 04:47:50.067239
1400 04:47:50.067291 ==
1401 04:47:50.067343 Dram Type= 6, Freq= 0, CH_0, rank 1
1402 04:47:50.067396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 04:47:50.067449 ==
1404 04:47:50.067501 RX Vref Scan: 0
1405 04:47:50.067553
1406 04:47:50.067605 RX Vref 0 -> 0, step: 1
1407 04:47:50.067657
1408 04:47:50.067710 RX Delay -95 -> 252, step: 8
1409 04:47:50.067762 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1410 04:47:50.067815 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1411 04:47:50.067868 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1412 04:47:50.067920 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1413 04:47:50.067973 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1414 04:47:50.068025 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1415 04:47:50.068078 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1416 04:47:50.068131 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1417 04:47:50.068183 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1418 04:47:50.068235 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1419 04:47:50.068294 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1420 04:47:50.068380 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1421 04:47:50.068433 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1422 04:47:50.068486 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1423 04:47:50.068538 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1424 04:47:50.068590 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1425 04:47:50.068642 ==
1426 04:47:50.068695 Dram Type= 6, Freq= 0, CH_0, rank 1
1427 04:47:50.068748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 04:47:50.068800 ==
1429 04:47:50.068853 DQS Delay:
1430 04:47:50.068904 DQS0 = 0, DQS1 = 0
1431 04:47:50.068957 DQM Delay:
1432 04:47:50.069008 DQM0 = 93, DQM1 = 82
1433 04:47:50.069061 DQ Delay:
1434 04:47:50.069114 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1435 04:47:50.069167 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1436 04:47:50.069219 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1437 04:47:50.069272 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1438 04:47:50.069325
1439 04:47:50.069377
1440 04:47:50.069428 [DQSOSCAuto] RK1, (LSB)MR18= 0x4515, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1441 04:47:50.069482 CH0 RK1: MR19=606, MR18=4515
1442 04:47:50.069535 CH0_RK1: MR19=0x606, MR18=0x4515, DQSOSC=392, MR23=63, INC=96, DEC=64
1443 04:47:50.069588 [RxdqsGatingPostProcess] freq 800
1444 04:47:50.069641 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1445 04:47:50.069694 Pre-setting of DQS Precalculation
1446 04:47:50.069746 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1447 04:47:50.069798 ==
1448 04:47:50.069851 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 04:47:50.069904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 04:47:50.069956 ==
1451 04:47:50.070009 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1452 04:47:50.070062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1453 04:47:50.070115 [CA 0] Center 36 (6~67) winsize 62
1454 04:47:50.070168 [CA 1] Center 36 (6~67) winsize 62
1455 04:47:50.070221 [CA 2] Center 35 (5~65) winsize 61
1456 04:47:50.070274 [CA 3] Center 34 (4~65) winsize 62
1457 04:47:50.070326 [CA 4] Center 35 (5~65) winsize 61
1458 04:47:50.070379 [CA 5] Center 34 (4~65) winsize 62
1459 04:47:50.070431
1460 04:47:50.070483 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1461 04:47:50.070536
1462 04:47:50.070588 [CATrainingPosCal] consider 1 rank data
1463 04:47:50.070641 u2DelayCellTimex100 = 270/100 ps
1464 04:47:50.070694 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1465 04:47:50.070746 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1466 04:47:50.070798 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1467 04:47:50.070862 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1468 04:47:50.070917 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1469 04:47:50.070969 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1470 04:47:50.071034
1471 04:47:50.071086 CA PerBit enable=1, Macro0, CA PI delay=34
1472 04:47:50.071142
1473 04:47:50.071203 [CBTSetCACLKResult] CA Dly = 34
1474 04:47:50.071256 CS Dly: 5 (0~36)
1475 04:47:50.071312 ==
1476 04:47:50.071372 Dram Type= 6, Freq= 0, CH_1, rank 1
1477 04:47:50.071426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1478 04:47:50.071480 ==
1479 04:47:50.071533 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1480 04:47:50.071782 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1481 04:47:50.071844 [CA 0] Center 36 (6~67) winsize 62
1482 04:47:50.071900 [CA 1] Center 36 (6~67) winsize 62
1483 04:47:50.071953 [CA 2] Center 35 (5~66) winsize 62
1484 04:47:50.072006 [CA 3] Center 35 (5~65) winsize 61
1485 04:47:50.072060 [CA 4] Center 35 (5~66) winsize 62
1486 04:47:50.072113 [CA 5] Center 34 (4~65) winsize 62
1487 04:47:50.072169
1488 04:47:50.072257 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1489 04:47:50.072364
1490 04:47:50.072418 [CATrainingPosCal] consider 2 rank data
1491 04:47:50.072485 u2DelayCellTimex100 = 270/100 ps
1492 04:47:50.072540 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1493 04:47:50.072594 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1494 04:47:50.072652 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1495 04:47:50.072711 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1496 04:47:50.072764 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1497 04:47:50.072817 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1498 04:47:50.072869
1499 04:47:50.072922 CA PerBit enable=1, Macro0, CA PI delay=34
1500 04:47:50.072975
1501 04:47:50.073026 [CBTSetCACLKResult] CA Dly = 34
1502 04:47:50.073079 CS Dly: 6 (0~38)
1503 04:47:50.073131
1504 04:47:50.073184 ----->DramcWriteLeveling(PI) begin...
1505 04:47:50.073238 ==
1506 04:47:50.073291 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 04:47:50.073344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1508 04:47:50.073398 ==
1509 04:47:50.073450 Write leveling (Byte 0): 30 => 30
1510 04:47:50.073503 Write leveling (Byte 1): 29 => 29
1511 04:47:50.073564 DramcWriteLeveling(PI) end<-----
1512 04:47:50.073620
1513 04:47:50.073673 ==
1514 04:47:50.073738 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 04:47:50.073792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1516 04:47:50.073853 ==
1517 04:47:50.073908 [Gating] SW mode calibration
1518 04:47:50.073961 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1519 04:47:50.074015 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1520 04:47:50.074069 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1521 04:47:50.074122 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 04:47:50.074188 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 04:47:50.074242 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 04:47:50.074295 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 04:47:50.074349 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 04:47:50.074401 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 04:47:50.074454 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 04:47:50.074507 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 04:47:50.074560 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 04:47:50.074613 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 04:47:50.074666 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 04:47:50.074719 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 04:47:50.074772 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 04:47:50.074824 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 04:47:50.074877 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1536 04:47:50.074930 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1537 04:47:50.074983 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1538 04:47:50.075036 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 04:47:50.075089 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 04:47:50.075142 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 04:47:50.075194 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 04:47:50.075247 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 04:47:50.075300 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 04:47:50.075353 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 04:47:50.075405 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1546 04:47:50.075457 0 9 8 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
1547 04:47:50.075510 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 04:47:50.075563 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 04:47:50.075616 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 04:47:50.075669 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 04:47:50.075721 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 04:47:50.075774 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1553 04:47:50.075827 0 10 4 | B1->B0 | 3030 2b2b | 0 0 | (0 0) (0 1)
1554 04:47:50.075879 0 10 8 | B1->B0 | 2626 2323 | 1 0 | (0 0) (1 0)
1555 04:47:50.075932 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 04:47:50.075985 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 04:47:50.076038 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 04:47:50.076091 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 04:47:50.076144 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 04:47:50.076196 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 04:47:50.076249 0 11 4 | B1->B0 | 2c2c 3838 | 0 0 | (0 0) (1 1)
1562 04:47:50.076329 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1563 04:47:50.076398 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 04:47:50.076451 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 04:47:50.076504 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 04:47:50.076557 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 04:47:50.076610 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 04:47:50.076663 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 04:47:50.076716 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1570 04:47:50.076769 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 04:47:50.076822 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 04:47:50.076875 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 04:47:50.076927 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 04:47:50.076980 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 04:47:50.077033 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 04:47:50.077277 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 04:47:50.077336 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 04:47:50.077390 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 04:47:50.077443 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 04:47:50.077497 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 04:47:50.077550 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 04:47:50.077602 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 04:47:50.077655 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 04:47:50.077707 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1585 04:47:50.077760 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1586 04:47:50.077812 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1587 04:47:50.077865 Total UI for P1: 0, mck2ui 16
1588 04:47:50.077917 best dqsien dly found for B0: ( 0, 14, 2)
1589 04:47:50.077970 Total UI for P1: 0, mck2ui 16
1590 04:47:50.078023 best dqsien dly found for B1: ( 0, 14, 2)
1591 04:47:50.078075 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1592 04:47:50.078128 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1593 04:47:50.078180
1594 04:47:50.078233 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1595 04:47:50.078285 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1596 04:47:50.078338 [Gating] SW calibration Done
1597 04:47:50.078390 ==
1598 04:47:50.078442 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 04:47:50.078495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 04:47:50.078548 ==
1601 04:47:50.078601 RX Vref Scan: 0
1602 04:47:50.078653
1603 04:47:50.078705 RX Vref 0 -> 0, step: 1
1604 04:47:50.078758
1605 04:47:50.078810 RX Delay -130 -> 252, step: 16
1606 04:47:50.078862 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1607 04:47:50.078915 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1608 04:47:50.078968 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1609 04:47:50.079020 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1610 04:47:50.079072 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1611 04:47:50.079125 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1612 04:47:50.079177 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1613 04:47:50.079229 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1614 04:47:50.079282 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1615 04:47:50.079334 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1616 04:47:50.079386 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1617 04:47:50.079439 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1618 04:47:50.079492 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1619 04:47:50.079545 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1620 04:47:50.079597 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1621 04:47:50.079650 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1622 04:47:50.079702 ==
1623 04:47:50.079755 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 04:47:50.079808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 04:47:50.079861 ==
1626 04:47:50.079913 DQS Delay:
1627 04:47:50.079965 DQS0 = 0, DQS1 = 0
1628 04:47:50.080018 DQM Delay:
1629 04:47:50.080070 DQM0 = 93, DQM1 = 87
1630 04:47:50.080122 DQ Delay:
1631 04:47:50.080174 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1632 04:47:50.080227 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1633 04:47:50.080280 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1634 04:47:50.080377 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1635 04:47:50.080430
1636 04:47:50.080483
1637 04:47:50.080535 ==
1638 04:47:50.080587 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 04:47:50.080639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 04:47:50.080692 ==
1641 04:47:50.080745
1642 04:47:50.080797
1643 04:47:50.080849 TX Vref Scan disable
1644 04:47:50.080901 == TX Byte 0 ==
1645 04:47:50.080954 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1646 04:47:50.081007 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1647 04:47:50.081060 == TX Byte 1 ==
1648 04:47:50.081113 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1649 04:47:50.081165 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1650 04:47:50.081218 ==
1651 04:47:50.081270 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 04:47:50.081323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 04:47:50.081376 ==
1654 04:47:50.081428 TX Vref=22, minBit 0, minWin=27, winSum=443
1655 04:47:50.081481 TX Vref=24, minBit 1, minWin=27, winSum=444
1656 04:47:50.081533 TX Vref=26, minBit 2, minWin=27, winSum=446
1657 04:47:50.081586 TX Vref=28, minBit 1, minWin=27, winSum=446
1658 04:47:50.081640 TX Vref=30, minBit 1, minWin=27, winSum=447
1659 04:47:50.081693 TX Vref=32, minBit 1, minWin=27, winSum=449
1660 04:47:50.081745 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 32
1661 04:47:50.081798
1662 04:47:50.081850 Final TX Range 1 Vref 32
1663 04:47:50.081903
1664 04:47:50.081955 ==
1665 04:47:50.082007 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 04:47:50.082060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1667 04:47:50.082113 ==
1668 04:47:50.082165
1669 04:47:50.082217
1670 04:47:50.082269 TX Vref Scan disable
1671 04:47:50.082322 == TX Byte 0 ==
1672 04:47:50.082375 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1673 04:47:50.082427 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1674 04:47:50.082480 == TX Byte 1 ==
1675 04:47:50.082533 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1676 04:47:50.082586 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1677 04:47:50.082638
1678 04:47:50.082690 [DATLAT]
1679 04:47:50.082742 Freq=800, CH1 RK0
1680 04:47:50.082795
1681 04:47:50.082847 DATLAT Default: 0xa
1682 04:47:50.082900 0, 0xFFFF, sum = 0
1683 04:47:50.082954 1, 0xFFFF, sum = 0
1684 04:47:50.083008 2, 0xFFFF, sum = 0
1685 04:47:50.083061 3, 0xFFFF, sum = 0
1686 04:47:50.083114 4, 0xFFFF, sum = 0
1687 04:47:50.083168 5, 0xFFFF, sum = 0
1688 04:47:50.083221 6, 0xFFFF, sum = 0
1689 04:47:50.083275 7, 0xFFFF, sum = 0
1690 04:47:50.083327 8, 0xFFFF, sum = 0
1691 04:47:50.083380 9, 0x0, sum = 1
1692 04:47:50.083433 10, 0x0, sum = 2
1693 04:47:50.083486 11, 0x0, sum = 3
1694 04:47:50.083539 12, 0x0, sum = 4
1695 04:47:50.083593 best_step = 10
1696 04:47:50.083645
1697 04:47:50.083696 ==
1698 04:47:50.083748 Dram Type= 6, Freq= 0, CH_1, rank 0
1699 04:47:50.083802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1700 04:47:50.083854 ==
1701 04:47:50.083907 RX Vref Scan: 1
1702 04:47:50.083959
1703 04:47:50.084011 Set Vref Range= 32 -> 127
1704 04:47:50.084064
1705 04:47:50.084116 RX Vref 32 -> 127, step: 1
1706 04:47:50.084168
1707 04:47:50.084220 RX Delay -79 -> 252, step: 8
1708 04:47:50.084272
1709 04:47:50.084363 Set Vref, RX VrefLevel [Byte0]: 32
1710 04:47:50.084417 [Byte1]: 32
1711 04:47:50.084470
1712 04:47:50.084523 Set Vref, RX VrefLevel [Byte0]: 33
1713 04:47:50.084575 [Byte1]: 33
1714 04:47:50.084628
1715 04:47:50.084680 Set Vref, RX VrefLevel [Byte0]: 34
1716 04:47:50.084733 [Byte1]: 34
1717 04:47:50.084785
1718 04:47:50.085034 Set Vref, RX VrefLevel [Byte0]: 35
1719 04:47:50.085096 [Byte1]: 35
1720 04:47:50.085151
1721 04:47:50.085205 Set Vref, RX VrefLevel [Byte0]: 36
1722 04:47:50.085259 [Byte1]: 36
1723 04:47:50.085311
1724 04:47:50.085363 Set Vref, RX VrefLevel [Byte0]: 37
1725 04:47:50.085417 [Byte1]: 37
1726 04:47:50.085469
1727 04:47:50.085522 Set Vref, RX VrefLevel [Byte0]: 38
1728 04:47:50.085575 [Byte1]: 38
1729 04:47:50.085627
1730 04:47:50.085679 Set Vref, RX VrefLevel [Byte0]: 39
1731 04:47:50.085732 [Byte1]: 39
1732 04:47:50.085784
1733 04:47:50.085837 Set Vref, RX VrefLevel [Byte0]: 40
1734 04:47:50.085890 [Byte1]: 40
1735 04:47:50.085942
1736 04:47:50.085994 Set Vref, RX VrefLevel [Byte0]: 41
1737 04:47:50.086046 [Byte1]: 41
1738 04:47:50.086098
1739 04:47:50.086150 Set Vref, RX VrefLevel [Byte0]: 42
1740 04:47:50.086202 [Byte1]: 42
1741 04:47:50.086258
1742 04:47:50.086310 Set Vref, RX VrefLevel [Byte0]: 43
1743 04:47:50.086362 [Byte1]: 43
1744 04:47:50.086414
1745 04:47:50.086467 Set Vref, RX VrefLevel [Byte0]: 44
1746 04:47:50.086519 [Byte1]: 44
1747 04:47:50.086572
1748 04:47:50.086624 Set Vref, RX VrefLevel [Byte0]: 45
1749 04:47:50.086677 [Byte1]: 45
1750 04:47:50.086730
1751 04:47:50.086782 Set Vref, RX VrefLevel [Byte0]: 46
1752 04:47:50.086835 [Byte1]: 46
1753 04:47:50.086887
1754 04:47:50.086939 Set Vref, RX VrefLevel [Byte0]: 47
1755 04:47:50.086991 [Byte1]: 47
1756 04:47:50.087044
1757 04:47:50.087096 Set Vref, RX VrefLevel [Byte0]: 48
1758 04:47:50.087148 [Byte1]: 48
1759 04:47:50.087201
1760 04:47:50.087254 Set Vref, RX VrefLevel [Byte0]: 49
1761 04:47:50.087306 [Byte1]: 49
1762 04:47:50.087359
1763 04:47:50.087411 Set Vref, RX VrefLevel [Byte0]: 50
1764 04:47:50.087464 [Byte1]: 50
1765 04:47:50.087516
1766 04:47:50.087597 Set Vref, RX VrefLevel [Byte0]: 51
1767 04:47:50.087650 [Byte1]: 51
1768 04:47:50.087703
1769 04:47:50.087755 Set Vref, RX VrefLevel [Byte0]: 52
1770 04:47:50.087807 [Byte1]: 52
1771 04:47:50.087859
1772 04:47:50.087912 Set Vref, RX VrefLevel [Byte0]: 53
1773 04:47:50.087965 [Byte1]: 53
1774 04:47:50.088017
1775 04:47:50.088069 Set Vref, RX VrefLevel [Byte0]: 54
1776 04:47:50.088137 [Byte1]: 54
1777 04:47:50.088191
1778 04:47:50.088244 Set Vref, RX VrefLevel [Byte0]: 55
1779 04:47:50.088306 [Byte1]: 55
1780 04:47:50.088374
1781 04:47:50.088426 Set Vref, RX VrefLevel [Byte0]: 56
1782 04:47:50.088478 [Byte1]: 56
1783 04:47:50.088530
1784 04:47:50.088581 Set Vref, RX VrefLevel [Byte0]: 57
1785 04:47:50.088634 [Byte1]: 57
1786 04:47:50.088686
1787 04:47:50.088738 Set Vref, RX VrefLevel [Byte0]: 58
1788 04:47:50.088791 [Byte1]: 58
1789 04:47:50.088844
1790 04:47:50.088896 Set Vref, RX VrefLevel [Byte0]: 59
1791 04:47:50.088949 [Byte1]: 59
1792 04:47:50.089001
1793 04:47:50.089053 Set Vref, RX VrefLevel [Byte0]: 60
1794 04:47:50.089105 [Byte1]: 60
1795 04:47:50.089157
1796 04:47:50.089208 Set Vref, RX VrefLevel [Byte0]: 61
1797 04:47:50.089260 [Byte1]: 61
1798 04:47:50.089313
1799 04:47:50.089365 Set Vref, RX VrefLevel [Byte0]: 62
1800 04:47:50.089417 [Byte1]: 62
1801 04:47:50.089469
1802 04:47:50.089521 Set Vref, RX VrefLevel [Byte0]: 63
1803 04:47:50.089573 [Byte1]: 63
1804 04:47:50.089626
1805 04:47:50.089678 Set Vref, RX VrefLevel [Byte0]: 64
1806 04:47:50.089730 [Byte1]: 64
1807 04:47:50.089783
1808 04:47:50.089835 Set Vref, RX VrefLevel [Byte0]: 65
1809 04:47:50.089888 [Byte1]: 65
1810 04:47:50.089941
1811 04:47:50.089993 Set Vref, RX VrefLevel [Byte0]: 66
1812 04:47:50.090045 [Byte1]: 66
1813 04:47:50.090098
1814 04:47:50.090150 Set Vref, RX VrefLevel [Byte0]: 67
1815 04:47:50.090202 [Byte1]: 67
1816 04:47:50.090255
1817 04:47:50.090307 Set Vref, RX VrefLevel [Byte0]: 68
1818 04:47:50.090359 [Byte1]: 68
1819 04:47:50.090411
1820 04:47:50.090463 Set Vref, RX VrefLevel [Byte0]: 69
1821 04:47:50.090516 [Byte1]: 69
1822 04:47:50.090568
1823 04:47:50.090620 Set Vref, RX VrefLevel [Byte0]: 70
1824 04:47:50.090673 [Byte1]: 70
1825 04:47:50.090726
1826 04:47:50.090777 Set Vref, RX VrefLevel [Byte0]: 71
1827 04:47:50.090830 [Byte1]: 71
1828 04:47:50.090882
1829 04:47:50.090934 Set Vref, RX VrefLevel [Byte0]: 72
1830 04:47:50.090988 [Byte1]: 72
1831 04:47:50.091040
1832 04:47:50.091093 Set Vref, RX VrefLevel [Byte0]: 73
1833 04:47:50.091145 [Byte1]: 73
1834 04:47:50.091198
1835 04:47:50.091249 Set Vref, RX VrefLevel [Byte0]: 74
1836 04:47:50.091301 [Byte1]: 74
1837 04:47:50.091354
1838 04:47:50.091407 Final RX Vref Byte 0 = 56 to rank0
1839 04:47:50.091474 Final RX Vref Byte 1 = 54 to rank0
1840 04:47:50.091528 Final RX Vref Byte 0 = 56 to rank1
1841 04:47:50.091582 Final RX Vref Byte 1 = 54 to rank1==
1842 04:47:50.091635 Dram Type= 6, Freq= 0, CH_1, rank 0
1843 04:47:50.091688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1844 04:47:50.091741 ==
1845 04:47:50.091794 DQS Delay:
1846 04:47:50.091846 DQS0 = 0, DQS1 = 0
1847 04:47:50.091899 DQM Delay:
1848 04:47:50.091951 DQM0 = 95, DQM1 = 90
1849 04:47:50.092004 DQ Delay:
1850 04:47:50.092057 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1851 04:47:50.092109 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1852 04:47:50.092162 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1853 04:47:50.092214 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1854 04:47:50.092267
1855 04:47:50.092371
1856 04:47:50.092424 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a47, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1857 04:47:50.092478 CH1 RK0: MR19=606, MR18=2A47
1858 04:47:50.092530 CH1_RK0: MR19=0x606, MR18=0x2A47, DQSOSC=392, MR23=63, INC=96, DEC=64
1859 04:47:50.092584
1860 04:47:50.092636 ----->DramcWriteLeveling(PI) begin...
1861 04:47:50.092690 ==
1862 04:47:50.092743 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 04:47:50.092796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1864 04:47:50.092849 ==
1865 04:47:50.092902 Write leveling (Byte 0): 28 => 28
1866 04:47:50.092955 Write leveling (Byte 1): 29 => 29
1867 04:47:50.093008 DramcWriteLeveling(PI) end<-----
1868 04:47:50.093060
1869 04:47:50.093112 ==
1870 04:47:50.093165 Dram Type= 6, Freq= 0, CH_1, rank 1
1871 04:47:50.093219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1872 04:47:50.093273 ==
1873 04:47:50.093325 [Gating] SW mode calibration
1874 04:47:50.093569 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1875 04:47:50.093629 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1876 04:47:50.093684 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1877 04:47:50.093738 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 04:47:50.093792 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 04:47:50.093848 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 04:47:50.093901 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 04:47:50.093954 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 04:47:50.094006 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 04:47:50.094059 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 04:47:50.094111 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 04:47:50.094164 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 04:47:50.094216 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 04:47:50.094269 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 04:47:50.094321 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 04:47:50.094374 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 04:47:50.094428 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 04:47:50.094480 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 04:47:50.094534 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1893 04:47:50.094585 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1894 04:47:50.094638 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 04:47:50.094691 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 04:47:50.094743 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 04:47:50.094796 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 04:47:50.094848 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 04:47:50.094901 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 04:47:50.094970 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 04:47:50.095036 0 9 4 | B1->B0 | 2c2c 2323 | 1 0 | (0 0) (0 0)
1902 04:47:50.095089 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1903 04:47:50.095142 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 04:47:50.095194 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 04:47:51.631607 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 04:47:51.631740 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 04:47:51.631805 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 04:47:51.631866 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
1909 04:47:51.631925 0 10 4 | B1->B0 | 2929 2f2f | 0 1 | (0 0) (0 0)
1910 04:47:51.631983 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1911 04:47:51.632038 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 04:47:51.632092 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 04:47:51.632146 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 04:47:51.632201 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 04:47:51.632255 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 04:47:51.632345 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1917 04:47:51.632431 0 11 4 | B1->B0 | 3c3c 2f2f | 0 0 | (0 0) (1 1)
1918 04:47:51.632499 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1919 04:47:51.632553 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 04:47:51.632606 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 04:47:51.632659 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 04:47:51.632712 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 04:47:51.632764 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 04:47:51.632817 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 04:47:51.632870 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1926 04:47:51.632923 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1927 04:47:51.632976 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 04:47:51.633030 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 04:47:51.633083 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 04:47:51.633137 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 04:47:51.633222 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 04:47:51.633275 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 04:47:51.633328 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 04:47:51.633381 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 04:47:51.633434 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 04:47:51.633486 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 04:47:51.633538 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 04:47:51.633591 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 04:47:51.633644 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 04:47:51.633696 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1941 04:47:51.633749 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1942 04:47:51.633802 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 04:47:51.633855 Total UI for P1: 0, mck2ui 16
1944 04:47:51.633908 best dqsien dly found for B0: ( 0, 14, 2)
1945 04:47:51.633962 Total UI for P1: 0, mck2ui 16
1946 04:47:51.634022 best dqsien dly found for B1: ( 0, 14, 4)
1947 04:47:51.634088 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1948 04:47:51.634142 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1949 04:47:51.634195
1950 04:47:51.634248 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1951 04:47:51.634302 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1952 04:47:51.634355 [Gating] SW calibration Done
1953 04:47:51.634408 ==
1954 04:47:51.634462 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 04:47:51.634515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 04:47:51.634569 ==
1957 04:47:51.634622 RX Vref Scan: 0
1958 04:47:51.634675
1959 04:47:51.634728 RX Vref 0 -> 0, step: 1
1960 04:47:51.634780
1961 04:47:51.634833 RX Delay -130 -> 252, step: 16
1962 04:47:51.634886 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1963 04:47:51.635150 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1964 04:47:51.635211 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1965 04:47:51.635267 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1966 04:47:51.635321 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1967 04:47:51.635374 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1968 04:47:51.635428 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1969 04:47:51.635481 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1970 04:47:51.635534 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1971 04:47:51.635587 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1972 04:47:51.635640 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1973 04:47:51.635693 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1974 04:47:51.635746 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1975 04:47:51.635830 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1976 04:47:51.635883 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1977 04:47:51.635936 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1978 04:47:51.635989 ==
1979 04:47:51.636043 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 04:47:51.636096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 04:47:51.636149 ==
1982 04:47:51.636202 DQS Delay:
1983 04:47:51.636255 DQS0 = 0, DQS1 = 0
1984 04:47:51.636342 DQM Delay:
1985 04:47:51.636411 DQM0 = 92, DQM1 = 88
1986 04:47:51.636465 DQ Delay:
1987 04:47:51.636517 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1988 04:47:51.636571 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1989 04:47:51.636625 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1990 04:47:51.636678 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1991 04:47:51.636730
1992 04:47:51.636783
1993 04:47:51.636836 ==
1994 04:47:51.636889 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 04:47:51.636942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 04:47:51.636996 ==
1997 04:47:51.637048
1998 04:47:51.637100
1999 04:47:51.637169 TX Vref Scan disable
2000 04:47:51.637252 == TX Byte 0 ==
2001 04:47:51.637387 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2002 04:47:51.637445 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2003 04:47:51.637499 == TX Byte 1 ==
2004 04:47:51.637553 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2005 04:47:51.637606 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2006 04:47:51.637659 ==
2007 04:47:51.637712 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 04:47:51.637765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 04:47:51.637819 ==
2010 04:47:51.637872 TX Vref=22, minBit 0, minWin=27, winSum=446
2011 04:47:51.637926 TX Vref=24, minBit 1, minWin=27, winSum=446
2012 04:47:51.637979 TX Vref=26, minBit 2, minWin=27, winSum=450
2013 04:47:51.638033 TX Vref=28, minBit 2, minWin=27, winSum=450
2014 04:47:51.638086 TX Vref=30, minBit 1, minWin=27, winSum=452
2015 04:47:51.638140 TX Vref=32, minBit 2, minWin=27, winSum=450
2016 04:47:51.638193 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 30
2017 04:47:51.638248
2018 04:47:51.638300 Final TX Range 1 Vref 30
2019 04:47:51.638354
2020 04:47:51.638406 ==
2021 04:47:51.638460 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 04:47:51.638513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 04:47:51.638567 ==
2024 04:47:51.638652
2025 04:47:51.638704
2026 04:47:51.638757 TX Vref Scan disable
2027 04:47:51.638810 == TX Byte 0 ==
2028 04:47:51.638862 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2029 04:47:51.638917 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2030 04:47:51.638970 == TX Byte 1 ==
2031 04:47:51.639023 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2032 04:47:51.639077 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2033 04:47:51.639156
2034 04:47:51.639232 [DATLAT]
2035 04:47:51.639341 Freq=800, CH1 RK1
2036 04:47:51.639399
2037 04:47:51.639454 DATLAT Default: 0xa
2038 04:47:51.639508 0, 0xFFFF, sum = 0
2039 04:47:51.639563 1, 0xFFFF, sum = 0
2040 04:47:51.639617 2, 0xFFFF, sum = 0
2041 04:47:51.639672 3, 0xFFFF, sum = 0
2042 04:47:51.639726 4, 0xFFFF, sum = 0
2043 04:47:51.639780 5, 0xFFFF, sum = 0
2044 04:47:51.639834 6, 0xFFFF, sum = 0
2045 04:47:51.639887 7, 0xFFFF, sum = 0
2046 04:47:51.639941 8, 0xFFFF, sum = 0
2047 04:47:51.639995 9, 0x0, sum = 1
2048 04:47:51.640049 10, 0x0, sum = 2
2049 04:47:51.640103 11, 0x0, sum = 3
2050 04:47:51.640157 12, 0x0, sum = 4
2051 04:47:51.640211 best_step = 10
2052 04:47:51.640264
2053 04:47:51.640362 ==
2054 04:47:51.640417 Dram Type= 6, Freq= 0, CH_1, rank 1
2055 04:47:51.640471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2056 04:47:51.640525 ==
2057 04:47:51.640578 RX Vref Scan: 0
2058 04:47:51.640632
2059 04:47:51.640685 RX Vref 0 -> 0, step: 1
2060 04:47:51.640737
2061 04:47:51.640790 RX Delay -79 -> 252, step: 8
2062 04:47:51.640844 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2063 04:47:51.640898 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2064 04:47:51.640952 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2065 04:47:51.641005 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2066 04:47:51.641058 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2067 04:47:51.641112 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2068 04:47:51.641182 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2069 04:47:51.641269 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2070 04:47:51.641367 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2071 04:47:51.641420 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2072 04:47:51.641473 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2073 04:47:51.641527 iDelay=209, Bit 11, Center 84 (-15 ~ 184) 200
2074 04:47:51.641580 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2075 04:47:51.641634 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2076 04:47:51.641687 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2077 04:47:51.641740 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2078 04:47:51.641793 ==
2079 04:47:51.641847 Dram Type= 6, Freq= 0, CH_1, rank 1
2080 04:47:51.641901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2081 04:47:51.641955 ==
2082 04:47:51.642008 DQS Delay:
2083 04:47:51.642061 DQS0 = 0, DQS1 = 0
2084 04:47:51.642114 DQM Delay:
2085 04:47:51.642167 DQM0 = 97, DQM1 = 91
2086 04:47:51.642221 DQ Delay:
2087 04:47:51.642274 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2088 04:47:51.642328 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2089 04:47:51.642381 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2090 04:47:51.642434 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2091 04:47:51.642521
2092 04:47:51.642574
2093 04:47:51.642626 [DQSOSCAuto] RK1, (LSB)MR18= 0x460f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2094 04:47:51.642681 CH1 RK1: MR19=606, MR18=460F
2095 04:47:51.642735 CH1_RK1: MR19=0x606, MR18=0x460F, DQSOSC=392, MR23=63, INC=96, DEC=64
2096 04:47:51.642789 [RxdqsGatingPostProcess] freq 800
2097 04:47:51.642873 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2098 04:47:51.642927 Pre-setting of DQS Precalculation
2099 04:47:51.643182 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2100 04:47:51.643287 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2101 04:47:51.643344 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2102 04:47:51.643399
2103 04:47:51.643453
2104 04:47:51.643506 [Calibration Summary] 1600 Mbps
2105 04:47:51.643560 CH 0, Rank 0
2106 04:47:51.643613 SW Impedance : PASS
2107 04:47:51.643666 DUTY Scan : NO K
2108 04:47:51.643720 ZQ Calibration : PASS
2109 04:47:51.643773 Jitter Meter : NO K
2110 04:47:51.643827 CBT Training : PASS
2111 04:47:51.643880 Write leveling : PASS
2112 04:47:51.643934 RX DQS gating : PASS
2113 04:47:51.643987 RX DQ/DQS(RDDQC) : PASS
2114 04:47:51.644040 TX DQ/DQS : PASS
2115 04:47:51.644094 RX DATLAT : PASS
2116 04:47:51.644147 RX DQ/DQS(Engine): PASS
2117 04:47:51.644200 TX OE : NO K
2118 04:47:51.644312 All Pass.
2119 04:47:51.644388
2120 04:47:51.644442 CH 0, Rank 1
2121 04:47:51.644495 SW Impedance : PASS
2122 04:47:51.644549 DUTY Scan : NO K
2123 04:47:51.644602 ZQ Calibration : PASS
2124 04:47:51.644655 Jitter Meter : NO K
2125 04:47:51.644708 CBT Training : PASS
2126 04:47:51.644761 Write leveling : PASS
2127 04:47:51.644814 RX DQS gating : PASS
2128 04:47:51.644867 RX DQ/DQS(RDDQC) : PASS
2129 04:47:51.644921 TX DQ/DQS : PASS
2130 04:47:51.644975 RX DATLAT : PASS
2131 04:47:51.645028 RX DQ/DQS(Engine): PASS
2132 04:47:51.645081 TX OE : NO K
2133 04:47:51.645135 All Pass.
2134 04:47:51.645187
2135 04:47:51.645240 CH 1, Rank 0
2136 04:47:51.645294 SW Impedance : PASS
2137 04:47:51.645347 DUTY Scan : NO K
2138 04:47:51.645401 ZQ Calibration : PASS
2139 04:47:51.645454 Jitter Meter : NO K
2140 04:47:51.645508 CBT Training : PASS
2141 04:47:51.645561 Write leveling : PASS
2142 04:47:51.645614 RX DQS gating : PASS
2143 04:47:51.645667 RX DQ/DQS(RDDQC) : PASS
2144 04:47:51.645720 TX DQ/DQS : PASS
2145 04:47:51.645790 RX DATLAT : PASS
2146 04:47:51.645860 RX DQ/DQS(Engine): PASS
2147 04:47:51.645913 TX OE : NO K
2148 04:47:51.645966 All Pass.
2149 04:47:51.646019
2150 04:47:51.646072 CH 1, Rank 1
2151 04:47:51.646125 SW Impedance : PASS
2152 04:47:51.646178 DUTY Scan : NO K
2153 04:47:51.646231 ZQ Calibration : PASS
2154 04:47:51.646284 Jitter Meter : NO K
2155 04:47:51.646337 CBT Training : PASS
2156 04:47:51.646389 Write leveling : PASS
2157 04:47:51.646443 RX DQS gating : PASS
2158 04:47:51.646495 RX DQ/DQS(RDDQC) : PASS
2159 04:47:51.646548 TX DQ/DQS : PASS
2160 04:47:51.646602 RX DATLAT : PASS
2161 04:47:51.646655 RX DQ/DQS(Engine): PASS
2162 04:47:51.646707 TX OE : NO K
2163 04:47:51.646761 All Pass.
2164 04:47:51.646814
2165 04:47:51.646866 DramC Write-DBI off
2166 04:47:51.646919 PER_BANK_REFRESH: Hybrid Mode
2167 04:47:51.646972 TX_TRACKING: ON
2168 04:47:51.647026 [GetDramInforAfterCalByMRR] Vendor 6.
2169 04:47:51.647079 [GetDramInforAfterCalByMRR] Revision 606.
2170 04:47:51.647132 [GetDramInforAfterCalByMRR] Revision 2 0.
2171 04:47:51.647186 MR0 0x3b3b
2172 04:47:51.647266 MR8 0x5151
2173 04:47:51.647344 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2174 04:47:51.647398
2175 04:47:51.647452 MR0 0x3b3b
2176 04:47:51.647504 MR8 0x5151
2177 04:47:51.647567 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2178 04:47:51.647628
2179 04:47:51.647682 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2180 04:47:51.647737 [FAST_K] Save calibration result to emmc
2181 04:47:51.647791 [FAST_K] Save calibration result to emmc
2182 04:47:51.647844 dram_init: config_dvfs: 1
2183 04:47:51.647898 dramc_set_vcore_voltage set vcore to 662500
2184 04:47:51.647951 Read voltage for 1200, 2
2185 04:47:51.648004 Vio18 = 0
2186 04:47:51.648057 Vcore = 662500
2187 04:47:51.648110 Vdram = 0
2188 04:47:51.648163 Vddq = 0
2189 04:47:51.648216 Vmddr = 0
2190 04:47:51.648269 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2191 04:47:51.648355 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2192 04:47:51.648412 MEM_TYPE=3, freq_sel=15
2193 04:47:51.648466 sv_algorithm_assistance_LP4_1600
2194 04:47:51.648521 ============ PULL DRAM RESETB DOWN ============
2195 04:47:51.648576 ========== PULL DRAM RESETB DOWN end =========
2196 04:47:51.648646 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2197 04:47:51.648718 ===================================
2198 04:47:51.648786 LPDDR4 DRAM CONFIGURATION
2199 04:47:51.648840 ===================================
2200 04:47:51.648894 EX_ROW_EN[0] = 0x0
2201 04:47:51.648947 EX_ROW_EN[1] = 0x0
2202 04:47:51.649000 LP4Y_EN = 0x0
2203 04:47:51.649053 WORK_FSP = 0x0
2204 04:47:51.649106 WL = 0x4
2205 04:47:51.649159 RL = 0x4
2206 04:47:51.649212 BL = 0x2
2207 04:47:51.649265 RPST = 0x0
2208 04:47:51.649318 RD_PRE = 0x0
2209 04:47:51.649371 WR_PRE = 0x1
2210 04:47:51.649424 WR_PST = 0x0
2211 04:47:51.649477 DBI_WR = 0x0
2212 04:47:51.649530 DBI_RD = 0x0
2213 04:47:51.649583 OTF = 0x1
2214 04:47:51.649636 ===================================
2215 04:47:51.649690 ===================================
2216 04:47:51.649743 ANA top config
2217 04:47:51.649797 ===================================
2218 04:47:51.649851 DLL_ASYNC_EN = 0
2219 04:47:51.649904 ALL_SLAVE_EN = 0
2220 04:47:51.649956 NEW_RANK_MODE = 1
2221 04:47:51.650010 DLL_IDLE_MODE = 1
2222 04:47:51.650064 LP45_APHY_COMB_EN = 1
2223 04:47:51.650117 TX_ODT_DIS = 1
2224 04:47:51.650170 NEW_8X_MODE = 1
2225 04:47:51.650224 ===================================
2226 04:47:51.650277 ===================================
2227 04:47:51.650331 data_rate = 2400
2228 04:47:51.650384 CKR = 1
2229 04:47:51.650437 DQ_P2S_RATIO = 8
2230 04:47:51.650491 ===================================
2231 04:47:51.650544 CA_P2S_RATIO = 8
2232 04:47:51.650597 DQ_CA_OPEN = 0
2233 04:47:51.650650 DQ_SEMI_OPEN = 0
2234 04:47:51.650702 CA_SEMI_OPEN = 0
2235 04:47:51.650755 CA_FULL_RATE = 0
2236 04:47:51.650808 DQ_CKDIV4_EN = 0
2237 04:47:51.650861 CA_CKDIV4_EN = 0
2238 04:47:51.650914 CA_PREDIV_EN = 0
2239 04:47:51.650967 PH8_DLY = 17
2240 04:47:51.651021 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2241 04:47:51.651074 DQ_AAMCK_DIV = 4
2242 04:47:51.651127 CA_AAMCK_DIV = 4
2243 04:47:51.651180 CA_ADMCK_DIV = 4
2244 04:47:51.651256 DQ_TRACK_CA_EN = 0
2245 04:47:51.651368 CA_PICK = 1200
2246 04:47:51.651424 CA_MCKIO = 1200
2247 04:47:51.651479 MCKIO_SEMI = 0
2248 04:47:51.651533 PLL_FREQ = 2366
2249 04:47:51.651589 DQ_UI_PI_RATIO = 32
2250 04:47:51.651854 CA_UI_PI_RATIO = 0
2251 04:47:51.651946 ===================================
2252 04:47:51.652065 ===================================
2253 04:47:51.652122 memory_type:LPDDR4
2254 04:47:51.652176 GP_NUM : 10
2255 04:47:51.652246 SRAM_EN : 1
2256 04:47:51.652310 MD32_EN : 0
2257 04:47:51.652380 ===================================
2258 04:47:51.652433 [ANA_INIT] >>>>>>>>>>>>>>
2259 04:47:51.652487 <<<<<< [CONFIGURE PHASE]: ANA_TX
2260 04:47:51.652541 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2261 04:47:51.652595 ===================================
2262 04:47:51.652648 data_rate = 2400,PCW = 0X5b00
2263 04:47:51.652702 ===================================
2264 04:47:51.652755 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2265 04:47:51.652808 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2266 04:47:51.652862 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2267 04:47:51.652916 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2268 04:47:51.652970 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2269 04:47:51.653023 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2270 04:47:51.653095 [ANA_INIT] flow start
2271 04:47:51.653163 [ANA_INIT] PLL >>>>>>>>
2272 04:47:51.653216 [ANA_INIT] PLL <<<<<<<<
2273 04:47:51.653276 [ANA_INIT] MIDPI >>>>>>>>
2274 04:47:51.653331 [ANA_INIT] MIDPI <<<<<<<<
2275 04:47:51.653384 [ANA_INIT] DLL >>>>>>>>
2276 04:47:51.653436 [ANA_INIT] DLL <<<<<<<<
2277 04:47:51.653488 [ANA_INIT] flow end
2278 04:47:51.653541 ============ LP4 DIFF to SE enter ============
2279 04:47:51.653594 ============ LP4 DIFF to SE exit ============
2280 04:47:51.653646 [ANA_INIT] <<<<<<<<<<<<<
2281 04:47:51.653699 [Flow] Enable top DCM control >>>>>
2282 04:47:51.653751 [Flow] Enable top DCM control <<<<<
2283 04:47:51.653804 Enable DLL master slave shuffle
2284 04:47:51.653856 ==============================================================
2285 04:47:51.653909 Gating Mode config
2286 04:47:51.653961 ==============================================================
2287 04:47:51.654014 Config description:
2288 04:47:51.654067 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2289 04:47:51.654121 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2290 04:47:51.654174 SELPH_MODE 0: By rank 1: By Phase
2291 04:47:51.654226 ==============================================================
2292 04:47:51.654279 GAT_TRACK_EN = 1
2293 04:47:51.654332 RX_GATING_MODE = 2
2294 04:47:51.654384 RX_GATING_TRACK_MODE = 2
2295 04:47:51.654436 SELPH_MODE = 1
2296 04:47:51.654489 PICG_EARLY_EN = 1
2297 04:47:51.654541 VALID_LAT_VALUE = 1
2298 04:47:51.654594 ==============================================================
2299 04:47:51.654646 Enter into Gating configuration >>>>
2300 04:47:51.654699 Exit from Gating configuration <<<<
2301 04:47:51.654752 Enter into DVFS_PRE_config >>>>>
2302 04:47:51.654805 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2303 04:47:51.654859 Exit from DVFS_PRE_config <<<<<
2304 04:47:51.654912 Enter into PICG configuration >>>>
2305 04:47:51.654965 Exit from PICG configuration <<<<
2306 04:47:51.655016 [RX_INPUT] configuration >>>>>
2307 04:47:51.655068 [RX_INPUT] configuration <<<<<
2308 04:47:51.655121 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2309 04:47:51.655176 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2310 04:47:51.655230 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2311 04:47:51.655320 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2312 04:47:51.655390 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2313 04:47:51.655443 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2314 04:47:51.655496 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2315 04:47:51.655548 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2316 04:47:51.655601 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2317 04:47:51.655654 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2318 04:47:51.655707 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2319 04:47:51.655759 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2320 04:47:51.655813 ===================================
2321 04:47:51.655866 LPDDR4 DRAM CONFIGURATION
2322 04:47:51.655919 ===================================
2323 04:47:51.655989 EX_ROW_EN[0] = 0x0
2324 04:47:51.656111 EX_ROW_EN[1] = 0x0
2325 04:47:51.656195 LP4Y_EN = 0x0
2326 04:47:51.656278 WORK_FSP = 0x0
2327 04:47:51.656361 WL = 0x4
2328 04:47:51.656415 RL = 0x4
2329 04:47:51.656468 BL = 0x2
2330 04:47:51.656521 RPST = 0x0
2331 04:47:51.656574 RD_PRE = 0x0
2332 04:47:51.656626 WR_PRE = 0x1
2333 04:47:51.656679 WR_PST = 0x0
2334 04:47:51.656731 DBI_WR = 0x0
2335 04:47:51.656784 DBI_RD = 0x0
2336 04:47:51.656836 OTF = 0x1
2337 04:47:51.656920 ===================================
2338 04:47:51.656973 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2339 04:47:51.657026 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2340 04:47:51.657078 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2341 04:47:51.657131 ===================================
2342 04:47:51.657184 LPDDR4 DRAM CONFIGURATION
2343 04:47:51.657237 ===================================
2344 04:47:51.657289 EX_ROW_EN[0] = 0x10
2345 04:47:51.657342 EX_ROW_EN[1] = 0x0
2346 04:47:51.657394 LP4Y_EN = 0x0
2347 04:47:51.657448 WORK_FSP = 0x0
2348 04:47:51.657501 WL = 0x4
2349 04:47:51.657553 RL = 0x4
2350 04:47:51.657605 BL = 0x2
2351 04:47:51.657658 RPST = 0x0
2352 04:47:51.657710 RD_PRE = 0x0
2353 04:47:51.657762 WR_PRE = 0x1
2354 04:47:51.657814 WR_PST = 0x0
2355 04:47:51.657867 DBI_WR = 0x0
2356 04:47:51.657919 DBI_RD = 0x0
2357 04:47:51.657971 OTF = 0x1
2358 04:47:51.658023 ===================================
2359 04:47:51.658278 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2360 04:47:51.658365 ==
2361 04:47:51.658433 Dram Type= 6, Freq= 0, CH_0, rank 0
2362 04:47:51.658487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 04:47:51.658540 ==
2364 04:47:51.658593 [Duty_Offset_Calibration]
2365 04:47:51.658646 B0:2 B1:1 CA:1
2366 04:47:51.658698
2367 04:47:51.658750 [DutyScan_Calibration_Flow] k_type=0
2368 04:47:51.658803
2369 04:47:51.658855 ==CLK 0==
2370 04:47:51.658908 Final CLK duty delay cell = 0
2371 04:47:51.658961 [0] MAX Duty = 5187%(X100), DQS PI = 24
2372 04:47:51.659014 [0] MIN Duty = 4844%(X100), DQS PI = 48
2373 04:47:51.659067 [0] AVG Duty = 5015%(X100)
2374 04:47:51.659119
2375 04:47:51.659171 CH0 CLK Duty spec in!! Max-Min= 343%
2376 04:47:51.659224 [DutyScan_Calibration_Flow] ====Done====
2377 04:47:51.659283
2378 04:47:51.659336 [DutyScan_Calibration_Flow] k_type=1
2379 04:47:51.659389
2380 04:47:51.659441 ==DQS 0 ==
2381 04:47:51.659494 Final DQS duty delay cell = -4
2382 04:47:51.659547 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2383 04:47:51.659599 [-4] MIN Duty = 4751%(X100), DQS PI = 62
2384 04:47:51.659652 [-4] AVG Duty = 4937%(X100)
2385 04:47:51.659705
2386 04:47:51.659757 ==DQS 1 ==
2387 04:47:51.659810 Final DQS duty delay cell = 0
2388 04:47:51.659863 [0] MAX Duty = 5156%(X100), DQS PI = 62
2389 04:47:51.659925 [0] MIN Duty = 5000%(X100), DQS PI = 36
2390 04:47:51.659988 [0] AVG Duty = 5078%(X100)
2391 04:47:51.660041
2392 04:47:51.660094 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2393 04:47:51.660148
2394 04:47:51.660201 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2395 04:47:51.660253 [DutyScan_Calibration_Flow] ====Done====
2396 04:47:51.660353
2397 04:47:51.660438 [DutyScan_Calibration_Flow] k_type=3
2398 04:47:51.660502
2399 04:47:51.660555 ==DQM 0 ==
2400 04:47:51.660608 Final DQM duty delay cell = 0
2401 04:47:51.660662 [0] MAX Duty = 5156%(X100), DQS PI = 30
2402 04:47:51.660715 [0] MIN Duty = 4907%(X100), DQS PI = 58
2403 04:47:51.660768 [0] AVG Duty = 5031%(X100)
2404 04:47:51.660821
2405 04:47:51.660873 ==DQM 1 ==
2406 04:47:51.660926 Final DQM duty delay cell = -4
2407 04:47:51.660979 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2408 04:47:51.661032 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2409 04:47:51.661085 [-4] AVG Duty = 4922%(X100)
2410 04:47:51.661155
2411 04:47:51.661209 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2412 04:47:51.661277
2413 04:47:51.661331 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2414 04:47:51.661384 [DutyScan_Calibration_Flow] ====Done====
2415 04:47:51.661437
2416 04:47:51.661489 [DutyScan_Calibration_Flow] k_type=2
2417 04:47:51.661542
2418 04:47:51.661595 ==DQ 0 ==
2419 04:47:51.661647 Final DQ duty delay cell = 0
2420 04:47:51.661701 [0] MAX Duty = 5031%(X100), DQS PI = 24
2421 04:47:51.661754 [0] MIN Duty = 4844%(X100), DQS PI = 62
2422 04:47:51.661807 [0] AVG Duty = 4937%(X100)
2423 04:47:51.661859
2424 04:47:51.661911 ==DQ 1 ==
2425 04:47:51.661963 Final DQ duty delay cell = 0
2426 04:47:51.662016 [0] MAX Duty = 5093%(X100), DQS PI = 8
2427 04:47:51.662069 [0] MIN Duty = 4907%(X100), DQS PI = 36
2428 04:47:51.662121 [0] AVG Duty = 5000%(X100)
2429 04:47:51.662173
2430 04:47:51.662226 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2431 04:47:51.662278
2432 04:47:51.662330 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2433 04:47:51.662384 [DutyScan_Calibration_Flow] ====Done====
2434 04:47:51.662438 ==
2435 04:47:51.662490 Dram Type= 6, Freq= 0, CH_1, rank 0
2436 04:47:51.662543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2437 04:47:51.662597 ==
2438 04:47:51.662649 [Duty_Offset_Calibration]
2439 04:47:51.662701 B0:1 B1:0 CA:0
2440 04:47:51.662753
2441 04:47:51.662805 [DutyScan_Calibration_Flow] k_type=0
2442 04:47:51.662858
2443 04:47:51.662910 ==CLK 0==
2444 04:47:51.662963 Final CLK duty delay cell = -4
2445 04:47:51.663016 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2446 04:47:51.663068 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2447 04:47:51.663120 [-4] AVG Duty = 4969%(X100)
2448 04:47:51.663173
2449 04:47:51.663225 CH1 CLK Duty spec in!! Max-Min= 124%
2450 04:47:51.663284 [DutyScan_Calibration_Flow] ====Done====
2451 04:47:51.663336
2452 04:47:51.663388 [DutyScan_Calibration_Flow] k_type=1
2453 04:47:51.663441
2454 04:47:51.663555 ==DQS 0 ==
2455 04:47:51.663609 Final DQS duty delay cell = 0
2456 04:47:51.663663 [0] MAX Duty = 5062%(X100), DQS PI = 16
2457 04:47:51.663716 [0] MIN Duty = 4844%(X100), DQS PI = 0
2458 04:47:51.663769 [0] AVG Duty = 4953%(X100)
2459 04:47:51.663821
2460 04:47:51.663874 ==DQS 1 ==
2461 04:47:51.663945 Final DQS duty delay cell = 0
2462 04:47:51.664013 [0] MAX Duty = 5218%(X100), DQS PI = 20
2463 04:47:51.664066 [0] MIN Duty = 4969%(X100), DQS PI = 10
2464 04:47:51.664118 [0] AVG Duty = 5093%(X100)
2465 04:47:51.664171
2466 04:47:51.664223 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2467 04:47:51.664275
2468 04:47:51.664367 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2469 04:47:51.664421 [DutyScan_Calibration_Flow] ====Done====
2470 04:47:51.664474
2471 04:47:51.664526 [DutyScan_Calibration_Flow] k_type=3
2472 04:47:51.664579
2473 04:47:51.664631 ==DQM 0 ==
2474 04:47:51.664684 Final DQM duty delay cell = 0
2475 04:47:51.664738 [0] MAX Duty = 5156%(X100), DQS PI = 6
2476 04:47:51.664792 [0] MIN Duty = 5031%(X100), DQS PI = 0
2477 04:47:51.664885 [0] AVG Duty = 5093%(X100)
2478 04:47:51.664938
2479 04:47:51.664990 ==DQM 1 ==
2480 04:47:51.665043 Final DQM duty delay cell = 0
2481 04:47:51.665096 [0] MAX Duty = 5031%(X100), DQS PI = 18
2482 04:47:51.665149 [0] MIN Duty = 4907%(X100), DQS PI = 34
2483 04:47:51.665202 [0] AVG Duty = 4969%(X100)
2484 04:47:51.665298
2485 04:47:51.665399 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2486 04:47:51.665471
2487 04:47:51.665540 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2488 04:47:51.665594 [DutyScan_Calibration_Flow] ====Done====
2489 04:47:51.665647
2490 04:47:51.665699 [DutyScan_Calibration_Flow] k_type=2
2491 04:47:51.665752
2492 04:47:51.665822 ==DQ 0 ==
2493 04:47:51.665889 Final DQ duty delay cell = -4
2494 04:47:51.665942 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2495 04:47:51.665995 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2496 04:47:51.666048 [-4] AVG Duty = 5016%(X100)
2497 04:47:51.666101
2498 04:47:51.666153 ==DQ 1 ==
2499 04:47:51.666206 Final DQ duty delay cell = 0
2500 04:47:51.666259 [0] MAX Duty = 5125%(X100), DQS PI = 20
2501 04:47:51.666312 [0] MIN Duty = 4969%(X100), DQS PI = 10
2502 04:47:51.666365 [0] AVG Duty = 5047%(X100)
2503 04:47:51.666417
2504 04:47:51.666469 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2505 04:47:51.666522
2506 04:47:51.666574 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2507 04:47:51.666627 [DutyScan_Calibration_Flow] ====Done====
2508 04:47:51.666680 nWR fixed to 30
2509 04:47:51.666734 [ModeRegInit_LP4] CH0 RK0
2510 04:47:51.666787 [ModeRegInit_LP4] CH0 RK1
2511 04:47:51.666840 [ModeRegInit_LP4] CH1 RK0
2512 04:47:51.666892 [ModeRegInit_LP4] CH1 RK1
2513 04:47:51.666945 match AC timing 7
2514 04:47:51.666997 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2515 04:47:51.667050 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2516 04:47:51.667104 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2517 04:47:51.667158 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2518 04:47:51.667411 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2519 04:47:51.667470 ==
2520 04:47:51.667557 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 04:47:51.667610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 04:47:51.667664 ==
2523 04:47:51.667734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2524 04:47:51.667803 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2525 04:47:51.667856 [CA 0] Center 39 (8~70) winsize 63
2526 04:47:51.667956 [CA 1] Center 39 (8~70) winsize 63
2527 04:47:51.668013 [CA 2] Center 35 (5~66) winsize 62
2528 04:47:51.668082 [CA 3] Center 34 (4~65) winsize 62
2529 04:47:51.668137 [CA 4] Center 33 (3~64) winsize 62
2530 04:47:51.668191 [CA 5] Center 32 (3~62) winsize 60
2531 04:47:51.668245
2532 04:47:51.668336 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2533 04:47:51.668437
2534 04:47:51.668491 [CATrainingPosCal] consider 1 rank data
2535 04:47:51.668546 u2DelayCellTimex100 = 270/100 ps
2536 04:47:51.668600 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2537 04:47:51.668655 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2538 04:47:51.668709 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2539 04:47:51.668764 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2540 04:47:51.668817 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2541 04:47:51.668886 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2542 04:47:51.668938
2543 04:47:51.668991 CA PerBit enable=1, Macro0, CA PI delay=32
2544 04:47:51.669059
2545 04:47:51.669127 [CBTSetCACLKResult] CA Dly = 32
2546 04:47:51.669179 CS Dly: 6 (0~37)
2547 04:47:51.669247 ==
2548 04:47:51.669315 Dram Type= 6, Freq= 0, CH_0, rank 1
2549 04:47:51.669368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2550 04:47:51.669438 ==
2551 04:47:51.669506 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2552 04:47:51.669562 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2553 04:47:51.669616 [CA 0] Center 38 (8~69) winsize 62
2554 04:47:51.669671 [CA 1] Center 38 (8~69) winsize 62
2555 04:47:51.669725 [CA 2] Center 35 (4~66) winsize 63
2556 04:47:51.669780 [CA 3] Center 34 (4~65) winsize 62
2557 04:47:51.669880 [CA 4] Center 33 (3~64) winsize 62
2558 04:47:51.669933 [CA 5] Center 32 (3~62) winsize 60
2559 04:47:51.669986
2560 04:47:51.670085 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2561 04:47:51.670155
2562 04:47:51.670236 [CATrainingPosCal] consider 2 rank data
2563 04:47:51.670289 u2DelayCellTimex100 = 270/100 ps
2564 04:47:51.670341 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2565 04:47:51.670425 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2566 04:47:51.670477 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2567 04:47:51.670530 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2568 04:47:51.670598 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2569 04:47:51.670665 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2570 04:47:51.670718
2571 04:47:51.670785 CA PerBit enable=1, Macro0, CA PI delay=32
2572 04:47:51.670838
2573 04:47:51.670891 [CBTSetCACLKResult] CA Dly = 32
2574 04:47:51.670945 CS Dly: 6 (0~38)
2575 04:47:51.670999
2576 04:47:51.671052 ----->DramcWriteLeveling(PI) begin...
2577 04:47:51.671107 ==
2578 04:47:51.671162 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 04:47:51.671216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 04:47:51.671270 ==
2581 04:47:51.671323 Write leveling (Byte 0): 33 => 33
2582 04:47:51.671393 Write leveling (Byte 1): 28 => 28
2583 04:47:51.671446 DramcWriteLeveling(PI) end<-----
2584 04:47:51.671499
2585 04:47:51.671582 ==
2586 04:47:51.671634 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 04:47:51.671687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 04:47:51.671757 ==
2589 04:47:51.671824 [Gating] SW mode calibration
2590 04:47:51.671918 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2591 04:47:51.672018 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2592 04:47:51.672073 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2593 04:47:51.672126 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2594 04:47:51.672179 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 04:47:51.672233 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 04:47:51.672310 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 04:47:51.672381 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 04:47:51.672434 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
2599 04:47:51.672487 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
2600 04:47:51.672540 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2601 04:47:51.672592 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 04:47:51.672645 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 04:47:51.672737 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 04:47:51.672789 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 04:47:51.672842 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 04:47:51.672894 1 0 24 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
2607 04:47:51.672946 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2608 04:47:51.672998 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2609 04:47:51.673051 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 04:47:51.673103 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 04:47:51.673156 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 04:47:51.673208 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 04:47:51.673261 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 04:47:51.673314 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 04:47:51.673366 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2616 04:47:51.673433 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2617 04:47:51.673500 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 04:47:51.673553 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 04:47:51.673606 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 04:47:51.673658 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 04:47:51.673711 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 04:47:51.673764 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 04:47:51.673817 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 04:47:51.673870 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 04:47:51.674120 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 04:47:51.674180 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 04:47:51.674235 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 04:47:51.674289 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 04:47:51.674343 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 04:47:51.674396 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 04:47:51.674449 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2632 04:47:51.674502 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2633 04:47:51.674554 Total UI for P1: 0, mck2ui 16
2634 04:47:51.674608 best dqsien dly found for B0: ( 1, 3, 28)
2635 04:47:51.674661 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2636 04:47:51.674713 Total UI for P1: 0, mck2ui 16
2637 04:47:51.674766 best dqsien dly found for B1: ( 1, 4, 0)
2638 04:47:51.674819 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2639 04:47:51.674872 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2640 04:47:51.674924
2641 04:47:51.674977 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2642 04:47:51.675029 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2643 04:47:51.675082 [Gating] SW calibration Done
2644 04:47:51.675135 ==
2645 04:47:51.675187 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 04:47:51.675239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 04:47:51.675293 ==
2648 04:47:51.675345 RX Vref Scan: 0
2649 04:47:51.675397
2650 04:47:51.675449 RX Vref 0 -> 0, step: 1
2651 04:47:51.675501
2652 04:47:51.675553 RX Delay -40 -> 252, step: 8
2653 04:47:51.675606 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2654 04:47:51.675660 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2655 04:47:51.675712 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2656 04:47:51.675785 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2657 04:47:51.675858 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2658 04:47:51.675933 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2659 04:47:51.675988 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2660 04:47:51.676041 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2661 04:47:51.676094 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2662 04:47:51.676147 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2663 04:47:51.676200 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2664 04:47:51.676253 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2665 04:47:51.676349 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2666 04:47:51.676404 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2667 04:47:51.676458 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2668 04:47:51.676511 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2669 04:47:51.676564 ==
2670 04:47:51.676616 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 04:47:51.676699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 04:47:51.676752 ==
2673 04:47:51.676805 DQS Delay:
2674 04:47:51.676858 DQS0 = 0, DQS1 = 0
2675 04:47:51.676910 DQM Delay:
2676 04:47:51.676963 DQM0 = 121, DQM1 = 113
2677 04:47:51.677016 DQ Delay:
2678 04:47:51.677068 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2679 04:47:51.677121 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2680 04:47:51.677174 DQ8 =99, DQ9 =107, DQ10 =115, DQ11 =107
2681 04:47:51.677227 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2682 04:47:51.677280
2683 04:47:51.677332
2684 04:47:51.677384 ==
2685 04:47:51.677436 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 04:47:51.677489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 04:47:51.677542 ==
2688 04:47:51.677595
2689 04:47:51.677647
2690 04:47:51.677699 TX Vref Scan disable
2691 04:47:51.677753 == TX Byte 0 ==
2692 04:47:51.677805 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2693 04:47:51.677858 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2694 04:47:51.677911 == TX Byte 1 ==
2695 04:47:51.677964 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2696 04:47:51.678018 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2697 04:47:51.678071 ==
2698 04:47:51.678123 Dram Type= 6, Freq= 0, CH_0, rank 0
2699 04:47:51.678177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2700 04:47:51.678230 ==
2701 04:47:51.678282 TX Vref=22, minBit 0, minWin=25, winSum=409
2702 04:47:51.678335 TX Vref=24, minBit 0, minWin=25, winSum=414
2703 04:47:51.678388 TX Vref=26, minBit 7, minWin=25, winSum=421
2704 04:47:51.678441 TX Vref=28, minBit 0, minWin=26, winSum=425
2705 04:47:51.678494 TX Vref=30, minBit 0, minWin=26, winSum=425
2706 04:47:51.678546 TX Vref=32, minBit 0, minWin=26, winSum=424
2707 04:47:51.678600 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
2708 04:47:51.678654
2709 04:47:51.678707 Final TX Range 1 Vref 28
2710 04:47:51.678760
2711 04:47:51.678813 ==
2712 04:47:51.678865 Dram Type= 6, Freq= 0, CH_0, rank 0
2713 04:47:51.678918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2714 04:47:51.678971 ==
2715 04:47:51.679024
2716 04:47:51.679076
2717 04:47:51.679128 TX Vref Scan disable
2718 04:47:51.679181 == TX Byte 0 ==
2719 04:47:51.679233 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2720 04:47:51.679287 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2721 04:47:51.679340 == TX Byte 1 ==
2722 04:47:51.679392 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2723 04:47:51.679445 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2724 04:47:51.679498
2725 04:47:51.679568 [DATLAT]
2726 04:47:51.679659 Freq=1200, CH0 RK0
2727 04:47:51.679729
2728 04:47:51.679864 DATLAT Default: 0xd
2729 04:47:51.679951 0, 0xFFFF, sum = 0
2730 04:47:51.680029 1, 0xFFFF, sum = 0
2731 04:47:51.680086 2, 0xFFFF, sum = 0
2732 04:47:51.680140 3, 0xFFFF, sum = 0
2733 04:47:51.680194 4, 0xFFFF, sum = 0
2734 04:47:51.680248 5, 0xFFFF, sum = 0
2735 04:47:51.680346 6, 0xFFFF, sum = 0
2736 04:47:51.680402 7, 0xFFFF, sum = 0
2737 04:47:51.680456 8, 0xFFFF, sum = 0
2738 04:47:51.680510 9, 0xFFFF, sum = 0
2739 04:47:51.680563 10, 0xFFFF, sum = 0
2740 04:47:51.680617 11, 0xFFFF, sum = 0
2741 04:47:51.680671 12, 0x0, sum = 1
2742 04:47:51.680724 13, 0x0, sum = 2
2743 04:47:51.680778 14, 0x0, sum = 3
2744 04:47:51.680835 15, 0x0, sum = 4
2745 04:47:51.680889 best_step = 13
2746 04:47:51.680942
2747 04:47:51.680994 ==
2748 04:47:51.681047 Dram Type= 6, Freq= 0, CH_0, rank 0
2749 04:47:51.681100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2750 04:47:51.681183 ==
2751 04:47:51.681236 RX Vref Scan: 1
2752 04:47:51.681288
2753 04:47:51.681341 Set Vref Range= 32 -> 127
2754 04:47:51.681394
2755 04:47:51.681446 RX Vref 32 -> 127, step: 1
2756 04:47:51.681498
2757 04:47:51.681551 RX Delay -13 -> 252, step: 4
2758 04:47:51.681603
2759 04:47:51.681655 Set Vref, RX VrefLevel [Byte0]: 32
2760 04:47:51.681708 [Byte1]: 32
2761 04:47:51.681761
2762 04:47:51.681812 Set Vref, RX VrefLevel [Byte0]: 33
2763 04:47:51.681864 [Byte1]: 33
2764 04:47:51.681917
2765 04:47:51.681969 Set Vref, RX VrefLevel [Byte0]: 34
2766 04:47:51.682021 [Byte1]: 34
2767 04:47:51.682073
2768 04:47:51.682125 Set Vref, RX VrefLevel [Byte0]: 35
2769 04:47:51.682178 [Byte1]: 35
2770 04:47:51.682231
2771 04:47:51.682535 Set Vref, RX VrefLevel [Byte0]: 36
2772 04:47:51.682599 [Byte1]: 36
2773 04:47:51.682654
2774 04:47:51.682708 Set Vref, RX VrefLevel [Byte0]: 37
2775 04:47:51.682763 [Byte1]: 37
2776 04:47:51.682817
2777 04:47:51.682871 Set Vref, RX VrefLevel [Byte0]: 38
2778 04:47:51.682926 [Byte1]: 38
2779 04:47:51.682980
2780 04:47:51.683034 Set Vref, RX VrefLevel [Byte0]: 39
2781 04:47:51.683088 [Byte1]: 39
2782 04:47:51.683171
2783 04:47:51.683256 Set Vref, RX VrefLevel [Byte0]: 40
2784 04:47:51.683339 [Byte1]: 40
2785 04:47:51.683416
2786 04:47:51.683485 Set Vref, RX VrefLevel [Byte0]: 41
2787 04:47:51.683539 [Byte1]: 41
2788 04:47:51.683592
2789 04:47:51.683645 Set Vref, RX VrefLevel [Byte0]: 42
2790 04:47:51.683698 [Byte1]: 42
2791 04:47:51.683751
2792 04:47:51.683804 Set Vref, RX VrefLevel [Byte0]: 43
2793 04:47:51.683857 [Byte1]: 43
2794 04:47:51.683910
2795 04:47:51.683963 Set Vref, RX VrefLevel [Byte0]: 44
2796 04:47:51.684016 [Byte1]: 44
2797 04:47:51.684069
2798 04:47:51.684121 Set Vref, RX VrefLevel [Byte0]: 45
2799 04:47:51.684203 [Byte1]: 45
2800 04:47:51.684317
2801 04:47:51.684390 Set Vref, RX VrefLevel [Byte0]: 46
2802 04:47:51.684443 [Byte1]: 46
2803 04:47:51.684496
2804 04:47:51.684549 Set Vref, RX VrefLevel [Byte0]: 47
2805 04:47:51.684602 [Byte1]: 47
2806 04:47:51.684654
2807 04:47:51.684706 Set Vref, RX VrefLevel [Byte0]: 48
2808 04:47:51.684759 [Byte1]: 48
2809 04:47:51.684811
2810 04:47:51.684863 Set Vref, RX VrefLevel [Byte0]: 49
2811 04:47:51.684916 [Byte1]: 49
2812 04:47:51.684968
2813 04:47:51.685020 Set Vref, RX VrefLevel [Byte0]: 50
2814 04:47:51.685072 [Byte1]: 50
2815 04:47:51.685125
2816 04:47:51.685176 Set Vref, RX VrefLevel [Byte0]: 51
2817 04:47:51.685229 [Byte1]: 51
2818 04:47:51.685282
2819 04:47:51.685334 Set Vref, RX VrefLevel [Byte0]: 52
2820 04:47:51.685386 [Byte1]: 52
2821 04:47:51.685439
2822 04:47:51.685491 Set Vref, RX VrefLevel [Byte0]: 53
2823 04:47:51.685543 [Byte1]: 53
2824 04:47:51.685596
2825 04:47:51.685647 Set Vref, RX VrefLevel [Byte0]: 54
2826 04:47:51.685700 [Byte1]: 54
2827 04:47:51.685752
2828 04:47:51.685804 Set Vref, RX VrefLevel [Byte0]: 55
2829 04:47:51.685857 [Byte1]: 55
2830 04:47:51.685909
2831 04:47:51.685961 Set Vref, RX VrefLevel [Byte0]: 56
2832 04:47:51.686013 [Byte1]: 56
2833 04:47:51.686065
2834 04:47:51.686117 Set Vref, RX VrefLevel [Byte0]: 57
2835 04:47:51.686170 [Byte1]: 57
2836 04:47:51.686224
2837 04:47:51.686276 Set Vref, RX VrefLevel [Byte0]: 58
2838 04:47:51.686328 [Byte1]: 58
2839 04:47:51.686381
2840 04:47:51.686433 Set Vref, RX VrefLevel [Byte0]: 59
2841 04:47:51.686486 [Byte1]: 59
2842 04:47:51.686538
2843 04:47:51.686590 Set Vref, RX VrefLevel [Byte0]: 60
2844 04:47:51.686643 [Byte1]: 60
2845 04:47:51.686695
2846 04:47:51.686747 Set Vref, RX VrefLevel [Byte0]: 61
2847 04:47:51.686800 [Byte1]: 61
2848 04:47:51.686853
2849 04:47:51.686905 Set Vref, RX VrefLevel [Byte0]: 62
2850 04:47:51.686957 [Byte1]: 62
2851 04:47:51.687009
2852 04:47:51.687061 Set Vref, RX VrefLevel [Byte0]: 63
2853 04:47:51.687134 [Byte1]: 63
2854 04:47:51.687188
2855 04:47:51.687240 Set Vref, RX VrefLevel [Byte0]: 64
2856 04:47:51.687293 [Byte1]: 64
2857 04:47:51.687346
2858 04:47:51.687398 Set Vref, RX VrefLevel [Byte0]: 65
2859 04:47:51.687450 [Byte1]: 65
2860 04:47:51.687503
2861 04:47:51.687555 Set Vref, RX VrefLevel [Byte0]: 66
2862 04:47:51.687608 [Byte1]: 66
2863 04:47:51.687661
2864 04:47:51.687713 Set Vref, RX VrefLevel [Byte0]: 67
2865 04:47:51.687765 [Byte1]: 67
2866 04:47:51.687818
2867 04:47:51.687870 Set Vref, RX VrefLevel [Byte0]: 68
2868 04:47:51.687923 [Byte1]: 68
2869 04:47:51.687976
2870 04:47:51.688028 Set Vref, RX VrefLevel [Byte0]: 69
2871 04:47:51.688081 [Byte1]: 69
2872 04:47:51.688133
2873 04:47:51.688185 Set Vref, RX VrefLevel [Byte0]: 70
2874 04:47:51.688237 [Byte1]: 70
2875 04:47:51.688317
2876 04:47:51.688387 Final RX Vref Byte 0 = 57 to rank0
2877 04:47:51.688440 Final RX Vref Byte 1 = 48 to rank0
2878 04:47:51.688495 Final RX Vref Byte 0 = 57 to rank1
2879 04:47:51.688548 Final RX Vref Byte 1 = 48 to rank1==
2880 04:47:51.688602 Dram Type= 6, Freq= 0, CH_0, rank 0
2881 04:47:51.688655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 04:47:51.688708 ==
2883 04:47:51.688760 DQS Delay:
2884 04:47:51.688813 DQS0 = 0, DQS1 = 0
2885 04:47:51.688865 DQM Delay:
2886 04:47:51.688917 DQM0 = 120, DQM1 = 112
2887 04:47:51.688970 DQ Delay:
2888 04:47:51.689023 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =120
2889 04:47:51.689076 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2890 04:47:51.689129 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2891 04:47:51.689182 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2892 04:47:51.689235
2893 04:47:51.689287
2894 04:47:51.689339 [DQSOSCAuto] RK0, (LSB)MR18= 0x130d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2895 04:47:51.689394 CH0 RK0: MR19=404, MR18=130D
2896 04:47:51.689447 CH0_RK0: MR19=0x404, MR18=0x130D, DQSOSC=402, MR23=63, INC=40, DEC=27
2897 04:47:51.689500
2898 04:47:51.689552 ----->DramcWriteLeveling(PI) begin...
2899 04:47:51.689606 ==
2900 04:47:51.689659 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 04:47:51.689711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 04:47:51.689764 ==
2903 04:47:51.689817 Write leveling (Byte 0): 33 => 33
2904 04:47:51.689870 Write leveling (Byte 1): 28 => 28
2905 04:47:51.689923 DramcWriteLeveling(PI) end<-----
2906 04:47:51.689976
2907 04:47:51.690028 ==
2908 04:47:51.690081 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 04:47:51.690133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 04:47:51.690187 ==
2911 04:47:51.690239 [Gating] SW mode calibration
2912 04:47:51.690292 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2913 04:47:51.690346 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2914 04:47:51.690399 0 15 0 | B1->B0 | 3333 2d2d | 0 0 | (0 0) (0 0)
2915 04:47:51.690452 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 04:47:51.690505 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2917 04:47:52.515187 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 04:47:52.515363 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 04:47:52.515693 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 04:47:52.515801 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
2921 04:47:52.515899 0 15 28 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 1)
2922 04:47:52.515994 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2923 04:47:52.516089 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 04:47:52.516199 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 04:47:52.516304 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 04:47:52.516401 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 04:47:52.516500 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 04:47:52.516597 1 0 24 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
2929 04:47:52.516690 1 0 28 | B1->B0 | 3939 3d3d | 1 1 | (0 0) (1 1)
2930 04:47:52.516785 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2931 04:47:52.516879 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 04:47:52.516971 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 04:47:52.517070 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 04:47:52.517163 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 04:47:52.517259 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 04:47:52.517355 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2937 04:47:52.517452 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2938 04:47:52.517546 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2939 04:47:52.517641 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 04:47:52.517739 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 04:47:52.517837 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 04:47:52.517935 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 04:47:52.518032 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 04:47:52.518128 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 04:47:52.518226 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 04:47:52.518324 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 04:47:52.518420 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 04:47:52.518515 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 04:47:52.518610 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 04:47:52.518703 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 04:47:52.518794 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 04:47:52.518888 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 04:47:52.518981 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2954 04:47:52.519077 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2955 04:47:52.519176 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2956 04:47:52.519273 Total UI for P1: 0, mck2ui 16
2957 04:47:52.519371 best dqsien dly found for B0: ( 1, 3, 30)
2958 04:47:52.519466 Total UI for P1: 0, mck2ui 16
2959 04:47:52.519564 best dqsien dly found for B1: ( 1, 3, 30)
2960 04:47:52.519659 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2961 04:47:52.519755 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2962 04:47:52.519850
2963 04:47:52.519943 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2964 04:47:52.520036 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2965 04:47:52.520127 [Gating] SW calibration Done
2966 04:47:52.520226 ==
2967 04:47:52.520325 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 04:47:52.520423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 04:47:52.520518 ==
2970 04:47:52.520613 RX Vref Scan: 0
2971 04:47:52.520704
2972 04:47:52.520799 RX Vref 0 -> 0, step: 1
2973 04:47:52.520891
2974 04:47:52.520988 RX Delay -40 -> 252, step: 8
2975 04:47:52.521082 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2976 04:47:52.521180 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2977 04:47:52.521273 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2978 04:47:52.521367 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2979 04:47:52.521461 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2980 04:47:52.521557 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2981 04:47:52.521651 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2982 04:47:52.521748 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2983 04:47:52.521849 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2984 04:47:52.521944 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2985 04:47:52.522039 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2986 04:47:52.522132 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2987 04:47:52.522225 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2988 04:47:52.522321 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2989 04:47:52.522417 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2990 04:47:52.522513 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2991 04:47:52.522608 ==
2992 04:47:52.522700 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 04:47:52.522797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 04:47:52.522890 ==
2995 04:47:52.522984 DQS Delay:
2996 04:47:52.523077 DQS0 = 0, DQS1 = 0
2997 04:47:52.523171 DQM Delay:
2998 04:47:52.523265 DQM0 = 122, DQM1 = 112
2999 04:47:52.523363 DQ Delay:
3000 04:47:52.523459 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
3001 04:47:52.523556 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
3002 04:47:52.523651 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3003 04:47:52.523744 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
3004 04:47:52.523840
3005 04:47:52.523937
3006 04:47:52.524034 ==
3007 04:47:52.524132 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 04:47:52.524224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 04:47:52.524325 ==
3010 04:47:52.524416
3011 04:47:52.524508
3012 04:47:52.524602 TX Vref Scan disable
3013 04:47:52.524699 == TX Byte 0 ==
3014 04:47:52.524795 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3015 04:47:52.524893 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3016 04:47:52.524989 == TX Byte 1 ==
3017 04:47:52.525080 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3018 04:47:52.525177 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3019 04:47:52.525270 ==
3020 04:47:52.525366 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 04:47:52.525463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 04:47:52.525560 ==
3023 04:47:52.525652 TX Vref=22, minBit 1, minWin=25, winSum=416
3024 04:47:52.525750 TX Vref=24, minBit 1, minWin=25, winSum=416
3025 04:47:52.525844 TX Vref=26, minBit 3, minWin=25, winSum=419
3026 04:47:52.526158 TX Vref=28, minBit 0, minWin=26, winSum=427
3027 04:47:52.526269 TX Vref=30, minBit 3, minWin=26, winSum=430
3028 04:47:52.526366 TX Vref=32, minBit 0, minWin=26, winSum=428
3029 04:47:52.526462 [TxChooseVref] Worse bit 3, Min win 26, Win sum 430, Final Vref 30
3030 04:47:52.526560
3031 04:47:52.526652 Final TX Range 1 Vref 30
3032 04:47:52.526748
3033 04:47:52.526839 ==
3034 04:47:52.526938 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 04:47:52.527030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 04:47:52.527123 ==
3037 04:47:52.527220
3038 04:47:52.527311
3039 04:47:52.527406 TX Vref Scan disable
3040 04:47:52.527499 == TX Byte 0 ==
3041 04:47:52.527597 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3042 04:47:52.527693 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3043 04:47:52.527790 == TX Byte 1 ==
3044 04:47:52.527887 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3045 04:47:52.527985 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3046 04:47:52.528080
3047 04:47:52.528174 [DATLAT]
3048 04:47:52.528270 Freq=1200, CH0 RK1
3049 04:47:52.528375
3050 04:47:52.528468 DATLAT Default: 0xd
3051 04:47:52.528565 0, 0xFFFF, sum = 0
3052 04:47:52.528661 1, 0xFFFF, sum = 0
3053 04:47:52.528759 2, 0xFFFF, sum = 0
3054 04:47:52.528858 3, 0xFFFF, sum = 0
3055 04:47:52.528955 4, 0xFFFF, sum = 0
3056 04:47:52.529054 5, 0xFFFF, sum = 0
3057 04:47:52.529149 6, 0xFFFF, sum = 0
3058 04:47:52.529248 7, 0xFFFF, sum = 0
3059 04:47:52.529344 8, 0xFFFF, sum = 0
3060 04:47:52.529440 9, 0xFFFF, sum = 0
3061 04:47:52.529535 10, 0xFFFF, sum = 0
3062 04:47:52.529632 11, 0xFFFF, sum = 0
3063 04:47:52.529727 12, 0x0, sum = 1
3064 04:47:52.529838 13, 0x0, sum = 2
3065 04:47:52.529939 14, 0x0, sum = 3
3066 04:47:52.530040 15, 0x0, sum = 4
3067 04:47:52.530140 best_step = 13
3068 04:47:52.530241
3069 04:47:52.530337 ==
3070 04:47:52.530428 Dram Type= 6, Freq= 0, CH_0, rank 1
3071 04:47:52.530524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 04:47:52.530618 ==
3073 04:47:52.530714 RX Vref Scan: 0
3074 04:47:52.530807
3075 04:47:52.530897 RX Vref 0 -> 0, step: 1
3076 04:47:52.530996
3077 04:47:52.531087 RX Delay -13 -> 252, step: 4
3078 04:47:52.531181 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3079 04:47:52.531274 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3080 04:47:52.531368 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3081 04:47:52.531466 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3082 04:47:52.531558 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3083 04:47:52.531656 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3084 04:47:52.531748 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3085 04:47:52.531842 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3086 04:47:52.531936 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3087 04:47:52.532029 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3088 04:47:52.532126 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3089 04:47:52.532218 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3090 04:47:52.532318 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3091 04:47:52.532412 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3092 04:47:52.532510 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3093 04:47:52.532609 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3094 04:47:52.532707 ==
3095 04:47:52.532803 Dram Type= 6, Freq= 0, CH_0, rank 1
3096 04:47:52.532896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3097 04:47:52.532992 ==
3098 04:47:52.533088 DQS Delay:
3099 04:47:52.533185 DQS0 = 0, DQS1 = 0
3100 04:47:52.533283 DQM Delay:
3101 04:47:52.533382 DQM0 = 120, DQM1 = 110
3102 04:47:52.533480 DQ Delay:
3103 04:47:52.533576 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3104 04:47:52.533675 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3105 04:47:52.533772 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3106 04:47:52.533867 DQ12 =116, DQ13 =116, DQ14 =122, DQ15 =120
3107 04:47:52.533964
3108 04:47:52.534058
3109 04:47:52.534150 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3110 04:47:52.534250 CH0 RK1: MR19=403, MR18=11F2
3111 04:47:52.534342 CH0_RK1: MR19=0x403, MR18=0x11F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3112 04:47:52.534439 [RxdqsGatingPostProcess] freq 1200
3113 04:47:52.534534 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3114 04:47:52.534632 best DQS0 dly(2T, 0.5T) = (0, 11)
3115 04:47:52.534728 best DQS1 dly(2T, 0.5T) = (0, 12)
3116 04:47:52.534824 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3117 04:47:52.534917 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3118 04:47:52.535013 best DQS0 dly(2T, 0.5T) = (0, 11)
3119 04:47:52.535113 best DQS1 dly(2T, 0.5T) = (0, 11)
3120 04:47:52.535209 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3121 04:47:52.535304 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3122 04:47:52.535398 Pre-setting of DQS Precalculation
3123 04:47:52.535496 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3124 04:47:52.535594 ==
3125 04:47:52.535691 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 04:47:52.535784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 04:47:52.535879 ==
3128 04:47:52.535974 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3129 04:47:52.536072 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3130 04:47:52.536167 [CA 0] Center 37 (7~68) winsize 62
3131 04:47:52.536262 [CA 1] Center 37 (7~68) winsize 62
3132 04:47:52.536363 [CA 2] Center 35 (5~65) winsize 61
3133 04:47:52.536460 [CA 3] Center 34 (4~64) winsize 61
3134 04:47:52.536558 [CA 4] Center 34 (4~64) winsize 61
3135 04:47:52.536655 [CA 5] Center 33 (3~63) winsize 61
3136 04:47:52.536750
3137 04:47:52.536849 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3138 04:47:52.536948
3139 04:47:52.537040 [CATrainingPosCal] consider 1 rank data
3140 04:47:52.537135 u2DelayCellTimex100 = 270/100 ps
3141 04:47:52.537230 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3142 04:47:52.537326 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3143 04:47:52.537424 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3144 04:47:52.537524 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3145 04:47:52.537617 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3146 04:47:52.537713 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3147 04:47:52.537807
3148 04:47:52.537901 CA PerBit enable=1, Macro0, CA PI delay=33
3149 04:47:52.537995
3150 04:47:52.538087 [CBTSetCACLKResult] CA Dly = 33
3151 04:47:52.538182 CS Dly: 7 (0~38)
3152 04:47:52.538274 ==
3153 04:47:52.538370 Dram Type= 6, Freq= 0, CH_1, rank 1
3154 04:47:52.538468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3155 04:47:52.538566 ==
3156 04:47:52.538661 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3157 04:47:52.538760 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3158 04:47:52.538857 [CA 0] Center 37 (7~68) winsize 62
3159 04:47:52.538952 [CA 1] Center 37 (7~68) winsize 62
3160 04:47:52.539267 [CA 2] Center 35 (5~65) winsize 61
3161 04:47:52.539376 [CA 3] Center 34 (4~65) winsize 62
3162 04:47:52.539475 [CA 4] Center 35 (5~65) winsize 61
3163 04:47:52.539569 [CA 5] Center 34 (4~64) winsize 61
3164 04:47:52.539664
3165 04:47:52.539760 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3166 04:47:52.539856
3167 04:47:52.539953 [CATrainingPosCal] consider 2 rank data
3168 04:47:52.540051 u2DelayCellTimex100 = 270/100 ps
3169 04:47:52.540152 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3170 04:47:52.540252 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3171 04:47:52.540360 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3172 04:47:52.540458 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3173 04:47:52.540557 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3174 04:47:52.540657 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3175 04:47:52.540755
3176 04:47:52.540853 CA PerBit enable=1, Macro0, CA PI delay=33
3177 04:47:52.540946
3178 04:47:52.541040 [CBTSetCACLKResult] CA Dly = 33
3179 04:47:52.541138 CS Dly: 8 (0~40)
3180 04:47:52.541236
3181 04:47:52.541332 ----->DramcWriteLeveling(PI) begin...
3182 04:47:52.541431 ==
3183 04:47:52.541529 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 04:47:52.541620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 04:47:52.541718 ==
3186 04:47:52.541810 Write leveling (Byte 0): 26 => 26
3187 04:47:52.541905 Write leveling (Byte 1): 28 => 28
3188 04:47:52.541999 DramcWriteLeveling(PI) end<-----
3189 04:47:52.542093
3190 04:47:52.542185 ==
3191 04:47:52.542277 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 04:47:52.542369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 04:47:52.542464 ==
3194 04:47:52.542557 [Gating] SW mode calibration
3195 04:47:52.542649 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3196 04:47:52.542749 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3197 04:47:52.542843 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3198 04:47:52.542938 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 04:47:52.543032 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 04:47:52.543124 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 04:47:52.543220 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 04:47:52.543316 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 04:47:52.543410 0 15 24 | B1->B0 | 3434 2f2f | 0 1 | (0 1) (1 0)
3204 04:47:52.543503 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3205 04:47:52.543595 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 04:47:52.543690 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 04:47:52.543783 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 04:47:52.543878 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 04:47:52.543974 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 04:47:52.544067 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 04:47:52.544164 1 0 24 | B1->B0 | 2e2e 3d3d | 0 1 | (0 0) (0 0)
3212 04:47:52.544257 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 04:47:52.544365 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 04:47:52.544461 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 04:47:52.544555 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 04:47:52.544654 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 04:47:52.544746 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 04:47:52.544839 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 04:47:52.544936 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3220 04:47:52.545028 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3221 04:47:52.545127 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 04:47:52.545221 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 04:47:52.545315 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 04:47:52.545408 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 04:47:52.545503 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 04:47:52.545597 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 04:47:52.545691 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 04:47:52.545787 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 04:47:52.545882 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 04:47:52.545976 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 04:47:52.546068 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 04:47:52.546165 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 04:47:52.546258 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 04:47:52.546353 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 04:47:52.546448 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3236 04:47:52.546539 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3237 04:47:52.546638 Total UI for P1: 0, mck2ui 16
3238 04:47:52.546731 best dqsien dly found for B1: ( 1, 3, 24)
3239 04:47:52.546826 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3240 04:47:52.546919 Total UI for P1: 0, mck2ui 16
3241 04:47:52.547014 best dqsien dly found for B0: ( 1, 3, 26)
3242 04:47:52.547112 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3243 04:47:52.547205 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3244 04:47:52.547303
3245 04:47:52.547395 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3246 04:47:52.547492 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3247 04:47:52.547587 [Gating] SW calibration Done
3248 04:47:52.547682 ==
3249 04:47:52.547776 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 04:47:52.547869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 04:47:52.547967 ==
3252 04:47:52.548059 RX Vref Scan: 0
3253 04:47:52.548153
3254 04:47:52.548247 RX Vref 0 -> 0, step: 1
3255 04:47:52.548347
3256 04:47:52.548441 RX Delay -40 -> 252, step: 8
3257 04:47:52.548540 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3258 04:47:52.548634 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3259 04:47:52.548728 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3260 04:47:52.548826 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3261 04:47:52.548926 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3262 04:47:52.549021 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3263 04:47:52.549118 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3264 04:47:52.549428 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3265 04:47:52.549536 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3266 04:47:52.549636 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3267 04:47:52.549736 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3268 04:47:52.549834 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3269 04:47:52.549928 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3270 04:47:52.550023 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3271 04:47:52.550122 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3272 04:47:52.550220 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3273 04:47:52.550318 ==
3274 04:47:52.550416 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 04:47:52.550512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 04:47:52.550609 ==
3277 04:47:52.550705 DQS Delay:
3278 04:47:52.550801 DQS0 = 0, DQS1 = 0
3279 04:47:52.550895 DQM Delay:
3280 04:47:52.551000 DQM0 = 119, DQM1 = 116
3281 04:47:52.551096 DQ Delay:
3282 04:47:52.551188 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3283 04:47:52.551283 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3284 04:47:52.551377 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3285 04:47:52.551473 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3286 04:47:52.551568
3287 04:47:52.551662
3288 04:47:52.551756 ==
3289 04:47:52.551848 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 04:47:52.551942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 04:47:52.552034 ==
3292 04:47:52.552128
3293 04:47:52.552218
3294 04:47:52.552320 TX Vref Scan disable
3295 04:47:52.552419 == TX Byte 0 ==
3296 04:47:52.552510 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3297 04:47:52.552607 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3298 04:47:52.552701 == TX Byte 1 ==
3299 04:47:52.552799 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3300 04:47:52.552891 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3301 04:47:52.552984 ==
3302 04:47:52.553076 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 04:47:52.553167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 04:47:52.553261 ==
3305 04:47:52.553354 TX Vref=22, minBit 11, minWin=24, winSum=409
3306 04:47:52.553452 TX Vref=24, minBit 9, minWin=24, winSum=416
3307 04:47:52.553544 TX Vref=26, minBit 1, minWin=26, winSum=427
3308 04:47:52.553643 TX Vref=28, minBit 9, minWin=25, winSum=427
3309 04:47:52.553738 TX Vref=30, minBit 9, minWin=26, winSum=429
3310 04:47:52.553832 TX Vref=32, minBit 9, minWin=26, winSum=434
3311 04:47:52.553925 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 32
3312 04:47:52.554022
3313 04:47:52.554115 Final TX Range 1 Vref 32
3314 04:47:52.554208
3315 04:47:52.554305 ==
3316 04:47:52.554397 Dram Type= 6, Freq= 0, CH_1, rank 0
3317 04:47:52.554495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3318 04:47:52.554591 ==
3319 04:47:52.554684
3320 04:47:52.554774
3321 04:47:52.554866 TX Vref Scan disable
3322 04:47:52.554957 == TX Byte 0 ==
3323 04:47:52.555051 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3324 04:47:52.555144 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3325 04:47:52.555240 == TX Byte 1 ==
3326 04:47:52.555331 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3327 04:47:52.555428 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3328 04:47:52.555520
3329 04:47:52.555616 [DATLAT]
3330 04:47:52.555707 Freq=1200, CH1 RK0
3331 04:47:52.555804
3332 04:47:52.555895 DATLAT Default: 0xd
3333 04:47:52.555990 0, 0xFFFF, sum = 0
3334 04:47:52.556085 1, 0xFFFF, sum = 0
3335 04:47:52.556180 2, 0xFFFF, sum = 0
3336 04:47:52.556274 3, 0xFFFF, sum = 0
3337 04:47:52.556375 4, 0xFFFF, sum = 0
3338 04:47:52.556473 5, 0xFFFF, sum = 0
3339 04:47:52.556568 6, 0xFFFF, sum = 0
3340 04:47:52.556660 7, 0xFFFF, sum = 0
3341 04:47:52.556758 8, 0xFFFF, sum = 0
3342 04:47:52.556851 9, 0xFFFF, sum = 0
3343 04:47:52.556949 10, 0xFFFF, sum = 0
3344 04:47:52.557044 11, 0xFFFF, sum = 0
3345 04:47:52.557139 12, 0x0, sum = 1
3346 04:47:52.557236 13, 0x0, sum = 2
3347 04:47:52.557329 14, 0x0, sum = 3
3348 04:47:52.557426 15, 0x0, sum = 4
3349 04:47:52.557519 best_step = 13
3350 04:47:52.557616
3351 04:47:52.557709 ==
3352 04:47:52.557802 Dram Type= 6, Freq= 0, CH_1, rank 0
3353 04:47:52.557894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3354 04:47:52.557985 ==
3355 04:47:52.558079 RX Vref Scan: 1
3356 04:47:52.558169
3357 04:47:52.558265 Set Vref Range= 32 -> 127
3358 04:47:52.558359
3359 04:47:52.558449 RX Vref 32 -> 127, step: 1
3360 04:47:52.558546
3361 04:47:52.558637 RX Delay -5 -> 252, step: 4
3362 04:47:52.558733
3363 04:47:52.558824 Set Vref, RX VrefLevel [Byte0]: 32
3364 04:47:52.558918 [Byte1]: 32
3365 04:47:52.559012
3366 04:47:52.559101 Set Vref, RX VrefLevel [Byte0]: 33
3367 04:47:52.559196 [Byte1]: 33
3368 04:47:52.559287
3369 04:47:52.559380 Set Vref, RX VrefLevel [Byte0]: 34
3370 04:47:52.559472 [Byte1]: 34
3371 04:47:52.559565
3372 04:47:52.559661 Set Vref, RX VrefLevel [Byte0]: 35
3373 04:47:52.559754 [Byte1]: 35
3374 04:47:52.559847
3375 04:47:52.559939 Set Vref, RX VrefLevel [Byte0]: 36
3376 04:47:52.560030 [Byte1]: 36
3377 04:47:52.560126
3378 04:47:52.560219 Set Vref, RX VrefLevel [Byte0]: 37
3379 04:47:52.560322 [Byte1]: 37
3380 04:47:52.560416
3381 04:47:52.560509 Set Vref, RX VrefLevel [Byte0]: 38
3382 04:47:52.560606 [Byte1]: 38
3383 04:47:52.560697
3384 04:47:52.560794 Set Vref, RX VrefLevel [Byte0]: 39
3385 04:47:52.560887 [Byte1]: 39
3386 04:47:52.560981
3387 04:47:52.561073 Set Vref, RX VrefLevel [Byte0]: 40
3388 04:47:52.561166 [Byte1]: 40
3389 04:47:52.561260
3390 04:47:52.561352 Set Vref, RX VrefLevel [Byte0]: 41
3391 04:47:52.561449 [Byte1]: 41
3392 04:47:52.561545
3393 04:47:52.561637 Set Vref, RX VrefLevel [Byte0]: 42
3394 04:47:52.561728 [Byte1]: 42
3395 04:47:52.561823
3396 04:47:52.561915 Set Vref, RX VrefLevel [Byte0]: 43
3397 04:47:52.562008 [Byte1]: 43
3398 04:47:52.562099
3399 04:47:52.562194 Set Vref, RX VrefLevel [Byte0]: 44
3400 04:47:52.562288 [Byte1]: 44
3401 04:47:52.562379
3402 04:47:52.562474 Set Vref, RX VrefLevel [Byte0]: 45
3403 04:47:52.562569 [Byte1]: 45
3404 04:47:52.562664
3405 04:47:52.562760 Set Vref, RX VrefLevel [Byte0]: 46
3406 04:47:52.562854 [Byte1]: 46
3407 04:47:52.562948
3408 04:47:52.563041 Set Vref, RX VrefLevel [Byte0]: 47
3409 04:47:52.563139 [Byte1]: 47
3410 04:47:52.563235
3411 04:47:52.563330 Set Vref, RX VrefLevel [Byte0]: 48
3412 04:47:52.563425 [Byte1]: 48
3413 04:47:52.563518
3414 04:47:52.563612 Set Vref, RX VrefLevel [Byte0]: 49
3415 04:47:52.563709 [Byte1]: 49
3416 04:47:52.563805
3417 04:47:52.563900 Set Vref, RX VrefLevel [Byte0]: 50
3418 04:47:52.563997 [Byte1]: 50
3419 04:47:52.564093
3420 04:47:52.564189 Set Vref, RX VrefLevel [Byte0]: 51
3421 04:47:52.564290 [Byte1]: 51
3422 04:47:52.564388
3423 04:47:52.564482 Set Vref, RX VrefLevel [Byte0]: 52
3424 04:47:52.564579 [Byte1]: 52
3425 04:47:52.564673
3426 04:47:52.564987 Set Vref, RX VrefLevel [Byte0]: 53
3427 04:47:52.565094 [Byte1]: 53
3428 04:47:52.565192
3429 04:47:52.565287 Set Vref, RX VrefLevel [Byte0]: 54
3430 04:47:52.565382 [Byte1]: 54
3431 04:47:52.565475
3432 04:47:52.565568 Set Vref, RX VrefLevel [Byte0]: 55
3433 04:47:52.565662 [Byte1]: 55
3434 04:47:52.565754
3435 04:47:52.565847 Set Vref, RX VrefLevel [Byte0]: 56
3436 04:47:52.565937 [Byte1]: 56
3437 04:47:52.566031
3438 04:47:52.566123 Set Vref, RX VrefLevel [Byte0]: 57
3439 04:47:52.566215 [Byte1]: 57
3440 04:47:52.566310
3441 04:47:52.566401 Set Vref, RX VrefLevel [Byte0]: 58
3442 04:47:52.566494 [Byte1]: 58
3443 04:47:52.566588
3444 04:47:52.566682 Set Vref, RX VrefLevel [Byte0]: 59
3445 04:47:52.566781 [Byte1]: 59
3446 04:47:52.566873
3447 04:47:52.566967 Set Vref, RX VrefLevel [Byte0]: 60
3448 04:47:52.567059 [Byte1]: 60
3449 04:47:52.567153
3450 04:47:52.567247 Set Vref, RX VrefLevel [Byte0]: 61
3451 04:47:52.567341 [Byte1]: 61
3452 04:47:52.567431
3453 04:47:52.567525 Set Vref, RX VrefLevel [Byte0]: 62
3454 04:47:52.567616 [Byte1]: 62
3455 04:47:52.567711
3456 04:47:52.567801 Set Vref, RX VrefLevel [Byte0]: 63
3457 04:47:52.567892 [Byte1]: 63
3458 04:47:52.567989
3459 04:47:52.568079 Set Vref, RX VrefLevel [Byte0]: 64
3460 04:47:52.568174 [Byte1]: 64
3461 04:47:52.568266
3462 04:47:52.568402 Set Vref, RX VrefLevel [Byte0]: 65
3463 04:47:52.568502 [Byte1]: 65
3464 04:47:52.568597
3465 04:47:52.568698 Set Vref, RX VrefLevel [Byte0]: 66
3466 04:47:52.568787 [Byte1]: 66
3467 04:47:52.568873
3468 04:47:52.568960 Set Vref, RX VrefLevel [Byte0]: 67
3469 04:47:52.569048 [Byte1]: 67
3470 04:47:52.569134
3471 04:47:52.569219 Set Vref, RX VrefLevel [Byte0]: 68
3472 04:47:52.569303 [Byte1]: 68
3473 04:47:52.569387
3474 04:47:52.569472 Final RX Vref Byte 0 = 56 to rank0
3475 04:47:52.569560 Final RX Vref Byte 1 = 56 to rank0
3476 04:47:52.569644 Final RX Vref Byte 0 = 56 to rank1
3477 04:47:52.569729 Final RX Vref Byte 1 = 56 to rank1==
3478 04:47:52.569813 Dram Type= 6, Freq= 0, CH_1, rank 0
3479 04:47:52.569897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 04:47:52.569960 ==
3481 04:47:52.570018 DQS Delay:
3482 04:47:52.570073 DQS0 = 0, DQS1 = 0
3483 04:47:52.570128 DQM Delay:
3484 04:47:52.570182 DQM0 = 120, DQM1 = 118
3485 04:47:52.570236 DQ Delay:
3486 04:47:52.570290 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3487 04:47:52.570345 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3488 04:47:52.570400 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3489 04:47:52.570455 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3490 04:47:52.570540
3491 04:47:52.570626
3492 04:47:52.570713 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe11, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3493 04:47:52.570798 CH1 RK0: MR19=304, MR18=FE11
3494 04:47:52.570883 CH1_RK0: MR19=0x304, MR18=0xFE11, DQSOSC=403, MR23=63, INC=40, DEC=26
3495 04:47:52.570967
3496 04:47:52.571027 ----->DramcWriteLeveling(PI) begin...
3497 04:47:52.571083 ==
3498 04:47:52.571138 Dram Type= 6, Freq= 0, CH_1, rank 1
3499 04:47:52.571192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 04:47:52.571247 ==
3501 04:47:52.571301 Write leveling (Byte 0): 26 => 26
3502 04:47:52.571356 Write leveling (Byte 1): 30 => 30
3503 04:47:52.571410 DramcWriteLeveling(PI) end<-----
3504 04:47:52.571463
3505 04:47:52.571521 ==
3506 04:47:52.571578 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 04:47:52.571633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 04:47:52.571688 ==
3509 04:47:52.571741 [Gating] SW mode calibration
3510 04:47:52.571795 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3511 04:47:52.571850 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3512 04:47:52.571905 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 04:47:52.571959 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 04:47:52.572012 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 04:47:52.572069 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 04:47:52.572128 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 04:47:52.572212 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3518 04:47:52.572303 0 15 24 | B1->B0 | 2a2a 3434 | 0 0 | (0 1) (0 0)
3519 04:47:52.572361 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3520 04:47:52.572416 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 04:47:52.572471 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 04:47:52.572525 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 04:47:52.572579 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 04:47:52.572639 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 04:47:52.572704 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3526 04:47:52.572762 1 0 24 | B1->B0 | 4343 2f2f | 0 0 | (0 0) (0 0)
3527 04:47:52.572817 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3528 04:47:52.572871 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 04:47:52.572925 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 04:47:52.572979 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 04:47:52.573033 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 04:47:52.573087 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 04:47:52.573145 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 04:47:52.573202 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3535 04:47:52.573256 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3536 04:47:52.573310 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 04:47:52.573364 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 04:47:52.573417 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 04:47:52.573471 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 04:47:52.573528 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 04:47:52.573585 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 04:47:52.573640 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 04:47:52.573694 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 04:47:52.573748 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 04:47:52.574011 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 04:47:52.574131 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 04:47:52.574237 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 04:47:52.574332 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 04:47:52.574412 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3550 04:47:52.574503 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3551 04:47:52.574589 Total UI for P1: 0, mck2ui 16
3552 04:47:52.574674 best dqsien dly found for B1: ( 1, 3, 20)
3553 04:47:52.574758 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3554 04:47:52.574835 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3555 04:47:52.574895 Total UI for P1: 0, mck2ui 16
3556 04:47:52.574951 best dqsien dly found for B0: ( 1, 3, 26)
3557 04:47:52.575005 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3558 04:47:52.575061 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3559 04:47:52.575116
3560 04:47:52.575170 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3561 04:47:52.575225 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3562 04:47:52.575279 [Gating] SW calibration Done
3563 04:47:52.575337 ==
3564 04:47:52.575394 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 04:47:52.575450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 04:47:52.575505 ==
3567 04:47:52.575559 RX Vref Scan: 0
3568 04:47:52.575612
3569 04:47:52.575667 RX Vref 0 -> 0, step: 1
3570 04:47:52.575720
3571 04:47:52.575774 RX Delay -40 -> 252, step: 8
3572 04:47:52.575828 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3573 04:47:52.575885 iDelay=200, Bit 1, Center 119 (56 ~ 183) 128
3574 04:47:52.575943 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3575 04:47:52.575998 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3576 04:47:52.576052 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3577 04:47:52.576106 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3578 04:47:52.576160 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3579 04:47:52.576214 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3580 04:47:52.576267 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3581 04:47:52.576329 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3582 04:47:52.576389 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3583 04:47:52.576446 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3584 04:47:52.576501 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3585 04:47:52.576555 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3586 04:47:52.576609 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3587 04:47:52.576663 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3588 04:47:52.576717 ==
3589 04:47:52.576772 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 04:47:52.576826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 04:47:52.576880 ==
3592 04:47:52.576935 DQS Delay:
3593 04:47:52.576988 DQS0 = 0, DQS1 = 0
3594 04:47:52.577047 DQM Delay:
3595 04:47:52.577103 DQM0 = 121, DQM1 = 116
3596 04:47:52.577158 DQ Delay:
3597 04:47:52.577212 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =119
3598 04:47:52.577267 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3599 04:47:52.577321 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3600 04:47:52.577375 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3601 04:47:52.577428
3602 04:47:52.577485
3603 04:47:52.577541 ==
3604 04:47:52.577596 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 04:47:52.577650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 04:47:52.577704 ==
3607 04:47:52.577758
3608 04:47:52.577811
3609 04:47:52.577865 TX Vref Scan disable
3610 04:47:52.577918 == TX Byte 0 ==
3611 04:47:52.577972 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3612 04:47:52.578026 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3613 04:47:52.578080 == TX Byte 1 ==
3614 04:47:52.578133 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3615 04:47:52.578190 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3616 04:47:52.578246 ==
3617 04:47:52.578301 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 04:47:52.578355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 04:47:52.578409 ==
3620 04:47:52.578463 TX Vref=22, minBit 9, minWin=25, winSum=421
3621 04:47:52.578517 TX Vref=24, minBit 1, minWin=26, winSum=426
3622 04:47:52.578570 TX Vref=26, minBit 9, minWin=26, winSum=432
3623 04:47:52.578632 TX Vref=28, minBit 9, minWin=26, winSum=431
3624 04:47:52.578688 TX Vref=30, minBit 6, minWin=26, winSum=436
3625 04:47:52.578743 TX Vref=32, minBit 9, minWin=26, winSum=435
3626 04:47:52.578798 [TxChooseVref] Worse bit 6, Min win 26, Win sum 436, Final Vref 30
3627 04:47:52.578856
3628 04:47:52.578913 Final TX Range 1 Vref 30
3629 04:47:52.578967
3630 04:47:52.579020 ==
3631 04:47:52.579074 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 04:47:52.579127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 04:47:52.579182 ==
3634 04:47:52.579235
3635 04:47:52.579288
3636 04:47:52.579341 TX Vref Scan disable
3637 04:47:52.579400 == TX Byte 0 ==
3638 04:47:52.579458 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3639 04:47:52.579515 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3640 04:47:52.579569 == TX Byte 1 ==
3641 04:47:52.579623 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3642 04:47:52.579678 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3643 04:47:52.579732
3644 04:47:52.579785 [DATLAT]
3645 04:47:52.579838 Freq=1200, CH1 RK1
3646 04:47:52.579895
3647 04:47:52.579950 DATLAT Default: 0xd
3648 04:47:52.580006 0, 0xFFFF, sum = 0
3649 04:47:52.580062 1, 0xFFFF, sum = 0
3650 04:47:52.580117 2, 0xFFFF, sum = 0
3651 04:47:52.580171 3, 0xFFFF, sum = 0
3652 04:47:52.580226 4, 0xFFFF, sum = 0
3653 04:47:52.580281 5, 0xFFFF, sum = 0
3654 04:47:52.580345 6, 0xFFFF, sum = 0
3655 04:47:52.580400 7, 0xFFFF, sum = 0
3656 04:47:52.580455 8, 0xFFFF, sum = 0
3657 04:47:52.580513 9, 0xFFFF, sum = 0
3658 04:47:52.580571 10, 0xFFFF, sum = 0
3659 04:47:52.580659 11, 0xFFFF, sum = 0
3660 04:47:52.580740 12, 0x0, sum = 1
3661 04:47:52.580797 13, 0x0, sum = 2
3662 04:47:52.580852 14, 0x0, sum = 3
3663 04:47:52.580908 15, 0x0, sum = 4
3664 04:47:52.580966 best_step = 13
3665 04:47:52.581023
3666 04:47:52.581078 ==
3667 04:47:52.581132 Dram Type= 6, Freq= 0, CH_1, rank 1
3668 04:47:52.581186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3669 04:47:52.581241 ==
3670 04:47:52.581295 RX Vref Scan: 0
3671 04:47:52.581349
3672 04:47:52.581402 RX Vref 0 -> 0, step: 1
3673 04:47:52.581456
3674 04:47:52.581508 RX Delay -5 -> 252, step: 4
3675 04:47:52.581562 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3676 04:47:52.581617 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3677 04:47:52.581671 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3678 04:47:52.581725 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3679 04:47:52.581784 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3680 04:47:52.581846 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3681 04:47:52.581901 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3682 04:47:52.581956 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3683 04:47:52.582212 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3684 04:47:52.582295 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3685 04:47:52.582401 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3686 04:47:52.582508 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3687 04:47:52.582599 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3688 04:47:52.582704 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3689 04:47:52.582801 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3690 04:47:52.582865 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3691 04:47:52.582942 ==
3692 04:47:52.583003 Dram Type= 6, Freq= 0, CH_1, rank 1
3693 04:47:52.583065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3694 04:47:52.583134 ==
3695 04:47:52.583226 DQS Delay:
3696 04:47:52.583314 DQS0 = 0, DQS1 = 0
3697 04:47:52.583397 DQM Delay:
3698 04:47:52.583487 DQM0 = 120, DQM1 = 118
3699 04:47:52.583574 DQ Delay:
3700 04:47:52.583642 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3701 04:47:52.583702 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3702 04:47:52.583773 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3703 04:47:52.583864 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3704 04:47:52.583950
3705 04:47:52.584036
3706 04:47:52.584126 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3707 04:47:52.584218 CH1 RK1: MR19=403, MR18=11ED
3708 04:47:52.584331 CH1_RK1: MR19=0x403, MR18=0x11ED, DQSOSC=403, MR23=63, INC=40, DEC=26
3709 04:47:52.584400 [RxdqsGatingPostProcess] freq 1200
3710 04:47:52.584486 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3711 04:47:52.584558 best DQS0 dly(2T, 0.5T) = (0, 11)
3712 04:47:52.584629 best DQS1 dly(2T, 0.5T) = (0, 11)
3713 04:47:52.584719 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3714 04:47:52.584785 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3715 04:47:52.584840 best DQS0 dly(2T, 0.5T) = (0, 11)
3716 04:47:52.584895 best DQS1 dly(2T, 0.5T) = (0, 11)
3717 04:47:52.584982 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3718 04:47:52.585075 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3719 04:47:52.585161 Pre-setting of DQS Precalculation
3720 04:47:52.585247 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3721 04:47:52.585341 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3722 04:47:52.585436 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3723 04:47:52.585527
3724 04:47:52.585616
3725 04:47:52.585699 [Calibration Summary] 2400 Mbps
3726 04:47:52.585785 CH 0, Rank 0
3727 04:47:52.585869 SW Impedance : PASS
3728 04:47:52.585952 DUTY Scan : NO K
3729 04:47:52.586038 ZQ Calibration : PASS
3730 04:47:52.586123 Jitter Meter : NO K
3731 04:47:52.586207 CBT Training : PASS
3732 04:47:52.586290 Write leveling : PASS
3733 04:47:52.586373 RX DQS gating : PASS
3734 04:47:52.586458 RX DQ/DQS(RDDQC) : PASS
3735 04:47:52.586543 TX DQ/DQS : PASS
3736 04:47:52.586627 RX DATLAT : PASS
3737 04:47:52.586709 RX DQ/DQS(Engine): PASS
3738 04:47:52.586793 TX OE : NO K
3739 04:47:52.586880 All Pass.
3740 04:47:52.586967
3741 04:47:52.587050 CH 0, Rank 1
3742 04:47:52.587133 SW Impedance : PASS
3743 04:47:52.587216 DUTY Scan : NO K
3744 04:47:52.587299 ZQ Calibration : PASS
3745 04:47:52.587386 Jitter Meter : NO K
3746 04:47:52.587473 CBT Training : PASS
3747 04:47:52.587562 Write leveling : PASS
3748 04:47:52.587646 RX DQS gating : PASS
3749 04:47:52.587729 RX DQ/DQS(RDDQC) : PASS
3750 04:47:52.587812 TX DQ/DQS : PASS
3751 04:47:52.587896 RX DATLAT : PASS
3752 04:47:52.587980 RX DQ/DQS(Engine): PASS
3753 04:47:52.588065 TX OE : NO K
3754 04:47:52.588148 All Pass.
3755 04:47:52.588231
3756 04:47:52.588321 CH 1, Rank 0
3757 04:47:52.588405 SW Impedance : PASS
3758 04:47:52.588488 DUTY Scan : NO K
3759 04:47:52.588571 ZQ Calibration : PASS
3760 04:47:52.588656 Jitter Meter : NO K
3761 04:47:52.588733 CBT Training : PASS
3762 04:47:52.588824 Write leveling : PASS
3763 04:47:52.588920 RX DQS gating : PASS
3764 04:47:52.589007 RX DQ/DQS(RDDQC) : PASS
3765 04:47:52.589091 TX DQ/DQS : PASS
3766 04:47:52.589174 RX DATLAT : PASS
3767 04:47:52.589257 RX DQ/DQS(Engine): PASS
3768 04:47:52.589340 TX OE : NO K
3769 04:47:52.589426 All Pass.
3770 04:47:52.589511
3771 04:47:52.589593 CH 1, Rank 1
3772 04:47:52.589681 SW Impedance : PASS
3773 04:47:52.589766 DUTY Scan : NO K
3774 04:47:52.589849 ZQ Calibration : PASS
3775 04:47:52.589934 Jitter Meter : NO K
3776 04:47:52.589994 CBT Training : PASS
3777 04:47:52.590050 Write leveling : PASS
3778 04:47:52.590107 RX DQS gating : PASS
3779 04:47:52.590162 RX DQ/DQS(RDDQC) : PASS
3780 04:47:52.590215 TX DQ/DQS : PASS
3781 04:47:52.590270 RX DATLAT : PASS
3782 04:47:52.590323 RX DQ/DQS(Engine): PASS
3783 04:47:52.590381 TX OE : NO K
3784 04:47:52.590438 All Pass.
3785 04:47:52.590493
3786 04:47:52.590546 DramC Write-DBI off
3787 04:47:52.590600 PER_BANK_REFRESH: Hybrid Mode
3788 04:47:52.590655 TX_TRACKING: ON
3789 04:47:52.590709 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3790 04:47:52.590765 [FAST_K] Save calibration result to emmc
3791 04:47:52.590825 dramc_set_vcore_voltage set vcore to 650000
3792 04:47:52.590879 Read voltage for 600, 5
3793 04:47:52.590937 Vio18 = 0
3794 04:47:52.590994 Vcore = 650000
3795 04:47:52.591048 Vdram = 0
3796 04:47:52.591102 Vddq = 0
3797 04:47:52.591161 Vmddr = 0
3798 04:47:52.591248 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3799 04:47:52.591333 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3800 04:47:52.591421 MEM_TYPE=3, freq_sel=19
3801 04:47:52.591505 sv_algorithm_assistance_LP4_1600
3802 04:47:52.591588 ============ PULL DRAM RESETB DOWN ============
3803 04:47:52.591672 ========== PULL DRAM RESETB DOWN end =========
3804 04:47:52.591758 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3805 04:47:52.591842 ===================================
3806 04:47:52.591925 LPDDR4 DRAM CONFIGURATION
3807 04:47:52.592008 ===================================
3808 04:47:52.592091 EX_ROW_EN[0] = 0x0
3809 04:47:52.592176 EX_ROW_EN[1] = 0x0
3810 04:47:52.592261 LP4Y_EN = 0x0
3811 04:47:52.592352 WORK_FSP = 0x0
3812 04:47:52.592436 WL = 0x2
3813 04:47:52.592518 RL = 0x2
3814 04:47:52.592601 BL = 0x2
3815 04:47:52.592686 RPST = 0x0
3816 04:47:52.592770 RD_PRE = 0x0
3817 04:47:52.592853 WR_PRE = 0x1
3818 04:47:52.592935 WR_PST = 0x0
3819 04:47:52.593017 DBI_WR = 0x0
3820 04:47:52.593099 DBI_RD = 0x0
3821 04:47:52.593185 OTF = 0x1
3822 04:47:52.593270 ===================================
3823 04:47:52.593353 ===================================
3824 04:47:52.593436 ANA top config
3825 04:47:52.593519 ===================================
3826 04:47:52.593811 DLL_ASYNC_EN = 0
3827 04:47:52.593921 ALL_SLAVE_EN = 1
3828 04:47:52.594029 NEW_RANK_MODE = 1
3829 04:47:52.594135 DLL_IDLE_MODE = 1
3830 04:47:52.594223 LP45_APHY_COMB_EN = 1
3831 04:47:52.594280 TX_ODT_DIS = 1
3832 04:47:52.594336 NEW_8X_MODE = 1
3833 04:47:52.594391 ===================================
3834 04:47:52.594446 ===================================
3835 04:47:52.594500 data_rate = 1200
3836 04:47:52.594562 CKR = 1
3837 04:47:52.594647 DQ_P2S_RATIO = 8
3838 04:47:52.594731 ===================================
3839 04:47:52.594815 CA_P2S_RATIO = 8
3840 04:47:52.594898 DQ_CA_OPEN = 0
3841 04:47:52.594980 DQ_SEMI_OPEN = 0
3842 04:47:52.595068 CA_SEMI_OPEN = 0
3843 04:47:52.595152 CA_FULL_RATE = 0
3844 04:47:52.595238 DQ_CKDIV4_EN = 1
3845 04:47:52.595324 CA_CKDIV4_EN = 1
3846 04:47:52.595408 CA_PREDIV_EN = 0
3847 04:47:52.595491 PH8_DLY = 0
3848 04:47:52.595574 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3849 04:47:52.595657 DQ_AAMCK_DIV = 4
3850 04:47:52.595739 CA_AAMCK_DIV = 4
3851 04:47:52.595795 CA_ADMCK_DIV = 4
3852 04:47:52.595849 DQ_TRACK_CA_EN = 0
3853 04:47:52.595903 CA_PICK = 600
3854 04:47:52.595957 CA_MCKIO = 600
3855 04:47:52.596011 MCKIO_SEMI = 0
3856 04:47:52.596065 PLL_FREQ = 2288
3857 04:47:52.596119 DQ_UI_PI_RATIO = 32
3858 04:47:52.596203 CA_UI_PI_RATIO = 0
3859 04:47:52.596296 ===================================
3860 04:47:52.596382 ===================================
3861 04:47:52.596466 memory_type:LPDDR4
3862 04:47:52.596548 GP_NUM : 10
3863 04:47:52.596634 SRAM_EN : 1
3864 04:47:52.596722 MD32_EN : 0
3865 04:47:52.596811 ===================================
3866 04:47:52.596895 [ANA_INIT] >>>>>>>>>>>>>>
3867 04:47:52.596978 <<<<<< [CONFIGURE PHASE]: ANA_TX
3868 04:47:52.597066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3869 04:47:52.597152 ===================================
3870 04:47:52.597238 data_rate = 1200,PCW = 0X5800
3871 04:47:52.597322 ===================================
3872 04:47:52.597405 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3873 04:47:52.597490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3874 04:47:52.597574 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3875 04:47:52.597643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3876 04:47:52.597701 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3877 04:47:52.597756 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3878 04:47:52.597810 [ANA_INIT] flow start
3879 04:47:52.597864 [ANA_INIT] PLL >>>>>>>>
3880 04:47:52.597918 [ANA_INIT] PLL <<<<<<<<
3881 04:47:52.597972 [ANA_INIT] MIDPI >>>>>>>>
3882 04:47:52.598027 [ANA_INIT] MIDPI <<<<<<<<
3883 04:47:52.598081 [ANA_INIT] DLL >>>>>>>>
3884 04:47:52.598140 [ANA_INIT] flow end
3885 04:47:52.598195 ============ LP4 DIFF to SE enter ============
3886 04:47:52.598249 ============ LP4 DIFF to SE exit ============
3887 04:47:52.598304 [ANA_INIT] <<<<<<<<<<<<<
3888 04:47:52.598357 [Flow] Enable top DCM control >>>>>
3889 04:47:52.598434 [Flow] Enable top DCM control <<<<<
3890 04:47:52.598520 Enable DLL master slave shuffle
3891 04:47:52.598585 ==============================================================
3892 04:47:52.598641 Gating Mode config
3893 04:47:52.598694 ==============================================================
3894 04:47:52.598748 Config description:
3895 04:47:52.598802 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3896 04:47:52.598857 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3897 04:47:52.598913 SELPH_MODE 0: By rank 1: By Phase
3898 04:47:52.598967 ==============================================================
3899 04:47:52.599027 GAT_TRACK_EN = 1
3900 04:47:52.599085 RX_GATING_MODE = 2
3901 04:47:52.599139 RX_GATING_TRACK_MODE = 2
3902 04:47:52.599193 SELPH_MODE = 1
3903 04:47:52.599247 PICG_EARLY_EN = 1
3904 04:47:52.599301 VALID_LAT_VALUE = 1
3905 04:47:52.599354 ==============================================================
3906 04:47:52.599408 Enter into Gating configuration >>>>
3907 04:47:52.599465 Exit from Gating configuration <<<<
3908 04:47:52.599523 Enter into DVFS_PRE_config >>>>>
3909 04:47:52.599578 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3910 04:47:52.599633 Exit from DVFS_PRE_config <<<<<
3911 04:47:52.599688 Enter into PICG configuration >>>>
3912 04:47:52.599742 Exit from PICG configuration <<<<
3913 04:47:52.599795 [RX_INPUT] configuration >>>>>
3914 04:47:52.599852 [RX_INPUT] configuration <<<<<
3915 04:47:52.599906 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3916 04:47:52.599965 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3917 04:47:52.600023 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3918 04:47:52.600079 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3919 04:47:53.610725 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3920 04:47:53.610867 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3921 04:47:53.610940 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3922 04:47:53.611006 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3923 04:47:53.611065 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3924 04:47:53.611123 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3925 04:47:53.611184 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3926 04:47:53.611243 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3927 04:47:53.611510 ===================================
3928 04:47:53.611579 LPDDR4 DRAM CONFIGURATION
3929 04:47:53.611637 ===================================
3930 04:47:53.611708 EX_ROW_EN[0] = 0x0
3931 04:47:53.611779 EX_ROW_EN[1] = 0x0
3932 04:47:53.611834 LP4Y_EN = 0x0
3933 04:47:53.611887 WORK_FSP = 0x0
3934 04:47:53.611940 WL = 0x2
3935 04:47:53.612022 RL = 0x2
3936 04:47:53.612078 BL = 0x2
3937 04:47:53.612145 RPST = 0x0
3938 04:47:53.612227 RD_PRE = 0x0
3939 04:47:53.612340 WR_PRE = 0x1
3940 04:47:53.612396 WR_PST = 0x0
3941 04:47:53.612449 DBI_WR = 0x0
3942 04:47:53.612503 DBI_RD = 0x0
3943 04:47:53.612556 OTF = 0x1
3944 04:47:53.612610 ===================================
3945 04:47:53.612663 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3946 04:47:53.612716 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3947 04:47:53.612771 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3948 04:47:53.612824 ===================================
3949 04:47:53.612878 LPDDR4 DRAM CONFIGURATION
3950 04:47:53.612931 ===================================
3951 04:47:53.612984 EX_ROW_EN[0] = 0x10
3952 04:47:53.613038 EX_ROW_EN[1] = 0x0
3953 04:47:53.613091 LP4Y_EN = 0x0
3954 04:47:53.613144 WORK_FSP = 0x0
3955 04:47:53.613196 WL = 0x2
3956 04:47:53.613249 RL = 0x2
3957 04:47:53.613302 BL = 0x2
3958 04:47:53.613354 RPST = 0x0
3959 04:47:53.613407 RD_PRE = 0x0
3960 04:47:53.613459 WR_PRE = 0x1
3961 04:47:53.613512 WR_PST = 0x0
3962 04:47:53.613564 DBI_WR = 0x0
3963 04:47:53.613617 DBI_RD = 0x0
3964 04:47:53.613670 OTF = 0x1
3965 04:47:53.613723 ===================================
3966 04:47:53.613776 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3967 04:47:53.613830 nWR fixed to 30
3968 04:47:53.613883 [ModeRegInit_LP4] CH0 RK0
3969 04:47:53.613936 [ModeRegInit_LP4] CH0 RK1
3970 04:47:53.613989 [ModeRegInit_LP4] CH1 RK0
3971 04:47:53.614042 [ModeRegInit_LP4] CH1 RK1
3972 04:47:53.614094 match AC timing 17
3973 04:47:53.614146 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3974 04:47:53.614200 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3975 04:47:53.614252 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3976 04:47:53.614305 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3977 04:47:53.614358 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3978 04:47:53.614411 ==
3979 04:47:53.614464 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 04:47:53.614516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 04:47:53.614570 ==
3982 04:47:53.614623 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3983 04:47:53.614676 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3984 04:47:53.614728 [CA 0] Center 35 (5~66) winsize 62
3985 04:47:53.614781 [CA 1] Center 35 (5~66) winsize 62
3986 04:47:53.614834 [CA 2] Center 34 (3~65) winsize 63
3987 04:47:53.614886 [CA 3] Center 33 (3~64) winsize 62
3988 04:47:53.614939 [CA 4] Center 33 (2~64) winsize 63
3989 04:47:53.614992 [CA 5] Center 32 (2~63) winsize 62
3990 04:47:53.615044
3991 04:47:53.615096 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3992 04:47:53.615149
3993 04:47:53.615201 [CATrainingPosCal] consider 1 rank data
3994 04:47:53.615254 u2DelayCellTimex100 = 270/100 ps
3995 04:47:53.615306 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3996 04:47:53.615359 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3997 04:47:53.615412 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3998 04:47:53.615465 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3999 04:47:53.615518 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4000 04:47:53.615571 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4001 04:47:53.615623
4002 04:47:53.615676 CA PerBit enable=1, Macro0, CA PI delay=32
4003 04:47:53.615728
4004 04:47:53.615780 [CBTSetCACLKResult] CA Dly = 32
4005 04:47:53.615833 CS Dly: 4 (0~35)
4006 04:47:53.615885 ==
4007 04:47:53.615941 Dram Type= 6, Freq= 0, CH_0, rank 1
4008 04:47:53.615994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 04:47:53.616047 ==
4010 04:47:53.616134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4011 04:47:53.616218 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4012 04:47:53.616325 [CA 0] Center 36 (5~67) winsize 63
4013 04:47:53.616423 [CA 1] Center 36 (5~67) winsize 63
4014 04:47:53.616504 [CA 2] Center 34 (3~65) winsize 63
4015 04:47:53.616592 [CA 3] Center 34 (3~65) winsize 63
4016 04:47:53.616649 [CA 4] Center 33 (2~64) winsize 63
4017 04:47:53.616703 [CA 5] Center 32 (2~63) winsize 62
4018 04:47:53.616756
4019 04:47:53.616809 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4020 04:47:53.616862
4021 04:47:53.616915 [CATrainingPosCal] consider 2 rank data
4022 04:47:53.616968 u2DelayCellTimex100 = 270/100 ps
4023 04:47:53.617021 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4024 04:47:53.617074 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4025 04:47:53.617126 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4026 04:47:53.617179 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4027 04:47:53.617232 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4028 04:47:53.617284 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4029 04:47:53.617337
4030 04:47:53.617389 CA PerBit enable=1, Macro0, CA PI delay=32
4031 04:47:53.617442
4032 04:47:53.617495 [CBTSetCACLKResult] CA Dly = 32
4033 04:47:53.617547 CS Dly: 4 (0~36)
4034 04:47:53.617600
4035 04:47:53.617652 ----->DramcWriteLeveling(PI) begin...
4036 04:47:53.617706 ==
4037 04:47:53.617759 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 04:47:53.617812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 04:47:53.617865 ==
4040 04:47:53.617917 Write leveling (Byte 0): 35 => 35
4041 04:47:53.617970 Write leveling (Byte 1): 32 => 32
4042 04:47:53.618022 DramcWriteLeveling(PI) end<-----
4043 04:47:53.618074
4044 04:47:53.618127 ==
4045 04:47:53.618179 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 04:47:53.618231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 04:47:53.618284 ==
4048 04:47:53.618336 [Gating] SW mode calibration
4049 04:47:53.618389 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4050 04:47:53.618442 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4051 04:47:53.618495 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 04:47:53.618548 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4053 04:47:53.618600 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4054 04:47:53.618653 0 9 12 | B1->B0 | 3434 3030 | 0 1 | (0 0) (0 0)
4055 04:47:53.618704 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
4056 04:47:53.618955 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4057 04:47:53.619016 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 04:47:53.619085 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 04:47:53.619152 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 04:47:53.619205 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 04:47:53.619258 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 04:47:53.619311 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4063 04:47:53.619395 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4064 04:47:53.619448 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 04:47:53.619501 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 04:47:53.619554 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 04:47:53.619606 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 04:47:53.619660 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 04:47:53.619713 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 04:47:53.619766 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 04:47:53.619818 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4072 04:47:53.619871 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 04:47:53.619946 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 04:47:53.620013 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 04:47:53.620065 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 04:47:53.620123 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 04:47:53.620231 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 04:47:53.620332 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 04:47:53.620388 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 04:47:53.620442 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 04:47:53.620495 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 04:47:53.620548 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 04:47:53.620601 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 04:47:53.620654 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 04:47:53.620707 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 04:47:53.620759 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4087 04:47:53.620813 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4088 04:47:53.620866 Total UI for P1: 0, mck2ui 16
4089 04:47:53.620920 best dqsien dly found for B0: ( 0, 13, 12)
4090 04:47:53.620973 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4091 04:47:53.621026 Total UI for P1: 0, mck2ui 16
4092 04:47:53.621079 best dqsien dly found for B1: ( 0, 13, 16)
4093 04:47:53.621132 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4094 04:47:53.621184 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4095 04:47:53.621236
4096 04:47:53.621288 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4097 04:47:53.621342 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4098 04:47:53.621394 [Gating] SW calibration Done
4099 04:47:53.621447 ==
4100 04:47:53.621500 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 04:47:53.621553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 04:47:53.621606 ==
4103 04:47:53.621658 RX Vref Scan: 0
4104 04:47:53.621711
4105 04:47:53.621764 RX Vref 0 -> 0, step: 1
4106 04:47:53.621816
4107 04:47:53.621869 RX Delay -230 -> 252, step: 16
4108 04:47:53.621922 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4109 04:47:53.621975 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4110 04:47:53.622028 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4111 04:47:53.622081 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4112 04:47:53.622134 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4113 04:47:53.622187 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4114 04:47:53.622240 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4115 04:47:53.622293 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4116 04:47:53.622346 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4117 04:47:53.622399 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4118 04:47:53.622451 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4119 04:47:53.622504 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4120 04:47:53.622556 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4121 04:47:53.622608 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4122 04:47:53.622661 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4123 04:47:53.622714 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4124 04:47:53.622766 ==
4125 04:47:53.622819 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 04:47:53.622875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 04:47:53.622935 ==
4128 04:47:53.622993 DQS Delay:
4129 04:47:53.623046 DQS0 = 0, DQS1 = 0
4130 04:47:53.623100 DQM Delay:
4131 04:47:53.623152 DQM0 = 49, DQM1 = 45
4132 04:47:53.623210 DQ Delay:
4133 04:47:53.623264 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4134 04:47:53.623317 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4135 04:47:53.623370 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4136 04:47:53.623433 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4137 04:47:53.623487
4138 04:47:53.623539
4139 04:47:53.623597 ==
4140 04:47:53.623650 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 04:47:53.623703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 04:47:53.623777 ==
4143 04:47:53.623845
4144 04:47:53.623898
4145 04:47:53.623950 TX Vref Scan disable
4146 04:47:53.624003 == TX Byte 0 ==
4147 04:47:53.624055 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4148 04:47:53.624108 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4149 04:47:53.624215 == TX Byte 1 ==
4150 04:47:53.624303 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4151 04:47:53.624373 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4152 04:47:53.624427 ==
4153 04:47:53.624480 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 04:47:53.624533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 04:47:53.624587 ==
4156 04:47:53.624639
4157 04:47:53.624691
4158 04:47:53.624743 TX Vref Scan disable
4159 04:47:53.624796 == TX Byte 0 ==
4160 04:47:53.624850 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4161 04:47:53.624903 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4162 04:47:53.624956 == TX Byte 1 ==
4163 04:47:53.625008 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4164 04:47:53.625061 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4165 04:47:53.625113
4166 04:47:53.625165 [DATLAT]
4167 04:47:53.625218 Freq=600, CH0 RK0
4168 04:47:53.625271
4169 04:47:53.625323 DATLAT Default: 0x9
4170 04:47:53.625375 0, 0xFFFF, sum = 0
4171 04:47:53.625429 1, 0xFFFF, sum = 0
4172 04:47:53.625483 2, 0xFFFF, sum = 0
4173 04:47:53.625536 3, 0xFFFF, sum = 0
4174 04:47:53.625782 4, 0xFFFF, sum = 0
4175 04:47:53.625842 5, 0xFFFF, sum = 0
4176 04:47:53.625897 6, 0xFFFF, sum = 0
4177 04:47:53.625951 7, 0xFFFF, sum = 0
4178 04:47:53.626005 8, 0x0, sum = 1
4179 04:47:53.626059 9, 0x0, sum = 2
4180 04:47:53.626117 10, 0x0, sum = 3
4181 04:47:53.626172 11, 0x0, sum = 4
4182 04:47:53.626226 best_step = 9
4183 04:47:53.626278
4184 04:47:53.626330 ==
4185 04:47:53.626382 Dram Type= 6, Freq= 0, CH_0, rank 0
4186 04:47:53.626435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 04:47:53.626488 ==
4188 04:47:53.626541 RX Vref Scan: 1
4189 04:47:53.626594
4190 04:47:53.626646 RX Vref 0 -> 0, step: 1
4191 04:47:53.626698
4192 04:47:53.626750 RX Delay -163 -> 252, step: 8
4193 04:47:53.626803
4194 04:47:53.626856 Set Vref, RX VrefLevel [Byte0]: 57
4195 04:47:53.626909 [Byte1]: 48
4196 04:47:53.626961
4197 04:47:53.627014 Final RX Vref Byte 0 = 57 to rank0
4198 04:47:53.627067 Final RX Vref Byte 1 = 48 to rank0
4199 04:47:53.627120 Final RX Vref Byte 0 = 57 to rank1
4200 04:47:53.627173 Final RX Vref Byte 1 = 48 to rank1==
4201 04:47:53.627226 Dram Type= 6, Freq= 0, CH_0, rank 0
4202 04:47:53.627279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 04:47:53.627332 ==
4204 04:47:53.627400 DQS Delay:
4205 04:47:53.627466 DQS0 = 0, DQS1 = 0
4206 04:47:53.627519 DQM Delay:
4207 04:47:53.627571 DQM0 = 53, DQM1 = 47
4208 04:47:53.627624 DQ Delay:
4209 04:47:53.627676 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4210 04:47:53.627729 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4211 04:47:53.627782 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4212 04:47:53.627834 DQ12 =56, DQ13 =48, DQ14 =60, DQ15 =52
4213 04:47:53.627886
4214 04:47:53.627938
4215 04:47:53.627989 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4216 04:47:53.628043 CH0 RK0: MR19=808, MR18=6C5F
4217 04:47:53.628097 CH0_RK0: MR19=0x808, MR18=0x6C5F, DQSOSC=389, MR23=63, INC=173, DEC=115
4218 04:47:53.628150
4219 04:47:53.628202 ----->DramcWriteLeveling(PI) begin...
4220 04:47:53.628255 ==
4221 04:47:53.628319 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 04:47:53.628372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 04:47:53.628426 ==
4224 04:47:53.628478 Write leveling (Byte 0): 34 => 34
4225 04:47:53.628530 Write leveling (Byte 1): 30 => 30
4226 04:47:53.628582 DramcWriteLeveling(PI) end<-----
4227 04:47:53.628635
4228 04:47:53.628687 ==
4229 04:47:53.628740 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 04:47:53.628793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 04:47:53.628845 ==
4232 04:47:53.628897 [Gating] SW mode calibration
4233 04:47:53.628950 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4234 04:47:53.629004 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4235 04:47:53.629058 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4236 04:47:53.629111 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4237 04:47:53.629164 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4238 04:47:53.629217 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4239 04:47:53.629270 0 9 16 | B1->B0 | 2929 2626 | 0 0 | (0 0) (0 0)
4240 04:47:53.629323 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 04:47:53.629375 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 04:47:53.629427 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 04:47:53.629480 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 04:47:53.629532 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 04:47:53.629584 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 04:47:53.629642 0 10 12 | B1->B0 | 2727 2e2e | 0 1 | (1 1) (0 0)
4247 04:47:53.629701 0 10 16 | B1->B0 | 4343 3e3e | 0 0 | (0 0) (0 0)
4248 04:47:53.629759 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 04:47:53.629814 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 04:47:53.629867 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 04:47:53.629919 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 04:47:53.629982 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 04:47:53.630037 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 04:47:53.630091 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4255 04:47:53.630146 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 04:47:53.630200 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 04:47:53.630253 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 04:47:53.630306 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 04:47:53.630375 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 04:47:53.630457 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 04:47:53.630540 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 04:47:53.630623 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 04:47:53.630734 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 04:47:53.630842 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 04:47:53.630916 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 04:47:53.630973 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 04:47:53.631027 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 04:47:53.631081 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 04:47:53.631134 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 04:47:53.631187 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4271 04:47:53.631240 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4272 04:47:53.631292 Total UI for P1: 0, mck2ui 16
4273 04:47:53.631345 best dqsien dly found for B1: ( 0, 13, 14)
4274 04:47:53.631398 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 04:47:53.631451 Total UI for P1: 0, mck2ui 16
4276 04:47:53.631503 best dqsien dly found for B0: ( 0, 13, 14)
4277 04:47:53.631556 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4278 04:47:53.631609 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4279 04:47:53.631662
4280 04:47:53.631714 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4281 04:47:53.631768 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4282 04:47:53.631821 [Gating] SW calibration Done
4283 04:47:53.631873 ==
4284 04:47:53.631926 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 04:47:53.631979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 04:47:53.632031 ==
4287 04:47:53.632084 RX Vref Scan: 0
4288 04:47:53.632174
4289 04:47:53.632258 RX Vref 0 -> 0, step: 1
4290 04:47:53.632346
4291 04:47:53.632400 RX Delay -230 -> 252, step: 16
4292 04:47:53.632453 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4293 04:47:53.632708 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4294 04:47:53.632769 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4295 04:47:53.632824 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4296 04:47:53.632877 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4297 04:47:53.632931 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4298 04:47:53.632984 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4299 04:47:53.633036 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4300 04:47:53.633089 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4301 04:47:53.633143 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4302 04:47:53.633195 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4303 04:47:53.633249 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4304 04:47:53.633302 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4305 04:47:53.633355 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4306 04:47:53.633408 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4307 04:47:53.633460 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4308 04:47:53.633512 ==
4309 04:47:53.633565 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 04:47:53.633618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 04:47:53.633671 ==
4312 04:47:53.633723 DQS Delay:
4313 04:47:53.633776 DQS0 = 0, DQS1 = 0
4314 04:47:53.633828 DQM Delay:
4315 04:47:53.633881 DQM0 = 52, DQM1 = 44
4316 04:47:53.633936 DQ Delay:
4317 04:47:53.633989 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4318 04:47:53.634042 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4319 04:47:53.634095 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4320 04:47:53.634148 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4321 04:47:53.634201
4322 04:47:53.634253
4323 04:47:53.634306 ==
4324 04:47:53.634358 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 04:47:53.634411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 04:47:53.634464 ==
4327 04:47:53.634517
4328 04:47:53.634569
4329 04:47:53.634620 TX Vref Scan disable
4330 04:47:53.634686 == TX Byte 0 ==
4331 04:47:53.634741 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4332 04:47:53.634795 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4333 04:47:53.634848 == TX Byte 1 ==
4334 04:47:53.634901 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4335 04:47:53.634953 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4336 04:47:53.635006 ==
4337 04:47:53.635058 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 04:47:53.635111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 04:47:53.635165 ==
4340 04:47:53.635217
4341 04:47:53.635270
4342 04:47:53.635322 TX Vref Scan disable
4343 04:47:53.635375 == TX Byte 0 ==
4344 04:47:53.635455 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4345 04:47:53.635508 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4346 04:47:53.635560 == TX Byte 1 ==
4347 04:47:53.635613 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4348 04:47:53.635666 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4349 04:47:53.635719
4350 04:47:53.635771 [DATLAT]
4351 04:47:53.635822 Freq=600, CH0 RK1
4352 04:47:53.635875
4353 04:47:53.635927 DATLAT Default: 0x9
4354 04:47:53.635980 0, 0xFFFF, sum = 0
4355 04:47:53.636034 1, 0xFFFF, sum = 0
4356 04:47:53.636087 2, 0xFFFF, sum = 0
4357 04:47:53.636190 3, 0xFFFF, sum = 0
4358 04:47:53.636307 4, 0xFFFF, sum = 0
4359 04:47:53.636380 5, 0xFFFF, sum = 0
4360 04:47:53.636435 6, 0xFFFF, sum = 0
4361 04:47:53.636489 7, 0xFFFF, sum = 0
4362 04:47:53.636544 8, 0x0, sum = 1
4363 04:47:53.636597 9, 0x0, sum = 2
4364 04:47:53.636651 10, 0x0, sum = 3
4365 04:47:53.636705 11, 0x0, sum = 4
4366 04:47:53.636759 best_step = 9
4367 04:47:53.636812
4368 04:47:53.636864 ==
4369 04:47:53.636916 Dram Type= 6, Freq= 0, CH_0, rank 1
4370 04:47:53.636970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 04:47:53.637023 ==
4372 04:47:53.637076 RX Vref Scan: 0
4373 04:47:53.637128
4374 04:47:53.637180 RX Vref 0 -> 0, step: 1
4375 04:47:53.637232
4376 04:47:53.637322 RX Delay -163 -> 252, step: 8
4377 04:47:53.637375 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4378 04:47:53.637428 iDelay=205, Bit 1, Center 52 (-91 ~ 196) 288
4379 04:47:53.637481 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4380 04:47:53.637534 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4381 04:47:53.637587 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4382 04:47:53.637640 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4383 04:47:53.637692 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4384 04:47:53.637745 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4385 04:47:53.637797 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4386 04:47:53.637850 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4387 04:47:53.637903 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4388 04:47:53.637955 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4389 04:47:53.638012 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4390 04:47:53.638064 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4391 04:47:53.638117 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4392 04:47:53.638169 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4393 04:47:53.638222 ==
4394 04:47:53.638274 Dram Type= 6, Freq= 0, CH_0, rank 1
4395 04:47:53.638327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 04:47:53.638381 ==
4397 04:47:53.638433 DQS Delay:
4398 04:47:53.638485 DQS0 = 0, DQS1 = 0
4399 04:47:53.638538 DQM Delay:
4400 04:47:53.638592 DQM0 = 52, DQM1 = 46
4401 04:47:53.638645 DQ Delay:
4402 04:47:53.638698 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4403 04:47:53.638751 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =60
4404 04:47:53.638804 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4405 04:47:53.638856 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4406 04:47:53.638908
4407 04:47:53.638960
4408 04:47:53.639012 [DQSOSCAuto] RK1, (LSB)MR18= 0x6021, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4409 04:47:53.639066 CH0 RK1: MR19=808, MR18=6021
4410 04:47:53.639119 CH0_RK1: MR19=0x808, MR18=0x6021, DQSOSC=391, MR23=63, INC=171, DEC=114
4411 04:47:53.639172 [RxdqsGatingPostProcess] freq 600
4412 04:47:53.639225 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4413 04:47:53.639278 Pre-setting of DQS Precalculation
4414 04:47:53.639330 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4415 04:47:53.639383 ==
4416 04:47:53.639435 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 04:47:53.639488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 04:47:53.639542 ==
4419 04:47:53.639594 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4420 04:47:53.639647 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4421 04:47:53.639701 [CA 0] Center 35 (5~66) winsize 62
4422 04:47:53.639754 [CA 1] Center 36 (5~67) winsize 63
4423 04:47:53.639807 [CA 2] Center 34 (4~65) winsize 62
4424 04:47:53.639859 [CA 3] Center 34 (4~65) winsize 62
4425 04:47:53.639912 [CA 4] Center 34 (4~65) winsize 62
4426 04:47:53.640183 [CA 5] Center 33 (3~64) winsize 62
4427 04:47:53.640272
4428 04:47:53.640376 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4429 04:47:53.640431
4430 04:47:53.640485 [CATrainingPosCal] consider 1 rank data
4431 04:47:53.640542 u2DelayCellTimex100 = 270/100 ps
4432 04:47:53.640596 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4433 04:47:53.640649 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4434 04:47:53.640704 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4435 04:47:53.640757 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4436 04:47:53.640810 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4437 04:47:53.640863 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4438 04:47:53.640924
4439 04:47:53.640977 CA PerBit enable=1, Macro0, CA PI delay=33
4440 04:47:53.641030
4441 04:47:53.641090 [CBTSetCACLKResult] CA Dly = 33
4442 04:47:53.641146 CS Dly: 5 (0~36)
4443 04:47:53.641199 ==
4444 04:47:53.641252 Dram Type= 6, Freq= 0, CH_1, rank 1
4445 04:47:53.641309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 04:47:53.641363 ==
4447 04:47:53.641416 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4448 04:47:53.641472 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4449 04:47:53.641526 [CA 0] Center 36 (5~67) winsize 63
4450 04:47:53.641580 [CA 1] Center 36 (5~67) winsize 63
4451 04:47:53.641632 [CA 2] Center 34 (4~65) winsize 62
4452 04:47:53.641685 [CA 3] Center 34 (4~65) winsize 62
4453 04:47:53.641738 [CA 4] Center 34 (4~65) winsize 62
4454 04:47:53.641791 [CA 5] Center 34 (3~65) winsize 63
4455 04:47:53.641843
4456 04:47:53.641895 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4457 04:47:53.641949
4458 04:47:53.642001 [CATrainingPosCal] consider 2 rank data
4459 04:47:53.642060 u2DelayCellTimex100 = 270/100 ps
4460 04:47:53.642113 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4461 04:47:53.642203 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4462 04:47:53.642255 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4463 04:47:53.642308 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4464 04:47:53.642360 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4465 04:47:53.642413 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4466 04:47:53.642466
4467 04:47:53.642519 CA PerBit enable=1, Macro0, CA PI delay=33
4468 04:47:53.642571
4469 04:47:53.642623 [CBTSetCACLKResult] CA Dly = 33
4470 04:47:53.642676 CS Dly: 6 (0~38)
4471 04:47:53.642729
4472 04:47:53.642781 ----->DramcWriteLeveling(PI) begin...
4473 04:47:53.642838 ==
4474 04:47:53.642893 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 04:47:53.642947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 04:47:53.643000 ==
4477 04:47:53.643052 Write leveling (Byte 0): 30 => 30
4478 04:47:53.643105 Write leveling (Byte 1): 29 => 29
4479 04:47:53.643157 DramcWriteLeveling(PI) end<-----
4480 04:47:53.643210
4481 04:47:53.643262 ==
4482 04:47:53.643331 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 04:47:53.643397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 04:47:53.643450 ==
4485 04:47:53.643502 [Gating] SW mode calibration
4486 04:47:53.643555 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4487 04:47:53.643609 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4488 04:47:53.643661 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4489 04:47:53.643715 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4490 04:47:53.643768 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4491 04:47:53.643821 0 9 12 | B1->B0 | 3030 2b2b | 0 0 | (0 0) (0 0)
4492 04:47:53.643874 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 04:47:53.643927 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 04:47:53.643980 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 04:47:53.644033 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 04:47:53.644085 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 04:47:53.644162 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 04:47:53.644217 0 10 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
4499 04:47:53.644271 0 10 12 | B1->B0 | 3838 3a3a | 1 0 | (0 0) (0 0)
4500 04:47:53.644348 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 04:47:53.644402 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 04:47:53.644455 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 04:47:53.644507 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 04:47:53.644561 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 04:47:53.644614 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 04:47:53.644667 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4507 04:47:53.644720 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4508 04:47:53.644773 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 04:47:53.644826 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 04:47:53.644878 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 04:47:53.644931 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 04:47:53.644984 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 04:47:53.645037 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 04:47:53.645089 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 04:47:53.645143 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 04:47:53.645195 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 04:47:53.645248 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 04:47:53.645301 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 04:47:53.645354 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 04:47:53.645407 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 04:47:53.645459 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 04:47:53.645512 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 04:47:53.645565 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4524 04:47:53.645618 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4525 04:47:53.645671 Total UI for P1: 0, mck2ui 16
4526 04:47:53.645724 best dqsien dly found for B0: ( 0, 13, 12)
4527 04:47:53.645777 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 04:47:53.645830 Total UI for P1: 0, mck2ui 16
4529 04:47:53.645883 best dqsien dly found for B1: ( 0, 13, 16)
4530 04:47:53.645936 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4531 04:47:53.645989 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4532 04:47:53.646056
4533 04:47:53.646305 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4534 04:47:53.646366 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4535 04:47:53.646421 [Gating] SW calibration Done
4536 04:47:53.646475 ==
4537 04:47:53.646528 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 04:47:53.646581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 04:47:53.646636 ==
4540 04:47:53.646689 RX Vref Scan: 0
4541 04:47:53.646742
4542 04:47:53.646795 RX Vref 0 -> 0, step: 1
4543 04:47:53.646847
4544 04:47:53.646900 RX Delay -230 -> 252, step: 16
4545 04:47:53.646953 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4546 04:47:53.647005 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4547 04:47:53.647058 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4548 04:47:53.647111 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4549 04:47:53.647164 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4550 04:47:53.647232 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4551 04:47:53.647300 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4552 04:47:53.647384 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4553 04:47:53.647437 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4554 04:47:53.647490 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4555 04:47:53.647542 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4556 04:47:53.647595 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4557 04:47:53.647648 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4558 04:47:53.647701 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4559 04:47:53.647755 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4560 04:47:53.647807 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4561 04:47:53.647859 ==
4562 04:47:53.647912 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 04:47:53.647964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 04:47:53.648017 ==
4565 04:47:53.648070 DQS Delay:
4566 04:47:53.648131 DQS0 = 0, DQS1 = 0
4567 04:47:53.648232 DQM Delay:
4568 04:47:53.648333 DQM0 = 50, DQM1 = 46
4569 04:47:53.648389 DQ Delay:
4570 04:47:53.648442 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4571 04:47:53.648496 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4572 04:47:53.648549 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4573 04:47:53.648602 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4574 04:47:53.648655
4575 04:47:53.648708
4576 04:47:53.648760 ==
4577 04:47:53.648813 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 04:47:53.648866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 04:47:53.648920 ==
4580 04:47:53.648973
4581 04:47:53.649025
4582 04:47:53.649077 TX Vref Scan disable
4583 04:47:53.649130 == TX Byte 0 ==
4584 04:47:53.649183 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4585 04:47:53.649236 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4586 04:47:53.649288 == TX Byte 1 ==
4587 04:47:53.649341 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4588 04:47:53.649393 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4589 04:47:53.649446 ==
4590 04:47:53.649499 Dram Type= 6, Freq= 0, CH_1, rank 0
4591 04:47:53.649552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 04:47:53.649604 ==
4593 04:47:53.649657
4594 04:47:53.649709
4595 04:47:53.649761 TX Vref Scan disable
4596 04:47:53.649814 == TX Byte 0 ==
4597 04:47:53.649869 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4598 04:47:53.649926 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4599 04:47:53.649982 == TX Byte 1 ==
4600 04:47:53.650035 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4601 04:47:53.650088 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4602 04:47:53.650140
4603 04:47:53.650191 [DATLAT]
4604 04:47:53.650244 Freq=600, CH1 RK0
4605 04:47:53.650296
4606 04:47:53.650348 DATLAT Default: 0x9
4607 04:47:53.650400 0, 0xFFFF, sum = 0
4608 04:47:53.650455 1, 0xFFFF, sum = 0
4609 04:47:53.650509 2, 0xFFFF, sum = 0
4610 04:47:53.650562 3, 0xFFFF, sum = 0
4611 04:47:53.650615 4, 0xFFFF, sum = 0
4612 04:47:53.650669 5, 0xFFFF, sum = 0
4613 04:47:53.650727 6, 0xFFFF, sum = 0
4614 04:47:53.650783 7, 0xFFFF, sum = 0
4615 04:47:53.650853 8, 0x0, sum = 1
4616 04:47:53.650967 9, 0x0, sum = 2
4617 04:47:53.651051 10, 0x0, sum = 3
4618 04:47:53.651119 11, 0x0, sum = 4
4619 04:47:53.651173 best_step = 9
4620 04:47:53.651225
4621 04:47:53.651277 ==
4622 04:47:53.651330 Dram Type= 6, Freq= 0, CH_1, rank 0
4623 04:47:53.651383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 04:47:53.651437 ==
4625 04:47:53.651489 RX Vref Scan: 1
4626 04:47:53.651541
4627 04:47:53.651593 RX Vref 0 -> 0, step: 1
4628 04:47:53.651646
4629 04:47:53.651698 RX Delay -163 -> 252, step: 8
4630 04:47:53.651750
4631 04:47:53.651802 Set Vref, RX VrefLevel [Byte0]: 56
4632 04:47:53.651854 [Byte1]: 56
4633 04:47:53.651907
4634 04:47:53.651959 Final RX Vref Byte 0 = 56 to rank0
4635 04:47:53.652012 Final RX Vref Byte 1 = 56 to rank0
4636 04:47:53.652064 Final RX Vref Byte 0 = 56 to rank1
4637 04:47:53.652124 Final RX Vref Byte 1 = 56 to rank1==
4638 04:47:53.652233 Dram Type= 6, Freq= 0, CH_1, rank 0
4639 04:47:53.652341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 04:47:53.652397 ==
4641 04:47:53.652450 DQS Delay:
4642 04:47:53.652502 DQS0 = 0, DQS1 = 0
4643 04:47:53.652555 DQM Delay:
4644 04:47:53.652607 DQM0 = 49, DQM1 = 44
4645 04:47:53.652660 DQ Delay:
4646 04:47:53.652713 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =48
4647 04:47:53.652766 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4648 04:47:53.652818 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4649 04:47:53.652871 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4650 04:47:53.652924
4651 04:47:53.652980
4652 04:47:53.653036 [DQSOSCAuto] RK0, (LSB)MR18= 0x496f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4653 04:47:53.653100 CH1 RK0: MR19=808, MR18=496F
4654 04:47:53.653160 CH1_RK0: MR19=0x808, MR18=0x496F, DQSOSC=389, MR23=63, INC=173, DEC=115
4655 04:47:53.653216
4656 04:47:53.653269 ----->DramcWriteLeveling(PI) begin...
4657 04:47:53.653323 ==
4658 04:47:53.653379 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 04:47:53.653433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 04:47:53.653486 ==
4661 04:47:53.653538 Write leveling (Byte 0): 29 => 29
4662 04:47:53.653596 Write leveling (Byte 1): 30 => 30
4663 04:47:53.653649 DramcWriteLeveling(PI) end<-----
4664 04:47:53.653701
4665 04:47:53.653757 ==
4666 04:47:53.653811 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 04:47:53.653864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 04:47:53.653918 ==
4669 04:47:53.653974 [Gating] SW mode calibration
4670 04:47:53.654028 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4671 04:47:53.654082 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4672 04:47:53.654183 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4673 04:47:53.654306 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4674 04:47:53.654392 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4675 04:47:53.654474 0 9 12 | B1->B0 | 2c2c 2e2e | 1 1 | (1 0) (1 0)
4676 04:47:53.654564 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 04:47:53.654647 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 04:47:53.654981 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 04:47:53.655093 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 04:47:53.655187 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 04:47:53.655281 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 04:47:53.655367 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 04:47:53.655451 0 10 12 | B1->B0 | 3939 3939 | 0 0 | (0 0) (0 0)
4684 04:47:53.655509 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 04:47:53.655564 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 04:47:53.655617 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 04:47:53.655675 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 04:47:53.655731 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 04:47:53.655788 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 04:47:53.655840 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 04:47:53.655893 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 04:47:53.655945 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 04:47:53.656005 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 04:47:53.656089 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 04:47:53.656182 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 04:47:53.656272 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 04:47:53.656370 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 04:47:53.656425 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 04:47:53.656478 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 04:47:53.656539 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 04:47:53.656594 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 04:47:53.656646 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 04:47:53.656707 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 04:47:53.656761 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 04:47:53.656814 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 04:47:53.656903 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 04:47:53.656961 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 04:47:53.657014 Total UI for P1: 0, mck2ui 16
4709 04:47:53.657067 best dqsien dly found for B0: ( 0, 13, 10)
4710 04:47:53.657120 Total UI for P1: 0, mck2ui 16
4711 04:47:53.657234 best dqsien dly found for B1: ( 0, 13, 10)
4712 04:47:53.657316 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4713 04:47:53.657397 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4714 04:47:53.657484
4715 04:47:53.657566 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4716 04:47:53.657651 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4717 04:47:53.657734 [Gating] SW calibration Done
4718 04:47:53.657814 ==
4719 04:47:53.657895 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 04:47:53.657981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 04:47:53.658062 ==
4722 04:47:53.658146 RX Vref Scan: 0
4723 04:47:53.658227
4724 04:47:53.658307 RX Vref 0 -> 0, step: 1
4725 04:47:53.658387
4726 04:47:53.658471 RX Delay -230 -> 252, step: 16
4727 04:47:53.658553 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4728 04:47:53.658640 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4729 04:47:53.658723 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4730 04:47:53.658804 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4731 04:47:53.658885 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4732 04:47:53.658970 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4733 04:47:53.659051 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4734 04:47:53.659136 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4735 04:47:53.659218 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4736 04:47:53.659299 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4737 04:47:53.659381 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4738 04:47:53.659450 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4739 04:47:53.659504 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4740 04:47:53.659557 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4741 04:47:53.659615 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4742 04:47:53.659671 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4743 04:47:53.659723 ==
4744 04:47:53.659776 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 04:47:53.659828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 04:47:53.659910 ==
4747 04:47:53.659991 DQS Delay:
4748 04:47:53.660071 DQS0 = 0, DQS1 = 0
4749 04:47:53.660181 DQM Delay:
4750 04:47:53.660271 DQM0 = 48, DQM1 = 48
4751 04:47:53.660356 DQ Delay:
4752 04:47:53.660416 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =49
4753 04:47:53.660471 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4754 04:47:53.660523 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4755 04:47:53.660577 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4756 04:47:53.660629
4757 04:47:53.660692
4758 04:47:53.660745 ==
4759 04:47:53.660797 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 04:47:53.660855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 04:47:53.660909 ==
4762 04:47:53.660961
4763 04:47:53.661012
4764 04:47:53.661066 TX Vref Scan disable
4765 04:47:53.661123 == TX Byte 0 ==
4766 04:47:53.661176 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4767 04:47:53.661229 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4768 04:47:53.661287 == TX Byte 1 ==
4769 04:47:53.661373 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4770 04:47:53.661465 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4771 04:47:53.661547 ==
4772 04:47:53.661634 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 04:47:53.661717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 04:47:53.661802 ==
4775 04:47:53.661884
4776 04:47:53.661964
4777 04:47:53.662051 TX Vref Scan disable
4778 04:47:53.662132 == TX Byte 0 ==
4779 04:47:53.662219 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4780 04:47:53.662301 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4781 04:47:53.662384 == TX Byte 1 ==
4782 04:47:53.662466 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4783 04:47:53.662548 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4784 04:47:53.662632
4785 04:47:53.662712 [DATLAT]
4786 04:47:53.662792 Freq=600, CH1 RK1
4787 04:47:53.662876
4788 04:47:53.662957 DATLAT Default: 0x9
4789 04:47:53.663038 0, 0xFFFF, sum = 0
4790 04:47:53.663121 1, 0xFFFF, sum = 0
4791 04:47:53.663197 2, 0xFFFF, sum = 0
4792 04:47:53.663261 3, 0xFFFF, sum = 0
4793 04:47:53.663316 4, 0xFFFF, sum = 0
4794 04:47:53.663374 5, 0xFFFF, sum = 0
4795 04:47:53.663458 6, 0xFFFF, sum = 0
4796 04:47:53.663540 7, 0xFFFF, sum = 0
4797 04:47:53.663627 8, 0x0, sum = 1
4798 04:47:53.663712 9, 0x0, sum = 2
4799 04:47:53.663994 10, 0x0, sum = 3
4800 04:47:53.664121 11, 0x0, sum = 4
4801 04:47:53.664244 best_step = 9
4802 04:47:53.664350
4803 04:47:53.664406 ==
4804 04:47:53.664460 Dram Type= 6, Freq= 0, CH_1, rank 1
4805 04:47:53.664514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4806 04:47:53.664574 ==
4807 04:47:53.664629 RX Vref Scan: 0
4808 04:47:53.664682
4809 04:47:53.664742 RX Vref 0 -> 0, step: 1
4810 04:47:53.664795
4811 04:47:53.664847 RX Delay -163 -> 252, step: 8
4812 04:47:53.664900 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4813 04:47:53.664960 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4814 04:47:53.665013 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4815 04:47:53.665066 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4816 04:47:53.665119 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4817 04:47:53.665172 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4818 04:47:53.665224 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4819 04:47:53.665282 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4820 04:47:53.665339 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4821 04:47:53.665393 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4822 04:47:53.665453 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4823 04:47:53.665506 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4824 04:47:53.665559 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4825 04:47:53.665611 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4826 04:47:53.665663 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4827 04:47:53.665715 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4828 04:47:53.665772 ==
4829 04:47:53.665826 Dram Type= 6, Freq= 0, CH_1, rank 1
4830 04:47:53.665879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4831 04:47:53.665940 ==
4832 04:47:53.665993 DQS Delay:
4833 04:47:53.666046 DQS0 = 0, DQS1 = 0
4834 04:47:53.666099 DQM Delay:
4835 04:47:53.666150 DQM0 = 48, DQM1 = 44
4836 04:47:53.666202 DQ Delay:
4837 04:47:53.666259 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4838 04:47:53.666312 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4839 04:47:53.666364 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4840 04:47:53.666425 DQ12 =52, DQ13 =48, DQ14 =52, DQ15 =52
4841 04:47:53.666480
4842 04:47:53.666532
4843 04:47:53.666583 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4844 04:47:53.666636 CH1 RK1: MR19=808, MR18=6B22
4845 04:47:53.666689 CH1_RK1: MR19=0x808, MR18=0x6B22, DQSOSC=389, MR23=63, INC=173, DEC=115
4846 04:47:53.666742 [RxdqsGatingPostProcess] freq 600
4847 04:47:53.666799 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4848 04:47:53.666852 Pre-setting of DQS Precalculation
4849 04:47:53.666910 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4850 04:47:53.666964 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4851 04:47:53.667017 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4852 04:47:53.667069
4853 04:47:53.667121
4854 04:47:53.667172 [Calibration Summary] 1200 Mbps
4855 04:47:53.667224 CH 0, Rank 0
4856 04:47:53.667283 SW Impedance : PASS
4857 04:47:53.667335 DUTY Scan : NO K
4858 04:47:53.667394 ZQ Calibration : PASS
4859 04:47:53.667477 Jitter Meter : NO K
4860 04:47:53.667558 CBT Training : PASS
4861 04:47:53.667639 Write leveling : PASS
4862 04:47:53.667720 RX DQS gating : PASS
4863 04:47:53.667806 RX DQ/DQS(RDDQC) : PASS
4864 04:47:53.667890 TX DQ/DQS : PASS
4865 04:47:53.667972 RX DATLAT : PASS
4866 04:47:53.668053 RX DQ/DQS(Engine): PASS
4867 04:47:53.668133 TX OE : NO K
4868 04:47:53.668241 All Pass.
4869 04:47:53.668334
4870 04:47:53.668393 CH 0, Rank 1
4871 04:47:53.668447 SW Impedance : PASS
4872 04:47:53.668500 DUTY Scan : NO K
4873 04:47:53.668552 ZQ Calibration : PASS
4874 04:47:53.668605 Jitter Meter : NO K
4875 04:47:53.668663 CBT Training : PASS
4876 04:47:53.668716 Write leveling : PASS
4877 04:47:53.668769 RX DQS gating : PASS
4878 04:47:53.668821 RX DQ/DQS(RDDQC) : PASS
4879 04:47:53.668873 TX DQ/DQS : PASS
4880 04:47:53.668925 RX DATLAT : PASS
4881 04:47:53.668991 RX DQ/DQS(Engine): PASS
4882 04:47:53.669045 TX OE : NO K
4883 04:47:53.669097 All Pass.
4884 04:47:53.669157
4885 04:47:53.669210 CH 1, Rank 0
4886 04:47:53.669262 SW Impedance : PASS
4887 04:47:53.669315 DUTY Scan : NO K
4888 04:47:53.669367 ZQ Calibration : PASS
4889 04:47:53.669419 Jitter Meter : NO K
4890 04:47:53.669480 CBT Training : PASS
4891 04:47:53.669533 Write leveling : PASS
4892 04:47:53.669585 RX DQS gating : PASS
4893 04:47:53.669649 RX DQ/DQS(RDDQC) : PASS
4894 04:47:53.669703 TX DQ/DQS : PASS
4895 04:47:53.669755 RX DATLAT : PASS
4896 04:47:53.669808 RX DQ/DQS(Engine): PASS
4897 04:47:53.669860 TX OE : NO K
4898 04:47:53.669913 All Pass.
4899 04:47:53.669964
4900 04:47:53.670016 CH 1, Rank 1
4901 04:47:53.670068 SW Impedance : PASS
4902 04:47:53.670120 DUTY Scan : NO K
4903 04:47:53.969785 ZQ Calibration : PASS
4904 04:47:53.969944 Jitter Meter : NO K
4905 04:47:53.970078 CBT Training : PASS
4906 04:47:53.970141 Write leveling : PASS
4907 04:47:53.970200 RX DQS gating : PASS
4908 04:47:53.970257 RX DQ/DQS(RDDQC) : PASS
4909 04:47:53.970312 TX DQ/DQS : PASS
4910 04:47:53.970368 RX DATLAT : PASS
4911 04:47:53.970421 RX DQ/DQS(Engine): PASS
4912 04:47:53.970492 TX OE : NO K
4913 04:47:53.970573 All Pass.
4914 04:47:53.970641
4915 04:47:53.970693 DramC Write-DBI off
4916 04:47:53.970747 PER_BANK_REFRESH: Hybrid Mode
4917 04:47:53.970838 TX_TRACKING: ON
4918 04:47:53.970894 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4919 04:47:53.970949 [FAST_K] Save calibration result to emmc
4920 04:47:53.971003 dramc_set_vcore_voltage set vcore to 662500
4921 04:47:53.971056 Read voltage for 933, 3
4922 04:47:53.971108 Vio18 = 0
4923 04:47:53.971165 Vcore = 662500
4924 04:47:53.971219 Vdram = 0
4925 04:47:53.971271 Vddq = 0
4926 04:47:53.971324 Vmddr = 0
4927 04:47:53.971376 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4928 04:47:53.971429 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4929 04:47:53.971483 MEM_TYPE=3, freq_sel=17
4930 04:47:53.971535 sv_algorithm_assistance_LP4_1600
4931 04:47:53.971587 ============ PULL DRAM RESETB DOWN ============
4932 04:47:53.971641 ========== PULL DRAM RESETB DOWN end =========
4933 04:47:53.971694 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4934 04:47:53.971746 ===================================
4935 04:47:53.971798 LPDDR4 DRAM CONFIGURATION
4936 04:47:53.971850 ===================================
4937 04:47:53.971902 EX_ROW_EN[0] = 0x0
4938 04:47:53.971955 EX_ROW_EN[1] = 0x0
4939 04:47:53.972007 LP4Y_EN = 0x0
4940 04:47:53.972059 WORK_FSP = 0x0
4941 04:47:53.972111 WL = 0x3
4942 04:47:53.972163 RL = 0x3
4943 04:47:53.972427 BL = 0x2
4944 04:47:53.972530 RPST = 0x0
4945 04:47:53.972612 RD_PRE = 0x0
4946 04:47:53.972697 WR_PRE = 0x1
4947 04:47:53.972753 WR_PST = 0x0
4948 04:47:53.972806 DBI_WR = 0x0
4949 04:47:53.972859 DBI_RD = 0x0
4950 04:47:53.972911 OTF = 0x1
4951 04:47:53.972964 ===================================
4952 04:47:53.973016 ===================================
4953 04:47:53.973069 ANA top config
4954 04:47:53.973121 ===================================
4955 04:47:53.973174 DLL_ASYNC_EN = 0
4956 04:47:53.973226 ALL_SLAVE_EN = 1
4957 04:47:53.973279 NEW_RANK_MODE = 1
4958 04:47:53.973332 DLL_IDLE_MODE = 1
4959 04:47:53.973458 LP45_APHY_COMB_EN = 1
4960 04:47:53.973528 TX_ODT_DIS = 1
4961 04:47:53.973582 NEW_8X_MODE = 1
4962 04:47:53.973635 ===================================
4963 04:47:53.973688 ===================================
4964 04:47:53.973741 data_rate = 1866
4965 04:47:53.973793 CKR = 1
4966 04:47:53.973846 DQ_P2S_RATIO = 8
4967 04:47:53.973899 ===================================
4968 04:47:53.973952 CA_P2S_RATIO = 8
4969 04:47:53.974004 DQ_CA_OPEN = 0
4970 04:47:53.974057 DQ_SEMI_OPEN = 0
4971 04:47:53.974109 CA_SEMI_OPEN = 0
4972 04:47:53.974161 CA_FULL_RATE = 0
4973 04:47:53.974216 DQ_CKDIV4_EN = 1
4974 04:47:53.974269 CA_CKDIV4_EN = 1
4975 04:47:53.974320 CA_PREDIV_EN = 0
4976 04:47:53.974372 PH8_DLY = 0
4977 04:47:53.974424 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4978 04:47:53.974475 DQ_AAMCK_DIV = 4
4979 04:47:53.974527 CA_AAMCK_DIV = 4
4980 04:47:53.974579 CA_ADMCK_DIV = 4
4981 04:47:53.974646 DQ_TRACK_CA_EN = 0
4982 04:47:53.974727 CA_PICK = 933
4983 04:47:53.974793 CA_MCKIO = 933
4984 04:47:53.974845 MCKIO_SEMI = 0
4985 04:47:53.974913 PLL_FREQ = 3732
4986 04:47:53.974966 DQ_UI_PI_RATIO = 32
4987 04:47:53.975033 CA_UI_PI_RATIO = 0
4988 04:47:53.975084 ===================================
4989 04:47:53.975136 ===================================
4990 04:47:53.975188 memory_type:LPDDR4
4991 04:47:53.975240 GP_NUM : 10
4992 04:47:53.975292 SRAM_EN : 1
4993 04:47:53.975350 MD32_EN : 0
4994 04:47:53.975406 ===================================
4995 04:47:53.975459 [ANA_INIT] >>>>>>>>>>>>>>
4996 04:47:53.975511 <<<<<< [CONFIGURE PHASE]: ANA_TX
4997 04:47:53.975564 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4998 04:47:53.975616 ===================================
4999 04:47:53.975668 data_rate = 1866,PCW = 0X8f00
5000 04:47:53.975720 ===================================
5001 04:47:53.975773 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5002 04:47:53.975825 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5003 04:47:53.975878 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5004 04:47:53.975930 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5005 04:47:53.975983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5006 04:47:53.976036 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5007 04:47:53.976088 [ANA_INIT] flow start
5008 04:47:53.976141 [ANA_INIT] PLL >>>>>>>>
5009 04:47:53.976193 [ANA_INIT] PLL <<<<<<<<
5010 04:47:53.976245 [ANA_INIT] MIDPI >>>>>>>>
5011 04:47:53.976323 [ANA_INIT] MIDPI <<<<<<<<
5012 04:47:53.976391 [ANA_INIT] DLL >>>>>>>>
5013 04:47:53.976444 [ANA_INIT] flow end
5014 04:47:53.976496 ============ LP4 DIFF to SE enter ============
5015 04:47:53.976549 ============ LP4 DIFF to SE exit ============
5016 04:47:53.976602 [ANA_INIT] <<<<<<<<<<<<<
5017 04:47:53.976655 [Flow] Enable top DCM control >>>>>
5018 04:47:53.976707 [Flow] Enable top DCM control <<<<<
5019 04:47:53.976760 Enable DLL master slave shuffle
5020 04:47:53.976812 ==============================================================
5021 04:47:53.976866 Gating Mode config
5022 04:47:53.976924 ==============================================================
5023 04:47:53.976979 Config description:
5024 04:47:53.977032 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5025 04:47:53.977086 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5026 04:47:53.977139 SELPH_MODE 0: By rank 1: By Phase
5027 04:47:53.977192 ==============================================================
5028 04:47:53.977245 GAT_TRACK_EN = 1
5029 04:47:53.977376 RX_GATING_MODE = 2
5030 04:47:53.977445 RX_GATING_TRACK_MODE = 2
5031 04:47:53.977498 SELPH_MODE = 1
5032 04:47:53.977551 PICG_EARLY_EN = 1
5033 04:47:53.977603 VALID_LAT_VALUE = 1
5034 04:47:53.977656 ==============================================================
5035 04:47:53.977709 Enter into Gating configuration >>>>
5036 04:47:53.977762 Exit from Gating configuration <<<<
5037 04:47:53.977815 Enter into DVFS_PRE_config >>>>>
5038 04:47:53.977867 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5039 04:47:53.977921 Exit from DVFS_PRE_config <<<<<
5040 04:47:53.977974 Enter into PICG configuration >>>>
5041 04:47:53.978027 Exit from PICG configuration <<<<
5042 04:47:53.978079 [RX_INPUT] configuration >>>>>
5043 04:47:53.978132 [RX_INPUT] configuration <<<<<
5044 04:47:53.978185 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5045 04:47:53.978238 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5046 04:47:53.978321 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5047 04:47:53.978391 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5048 04:47:53.978445 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5049 04:47:53.978500 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5050 04:47:53.978754 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5051 04:47:53.978819 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5052 04:47:53.978891 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5053 04:47:53.978961 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5054 04:47:53.979016 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5055 04:47:53.979069 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5056 04:47:53.979123 ===================================
5057 04:47:53.979177 LPDDR4 DRAM CONFIGURATION
5058 04:47:53.979233 ===================================
5059 04:47:53.979290 EX_ROW_EN[0] = 0x0
5060 04:47:53.979343 EX_ROW_EN[1] = 0x0
5061 04:47:53.979396 LP4Y_EN = 0x0
5062 04:47:53.979448 WORK_FSP = 0x0
5063 04:47:53.979501 WL = 0x3
5064 04:47:53.979554 RL = 0x3
5065 04:47:53.979606 BL = 0x2
5066 04:47:53.979658 RPST = 0x0
5067 04:47:53.979715 RD_PRE = 0x0
5068 04:47:53.979772 WR_PRE = 0x1
5069 04:47:53.979825 WR_PST = 0x0
5070 04:47:53.979877 DBI_WR = 0x0
5071 04:47:53.979930 DBI_RD = 0x0
5072 04:47:53.979982 OTF = 0x1
5073 04:47:53.980035 ===================================
5074 04:47:53.980089 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5075 04:47:53.980142 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5076 04:47:53.980195 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5077 04:47:53.980248 ===================================
5078 04:47:53.980327 LPDDR4 DRAM CONFIGURATION
5079 04:47:53.980438 ===================================
5080 04:47:53.980497 EX_ROW_EN[0] = 0x10
5081 04:47:53.980559 EX_ROW_EN[1] = 0x0
5082 04:47:53.980631 LP4Y_EN = 0x0
5083 04:47:53.980684 WORK_FSP = 0x0
5084 04:47:53.980737 WL = 0x3
5085 04:47:53.980790 RL = 0x3
5086 04:47:53.980843 BL = 0x2
5087 04:47:53.980895 RPST = 0x0
5088 04:47:53.980947 RD_PRE = 0x0
5089 04:47:53.981059 WR_PRE = 0x1
5090 04:47:53.981135 WR_PST = 0x0
5091 04:47:53.981220 DBI_WR = 0x0
5092 04:47:53.981310 DBI_RD = 0x0
5093 04:47:53.981424 OTF = 0x1
5094 04:47:53.981482 ===================================
5095 04:47:53.981538 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5096 04:47:53.981593 nWR fixed to 30
5097 04:47:53.981647 [ModeRegInit_LP4] CH0 RK0
5098 04:47:53.981701 [ModeRegInit_LP4] CH0 RK1
5099 04:47:53.981753 [ModeRegInit_LP4] CH1 RK0
5100 04:47:53.981806 [ModeRegInit_LP4] CH1 RK1
5101 04:47:53.981859 match AC timing 9
5102 04:47:53.981912 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5103 04:47:53.981965 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5104 04:47:53.982018 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5105 04:47:53.982101 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5106 04:47:53.982170 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5107 04:47:53.982225 ==
5108 04:47:53.982279 Dram Type= 6, Freq= 0, CH_0, rank 0
5109 04:47:53.982333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5110 04:47:53.982401 ==
5111 04:47:53.982454 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5112 04:47:53.982507 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5113 04:47:53.982561 [CA 0] Center 37 (6~68) winsize 63
5114 04:47:53.982613 [CA 1] Center 37 (6~68) winsize 63
5115 04:47:53.982666 [CA 2] Center 34 (4~65) winsize 62
5116 04:47:53.982719 [CA 3] Center 34 (3~65) winsize 63
5117 04:47:53.982772 [CA 4] Center 33 (3~64) winsize 62
5118 04:47:53.982825 [CA 5] Center 32 (2~62) winsize 61
5119 04:47:53.982879
5120 04:47:53.982931 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5121 04:47:53.982985
5122 04:47:53.983037 [CATrainingPosCal] consider 1 rank data
5123 04:47:53.983090 u2DelayCellTimex100 = 270/100 ps
5124 04:47:53.983143 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5125 04:47:53.983196 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5126 04:47:53.983249 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5127 04:47:53.983302 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5128 04:47:53.983354 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5129 04:47:53.983423 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5130 04:47:53.983536
5131 04:47:53.983610 CA PerBit enable=1, Macro0, CA PI delay=32
5132 04:47:53.983693
5133 04:47:53.983775 [CBTSetCACLKResult] CA Dly = 32
5134 04:47:53.983857 CS Dly: 5 (0~36)
5135 04:47:53.983938 ==
5136 04:47:53.984062 Dram Type= 6, Freq= 0, CH_0, rank 1
5137 04:47:53.984175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5138 04:47:53.984264 ==
5139 04:47:53.984351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5140 04:47:53.984408 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5141 04:47:53.984462 [CA 0] Center 37 (7~68) winsize 62
5142 04:47:53.984516 [CA 1] Center 37 (7~68) winsize 62
5143 04:47:53.984568 [CA 2] Center 34 (4~65) winsize 62
5144 04:47:53.984621 [CA 3] Center 34 (3~65) winsize 63
5145 04:47:53.984674 [CA 4] Center 33 (3~63) winsize 61
5146 04:47:53.984726 [CA 5] Center 32 (2~62) winsize 61
5147 04:47:53.984780
5148 04:47:53.984838 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5149 04:47:53.984928
5150 04:47:53.985035 [CATrainingPosCal] consider 2 rank data
5151 04:47:53.985130 u2DelayCellTimex100 = 270/100 ps
5152 04:47:53.985214 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5153 04:47:53.985304 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5154 04:47:53.985390 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5155 04:47:53.985474 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5156 04:47:53.985556 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5157 04:47:53.985638 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5158 04:47:53.985719
5159 04:47:53.985802 CA PerBit enable=1, Macro0, CA PI delay=32
5160 04:47:53.985862
5161 04:47:53.985918 [CBTSetCACLKResult] CA Dly = 32
5162 04:47:53.985972 CS Dly: 5 (0~37)
5163 04:47:53.986025
5164 04:47:53.986083 ----->DramcWriteLeveling(PI) begin...
5165 04:47:53.986140 ==
5166 04:47:53.986193 Dram Type= 6, Freq= 0, CH_0, rank 0
5167 04:47:53.986246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5168 04:47:53.986300 ==
5169 04:47:53.986423 Write leveling (Byte 0): 34 => 34
5170 04:47:53.986511 Write leveling (Byte 1): 29 => 29
5171 04:47:53.986576 DramcWriteLeveling(PI) end<-----
5172 04:47:53.986661
5173 04:47:53.986770 ==
5174 04:47:53.989968 Dram Type= 6, Freq= 0, CH_0, rank 0
5175 04:47:53.993635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5176 04:47:53.993736 ==
5177 04:47:53.996800 [Gating] SW mode calibration
5178 04:47:54.003617 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5179 04:47:54.006994 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5180 04:47:54.013390 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
5181 04:47:54.016463 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 04:47:54.019974 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 04:47:54.026501 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 04:47:54.029872 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 04:47:54.033329 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5186 04:47:54.040224 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5187 04:47:54.043131 0 14 28 | B1->B0 | 3232 2424 | 1 0 | (1 0) (0 0)
5188 04:47:54.046867 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5189 04:47:54.053013 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 04:47:54.056383 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 04:47:54.059748 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 04:47:54.066365 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 04:47:54.069716 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 04:47:54.073137 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5195 04:47:54.079941 0 15 28 | B1->B0 | 2424 4141 | 0 1 | (0 0) (1 1)
5196 04:47:54.083450 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5197 04:47:54.086123 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 04:47:54.092712 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 04:47:54.095931 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 04:47:54.099741 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 04:47:54.106417 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 04:47:54.109305 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5203 04:47:54.112751 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5204 04:47:54.116116 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5205 04:47:54.122558 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 04:47:54.125821 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 04:47:54.132384 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 04:47:54.136350 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 04:47:54.139021 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 04:47:54.142404 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 04:47:54.149389 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 04:47:54.152446 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 04:47:54.155931 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 04:47:54.162543 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 04:47:54.165830 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 04:47:54.168917 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 04:47:54.176073 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 04:47:54.179585 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5219 04:47:54.182864 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5220 04:47:54.186158 Total UI for P1: 0, mck2ui 16
5221 04:47:54.188863 best dqsien dly found for B0: ( 1, 2, 24)
5222 04:47:54.195774 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5223 04:47:54.199163 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 04:47:54.202435 Total UI for P1: 0, mck2ui 16
5225 04:47:54.205676 best dqsien dly found for B1: ( 1, 2, 30)
5226 04:47:54.209346 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5227 04:47:54.212647 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5228 04:47:54.212730
5229 04:47:54.215999 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5230 04:47:54.219364 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5231 04:47:54.222694 [Gating] SW calibration Done
5232 04:47:54.222802 ==
5233 04:47:54.226020 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 04:47:54.229306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 04:47:54.229388 ==
5236 04:47:54.232644 RX Vref Scan: 0
5237 04:47:54.232771
5238 04:47:54.236001 RX Vref 0 -> 0, step: 1
5239 04:47:54.236108
5240 04:47:54.236201 RX Delay -80 -> 252, step: 8
5241 04:47:54.242925 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5242 04:47:54.246342 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5243 04:47:54.249546 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5244 04:47:54.252209 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5245 04:47:54.255585 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5246 04:47:54.262266 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5247 04:47:54.265632 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5248 04:47:54.269085 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5249 04:47:54.272531 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5250 04:47:54.275815 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5251 04:47:54.282539 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5252 04:47:54.285689 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5253 04:47:54.289358 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5254 04:47:54.292611 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5255 04:47:54.295560 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5256 04:47:54.298644 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5257 04:47:54.298726 ==
5258 04:47:54.302412 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 04:47:54.308934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 04:47:54.309025 ==
5261 04:47:54.309092 DQS Delay:
5262 04:47:54.312222 DQS0 = 0, DQS1 = 0
5263 04:47:54.312354 DQM Delay:
5264 04:47:54.315649 DQM0 = 106, DQM1 = 93
5265 04:47:54.315732 DQ Delay:
5266 04:47:54.318706 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5267 04:47:54.321895 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5268 04:47:54.325708 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5269 04:47:54.329007 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5270 04:47:54.329090
5271 04:47:54.329155
5272 04:47:54.329214 ==
5273 04:47:54.332146 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 04:47:54.335478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 04:47:54.335563 ==
5276 04:47:54.335628
5277 04:47:54.338749
5278 04:47:54.338852 TX Vref Scan disable
5279 04:47:54.342112 == TX Byte 0 ==
5280 04:47:54.345266 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5281 04:47:54.348732 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5282 04:47:54.352200 == TX Byte 1 ==
5283 04:47:54.355434 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5284 04:47:54.358988 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5285 04:47:54.359063 ==
5286 04:47:54.361822 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 04:47:54.368269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 04:47:54.368391 ==
5289 04:47:54.368455
5290 04:47:54.368513
5291 04:47:54.368577 TX Vref Scan disable
5292 04:47:54.372979 == TX Byte 0 ==
5293 04:47:54.376266 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5294 04:47:54.379640 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5295 04:47:54.382945 == TX Byte 1 ==
5296 04:47:54.386395 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5297 04:47:54.389777 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5298 04:47:54.389854
5299 04:47:54.393316 [DATLAT]
5300 04:47:54.393390 Freq=933, CH0 RK0
5301 04:47:54.393453
5302 04:47:54.396622 DATLAT Default: 0xd
5303 04:47:54.396694 0, 0xFFFF, sum = 0
5304 04:47:54.399372 1, 0xFFFF, sum = 0
5305 04:47:54.399450 2, 0xFFFF, sum = 0
5306 04:47:54.403301 3, 0xFFFF, sum = 0
5307 04:47:54.403379 4, 0xFFFF, sum = 0
5308 04:47:54.406050 5, 0xFFFF, sum = 0
5309 04:47:54.406129 6, 0xFFFF, sum = 0
5310 04:47:54.409511 7, 0xFFFF, sum = 0
5311 04:47:54.413431 8, 0xFFFF, sum = 0
5312 04:47:54.413503 9, 0xFFFF, sum = 0
5313 04:47:54.413565 10, 0x0, sum = 1
5314 04:47:54.416413 11, 0x0, sum = 2
5315 04:47:54.416512 12, 0x0, sum = 3
5316 04:47:54.419329 13, 0x0, sum = 4
5317 04:47:54.419426 best_step = 11
5318 04:47:54.419522
5319 04:47:54.419593 ==
5320 04:47:54.423153 Dram Type= 6, Freq= 0, CH_0, rank 0
5321 04:47:54.429438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 04:47:54.429521 ==
5323 04:47:54.429583 RX Vref Scan: 1
5324 04:47:54.429642
5325 04:47:54.432740 RX Vref 0 -> 0, step: 1
5326 04:47:54.432817
5327 04:47:54.435962 RX Delay -53 -> 252, step: 4
5328 04:47:54.436038
5329 04:47:54.439553 Set Vref, RX VrefLevel [Byte0]: 57
5330 04:47:54.442833 [Byte1]: 48
5331 04:47:54.442912
5332 04:47:54.446670 Final RX Vref Byte 0 = 57 to rank0
5333 04:47:54.449479 Final RX Vref Byte 1 = 48 to rank0
5334 04:47:54.452821 Final RX Vref Byte 0 = 57 to rank1
5335 04:47:54.456132 Final RX Vref Byte 1 = 48 to rank1==
5336 04:47:54.459434 Dram Type= 6, Freq= 0, CH_0, rank 0
5337 04:47:54.462722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 04:47:54.462806 ==
5339 04:47:54.466074 DQS Delay:
5340 04:47:54.466155 DQS0 = 0, DQS1 = 0
5341 04:47:54.466219 DQM Delay:
5342 04:47:54.469446 DQM0 = 105, DQM1 = 94
5343 04:47:54.469527 DQ Delay:
5344 04:47:54.472708 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5345 04:47:54.476607 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5346 04:47:54.479360 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =88
5347 04:47:54.486188 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5348 04:47:54.486274
5349 04:47:54.486339
5350 04:47:54.492726 [DQSOSCAuto] RK0, (LSB)MR18= 0x3029, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5351 04:47:54.496087 CH0 RK0: MR19=505, MR18=3029
5352 04:47:54.502762 CH0_RK0: MR19=0x505, MR18=0x3029, DQSOSC=406, MR23=63, INC=65, DEC=43
5353 04:47:54.502848
5354 04:47:54.506148 ----->DramcWriteLeveling(PI) begin...
5355 04:47:54.506234 ==
5356 04:47:54.509526 Dram Type= 6, Freq= 0, CH_0, rank 1
5357 04:47:54.512975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 04:47:54.513057 ==
5359 04:47:54.515661 Write leveling (Byte 0): 32 => 32
5360 04:47:54.519027 Write leveling (Byte 1): 27 => 27
5361 04:47:54.522445 DramcWriteLeveling(PI) end<-----
5362 04:47:54.522526
5363 04:47:54.522590 ==
5364 04:47:54.525855 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 04:47:54.529391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 04:47:54.529467 ==
5367 04:47:54.532786 [Gating] SW mode calibration
5368 04:47:54.539443 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5369 04:47:54.545863 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5370 04:47:54.548865 0 14 0 | B1->B0 | 3232 3030 | 1 0 | (1 1) (0 0)
5371 04:47:54.552179 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 04:47:54.559494 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 04:47:54.562039 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 04:47:54.565864 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 04:47:54.572237 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 04:47:54.575699 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5377 04:47:54.579375 0 14 28 | B1->B0 | 2c2c 2b2b | 0 0 | (0 0) (0 1)
5378 04:47:54.585618 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5379 04:47:54.588870 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 04:47:54.592612 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 04:47:54.599358 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 04:47:54.602649 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 04:47:54.605328 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 04:47:54.612655 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 04:47:54.616107 0 15 28 | B1->B0 | 4242 3535 | 1 0 | (0 0) (0 0)
5386 04:47:54.618811 1 0 0 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5387 04:47:54.625546 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 04:47:54.628972 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 04:47:54.632278 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 04:47:54.639068 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 04:47:54.642406 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 04:47:54.645643 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 04:47:54.652381 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5394 04:47:54.655658 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5395 04:47:54.658944 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 04:47:54.662380 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 04:47:54.669084 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 04:47:54.672400 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 04:47:54.675798 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 04:47:54.682184 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 04:47:54.685659 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 04:47:54.689326 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 04:47:54.695552 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 04:47:54.698612 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 04:47:54.702357 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 04:47:54.709220 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 04:47:54.712509 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 04:47:54.715565 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 04:47:54.722500 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5410 04:47:54.725998 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 04:47:54.728869 Total UI for P1: 0, mck2ui 16
5412 04:47:54.732385 best dqsien dly found for B0: ( 1, 2, 28)
5413 04:47:54.735651 Total UI for P1: 0, mck2ui 16
5414 04:47:54.739022 best dqsien dly found for B1: ( 1, 2, 30)
5415 04:47:54.742393 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5416 04:47:54.745721 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5417 04:47:54.745835
5418 04:47:54.748870 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5419 04:47:54.752140 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5420 04:47:54.755517 [Gating] SW calibration Done
5421 04:47:54.755598 ==
5422 04:47:54.758861 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 04:47:54.762114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 04:47:54.765535 ==
5425 04:47:54.765641 RX Vref Scan: 0
5426 04:47:54.765729
5427 04:47:54.768812 RX Vref 0 -> 0, step: 1
5428 04:47:54.768890
5429 04:47:54.768949 RX Delay -80 -> 252, step: 8
5430 04:47:54.775485 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5431 04:47:54.779015 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5432 04:47:54.782268 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5433 04:47:54.785662 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5434 04:47:54.789010 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5435 04:47:54.795407 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5436 04:47:54.799048 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5437 04:47:54.802158 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5438 04:47:54.805897 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5439 04:47:54.809240 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5440 04:47:54.811923 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5441 04:47:54.818713 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5442 04:47:54.822114 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5443 04:47:54.825341 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5444 04:47:54.829058 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5445 04:47:54.832305 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5446 04:47:54.832424 ==
5447 04:47:54.835260 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 04:47:54.842184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 04:47:54.842265 ==
5450 04:47:54.842368 DQS Delay:
5451 04:47:54.845367 DQS0 = 0, DQS1 = 0
5452 04:47:54.845462 DQM Delay:
5453 04:47:54.845540 DQM0 = 105, DQM1 = 93
5454 04:47:54.848783 DQ Delay:
5455 04:47:54.852416 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5456 04:47:54.855257 DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =115
5457 04:47:54.858384 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5458 04:47:54.861797 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5459 04:47:54.861915
5460 04:47:54.861979
5461 04:47:54.862038 ==
5462 04:47:54.865691 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 04:47:54.868824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 04:47:54.868905 ==
5465 04:47:54.868969
5466 04:47:54.869028
5467 04:47:54.872147 TX Vref Scan disable
5468 04:47:54.875509 == TX Byte 0 ==
5469 04:47:54.878293 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5470 04:47:54.881818 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5471 04:47:54.885266 == TX Byte 1 ==
5472 04:47:54.888624 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5473 04:47:54.892065 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5474 04:47:54.892146 ==
5475 04:47:54.895394 Dram Type= 6, Freq= 0, CH_0, rank 1
5476 04:47:54.901591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 04:47:54.901673 ==
5478 04:47:54.901737
5479 04:47:54.901796
5480 04:47:54.901852 TX Vref Scan disable
5481 04:47:54.905349 == TX Byte 0 ==
5482 04:47:54.908968 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5483 04:47:54.912168 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5484 04:47:54.915543 == TX Byte 1 ==
5485 04:47:54.919005 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5486 04:47:54.922301 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5487 04:47:54.925729
5488 04:47:54.925809 [DATLAT]
5489 04:47:54.925872 Freq=933, CH0 RK1
5490 04:47:54.925932
5491 04:47:54.929181 DATLAT Default: 0xb
5492 04:47:54.929261 0, 0xFFFF, sum = 0
5493 04:47:54.932235 1, 0xFFFF, sum = 0
5494 04:47:54.932354 2, 0xFFFF, sum = 0
5495 04:47:54.935372 3, 0xFFFF, sum = 0
5496 04:47:54.938703 4, 0xFFFF, sum = 0
5497 04:47:54.938784 5, 0xFFFF, sum = 0
5498 04:47:54.942134 6, 0xFFFF, sum = 0
5499 04:47:54.942216 7, 0xFFFF, sum = 0
5500 04:47:54.945451 8, 0xFFFF, sum = 0
5501 04:47:54.945533 9, 0xFFFF, sum = 0
5502 04:47:54.948746 10, 0x0, sum = 1
5503 04:47:54.948819 11, 0x0, sum = 2
5504 04:47:54.951983 12, 0x0, sum = 3
5505 04:47:54.952051 13, 0x0, sum = 4
5506 04:47:54.952110 best_step = 11
5507 04:47:54.952165
5508 04:47:54.955144 ==
5509 04:47:54.958791 Dram Type= 6, Freq= 0, CH_0, rank 1
5510 04:47:54.962011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 04:47:54.962119 ==
5512 04:47:54.962212 RX Vref Scan: 0
5513 04:47:54.962302
5514 04:47:54.965103 RX Vref 0 -> 0, step: 1
5515 04:47:54.965186
5516 04:47:54.968788 RX Delay -53 -> 252, step: 4
5517 04:47:54.972045 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5518 04:47:54.978289 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5519 04:47:54.981811 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5520 04:47:54.985095 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5521 04:47:54.988489 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5522 04:47:54.992001 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5523 04:47:54.998861 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5524 04:47:55.002261 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5525 04:47:55.005080 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5526 04:47:55.008543 iDelay=199, Bit 9, Center 84 (-1 ~ 170) 172
5527 04:47:55.011838 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5528 04:47:55.015106 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5529 04:47:55.021612 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5530 04:47:55.024817 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5531 04:47:55.028314 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5532 04:47:55.031758 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5533 04:47:55.031839 ==
5534 04:47:55.035221 Dram Type= 6, Freq= 0, CH_0, rank 1
5535 04:47:55.041852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 04:47:55.041967 ==
5537 04:47:55.042031 DQS Delay:
5538 04:47:55.042090 DQS0 = 0, DQS1 = 0
5539 04:47:55.045258 DQM Delay:
5540 04:47:55.045338 DQM0 = 104, DQM1 = 94
5541 04:47:55.048687 DQ Delay:
5542 04:47:55.052062 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5543 04:47:55.055516 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5544 04:47:55.058189 DQ8 =86, DQ9 =84, DQ10 =94, DQ11 =86
5545 04:47:55.061677 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5546 04:47:55.061757
5547 04:47:55.061839
5548 04:47:55.068339 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5549 04:47:55.071657 CH0 RK1: MR19=505, MR18=2B04
5550 04:47:55.078304 CH0_RK1: MR19=0x505, MR18=0x2B04, DQSOSC=408, MR23=63, INC=65, DEC=43
5551 04:47:55.081656 [RxdqsGatingPostProcess] freq 933
5552 04:47:55.087909 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5553 04:47:55.091485 best DQS0 dly(2T, 0.5T) = (0, 10)
5554 04:47:55.091570 best DQS1 dly(2T, 0.5T) = (0, 10)
5555 04:47:55.094613 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5556 04:47:55.098515 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5557 04:47:55.101266 best DQS0 dly(2T, 0.5T) = (0, 10)
5558 04:47:55.104565 best DQS1 dly(2T, 0.5T) = (0, 10)
5559 04:47:55.108004 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5560 04:47:55.111472 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5561 04:47:55.114743 Pre-setting of DQS Precalculation
5562 04:47:55.121115 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5563 04:47:55.121199 ==
5564 04:47:55.124543 Dram Type= 6, Freq= 0, CH_1, rank 0
5565 04:47:55.127466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5566 04:47:55.127550 ==
5567 04:47:55.133945 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5568 04:47:55.141183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5569 04:47:55.144012 [CA 0] Center 36 (6~67) winsize 62
5570 04:47:55.148065 [CA 1] Center 37 (6~68) winsize 63
5571 04:47:55.151094 [CA 2] Center 34 (4~65) winsize 62
5572 04:47:55.154510 [CA 3] Center 34 (4~65) winsize 62
5573 04:47:55.154594 [CA 4] Center 34 (4~64) winsize 61
5574 04:47:55.157355 [CA 5] Center 33 (3~64) winsize 62
5575 04:47:55.157438
5576 04:47:55.164076 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5577 04:47:55.164160
5578 04:47:55.167502 [CATrainingPosCal] consider 1 rank data
5579 04:47:55.170794 u2DelayCellTimex100 = 270/100 ps
5580 04:47:55.174114 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5581 04:47:55.177533 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5582 04:47:55.180846 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5583 04:47:55.184110 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5584 04:47:55.187458 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5585 04:47:55.190917 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5586 04:47:55.191024
5587 04:47:55.194473 CA PerBit enable=1, Macro0, CA PI delay=33
5588 04:47:55.194559
5589 04:47:55.197352 [CBTSetCACLKResult] CA Dly = 33
5590 04:47:55.200983 CS Dly: 6 (0~37)
5591 04:47:55.201094 ==
5592 04:47:55.204305 Dram Type= 6, Freq= 0, CH_1, rank 1
5593 04:47:55.207881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5594 04:47:55.207997 ==
5595 04:47:55.214388 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5596 04:47:55.220785 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5597 04:47:55.224314 [CA 0] Center 36 (6~67) winsize 62
5598 04:47:55.227588 [CA 1] Center 37 (6~68) winsize 63
5599 04:47:55.230664 [CA 2] Center 35 (5~66) winsize 62
5600 04:47:55.234431 [CA 3] Center 34 (4~65) winsize 62
5601 04:47:55.237608 [CA 4] Center 34 (4~65) winsize 62
5602 04:47:55.237692 [CA 5] Center 33 (3~64) winsize 62
5603 04:47:55.240879
5604 04:47:55.243934 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5605 04:47:55.244017
5606 04:47:55.247699 [CATrainingPosCal] consider 2 rank data
5607 04:47:55.250915 u2DelayCellTimex100 = 270/100 ps
5608 04:47:55.254441 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5609 04:47:55.257604 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5610 04:47:55.260951 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5611 04:47:55.264396 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5612 04:47:55.267673 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5613 04:47:55.270402 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5614 04:47:55.270484
5615 04:47:55.273689 CA PerBit enable=1, Macro0, CA PI delay=33
5616 04:47:55.273772
5617 04:47:55.276979 [CBTSetCACLKResult] CA Dly = 33
5618 04:47:55.280853 CS Dly: 7 (0~40)
5619 04:47:55.280969
5620 04:47:55.283746 ----->DramcWriteLeveling(PI) begin...
5621 04:47:55.283855 ==
5622 04:47:55.287183 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 04:47:55.290511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 04:47:55.290597 ==
5625 04:47:55.293753 Write leveling (Byte 0): 23 => 23
5626 04:47:55.297165 Write leveling (Byte 1): 28 => 28
5627 04:47:55.300614 DramcWriteLeveling(PI) end<-----
5628 04:47:55.300697
5629 04:47:55.300766 ==
5630 04:47:55.304072 Dram Type= 6, Freq= 0, CH_1, rank 0
5631 04:47:55.306903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5632 04:47:55.306994 ==
5633 04:47:55.310343 [Gating] SW mode calibration
5634 04:47:55.317418 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5635 04:47:55.323557 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5636 04:47:55.326869 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 04:47:55.333836 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 04:47:55.337233 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 04:47:55.340519 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 04:47:55.347096 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 04:47:55.350164 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 04:47:55.353516 0 14 24 | B1->B0 | 3333 2d2d | 1 0 | (1 0) (0 0)
5643 04:47:55.360283 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
5644 04:47:55.363411 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 04:47:55.366700 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 04:47:55.373631 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 04:47:55.376730 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 04:47:55.380115 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 04:47:55.386666 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 04:47:55.390023 0 15 24 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5651 04:47:55.393442 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5652 04:47:55.396806 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 04:47:55.403403 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 04:47:55.406940 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 04:47:55.409724 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 04:47:55.416498 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 04:47:55.420061 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 04:47:55.423520 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5659 04:47:55.429810 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5660 04:47:55.433205 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 04:47:55.436759 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 04:47:55.443447 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 04:47:55.446119 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 04:47:55.450226 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 04:47:55.456126 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 04:47:55.460147 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 04:47:55.462729 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 04:47:55.469850 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 04:47:55.473062 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 04:47:55.476246 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 04:47:55.483039 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 04:47:55.486501 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 04:47:55.489400 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 04:47:55.496491 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5675 04:47:55.499594 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5676 04:47:55.502713 Total UI for P1: 0, mck2ui 16
5677 04:47:55.506078 best dqsien dly found for B1: ( 1, 2, 24)
5678 04:47:55.509366 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 04:47:55.512748 Total UI for P1: 0, mck2ui 16
5680 04:47:55.516186 best dqsien dly found for B0: ( 1, 2, 26)
5681 04:47:55.519631 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5682 04:47:55.522450 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5683 04:47:55.522533
5684 04:47:55.529403 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5685 04:47:55.532933 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5686 04:47:55.533016 [Gating] SW calibration Done
5687 04:47:55.535830 ==
5688 04:47:55.539130 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 04:47:55.542446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 04:47:55.542530 ==
5691 04:47:55.542596 RX Vref Scan: 0
5692 04:47:55.542656
5693 04:47:55.545779 RX Vref 0 -> 0, step: 1
5694 04:47:55.545862
5695 04:47:55.549002 RX Delay -80 -> 252, step: 8
5696 04:47:55.552406 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5697 04:47:55.555800 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5698 04:47:55.559099 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5699 04:47:55.565562 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5700 04:47:55.568924 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5701 04:47:55.572216 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5702 04:47:55.575653 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5703 04:47:55.579258 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5704 04:47:55.582689 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5705 04:47:55.585879 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5706 04:47:55.592667 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5707 04:47:55.595549 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5708 04:47:55.598781 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5709 04:47:55.602111 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5710 04:47:55.605744 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5711 04:47:55.612299 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5712 04:47:55.612384 ==
5713 04:47:55.615487 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 04:47:55.619249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 04:47:55.619333 ==
5716 04:47:55.619399 DQS Delay:
5717 04:47:55.622495 DQS0 = 0, DQS1 = 0
5718 04:47:55.622578 DQM Delay:
5719 04:47:55.625551 DQM0 = 103, DQM1 = 98
5720 04:47:55.625637 DQ Delay:
5721 04:47:55.629050 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5722 04:47:55.632392 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5723 04:47:55.635769 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5724 04:47:55.638595 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5725 04:47:55.638678
5726 04:47:55.638744
5727 04:47:55.638805 ==
5728 04:47:55.642071 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 04:47:55.648908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 04:47:55.649022 ==
5731 04:47:55.649115
5732 04:47:55.649204
5733 04:47:55.649291 TX Vref Scan disable
5734 04:47:55.652776 == TX Byte 0 ==
5735 04:47:55.655691 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5736 04:47:55.662562 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5737 04:47:55.662648 == TX Byte 1 ==
5738 04:47:55.666035 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5739 04:47:55.672701 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5740 04:47:55.672785 ==
5741 04:47:55.675467 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 04:47:55.678791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 04:47:55.678875 ==
5744 04:47:55.678949
5745 04:47:55.679011
5746 04:47:55.682729 TX Vref Scan disable
5747 04:47:55.682842 == TX Byte 0 ==
5748 04:47:55.689110 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5749 04:47:55.692409 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5750 04:47:55.692488 == TX Byte 1 ==
5751 04:47:55.698763 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5752 04:47:55.702225 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5753 04:47:55.702303
5754 04:47:55.702367 [DATLAT]
5755 04:47:55.705650 Freq=933, CH1 RK0
5756 04:47:55.705733
5757 04:47:55.705799 DATLAT Default: 0xd
5758 04:47:55.709213 0, 0xFFFF, sum = 0
5759 04:47:55.709313 1, 0xFFFF, sum = 0
5760 04:47:55.711956 2, 0xFFFF, sum = 0
5761 04:47:55.715474 3, 0xFFFF, sum = 0
5762 04:47:55.715558 4, 0xFFFF, sum = 0
5763 04:47:55.718847 5, 0xFFFF, sum = 0
5764 04:47:55.718957 6, 0xFFFF, sum = 0
5765 04:47:55.722268 7, 0xFFFF, sum = 0
5766 04:47:55.722352 8, 0xFFFF, sum = 0
5767 04:47:55.725615 9, 0xFFFF, sum = 0
5768 04:47:55.725698 10, 0x0, sum = 1
5769 04:47:55.728696 11, 0x0, sum = 2
5770 04:47:55.728808 12, 0x0, sum = 3
5771 04:47:55.728889 13, 0x0, sum = 4
5772 04:47:55.732222 best_step = 11
5773 04:47:55.732348
5774 04:47:55.732448 ==
5775 04:47:55.735237 Dram Type= 6, Freq= 0, CH_1, rank 0
5776 04:47:55.738690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 04:47:55.738800 ==
5778 04:47:55.742047 RX Vref Scan: 1
5779 04:47:55.742130
5780 04:47:55.745482 RX Vref 0 -> 0, step: 1
5781 04:47:55.745587
5782 04:47:55.745681 RX Delay -45 -> 252, step: 4
5783 04:47:55.745746
5784 04:47:55.748574 Set Vref, RX VrefLevel [Byte0]: 56
5785 04:47:55.751893 [Byte1]: 56
5786 04:47:55.756724
5787 04:47:55.756835 Final RX Vref Byte 0 = 56 to rank0
5788 04:47:55.760038 Final RX Vref Byte 1 = 56 to rank0
5789 04:47:55.762942 Final RX Vref Byte 0 = 56 to rank1
5790 04:47:55.766908 Final RX Vref Byte 1 = 56 to rank1==
5791 04:47:55.769696 Dram Type= 6, Freq= 0, CH_1, rank 0
5792 04:47:55.776514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 04:47:55.776598 ==
5794 04:47:55.776664 DQS Delay:
5795 04:47:55.776726 DQS0 = 0, DQS1 = 0
5796 04:47:55.779765 DQM Delay:
5797 04:47:55.779847 DQM0 = 103, DQM1 = 99
5798 04:47:55.782963 DQ Delay:
5799 04:47:55.786203 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100
5800 04:47:55.789506 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =104
5801 04:47:55.793163 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =96
5802 04:47:55.796508 DQ12 =104, DQ13 =106, DQ14 =106, DQ15 =106
5803 04:47:55.796614
5804 04:47:55.796710
5805 04:47:55.803010 [DQSOSCAuto] RK0, (LSB)MR18= 0x1830, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5806 04:47:55.806515 CH1 RK0: MR19=505, MR18=1830
5807 04:47:55.812643 CH1_RK0: MR19=0x505, MR18=0x1830, DQSOSC=406, MR23=63, INC=65, DEC=43
5808 04:47:55.812727
5809 04:47:55.816164 ----->DramcWriteLeveling(PI) begin...
5810 04:47:55.816275 ==
5811 04:47:55.819657 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 04:47:55.823168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 04:47:55.823280 ==
5814 04:47:55.826057 Write leveling (Byte 0): 24 => 24
5815 04:47:55.829431 Write leveling (Byte 1): 30 => 30
5816 04:47:55.832995 DramcWriteLeveling(PI) end<-----
5817 04:47:55.833099
5818 04:47:55.833197 ==
5819 04:47:55.836193 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 04:47:55.839479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 04:47:55.842950 ==
5822 04:47:55.843060 [Gating] SW mode calibration
5823 04:47:55.853261 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5824 04:47:55.856170 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5825 04:47:55.859275 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 04:47:55.866210 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 04:47:55.869425 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 04:47:55.873207 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 04:47:55.879228 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 04:47:55.882743 0 14 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5831 04:47:55.885688 0 14 24 | B1->B0 | 2d2d 3333 | 0 1 | (1 0) (1 1)
5832 04:47:55.892477 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5833 04:47:55.895903 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 04:47:55.898900 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 04:47:55.906116 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 04:47:55.909489 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 04:47:55.912363 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 04:47:55.919304 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 04:47:55.922783 0 15 24 | B1->B0 | 3333 2a2a | 0 0 | (0 0) (1 1)
5840 04:47:55.925448 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5841 04:47:55.932423 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 04:47:55.935289 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 04:47:55.938537 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 04:47:55.945446 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 04:47:55.948668 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 04:47:55.952119 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 04:47:55.958911 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 04:47:55.962444 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5849 04:47:55.965226 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 04:47:55.972342 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 04:47:55.975368 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 04:47:55.978505 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 04:47:55.985567 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 04:47:55.988606 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 04:47:55.991745 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 04:47:55.998419 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 04:47:56.002242 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 04:47:56.005383 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 04:47:56.012121 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 04:47:56.015352 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 04:47:56.018330 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 04:47:56.021728 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 04:47:56.028514 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5864 04:47:56.031866 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5865 04:47:56.035093 Total UI for P1: 0, mck2ui 16
5866 04:47:56.038548 best dqsien dly found for B1: ( 1, 2, 24)
5867 04:47:56.042057 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 04:47:56.045440 Total UI for P1: 0, mck2ui 16
5869 04:47:56.048899 best dqsien dly found for B0: ( 1, 2, 26)
5870 04:47:56.052239 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5871 04:47:56.055513 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5872 04:47:56.055623
5873 04:47:56.062096 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5874 04:47:56.065479 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5875 04:47:56.068876 [Gating] SW calibration Done
5876 04:47:56.068967 ==
5877 04:47:56.072204 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 04:47:56.075611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 04:47:56.075716 ==
5880 04:47:56.075817 RX Vref Scan: 0
5881 04:47:56.075883
5882 04:47:56.078530 RX Vref 0 -> 0, step: 1
5883 04:47:56.078653
5884 04:47:56.081727 RX Delay -80 -> 252, step: 8
5885 04:47:56.085532 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5886 04:47:56.088756 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5887 04:47:56.092111 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5888 04:47:56.098592 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5889 04:47:56.101845 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5890 04:47:56.105029 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5891 04:47:56.108238 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5892 04:47:56.111939 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5893 04:47:56.115034 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5894 04:47:56.121580 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5895 04:47:56.125313 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5896 04:47:56.128630 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5897 04:47:56.131621 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5898 04:47:56.135356 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5899 04:47:56.138711 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5900 04:47:56.144786 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5901 04:47:56.144867 ==
5902 04:47:56.148783 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 04:47:56.151422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 04:47:56.151503 ==
5905 04:47:56.151568 DQS Delay:
5906 04:47:56.154812 DQS0 = 0, DQS1 = 0
5907 04:47:56.154894 DQM Delay:
5908 04:47:56.158500 DQM0 = 102, DQM1 = 98
5909 04:47:56.158583 DQ Delay:
5910 04:47:56.161836 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =95
5911 04:47:56.164933 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5912 04:47:56.168236 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5913 04:47:56.171558 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5914 04:47:56.171638
5915 04:47:56.171702
5916 04:47:56.171760 ==
5917 04:47:56.174931 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 04:47:56.181805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 04:47:56.181886 ==
5920 04:47:56.181951
5921 04:47:56.182010
5922 04:47:56.182066 TX Vref Scan disable
5923 04:47:56.185125 == TX Byte 0 ==
5924 04:47:56.188487 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5925 04:47:56.195301 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5926 04:47:56.195382 == TX Byte 1 ==
5927 04:47:56.198468 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5928 04:47:56.201715 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5929 04:47:56.204991 ==
5930 04:47:56.208532 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 04:47:56.211867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 04:47:56.211948 ==
5933 04:47:56.212012
5934 04:47:56.212071
5935 04:47:56.215089 TX Vref Scan disable
5936 04:47:56.215170 == TX Byte 0 ==
5937 04:47:56.221857 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5938 04:47:56.225296 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5939 04:47:56.225376 == TX Byte 1 ==
5940 04:47:56.231416 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5941 04:47:56.234755 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5942 04:47:56.234901
5943 04:47:56.234967 [DATLAT]
5944 04:47:56.238614 Freq=933, CH1 RK1
5945 04:47:56.238695
5946 04:47:56.238758 DATLAT Default: 0xb
5947 04:47:56.241518 0, 0xFFFF, sum = 0
5948 04:47:56.241602 1, 0xFFFF, sum = 0
5949 04:47:56.245012 2, 0xFFFF, sum = 0
5950 04:47:56.245094 3, 0xFFFF, sum = 0
5951 04:47:56.248166 4, 0xFFFF, sum = 0
5952 04:47:56.248267 5, 0xFFFF, sum = 0
5953 04:47:56.251809 6, 0xFFFF, sum = 0
5954 04:47:56.254721 7, 0xFFFF, sum = 0
5955 04:47:56.254803 8, 0xFFFF, sum = 0
5956 04:47:56.257915 9, 0xFFFF, sum = 0
5957 04:47:56.257997 10, 0x0, sum = 1
5958 04:47:56.261231 11, 0x0, sum = 2
5959 04:47:56.261313 12, 0x0, sum = 3
5960 04:47:56.261378 13, 0x0, sum = 4
5961 04:47:56.264435 best_step = 11
5962 04:47:56.264515
5963 04:47:56.264578 ==
5964 04:47:56.268167 Dram Type= 6, Freq= 0, CH_1, rank 1
5965 04:47:56.271542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5966 04:47:56.271623 ==
5967 04:47:56.274873 RX Vref Scan: 0
5968 04:47:56.274953
5969 04:47:56.277601 RX Vref 0 -> 0, step: 1
5970 04:47:56.277681
5971 04:47:56.277745 RX Delay -45 -> 252, step: 4
5972 04:47:56.285784 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5973 04:47:56.289125 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5974 04:47:56.292508 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5975 04:47:56.295598 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5976 04:47:56.298786 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5977 04:47:56.305729 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5978 04:47:56.308897 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5979 04:47:56.312132 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5980 04:47:56.315428 iDelay=203, Bit 8, Center 90 (11 ~ 170) 160
5981 04:47:56.318802 iDelay=203, Bit 9, Center 92 (11 ~ 174) 164
5982 04:47:56.325634 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5983 04:47:56.328821 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5984 04:47:56.332066 iDelay=203, Bit 12, Center 108 (23 ~ 194) 172
5985 04:47:56.335574 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5986 04:47:56.338628 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5987 04:47:56.345368 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5988 04:47:56.345450 ==
5989 04:47:56.348795 Dram Type= 6, Freq= 0, CH_1, rank 1
5990 04:47:56.352130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5991 04:47:56.352237 ==
5992 04:47:56.352359 DQS Delay:
5993 04:47:56.354998 DQS0 = 0, DQS1 = 0
5994 04:47:56.355079 DQM Delay:
5995 04:47:56.358738 DQM0 = 105, DQM1 = 101
5996 04:47:56.358818 DQ Delay:
5997 04:47:56.361659 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5998 04:47:56.365303 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5999 04:47:56.368574 DQ8 =90, DQ9 =92, DQ10 =102, DQ11 =94
6000 04:47:56.371849 DQ12 =108, DQ13 =108, DQ14 =104, DQ15 =110
6001 04:47:56.371929
6002 04:47:56.371992
6003 04:47:56.381834 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d00, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 407 ps
6004 04:47:56.385330 CH1 RK1: MR19=505, MR18=2D00
6005 04:47:56.388667 CH1_RK1: MR19=0x505, MR18=0x2D00, DQSOSC=407, MR23=63, INC=65, DEC=43
6006 04:47:56.392010 [RxdqsGatingPostProcess] freq 933
6007 04:47:56.398304 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6008 04:47:56.402178 best DQS0 dly(2T, 0.5T) = (0, 10)
6009 04:47:56.405021 best DQS1 dly(2T, 0.5T) = (0, 10)
6010 04:47:56.408482 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6011 04:47:56.411540 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6012 04:47:56.415331 best DQS0 dly(2T, 0.5T) = (0, 10)
6013 04:47:56.418451 best DQS1 dly(2T, 0.5T) = (0, 10)
6014 04:47:56.421645 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6015 04:47:56.424990 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6016 04:47:56.428444 Pre-setting of DQS Precalculation
6017 04:47:56.431980 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6018 04:47:56.438767 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6019 04:47:56.444935 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6020 04:47:56.445047
6021 04:47:56.445142
6022 04:47:56.448028 [Calibration Summary] 1866 Mbps
6023 04:47:56.451771 CH 0, Rank 0
6024 04:47:56.451892 SW Impedance : PASS
6025 04:47:56.455122 DUTY Scan : NO K
6026 04:47:56.458580 ZQ Calibration : PASS
6027 04:47:56.458678 Jitter Meter : NO K
6028 04:47:56.462034 CBT Training : PASS
6029 04:47:56.464832 Write leveling : PASS
6030 04:47:56.464936 RX DQS gating : PASS
6031 04:47:56.468857 RX DQ/DQS(RDDQC) : PASS
6032 04:47:56.468957 TX DQ/DQS : PASS
6033 04:47:56.471534 RX DATLAT : PASS
6034 04:47:56.474957 RX DQ/DQS(Engine): PASS
6035 04:47:56.475058 TX OE : NO K
6036 04:47:56.478354 All Pass.
6037 04:47:56.478452
6038 04:47:56.478540 CH 0, Rank 1
6039 04:47:56.481706 SW Impedance : PASS
6040 04:47:56.481806 DUTY Scan : NO K
6041 04:47:56.485318 ZQ Calibration : PASS
6042 04:47:56.488333 Jitter Meter : NO K
6043 04:47:56.488415 CBT Training : PASS
6044 04:47:56.491804 Write leveling : PASS
6045 04:47:56.494882 RX DQS gating : PASS
6046 04:47:56.494983 RX DQ/DQS(RDDQC) : PASS
6047 04:47:56.498628 TX DQ/DQS : PASS
6048 04:47:56.501559 RX DATLAT : PASS
6049 04:47:56.501659 RX DQ/DQS(Engine): PASS
6050 04:47:56.504905 TX OE : NO K
6051 04:47:56.504979 All Pass.
6052 04:47:56.505044
6053 04:47:56.508779 CH 1, Rank 0
6054 04:47:56.508878 SW Impedance : PASS
6055 04:47:56.511627 DUTY Scan : NO K
6056 04:47:56.511729 ZQ Calibration : PASS
6057 04:47:56.515266 Jitter Meter : NO K
6058 04:47:56.518340 CBT Training : PASS
6059 04:47:56.518421 Write leveling : PASS
6060 04:47:56.521531 RX DQS gating : PASS
6061 04:47:56.524732 RX DQ/DQS(RDDQC) : PASS
6062 04:47:56.524813 TX DQ/DQS : PASS
6063 04:47:56.528601 RX DATLAT : PASS
6064 04:47:56.531435 RX DQ/DQS(Engine): PASS
6065 04:47:56.531516 TX OE : NO K
6066 04:47:56.534600 All Pass.
6067 04:47:56.534700
6068 04:47:56.534789 CH 1, Rank 1
6069 04:47:56.538026 SW Impedance : PASS
6070 04:47:56.538108 DUTY Scan : NO K
6071 04:47:56.541393 ZQ Calibration : PASS
6072 04:47:56.544901 Jitter Meter : NO K
6073 04:47:56.544982 CBT Training : PASS
6074 04:47:56.548146 Write leveling : PASS
6075 04:47:56.551631 RX DQS gating : PASS
6076 04:47:56.551712 RX DQ/DQS(RDDQC) : PASS
6077 04:47:56.554967 TX DQ/DQS : PASS
6078 04:47:56.558186 RX DATLAT : PASS
6079 04:47:56.558267 RX DQ/DQS(Engine): PASS
6080 04:47:56.561367 TX OE : NO K
6081 04:47:56.561449 All Pass.
6082 04:47:56.561513
6083 04:47:56.564567 DramC Write-DBI off
6084 04:47:56.568017 PER_BANK_REFRESH: Hybrid Mode
6085 04:47:56.568097 TX_TRACKING: ON
6086 04:47:56.578307 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6087 04:47:56.581805 [FAST_K] Save calibration result to emmc
6088 04:47:56.584557 dramc_set_vcore_voltage set vcore to 650000
6089 04:47:56.587904 Read voltage for 400, 6
6090 04:47:56.588010 Vio18 = 0
6091 04:47:56.588103 Vcore = 650000
6092 04:47:56.591198 Vdram = 0
6093 04:47:56.591278 Vddq = 0
6094 04:47:56.591342 Vmddr = 0
6095 04:47:56.597912 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6096 04:47:56.601448 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6097 04:47:56.604765 MEM_TYPE=3, freq_sel=20
6098 04:47:56.608003 sv_algorithm_assistance_LP4_800
6099 04:47:56.611526 ============ PULL DRAM RESETB DOWN ============
6100 04:47:56.614681 ========== PULL DRAM RESETB DOWN end =========
6101 04:47:56.621524 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6102 04:47:56.624380 ===================================
6103 04:47:56.624477 LPDDR4 DRAM CONFIGURATION
6104 04:47:56.627761 ===================================
6105 04:47:56.631475 EX_ROW_EN[0] = 0x0
6106 04:47:56.634450 EX_ROW_EN[1] = 0x0
6107 04:47:56.634549 LP4Y_EN = 0x0
6108 04:47:56.638280 WORK_FSP = 0x0
6109 04:47:56.638382 WL = 0x2
6110 04:47:56.641400 RL = 0x2
6111 04:47:56.641503 BL = 0x2
6112 04:47:56.644473 RPST = 0x0
6113 04:47:56.644569 RD_PRE = 0x0
6114 04:47:56.648016 WR_PRE = 0x1
6115 04:47:56.648119 WR_PST = 0x0
6116 04:47:56.650962 DBI_WR = 0x0
6117 04:47:56.651064 DBI_RD = 0x0
6118 04:47:56.654295 OTF = 0x1
6119 04:47:56.657662 ===================================
6120 04:47:56.661356 ===================================
6121 04:47:56.661437 ANA top config
6122 04:47:56.664596 ===================================
6123 04:47:56.667796 DLL_ASYNC_EN = 0
6124 04:47:56.670898 ALL_SLAVE_EN = 1
6125 04:47:56.671015 NEW_RANK_MODE = 1
6126 04:47:56.674461 DLL_IDLE_MODE = 1
6127 04:47:56.677603 LP45_APHY_COMB_EN = 1
6128 04:47:56.681106 TX_ODT_DIS = 1
6129 04:47:56.684409 NEW_8X_MODE = 1
6130 04:47:56.687728 ===================================
6131 04:47:56.691229 ===================================
6132 04:47:56.691383 data_rate = 800
6133 04:47:56.694591 CKR = 1
6134 04:47:56.697379 DQ_P2S_RATIO = 4
6135 04:47:56.700650 ===================================
6136 04:47:56.704019 CA_P2S_RATIO = 4
6137 04:47:56.707408 DQ_CA_OPEN = 0
6138 04:47:56.710682 DQ_SEMI_OPEN = 1
6139 04:47:56.710790 CA_SEMI_OPEN = 1
6140 04:47:56.714599 CA_FULL_RATE = 0
6141 04:47:56.717373 DQ_CKDIV4_EN = 0
6142 04:47:56.720680 CA_CKDIV4_EN = 1
6143 04:47:56.724030 CA_PREDIV_EN = 0
6144 04:47:56.727342 PH8_DLY = 0
6145 04:47:56.727449 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6146 04:47:56.730691 DQ_AAMCK_DIV = 0
6147 04:47:56.733954 CA_AAMCK_DIV = 0
6148 04:47:56.737353 CA_ADMCK_DIV = 4
6149 04:47:56.741185 DQ_TRACK_CA_EN = 0
6150 04:47:56.743774 CA_PICK = 800
6151 04:47:56.743899 CA_MCKIO = 400
6152 04:47:56.747102 MCKIO_SEMI = 400
6153 04:47:56.750437 PLL_FREQ = 3016
6154 04:47:56.753789 DQ_UI_PI_RATIO = 32
6155 04:47:56.757699 CA_UI_PI_RATIO = 32
6156 04:47:56.760877 ===================================
6157 04:47:56.763944 ===================================
6158 04:47:56.767044 memory_type:LPDDR4
6159 04:47:56.767159 GP_NUM : 10
6160 04:47:56.770580 SRAM_EN : 1
6161 04:47:56.774083 MD32_EN : 0
6162 04:47:56.777206 ===================================
6163 04:47:56.777322 [ANA_INIT] >>>>>>>>>>>>>>
6164 04:47:56.780586 <<<<<< [CONFIGURE PHASE]: ANA_TX
6165 04:47:56.783702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6166 04:47:56.787227 ===================================
6167 04:47:56.790466 data_rate = 800,PCW = 0X7400
6168 04:47:56.793932 ===================================
6169 04:47:56.797351 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6170 04:47:56.803612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6171 04:47:56.813818 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6172 04:47:56.820699 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6173 04:47:56.823417 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6174 04:47:56.826707 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6175 04:47:56.826813 [ANA_INIT] flow start
6176 04:47:56.830071 [ANA_INIT] PLL >>>>>>>>
6177 04:47:56.833397 [ANA_INIT] PLL <<<<<<<<
6178 04:47:56.833514 [ANA_INIT] MIDPI >>>>>>>>
6179 04:47:56.836788 [ANA_INIT] MIDPI <<<<<<<<
6180 04:47:56.840064 [ANA_INIT] DLL >>>>>>>>
6181 04:47:56.840173 [ANA_INIT] flow end
6182 04:47:56.846668 ============ LP4 DIFF to SE enter ============
6183 04:47:56.849959 ============ LP4 DIFF to SE exit ============
6184 04:47:56.850070 [ANA_INIT] <<<<<<<<<<<<<
6185 04:47:56.853339 [Flow] Enable top DCM control >>>>>
6186 04:47:56.856592 [Flow] Enable top DCM control <<<<<
6187 04:47:56.860028 Enable DLL master slave shuffle
6188 04:47:56.866667 ==============================================================
6189 04:47:56.870015 Gating Mode config
6190 04:47:56.873351 ==============================================================
6191 04:47:56.876681 Config description:
6192 04:47:56.886726 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6193 04:47:56.893557 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6194 04:47:56.896741 SELPH_MODE 0: By rank 1: By Phase
6195 04:47:56.902942 ==============================================================
6196 04:47:56.906546 GAT_TRACK_EN = 0
6197 04:47:56.909934 RX_GATING_MODE = 2
6198 04:47:56.910017 RX_GATING_TRACK_MODE = 2
6199 04:47:56.913316 SELPH_MODE = 1
6200 04:47:56.918161 PICG_EARLY_EN = 1
6201 04:47:56.919960 VALID_LAT_VALUE = 1
6202 04:47:56.926647 ==============================================================
6203 04:47:56.929625 Enter into Gating configuration >>>>
6204 04:47:56.933042 Exit from Gating configuration <<<<
6205 04:47:56.936382 Enter into DVFS_PRE_config >>>>>
6206 04:47:56.946288 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6207 04:47:56.949722 Exit from DVFS_PRE_config <<<<<
6208 04:47:56.953025 Enter into PICG configuration >>>>
6209 04:47:56.956312 Exit from PICG configuration <<<<
6210 04:47:56.959648 [RX_INPUT] configuration >>>>>
6211 04:47:56.997990 [RX_INPUT] configuration <<<<<
6212 04:47:56.998157 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6213 04:47:56.998288 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6214 04:47:56.998408 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6215 04:47:56.998526 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6216 04:47:56.998641 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6217 04:47:56.998755 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6218 04:47:56.999385 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6219 04:47:57.006234 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6220 04:47:57.009369 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6221 04:47:57.012896 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6222 04:47:57.016257 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6223 04:47:57.022668 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6224 04:47:57.025925 ===================================
6225 04:47:57.029318 LPDDR4 DRAM CONFIGURATION
6226 04:47:57.032742 ===================================
6227 04:47:57.032827 EX_ROW_EN[0] = 0x0
6228 04:47:57.036219 EX_ROW_EN[1] = 0x0
6229 04:47:57.036334 LP4Y_EN = 0x0
6230 04:47:57.039477 WORK_FSP = 0x0
6231 04:47:57.039561 WL = 0x2
6232 04:47:57.042363 RL = 0x2
6233 04:47:57.042446 BL = 0x2
6234 04:47:57.045925 RPST = 0x0
6235 04:47:57.046007 RD_PRE = 0x0
6236 04:47:57.049166 WR_PRE = 0x1
6237 04:47:57.049248 WR_PST = 0x0
6238 04:47:57.052427 DBI_WR = 0x0
6239 04:47:57.052536 DBI_RD = 0x0
6240 04:47:57.055573 OTF = 0x1
6241 04:47:57.059277 ===================================
6242 04:47:57.062446 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6243 04:47:57.065923 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6244 04:47:57.072185 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6245 04:47:57.075802 ===================================
6246 04:47:57.075876 LPDDR4 DRAM CONFIGURATION
6247 04:47:57.078801 ===================================
6248 04:47:57.082269 EX_ROW_EN[0] = 0x10
6249 04:47:57.085767 EX_ROW_EN[1] = 0x0
6250 04:47:57.085868 LP4Y_EN = 0x0
6251 04:47:57.089054 WORK_FSP = 0x0
6252 04:47:57.089133 WL = 0x2
6253 04:47:57.092252 RL = 0x2
6254 04:47:57.092428 BL = 0x2
6255 04:47:57.095657 RPST = 0x0
6256 04:47:57.095770 RD_PRE = 0x0
6257 04:47:57.099175 WR_PRE = 0x1
6258 04:47:57.099259 WR_PST = 0x0
6259 04:47:57.102537 DBI_WR = 0x0
6260 04:47:57.102671 DBI_RD = 0x0
6261 04:47:57.105889 OTF = 0x1
6262 04:47:57.109277 ===================================
6263 04:47:57.115877 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6264 04:47:57.119290 nWR fixed to 30
6265 04:47:57.119376 [ModeRegInit_LP4] CH0 RK0
6266 04:47:57.122631 [ModeRegInit_LP4] CH0 RK1
6267 04:47:57.125927 [ModeRegInit_LP4] CH1 RK0
6268 04:47:57.129174 [ModeRegInit_LP4] CH1 RK1
6269 04:47:57.129257 match AC timing 19
6270 04:47:57.135663 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6271 04:47:57.139067 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6272 04:47:57.142407 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6273 04:47:57.149168 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6274 04:47:57.152564 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6275 04:47:57.152648 ==
6276 04:47:57.155858 Dram Type= 6, Freq= 0, CH_0, rank 0
6277 04:47:57.159232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 04:47:57.159314 ==
6279 04:47:57.165571 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6280 04:47:57.172315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6281 04:47:57.175358 [CA 0] Center 36 (8~64) winsize 57
6282 04:47:57.175440 [CA 1] Center 36 (8~64) winsize 57
6283 04:47:57.178558 [CA 2] Center 36 (8~64) winsize 57
6284 04:47:57.182184 [CA 3] Center 36 (8~64) winsize 57
6285 04:47:57.185636 [CA 4] Center 36 (8~64) winsize 57
6286 04:47:57.212923 [CA 5] Center 36 (8~64) winsize 57
6287 04:47:57.213017
6288 04:47:57.213082 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6289 04:47:57.213143
6290 04:47:57.213201 [CATrainingPosCal] consider 1 rank data
6291 04:47:57.213257 u2DelayCellTimex100 = 270/100 ps
6292 04:47:57.213313 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 04:47:57.213368 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 04:47:57.213441 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 04:47:57.215123 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 04:47:57.218312 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 04:47:57.221610 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 04:47:57.221689
6299 04:47:57.224918 CA PerBit enable=1, Macro0, CA PI delay=36
6300 04:47:57.224997
6301 04:47:57.228230 [CBTSetCACLKResult] CA Dly = 36
6302 04:47:57.231649 CS Dly: 1 (0~32)
6303 04:47:57.231728 ==
6304 04:47:57.234884 Dram Type= 6, Freq= 0, CH_0, rank 1
6305 04:47:57.238704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 04:47:57.238785 ==
6307 04:47:57.245366 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6308 04:47:57.248679 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6309 04:47:57.252007 [CA 0] Center 36 (8~64) winsize 57
6310 04:47:57.255424 [CA 1] Center 36 (8~64) winsize 57
6311 04:47:57.258066 [CA 2] Center 36 (8~64) winsize 57
6312 04:47:57.261418 [CA 3] Center 36 (8~64) winsize 57
6313 04:47:57.265195 [CA 4] Center 36 (8~64) winsize 57
6314 04:47:57.268083 [CA 5] Center 36 (8~64) winsize 57
6315 04:47:57.268161
6316 04:47:57.271331 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6317 04:47:57.271411
6318 04:47:57.274764 [CATrainingPosCal] consider 2 rank data
6319 04:47:57.278096 u2DelayCellTimex100 = 270/100 ps
6320 04:47:57.281385 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 04:47:57.284788 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 04:47:57.288032 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 04:47:57.294699 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 04:47:57.298046 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 04:47:57.301261 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 04:47:57.301341
6327 04:47:57.304578 CA PerBit enable=1, Macro0, CA PI delay=36
6328 04:47:57.304658
6329 04:47:57.307733 [CBTSetCACLKResult] CA Dly = 36
6330 04:47:57.307813 CS Dly: 1 (0~32)
6331 04:47:57.307877
6332 04:47:57.311721 ----->DramcWriteLeveling(PI) begin...
6333 04:47:57.311805 ==
6334 04:47:57.314767 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 04:47:57.321183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 04:47:57.321265 ==
6337 04:47:57.324591 Write leveling (Byte 0): 40 => 8
6338 04:47:57.324676 Write leveling (Byte 1): 40 => 8
6339 04:47:57.328124 DramcWriteLeveling(PI) end<-----
6340 04:47:57.328236
6341 04:47:57.331423 ==
6342 04:47:57.331528 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 04:47:57.337892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 04:47:57.338004 ==
6345 04:47:57.341201 [Gating] SW mode calibration
6346 04:47:57.348015 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6347 04:47:57.350944 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6348 04:47:57.358436 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6349 04:47:57.361315 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6350 04:47:57.364626 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6351 04:47:57.371349 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 04:47:57.374282 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 04:47:57.377842 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 04:47:57.384449 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 04:47:57.387761 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 04:47:57.391218 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6357 04:47:57.394383 Total UI for P1: 0, mck2ui 16
6358 04:47:57.397620 best dqsien dly found for B0: ( 0, 14, 24)
6359 04:47:57.401016 Total UI for P1: 0, mck2ui 16
6360 04:47:57.404448 best dqsien dly found for B1: ( 0, 14, 24)
6361 04:47:57.407825 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6362 04:47:57.411098 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6363 04:47:57.411203
6364 04:47:57.414369 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6365 04:47:57.421070 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6366 04:47:57.421175 [Gating] SW calibration Done
6367 04:47:57.421268 ==
6368 04:47:57.424409 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 04:47:57.431353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 04:47:57.431462 ==
6371 04:47:57.431553 RX Vref Scan: 0
6372 04:47:57.431645
6373 04:47:57.434734 RX Vref 0 -> 0, step: 1
6374 04:47:57.434840
6375 04:47:57.437445 RX Delay -410 -> 252, step: 16
6376 04:47:57.441360 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6377 04:47:57.444522 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6378 04:47:57.450749 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6379 04:47:57.454331 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6380 04:47:57.457865 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6381 04:47:57.461050 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6382 04:47:57.467850 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6383 04:47:57.471094 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6384 04:47:57.474507 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6385 04:47:57.477496 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6386 04:47:57.484198 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6387 04:47:57.487716 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6388 04:47:57.490818 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6389 04:47:57.494066 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6390 04:47:57.500685 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6391 04:47:57.503945 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6392 04:47:57.504051 ==
6393 04:47:57.507330 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 04:47:57.510643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 04:47:57.510750 ==
6396 04:47:57.514345 DQS Delay:
6397 04:47:57.514451 DQS0 = 27, DQS1 = 35
6398 04:47:57.517716 DQM Delay:
6399 04:47:57.517818 DQM0 = 11, DQM1 = 12
6400 04:47:57.517907 DQ Delay:
6401 04:47:57.521014 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6402 04:47:57.523696 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6403 04:47:57.527550 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6404 04:47:57.530894 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6405 04:47:57.531000
6406 04:47:57.531087
6407 04:47:57.531173 ==
6408 04:47:57.534177 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 04:47:57.540797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 04:47:57.540912 ==
6411 04:47:57.541004
6412 04:47:57.541092
6413 04:47:57.541180 TX Vref Scan disable
6414 04:47:57.544069 == TX Byte 0 ==
6415 04:47:57.547370 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 04:47:57.550508 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 04:47:57.553672 == TX Byte 1 ==
6418 04:47:57.557080 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 04:47:57.560542 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 04:47:57.560647 ==
6421 04:47:57.563741 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 04:47:57.570860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 04:47:57.570972 ==
6424 04:47:57.571061
6425 04:47:57.571145
6426 04:47:57.571233 TX Vref Scan disable
6427 04:47:57.574017 == TX Byte 0 ==
6428 04:47:57.577309 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6429 04:47:57.580675 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6430 04:47:57.583842 == TX Byte 1 ==
6431 04:47:57.587282 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6432 04:47:57.590428 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6433 04:47:57.590512
6434 04:47:57.593795 [DATLAT]
6435 04:47:57.593874 Freq=400, CH0 RK0
6436 04:47:57.593938
6437 04:47:57.597443 DATLAT Default: 0xf
6438 04:47:57.597523 0, 0xFFFF, sum = 0
6439 04:47:57.600457 1, 0xFFFF, sum = 0
6440 04:47:57.600537 2, 0xFFFF, sum = 0
6441 04:47:57.603926 3, 0xFFFF, sum = 0
6442 04:47:57.604006 4, 0xFFFF, sum = 0
6443 04:47:57.607526 5, 0xFFFF, sum = 0
6444 04:47:57.607610 6, 0xFFFF, sum = 0
6445 04:47:57.610388 7, 0xFFFF, sum = 0
6446 04:47:57.610469 8, 0xFFFF, sum = 0
6447 04:47:57.613902 9, 0xFFFF, sum = 0
6448 04:47:57.613982 10, 0xFFFF, sum = 0
6449 04:47:57.617345 11, 0xFFFF, sum = 0
6450 04:47:57.617426 12, 0xFFFF, sum = 0
6451 04:47:57.620480 13, 0x0, sum = 1
6452 04:47:57.620590 14, 0x0, sum = 2
6453 04:47:57.624000 15, 0x0, sum = 3
6454 04:47:57.624112 16, 0x0, sum = 4
6455 04:47:57.627178 best_step = 14
6456 04:47:57.627282
6457 04:47:57.627374 ==
6458 04:47:57.630579 Dram Type= 6, Freq= 0, CH_0, rank 0
6459 04:47:57.633947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 04:47:57.634056 ==
6461 04:47:57.637075 RX Vref Scan: 1
6462 04:47:57.637227
6463 04:47:57.637329 RX Vref 0 -> 0, step: 1
6464 04:47:57.637416
6465 04:47:57.640497 RX Delay -311 -> 252, step: 8
6466 04:47:57.640646
6467 04:47:57.643792 Set Vref, RX VrefLevel [Byte0]: 57
6468 04:47:57.647165 [Byte1]: 48
6469 04:47:57.651718
6470 04:47:57.651825 Final RX Vref Byte 0 = 57 to rank0
6471 04:47:57.655184 Final RX Vref Byte 1 = 48 to rank0
6472 04:47:57.658374 Final RX Vref Byte 0 = 57 to rank1
6473 04:47:57.661749 Final RX Vref Byte 1 = 48 to rank1==
6474 04:47:57.665058 Dram Type= 6, Freq= 0, CH_0, rank 0
6475 04:47:57.671550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 04:47:57.671734 ==
6477 04:47:57.671862 DQS Delay:
6478 04:47:57.674748 DQS0 = 24, DQS1 = 32
6479 04:47:57.674853 DQM Delay:
6480 04:47:57.674944 DQM0 = 7, DQM1 = 9
6481 04:47:57.678588 DQ Delay:
6482 04:47:57.678693 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6483 04:47:57.682027 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6484 04:47:57.685445 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6485 04:47:57.688736 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6486 04:47:57.688844
6487 04:47:57.688933
6488 04:47:57.698400 [DQSOSCAuto] RK0, (LSB)MR18= 0xcfbc, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6489 04:47:57.701728 CH0 RK0: MR19=C0C, MR18=CFBC
6490 04:47:57.704973 CH0_RK0: MR19=0xC0C, MR18=0xCFBC, DQSOSC=384, MR23=63, INC=400, DEC=267
6491 04:47:57.708704 ==
6492 04:47:57.712001 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 04:47:57.714751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 04:47:57.714859 ==
6495 04:47:57.718122 [Gating] SW mode calibration
6496 04:47:57.724760 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6497 04:47:57.728013 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6498 04:47:57.734785 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6499 04:47:57.738642 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6500 04:47:57.741620 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6501 04:47:57.748066 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 04:47:57.751326 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 04:47:57.754639 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 04:47:57.761782 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 04:47:57.764517 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 04:47:57.767749 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 04:47:57.771094 Total UI for P1: 0, mck2ui 16
6508 04:47:57.774436 best dqsien dly found for B0: ( 0, 14, 24)
6509 04:47:57.777624 Total UI for P1: 0, mck2ui 16
6510 04:47:57.780953 best dqsien dly found for B1: ( 0, 14, 24)
6511 04:47:57.784823 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6512 04:47:57.788130 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6513 04:47:57.788238
6514 04:47:57.794826 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6515 04:47:57.797877 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6516 04:47:57.801178 [Gating] SW calibration Done
6517 04:47:57.801288 ==
6518 04:47:57.804684 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 04:47:57.807962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 04:47:57.808074 ==
6521 04:47:57.808170 RX Vref Scan: 0
6522 04:47:57.808262
6523 04:47:57.811280 RX Vref 0 -> 0, step: 1
6524 04:47:57.811389
6525 04:47:57.814337 RX Delay -410 -> 252, step: 16
6526 04:47:57.817642 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6527 04:47:57.824333 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6528 04:47:57.827716 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6529 04:47:57.830881 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6530 04:47:57.834269 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6531 04:47:57.840808 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6532 04:47:57.844229 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6533 04:47:57.847392 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6534 04:47:57.850747 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6535 04:47:57.854030 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6536 04:47:57.860771 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6537 04:47:57.864138 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6538 04:47:57.867929 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6539 04:47:57.874249 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6540 04:47:57.877145 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6541 04:47:57.880622 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6542 04:47:57.880731 ==
6543 04:47:57.883676 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 04:47:57.887008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 04:47:57.890371 ==
6546 04:47:57.890479 DQS Delay:
6547 04:47:57.890572 DQS0 = 27, DQS1 = 35
6548 04:47:57.894048 DQM Delay:
6549 04:47:57.894156 DQM0 = 12, DQM1 = 12
6550 04:47:57.897313 DQ Delay:
6551 04:47:57.897415 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6552 04:47:57.900587 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6553 04:47:57.903676 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6554 04:47:57.906933 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6555 04:47:57.907039
6556 04:47:57.907132
6557 04:47:57.907222 ==
6558 04:47:57.910316 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 04:47:57.916948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 04:47:57.917059 ==
6561 04:47:57.917153
6562 04:47:57.917243
6563 04:47:57.917332 TX Vref Scan disable
6564 04:47:57.920519 == TX Byte 0 ==
6565 04:47:57.923793 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6566 04:47:57.927037 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6567 04:47:57.930477 == TX Byte 1 ==
6568 04:47:57.933770 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6569 04:47:57.937082 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6570 04:47:57.937208 ==
6571 04:47:57.940406 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 04:47:57.947265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 04:47:57.947377 ==
6574 04:47:57.947472
6575 04:47:57.947562
6576 04:47:57.947651 TX Vref Scan disable
6577 04:47:57.950501 == TX Byte 0 ==
6578 04:47:57.953716 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6579 04:47:57.956996 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6580 04:47:57.960413 == TX Byte 1 ==
6581 04:47:57.963712 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6582 04:47:57.966986 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6583 04:47:57.967090
6584 04:47:57.970499 [DATLAT]
6585 04:47:57.970600 Freq=400, CH0 RK1
6586 04:47:57.970689
6587 04:47:57.973658 DATLAT Default: 0xe
6588 04:47:57.973762 0, 0xFFFF, sum = 0
6589 04:47:57.977402 1, 0xFFFF, sum = 0
6590 04:47:57.977509 2, 0xFFFF, sum = 0
6591 04:47:57.980708 3, 0xFFFF, sum = 0
6592 04:47:57.980813 4, 0xFFFF, sum = 0
6593 04:47:57.983995 5, 0xFFFF, sum = 0
6594 04:47:57.984101 6, 0xFFFF, sum = 0
6595 04:47:57.987339 7, 0xFFFF, sum = 0
6596 04:47:57.987442 8, 0xFFFF, sum = 0
6597 04:47:57.990359 9, 0xFFFF, sum = 0
6598 04:47:57.993635 10, 0xFFFF, sum = 0
6599 04:47:57.993745 11, 0xFFFF, sum = 0
6600 04:47:57.996767 12, 0xFFFF, sum = 0
6601 04:47:57.996853 13, 0x0, sum = 1
6602 04:47:58.000772 14, 0x0, sum = 2
6603 04:47:58.000884 15, 0x0, sum = 3
6604 04:47:58.000980 16, 0x0, sum = 4
6605 04:47:58.003723 best_step = 14
6606 04:47:58.003828
6607 04:47:58.003919 ==
6608 04:47:58.006886 Dram Type= 6, Freq= 0, CH_0, rank 1
6609 04:47:58.010440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 04:47:58.010549 ==
6611 04:47:58.013644 RX Vref Scan: 0
6612 04:47:58.013748
6613 04:47:58.017014 RX Vref 0 -> 0, step: 1
6614 04:47:58.017122
6615 04:47:58.017214 RX Delay -311 -> 252, step: 8
6616 04:47:58.025146 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6617 04:47:58.028995 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6618 04:47:58.032449 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6619 04:47:58.035883 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6620 04:47:58.042398 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6621 04:47:58.045953 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6622 04:47:58.049056 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6623 04:47:58.052497 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6624 04:47:58.058873 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6625 04:47:58.062158 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6626 04:47:58.065402 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6627 04:47:58.068781 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6628 04:47:58.075257 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6629 04:47:58.079184 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6630 04:47:58.082389 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6631 04:47:58.085374 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6632 04:47:58.089109 ==
6633 04:47:58.092580 Dram Type= 6, Freq= 0, CH_0, rank 1
6634 04:47:58.095627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 04:47:58.095728 ==
6636 04:47:58.095830 DQS Delay:
6637 04:47:58.099055 DQS0 = 24, DQS1 = 32
6638 04:47:58.099153 DQM Delay:
6639 04:47:58.101839 DQM0 = 8, DQM1 = 10
6640 04:47:58.101945 DQ Delay:
6641 04:47:58.105344 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6642 04:47:58.108571 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6643 04:47:58.111831 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6644 04:47:58.115086 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6645 04:47:58.115184
6646 04:47:58.115256
6647 04:47:58.122201 [DQSOSCAuto] RK1, (LSB)MR18= 0xbb5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6648 04:47:58.125316 CH0 RK1: MR19=C0C, MR18=BB5B
6649 04:47:58.131845 CH0_RK1: MR19=0xC0C, MR18=0xBB5B, DQSOSC=386, MR23=63, INC=396, DEC=264
6650 04:47:58.135135 [RxdqsGatingPostProcess] freq 400
6651 04:47:58.138934 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6652 04:47:58.142018 best DQS0 dly(2T, 0.5T) = (0, 10)
6653 04:47:58.145529 best DQS1 dly(2T, 0.5T) = (0, 10)
6654 04:47:58.148549 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6655 04:47:58.151967 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6656 04:47:58.155265 best DQS0 dly(2T, 0.5T) = (0, 10)
6657 04:47:58.158475 best DQS1 dly(2T, 0.5T) = (0, 10)
6658 04:47:58.162064 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6659 04:47:58.165371 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6660 04:47:58.168785 Pre-setting of DQS Precalculation
6661 04:47:58.172051 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6662 04:47:58.172156 ==
6663 04:47:58.175371 Dram Type= 6, Freq= 0, CH_1, rank 0
6664 04:47:58.181902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 04:47:58.182009 ==
6666 04:47:58.185251 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6667 04:47:58.191948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6668 04:47:58.195581 [CA 0] Center 36 (8~64) winsize 57
6669 04:47:58.198691 [CA 1] Center 36 (8~64) winsize 57
6670 04:47:58.202262 [CA 2] Center 36 (8~64) winsize 57
6671 04:47:58.205456 [CA 3] Center 36 (8~64) winsize 57
6672 04:47:58.208719 [CA 4] Center 36 (8~64) winsize 57
6673 04:47:58.212060 [CA 5] Center 36 (8~64) winsize 57
6674 04:47:58.212172
6675 04:47:58.215468 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6676 04:47:58.215572
6677 04:47:58.218715 [CATrainingPosCal] consider 1 rank data
6678 04:47:58.222110 u2DelayCellTimex100 = 270/100 ps
6679 04:47:58.225491 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 04:47:58.228766 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 04:47:58.232106 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 04:47:58.235413 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 04:47:58.238183 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 04:47:58.241410 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 04:47:58.245059
6686 04:47:58.248767 CA PerBit enable=1, Macro0, CA PI delay=36
6687 04:47:58.248869
6688 04:47:58.251814 [CBTSetCACLKResult] CA Dly = 36
6689 04:47:58.251918 CS Dly: 1 (0~32)
6690 04:47:58.252005 ==
6691 04:47:58.254679 Dram Type= 6, Freq= 0, CH_1, rank 1
6692 04:47:58.258514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 04:47:58.258620 ==
6694 04:47:58.265065 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6695 04:47:58.271558 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6696 04:47:58.274808 [CA 0] Center 36 (8~64) winsize 57
6697 04:47:58.277988 [CA 1] Center 36 (8~64) winsize 57
6698 04:47:58.281071 [CA 2] Center 36 (8~64) winsize 57
6699 04:47:58.284568 [CA 3] Center 36 (8~64) winsize 57
6700 04:47:58.287761 [CA 4] Center 36 (8~64) winsize 57
6701 04:47:58.291191 [CA 5] Center 36 (8~64) winsize 57
6702 04:47:58.291297
6703 04:47:58.294508 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6704 04:47:58.294615
6705 04:47:58.297761 [CATrainingPosCal] consider 2 rank data
6706 04:47:58.301060 u2DelayCellTimex100 = 270/100 ps
6707 04:47:58.304442 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 04:47:58.307608 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 04:47:58.310917 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 04:47:58.314434 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 04:47:58.317514 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 04:47:58.320850 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 04:47:58.320957
6714 04:47:58.324150 CA PerBit enable=1, Macro0, CA PI delay=36
6715 04:47:58.327508
6716 04:47:58.327612 [CBTSetCACLKResult] CA Dly = 36
6717 04:47:58.330748 CS Dly: 1 (0~32)
6718 04:47:58.330848
6719 04:47:58.334189 ----->DramcWriteLeveling(PI) begin...
6720 04:47:58.334297 ==
6721 04:47:58.337520 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 04:47:58.340868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 04:47:58.340976 ==
6724 04:47:58.344140 Write leveling (Byte 0): 40 => 8
6725 04:47:58.347439 Write leveling (Byte 1): 40 => 8
6726 04:47:58.350802 DramcWriteLeveling(PI) end<-----
6727 04:47:58.350909
6728 04:47:58.351003 ==
6729 04:47:58.353973 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 04:47:58.357332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 04:47:58.357441 ==
6732 04:47:58.360630 [Gating] SW mode calibration
6733 04:47:58.367661 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6734 04:47:58.373800 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6735 04:47:58.377571 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6736 04:47:58.384512 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6737 04:47:58.387493 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6738 04:47:58.390930 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 04:47:58.397626 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 04:47:58.400597 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 04:47:58.404483 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 04:47:58.407681 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 04:47:58.414064 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6744 04:47:58.417866 Total UI for P1: 0, mck2ui 16
6745 04:47:58.421028 best dqsien dly found for B0: ( 0, 14, 24)
6746 04:47:58.424058 Total UI for P1: 0, mck2ui 16
6747 04:47:58.427775 best dqsien dly found for B1: ( 0, 14, 24)
6748 04:47:58.430840 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6749 04:47:58.434195 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6750 04:47:58.434301
6751 04:47:58.437354 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6752 04:47:58.440670 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6753 04:47:58.444099 [Gating] SW calibration Done
6754 04:47:58.444211 ==
6755 04:47:58.447571 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 04:47:58.450889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 04:47:58.450988 ==
6758 04:47:58.454061 RX Vref Scan: 0
6759 04:47:58.454136
6760 04:47:58.454197 RX Vref 0 -> 0, step: 1
6761 04:47:58.457355
6762 04:47:58.457427 RX Delay -410 -> 252, step: 16
6763 04:47:58.464038 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6764 04:47:58.467320 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6765 04:47:58.470433 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6766 04:47:58.473705 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6767 04:47:58.480300 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6768 04:47:58.484099 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6769 04:47:58.487401 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6770 04:47:58.490690 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6771 04:47:58.497265 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6772 04:47:58.500468 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6773 04:47:58.504157 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6774 04:47:58.507576 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6775 04:47:58.513671 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6776 04:47:58.517215 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6777 04:47:58.520842 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6778 04:47:58.523693 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6779 04:47:58.527194 ==
6780 04:47:58.530489 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 04:47:58.533811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 04:47:58.533909 ==
6783 04:47:58.534000 DQS Delay:
6784 04:47:58.537137 DQS0 = 27, DQS1 = 35
6785 04:47:58.537238 DQM Delay:
6786 04:47:58.540540 DQM0 = 11, DQM1 = 13
6787 04:47:58.540621 DQ Delay:
6788 04:47:58.543725 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6789 04:47:58.547448 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6790 04:47:58.550776 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6791 04:47:58.553433 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6792 04:47:58.553537
6793 04:47:58.553632
6794 04:47:58.553718 ==
6795 04:47:58.556828 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 04:47:58.560100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 04:47:58.560208 ==
6798 04:47:58.560304
6799 04:47:58.560405
6800 04:47:58.563954 TX Vref Scan disable
6801 04:47:58.564053 == TX Byte 0 ==
6802 04:47:58.570683 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 04:47:58.574006 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 04:47:58.574107 == TX Byte 1 ==
6805 04:47:58.580390 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 04:47:58.583679 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 04:47:58.583790 ==
6808 04:47:58.587029 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 04:47:58.590083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 04:47:58.590199 ==
6811 04:47:58.590294
6812 04:47:58.590422
6813 04:47:58.593447 TX Vref Scan disable
6814 04:47:58.593555 == TX Byte 0 ==
6815 04:47:58.600089 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6816 04:47:58.603403 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6817 04:47:58.603504 == TX Byte 1 ==
6818 04:47:58.610361 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6819 04:47:58.613366 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6820 04:47:58.613473
6821 04:47:58.613566 [DATLAT]
6822 04:47:58.616702 Freq=400, CH1 RK0
6823 04:47:58.616804
6824 04:47:58.616897 DATLAT Default: 0xf
6825 04:47:58.620026 0, 0xFFFF, sum = 0
6826 04:47:58.620134 1, 0xFFFF, sum = 0
6827 04:47:58.623735 2, 0xFFFF, sum = 0
6828 04:47:58.623844 3, 0xFFFF, sum = 0
6829 04:47:58.627024 4, 0xFFFF, sum = 0
6830 04:47:58.627133 5, 0xFFFF, sum = 0
6831 04:47:58.630310 6, 0xFFFF, sum = 0
6832 04:47:58.630417 7, 0xFFFF, sum = 0
6833 04:47:58.633674 8, 0xFFFF, sum = 0
6834 04:47:58.633783 9, 0xFFFF, sum = 0
6835 04:47:58.637042 10, 0xFFFF, sum = 0
6836 04:47:58.640229 11, 0xFFFF, sum = 0
6837 04:47:58.640376 12, 0xFFFF, sum = 0
6838 04:47:58.643305 13, 0x0, sum = 1
6839 04:47:58.643410 14, 0x0, sum = 2
6840 04:47:58.643505 15, 0x0, sum = 3
6841 04:47:58.647243 16, 0x0, sum = 4
6842 04:47:58.647352 best_step = 14
6843 04:47:58.647446
6844 04:47:58.649939 ==
6845 04:47:58.650045 Dram Type= 6, Freq= 0, CH_1, rank 0
6846 04:47:58.656839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 04:47:58.656988 ==
6848 04:47:58.657086 RX Vref Scan: 1
6849 04:47:58.657178
6850 04:47:58.660078 RX Vref 0 -> 0, step: 1
6851 04:47:58.660181
6852 04:47:58.663582 RX Delay -311 -> 252, step: 8
6853 04:47:58.663687
6854 04:47:58.666543 Set Vref, RX VrefLevel [Byte0]: 56
6855 04:47:58.669661 [Byte1]: 56
6856 04:47:58.673549
6857 04:47:58.673654 Final RX Vref Byte 0 = 56 to rank0
6858 04:47:58.676817 Final RX Vref Byte 1 = 56 to rank0
6859 04:47:58.680170 Final RX Vref Byte 0 = 56 to rank1
6860 04:47:58.683270 Final RX Vref Byte 1 = 56 to rank1==
6861 04:47:58.686501 Dram Type= 6, Freq= 0, CH_1, rank 0
6862 04:47:58.693687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 04:47:58.693796 ==
6864 04:47:58.693890 DQS Delay:
6865 04:47:58.693980 DQS0 = 28, DQS1 = 32
6866 04:47:58.696755 DQM Delay:
6867 04:47:58.696862 DQM0 = 11, DQM1 = 10
6868 04:47:58.700140 DQ Delay:
6869 04:47:58.703588 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =12
6870 04:47:58.703694 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6871 04:47:58.706138 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6872 04:47:58.709651 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6873 04:47:58.709733
6874 04:47:58.712883
6875 04:47:58.719792 [DQSOSCAuto] RK0, (LSB)MR18= 0x8dc6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6876 04:47:58.722868 CH1 RK0: MR19=C0C, MR18=8DC6
6877 04:47:58.729732 CH1_RK0: MR19=0xC0C, MR18=0x8DC6, DQSOSC=385, MR23=63, INC=398, DEC=265
6878 04:47:58.729815 ==
6879 04:47:58.732877 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 04:47:58.736163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 04:47:58.736273 ==
6882 04:47:58.739610 [Gating] SW mode calibration
6883 04:47:58.746409 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6884 04:47:58.749777 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6885 04:47:58.756183 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6886 04:47:58.760093 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6887 04:47:58.763397 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6888 04:47:58.770019 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 04:47:58.772958 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 04:47:58.776155 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 04:47:58.783276 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 04:47:58.786213 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 04:47:58.789638 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6894 04:47:58.793074 Total UI for P1: 0, mck2ui 16
6895 04:47:58.796037 best dqsien dly found for B0: ( 0, 14, 24)
6896 04:47:58.799785 Total UI for P1: 0, mck2ui 16
6897 04:47:58.803072 best dqsien dly found for B1: ( 0, 14, 24)
6898 04:47:58.806385 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6899 04:47:58.809752 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6900 04:47:58.813042
6901 04:47:58.816470 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6902 04:47:58.819726 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6903 04:47:58.822879 [Gating] SW calibration Done
6904 04:47:58.822962 ==
6905 04:47:58.826340 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 04:47:58.829568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 04:47:58.829651 ==
6908 04:47:58.829717 RX Vref Scan: 0
6909 04:47:58.829778
6910 04:47:58.832677 RX Vref 0 -> 0, step: 1
6911 04:47:58.832760
6912 04:47:58.836412 RX Delay -410 -> 252, step: 16
6913 04:47:58.839433 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6914 04:47:58.845899 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6915 04:47:58.849323 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6916 04:47:58.853177 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6917 04:47:58.856398 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6918 04:47:58.862929 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6919 04:47:58.866349 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6920 04:47:58.869641 iDelay=230, Bit 7, Center -11 (-234 ~ 213) 448
6921 04:47:58.872913 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6922 04:47:58.879459 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6923 04:47:58.882822 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6924 04:47:58.886117 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6925 04:47:58.889550 iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464
6926 04:47:58.895854 iDelay=230, Bit 13, Center -3 (-234 ~ 229) 464
6927 04:47:58.899066 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6928 04:47:58.902232 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6929 04:47:58.902320 ==
6930 04:47:58.905758 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 04:47:58.909127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 04:47:58.909211 ==
6933 04:47:58.912475 DQS Delay:
6934 04:47:58.912558 DQS0 = 35, DQS1 = 35
6935 04:47:58.915975 DQM Delay:
6936 04:47:58.916059 DQM0 = 20, DQM1 = 19
6937 04:47:58.919302 DQ Delay:
6938 04:47:58.919385 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6939 04:47:58.922492 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =24
6940 04:47:58.925668 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6941 04:47:58.928935 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =32
6942 04:47:58.929018
6943 04:47:58.929083
6944 04:47:58.932224 ==
6945 04:47:58.935522 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 04:47:58.939261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 04:47:58.939355 ==
6948 04:47:58.939437
6949 04:47:58.939498
6950 04:47:58.942259 TX Vref Scan disable
6951 04:47:58.942343 == TX Byte 0 ==
6952 04:47:58.945394 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6953 04:47:58.952458 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6954 04:47:58.952551 == TX Byte 1 ==
6955 04:47:58.955685 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6956 04:47:58.958981 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6957 04:47:58.962248 ==
6958 04:47:58.965474 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 04:47:58.968714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 04:47:58.968801 ==
6961 04:47:58.968867
6962 04:47:58.968927
6963 04:47:58.972015 TX Vref Scan disable
6964 04:47:58.972097 == TX Byte 0 ==
6965 04:47:58.975364 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6966 04:47:58.982410 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6967 04:47:58.982504 == TX Byte 1 ==
6968 04:47:58.985748 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6969 04:47:58.989064 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6970 04:47:58.992441
6971 04:47:58.992526 [DATLAT]
6972 04:47:58.992592 Freq=400, CH1 RK1
6973 04:47:58.992678
6974 04:47:58.995565 DATLAT Default: 0xe
6975 04:47:58.995648 0, 0xFFFF, sum = 0
6976 04:47:58.998689 1, 0xFFFF, sum = 0
6977 04:47:58.998774 2, 0xFFFF, sum = 0
6978 04:47:59.002034 3, 0xFFFF, sum = 0
6979 04:47:59.002119 4, 0xFFFF, sum = 0
6980 04:47:59.005446 5, 0xFFFF, sum = 0
6981 04:47:59.008703 6, 0xFFFF, sum = 0
6982 04:47:59.008789 7, 0xFFFF, sum = 0
6983 04:47:59.012135 8, 0xFFFF, sum = 0
6984 04:47:59.012223 9, 0xFFFF, sum = 0
6985 04:47:59.015406 10, 0xFFFF, sum = 0
6986 04:47:59.015491 11, 0xFFFF, sum = 0
6987 04:47:59.018655 12, 0xFFFF, sum = 0
6988 04:47:59.018740 13, 0x0, sum = 1
6989 04:47:59.021906 14, 0x0, sum = 2
6990 04:47:59.021992 15, 0x0, sum = 3
6991 04:47:59.025316 16, 0x0, sum = 4
6992 04:47:59.025446 best_step = 14
6993 04:47:59.025540
6994 04:47:59.025630 ==
6995 04:47:59.028702 Dram Type= 6, Freq= 0, CH_1, rank 1
6996 04:47:59.032473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6997 04:47:59.032562 ==
6998 04:47:59.035352 RX Vref Scan: 0
6999 04:47:59.035435
7000 04:47:59.038667 RX Vref 0 -> 0, step: 1
7001 04:47:59.038751
7002 04:47:59.038816 RX Delay -311 -> 252, step: 8
7003 04:47:59.047208 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
7004 04:47:59.050475 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
7005 04:47:59.054017 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
7006 04:47:59.057601 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
7007 04:47:59.064028 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
7008 04:47:59.067359 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
7009 04:47:59.070726 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
7010 04:47:59.074038 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
7011 04:47:59.080764 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
7012 04:47:59.083996 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7013 04:47:59.087142 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
7014 04:47:59.090499 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7015 04:47:59.097091 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7016 04:47:59.100455 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7017 04:47:59.103603 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7018 04:47:59.110834 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7019 04:47:59.110935 ==
7020 04:47:59.113620 Dram Type= 6, Freq= 0, CH_1, rank 1
7021 04:47:59.117209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7022 04:47:59.117295 ==
7023 04:47:59.117361 DQS Delay:
7024 04:47:59.120347 DQS0 = 28, DQS1 = 32
7025 04:47:59.120430 DQM Delay:
7026 04:47:59.123699 DQM0 = 11, DQM1 = 11
7027 04:47:59.123783 DQ Delay:
7028 04:47:59.126971 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7029 04:47:59.130257 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
7030 04:47:59.133590 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7031 04:47:59.136761 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7032 04:47:59.136846
7033 04:47:59.136912
7034 04:47:59.143589 [DQSOSCAuto] RK1, (LSB)MR18= 0xc758, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
7035 04:47:59.146732 CH1 RK1: MR19=C0C, MR18=C758
7036 04:47:59.153407 CH1_RK1: MR19=0xC0C, MR18=0xC758, DQSOSC=385, MR23=63, INC=398, DEC=265
7037 04:47:59.156793 [RxdqsGatingPostProcess] freq 400
7038 04:47:59.163870 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7039 04:47:59.164015 best DQS0 dly(2T, 0.5T) = (0, 10)
7040 04:47:59.167256 best DQS1 dly(2T, 0.5T) = (0, 10)
7041 04:47:59.170367 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7042 04:47:59.173742 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7043 04:47:59.177010 best DQS0 dly(2T, 0.5T) = (0, 10)
7044 04:47:59.180407 best DQS1 dly(2T, 0.5T) = (0, 10)
7045 04:47:59.183328 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7046 04:47:59.186889 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7047 04:47:59.189983 Pre-setting of DQS Precalculation
7048 04:47:59.193605 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7049 04:47:59.203749 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7050 04:47:59.210088 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7051 04:47:59.210200
7052 04:47:59.210337
7053 04:47:59.213395 [Calibration Summary] 800 Mbps
7054 04:47:59.213483 CH 0, Rank 0
7055 04:47:59.216819 SW Impedance : PASS
7056 04:47:59.216908 DUTY Scan : NO K
7057 04:47:59.220024 ZQ Calibration : PASS
7058 04:47:59.223334 Jitter Meter : NO K
7059 04:47:59.223421 CBT Training : PASS
7060 04:47:59.226731 Write leveling : PASS
7061 04:47:59.229980 RX DQS gating : PASS
7062 04:47:59.230066 RX DQ/DQS(RDDQC) : PASS
7063 04:47:59.233261 TX DQ/DQS : PASS
7064 04:47:59.236504 RX DATLAT : PASS
7065 04:47:59.236591 RX DQ/DQS(Engine): PASS
7066 04:47:59.239754 TX OE : NO K
7067 04:47:59.239853 All Pass.
7068 04:47:59.239958
7069 04:47:59.243183 CH 0, Rank 1
7070 04:47:59.243270 SW Impedance : PASS
7071 04:47:59.246421 DUTY Scan : NO K
7072 04:47:59.249840 ZQ Calibration : PASS
7073 04:47:59.249938 Jitter Meter : NO K
7074 04:47:59.253149 CBT Training : PASS
7075 04:47:59.253235 Write leveling : NO K
7076 04:47:59.256454 RX DQS gating : PASS
7077 04:47:59.259755 RX DQ/DQS(RDDQC) : PASS
7078 04:47:59.259844 TX DQ/DQS : PASS
7079 04:47:59.263165 RX DATLAT : PASS
7080 04:47:59.266465 RX DQ/DQS(Engine): PASS
7081 04:47:59.266553 TX OE : NO K
7082 04:47:59.270171 All Pass.
7083 04:47:59.270261
7084 04:47:59.270347 CH 1, Rank 0
7085 04:47:59.273468 SW Impedance : PASS
7086 04:47:59.273579 DUTY Scan : NO K
7087 04:47:59.276833 ZQ Calibration : PASS
7088 04:47:59.280124 Jitter Meter : NO K
7089 04:47:59.280213 CBT Training : PASS
7090 04:47:59.283398 Write leveling : PASS
7091 04:47:59.286364 RX DQS gating : PASS
7092 04:47:59.286452 RX DQ/DQS(RDDQC) : PASS
7093 04:47:59.289603 TX DQ/DQS : PASS
7094 04:47:59.293104 RX DATLAT : PASS
7095 04:47:59.293194 RX DQ/DQS(Engine): PASS
7096 04:47:59.296036 TX OE : NO K
7097 04:47:59.296123 All Pass.
7098 04:47:59.296223
7099 04:47:59.299559 CH 1, Rank 1
7100 04:47:59.299637 SW Impedance : PASS
7101 04:47:59.302581 DUTY Scan : NO K
7102 04:47:59.306417 ZQ Calibration : PASS
7103 04:47:59.306510 Jitter Meter : NO K
7104 04:47:59.309606 CBT Training : PASS
7105 04:47:59.312981 Write leveling : NO K
7106 04:47:59.313072 RX DQS gating : PASS
7107 04:47:59.316568 RX DQ/DQS(RDDQC) : PASS
7108 04:47:59.316655 TX DQ/DQS : PASS
7109 04:47:59.319232 RX DATLAT : PASS
7110 04:47:59.322854 RX DQ/DQS(Engine): PASS
7111 04:47:59.322947 TX OE : NO K
7112 04:47:59.325883 All Pass.
7113 04:47:59.325971
7114 04:47:59.326057 DramC Write-DBI off
7115 04:47:59.328991 PER_BANK_REFRESH: Hybrid Mode
7116 04:47:59.332395 TX_TRACKING: ON
7117 04:47:59.338879 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7118 04:47:59.342346 [FAST_K] Save calibration result to emmc
7119 04:47:59.349467 dramc_set_vcore_voltage set vcore to 725000
7120 04:47:59.349582 Read voltage for 1600, 0
7121 04:47:59.349675 Vio18 = 0
7122 04:47:59.352827 Vcore = 725000
7123 04:47:59.352914 Vdram = 0
7124 04:47:59.352999 Vddq = 0
7125 04:47:59.356118 Vmddr = 0
7126 04:47:59.359454 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7127 04:47:59.366054 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7128 04:47:59.369481 MEM_TYPE=3, freq_sel=13
7129 04:47:59.369578 sv_algorithm_assistance_LP4_3733
7130 04:47:59.375755 ============ PULL DRAM RESETB DOWN ============
7131 04:47:59.378958 ========== PULL DRAM RESETB DOWN end =========
7132 04:47:59.382245 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7133 04:47:59.385632 ===================================
7134 04:47:59.389001 LPDDR4 DRAM CONFIGURATION
7135 04:47:59.392387 ===================================
7136 04:47:59.395686 EX_ROW_EN[0] = 0x0
7137 04:47:59.395778 EX_ROW_EN[1] = 0x0
7138 04:47:59.399070 LP4Y_EN = 0x0
7139 04:47:59.399158 WORK_FSP = 0x1
7140 04:47:59.402360 WL = 0x5
7141 04:47:59.402448 RL = 0x5
7142 04:47:59.405766 BL = 0x2
7143 04:47:59.405854 RPST = 0x0
7144 04:47:59.408922 RD_PRE = 0x0
7145 04:47:59.409015 WR_PRE = 0x1
7146 04:47:59.412692 WR_PST = 0x1
7147 04:47:59.412780 DBI_WR = 0x0
7148 04:47:59.415308 DBI_RD = 0x0
7149 04:47:59.415393 OTF = 0x1
7150 04:47:59.418747 ===================================
7151 04:47:59.422140 ===================================
7152 04:47:59.425414 ANA top config
7153 04:47:59.428570 ===================================
7154 04:47:59.432231 DLL_ASYNC_EN = 0
7155 04:47:59.432362 ALL_SLAVE_EN = 0
7156 04:47:59.435211 NEW_RANK_MODE = 1
7157 04:47:59.438495 DLL_IDLE_MODE = 1
7158 04:47:59.442109 LP45_APHY_COMB_EN = 1
7159 04:47:59.442240 TX_ODT_DIS = 0
7160 04:47:59.445482 NEW_8X_MODE = 1
7161 04:47:59.448753 ===================================
7162 04:47:59.452138 ===================================
7163 04:47:59.455250 data_rate = 3200
7164 04:47:59.458647 CKR = 1
7165 04:47:59.462181 DQ_P2S_RATIO = 8
7166 04:47:59.465498 ===================================
7167 04:47:59.468804 CA_P2S_RATIO = 8
7168 04:47:59.468894 DQ_CA_OPEN = 0
7169 04:47:59.472178 DQ_SEMI_OPEN = 0
7170 04:47:59.475568 CA_SEMI_OPEN = 0
7171 04:47:59.478684 CA_FULL_RATE = 0
7172 04:47:59.482078 DQ_CKDIV4_EN = 0
7173 04:47:59.485274 CA_CKDIV4_EN = 0
7174 04:47:59.485363 CA_PREDIV_EN = 0
7175 04:47:59.488627 PH8_DLY = 12
7176 04:47:59.492051 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7177 04:47:59.495524 DQ_AAMCK_DIV = 4
7178 04:47:59.498824 CA_AAMCK_DIV = 4
7179 04:47:59.501949 CA_ADMCK_DIV = 4
7180 04:47:59.502036 DQ_TRACK_CA_EN = 0
7181 04:47:59.505337 CA_PICK = 1600
7182 04:47:59.508711 CA_MCKIO = 1600
7183 04:47:59.511986 MCKIO_SEMI = 0
7184 04:47:59.515282 PLL_FREQ = 3068
7185 04:47:59.518768 DQ_UI_PI_RATIO = 32
7186 04:47:59.522090 CA_UI_PI_RATIO = 0
7187 04:47:59.525251 ===================================
7188 04:47:59.528251 ===================================
7189 04:47:59.528380 memory_type:LPDDR4
7190 04:47:59.531530 GP_NUM : 10
7191 04:47:59.534868 SRAM_EN : 1
7192 04:47:59.534954 MD32_EN : 0
7193 04:47:59.538767 ===================================
7194 04:47:59.542017 [ANA_INIT] >>>>>>>>>>>>>>
7195 04:47:59.545365 <<<<<< [CONFIGURE PHASE]: ANA_TX
7196 04:47:59.548577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7197 04:47:59.551600 ===================================
7198 04:47:59.554743 data_rate = 3200,PCW = 0X7600
7199 04:47:59.558757 ===================================
7200 04:47:59.562056 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7201 04:47:59.565155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7202 04:47:59.571648 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7203 04:47:59.574888 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7204 04:47:59.578069 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7205 04:47:59.581837 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7206 04:47:59.584943 [ANA_INIT] flow start
7207 04:47:59.588085 [ANA_INIT] PLL >>>>>>>>
7208 04:47:59.588174 [ANA_INIT] PLL <<<<<<<<
7209 04:47:59.591721 [ANA_INIT] MIDPI >>>>>>>>
7210 04:47:59.594872 [ANA_INIT] MIDPI <<<<<<<<
7211 04:47:59.598176 [ANA_INIT] DLL >>>>>>>>
7212 04:47:59.598265 [ANA_INIT] DLL <<<<<<<<
7213 04:47:59.601517 [ANA_INIT] flow end
7214 04:47:59.604786 ============ LP4 DIFF to SE enter ============
7215 04:47:59.608215 ============ LP4 DIFF to SE exit ============
7216 04:47:59.611487 [ANA_INIT] <<<<<<<<<<<<<
7217 04:47:59.614850 [Flow] Enable top DCM control >>>>>
7218 04:47:59.618129 [Flow] Enable top DCM control <<<<<
7219 04:47:59.621477 Enable DLL master slave shuffle
7220 04:47:59.628141 ==============================================================
7221 04:47:59.628241 Gating Mode config
7222 04:47:59.634658 ==============================================================
7223 04:47:59.634755 Config description:
7224 04:47:59.644467 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7225 04:47:59.651460 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7226 04:47:59.657574 SELPH_MODE 0: By rank 1: By Phase
7227 04:47:59.661407 ==============================================================
7228 04:47:59.664651 GAT_TRACK_EN = 1
7229 04:47:59.667580 RX_GATING_MODE = 2
7230 04:47:59.671390 RX_GATING_TRACK_MODE = 2
7231 04:47:59.674645 SELPH_MODE = 1
7232 04:47:59.678065 PICG_EARLY_EN = 1
7233 04:47:59.681330 VALID_LAT_VALUE = 1
7234 04:47:59.684446 ==============================================================
7235 04:47:59.688049 Enter into Gating configuration >>>>
7236 04:47:59.691236 Exit from Gating configuration <<<<
7237 04:47:59.694251 Enter into DVFS_PRE_config >>>>>
7238 04:47:59.707721 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7239 04:47:59.711040 Exit from DVFS_PRE_config <<<<<
7240 04:47:59.714599 Enter into PICG configuration >>>>
7241 04:47:59.714690 Exit from PICG configuration <<<<
7242 04:47:59.717936 [RX_INPUT] configuration >>>>>
7243 04:47:59.720850 [RX_INPUT] configuration <<<<<
7244 04:47:59.727436 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7245 04:47:59.730717 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7246 04:47:59.737371 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7247 04:47:59.744206 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7248 04:47:59.750890 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7249 04:47:59.757298 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7250 04:47:59.760607 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7251 04:47:59.763628 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7252 04:47:59.770524 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7253 04:47:59.773846 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7254 04:47:59.777183 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7255 04:47:59.780521 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7256 04:47:59.783935 ===================================
7257 04:47:59.787412 LPDDR4 DRAM CONFIGURATION
7258 04:47:59.790600 ===================================
7259 04:47:59.793808 EX_ROW_EN[0] = 0x0
7260 04:47:59.793898 EX_ROW_EN[1] = 0x0
7261 04:47:59.797013 LP4Y_EN = 0x0
7262 04:47:59.797098 WORK_FSP = 0x1
7263 04:47:59.800363 WL = 0x5
7264 04:47:59.800448 RL = 0x5
7265 04:47:59.803628 BL = 0x2
7266 04:47:59.803713 RPST = 0x0
7267 04:47:59.807666 RD_PRE = 0x0
7268 04:47:59.807752 WR_PRE = 0x1
7269 04:47:59.810782 WR_PST = 0x1
7270 04:47:59.810867 DBI_WR = 0x0
7271 04:47:59.814047 DBI_RD = 0x0
7272 04:47:59.814134 OTF = 0x1
7273 04:47:59.817259 ===================================
7274 04:47:59.824019 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7275 04:47:59.827381 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7276 04:47:59.830266 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7277 04:47:59.833746 ===================================
7278 04:47:59.837038 LPDDR4 DRAM CONFIGURATION
7279 04:47:59.840552 ===================================
7280 04:47:59.843707 EX_ROW_EN[0] = 0x10
7281 04:47:59.843807 EX_ROW_EN[1] = 0x0
7282 04:47:59.846997 LP4Y_EN = 0x0
7283 04:47:59.847096 WORK_FSP = 0x1
7284 04:47:59.850254 WL = 0x5
7285 04:47:59.850341 RL = 0x5
7286 04:47:59.853581 BL = 0x2
7287 04:47:59.853666 RPST = 0x0
7288 04:47:59.856868 RD_PRE = 0x0
7289 04:47:59.856952 WR_PRE = 0x1
7290 04:47:59.860127 WR_PST = 0x1
7291 04:47:59.860211 DBI_WR = 0x0
7292 04:47:59.863505 DBI_RD = 0x0
7293 04:47:59.863590 OTF = 0x1
7294 04:47:59.867353 ===================================
7295 04:47:59.873993 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7296 04:47:59.874096 ==
7297 04:47:59.876669 Dram Type= 6, Freq= 0, CH_0, rank 0
7298 04:47:59.883665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7299 04:47:59.883769 ==
7300 04:47:59.883835 [Duty_Offset_Calibration]
7301 04:47:59.886914 B0:2 B1:1 CA:1
7302 04:47:59.886998
7303 04:47:59.890108 [DutyScan_Calibration_Flow] k_type=0
7304 04:47:59.899065
7305 04:47:59.899172 ==CLK 0==
7306 04:47:59.902966 Final CLK duty delay cell = 0
7307 04:47:59.906228 [0] MAX Duty = 5156%(X100), DQS PI = 22
7308 04:47:59.909065 [0] MIN Duty = 4907%(X100), DQS PI = 0
7309 04:47:59.909153 [0] AVG Duty = 5031%(X100)
7310 04:47:59.912743
7311 04:47:59.916000 CH0 CLK Duty spec in!! Max-Min= 249%
7312 04:47:59.919366 [DutyScan_Calibration_Flow] ====Done====
7313 04:47:59.919455
7314 04:47:59.922615 [DutyScan_Calibration_Flow] k_type=1
7315 04:47:59.938788
7316 04:47:59.938936 ==DQS 0 ==
7317 04:47:59.941866 Final DQS duty delay cell = -4
7318 04:47:59.944915 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7319 04:47:59.948464 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7320 04:47:59.951913 [-4] AVG Duty = 4891%(X100)
7321 04:47:59.952005
7322 04:47:59.952071 ==DQS 1 ==
7323 04:47:59.954861 Final DQS duty delay cell = 0
7324 04:47:59.958391 [0] MAX Duty = 5187%(X100), DQS PI = 4
7325 04:47:59.961821 [0] MIN Duty = 5031%(X100), DQS PI = 52
7326 04:47:59.965328 [0] AVG Duty = 5109%(X100)
7327 04:47:59.965423
7328 04:47:59.968475 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7329 04:47:59.968578
7330 04:47:59.971747 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7331 04:47:59.975024 [DutyScan_Calibration_Flow] ====Done====
7332 04:47:59.975112
7333 04:47:59.978399 [DutyScan_Calibration_Flow] k_type=3
7334 04:47:59.995129
7335 04:47:59.995273 ==DQM 0 ==
7336 04:47:59.998401 Final DQM duty delay cell = 0
7337 04:48:00.001869 [0] MAX Duty = 5218%(X100), DQS PI = 34
7338 04:48:00.005220 [0] MIN Duty = 4875%(X100), DQS PI = 60
7339 04:48:00.005316 [0] AVG Duty = 5046%(X100)
7340 04:48:00.008605
7341 04:48:00.008729 ==DQM 1 ==
7342 04:48:00.012077 Final DQM duty delay cell = -4
7343 04:48:00.015068 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7344 04:48:00.018701 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7345 04:48:00.022202 [-4] AVG Duty = 4906%(X100)
7346 04:48:00.022290
7347 04:48:00.024794 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7348 04:48:00.024881
7349 04:48:00.028279 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7350 04:48:00.031616 [DutyScan_Calibration_Flow] ====Done====
7351 04:48:00.031707
7352 04:48:00.034970 [DutyScan_Calibration_Flow] k_type=2
7353 04:48:00.052925
7354 04:48:00.053069 ==DQ 0 ==
7355 04:48:00.056395 Final DQ duty delay cell = 0
7356 04:48:00.058904 [0] MAX Duty = 5062%(X100), DQS PI = 24
7357 04:48:00.062862 [0] MIN Duty = 4907%(X100), DQS PI = 0
7358 04:48:00.062976 [0] AVG Duty = 4984%(X100)
7359 04:48:00.063068
7360 04:48:00.065949 ==DQ 1 ==
7361 04:48:00.069680 Final DQ duty delay cell = 0
7362 04:48:00.072564 [0] MAX Duty = 5124%(X100), DQS PI = 22
7363 04:48:00.075654 [0] MIN Duty = 4938%(X100), DQS PI = 34
7364 04:48:00.075732 [0] AVG Duty = 5031%(X100)
7365 04:48:00.075799
7366 04:48:00.078883 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7367 04:48:00.082653
7368 04:48:00.086022 CH0 DQ 1 Duty spec in!! Max-Min= 186%
7369 04:48:00.089255 [DutyScan_Calibration_Flow] ====Done====
7370 04:48:00.089338 ==
7371 04:48:00.092674 Dram Type= 6, Freq= 0, CH_1, rank 0
7372 04:48:00.095944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7373 04:48:00.096036 ==
7374 04:48:00.099392 [Duty_Offset_Calibration]
7375 04:48:00.099473 B0:1 B1:0 CA:0
7376 04:48:00.099536
7377 04:48:00.102678 [DutyScan_Calibration_Flow] k_type=0
7378 04:48:00.112117
7379 04:48:00.112226 ==CLK 0==
7380 04:48:00.115376 Final CLK duty delay cell = -4
7381 04:48:00.118694 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7382 04:48:00.121970 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7383 04:48:00.125268 [-4] AVG Duty = 4922%(X100)
7384 04:48:00.125353
7385 04:48:00.128415 CH1 CLK Duty spec in!! Max-Min= 156%
7386 04:48:00.131523 [DutyScan_Calibration_Flow] ====Done====
7387 04:48:00.131615
7388 04:48:00.135367 [DutyScan_Calibration_Flow] k_type=1
7389 04:48:00.151654
7390 04:48:00.151806 ==DQS 0 ==
7391 04:48:00.154392 Final DQS duty delay cell = 0
7392 04:48:00.157756 [0] MAX Duty = 5094%(X100), DQS PI = 26
7393 04:48:00.161016 [0] MIN Duty = 4844%(X100), DQS PI = 48
7394 04:48:00.164380 [0] AVG Duty = 4969%(X100)
7395 04:48:00.164467
7396 04:48:00.164534 ==DQS 1 ==
7397 04:48:00.167821 Final DQS duty delay cell = -4
7398 04:48:00.171101 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7399 04:48:00.174469 [-4] MIN Duty = 4750%(X100), DQS PI = 8
7400 04:48:00.177692 [-4] AVG Duty = 4859%(X100)
7401 04:48:00.177779
7402 04:48:00.181092 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7403 04:48:00.181174
7404 04:48:00.184259 CH1 DQS 1 Duty spec in!! Max-Min= 219%
7405 04:48:00.188219 [DutyScan_Calibration_Flow] ====Done====
7406 04:48:00.188362
7407 04:48:00.191462 [DutyScan_Calibration_Flow] k_type=3
7408 04:48:00.208689
7409 04:48:00.208833 ==DQM 0 ==
7410 04:48:00.211496 Final DQM duty delay cell = 0
7411 04:48:00.214984 [0] MAX Duty = 5218%(X100), DQS PI = 18
7412 04:48:00.218384 [0] MIN Duty = 4969%(X100), DQS PI = 48
7413 04:48:00.221499 [0] AVG Duty = 5093%(X100)
7414 04:48:00.221596
7415 04:48:00.221700 ==DQM 1 ==
7416 04:48:00.224874 Final DQM duty delay cell = 0
7417 04:48:00.228062 [0] MAX Duty = 5093%(X100), DQS PI = 16
7418 04:48:00.231440 [0] MIN Duty = 4907%(X100), DQS PI = 34
7419 04:48:00.234683 [0] AVG Duty = 5000%(X100)
7420 04:48:00.234776
7421 04:48:00.238383 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7422 04:48:00.238475
7423 04:48:00.241699 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7424 04:48:00.245058 [DutyScan_Calibration_Flow] ====Done====
7425 04:48:00.245149
7426 04:48:00.247711 [DutyScan_Calibration_Flow] k_type=2
7427 04:48:00.264885
7428 04:48:00.265032 ==DQ 0 ==
7429 04:48:00.268155 Final DQ duty delay cell = -4
7430 04:48:00.271315 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7431 04:48:00.274609 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7432 04:48:00.278073 [-4] AVG Duty = 4968%(X100)
7433 04:48:00.278160
7434 04:48:00.278225 ==DQ 1 ==
7435 04:48:00.281210 Final DQ duty delay cell = 0
7436 04:48:00.284672 [0] MAX Duty = 5156%(X100), DQS PI = 18
7437 04:48:00.287904 [0] MIN Duty = 4938%(X100), DQS PI = 8
7438 04:48:00.291391 [0] AVG Duty = 5047%(X100)
7439 04:48:00.291476
7440 04:48:00.294847 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7441 04:48:00.294925
7442 04:48:00.298067 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7443 04:48:00.300757 [DutyScan_Calibration_Flow] ====Done====
7444 04:48:00.304225 nWR fixed to 30
7445 04:48:00.307452 [ModeRegInit_LP4] CH0 RK0
7446 04:48:00.307536 [ModeRegInit_LP4] CH0 RK1
7447 04:48:00.311051 [ModeRegInit_LP4] CH1 RK0
7448 04:48:00.314608 [ModeRegInit_LP4] CH1 RK1
7449 04:48:00.314688 match AC timing 5
7450 04:48:00.320710 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7451 04:48:00.324085 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7452 04:48:00.327626 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7453 04:48:00.334240 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7454 04:48:00.337794 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7455 04:48:00.337927 [MiockJmeterHQA]
7456 04:48:00.338027
7457 04:48:00.340920 [DramcMiockJmeter] u1RxGatingPI = 0
7458 04:48:00.344235 0 : 4252, 4026
7459 04:48:00.344373 4 : 4252, 4027
7460 04:48:00.347297 8 : 4363, 4137
7461 04:48:00.347388 12 : 4252, 4027
7462 04:48:00.347474 16 : 4363, 4137
7463 04:48:00.350603 20 : 4252, 4027
7464 04:48:00.350697 24 : 4363, 4137
7465 04:48:00.353933 28 : 4253, 4027
7466 04:48:00.354024 32 : 4253, 4026
7467 04:48:00.357888 36 : 4252, 4027
7468 04:48:00.357979 40 : 4255, 4029
7469 04:48:00.361067 44 : 4252, 4027
7470 04:48:00.361156 48 : 4250, 4027
7471 04:48:00.361245 52 : 4363, 4140
7472 04:48:00.364276 56 : 4250, 4027
7473 04:48:00.364406 60 : 4252, 4029
7474 04:48:00.367198 64 : 4250, 4026
7475 04:48:00.367287 68 : 4361, 4137
7476 04:48:00.370703 72 : 4250, 4027
7477 04:48:00.370794 76 : 4361, 4137
7478 04:48:00.374162 80 : 4253, 4029
7479 04:48:00.374253 84 : 4250, 4026
7480 04:48:00.374342 88 : 4252, 66
7481 04:48:00.377830 92 : 4253, 0
7482 04:48:00.377980 96 : 4361, 0
7483 04:48:00.378086 100 : 4363, 0
7484 04:48:00.381116 104 : 4361, 0
7485 04:48:00.381207 108 : 4249, 0
7486 04:48:00.384469 112 : 4250, 0
7487 04:48:00.384559 116 : 4253, 0
7488 04:48:00.384647 120 : 4250, 0
7489 04:48:00.387133 124 : 4250, 0
7490 04:48:00.387220 128 : 4253, 0
7491 04:48:00.390935 132 : 4250, 0
7492 04:48:00.391023 136 : 4250, 0
7493 04:48:00.391110 140 : 4363, 0
7494 04:48:00.393616 144 : 4253, 0
7495 04:48:00.393704 148 : 4249, 0
7496 04:48:00.397092 152 : 4252, 0
7497 04:48:00.397178 156 : 4361, 0
7498 04:48:00.397266 160 : 4250, 0
7499 04:48:00.400475 164 : 4250, 0
7500 04:48:00.400563 168 : 4250, 0
7501 04:48:00.400650 172 : 4360, 0
7502 04:48:00.403757 176 : 4361, 0
7503 04:48:00.403844 180 : 4250, 0
7504 04:48:00.407007 184 : 4360, 0
7505 04:48:00.407094 188 : 4250, 0
7506 04:48:00.407182 192 : 4250, 0
7507 04:48:00.410308 196 : 4250, 0
7508 04:48:00.410395 200 : 4250, 0
7509 04:48:00.413574 204 : 4252, 1297
7510 04:48:00.413663 208 : 4250, 4006
7511 04:48:00.416978 212 : 4360, 4137
7512 04:48:00.417076 216 : 4361, 4137
7513 04:48:00.420323 220 : 4247, 4025
7514 04:48:00.420425 224 : 4363, 4139
7515 04:48:00.420513 228 : 4250, 4027
7516 04:48:00.423552 232 : 4250, 4026
7517 04:48:00.423657 236 : 4250, 4027
7518 04:48:00.427435 240 : 4252, 4030
7519 04:48:00.427525 244 : 4250, 4027
7520 04:48:00.430370 248 : 4250, 4027
7521 04:48:00.430463 252 : 4252, 4027
7522 04:48:00.433811 256 : 4252, 4030
7523 04:48:00.433900 260 : 4250, 4027
7524 04:48:00.437163 264 : 4360, 4138
7525 04:48:00.437253 268 : 4363, 4137
7526 04:48:00.440304 272 : 4250, 4026
7527 04:48:00.440408 276 : 4363, 4140
7528 04:48:00.444001 280 : 4250, 4027
7529 04:48:00.444096 284 : 4253, 4026
7530 04:48:00.444220 288 : 4250, 4027
7531 04:48:00.447031 292 : 4252, 4030
7532 04:48:00.447119 296 : 4250, 4027
7533 04:48:00.450376 300 : 4250, 4027
7534 04:48:00.450468 304 : 4250, 4027
7535 04:48:00.454306 308 : 4252, 3976
7536 04:48:00.454399 312 : 4250, 2054
7537 04:48:00.454502
7538 04:48:00.457487 MIOCK jitter meter ch=0
7539 04:48:00.457574
7540 04:48:00.460710 1T = (312-88) = 224 dly cells
7541 04:48:00.464032 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7542 04:48:00.467403 ==
7543 04:48:00.470590 Dram Type= 6, Freq= 0, CH_0, rank 0
7544 04:48:00.473867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7545 04:48:00.473964 ==
7546 04:48:00.477463 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7547 04:48:00.483865 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7548 04:48:00.486937 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7549 04:48:00.493865 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7550 04:48:00.502325 [CA 0] Center 42 (12~73) winsize 62
7551 04:48:00.505711 [CA 1] Center 42 (12~73) winsize 62
7552 04:48:00.509013 [CA 2] Center 37 (8~67) winsize 60
7553 04:48:00.512446 [CA 3] Center 37 (7~67) winsize 61
7554 04:48:00.515680 [CA 4] Center 36 (6~66) winsize 61
7555 04:48:00.519055 [CA 5] Center 35 (6~64) winsize 59
7556 04:48:00.519167
7557 04:48:00.522232 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7558 04:48:00.522319
7559 04:48:00.525726 [CATrainingPosCal] consider 1 rank data
7560 04:48:00.529156 u2DelayCellTimex100 = 290/100 ps
7561 04:48:00.531827 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7562 04:48:00.538586 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7563 04:48:00.541597 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7564 04:48:00.545184 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7565 04:48:00.548828 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7566 04:48:00.551863 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7567 04:48:00.551958
7568 04:48:00.555137 CA PerBit enable=1, Macro0, CA PI delay=35
7569 04:48:00.555227
7570 04:48:00.558373 [CBTSetCACLKResult] CA Dly = 35
7571 04:48:00.561658 CS Dly: 9 (0~40)
7572 04:48:00.564875 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7573 04:48:00.568771 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7574 04:48:00.568867 ==
7575 04:48:00.571680 Dram Type= 6, Freq= 0, CH_0, rank 1
7576 04:48:00.575078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 04:48:00.578422 ==
7578 04:48:00.581701 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7579 04:48:00.585049 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7580 04:48:00.591847 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7581 04:48:00.595104 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7582 04:48:00.605431 [CA 0] Center 42 (12~73) winsize 62
7583 04:48:00.609214 [CA 1] Center 42 (12~73) winsize 62
7584 04:48:00.612051 [CA 2] Center 38 (8~68) winsize 61
7585 04:48:00.615334 [CA 3] Center 37 (8~67) winsize 60
7586 04:48:00.618582 [CA 4] Center 36 (6~66) winsize 61
7587 04:48:00.622470 [CA 5] Center 35 (5~65) winsize 61
7588 04:48:00.622568
7589 04:48:00.625797 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7590 04:48:00.625884
7591 04:48:00.629011 [CATrainingPosCal] consider 2 rank data
7592 04:48:00.632442 u2DelayCellTimex100 = 290/100 ps
7593 04:48:00.635721 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7594 04:48:00.642412 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7595 04:48:00.645723 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7596 04:48:00.648331 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7597 04:48:00.652160 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7598 04:48:00.655256 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7599 04:48:00.655350
7600 04:48:00.658794 CA PerBit enable=1, Macro0, CA PI delay=35
7601 04:48:00.658881
7602 04:48:00.661716 [CBTSetCACLKResult] CA Dly = 35
7603 04:48:00.665530 CS Dly: 10 (0~42)
7604 04:48:00.668758 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7605 04:48:00.672053 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7606 04:48:00.672141
7607 04:48:00.675361 ----->DramcWriteLeveling(PI) begin...
7608 04:48:00.675450 ==
7609 04:48:00.678676 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 04:48:00.681999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 04:48:00.685115 ==
7612 04:48:00.685209 Write leveling (Byte 0): 37 => 37
7613 04:48:00.688156 Write leveling (Byte 1): 29 => 29
7614 04:48:00.692031 DramcWriteLeveling(PI) end<-----
7615 04:48:00.692123
7616 04:48:00.692189 ==
7617 04:48:00.695003 Dram Type= 6, Freq= 0, CH_0, rank 0
7618 04:48:00.701759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 04:48:00.701882 ==
7620 04:48:00.705120 [Gating] SW mode calibration
7621 04:48:00.711598 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7622 04:48:00.715020 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7623 04:48:00.721584 1 4 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7624 04:48:00.725412 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7625 04:48:00.728244 1 4 8 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7626 04:48:00.731841 1 4 12 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
7627 04:48:00.738097 1 4 16 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (1 1)
7628 04:48:00.741601 1 4 20 | B1->B0 | 3333 3a3a | 1 0 | (1 1) (0 0)
7629 04:48:00.745022 1 4 24 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
7630 04:48:00.751482 1 4 28 | B1->B0 | 3434 3939 | 1 1 | (1 1) (0 0)
7631 04:48:00.754875 1 5 0 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7632 04:48:00.758090 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7633 04:48:00.764498 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7634 04:48:00.768025 1 5 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
7635 04:48:00.771136 1 5 16 | B1->B0 | 3333 2c2c | 1 0 | (1 0) (1 1)
7636 04:48:00.778015 1 5 20 | B1->B0 | 2626 2626 | 0 0 | (0 1) (1 1)
7637 04:48:00.781313 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7638 04:48:00.784700 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7639 04:48:00.791420 1 6 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7640 04:48:00.794415 1 6 4 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7641 04:48:00.797611 1 6 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
7642 04:48:00.804201 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7643 04:48:00.808397 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7644 04:48:00.811623 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7645 04:48:00.818056 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 04:48:00.821494 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 04:48:00.824662 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7648 04:48:00.831141 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 04:48:00.834450 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 04:48:00.837855 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7651 04:48:00.844775 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7652 04:48:00.847745 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7653 04:48:00.851449 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 04:48:00.857872 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 04:48:00.861135 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 04:48:00.864493 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 04:48:00.870963 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 04:48:00.874136 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 04:48:00.877503 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 04:48:00.884406 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 04:48:00.887625 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 04:48:00.890962 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 04:48:00.894390 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 04:48:00.900739 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 04:48:00.904493 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 04:48:00.907579 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7667 04:48:00.914331 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7668 04:48:00.917635 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7669 04:48:00.920773 Total UI for P1: 0, mck2ui 16
7670 04:48:00.924119 best dqsien dly found for B0: ( 1, 9, 14)
7671 04:48:00.927484 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7672 04:48:00.930857 Total UI for P1: 0, mck2ui 16
7673 04:48:00.934289 best dqsien dly found for B1: ( 1, 9, 20)
7674 04:48:00.937082 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7675 04:48:00.940824 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7676 04:48:00.944052
7677 04:48:00.947335 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7678 04:48:00.950397 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7679 04:48:00.953866 [Gating] SW calibration Done
7680 04:48:00.953963 ==
7681 04:48:00.957037 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 04:48:00.960567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 04:48:00.960659 ==
7684 04:48:00.960727 RX Vref Scan: 0
7685 04:48:00.963670
7686 04:48:00.963755 RX Vref 0 -> 0, step: 1
7687 04:48:00.963821
7688 04:48:00.967376 RX Delay 0 -> 252, step: 8
7689 04:48:00.970354 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7690 04:48:00.974122 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7691 04:48:00.980446 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7692 04:48:00.983782 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7693 04:48:00.987068 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7694 04:48:00.990794 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7695 04:48:00.993883 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7696 04:48:00.997244 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7697 04:48:01.003963 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7698 04:48:01.007329 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7699 04:48:01.010471 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7700 04:48:01.013658 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7701 04:48:01.017251 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7702 04:48:01.023810 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7703 04:48:01.026964 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7704 04:48:01.030362 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7705 04:48:01.030454 ==
7706 04:48:01.033754 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 04:48:01.037025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 04:48:01.040433 ==
7709 04:48:01.040522 DQS Delay:
7710 04:48:01.040589 DQS0 = 0, DQS1 = 0
7711 04:48:01.043423 DQM Delay:
7712 04:48:01.043547 DQM0 = 137, DQM1 = 129
7713 04:48:01.046634 DQ Delay:
7714 04:48:01.050323 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7715 04:48:01.053595 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7716 04:48:01.056816 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7717 04:48:01.060046 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7718 04:48:01.060140
7719 04:48:01.060208
7720 04:48:01.060270 ==
7721 04:48:01.063479 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 04:48:01.067181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 04:48:01.067292 ==
7724 04:48:01.070496
7725 04:48:01.070613
7726 04:48:01.070694 TX Vref Scan disable
7727 04:48:01.074079 == TX Byte 0 ==
7728 04:48:01.077154 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7729 04:48:01.080149 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7730 04:48:01.083654 == TX Byte 1 ==
7731 04:48:01.086897 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7732 04:48:01.090305 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7733 04:48:01.090413 ==
7734 04:48:01.093564 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 04:48:01.099977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 04:48:01.100104 ==
7737 04:48:01.112471
7738 04:48:01.115791 TX Vref early break, caculate TX vref
7739 04:48:01.119032 TX Vref=16, minBit 1, minWin=22, winSum=374
7740 04:48:01.122433 TX Vref=18, minBit 0, minWin=23, winSum=387
7741 04:48:01.125886 TX Vref=20, minBit 0, minWin=23, winSum=397
7742 04:48:01.128869 TX Vref=22, minBit 3, minWin=24, winSum=408
7743 04:48:01.132685 TX Vref=24, minBit 7, minWin=24, winSum=415
7744 04:48:01.139255 TX Vref=26, minBit 0, minWin=25, winSum=425
7745 04:48:01.142555 TX Vref=28, minBit 2, minWin=25, winSum=423
7746 04:48:01.145888 TX Vref=30, minBit 8, minWin=24, winSum=414
7747 04:48:01.149141 TX Vref=32, minBit 0, minWin=24, winSum=403
7748 04:48:01.152509 TX Vref=34, minBit 6, minWin=23, winSum=395
7749 04:48:01.158658 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
7750 04:48:01.158753
7751 04:48:01.162429 Final TX Range 0 Vref 26
7752 04:48:01.162519
7753 04:48:01.162584 ==
7754 04:48:01.165921 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 04:48:01.169286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 04:48:01.169374 ==
7757 04:48:01.169442
7758 04:48:01.169502
7759 04:48:01.172470 TX Vref Scan disable
7760 04:48:01.178842 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7761 04:48:01.178942 == TX Byte 0 ==
7762 04:48:01.182263 u2DelayCellOfst[0]=13 cells (4 PI)
7763 04:48:01.185620 u2DelayCellOfst[1]=16 cells (5 PI)
7764 04:48:01.188909 u2DelayCellOfst[2]=13 cells (4 PI)
7765 04:48:01.192599 u2DelayCellOfst[3]=13 cells (4 PI)
7766 04:48:01.196032 u2DelayCellOfst[4]=10 cells (3 PI)
7767 04:48:01.199061 u2DelayCellOfst[5]=0 cells (0 PI)
7768 04:48:01.202604 u2DelayCellOfst[6]=16 cells (5 PI)
7769 04:48:01.202707 u2DelayCellOfst[7]=20 cells (6 PI)
7770 04:48:01.209262 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7771 04:48:01.212579 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7772 04:48:01.215314 == TX Byte 1 ==
7773 04:48:01.215478 u2DelayCellOfst[8]=3 cells (1 PI)
7774 04:48:01.218980 u2DelayCellOfst[9]=0 cells (0 PI)
7775 04:48:01.222360 u2DelayCellOfst[10]=10 cells (3 PI)
7776 04:48:01.225775 u2DelayCellOfst[11]=3 cells (1 PI)
7777 04:48:01.229039 u2DelayCellOfst[12]=10 cells (3 PI)
7778 04:48:01.232456 u2DelayCellOfst[13]=10 cells (3 PI)
7779 04:48:01.235656 u2DelayCellOfst[14]=13 cells (4 PI)
7780 04:48:01.238688 u2DelayCellOfst[15]=10 cells (3 PI)
7781 04:48:01.242314 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7782 04:48:01.249254 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7783 04:48:01.249384 DramC Write-DBI on
7784 04:48:01.249454 ==
7785 04:48:01.251913 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 04:48:01.255847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 04:48:01.259281 ==
7788 04:48:01.259472
7789 04:48:01.259570
7790 04:48:01.259674 TX Vref Scan disable
7791 04:48:01.262404 == TX Byte 0 ==
7792 04:48:01.265537 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7793 04:48:01.269286 == TX Byte 1 ==
7794 04:48:01.272386 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7795 04:48:01.272568 DramC Write-DBI off
7796 04:48:01.275731
7797 04:48:01.275841 [DATLAT]
7798 04:48:01.275935 Freq=1600, CH0 RK0
7799 04:48:01.276044
7800 04:48:01.279049 DATLAT Default: 0xf
7801 04:48:01.279159 0, 0xFFFF, sum = 0
7802 04:48:01.282232 1, 0xFFFF, sum = 0
7803 04:48:01.282343 2, 0xFFFF, sum = 0
7804 04:48:01.285738 3, 0xFFFF, sum = 0
7805 04:48:01.289235 4, 0xFFFF, sum = 0
7806 04:48:01.289329 5, 0xFFFF, sum = 0
7807 04:48:01.291920 6, 0xFFFF, sum = 0
7808 04:48:01.291996 7, 0xFFFF, sum = 0
7809 04:48:01.295377 8, 0xFFFF, sum = 0
7810 04:48:01.295480 9, 0xFFFF, sum = 0
7811 04:48:01.299143 10, 0xFFFF, sum = 0
7812 04:48:01.299231 11, 0xFFFF, sum = 0
7813 04:48:01.302719 12, 0xFFFF, sum = 0
7814 04:48:01.302806 13, 0xFFFF, sum = 0
7815 04:48:01.305426 14, 0x0, sum = 1
7816 04:48:01.305511 15, 0x0, sum = 2
7817 04:48:01.308788 16, 0x0, sum = 3
7818 04:48:01.308880 17, 0x0, sum = 4
7819 04:48:01.312078 best_step = 15
7820 04:48:01.312162
7821 04:48:01.312228 ==
7822 04:48:01.315746 Dram Type= 6, Freq= 0, CH_0, rank 0
7823 04:48:01.319072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7824 04:48:01.319162 ==
7825 04:48:01.319229 RX Vref Scan: 1
7826 04:48:01.319291
7827 04:48:01.322238 Set Vref Range= 24 -> 127
7828 04:48:01.322323
7829 04:48:01.325253 RX Vref 24 -> 127, step: 1
7830 04:48:01.325339
7831 04:48:01.328657 RX Delay 19 -> 252, step: 4
7832 04:48:01.328745
7833 04:48:01.332122 Set Vref, RX VrefLevel [Byte0]: 24
7834 04:48:01.335483 [Byte1]: 24
7835 04:48:01.335577
7836 04:48:01.339026 Set Vref, RX VrefLevel [Byte0]: 25
7837 04:48:01.342354 [Byte1]: 25
7838 04:48:01.342446
7839 04:48:01.345656 Set Vref, RX VrefLevel [Byte0]: 26
7840 04:48:01.348936 [Byte1]: 26
7841 04:48:01.352617
7842 04:48:01.352709 Set Vref, RX VrefLevel [Byte0]: 27
7843 04:48:01.355718 [Byte1]: 27
7844 04:48:01.360308
7845 04:48:01.360406 Set Vref, RX VrefLevel [Byte0]: 28
7846 04:48:01.363595 [Byte1]: 28
7847 04:48:01.367623
7848 04:48:01.367713 Set Vref, RX VrefLevel [Byte0]: 29
7849 04:48:01.370850 [Byte1]: 29
7850 04:48:01.375291
7851 04:48:01.375384 Set Vref, RX VrefLevel [Byte0]: 30
7852 04:48:01.378713 [Byte1]: 30
7853 04:48:01.382591
7854 04:48:01.382686 Set Vref, RX VrefLevel [Byte0]: 31
7855 04:48:01.386039 [Byte1]: 31
7856 04:48:01.390546
7857 04:48:01.390641 Set Vref, RX VrefLevel [Byte0]: 32
7858 04:48:01.393830 [Byte1]: 32
7859 04:48:01.397746
7860 04:48:01.397852 Set Vref, RX VrefLevel [Byte0]: 33
7861 04:48:01.400941 [Byte1]: 33
7862 04:48:01.405450
7863 04:48:01.405545 Set Vref, RX VrefLevel [Byte0]: 34
7864 04:48:01.408740 [Byte1]: 34
7865 04:48:01.412879
7866 04:48:01.412972 Set Vref, RX VrefLevel [Byte0]: 35
7867 04:48:01.416071 [Byte1]: 35
7868 04:48:01.420459
7869 04:48:01.420571 Set Vref, RX VrefLevel [Byte0]: 36
7870 04:48:01.423704 [Byte1]: 36
7871 04:48:01.428272
7872 04:48:01.428404 Set Vref, RX VrefLevel [Byte0]: 37
7873 04:48:01.431528 [Byte1]: 37
7874 04:48:01.435595
7875 04:48:01.435702 Set Vref, RX VrefLevel [Byte0]: 38
7876 04:48:01.438903 [Byte1]: 38
7877 04:48:01.443355
7878 04:48:01.443465 Set Vref, RX VrefLevel [Byte0]: 39
7879 04:48:01.447098 [Byte1]: 39
7880 04:48:01.451103
7881 04:48:01.451218 Set Vref, RX VrefLevel [Byte0]: 40
7882 04:48:01.454516 [Byte1]: 40
7883 04:48:01.458319
7884 04:48:01.458430 Set Vref, RX VrefLevel [Byte0]: 41
7885 04:48:01.461996 [Byte1]: 41
7886 04:48:01.466030
7887 04:48:01.466144 Set Vref, RX VrefLevel [Byte0]: 42
7888 04:48:01.469576 [Byte1]: 42
7889 04:48:01.473961
7890 04:48:01.474059 Set Vref, RX VrefLevel [Byte0]: 43
7891 04:48:01.477345 [Byte1]: 43
7892 04:48:01.481255
7893 04:48:01.481343 Set Vref, RX VrefLevel [Byte0]: 44
7894 04:48:01.484306 [Byte1]: 44
7895 04:48:01.488498
7896 04:48:01.488589 Set Vref, RX VrefLevel [Byte0]: 45
7897 04:48:01.492361 [Byte1]: 45
7898 04:48:01.496314
7899 04:48:01.496414 Set Vref, RX VrefLevel [Byte0]: 46
7900 04:48:01.499544 [Byte1]: 46
7901 04:48:01.503793
7902 04:48:01.503901 Set Vref, RX VrefLevel [Byte0]: 47
7903 04:48:01.506885 [Byte1]: 47
7904 04:48:01.511601
7905 04:48:01.511710 Set Vref, RX VrefLevel [Byte0]: 48
7906 04:48:01.515069 [Byte1]: 48
7907 04:48:01.519044
7908 04:48:01.519153 Set Vref, RX VrefLevel [Byte0]: 49
7909 04:48:01.522341 [Byte1]: 49
7910 04:48:01.526849
7911 04:48:01.526938 Set Vref, RX VrefLevel [Byte0]: 50
7912 04:48:01.530196 [Byte1]: 50
7913 04:48:01.534137
7914 04:48:01.534219 Set Vref, RX VrefLevel [Byte0]: 51
7915 04:48:01.537381 [Byte1]: 51
7916 04:48:01.542134
7917 04:48:01.542218 Set Vref, RX VrefLevel [Byte0]: 52
7918 04:48:01.544850 [Byte1]: 52
7919 04:48:01.549536
7920 04:48:01.549650 Set Vref, RX VrefLevel [Byte0]: 53
7921 04:48:01.552826 [Byte1]: 53
7922 04:48:01.556734
7923 04:48:01.556832 Set Vref, RX VrefLevel [Byte0]: 54
7924 04:48:01.560498 [Byte1]: 54
7925 04:48:01.564563
7926 04:48:01.564646 Set Vref, RX VrefLevel [Byte0]: 55
7927 04:48:01.567735 [Byte1]: 55
7928 04:48:01.571970
7929 04:48:01.572066 Set Vref, RX VrefLevel [Byte0]: 56
7930 04:48:01.575571 [Byte1]: 56
7931 04:48:01.579487
7932 04:48:01.579579 Set Vref, RX VrefLevel [Byte0]: 57
7933 04:48:01.582834 [Byte1]: 57
7934 04:48:01.587429
7935 04:48:01.587520 Set Vref, RX VrefLevel [Byte0]: 58
7936 04:48:01.590416 [Byte1]: 58
7937 04:48:01.594958
7938 04:48:01.595073 Set Vref, RX VrefLevel [Byte0]: 59
7939 04:48:01.597906 [Byte1]: 59
7940 04:48:01.602391
7941 04:48:01.602474 Set Vref, RX VrefLevel [Byte0]: 60
7942 04:48:01.605681 [Byte1]: 60
7943 04:48:01.610035
7944 04:48:01.610131 Set Vref, RX VrefLevel [Byte0]: 61
7945 04:48:01.613097 [Byte1]: 61
7946 04:48:01.617226
7947 04:48:01.617316 Set Vref, RX VrefLevel [Byte0]: 62
7948 04:48:01.620457 [Byte1]: 62
7949 04:48:01.624976
7950 04:48:01.625086 Set Vref, RX VrefLevel [Byte0]: 63
7951 04:48:01.628075 [Byte1]: 63
7952 04:48:01.632682
7953 04:48:01.632770 Set Vref, RX VrefLevel [Byte0]: 64
7954 04:48:01.636019 [Byte1]: 64
7955 04:48:01.640604
7956 04:48:01.640729 Set Vref, RX VrefLevel [Byte0]: 65
7957 04:48:01.643847 [Byte1]: 65
7958 04:48:01.647846
7959 04:48:01.647944 Set Vref, RX VrefLevel [Byte0]: 66
7960 04:48:01.651194 [Byte1]: 66
7961 04:48:01.655242
7962 04:48:01.655331 Set Vref, RX VrefLevel [Byte0]: 67
7963 04:48:01.658484 [Byte1]: 67
7964 04:48:01.663093
7965 04:48:01.663184 Set Vref, RX VrefLevel [Byte0]: 68
7966 04:48:01.666247 [Byte1]: 68
7967 04:48:01.670371
7968 04:48:01.670473 Set Vref, RX VrefLevel [Byte0]: 69
7969 04:48:01.673796 [Byte1]: 69
7970 04:48:01.677777
7971 04:48:01.677865 Set Vref, RX VrefLevel [Byte0]: 70
7972 04:48:01.681074 [Byte1]: 70
7973 04:48:01.685678
7974 04:48:01.685771 Set Vref, RX VrefLevel [Byte0]: 71
7975 04:48:01.689031 [Byte1]: 71
7976 04:48:01.693658
7977 04:48:01.693749 Set Vref, RX VrefLevel [Byte0]: 72
7978 04:48:01.696771 [Byte1]: 72
7979 04:48:01.700803
7980 04:48:01.700908 Set Vref, RX VrefLevel [Byte0]: 73
7981 04:48:01.704426 [Byte1]: 73
7982 04:48:01.708552
7983 04:48:01.708641 Set Vref, RX VrefLevel [Byte0]: 74
7984 04:48:01.711403 [Byte1]: 74
7985 04:48:01.716013
7986 04:48:01.716124 Set Vref, RX VrefLevel [Byte0]: 75
7987 04:48:01.719107 [Byte1]: 75
7988 04:48:01.723366
7989 04:48:01.723455 Set Vref, RX VrefLevel [Byte0]: 76
7990 04:48:01.726654 [Byte1]: 76
7991 04:48:01.730867
7992 04:48:01.730961 Final RX Vref Byte 0 = 60 to rank0
7993 04:48:01.734526 Final RX Vref Byte 1 = 59 to rank0
7994 04:48:01.737715 Final RX Vref Byte 0 = 60 to rank1
7995 04:48:01.741054 Final RX Vref Byte 1 = 59 to rank1==
7996 04:48:01.744525 Dram Type= 6, Freq= 0, CH_0, rank 0
7997 04:48:01.751103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7998 04:48:01.751263 ==
7999 04:48:01.751397 DQS Delay:
8000 04:48:01.751517 DQS0 = 0, DQS1 = 0
8001 04:48:01.754432 DQM Delay:
8002 04:48:01.754549 DQM0 = 134, DQM1 = 127
8003 04:48:01.757629 DQ Delay:
8004 04:48:01.760948 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
8005 04:48:01.764168 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8006 04:48:01.767519 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
8007 04:48:01.771396 DQ12 =134, DQ13 =134, DQ14 =138, DQ15 =134
8008 04:48:01.771483
8009 04:48:01.771546
8010 04:48:01.771612
8011 04:48:01.774704 [DramC_TX_OE_Calibration] TA2
8012 04:48:01.777940 Original DQ_B0 (3 6) =30, OEN = 27
8013 04:48:01.781231 Original DQ_B1 (3 6) =30, OEN = 27
8014 04:48:01.784560 24, 0x0, End_B0=24 End_B1=24
8015 04:48:01.784640 25, 0x0, End_B0=25 End_B1=25
8016 04:48:01.787810 26, 0x0, End_B0=26 End_B1=26
8017 04:48:01.791067 27, 0x0, End_B0=27 End_B1=27
8018 04:48:01.794197 28, 0x0, End_B0=28 End_B1=28
8019 04:48:01.794310 29, 0x0, End_B0=29 End_B1=29
8020 04:48:01.797506 30, 0x0, End_B0=30 End_B1=30
8021 04:48:01.800944 31, 0x4545, End_B0=30 End_B1=30
8022 04:48:01.804454 Byte0 end_step=30 best_step=27
8023 04:48:01.807637 Byte1 end_step=30 best_step=27
8024 04:48:01.810835 Byte0 TX OE(2T, 0.5T) = (3, 3)
8025 04:48:01.810940 Byte1 TX OE(2T, 0.5T) = (3, 3)
8026 04:48:01.811039
8027 04:48:01.814543
8028 04:48:01.820619 [DQSOSCAuto] RK0, (LSB)MR18= 0x231f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
8029 04:48:01.824642 CH0 RK0: MR19=303, MR18=231F
8030 04:48:01.831106 CH0_RK0: MR19=0x303, MR18=0x231F, DQSOSC=392, MR23=63, INC=24, DEC=16
8031 04:48:01.831237
8032 04:48:01.834275 ----->DramcWriteLeveling(PI) begin...
8033 04:48:01.834364 ==
8034 04:48:01.837360 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 04:48:01.841322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 04:48:01.841419 ==
8037 04:48:01.844346 Write leveling (Byte 0): 37 => 37
8038 04:48:01.847399 Write leveling (Byte 1): 26 => 26
8039 04:48:01.851307 DramcWriteLeveling(PI) end<-----
8040 04:48:01.851407
8041 04:48:01.851475 ==
8042 04:48:01.854345 Dram Type= 6, Freq= 0, CH_0, rank 1
8043 04:48:01.857908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8044 04:48:01.858011 ==
8045 04:48:01.860672 [Gating] SW mode calibration
8046 04:48:01.867567 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8047 04:48:01.873982 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8048 04:48:01.877683 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 04:48:01.880996 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8050 04:48:01.887666 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 04:48:01.890917 1 4 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
8052 04:48:01.894161 1 4 16 | B1->B0 | 3131 3737 | 0 1 | (0 0) (1 1)
8053 04:48:01.900781 1 4 20 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8054 04:48:01.904178 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8055 04:48:01.907512 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
8056 04:48:01.914036 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8057 04:48:01.917315 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8058 04:48:01.921062 1 5 8 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
8059 04:48:01.927811 1 5 12 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 1)
8060 04:48:01.930931 1 5 16 | B1->B0 | 2e2e 2928 | 0 1 | (1 0) (0 0)
8061 04:48:01.934015 1 5 20 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8062 04:48:01.937812 1 5 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8063 04:48:01.944120 1 5 28 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (1 1)
8064 04:48:01.947405 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8065 04:48:01.950712 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8066 04:48:01.957827 1 6 8 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8067 04:48:01.961119 1 6 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
8068 04:48:01.964488 1 6 16 | B1->B0 | 3939 4645 | 0 1 | (0 0) (1 1)
8069 04:48:01.970964 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 04:48:01.974437 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8071 04:48:01.977563 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8072 04:48:01.984089 1 7 0 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8073 04:48:01.987434 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 04:48:01.991011 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 04:48:01.997319 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8076 04:48:02.000595 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8077 04:48:02.003958 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 04:48:02.010764 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 04:48:02.014032 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 04:48:02.017327 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 04:48:02.024022 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 04:48:02.027141 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 04:48:02.030473 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 04:48:02.037005 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 04:48:02.040709 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 04:48:02.043878 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 04:48:02.050465 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 04:48:02.053564 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 04:48:02.057209 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 04:48:02.063832 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 04:48:02.067210 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8092 04:48:02.070447 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8093 04:48:02.077075 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8094 04:48:02.077184 Total UI for P1: 0, mck2ui 16
8095 04:48:02.080405 best dqsien dly found for B0: ( 1, 9, 14)
8096 04:48:02.083627 Total UI for P1: 0, mck2ui 16
8097 04:48:02.086928 best dqsien dly found for B1: ( 1, 9, 14)
8098 04:48:02.093037 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8099 04:48:02.096414 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8100 04:48:02.096507
8101 04:48:02.100139 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8102 04:48:02.103409 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8103 04:48:02.106545 [Gating] SW calibration Done
8104 04:48:02.106662 ==
8105 04:48:02.110410 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 04:48:02.113257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 04:48:02.113345 ==
8108 04:48:02.116740 RX Vref Scan: 0
8109 04:48:02.116825
8110 04:48:02.116933 RX Vref 0 -> 0, step: 1
8111 04:48:02.117020
8112 04:48:02.119977 RX Delay 0 -> 252, step: 8
8113 04:48:02.123397 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8114 04:48:02.130207 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8115 04:48:02.133291 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8116 04:48:02.136859 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8117 04:48:02.140012 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8118 04:48:02.143279 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8119 04:48:02.146801 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8120 04:48:02.153295 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8121 04:48:02.156409 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8122 04:48:02.159964 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8123 04:48:02.163300 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8124 04:48:02.166260 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8125 04:48:02.173463 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8126 04:48:02.176833 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8127 04:48:02.179828 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8128 04:48:02.183251 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8129 04:48:02.183332 ==
8130 04:48:02.186581 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 04:48:02.193375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 04:48:02.193473 ==
8133 04:48:02.193539 DQS Delay:
8134 04:48:02.196809 DQS0 = 0, DQS1 = 0
8135 04:48:02.196895 DQM Delay:
8136 04:48:02.196961 DQM0 = 137, DQM1 = 128
8137 04:48:02.200107 DQ Delay:
8138 04:48:02.203388 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8139 04:48:02.206541 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8140 04:48:02.209802 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8141 04:48:02.213102 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8142 04:48:02.213193
8143 04:48:02.213261
8144 04:48:02.213321 ==
8145 04:48:02.216439 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 04:48:02.219690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 04:48:02.223047 ==
8148 04:48:02.223136
8149 04:48:02.223202
8150 04:48:02.223263 TX Vref Scan disable
8151 04:48:02.226348 == TX Byte 0 ==
8152 04:48:02.229631 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8153 04:48:02.232935 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8154 04:48:02.236189 == TX Byte 1 ==
8155 04:48:02.239748 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8156 04:48:02.242716 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8157 04:48:02.246485 ==
8158 04:48:02.249357 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 04:48:02.253006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 04:48:02.253115 ==
8161 04:48:02.266217
8162 04:48:02.269834 TX Vref early break, caculate TX vref
8163 04:48:02.273170 TX Vref=16, minBit 0, minWin=23, winSum=388
8164 04:48:02.276651 TX Vref=18, minBit 1, minWin=23, winSum=396
8165 04:48:02.279861 TX Vref=20, minBit 3, minWin=24, winSum=405
8166 04:48:02.283220 TX Vref=22, minBit 1, minWin=24, winSum=409
8167 04:48:02.286380 TX Vref=24, minBit 1, minWin=25, winSum=419
8168 04:48:02.293058 TX Vref=26, minBit 1, minWin=25, winSum=426
8169 04:48:02.296528 TX Vref=28, minBit 3, minWin=25, winSum=426
8170 04:48:02.299887 TX Vref=30, minBit 0, minWin=25, winSum=417
8171 04:48:02.303042 TX Vref=32, minBit 4, minWin=24, winSum=408
8172 04:48:02.306348 TX Vref=34, minBit 0, minWin=24, winSum=403
8173 04:48:02.313050 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 26
8174 04:48:02.313187
8175 04:48:02.316202 Final TX Range 0 Vref 26
8176 04:48:02.316341
8177 04:48:02.316439 ==
8178 04:48:02.319648 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 04:48:02.323176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 04:48:02.323271 ==
8181 04:48:02.323339
8182 04:48:02.323405
8183 04:48:02.326292 TX Vref Scan disable
8184 04:48:02.332937 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8185 04:48:02.333082 == TX Byte 0 ==
8186 04:48:02.336363 u2DelayCellOfst[0]=16 cells (5 PI)
8187 04:48:02.339713 u2DelayCellOfst[1]=16 cells (5 PI)
8188 04:48:02.343006 u2DelayCellOfst[2]=10 cells (3 PI)
8189 04:48:02.346377 u2DelayCellOfst[3]=13 cells (4 PI)
8190 04:48:02.349727 u2DelayCellOfst[4]=10 cells (3 PI)
8191 04:48:02.353086 u2DelayCellOfst[5]=0 cells (0 PI)
8192 04:48:02.356371 u2DelayCellOfst[6]=16 cells (5 PI)
8193 04:48:02.359739 u2DelayCellOfst[7]=16 cells (5 PI)
8194 04:48:02.363070 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8195 04:48:02.366050 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8196 04:48:02.369707 == TX Byte 1 ==
8197 04:48:02.369823 u2DelayCellOfst[8]=3 cells (1 PI)
8198 04:48:02.372545 u2DelayCellOfst[9]=0 cells (0 PI)
8199 04:48:02.376591 u2DelayCellOfst[10]=6 cells (2 PI)
8200 04:48:02.379779 u2DelayCellOfst[11]=6 cells (2 PI)
8201 04:48:02.382656 u2DelayCellOfst[12]=10 cells (3 PI)
8202 04:48:02.386102 u2DelayCellOfst[13]=10 cells (3 PI)
8203 04:48:02.390111 u2DelayCellOfst[14]=13 cells (4 PI)
8204 04:48:02.392973 u2DelayCellOfst[15]=10 cells (3 PI)
8205 04:48:02.395988 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8206 04:48:02.402443 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8207 04:48:02.402559 DramC Write-DBI on
8208 04:48:02.402631 ==
8209 04:48:02.405812 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 04:48:02.409147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 04:48:02.412770 ==
8212 04:48:02.412869
8213 04:48:02.412938
8214 04:48:02.413000 TX Vref Scan disable
8215 04:48:02.416221 == TX Byte 0 ==
8216 04:48:02.419617 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8217 04:48:02.422583 == TX Byte 1 ==
8218 04:48:02.426222 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8219 04:48:02.429596 DramC Write-DBI off
8220 04:48:02.429692
8221 04:48:02.429761 [DATLAT]
8222 04:48:02.429823 Freq=1600, CH0 RK1
8223 04:48:02.429885
8224 04:48:02.433026 DATLAT Default: 0xf
8225 04:48:02.433114 0, 0xFFFF, sum = 0
8226 04:48:02.436299 1, 0xFFFF, sum = 0
8227 04:48:02.439608 2, 0xFFFF, sum = 0
8228 04:48:02.439696 3, 0xFFFF, sum = 0
8229 04:48:02.442947 4, 0xFFFF, sum = 0
8230 04:48:02.443036 5, 0xFFFF, sum = 0
8231 04:48:02.446299 6, 0xFFFF, sum = 0
8232 04:48:02.446403 7, 0xFFFF, sum = 0
8233 04:48:02.449510 8, 0xFFFF, sum = 0
8234 04:48:02.449602 9, 0xFFFF, sum = 0
8235 04:48:02.452811 10, 0xFFFF, sum = 0
8236 04:48:02.452903 11, 0xFFFF, sum = 0
8237 04:48:02.456105 12, 0xFFFF, sum = 0
8238 04:48:02.456193 13, 0xFFFF, sum = 0
8239 04:48:02.459483 14, 0x0, sum = 1
8240 04:48:02.459573 15, 0x0, sum = 2
8241 04:48:02.462784 16, 0x0, sum = 3
8242 04:48:02.462873 17, 0x0, sum = 4
8243 04:48:02.466080 best_step = 15
8244 04:48:02.466167
8245 04:48:02.466235 ==
8246 04:48:02.469470 Dram Type= 6, Freq= 0, CH_0, rank 1
8247 04:48:02.472793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8248 04:48:02.472883 ==
8249 04:48:02.472952 RX Vref Scan: 0
8250 04:48:02.476323
8251 04:48:02.476410 RX Vref 0 -> 0, step: 1
8252 04:48:02.476478
8253 04:48:02.479517 RX Delay 19 -> 252, step: 4
8254 04:48:02.482641 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8255 04:48:02.489585 iDelay=195, Bit 1, Center 138 (91 ~ 186) 96
8256 04:48:02.492307 iDelay=195, Bit 2, Center 130 (79 ~ 182) 104
8257 04:48:02.495744 iDelay=195, Bit 3, Center 134 (83 ~ 186) 104
8258 04:48:02.499360 iDelay=195, Bit 4, Center 136 (87 ~ 186) 100
8259 04:48:02.502603 iDelay=195, Bit 5, Center 126 (75 ~ 178) 104
8260 04:48:02.509368 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
8261 04:48:02.512083 iDelay=195, Bit 7, Center 142 (91 ~ 194) 104
8262 04:48:02.515986 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8263 04:48:02.518911 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8264 04:48:02.522639 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8265 04:48:02.528841 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
8266 04:48:02.532515 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8267 04:48:02.535901 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8268 04:48:02.539312 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8269 04:48:02.542304 iDelay=195, Bit 15, Center 136 (87 ~ 186) 100
8270 04:48:02.545869 ==
8271 04:48:02.549047 Dram Type= 6, Freq= 0, CH_0, rank 1
8272 04:48:02.552277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8273 04:48:02.552413 ==
8274 04:48:02.552480 DQS Delay:
8275 04:48:02.556037 DQS0 = 0, DQS1 = 0
8276 04:48:02.556125 DQM Delay:
8277 04:48:02.559343 DQM0 = 135, DQM1 = 127
8278 04:48:02.559435 DQ Delay:
8279 04:48:02.562623 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8280 04:48:02.565849 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =142
8281 04:48:02.569102 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8282 04:48:02.572495 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8283 04:48:02.572588
8284 04:48:02.572655
8285 04:48:02.572731
8286 04:48:02.575777 [DramC_TX_OE_Calibration] TA2
8287 04:48:02.579056 Original DQ_B0 (3 6) =30, OEN = 27
8288 04:48:02.582497 Original DQ_B1 (3 6) =30, OEN = 27
8289 04:48:02.585743 24, 0x0, End_B0=24 End_B1=24
8290 04:48:02.588977 25, 0x0, End_B0=25 End_B1=25
8291 04:48:02.589065 26, 0x0, End_B0=26 End_B1=26
8292 04:48:02.592216 27, 0x0, End_B0=27 End_B1=27
8293 04:48:02.595684 28, 0x0, End_B0=28 End_B1=28
8294 04:48:02.599028 29, 0x0, End_B0=29 End_B1=29
8295 04:48:02.602007 30, 0x0, End_B0=30 End_B1=30
8296 04:48:02.602098 31, 0x4141, End_B0=30 End_B1=30
8297 04:48:02.605920 Byte0 end_step=30 best_step=27
8298 04:48:02.608939 Byte1 end_step=30 best_step=27
8299 04:48:02.611987 Byte0 TX OE(2T, 0.5T) = (3, 3)
8300 04:48:02.615636 Byte1 TX OE(2T, 0.5T) = (3, 3)
8301 04:48:02.615802
8302 04:48:02.615896
8303 04:48:02.622342 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
8304 04:48:02.625623 CH0 RK1: MR19=303, MR18=1F08
8305 04:48:02.632466 CH0_RK1: MR19=0x303, MR18=0x1F08, DQSOSC=394, MR23=63, INC=23, DEC=15
8306 04:48:02.635265 [RxdqsGatingPostProcess] freq 1600
8307 04:48:02.638568 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8308 04:48:02.642325 best DQS0 dly(2T, 0.5T) = (1, 1)
8309 04:48:02.645414 best DQS1 dly(2T, 0.5T) = (1, 1)
8310 04:48:02.648604 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8311 04:48:02.651727 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8312 04:48:02.655563 best DQS0 dly(2T, 0.5T) = (1, 1)
8313 04:48:02.658482 best DQS1 dly(2T, 0.5T) = (1, 1)
8314 04:48:02.661818 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8315 04:48:02.665571 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8316 04:48:02.668478 Pre-setting of DQS Precalculation
8317 04:48:02.672027 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8318 04:48:02.672143 ==
8319 04:48:02.675183 Dram Type= 6, Freq= 0, CH_1, rank 0
8320 04:48:02.681904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 04:48:02.682015 ==
8322 04:48:02.685541 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8323 04:48:02.692135 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8324 04:48:02.695391 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8325 04:48:02.701972 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8326 04:48:02.709106 [CA 0] Center 42 (13~72) winsize 60
8327 04:48:02.712447 [CA 1] Center 42 (13~72) winsize 60
8328 04:48:02.715740 [CA 2] Center 38 (9~68) winsize 60
8329 04:48:02.719103 [CA 3] Center 38 (9~68) winsize 60
8330 04:48:02.722269 [CA 4] Center 39 (10~68) winsize 59
8331 04:48:02.725878 [CA 5] Center 37 (8~67) winsize 60
8332 04:48:02.725972
8333 04:48:02.728959 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8334 04:48:02.729047
8335 04:48:02.732308 [CATrainingPosCal] consider 1 rank data
8336 04:48:02.735741 u2DelayCellTimex100 = 290/100 ps
8337 04:48:02.742343 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8338 04:48:02.745714 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8339 04:48:02.748846 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8340 04:48:02.752139 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
8341 04:48:02.755453 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8342 04:48:02.758724 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8343 04:48:02.758816
8344 04:48:02.762127 CA PerBit enable=1, Macro0, CA PI delay=37
8345 04:48:02.762214
8346 04:48:02.765378 [CBTSetCACLKResult] CA Dly = 37
8347 04:48:02.768824 CS Dly: 10 (0~41)
8348 04:48:02.771987 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8349 04:48:02.775108 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8350 04:48:02.775200 ==
8351 04:48:02.778465 Dram Type= 6, Freq= 0, CH_1, rank 1
8352 04:48:02.785650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 04:48:02.785763 ==
8354 04:48:02.788634 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8355 04:48:02.795439 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8356 04:48:02.798870 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8357 04:48:02.804920 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8358 04:48:02.812805 [CA 0] Center 42 (12~72) winsize 61
8359 04:48:02.816123 [CA 1] Center 41 (12~71) winsize 60
8360 04:48:02.819404 [CA 2] Center 38 (9~68) winsize 60
8361 04:48:02.822812 [CA 3] Center 38 (9~67) winsize 59
8362 04:48:02.825996 [CA 4] Center 38 (8~68) winsize 61
8363 04:48:02.829406 [CA 5] Center 37 (8~67) winsize 60
8364 04:48:02.829544
8365 04:48:02.832572 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8366 04:48:02.832741
8367 04:48:02.835916 [CATrainingPosCal] consider 2 rank data
8368 04:48:02.838958 u2DelayCellTimex100 = 290/100 ps
8369 04:48:02.842710 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8370 04:48:02.849344 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8371 04:48:02.852685 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8372 04:48:02.855832 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8373 04:48:02.859087 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8374 04:48:02.862358 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8375 04:48:02.862465
8376 04:48:02.865689 CA PerBit enable=1, Macro0, CA PI delay=37
8377 04:48:02.865775
8378 04:48:02.869014 [CBTSetCACLKResult] CA Dly = 37
8379 04:48:02.872438 CS Dly: 11 (0~44)
8380 04:48:02.875723 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8381 04:48:02.878639 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8382 04:48:02.878728
8383 04:48:02.882410 ----->DramcWriteLeveling(PI) begin...
8384 04:48:02.882499 ==
8385 04:48:02.885620 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 04:48:02.889078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 04:48:02.892602 ==
8388 04:48:02.895731 Write leveling (Byte 0): 25 => 25
8389 04:48:02.895815 Write leveling (Byte 1): 27 => 27
8390 04:48:02.898850 DramcWriteLeveling(PI) end<-----
8391 04:48:02.898960
8392 04:48:02.899052 ==
8393 04:48:02.902675 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 04:48:02.909065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 04:48:02.909172 ==
8396 04:48:02.912798 [Gating] SW mode calibration
8397 04:48:02.919339 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8398 04:48:02.922669 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8399 04:48:02.928958 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 04:48:02.932267 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 04:48:02.935860 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8402 04:48:02.939175 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8403 04:48:02.945699 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 04:48:02.948835 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 04:48:02.952270 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8406 04:48:02.959361 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8407 04:48:02.962553 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8408 04:48:02.965986 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 04:48:02.972628 1 5 8 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (0 0)
8410 04:48:02.975983 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (1 0)
8411 04:48:02.979316 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 04:48:02.985782 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 04:48:02.988870 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 04:48:02.992447 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 04:48:02.999106 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 04:48:03.002342 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 04:48:03.005480 1 6 8 | B1->B0 | 2828 4444 | 0 0 | (0 0) (0 0)
8418 04:48:03.012146 1 6 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8419 04:48:03.015557 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 04:48:03.018875 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 04:48:03.025460 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 04:48:03.028738 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 04:48:03.032156 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 04:48:03.038942 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 04:48:03.042024 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8426 04:48:03.045329 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8427 04:48:03.051659 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 04:48:03.055030 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 04:48:03.058292 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 04:48:03.065348 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 04:48:03.068296 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 04:48:03.071664 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 04:48:03.078633 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 04:48:03.081867 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 04:48:03.085358 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 04:48:03.088501 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 04:48:03.094916 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 04:48:03.098759 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 04:48:03.101683 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 04:48:03.108614 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 04:48:03.111812 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8442 04:48:03.115018 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8443 04:48:03.121643 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 04:48:03.121784 Total UI for P1: 0, mck2ui 16
8445 04:48:03.128264 best dqsien dly found for B0: ( 1, 9, 10)
8446 04:48:03.128446 Total UI for P1: 0, mck2ui 16
8447 04:48:03.134997 best dqsien dly found for B1: ( 1, 9, 10)
8448 04:48:03.138360 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8449 04:48:03.141686 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8450 04:48:03.141802
8451 04:48:03.144973 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8452 04:48:03.148374 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8453 04:48:03.151578 [Gating] SW calibration Done
8454 04:48:03.151667 ==
8455 04:48:03.154755 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 04:48:03.158609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 04:48:03.158702 ==
8458 04:48:03.161785 RX Vref Scan: 0
8459 04:48:03.161873
8460 04:48:03.161940 RX Vref 0 -> 0, step: 1
8461 04:48:03.162001
8462 04:48:03.164877 RX Delay 0 -> 252, step: 8
8463 04:48:03.168518 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8464 04:48:03.174879 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8465 04:48:03.178395 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8466 04:48:03.181844 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8467 04:48:03.185413 iDelay=200, Bit 4, Center 135 (88 ~ 183) 96
8468 04:48:03.188510 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8469 04:48:03.191981 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8470 04:48:03.198472 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8471 04:48:03.201872 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8472 04:48:03.204834 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8473 04:48:03.208663 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8474 04:48:03.211686 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8475 04:48:03.218361 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8476 04:48:03.221550 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8477 04:48:03.224858 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8478 04:48:03.228114 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8479 04:48:03.228204 ==
8480 04:48:03.232065 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 04:48:03.238619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 04:48:03.238726 ==
8483 04:48:03.238794 DQS Delay:
8484 04:48:03.241912 DQS0 = 0, DQS1 = 0
8485 04:48:03.241996 DQM Delay:
8486 04:48:03.245305 DQM0 = 136, DQM1 = 132
8487 04:48:03.245414 DQ Delay:
8488 04:48:03.247988 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8489 04:48:03.251384 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8490 04:48:03.254709 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8491 04:48:03.258752 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8492 04:48:03.258863
8493 04:48:03.258955
8494 04:48:03.259041 ==
8495 04:48:03.261355 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 04:48:03.268627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 04:48:03.268730 ==
8498 04:48:03.268830
8499 04:48:03.268896
8500 04:48:03.268954 TX Vref Scan disable
8501 04:48:03.271437 == TX Byte 0 ==
8502 04:48:03.274858 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8503 04:48:03.278751 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8504 04:48:03.281778 == TX Byte 1 ==
8505 04:48:03.284826 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8506 04:48:03.288634 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8507 04:48:03.291821 ==
8508 04:48:03.291939 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 04:48:03.298412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 04:48:03.298511 ==
8511 04:48:03.311271
8512 04:48:03.314689 TX Vref early break, caculate TX vref
8513 04:48:03.317916 TX Vref=16, minBit 0, minWin=23, winSum=375
8514 04:48:03.321241 TX Vref=18, minBit 1, minWin=23, winSum=384
8515 04:48:03.324325 TX Vref=20, minBit 0, minWin=24, winSum=398
8516 04:48:03.328038 TX Vref=22, minBit 0, minWin=24, winSum=404
8517 04:48:03.331284 TX Vref=24, minBit 0, minWin=25, winSum=409
8518 04:48:03.338206 TX Vref=26, minBit 0, minWin=25, winSum=424
8519 04:48:03.341278 TX Vref=28, minBit 1, minWin=25, winSum=427
8520 04:48:03.344723 TX Vref=30, minBit 0, minWin=25, winSum=422
8521 04:48:03.348058 TX Vref=32, minBit 6, minWin=24, winSum=412
8522 04:48:03.351432 TX Vref=34, minBit 6, minWin=24, winSum=405
8523 04:48:03.354803 TX Vref=36, minBit 2, minWin=23, winSum=391
8524 04:48:03.361515 [TxChooseVref] Worse bit 1, Min win 25, Win sum 427, Final Vref 28
8525 04:48:03.361621
8526 04:48:03.364880 Final TX Range 0 Vref 28
8527 04:48:03.364968
8528 04:48:03.365033 ==
8529 04:48:03.368111 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 04:48:03.370819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 04:48:03.370905 ==
8532 04:48:03.370970
8533 04:48:03.371030
8534 04:48:03.374197 TX Vref Scan disable
8535 04:48:03.381152 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8536 04:48:03.381252 == TX Byte 0 ==
8537 04:48:03.384124 u2DelayCellOfst[0]=16 cells (5 PI)
8538 04:48:03.387983 u2DelayCellOfst[1]=10 cells (3 PI)
8539 04:48:03.391347 u2DelayCellOfst[2]=0 cells (0 PI)
8540 04:48:03.394383 u2DelayCellOfst[3]=6 cells (2 PI)
8541 04:48:03.397391 u2DelayCellOfst[4]=10 cells (3 PI)
8542 04:48:03.400754 u2DelayCellOfst[5]=16 cells (5 PI)
8543 04:48:03.404066 u2DelayCellOfst[6]=16 cells (5 PI)
8544 04:48:03.407414 u2DelayCellOfst[7]=6 cells (2 PI)
8545 04:48:03.411153 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8546 04:48:03.414299 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8547 04:48:03.417355 == TX Byte 1 ==
8548 04:48:03.420726 u2DelayCellOfst[8]=0 cells (0 PI)
8549 04:48:03.420816 u2DelayCellOfst[9]=3 cells (1 PI)
8550 04:48:03.423788 u2DelayCellOfst[10]=13 cells (4 PI)
8551 04:48:03.427183 u2DelayCellOfst[11]=6 cells (2 PI)
8552 04:48:03.430896 u2DelayCellOfst[12]=16 cells (5 PI)
8553 04:48:03.434232 u2DelayCellOfst[13]=16 cells (5 PI)
8554 04:48:03.437356 u2DelayCellOfst[14]=20 cells (6 PI)
8555 04:48:03.440487 u2DelayCellOfst[15]=20 cells (6 PI)
8556 04:48:03.447012 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8557 04:48:03.450703 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8558 04:48:03.450809 DramC Write-DBI on
8559 04:48:03.450877 ==
8560 04:48:03.453998 Dram Type= 6, Freq= 0, CH_1, rank 0
8561 04:48:03.460508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8562 04:48:03.460609 ==
8563 04:48:03.460676
8564 04:48:03.460737
8565 04:48:03.460793 TX Vref Scan disable
8566 04:48:03.464508 == TX Byte 0 ==
8567 04:48:03.467822 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8568 04:48:03.471103 == TX Byte 1 ==
8569 04:48:03.474793 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8570 04:48:03.474882 DramC Write-DBI off
8571 04:48:03.478098
8572 04:48:03.478182 [DATLAT]
8573 04:48:03.478247 Freq=1600, CH1 RK0
8574 04:48:03.478308
8575 04:48:03.481405 DATLAT Default: 0xf
8576 04:48:03.481487 0, 0xFFFF, sum = 0
8577 04:48:03.484697 1, 0xFFFF, sum = 0
8578 04:48:03.484781 2, 0xFFFF, sum = 0
8579 04:48:03.488206 3, 0xFFFF, sum = 0
8580 04:48:03.491464 4, 0xFFFF, sum = 0
8581 04:48:03.491550 5, 0xFFFF, sum = 0
8582 04:48:03.494533 6, 0xFFFF, sum = 0
8583 04:48:03.494618 7, 0xFFFF, sum = 0
8584 04:48:03.497725 8, 0xFFFF, sum = 0
8585 04:48:03.497812 9, 0xFFFF, sum = 0
8586 04:48:03.500894 10, 0xFFFF, sum = 0
8587 04:48:03.500979 11, 0xFFFF, sum = 0
8588 04:48:03.503982 12, 0xFFFF, sum = 0
8589 04:48:03.504094 13, 0xFFFF, sum = 0
8590 04:48:03.507881 14, 0x0, sum = 1
8591 04:48:03.507993 15, 0x0, sum = 2
8592 04:48:03.511033 16, 0x0, sum = 3
8593 04:48:03.511144 17, 0x0, sum = 4
8594 04:48:03.514495 best_step = 15
8595 04:48:03.514580
8596 04:48:03.514644 ==
8597 04:48:03.517772 Dram Type= 6, Freq= 0, CH_1, rank 0
8598 04:48:03.520906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8599 04:48:03.520992 ==
8600 04:48:03.521061 RX Vref Scan: 1
8601 04:48:03.524141
8602 04:48:03.524257 Set Vref Range= 24 -> 127
8603 04:48:03.524357
8604 04:48:03.527418 RX Vref 24 -> 127, step: 1
8605 04:48:03.527488
8606 04:48:03.531280 RX Delay 27 -> 252, step: 4
8607 04:48:03.531353
8608 04:48:03.534333 Set Vref, RX VrefLevel [Byte0]: 24
8609 04:48:03.537417 [Byte1]: 24
8610 04:48:03.537528
8611 04:48:03.541149 Set Vref, RX VrefLevel [Byte0]: 25
8612 04:48:03.544012 [Byte1]: 25
8613 04:48:03.544122
8614 04:48:03.547237 Set Vref, RX VrefLevel [Byte0]: 26
8615 04:48:03.550976 [Byte1]: 26
8616 04:48:03.554535
8617 04:48:03.554653 Set Vref, RX VrefLevel [Byte0]: 27
8618 04:48:03.558176 [Byte1]: 27
8619 04:48:03.562047
8620 04:48:03.562138 Set Vref, RX VrefLevel [Byte0]: 28
8621 04:48:03.565480 [Byte1]: 28
8622 04:48:03.569364
8623 04:48:03.569476 Set Vref, RX VrefLevel [Byte0]: 29
8624 04:48:03.572772 [Byte1]: 29
8625 04:48:03.577299
8626 04:48:03.577415 Set Vref, RX VrefLevel [Byte0]: 30
8627 04:48:03.580457 [Byte1]: 30
8628 04:48:03.584470
8629 04:48:03.584560 Set Vref, RX VrefLevel [Byte0]: 31
8630 04:48:03.587806 [Byte1]: 31
8631 04:48:03.592437
8632 04:48:03.592552 Set Vref, RX VrefLevel [Byte0]: 32
8633 04:48:03.595763 [Byte1]: 32
8634 04:48:03.599598
8635 04:48:03.599688 Set Vref, RX VrefLevel [Byte0]: 33
8636 04:48:03.603356 [Byte1]: 33
8637 04:48:03.607070
8638 04:48:03.607162 Set Vref, RX VrefLevel [Byte0]: 34
8639 04:48:03.610724 [Byte1]: 34
8640 04:48:03.614962
8641 04:48:03.615085 Set Vref, RX VrefLevel [Byte0]: 35
8642 04:48:03.618368 [Byte1]: 35
8643 04:48:03.622477
8644 04:48:03.622563 Set Vref, RX VrefLevel [Byte0]: 36
8645 04:48:03.625650 [Byte1]: 36
8646 04:48:03.630045
8647 04:48:03.630138 Set Vref, RX VrefLevel [Byte0]: 37
8648 04:48:03.633280 [Byte1]: 37
8649 04:48:03.637306
8650 04:48:03.637394 Set Vref, RX VrefLevel [Byte0]: 38
8651 04:48:03.641056 [Byte1]: 38
8652 04:48:03.645127
8653 04:48:03.645215 Set Vref, RX VrefLevel [Byte0]: 39
8654 04:48:03.648428 [Byte1]: 39
8655 04:48:03.652223
8656 04:48:03.652354 Set Vref, RX VrefLevel [Byte0]: 40
8657 04:48:03.655880 [Byte1]: 40
8658 04:48:03.660102
8659 04:48:03.660191 Set Vref, RX VrefLevel [Byte0]: 41
8660 04:48:03.663368 [Byte1]: 41
8661 04:48:03.667654
8662 04:48:03.667744 Set Vref, RX VrefLevel [Byte0]: 42
8663 04:48:03.670708 [Byte1]: 42
8664 04:48:03.675052
8665 04:48:03.675143 Set Vref, RX VrefLevel [Byte0]: 43
8666 04:48:03.678679 [Byte1]: 43
8667 04:48:03.682955
8668 04:48:03.683049 Set Vref, RX VrefLevel [Byte0]: 44
8669 04:48:03.685945 [Byte1]: 44
8670 04:48:03.690451
8671 04:48:03.690543 Set Vref, RX VrefLevel [Byte0]: 45
8672 04:48:03.693866 [Byte1]: 45
8673 04:48:03.697873
8674 04:48:03.697987 Set Vref, RX VrefLevel [Byte0]: 46
8675 04:48:03.701343 [Byte1]: 46
8676 04:48:03.705179
8677 04:48:03.705293 Set Vref, RX VrefLevel [Byte0]: 47
8678 04:48:03.708416 [Byte1]: 47
8679 04:48:03.712956
8680 04:48:03.713048 Set Vref, RX VrefLevel [Byte0]: 48
8681 04:48:03.716198 [Byte1]: 48
8682 04:48:03.720513
8683 04:48:03.720600 Set Vref, RX VrefLevel [Byte0]: 49
8684 04:48:03.723360 [Byte1]: 49
8685 04:48:03.727891
8686 04:48:03.727981 Set Vref, RX VrefLevel [Byte0]: 50
8687 04:48:03.731223 [Byte1]: 50
8688 04:48:03.735440
8689 04:48:03.735527 Set Vref, RX VrefLevel [Byte0]: 51
8690 04:48:03.738574 [Byte1]: 51
8691 04:48:03.743071
8692 04:48:03.743157 Set Vref, RX VrefLevel [Byte0]: 52
8693 04:48:03.746337 [Byte1]: 52
8694 04:48:03.750212
8695 04:48:03.750303 Set Vref, RX VrefLevel [Byte0]: 53
8696 04:48:03.753701 [Byte1]: 53
8697 04:48:03.757737
8698 04:48:03.757826 Set Vref, RX VrefLevel [Byte0]: 54
8699 04:48:03.760965 [Byte1]: 54
8700 04:48:03.765892
8701 04:48:03.765984 Set Vref, RX VrefLevel [Byte0]: 55
8702 04:48:03.768562 [Byte1]: 55
8703 04:48:03.772904
8704 04:48:03.772995 Set Vref, RX VrefLevel [Byte0]: 56
8705 04:48:03.776416 [Byte1]: 56
8706 04:48:03.780939
8707 04:48:03.781041 Set Vref, RX VrefLevel [Byte0]: 57
8708 04:48:03.784108 [Byte1]: 57
8709 04:48:03.788503
8710 04:48:03.788595 Set Vref, RX VrefLevel [Byte0]: 58
8711 04:48:03.791519 [Byte1]: 58
8712 04:48:03.795317
8713 04:48:03.795406 Set Vref, RX VrefLevel [Byte0]: 59
8714 04:48:03.798756 [Byte1]: 59
8715 04:48:03.803361
8716 04:48:03.803458 Set Vref, RX VrefLevel [Byte0]: 60
8717 04:48:03.806665 [Byte1]: 60
8718 04:48:03.810835
8719 04:48:03.810927 Set Vref, RX VrefLevel [Byte0]: 61
8720 04:48:03.814039 [Byte1]: 61
8721 04:48:03.817920
8722 04:48:03.818018 Set Vref, RX VrefLevel [Byte0]: 62
8723 04:48:03.821254 [Byte1]: 62
8724 04:48:03.825740
8725 04:48:03.825829 Set Vref, RX VrefLevel [Byte0]: 63
8726 04:48:03.828905 [Byte1]: 63
8727 04:48:03.833148
8728 04:48:03.833239 Set Vref, RX VrefLevel [Byte0]: 64
8729 04:48:03.836913 [Byte1]: 64
8730 04:48:03.840990
8731 04:48:03.841077 Set Vref, RX VrefLevel [Byte0]: 65
8732 04:48:03.843880 [Byte1]: 65
8733 04:48:03.848210
8734 04:48:03.848326 Set Vref, RX VrefLevel [Byte0]: 66
8735 04:48:03.851504 [Byte1]: 66
8736 04:48:03.856226
8737 04:48:03.856363 Set Vref, RX VrefLevel [Byte0]: 67
8738 04:48:03.859425 [Byte1]: 67
8739 04:48:03.863439
8740 04:48:03.863529 Set Vref, RX VrefLevel [Byte0]: 68
8741 04:48:03.866809 [Byte1]: 68
8742 04:48:03.871147
8743 04:48:03.871236 Set Vref, RX VrefLevel [Byte0]: 69
8744 04:48:03.874453 [Byte1]: 69
8745 04:48:03.878491
8746 04:48:03.878581 Set Vref, RX VrefLevel [Byte0]: 70
8747 04:48:03.881720 [Byte1]: 70
8748 04:48:03.886226
8749 04:48:03.886317 Set Vref, RX VrefLevel [Byte0]: 71
8750 04:48:03.889354 [Byte1]: 71
8751 04:48:03.893469
8752 04:48:03.893559 Set Vref, RX VrefLevel [Byte0]: 72
8753 04:48:03.896983 [Byte1]: 72
8754 04:48:03.900877
8755 04:48:03.900969 Set Vref, RX VrefLevel [Byte0]: 73
8756 04:48:03.904174 [Byte1]: 73
8757 04:48:03.908507
8758 04:48:03.908596 Set Vref, RX VrefLevel [Byte0]: 74
8759 04:48:03.912096 [Byte1]: 74
8760 04:48:03.916029
8761 04:48:03.916121 Set Vref, RX VrefLevel [Byte0]: 75
8762 04:48:03.919332 [Byte1]: 75
8763 04:48:03.923846
8764 04:48:03.923936 Set Vref, RX VrefLevel [Byte0]: 76
8765 04:48:03.927199 [Byte1]: 76
8766 04:48:03.931192
8767 04:48:03.931279 Set Vref, RX VrefLevel [Byte0]: 77
8768 04:48:03.934616 [Byte1]: 77
8769 04:48:03.939036
8770 04:48:03.939129 Final RX Vref Byte 0 = 57 to rank0
8771 04:48:03.941966 Final RX Vref Byte 1 = 51 to rank0
8772 04:48:03.945853 Final RX Vref Byte 0 = 57 to rank1
8773 04:48:03.949152 Final RX Vref Byte 1 = 51 to rank1==
8774 04:48:03.952272 Dram Type= 6, Freq= 0, CH_1, rank 0
8775 04:48:03.955307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 04:48:03.958957 ==
8777 04:48:03.959049 DQS Delay:
8778 04:48:03.959117 DQS0 = 0, DQS1 = 0
8779 04:48:03.962423 DQM Delay:
8780 04:48:03.962507 DQM0 = 134, DQM1 = 130
8781 04:48:03.965686 DQ Delay:
8782 04:48:03.969155 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8783 04:48:03.972529 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
8784 04:48:03.975193 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8785 04:48:03.978996 DQ12 =136, DQ13 =136, DQ14 =140, DQ15 =140
8786 04:48:03.979085
8787 04:48:03.979152
8788 04:48:03.979212
8789 04:48:03.982220 [DramC_TX_OE_Calibration] TA2
8790 04:48:03.985641 Original DQ_B0 (3 6) =30, OEN = 27
8791 04:48:03.988860 Original DQ_B1 (3 6) =30, OEN = 27
8792 04:48:03.992117 24, 0x0, End_B0=24 End_B1=24
8793 04:48:03.992233 25, 0x0, End_B0=25 End_B1=25
8794 04:48:03.995451 26, 0x0, End_B0=26 End_B1=26
8795 04:48:03.998668 27, 0x0, End_B0=27 End_B1=27
8796 04:48:04.001897 28, 0x0, End_B0=28 End_B1=28
8797 04:48:04.001986 29, 0x0, End_B0=29 End_B1=29
8798 04:48:04.004963 30, 0x0, End_B0=30 End_B1=30
8799 04:48:04.008411 31, 0x4141, End_B0=30 End_B1=30
8800 04:48:04.012162 Byte0 end_step=30 best_step=27
8801 04:48:04.015424 Byte1 end_step=30 best_step=27
8802 04:48:04.018481 Byte0 TX OE(2T, 0.5T) = (3, 3)
8803 04:48:04.018569 Byte1 TX OE(2T, 0.5T) = (3, 3)
8804 04:48:04.022188
8805 04:48:04.022275
8806 04:48:04.028483 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8807 04:48:04.032111 CH1 RK0: MR19=303, MR18=1624
8808 04:48:04.038787 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8809 04:48:04.038891
8810 04:48:04.042057 ----->DramcWriteLeveling(PI) begin...
8811 04:48:04.042146 ==
8812 04:48:04.045334 Dram Type= 6, Freq= 0, CH_1, rank 1
8813 04:48:04.048497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 04:48:04.048585 ==
8815 04:48:04.051614 Write leveling (Byte 0): 24 => 24
8816 04:48:04.055241 Write leveling (Byte 1): 28 => 28
8817 04:48:04.058463 DramcWriteLeveling(PI) end<-----
8818 04:48:04.058554
8819 04:48:04.058620 ==
8820 04:48:04.061618 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 04:48:04.065391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 04:48:04.065484 ==
8823 04:48:04.068553 [Gating] SW mode calibration
8824 04:48:04.075379 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8825 04:48:04.081849 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8826 04:48:04.085090 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 04:48:04.088494 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 04:48:04.094967 1 4 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8829 04:48:04.098290 1 4 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
8830 04:48:04.101469 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 04:48:04.108060 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 04:48:04.111951 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 04:48:04.115078 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 04:48:04.121673 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 04:48:04.124908 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8836 04:48:04.127973 1 5 8 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 0)
8837 04:48:04.135078 1 5 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 1)
8838 04:48:04.138141 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 04:48:04.141904 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 04:48:04.147898 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 04:48:04.151207 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 04:48:04.155161 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 04:48:04.161195 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 04:48:04.164817 1 6 8 | B1->B0 | 3535 2323 | 1 0 | (1 1) (0 0)
8845 04:48:04.167817 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8846 04:48:04.174481 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 04:48:04.177590 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 04:48:04.180938 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 04:48:04.187487 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 04:48:04.190789 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 04:48:04.194135 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8852 04:48:04.200815 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8853 04:48:04.203998 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8854 04:48:04.207498 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8855 04:48:04.214060 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 04:48:04.217453 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 04:48:04.220738 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 04:48:04.227767 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 04:48:04.230685 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 04:48:04.234224 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 04:48:04.237406 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 04:48:04.244355 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 04:48:04.247523 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 04:48:04.250550 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 04:48:04.257318 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 04:48:04.260647 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 04:48:04.264064 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8868 04:48:04.271033 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8869 04:48:04.273957 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8870 04:48:04.277715 Total UI for P1: 0, mck2ui 16
8871 04:48:04.280890 best dqsien dly found for B1: ( 1, 9, 6)
8872 04:48:04.284457 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8873 04:48:04.287305 Total UI for P1: 0, mck2ui 16
8874 04:48:04.290668 best dqsien dly found for B0: ( 1, 9, 12)
8875 04:48:04.294000 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8876 04:48:04.297443 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8877 04:48:04.297536
8878 04:48:04.304027 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8879 04:48:04.307378 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8880 04:48:04.307473 [Gating] SW calibration Done
8881 04:48:04.310657 ==
8882 04:48:04.314045 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 04:48:04.317386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 04:48:04.317479 ==
8885 04:48:04.317546 RX Vref Scan: 0
8886 04:48:04.317607
8887 04:48:04.320774 RX Vref 0 -> 0, step: 1
8888 04:48:04.320859
8889 04:48:04.324075 RX Delay 0 -> 252, step: 8
8890 04:48:04.327344 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8891 04:48:04.330697 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8892 04:48:04.334060 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8893 04:48:04.341090 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8894 04:48:04.343838 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8895 04:48:04.347718 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8896 04:48:04.350854 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8897 04:48:04.353945 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8898 04:48:04.360742 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8899 04:48:04.364518 iDelay=208, Bit 9, Center 127 (72 ~ 183) 112
8900 04:48:04.367291 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8901 04:48:04.370549 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8902 04:48:04.373849 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8903 04:48:04.380838 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8904 04:48:04.383854 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8905 04:48:04.387631 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8906 04:48:04.387730 ==
8907 04:48:04.390476 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 04:48:04.394096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 04:48:04.394186 ==
8910 04:48:04.397188 DQS Delay:
8911 04:48:04.397271 DQS0 = 0, DQS1 = 0
8912 04:48:04.400806 DQM Delay:
8913 04:48:04.400892 DQM0 = 136, DQM1 = 134
8914 04:48:04.400956 DQ Delay:
8915 04:48:04.407076 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8916 04:48:04.410861 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8917 04:48:04.414071 DQ8 =119, DQ9 =127, DQ10 =135, DQ11 =127
8918 04:48:04.417479 DQ12 =143, DQ13 =143, DQ14 =135, DQ15 =143
8919 04:48:04.417573
8920 04:48:04.417647
8921 04:48:04.417707 ==
8922 04:48:04.420860 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 04:48:04.423546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 04:48:04.423633 ==
8925 04:48:04.423698
8926 04:48:04.423758
8927 04:48:04.426873 TX Vref Scan disable
8928 04:48:04.430186 == TX Byte 0 ==
8929 04:48:04.433675 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8930 04:48:04.436949 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8931 04:48:04.440156 == TX Byte 1 ==
8932 04:48:04.443864 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8933 04:48:04.447159 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8934 04:48:04.447253 ==
8935 04:48:04.450575 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 04:48:04.453714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 04:48:04.457008 ==
8938 04:48:04.469809
8939 04:48:04.472582 TX Vref early break, caculate TX vref
8940 04:48:04.476407 TX Vref=16, minBit 0, minWin=23, winSum=381
8941 04:48:04.479402 TX Vref=18, minBit 10, minWin=23, winSum=392
8942 04:48:04.482394 TX Vref=20, minBit 1, minWin=24, winSum=396
8943 04:48:04.486401 TX Vref=22, minBit 0, minWin=25, winSum=410
8944 04:48:04.489522 TX Vref=24, minBit 0, minWin=25, winSum=416
8945 04:48:04.495681 TX Vref=26, minBit 0, minWin=26, winSum=424
8946 04:48:04.499131 TX Vref=28, minBit 0, minWin=26, winSum=427
8947 04:48:04.502542 TX Vref=30, minBit 6, minWin=25, winSum=422
8948 04:48:04.505656 TX Vref=32, minBit 0, minWin=25, winSum=413
8949 04:48:04.509227 TX Vref=34, minBit 0, minWin=25, winSum=406
8950 04:48:04.512414 TX Vref=36, minBit 0, minWin=23, winSum=392
8951 04:48:04.519284 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8952 04:48:04.519394
8953 04:48:04.522226 Final TX Range 0 Vref 28
8954 04:48:04.522312
8955 04:48:04.522377 ==
8956 04:48:04.525869 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 04:48:04.529122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 04:48:04.529211 ==
8959 04:48:04.529277
8960 04:48:04.532423
8961 04:48:04.532507 TX Vref Scan disable
8962 04:48:04.539136 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8963 04:48:04.539234 == TX Byte 0 ==
8964 04:48:04.542440 u2DelayCellOfst[0]=16 cells (5 PI)
8965 04:48:04.545892 u2DelayCellOfst[1]=13 cells (4 PI)
8966 04:48:04.548985 u2DelayCellOfst[2]=0 cells (0 PI)
8967 04:48:04.552094 u2DelayCellOfst[3]=6 cells (2 PI)
8968 04:48:04.555403 u2DelayCellOfst[4]=10 cells (3 PI)
8969 04:48:04.558686 u2DelayCellOfst[5]=16 cells (5 PI)
8970 04:48:04.562112 u2DelayCellOfst[6]=20 cells (6 PI)
8971 04:48:04.565355 u2DelayCellOfst[7]=6 cells (2 PI)
8972 04:48:04.569168 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8973 04:48:04.572067 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8974 04:48:04.575322 == TX Byte 1 ==
8975 04:48:04.578716 u2DelayCellOfst[8]=0 cells (0 PI)
8976 04:48:04.581988 u2DelayCellOfst[9]=3 cells (1 PI)
8977 04:48:04.582078 u2DelayCellOfst[10]=10 cells (3 PI)
8978 04:48:04.585416 u2DelayCellOfst[11]=6 cells (2 PI)
8979 04:48:04.588504 u2DelayCellOfst[12]=13 cells (4 PI)
8980 04:48:04.592231 u2DelayCellOfst[13]=16 cells (5 PI)
8981 04:48:04.595758 u2DelayCellOfst[14]=16 cells (5 PI)
8982 04:48:04.598894 u2DelayCellOfst[15]=16 cells (5 PI)
8983 04:48:04.605726 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8984 04:48:04.609051 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8985 04:48:04.609147 DramC Write-DBI on
8986 04:48:04.609214 ==
8987 04:48:04.612140 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 04:48:04.618432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 04:48:04.618533 ==
8990 04:48:04.618602
8991 04:48:04.618663
8992 04:48:04.618723 TX Vref Scan disable
8993 04:48:04.622650 == TX Byte 0 ==
8994 04:48:04.625863 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8995 04:48:04.629675 == TX Byte 1 ==
8996 04:48:04.632816 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8997 04:48:04.632909 DramC Write-DBI off
8998 04:48:04.635974
8999 04:48:04.636058 [DATLAT]
9000 04:48:04.636124 Freq=1600, CH1 RK1
9001 04:48:04.636186
9002 04:48:04.639217 DATLAT Default: 0xf
9003 04:48:04.639302 0, 0xFFFF, sum = 0
9004 04:48:04.642600 1, 0xFFFF, sum = 0
9005 04:48:04.642686 2, 0xFFFF, sum = 0
9006 04:48:04.645847 3, 0xFFFF, sum = 0
9007 04:48:04.649767 4, 0xFFFF, sum = 0
9008 04:48:04.649861 5, 0xFFFF, sum = 0
9009 04:48:04.652995 6, 0xFFFF, sum = 0
9010 04:48:04.653089 7, 0xFFFF, sum = 0
9011 04:48:04.656033 8, 0xFFFF, sum = 0
9012 04:48:04.656121 9, 0xFFFF, sum = 0
9013 04:48:04.659280 10, 0xFFFF, sum = 0
9014 04:48:04.659370 11, 0xFFFF, sum = 0
9015 04:48:04.662629 12, 0xFFFF, sum = 0
9016 04:48:04.662716 13, 0xFFFF, sum = 0
9017 04:48:04.665786 14, 0x0, sum = 1
9018 04:48:04.665872 15, 0x0, sum = 2
9019 04:48:04.669141 16, 0x0, sum = 3
9020 04:48:04.669227 17, 0x0, sum = 4
9021 04:48:04.672486 best_step = 15
9022 04:48:04.672571
9023 04:48:04.672638 ==
9024 04:48:04.675826 Dram Type= 6, Freq= 0, CH_1, rank 1
9025 04:48:04.679375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9026 04:48:04.679465 ==
9027 04:48:04.682614 RX Vref Scan: 0
9028 04:48:04.682701
9029 04:48:04.682767 RX Vref 0 -> 0, step: 1
9030 04:48:04.682829
9031 04:48:04.685715 RX Delay 19 -> 252, step: 4
9032 04:48:04.689324 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9033 04:48:04.695979 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9034 04:48:04.699157 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9035 04:48:04.702162 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9036 04:48:04.705700 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9037 04:48:04.708942 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9038 04:48:04.712061 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9039 04:48:04.718745 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9040 04:48:04.722139 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9041 04:48:04.725442 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
9042 04:48:04.728502 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9043 04:48:04.735068 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9044 04:48:04.738863 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9045 04:48:04.741939 iDelay=195, Bit 13, Center 136 (87 ~ 186) 100
9046 04:48:04.744992 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9047 04:48:04.748816 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9048 04:48:04.752094 ==
9049 04:48:04.755703 Dram Type= 6, Freq= 0, CH_1, rank 1
9050 04:48:04.758237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9051 04:48:04.758328 ==
9052 04:48:04.758399 DQS Delay:
9053 04:48:04.762057 DQS0 = 0, DQS1 = 0
9054 04:48:04.762145 DQM Delay:
9055 04:48:04.765269 DQM0 = 134, DQM1 = 130
9056 04:48:04.765359 DQ Delay:
9057 04:48:04.768605 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9058 04:48:04.771929 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9059 04:48:04.775269 DQ8 =116, DQ9 =120, DQ10 =130, DQ11 =126
9060 04:48:04.778544 DQ12 =140, DQ13 =136, DQ14 =136, DQ15 =138
9061 04:48:04.778636
9062 04:48:04.778701
9063 04:48:04.778762
9064 04:48:04.781920 [DramC_TX_OE_Calibration] TA2
9065 04:48:04.785254 Original DQ_B0 (3 6) =30, OEN = 27
9066 04:48:04.788412 Original DQ_B1 (3 6) =30, OEN = 27
9067 04:48:04.792025 24, 0x0, End_B0=24 End_B1=24
9068 04:48:04.795296 25, 0x0, End_B0=25 End_B1=25
9069 04:48:04.795392 26, 0x0, End_B0=26 End_B1=26
9070 04:48:04.798597 27, 0x0, End_B0=27 End_B1=27
9071 04:48:04.801928 28, 0x0, End_B0=28 End_B1=28
9072 04:48:04.805175 29, 0x0, End_B0=29 End_B1=29
9073 04:48:04.805271 30, 0x0, End_B0=30 End_B1=30
9074 04:48:04.808649 31, 0x4545, End_B0=30 End_B1=30
9075 04:48:04.811831 Byte0 end_step=30 best_step=27
9076 04:48:04.814977 Byte1 end_step=30 best_step=27
9077 04:48:04.817991 Byte0 TX OE(2T, 0.5T) = (3, 3)
9078 04:48:04.821812 Byte1 TX OE(2T, 0.5T) = (3, 3)
9079 04:48:04.821906
9080 04:48:04.821972
9081 04:48:04.828076 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
9082 04:48:04.831729 CH1 RK1: MR19=303, MR18=2409
9083 04:48:04.838475 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
9084 04:48:04.841517 [RxdqsGatingPostProcess] freq 1600
9085 04:48:04.845097 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9086 04:48:04.848326 best DQS0 dly(2T, 0.5T) = (1, 1)
9087 04:48:04.851486 best DQS1 dly(2T, 0.5T) = (1, 1)
9088 04:48:04.854718 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9089 04:48:04.857958 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9090 04:48:04.861257 best DQS0 dly(2T, 0.5T) = (1, 1)
9091 04:48:04.865182 best DQS1 dly(2T, 0.5T) = (1, 1)
9092 04:48:04.868236 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9093 04:48:04.871570 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9094 04:48:04.874945 Pre-setting of DQS Precalculation
9095 04:48:04.878315 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9096 04:48:04.887779 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9097 04:48:04.894398 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9098 04:48:04.894538
9099 04:48:04.894610
9100 04:48:04.897528 [Calibration Summary] 3200 Mbps
9101 04:48:04.897613 CH 0, Rank 0
9102 04:48:04.901251 SW Impedance : PASS
9103 04:48:04.901343 DUTY Scan : NO K
9104 04:48:04.904477 ZQ Calibration : PASS
9105 04:48:04.907775 Jitter Meter : NO K
9106 04:48:04.907861 CBT Training : PASS
9107 04:48:04.911143 Write leveling : PASS
9108 04:48:04.914519 RX DQS gating : PASS
9109 04:48:04.914606 RX DQ/DQS(RDDQC) : PASS
9110 04:48:04.917768 TX DQ/DQS : PASS
9111 04:48:04.917852 RX DATLAT : PASS
9112 04:48:04.920997 RX DQ/DQS(Engine): PASS
9113 04:48:04.924117 TX OE : PASS
9114 04:48:04.924206 All Pass.
9115 04:48:04.924271
9116 04:48:04.924406 CH 0, Rank 1
9117 04:48:04.927993 SW Impedance : PASS
9118 04:48:04.931376 DUTY Scan : NO K
9119 04:48:04.931463 ZQ Calibration : PASS
9120 04:48:04.934621 Jitter Meter : NO K
9121 04:48:04.937495 CBT Training : PASS
9122 04:48:04.937580 Write leveling : PASS
9123 04:48:04.941002 RX DQS gating : PASS
9124 04:48:04.944206 RX DQ/DQS(RDDQC) : PASS
9125 04:48:04.944354 TX DQ/DQS : PASS
9126 04:48:04.947999 RX DATLAT : PASS
9127 04:48:04.951029 RX DQ/DQS(Engine): PASS
9128 04:48:04.951116 TX OE : PASS
9129 04:48:04.954113 All Pass.
9130 04:48:04.954203
9131 04:48:04.954269 CH 1, Rank 0
9132 04:48:04.957753 SW Impedance : PASS
9133 04:48:04.957841 DUTY Scan : NO K
9134 04:48:04.960994 ZQ Calibration : PASS
9135 04:48:04.964133 Jitter Meter : NO K
9136 04:48:04.964247 CBT Training : PASS
9137 04:48:04.967415 Write leveling : PASS
9138 04:48:04.967500 RX DQS gating : PASS
9139 04:48:04.971259 RX DQ/DQS(RDDQC) : PASS
9140 04:48:04.974469 TX DQ/DQS : PASS
9141 04:48:04.974559 RX DATLAT : PASS
9142 04:48:04.977729 RX DQ/DQS(Engine): PASS
9143 04:48:04.981120 TX OE : PASS
9144 04:48:04.981208 All Pass.
9145 04:48:04.981274
9146 04:48:04.981334 CH 1, Rank 1
9147 04:48:04.984481 SW Impedance : PASS
9148 04:48:04.987962 DUTY Scan : NO K
9149 04:48:04.988048 ZQ Calibration : PASS
9150 04:48:04.990486 Jitter Meter : NO K
9151 04:48:04.993898 CBT Training : PASS
9152 04:48:04.993986 Write leveling : PASS
9153 04:48:04.997844 RX DQS gating : PASS
9154 04:48:05.001053 RX DQ/DQS(RDDQC) : PASS
9155 04:48:05.001144 TX DQ/DQS : PASS
9156 04:48:05.004434 RX DATLAT : PASS
9157 04:48:05.007578 RX DQ/DQS(Engine): PASS
9158 04:48:05.007691 TX OE : PASS
9159 04:48:05.010599 All Pass.
9160 04:48:05.010685
9161 04:48:05.010750 DramC Write-DBI on
9162 04:48:05.013762 PER_BANK_REFRESH: Hybrid Mode
9163 04:48:05.013847 TX_TRACKING: ON
9164 04:48:05.024406 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9165 04:48:05.033850 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9166 04:48:05.040597 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9167 04:48:05.043892 [FAST_K] Save calibration result to emmc
9168 04:48:05.047133 sync common calibartion params.
9169 04:48:05.047224 sync cbt_mode0:1, 1:1
9170 04:48:05.050373 dram_init: ddr_geometry: 2
9171 04:48:05.053903 dram_init: ddr_geometry: 2
9172 04:48:05.053999 dram_init: ddr_geometry: 2
9173 04:48:05.056782 0:dram_rank_size:100000000
9174 04:48:05.060524 1:dram_rank_size:100000000
9175 04:48:05.067286 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9176 04:48:05.067428 DFS_SHUFFLE_HW_MODE: ON
9177 04:48:05.070330 dramc_set_vcore_voltage set vcore to 725000
9178 04:48:05.073384 Read voltage for 1600, 0
9179 04:48:05.073484 Vio18 = 0
9180 04:48:05.077015 Vcore = 725000
9181 04:48:05.077104 Vdram = 0
9182 04:48:05.077170 Vddq = 0
9183 04:48:05.080691 Vmddr = 0
9184 04:48:05.080775 switch to 3200 Mbps bootup
9185 04:48:05.083697 [DramcRunTimeConfig]
9186 04:48:05.083783 PHYPLL
9187 04:48:05.087160 DPM_CONTROL_AFTERK: ON
9188 04:48:05.087245 PER_BANK_REFRESH: ON
9189 04:48:05.090043 REFRESH_OVERHEAD_REDUCTION: ON
9190 04:48:05.093385 CMD_PICG_NEW_MODE: OFF
9191 04:48:05.093475 XRTWTW_NEW_MODE: ON
9192 04:48:05.096870 XRTRTR_NEW_MODE: ON
9193 04:48:05.096968 TX_TRACKING: ON
9194 04:48:05.100159 RDSEL_TRACKING: OFF
9195 04:48:05.103415 DQS Precalculation for DVFS: ON
9196 04:48:05.103500 RX_TRACKING: OFF
9197 04:48:05.106833 HW_GATING DBG: ON
9198 04:48:05.106917 ZQCS_ENABLE_LP4: ON
9199 04:48:05.110218 RX_PICG_NEW_MODE: ON
9200 04:48:05.110302 TX_PICG_NEW_MODE: ON
9201 04:48:05.113626 ENABLE_RX_DCM_DPHY: ON
9202 04:48:05.116789 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9203 04:48:05.119799 DUMMY_READ_FOR_TRACKING: OFF
9204 04:48:05.119887 !!! SPM_CONTROL_AFTERK: OFF
9205 04:48:05.123703 !!! SPM could not control APHY
9206 04:48:05.126783 IMPEDANCE_TRACKING: ON
9207 04:48:05.126876 TEMP_SENSOR: ON
9208 04:48:05.130060 HW_SAVE_FOR_SR: OFF
9209 04:48:05.133753 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9210 04:48:05.137048 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9211 04:48:05.137142 Read ODT Tracking: ON
9212 04:48:05.140238 Refresh Rate DeBounce: ON
9213 04:48:05.143595 DFS_NO_QUEUE_FLUSH: ON
9214 04:48:05.146819 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9215 04:48:05.146907 ENABLE_DFS_RUNTIME_MRW: OFF
9216 04:48:05.150182 DDR_RESERVE_NEW_MODE: ON
9217 04:48:05.153516 MR_CBT_SWITCH_FREQ: ON
9218 04:48:05.153609 =========================
9219 04:48:05.173806 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9220 04:48:05.176868 dram_init: ddr_geometry: 2
9221 04:48:05.195166 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9222 04:48:05.198734 dram_init: dram init end (result: 0)
9223 04:48:05.204938 DRAM-K: Full calibration passed in 24516 msecs
9224 04:48:05.208312 MRC: failed to locate region type 0.
9225 04:48:05.208428 DRAM rank0 size:0x100000000,
9226 04:48:05.211651 DRAM rank1 size=0x100000000
9227 04:48:05.221792 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9228 04:48:05.228858 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9229 04:48:05.235132 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9230 04:48:05.241497 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9231 04:48:05.245365 DRAM rank0 size:0x100000000,
9232 04:48:05.248633 DRAM rank1 size=0x100000000
9233 04:48:05.248727 CBMEM:
9234 04:48:05.251919 IMD: root @ 0xfffff000 254 entries.
9235 04:48:05.255507 IMD: root @ 0xffffec00 62 entries.
9236 04:48:05.258702 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9237 04:48:05.262116 WARNING: RO_VPD is uninitialized or empty.
9238 04:48:05.268519 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9239 04:48:05.275235 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9240 04:48:05.288013 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9241 04:48:05.299515 BS: romstage times (exec / console): total (unknown) / 24037 ms
9242 04:48:05.299649
9243 04:48:05.299719
9244 04:48:05.309114 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9245 04:48:05.312495 ARM64: Exception handlers installed.
9246 04:48:05.316218 ARM64: Testing exception
9247 04:48:05.319559 ARM64: Done test exception
9248 04:48:05.319652 Enumerating buses...
9249 04:48:05.322871 Show all devs... Before device enumeration.
9250 04:48:05.326233 Root Device: enabled 1
9251 04:48:05.329537 CPU_CLUSTER: 0: enabled 1
9252 04:48:05.329627 CPU: 00: enabled 1
9253 04:48:05.332769 Compare with tree...
9254 04:48:05.332856 Root Device: enabled 1
9255 04:48:05.336089 CPU_CLUSTER: 0: enabled 1
9256 04:48:05.339324 CPU: 00: enabled 1
9257 04:48:05.339411 Root Device scanning...
9258 04:48:05.342478 scan_static_bus for Root Device
9259 04:48:05.345733 CPU_CLUSTER: 0 enabled
9260 04:48:05.349221 scan_static_bus for Root Device done
9261 04:48:05.352455 scan_bus: bus Root Device finished in 8 msecs
9262 04:48:05.352577 done
9263 04:48:05.359424 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9264 04:48:05.362906 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9265 04:48:05.368847 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9266 04:48:05.371984 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9267 04:48:05.375828 Allocating resources...
9268 04:48:05.379028 Reading resources...
9269 04:48:05.382179 Root Device read_resources bus 0 link: 0
9270 04:48:05.382275 DRAM rank0 size:0x100000000,
9271 04:48:05.385435 DRAM rank1 size=0x100000000
9272 04:48:05.388726 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9273 04:48:05.391916 CPU: 00 missing read_resources
9274 04:48:05.398538 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9275 04:48:05.402218 Root Device read_resources bus 0 link: 0 done
9276 04:48:05.402323 Done reading resources.
9277 04:48:05.408548 Show resources in subtree (Root Device)...After reading.
9278 04:48:05.412074 Root Device child on link 0 CPU_CLUSTER: 0
9279 04:48:05.415251 CPU_CLUSTER: 0 child on link 0 CPU: 00
9280 04:48:05.425526 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9281 04:48:05.425657 CPU: 00
9282 04:48:05.428726 Root Device assign_resources, bus 0 link: 0
9283 04:48:05.431945 CPU_CLUSTER: 0 missing set_resources
9284 04:48:05.438578 Root Device assign_resources, bus 0 link: 0 done
9285 04:48:05.438691 Done setting resources.
9286 04:48:05.445364 Show resources in subtree (Root Device)...After assigning values.
9287 04:48:05.448684 Root Device child on link 0 CPU_CLUSTER: 0
9288 04:48:05.451951 CPU_CLUSTER: 0 child on link 0 CPU: 00
9289 04:48:05.462182 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9290 04:48:05.462313 CPU: 00
9291 04:48:05.464971 Done allocating resources.
9292 04:48:05.468435 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9293 04:48:05.471807 Enabling resources...
9294 04:48:05.471921 done.
9295 04:48:05.478404 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9296 04:48:05.478502 Initializing devices...
9297 04:48:05.481664 Root Device init
9298 04:48:05.481749 init hardware done!
9299 04:48:05.485529 0x00000018: ctrlr->caps
9300 04:48:05.488685 52.000 MHz: ctrlr->f_max
9301 04:48:05.488776 0.400 MHz: ctrlr->f_min
9302 04:48:05.492033 0x40ff8080: ctrlr->voltages
9303 04:48:05.492118 sclk: 390625
9304 04:48:05.495386 Bus Width = 1
9305 04:48:05.495470 sclk: 390625
9306 04:48:05.498656 Bus Width = 1
9307 04:48:05.498741 Early init status = 3
9308 04:48:05.505176 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9309 04:48:05.508266 in-header: 03 fc 00 00 01 00 00 00
9310 04:48:05.508399 in-data: 00
9311 04:48:05.515454 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9312 04:48:05.518537 in-header: 03 fd 00 00 00 00 00 00
9313 04:48:05.521703 in-data:
9314 04:48:05.525455 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9315 04:48:05.528605 in-header: 03 fc 00 00 01 00 00 00
9316 04:48:05.531596 in-data: 00
9317 04:48:05.534842 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9318 04:48:05.539264 in-header: 03 fd 00 00 00 00 00 00
9319 04:48:05.542857 in-data:
9320 04:48:05.546065 [SSUSB] Setting up USB HOST controller...
9321 04:48:05.549469 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9322 04:48:05.552741 [SSUSB] phy power-on done.
9323 04:48:05.556069 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9324 04:48:05.562614 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9325 04:48:05.566022 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9326 04:48:05.572782 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9327 04:48:05.579609 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9328 04:48:05.586196 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9329 04:48:05.592778 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9330 04:48:05.599469 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9331 04:48:05.602847 SPM: binary array size = 0x9dc
9332 04:48:05.606023 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9333 04:48:05.612672 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9334 04:48:05.619248 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9335 04:48:05.622338 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9336 04:48:05.626000 configure_display: Starting display init
9337 04:48:05.662788 anx7625_power_on_init: Init interface.
9338 04:48:05.665896 anx7625_disable_pd_protocol: Disabled PD feature.
9339 04:48:05.669243 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9340 04:48:05.697150 anx7625_start_dp_work: Secure OCM version=00
9341 04:48:05.700409 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9342 04:48:05.715221 sp_tx_get_edid_block: EDID Block = 1
9343 04:48:05.817452 Extracted contents:
9344 04:48:05.821486 header: 00 ff ff ff ff ff ff 00
9345 04:48:05.824611 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9346 04:48:05.827687 version: 01 04
9347 04:48:05.831007 basic params: 95 1f 11 78 0a
9348 04:48:05.834310 chroma info: 76 90 94 55 54 90 27 21 50 54
9349 04:48:05.837605 established: 00 00 00
9350 04:48:05.844684 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9351 04:48:05.847941 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9352 04:48:05.854200 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9353 04:48:05.860670 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9354 04:48:05.867297 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9355 04:48:05.871098 extensions: 00
9356 04:48:05.871207 checksum: fb
9357 04:48:05.871291
9358 04:48:05.874180 Manufacturer: IVO Model 57d Serial Number 0
9359 04:48:05.877738 Made week 0 of 2020
9360 04:48:05.877819 EDID version: 1.4
9361 04:48:05.880808 Digital display
9362 04:48:05.883949 6 bits per primary color channel
9363 04:48:05.884032 DisplayPort interface
9364 04:48:05.887376 Maximum image size: 31 cm x 17 cm
9365 04:48:05.890585 Gamma: 220%
9366 04:48:05.890666 Check DPMS levels
9367 04:48:05.893915 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9368 04:48:05.897076 First detailed timing is preferred timing
9369 04:48:05.900844 Established timings supported:
9370 04:48:05.903961 Standard timings supported:
9371 04:48:05.907051 Detailed timings
9372 04:48:05.910545 Hex of detail: 383680a07038204018303c0035ae10000019
9373 04:48:05.914079 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9374 04:48:05.920875 0780 0798 07c8 0820 hborder 0
9375 04:48:05.924267 0438 043b 0447 0458 vborder 0
9376 04:48:05.927047 -hsync -vsync
9377 04:48:05.927153 Did detailed timing
9378 04:48:05.933963 Hex of detail: 000000000000000000000000000000000000
9379 04:48:05.934072 Manufacturer-specified data, tag 0
9380 04:48:05.940723 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9381 04:48:05.943341 ASCII string: InfoVision
9382 04:48:05.946677 Hex of detail: 000000fe00523134304e574635205248200a
9383 04:48:05.949929 ASCII string: R140NWF5 RH
9384 04:48:05.950036 Checksum
9385 04:48:05.953745 Checksum: 0xfb (valid)
9386 04:48:05.957076 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9387 04:48:05.960298 DSI data_rate: 832800000 bps
9388 04:48:05.966676 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9389 04:48:05.970009 anx7625_parse_edid: pixelclock(138800).
9390 04:48:05.973422 hactive(1920), hsync(48), hfp(24), hbp(88)
9391 04:48:05.976849 vactive(1080), vsync(12), vfp(3), vbp(17)
9392 04:48:05.979867 anx7625_dsi_config: config dsi.
9393 04:48:05.987068 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9394 04:48:06.000106 anx7625_dsi_config: success to config DSI
9395 04:48:06.003425 anx7625_dp_start: MIPI phy setup OK.
9396 04:48:06.006834 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9397 04:48:06.009901 mtk_ddp_mode_set invalid vrefresh 60
9398 04:48:06.013114 main_disp_path_setup
9399 04:48:06.013198 ovl_layer_smi_id_en
9400 04:48:06.016311 ovl_layer_smi_id_en
9401 04:48:06.016433 ccorr_config
9402 04:48:06.016525 aal_config
9403 04:48:06.019559 gamma_config
9404 04:48:06.019641 postmask_config
9405 04:48:06.023010 dither_config
9406 04:48:06.026171 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9407 04:48:06.032995 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9408 04:48:06.036467 Root Device init finished in 551 msecs
9409 04:48:06.039490 CPU_CLUSTER: 0 init
9410 04:48:06.046464 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9411 04:48:06.049197 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9412 04:48:06.053331 APU_MBOX 0x190000b0 = 0x10001
9413 04:48:06.056449 APU_MBOX 0x190001b0 = 0x10001
9414 04:48:06.059633 APU_MBOX 0x190005b0 = 0x10001
9415 04:48:06.062641 APU_MBOX 0x190006b0 = 0x10001
9416 04:48:06.065989 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9417 04:48:06.078605 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9418 04:48:06.090935 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9419 04:48:06.097856 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9420 04:48:06.109084 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9421 04:48:06.118791 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9422 04:48:06.122131 CPU_CLUSTER: 0 init finished in 81 msecs
9423 04:48:06.125450 Devices initialized
9424 04:48:06.128576 Show all devs... After init.
9425 04:48:06.128666 Root Device: enabled 1
9426 04:48:06.131708 CPU_CLUSTER: 0: enabled 1
9427 04:48:06.135044 CPU: 00: enabled 1
9428 04:48:06.138168 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9429 04:48:06.141387 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9430 04:48:06.144676 ELOG: NV offset 0x57f000 size 0x1000
9431 04:48:06.152017 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9432 04:48:06.158218 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9433 04:48:06.161420 ELOG: Event(17) added with size 13 at 2024-02-04 04:45:24 UTC
9434 04:48:06.164728 out: cmd=0x121: 03 db 21 01 00 00 00 00
9435 04:48:06.169151 in-header: 03 a5 00 00 2c 00 00 00
9436 04:48:06.182042 in-data: ba 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9437 04:48:06.188622 ELOG: Event(A1) added with size 10 at 2024-02-04 04:45:25 UTC
9438 04:48:06.195443 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9439 04:48:06.202421 ELOG: Event(A0) added with size 9 at 2024-02-04 04:45:25 UTC
9440 04:48:06.205565 elog_add_boot_reason: Logged dev mode boot
9441 04:48:06.208941 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9442 04:48:06.212082 Finalize devices...
9443 04:48:06.212164 Devices finalized
9444 04:48:06.218647 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9445 04:48:06.222310 Writing coreboot table at 0xffe64000
9446 04:48:06.225689 0. 000000000010a000-0000000000113fff: RAMSTAGE
9447 04:48:06.229017 1. 0000000040000000-00000000400fffff: RAM
9448 04:48:06.232317 2. 0000000040100000-000000004032afff: RAMSTAGE
9449 04:48:06.238406 3. 000000004032b000-00000000545fffff: RAM
9450 04:48:06.242443 4. 0000000054600000-000000005465ffff: BL31
9451 04:48:06.245439 5. 0000000054660000-00000000ffe63fff: RAM
9452 04:48:06.252087 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9453 04:48:06.255346 7. 0000000100000000-000000023fffffff: RAM
9454 04:48:06.255438 Passing 5 GPIOs to payload:
9455 04:48:06.261583 NAME | PORT | POLARITY | VALUE
9456 04:48:06.264786 EC in RW | 0x000000aa | low | undefined
9457 04:48:06.271563 EC interrupt | 0x00000005 | low | undefined
9458 04:48:06.274706 TPM interrupt | 0x000000ab | high | undefined
9459 04:48:06.278221 SD card detect | 0x00000011 | high | undefined
9460 04:48:06.284879 speaker enable | 0x00000093 | high | undefined
9461 04:48:06.288041 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9462 04:48:06.291871 in-header: 03 f9 00 00 02 00 00 00
9463 04:48:06.291975 in-data: 02 00
9464 04:48:06.294618 ADC[4]: Raw value=904726 ID=7
9465 04:48:06.297991 ADC[3]: Raw value=213810 ID=1
9466 04:48:06.298074 RAM Code: 0x71
9467 04:48:06.301703 ADC[6]: Raw value=75332 ID=0
9468 04:48:06.304736 ADC[5]: Raw value=213441 ID=1
9469 04:48:06.304818 SKU Code: 0x1
9470 04:48:06.311494 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b313
9471 04:48:06.314766 coreboot table: 964 bytes.
9472 04:48:06.318104 IMD ROOT 0. 0xfffff000 0x00001000
9473 04:48:06.321148 IMD SMALL 1. 0xffffe000 0x00001000
9474 04:48:06.324593 RO MCACHE 2. 0xffffc000 0x00001104
9475 04:48:06.328186 CONSOLE 3. 0xfff7c000 0x00080000
9476 04:48:06.331478 FMAP 4. 0xfff7b000 0x00000452
9477 04:48:06.334717 TIME STAMP 5. 0xfff7a000 0x00000910
9478 04:48:06.338077 VBOOT WORK 6. 0xfff66000 0x00014000
9479 04:48:06.341355 RAMOOPS 7. 0xffe66000 0x00100000
9480 04:48:06.344428 COREBOOT 8. 0xffe64000 0x00002000
9481 04:48:06.344511 IMD small region:
9482 04:48:06.348153 IMD ROOT 0. 0xffffec00 0x00000400
9483 04:48:06.351150 VPD 1. 0xffffeb80 0x0000006c
9484 04:48:06.354802 MMC STATUS 2. 0xffffeb60 0x00000004
9485 04:48:06.361815 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9486 04:48:06.364460 Probing TPM: done!
9487 04:48:06.368155 Connected to device vid:did:rid of 1ae0:0028:00
9488 04:48:06.378065 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9489 04:48:06.381339 Initialized TPM device CR50 revision 0
9490 04:48:06.385102 Checking cr50 for pending updates
9491 04:48:06.388446 Reading cr50 TPM mode
9492 04:48:06.396681 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9493 04:48:06.403264 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9494 04:48:06.443578 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9495 04:48:06.447439 Checking segment from ROM address 0x40100000
9496 04:48:06.450700 Checking segment from ROM address 0x4010001c
9497 04:48:06.457372 Loading segment from ROM address 0x40100000
9498 04:48:06.457472 code (compression=0)
9499 04:48:06.464136 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9500 04:48:06.473929 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9501 04:48:06.474073 it's not compressed!
9502 04:48:06.480326 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9503 04:48:06.483709 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9504 04:48:06.504224 Loading segment from ROM address 0x4010001c
9505 04:48:06.504380 Entry Point 0x80000000
9506 04:48:06.507682 Loaded segments
9507 04:48:06.510877 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9508 04:48:06.517334 Jumping to boot code at 0x80000000(0xffe64000)
9509 04:48:06.523785 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9510 04:48:06.530649 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9511 04:48:06.538923 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9512 04:48:06.542234 Checking segment from ROM address 0x40100000
9513 04:48:06.545493 Checking segment from ROM address 0x4010001c
9514 04:48:06.551832 Loading segment from ROM address 0x40100000
9515 04:48:06.551924 code (compression=1)
9516 04:48:06.558833 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9517 04:48:06.568860 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9518 04:48:06.568968 using LZMA
9519 04:48:06.576770 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9520 04:48:06.583367 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9521 04:48:06.586997 Loading segment from ROM address 0x4010001c
9522 04:48:06.587089 Entry Point 0x54601000
9523 04:48:06.590111 Loaded segments
9524 04:48:06.593355 NOTICE: MT8192 bl31_setup
9525 04:48:06.600525 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9526 04:48:06.603710 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9527 04:48:06.607109 WARNING: region 0:
9528 04:48:06.610426 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 04:48:06.610512 WARNING: region 1:
9530 04:48:06.617466 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9531 04:48:06.620631 WARNING: region 2:
9532 04:48:06.624009 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9533 04:48:06.627029 WARNING: region 3:
9534 04:48:06.630320 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9535 04:48:06.633643 WARNING: region 4:
9536 04:48:06.640471 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9537 04:48:06.640563 WARNING: region 5:
9538 04:48:06.643779 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 04:48:06.647047 WARNING: region 6:
9540 04:48:06.650499 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 04:48:06.653819 WARNING: region 7:
9542 04:48:06.657180 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 04:48:06.663875 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9544 04:48:06.667370 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9545 04:48:06.670782 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9546 04:48:06.677088 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9547 04:48:06.680766 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9548 04:48:06.683757 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9549 04:48:06.690849 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9550 04:48:06.693806 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9551 04:48:06.700476 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9552 04:48:06.704023 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9553 04:48:06.707331 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9554 04:48:06.714105 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9555 04:48:06.717324 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9556 04:48:06.720966 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9557 04:48:06.727679 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9558 04:48:06.730951 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9559 04:48:06.734122 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9560 04:48:06.740807 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9561 04:48:06.744089 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9562 04:48:06.747457 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9563 04:48:06.754536 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9564 04:48:06.757896 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9565 04:48:06.764013 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9566 04:48:06.767412 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9567 04:48:06.770766 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9568 04:48:06.777769 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9569 04:48:06.780930 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9570 04:48:06.787769 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9571 04:48:06.791044 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9572 04:48:06.794099 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9573 04:48:06.800970 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9574 04:48:06.804420 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9575 04:48:06.807711 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9576 04:48:06.814447 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9577 04:48:06.817828 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9578 04:48:06.821505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9579 04:48:06.824692 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9580 04:48:06.831324 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9581 04:48:06.834799 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9582 04:48:06.838119 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9583 04:48:06.841137 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9584 04:48:06.844929 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9585 04:48:06.851517 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9586 04:48:06.854802 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9587 04:48:06.858257 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9588 04:48:06.864796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9589 04:48:06.868069 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9590 04:48:06.871445 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9591 04:48:06.874761 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9592 04:48:06.881457 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9593 04:48:06.884604 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9594 04:48:06.891288 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9595 04:48:06.894634 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9596 04:48:06.901302 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9597 04:48:06.904657 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9598 04:48:06.908471 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9599 04:48:06.914990 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9600 04:48:06.918041 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9601 04:48:06.924762 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9602 04:48:06.928034 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9603 04:48:06.934799 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9604 04:48:06.938626 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9605 04:48:06.941466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9606 04:48:06.948455 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9607 04:48:06.951612 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9608 04:48:06.958317 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9609 04:48:06.961693 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9610 04:48:06.968472 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9611 04:48:06.971781 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9612 04:48:06.975194 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9613 04:48:06.981885 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9614 04:48:06.984543 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9615 04:48:06.991717 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9616 04:48:06.995064 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9617 04:48:07.001886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9618 04:48:07.004990 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9619 04:48:07.008060 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9620 04:48:07.015381 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9621 04:48:07.018555 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9622 04:48:07.024756 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9623 04:48:07.028561 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9624 04:48:07.034791 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9625 04:48:07.038099 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9626 04:48:07.041499 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9627 04:48:07.048082 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9628 04:48:07.051394 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9629 04:48:07.058050 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9630 04:48:07.061917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9631 04:48:07.068130 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9632 04:48:07.071207 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9633 04:48:07.074893 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9634 04:48:07.081254 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9635 04:48:07.084880 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9636 04:48:07.091991 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9637 04:48:07.095311 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9638 04:48:07.101563 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9639 04:48:07.104990 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9640 04:48:07.108168 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9641 04:48:07.111679 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9642 04:48:07.118549 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9643 04:48:07.121868 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9644 04:48:07.125421 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9645 04:48:07.131764 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9646 04:48:07.135105 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9647 04:48:07.138811 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9648 04:48:07.145027 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9649 04:48:07.148281 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9650 04:48:07.154959 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9651 04:48:07.158313 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9652 04:48:07.162168 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9653 04:48:07.168722 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9654 04:48:07.171849 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9655 04:48:07.179132 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9656 04:48:07.182408 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9657 04:48:07.185160 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9658 04:48:07.192473 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9659 04:48:07.195571 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9660 04:48:07.199060 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9661 04:48:07.205722 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9662 04:48:07.209064 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9663 04:48:07.212323 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9664 04:48:07.215540 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9665 04:48:07.218807 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9666 04:48:07.225578 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9667 04:48:07.228719 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9668 04:48:07.235420 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9669 04:48:07.238761 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9670 04:48:07.241982 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9671 04:48:07.248764 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9672 04:48:07.252495 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9673 04:48:07.255317 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9674 04:48:07.262159 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9675 04:48:07.265485 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9676 04:48:07.272005 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9677 04:48:07.275270 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9678 04:48:07.278629 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9679 04:48:07.285314 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9680 04:48:07.288687 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9681 04:48:07.295383 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9682 04:48:07.298769 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9683 04:48:07.302347 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9684 04:48:07.308697 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9685 04:48:07.312066 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9686 04:48:07.315483 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9687 04:48:07.322185 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9688 04:48:07.325413 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9689 04:48:07.332483 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9690 04:48:07.335941 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9691 04:48:07.338957 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9692 04:48:07.345511 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9693 04:48:07.348709 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9694 04:48:07.352255 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9695 04:48:07.359441 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9696 04:48:07.362697 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9697 04:48:07.368868 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9698 04:48:07.372293 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9699 04:48:07.375936 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9700 04:48:07.382423 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9701 04:48:07.385765 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9702 04:48:07.392484 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9703 04:48:07.395874 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9704 04:48:07.399181 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9705 04:48:07.405774 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9706 04:48:07.409228 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9707 04:48:07.415686 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9708 04:48:07.418893 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9709 04:48:07.422338 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9710 04:48:07.428825 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9711 04:48:07.432126 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9712 04:48:07.435524 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9713 04:48:07.442010 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9714 04:48:07.445207 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9715 04:48:07.452491 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9716 04:48:07.455344 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9717 04:48:07.458518 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9718 04:48:07.465316 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9719 04:48:07.468828 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9720 04:48:07.475375 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9721 04:48:07.478760 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9722 04:48:07.482310 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9723 04:48:07.488377 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9724 04:48:07.491862 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9725 04:48:07.498169 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9726 04:48:07.501566 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9727 04:48:07.505006 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9728 04:48:07.511739 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9729 04:48:07.515067 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9730 04:48:07.521819 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9731 04:48:07.525173 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9732 04:48:07.527870 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9733 04:48:07.535026 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9734 04:48:07.538362 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9735 04:48:07.545106 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9736 04:48:07.548215 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9737 04:48:07.554947 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9738 04:48:07.558349 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9739 04:48:07.561517 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9740 04:48:07.568029 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9741 04:48:07.571447 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9742 04:48:07.577943 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9743 04:48:07.581069 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9744 04:48:07.584711 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9745 04:48:07.591052 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9746 04:48:07.594656 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9747 04:48:07.601062 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9748 04:48:07.604124 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9749 04:48:07.611387 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9750 04:48:07.614407 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9751 04:48:07.617382 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9752 04:48:07.624123 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9753 04:48:07.627463 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9754 04:48:07.634094 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9755 04:48:07.637403 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9756 04:48:07.643980 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9757 04:48:07.647187 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9758 04:48:07.651024 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9759 04:48:07.657755 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9760 04:48:07.660430 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9761 04:48:07.667142 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9762 04:48:07.670315 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9763 04:48:07.674112 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9764 04:48:07.680553 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9765 04:48:07.683647 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9766 04:48:07.690541 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9767 04:48:07.693844 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9768 04:48:07.700421 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9769 04:48:07.703680 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9770 04:48:07.707259 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9771 04:48:07.714107 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9772 04:48:07.717309 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9773 04:48:07.720426 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9774 04:48:07.723747 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9775 04:48:07.730561 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9776 04:48:07.733945 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9777 04:48:07.737067 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9778 04:48:07.743698 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9779 04:48:07.747037 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9780 04:48:07.750242 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9781 04:48:07.757031 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9782 04:48:07.760303 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9783 04:48:07.763725 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9784 04:48:07.770349 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9785 04:48:07.773677 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9786 04:48:07.780134 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9787 04:48:07.783512 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9788 04:48:07.786458 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9789 04:48:07.793647 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9790 04:48:07.796771 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9791 04:48:07.800040 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9792 04:48:07.806681 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9793 04:48:07.810029 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9794 04:48:07.816832 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9795 04:48:07.819897 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9796 04:48:07.823066 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9797 04:48:07.829958 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9798 04:48:07.833075 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9799 04:48:07.836468 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9800 04:48:07.843368 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9801 04:48:07.846171 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9802 04:48:07.849750 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9803 04:48:07.856514 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9804 04:48:07.859795 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9805 04:48:07.865998 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9806 04:48:07.869560 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9807 04:48:07.872766 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9808 04:48:07.879470 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9809 04:48:07.882835 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9810 04:48:07.886617 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9811 04:48:07.892866 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9812 04:48:07.896059 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9813 04:48:07.899291 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9814 04:48:07.903116 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9815 04:48:07.909700 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9816 04:48:07.912467 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9817 04:48:07.916427 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9818 04:48:07.919206 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9819 04:48:07.926327 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9820 04:48:07.929422 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9821 04:48:07.932795 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9822 04:48:07.936053 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9823 04:48:07.942545 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9824 04:48:07.945672 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9825 04:48:07.949471 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9826 04:48:07.956274 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9827 04:48:07.959345 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9828 04:48:07.965925 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9829 04:48:07.969059 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9830 04:48:07.972953 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9831 04:48:07.979384 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9832 04:48:07.982727 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9833 04:48:07.988907 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9834 04:48:07.992213 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9835 04:48:07.995539 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9836 04:48:08.002414 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9837 04:48:08.005926 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9838 04:48:08.012193 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9839 04:48:08.015610 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9840 04:48:08.018834 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9841 04:48:08.025398 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9842 04:48:08.028799 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9843 04:48:08.035591 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9844 04:48:08.038750 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9845 04:48:08.045391 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9846 04:48:08.048530 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9847 04:48:08.052620 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9848 04:48:08.058221 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9849 04:48:08.062058 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9850 04:48:08.068771 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9851 04:48:08.071969 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9852 04:48:08.078103 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9853 04:48:08.081454 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9854 04:48:08.084760 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9855 04:48:08.091424 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9856 04:48:08.094794 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9857 04:48:08.101421 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9858 04:48:08.104750 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9859 04:48:08.108059 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9860 04:48:08.114968 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9861 04:48:08.118096 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9862 04:48:08.124778 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9863 04:48:08.127500 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9864 04:48:08.131358 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9865 04:48:08.138026 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9866 04:48:08.141435 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9867 04:48:08.147866 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9868 04:48:08.151119 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9869 04:48:08.157509 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9870 04:48:08.161276 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9871 04:48:08.164410 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9872 04:48:08.171137 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9873 04:48:08.174477 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9874 04:48:08.181039 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9875 04:48:08.184302 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9876 04:48:08.187620 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9877 04:48:08.193846 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9878 04:48:08.197385 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9879 04:48:08.203762 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9880 04:48:08.207578 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9881 04:48:08.211027 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9882 04:48:08.217427 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9883 04:48:08.220563 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9884 04:48:08.226985 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9885 04:48:08.230681 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9886 04:48:08.236965 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9887 04:48:08.240436 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9888 04:48:08.243819 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9889 04:48:08.250809 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9890 04:48:08.254095 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9891 04:48:08.260627 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9892 04:48:08.263713 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9893 04:48:08.267021 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9894 04:48:08.274017 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9895 04:48:08.277107 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9896 04:48:08.283863 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9897 04:48:08.287213 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9898 04:48:08.290469 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9899 04:48:08.297230 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9900 04:48:08.300499 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9901 04:48:08.307031 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9902 04:48:08.310322 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9903 04:48:08.317045 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9904 04:48:08.320013 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9905 04:48:08.323629 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9906 04:48:08.330184 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9907 04:48:08.333594 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9908 04:48:08.340231 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9909 04:48:08.343138 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9910 04:48:08.350126 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9911 04:48:08.353537 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9912 04:48:08.356749 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9913 04:48:08.363859 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9914 04:48:08.366889 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9915 04:48:08.373466 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9916 04:48:08.376764 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9917 04:48:08.383663 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9918 04:48:08.386855 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9919 04:48:08.393241 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9920 04:48:08.396706 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9921 04:48:08.400042 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9922 04:48:08.406791 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9923 04:48:08.410126 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9924 04:48:08.416605 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9925 04:48:08.419919 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9926 04:48:08.426462 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9927 04:48:08.429763 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9928 04:48:08.433019 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9929 04:48:08.439880 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9930 04:48:08.442841 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9931 04:48:08.449826 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9932 04:48:08.453412 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9933 04:48:08.459676 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9934 04:48:08.463148 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9935 04:48:08.469355 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9936 04:48:08.472882 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9937 04:48:08.476568 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9938 04:48:08.483203 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9939 04:48:08.486238 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9940 04:48:08.492828 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9941 04:48:08.496651 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9942 04:48:08.503111 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9943 04:48:08.506457 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9944 04:48:08.509759 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9945 04:48:08.515777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9946 04:48:08.519684 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9947 04:48:08.526046 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9948 04:48:08.529373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9949 04:48:08.535849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9950 04:48:08.539102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9951 04:48:08.545738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9952 04:48:08.549019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9953 04:48:08.555588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9954 04:48:08.559426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9955 04:48:08.562759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9956 04:48:08.569233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9957 04:48:08.572610 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9958 04:48:08.578892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9959 04:48:08.582506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9960 04:48:08.588767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9961 04:48:08.592107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9962 04:48:08.598894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9963 04:48:08.602338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9964 04:48:08.609030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9965 04:48:08.612498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9966 04:48:08.619016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9967 04:48:08.622394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9968 04:48:08.628544 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9969 04:48:08.631849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9970 04:48:08.638577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9971 04:48:08.641987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9972 04:48:08.648510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9973 04:48:08.651847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9974 04:48:08.658946 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9975 04:48:08.662132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9976 04:48:08.668674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9977 04:48:08.672092 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9978 04:48:08.675189 INFO: [APUAPC] vio 0
9979 04:48:08.678555 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9980 04:48:08.685045 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9981 04:48:08.688277 INFO: [APUAPC] D0_APC_0: 0x400510
9982 04:48:08.688404 INFO: [APUAPC] D0_APC_1: 0x0
9983 04:48:08.691704 INFO: [APUAPC] D0_APC_2: 0x1540
9984 04:48:08.695052 INFO: [APUAPC] D0_APC_3: 0x0
9985 04:48:08.698503 INFO: [APUAPC] D1_APC_0: 0xffffffff
9986 04:48:08.701865 INFO: [APUAPC] D1_APC_1: 0xffffffff
9987 04:48:08.705317 INFO: [APUAPC] D1_APC_2: 0x3fffff
9988 04:48:08.708777 INFO: [APUAPC] D1_APC_3: 0x0
9989 04:48:08.711764 INFO: [APUAPC] D2_APC_0: 0xffffffff
9990 04:48:08.715128 INFO: [APUAPC] D2_APC_1: 0xffffffff
9991 04:48:08.718498 INFO: [APUAPC] D2_APC_2: 0x3fffff
9992 04:48:08.721982 INFO: [APUAPC] D2_APC_3: 0x0
9993 04:48:08.725145 INFO: [APUAPC] D3_APC_0: 0xffffffff
9994 04:48:08.728224 INFO: [APUAPC] D3_APC_1: 0xffffffff
9995 04:48:08.731885 INFO: [APUAPC] D3_APC_2: 0x3fffff
9996 04:48:08.735149 INFO: [APUAPC] D3_APC_3: 0x0
9997 04:48:08.738747 INFO: [APUAPC] D4_APC_0: 0xffffffff
9998 04:48:08.742021 INFO: [APUAPC] D4_APC_1: 0xffffffff
9999 04:48:08.745347 INFO: [APUAPC] D4_APC_2: 0x3fffff
10000 04:48:08.748636 INFO: [APUAPC] D4_APC_3: 0x0
10001 04:48:08.751853 INFO: [APUAPC] D5_APC_0: 0xffffffff
10002 04:48:08.755081 INFO: [APUAPC] D5_APC_1: 0xffffffff
10003 04:48:08.758368 INFO: [APUAPC] D5_APC_2: 0x3fffff
10004 04:48:08.761675 INFO: [APUAPC] D5_APC_3: 0x0
10005 04:48:08.765571 INFO: [APUAPC] D6_APC_0: 0xffffffff
10006 04:48:08.768625 INFO: [APUAPC] D6_APC_1: 0xffffffff
10007 04:48:08.771799 INFO: [APUAPC] D6_APC_2: 0x3fffff
10008 04:48:08.775085 INFO: [APUAPC] D6_APC_3: 0x0
10009 04:48:08.778304 INFO: [APUAPC] D7_APC_0: 0xffffffff
10010 04:48:08.781584 INFO: [APUAPC] D7_APC_1: 0xffffffff
10011 04:48:08.784902 INFO: [APUAPC] D7_APC_2: 0x3fffff
10012 04:48:08.788259 INFO: [APUAPC] D7_APC_3: 0x0
10013 04:48:08.791565 INFO: [APUAPC] D8_APC_0: 0xffffffff
10014 04:48:08.794806 INFO: [APUAPC] D8_APC_1: 0xffffffff
10015 04:48:08.798268 INFO: [APUAPC] D8_APC_2: 0x3fffff
10016 04:48:08.801614 INFO: [APUAPC] D8_APC_3: 0x0
10017 04:48:08.805048 INFO: [APUAPC] D9_APC_0: 0xffffffff
10018 04:48:08.808442 INFO: [APUAPC] D9_APC_1: 0xffffffff
10019 04:48:08.811749 INFO: [APUAPC] D9_APC_2: 0x3fffff
10020 04:48:08.811832 INFO: [APUAPC] D9_APC_3: 0x0
10021 04:48:08.818390 INFO: [APUAPC] D10_APC_0: 0xffffffff
10022 04:48:08.821643 INFO: [APUAPC] D10_APC_1: 0xffffffff
10023 04:48:08.824953 INFO: [APUAPC] D10_APC_2: 0x3fffff
10024 04:48:08.825036 INFO: [APUAPC] D10_APC_3: 0x0
10025 04:48:08.831659 INFO: [APUAPC] D11_APC_0: 0xffffffff
10026 04:48:08.835287 INFO: [APUAPC] D11_APC_1: 0xffffffff
10027 04:48:08.838186 INFO: [APUAPC] D11_APC_2: 0x3fffff
10028 04:48:08.838270 INFO: [APUAPC] D11_APC_3: 0x0
10029 04:48:08.844926 INFO: [APUAPC] D12_APC_0: 0xffffffff
10030 04:48:08.848251 INFO: [APUAPC] D12_APC_1: 0xffffffff
10031 04:48:08.851430 INFO: [APUAPC] D12_APC_2: 0x3fffff
10032 04:48:08.851514 INFO: [APUAPC] D12_APC_3: 0x0
10033 04:48:08.858255 INFO: [APUAPC] D13_APC_0: 0xffffffff
10034 04:48:08.861493 INFO: [APUAPC] D13_APC_1: 0xffffffff
10035 04:48:08.864750 INFO: [APUAPC] D13_APC_2: 0x3fffff
10036 04:48:08.864838 INFO: [APUAPC] D13_APC_3: 0x0
10037 04:48:08.871592 INFO: [APUAPC] D14_APC_0: 0xffffffff
10038 04:48:08.874702 INFO: [APUAPC] D14_APC_1: 0xffffffff
10039 04:48:08.878442 INFO: [APUAPC] D14_APC_2: 0x3fffff
10040 04:48:08.881460 INFO: [APUAPC] D14_APC_3: 0x0
10041 04:48:08.884646 INFO: [APUAPC] D15_APC_0: 0xffffffff
10042 04:48:08.888394 INFO: [APUAPC] D15_APC_1: 0xffffffff
10043 04:48:08.891747 INFO: [APUAPC] D15_APC_2: 0x3fffff
10044 04:48:08.895198 INFO: [APUAPC] D15_APC_3: 0x0
10045 04:48:08.895282 INFO: [APUAPC] APC_CON: 0x4
10046 04:48:08.898435 INFO: [NOCDAPC] D0_APC_0: 0x0
10047 04:48:08.901192 INFO: [NOCDAPC] D0_APC_1: 0x0
10048 04:48:08.904536 INFO: [NOCDAPC] D1_APC_0: 0x0
10049 04:48:08.908457 INFO: [NOCDAPC] D1_APC_1: 0xfff
10050 04:48:08.911061 INFO: [NOCDAPC] D2_APC_0: 0x0
10051 04:48:08.914378 INFO: [NOCDAPC] D2_APC_1: 0xfff
10052 04:48:08.917622 INFO: [NOCDAPC] D3_APC_0: 0x0
10053 04:48:08.921578 INFO: [NOCDAPC] D3_APC_1: 0xfff
10054 04:48:08.924928 INFO: [NOCDAPC] D4_APC_0: 0x0
10055 04:48:08.925012 INFO: [NOCDAPC] D4_APC_1: 0xfff
10056 04:48:08.928199 INFO: [NOCDAPC] D5_APC_0: 0x0
10057 04:48:08.931538 INFO: [NOCDAPC] D5_APC_1: 0xfff
10058 04:48:08.934867 INFO: [NOCDAPC] D6_APC_0: 0x0
10059 04:48:08.937924 INFO: [NOCDAPC] D6_APC_1: 0xfff
10060 04:48:08.941337 INFO: [NOCDAPC] D7_APC_0: 0x0
10061 04:48:08.944633 INFO: [NOCDAPC] D7_APC_1: 0xfff
10062 04:48:08.947744 INFO: [NOCDAPC] D8_APC_0: 0x0
10063 04:48:08.950834 INFO: [NOCDAPC] D8_APC_1: 0xfff
10064 04:48:08.954095 INFO: [NOCDAPC] D9_APC_0: 0x0
10065 04:48:08.957478 INFO: [NOCDAPC] D9_APC_1: 0xfff
10066 04:48:08.957563 INFO: [NOCDAPC] D10_APC_0: 0x0
10067 04:48:08.961068 INFO: [NOCDAPC] D10_APC_1: 0xfff
10068 04:48:08.964167 INFO: [NOCDAPC] D11_APC_0: 0x0
10069 04:48:08.967431 INFO: [NOCDAPC] D11_APC_1: 0xfff
10070 04:48:08.970725 INFO: [NOCDAPC] D12_APC_0: 0x0
10071 04:48:08.974227 INFO: [NOCDAPC] D12_APC_1: 0xfff
10072 04:48:08.977995 INFO: [NOCDAPC] D13_APC_0: 0x0
10073 04:48:08.980748 INFO: [NOCDAPC] D13_APC_1: 0xfff
10074 04:48:08.984045 INFO: [NOCDAPC] D14_APC_0: 0x0
10075 04:48:08.987570 INFO: [NOCDAPC] D14_APC_1: 0xfff
10076 04:48:08.991072 INFO: [NOCDAPC] D15_APC_0: 0x0
10077 04:48:08.994146 INFO: [NOCDAPC] D15_APC_1: 0xfff
10078 04:48:08.997668 INFO: [NOCDAPC] APC_CON: 0x4
10079 04:48:09.001135 INFO: [APUAPC] set_apusys_apc done
10080 04:48:09.004225 INFO: [DEVAPC] devapc_init done
10081 04:48:09.007825 INFO: GICv3 without legacy support detected.
10082 04:48:09.010879 INFO: ARM GICv3 driver initialized in EL3
10083 04:48:09.014106 INFO: Maximum SPI INTID supported: 639
10084 04:48:09.017983 INFO: BL31: Initializing runtime services
10085 04:48:09.024447 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10086 04:48:09.027885 INFO: SPM: enable CPC mode
10087 04:48:09.031132 INFO: mcdi ready for mcusys-off-idle and system suspend
10088 04:48:09.037773 INFO: BL31: Preparing for EL3 exit to normal world
10089 04:48:09.041076 INFO: Entry point address = 0x80000000
10090 04:48:09.041159 INFO: SPSR = 0x8
10091 04:48:09.048179
10092 04:48:09.048260
10093 04:48:09.048373
10094 04:48:09.051515 Starting depthcharge on Spherion...
10095 04:48:09.051596
10096 04:48:09.051661 Wipe memory regions:
10097 04:48:09.051721
10098 04:48:09.052408 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10099 04:48:09.052507 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10100 04:48:09.052589 Setting prompt string to ['asurada:']
10101 04:48:09.052667 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10102 04:48:09.054737 [0x00000040000000, 0x00000054600000)
10103 04:48:09.177695
10104 04:48:09.177850 [0x00000054660000, 0x00000080000000)
10105 04:48:09.438541
10106 04:48:09.438698 [0x000000821a7280, 0x000000ffe64000)
10107 04:48:10.183142
10108 04:48:10.183277 [0x00000100000000, 0x00000240000000)
10109 04:48:12.073062
10110 04:48:12.076427 Initializing XHCI USB controller at 0x11200000.
10111 04:48:13.115119
10112 04:48:13.118419 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10113 04:48:13.118527
10114 04:48:13.118620
10115 04:48:13.118714
10116 04:48:13.119029 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 04:48:13.219415 asurada: tftpboot 192.168.201.1 12699821/tftp-deploy-ystyxgkl/kernel/image.itb 12699821/tftp-deploy-ystyxgkl/kernel/cmdline
10119 04:48:13.219560 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10120 04:48:13.219665 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10121 04:48:13.223688 tftpboot 192.168.201.1 12699821/tftp-deploy-ystyxgkl/kernel/image.ittp-deploy-ystyxgkl/kernel/cmdline
10122 04:48:13.223774
10123 04:48:13.223860 Waiting for link
10124 04:48:13.384502
10125 04:48:13.384632 R8152: Initializing
10126 04:48:13.384726
10127 04:48:13.387302 Version 9 (ocp_data = 6010)
10128 04:48:13.387386
10129 04:48:13.390816 R8152: Done initializing
10130 04:48:13.390900
10131 04:48:13.390985 Adding net device
10132 04:48:15.264124
10133 04:48:15.264614 done.
10134 04:48:15.265028
10135 04:48:15.265413 MAC: 00:e0:4c:78:7a:aa
10136 04:48:15.265789
10137 04:48:15.267373 Sending DHCP discover... done.
10138 04:48:15.267804
10139 04:48:15.270258 Waiting for reply... done.
10140 04:48:15.270784
10141 04:48:15.273730 Sending DHCP request... done.
10142 04:48:15.274147
10143 04:48:15.280138 Waiting for reply... done.
10144 04:48:15.280598
10145 04:48:15.280963 My ip is 192.168.201.12
10146 04:48:15.281291
10147 04:48:15.283507 The DHCP server ip is 192.168.201.1
10148 04:48:15.283975
10149 04:48:15.290165 TFTP server IP predefined by user: 192.168.201.1
10150 04:48:15.290582
10151 04:48:15.296676 Bootfile predefined by user: 12699821/tftp-deploy-ystyxgkl/kernel/image.itb
10152 04:48:15.297093
10153 04:48:15.297528 Sending tftp read request... done.
10154 04:48:15.299903
10155 04:48:15.305985 Waiting for the transfer...
10156 04:48:15.306403
10157 04:48:15.653213 00000000 ################################################################
10158 04:48:15.653352
10159 04:48:15.910310 00080000 ################################################################
10160 04:48:15.910447
10161 04:48:16.164222 00100000 ################################################################
10162 04:48:16.164382
10163 04:48:16.428256 00180000 ################################################################
10164 04:48:16.428448
10165 04:48:16.690804 00200000 ################################################################
10166 04:48:16.690939
10167 04:48:16.943757 00280000 ################################################################
10168 04:48:16.943896
10169 04:48:17.213409 00300000 ################################################################
10170 04:48:17.213543
10171 04:48:17.476156 00380000 ################################################################
10172 04:48:17.476308
10173 04:48:17.751082 00400000 ################################################################
10174 04:48:17.751264
10175 04:48:18.021284 00480000 ################################################################
10176 04:48:18.021420
10177 04:48:18.286219 00500000 ################################################################
10178 04:48:18.286349
10179 04:48:18.546644 00580000 ################################################################
10180 04:48:18.546782
10181 04:48:18.806508 00600000 ################################################################
10182 04:48:18.806639
10183 04:48:19.064266 00680000 ################################################################
10184 04:48:19.064410
10185 04:48:19.321441 00700000 ################################################################
10186 04:48:19.321575
10187 04:48:19.579320 00780000 ################################################################
10188 04:48:19.579457
10189 04:48:19.830835 00800000 ################################################################
10190 04:48:19.831006
10191 04:48:20.100480 00880000 ################################################################
10192 04:48:20.100615
10193 04:48:20.383070 00900000 ################################################################
10194 04:48:20.383230
10195 04:48:20.638540 00980000 ################################################################
10196 04:48:20.638712
10197 04:48:20.902813 00a00000 ################################################################
10198 04:48:20.902974
10199 04:48:21.166864 00a80000 ################################################################
10200 04:48:21.167043
10201 04:48:21.436743 00b00000 ################################################################
10202 04:48:21.436915
10203 04:48:21.710010 00b80000 ################################################################
10204 04:48:21.710160
10205 04:48:21.995717 00c00000 ################################################################
10206 04:48:21.995871
10207 04:48:22.257357 00c80000 ################################################################
10208 04:48:22.257561
10209 04:48:22.513161 00d00000 ################################################################
10210 04:48:22.513308
10211 04:48:22.778666 00d80000 ################################################################
10212 04:48:22.778892
10213 04:48:23.042720 00e00000 ################################################################
10214 04:48:23.042889
10215 04:48:23.292423 00e80000 ################################################################
10216 04:48:23.292569
10217 04:48:23.559216 00f00000 ################################################################
10218 04:48:23.559367
10219 04:48:23.824936 00f80000 ################################################################
10220 04:48:23.825098
10221 04:48:24.085557 01000000 ################################################################
10222 04:48:24.085712
10223 04:48:24.348732 01080000 ################################################################
10224 04:48:24.348907
10225 04:48:24.618233 01100000 ################################################################
10226 04:48:24.618380
10227 04:48:24.873222 01180000 ################################################################
10228 04:48:24.873362
10229 04:48:25.128166 01200000 ################################################################
10230 04:48:25.128345
10231 04:48:25.385223 01280000 ################################################################
10232 04:48:25.385358
10233 04:48:25.645449 01300000 ################################################################
10234 04:48:25.645582
10235 04:48:25.911136 01380000 ################################################################
10236 04:48:25.911279
10237 04:48:26.174543 01400000 ################################################################
10238 04:48:26.174702
10239 04:48:26.434576 01480000 ################################################################
10240 04:48:26.434753
10241 04:48:26.699464 01500000 ################################################################
10242 04:48:26.699605
10243 04:48:26.965671 01580000 ################################################################
10244 04:48:26.965836
10245 04:48:27.225587 01600000 ################################################################
10246 04:48:27.225769
10247 04:48:27.481365 01680000 ################################################################
10248 04:48:27.481540
10249 04:48:27.740057 01700000 ################################################################
10250 04:48:27.740247
10251 04:48:27.998432 01780000 ################################################################
10252 04:48:27.998621
10253 04:48:28.251684 01800000 ################################################################
10254 04:48:28.251878
10255 04:48:28.507300 01880000 ################################################################
10256 04:48:28.507472
10257 04:48:28.764523 01900000 ################################################################
10258 04:48:28.764666
10259 04:48:29.033144 01980000 ################################################################
10260 04:48:29.033298
10261 04:48:29.294991 01a00000 ################################################################
10262 04:48:29.295129
10263 04:48:29.554429 01a80000 ################################################################
10264 04:48:29.554593
10265 04:48:29.815420 01b00000 ################################################################
10266 04:48:29.815570
10267 04:48:30.083261 01b80000 ################################################################
10268 04:48:30.083398
10269 04:48:30.339520 01c00000 ################################################################
10270 04:48:30.339659
10271 04:48:30.344850 01c80000 ## done.
10272 04:48:30.344939
10273 04:48:30.348403 The bootfile was 29896402 bytes long.
10274 04:48:30.348489
10275 04:48:30.351009 Sending tftp read request... done.
10276 04:48:30.351094
10277 04:48:30.354302 Waiting for the transfer...
10278 04:48:30.354386
10279 04:48:30.354455 00000000 # done.
10280 04:48:30.354519
10281 04:48:30.364408 Command line loaded dynamically from TFTP file: 12699821/tftp-deploy-ystyxgkl/kernel/cmdline
10282 04:48:30.364492
10283 04:48:30.384850 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12699821/extract-nfsrootfs-a_4q7roz,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10284 04:48:30.387868
10285 04:48:30.387953 Loading FIT.
10286 04:48:30.388019
10287 04:48:30.390961 Image ramdisk-1 has 17798584 bytes.
10288 04:48:30.391045
10289 04:48:30.394581 Image fdt-1 has 47278 bytes.
10290 04:48:30.394665
10291 04:48:30.394732 Image kernel-1 has 12048508 bytes.
10292 04:48:30.397755
10293 04:48:30.403898 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10294 04:48:30.404013
10295 04:48:30.421172 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10296 04:48:30.424231
10297 04:48:30.427633 Choosing best match conf-1 for compat google,spherion-rev2.
10298 04:48:30.432247
10299 04:48:30.436911 Connected to device vid:did:rid of 1ae0:0028:00
10300 04:48:30.444771
10301 04:48:30.448133 tpm_get_response: command 0x17b, return code 0x0
10302 04:48:30.448245
10303 04:48:30.451517 ec_init: CrosEC protocol v3 supported (256, 248)
10304 04:48:30.456876
10305 04:48:30.459651 tpm_cleanup: add release locality here.
10306 04:48:30.459754
10307 04:48:30.459846 Shutting down all USB controllers.
10308 04:48:30.463251
10309 04:48:30.463350 Removing current net device
10310 04:48:30.463450
10311 04:48:30.469921 Exiting depthcharge with code 4 at timestamp: 50753162
10312 04:48:30.469999
10313 04:48:30.473573 LZMA decompressing kernel-1 to 0x821a6718
10314 04:48:30.473660
10315 04:48:30.476800 LZMA decompressing kernel-1 to 0x40000000
10316 04:48:31.974789
10317 04:48:31.974969 jumping to kernel
10318 04:48:31.975811 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10319 04:48:31.975948 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10320 04:48:31.976053 Setting prompt string to ['Linux version [0-9]']
10321 04:48:31.976159 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10322 04:48:31.976257 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10323 04:48:32.057214
10324 04:48:32.059983 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10325 04:48:32.064411 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10326 04:48:32.064513 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10327 04:48:32.064587 Setting prompt string to []
10328 04:48:32.064682 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10329 04:48:32.064762 Using line separator: #'\n'#
10330 04:48:32.064823 No login prompt set.
10331 04:48:32.064903 Parsing kernel messages
10332 04:48:32.064980 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10333 04:48:32.065156 [login-action] Waiting for messages, (timeout 00:04:02)
10334 04:48:32.083322 [ 0.000000] Linux version 6.1.75-cip14-rt8 (KernelCI@build-j97480-arm64-gcc-10-defconfig-arm64-chromebook-6n26j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024
10335 04:48:32.086617 [ 0.000000] random: crng init done
10336 04:48:32.093541 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10337 04:48:32.096814 [ 0.000000] efi: UEFI not found.
10338 04:48:32.103044 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10339 04:48:32.113026 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10340 04:48:32.119716 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10341 04:48:32.129978 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10342 04:48:32.136621 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10343 04:48:32.142748 [ 0.000000] printk: bootconsole [mtk8250] enabled
10344 04:48:32.149540 [ 0.000000] NUMA: No NUMA configuration found
10345 04:48:32.156028 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10346 04:48:32.159683 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10347 04:48:32.163113 [ 0.000000] Zone ranges:
10348 04:48:32.169294 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10349 04:48:32.172672 [ 0.000000] DMA32 empty
10350 04:48:32.179401 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10351 04:48:32.182300 [ 0.000000] Movable zone start for each node
10352 04:48:32.185644 [ 0.000000] Early memory node ranges
10353 04:48:32.192799 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10354 04:48:32.199311 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10355 04:48:32.205729 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10356 04:48:32.212482 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10357 04:48:32.219370 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10358 04:48:32.225429 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10359 04:48:32.281654 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10360 04:48:32.288402 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10361 04:48:32.295123 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10362 04:48:32.298263 [ 0.000000] psci: probing for conduit method from DT.
10363 04:48:32.305417 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10364 04:48:32.308132 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10365 04:48:32.315151 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10366 04:48:32.318122 [ 0.000000] psci: SMC Calling Convention v1.2
10367 04:48:32.324441 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10368 04:48:32.327829 [ 0.000000] Detected VIPT I-cache on CPU0
10369 04:48:32.334563 [ 0.000000] CPU features: detected: GIC system register CPU interface
10370 04:48:32.341353 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10371 04:48:32.347769 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10372 04:48:32.354318 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10373 04:48:32.364511 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10374 04:48:32.370956 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10375 04:48:32.374121 [ 0.000000] alternatives: applying boot alternatives
10376 04:48:32.381406 [ 0.000000] Fallback order for Node 0: 0
10377 04:48:32.387401 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10378 04:48:32.390685 [ 0.000000] Policy zone: Normal
10379 04:48:32.414374 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12699821/extract-nfsrootfs-a_4q7roz,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10380 04:48:32.424164 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10381 04:48:32.434511 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10382 04:48:32.444890 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10383 04:48:32.451539 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10384 04:48:32.454263 <6>[ 0.000000] software IO TLB: area num 8.
10385 04:48:32.511251 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10386 04:48:32.660560 <6>[ 0.000000] Memory: 7949812K/8385536K available (18048K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 616K bss, 402956K reserved, 32768K cma-reserved)
10387 04:48:32.667229 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10388 04:48:32.673819 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10389 04:48:32.677228 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10390 04:48:32.683880 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10391 04:48:32.690525 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10392 04:48:32.694229 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10393 04:48:32.703954 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10394 04:48:32.710505 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10395 04:48:32.714028 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10396 04:48:32.722052 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10397 04:48:32.724767 <6>[ 0.000000] GICv3: 608 SPIs implemented
10398 04:48:32.731456 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10399 04:48:32.734702 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10400 04:48:32.738541 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10401 04:48:32.747786 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10402 04:48:32.757755 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10403 04:48:32.771574 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10404 04:48:32.778276 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10405 04:48:32.787311 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10406 04:48:32.800251 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10407 04:48:32.807217 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10408 04:48:32.813719 <6>[ 0.009181] Console: colour dummy device 80x25
10409 04:48:32.823569 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10410 04:48:32.830617 <6>[ 0.024387] pid_max: default: 32768 minimum: 301
10411 04:48:32.833962 <6>[ 0.029288] LSM: Security Framework initializing
10412 04:48:32.840053 <6>[ 0.034226] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10413 04:48:32.850240 <6>[ 0.042040] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10414 04:48:32.856713 <6>[ 0.051507] cblist_init_generic: Setting adjustable number of callback queues.
10415 04:48:32.863335 <6>[ 0.058952] cblist_init_generic: Setting shift to 3 and lim to 1.
10416 04:48:32.873340 <6>[ 0.065290] cblist_init_generic: Setting adjustable number of callback queues.
10417 04:48:32.880306 <6>[ 0.072717] cblist_init_generic: Setting shift to 3 and lim to 1.
10418 04:48:32.883621 <6>[ 0.079154] rcu: Hierarchical SRCU implementation.
10419 04:48:32.890370 <6>[ 0.079157] rcu: Max phase no-delay instances is 1000.
10420 04:48:32.896579 <6>[ 0.079181] printk: bootconsole [mtk8250] printing thread started
10421 04:48:32.903419 <6>[ 0.097476] EFI services will not be available.
10422 04:48:32.906806 <6>[ 0.097681] smp: Bringing up secondary CPUs ...
10423 04:48:32.910259 <6>[ 0.097994] Detected VIPT I-cache on CPU1
10424 04:48:32.919870 <6>[ 0.098064] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10425 04:48:32.926363 <6>[ 0.098096] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10426 04:48:32.935702 <6>[ 0.125994] Detected VIPT I-cache on CPU2
10427 04:48:32.945616 <6>[ 0.126043] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10428 04:48:32.952118 <6>[ 0.126057] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10429 04:48:32.955590 <6>[ 0.126312] Detected VIPT I-cache on CPU3
10430 04:48:32.962149 <6>[ 0.126357] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10431 04:48:32.968204 <6>[ 0.126371] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10432 04:48:32.972238 <6>[ 0.126679] CPU features: detected: Spectre-v4
10433 04:48:32.978753 <6>[ 0.126686] CPU features: detected: Spectre-BHB
10434 04:48:32.981803 <6>[ 0.126691] Detected PIPT I-cache on CPU4
10435 04:48:32.988158 <6>[ 0.126750] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10436 04:48:32.994768 <6>[ 0.126766] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10437 04:48:33.001890 <6>[ 0.127058] Detected PIPT I-cache on CPU5
10438 04:48:33.007973 <6>[ 0.127118] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10439 04:48:33.014819 <6>[ 0.127134] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10440 04:48:33.018292 <6>[ 0.127407] Detected PIPT I-cache on CPU6
10441 04:48:33.024915 <6>[ 0.127471] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10442 04:48:33.031314 <6>[ 0.127487] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10443 04:48:33.039919 <6>[ 0.127778] Detected PIPT I-cache on CPU7
10444 04:48:33.046750 <6>[ 0.127841] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10445 04:48:33.053454 <6>[ 0.127857] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10446 04:48:33.056834 <6>[ 0.127903] smp: Brought up 1 node, 8 CPUs
10447 04:48:33.063477 <6>[ 0.127908] SMP: Total of 8 processors activated.
10448 04:48:33.066694 <6>[ 0.127910] CPU features: detected: 32-bit EL0 Support
10449 04:48:33.076722 <6>[ 0.127912] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10450 04:48:33.083371 <6>[ 0.127915] CPU features: detected: Common not Private translations
10451 04:48:33.089568 <6>[ 0.127917] CPU features: detected: CRC32 instructions
10452 04:48:33.093175 <6>[ 0.127920] CPU features: detected: RCpc load-acquire (LDAPR)
10453 04:48:33.099811 <6>[ 0.127921] CPU features: detected: LSE atomic instructions
10454 04:48:33.106701 <6>[ 0.127922] CPU features: detected: Privileged Access Never
10455 04:48:33.112977 <6>[ 0.127924] CPU features: detected: RAS Extension Support
10456 04:48:33.119988 <6>[ 0.127927] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10457 04:48:33.123333 <6>[ 0.127992] CPU: All CPU(s) started at EL2
10458 04:48:33.129975 <6>[ 0.127994] alternatives: applying system-wide alternatives
10459 04:48:33.133380 <6>[ 0.141052] devtmpfs: initialized
10460 04:48:33.142638 <6>[ 0.147314] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10461 04:48:33.149378 <6>[ 0.147328] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10462 04:48:33.174908 �^ZY.'HL�LL�&$JKV�.'HN��1048576 bytes, linear)
10463 04:48:33.181519 <6>[ 0.3<74604] printk: console [ttyS0] printing thread started
10464 04:48:33.184566 6<6>[ 0.374636] printk: console [ttyS0] enabled
10465 04:48:33.194477 >[ 0.247421] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10466 04:48:33.201340 <6>[ 0.374639] printk: bootconsole [mtk8250] disabled
10467 04:48:33.207832 <6>[ 0.393679] printk: bootconsole [mtk8250] printing thread stopped
10468 04:48:33.211319 <6>[ 0.394920] SuperH (H)SCI(F) driver initialized
10469 04:48:33.214534 <6>[ 0.395395] msm_serial: driver initialized
10470 04:48:33.224459 <6>[ 0.400007] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10471 04:48:33.231177 <6>[ 0.400036] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10472 04:48:33.241155 <6>[ 0.400065] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10473 04:48:33.253483 <6>[ 0.400094] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10474 04:48:33.264817 <6>[ 0.400115] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10475 04:48:33.272821 <6>[ 0.400142] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10476 04:48:33.289102 <6>[ 0.400171] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10477 04:48:33.289447 <6>[ 0.400283] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10478 04:48:33.295256 <6>[ 0.400313] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10479 04:48:33.302942 <6>[ 0.410294] loop: module loaded
10480 04:48:33.308879 <6>[ 0.412845] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10481 04:48:33.312363 <4>[ 0.429610] mtk-pmic-keys: Failed to locate of_node [id: -1]
10482 04:48:33.312453 <6>[ 0.430584] megasas: 07.719.03.00-rc1
10483 04:48:33.315608 <6>[ 0.443005] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10484 04:48:33.322243 <6>[ 0.446868] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10485 04:48:33.329003 <6>[ 0.459164] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10486 04:48:33.342575 <6>[ 0.512964] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10487 04:48:33.791722 <6>[ 0.986706] Freeing initrd memory: 17376K
10488 04:48:33.799834 <6>[ 0.992724] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10489 04:48:33.806296 <6>[ 0.997280] tun: Universal TUN/TAP device driver, 1.6
10490 04:48:33.809867 <6>[ 0.998019] thunder_xcv, ver 1.0
10491 04:48:33.812936 <6>[ 0.998041] thunder_bgx, ver 1.0
10492 04:48:33.816187 <6>[ 0.998055] nicpf, ver 1.0
10493 04:48:33.822844 <6>[ 0.999085] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10494 04:48:33.829733 <6>[ 0.999088] hns3: Copyright (c) 2017 Huawei Corporation.
10495 04:48:33.832933 <6>[ 0.999112] hclge is initializing
10496 04:48:33.839329 <6>[ 0.999125] e1000: Intel(R) PRO/1000 Network Driver
10497 04:48:33.843298 <6>[ 0.999127] e1000: Copyright (c) 1999-2006 Intel Corporation.
10498 04:48:33.850721 <6>[ 0.999143] e1000e: Intel(R) PRO/1000 Network Driver
10499 04:48:33.854149 <6>[ 0.999145] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10500 04:48:33.861455 <6>[ 0.999160] igb: Intel(R) Gigabit Ethernet Network Driver
10501 04:48:33.868206 <6>[ 0.999162] igb: Copyright (c) 2007-2014 Intel Corporation.
10502 04:48:33.874646 <6>[ 0.999178] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10503 04:48:33.877883 <6>[ 0.999180] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10504 04:48:33.884900 <6>[ 0.999479] sky2: driver version 1.30
10505 04:48:33.888085 <6>[ 1.000549] VFIO - User Level meta-driver version: 0.3
10506 04:48:33.894919 <6>[ 1.003349] usbcore: registered new interface driver usb-storage
10507 04:48:33.901920 <6>[ 1.003545] usbcore: registered new device driver onboard-usb-hub
10508 04:48:33.908588 <6>[ 1.006280] mt6397-rtc mt6359-rtc: registered as rtc0
10509 04:48:33.914638 <6>[ 1.006434] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-04T04:45:52 UTC (1707021952)
10510 04:48:33.921279 <6>[ 1.007038] i2c_dev: i2c /dev entries driver
10511 04:48:33.927907 <6>[ 1.014107] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10512 04:48:33.931353 <6>[ 1.029090] cpu cpu0: EM: created perf domain
10513 04:48:33.938076 <6>[ 1.029402] cpu cpu4: EM: created perf domain
10514 04:48:33.944646 <6>[ 1.033669] sdhci: Secure Digital Host Controller Interface driver
10515 04:48:33.947937 <6>[ 1.033670] sdhci: Copyright(c) Pierre Ossman
10516 04:48:33.955345 <6>[ 1.034026] Synopsys Designware Multimedia Card Interface Driver
10517 04:48:33.961429 <6>[ 1.034397] sdhci-pltfm: SDHCI platform and OF driver helper
10518 04:48:33.968079 <6>[ 1.038681] ledtrig-cpu: registered to indicate activity on CPUs
10519 04:48:33.971401 <6>[ 1.039260] mmc0: CQHCI version 5.10
10520 04:48:33.977979 <6>[ 1.039339] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10521 04:48:33.984434 <6>[ 1.039620] usbcore: registered new interface driver usbhid
10522 04:48:33.988452 <6>[ 1.039622] usbhid: USB HID core driver
10523 04:48:33.995091 <6>[ 1.039751] spi_master spi0: will run message pump with realtime priority
10524 04:48:34.008054 <6>[ 1.076099] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10525 04:48:34.021426 <6>[ 1.078992] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10526 04:48:34.024523 <6>[ 1.080124] cros-ec-spi spi0.0: Chrome EC device registered
10527 04:48:34.034607 <6>[ 1.096508] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10528 04:48:34.041252 <6>[ 1.098844] NET: Registered PF_PACKET protocol family
10529 04:48:34.044668 <6>[ 1.098941] 9pnet: Installing 9P2000 support
10530 04:48:34.051196 <5>[ 1.098981] Key type dns_resolver registered
10531 04:48:34.054515 <6>[ 1.099344] registered taskstats version 1
10532 04:48:34.057950 <5>[ 1.099364] Loading compiled-in X.509 certificates
10533 04:48:34.071047 <4>[ 1.121174] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10534 04:48:34.080706 <4>[ 1.121317] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10535 04:48:34.087278 <3>[ 1.121327] debugfs: File 'uA_load' in directory '/' already present!
10536 04:48:34.094419 <3>[ 1.121335] debugfs: File 'min_uV' in directory '/' already present!
10537 04:48:34.101251 <3>[ 1.121338] debugfs: File 'max_uV' in directory '/' already present!
10538 04:48:34.107278 <3>[ 1.121341] debugfs: File 'constraint_flags' in directory '/' already present!
10539 04:48:34.117743 <3>[ 1.123123] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10540 04:48:34.120873 <6>[ 1.129832] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10541 04:48:34.127624 <6>[ 1.130535] xhci-mtk 11200000.usb: xHCI Host Controller
10542 04:48:34.134524 <6>[ 1.130561] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10543 04:48:34.144295 <6>[ 1.130778] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10544 04:48:34.150992 <6>[ 1.130827] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10545 04:48:34.157720 <6>[ 1.130939] xhci-mtk 11200000.usb: xHCI Host Controller
10546 04:48:34.164425 <6>[ 1.130945] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10547 04:48:34.171272 <6>[ 1.130952] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10548 04:48:34.174060 <6>[ 1.131356] hub 1-0:1.0: USB hub found
10549 04:48:34.181223 <6>[ 1.131380] hub 1-0:1.0: 1 port detected
10550 04:48:34.187328 <6>[ 1.131793] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10551 04:48:34.191007 <6>[ 1.132867] hub 2-0:1.0: USB hub found
10552 04:48:34.197263 <6>[ 1.132979] hub 2-0:1.0: 1 port detected
10553 04:48:34.201071 <6>[ 1.133613] mmc0: Command Queue Engine enabled
10554 04:48:34.207851 <6>[ 1.133641] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10555 04:48:34.211298 <6>[ 1.134493] mmcblk0: mmc0:0001 DA4128 116 GiB
10556 04:48:34.217849 <6>[ 1.136287] mtk-msdc 11f70000.mmc: Got CD GPIO
10557 04:48:34.221133 <6>[ 1.138660] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10558 04:48:34.227546 <6>[ 1.140677] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10559 04:48:34.234628 <6>[ 1.141868] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10560 04:48:34.240688 <6>[ 1.142835] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10561 04:48:34.247685 <6>[ 1.146674] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10562 04:48:34.254275 <6>[ 1.146680] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10563 04:48:34.263856 <4>[ 1.146769] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10564 04:48:34.271254 <6>[ 1.147261] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10565 04:48:34.280641 <6>[ 1.147262] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10566 04:48:34.287403 <6>[ 1.147391] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10567 04:48:34.297712 <6>[ 1.147399] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10568 04:48:34.304209 <6>[ 1.147401] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10569 04:48:34.314164 <6>[ 1.147403] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10570 04:48:34.320931 <6>[ 1.148551] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10571 04:48:34.330884 <6>[ 1.148568] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10572 04:48:34.337510 <6>[ 1.148572] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10573 04:48:34.347377 <6>[ 1.148576] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10574 04:48:34.354109 <6>[ 1.148579] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10575 04:48:34.363874 <6>[ 1.148583] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10576 04:48:34.370693 <6>[ 1.148587] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10577 04:48:34.380169 <6>[ 1.148591] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10578 04:48:34.387230 <6>[ 1.148597] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10579 04:48:34.397221 <6>[ 1.148601] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10580 04:48:34.403618 <6>[ 1.148605] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10581 04:48:34.413091 <6>[ 1.148609] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10582 04:48:34.420014 <6>[ 1.148612] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10583 04:48:34.430050 <6>[ 1.148616] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10584 04:48:34.436553 <6>[ 1.148620] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10585 04:48:34.443200 <6>[ 1.148898] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10586 04:48:34.449764 <6>[ 1.149455] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10587 04:48:34.456479 <6>[ 1.149673] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10588 04:48:34.463279 <6>[ 1.149902] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10589 04:48:34.469845 <6>[ 1.150141] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10590 04:48:34.479293 <6>[ 1.150304] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10591 04:48:34.489502 <6>[ 1.150312] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10592 04:48:34.499419 <6>[ 1.150315] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10593 04:48:34.509423 <6>[ 1.150318] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10594 04:48:34.515772 <6>[ 1.150321] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10595 04:48:34.525718 <6>[ 1.150325] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10596 04:48:34.536155 <6>[ 1.150328] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10597 04:48:34.546053 <6>[ 1.150330] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10598 04:48:34.555313 <6>[ 1.150333] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10599 04:48:34.565443 <6>[ 1.150337] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10600 04:48:34.575233 <6>[ 1.150340] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10601 04:48:34.581979 <6>[ 1.151083] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10602 04:48:34.588845 <6>[ 1.172914] Trying to probe devices needed for running init ...
10603 04:48:34.595381 <6>[ 1.519830] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10604 04:48:34.598825 <6>[ 1.550871] hub 2-1:1.0: USB hub found
10605 04:48:34.605429 <6>[ 1.551232] hub 2-1:1.0: 3 ports detected
10606 04:48:34.608645 <6>[ 1.553629] hub 2-1:1.0: USB hub found
10607 04:48:34.611819 <6>[ 1.553974] hub 2-1:1.0: 3 ports detected
10608 04:48:34.618449 <6>[ 1.671619] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10609 04:48:34.631561 <6>[ 1.824575] hub 1-1:1.0: USB hub found
10610 04:48:34.635212 <6>[ 1.824964] hub 1-1:1.0: 4 ports detected
10611 04:48:34.638317 <6>[ 1.829048] hub 1-1:1.0: USB hub found
10612 04:48:34.641560 <6>[ 1.829437] hub 1-1:1.0: 4 ports detected
10613 04:48:34.715046 <6>[ 1.903983] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10614 04:48:34.950996 <6>[ 2.139771] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10615 04:48:35.075545 <6>[ 2.267899] hub 1-1.4:1.0: USB hub found
10616 04:48:35.079235 <6>[ 2.268372] hub 1-1.4:1.0: 2 ports detected
10617 04:48:35.082100 <6>[ 2.272663] hub 1-1.4:1.0: USB hub found
10618 04:48:35.088979 <6>[ 2.273009] hub 1-1.4:1.0: 2 ports detected
10619 04:48:35.371185 <6>[ 2.559744] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10620 04:48:35.554729 <6>[ 2.743742] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10621 04:48:46.275716 <6>[ 13.472828] ALSA device list:
10622 04:48:46.281850 <6>[ 13.472852] No soundcards found.
10623 04:48:46.285190 <6>[ 13.477389] Freeing unused kernel memory: 8448K
10624 04:48:46.288574 <6>[ 13.477554] Run /init as init process
10625 04:48:46.291845 Loading, please wait...
10626 04:48:46.311688 Starting version 247.3-7+deb11u2
10627 04:48:46.561755 <6>[ 13.753055] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10628 04:48:46.570762 <6>[ 13.767045] remoteproc remoteproc0: scp is available
10629 04:48:46.577240 <6>[ 13.767224] remoteproc remoteproc0: powering up scp
10630 04:48:46.583890 <6>[ 13.767241] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10631 04:48:46.590895 <6>[ 13.767296] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10632 04:48:46.597080 <6>[ 13.780943] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10633 04:48:46.607218 <6>[ 13.780973] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10634 04:48:46.614182 <6>[ 13.780983] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10635 04:48:46.620249 <6>[ 13.792726] mc: Linux media interface: v0.10
10636 04:48:46.627195 <6>[ 13.800855] videodev: Linux video capture interface: v2.00
10637 04:48:46.633787 <6>[ 13.801058] usbcore: registered new device driver r8152-cfgselector
10638 04:48:46.640316 <4>[ 13.809468] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10639 04:48:46.646841 <4>[ 13.809591] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10640 04:48:46.653627 <6>[ 13.831043] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10641 04:48:46.669974 <3>[ 13.860222] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10642 04:48:46.676672 <3>[ 13.860292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10643 04:48:46.686415 <3>[ 13.860299] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10644 04:48:46.693462 <3>[ 13.866231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10645 04:48:46.703722 <3>[ 13.866274] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10646 04:48:46.710424 <3>[ 13.866279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10647 04:48:46.717541 <3>[ 13.866288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10648 04:48:46.727467 <3>[ 13.866294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10649 04:48:46.733974 <3>[ 13.867283] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10650 04:48:46.743959 <3>[ 13.867357] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10651 04:48:46.751021 <3>[ 13.867365] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10652 04:48:46.757556 <3>[ 13.867375] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10653 04:48:46.766927 <3>[ 13.867464] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10654 04:48:46.773616 <3>[ 13.867474] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10655 04:48:46.783578 <3>[ 13.867480] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10656 04:48:46.790243 <3>[ 13.867490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10657 04:48:46.800868 <3>[ 13.867496] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10658 04:48:46.806853 <3>[ 13.867526] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10659 04:48:46.816782 <4>[ 13.867982] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10660 04:48:46.820186 <4>[ 13.867982] Fallback method does not support PEC.
10661 04:48:46.830182 <6>[ 13.891747] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10662 04:48:46.836960 <6>[ 13.895209] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10663 04:48:46.843549 <6>[ 13.895216] remoteproc remoteproc0: remote processor scp is now up
10664 04:48:46.850398 <6>[ 13.895227] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10665 04:48:46.860559 <3>[ 13.897764] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10666 04:48:46.867114 <6>[ 13.905026] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10667 04:48:46.873303 <6>[ 13.905034] pci_bus 0000:00: root bus resource [bus 00-ff]
10668 04:48:46.879895 <6>[ 13.905042] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10669 04:48:46.890097 <6>[ 13.905048] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10670 04:48:46.896848 <6>[ 13.905091] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10671 04:48:46.903339 <6>[ 13.905114] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10672 04:48:46.906668 <6>[ 13.905205] pci 0000:00:00.0: supports D1 D2
10673 04:48:46.913530 <6>[ 13.905208] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10674 04:48:46.923353 <6>[ 13.906032] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10675 04:48:46.930263 <6>[ 13.907153] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10676 04:48:46.939906 <6>[ 13.907226] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10677 04:48:46.946225 <6>[ 13.907293] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10678 04:48:46.952895 <6>[ 13.907325] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10679 04:48:46.959096 <6>[ 13.907345] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10680 04:48:46.969492 <6>[ 13.907363] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10681 04:48:46.972628 <6>[ 13.907531] pci 0000:01:00.0: supports D1 D2
10682 04:48:46.979236 <6>[ 13.907536] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10683 04:48:46.989408 <6>[ 13.914043] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10684 04:48:46.999439 <6>[ 13.914564] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10685 04:48:47.009304 <4>[ 13.914666] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10686 04:48:47.015677 <4>[ 13.914677] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10687 04:48:47.025716 <6>[ 13.915579] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10688 04:48:47.032244 <6>[ 13.923571] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10689 04:48:47.039194 <6>[ 13.923623] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10690 04:48:47.048582 <6>[ 13.923630] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10691 04:48:47.055171 <6>[ 13.923652] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10692 04:48:47.065248 <6>[ 13.923669] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10693 04:48:47.072044 <6>[ 13.923694] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10694 04:48:47.078779 <6>[ 13.923711] pci 0000:00:00.0: PCI bridge to [bus 01]
10695 04:48:47.085339 <6>[ 13.923728] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10696 04:48:47.091660 <6>[ 13.923915] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10697 04:48:47.098410 <6>[ 13.924960] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10698 04:48:47.101717 <6>[ 13.925192] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10699 04:48:47.111962 <3>[ 13.930846] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10700 04:48:47.114775 <6>[ 13.946047] Bluetooth: Core ver 2.22
10701 04:48:47.121944 <6>[ 13.946166] NET: Registered PF_BLUETOOTH protocol family
10702 04:48:47.128738 <6>[ 13.946170] Bluetooth: HCI device and connection manager initialized
10703 04:48:47.131461 <6>[ 13.946197] Bluetooth: HCI socket layer initialized
10704 04:48:47.138257 <6>[ 13.946207] Bluetooth: L2CAP socket layer initialized
10705 04:48:47.144631 <6>[ 13.946220] Bluetooth: SCO socket layer initialized
10706 04:48:47.151313 <5>[ 13.948662] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10707 04:48:47.157968 <5>[ 13.960162] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10708 04:48:47.167989 <5>[ 13.960619] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10709 04:48:47.174624 <4>[ 13.960698] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10710 04:48:47.181155 <6>[ 13.960706] cfg80211: failed to load regulatory.db
10711 04:48:47.187781 <6>[ 13.970322] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10712 04:48:47.201342 <6>[ 13.971302] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10713 04:48:47.204652 <6>[ 13.971391] usbcore: registered new interface driver uvcvideo
10714 04:48:47.211220 <6>[ 13.971537] r8152 2-1.3:1.0 eth0: v1.12.13
10715 04:48:47.217853 <6>[ 13.971568] usbcore: registered new interface driver r8152
10716 04:48:47.221069 <6>[ 13.993999] usbcore: registered new interface driver cdc_ether
10717 04:48:47.227675 <6>[ 14.001516] usbcore: registered new interface driver r8153_ecm
10718 04:48:47.234259 <6>[ 14.010662] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10719 04:48:47.240789 <6>[ 14.011062] usbcore: registered new interface driver btusb
10720 04:48:47.250920 <4>[ 14.011897] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10721 04:48:47.257447 <3>[ 14.011909] Bluetooth: hci0: Failed to load firmware file (-2)
10722 04:48:47.263951 <3>[ 14.011914] Bluetooth: hci0: Failed to set up firmware (-2)
10723 04:48:47.274098 <4>[ 14.011918] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10724 04:48:47.280839 <6>[ 14.015912] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10725 04:48:47.287277 <6>[ 14.072942] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10726 04:48:47.293760 <6>[ 14.073038] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10727 04:48:47.297159 <6>[ 14.091621] mt7921e 0000:01:00.0: ASIC revision: 79610010
10728 04:48:47.307393 <6>[ 14.178464] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10729 04:48:47.310129 <6>[ 14.178464]
10730 04:48:47.316927 <6>[ 14.438191] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10731 04:48:47.320209 Begin: Loading essential drivers ... done.
10732 04:48:47.327024 Begin: Running /scripts/init-premount ... done.
10733 04:48:47.333543 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10734 04:48:47.340566 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10735 04:48:47.346901 Device /sys/class/net/enx00e04c787aaa found
10736 04:48:47.347019 done.
10737 04:48:47.353759 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10738 04:48:48.082057 <6>[ 15.277597] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10739 04:48:48.390408 <6>[ 15.584230] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10740 04:48:49.309544 IP-Config: no response after 2 secs - giving up
10741 04:48:49.342507 IP-Config: wlp1s0 hardware address d8:f3:bc:78:17:6f mtu 1500 DHCP
10742 04:48:50.081657 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10743 04:48:50.104875 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10744 04:48:50.111655 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10745 04:48:50.118114 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10746 04:48:50.124795 host : mt8192-asurada-spherion-r0-cbg-0
10747 04:48:50.131636 domain : lava-rack
10748 04:48:50.134761 rootserver: 192.168.201.1 rootpath:
10749 04:48:50.137886 filename :
10750 04:48:50.258583 done.
10751 04:48:50.265072 Begin: Running /scripts/nfs-bottom ... done.
10752 04:48:50.283991 Begin: Running /scripts/init-bottom ... done.
10753 04:48:51.457974 <6>[ 18.655365] NET: Registered PF_INET6 protocol family
10754 04:48:51.461431 <6>[ 18.657335] Segment Routing with IPv6
10755 04:48:51.467520 <6>[ 18.657351] In-situ OAM (IOAM) with IPv6
10756 04:48:51.577566 <30>[ 18.754957] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10757 04:48:51.581091 <30>[ 18.755833] systemd[1]: Detected architecture arm64.
10758 04:48:51.581204
10759 04:48:51.587674 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10760 04:48:51.587782
10761 04:48:51.605891 <30>[ 18.801829] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10762 04:48:52.409002 <30>[ 19.602833] systemd[1]: Queued start job for default target Graphical Interface.
10763 04:48:52.440465 [[0;32m OK [<30>[ 19.634410] systemd[1]: Created slice system-getty.slice.
10764 04:48:52.443799 0m] Created slice [0;1;39msystem-getty.slice[0m.
10765 04:48:52.462931 [[0;32m OK [0m] Created slic<30>[ 19.657261] systemd[1]: Created slice system-modprobe.slice.
10766 04:48:52.466263 e [0;1;39msystem-modprobe.slice[0m.
10767 04:48:52.487203 [[0;32m OK [0m] Created slic<30>[ 19.681204] systemd[1]: Created slice system-serial\x2dgetty.slice.
10768 04:48:52.493272 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10769 04:48:52.511803 [[0;32m OK [0m] Created slic<30>[ 19.705808] systemd[1]: Created slice User and Session Slice.
10770 04:48:52.514833 e [0;1;39mUser and Session Slice[0m.
10771 04:48:52.537746 [[0;32m OK [0m] Started [0;<30>[ 19.728595] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10772 04:48:52.541168 1;39mDispatch Password …ts to Console Directory Watch[0m.
10773 04:48:52.566096 [[0;32m OK [0m] Started [0;<30>[ 19.756568] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10774 04:48:52.568923 1;39mForward Password R…uests to Wall Directory Watch[0m.
10775 04:48:52.596841 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 19.783928] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10776 04:48:52.603632 <30>[ 19.784142] systemd[1]: Reached target Local Encrypted Volumes.
10777 04:48:52.606722 l Encrypted Volumes[0m.
10778 04:48:52.625503 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.819898] systemd[1]: Reached target Paths.
10779 04:48:52.625691 s[0m.
10780 04:48:52.648992 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.839785] systemd[1]: Reached target Remote File Systems.
10781 04:48:52.649183 te File Systems[0m.
10782 04:48:52.670292 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.864116] systemd[1]: Reached target Slices.
10783 04:48:52.670479 es[0m.
10784 04:48:52.689787 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.883792] systemd[1]: Reached target Swap.
10785 04:48:52.690008 [0m.
10786 04:48:52.713460 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.904313] systemd[1]: Listening on initctl Compatibility Named Pipe.
10787 04:48:52.717269 l Compatibility Named Pipe[0m.
10788 04:48:52.727036 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.920419] systemd[1]: Listening on Journal Audit Socket.
10789 04:48:52.730242 l Audit Socket[0m.
10790 04:48:52.751053 [[0;32m OK [0m] Listening on<30>[ 19.945040] systemd[1]: Listening on Journal Socket (/dev/log).
10791 04:48:52.754307 [0;1;39mJournal Socket (/dev/log)[0m.
10792 04:48:52.774440 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.968421] systemd[1]: Listening on Journal Socket.
10793 04:48:52.777765 l Socket[0m.
10794 04:48:52.795444 [[0;32m OK [0m] Listening on<30>[ 19.989252] systemd[1]: Listening on Network Service Netlink Socket.
10795 04:48:52.801855 [0;1;39mNetwork Service Netlink Socket[0m.
10796 04:48:52.821018 [[0;32m OK [<30>[ 20.015203] systemd[1]: Listening on udev Control Socket.
10797 04:48:52.824665 0m] Listening on [0;1;39mudev Control Socket[0m.
10798 04:48:52.842706 [[0;32m OK [0m] Listening on<30>[ 20.036941] systemd[1]: Listening on udev Kernel Socket.
10799 04:48:52.846386 [0;1;39mudev Kernel Socket[0m.
10800 04:48:52.901729 Mounting [0;1;39mHuge Pages File Syste<30>[ 20.092244] systemd[1]: Mounting Huge Pages File System...
10801 04:48:52.901916 m[0m...
10802 04:48:52.920187 Mounting [0;1;39mPOSIX<30>[ 20.114023] systemd[1]: Mounting POSIX Message Queue File System...
10803 04:48:52.923502 Message Queue File System[0m...
10804 04:48:52.949044 Mounting [0;1;39mKernel Debug File Sys<30>[ 20.139425] systemd[1]: Mounting Kernel Debug File System...
10805 04:48:52.949232 tem[0m...
10806 04:48:52.969029 <30>[ 20.160169] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10807 04:48:52.979325 <30>[ 20.166849] systemd[1]: Starting Create list of static device nodes for the current kernel...
10808 04:48:52.986220 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10809 04:48:53.042735 Starting [0;1;39mLoad <30>[ 20.236610] systemd[1]: Starting Load Kernel Module configfs...
10810 04:48:53.045775 Kernel Module configfs[0m...
10811 04:48:53.067143 Starting [0;1;39mLoad <30>[ 20.261162] systemd[1]: Starting Load Kernel Module drm...
10812 04:48:53.070426 Kernel Module drm[0m...
10813 04:48:53.095515 Starting [0;1;39mLoad <30>[ 20.289528] systemd[1]: Starting Load Kernel Module fuse...
10814 04:48:53.099026 Kernel Module fuse[0m...
10815 04:48:53.129875 <6>[ 20.324636] fuse: init (API version 7.37)
10816 04:48:53.139976 <30>[ 20.326201] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10817 04:48:53.151197 Starting [0;1;39mJourn<30>[ 20.344922] systemd[1]: Starting Journal Service...
10818 04:48:53.151381 al Service[0m...
10819 04:48:53.179805 Starting [0;1;39mLoad <30>[ 20.373840] systemd[1]: Starting Load Kernel Modules...
10820 04:48:53.183101 Kernel Modules[0m...
10821 04:48:53.209157 <30>[ 20.403290] systemd[1]: Starting Remount Root and Kernel File Systems...
10822 04:48:53.216127 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10823 04:48:53.274711 Starting [0;1;39mColdp<30>[ 20.468731] systemd[1]: Starting Coldplug All udev Devices...
10824 04:48:53.284788 lug All udev Dev<3>[ 20.471761] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10825 04:48:53.284930 ices[0m...
10826 04:48:53.311878 [[0;32m OK [<3>[ 20.500917] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10827 04:48:53.318947 0m] Mounted [0;<30>[ 20.502827] systemd[1]: Mounted Huge Pages File System.
10828 04:48:53.321530 1;39mHuge Pages File System[0m.
10829 04:48:53.341324 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Messa<30>[ 20.532161] systemd[1]: Mounted POSIX Message Queue File System.
10830 04:48:53.352230 ge Queue File Sy<3>[ 20.533827] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10831 04:48:53.352401 stem[0m.
10832 04:48:53.362089 <3>[ 20.555399] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10833 04:48:53.372224 [[0;32m OK [0m] Mounted [0;<30>[ 20.564715] systemd[1]: Mounted Kernel Debug File System.
10834 04:48:53.372389 1;39mKernel Debug File System[0m.
10835 04:48:53.386576 [[0;32m OK [0m] Finished [0<30>[ 20.577589] systemd[1]: Finished Create list of static device nodes for the current kernel.
10836 04:48:53.397553 ;1;39mCreate lis<3>[ 20.578172] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10837 04:48:53.407564 t of st… nodes<3>[ 20.598903] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10838 04:48:53.410734 for the current kernel[0m.
10839 04:48:53.429055 <3>[ 20.620323] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10840 04:48:53.440390 [[0;32m OK [<30>[ 20.633607] systemd[1]: modprobe@configfs.service: Succeeded.
10841 04:48:53.447116 0m] Finished [0<30>[ 20.634292] systemd[1]: Finished Load Kernel Module configfs.
10842 04:48:53.457775 ;1;39mLoad Kerne<3>[ 20.640728] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10843 04:48:53.457956 l Module configfs[0m.
10844 04:48:53.468897 <3>[ 20.662391] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10845 04:48:53.484267 [[0;32m OK [<30>[ 20.677338] systemd[1]: modprobe@drm.service: Succeeded.
10846 04:48:53.490914 0m] Finished [0<30>[ 20.678449] systemd[1]: Finished Load Kernel Module drm.
10847 04:48:53.501140 ;1;39mLoad Kerne<3>[ 20.682753] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10848 04:48:53.501338 l Module drm[0m.
10849 04:48:53.523791 [[0;32m OK [0m] Finished [0<30>[ 20.716819] systemd[1]: modprobe@fuse.service: Succeeded.
10850 04:48:53.530767 ;1;39mLoad Kerne<30>[ 20.717482] systemd[1]: Finished Load Kernel Module fuse.
10851 04:48:53.533769 l Module fuse[0m.
10852 04:48:53.550331 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 20.744494] systemd[1]: Started Journal Service.
10853 04:48:53.553635 vice[0m.
10854 04:48:53.569307 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10855 04:48:53.591406 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10856 04:48:53.654892 Mounting [0;1;39mFUSE Control File System[0m...
10857 04:48:53.677191 Mounting [0;1;39mKernel Configuration File System[0m...
10858 04:48:53.703780 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10859 04:48:53.729700 Starting [0;1;39mLoad/Save Random Seed[0m...
10860 04:48:53.745219 <46>[ 20.938303] systemd-journald[306]: Received client request to flush runtime journal.
10861 04:48:53.754299 Starting [0;1;39mApply Kernel Variables[0m...
10862 04:48:53.775316 Starting [0;1;39mCreate System Users[0m...
10863 04:48:53.796240 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10864 04:48:53.823508 <4>[ 21.008115] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10865 04:48:53.833873 <3>[ 21.008130] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10866 04:48:53.840195 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10867 04:48:53.858127 See 'systemctl status systemd-udev-trigger.service' for details.
10868 04:48:53.874961 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10869 04:48:53.892188 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10870 04:48:54.510656 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10871 04:48:55.196865 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10872 04:48:55.219478 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10873 04:48:55.259609 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10874 04:48:55.327193 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10875 04:48:55.342592 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10876 04:48:55.358213 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10877 04:48:55.398640 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10878 04:48:55.427761 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10879 04:48:55.617490 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10880 04:48:55.671311 Starting [0;1;39mNetwork Service[0m...
10881 04:48:55.718876 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10882 04:48:55.784674 Starting [0;1;39mNetwork Time Synchronization[0m...
10883 04:48:55.807137 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10884 04:48:56.003821 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10885 04:48:56.034602 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10886 04:48:56.103745 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10887 04:48:56.323094 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10888 04:48:56.363189 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10889 04:48:56.387881 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10890 04:48:56.402029 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10891 04:48:56.454465 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10892 04:48:56.470318 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10893 04:48:56.489214 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10894 04:48:56.502106 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10895 04:48:56.517972 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10896 04:48:57.201541 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10897 04:48:57.223654 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10898 04:48:57.552577 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10899 04:48:57.567523 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10900 04:48:57.589790 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10901 04:48:57.610580 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10902 04:48:57.621902 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10903 04:48:57.637391 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10904 04:48:57.657855 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10905 04:48:57.698388 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10906 04:48:57.750422 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10907 04:48:57.814178 Starting [0;1;39mUser Login Management[0m...
10908 04:48:57.974152 Starting [0;1;39mNetwork Name Resolution[0m...
10909 04:48:57.996357 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10910 04:48:58.078874 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10911 04:48:58.098820 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10912 04:48:58.138011 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10913 04:48:58.730865 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10914 04:48:58.751630 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10915 04:48:58.773322 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10916 04:48:58.819641 Starting [0;1;39mPermit User Sessions[0m...
10917 04:48:58.848998 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10918 04:48:58.876459 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10919 04:48:58.899141 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10920 04:48:58.916320 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10921 04:48:58.931504 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10922 04:48:58.951575 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10923 04:48:59.003966 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10924 04:48:59.043571 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10925 04:48:59.110206
10926 04:48:59.110358
10927 04:48:59.113586 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10928 04:48:59.113675
10929 04:48:59.117148 debian-bullseye-arm64 login: root (automatic login)
10930 04:48:59.117233
10931 04:48:59.117297
10932 04:48:59.475120 Linux debian-bullseye-arm64 6.1.75-cip14-rt8 #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024 aarch64
10933 04:48:59.475272
10934 04:48:59.481354 The programs included with the Debian GNU/Linux system are free software;
10935 04:48:59.488213 the exact distribution terms for each program are described in the
10936 04:48:59.491755 individual files in /usr/share/doc/*/copyright.
10937 04:48:59.491845
10938 04:48:59.498334 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10939 04:48:59.501429 permitted by applicable law.
10940 04:49:00.363668 Matched prompt #10: / #
10942 04:49:00.363950 Setting prompt string to ['/ #']
10943 04:49:00.364046 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10945 04:49:00.364243 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10946 04:49:00.364370 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10947 04:49:00.364442 Setting prompt string to ['/ #']
10948 04:49:00.364504 Forcing a shell prompt, looking for ['/ #']
10950 04:49:00.414703 / #
10951 04:49:00.414872 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10952 04:49:00.414962 Waiting using forced prompt support (timeout 00:02:30)
10953 04:49:00.419720
10954 04:49:00.420007 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10955 04:49:00.420107 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
10957 04:49:00.520445 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12699821/extract-nfsrootfs-a_4q7roz'
10958 04:49:00.525424 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12699821/extract-nfsrootfs-a_4q7roz'
10960 04:49:00.626036 / # export NFS_SERVER_IP='192.168.201.1'
10961 04:49:00.630776 export NFS_SERVER_IP='192.168.201.1'
10962 04:49:00.631108 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10963 04:49:00.631240 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10964 04:49:00.631364 end: 2 depthcharge-action (duration 00:01:26) [common]
10965 04:49:00.631456 start: 3 lava-test-retry (timeout 00:07:53) [common]
10966 04:49:00.631543 start: 3.1 lava-test-shell (timeout 00:07:53) [common]
10967 04:49:00.631620 Using namespace: common
10969 04:49:00.731982 / # #
10970 04:49:00.732168 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10971 04:49:00.736825 #
10972 04:49:00.737134 Using /lava-12699821
10974 04:49:00.837513 / # export SHELL=/bin/bash
10975 04:49:00.842479 export SHELL=/bin/bash
10977 04:49:00.943077 / # . /lava-12699821/environment
10978 04:49:00.948138 . /lava-12699821/environment
10980 04:49:01.054578 / # /lava-12699821/bin/lava-test-runner /lava-12699821/0
10981 04:49:01.054725 Test shell timeout: 10s (minimum of the action and connection timeout)
10982 04:49:01.060101 /lava-12699821/bin/lava-test-runner /lava-12699821/0
10983 04:49:01.272195 + export TESTRUN_ID=0_timesync-off
10984 04:49:01.275448 + TESTRUN_ID=0_timesync-off
10985 04:49:01.278965 + cd /lava-12699821/0/tests/0_timesync-off
10986 04:49:01.282116 ++ cat uuid
10987 04:49:01.282224 + UUID=12699821_1.6.2.3.1
10988 04:49:01.285042 + set +x
10989 04:49:01.288282 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12699821_1.6.2.3.1>
10990 04:49:01.288553 Received signal: <STARTRUN> 0_timesync-off 12699821_1.6.2.3.1
10991 04:49:01.288632 Starting test lava.0_timesync-off (12699821_1.6.2.3.1)
10992 04:49:01.288721 Skipping test definition patterns.
10993 04:49:01.291992 + systemctl stop systemd-timesyncd
10994 04:49:01.343261 + set +x
10995 04:49:01.346683 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12699821_1.6.2.3.1>
10996 04:49:01.346987 Received signal: <ENDRUN> 0_timesync-off 12699821_1.6.2.3.1
10997 04:49:01.347102 Ending use of test pattern.
10998 04:49:01.347195 Ending test lava.0_timesync-off (12699821_1.6.2.3.1), duration 0.06
11000 04:49:01.397565 + export TESTRUN_ID=1_kselftest-arm64
11001 04:49:01.397713 + TESTRUN_ID=1_kselftest-arm64
11002 04:49:01.404360 + cd /lava-12699821/0/tests/1_kselftest-arm64
11003 04:49:01.404488 ++ cat uuid
11004 04:49:01.407461 + UUID=12699821_1.6.2.3.5
11005 04:49:01.407541 + set +x
11006 04:49:01.410865 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 12699821_1.6.2.3.5>
11007 04:49:01.411142 Received signal: <STARTRUN> 1_kselftest-arm64 12699821_1.6.2.3.5
11008 04:49:01.411218 Starting test lava.1_kselftest-arm64 (12699821_1.6.2.3.5)
11009 04:49:01.411305 Skipping test definition patterns.
11010 04:49:01.414212 + cd ./automated/linux/kselftest/
11011 04:49:01.443953 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11012 04:49:01.461970 INFO: install_deps skipped
11013 04:49:01.571853 --2024-02-04 04:46:18-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11014 04:49:01.578771 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11015 04:49:01.707296 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11016 04:49:01.839933 HTTP request sent, awaiting response... 200 OK
11017 04:49:01.842968 Length: 2966368 (2.8M) [application/octet-stream]
11018 04:49:01.846014 Saving to: 'kselftest.tar.xz'
11019 04:49:01.846102
11020 04:49:01.846166
11021 04:49:02.105400 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11022 04:49:02.370468 kselftest.tar.xz 1%[ ] 49.22K 186KB/s
11023 04:49:02.684483 kselftest.tar.xz 7%[> ] 218.91K 414KB/s
11024 04:49:02.962034 kselftest.tar.xz 28%[====> ] 818.47K 971KB/s
11025 04:49:03.085061 kselftest.tar.xz 68%[============> ] 1.95M 1.74MB/s
11026 04:49:03.091323 kselftest.tar.xz 100%[===================>] 2.83M 2.27MB/s in 1.2s
11027 04:49:03.091437
11028 04:49:03.350403 2024-02-04 04:46:20 (2.27 MB/s) - 'kselftest.tar.xz' saved [2966368/2966368]
11029 04:49:03.350578
11030 04:49:08.476681 skiplist:
11031 04:49:08.480068 ========================================
11032 04:49:08.483502 ========================================
11033 04:49:08.520844 arm64:tags_test
11034 04:49:08.524495 arm64:run_tags_test.sh
11035 04:49:08.524600 arm64:fake_sigreturn_bad_magic
11036 04:49:08.527929 arm64:fake_sigreturn_bad_size
11037 04:49:08.531283 arm64:fake_sigreturn_bad_size_for_magic0
11038 04:49:08.534248 arm64:fake_sigreturn_duplicated_fpsimd
11039 04:49:08.537765 arm64:fake_sigreturn_misaligned_sp
11040 04:49:08.540963 arm64:fake_sigreturn_missing_fpsimd
11041 04:49:08.544278 arm64:fake_sigreturn_sme_change_vl
11042 04:49:08.547551 arm64:fake_sigreturn_sve_change_vl
11043 04:49:08.550497 arm64:mangle_pstate_invalid_compat_toggle
11044 04:49:08.554289 arm64:mangle_pstate_invalid_daif_bits
11045 04:49:08.557802 arm64:mangle_pstate_invalid_mode_el1h
11046 04:49:08.561140 arm64:mangle_pstate_invalid_mode_el1t
11047 04:49:08.564323 arm64:mangle_pstate_invalid_mode_el2h
11048 04:49:08.567391 arm64:mangle_pstate_invalid_mode_el2t
11049 04:49:08.570858 arm64:mangle_pstate_invalid_mode_el3h
11050 04:49:08.574287 arm64:mangle_pstate_invalid_mode_el3t
11051 04:49:08.577066 arm64:sme_trap_no_sm
11052 04:49:08.580977 arm64:sme_trap_non_streaming
11053 04:49:08.581071 arm64:sme_trap_za
11054 04:49:08.584134 arm64:sme_vl
11055 04:49:08.584223 arm64:ssve_regs
11056 04:49:08.587609 arm64:sve_regs
11057 04:49:08.587695 arm64:sve_vl
11058 04:49:08.587762 arm64:za_no_regs
11059 04:49:08.590917 arm64:za_regs
11060 04:49:08.591014 arm64:pac
11061 04:49:08.591079 arm64:fp-stress
11062 04:49:08.594476 arm64:sve-ptrace
11063 04:49:08.594569 arm64:sve-probe-vls
11064 04:49:08.597032 arm64:vec-syscfg
11065 04:49:08.597119 arm64:za-fork
11066 04:49:08.600530 arm64:za-ptrace
11067 04:49:08.600615 arm64:check_buffer_fill
11068 04:49:08.603842 arm64:check_child_memory
11069 04:49:08.607296 arm64:check_gcr_el1_cswitch
11070 04:49:08.610551 arm64:check_ksm_options
11071 04:49:08.610641 arm64:check_mmap_options
11072 04:49:08.613963 arm64:check_prctl
11073 04:49:08.614048 arm64:check_tags_inclusion
11074 04:49:08.617379 arm64:check_user_mem
11075 04:49:08.617464 arm64:btitest
11076 04:49:08.620804 arm64:nobtitest
11077 04:49:08.620892 arm64:hwcap
11078 04:49:08.623489 arm64:ptrace
11079 04:49:08.623573 arm64:syscall-abi
11080 04:49:08.623637 arm64:tpidr2
11081 04:49:08.630482 ============== Tests to run ===============
11082 04:49:08.630584 arm64:tags_test
11083 04:49:08.633433 arm64:run_tags_test.sh
11084 04:49:08.636947 arm64:fake_sigreturn_bad_magic
11085 04:49:08.637038 arm64:fake_sigreturn_bad_size
11086 04:49:08.640198 arm64:fake_sigreturn_bad_size_for_magic0
11087 04:49:08.646994 arm64:fake_sigreturn_duplicated_fpsimd
11088 04:49:08.647111 arm64:fake_sigreturn_misaligned_sp
11089 04:49:08.650257 arm64:fake_sigreturn_missing_fpsimd
11090 04:49:08.653504 arm64:fake_sigreturn_sme_change_vl
11091 04:49:08.656809 arm64:fake_sigreturn_sve_change_vl
11092 04:49:08.660232 arm64:mangle_pstate_invalid_compat_toggle
11093 04:49:08.666372 arm64:mangle_pstate_invalid_daif_bits
11094 04:49:08.670004 arm64:mangle_pstate_invalid_mode_el1h
11095 04:49:08.673234 arm64:mangle_pstate_invalid_mode_el1t
11096 04:49:08.676508 arm64:mangle_pstate_invalid_mode_el2h
11097 04:49:08.679845 arm64:mangle_pstate_invalid_mode_el2t
11098 04:49:08.683052 arm64:mangle_pstate_invalid_mode_el3h
11099 04:49:08.686865 arm64:mangle_pstate_invalid_mode_el3t
11100 04:49:08.686965 arm64:sme_trap_no_sm
11101 04:49:08.689757 arm64:sme_trap_non_streaming
11102 04:49:08.692859 arm64:sme_trap_za
11103 04:49:08.692952 arm64:sme_vl
11104 04:49:08.693040 arm64:ssve_regs
11105 04:49:08.696015 arm64:sve_regs
11106 04:49:08.696100 arm64:sve_vl
11107 04:49:08.699865 arm64:za_no_regs
11108 04:49:08.699956 arm64:za_regs
11109 04:49:08.700023 arm64:pac
11110 04:49:08.703219 arm64:fp-stress
11111 04:49:08.703305 arm64:sve-ptrace
11112 04:49:08.706024 arm64:sve-probe-vls
11113 04:49:08.706109 arm64:vec-syscfg
11114 04:49:08.709579 arm64:za-fork
11115 04:49:08.709664 arm64:za-ptrace
11116 04:49:08.712841 arm64:check_buffer_fill
11117 04:49:08.712926 arm64:check_child_memory
11118 04:49:08.716224 arm64:check_gcr_el1_cswitch
11119 04:49:08.719681 arm64:check_ksm_options
11120 04:49:08.722500 arm64:check_mmap_options
11121 04:49:08.722593 arm64:check_prctl
11122 04:49:08.725958 arm64:check_tags_inclusion
11123 04:49:08.726044 arm64:check_user_mem
11124 04:49:08.729420 arm64:btitest
11125 04:49:08.729507 arm64:nobtitest
11126 04:49:08.732771 arm64:hwcap
11127 04:49:08.732900 arm64:ptrace
11128 04:49:08.732968 arm64:syscall-abi
11129 04:49:08.736032 arm64:tpidr2
11130 04:49:08.739274 ===========End Tests to run ===============
11131 04:49:08.739359 shardfile-arm64 pass
11132 04:49:08.928157 <12>[ 36.124410] kselftest: Running tests in arm64
11133 04:49:08.928297 TAP version 13
11134 04:49:08.941513 1..48
11135 04:49:08.956519 # selftests: arm64: tags_test
11136 04:49:09.388160 ok 1 selftests: arm64: tags_test
11137 04:49:09.405797 # selftests: arm64: run_tags_test.sh
11138 04:49:09.463121 # --------------------
11139 04:49:09.466197 # running tags test
11140 04:49:09.466299 # --------------------
11141 04:49:09.469429 # [PASS]
11142 04:49:09.472807 ok 2 selftests: arm64: run_tags_test.sh
11143 04:49:09.484864 # selftests: arm64: fake_sigreturn_bad_magic
11144 04:49:09.545694 # Registered handlers for all signals.
11145 04:49:09.545832 # Detected MINSTKSIGSZ:4720
11146 04:49:09.549013 # Testcase initialized.
11147 04:49:09.552431 # uc context validated.
11148 04:49:09.555708 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11149 04:49:09.558994 # Handled SIG_COPYCTX
11150 04:49:09.559088 # Available space:3568
11151 04:49:09.565684 # Using badly built context - ERR: BAD MAGIC !
11152 04:49:09.571995 # SIG_OK -- SP:0xFFFFF50D1B20 si_addr@:0xfffff50d1b20 si_code:2 token@:0xfffff50d08c0 offset:-4704
11153 04:49:09.575287 # ==>> completed. PASS(1)
11154 04:49:09.581872 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11155 04:49:09.588439 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF50D08C0
11156 04:49:09.592257 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11157 04:49:09.598247 # selftests: arm64: fake_sigreturn_bad_size
11158 04:49:09.623478 # Registered handlers for all signals.
11159 04:49:09.623637 # Detected MINSTKSIGSZ:4720
11160 04:49:09.626842 # Testcase initialized.
11161 04:49:09.630169 # uc context validated.
11162 04:49:09.633633 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11163 04:49:09.637013 # Handled SIG_COPYCTX
11164 04:49:09.637110 # Available space:3568
11165 04:49:09.640391 # uc context validated.
11166 04:49:09.647153 # Using badly built context - ERR: Bad size for esr_context
11167 04:49:09.653160 # SIG_OK -- SP:0xFFFFFD3ECC50 si_addr@:0xfffffd3ecc50 si_code:2 token@:0xfffffd3eb9f0 offset:-4704
11168 04:49:09.656623 # ==>> completed. PASS(1)
11169 04:49:09.663531 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11170 04:49:09.669783 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFD3EB9F0
11171 04:49:09.672920 ok 4 selftests: arm64: fake_sigreturn_bad_size
11172 04:49:09.679591 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11173 04:49:09.697844 # Registered handlers for all signals.
11174 04:49:09.697981 # Detected MINSTKSIGSZ:4720
11175 04:49:09.701379 # Testcase initialized.
11176 04:49:09.704244 # uc context validated.
11177 04:49:09.707788 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11178 04:49:09.711051 # Handled SIG_COPYCTX
11179 04:49:09.711191 # Available space:3568
11180 04:49:09.717616 # Using badly built context - ERR: Bad size for terminator
11181 04:49:09.728034 # SIG_OK -- SP:0xFFFFF41B6DC0 si_addr@:0xfffff41b6dc0 si_code:2 token@:0xfffff41b5b60 offset:-4704
11182 04:49:09.728162 # ==>> completed. PASS(1)
11183 04:49:09.737628 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11184 04:49:09.743979 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF41B5B60
11185 04:49:09.747363 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11186 04:49:09.753862 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11187 04:49:09.779113 # Registered handlers for all signals.
11188 04:49:09.779251 # Detected MINSTKSIGSZ:4720
11189 04:49:09.781949 # Testcase initialized.
11190 04:49:09.785787 # uc context validated.
11191 04:49:09.788365 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11192 04:49:09.791830 # Handled SIG_COPYCTX
11193 04:49:09.791928 # Available space:3568
11194 04:49:09.798852 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11195 04:49:09.808935 # SIG_OK -- SP:0xFFFFF9D0A1E0 si_addr@:0xfffff9d0a1e0 si_code:2 token@:0xfffff9d08f80 offset:-4704
11196 04:49:09.809066 # ==>> completed. PASS(1)
11197 04:49:09.818531 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11198 04:49:09.825419 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF9D08F80
11199 04:49:09.828446 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11200 04:49:09.831700 # selftests: arm64: fake_sigreturn_misaligned_sp
11201 04:49:09.854666 # Registered handlers for all signals.
11202 04:49:09.854802 # Detected MINSTKSIGSZ:4720
11203 04:49:09.857537 # Testcase initialized.
11204 04:49:09.861182 # uc context validated.
11205 04:49:09.864324 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11206 04:49:09.867970 # Handled SIG_COPYCTX
11207 04:49:09.874456 # SIG_OK -- SP:0xFFFFD6C18063 si_addr@:0xffffd6c18063 si_code:2 token@:0xffffd6c18063 offset:0
11208 04:49:09.877851 # ==>> completed. PASS(1)
11209 04:49:09.884785 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11210 04:49:09.890812 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD6C18063
11211 04:49:09.897747 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11212 04:49:09.900633 # selftests: arm64: fake_sigreturn_missing_fpsimd
11213 04:49:09.908784 # Registered handlers for all signals.
11214 04:49:09.908904 # Detected MINSTKSIGSZ:4720
11215 04:49:09.912298 # Testcase initialized.
11216 04:49:09.915794 # uc context validated.
11217 04:49:09.919191 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11218 04:49:09.922588 # Handled SIG_COPYCTX
11219 04:49:09.926104 # Mangling template header. Spare space:4096
11220 04:49:09.928750 # Using badly built context - ERR: Missing FPSIMD
11221 04:49:09.939205 # SIG_OK -- SP:0xFFFFCD247B40 si_addr@:0xffffcd247b40 si_code:2 token@:0xffffcd2468e0 offset:-4704
11222 04:49:09.942058 # ==>> completed. PASS(1)
11223 04:49:09.948699 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11224 04:49:09.955373 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCD2468E0
11225 04:49:09.959083 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11226 04:49:09.965752 # selftests: arm64: fake_sigreturn_sme_change_vl
11227 04:49:09.989737 # Registered handlers for all signals.
11228 04:49:09.989874 # Detected MINSTKSIGSZ:4720
11229 04:49:09.993217 # ==>> completed. SKIP.
11230 04:49:09.999664 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11231 04:49:10.003065 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11232 04:49:10.009835 # selftests: arm64: fake_sigreturn_sve_change_vl
11233 04:49:10.072533 # Registered handlers for all signals.
11234 04:49:10.072673 # Detected MINSTKSIGSZ:4720
11235 04:49:10.075965 # ==>> completed. SKIP.
11236 04:49:10.079459 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11237 04:49:10.085789 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11238 04:49:10.092316 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11239 04:49:10.147028 # Registered handlers for all signals.
11240 04:49:10.147170 # Detected MINSTKSIGSZ:4720
11241 04:49:10.150341 # Testcase initialized.
11242 04:49:10.153278 # uc context validated.
11243 04:49:10.153368 # Handled SIG_TRIG
11244 04:49:10.163152 # SIG_OK -- SP:0xFFFFC68A49C0 si_addr@:0xffffc68a49c0 si_code:2 token@:(nil) offset:-281474012694976
11245 04:49:10.166709 # ==>> completed. PASS(1)
11246 04:49:10.173223 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11247 04:49:10.179713 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11248 04:49:10.183394 # selftests: arm64: mangle_pstate_invalid_daif_bits
11249 04:49:10.225031 # Registered handlers for all signals.
11250 04:49:10.225183 # Detected MINSTKSIGSZ:4720
11251 04:49:10.228116 # Testcase initialized.
11252 04:49:10.231406 # uc context validated.
11253 04:49:10.231500 # Handled SIG_TRIG
11254 04:49:10.241293 # SIG_OK -- SP:0xFFFFC5EF2BF0 si_addr@:0xffffc5ef2bf0 si_code:2 token@:(nil) offset:-281474002529264
11255 04:49:10.244678 # ==>> completed. PASS(1)
11256 04:49:10.251644 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11257 04:49:10.254331 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11258 04:49:10.261067 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11259 04:49:10.293813 # Registered handlers for all signals.
11260 04:49:10.293952 # Detected MINSTKSIGSZ:4720
11261 04:49:10.297195 # Testcase initialized.
11262 04:49:10.300326 # uc context validated.
11263 04:49:10.300435 # Handled SIG_TRIG
11264 04:49:10.310201 # SIG_OK -- SP:0xFFFFC5B559C0 si_addr@:0xffffc5b559c0 si_code:2 token@:(nil) offset:-281473998739904
11265 04:49:10.313408 # ==>> completed. PASS(1)
11266 04:49:10.320458 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11267 04:49:10.323632 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11268 04:49:10.329887 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11269 04:49:10.375125 # Registered handlers for all signals.
11270 04:49:10.375307 # Detected MINSTKSIGSZ:4720
11271 04:49:10.378410 # Testcase initialized.
11272 04:49:10.381838 # uc context validated.
11273 04:49:10.381925 # Handled SIG_TRIG
11274 04:49:10.391376 # SIG_OK -- SP:0xFFFFFDAC42D0 si_addr@:0xfffffdac42d0 si_code:2 token@:(nil) offset:-281474937668304
11275 04:49:10.394811 # ==>> completed. PASS(1)
11276 04:49:10.401467 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11277 04:49:10.404902 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11278 04:49:10.411540 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11279 04:49:10.445099 # Registered handlers for all signals.
11280 04:49:10.445251 # Detected MINSTKSIGSZ:4720
11281 04:49:10.448422 # Testcase initialized.
11282 04:49:10.451558 # uc context validated.
11283 04:49:10.451654 # Handled SIG_TRIG
11284 04:49:10.461716 # SIG_OK -- SP:0xFFFFD4608650 si_addr@:0xffffd4608650 si_code:2 token@:(nil) offset:-281474244838992
11285 04:49:10.465381 # ==>> completed. PASS(1)
11286 04:49:10.472025 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11287 04:49:10.475224 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11288 04:49:10.481948 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11289 04:49:10.510155 # Registered handlers for all signals.
11290 04:49:10.510322 # Detected MINSTKSIGSZ:4720
11291 04:49:10.513531 # Testcase initialized.
11292 04:49:10.516827 # uc context validated.
11293 04:49:10.516917 # Handled SIG_TRIG
11294 04:49:10.526870 # SIG_OK -- SP:0xFFFFE40624A0 si_addr@:0xffffe40624a0 si_code:2 token@:(nil) offset:-281474507351200
11295 04:49:10.530321 # ==>> completed. PASS(1)
11296 04:49:10.536840 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11297 04:49:10.539866 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11298 04:49:10.546843 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11299 04:49:10.585527 # Registered handlers for all signals.
11300 04:49:10.585743 # Detected MINSTKSIGSZ:4720
11301 04:49:10.588316 # Testcase initialized.
11302 04:49:10.591759 # uc context validated.
11303 04:49:10.591859 # Handled SIG_TRIG
11304 04:49:10.602215 # SIG_OK -- SP:0xFFFFC4390E40 si_addr@:0xffffc4390e40 si_code:2 token@:(nil) offset:-281473973816896
11305 04:49:10.604997 # ==>> completed. PASS(1)
11306 04:49:10.611911 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11307 04:49:10.615351 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11308 04:49:10.621280 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11309 04:49:10.652985 # Registered handlers for all signals.
11310 04:49:10.653130 # Detected MINSTKSIGSZ:4720
11311 04:49:10.656229 # Testcase initialized.
11312 04:49:10.659479 # uc context validated.
11313 04:49:10.659595 # Handled SIG_TRIG
11314 04:49:10.668856 # SIG_OK -- SP:0xFFFFEB0B0C10 si_addr@:0xffffeb0b0c10 si_code:2 token@:(nil) offset:-281474625113104
11315 04:49:10.672745 # ==>> completed. PASS(1)
11316 04:49:10.678926 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11317 04:49:10.682460 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11318 04:49:10.685786 # selftests: arm64: sme_trap_no_sm
11319 04:49:10.719646 # Registered handlers for all signals.
11320 04:49:10.719816 # Detected MINSTKSIGSZ:4720
11321 04:49:10.723637 # ==>> completed. SKIP.
11322 04:49:10.733411 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11323 04:49:10.736805 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11324 04:49:10.739513 # selftests: arm64: sme_trap_non_streaming
11325 04:49:10.794181 # Registered handlers for all signals.
11326 04:49:10.794358 # Detected MINSTKSIGSZ:4720
11327 04:49:10.797737 # ==>> completed. SKIP.
11328 04:49:10.807629 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11329 04:49:10.814535 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11330 04:49:10.817177 # selftests: arm64: sme_trap_za
11331 04:49:10.866312 # Registered handlers for all signals.
11332 04:49:10.866461 # Detected MINSTKSIGSZ:4720
11333 04:49:10.869508 # Testcase initialized.
11334 04:49:10.879410 # SIG_OK -- SP:0xFFFFEE8E6090 si_addr@:0xaaaaab092510 si_code:1 token@:(nil) offset:-187649990665488
11335 04:49:10.879620 # ==>> completed. PASS(1)
11336 04:49:10.889548 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11337 04:49:10.889672 ok 21 selftests: arm64: sme_trap_za
11338 04:49:10.892995 # selftests: arm64: sme_vl
11339 04:49:10.939829 # Registered handlers for all signals.
11340 04:49:10.939969 # Detected MINSTKSIGSZ:4720
11341 04:49:10.943542 # ==>> completed. SKIP.
11342 04:49:10.946447 # # SME VL :: Check that we get the right SME VL reported
11343 04:49:10.953437 ok 22 selftests: arm64: sme_vl # SKIP
11344 04:49:10.956494 # selftests: arm64: ssve_regs
11345 04:49:11.011958 # Registered handlers for all signals.
11346 04:49:11.012133 # Detected MINSTKSIGSZ:4720
11347 04:49:11.015235 # ==>> completed. SKIP.
11348 04:49:11.021700 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11349 04:49:11.024981 ok 23 selftests: arm64: ssve_regs # SKIP
11350 04:49:11.028404 # selftests: arm64: sve_regs
11351 04:49:11.075930 # Registered handlers for all signals.
11352 04:49:11.076077 # Detected MINSTKSIGSZ:4720
11353 04:49:11.079518 # ==>> completed. SKIP.
11354 04:49:11.086334 # # SVE registers :: Check that we get the right SVE registers reported
11355 04:49:11.089585 ok 24 selftests: arm64: sve_regs # SKIP
11356 04:49:11.092806 # selftests: arm64: sve_vl
11357 04:49:11.140330 # Registered handlers for all signals.
11358 04:49:11.140540 # Detected MINSTKSIGSZ:4720
11359 04:49:11.143019 # ==>> completed. SKIP.
11360 04:49:11.146391 # # SVE VL :: Check that we get the right SVE VL reported
11361 04:49:11.149735 ok 25 selftests: arm64: sve_vl # SKIP
11362 04:49:11.152956 # selftests: arm64: za_no_regs
11363 04:49:11.212176 # Registered handlers for all signals.
11364 04:49:11.212366 # Detected MINSTKSIGSZ:4720
11365 04:49:11.215600 # ==>> completed. SKIP.
11366 04:49:11.222444 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11367 04:49:11.225799 ok 26 selftests: arm64: za_no_regs # SKIP
11368 04:49:11.228602 # selftests: arm64: za_regs
11369 04:49:11.282280 # Registered handlers for all signals.
11370 04:49:11.282432 # Detected MINSTKSIGSZ:4720
11371 04:49:11.285215 # ==>> completed. SKIP.
11372 04:49:11.291977 # # ZA register :: Check that we get the right ZA registers reported
11373 04:49:11.295051 ok 27 selftests: arm64: za_regs # SKIP
11374 04:49:11.298170 # selftests: arm64: pac
11375 04:49:11.346324 # TAP version 13
11376 04:49:11.346480 # 1..7
11377 04:49:11.349455 # # Starting 7 tests from 1 test cases.
11378 04:49:11.352965 # # RUN global.corrupt_pac ...
11379 04:49:11.356215 # # SKIP PAUTH not enabled
11380 04:49:11.359646 # # OK global.corrupt_pac
11381 04:49:11.363123 # ok 1 # SKIP PAUTH not enabled
11382 04:49:11.369787 # # RUN global.pac_instructions_not_nop ...
11383 04:49:11.373064 # # SKIP PAUTH not enabled
11384 04:49:11.375825 # # OK global.pac_instructions_not_nop
11385 04:49:11.379278 # ok 2 # SKIP PAUTH not enabled
11386 04:49:11.386172 # # RUN global.pac_instructions_not_nop_generic ...
11387 04:49:11.389678 # # SKIP Generic PAUTH not enabled
11388 04:49:11.392550 # # OK global.pac_instructions_not_nop_generic
11389 04:49:11.399604 # ok 3 # SKIP Generic PAUTH not enabled
11390 04:49:11.402475 # # RUN global.single_thread_different_keys ...
11391 04:49:11.406138 # # SKIP PAUTH not enabled
11392 04:49:11.412547 # # OK global.single_thread_different_keys
11393 04:49:11.412657 # ok 4 # SKIP PAUTH not enabled
11394 04:49:11.419400 # # RUN global.exec_changed_keys ...
11395 04:49:11.422622 # # SKIP PAUTH not enabled
11396 04:49:11.425742 # # OK global.exec_changed_keys
11397 04:49:11.428828 # ok 5 # SKIP PAUTH not enabled
11398 04:49:11.432362 # # RUN global.context_switch_keep_keys ...
11399 04:49:11.435627 # # SKIP PAUTH not enabled
11400 04:49:11.442101 # # OK global.context_switch_keep_keys
11401 04:49:11.442217 # ok 6 # SKIP PAUTH not enabled
11402 04:49:11.448872 # # RUN global.context_switch_keep_keys_generic ...
11403 04:49:11.452414 # # SKIP Generic PAUTH not enabled
11404 04:49:11.458855 # # OK global.context_switch_keep_keys_generic
11405 04:49:11.462312 # ok 7 # SKIP Generic PAUTH not enabled
11406 04:49:11.465652 # # PASSED: 7 / 7 tests passed.
11407 04:49:11.468999 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11408 04:49:11.472512 ok 28 selftests: arm64: pac
11409 04:49:11.475105 # selftests: arm64: fp-stress
11410 04:49:16.835742 <6>[ 44.035469] vpu: disabling
11411 04:49:16.839148 <6>[ 44.035568] vproc2: disabling
11412 04:49:16.842396 <6>[ 44.035606] vproc1: disabling
11413 04:49:16.845757 <6>[ 44.035645] vaud18: disabling
11414 04:49:16.849092 <6>[ 44.035832] vsram_others: disabling
11415 04:49:16.852173 <6>[ 44.035965] va09: disabling
11416 04:49:16.855781 <6>[ 44.036021] vsram_md: disabling
11417 04:49:16.858727 <6>[ 44.036122] Vgpu: disabling
11418 04:49:21.428332 # TAP version 13
11419 04:49:21.428515 # 1..16
11420 04:49:21.431510 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11421 04:49:21.435660 # # Will run for 10s
11422 04:49:21.435782 # # Started FPSIMD-0-0
11423 04:49:21.438431 # # Started FPSIMD-0-1
11424 04:49:21.441346 # # Started FPSIMD-1-0
11425 04:49:21.441461 # # Started FPSIMD-1-1
11426 04:49:21.444858 # # Started FPSIMD-2-0
11427 04:49:21.447997 # # Started FPSIMD-2-1
11428 04:49:21.448108 # # Started FPSIMD-3-0
11429 04:49:21.451284 # # Started FPSIMD-3-1
11430 04:49:21.451402 # # Started FPSIMD-4-0
11431 04:49:21.454636 # # Started FPSIMD-4-1
11432 04:49:21.458074 # # Started FPSIMD-5-0
11433 04:49:21.458188 # # Started FPSIMD-5-1
11434 04:49:21.461369 # # Started FPSIMD-6-0
11435 04:49:21.464793 # # Started FPSIMD-6-1
11436 04:49:21.464907 # # Started FPSIMD-7-0
11437 04:49:21.468380 # # Started FPSIMD-7-1
11438 04:49:21.471625 # # FPSIMD-0-0: Vector length: 128 bits
11439 04:49:21.475128 # # FPSIMD-0-0: PID: 1166
11440 04:49:21.477824 # # FPSIMD-1-1: Vector length: 128 bits
11441 04:49:21.477938 # # FPSIMD-1-1: PID: 1169
11442 04:49:21.481707 # # FPSIMD-0-1: Vector length: 128 bits
11443 04:49:21.484635 # # FPSIMD-0-1: PID: 1167
11444 04:49:21.488263 # # FPSIMD-3-0: Vector length: 128 bits
11445 04:49:21.491660 # # FPSIMD-3-0: PID: 1172
11446 04:49:21.494800 # # FPSIMD-2-0: Vector length: 128 bits
11447 04:49:21.497815 # # FPSIMD-2-0: PID: 1170
11448 04:49:21.501308 # # FPSIMD-6-0: Vector length: 128 bits
11449 04:49:21.501428 # # FPSIMD-6-0: PID: 1178
11450 04:49:21.507881 # # FPSIMD-5-0: Vector length: 128 bits
11451 04:49:21.508003 # # FPSIMD-5-0: PID: 1176
11452 04:49:21.511373 # # FPSIMD-4-0: Vector length: 128 bits
11453 04:49:21.514673 # # FPSIMD-4-0: PID: 1174
11454 04:49:21.518101 # # FPSIMD-5-1: Vector length: 128 bits
11455 04:49:21.521507 # # FPSIMD-5-1: PID: 1177
11456 04:49:21.524724 # # FPSIMD-4-1: Vector length: 128 bits
11457 04:49:21.527591 # # FPSIMD-4-1: PID: 1175
11458 04:49:21.531103 # # FPSIMD-3-1: Vector length: 128 bits
11459 04:49:21.531220 # # FPSIMD-3-1: PID: 1173
11460 04:49:21.534525 # # FPSIMD-7-0: Vector length: 128 bits
11461 04:49:21.538028 # # FPSIMD-7-0: PID: 1180
11462 04:49:21.541389 # # FPSIMD-1-0: Vector length: 128 bits
11463 04:49:21.544601 # # FPSIMD-1-0: PID: 1168
11464 04:49:21.547992 # # FPSIMD-6-1: Vector length: 128 bits
11465 04:49:21.551419 # # FPSIMD-6-1: PID: 1179
11466 04:49:21.553977 # # FPSIMD-2-1: Vector length: 128 bits
11467 04:49:21.557707 # # FPSIMD-2-1: PID: 1171
11468 04:49:21.560689 # # FPSIMD-7-1: Vector length: 128 bits
11469 04:49:21.560771 # # FPSIMD-7-1: PID: 1181
11470 04:49:21.563916 # # Finishing up...
11471 04:49:21.570624 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1283302, signals=10
11472 04:49:21.577529 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1171376, signals=10
11473 04:49:21.584410 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1062231, signals=10
11474 04:49:21.593687 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1737024, signals=10
11475 04:49:21.600510 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1666688, signals=10
11476 04:49:21.607445 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=2102497, signals=10
11477 04:49:21.613668 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=2073862, signals=10
11478 04:49:21.616893 # ok 1 FPSIMD-0-0
11479 04:49:21.616996 # ok 2 FPSIMD-0-1
11480 04:49:21.620582 # ok 3 FPSIMD-1-0
11481 04:49:21.620665 # ok 4 FPSIMD-1-1
11482 04:49:21.623925 # ok 5 FPSIMD-2-0
11483 04:49:21.624008 # ok 6 FPSIMD-2-1
11484 04:49:21.627215 # ok 7 FPSIMD-3-0
11485 04:49:21.627313 # ok 8 FPSIMD-3-1
11486 04:49:21.630618 # ok 9 FPSIMD-4-0
11487 04:49:21.630699 # ok 10 FPSIMD-4-1
11488 04:49:21.633440 # ok 11 FPSIMD-5-0
11489 04:49:21.633521 # ok 12 FPSIMD-5-1
11490 04:49:21.636965 # ok 13 FPSIMD-6-0
11491 04:49:21.637046 # ok 14 FPSIMD-6-1
11492 04:49:21.640475 # ok 15 FPSIMD-7-0
11493 04:49:21.640573 # ok 16 FPSIMD-7-1
11494 04:49:21.646668 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=987276, signals=9
11495 04:49:21.656653 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1013493, signals=9
11496 04:49:21.663503 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=964683, signals=10
11497 04:49:21.669685 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=985690, signals=10
11498 04:49:21.676320 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1054782, signals=10
11499 04:49:21.683119 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1363089, signals=10
11500 04:49:21.689554 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=989463, signals=10
11501 04:49:21.699357 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=999273, signals=10
11502 04:49:21.706557 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=997656, signals=9
11503 04:49:21.709894 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11504 04:49:21.712700 ok 29 selftests: arm64: fp-stress
11505 04:49:21.716069 # selftests: arm64: sve-ptrace
11506 04:49:21.716150 # TAP version 13
11507 04:49:21.719313 # 1..4104
11508 04:49:21.723109 # ok 2 # SKIP SVE not available
11509 04:49:21.726066 # # Planned tests != run tests (4104 != 1)
11510 04:49:21.729692 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11511 04:49:21.732670 ok 30 selftests: arm64: sve-ptrace # SKIP
11512 04:49:21.736126 # selftests: arm64: sve-probe-vls
11513 04:49:21.739577 # TAP version 13
11514 04:49:21.739658 # 1..2
11515 04:49:21.742709 # ok 2 # SKIP SVE not available
11516 04:49:21.745732 # # Planned tests != run tests (2 != 1)
11517 04:49:21.749177 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11518 04:49:21.755820 ok 31 selftests: arm64: sve-probe-vls # SKIP
11519 04:49:21.759308 # selftests: arm64: vec-syscfg
11520 04:49:21.759390 # TAP version 13
11521 04:49:21.759454 # 1..20
11522 04:49:21.762162 # ok 1 # SKIP SVE not supported
11523 04:49:21.765653 # ok 2 # SKIP SVE not supported
11524 04:49:21.768929 # ok 3 # SKIP SVE not supported
11525 04:49:21.772247 # ok 4 # SKIP SVE not supported
11526 04:49:21.775668 # ok 5 # SKIP SVE not supported
11527 04:49:21.775749 # ok 6 # SKIP SVE not supported
11528 04:49:21.779044 # ok 7 # SKIP SVE not supported
11529 04:49:21.782377 # ok 8 # SKIP SVE not supported
11530 04:49:21.785759 # ok 9 # SKIP SVE not supported
11531 04:49:21.788989 # ok 10 # SKIP SVE not supported
11532 04:49:21.792344 # ok 11 # SKIP SME not supported
11533 04:49:21.795704 # ok 12 # SKIP SME not supported
11534 04:49:21.798821 # ok 13 # SKIP SME not supported
11535 04:49:21.798936 # ok 14 # SKIP SME not supported
11536 04:49:21.802256 # ok 15 # SKIP SME not supported
11537 04:49:21.805607 # ok 16 # SKIP SME not supported
11538 04:49:21.809131 # ok 17 # SKIP SME not supported
11539 04:49:21.811767 # ok 18 # SKIP SME not supported
11540 04:49:21.815058 # ok 19 # SKIP SME not supported
11541 04:49:21.818540 # ok 20 # SKIP SME not supported
11542 04:49:21.821854 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11543 04:49:21.825250 ok 32 selftests: arm64: vec-syscfg
11544 04:49:21.828740 # selftests: arm64: za-fork
11545 04:49:21.832158 # TAP version 13
11546 04:49:21.832258 # 1..1
11547 04:49:21.832370 # # PID: 1255
11548 04:49:21.834752 # # SME support not present
11549 04:49:21.834825 # ok 0 skipped
11550 04:49:21.841635 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11551 04:49:21.844856 ok 33 selftests: arm64: za-fork
11552 04:49:21.848056 # selftests: arm64: za-ptrace
11553 04:49:21.848129 # TAP version 13
11554 04:49:21.848190 # 1..1
11555 04:49:21.851712 # ok 2 # SKIP SME not available
11556 04:49:21.858264 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11557 04:49:21.861771 ok 34 selftests: arm64: za-ptrace # SKIP
11558 04:49:21.864644 # selftests: arm64: check_buffer_fill
11559 04:49:21.890146 # # SKIP: MTE features unavailable
11560 04:49:21.897287 ok 35 selftests: arm64: check_buffer_fill # SKIP
11561 04:49:21.911924 # selftests: arm64: check_child_memory
11562 04:49:21.964963 # # SKIP: MTE features unavailable
11563 04:49:21.973529 ok 36 selftests: arm64: check_child_memory # SKIP
11564 04:49:21.985687 # selftests: arm64: check_gcr_el1_cswitch
11565 04:49:22.036801 # # SKIP: MTE features unavailable
11566 04:49:22.043743 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11567 04:49:22.059055 # selftests: arm64: check_ksm_options
11568 04:49:22.105325 # # SKIP: MTE features unavailable
11569 04:49:22.112342 ok 38 selftests: arm64: check_ksm_options # SKIP
11570 04:49:22.129564 # selftests: arm64: check_mmap_options
11571 04:49:22.182036 # # SKIP: MTE features unavailable
11572 04:49:22.189611 ok 39 selftests: arm64: check_mmap_options # SKIP
11573 04:49:22.200134 # selftests: arm64: check_prctl
11574 04:49:22.254261 # TAP version 13
11575 04:49:22.254416 # 1..5
11576 04:49:22.257241 # ok 1 check_basic_read
11577 04:49:22.257349 # ok 2 NONE
11578 04:49:22.260393 # ok 3 # SKIP SYNC
11579 04:49:22.260471 # ok 4 # SKIP ASYNC
11580 04:49:22.263645 # ok 5 # SKIP SYNC+ASYNC
11581 04:49:22.267292 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11582 04:49:22.270199 ok 40 selftests: arm64: check_prctl
11583 04:49:22.276937 # selftests: arm64: check_tags_inclusion
11584 04:49:22.324701 # # SKIP: MTE features unavailable
11585 04:49:22.331802 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11586 04:49:22.340867 # selftests: arm64: check_user_mem
11587 04:49:22.399662 # # SKIP: MTE features unavailable
11588 04:49:22.407150 ok 42 selftests: arm64: check_user_mem # SKIP
11589 04:49:22.415342 # selftests: arm64: btitest
11590 04:49:22.491114 # TAP version 13
11591 04:49:22.491303 # 1..18
11592 04:49:22.491409 # # HWCAP_PACA not present
11593 04:49:22.491501 # # HWCAP2_BTI not present
11594 04:49:22.491589 # # Test binary built for BTI
11595 04:49:22.491682 # ok 1 nohint_func/call_using_br_x0 # SKIP
11596 04:49:22.491769 # ok 1 nohint_func/call_using_br_x16 # SKIP
11597 04:49:22.491856 # ok 1 nohint_func/call_using_blr # SKIP
11598 04:49:22.492142 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11599 04:49:22.494275 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11600 04:49:22.500852 # ok 1 bti_none_func/call_using_blr # SKIP
11601 04:49:22.504705 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11602 04:49:22.507448 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11603 04:49:22.510826 # ok 1 bti_c_func/call_using_blr # SKIP
11604 04:49:22.514149 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11605 04:49:22.517527 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11606 04:49:22.520941 # ok 1 bti_j_func/call_using_blr # SKIP
11607 04:49:22.524253 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11608 04:49:22.530473 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11609 04:49:22.533894 # ok 1 bti_jc_func/call_using_blr # SKIP
11610 04:49:22.537221 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11611 04:49:22.540541 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11612 04:49:22.544158 # ok 1 paciasp_func/call_using_blr # SKIP
11613 04:49:22.550341 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11614 04:49:22.553706 # # WARNING - EXPECTED TEST COUNT WRONG
11615 04:49:22.557060 ok 43 selftests: arm64: btitest
11616 04:49:22.560407 # selftests: arm64: nobtitest
11617 04:49:22.560487 # TAP version 13
11618 04:49:22.560561 # 1..18
11619 04:49:22.563586 # # HWCAP_PACA not present
11620 04:49:22.566657 # # HWCAP2_BTI not present
11621 04:49:22.570199 # # Test binary not built for BTI
11622 04:49:22.573245 # ok 1 nohint_func/call_using_br_x0 # SKIP
11623 04:49:22.576520 # ok 1 nohint_func/call_using_br_x16 # SKIP
11624 04:49:22.580297 # ok 1 nohint_func/call_using_blr # SKIP
11625 04:49:22.583656 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11626 04:49:22.589703 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11627 04:49:22.593108 # ok 1 bti_none_func/call_using_blr # SKIP
11628 04:49:22.596422 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11629 04:49:22.599794 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11630 04:49:22.603122 # ok 1 bti_c_func/call_using_blr # SKIP
11631 04:49:22.606343 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11632 04:49:22.610247 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11633 04:49:22.613048 # ok 1 bti_j_func/call_using_blr # SKIP
11634 04:49:22.619848 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11635 04:49:22.623276 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11636 04:49:22.626228 # ok 1 bti_jc_func/call_using_blr # SKIP
11637 04:49:22.629979 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11638 04:49:22.633339 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11639 04:49:22.636765 # ok 1 paciasp_func/call_using_blr # SKIP
11640 04:49:22.642850 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11641 04:49:22.646233 # # WARNING - EXPECTED TEST COUNT WRONG
11642 04:49:22.649670 ok 44 selftests: arm64: nobtitest
11643 04:49:22.653137 # selftests: arm64: hwcap
11644 04:49:22.653244 # TAP version 13
11645 04:49:22.653313 # 1..28
11646 04:49:22.655886 # ok 1 cpuinfo_match_RNG
11647 04:49:22.659428 # # SIGILL reported for RNG
11648 04:49:22.659515 # ok 2 # SKIP sigill_RNG
11649 04:49:22.662921 # ok 3 cpuinfo_match_SME
11650 04:49:22.666411 # ok 4 sigill_SME
11651 04:49:22.666507 # ok 5 cpuinfo_match_SVE
11652 04:49:22.669195 # ok 6 sigill_SVE
11653 04:49:22.673044 # ok 7 cpuinfo_match_SVE 2
11654 04:49:22.673160 # # SIGILL reported for SVE 2
11655 04:49:22.676213 # ok 8 # SKIP sigill_SVE 2
11656 04:49:22.679500 # ok 9 cpuinfo_match_SVE AES
11657 04:49:22.682438 # # SIGILL reported for SVE AES
11658 04:49:22.686394 # ok 10 # SKIP sigill_SVE AES
11659 04:49:22.686514 # ok 11 cpuinfo_match_SVE2 PMULL
11660 04:49:22.689585 # # SIGILL reported for SVE2 PMULL
11661 04:49:22.692637 # ok 12 # SKIP sigill_SVE2 PMULL
11662 04:49:22.695702 # ok 13 cpuinfo_match_SVE2 BITPERM
11663 04:49:22.699483 # # SIGILL reported for SVE2 BITPERM
11664 04:49:22.702879 # ok 14 # SKIP sigill_SVE2 BITPERM
11665 04:49:22.705588 # ok 15 cpuinfo_match_SVE2 SHA3
11666 04:49:22.709071 # # SIGILL reported for SVE2 SHA3
11667 04:49:22.712485 # ok 16 # SKIP sigill_SVE2 SHA3
11668 04:49:22.715947 # ok 17 cpuinfo_match_SVE2 SM4
11669 04:49:22.719287 # # SIGILL reported for SVE2 SM4
11670 04:49:22.719371 # ok 18 # SKIP sigill_SVE2 SM4
11671 04:49:22.722660 # ok 19 cpuinfo_match_SVE2 I8MM
11672 04:49:22.726230 # # SIGILL reported for SVE2 I8MM
11673 04:49:22.729102 # ok 20 # SKIP sigill_SVE2 I8MM
11674 04:49:22.732495 # ok 21 cpuinfo_match_SVE2 F32MM
11675 04:49:22.735487 # # SIGILL reported for SVE2 F32MM
11676 04:49:22.739514 # ok 22 # SKIP sigill_SVE2 F32MM
11677 04:49:22.742274 # ok 23 cpuinfo_match_SVE2 F64MM
11678 04:49:22.745600 # # SIGILL reported for SVE2 F64MM
11679 04:49:22.745685 # ok 24 # SKIP sigill_SVE2 F64MM
11680 04:49:22.748915 # ok 25 cpuinfo_match_SVE2 BF16
11681 04:49:22.752421 # # SIGILL reported for SVE2 BF16
11682 04:49:22.755649 # ok 26 # SKIP sigill_SVE2 BF16
11683 04:49:22.759196 # ok 27 cpuinfo_match_SVE2 EBF16
11684 04:49:22.762572 # ok 28 # SKIP sigill_SVE2 EBF16
11685 04:49:22.765985 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11686 04:49:22.768789 ok 45 selftests: arm64: hwcap
11687 04:49:22.772205 # selftests: arm64: ptrace
11688 04:49:22.772339 # TAP version 13
11689 04:49:22.775611 # 1..7
11690 04:49:22.779049 # # Parent is 1497, child is 1498
11691 04:49:22.779181 # ok 1 read_tpidr_one
11692 04:49:22.782471 # ok 2 write_tpidr_one
11693 04:49:22.782589 # ok 3 verify_tpidr_one
11694 04:49:22.785783 # ok 4 count_tpidrs
11695 04:49:22.789076 # ok 5 tpidr2_write
11696 04:49:22.789191 # ok 6 tpidr2_read
11697 04:49:22.792262 # ok 7 write_tpidr_only
11698 04:49:22.795482 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11699 04:49:22.798741 ok 46 selftests: arm64: ptrace
11700 04:49:22.802058 # selftests: arm64: syscall-abi
11701 04:49:22.802186 # TAP version 13
11702 04:49:22.805811 # 1..2
11703 04:49:22.805924 # ok 1 getpid() FPSIMD
11704 04:49:22.808939 # ok 2 sched_yield() FPSIMD
11705 04:49:22.815743 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11706 04:49:22.815859 ok 47 selftests: arm64: syscall-abi
11707 04:49:22.819088 # selftests: arm64: tpidr2
11708 04:49:22.829396 # TAP version 13
11709 04:49:22.829517 # 1..5
11710 04:49:22.832674 # # PID: 1534
11711 04:49:22.832792 # # SME support not present
11712 04:49:22.835936 # ok 0 skipped, TPIDR2 not supported
11713 04:49:22.839161 # ok 1 skipped, TPIDR2 not supported
11714 04:49:22.842604 # ok 2 skipped, TPIDR2 not supported
11715 04:49:22.845478 # ok 3 skipped, TPIDR2 not supported
11716 04:49:22.848982 # ok 4 skipped, TPIDR2 not supported
11717 04:49:22.855615 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11718 04:49:22.858699 ok 48 selftests: arm64: tpidr2
11719 04:49:23.461600 arm64_tags_test pass
11720 04:49:23.464887 arm64_run_tags_test_sh pass
11721 04:49:23.468352 arm64_fake_sigreturn_bad_magic pass
11722 04:49:23.471768 arm64_fake_sigreturn_bad_size pass
11723 04:49:23.475151 arm64_fake_sigreturn_bad_size_for_magic0 pass
11724 04:49:23.478544 arm64_fake_sigreturn_duplicated_fpsimd pass
11725 04:49:23.481408 arm64_fake_sigreturn_misaligned_sp pass
11726 04:49:23.485335 arm64_fake_sigreturn_missing_fpsimd pass
11727 04:49:23.487806 arm64_fake_sigreturn_sme_change_vl skip
11728 04:49:23.491777 arm64_fake_sigreturn_sve_change_vl skip
11729 04:49:23.498191 arm64_mangle_pstate_invalid_compat_toggle pass
11730 04:49:23.501601 arm64_mangle_pstate_invalid_daif_bits pass
11731 04:49:23.504807 arm64_mangle_pstate_invalid_mode_el1h pass
11732 04:49:23.508010 arm64_mangle_pstate_invalid_mode_el1t pass
11733 04:49:23.511193 arm64_mangle_pstate_invalid_mode_el2h pass
11734 04:49:23.514732 arm64_mangle_pstate_invalid_mode_el2t pass
11735 04:49:23.520796 arm64_mangle_pstate_invalid_mode_el3h pass
11736 04:49:23.524255 arm64_mangle_pstate_invalid_mode_el3t pass
11737 04:49:23.527795 arm64_sme_trap_no_sm skip
11738 04:49:23.527915 arm64_sme_trap_non_streaming skip
11739 04:49:23.531180 arm64_sme_trap_za pass
11740 04:49:23.534608 arm64_sme_vl skip
11741 04:49:23.534718 arm64_ssve_regs skip
11742 04:49:23.537368 arm64_sve_regs skip
11743 04:49:23.537478 arm64_sve_vl skip
11744 04:49:23.540869 arm64_za_no_regs skip
11745 04:49:23.540984 arm64_za_regs skip
11746 04:49:23.544039 arm64_pac_pauth_not_enabled skip
11747 04:49:23.547397 arm64_pac_pauth_not_enabled skip
11748 04:49:23.550825 arm64_pac_generic_pauth_not_enabled skip
11749 04:49:23.554225 arm64_pac_pauth_not_enabled skip
11750 04:49:23.557524 arm64_pac_pauth_not_enabled skip
11751 04:49:23.560784 arm64_pac_pauth_not_enabled skip
11752 04:49:23.564176 arm64_pac_generic_pauth_not_enabled skip
11753 04:49:23.564309 arm64_pac pass
11754 04:49:23.567617 arm64_fp-stress_FPSIMD-0-0 pass
11755 04:49:23.570451 arm64_fp-stress_FPSIMD-0-1 pass
11756 04:49:23.574252 arm64_fp-stress_FPSIMD-1-0 pass
11757 04:49:23.577404 arm64_fp-stress_FPSIMD-1-1 pass
11758 04:49:23.581092 arm64_fp-stress_FPSIMD-2-0 pass
11759 04:49:23.583805 arm64_fp-stress_FPSIMD-2-1 pass
11760 04:49:23.583915 arm64_fp-stress_FPSIMD-3-0 pass
11761 04:49:23.587071 arm64_fp-stress_FPSIMD-3-1 pass
11762 04:49:23.590623 arm64_fp-stress_FPSIMD-4-0 pass
11763 04:49:23.593986 arm64_fp-stress_FPSIMD-4-1 pass
11764 04:49:23.597152 arm64_fp-stress_FPSIMD-5-0 pass
11765 04:49:23.600518 arm64_fp-stress_FPSIMD-5-1 pass
11766 04:49:23.603436 arm64_fp-stress_FPSIMD-6-0 pass
11767 04:49:23.607034 arm64_fp-stress_FPSIMD-6-1 pass
11768 04:49:23.607126 arm64_fp-stress_FPSIMD-7-0 pass
11769 04:49:23.610154 arm64_fp-stress_FPSIMD-7-1 pass
11770 04:49:23.613483 arm64_fp-stress pass
11771 04:49:23.617186 arm64_sve-ptrace_sve_not_available skip
11772 04:49:23.620493 arm64_sve-ptrace skip
11773 04:49:23.623861 arm64_sve-probe-vls_sve_not_available skip
11774 04:49:23.623977 arm64_sve-probe-vls skip
11775 04:49:23.626515 arm64_vec-syscfg_sve_not_supported skip
11776 04:49:23.633280 arm64_vec-syscfg_sve_not_supported skip
11777 04:49:23.636778 arm64_vec-syscfg_sve_not_supported skip
11778 04:49:23.640222 arm64_vec-syscfg_sve_not_supported skip
11779 04:49:23.643154 arm64_vec-syscfg_sve_not_supported skip
11780 04:49:23.646526 arm64_vec-syscfg_sve_not_supported skip
11781 04:49:23.650204 arm64_vec-syscfg_sve_not_supported skip
11782 04:49:23.653424 arm64_vec-syscfg_sve_not_supported skip
11783 04:49:23.656641 arm64_vec-syscfg_sve_not_supported skip
11784 04:49:23.659925 arm64_vec-syscfg_sve_not_supported skip
11785 04:49:23.663362 arm64_vec-syscfg_sme_not_supported skip
11786 04:49:23.666858 arm64_vec-syscfg_sme_not_supported skip
11787 04:49:23.669656 arm64_vec-syscfg_sme_not_supported skip
11788 04:49:23.673025 arm64_vec-syscfg_sme_not_supported skip
11789 04:49:23.679824 arm64_vec-syscfg_sme_not_supported skip
11790 04:49:23.682947 arm64_vec-syscfg_sme_not_supported skip
11791 04:49:23.686453 arm64_vec-syscfg_sme_not_supported skip
11792 04:49:23.689861 arm64_vec-syscfg_sme_not_supported skip
11793 04:49:23.692997 arm64_vec-syscfg_sme_not_supported skip
11794 04:49:23.696470 arm64_vec-syscfg_sme_not_supported skip
11795 04:49:23.696603 arm64_vec-syscfg pass
11796 04:49:23.699924 arm64_za-fork_skipped pass
11797 04:49:23.703390 arm64_za-fork pass
11798 04:49:23.706641 arm64_za-ptrace_sme_not_available skip
11799 04:49:23.706749 arm64_za-ptrace skip
11800 04:49:23.709985 arm64_check_buffer_fill skip
11801 04:49:23.713155 arm64_check_child_memory skip
11802 04:49:23.716475 arm64_check_gcr_el1_cswitch skip
11803 04:49:23.719413 arm64_check_ksm_options skip
11804 04:49:23.719526 arm64_check_mmap_options skip
11805 04:49:23.722643 arm64_check_prctl_check_basic_read pass
11806 04:49:23.726325 arm64_check_prctl_NONE pass
11807 04:49:23.729789 arm64_check_prctl_sync skip
11808 04:49:23.732517 arm64_check_prctl_async skip
11809 04:49:23.735903 arm64_check_prctl_sync_async skip
11810 04:49:23.736018 arm64_check_prctl pass
11811 04:49:23.739611 arm64_check_tags_inclusion skip
11812 04:49:23.742428 arm64_check_user_mem skip
11813 04:49:23.745881 arm64_btitest_nohint_func_call_using_br_x0 skip
11814 04:49:23.752668 arm64_btitest_nohint_func_call_using_br_x16 skip
11815 04:49:23.755932 arm64_btitest_nohint_func_call_using_blr skip
11816 04:49:23.759120 arm64_btitest_bti_none_func_call_using_br_x0 skip
11817 04:49:23.762376 arm64_btitest_bti_none_func_call_using_br_x16 skip
11818 04:49:23.769123 arm64_btitest_bti_none_func_call_using_blr skip
11819 04:49:23.772574 arm64_btitest_bti_c_func_call_using_br_x0 skip
11820 04:49:23.775403 arm64_btitest_bti_c_func_call_using_br_x16 skip
11821 04:49:23.782143 arm64_btitest_bti_c_func_call_using_blr skip
11822 04:49:23.785463 arm64_btitest_bti_j_func_call_using_br_x0 skip
11823 04:49:23.788685 arm64_btitest_bti_j_func_call_using_br_x16 skip
11824 04:49:23.792020 arm64_btitest_bti_j_func_call_using_blr skip
11825 04:49:23.798851 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11826 04:49:23.801949 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11827 04:49:23.805136 arm64_btitest_bti_jc_func_call_using_blr skip
11828 04:49:23.808701 arm64_btitest_paciasp_func_call_using_br_x0 skip
11829 04:49:23.814847 arm64_btitest_paciasp_func_call_using_br_x16 skip
11830 04:49:23.818842 arm64_btitest_paciasp_func_call_using_blr skip
11831 04:49:23.821494 arm64_btitest pass
11832 04:49:23.825301 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11833 04:49:23.828691 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11834 04:49:23.834752 arm64_nobtitest_nohint_func_call_using_blr skip
11835 04:49:23.838111 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11836 04:49:23.841339 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11837 04:49:23.847998 arm64_nobtitest_bti_none_func_call_using_blr skip
11838 04:49:23.851564 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11839 04:49:23.854515 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11840 04:49:23.861368 arm64_nobtitest_bti_c_func_call_using_blr skip
11841 04:49:23.864819 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11842 04:49:23.868079 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11843 04:49:23.874544 arm64_nobtitest_bti_j_func_call_using_blr skip
11844 04:49:23.877487 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11845 04:49:23.881050 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11846 04:49:23.887962 arm64_nobtitest_bti_jc_func_call_using_blr skip
11847 04:49:23.891235 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11848 04:49:23.894076 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11849 04:49:23.901000 arm64_nobtitest_paciasp_func_call_using_blr skip
11850 04:49:23.901121 arm64_nobtitest pass
11851 04:49:23.904222 arm64_hwcap_cpuinfo_match_RNG pass
11852 04:49:23.907413 arm64_hwcap_sigill_rng skip
11853 04:49:23.910640 arm64_hwcap_cpuinfo_match_SME pass
11854 04:49:23.914243 arm64_hwcap_sigill_SME pass
11855 04:49:23.917510 arm64_hwcap_cpuinfo_match_SVE pass
11856 04:49:23.917624 arm64_hwcap_sigill_SVE pass
11857 04:49:23.920820 arm64_hwcap_cpuinfo_match_SVE_2 pass
11858 04:49:23.924309 arm64_hwcap_sigill_sve_2 skip
11859 04:49:23.927584 arm64_hwcap_cpuinfo_match_SVE_AES pass
11860 04:49:23.930926 arm64_hwcap_sigill_sve_aes skip
11861 04:49:23.934237 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11862 04:49:23.936976 arm64_hwcap_sigill_sve2_pmull skip
11863 04:49:23.940687 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11864 04:49:23.944307 arm64_hwcap_sigill_sve2_bitperm skip
11865 04:49:23.947077 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11866 04:49:23.950611 arm64_hwcap_sigill_sve2_sha3 skip
11867 04:49:23.954002 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11868 04:49:23.957553 arm64_hwcap_sigill_sve2_sm4 skip
11869 04:49:23.960171 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11870 04:49:23.964141 arm64_hwcap_sigill_sve2_i8mm skip
11871 04:49:23.970635 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11872 04:49:23.970760 arm64_hwcap_sigill_sve2_f32mm skip
11873 04:49:23.977012 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11874 04:49:23.980610 arm64_hwcap_sigill_sve2_f64mm skip
11875 04:49:23.983366 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11876 04:49:23.987025 arm64_hwcap_sigill_sve2_bf16 skip
11877 04:49:23.990500 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11878 04:49:23.993981 arm64_hwcap_sigill_sve2_ebf16 skip
11879 04:49:23.994065 arm64_hwcap pass
11880 04:49:23.996604 arm64_ptrace_read_tpidr_one pass
11881 04:49:24.000073 arm64_ptrace_write_tpidr_one pass
11882 04:49:24.003585 arm64_ptrace_verify_tpidr_one pass
11883 04:49:24.007089 arm64_ptrace_count_tpidrs pass
11884 04:49:24.010005 arm64_ptrace_tpidr2_write pass
11885 04:49:24.010118 arm64_ptrace_tpidr2_read pass
11886 04:49:24.013458 arm64_ptrace_write_tpidr_only pass
11887 04:49:24.016904 arm64_ptrace pass
11888 04:49:24.020358 arm64_syscall-abi_getpid_FPSIMD pass
11889 04:49:24.023069 arm64_syscall-abi_sched_yield_FPSIMD pass
11890 04:49:24.026727 arm64_syscall-abi pass
11891 04:49:24.030233 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11892 04:49:24.033636 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11893 04:49:24.036326 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11894 04:49:24.043560 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11895 04:49:24.046317 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11896 04:49:24.046431 arm64_tpidr2 pass
11897 04:49:24.053124 + ../../utils/send-to-lava.sh ./output/result.txt
11898 04:49:24.056521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11899 04:49:24.056844 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11901 04:49:24.063348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11902 04:49:24.063633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11904 04:49:24.069939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11905 04:49:24.070226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11907 04:49:24.076100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11908 04:49:24.076383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11910 04:49:24.082755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11911 04:49:24.083041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11913 04:49:24.089851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11914 04:49:24.090134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11916 04:49:24.099185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11917 04:49:24.099470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11919 04:49:24.132219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11920 04:49:24.132540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11922 04:49:24.170024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11923 04:49:24.170360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11925 04:49:24.204687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11926 04:49:24.204995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11928 04:49:24.236867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11929 04:49:24.237164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
11931 04:49:24.273436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
11932 04:49:24.273755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
11934 04:49:24.307612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
11935 04:49:24.307907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
11937 04:49:24.337645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
11938 04:49:24.337932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
11940 04:49:24.377025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
11941 04:49:24.377348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
11943 04:49:24.417129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
11944 04:49:24.417492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
11946 04:49:24.451406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
11947 04:49:24.451712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
11949 04:49:24.489636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
11950 04:49:24.490008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
11952 04:49:24.525130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
11953 04:49:24.525466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
11955 04:49:24.555877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
11956 04:49:24.556199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
11958 04:49:24.592107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
11960 04:49:24.595312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
11961 04:49:24.625852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
11962 04:49:24.626162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
11964 04:49:24.661527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
11965 04:49:24.661859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
11967 04:49:24.699534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
11968 04:49:24.699869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
11970 04:49:24.735312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
11971 04:49:24.735606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
11973 04:49:24.772142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
11974 04:49:24.772457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
11976 04:49:24.810157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
11977 04:49:24.810482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
11979 04:49:24.849610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
11980 04:49:24.849906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
11982 04:49:24.886650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11984 04:49:24.889840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11985 04:49:24.921571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11987 04:49:24.924779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11988 04:49:24.962899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
11989 04:49:24.963195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
11991 04:49:24.996271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11993 04:49:24.999389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11994 04:49:25.030370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11996 04:49:25.032864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11997 04:49:25.063764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11999 04:49:25.067057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12000 04:49:25.100856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12001 04:49:25.101154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12003 04:49:25.136169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12004 04:49:25.136472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12006 04:49:25.173528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12007 04:49:25.173832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12009 04:49:25.207084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12010 04:49:25.207411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12012 04:49:25.240917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12013 04:49:25.241241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12015 04:49:25.271459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12016 04:49:25.271780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12018 04:49:25.312075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12019 04:49:25.312408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12021 04:49:25.348149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12022 04:49:25.348488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12024 04:49:25.389677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12025 04:49:25.390022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12027 04:49:25.426494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12028 04:49:25.426844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12030 04:49:25.465576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12031 04:49:25.465910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12033 04:49:25.498450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12034 04:49:25.498786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12036 04:49:25.534681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12037 04:49:25.535033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12039 04:49:25.573749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12040 04:49:25.574094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12042 04:49:25.608827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12043 04:49:25.609177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12045 04:49:25.647412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12046 04:49:25.647731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12048 04:49:25.686792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12049 04:49:25.687135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12051 04:49:25.722427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12052 04:49:25.722784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12054 04:49:25.753616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12055 04:49:25.753957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12057 04:49:25.789567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip>
12058 04:49:25.789917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip
12060 04:49:25.825627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12061 04:49:25.825964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12063 04:49:25.867303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip>
12064 04:49:25.867618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip
12066 04:49:25.900055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12067 04:49:25.900388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12069 04:49:25.936169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12070 04:49:25.936514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12072 04:49:25.969323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12073 04:49:25.969655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12075 04:49:26.004415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12076 04:49:26.004748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12078 04:49:26.036601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12079 04:49:26.036933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12081 04:49:26.068983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12082 04:49:26.069312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12084 04:49:26.108276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12085 04:49:26.108619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12087 04:49:26.142280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12088 04:49:26.142636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12090 04:49:26.176495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12091 04:49:26.176832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12093 04:49:26.208034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12094 04:49:26.208380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12096 04:49:26.245518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12097 04:49:26.245833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12099 04:49:26.280898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12100 04:49:26.281237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12102 04:49:26.316338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12103 04:49:26.316693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12105 04:49:26.357472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12106 04:49:26.357787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12108 04:49:26.392486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12109 04:49:26.392798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12111 04:49:26.431244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12112 04:49:26.431555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12114 04:49:26.465398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12115 04:49:26.465708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12117 04:49:26.496331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12118 04:49:26.496622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12120 04:49:26.531820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12121 04:49:26.532115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12123 04:49:26.565222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12124 04:49:26.565499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12126 04:49:26.601277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12127 04:49:26.601605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12129 04:49:26.636489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12130 04:49:26.636769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12132 04:49:26.675209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12133 04:49:26.675531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12135 04:49:26.710905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12136 04:49:26.711196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12138 04:49:26.756740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip>
12139 04:49:26.757033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip
12141 04:49:26.790669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12142 04:49:26.790952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12144 04:49:26.827909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12145 04:49:26.828200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12147 04:49:26.869401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12148 04:49:26.869673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12150 04:49:26.906424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12152 04:49:26.909682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12153 04:49:26.945628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12154 04:49:26.945927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12156 04:49:26.984125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12157 04:49:26.984398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12159 04:49:27.021139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12160 04:49:27.021436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12162 04:49:27.054579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12163 04:49:27.054857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12165 04:49:27.094916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip>
12166 04:49:27.095210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip
12168 04:49:27.133660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_async RESULT=skip>
12169 04:49:27.133934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_async RESULT=skip
12171 04:49:27.172503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip
12173 04:49:27.175731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip>
12174 04:49:27.214048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12175 04:49:27.214334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12177 04:49:27.257670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12178 04:49:27.257938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12180 04:49:27.295132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12181 04:49:27.295403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12183 04:49:27.340663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12184 04:49:27.340939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12186 04:49:27.376953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12187 04:49:27.377214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12189 04:49:27.418536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12190 04:49:27.418817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12192 04:49:27.463760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12193 04:49:27.464091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12195 04:49:27.508712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12196 04:49:27.508987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12198 04:49:27.549114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12199 04:49:27.549384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12201 04:49:27.587889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12202 04:49:27.588156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12204 04:49:27.628187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12205 04:49:27.628481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12207 04:49:27.676850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12208 04:49:27.677132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12210 04:49:27.716071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12211 04:49:27.716401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12213 04:49:27.752396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12214 04:49:27.752713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12216 04:49:27.793239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12217 04:49:27.793568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12219 04:49:27.833018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12220 04:49:27.833340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12222 04:49:27.873189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12223 04:49:27.873519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12225 04:49:27.912824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12226 04:49:27.913145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12228 04:49:27.952841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12229 04:49:27.953172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12231 04:49:27.996456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12232 04:49:27.996793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12234 04:49:28.040222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12235 04:49:28.040563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12237 04:49:28.079452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12238 04:49:28.079809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12240 04:49:28.122395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12241 04:49:28.122723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12243 04:49:28.159296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12244 04:49:28.159624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12246 04:49:28.196918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12247 04:49:28.197254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12249 04:49:28.235634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12250 04:49:28.235980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12252 04:49:28.272348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12253 04:49:28.272706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12255 04:49:28.308889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12256 04:49:28.309255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12258 04:49:28.349364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12259 04:49:28.349706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12261 04:49:28.387592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12262 04:49:28.387949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12264 04:49:28.428604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12265 04:49:28.428961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12267 04:49:28.464459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12268 04:49:28.464775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12270 04:49:28.496696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12271 04:49:28.497005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12273 04:49:28.536414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12274 04:49:28.536779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12276 04:49:28.573241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12277 04:49:28.573570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12279 04:49:28.607032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12280 04:49:28.607336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12282 04:49:28.640839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12283 04:49:28.641156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12285 04:49:28.685066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12286 04:49:28.685395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12288 04:49:28.724793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12289 04:49:28.725103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12291 04:49:28.759210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12292 04:49:28.759526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12294 04:49:28.790766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12295 04:49:28.791057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12297 04:49:28.829132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12298 04:49:28.829453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12300 04:49:28.858215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip>
12301 04:49:28.858541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip
12303 04:49:28.897542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12305 04:49:28.900614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12306 04:49:28.932883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12307 04:49:28.933210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12309 04:49:28.969682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12310 04:49:28.970005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12312 04:49:29.002762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12313 04:49:29.003095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12315 04:49:29.042021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12316 04:49:29.042405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12318 04:49:29.076817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip>
12319 04:49:29.077134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip
12321 04:49:29.115687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12322 04:49:29.115995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12324 04:49:29.144728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip>
12325 04:49:29.145045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip
12327 04:49:29.188488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12328 04:49:29.188827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12330 04:49:29.226167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip
12332 04:49:29.228689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip>
12333 04:49:29.268755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12334 04:49:29.269066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12336 04:49:29.302563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip>
12337 04:49:29.303001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip
12339 04:49:29.337886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12340 04:49:29.338289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12342 04:49:29.370935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip
12344 04:49:29.374231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip>
12345 04:49:29.406996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12346 04:49:29.407312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12348 04:49:29.439306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip
12350 04:49:29.442191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip>
12351 04:49:29.477877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12352 04:49:29.478292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12354 04:49:29.509271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip
12356 04:49:29.511701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip>
12357 04:49:29.547205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12358 04:49:29.547610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12360 04:49:29.582411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip>
12361 04:49:29.582763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip
12363 04:49:29.617450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12364 04:49:29.617758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12366 04:49:29.651477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip>
12367 04:49:29.651842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip
12369 04:49:29.685065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12370 04:49:29.685341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12372 04:49:29.716241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip
12374 04:49:29.719338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip>
12375 04:49:29.755360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12376 04:49:29.755657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12378 04:49:29.789958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip>
12379 04:49:29.790232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip
12381 04:49:29.820736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12382 04:49:29.821008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12384 04:49:29.858224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12386 04:49:29.861200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12387 04:49:29.896984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12389 04:49:29.899647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12390 04:49:29.935890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12391 04:49:29.936169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12393 04:49:29.970583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12394 04:49:29.970859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12396 04:49:30.008703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12397 04:49:30.009013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12399 04:49:30.043708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12400 04:49:30.043986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12402 04:49:30.082603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12403 04:49:30.082874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12405 04:49:30.116209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12406 04:49:30.116583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12408 04:49:30.154244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12409 04:49:30.154570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12411 04:49:30.192944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12412 04:49:30.193227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12414 04:49:30.226190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12415 04:49:30.226506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12417 04:49:30.265425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12418 04:49:30.265724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12420 04:49:30.298325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12421 04:49:30.298606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12423 04:49:30.334464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12424 04:49:30.334776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12426 04:49:30.369231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12427 04:49:30.369530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12429 04:49:30.404713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12430 04:49:30.405010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12432 04:49:30.443479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12433 04:49:30.443624 + set +x
12434 04:49:30.443902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12436 04:49:30.450358 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 12699821_1.6.2.3.5>
12437 04:49:30.450639 Received signal: <ENDRUN> 1_kselftest-arm64 12699821_1.6.2.3.5
12438 04:49:30.450740 Ending use of test pattern.
12439 04:49:30.450828 Ending test lava.1_kselftest-arm64 (12699821_1.6.2.3.5), duration 29.04
12441 04:49:30.453168 <LAVA_TEST_RUNNER EXIT>
12442 04:49:30.453442 ok: lava_test_shell seems to have completed
12443 04:49:30.455481 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_async: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_sync: skip
arm64_check_prctl_sync_async: skip
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_rng: skip
arm64_hwcap_sigill_sve2_bf16: skip
arm64_hwcap_sigill_sve2_bitperm: skip
arm64_hwcap_sigill_sve2_ebf16: skip
arm64_hwcap_sigill_sve2_f32mm: skip
arm64_hwcap_sigill_sve2_f64mm: skip
arm64_hwcap_sigill_sve2_i8mm: skip
arm64_hwcap_sigill_sve2_pmull: skip
arm64_hwcap_sigill_sve2_sha3: skip
arm64_hwcap_sigill_sve2_sm4: skip
arm64_hwcap_sigill_sve_2: skip
arm64_hwcap_sigill_sve_aes: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_generic_pauth_not_enabled: skip
arm64_pac_pauth_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_sve_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_sve_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_sme_not_supported: skip
arm64_vec-syscfg_sve_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_sme_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12444 04:49:30.455658 end: 3.1 lava-test-shell (duration 00:00:30) [common]
12445 04:49:30.455808 end: 3 lava-test-retry (duration 00:00:30) [common]
12446 04:49:30.455927 start: 4 finalize (timeout 00:07:23) [common]
12447 04:49:30.456044 start: 4.1 power-off (timeout 00:00:30) [common]
12448 04:49:30.456329 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
12449 04:49:30.533221 >> Command sent successfully.
12450 04:49:30.536050 Returned 0 in 0 seconds
12451 04:49:30.636441 end: 4.1 power-off (duration 00:00:00) [common]
12453 04:49:30.636774 start: 4.2 read-feedback (timeout 00:07:23) [common]
12454 04:49:30.637068 Listened to connection for namespace 'common' for up to 1s
12455 04:49:31.637996 Finalising connection for namespace 'common'
12456 04:49:31.638168 Disconnecting from shell: Finalise
12457 04:49:31.638252 / #
12458 04:49:31.738587 end: 4.2 read-feedback (duration 00:00:01) [common]
12459 04:49:31.738755 end: 4 finalize (duration 00:00:01) [common]
12460 04:49:31.738867 Cleaning after the job
12461 04:49:31.738964 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/ramdisk
12462 04:49:31.741799 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/kernel
12463 04:49:31.755327 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/dtb
12464 04:49:31.755534 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/nfsrootfs
12465 04:49:31.847583 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699821/tftp-deploy-ystyxgkl/modules
12466 04:49:31.854996 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12699821
12467 04:49:32.551102 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12699821
12468 04:49:32.551307 Job finished correctly