Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 14
- Kernel Errors: 33
1 04:45:07.901769 lava-dispatcher, installed at version: 2023.10
2 04:45:07.901995 start: 0 validate
3 04:45:07.902134 Start time: 2024-02-04 04:45:07.902126+00:00 (UTC)
4 04:45:07.902253 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:45:07.902384 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 04:45:08.164443 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:45:08.165100 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:45:08.435449 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:45:08.436249 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:45:08.699095 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:45:08.700006 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 04:45:08.964445 Using caching service: 'http://localhost/cache/?uri=%s'
13 04:45:08.965211 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 04:45:09.241551 validate duration: 1.34
16 04:45:09.242678 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:45:09.243179 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:45:09.243908 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:45:09.244513 Not decompressing ramdisk as can be used compressed.
20 04:45:09.244966 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 04:45:09.245318 saving as /var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/ramdisk/initrd.cpio.gz
22 04:45:09.245663 total size: 4665395 (4 MB)
23 04:45:09.250457 progress 0 % (0 MB)
24 04:45:09.257927 progress 5 % (0 MB)
25 04:45:09.264600 progress 10 % (0 MB)
26 04:45:09.269157 progress 15 % (0 MB)
27 04:45:09.272769 progress 20 % (0 MB)
28 04:45:09.275877 progress 25 % (1 MB)
29 04:45:09.278658 progress 30 % (1 MB)
30 04:45:09.281123 progress 35 % (1 MB)
31 04:45:09.283392 progress 40 % (1 MB)
32 04:45:09.285790 progress 45 % (2 MB)
33 04:45:09.287738 progress 50 % (2 MB)
34 04:45:09.289686 progress 55 % (2 MB)
35 04:45:09.291407 progress 60 % (2 MB)
36 04:45:09.293113 progress 65 % (2 MB)
37 04:45:09.294826 progress 70 % (3 MB)
38 04:45:09.296363 progress 75 % (3 MB)
39 04:45:09.297883 progress 80 % (3 MB)
40 04:45:09.299687 progress 85 % (3 MB)
41 04:45:09.301100 progress 90 % (4 MB)
42 04:45:09.302474 progress 95 % (4 MB)
43 04:45:09.303873 progress 100 % (4 MB)
44 04:45:09.304043 4 MB downloaded in 0.06 s (76.17 MB/s)
45 04:45:09.304209 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:45:09.304475 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:45:09.304570 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:45:09.304662 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:45:09.304819 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 04:45:09.304891 saving as /var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/kernel/Image
52 04:45:09.304953 total size: 51597824 (49 MB)
53 04:45:09.305014 No compression specified
54 04:45:09.306146 progress 0 % (0 MB)
55 04:45:09.319587 progress 5 % (2 MB)
56 04:45:09.332984 progress 10 % (4 MB)
57 04:45:09.346388 progress 15 % (7 MB)
58 04:45:09.359747 progress 20 % (9 MB)
59 04:45:09.373105 progress 25 % (12 MB)
60 04:45:09.386408 progress 30 % (14 MB)
61 04:45:09.399795 progress 35 % (17 MB)
62 04:45:09.412953 progress 40 % (19 MB)
63 04:45:09.426389 progress 45 % (22 MB)
64 04:45:09.439972 progress 50 % (24 MB)
65 04:45:09.453371 progress 55 % (27 MB)
66 04:45:09.466611 progress 60 % (29 MB)
67 04:45:09.480006 progress 65 % (32 MB)
68 04:45:09.493375 progress 70 % (34 MB)
69 04:45:09.506603 progress 75 % (36 MB)
70 04:45:09.519979 progress 80 % (39 MB)
71 04:45:09.533279 progress 85 % (41 MB)
72 04:45:09.546755 progress 90 % (44 MB)
73 04:45:09.559771 progress 95 % (46 MB)
74 04:45:09.572818 progress 100 % (49 MB)
75 04:45:09.573022 49 MB downloaded in 0.27 s (183.57 MB/s)
76 04:45:09.573171 end: 1.2.1 http-download (duration 00:00:00) [common]
78 04:45:09.573406 end: 1.2 download-retry (duration 00:00:00) [common]
79 04:45:09.573492 start: 1.3 download-retry (timeout 00:10:00) [common]
80 04:45:09.573579 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 04:45:09.573723 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 04:45:09.573791 saving as /var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/dtb/mt8192-asurada-spherion-r0.dtb
83 04:45:09.573852 total size: 47278 (0 MB)
84 04:45:09.573912 No compression specified
85 04:45:09.575035 progress 69 % (0 MB)
86 04:45:09.575308 progress 100 % (0 MB)
87 04:45:09.575538 0 MB downloaded in 0.00 s (26.77 MB/s)
88 04:45:09.575663 end: 1.3.1 http-download (duration 00:00:00) [common]
90 04:45:09.575886 end: 1.3 download-retry (duration 00:00:00) [common]
91 04:45:09.575973 start: 1.4 download-retry (timeout 00:10:00) [common]
92 04:45:09.576055 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 04:45:09.576171 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 04:45:09.576238 saving as /var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/nfsrootfs/full.rootfs.tar
95 04:45:09.576298 total size: 200813988 (191 MB)
96 04:45:09.576358 Using unxz to decompress xz
97 04:45:09.580311 progress 0 % (0 MB)
98 04:45:10.109324 progress 5 % (9 MB)
99 04:45:10.637150 progress 10 % (19 MB)
100 04:45:11.226666 progress 15 % (28 MB)
101 04:45:11.600104 progress 20 % (38 MB)
102 04:45:11.923964 progress 25 % (47 MB)
103 04:45:12.511945 progress 30 % (57 MB)
104 04:45:13.058798 progress 35 % (67 MB)
105 04:45:13.655561 progress 40 % (76 MB)
106 04:45:14.217272 progress 45 % (86 MB)
107 04:45:14.806710 progress 50 % (95 MB)
108 04:45:15.440092 progress 55 % (105 MB)
109 04:45:16.105709 progress 60 % (114 MB)
110 04:45:16.225707 progress 65 % (124 MB)
111 04:45:16.366902 progress 70 % (134 MB)
112 04:45:16.463860 progress 75 % (143 MB)
113 04:45:16.536841 progress 80 % (153 MB)
114 04:45:16.606195 progress 85 % (162 MB)
115 04:45:16.708783 progress 90 % (172 MB)
116 04:45:16.986225 progress 95 % (181 MB)
117 04:45:17.560673 progress 100 % (191 MB)
118 04:45:17.566136 191 MB downloaded in 7.99 s (23.97 MB/s)
119 04:45:17.566408 end: 1.4.1 http-download (duration 00:00:08) [common]
121 04:45:17.566709 end: 1.4 download-retry (duration 00:00:08) [common]
122 04:45:17.566798 start: 1.5 download-retry (timeout 00:09:52) [common]
123 04:45:17.566885 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 04:45:17.567048 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 04:45:17.567127 saving as /var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/modules/modules.tar
126 04:45:17.567190 total size: 8633524 (8 MB)
127 04:45:17.567253 Using unxz to decompress xz
128 04:45:17.571660 progress 0 % (0 MB)
129 04:45:17.593193 progress 5 % (0 MB)
130 04:45:17.617970 progress 10 % (0 MB)
131 04:45:17.641413 progress 15 % (1 MB)
132 04:45:17.664561 progress 20 % (1 MB)
133 04:45:17.688628 progress 25 % (2 MB)
134 04:45:17.716475 progress 30 % (2 MB)
135 04:45:17.742021 progress 35 % (2 MB)
136 04:45:17.766897 progress 40 % (3 MB)
137 04:45:17.791391 progress 45 % (3 MB)
138 04:45:17.816908 progress 50 % (4 MB)
139 04:45:17.841213 progress 55 % (4 MB)
140 04:45:17.867823 progress 60 % (4 MB)
141 04:45:17.893343 progress 65 % (5 MB)
142 04:45:17.918510 progress 70 % (5 MB)
143 04:45:17.942721 progress 75 % (6 MB)
144 04:45:17.969960 progress 80 % (6 MB)
145 04:45:17.995431 progress 85 % (7 MB)
146 04:45:18.022095 progress 90 % (7 MB)
147 04:45:18.051663 progress 95 % (7 MB)
148 04:45:18.079487 progress 100 % (8 MB)
149 04:45:18.084941 8 MB downloaded in 0.52 s (15.90 MB/s)
150 04:45:18.085196 end: 1.5.1 http-download (duration 00:00:01) [common]
152 04:45:18.085480 end: 1.5 download-retry (duration 00:00:01) [common]
153 04:45:18.085573 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 04:45:18.085668 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 04:45:21.932231 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12699825/extract-nfsrootfs-wnf_mrip
156 04:45:21.932421 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 04:45:21.932525 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 04:45:21.932708 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5
159 04:45:21.932849 makedir: /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin
160 04:45:21.932960 makedir: /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/tests
161 04:45:21.933069 makedir: /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/results
162 04:45:21.933173 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-add-keys
163 04:45:21.933322 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-add-sources
164 04:45:21.933459 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-background-process-start
165 04:45:21.933592 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-background-process-stop
166 04:45:21.933722 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-common-functions
167 04:45:21.933896 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-echo-ipv4
168 04:45:21.934047 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-install-packages
169 04:45:21.934195 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-installed-packages
170 04:45:21.934323 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-os-build
171 04:45:21.934471 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-probe-channel
172 04:45:21.934638 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-probe-ip
173 04:45:21.934783 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-target-ip
174 04:45:21.934915 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-target-mac
175 04:45:21.935043 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-target-storage
176 04:45:21.935180 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-test-case
177 04:45:21.935324 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-test-event
178 04:45:21.935509 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-test-feedback
179 04:45:21.935638 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-test-raise
180 04:45:21.935790 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-test-reference
181 04:45:21.935919 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-test-runner
182 04:45:21.936055 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-test-set
183 04:45:21.936189 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-test-shell
184 04:45:21.936333 Updating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-add-keys (debian)
185 04:45:21.936501 Updating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-add-sources (debian)
186 04:45:21.936647 Updating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-install-packages (debian)
187 04:45:21.936799 Updating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-installed-packages (debian)
188 04:45:21.936953 Updating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/bin/lava-os-build (debian)
189 04:45:21.937087 Creating /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/environment
190 04:45:21.937185 LAVA metadata
191 04:45:21.937270 - LAVA_JOB_ID=12699825
192 04:45:21.937334 - LAVA_DISPATCHER_IP=192.168.201.1
193 04:45:21.937448 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 04:45:21.937529 skipped lava-vland-overlay
195 04:45:21.937608 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 04:45:21.937691 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 04:45:21.937753 skipped lava-multinode-overlay
198 04:45:21.937849 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 04:45:21.937941 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 04:45:21.938021 Loading test definitions
201 04:45:21.938113 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 04:45:21.938194 Using /lava-12699825 at stage 0
203 04:45:21.938522 uuid=12699825_1.6.2.3.1 testdef=None
204 04:45:21.938614 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 04:45:21.938709 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 04:45:21.939209 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 04:45:21.939489 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 04:45:21.940218 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 04:45:21.940451 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 04:45:21.941000 runner path: /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/0/tests/0_timesync-off test_uuid 12699825_1.6.2.3.1
213 04:45:21.941155 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 04:45:21.941383 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 04:45:21.941461 Using /lava-12699825 at stage 0
217 04:45:21.941562 Fetching tests from https://github.com/kernelci/test-definitions.git
218 04:45:21.941643 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/0/tests/1_kselftest-rtc'
219 04:45:27.271726 Running '/usr/bin/git checkout kernelci.org
220 04:45:27.419763 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 04:45:27.420505 uuid=12699825_1.6.2.3.5 testdef=None
222 04:45:27.420666 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 04:45:27.420923 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 04:45:27.421670 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 04:45:27.421917 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 04:45:27.422889 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 04:45:27.423127 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 04:45:27.424104 runner path: /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/0/tests/1_kselftest-rtc test_uuid 12699825_1.6.2.3.5
232 04:45:27.424195 BOARD='mt8192-asurada-spherion-r0'
233 04:45:27.424261 BRANCH='cip-gitlab'
234 04:45:27.424322 SKIPFILE='/dev/null'
235 04:45:27.424381 SKIP_INSTALL='True'
236 04:45:27.424439 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 04:45:27.424499 TST_CASENAME=''
238 04:45:27.424555 TST_CMDFILES='rtc'
239 04:45:27.424698 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 04:45:27.424901 Creating lava-test-runner.conf files
242 04:45:27.424964 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12699825/lava-overlay-hx1nlub5/lava-12699825/0 for stage 0
243 04:45:27.425057 - 0_timesync-off
244 04:45:27.425128 - 1_kselftest-rtc
245 04:45:27.425226 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 04:45:27.425314 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 04:45:34.891805 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 04:45:34.891965 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:34) [common]
249 04:45:34.892060 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 04:45:34.892159 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 04:45:34.892252 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
252 04:45:35.011604 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 04:45:35.011990 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 04:45:35.012104 extracting modules file /var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699825/extract-nfsrootfs-wnf_mrip
255 04:45:35.238425 extracting modules file /var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699825/extract-overlay-ramdisk-1k4m7f_o/ramdisk
256 04:45:35.475999 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 04:45:35.476170 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 04:45:35.476266 [common] Applying overlay to NFS
259 04:45:35.476339 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699825/compress-overlay-v3ybbmjk/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12699825/extract-nfsrootfs-wnf_mrip
260 04:45:36.393899 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 04:45:36.394069 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 04:45:36.394163 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 04:45:36.394254 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 04:45:36.394333 Building ramdisk /var/lib/lava/dispatcher/tmp/12699825/extract-overlay-ramdisk-1k4m7f_o/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12699825/extract-overlay-ramdisk-1k4m7f_o/ramdisk
265 04:45:36.719967 >> 119436 blocks
266 04:45:38.618599 rename /var/lib/lava/dispatcher/tmp/12699825/extract-overlay-ramdisk-1k4m7f_o/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/ramdisk/ramdisk.cpio.gz
267 04:45:38.619054 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 04:45:38.619174 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 04:45:38.619280 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 04:45:38.619423 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/kernel/Image'
271 04:45:51.129248 Returned 0 in 12 seconds
272 04:45:51.229888 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/kernel/image.itb
273 04:45:51.591157 output: FIT description: Kernel Image image with one or more FDT blobs
274 04:45:51.591563 output: Created: Sun Feb 4 04:45:51 2024
275 04:45:51.591642 output: Image 0 (kernel-1)
276 04:45:51.591708 output: Description:
277 04:45:51.591767 output: Created: Sun Feb 4 04:45:51 2024
278 04:45:51.591826 output: Type: Kernel Image
279 04:45:51.591886 output: Compression: lzma compressed
280 04:45:51.591946 output: Data Size: 12048508 Bytes = 11766.12 KiB = 11.49 MiB
281 04:45:51.592003 output: Architecture: AArch64
282 04:45:51.592061 output: OS: Linux
283 04:45:51.592120 output: Load Address: 0x00000000
284 04:45:51.592178 output: Entry Point: 0x00000000
285 04:45:51.592238 output: Hash algo: crc32
286 04:45:51.592295 output: Hash value: 3b31d50c
287 04:45:51.592349 output: Image 1 (fdt-1)
288 04:45:51.592403 output: Description: mt8192-asurada-spherion-r0
289 04:45:51.592456 output: Created: Sun Feb 4 04:45:51 2024
290 04:45:51.592510 output: Type: Flat Device Tree
291 04:45:51.592563 output: Compression: uncompressed
292 04:45:51.592617 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 04:45:51.592670 output: Architecture: AArch64
294 04:45:51.592723 output: Hash algo: crc32
295 04:45:51.592776 output: Hash value: cc4352de
296 04:45:51.592829 output: Image 2 (ramdisk-1)
297 04:45:51.592882 output: Description: unavailable
298 04:45:51.592935 output: Created: Sun Feb 4 04:45:51 2024
299 04:45:51.592989 output: Type: RAMDisk Image
300 04:45:51.593042 output: Compression: Unknown Compression
301 04:45:51.593095 output: Data Size: 17796204 Bytes = 17379.11 KiB = 16.97 MiB
302 04:45:51.593149 output: Architecture: AArch64
303 04:45:51.593202 output: OS: Linux
304 04:45:51.593255 output: Load Address: unavailable
305 04:45:51.593308 output: Entry Point: unavailable
306 04:45:51.593360 output: Hash algo: crc32
307 04:45:51.593413 output: Hash value: 7d5c327a
308 04:45:51.593466 output: Default Configuration: 'conf-1'
309 04:45:51.593519 output: Configuration 0 (conf-1)
310 04:45:51.593572 output: Description: mt8192-asurada-spherion-r0
311 04:45:51.593625 output: Kernel: kernel-1
312 04:45:51.593678 output: Init Ramdisk: ramdisk-1
313 04:45:51.593730 output: FDT: fdt-1
314 04:45:51.593782 output: Loadables: kernel-1
315 04:45:51.593834 output:
316 04:45:51.594036 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 04:45:51.594136 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 04:45:51.594247 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 04:45:51.594340 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 04:45:51.594416 No LXC device requested
321 04:45:51.594494 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 04:45:51.594575 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 04:45:51.594655 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 04:45:51.594726 Checking files for TFTP limit of 4294967296 bytes.
325 04:45:51.595234 end: 1 tftp-deploy (duration 00:00:42) [common]
326 04:45:51.595340 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 04:45:51.595495 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 04:45:51.595620 substitutions:
329 04:45:51.595689 - {DTB}: 12699825/tftp-deploy-qo_ublru/dtb/mt8192-asurada-spherion-r0.dtb
330 04:45:51.595755 - {INITRD}: 12699825/tftp-deploy-qo_ublru/ramdisk/ramdisk.cpio.gz
331 04:45:51.595816 - {KERNEL}: 12699825/tftp-deploy-qo_ublru/kernel/Image
332 04:45:51.595877 - {LAVA_MAC}: None
333 04:45:51.595935 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12699825/extract-nfsrootfs-wnf_mrip
334 04:45:51.595992 - {NFS_SERVER_IP}: 192.168.201.1
335 04:45:51.596048 - {PRESEED_CONFIG}: None
336 04:45:51.596103 - {PRESEED_LOCAL}: None
337 04:45:51.596159 - {RAMDISK}: 12699825/tftp-deploy-qo_ublru/ramdisk/ramdisk.cpio.gz
338 04:45:51.596213 - {ROOT_PART}: None
339 04:45:51.596267 - {ROOT}: None
340 04:45:51.596321 - {SERVER_IP}: 192.168.201.1
341 04:45:51.596375 - {TEE}: None
342 04:45:51.596429 Parsed boot commands:
343 04:45:51.596484 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 04:45:51.596670 Parsed boot commands: tftpboot 192.168.201.1 12699825/tftp-deploy-qo_ublru/kernel/image.itb 12699825/tftp-deploy-qo_ublru/kernel/cmdline
345 04:45:51.596779 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 04:45:51.596908 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 04:45:51.597000 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 04:45:51.597087 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 04:45:51.597159 Not connected, no need to disconnect.
350 04:45:51.597233 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 04:45:51.597313 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 04:45:51.597379 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 04:45:51.601334 Setting prompt string to ['lava-test: # ']
354 04:45:51.601707 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 04:45:51.601814 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 04:45:51.601916 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 04:45:51.602008 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 04:45:51.602207 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 04:45:56.751758 >> Command sent successfully.
360 04:45:56.754262 Returned 0 in 5 seconds
361 04:45:56.855022 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 04:45:56.856481 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 04:45:56.857042 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 04:45:56.857733 Setting prompt string to 'Starting depthcharge on Spherion...'
366 04:45:56.858210 Changing prompt to 'Starting depthcharge on Spherion...'
367 04:45:56.858586 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 04:45:56.859858 [Enter `^Ec?' for help]
369 04:45:57.030396
370 04:45:57.030978
371 04:45:57.031533 F0: 102B 0000
372 04:45:57.031883
373 04:45:57.032206 F3: 1001 0000 [0200]
374 04:45:57.032513
375 04:45:57.033733 F3: 1001 0000
376 04:45:57.034163
377 04:45:57.034501 F7: 102D 0000
378 04:45:57.034817
379 04:45:57.035137 F1: 0000 0000
380 04:45:57.035495
381 04:45:57.037237 V0: 0000 0000 [0001]
382 04:45:57.037715
383 04:45:57.038057 00: 0007 8000
384 04:45:57.038397
385 04:45:57.040667 01: 0000 0000
386 04:45:57.041165
387 04:45:57.041506 BP: 0C00 0209 [0000]
388 04:45:57.041825
389 04:45:57.044382 G0: 1182 0000
390 04:45:57.044881
391 04:45:57.045227 EC: 0000 0021 [4000]
392 04:45:57.045542
393 04:45:57.048386 S7: 0000 0000 [0000]
394 04:45:57.048812
395 04:45:57.049151 CC: 0000 0000 [0001]
396 04:45:57.049466
397 04:45:57.051780 T0: 0000 0040 [010F]
398 04:45:57.052208
399 04:45:57.052546 Jump to BL
400 04:45:57.052861
401 04:45:57.076890
402 04:45:57.077467
403 04:45:57.077819
404 04:45:57.084068 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 04:45:57.087919 ARM64: Exception handlers installed.
406 04:45:57.091563 ARM64: Testing exception
407 04:45:57.091647 ARM64: Done test exception
408 04:45:57.098947 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 04:45:57.110886 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 04:45:57.117466 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 04:45:57.127080 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 04:45:57.133971 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 04:45:57.143704 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 04:45:57.154554 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 04:45:57.160474 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 04:45:57.178899 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 04:45:57.182442 WDT: Last reset was cold boot
418 04:45:57.185518 SPI1(PAD0) initialized at 2873684 Hz
419 04:45:57.189163 SPI5(PAD0) initialized at 992727 Hz
420 04:45:57.192529 VBOOT: Loading verstage.
421 04:45:57.199041 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 04:45:57.201856 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 04:45:57.205440 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 04:45:57.208693 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 04:45:57.216823 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 04:45:57.222840 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 04:45:57.233923 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 04:45:57.234007
429 04:45:57.234072
430 04:45:57.244148 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 04:45:57.246999 ARM64: Exception handlers installed.
432 04:45:57.250612 ARM64: Testing exception
433 04:45:57.253828 ARM64: Done test exception
434 04:45:57.257607 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 04:45:57.261047 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 04:45:57.275493 Probing TPM: . done!
437 04:45:57.275575 TPM ready after 0 ms
438 04:45:57.283724 Connected to device vid:did:rid of 1ae0:0028:00
439 04:45:57.290092 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 04:45:57.347646 Initialized TPM device CR50 revision 0
441 04:45:57.357819 tlcl_send_startup: Startup return code is 0
442 04:45:57.357909 TPM: setup succeeded
443 04:45:57.369443 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 04:45:57.377994 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 04:45:57.388975 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 04:45:57.398173 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 04:45:57.401369 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 04:45:57.413639 in-header: 03 07 00 00 08 00 00 00
449 04:45:57.416639 in-data: aa e4 47 04 13 02 00 00
450 04:45:57.419802 Chrome EC: UHEPI supported
451 04:45:57.427730 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 04:45:57.431503 in-header: 03 95 00 00 08 00 00 00
453 04:45:57.431591 in-data: 18 20 20 08 00 00 00 00
454 04:45:57.434751 Phase 1
455 04:45:57.438962 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 04:45:57.442360 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 04:45:57.449667 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 04:45:57.453588 Recovery requested (1009000e)
459 04:45:57.461470 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 04:45:57.466677 tlcl_extend: response is 0
461 04:45:57.475868 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 04:45:57.481899 tlcl_extend: response is 0
463 04:45:57.488408 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 04:45:57.508828 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 04:45:57.515574 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 04:45:57.516073
467 04:45:57.516488
468 04:45:57.525377 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 04:45:57.528859 ARM64: Exception handlers installed.
470 04:45:57.532312 ARM64: Testing exception
471 04:45:57.532783 ARM64: Done test exception
472 04:45:57.554467 pmic_efuse_setting: Set efuses in 11 msecs
473 04:45:57.558157 pmwrap_interface_init: Select PMIF_VLD_RDY
474 04:45:57.564512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 04:45:57.567608 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 04:45:57.575064 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 04:45:57.578356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 04:45:57.581668 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 04:45:57.588941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 04:45:57.593080 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 04:45:57.597128 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 04:45:57.600476 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 04:45:57.607789 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 04:45:57.612080 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 04:45:57.615233 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 04:45:57.618932 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 04:45:57.626096 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 04:45:57.633215 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 04:45:57.637262 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 04:45:57.644436 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 04:45:57.648313 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 04:45:57.655669 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 04:45:57.659536 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 04:45:57.666323 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 04:45:57.670172 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 04:45:57.677815 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 04:45:57.681536 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 04:45:57.688730 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 04:45:57.692077 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 04:45:57.699914 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 04:45:57.702890 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 04:45:57.710024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 04:45:57.713813 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 04:45:57.717749 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 04:45:57.724847 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 04:45:57.728732 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 04:45:57.732186 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 04:45:57.739247 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 04:45:57.742665 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 04:45:57.749741 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 04:45:57.753536 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 04:45:57.757266 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 04:45:57.760944 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 04:45:57.764590 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 04:45:57.771960 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 04:45:57.776178 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 04:45:57.779034 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 04:45:57.782696 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 04:45:57.789846 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 04:45:57.793610 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 04:45:57.797362 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 04:45:57.801065 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 04:45:57.804344 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 04:45:57.808487 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 04:45:57.815310 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 04:45:57.826306 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 04:45:57.830084 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 04:45:57.836713 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 04:45:57.847985 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 04:45:57.852005 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 04:45:57.855773 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 04:45:57.858927 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 04:45:57.867576 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x3b
534 04:45:57.874167 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 04:45:57.877614 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 04:45:57.881111 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 04:45:57.891638 [RTC]rtc_get_frequency_meter,154: input=15, output=852
538 04:45:57.902278 [RTC]rtc_get_frequency_meter,154: input=7, output=724
539 04:45:57.910409 [RTC]rtc_get_frequency_meter,154: input=11, output=789
540 04:45:57.921145 [RTC]rtc_get_frequency_meter,154: input=13, output=823
541 04:45:57.929923 [RTC]rtc_get_frequency_meter,154: input=12, output=805
542 04:45:57.939601 [RTC]rtc_get_frequency_meter,154: input=11, output=789
543 04:45:57.949022 [RTC]rtc_get_frequency_meter,154: input=12, output=804
544 04:45:57.953175 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 04:45:57.956295 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 04:45:57.963908 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 04:45:57.968414 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 04:45:57.971417 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 04:45:57.975287 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 04:45:57.979185 ADC[4]: Raw value=904064 ID=7
551 04:45:57.979671 ADC[3]: Raw value=213916 ID=1
552 04:45:57.983106 RAM Code: 0x71
553 04:45:57.987067 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 04:45:57.990395 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 04:45:58.001771 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 04:45:58.005502 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 04:45:58.008385 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 04:45:58.012602 in-header: 03 07 00 00 08 00 00 00
559 04:45:58.016409 in-data: aa e4 47 04 13 02 00 00
560 04:45:58.020063 Chrome EC: UHEPI supported
561 04:45:58.026839 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 04:45:58.030739 in-header: 03 95 00 00 08 00 00 00
563 04:45:58.033781 in-data: 18 20 20 08 00 00 00 00
564 04:45:58.038529 MRC: failed to locate region type 0.
565 04:45:58.041779 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 04:45:58.045888 DRAM-K: Running full calibration
567 04:45:58.053134 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 04:45:58.053690 header.status = 0x0
569 04:45:58.057024 header.version = 0x6 (expected: 0x6)
570 04:45:58.060851 header.size = 0xd00 (expected: 0xd00)
571 04:45:58.061350 header.flags = 0x0
572 04:45:58.067052 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 04:45:58.086813 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 04:45:58.094031 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 04:45:58.097486 dram_init: ddr_geometry: 2
576 04:45:58.097932 [EMI] MDL number = 2
577 04:45:58.101366 [EMI] Get MDL freq = 0
578 04:45:58.101892 dram_init: ddr_type: 0
579 04:45:58.104928 is_discrete_lpddr4: 1
580 04:45:58.108416 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 04:45:58.108847
582 04:45:58.109189
583 04:45:58.109506 [Bian_co] ETT version 0.0.0.1
584 04:45:58.115917 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 04:45:58.116351
586 04:45:58.119242 dramc_set_vcore_voltage set vcore to 650000
587 04:45:58.119793 Read voltage for 800, 4
588 04:45:58.123744 Vio18 = 0
589 04:45:58.124358 Vcore = 650000
590 04:45:58.124852 Vdram = 0
591 04:45:58.127077 Vddq = 0
592 04:45:58.127549 Vmddr = 0
593 04:45:58.128100 dram_init: config_dvfs: 1
594 04:45:58.133712 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 04:45:58.137709 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 04:45:58.141262 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 04:45:58.144959 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 04:45:58.148098 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 04:45:58.155446 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 04:45:58.156118 MEM_TYPE=3, freq_sel=18
601 04:45:58.159172 sv_algorithm_assistance_LP4_1600
602 04:45:58.162637 ============ PULL DRAM RESETB DOWN ============
603 04:45:58.166481 ========== PULL DRAM RESETB DOWN end =========
604 04:45:58.173896 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 04:45:58.174668 ===================================
606 04:45:58.177243 LPDDR4 DRAM CONFIGURATION
607 04:45:58.180154 ===================================
608 04:45:58.184130 EX_ROW_EN[0] = 0x0
609 04:45:58.184601 EX_ROW_EN[1] = 0x0
610 04:45:58.187016 LP4Y_EN = 0x0
611 04:45:58.187607 WORK_FSP = 0x0
612 04:45:58.190273 WL = 0x2
613 04:45:58.190698 RL = 0x2
614 04:45:58.194097 BL = 0x2
615 04:45:58.194567 RPST = 0x0
616 04:45:58.197088 RD_PRE = 0x0
617 04:45:58.197596 WR_PRE = 0x1
618 04:45:58.200087 WR_PST = 0x0
619 04:45:58.203825 DBI_WR = 0x0
620 04:45:58.204349 DBI_RD = 0x0
621 04:45:58.207279 OTF = 0x1
622 04:45:58.210494 ===================================
623 04:45:58.213722 ===================================
624 04:45:58.214246 ANA top config
625 04:45:58.217527 ===================================
626 04:45:58.220091 DLL_ASYNC_EN = 0
627 04:45:58.220580 ALL_SLAVE_EN = 1
628 04:45:58.223508 NEW_RANK_MODE = 1
629 04:45:58.226989 DLL_IDLE_MODE = 1
630 04:45:58.229964 LP45_APHY_COMB_EN = 1
631 04:45:58.233614 TX_ODT_DIS = 1
632 04:45:58.234180 NEW_8X_MODE = 1
633 04:45:58.236871 ===================================
634 04:45:58.239845 ===================================
635 04:45:58.243501 data_rate = 1600
636 04:45:58.246525 CKR = 1
637 04:45:58.249825 DQ_P2S_RATIO = 8
638 04:45:58.253664 ===================================
639 04:45:58.256921 CA_P2S_RATIO = 8
640 04:45:58.257353 DQ_CA_OPEN = 0
641 04:45:58.260556 DQ_SEMI_OPEN = 0
642 04:45:58.263515 CA_SEMI_OPEN = 0
643 04:45:58.267636 CA_FULL_RATE = 0
644 04:45:58.270308 DQ_CKDIV4_EN = 1
645 04:45:58.273815 CA_CKDIV4_EN = 1
646 04:45:58.274339 CA_PREDIV_EN = 0
647 04:45:58.277738 PH8_DLY = 0
648 04:45:58.280413 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 04:45:58.283891 DQ_AAMCK_DIV = 4
650 04:45:58.287160 CA_AAMCK_DIV = 4
651 04:45:58.290314 CA_ADMCK_DIV = 4
652 04:45:58.290741 DQ_TRACK_CA_EN = 0
653 04:45:58.293821 CA_PICK = 800
654 04:45:58.297300 CA_MCKIO = 800
655 04:45:58.301097 MCKIO_SEMI = 0
656 04:45:58.304343 PLL_FREQ = 3068
657 04:45:58.307934 DQ_UI_PI_RATIO = 32
658 04:45:58.308364 CA_UI_PI_RATIO = 0
659 04:45:58.311318 ===================================
660 04:45:58.315444 ===================================
661 04:45:58.319353 memory_type:LPDDR4
662 04:45:58.319819 GP_NUM : 10
663 04:45:58.322382 SRAM_EN : 1
664 04:45:58.322809 MD32_EN : 0
665 04:45:58.326578 ===================================
666 04:45:58.329887 [ANA_INIT] >>>>>>>>>>>>>>
667 04:45:58.333401 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 04:45:58.337275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 04:45:58.340173 ===================================
670 04:45:58.340601 data_rate = 1600,PCW = 0X7600
671 04:45:58.343880 ===================================
672 04:45:58.347088 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 04:45:58.353902 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 04:45:58.360157 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 04:45:58.363730 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 04:45:58.367531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 04:45:58.370244 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 04:45:58.373293 [ANA_INIT] flow start
679 04:45:58.376678 [ANA_INIT] PLL >>>>>>>>
680 04:45:58.377112 [ANA_INIT] PLL <<<<<<<<
681 04:45:58.380491 [ANA_INIT] MIDPI >>>>>>>>
682 04:45:58.383642 [ANA_INIT] MIDPI <<<<<<<<
683 04:45:58.384073 [ANA_INIT] DLL >>>>>>>>
684 04:45:58.386776 [ANA_INIT] flow end
685 04:45:58.390096 ============ LP4 DIFF to SE enter ============
686 04:45:58.393381 ============ LP4 DIFF to SE exit ============
687 04:45:58.397013 [ANA_INIT] <<<<<<<<<<<<<
688 04:45:58.400396 [Flow] Enable top DCM control >>>>>
689 04:45:58.403243 [Flow] Enable top DCM control <<<<<
690 04:45:58.406608 Enable DLL master slave shuffle
691 04:45:58.413422 ==============================================================
692 04:45:58.413961 Gating Mode config
693 04:45:58.419972 ==============================================================
694 04:45:58.420402 Config description:
695 04:45:58.429938 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 04:45:58.436736 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 04:45:58.443873 SELPH_MODE 0: By rank 1: By Phase
698 04:45:58.446918 ==============================================================
699 04:45:58.449806 GAT_TRACK_EN = 1
700 04:45:58.453145 RX_GATING_MODE = 2
701 04:45:58.456782 RX_GATING_TRACK_MODE = 2
702 04:45:58.460125 SELPH_MODE = 1
703 04:45:58.463437 PICG_EARLY_EN = 1
704 04:45:58.466665 VALID_LAT_VALUE = 1
705 04:45:58.473417 ==============================================================
706 04:45:58.476230 Enter into Gating configuration >>>>
707 04:45:58.480284 Exit from Gating configuration <<<<
708 04:45:58.483210 Enter into DVFS_PRE_config >>>>>
709 04:45:58.493069 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 04:45:58.496601 Exit from DVFS_PRE_config <<<<<
711 04:45:58.500225 Enter into PICG configuration >>>>
712 04:45:58.503445 Exit from PICG configuration <<<<
713 04:45:58.506401 [RX_INPUT] configuration >>>>>
714 04:45:58.506925 [RX_INPUT] configuration <<<<<
715 04:45:58.513177 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 04:45:58.519863 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 04:45:58.523108 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 04:45:58.529307 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 04:45:58.536349 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 04:45:58.542906 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 04:45:58.546418 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 04:45:58.549529 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 04:45:58.555868 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 04:45:58.559650 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 04:45:58.563170 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 04:45:58.569406 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 04:45:58.572472 ===================================
728 04:45:58.572906 LPDDR4 DRAM CONFIGURATION
729 04:45:58.576012 ===================================
730 04:45:58.579071 EX_ROW_EN[0] = 0x0
731 04:45:58.579635 EX_ROW_EN[1] = 0x0
732 04:45:58.582242 LP4Y_EN = 0x0
733 04:45:58.582668 WORK_FSP = 0x0
734 04:45:58.585874 WL = 0x2
735 04:45:58.589573 RL = 0x2
736 04:45:58.590097 BL = 0x2
737 04:45:58.592658 RPST = 0x0
738 04:45:58.593085 RD_PRE = 0x0
739 04:45:58.596304 WR_PRE = 0x1
740 04:45:58.596828 WR_PST = 0x0
741 04:45:58.599709 DBI_WR = 0x0
742 04:45:58.600234 DBI_RD = 0x0
743 04:45:58.602209 OTF = 0x1
744 04:45:58.605956 ===================================
745 04:45:58.609119 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 04:45:58.612670 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 04:45:58.615351 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 04:45:58.618983 ===================================
749 04:45:58.621961 LPDDR4 DRAM CONFIGURATION
750 04:45:58.625264 ===================================
751 04:45:58.629278 EX_ROW_EN[0] = 0x10
752 04:45:58.629810 EX_ROW_EN[1] = 0x0
753 04:45:58.632222 LP4Y_EN = 0x0
754 04:45:58.632650 WORK_FSP = 0x0
755 04:45:58.635576 WL = 0x2
756 04:45:58.636005 RL = 0x2
757 04:45:58.638493 BL = 0x2
758 04:45:58.642171 RPST = 0x0
759 04:45:58.642595 RD_PRE = 0x0
760 04:45:58.645540 WR_PRE = 0x1
761 04:45:58.646062 WR_PST = 0x0
762 04:45:58.648604 DBI_WR = 0x0
763 04:45:58.649034 DBI_RD = 0x0
764 04:45:58.651850 OTF = 0x1
765 04:45:58.655172 ===================================
766 04:45:58.658334 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 04:45:58.664134 nWR fixed to 40
768 04:45:58.667438 [ModeRegInit_LP4] CH0 RK0
769 04:45:58.667869 [ModeRegInit_LP4] CH0 RK1
770 04:45:58.670556 [ModeRegInit_LP4] CH1 RK0
771 04:45:58.674429 [ModeRegInit_LP4] CH1 RK1
772 04:45:58.674951 match AC timing 13
773 04:45:58.680889 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 04:45:58.684068 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 04:45:58.687302 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 04:45:58.694874 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 04:45:58.697210 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 04:45:58.700951 [EMI DOE] emi_dcm 0
779 04:45:58.704019 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 04:45:58.704450 ==
781 04:45:58.707207 Dram Type= 6, Freq= 0, CH_0, rank 0
782 04:45:58.710540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 04:45:58.710972 ==
784 04:45:58.717233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 04:45:58.723993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 04:45:58.731697 [CA 0] Center 38 (7~69) winsize 63
787 04:45:58.735009 [CA 1] Center 37 (7~68) winsize 62
788 04:45:58.737970 [CA 2] Center 35 (5~65) winsize 61
789 04:45:58.741376 [CA 3] Center 34 (4~65) winsize 62
790 04:45:58.745132 [CA 4] Center 33 (3~64) winsize 62
791 04:45:58.748273 [CA 5] Center 33 (3~64) winsize 62
792 04:45:58.748803
793 04:45:58.752209 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 04:45:58.752735
795 04:45:58.754710 [CATrainingPosCal] consider 1 rank data
796 04:45:58.757943 u2DelayCellTimex100 = 270/100 ps
797 04:45:58.761565 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
798 04:45:58.767891 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 04:45:58.771150 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
800 04:45:58.774447 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 04:45:58.778393 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 04:45:58.781406 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 04:45:58.781838
804 04:45:58.784368 CA PerBit enable=1, Macro0, CA PI delay=33
805 04:45:58.784797
806 04:45:58.788277 [CBTSetCACLKResult] CA Dly = 33
807 04:45:58.791256 CS Dly: 5 (0~36)
808 04:45:58.791827 ==
809 04:45:58.795189 Dram Type= 6, Freq= 0, CH_0, rank 1
810 04:45:58.797903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 04:45:58.798338 ==
812 04:45:58.804586 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 04:45:58.807522 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 04:45:58.818140 [CA 0] Center 38 (7~69) winsize 63
815 04:45:58.821309 [CA 1] Center 37 (7~68) winsize 62
816 04:45:58.824404 [CA 2] Center 35 (4~66) winsize 63
817 04:45:58.828135 [CA 3] Center 35 (4~66) winsize 63
818 04:45:58.831121 [CA 4] Center 34 (3~65) winsize 63
819 04:45:58.835054 [CA 5] Center 33 (3~64) winsize 62
820 04:45:58.835542
821 04:45:58.837582 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 04:45:58.838021
823 04:45:58.840951 [CATrainingPosCal] consider 2 rank data
824 04:45:58.844504 u2DelayCellTimex100 = 270/100 ps
825 04:45:58.847561 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
826 04:45:58.854107 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 04:45:58.857758 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
828 04:45:58.860669 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 04:45:58.864353 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 04:45:58.867343 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 04:45:58.867816
832 04:45:58.870636 CA PerBit enable=1, Macro0, CA PI delay=33
833 04:45:58.871066
834 04:45:58.874628 [CBTSetCACLKResult] CA Dly = 33
835 04:45:58.877480 CS Dly: 6 (0~38)
836 04:45:58.877911
837 04:45:58.880799 ----->DramcWriteLeveling(PI) begin...
838 04:45:58.881244 ==
839 04:45:58.885180 Dram Type= 6, Freq= 0, CH_0, rank 0
840 04:45:58.888656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 04:45:58.889113 ==
842 04:45:58.892095 Write leveling (Byte 0): 29 => 29
843 04:45:58.892526 Write leveling (Byte 1): 29 => 29
844 04:45:58.895748 DramcWriteLeveling(PI) end<-----
845 04:45:58.896227
846 04:45:58.896569 ==
847 04:45:58.899285 Dram Type= 6, Freq= 0, CH_0, rank 0
848 04:45:58.902958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 04:45:58.906390 ==
850 04:45:58.906815 [Gating] SW mode calibration
851 04:45:58.913578 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 04:45:58.920421 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 04:45:58.923963 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 04:45:58.926797 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 04:45:58.933408 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 04:45:58.936850 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 04:45:58.939907 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 04:45:58.946757 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 04:45:58.950086 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 04:45:58.953454 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 04:45:58.959936 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 04:45:58.963653 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 04:45:58.966614 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 04:45:58.973282 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 04:45:58.977043 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 04:45:58.980487 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 04:45:58.987742 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 04:45:58.990098 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 04:45:58.993164 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 04:45:59.000064 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
871 04:45:59.003409 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
872 04:45:59.007484 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
873 04:45:59.013266 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 04:45:59.017220 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 04:45:59.020559 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 04:45:59.026489 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 04:45:59.030705 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 04:45:59.033932 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
879 04:45:59.036517 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
880 04:45:59.043275 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
881 04:45:59.046585 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 04:45:59.050105 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 04:45:59.058735 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 04:45:59.059630 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 04:45:59.063254 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 04:45:59.069717 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
887 04:45:59.073276 0 10 8 | B1->B0 | 3333 2424 | 1 0 | (1 0) (0 0)
888 04:45:59.076412 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
889 04:45:59.082988 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 04:45:59.086204 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 04:45:59.089870 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 04:45:59.096454 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 04:45:59.099225 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 04:45:59.102801 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
895 04:45:59.109867 0 11 8 | B1->B0 | 2828 4343 | 0 1 | (0 0) (0 0)
896 04:45:59.112803 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
897 04:45:59.116147 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 04:45:59.122829 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 04:45:59.126091 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 04:45:59.129177 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 04:45:59.135838 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 04:45:59.139208 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
903 04:45:59.143025 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 04:45:59.149976 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 04:45:59.153153 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 04:45:59.156343 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 04:45:59.162544 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 04:45:59.166154 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 04:45:59.169799 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 04:45:59.175953 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 04:45:59.179583 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 04:45:59.182984 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 04:45:59.185781 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 04:45:59.192659 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 04:45:59.195617 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 04:45:59.199504 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 04:45:59.206058 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 04:45:59.209626 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 04:45:59.212614 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 04:45:59.215710 Total UI for P1: 0, mck2ui 16
921 04:45:59.218928 best dqsien dly found for B0: ( 0, 14, 4)
922 04:45:59.225919 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 04:45:59.229002 Total UI for P1: 0, mck2ui 16
924 04:45:59.232284 best dqsien dly found for B1: ( 0, 14, 8)
925 04:45:59.235479 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 04:45:59.238603 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 04:45:59.239205
928 04:45:59.242244 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 04:45:59.245730 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 04:45:59.248673 [Gating] SW calibration Done
931 04:45:59.249099 ==
932 04:45:59.251992 Dram Type= 6, Freq= 0, CH_0, rank 0
933 04:45:59.255960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 04:45:59.256413 ==
935 04:45:59.259117 RX Vref Scan: 0
936 04:45:59.259574
937 04:45:59.259917 RX Vref 0 -> 0, step: 1
938 04:45:59.260235
939 04:45:59.262751 RX Delay -130 -> 252, step: 16
940 04:45:59.266147 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 04:45:59.272674 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 04:45:59.275757 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 04:45:59.279414 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 04:45:59.283145 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 04:45:59.285847 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 04:45:59.292901 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 04:45:59.295773 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 04:45:59.299514 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 04:45:59.302961 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
950 04:45:59.306343 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 04:45:59.312555 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 04:45:59.316322 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
953 04:45:59.318659 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 04:45:59.322173 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 04:45:59.329001 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 04:45:59.329428 ==
957 04:45:59.332066 Dram Type= 6, Freq= 0, CH_0, rank 0
958 04:45:59.335583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 04:45:59.336141 ==
960 04:45:59.336700 DQS Delay:
961 04:45:59.339122 DQS0 = 0, DQS1 = 0
962 04:45:59.339784 DQM Delay:
963 04:45:59.342263 DQM0 = 87, DQM1 = 74
964 04:45:59.342686 DQ Delay:
965 04:45:59.345565 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 04:45:59.349130 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =93
967 04:45:59.352243 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
968 04:45:59.355419 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
969 04:45:59.356145
970 04:45:59.356675
971 04:45:59.357058 ==
972 04:45:59.358992 Dram Type= 6, Freq= 0, CH_0, rank 0
973 04:45:59.362254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 04:45:59.362740 ==
975 04:45:59.363084
976 04:45:59.363441
977 04:45:59.365695 TX Vref Scan disable
978 04:45:59.368953 == TX Byte 0 ==
979 04:45:59.372303 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 04:45:59.375487 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 04:45:59.379191 == TX Byte 1 ==
982 04:45:59.382256 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
983 04:45:59.385294 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
984 04:45:59.385720 ==
985 04:45:59.388759 Dram Type= 6, Freq= 0, CH_0, rank 0
986 04:45:59.392162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 04:45:59.395745 ==
988 04:45:59.406749 TX Vref=22, minBit 0, minWin=27, winSum=442
989 04:45:59.410505 TX Vref=24, minBit 0, minWin=27, winSum=442
990 04:45:59.413122 TX Vref=26, minBit 1, minWin=27, winSum=446
991 04:45:59.417060 TX Vref=28, minBit 1, minWin=27, winSum=451
992 04:45:59.419933 TX Vref=30, minBit 1, minWin=27, winSum=450
993 04:45:59.426577 TX Vref=32, minBit 1, minWin=27, winSum=448
994 04:45:59.430072 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 28
995 04:45:59.430727
996 04:45:59.433553 Final TX Range 1 Vref 28
997 04:45:59.433980
998 04:45:59.434316 ==
999 04:45:59.436594 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 04:45:59.439904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 04:45:59.440371 ==
1002 04:45:59.442949
1003 04:45:59.443414
1004 04:45:59.443795 TX Vref Scan disable
1005 04:45:59.446802 == TX Byte 0 ==
1006 04:45:59.450248 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1007 04:45:59.456329 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1008 04:45:59.456887 == TX Byte 1 ==
1009 04:45:59.460317 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1010 04:45:59.466480 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1011 04:45:59.467050
1012 04:45:59.467473 [DATLAT]
1013 04:45:59.467830 Freq=800, CH0 RK0
1014 04:45:59.468226
1015 04:45:59.470015 DATLAT Default: 0xa
1016 04:45:59.470496 0, 0xFFFF, sum = 0
1017 04:45:59.473333 1, 0xFFFF, sum = 0
1018 04:45:59.473759 2, 0xFFFF, sum = 0
1019 04:45:59.476021 3, 0xFFFF, sum = 0
1020 04:45:59.479584 4, 0xFFFF, sum = 0
1021 04:45:59.480108 5, 0xFFFF, sum = 0
1022 04:45:59.483198 6, 0xFFFF, sum = 0
1023 04:45:59.483784 7, 0xFFFF, sum = 0
1024 04:45:59.486685 8, 0xFFFF, sum = 0
1025 04:45:59.487223 9, 0x0, sum = 1
1026 04:45:59.489749 10, 0x0, sum = 2
1027 04:45:59.490270 11, 0x0, sum = 3
1028 04:45:59.490610 12, 0x0, sum = 4
1029 04:45:59.493350 best_step = 10
1030 04:45:59.493864
1031 04:45:59.494197 ==
1032 04:45:59.496459 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 04:45:59.499561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 04:45:59.500075 ==
1035 04:45:59.503110 RX Vref Scan: 1
1036 04:45:59.503717
1037 04:45:59.506730 Set Vref Range= 32 -> 127
1038 04:45:59.507243
1039 04:45:59.507637 RX Vref 32 -> 127, step: 1
1040 04:45:59.507949
1041 04:45:59.509751 RX Delay -111 -> 252, step: 8
1042 04:45:59.510269
1043 04:45:59.513022 Set Vref, RX VrefLevel [Byte0]: 32
1044 04:45:59.516175 [Byte1]: 32
1045 04:45:59.519710
1046 04:45:59.520225 Set Vref, RX VrefLevel [Byte0]: 33
1047 04:45:59.522927 [Byte1]: 33
1048 04:45:59.527507
1049 04:45:59.528021 Set Vref, RX VrefLevel [Byte0]: 34
1050 04:45:59.530631 [Byte1]: 34
1051 04:45:59.534617
1052 04:45:59.535146 Set Vref, RX VrefLevel [Byte0]: 35
1053 04:45:59.537820 [Byte1]: 35
1054 04:45:59.542492
1055 04:45:59.542922 Set Vref, RX VrefLevel [Byte0]: 36
1056 04:45:59.545845 [Byte1]: 36
1057 04:45:59.549969
1058 04:45:59.550487 Set Vref, RX VrefLevel [Byte0]: 37
1059 04:45:59.553589 [Byte1]: 37
1060 04:45:59.557759
1061 04:45:59.558183 Set Vref, RX VrefLevel [Byte0]: 38
1062 04:45:59.561633 [Byte1]: 38
1063 04:45:59.565646
1064 04:45:59.566254 Set Vref, RX VrefLevel [Byte0]: 39
1065 04:45:59.568794 [Byte1]: 39
1066 04:45:59.573014
1067 04:45:59.573483 Set Vref, RX VrefLevel [Byte0]: 40
1068 04:45:59.576833 [Byte1]: 40
1069 04:45:59.580860
1070 04:45:59.581274 Set Vref, RX VrefLevel [Byte0]: 41
1071 04:45:59.583911 [Byte1]: 41
1072 04:45:59.588277
1073 04:45:59.588692 Set Vref, RX VrefLevel [Byte0]: 42
1074 04:45:59.591118 [Byte1]: 42
1075 04:45:59.596306
1076 04:45:59.596848 Set Vref, RX VrefLevel [Byte0]: 43
1077 04:45:59.599529 [Byte1]: 43
1078 04:45:59.603901
1079 04:45:59.604429 Set Vref, RX VrefLevel [Byte0]: 44
1080 04:45:59.607035 [Byte1]: 44
1081 04:45:59.610890
1082 04:45:59.611318 Set Vref, RX VrefLevel [Byte0]: 45
1083 04:45:59.614187 [Byte1]: 45
1084 04:45:59.618797
1085 04:45:59.619328 Set Vref, RX VrefLevel [Byte0]: 46
1086 04:45:59.622351 [Byte1]: 46
1087 04:45:59.626751
1088 04:45:59.627284 Set Vref, RX VrefLevel [Byte0]: 47
1089 04:45:59.630148 [Byte1]: 47
1090 04:45:59.633847
1091 04:45:59.634293 Set Vref, RX VrefLevel [Byte0]: 48
1092 04:45:59.637257 [Byte1]: 48
1093 04:45:59.641600
1094 04:45:59.642025 Set Vref, RX VrefLevel [Byte0]: 49
1095 04:45:59.644684 [Byte1]: 49
1096 04:45:59.649158
1097 04:45:59.649583 Set Vref, RX VrefLevel [Byte0]: 50
1098 04:45:59.652781 [Byte1]: 50
1099 04:45:59.657109
1100 04:45:59.657537 Set Vref, RX VrefLevel [Byte0]: 51
1101 04:45:59.660433 [Byte1]: 51
1102 04:45:59.664581
1103 04:45:59.665112 Set Vref, RX VrefLevel [Byte0]: 52
1104 04:45:59.668427 [Byte1]: 52
1105 04:45:59.672758
1106 04:45:59.673287 Set Vref, RX VrefLevel [Byte0]: 53
1107 04:45:59.675682 [Byte1]: 53
1108 04:45:59.680007
1109 04:45:59.680545 Set Vref, RX VrefLevel [Byte0]: 54
1110 04:45:59.683187 [Byte1]: 54
1111 04:45:59.687977
1112 04:45:59.688747 Set Vref, RX VrefLevel [Byte0]: 55
1113 04:45:59.691212 [Byte1]: 55
1114 04:45:59.695332
1115 04:45:59.695939 Set Vref, RX VrefLevel [Byte0]: 56
1116 04:45:59.698726 [Byte1]: 56
1117 04:45:59.702862
1118 04:45:59.703411 Set Vref, RX VrefLevel [Byte0]: 57
1119 04:45:59.706222 [Byte1]: 57
1120 04:45:59.710413
1121 04:45:59.710931 Set Vref, RX VrefLevel [Byte0]: 58
1122 04:45:59.713887 [Byte1]: 58
1123 04:45:59.718269
1124 04:45:59.718786 Set Vref, RX VrefLevel [Byte0]: 59
1125 04:45:59.721632 [Byte1]: 59
1126 04:45:59.725844
1127 04:45:59.726361 Set Vref, RX VrefLevel [Byte0]: 60
1128 04:45:59.729418 [Byte1]: 60
1129 04:45:59.733662
1130 04:45:59.734075 Set Vref, RX VrefLevel [Byte0]: 61
1131 04:45:59.737149 [Byte1]: 61
1132 04:45:59.740827
1133 04:45:59.741243 Set Vref, RX VrefLevel [Byte0]: 62
1134 04:45:59.744168 [Byte1]: 62
1135 04:45:59.749350
1136 04:45:59.749867 Set Vref, RX VrefLevel [Byte0]: 63
1137 04:45:59.752035 [Byte1]: 63
1138 04:45:59.756485
1139 04:45:59.757090 Set Vref, RX VrefLevel [Byte0]: 64
1140 04:45:59.759758 [Byte1]: 64
1141 04:45:59.764176
1142 04:45:59.764699 Set Vref, RX VrefLevel [Byte0]: 65
1143 04:45:59.767459 [Byte1]: 65
1144 04:45:59.772028
1145 04:45:59.772588 Set Vref, RX VrefLevel [Byte0]: 66
1146 04:45:59.775201 [Byte1]: 66
1147 04:45:59.779395
1148 04:45:59.779941 Set Vref, RX VrefLevel [Byte0]: 67
1149 04:45:59.782601 [Byte1]: 67
1150 04:45:59.787155
1151 04:45:59.787629 Set Vref, RX VrefLevel [Byte0]: 68
1152 04:45:59.790590 [Byte1]: 68
1153 04:45:59.794342
1154 04:45:59.794804 Set Vref, RX VrefLevel [Byte0]: 69
1155 04:45:59.798233 [Byte1]: 69
1156 04:45:59.802378
1157 04:45:59.802890 Set Vref, RX VrefLevel [Byte0]: 70
1158 04:45:59.806429 [Byte1]: 70
1159 04:45:59.809720
1160 04:45:59.810245 Set Vref, RX VrefLevel [Byte0]: 71
1161 04:45:59.813222 [Byte1]: 71
1162 04:45:59.817722
1163 04:45:59.818137 Final RX Vref Byte 0 = 57 to rank0
1164 04:45:59.821374 Final RX Vref Byte 1 = 59 to rank0
1165 04:45:59.824048 Final RX Vref Byte 0 = 57 to rank1
1166 04:45:59.827229 Final RX Vref Byte 1 = 59 to rank1==
1167 04:45:59.830564 Dram Type= 6, Freq= 0, CH_0, rank 0
1168 04:45:59.837458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1169 04:45:59.837873 ==
1170 04:45:59.838203 DQS Delay:
1171 04:45:59.838513 DQS0 = 0, DQS1 = 0
1172 04:45:59.841030 DQM Delay:
1173 04:45:59.841448 DQM0 = 88, DQM1 = 76
1174 04:45:59.843825 DQ Delay:
1175 04:45:59.847247 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1176 04:45:59.850883 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1177 04:45:59.854160 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1178 04:45:59.857404 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1179 04:45:59.857922
1180 04:45:59.858252
1181 04:45:59.864013 [DQSOSCAuto] RK0, (LSB)MR18= 0x342d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
1182 04:45:59.867602 CH0 RK0: MR19=606, MR18=342D
1183 04:45:59.873901 CH0_RK0: MR19=0x606, MR18=0x342D, DQSOSC=396, MR23=63, INC=94, DEC=62
1184 04:45:59.874428
1185 04:45:59.876968 ----->DramcWriteLeveling(PI) begin...
1186 04:45:59.877387 ==
1187 04:45:59.880324 Dram Type= 6, Freq= 0, CH_0, rank 1
1188 04:45:59.883890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 04:45:59.884385 ==
1190 04:45:59.887838 Write leveling (Byte 0): 31 => 31
1191 04:45:59.890963 Write leveling (Byte 1): 25 => 25
1192 04:45:59.893879 DramcWriteLeveling(PI) end<-----
1193 04:45:59.894293
1194 04:45:59.894618 ==
1195 04:45:59.897174 Dram Type= 6, Freq= 0, CH_0, rank 1
1196 04:45:59.900098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1197 04:45:59.900512 ==
1198 04:45:59.903408 [Gating] SW mode calibration
1199 04:45:59.910721 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1200 04:45:59.917001 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1201 04:45:59.920750 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1202 04:45:59.923588 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1203 04:45:59.930527 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1204 04:45:59.933557 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 04:45:59.937407 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 04:45:59.943828 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 04:45:59.988111 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 04:45:59.988674 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 04:45:59.989043 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 04:45:59.989746 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 04:45:59.990104 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 04:45:59.990431 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 04:45:59.990750 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 04:45:59.991062 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 04:45:59.991399 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 04:45:59.991714 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 04:46:00.031940 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 04:46:00.032497 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1219 04:46:00.032952 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1220 04:46:00.033827 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 04:46:00.034234 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 04:46:00.034685 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 04:46:00.035207 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 04:46:00.035732 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 04:46:00.036136 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 04:46:00.036546 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 04:46:00.059964 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
1228 04:46:00.060841 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1229 04:46:00.061227 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1230 04:46:00.061647 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1231 04:46:00.062130 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1232 04:46:00.062584 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 04:46:00.064498 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 04:46:00.064931 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
1235 04:46:00.071359 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
1236 04:46:00.074630 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1237 04:46:00.077893 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 04:46:00.084379 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 04:46:00.087886 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 04:46:00.091470 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 04:46:00.098402 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 04:46:00.101176 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1243 04:46:00.104813 0 11 8 | B1->B0 | 3131 4646 | 0 0 | (1 1) (0 0)
1244 04:46:00.111137 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 04:46:00.115004 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1246 04:46:00.117722 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1247 04:46:00.124394 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 04:46:00.128121 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 04:46:00.131312 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 04:46:00.134329 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1251 04:46:00.141619 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1252 04:46:00.145600 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 04:46:00.148478 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 04:46:00.152114 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 04:46:00.159283 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 04:46:00.163149 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 04:46:00.166510 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 04:46:00.173062 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 04:46:00.176183 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 04:46:00.179719 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 04:46:00.185967 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 04:46:00.189485 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 04:46:00.193318 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 04:46:00.196290 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 04:46:00.203242 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 04:46:00.206308 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1267 04:46:00.212761 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1268 04:46:00.213341 Total UI for P1: 0, mck2ui 16
1269 04:46:00.215718 best dqsien dly found for B0: ( 0, 14, 4)
1270 04:46:00.222773 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 04:46:00.226250 Total UI for P1: 0, mck2ui 16
1272 04:46:00.229035 best dqsien dly found for B1: ( 0, 14, 8)
1273 04:46:00.232453 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1274 04:46:00.235861 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1275 04:46:00.236434
1276 04:46:00.239248 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1277 04:46:00.242747 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1278 04:46:00.246127 [Gating] SW calibration Done
1279 04:46:00.246603 ==
1280 04:46:00.249226 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 04:46:00.252318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 04:46:00.252800 ==
1283 04:46:00.255780 RX Vref Scan: 0
1284 04:46:00.256256
1285 04:46:00.256717 RX Vref 0 -> 0, step: 1
1286 04:46:00.258830
1287 04:46:00.259255 RX Delay -130 -> 252, step: 16
1288 04:46:00.266012 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1289 04:46:00.268929 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1290 04:46:00.272710 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1291 04:46:00.275991 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1292 04:46:00.279002 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1293 04:46:00.285927 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1294 04:46:00.289038 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1295 04:46:00.292284 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1296 04:46:00.295665 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1297 04:46:00.299284 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1298 04:46:00.305418 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1299 04:46:00.308922 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1300 04:46:00.312084 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1301 04:46:00.315526 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1302 04:46:00.318923 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1303 04:46:00.325812 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1304 04:46:00.326372 ==
1305 04:46:00.328935 Dram Type= 6, Freq= 0, CH_0, rank 1
1306 04:46:00.332124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1307 04:46:00.332606 ==
1308 04:46:00.333100 DQS Delay:
1309 04:46:00.335456 DQS0 = 0, DQS1 = 0
1310 04:46:00.336035 DQM Delay:
1311 04:46:00.338980 DQM0 = 86, DQM1 = 76
1312 04:46:00.339563 DQ Delay:
1313 04:46:00.341747 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1314 04:46:00.345075 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1315 04:46:00.348234 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
1316 04:46:00.351721 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1317 04:46:00.352149
1318 04:46:00.352579
1319 04:46:00.352986 ==
1320 04:46:00.354933 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 04:46:00.358954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 04:46:00.362128 ==
1323 04:46:00.362652
1324 04:46:00.363155
1325 04:46:00.363666 TX Vref Scan disable
1326 04:46:00.365602 == TX Byte 0 ==
1327 04:46:00.368457 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1328 04:46:00.371465 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1329 04:46:00.375257 == TX Byte 1 ==
1330 04:46:00.378502 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1331 04:46:00.381655 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1332 04:46:00.384819 ==
1333 04:46:00.388212 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 04:46:00.391755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 04:46:00.392176 ==
1336 04:46:00.404426 TX Vref=22, minBit 0, minWin=27, winSum=443
1337 04:46:00.407439 TX Vref=24, minBit 1, minWin=27, winSum=448
1338 04:46:00.411105 TX Vref=26, minBit 1, minWin=27, winSum=447
1339 04:46:00.414405 TX Vref=28, minBit 2, minWin=27, winSum=450
1340 04:46:00.417863 TX Vref=30, minBit 1, minWin=27, winSum=450
1341 04:46:00.421143 TX Vref=32, minBit 1, minWin=27, winSum=450
1342 04:46:00.427497 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 28
1343 04:46:00.427995
1344 04:46:00.430865 Final TX Range 1 Vref 28
1345 04:46:00.431280
1346 04:46:00.431680 ==
1347 04:46:00.433972 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 04:46:00.437704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 04:46:00.438381 ==
1350 04:46:00.440957
1351 04:46:00.441369
1352 04:46:00.441696 TX Vref Scan disable
1353 04:46:00.444069 == TX Byte 0 ==
1354 04:46:00.447809 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1355 04:46:00.454084 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1356 04:46:00.454711 == TX Byte 1 ==
1357 04:46:00.457536 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1358 04:46:00.464556 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1359 04:46:00.465063
1360 04:46:00.465396 [DATLAT]
1361 04:46:00.465700 Freq=800, CH0 RK1
1362 04:46:00.465994
1363 04:46:00.467355 DATLAT Default: 0xa
1364 04:46:00.467819 0, 0xFFFF, sum = 0
1365 04:46:00.471041 1, 0xFFFF, sum = 0
1366 04:46:00.474005 2, 0xFFFF, sum = 0
1367 04:46:00.474596 3, 0xFFFF, sum = 0
1368 04:46:00.477523 4, 0xFFFF, sum = 0
1369 04:46:00.477970 5, 0xFFFF, sum = 0
1370 04:46:00.480720 6, 0xFFFF, sum = 0
1371 04:46:00.481149 7, 0xFFFF, sum = 0
1372 04:46:00.484211 8, 0xFFFF, sum = 0
1373 04:46:00.484637 9, 0x0, sum = 1
1374 04:46:00.487514 10, 0x0, sum = 2
1375 04:46:00.487941 11, 0x0, sum = 3
1376 04:46:00.488277 12, 0x0, sum = 4
1377 04:46:00.490420 best_step = 10
1378 04:46:00.490838
1379 04:46:00.491168 ==
1380 04:46:00.493823 Dram Type= 6, Freq= 0, CH_0, rank 1
1381 04:46:00.497759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 04:46:00.498202 ==
1383 04:46:00.500465 RX Vref Scan: 0
1384 04:46:00.500882
1385 04:46:00.501210 RX Vref 0 -> 0, step: 1
1386 04:46:00.504195
1387 04:46:00.504613 RX Delay -111 -> 252, step: 8
1388 04:46:00.510882 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1389 04:46:00.514907 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1390 04:46:00.517883 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1391 04:46:00.520949 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1392 04:46:00.524063 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1393 04:46:00.530872 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1394 04:46:00.534185 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1395 04:46:00.537351 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1396 04:46:00.540805 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1397 04:46:00.544467 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1398 04:46:00.550698 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1399 04:46:00.554106 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1400 04:46:00.557381 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1401 04:46:00.560916 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1402 04:46:00.568137 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1403 04:46:00.570773 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1404 04:46:00.571190 ==
1405 04:46:00.574243 Dram Type= 6, Freq= 0, CH_0, rank 1
1406 04:46:00.577388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 04:46:00.578105 ==
1408 04:46:00.580958 DQS Delay:
1409 04:46:00.581690 DQS0 = 0, DQS1 = 0
1410 04:46:00.582141 DQM Delay:
1411 04:46:00.584108 DQM0 = 86, DQM1 = 76
1412 04:46:00.584553 DQ Delay:
1413 04:46:00.587810 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1414 04:46:00.591044 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1415 04:46:00.593973 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1416 04:46:00.597034 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1417 04:46:00.597576
1418 04:46:00.598040
1419 04:46:00.607693 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1420 04:46:00.608117 CH0 RK1: MR19=606, MR18=2A27
1421 04:46:00.614770 CH0_RK1: MR19=0x606, MR18=0x2A27, DQSOSC=399, MR23=63, INC=92, DEC=61
1422 04:46:00.617456 [RxdqsGatingPostProcess] freq 800
1423 04:46:00.623948 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1424 04:46:00.626989 Pre-setting of DQS Precalculation
1425 04:46:00.630498 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1426 04:46:00.630912 ==
1427 04:46:00.634053 Dram Type= 6, Freq= 0, CH_1, rank 0
1428 04:46:00.640535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 04:46:00.640951 ==
1430 04:46:00.643946 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1431 04:46:00.650468 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1432 04:46:00.659217 [CA 0] Center 37 (6~68) winsize 63
1433 04:46:00.663254 [CA 1] Center 37 (6~68) winsize 63
1434 04:46:00.666210 [CA 2] Center 35 (5~66) winsize 62
1435 04:46:00.669335 [CA 3] Center 34 (4~65) winsize 62
1436 04:46:00.673172 [CA 4] Center 35 (5~66) winsize 62
1437 04:46:00.675512 [CA 5] Center 34 (4~65) winsize 62
1438 04:46:00.675928
1439 04:46:00.679111 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1440 04:46:00.679644
1441 04:46:00.682833 [CATrainingPosCal] consider 1 rank data
1442 04:46:00.685908 u2DelayCellTimex100 = 270/100 ps
1443 04:46:00.689272 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1444 04:46:00.695849 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1445 04:46:00.699049 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1446 04:46:00.702404 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1447 04:46:00.705525 CA4 delay=35 (5~66),Diff = 1 PI (7 cell)
1448 04:46:00.708977 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1449 04:46:00.709391
1450 04:46:00.712131 CA PerBit enable=1, Macro0, CA PI delay=34
1451 04:46:00.712547
1452 04:46:00.715889 [CBTSetCACLKResult] CA Dly = 34
1453 04:46:00.718985 CS Dly: 4 (0~35)
1454 04:46:00.719637 ==
1455 04:46:00.722342 Dram Type= 6, Freq= 0, CH_1, rank 1
1456 04:46:00.726025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 04:46:00.726546 ==
1458 04:46:00.732046 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1459 04:46:00.735500 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1460 04:46:00.745280 [CA 0] Center 36 (6~67) winsize 62
1461 04:46:00.749004 [CA 1] Center 37 (6~68) winsize 63
1462 04:46:00.752080 [CA 2] Center 35 (4~66) winsize 63
1463 04:46:00.755474 [CA 3] Center 34 (4~65) winsize 62
1464 04:46:00.758742 [CA 4] Center 34 (4~65) winsize 62
1465 04:46:00.762156 [CA 5] Center 34 (4~65) winsize 62
1466 04:46:00.762665
1467 04:46:00.765717 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1468 04:46:00.766133
1469 04:46:00.768817 [CATrainingPosCal] consider 2 rank data
1470 04:46:00.772050 u2DelayCellTimex100 = 270/100 ps
1471 04:46:00.775840 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1472 04:46:00.778999 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1473 04:46:00.785575 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1474 04:46:00.788880 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1475 04:46:00.792118 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1476 04:46:00.795858 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1477 04:46:00.796320
1478 04:46:00.799559 CA PerBit enable=1, Macro0, CA PI delay=34
1479 04:46:00.800039
1480 04:46:00.803448 [CBTSetCACLKResult] CA Dly = 34
1481 04:46:00.803964 CS Dly: 5 (0~37)
1482 04:46:00.804400
1483 04:46:00.806737 ----->DramcWriteLeveling(PI) begin...
1484 04:46:00.807249 ==
1485 04:46:00.811113 Dram Type= 6, Freq= 0, CH_1, rank 0
1486 04:46:00.814006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1487 04:46:00.814437 ==
1488 04:46:00.817758 Write leveling (Byte 0): 28 => 28
1489 04:46:00.821755 Write leveling (Byte 1): 29 => 29
1490 04:46:00.825081 DramcWriteLeveling(PI) end<-----
1491 04:46:00.825511
1492 04:46:00.825943 ==
1493 04:46:00.828734 Dram Type= 6, Freq= 0, CH_1, rank 0
1494 04:46:00.832009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1495 04:46:00.832443 ==
1496 04:46:00.835943 [Gating] SW mode calibration
1497 04:46:00.842261 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1498 04:46:00.845410 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1499 04:46:00.851948 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1500 04:46:00.855786 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1501 04:46:00.859205 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 04:46:00.865421 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 04:46:00.868821 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 04:46:00.872150 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 04:46:00.878649 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 04:46:00.882399 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 04:46:00.885477 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 04:46:00.891958 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 04:46:00.895491 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 04:46:00.898588 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 04:46:00.905377 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 04:46:00.908321 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 04:46:00.911531 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 04:46:00.918549 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 04:46:00.921990 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1516 04:46:00.925480 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1517 04:46:00.931745 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 04:46:00.935201 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 04:46:00.938585 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 04:46:00.945503 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 04:46:00.948123 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 04:46:00.951960 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 04:46:00.958710 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 04:46:00.961717 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1525 04:46:00.964780 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1526 04:46:00.971812 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1527 04:46:00.975215 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1528 04:46:00.978535 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1529 04:46:00.985188 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1530 04:46:00.987993 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 04:46:00.991405 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 04:46:00.998060 0 10 4 | B1->B0 | 3434 3131 | 0 0 | (0 1) (0 1)
1533 04:46:01.001577 0 10 8 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
1534 04:46:01.005023 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 04:46:01.008304 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 04:46:01.014723 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 04:46:01.017797 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 04:46:01.021564 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 04:46:01.027991 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 04:46:01.031134 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
1541 04:46:01.034582 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1542 04:46:01.040954 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 04:46:01.044547 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1544 04:46:01.047926 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 04:46:01.054452 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 04:46:01.058134 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 04:46:01.061192 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 04:46:01.067612 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1549 04:46:01.070915 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1550 04:46:01.074303 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 04:46:01.081050 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 04:46:01.083853 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 04:46:01.087793 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 04:46:01.094208 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 04:46:01.097662 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 04:46:01.100929 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 04:46:01.107190 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 04:46:01.110864 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 04:46:01.113936 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 04:46:01.120560 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 04:46:01.123685 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 04:46:01.127745 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 04:46:01.133623 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 04:46:01.136945 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 04:46:01.139900 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 04:46:01.144097 Total UI for P1: 0, mck2ui 16
1567 04:46:01.146259 best dqsien dly found for B0: ( 0, 14, 6)
1568 04:46:01.150129 Total UI for P1: 0, mck2ui 16
1569 04:46:01.153523 best dqsien dly found for B1: ( 0, 14, 6)
1570 04:46:01.156481 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1571 04:46:01.159876 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1572 04:46:01.160298
1573 04:46:01.166783 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1574 04:46:01.170138 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1575 04:46:01.173166 [Gating] SW calibration Done
1576 04:46:01.173684 ==
1577 04:46:01.176330 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 04:46:01.179825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 04:46:01.180371 ==
1580 04:46:01.180873 RX Vref Scan: 0
1581 04:46:01.181209
1582 04:46:01.183066 RX Vref 0 -> 0, step: 1
1583 04:46:01.183527
1584 04:46:01.186646 RX Delay -130 -> 252, step: 16
1585 04:46:01.190121 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1586 04:46:01.193129 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1587 04:46:01.199503 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1588 04:46:01.203705 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1589 04:46:01.206832 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1590 04:46:01.209631 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1591 04:46:01.212959 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1592 04:46:01.220269 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1593 04:46:01.222913 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1594 04:46:01.226203 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1595 04:46:01.229406 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1596 04:46:01.233086 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1597 04:46:01.239715 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1598 04:46:01.243083 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1599 04:46:01.246705 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1600 04:46:01.249302 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1601 04:46:01.249910 ==
1602 04:46:01.253116 Dram Type= 6, Freq= 0, CH_1, rank 0
1603 04:46:01.259728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1604 04:46:01.260264 ==
1605 04:46:01.260603 DQS Delay:
1606 04:46:01.262929 DQS0 = 0, DQS1 = 0
1607 04:46:01.263350 DQM Delay:
1608 04:46:01.263749 DQM0 = 88, DQM1 = 79
1609 04:46:01.266145 DQ Delay:
1610 04:46:01.269524 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1611 04:46:01.273002 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1612 04:46:01.276066 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1613 04:46:01.279195 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1614 04:46:01.279653
1615 04:46:01.279989
1616 04:46:01.280300 ==
1617 04:46:01.282425 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 04:46:01.286045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 04:46:01.286472 ==
1620 04:46:01.286804
1621 04:46:01.287109
1622 04:46:01.288966 TX Vref Scan disable
1623 04:46:01.292243 == TX Byte 0 ==
1624 04:46:01.295449 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1625 04:46:01.299314 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1626 04:46:01.302322 == TX Byte 1 ==
1627 04:46:01.306136 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1628 04:46:01.309041 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1629 04:46:01.309559 ==
1630 04:46:01.312838 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 04:46:01.315815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 04:46:01.319096 ==
1633 04:46:01.330305 TX Vref=22, minBit 4, minWin=26, winSum=439
1634 04:46:01.333758 TX Vref=24, minBit 0, minWin=27, winSum=445
1635 04:46:01.337157 TX Vref=26, minBit 1, minWin=27, winSum=449
1636 04:46:01.339904 TX Vref=28, minBit 1, minWin=27, winSum=451
1637 04:46:01.343228 TX Vref=30, minBit 1, minWin=27, winSum=450
1638 04:46:01.349674 TX Vref=32, minBit 1, minWin=27, winSum=451
1639 04:46:01.353293 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 28
1640 04:46:01.353762
1641 04:46:01.357163 Final TX Range 1 Vref 28
1642 04:46:01.357716
1643 04:46:01.358084 ==
1644 04:46:01.359987 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 04:46:01.363630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 04:46:01.364144 ==
1647 04:46:01.366641
1648 04:46:01.367150
1649 04:46:01.367555 TX Vref Scan disable
1650 04:46:01.370434 == TX Byte 0 ==
1651 04:46:01.373617 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1652 04:46:01.377848 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1653 04:46:01.381097 == TX Byte 1 ==
1654 04:46:01.384429 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1655 04:46:01.387615 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1656 04:46:01.388126
1657 04:46:01.391472 [DATLAT]
1658 04:46:01.391989 Freq=800, CH1 RK0
1659 04:46:01.392330
1660 04:46:01.394724 DATLAT Default: 0xa
1661 04:46:01.395242 0, 0xFFFF, sum = 0
1662 04:46:01.397639 1, 0xFFFF, sum = 0
1663 04:46:01.398156 2, 0xFFFF, sum = 0
1664 04:46:01.400839 3, 0xFFFF, sum = 0
1665 04:46:01.401266 4, 0xFFFF, sum = 0
1666 04:46:01.404171 5, 0xFFFF, sum = 0
1667 04:46:01.404598 6, 0xFFFF, sum = 0
1668 04:46:01.407420 7, 0xFFFF, sum = 0
1669 04:46:01.407888 8, 0xFFFF, sum = 0
1670 04:46:01.410928 9, 0x0, sum = 1
1671 04:46:01.411498 10, 0x0, sum = 2
1672 04:46:01.414714 11, 0x0, sum = 3
1673 04:46:01.415231 12, 0x0, sum = 4
1674 04:46:01.417222 best_step = 10
1675 04:46:01.417641
1676 04:46:01.417972 ==
1677 04:46:01.420940 Dram Type= 6, Freq= 0, CH_1, rank 0
1678 04:46:01.424007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1679 04:46:01.424431 ==
1680 04:46:01.424764 RX Vref Scan: 1
1681 04:46:01.427655
1682 04:46:01.428170 Set Vref Range= 32 -> 127
1683 04:46:01.428505
1684 04:46:01.430639 RX Vref 32 -> 127, step: 1
1685 04:46:01.431061
1686 04:46:01.433871 RX Delay -95 -> 252, step: 8
1687 04:46:01.434291
1688 04:46:01.437051 Set Vref, RX VrefLevel [Byte0]: 32
1689 04:46:01.440540 [Byte1]: 32
1690 04:46:01.440961
1691 04:46:01.444784 Set Vref, RX VrefLevel [Byte0]: 33
1692 04:46:01.447223 [Byte1]: 33
1693 04:46:01.450139
1694 04:46:01.450653 Set Vref, RX VrefLevel [Byte0]: 34
1695 04:46:01.453495 [Byte1]: 34
1696 04:46:01.458062
1697 04:46:01.458592 Set Vref, RX VrefLevel [Byte0]: 35
1698 04:46:01.461202 [Byte1]: 35
1699 04:46:01.465255
1700 04:46:01.465678 Set Vref, RX VrefLevel [Byte0]: 36
1701 04:46:01.469157 [Byte1]: 36
1702 04:46:01.473144
1703 04:46:01.473562 Set Vref, RX VrefLevel [Byte0]: 37
1704 04:46:01.476670 [Byte1]: 37
1705 04:46:01.481092
1706 04:46:01.481511 Set Vref, RX VrefLevel [Byte0]: 38
1707 04:46:01.483900 [Byte1]: 38
1708 04:46:01.488033
1709 04:46:01.488452 Set Vref, RX VrefLevel [Byte0]: 39
1710 04:46:01.492128 [Byte1]: 39
1711 04:46:01.496366
1712 04:46:01.496787 Set Vref, RX VrefLevel [Byte0]: 40
1713 04:46:01.499416 [Byte1]: 40
1714 04:46:01.504026
1715 04:46:01.504602 Set Vref, RX VrefLevel [Byte0]: 41
1716 04:46:01.506949 [Byte1]: 41
1717 04:46:01.511282
1718 04:46:01.511729 Set Vref, RX VrefLevel [Byte0]: 42
1719 04:46:01.514323 [Byte1]: 42
1720 04:46:01.518407
1721 04:46:01.518822 Set Vref, RX VrefLevel [Byte0]: 43
1722 04:46:01.522202 [Byte1]: 43
1723 04:46:01.526030
1724 04:46:01.526502 Set Vref, RX VrefLevel [Byte0]: 44
1725 04:46:01.530086 [Byte1]: 44
1726 04:46:01.534381
1727 04:46:01.534800 Set Vref, RX VrefLevel [Byte0]: 45
1728 04:46:01.537266 [Byte1]: 45
1729 04:46:01.541532
1730 04:46:01.541973 Set Vref, RX VrefLevel [Byte0]: 46
1731 04:46:01.544564 [Byte1]: 46
1732 04:46:01.548789
1733 04:46:01.549198 Set Vref, RX VrefLevel [Byte0]: 47
1734 04:46:01.552497 [Byte1]: 47
1735 04:46:01.556684
1736 04:46:01.557200 Set Vref, RX VrefLevel [Byte0]: 48
1737 04:46:01.560029 [Byte1]: 48
1738 04:46:01.563933
1739 04:46:01.564347 Set Vref, RX VrefLevel [Byte0]: 49
1740 04:46:01.567481 [Byte1]: 49
1741 04:46:01.571528
1742 04:46:01.571985 Set Vref, RX VrefLevel [Byte0]: 50
1743 04:46:01.575252 [Byte1]: 50
1744 04:46:01.579358
1745 04:46:01.579946 Set Vref, RX VrefLevel [Byte0]: 51
1746 04:46:01.582765 [Byte1]: 51
1747 04:46:01.587166
1748 04:46:01.587741 Set Vref, RX VrefLevel [Byte0]: 52
1749 04:46:01.590912 [Byte1]: 52
1750 04:46:01.594975
1751 04:46:01.595529 Set Vref, RX VrefLevel [Byte0]: 53
1752 04:46:01.598811 [Byte1]: 53
1753 04:46:01.602299
1754 04:46:01.602811 Set Vref, RX VrefLevel [Byte0]: 54
1755 04:46:01.606358 [Byte1]: 54
1756 04:46:01.609921
1757 04:46:01.610433 Set Vref, RX VrefLevel [Byte0]: 55
1758 04:46:01.613254 [Byte1]: 55
1759 04:46:01.617900
1760 04:46:01.618418 Set Vref, RX VrefLevel [Byte0]: 56
1761 04:46:01.621193 [Byte1]: 56
1762 04:46:01.625410
1763 04:46:01.625923 Set Vref, RX VrefLevel [Byte0]: 57
1764 04:46:01.628696 [Byte1]: 57
1765 04:46:01.632482
1766 04:46:01.632991 Set Vref, RX VrefLevel [Byte0]: 58
1767 04:46:01.635932 [Byte1]: 58
1768 04:46:01.640031
1769 04:46:01.640457 Set Vref, RX VrefLevel [Byte0]: 59
1770 04:46:01.643447 [Byte1]: 59
1771 04:46:01.647898
1772 04:46:01.648427 Set Vref, RX VrefLevel [Byte0]: 60
1773 04:46:01.651005 [Byte1]: 60
1774 04:46:01.655850
1775 04:46:01.656270 Set Vref, RX VrefLevel [Byte0]: 61
1776 04:46:01.658685 [Byte1]: 61
1777 04:46:01.662990
1778 04:46:01.663452 Set Vref, RX VrefLevel [Byte0]: 62
1779 04:46:01.666073 [Byte1]: 62
1780 04:46:01.670782
1781 04:46:01.671296 Set Vref, RX VrefLevel [Byte0]: 63
1782 04:46:01.674273 [Byte1]: 63
1783 04:46:01.678461
1784 04:46:01.678974 Set Vref, RX VrefLevel [Byte0]: 64
1785 04:46:01.681654 [Byte1]: 64
1786 04:46:01.685684
1787 04:46:01.686112 Set Vref, RX VrefLevel [Byte0]: 65
1788 04:46:01.689129 [Byte1]: 65
1789 04:46:01.693550
1790 04:46:01.694067 Set Vref, RX VrefLevel [Byte0]: 66
1791 04:46:01.696687 [Byte1]: 66
1792 04:46:01.701210
1793 04:46:01.701744 Set Vref, RX VrefLevel [Byte0]: 67
1794 04:46:01.704267 [Byte1]: 67
1795 04:46:01.708953
1796 04:46:01.709520 Set Vref, RX VrefLevel [Byte0]: 68
1797 04:46:01.712559 [Byte1]: 68
1798 04:46:01.716383
1799 04:46:01.716805 Set Vref, RX VrefLevel [Byte0]: 69
1800 04:46:01.719740 [Byte1]: 69
1801 04:46:01.723939
1802 04:46:01.724453 Set Vref, RX VrefLevel [Byte0]: 70
1803 04:46:01.727484 [Byte1]: 70
1804 04:46:01.731397
1805 04:46:01.731936 Set Vref, RX VrefLevel [Byte0]: 71
1806 04:46:01.734903 [Byte1]: 71
1807 04:46:01.739140
1808 04:46:01.739604 Set Vref, RX VrefLevel [Byte0]: 72
1809 04:46:01.742357 [Byte1]: 72
1810 04:46:01.746535
1811 04:46:01.747046 Set Vref, RX VrefLevel [Byte0]: 73
1812 04:46:01.750038 [Byte1]: 73
1813 04:46:01.753993
1814 04:46:01.754416 Set Vref, RX VrefLevel [Byte0]: 74
1815 04:46:01.757350 [Byte1]: 74
1816 04:46:01.761681
1817 04:46:01.762197 Final RX Vref Byte 0 = 59 to rank0
1818 04:46:01.765716 Final RX Vref Byte 1 = 52 to rank0
1819 04:46:01.768044 Final RX Vref Byte 0 = 59 to rank1
1820 04:46:01.772076 Final RX Vref Byte 1 = 52 to rank1==
1821 04:46:01.775657 Dram Type= 6, Freq= 0, CH_1, rank 0
1822 04:46:01.781715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1823 04:46:01.782140 ==
1824 04:46:01.782473 DQS Delay:
1825 04:46:01.782783 DQS0 = 0, DQS1 = 0
1826 04:46:01.785437 DQM Delay:
1827 04:46:01.785976 DQM0 = 87, DQM1 = 81
1828 04:46:01.788567 DQ Delay:
1829 04:46:01.791822 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1830 04:46:01.792243 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
1831 04:46:01.795076 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =76
1832 04:46:01.801924 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1833 04:46:01.802363
1834 04:46:01.802695
1835 04:46:01.808595 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a2d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1836 04:46:01.811593 CH1 RK0: MR19=606, MR18=1A2D
1837 04:46:01.818071 CH1_RK0: MR19=0x606, MR18=0x1A2D, DQSOSC=398, MR23=63, INC=93, DEC=62
1838 04:46:01.818664
1839 04:46:01.821779 ----->DramcWriteLeveling(PI) begin...
1840 04:46:01.822206 ==
1841 04:46:01.825259 Dram Type= 6, Freq= 0, CH_1, rank 1
1842 04:46:01.828127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1843 04:46:01.828552 ==
1844 04:46:01.831412 Write leveling (Byte 0): 26 => 26
1845 04:46:01.834837 Write leveling (Byte 1): 27 => 27
1846 04:46:01.838086 DramcWriteLeveling(PI) end<-----
1847 04:46:01.838507
1848 04:46:01.838872 ==
1849 04:46:01.841544 Dram Type= 6, Freq= 0, CH_1, rank 1
1850 04:46:01.844798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1851 04:46:01.845223 ==
1852 04:46:01.848585 [Gating] SW mode calibration
1853 04:46:01.854923 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1854 04:46:01.862027 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1855 04:46:01.864588 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1856 04:46:01.867913 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1857 04:46:01.874770 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 04:46:01.878181 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 04:46:01.881603 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 04:46:01.888604 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 04:46:01.891533 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 04:46:01.895332 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 04:46:01.901401 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 04:46:01.904754 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 04:46:01.908020 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 04:46:01.915486 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 04:46:01.917999 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 04:46:01.921255 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 04:46:01.927957 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 04:46:01.931283 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 04:46:01.934644 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1872 04:46:01.941052 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1873 04:46:01.944830 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 04:46:01.947565 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 04:46:01.954312 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 04:46:01.957321 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 04:46:01.961175 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 04:46:01.967630 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 04:46:01.970720 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 04:46:01.973968 0 9 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
1881 04:46:01.980494 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
1882 04:46:01.984192 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1883 04:46:01.987627 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1884 04:46:01.994045 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1885 04:46:01.997166 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1886 04:46:02.000590 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 04:46:02.007446 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 04:46:02.010963 0 10 4 | B1->B0 | 3434 2a2a | 0 0 | (0 1) (1 1)
1889 04:46:02.014517 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 04:46:02.020725 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 04:46:02.023895 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 04:46:02.027332 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 04:46:02.034502 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 04:46:02.037099 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 04:46:02.040559 0 11 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1896 04:46:02.043985 0 11 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
1897 04:46:02.051169 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1898 04:46:02.054231 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 04:46:02.057175 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 04:46:02.064095 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 04:46:02.066927 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 04:46:02.070299 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 04:46:02.076883 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1904 04:46:02.079913 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1905 04:46:02.083838 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 04:46:02.090303 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 04:46:02.094135 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 04:46:02.096992 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 04:46:02.103637 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 04:46:02.106932 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 04:46:02.111027 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 04:46:02.117046 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 04:46:02.120097 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 04:46:02.123259 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 04:46:02.129975 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 04:46:02.133427 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 04:46:02.136559 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 04:46:02.143106 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 04:46:02.146336 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1920 04:46:02.149833 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1921 04:46:02.153598 Total UI for P1: 0, mck2ui 16
1922 04:46:02.156586 best dqsien dly found for B0: ( 0, 14, 0)
1923 04:46:02.163398 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 04:46:02.164085 Total UI for P1: 0, mck2ui 16
1925 04:46:02.166209 best dqsien dly found for B1: ( 0, 14, 6)
1926 04:46:02.173050 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1927 04:46:02.176515 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1928 04:46:02.177045
1929 04:46:02.179569 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1930 04:46:02.182797 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1931 04:46:02.186031 [Gating] SW calibration Done
1932 04:46:02.186447 ==
1933 04:46:02.189497 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 04:46:02.192711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 04:46:02.193133 ==
1936 04:46:02.196490 RX Vref Scan: 0
1937 04:46:02.196908
1938 04:46:02.197238 RX Vref 0 -> 0, step: 1
1939 04:46:02.197547
1940 04:46:02.199757 RX Delay -130 -> 252, step: 16
1941 04:46:02.203584 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1942 04:46:02.209925 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1943 04:46:02.213238 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1944 04:46:02.216540 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1945 04:46:02.219544 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1946 04:46:02.222842 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1947 04:46:02.229218 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1948 04:46:02.232921 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1949 04:46:02.235777 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1950 04:46:02.238929 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1951 04:46:02.242266 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1952 04:46:02.249649 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1953 04:46:02.252226 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1954 04:46:02.255835 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1955 04:46:02.259567 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1956 04:46:02.265621 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1957 04:46:02.266136 ==
1958 04:46:02.268894 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 04:46:02.272337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 04:46:02.272856 ==
1961 04:46:02.273194 DQS Delay:
1962 04:46:02.275565 DQS0 = 0, DQS1 = 0
1963 04:46:02.276158 DQM Delay:
1964 04:46:02.278858 DQM0 = 83, DQM1 = 82
1965 04:46:02.279317 DQ Delay:
1966 04:46:02.282155 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1967 04:46:02.285805 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1968 04:46:02.288287 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1969 04:46:02.291829 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1970 04:46:02.292347
1971 04:46:02.292683
1972 04:46:02.292994 ==
1973 04:46:02.295698 Dram Type= 6, Freq= 0, CH_1, rank 1
1974 04:46:02.298404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1975 04:46:02.298944 ==
1976 04:46:02.302141
1977 04:46:02.302658
1978 04:46:02.302994 TX Vref Scan disable
1979 04:46:02.305141 == TX Byte 0 ==
1980 04:46:02.308938 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1981 04:46:02.311911 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1982 04:46:02.315188 == TX Byte 1 ==
1983 04:46:02.318301 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1984 04:46:02.321895 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1985 04:46:02.322402 ==
1986 04:46:02.325650 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 04:46:02.331768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 04:46:02.332194 ==
1989 04:46:02.343356 TX Vref=22, minBit 5, minWin=26, winSum=446
1990 04:46:02.346763 TX Vref=24, minBit 2, minWin=27, winSum=450
1991 04:46:02.350136 TX Vref=26, minBit 1, minWin=27, winSum=451
1992 04:46:02.353231 TX Vref=28, minBit 2, minWin=27, winSum=452
1993 04:46:02.357052 TX Vref=30, minBit 2, minWin=27, winSum=455
1994 04:46:02.360182 TX Vref=32, minBit 2, minWin=27, winSum=453
1995 04:46:02.366741 [TxChooseVref] Worse bit 2, Min win 27, Win sum 455, Final Vref 30
1996 04:46:02.367235
1997 04:46:02.370376 Final TX Range 1 Vref 30
1998 04:46:02.370795
1999 04:46:02.371124 ==
2000 04:46:02.373426 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 04:46:02.377063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 04:46:02.377484 ==
2003 04:46:02.377812
2004 04:46:02.380196
2005 04:46:02.380644 TX Vref Scan disable
2006 04:46:02.383799 == TX Byte 0 ==
2007 04:46:02.387023 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2008 04:46:02.393528 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2009 04:46:02.394048 == TX Byte 1 ==
2010 04:46:02.396893 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2011 04:46:02.400659 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2012 04:46:02.403517
2013 04:46:02.404026 [DATLAT]
2014 04:46:02.404361 Freq=800, CH1 RK1
2015 04:46:02.404673
2016 04:46:02.407742 DATLAT Default: 0xa
2017 04:46:02.408254 0, 0xFFFF, sum = 0
2018 04:46:02.409980 1, 0xFFFF, sum = 0
2019 04:46:02.410498 2, 0xFFFF, sum = 0
2020 04:46:02.413630 3, 0xFFFF, sum = 0
2021 04:46:02.414055 4, 0xFFFF, sum = 0
2022 04:46:02.417112 5, 0xFFFF, sum = 0
2023 04:46:02.420460 6, 0xFFFF, sum = 0
2024 04:46:02.420881 7, 0xFFFF, sum = 0
2025 04:46:02.423428 8, 0xFFFF, sum = 0
2026 04:46:02.423950 9, 0x0, sum = 1
2027 04:46:02.424293 10, 0x0, sum = 2
2028 04:46:02.426867 11, 0x0, sum = 3
2029 04:46:02.427427 12, 0x0, sum = 4
2030 04:46:02.430027 best_step = 10
2031 04:46:02.430540
2032 04:46:02.430873 ==
2033 04:46:02.433032 Dram Type= 6, Freq= 0, CH_1, rank 1
2034 04:46:02.436989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2035 04:46:02.437510 ==
2036 04:46:02.439572 RX Vref Scan: 0
2037 04:46:02.439991
2038 04:46:02.440323 RX Vref 0 -> 0, step: 1
2039 04:46:02.442853
2040 04:46:02.443265 RX Delay -95 -> 252, step: 8
2041 04:46:02.450073 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2042 04:46:02.453728 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2043 04:46:02.456875 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2044 04:46:02.460040 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2045 04:46:02.467141 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2046 04:46:02.469756 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2047 04:46:02.473082 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2048 04:46:02.476171 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2049 04:46:02.479441 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2050 04:46:02.486131 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2051 04:46:02.489738 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2052 04:46:02.492785 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2053 04:46:02.496299 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2054 04:46:02.499293 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2055 04:46:02.506046 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2056 04:46:02.509192 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2057 04:46:02.509762 ==
2058 04:46:02.512742 Dram Type= 6, Freq= 0, CH_1, rank 1
2059 04:46:02.515998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2060 04:46:02.516464 ==
2061 04:46:02.519262 DQS Delay:
2062 04:46:02.519886 DQS0 = 0, DQS1 = 0
2063 04:46:02.520276 DQM Delay:
2064 04:46:02.523185 DQM0 = 86, DQM1 = 82
2065 04:46:02.523704 DQ Delay:
2066 04:46:02.525908 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2067 04:46:02.529586 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2068 04:46:02.532949 DQ8 =68, DQ9 =76, DQ10 =80, DQ11 =76
2069 04:46:02.535481 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =88
2070 04:46:02.535905
2071 04:46:02.536239
2072 04:46:02.545816 [DQSOSCAuto] RK1, (LSB)MR18= 0x203c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2073 04:46:02.548714 CH1 RK1: MR19=606, MR18=203C
2074 04:46:02.551948 CH1_RK1: MR19=0x606, MR18=0x203C, DQSOSC=394, MR23=63, INC=95, DEC=63
2075 04:46:02.555547 [RxdqsGatingPostProcess] freq 800
2076 04:46:02.562117 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2077 04:46:02.565684 Pre-setting of DQS Precalculation
2078 04:46:02.568940 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2079 04:46:02.578829 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2080 04:46:02.585393 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2081 04:46:02.585821
2082 04:46:02.586152
2083 04:46:02.589036 [Calibration Summary] 1600 Mbps
2084 04:46:02.589843 CH 0, Rank 0
2085 04:46:02.591775 SW Impedance : PASS
2086 04:46:02.592194 DUTY Scan : NO K
2087 04:46:02.595072 ZQ Calibration : PASS
2088 04:46:02.598295 Jitter Meter : NO K
2089 04:46:02.598903 CBT Training : PASS
2090 04:46:02.601554 Write leveling : PASS
2091 04:46:02.604910 RX DQS gating : PASS
2092 04:46:02.605464 RX DQ/DQS(RDDQC) : PASS
2093 04:46:02.608251 TX DQ/DQS : PASS
2094 04:46:02.611854 RX DATLAT : PASS
2095 04:46:02.612276 RX DQ/DQS(Engine): PASS
2096 04:46:02.614941 TX OE : NO K
2097 04:46:02.615506 All Pass.
2098 04:46:02.615854
2099 04:46:02.618477 CH 0, Rank 1
2100 04:46:02.618898 SW Impedance : PASS
2101 04:46:02.622039 DUTY Scan : NO K
2102 04:46:02.624985 ZQ Calibration : PASS
2103 04:46:02.625522 Jitter Meter : NO K
2104 04:46:02.628589 CBT Training : PASS
2105 04:46:02.631804 Write leveling : PASS
2106 04:46:02.632315 RX DQS gating : PASS
2107 04:46:02.634842 RX DQ/DQS(RDDQC) : PASS
2108 04:46:02.635263 TX DQ/DQS : PASS
2109 04:46:02.638209 RX DATLAT : PASS
2110 04:46:02.641504 RX DQ/DQS(Engine): PASS
2111 04:46:02.641926 TX OE : NO K
2112 04:46:02.645090 All Pass.
2113 04:46:02.645509
2114 04:46:02.645841 CH 1, Rank 0
2115 04:46:02.647995 SW Impedance : PASS
2116 04:46:02.648417 DUTY Scan : NO K
2117 04:46:02.651910 ZQ Calibration : PASS
2118 04:46:02.654947 Jitter Meter : NO K
2119 04:46:02.655405 CBT Training : PASS
2120 04:46:02.659437 Write leveling : PASS
2121 04:46:02.661470 RX DQS gating : PASS
2122 04:46:02.661890 RX DQ/DQS(RDDQC) : PASS
2123 04:46:02.664925 TX DQ/DQS : PASS
2124 04:46:02.668064 RX DATLAT : PASS
2125 04:46:02.668487 RX DQ/DQS(Engine): PASS
2126 04:46:02.671054 TX OE : NO K
2127 04:46:02.671532 All Pass.
2128 04:46:02.671874
2129 04:46:02.674925 CH 1, Rank 1
2130 04:46:02.675346 SW Impedance : PASS
2131 04:46:02.678184 DUTY Scan : NO K
2132 04:46:02.681308 ZQ Calibration : PASS
2133 04:46:02.681731 Jitter Meter : NO K
2134 04:46:02.685164 CBT Training : PASS
2135 04:46:02.687700 Write leveling : PASS
2136 04:46:02.688127 RX DQS gating : PASS
2137 04:46:02.691934 RX DQ/DQS(RDDQC) : PASS
2138 04:46:02.695134 TX DQ/DQS : PASS
2139 04:46:02.695696 RX DATLAT : PASS
2140 04:46:02.698241 RX DQ/DQS(Engine): PASS
2141 04:46:02.698788 TX OE : NO K
2142 04:46:02.701519 All Pass.
2143 04:46:02.702035
2144 04:46:02.702368 DramC Write-DBI off
2145 04:46:02.704785 PER_BANK_REFRESH: Hybrid Mode
2146 04:46:02.708042 TX_TRACKING: ON
2147 04:46:02.711516 [GetDramInforAfterCalByMRR] Vendor 6.
2148 04:46:02.714968 [GetDramInforAfterCalByMRR] Revision 606.
2149 04:46:02.717940 [GetDramInforAfterCalByMRR] Revision 2 0.
2150 04:46:02.718457 MR0 0x3b3b
2151 04:46:02.718793 MR8 0x5151
2152 04:46:02.724666 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2153 04:46:02.725177
2154 04:46:02.725576 MR0 0x3b3b
2155 04:46:02.725921 MR8 0x5151
2156 04:46:02.727968 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2157 04:46:02.728390
2158 04:46:02.738019 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2159 04:46:02.740955 [FAST_K] Save calibration result to emmc
2160 04:46:02.744804 [FAST_K] Save calibration result to emmc
2161 04:46:02.747604 dram_init: config_dvfs: 1
2162 04:46:02.751741 dramc_set_vcore_voltage set vcore to 662500
2163 04:46:02.754815 Read voltage for 1200, 2
2164 04:46:02.755234 Vio18 = 0
2165 04:46:02.755639 Vcore = 662500
2166 04:46:02.757550 Vdram = 0
2167 04:46:02.757969 Vddq = 0
2168 04:46:02.758340 Vmddr = 0
2169 04:46:02.764886 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2170 04:46:02.767710 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2171 04:46:02.771422 MEM_TYPE=3, freq_sel=15
2172 04:46:02.774594 sv_algorithm_assistance_LP4_1600
2173 04:46:02.777691 ============ PULL DRAM RESETB DOWN ============
2174 04:46:02.784031 ========== PULL DRAM RESETB DOWN end =========
2175 04:46:02.788045 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2176 04:46:02.790815 ===================================
2177 04:46:02.794171 LPDDR4 DRAM CONFIGURATION
2178 04:46:02.797425 ===================================
2179 04:46:02.797943 EX_ROW_EN[0] = 0x0
2180 04:46:02.800764 EX_ROW_EN[1] = 0x0
2181 04:46:02.801276 LP4Y_EN = 0x0
2182 04:46:02.803829 WORK_FSP = 0x0
2183 04:46:02.804252 WL = 0x4
2184 04:46:02.807483 RL = 0x4
2185 04:46:02.807998 BL = 0x2
2186 04:46:02.810855 RPST = 0x0
2187 04:46:02.811408 RD_PRE = 0x0
2188 04:46:02.813949 WR_PRE = 0x1
2189 04:46:02.817318 WR_PST = 0x0
2190 04:46:02.817830 DBI_WR = 0x0
2191 04:46:02.820957 DBI_RD = 0x0
2192 04:46:02.821380 OTF = 0x1
2193 04:46:02.824065 ===================================
2194 04:46:02.827800 ===================================
2195 04:46:02.830834 ANA top config
2196 04:46:02.831347 ===================================
2197 04:46:02.833492 DLL_ASYNC_EN = 0
2198 04:46:02.837099 ALL_SLAVE_EN = 0
2199 04:46:02.841055 NEW_RANK_MODE = 1
2200 04:46:02.843424 DLL_IDLE_MODE = 1
2201 04:46:02.843850 LP45_APHY_COMB_EN = 1
2202 04:46:02.847239 TX_ODT_DIS = 1
2203 04:46:02.850937 NEW_8X_MODE = 1
2204 04:46:02.853583 ===================================
2205 04:46:02.856961 ===================================
2206 04:46:02.860181 data_rate = 2400
2207 04:46:02.863411 CKR = 1
2208 04:46:02.867359 DQ_P2S_RATIO = 8
2209 04:46:02.870089 ===================================
2210 04:46:02.870607 CA_P2S_RATIO = 8
2211 04:46:02.873788 DQ_CA_OPEN = 0
2212 04:46:02.877622 DQ_SEMI_OPEN = 0
2213 04:46:02.880138 CA_SEMI_OPEN = 0
2214 04:46:02.883262 CA_FULL_RATE = 0
2215 04:46:02.886773 DQ_CKDIV4_EN = 0
2216 04:46:02.887192 CA_CKDIV4_EN = 0
2217 04:46:02.890063 CA_PREDIV_EN = 0
2218 04:46:02.893519 PH8_DLY = 17
2219 04:46:02.897100 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2220 04:46:02.900570 DQ_AAMCK_DIV = 4
2221 04:46:02.902998 CA_AAMCK_DIV = 4
2222 04:46:02.903452 CA_ADMCK_DIV = 4
2223 04:46:02.906556 DQ_TRACK_CA_EN = 0
2224 04:46:02.909946 CA_PICK = 1200
2225 04:46:02.913388 CA_MCKIO = 1200
2226 04:46:02.916981 MCKIO_SEMI = 0
2227 04:46:02.919931 PLL_FREQ = 2366
2228 04:46:02.923125 DQ_UI_PI_RATIO = 32
2229 04:46:02.923584 CA_UI_PI_RATIO = 0
2230 04:46:02.927121 ===================================
2231 04:46:02.930208 ===================================
2232 04:46:02.933640 memory_type:LPDDR4
2233 04:46:02.936640 GP_NUM : 10
2234 04:46:02.937103 SRAM_EN : 1
2235 04:46:02.939979 MD32_EN : 0
2236 04:46:02.942839 ===================================
2237 04:46:02.946722 [ANA_INIT] >>>>>>>>>>>>>>
2238 04:46:02.950063 <<<<<< [CONFIGURE PHASE]: ANA_TX
2239 04:46:02.953521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2240 04:46:02.956374 ===================================
2241 04:46:02.956799 data_rate = 2400,PCW = 0X5b00
2242 04:46:02.959520 ===================================
2243 04:46:02.963123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2244 04:46:02.970219 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2245 04:46:02.976497 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2246 04:46:02.979847 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2247 04:46:02.982735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2248 04:46:02.986260 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2249 04:46:02.989589 [ANA_INIT] flow start
2250 04:46:02.990013 [ANA_INIT] PLL >>>>>>>>
2251 04:46:02.992759 [ANA_INIT] PLL <<<<<<<<
2252 04:46:02.996360 [ANA_INIT] MIDPI >>>>>>>>
2253 04:46:02.999675 [ANA_INIT] MIDPI <<<<<<<<
2254 04:46:03.000095 [ANA_INIT] DLL >>>>>>>>
2255 04:46:03.003191 [ANA_INIT] DLL <<<<<<<<
2256 04:46:03.006407 [ANA_INIT] flow end
2257 04:46:03.009631 ============ LP4 DIFF to SE enter ============
2258 04:46:03.013035 ============ LP4 DIFF to SE exit ============
2259 04:46:03.016044 [ANA_INIT] <<<<<<<<<<<<<
2260 04:46:03.019316 [Flow] Enable top DCM control >>>>>
2261 04:46:03.022587 [Flow] Enable top DCM control <<<<<
2262 04:46:03.026075 Enable DLL master slave shuffle
2263 04:46:03.029337 ==============================================================
2264 04:46:03.032751 Gating Mode config
2265 04:46:03.039041 ==============================================================
2266 04:46:03.039490 Config description:
2267 04:46:03.048937 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2268 04:46:03.056220 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2269 04:46:03.058868 SELPH_MODE 0: By rank 1: By Phase
2270 04:46:03.065945 ==============================================================
2271 04:46:03.068841 GAT_TRACK_EN = 1
2272 04:46:03.072123 RX_GATING_MODE = 2
2273 04:46:03.075355 RX_GATING_TRACK_MODE = 2
2274 04:46:03.078616 SELPH_MODE = 1
2275 04:46:03.082018 PICG_EARLY_EN = 1
2276 04:46:03.085636 VALID_LAT_VALUE = 1
2277 04:46:03.088931 ==============================================================
2278 04:46:03.092146 Enter into Gating configuration >>>>
2279 04:46:03.095131 Exit from Gating configuration <<<<
2280 04:46:03.099355 Enter into DVFS_PRE_config >>>>>
2281 04:46:03.111864 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2282 04:46:03.112380 Exit from DVFS_PRE_config <<<<<
2283 04:46:03.115097 Enter into PICG configuration >>>>
2284 04:46:03.118707 Exit from PICG configuration <<<<
2285 04:46:03.122174 [RX_INPUT] configuration >>>>>
2286 04:46:03.126182 [RX_INPUT] configuration <<<<<
2287 04:46:03.132279 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2288 04:46:03.135315 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2289 04:46:03.141993 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2290 04:46:03.148948 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2291 04:46:03.155024 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2292 04:46:03.162110 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2293 04:46:03.165193 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2294 04:46:03.168511 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2295 04:46:03.171644 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2296 04:46:03.178600 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2297 04:46:03.181436 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2298 04:46:03.185387 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2299 04:46:03.188397 ===================================
2300 04:46:03.192158 LPDDR4 DRAM CONFIGURATION
2301 04:46:03.195225 ===================================
2302 04:46:03.195789 EX_ROW_EN[0] = 0x0
2303 04:46:03.198700 EX_ROW_EN[1] = 0x0
2304 04:46:03.201412 LP4Y_EN = 0x0
2305 04:46:03.201838 WORK_FSP = 0x0
2306 04:46:03.204638 WL = 0x4
2307 04:46:03.205058 RL = 0x4
2308 04:46:03.208690 BL = 0x2
2309 04:46:03.209208 RPST = 0x0
2310 04:46:03.211812 RD_PRE = 0x0
2311 04:46:03.212328 WR_PRE = 0x1
2312 04:46:03.215026 WR_PST = 0x0
2313 04:46:03.215584 DBI_WR = 0x0
2314 04:46:03.218282 DBI_RD = 0x0
2315 04:46:03.218797 OTF = 0x1
2316 04:46:03.221670 ===================================
2317 04:46:03.224920 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2318 04:46:03.231462 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2319 04:46:03.234749 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2320 04:46:03.237778 ===================================
2321 04:46:03.241447 LPDDR4 DRAM CONFIGURATION
2322 04:46:03.244673 ===================================
2323 04:46:03.245098 EX_ROW_EN[0] = 0x10
2324 04:46:03.248072 EX_ROW_EN[1] = 0x0
2325 04:46:03.251200 LP4Y_EN = 0x0
2326 04:46:03.251758 WORK_FSP = 0x0
2327 04:46:03.255255 WL = 0x4
2328 04:46:03.255814 RL = 0x4
2329 04:46:03.257876 BL = 0x2
2330 04:46:03.258296 RPST = 0x0
2331 04:46:03.261098 RD_PRE = 0x0
2332 04:46:03.261550 WR_PRE = 0x1
2333 04:46:03.264459 WR_PST = 0x0
2334 04:46:03.264874 DBI_WR = 0x0
2335 04:46:03.268368 DBI_RD = 0x0
2336 04:46:03.268895 OTF = 0x1
2337 04:46:03.271833 ===================================
2338 04:46:03.277862 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2339 04:46:03.278372 ==
2340 04:46:03.281080 Dram Type= 6, Freq= 0, CH_0, rank 0
2341 04:46:03.284417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2342 04:46:03.287792 ==
2343 04:46:03.288214 [Duty_Offset_Calibration]
2344 04:46:03.291200 B0:2 B1:0 CA:4
2345 04:46:03.291643
2346 04:46:03.294133 [DutyScan_Calibration_Flow] k_type=0
2347 04:46:03.303131
2348 04:46:03.303701 ==CLK 0==
2349 04:46:03.306222 Final CLK duty delay cell = 0
2350 04:46:03.310267 [0] MAX Duty = 5156%(X100), DQS PI = 14
2351 04:46:03.313247 [0] MIN Duty = 4969%(X100), DQS PI = 8
2352 04:46:03.313812 [0] AVG Duty = 5062%(X100)
2353 04:46:03.316612
2354 04:46:03.319616 CH0 CLK Duty spec in!! Max-Min= 187%
2355 04:46:03.322550 [DutyScan_Calibration_Flow] ====Done====
2356 04:46:03.323014
2357 04:46:03.326470 [DutyScan_Calibration_Flow] k_type=1
2358 04:46:03.342477
2359 04:46:03.343048 ==DQS 0 ==
2360 04:46:03.345504 Final DQS duty delay cell = 0
2361 04:46:03.348751 [0] MAX Duty = 5156%(X100), DQS PI = 18
2362 04:46:03.352021 [0] MIN Duty = 5093%(X100), DQS PI = 2
2363 04:46:03.355428 [0] AVG Duty = 5124%(X100)
2364 04:46:03.355843
2365 04:46:03.356168 ==DQS 1 ==
2366 04:46:03.358943 Final DQS duty delay cell = 0
2367 04:46:03.361854 [0] MAX Duty = 5125%(X100), DQS PI = 50
2368 04:46:03.364878 [0] MIN Duty = 4969%(X100), DQS PI = 62
2369 04:46:03.368264 [0] AVG Duty = 5047%(X100)
2370 04:46:03.368679
2371 04:46:03.371648 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2372 04:46:03.372063
2373 04:46:03.375327 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2374 04:46:03.378640 [DutyScan_Calibration_Flow] ====Done====
2375 04:46:03.379162
2376 04:46:03.381794 [DutyScan_Calibration_Flow] k_type=3
2377 04:46:03.398612
2378 04:46:03.399129 ==DQM 0 ==
2379 04:46:03.401802 Final DQM duty delay cell = 0
2380 04:46:03.405134 [0] MAX Duty = 5125%(X100), DQS PI = 20
2381 04:46:03.408628 [0] MIN Duty = 4844%(X100), DQS PI = 52
2382 04:46:03.411555 [0] AVG Duty = 4984%(X100)
2383 04:46:03.411973
2384 04:46:03.412297 ==DQM 1 ==
2385 04:46:03.414948 Final DQM duty delay cell = 0
2386 04:46:03.418704 [0] MAX Duty = 4969%(X100), DQS PI = 2
2387 04:46:03.421983 [0] MIN Duty = 4875%(X100), DQS PI = 18
2388 04:46:03.425709 [0] AVG Duty = 4922%(X100)
2389 04:46:03.426248
2390 04:46:03.428527 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2391 04:46:03.429040
2392 04:46:03.431742 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2393 04:46:03.434796 [DutyScan_Calibration_Flow] ====Done====
2394 04:46:03.435310
2395 04:46:03.437983 [DutyScan_Calibration_Flow] k_type=2
2396 04:46:03.455244
2397 04:46:03.455870 ==DQ 0 ==
2398 04:46:03.458655 Final DQ duty delay cell = 0
2399 04:46:03.461120 [0] MAX Duty = 5125%(X100), DQS PI = 18
2400 04:46:03.464957 [0] MIN Duty = 4969%(X100), DQS PI = 52
2401 04:46:03.465467 [0] AVG Duty = 5047%(X100)
2402 04:46:03.468495
2403 04:46:03.469003 ==DQ 1 ==
2404 04:46:03.471301 Final DQ duty delay cell = 0
2405 04:46:03.474638 [0] MAX Duty = 5156%(X100), DQS PI = 6
2406 04:46:03.478166 [0] MIN Duty = 4938%(X100), DQS PI = 14
2407 04:46:03.478587 [0] AVG Duty = 5047%(X100)
2408 04:46:03.478917
2409 04:46:03.481786 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2410 04:46:03.484674
2411 04:46:03.487973 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2412 04:46:03.491396 [DutyScan_Calibration_Flow] ====Done====
2413 04:46:03.491839 ==
2414 04:46:03.494741 Dram Type= 6, Freq= 0, CH_1, rank 0
2415 04:46:03.497839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2416 04:46:03.498383 ==
2417 04:46:03.501387 [Duty_Offset_Calibration]
2418 04:46:03.501898 B0:0 B1:-1 CA:3
2419 04:46:03.502231
2420 04:46:03.504765 [DutyScan_Calibration_Flow] k_type=0
2421 04:46:03.515159
2422 04:46:03.515706 ==CLK 0==
2423 04:46:03.518424 Final CLK duty delay cell = 0
2424 04:46:03.521822 [0] MAX Duty = 5156%(X100), DQS PI = 10
2425 04:46:03.524533 [0] MIN Duty = 5000%(X100), DQS PI = 4
2426 04:46:03.524955 [0] AVG Duty = 5078%(X100)
2427 04:46:03.528056
2428 04:46:03.531556 CH1 CLK Duty spec in!! Max-Min= 156%
2429 04:46:03.535228 [DutyScan_Calibration_Flow] ====Done====
2430 04:46:03.535797
2431 04:46:03.538253 [DutyScan_Calibration_Flow] k_type=1
2432 04:46:03.554198
2433 04:46:03.554704 ==DQS 0 ==
2434 04:46:03.557860 Final DQS duty delay cell = 0
2435 04:46:03.560586 [0] MAX Duty = 5156%(X100), DQS PI = 50
2436 04:46:03.563962 [0] MIN Duty = 4907%(X100), DQS PI = 6
2437 04:46:03.564380 [0] AVG Duty = 5031%(X100)
2438 04:46:03.567199
2439 04:46:03.567648 ==DQS 1 ==
2440 04:46:03.570476 Final DQS duty delay cell = 0
2441 04:46:03.573686 [0] MAX Duty = 5156%(X100), DQS PI = 0
2442 04:46:03.577080 [0] MIN Duty = 5031%(X100), DQS PI = 52
2443 04:46:03.577511 [0] AVG Duty = 5093%(X100)
2444 04:46:03.580511
2445 04:46:03.584058 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2446 04:46:03.584597
2447 04:46:03.587443 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2448 04:46:03.590984 [DutyScan_Calibration_Flow] ====Done====
2449 04:46:03.591563
2450 04:46:03.593888 [DutyScan_Calibration_Flow] k_type=3
2451 04:46:03.610536
2452 04:46:03.611080 ==DQM 0 ==
2453 04:46:03.613580 Final DQM duty delay cell = 0
2454 04:46:03.617136 [0] MAX Duty = 5031%(X100), DQS PI = 12
2455 04:46:03.620173 [0] MIN Duty = 4782%(X100), DQS PI = 6
2456 04:46:03.620600 [0] AVG Duty = 4906%(X100)
2457 04:46:03.623996
2458 04:46:03.624478 ==DQM 1 ==
2459 04:46:03.626775 Final DQM duty delay cell = 0
2460 04:46:03.630352 [0] MAX Duty = 4969%(X100), DQS PI = 2
2461 04:46:03.633905 [0] MIN Duty = 4844%(X100), DQS PI = 30
2462 04:46:03.634428 [0] AVG Duty = 4906%(X100)
2463 04:46:03.636742
2464 04:46:03.640140 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2465 04:46:03.640562
2466 04:46:03.643331 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2467 04:46:03.646980 [DutyScan_Calibration_Flow] ====Done====
2468 04:46:03.647596
2469 04:46:03.650827 [DutyScan_Calibration_Flow] k_type=2
2470 04:46:03.666847
2471 04:46:03.667414 ==DQ 0 ==
2472 04:46:03.669021 Final DQ duty delay cell = -4
2473 04:46:03.672590 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2474 04:46:03.676014 [-4] MIN Duty = 4844%(X100), DQS PI = 4
2475 04:46:03.679827 [-4] AVG Duty = 4937%(X100)
2476 04:46:03.680350
2477 04:46:03.680688 ==DQ 1 ==
2478 04:46:03.682990 Final DQ duty delay cell = 0
2479 04:46:03.685935 [0] MAX Duty = 5031%(X100), DQS PI = 2
2480 04:46:03.689210 [0] MIN Duty = 4844%(X100), DQS PI = 30
2481 04:46:03.689740 [0] AVG Duty = 4937%(X100)
2482 04:46:03.692933
2483 04:46:03.695915 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2484 04:46:03.696342
2485 04:46:03.699966 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2486 04:46:03.702786 [DutyScan_Calibration_Flow] ====Done====
2487 04:46:03.706159 nWR fixed to 30
2488 04:46:03.706685 [ModeRegInit_LP4] CH0 RK0
2489 04:46:03.709445 [ModeRegInit_LP4] CH0 RK1
2490 04:46:03.712687 [ModeRegInit_LP4] CH1 RK0
2491 04:46:03.713209 [ModeRegInit_LP4] CH1 RK1
2492 04:46:03.716260 match AC timing 7
2493 04:46:03.719802 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2494 04:46:03.725984 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2495 04:46:03.729472 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2496 04:46:03.732966 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2497 04:46:03.739408 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2498 04:46:03.739980 ==
2499 04:46:03.742591 Dram Type= 6, Freq= 0, CH_0, rank 0
2500 04:46:03.745526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2501 04:46:03.746082 ==
2502 04:46:03.752257 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2503 04:46:03.758980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2504 04:46:03.766302 [CA 0] Center 39 (9~70) winsize 62
2505 04:46:03.769213 [CA 1] Center 39 (9~69) winsize 61
2506 04:46:03.772795 [CA 2] Center 35 (5~66) winsize 62
2507 04:46:03.776338 [CA 3] Center 35 (5~66) winsize 62
2508 04:46:03.779632 [CA 4] Center 34 (3~65) winsize 63
2509 04:46:03.782696 [CA 5] Center 33 (3~63) winsize 61
2510 04:46:03.783121
2511 04:46:03.785991 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2512 04:46:03.786522
2513 04:46:03.789325 [CATrainingPosCal] consider 1 rank data
2514 04:46:03.792706 u2DelayCellTimex100 = 270/100 ps
2515 04:46:03.795948 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2516 04:46:03.802638 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2517 04:46:03.806491 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2518 04:46:03.809767 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2519 04:46:03.812456 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2520 04:46:03.816349 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2521 04:46:03.816878
2522 04:46:03.819742 CA PerBit enable=1, Macro0, CA PI delay=33
2523 04:46:03.820272
2524 04:46:03.823081 [CBTSetCACLKResult] CA Dly = 33
2525 04:46:03.823644 CS Dly: 7 (0~38)
2526 04:46:03.826183 ==
2527 04:46:03.829471 Dram Type= 6, Freq= 0, CH_0, rank 1
2528 04:46:03.833142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 04:46:03.833674 ==
2530 04:46:03.835814 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2531 04:46:03.842326 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2532 04:46:03.851991 [CA 0] Center 39 (9~70) winsize 62
2533 04:46:03.855134 [CA 1] Center 39 (9~70) winsize 62
2534 04:46:03.858811 [CA 2] Center 35 (5~66) winsize 62
2535 04:46:03.861819 [CA 3] Center 35 (4~66) winsize 63
2536 04:46:03.865266 [CA 4] Center 34 (4~65) winsize 62
2537 04:46:03.868362 [CA 5] Center 33 (3~64) winsize 62
2538 04:46:03.868826
2539 04:46:03.871727 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2540 04:46:03.872162
2541 04:46:03.875075 [CATrainingPosCal] consider 2 rank data
2542 04:46:03.878736 u2DelayCellTimex100 = 270/100 ps
2543 04:46:03.881369 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2544 04:46:03.888348 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2545 04:46:03.891659 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2546 04:46:03.894785 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2547 04:46:03.897864 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2548 04:46:03.901178 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2549 04:46:03.901598
2550 04:46:03.904712 CA PerBit enable=1, Macro0, CA PI delay=33
2551 04:46:03.905238
2552 04:46:03.908506 [CBTSetCACLKResult] CA Dly = 33
2553 04:46:03.911041 CS Dly: 8 (0~41)
2554 04:46:03.911495
2555 04:46:03.914839 ----->DramcWriteLeveling(PI) begin...
2556 04:46:03.915400 ==
2557 04:46:03.918030 Dram Type= 6, Freq= 0, CH_0, rank 0
2558 04:46:03.921228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2559 04:46:03.921755 ==
2560 04:46:03.924783 Write leveling (Byte 0): 31 => 31
2561 04:46:03.927820 Write leveling (Byte 1): 26 => 26
2562 04:46:03.931249 DramcWriteLeveling(PI) end<-----
2563 04:46:03.931727
2564 04:46:03.932062 ==
2565 04:46:03.934960 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 04:46:03.937545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 04:46:03.937971 ==
2568 04:46:03.940992 [Gating] SW mode calibration
2569 04:46:03.948010 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2570 04:46:03.954667 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2571 04:46:03.958023 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2572 04:46:03.961173 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2573 04:46:03.967819 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2574 04:46:03.970878 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2575 04:46:03.974436 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2576 04:46:03.981377 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2577 04:46:03.984528 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 04:46:03.987815 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
2579 04:46:03.993998 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
2580 04:46:03.997241 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2581 04:46:04.001396 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2582 04:46:04.007527 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 04:46:04.010780 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2584 04:46:04.014323 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 04:46:04.020934 1 0 24 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
2586 04:46:04.024551 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2587 04:46:04.027466 1 1 0 | B1->B0 | 2e2d 4646 | 1 0 | (0 0) (0 0)
2588 04:46:04.034168 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2589 04:46:04.037108 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 04:46:04.040714 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 04:46:04.047497 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 04:46:04.050995 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 04:46:04.053796 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2594 04:46:04.057912 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2595 04:46:04.063905 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2596 04:46:04.067805 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 04:46:04.070406 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 04:46:04.077186 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 04:46:04.080416 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 04:46:04.083837 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 04:46:04.090162 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 04:46:04.094000 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 04:46:04.097281 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 04:46:04.103469 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 04:46:04.107062 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 04:46:04.110565 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 04:46:04.117261 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 04:46:04.120075 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 04:46:04.123204 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2610 04:46:04.129749 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2611 04:46:04.133201 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2612 04:46:04.136305 Total UI for P1: 0, mck2ui 16
2613 04:46:04.139563 best dqsien dly found for B0: ( 1, 3, 26)
2614 04:46:04.142940 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 04:46:04.146487 Total UI for P1: 0, mck2ui 16
2616 04:46:04.150091 best dqsien dly found for B1: ( 1, 4, 0)
2617 04:46:04.153688 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2618 04:46:04.156209 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2619 04:46:04.156646
2620 04:46:04.163154 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2621 04:46:04.166550 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2622 04:46:04.169786 [Gating] SW calibration Done
2623 04:46:04.170330 ==
2624 04:46:04.172887 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 04:46:04.176605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 04:46:04.177127 ==
2627 04:46:04.177463 RX Vref Scan: 0
2628 04:46:04.177771
2629 04:46:04.179511 RX Vref 0 -> 0, step: 1
2630 04:46:04.180032
2631 04:46:04.182523 RX Delay -40 -> 252, step: 8
2632 04:46:04.186182 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2633 04:46:04.189771 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2634 04:46:04.196219 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2635 04:46:04.199310 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2636 04:46:04.202918 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2637 04:46:04.206050 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2638 04:46:04.209957 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2639 04:46:04.216699 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2640 04:46:04.219605 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2641 04:46:04.222653 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2642 04:46:04.226529 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2643 04:46:04.229383 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2644 04:46:04.236398 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2645 04:46:04.239397 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2646 04:46:04.242691 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2647 04:46:04.245697 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2648 04:46:04.246149 ==
2649 04:46:04.249435 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 04:46:04.255976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 04:46:04.256529 ==
2652 04:46:04.256884 DQS Delay:
2653 04:46:04.257199 DQS0 = 0, DQS1 = 0
2654 04:46:04.259229 DQM Delay:
2655 04:46:04.259789 DQM0 = 120, DQM1 = 107
2656 04:46:04.263091 DQ Delay:
2657 04:46:04.265643 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2658 04:46:04.269812 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2659 04:46:04.272521 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2660 04:46:04.275739 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2661 04:46:04.276165
2662 04:46:04.276498
2663 04:46:04.276810 ==
2664 04:46:04.278992 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 04:46:04.282354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 04:46:04.285339 ==
2667 04:46:04.285760
2668 04:46:04.286198
2669 04:46:04.286520 TX Vref Scan disable
2670 04:46:04.289419 == TX Byte 0 ==
2671 04:46:04.292389 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2672 04:46:04.295729 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2673 04:46:04.299461 == TX Byte 1 ==
2674 04:46:04.302195 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2675 04:46:04.305758 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2676 04:46:04.306281 ==
2677 04:46:04.308854 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 04:46:04.315107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 04:46:04.315723 ==
2680 04:46:04.326688 TX Vref=22, minBit 4, minWin=24, winSum=408
2681 04:46:04.329957 TX Vref=24, minBit 1, minWin=25, winSum=416
2682 04:46:04.333167 TX Vref=26, minBit 3, minWin=25, winSum=419
2683 04:46:04.336883 TX Vref=28, minBit 13, minWin=25, winSum=427
2684 04:46:04.340055 TX Vref=30, minBit 0, minWin=26, winSum=425
2685 04:46:04.346473 TX Vref=32, minBit 5, minWin=25, winSum=427
2686 04:46:04.349761 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 30
2687 04:46:04.350336
2688 04:46:04.353440 Final TX Range 1 Vref 30
2689 04:46:04.353959
2690 04:46:04.354295 ==
2691 04:46:04.356095 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 04:46:04.359728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 04:46:04.362777 ==
2694 04:46:04.363316
2695 04:46:04.363706
2696 04:46:04.364015 TX Vref Scan disable
2697 04:46:04.366105 == TX Byte 0 ==
2698 04:46:04.369720 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2699 04:46:04.373798 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2700 04:46:04.376381 == TX Byte 1 ==
2701 04:46:04.379896 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2702 04:46:04.386782 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2703 04:46:04.387306
2704 04:46:04.387678 [DATLAT]
2705 04:46:04.387992 Freq=1200, CH0 RK0
2706 04:46:04.388288
2707 04:46:04.389575 DATLAT Default: 0xd
2708 04:46:04.389992 0, 0xFFFF, sum = 0
2709 04:46:04.393365 1, 0xFFFF, sum = 0
2710 04:46:04.396408 2, 0xFFFF, sum = 0
2711 04:46:04.396936 3, 0xFFFF, sum = 0
2712 04:46:04.400111 4, 0xFFFF, sum = 0
2713 04:46:04.400538 5, 0xFFFF, sum = 0
2714 04:46:04.402711 6, 0xFFFF, sum = 0
2715 04:46:04.403241 7, 0xFFFF, sum = 0
2716 04:46:04.406321 8, 0xFFFF, sum = 0
2717 04:46:04.406850 9, 0xFFFF, sum = 0
2718 04:46:04.409757 10, 0xFFFF, sum = 0
2719 04:46:04.410184 11, 0xFFFF, sum = 0
2720 04:46:04.412942 12, 0x0, sum = 1
2721 04:46:04.413470 13, 0x0, sum = 2
2722 04:46:04.416369 14, 0x0, sum = 3
2723 04:46:04.416895 15, 0x0, sum = 4
2724 04:46:04.419948 best_step = 13
2725 04:46:04.420469
2726 04:46:04.420799 ==
2727 04:46:04.422850 Dram Type= 6, Freq= 0, CH_0, rank 0
2728 04:46:04.426391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2729 04:46:04.426939 ==
2730 04:46:04.427274 RX Vref Scan: 1
2731 04:46:04.427625
2732 04:46:04.429344 Set Vref Range= 32 -> 127
2733 04:46:04.429763
2734 04:46:04.432278 RX Vref 32 -> 127, step: 1
2735 04:46:04.432698
2736 04:46:04.436026 RX Delay -21 -> 252, step: 4
2737 04:46:04.436445
2738 04:46:04.439524 Set Vref, RX VrefLevel [Byte0]: 32
2739 04:46:04.443057 [Byte1]: 32
2740 04:46:04.443518
2741 04:46:04.445801 Set Vref, RX VrefLevel [Byte0]: 33
2742 04:46:04.449593 [Byte1]: 33
2743 04:46:04.452812
2744 04:46:04.453234 Set Vref, RX VrefLevel [Byte0]: 34
2745 04:46:04.456350 [Byte1]: 34
2746 04:46:04.461214
2747 04:46:04.461738 Set Vref, RX VrefLevel [Byte0]: 35
2748 04:46:04.464019 [Byte1]: 35
2749 04:46:04.469100
2750 04:46:04.469621 Set Vref, RX VrefLevel [Byte0]: 36
2751 04:46:04.472104 [Byte1]: 36
2752 04:46:04.476572
2753 04:46:04.477101 Set Vref, RX VrefLevel [Byte0]: 37
2754 04:46:04.479982 [Byte1]: 37
2755 04:46:04.484592
2756 04:46:04.485012 Set Vref, RX VrefLevel [Byte0]: 38
2757 04:46:04.487474 [Byte1]: 38
2758 04:46:04.492739
2759 04:46:04.493261 Set Vref, RX VrefLevel [Byte0]: 39
2760 04:46:04.496629 [Byte1]: 39
2761 04:46:04.500700
2762 04:46:04.501247 Set Vref, RX VrefLevel [Byte0]: 40
2763 04:46:04.503830 [Byte1]: 40
2764 04:46:04.508432
2765 04:46:04.508962 Set Vref, RX VrefLevel [Byte0]: 41
2766 04:46:04.511735 [Byte1]: 41
2767 04:46:04.516991
2768 04:46:04.517516 Set Vref, RX VrefLevel [Byte0]: 42
2769 04:46:04.519898 [Byte1]: 42
2770 04:46:04.524341
2771 04:46:04.524761 Set Vref, RX VrefLevel [Byte0]: 43
2772 04:46:04.527865 [Byte1]: 43
2773 04:46:04.532598
2774 04:46:04.533117 Set Vref, RX VrefLevel [Byte0]: 44
2775 04:46:04.535340 [Byte1]: 44
2776 04:46:04.540231
2777 04:46:04.540683 Set Vref, RX VrefLevel [Byte0]: 45
2778 04:46:04.543260 [Byte1]: 45
2779 04:46:04.548276
2780 04:46:04.548692 Set Vref, RX VrefLevel [Byte0]: 46
2781 04:46:04.551162 [Byte1]: 46
2782 04:46:04.555903
2783 04:46:04.556590 Set Vref, RX VrefLevel [Byte0]: 47
2784 04:46:04.559113 [Byte1]: 47
2785 04:46:04.563978
2786 04:46:04.564510 Set Vref, RX VrefLevel [Byte0]: 48
2787 04:46:04.567173 [Byte1]: 48
2788 04:46:04.571946
2789 04:46:04.572472 Set Vref, RX VrefLevel [Byte0]: 49
2790 04:46:04.574940 [Byte1]: 49
2791 04:46:04.580563
2792 04:46:04.581084 Set Vref, RX VrefLevel [Byte0]: 50
2793 04:46:04.582947 [Byte1]: 50
2794 04:46:04.588265
2795 04:46:04.588793 Set Vref, RX VrefLevel [Byte0]: 51
2796 04:46:04.590684 [Byte1]: 51
2797 04:46:04.595319
2798 04:46:04.595768 Set Vref, RX VrefLevel [Byte0]: 52
2799 04:46:04.598498 [Byte1]: 52
2800 04:46:04.603871
2801 04:46:04.604390 Set Vref, RX VrefLevel [Byte0]: 53
2802 04:46:04.606860 [Byte1]: 53
2803 04:46:04.612042
2804 04:46:04.612578 Set Vref, RX VrefLevel [Byte0]: 54
2805 04:46:04.614804 [Byte1]: 54
2806 04:46:04.619420
2807 04:46:04.619942 Set Vref, RX VrefLevel [Byte0]: 55
2808 04:46:04.622596 [Byte1]: 55
2809 04:46:04.627508
2810 04:46:04.628029 Set Vref, RX VrefLevel [Byte0]: 56
2811 04:46:04.630634 [Byte1]: 56
2812 04:46:04.635516
2813 04:46:04.636060 Set Vref, RX VrefLevel [Byte0]: 57
2814 04:46:04.638182 [Byte1]: 57
2815 04:46:04.643047
2816 04:46:04.643616 Set Vref, RX VrefLevel [Byte0]: 58
2817 04:46:04.646314 [Byte1]: 58
2818 04:46:04.651073
2819 04:46:04.651657 Set Vref, RX VrefLevel [Byte0]: 59
2820 04:46:04.654162 [Byte1]: 59
2821 04:46:04.658977
2822 04:46:04.659530 Set Vref, RX VrefLevel [Byte0]: 60
2823 04:46:04.661951 [Byte1]: 60
2824 04:46:04.667011
2825 04:46:04.667462 Set Vref, RX VrefLevel [Byte0]: 61
2826 04:46:04.669813 [Byte1]: 61
2827 04:46:04.674692
2828 04:46:04.675217 Set Vref, RX VrefLevel [Byte0]: 62
2829 04:46:04.678165 [Byte1]: 62
2830 04:46:04.682541
2831 04:46:04.682958 Set Vref, RX VrefLevel [Byte0]: 63
2832 04:46:04.685666 [Byte1]: 63
2833 04:46:04.690269
2834 04:46:04.690685 Set Vref, RX VrefLevel [Byte0]: 64
2835 04:46:04.693910 [Byte1]: 64
2836 04:46:04.698547
2837 04:46:04.699240 Set Vref, RX VrefLevel [Byte0]: 65
2838 04:46:04.701845 [Byte1]: 65
2839 04:46:04.706184
2840 04:46:04.706603 Set Vref, RX VrefLevel [Byte0]: 66
2841 04:46:04.709561 [Byte1]: 66
2842 04:46:04.714540
2843 04:46:04.715060 Set Vref, RX VrefLevel [Byte0]: 67
2844 04:46:04.717836 [Byte1]: 67
2845 04:46:04.722703
2846 04:46:04.723120 Set Vref, RX VrefLevel [Byte0]: 68
2847 04:46:04.725532 [Byte1]: 68
2848 04:46:04.729875
2849 04:46:04.730295 Final RX Vref Byte 0 = 57 to rank0
2850 04:46:04.733631 Final RX Vref Byte 1 = 49 to rank0
2851 04:46:04.736937 Final RX Vref Byte 0 = 57 to rank1
2852 04:46:04.740270 Final RX Vref Byte 1 = 49 to rank1==
2853 04:46:04.743248 Dram Type= 6, Freq= 0, CH_0, rank 0
2854 04:46:04.750408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 04:46:04.750962 ==
2856 04:46:04.751307 DQS Delay:
2857 04:46:04.751686 DQS0 = 0, DQS1 = 0
2858 04:46:04.753187 DQM Delay:
2859 04:46:04.753661 DQM0 = 119, DQM1 = 105
2860 04:46:04.756303 DQ Delay:
2861 04:46:04.760259 DQ0 =118, DQ1 =118, DQ2 =116, DQ3 =114
2862 04:46:04.763530 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =122
2863 04:46:04.766261 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =100
2864 04:46:04.770074 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =114
2865 04:46:04.770602
2866 04:46:04.770936
2867 04:46:04.779581 [DQSOSCAuto] RK0, (LSB)MR18= 0x400, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2868 04:46:04.780111 CH0 RK0: MR19=404, MR18=400
2869 04:46:04.786542 CH0_RK0: MR19=0x404, MR18=0x400, DQSOSC=408, MR23=63, INC=39, DEC=26
2870 04:46:04.787082
2871 04:46:04.790335 ----->DramcWriteLeveling(PI) begin...
2872 04:46:04.790880 ==
2873 04:46:04.793377 Dram Type= 6, Freq= 0, CH_0, rank 1
2874 04:46:04.799475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2875 04:46:04.800000 ==
2876 04:46:04.802794 Write leveling (Byte 0): 32 => 32
2877 04:46:04.803215 Write leveling (Byte 1): 26 => 26
2878 04:46:04.806118 DramcWriteLeveling(PI) end<-----
2879 04:46:04.806644
2880 04:46:04.806979 ==
2881 04:46:04.809560 Dram Type= 6, Freq= 0, CH_0, rank 1
2882 04:46:04.816284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2883 04:46:04.816809 ==
2884 04:46:04.819504 [Gating] SW mode calibration
2885 04:46:04.826361 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2886 04:46:04.829454 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2887 04:46:04.836251 0 15 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2888 04:46:04.839116 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2889 04:46:04.842335 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2890 04:46:04.849246 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 04:46:04.852838 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 04:46:04.856263 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 04:46:04.862708 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2894 04:46:04.865918 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
2895 04:46:04.869132 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
2896 04:46:04.875626 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 04:46:04.878987 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 04:46:04.882859 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 04:46:04.889037 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 04:46:04.892175 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 04:46:04.895401 1 0 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
2902 04:46:04.901990 1 0 28 | B1->B0 | 2a2a 4545 | 0 0 | (0 0) (0 0)
2903 04:46:04.905681 1 1 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2904 04:46:04.908779 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 04:46:04.912068 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 04:46:04.919113 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 04:46:04.922589 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 04:46:04.925623 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 04:46:04.932557 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2910 04:46:04.936050 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2911 04:46:04.938711 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2912 04:46:04.945829 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 04:46:04.948812 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 04:46:04.952012 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 04:46:04.958806 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 04:46:04.962343 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 04:46:04.965572 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 04:46:04.971679 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 04:46:04.975292 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 04:46:04.978881 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 04:46:04.985042 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 04:46:04.988340 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 04:46:04.991791 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 04:46:04.998702 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 04:46:05.001964 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2926 04:46:05.005083 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2927 04:46:05.008302 Total UI for P1: 0, mck2ui 16
2928 04:46:05.011915 best dqsien dly found for B0: ( 1, 3, 24)
2929 04:46:05.018295 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2930 04:46:05.022124 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 04:46:05.025185 Total UI for P1: 0, mck2ui 16
2932 04:46:05.028138 best dqsien dly found for B1: ( 1, 3, 30)
2933 04:46:05.031769 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2934 04:46:05.035214 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2935 04:46:05.035778
2936 04:46:05.038324 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2937 04:46:05.041832 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2938 04:46:05.044581 [Gating] SW calibration Done
2939 04:46:05.045053 ==
2940 04:46:05.047828 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 04:46:05.051578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 04:46:05.054888 ==
2943 04:46:05.055311 RX Vref Scan: 0
2944 04:46:05.055680
2945 04:46:05.058594 RX Vref 0 -> 0, step: 1
2946 04:46:05.059151
2947 04:46:05.061464 RX Delay -40 -> 252, step: 8
2948 04:46:05.064606 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2949 04:46:05.067517 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2950 04:46:05.071556 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2951 04:46:05.074467 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2952 04:46:05.081086 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2953 04:46:05.084458 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2954 04:46:05.087670 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2955 04:46:05.091462 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2956 04:46:05.094601 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2957 04:46:05.101110 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2958 04:46:05.104600 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2959 04:46:05.107644 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2960 04:46:05.111056 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2961 04:46:05.114496 iDelay=200, Bit 13, Center 107 (40 ~ 175) 136
2962 04:46:05.121578 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2963 04:46:05.124074 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2964 04:46:05.124608 ==
2965 04:46:05.127661 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 04:46:05.130738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 04:46:05.131267 ==
2968 04:46:05.134734 DQS Delay:
2969 04:46:05.135260 DQS0 = 0, DQS1 = 0
2970 04:46:05.135758 DQM Delay:
2971 04:46:05.137634 DQM0 = 119, DQM1 = 105
2972 04:46:05.138056 DQ Delay:
2973 04:46:05.141092 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2974 04:46:05.144183 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2975 04:46:05.147627 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =95
2976 04:46:05.153872 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =115
2977 04:46:05.154473
2978 04:46:05.154816
2979 04:46:05.155154 ==
2980 04:46:05.157160 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 04:46:05.160652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 04:46:05.161186 ==
2983 04:46:05.161633
2984 04:46:05.161962
2985 04:46:05.163942 TX Vref Scan disable
2986 04:46:05.164364 == TX Byte 0 ==
2987 04:46:05.171036 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2988 04:46:05.174586 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2989 04:46:05.175117 == TX Byte 1 ==
2990 04:46:05.180553 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2991 04:46:05.183767 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2992 04:46:05.184196 ==
2993 04:46:05.187353 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 04:46:05.191086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 04:46:05.191687 ==
2996 04:46:05.204086 TX Vref=22, minBit 4, minWin=25, winSum=415
2997 04:46:05.207140 TX Vref=24, minBit 1, minWin=25, winSum=416
2998 04:46:05.210641 TX Vref=26, minBit 13, minWin=25, winSum=425
2999 04:46:05.213940 TX Vref=28, minBit 4, minWin=26, winSum=428
3000 04:46:05.217241 TX Vref=30, minBit 4, minWin=26, winSum=428
3001 04:46:05.223558 TX Vref=32, minBit 4, minWin=26, winSum=425
3002 04:46:05.227549 [TxChooseVref] Worse bit 4, Min win 26, Win sum 428, Final Vref 28
3003 04:46:05.228110
3004 04:46:05.230371 Final TX Range 1 Vref 28
3005 04:46:05.230932
3006 04:46:05.231302 ==
3007 04:46:05.233281 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 04:46:05.236925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 04:46:05.237492 ==
3010 04:46:05.240341
3011 04:46:05.240896
3012 04:46:05.241258 TX Vref Scan disable
3013 04:46:05.243681 == TX Byte 0 ==
3014 04:46:05.246828 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3015 04:46:05.253932 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3016 04:46:05.254469 == TX Byte 1 ==
3017 04:46:05.257171 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3018 04:46:05.263548 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3019 04:46:05.264063
3020 04:46:05.264413 [DATLAT]
3021 04:46:05.264753 Freq=1200, CH0 RK1
3022 04:46:05.265076
3023 04:46:05.267148 DATLAT Default: 0xd
3024 04:46:05.267771 0, 0xFFFF, sum = 0
3025 04:46:05.269734 1, 0xFFFF, sum = 0
3026 04:46:05.273356 2, 0xFFFF, sum = 0
3027 04:46:05.273789 3, 0xFFFF, sum = 0
3028 04:46:05.276987 4, 0xFFFF, sum = 0
3029 04:46:05.277417 5, 0xFFFF, sum = 0
3030 04:46:05.279607 6, 0xFFFF, sum = 0
3031 04:46:05.280051 7, 0xFFFF, sum = 0
3032 04:46:05.283051 8, 0xFFFF, sum = 0
3033 04:46:05.283631 9, 0xFFFF, sum = 0
3034 04:46:05.286085 10, 0xFFFF, sum = 0
3035 04:46:05.286570 11, 0xFFFF, sum = 0
3036 04:46:05.289924 12, 0x0, sum = 1
3037 04:46:05.290451 13, 0x0, sum = 2
3038 04:46:05.292875 14, 0x0, sum = 3
3039 04:46:05.293302 15, 0x0, sum = 4
3040 04:46:05.296509 best_step = 13
3041 04:46:05.296930
3042 04:46:05.297262 ==
3043 04:46:05.299657 Dram Type= 6, Freq= 0, CH_0, rank 1
3044 04:46:05.303049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 04:46:05.303653 ==
3046 04:46:05.304048 RX Vref Scan: 0
3047 04:46:05.306632
3048 04:46:05.307152 RX Vref 0 -> 0, step: 1
3049 04:46:05.307536
3050 04:46:05.309757 RX Delay -21 -> 252, step: 4
3051 04:46:05.316115 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3052 04:46:05.319582 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3053 04:46:05.323410 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3054 04:46:05.325893 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3055 04:46:05.329485 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3056 04:46:05.336120 iDelay=195, Bit 5, Center 112 (47 ~ 178) 132
3057 04:46:05.339662 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3058 04:46:05.342930 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3059 04:46:05.346360 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3060 04:46:05.350108 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3061 04:46:05.352970 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3062 04:46:05.359575 iDelay=195, Bit 11, Center 98 (35 ~ 162) 128
3063 04:46:05.362684 iDelay=195, Bit 12, Center 110 (47 ~ 174) 128
3064 04:46:05.366177 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3065 04:46:05.369875 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3066 04:46:05.376466 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3067 04:46:05.377044 ==
3068 04:46:05.379092 Dram Type= 6, Freq= 0, CH_0, rank 1
3069 04:46:05.382623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 04:46:05.383329 ==
3071 04:46:05.383766 DQS Delay:
3072 04:46:05.385823 DQS0 = 0, DQS1 = 0
3073 04:46:05.386236 DQM Delay:
3074 04:46:05.389125 DQM0 = 117, DQM1 = 105
3075 04:46:05.389624 DQ Delay:
3076 04:46:05.392334 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =114
3077 04:46:05.395611 DQ4 =120, DQ5 =112, DQ6 =128, DQ7 =122
3078 04:46:05.399014 DQ8 =94, DQ9 =94, DQ10 =108, DQ11 =98
3079 04:46:05.402452 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =114
3080 04:46:05.402970
3081 04:46:05.403403
3082 04:46:05.412889 [DQSOSCAuto] RK1, (LSB)MR18= 0xfe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
3083 04:46:05.413439 CH0 RK1: MR19=403, MR18=FE
3084 04:46:05.419496 CH0_RK1: MR19=0x403, MR18=0xFE, DQSOSC=410, MR23=63, INC=39, DEC=26
3085 04:46:05.422750 [RxdqsGatingPostProcess] freq 1200
3086 04:46:05.428865 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3087 04:46:05.433153 best DQS0 dly(2T, 0.5T) = (0, 11)
3088 04:46:05.435647 best DQS1 dly(2T, 0.5T) = (0, 12)
3089 04:46:05.439665 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3090 04:46:05.442392 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3091 04:46:05.442952 best DQS0 dly(2T, 0.5T) = (0, 11)
3092 04:46:05.445515 best DQS1 dly(2T, 0.5T) = (0, 11)
3093 04:46:05.448756 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3094 04:46:05.452233 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3095 04:46:05.455626 Pre-setting of DQS Precalculation
3096 04:46:05.462737 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3097 04:46:05.463436 ==
3098 04:46:05.465818 Dram Type= 6, Freq= 0, CH_1, rank 0
3099 04:46:05.468780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 04:46:05.469247 ==
3101 04:46:05.475584 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3102 04:46:05.482772 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3103 04:46:05.489330 [CA 0] Center 38 (8~68) winsize 61
3104 04:46:05.492601 [CA 1] Center 37 (7~68) winsize 62
3105 04:46:05.496250 [CA 2] Center 35 (5~65) winsize 61
3106 04:46:05.498771 [CA 3] Center 34 (4~64) winsize 61
3107 04:46:05.502577 [CA 4] Center 34 (4~65) winsize 62
3108 04:46:05.506203 [CA 5] Center 33 (3~63) winsize 61
3109 04:46:05.506717
3110 04:46:05.508986 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3111 04:46:05.509402
3112 04:46:05.512036 [CATrainingPosCal] consider 1 rank data
3113 04:46:05.515814 u2DelayCellTimex100 = 270/100 ps
3114 04:46:05.519140 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3115 04:46:05.525603 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3116 04:46:05.529151 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3117 04:46:05.532209 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3118 04:46:05.535305 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3119 04:46:05.538926 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3120 04:46:05.539487
3121 04:46:05.542543 CA PerBit enable=1, Macro0, CA PI delay=33
3122 04:46:05.542958
3123 04:46:05.545601 [CBTSetCACLKResult] CA Dly = 33
3124 04:46:05.546013 CS Dly: 5 (0~36)
3125 04:46:05.548516 ==
3126 04:46:05.552574 Dram Type= 6, Freq= 0, CH_1, rank 1
3127 04:46:05.555321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 04:46:05.555896 ==
3129 04:46:05.558847 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3130 04:46:05.565554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3131 04:46:05.574716 [CA 0] Center 37 (7~68) winsize 62
3132 04:46:05.578489 [CA 1] Center 38 (8~68) winsize 61
3133 04:46:05.581681 [CA 2] Center 34 (4~65) winsize 62
3134 04:46:05.584777 [CA 3] Center 33 (3~64) winsize 62
3135 04:46:05.588194 [CA 4] Center 34 (4~64) winsize 61
3136 04:46:05.591321 [CA 5] Center 33 (3~64) winsize 62
3137 04:46:05.591787
3138 04:46:05.594668 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3139 04:46:05.595085
3140 04:46:05.598384 [CATrainingPosCal] consider 2 rank data
3141 04:46:05.601532 u2DelayCellTimex100 = 270/100 ps
3142 04:46:05.604298 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3143 04:46:05.611300 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3144 04:46:05.614401 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3145 04:46:05.617802 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3146 04:46:05.620861 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3147 04:46:05.624029 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3148 04:46:05.624445
3149 04:46:05.627559 CA PerBit enable=1, Macro0, CA PI delay=33
3150 04:46:05.627976
3151 04:46:05.631235 [CBTSetCACLKResult] CA Dly = 33
3152 04:46:05.634575 CS Dly: 6 (0~39)
3153 04:46:05.635084
3154 04:46:05.637828 ----->DramcWriteLeveling(PI) begin...
3155 04:46:05.638251 ==
3156 04:46:05.641248 Dram Type= 6, Freq= 0, CH_1, rank 0
3157 04:46:05.644823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3158 04:46:05.645264 ==
3159 04:46:05.647677 Write leveling (Byte 0): 27 => 27
3160 04:46:05.651469 Write leveling (Byte 1): 27 => 27
3161 04:46:05.654564 DramcWriteLeveling(PI) end<-----
3162 04:46:05.655036
3163 04:46:05.655448 ==
3164 04:46:05.657202 Dram Type= 6, Freq= 0, CH_1, rank 0
3165 04:46:05.660756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3166 04:46:05.661211 ==
3167 04:46:05.664059 [Gating] SW mode calibration
3168 04:46:05.670819 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3169 04:46:05.677783 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3170 04:46:05.680828 0 15 0 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
3171 04:46:05.683917 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 04:46:05.690528 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 04:46:05.693969 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 04:46:05.697537 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 04:46:05.703837 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 04:46:05.707457 0 15 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
3177 04:46:05.710777 0 15 28 | B1->B0 | 2c2c 2525 | 1 1 | (1 0) (1 0)
3178 04:46:05.717309 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 04:46:05.721119 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 04:46:05.723892 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 04:46:05.730463 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 04:46:05.734276 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 04:46:05.737128 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 04:46:05.743442 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
3185 04:46:05.746993 1 0 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3186 04:46:05.750187 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 04:46:05.757097 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 04:46:05.760283 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 04:46:05.763826 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 04:46:05.767268 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 04:46:05.773434 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 04:46:05.776938 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 04:46:05.780293 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3194 04:46:05.786426 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 04:46:05.789667 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 04:46:05.793753 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 04:46:05.800106 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 04:46:05.803023 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 04:46:05.806231 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 04:46:05.813308 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 04:46:05.816398 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 04:46:05.819856 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 04:46:05.826358 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 04:46:05.829751 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 04:46:05.833019 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 04:46:05.839781 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 04:46:05.843434 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 04:46:05.846022 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3209 04:46:05.853007 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3210 04:46:05.856783 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 04:46:05.859473 Total UI for P1: 0, mck2ui 16
3212 04:46:05.863141 best dqsien dly found for B0: ( 1, 3, 26)
3213 04:46:05.866307 Total UI for P1: 0, mck2ui 16
3214 04:46:05.869784 best dqsien dly found for B1: ( 1, 3, 26)
3215 04:46:05.872719 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3216 04:46:05.876736 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3217 04:46:05.877262
3218 04:46:05.879957 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3219 04:46:05.882936 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3220 04:46:05.886364 [Gating] SW calibration Done
3221 04:46:05.886886 ==
3222 04:46:05.889627 Dram Type= 6, Freq= 0, CH_1, rank 0
3223 04:46:05.895885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3224 04:46:05.896430 ==
3225 04:46:05.896773 RX Vref Scan: 0
3226 04:46:05.897082
3227 04:46:05.899404 RX Vref 0 -> 0, step: 1
3228 04:46:05.899892
3229 04:46:05.902784 RX Delay -40 -> 252, step: 8
3230 04:46:05.906238 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3231 04:46:05.909459 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3232 04:46:05.912529 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3233 04:46:05.916092 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3234 04:46:05.922371 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3235 04:46:05.926482 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3236 04:46:05.929003 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3237 04:46:05.932351 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3238 04:46:05.935814 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3239 04:46:05.942363 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3240 04:46:05.945606 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3241 04:46:05.949261 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3242 04:46:05.952166 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3243 04:46:05.955728 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3244 04:46:05.962401 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3245 04:46:05.966107 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3246 04:46:05.966633 ==
3247 04:46:05.969468 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 04:46:05.972197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 04:46:05.972620 ==
3250 04:46:05.975288 DQS Delay:
3251 04:46:05.975874 DQS0 = 0, DQS1 = 0
3252 04:46:05.976218 DQM Delay:
3253 04:46:05.978892 DQM0 = 117, DQM1 = 113
3254 04:46:05.979305 DQ Delay:
3255 04:46:05.982254 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3256 04:46:05.986030 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3257 04:46:05.992137 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3258 04:46:05.995579 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3259 04:46:05.996000
3260 04:46:05.996330
3261 04:46:05.996637 ==
3262 04:46:05.998653 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 04:46:06.002300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 04:46:06.002827 ==
3265 04:46:06.003163
3266 04:46:06.003526
3267 04:46:06.005404 TX Vref Scan disable
3268 04:46:06.009170 == TX Byte 0 ==
3269 04:46:06.012201 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3270 04:46:06.015607 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3271 04:46:06.016133 == TX Byte 1 ==
3272 04:46:06.021978 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3273 04:46:06.025707 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3274 04:46:06.026227 ==
3275 04:46:06.028923 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 04:46:06.032125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 04:46:06.032554 ==
3278 04:46:06.045094 TX Vref=22, minBit 0, minWin=25, winSum=408
3279 04:46:06.047734 TX Vref=24, minBit 9, minWin=24, winSum=414
3280 04:46:06.051172 TX Vref=26, minBit 7, minWin=25, winSum=421
3281 04:46:06.054776 TX Vref=28, minBit 1, minWin=26, winSum=426
3282 04:46:06.058520 TX Vref=30, minBit 2, minWin=26, winSum=429
3283 04:46:06.065143 TX Vref=32, minBit 0, minWin=26, winSum=428
3284 04:46:06.068471 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 30
3285 04:46:06.069032
3286 04:46:06.071060 Final TX Range 1 Vref 30
3287 04:46:06.071523
3288 04:46:06.071861 ==
3289 04:46:06.074770 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 04:46:06.077989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 04:46:06.078517 ==
3292 04:46:06.081112
3293 04:46:06.081633
3294 04:46:06.081965 TX Vref Scan disable
3295 04:46:06.084637 == TX Byte 0 ==
3296 04:46:06.087614 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3297 04:46:06.094630 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3298 04:46:06.095168 == TX Byte 1 ==
3299 04:46:06.097717 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3300 04:46:06.104464 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3301 04:46:06.104995
3302 04:46:06.105373 [DATLAT]
3303 04:46:06.105693 Freq=1200, CH1 RK0
3304 04:46:06.105996
3305 04:46:06.107634 DATLAT Default: 0xd
3306 04:46:06.108052 0, 0xFFFF, sum = 0
3307 04:46:06.111117 1, 0xFFFF, sum = 0
3308 04:46:06.114447 2, 0xFFFF, sum = 0
3309 04:46:06.114852 3, 0xFFFF, sum = 0
3310 04:46:06.118216 4, 0xFFFF, sum = 0
3311 04:46:06.118746 5, 0xFFFF, sum = 0
3312 04:46:06.121093 6, 0xFFFF, sum = 0
3313 04:46:06.121625 7, 0xFFFF, sum = 0
3314 04:46:06.124378 8, 0xFFFF, sum = 0
3315 04:46:06.124905 9, 0xFFFF, sum = 0
3316 04:46:06.127945 10, 0xFFFF, sum = 0
3317 04:46:06.128476 11, 0xFFFF, sum = 0
3318 04:46:06.130609 12, 0x0, sum = 1
3319 04:46:06.131035 13, 0x0, sum = 2
3320 04:46:06.134321 14, 0x0, sum = 3
3321 04:46:06.134851 15, 0x0, sum = 4
3322 04:46:06.137805 best_step = 13
3323 04:46:06.138327
3324 04:46:06.138664 ==
3325 04:46:06.141380 Dram Type= 6, Freq= 0, CH_1, rank 0
3326 04:46:06.144145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3327 04:46:06.144572 ==
3328 04:46:06.144916 RX Vref Scan: 1
3329 04:46:06.145232
3330 04:46:06.147847 Set Vref Range= 32 -> 127
3331 04:46:06.148266
3332 04:46:06.150924 RX Vref 32 -> 127, step: 1
3333 04:46:06.151340
3334 04:46:06.154234 RX Delay -13 -> 252, step: 4
3335 04:46:06.154756
3336 04:46:06.157637 Set Vref, RX VrefLevel [Byte0]: 32
3337 04:46:06.160654 [Byte1]: 32
3338 04:46:06.161076
3339 04:46:06.164091 Set Vref, RX VrefLevel [Byte0]: 33
3340 04:46:06.167189 [Byte1]: 33
3341 04:46:06.170937
3342 04:46:06.171498 Set Vref, RX VrefLevel [Byte0]: 34
3343 04:46:06.174282 [Byte1]: 34
3344 04:46:06.179101
3345 04:46:06.179667 Set Vref, RX VrefLevel [Byte0]: 35
3346 04:46:06.183112 [Byte1]: 35
3347 04:46:06.186588
3348 04:46:06.187108 Set Vref, RX VrefLevel [Byte0]: 36
3349 04:46:06.189801 [Byte1]: 36
3350 04:46:06.194363
3351 04:46:06.194883 Set Vref, RX VrefLevel [Byte0]: 37
3352 04:46:06.197530 [Byte1]: 37
3353 04:46:06.202612
3354 04:46:06.203138 Set Vref, RX VrefLevel [Byte0]: 38
3355 04:46:06.205775 [Byte1]: 38
3356 04:46:06.210352
3357 04:46:06.210875 Set Vref, RX VrefLevel [Byte0]: 39
3358 04:46:06.213616 [Byte1]: 39
3359 04:46:06.217927
3360 04:46:06.218340 Set Vref, RX VrefLevel [Byte0]: 40
3361 04:46:06.221271 [Byte1]: 40
3362 04:46:06.226188
3363 04:46:06.226597 Set Vref, RX VrefLevel [Byte0]: 41
3364 04:46:06.229216 [Byte1]: 41
3365 04:46:06.233953
3366 04:46:06.234364 Set Vref, RX VrefLevel [Byte0]: 42
3367 04:46:06.237504 [Byte1]: 42
3368 04:46:06.242109
3369 04:46:06.242626 Set Vref, RX VrefLevel [Byte0]: 43
3370 04:46:06.245079 [Byte1]: 43
3371 04:46:06.249741
3372 04:46:06.250150 Set Vref, RX VrefLevel [Byte0]: 44
3373 04:46:06.253344 [Byte1]: 44
3374 04:46:06.257500
3375 04:46:06.258053 Set Vref, RX VrefLevel [Byte0]: 45
3376 04:46:06.260973 [Byte1]: 45
3377 04:46:06.265635
3378 04:46:06.266152 Set Vref, RX VrefLevel [Byte0]: 46
3379 04:46:06.268799 [Byte1]: 46
3380 04:46:06.273793
3381 04:46:06.274203 Set Vref, RX VrefLevel [Byte0]: 47
3382 04:46:06.276496 [Byte1]: 47
3383 04:46:06.281227
3384 04:46:06.281640 Set Vref, RX VrefLevel [Byte0]: 48
3385 04:46:06.284967 [Byte1]: 48
3386 04:46:06.288905
3387 04:46:06.289317 Set Vref, RX VrefLevel [Byte0]: 49
3388 04:46:06.292525 [Byte1]: 49
3389 04:46:06.297362
3390 04:46:06.297876 Set Vref, RX VrefLevel [Byte0]: 50
3391 04:46:06.300068 [Byte1]: 50
3392 04:46:06.304704
3393 04:46:06.305215 Set Vref, RX VrefLevel [Byte0]: 51
3394 04:46:06.308519 [Byte1]: 51
3395 04:46:06.313047
3396 04:46:06.313557 Set Vref, RX VrefLevel [Byte0]: 52
3397 04:46:06.315779 [Byte1]: 52
3398 04:46:06.321093
3399 04:46:06.321681 Set Vref, RX VrefLevel [Byte0]: 53
3400 04:46:06.323784 [Byte1]: 53
3401 04:46:06.328572
3402 04:46:06.328982 Set Vref, RX VrefLevel [Byte0]: 54
3403 04:46:06.331906 [Byte1]: 54
3404 04:46:06.336432
3405 04:46:06.337016 Set Vref, RX VrefLevel [Byte0]: 55
3406 04:46:06.339461 [Byte1]: 55
3407 04:46:06.344357
3408 04:46:06.344784 Set Vref, RX VrefLevel [Byte0]: 56
3409 04:46:06.347413 [Byte1]: 56
3410 04:46:06.352336
3411 04:46:06.352784 Set Vref, RX VrefLevel [Byte0]: 57
3412 04:46:06.355279 [Byte1]: 57
3413 04:46:06.360049
3414 04:46:06.360456 Set Vref, RX VrefLevel [Byte0]: 58
3415 04:46:06.363266 [Byte1]: 58
3416 04:46:06.367595
3417 04:46:06.368008 Set Vref, RX VrefLevel [Byte0]: 59
3418 04:46:06.371829 [Byte1]: 59
3419 04:46:06.375644
3420 04:46:06.376072 Set Vref, RX VrefLevel [Byte0]: 60
3421 04:46:06.379201 [Byte1]: 60
3422 04:46:06.383976
3423 04:46:06.384485 Set Vref, RX VrefLevel [Byte0]: 61
3424 04:46:06.386930 [Byte1]: 61
3425 04:46:06.391514
3426 04:46:06.392028 Set Vref, RX VrefLevel [Byte0]: 62
3427 04:46:06.394961 [Byte1]: 62
3428 04:46:06.399822
3429 04:46:06.400331 Set Vref, RX VrefLevel [Byte0]: 63
3430 04:46:06.402568 [Byte1]: 63
3431 04:46:06.407430
3432 04:46:06.407939 Set Vref, RX VrefLevel [Byte0]: 64
3433 04:46:06.410669 [Byte1]: 64
3434 04:46:06.415529
3435 04:46:06.416039 Set Vref, RX VrefLevel [Byte0]: 65
3436 04:46:06.418496 [Byte1]: 65
3437 04:46:06.423313
3438 04:46:06.423872 Final RX Vref Byte 0 = 54 to rank0
3439 04:46:06.426607 Final RX Vref Byte 1 = 54 to rank0
3440 04:46:06.429636 Final RX Vref Byte 0 = 54 to rank1
3441 04:46:06.433053 Final RX Vref Byte 1 = 54 to rank1==
3442 04:46:06.436746 Dram Type= 6, Freq= 0, CH_1, rank 0
3443 04:46:06.443341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3444 04:46:06.443903 ==
3445 04:46:06.444269 DQS Delay:
3446 04:46:06.444721 DQS0 = 0, DQS1 = 0
3447 04:46:06.446190 DQM Delay:
3448 04:46:06.446602 DQM0 = 116, DQM1 = 114
3449 04:46:06.449835 DQ Delay:
3450 04:46:06.452733 DQ0 =122, DQ1 =112, DQ2 =106, DQ3 =118
3451 04:46:06.456330 DQ4 =112, DQ5 =124, DQ6 =126, DQ7 =112
3452 04:46:06.460290 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =108
3453 04:46:06.463131 DQ12 =124, DQ13 =122, DQ14 =122, DQ15 =124
3454 04:46:06.463702
3455 04:46:06.464099
3456 04:46:06.473444 [DQSOSCAuto] RK0, (LSB)MR18= 0xf3ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3457 04:46:06.473989 CH1 RK0: MR19=303, MR18=F3FF
3458 04:46:06.479759 CH1_RK0: MR19=0x303, MR18=0xF3FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3459 04:46:06.480281
3460 04:46:06.482843 ----->DramcWriteLeveling(PI) begin...
3461 04:46:06.483390 ==
3462 04:46:06.485935 Dram Type= 6, Freq= 0, CH_1, rank 1
3463 04:46:06.492842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3464 04:46:06.493366 ==
3465 04:46:06.495746 Write leveling (Byte 0): 25 => 25
3466 04:46:06.496161 Write leveling (Byte 1): 28 => 28
3467 04:46:06.499460 DramcWriteLeveling(PI) end<-----
3468 04:46:06.499978
3469 04:46:06.502405 ==
3470 04:46:06.502821 Dram Type= 6, Freq= 0, CH_1, rank 1
3471 04:46:06.509542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3472 04:46:06.510066 ==
3473 04:46:06.512984 [Gating] SW mode calibration
3474 04:46:06.519808 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3475 04:46:06.522852 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3476 04:46:06.529444 0 15 0 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
3477 04:46:06.532344 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 04:46:06.536022 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 04:46:06.542671 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3480 04:46:06.545828 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 04:46:06.549026 0 15 20 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
3482 04:46:06.555537 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
3483 04:46:06.559125 0 15 28 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
3484 04:46:06.562701 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 04:46:06.569142 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 04:46:06.572256 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 04:46:06.575682 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 04:46:06.582177 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3489 04:46:06.585912 1 0 20 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
3490 04:46:06.588941 1 0 24 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
3491 04:46:06.595563 1 0 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3492 04:46:06.598968 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 04:46:06.602275 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 04:46:06.608900 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 04:46:06.612107 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 04:46:06.615430 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 04:46:06.622514 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 04:46:06.625344 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 04:46:06.628595 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3500 04:46:06.631752 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 04:46:06.638584 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 04:46:06.642002 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 04:46:06.645092 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 04:46:06.651545 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 04:46:06.654749 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 04:46:06.658250 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 04:46:06.665067 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 04:46:06.668633 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 04:46:06.671493 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 04:46:06.678217 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 04:46:06.681670 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 04:46:06.684517 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 04:46:06.691350 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3514 04:46:06.694865 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3515 04:46:06.697894 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3516 04:46:06.700870 Total UI for P1: 0, mck2ui 16
3517 04:46:06.704159 best dqsien dly found for B0: ( 1, 3, 22)
3518 04:46:06.711087 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 04:46:06.714270 Total UI for P1: 0, mck2ui 16
3520 04:46:06.718154 best dqsien dly found for B1: ( 1, 3, 28)
3521 04:46:06.720746 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3522 04:46:06.724279 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3523 04:46:06.724795
3524 04:46:06.727665 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3525 04:46:06.730683 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3526 04:46:06.734239 [Gating] SW calibration Done
3527 04:46:06.734755 ==
3528 04:46:06.737469 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 04:46:06.740871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 04:46:06.741391 ==
3531 04:46:06.744420 RX Vref Scan: 0
3532 04:46:06.744937
3533 04:46:06.747643 RX Vref 0 -> 0, step: 1
3534 04:46:06.748056
3535 04:46:06.748384 RX Delay -40 -> 252, step: 8
3536 04:46:06.753965 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3537 04:46:06.757553 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3538 04:46:06.760155 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3539 04:46:06.763445 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3540 04:46:06.770358 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3541 04:46:06.773624 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3542 04:46:06.776959 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3543 04:46:06.779807 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3544 04:46:06.783962 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3545 04:46:06.789840 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3546 04:46:06.793317 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3547 04:46:06.796396 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3548 04:46:06.800029 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3549 04:46:06.803089 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3550 04:46:06.809305 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3551 04:46:06.812779 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3552 04:46:06.813194 ==
3553 04:46:06.816316 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 04:46:06.819399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 04:46:06.819925 ==
3556 04:46:06.822984 DQS Delay:
3557 04:46:06.823549 DQS0 = 0, DQS1 = 0
3558 04:46:06.825858 DQM Delay:
3559 04:46:06.826271 DQM0 = 116, DQM1 = 114
3560 04:46:06.826601 DQ Delay:
3561 04:46:06.829182 DQ0 =119, DQ1 =115, DQ2 =103, DQ3 =115
3562 04:46:06.835851 DQ4 =119, DQ5 =127, DQ6 =119, DQ7 =115
3563 04:46:06.839703 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =107
3564 04:46:06.842747 DQ12 =123, DQ13 =123, DQ14 =115, DQ15 =123
3565 04:46:06.843160
3566 04:46:06.843783
3567 04:46:06.844112 ==
3568 04:46:06.845873 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 04:46:06.848820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 04:46:06.849238 ==
3571 04:46:06.849607
3572 04:46:06.849940
3573 04:46:06.852229 TX Vref Scan disable
3574 04:46:06.855471 == TX Byte 0 ==
3575 04:46:06.858734 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3576 04:46:06.862028 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3577 04:46:06.865902 == TX Byte 1 ==
3578 04:46:06.868777 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3579 04:46:06.872449 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3580 04:46:06.872960 ==
3581 04:46:06.875146 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 04:46:06.881803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 04:46:06.882241 ==
3584 04:46:06.892605 TX Vref=22, minBit 1, minWin=25, winSum=419
3585 04:46:06.895834 TX Vref=24, minBit 4, minWin=25, winSum=420
3586 04:46:06.898827 TX Vref=26, minBit 6, minWin=25, winSum=424
3587 04:46:06.902349 TX Vref=28, minBit 0, minWin=26, winSum=429
3588 04:46:06.905765 TX Vref=30, minBit 0, minWin=26, winSum=431
3589 04:46:06.912224 TX Vref=32, minBit 0, minWin=26, winSum=427
3590 04:46:06.915669 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 30
3591 04:46:06.916168
3592 04:46:06.918994 Final TX Range 1 Vref 30
3593 04:46:06.919548
3594 04:46:06.919883 ==
3595 04:46:06.922345 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 04:46:06.925852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 04:46:06.928695 ==
3598 04:46:06.929134
3599 04:46:06.929469
3600 04:46:06.929783 TX Vref Scan disable
3601 04:46:06.932437 == TX Byte 0 ==
3602 04:46:06.935717 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3603 04:46:06.939189 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3604 04:46:06.942693 == TX Byte 1 ==
3605 04:46:06.945855 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3606 04:46:06.949662 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3607 04:46:06.952596
3608 04:46:06.953162 [DATLAT]
3609 04:46:06.953525 Freq=1200, CH1 RK1
3610 04:46:06.953845
3611 04:46:06.955872 DATLAT Default: 0xd
3612 04:46:06.956395 0, 0xFFFF, sum = 0
3613 04:46:06.959188 1, 0xFFFF, sum = 0
3614 04:46:06.962596 2, 0xFFFF, sum = 0
3615 04:46:06.963134 3, 0xFFFF, sum = 0
3616 04:46:06.966152 4, 0xFFFF, sum = 0
3617 04:46:06.966682 5, 0xFFFF, sum = 0
3618 04:46:06.968802 6, 0xFFFF, sum = 0
3619 04:46:06.969349 7, 0xFFFF, sum = 0
3620 04:46:06.971926 8, 0xFFFF, sum = 0
3621 04:46:06.972354 9, 0xFFFF, sum = 0
3622 04:46:06.975592 10, 0xFFFF, sum = 0
3623 04:46:06.976122 11, 0xFFFF, sum = 0
3624 04:46:06.978564 12, 0x0, sum = 1
3625 04:46:06.978996 13, 0x0, sum = 2
3626 04:46:06.982103 14, 0x0, sum = 3
3627 04:46:06.982631 15, 0x0, sum = 4
3628 04:46:06.984970 best_step = 13
3629 04:46:06.985394
3630 04:46:06.985728 ==
3631 04:46:06.988178 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 04:46:06.991492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 04:46:06.991916 ==
3634 04:46:06.992249 RX Vref Scan: 0
3635 04:46:06.994659
3636 04:46:06.995113 RX Vref 0 -> 0, step: 1
3637 04:46:06.995497
3638 04:46:06.998254 RX Delay -13 -> 252, step: 4
3639 04:46:07.005342 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3640 04:46:07.008423 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3641 04:46:07.011636 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3642 04:46:07.014436 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3643 04:46:07.018270 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3644 04:46:07.024609 iDelay=195, Bit 5, Center 126 (59 ~ 194) 136
3645 04:46:07.027979 iDelay=195, Bit 6, Center 124 (59 ~ 190) 132
3646 04:46:07.031285 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3647 04:46:07.034582 iDelay=195, Bit 8, Center 102 (43 ~ 162) 120
3648 04:46:07.037746 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3649 04:46:07.044350 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3650 04:46:07.047502 iDelay=195, Bit 11, Center 108 (47 ~ 170) 124
3651 04:46:07.050823 iDelay=195, Bit 12, Center 122 (63 ~ 182) 120
3652 04:46:07.053798 iDelay=195, Bit 13, Center 124 (63 ~ 186) 124
3653 04:46:07.060929 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3654 04:46:07.064125 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3655 04:46:07.064546 ==
3656 04:46:07.067471 Dram Type= 6, Freq= 0, CH_1, rank 1
3657 04:46:07.071271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3658 04:46:07.071849 ==
3659 04:46:07.074176 DQS Delay:
3660 04:46:07.074700 DQS0 = 0, DQS1 = 0
3661 04:46:07.075033 DQM Delay:
3662 04:46:07.077263 DQM0 = 116, DQM1 = 115
3663 04:46:07.077814 DQ Delay:
3664 04:46:07.080606 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =114
3665 04:46:07.083993 DQ4 =118, DQ5 =126, DQ6 =124, DQ7 =114
3666 04:46:07.090140 DQ8 =102, DQ9 =104, DQ10 =118, DQ11 =108
3667 04:46:07.093552 DQ12 =122, DQ13 =124, DQ14 =120, DQ15 =124
3668 04:46:07.093973
3669 04:46:07.094308
3670 04:46:07.100277 [DQSOSCAuto] RK1, (LSB)MR18= 0xf406, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 415 ps
3671 04:46:07.103714 CH1 RK1: MR19=304, MR18=F406
3672 04:46:07.110141 CH1_RK1: MR19=0x304, MR18=0xF406, DQSOSC=407, MR23=63, INC=39, DEC=26
3673 04:46:07.113557 [RxdqsGatingPostProcess] freq 1200
3674 04:46:07.120342 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3675 04:46:07.120854 best DQS0 dly(2T, 0.5T) = (0, 11)
3676 04:46:07.123073 best DQS1 dly(2T, 0.5T) = (0, 11)
3677 04:46:07.126528 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3678 04:46:07.129992 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3679 04:46:07.133306 best DQS0 dly(2T, 0.5T) = (0, 11)
3680 04:46:07.136624 best DQS1 dly(2T, 0.5T) = (0, 11)
3681 04:46:07.140139 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3682 04:46:07.143079 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3683 04:46:07.146210 Pre-setting of DQS Precalculation
3684 04:46:07.152749 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3685 04:46:07.159628 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3686 04:46:07.165974 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3687 04:46:07.166488
3688 04:46:07.166822
3689 04:46:07.169704 [Calibration Summary] 2400 Mbps
3690 04:46:07.170219 CH 0, Rank 0
3691 04:46:07.172510 SW Impedance : PASS
3692 04:46:07.176269 DUTY Scan : NO K
3693 04:46:07.176803 ZQ Calibration : PASS
3694 04:46:07.178961 Jitter Meter : NO K
3695 04:46:07.182329 CBT Training : PASS
3696 04:46:07.182740 Write leveling : PASS
3697 04:46:07.186002 RX DQS gating : PASS
3698 04:46:07.188855 RX DQ/DQS(RDDQC) : PASS
3699 04:46:07.189271 TX DQ/DQS : PASS
3700 04:46:07.192503 RX DATLAT : PASS
3701 04:46:07.195736 RX DQ/DQS(Engine): PASS
3702 04:46:07.196247 TX OE : NO K
3703 04:46:07.196581 All Pass.
3704 04:46:07.199307
3705 04:46:07.199953 CH 0, Rank 1
3706 04:46:07.202452 SW Impedance : PASS
3707 04:46:07.202873 DUTY Scan : NO K
3708 04:46:07.205530 ZQ Calibration : PASS
3709 04:46:07.208683 Jitter Meter : NO K
3710 04:46:07.209096 CBT Training : PASS
3711 04:46:07.212569 Write leveling : PASS
3712 04:46:07.213087 RX DQS gating : PASS
3713 04:46:07.215700 RX DQ/DQS(RDDQC) : PASS
3714 04:46:07.218762 TX DQ/DQS : PASS
3715 04:46:07.219287 RX DATLAT : PASS
3716 04:46:07.222197 RX DQ/DQS(Engine): PASS
3717 04:46:07.225607 TX OE : NO K
3718 04:46:07.226134 All Pass.
3719 04:46:07.226515
3720 04:46:07.226832 CH 1, Rank 0
3721 04:46:07.228962 SW Impedance : PASS
3722 04:46:07.231840 DUTY Scan : NO K
3723 04:46:07.232369 ZQ Calibration : PASS
3724 04:46:07.235098 Jitter Meter : NO K
3725 04:46:07.238595 CBT Training : PASS
3726 04:46:07.239157 Write leveling : PASS
3727 04:46:07.241808 RX DQS gating : PASS
3728 04:46:07.245216 RX DQ/DQS(RDDQC) : PASS
3729 04:46:07.245678 TX DQ/DQS : PASS
3730 04:46:07.248131 RX DATLAT : PASS
3731 04:46:07.251415 RX DQ/DQS(Engine): PASS
3732 04:46:07.251858 TX OE : NO K
3733 04:46:07.255013 All Pass.
3734 04:46:07.255470
3735 04:46:07.255811 CH 1, Rank 1
3736 04:46:07.258470 SW Impedance : PASS
3737 04:46:07.258884 DUTY Scan : NO K
3738 04:46:07.261786 ZQ Calibration : PASS
3739 04:46:07.264614 Jitter Meter : NO K
3740 04:46:07.265039 CBT Training : PASS
3741 04:46:07.268061 Write leveling : PASS
3742 04:46:07.271649 RX DQS gating : PASS
3743 04:46:07.272172 RX DQ/DQS(RDDQC) : PASS
3744 04:46:07.274620 TX DQ/DQS : PASS
3745 04:46:07.277925 RX DATLAT : PASS
3746 04:46:07.278345 RX DQ/DQS(Engine): PASS
3747 04:46:07.281270 TX OE : NO K
3748 04:46:07.281689 All Pass.
3749 04:46:07.282024
3750 04:46:07.284936 DramC Write-DBI off
3751 04:46:07.287539 PER_BANK_REFRESH: Hybrid Mode
3752 04:46:07.287960 TX_TRACKING: ON
3753 04:46:07.298267 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3754 04:46:07.300888 [FAST_K] Save calibration result to emmc
3755 04:46:07.304275 dramc_set_vcore_voltage set vcore to 650000
3756 04:46:07.307579 Read voltage for 600, 5
3757 04:46:07.307995 Vio18 = 0
3758 04:46:07.308323 Vcore = 650000
3759 04:46:07.310807 Vdram = 0
3760 04:46:07.311224 Vddq = 0
3761 04:46:07.311625 Vmddr = 0
3762 04:46:07.317759 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3763 04:46:07.321280 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3764 04:46:07.323854 MEM_TYPE=3, freq_sel=19
3765 04:46:07.327530 sv_algorithm_assistance_LP4_1600
3766 04:46:07.330771 ============ PULL DRAM RESETB DOWN ============
3767 04:46:07.334473 ========== PULL DRAM RESETB DOWN end =========
3768 04:46:07.340662 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3769 04:46:07.343920 ===================================
3770 04:46:07.347294 LPDDR4 DRAM CONFIGURATION
3771 04:46:07.350438 ===================================
3772 04:46:07.350854 EX_ROW_EN[0] = 0x0
3773 04:46:07.353904 EX_ROW_EN[1] = 0x0
3774 04:46:07.354418 LP4Y_EN = 0x0
3775 04:46:07.357595 WORK_FSP = 0x0
3776 04:46:07.358014 WL = 0x2
3777 04:46:07.360033 RL = 0x2
3778 04:46:07.360453 BL = 0x2
3779 04:46:07.363535 RPST = 0x0
3780 04:46:07.363953 RD_PRE = 0x0
3781 04:46:07.367057 WR_PRE = 0x1
3782 04:46:07.367637 WR_PST = 0x0
3783 04:46:07.370403 DBI_WR = 0x0
3784 04:46:07.373370 DBI_RD = 0x0
3785 04:46:07.373789 OTF = 0x1
3786 04:46:07.376676 ===================================
3787 04:46:07.380052 ===================================
3788 04:46:07.380642 ANA top config
3789 04:46:07.383283 ===================================
3790 04:46:07.386981 DLL_ASYNC_EN = 0
3791 04:46:07.389791 ALL_SLAVE_EN = 1
3792 04:46:07.393172 NEW_RANK_MODE = 1
3793 04:46:07.396603 DLL_IDLE_MODE = 1
3794 04:46:07.397019 LP45_APHY_COMB_EN = 1
3795 04:46:07.400209 TX_ODT_DIS = 1
3796 04:46:07.402766 NEW_8X_MODE = 1
3797 04:46:07.406705 ===================================
3798 04:46:07.409524 ===================================
3799 04:46:07.413092 data_rate = 1200
3800 04:46:07.416179 CKR = 1
3801 04:46:07.419446 DQ_P2S_RATIO = 8
3802 04:46:07.422976 ===================================
3803 04:46:07.423558 CA_P2S_RATIO = 8
3804 04:46:07.425923 DQ_CA_OPEN = 0
3805 04:46:07.429088 DQ_SEMI_OPEN = 0
3806 04:46:07.432535 CA_SEMI_OPEN = 0
3807 04:46:07.435531 CA_FULL_RATE = 0
3808 04:46:07.439191 DQ_CKDIV4_EN = 1
3809 04:46:07.439773 CA_CKDIV4_EN = 1
3810 04:46:07.442767 CA_PREDIV_EN = 0
3811 04:46:07.445428 PH8_DLY = 0
3812 04:46:07.449136 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3813 04:46:07.452440 DQ_AAMCK_DIV = 4
3814 04:46:07.455971 CA_AAMCK_DIV = 4
3815 04:46:07.456495 CA_ADMCK_DIV = 4
3816 04:46:07.458948 DQ_TRACK_CA_EN = 0
3817 04:46:07.462517 CA_PICK = 600
3818 04:46:07.465666 CA_MCKIO = 600
3819 04:46:07.468803 MCKIO_SEMI = 0
3820 04:46:07.472157 PLL_FREQ = 2288
3821 04:46:07.476074 DQ_UI_PI_RATIO = 32
3822 04:46:07.478978 CA_UI_PI_RATIO = 0
3823 04:46:07.481837 ===================================
3824 04:46:07.485396 ===================================
3825 04:46:07.485919 memory_type:LPDDR4
3826 04:46:07.488505 GP_NUM : 10
3827 04:46:07.489024 SRAM_EN : 1
3828 04:46:07.491900 MD32_EN : 0
3829 04:46:07.494866 ===================================
3830 04:46:07.498132 [ANA_INIT] >>>>>>>>>>>>>>
3831 04:46:07.501736 <<<<<< [CONFIGURE PHASE]: ANA_TX
3832 04:46:07.505109 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3833 04:46:07.508030 ===================================
3834 04:46:07.511459 data_rate = 1200,PCW = 0X5800
3835 04:46:07.514763 ===================================
3836 04:46:07.517864 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3837 04:46:07.521583 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3838 04:46:07.528740 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3839 04:46:07.531242 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3840 04:46:07.534645 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3841 04:46:07.537903 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3842 04:46:07.541216 [ANA_INIT] flow start
3843 04:46:07.544362 [ANA_INIT] PLL >>>>>>>>
3844 04:46:07.544848 [ANA_INIT] PLL <<<<<<<<
3845 04:46:07.548068 [ANA_INIT] MIDPI >>>>>>>>
3846 04:46:07.551491 [ANA_INIT] MIDPI <<<<<<<<
3847 04:46:07.554713 [ANA_INIT] DLL >>>>>>>>
3848 04:46:07.555247 [ANA_INIT] flow end
3849 04:46:07.557284 ============ LP4 DIFF to SE enter ============
3850 04:46:07.564122 ============ LP4 DIFF to SE exit ============
3851 04:46:07.564682 [ANA_INIT] <<<<<<<<<<<<<
3852 04:46:07.567762 [Flow] Enable top DCM control >>>>>
3853 04:46:07.570868 [Flow] Enable top DCM control <<<<<
3854 04:46:07.574551 Enable DLL master slave shuffle
3855 04:46:07.580384 ==============================================================
3856 04:46:07.584035 Gating Mode config
3857 04:46:07.587524 ==============================================================
3858 04:46:07.590482 Config description:
3859 04:46:07.600888 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3860 04:46:07.607009 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3861 04:46:07.610531 SELPH_MODE 0: By rank 1: By Phase
3862 04:46:07.616845 ==============================================================
3863 04:46:07.620232 GAT_TRACK_EN = 1
3864 04:46:07.623727 RX_GATING_MODE = 2
3865 04:46:07.626413 RX_GATING_TRACK_MODE = 2
3866 04:46:07.630085 SELPH_MODE = 1
3867 04:46:07.630553 PICG_EARLY_EN = 1
3868 04:46:07.633031 VALID_LAT_VALUE = 1
3869 04:46:07.639849 ==============================================================
3870 04:46:07.642958 Enter into Gating configuration >>>>
3871 04:46:07.645994 Exit from Gating configuration <<<<
3872 04:46:07.649826 Enter into DVFS_PRE_config >>>>>
3873 04:46:07.659408 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3874 04:46:07.662893 Exit from DVFS_PRE_config <<<<<
3875 04:46:07.666619 Enter into PICG configuration >>>>
3876 04:46:07.669592 Exit from PICG configuration <<<<
3877 04:46:07.672453 [RX_INPUT] configuration >>>>>
3878 04:46:07.675826 [RX_INPUT] configuration <<<<<
3879 04:46:07.682802 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3880 04:46:07.686267 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3881 04:46:07.692357 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3882 04:46:07.699173 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3883 04:46:07.706113 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3884 04:46:07.712387 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3885 04:46:07.715175 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3886 04:46:07.718710 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3887 04:46:07.721928 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3888 04:46:07.728332 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3889 04:46:07.732053 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3890 04:46:07.735408 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3891 04:46:07.738288 ===================================
3892 04:46:07.741740 LPDDR4 DRAM CONFIGURATION
3893 04:46:07.745316 ===================================
3894 04:46:07.747889 EX_ROW_EN[0] = 0x0
3895 04:46:07.748395 EX_ROW_EN[1] = 0x0
3896 04:46:07.751264 LP4Y_EN = 0x0
3897 04:46:07.751925 WORK_FSP = 0x0
3898 04:46:07.754539 WL = 0x2
3899 04:46:07.755112 RL = 0x2
3900 04:46:07.757838 BL = 0x2
3901 04:46:07.758322 RPST = 0x0
3902 04:46:07.761354 RD_PRE = 0x0
3903 04:46:07.761790 WR_PRE = 0x1
3904 04:46:07.764628 WR_PST = 0x0
3905 04:46:07.765067 DBI_WR = 0x0
3906 04:46:07.768262 DBI_RD = 0x0
3907 04:46:07.768792 OTF = 0x1
3908 04:46:07.771470 ===================================
3909 04:46:07.777861 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3910 04:46:07.781231 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3911 04:46:07.784233 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3912 04:46:07.787755 ===================================
3913 04:46:07.790924 LPDDR4 DRAM CONFIGURATION
3914 04:46:07.794265 ===================================
3915 04:46:07.797623 EX_ROW_EN[0] = 0x10
3916 04:46:07.798044 EX_ROW_EN[1] = 0x0
3917 04:46:07.801071 LP4Y_EN = 0x0
3918 04:46:07.801616 WORK_FSP = 0x0
3919 04:46:07.803847 WL = 0x2
3920 04:46:07.804344 RL = 0x2
3921 04:46:07.807326 BL = 0x2
3922 04:46:07.808067 RPST = 0x0
3923 04:46:07.810242 RD_PRE = 0x0
3924 04:46:07.810615 WR_PRE = 0x1
3925 04:46:07.813882 WR_PST = 0x0
3926 04:46:07.817145 DBI_WR = 0x0
3927 04:46:07.817610 DBI_RD = 0x0
3928 04:46:07.820635 OTF = 0x1
3929 04:46:07.824006 ===================================
3930 04:46:07.827333 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3931 04:46:07.833135 nWR fixed to 30
3932 04:46:07.835628 [ModeRegInit_LP4] CH0 RK0
3933 04:46:07.836143 [ModeRegInit_LP4] CH0 RK1
3934 04:46:07.838844 [ModeRegInit_LP4] CH1 RK0
3935 04:46:07.842115 [ModeRegInit_LP4] CH1 RK1
3936 04:46:07.842633 match AC timing 17
3937 04:46:07.848647 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3938 04:46:07.851986 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3939 04:46:07.855708 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3940 04:46:07.861842 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3941 04:46:07.865221 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3942 04:46:07.865643 ==
3943 04:46:07.868386 Dram Type= 6, Freq= 0, CH_0, rank 0
3944 04:46:07.871513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3945 04:46:07.874820 ==
3946 04:46:07.877923 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3947 04:46:07.884860 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3948 04:46:07.887750 [CA 0] Center 36 (6~67) winsize 62
3949 04:46:07.891313 [CA 1] Center 36 (5~67) winsize 63
3950 04:46:07.894466 [CA 2] Center 34 (4~65) winsize 62
3951 04:46:07.897661 [CA 3] Center 34 (4~65) winsize 62
3952 04:46:07.900779 [CA 4] Center 33 (3~64) winsize 62
3953 04:46:07.904111 [CA 5] Center 33 (3~64) winsize 62
3954 04:46:07.904241
3955 04:46:07.907681 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3956 04:46:07.907874
3957 04:46:07.911504 [CATrainingPosCal] consider 1 rank data
3958 04:46:07.913943 u2DelayCellTimex100 = 270/100 ps
3959 04:46:07.917545 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3960 04:46:07.920422 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3961 04:46:07.927386 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3962 04:46:07.930470 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3963 04:46:07.933670 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3964 04:46:07.937165 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3965 04:46:07.937357
3966 04:46:07.940618 CA PerBit enable=1, Macro0, CA PI delay=33
3967 04:46:07.940873
3968 04:46:07.944041 [CBTSetCACLKResult] CA Dly = 33
3969 04:46:07.944284 CS Dly: 5 (0~36)
3970 04:46:07.947601 ==
3971 04:46:07.950701 Dram Type= 6, Freq= 0, CH_0, rank 1
3972 04:46:07.953843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3973 04:46:07.954228 ==
3974 04:46:07.957259 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3975 04:46:07.964038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3976 04:46:07.967787 [CA 0] Center 36 (6~67) winsize 62
3977 04:46:07.970890 [CA 1] Center 36 (6~67) winsize 62
3978 04:46:07.974107 [CA 2] Center 34 (4~65) winsize 62
3979 04:46:07.977442 [CA 3] Center 34 (4~65) winsize 62
3980 04:46:07.980602 [CA 4] Center 34 (3~65) winsize 63
3981 04:46:07.984146 [CA 5] Center 33 (3~64) winsize 62
3982 04:46:07.984595
3983 04:46:07.987541 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3984 04:46:07.987881
3985 04:46:07.990328 [CATrainingPosCal] consider 2 rank data
3986 04:46:07.993661 u2DelayCellTimex100 = 270/100 ps
3987 04:46:07.997330 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3988 04:46:08.003513 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3989 04:46:08.006930 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3990 04:46:08.009972 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3991 04:46:08.013646 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3992 04:46:08.016789 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3993 04:46:08.016943
3994 04:46:08.020053 CA PerBit enable=1, Macro0, CA PI delay=33
3995 04:46:08.020186
3996 04:46:08.023192 [CBTSetCACLKResult] CA Dly = 33
3997 04:46:08.026296 CS Dly: 6 (0~38)
3998 04:46:08.026430
3999 04:46:08.029971 ----->DramcWriteLeveling(PI) begin...
4000 04:46:08.030104 ==
4001 04:46:08.033148 Dram Type= 6, Freq= 0, CH_0, rank 0
4002 04:46:08.036096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4003 04:46:08.036228 ==
4004 04:46:08.039657 Write leveling (Byte 0): 31 => 31
4005 04:46:08.043165 Write leveling (Byte 1): 28 => 28
4006 04:46:08.046153 DramcWriteLeveling(PI) end<-----
4007 04:46:08.046288
4008 04:46:08.046426 ==
4009 04:46:08.049315 Dram Type= 6, Freq= 0, CH_0, rank 0
4010 04:46:08.052697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4011 04:46:08.052833 ==
4012 04:46:08.056430 [Gating] SW mode calibration
4013 04:46:08.062700 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4014 04:46:08.069855 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4015 04:46:08.072455 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4016 04:46:08.076328 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4017 04:46:08.082749 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4018 04:46:08.085540 0 9 12 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
4019 04:46:08.088929 0 9 16 | B1->B0 | 2e2e 2727 | 0 0 | (1 1) (0 0)
4020 04:46:08.095605 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 04:46:08.099068 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 04:46:08.105645 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 04:46:08.108885 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 04:46:08.111977 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 04:46:08.118679 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 04:46:08.122020 0 10 12 | B1->B0 | 2424 3232 | 0 0 | (0 0) (1 1)
4027 04:46:08.125471 0 10 16 | B1->B0 | 3838 4545 | 1 0 | (0 0) (0 0)
4028 04:46:08.131742 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 04:46:08.135301 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 04:46:08.138740 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 04:46:08.145069 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 04:46:08.148120 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 04:46:08.151348 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 04:46:08.158410 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4035 04:46:08.161860 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4036 04:46:08.164901 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 04:46:08.171623 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 04:46:08.174911 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 04:46:08.178376 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 04:46:08.184819 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 04:46:08.188119 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 04:46:08.190951 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 04:46:08.197685 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 04:46:08.200888 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 04:46:08.204201 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 04:46:08.210855 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 04:46:08.214172 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 04:46:08.217136 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 04:46:08.223750 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 04:46:08.227589 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4051 04:46:08.230892 Total UI for P1: 0, mck2ui 16
4052 04:46:08.234185 best dqsien dly found for B0: ( 0, 13, 10)
4053 04:46:08.236910 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4054 04:46:08.244381 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 04:46:08.244895 Total UI for P1: 0, mck2ui 16
4056 04:46:08.250582 best dqsien dly found for B1: ( 0, 13, 14)
4057 04:46:08.254382 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4058 04:46:08.256924 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4059 04:46:08.257390
4060 04:46:08.260583 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4061 04:46:08.263861 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4062 04:46:08.267014 [Gating] SW calibration Done
4063 04:46:08.267516 ==
4064 04:46:08.270176 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 04:46:08.273228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 04:46:08.273795 ==
4067 04:46:08.276499 RX Vref Scan: 0
4068 04:46:08.276913
4069 04:46:08.279924 RX Vref 0 -> 0, step: 1
4070 04:46:08.280463
4071 04:46:08.280960 RX Delay -230 -> 252, step: 16
4072 04:46:08.286898 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4073 04:46:08.290204 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4074 04:46:08.292949 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4075 04:46:08.296691 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4076 04:46:08.303179 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4077 04:46:08.306676 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4078 04:46:08.309863 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4079 04:46:08.313077 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4080 04:46:08.319550 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4081 04:46:08.323174 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4082 04:46:08.326131 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4083 04:46:08.329639 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4084 04:46:08.336240 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4085 04:46:08.339233 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4086 04:46:08.342486 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4087 04:46:08.345882 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4088 04:46:08.346304 ==
4089 04:46:08.349021 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 04:46:08.355739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 04:46:08.356260 ==
4092 04:46:08.356612 DQS Delay:
4093 04:46:08.358773 DQS0 = 0, DQS1 = 0
4094 04:46:08.359293 DQM Delay:
4095 04:46:08.359675 DQM0 = 47, DQM1 = 35
4096 04:46:08.362625 DQ Delay:
4097 04:46:08.365532 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4098 04:46:08.368945 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =57
4099 04:46:08.372737 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =33
4100 04:46:08.375647 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4101 04:46:08.376163
4102 04:46:08.376501
4103 04:46:08.376806 ==
4104 04:46:08.379111 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 04:46:08.382169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 04:46:08.382690 ==
4107 04:46:08.383023
4108 04:46:08.383328
4109 04:46:08.385275 TX Vref Scan disable
4110 04:46:08.388907 == TX Byte 0 ==
4111 04:46:08.391915 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4112 04:46:08.395174 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4113 04:46:08.398327 == TX Byte 1 ==
4114 04:46:08.401423 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4115 04:46:08.405430 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4116 04:46:08.405850 ==
4117 04:46:08.408956 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 04:46:08.412069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 04:46:08.415521 ==
4120 04:46:08.416100
4121 04:46:08.416433
4122 04:46:08.416741 TX Vref Scan disable
4123 04:46:08.419107 == TX Byte 0 ==
4124 04:46:08.422505 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4125 04:46:08.428819 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4126 04:46:08.429378 == TX Byte 1 ==
4127 04:46:08.432691 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4128 04:46:08.439121 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4129 04:46:08.439675
4130 04:46:08.440012 [DATLAT]
4131 04:46:08.440338 Freq=600, CH0 RK0
4132 04:46:08.440672
4133 04:46:08.442594 DATLAT Default: 0x9
4134 04:46:08.443108 0, 0xFFFF, sum = 0
4135 04:46:08.445337 1, 0xFFFF, sum = 0
4136 04:46:08.448343 2, 0xFFFF, sum = 0
4137 04:46:08.448767 3, 0xFFFF, sum = 0
4138 04:46:08.451994 4, 0xFFFF, sum = 0
4139 04:46:08.452415 5, 0xFFFF, sum = 0
4140 04:46:08.455306 6, 0xFFFF, sum = 0
4141 04:46:08.455884 7, 0xFFFF, sum = 0
4142 04:46:08.458245 8, 0x0, sum = 1
4143 04:46:08.458668 9, 0x0, sum = 2
4144 04:46:08.462033 10, 0x0, sum = 3
4145 04:46:08.462457 11, 0x0, sum = 4
4146 04:46:08.462794 best_step = 9
4147 04:46:08.463102
4148 04:46:08.465363 ==
4149 04:46:08.468190 Dram Type= 6, Freq= 0, CH_0, rank 0
4150 04:46:08.471638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 04:46:08.472059 ==
4152 04:46:08.472390 RX Vref Scan: 1
4153 04:46:08.472698
4154 04:46:08.474719 RX Vref 0 -> 0, step: 1
4155 04:46:08.475138
4156 04:46:08.478427 RX Delay -195 -> 252, step: 8
4157 04:46:08.478942
4158 04:46:08.481688 Set Vref, RX VrefLevel [Byte0]: 57
4159 04:46:08.484734 [Byte1]: 49
4160 04:46:08.485251
4161 04:46:08.488046 Final RX Vref Byte 0 = 57 to rank0
4162 04:46:08.491796 Final RX Vref Byte 1 = 49 to rank0
4163 04:46:08.494862 Final RX Vref Byte 0 = 57 to rank1
4164 04:46:08.498060 Final RX Vref Byte 1 = 49 to rank1==
4165 04:46:08.501365 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 04:46:08.507934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 04:46:08.508356 ==
4168 04:46:08.508689 DQS Delay:
4169 04:46:08.508999 DQS0 = 0, DQS1 = 0
4170 04:46:08.510934 DQM Delay:
4171 04:46:08.511408 DQM0 = 44, DQM1 = 37
4172 04:46:08.514742 DQ Delay:
4173 04:46:08.517850 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4174 04:46:08.521057 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4175 04:46:08.524091 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4176 04:46:08.527290 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4177 04:46:08.527753
4178 04:46:08.528085
4179 04:46:08.533777 [DQSOSCAuto] RK0, (LSB)MR18= 0x453d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4180 04:46:08.537535 CH0 RK0: MR19=808, MR18=453D
4181 04:46:08.544018 CH0_RK0: MR19=0x808, MR18=0x453D, DQSOSC=396, MR23=63, INC=167, DEC=111
4182 04:46:08.544524
4183 04:46:08.547475 ----->DramcWriteLeveling(PI) begin...
4184 04:46:08.547989 ==
4185 04:46:08.550407 Dram Type= 6, Freq= 0, CH_0, rank 1
4186 04:46:08.554023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 04:46:08.554440 ==
4188 04:46:08.557452 Write leveling (Byte 0): 32 => 32
4189 04:46:08.560729 Write leveling (Byte 1): 27 => 27
4190 04:46:08.563437 DramcWriteLeveling(PI) end<-----
4191 04:46:08.563856
4192 04:46:08.564186 ==
4193 04:46:08.567528 Dram Type= 6, Freq= 0, CH_0, rank 1
4194 04:46:08.570612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 04:46:08.573644 ==
4196 04:46:08.574320 [Gating] SW mode calibration
4197 04:46:08.583927 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4198 04:46:08.586985 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4199 04:46:08.590076 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4200 04:46:08.596424 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4201 04:46:08.600199 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4202 04:46:08.603275 0 9 12 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
4203 04:46:08.610239 0 9 16 | B1->B0 | 2e2e 2626 | 0 0 | (0 0) (0 0)
4204 04:46:08.613653 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 04:46:08.616320 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 04:46:08.623529 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 04:46:08.626593 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 04:46:08.629903 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 04:46:08.635822 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 04:46:08.639810 0 10 12 | B1->B0 | 2525 3030 | 0 1 | (1 1) (0 0)
4211 04:46:08.642872 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4212 04:46:08.649421 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 04:46:08.652464 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 04:46:08.655898 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 04:46:08.662237 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 04:46:08.666122 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 04:46:08.668903 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 04:46:08.676057 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 04:46:08.678895 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 04:46:08.682455 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 04:46:08.689264 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 04:46:08.692537 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 04:46:08.695309 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 04:46:08.702081 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 04:46:08.705624 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 04:46:08.708650 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 04:46:08.715490 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 04:46:08.718493 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 04:46:08.721385 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 04:46:08.728506 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 04:46:08.731896 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 04:46:08.735280 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 04:46:08.741705 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 04:46:08.744808 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4235 04:46:08.748020 Total UI for P1: 0, mck2ui 16
4236 04:46:08.751355 best dqsien dly found for B0: ( 0, 13, 10)
4237 04:46:08.754504 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 04:46:08.757671 Total UI for P1: 0, mck2ui 16
4239 04:46:08.761211 best dqsien dly found for B1: ( 0, 13, 12)
4240 04:46:08.764217 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4241 04:46:08.771324 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4242 04:46:08.771877
4243 04:46:08.774168 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4244 04:46:08.777372 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4245 04:46:08.780707 [Gating] SW calibration Done
4246 04:46:08.781341 ==
4247 04:46:08.783984 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 04:46:08.787334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 04:46:08.787796 ==
4250 04:46:08.790367 RX Vref Scan: 0
4251 04:46:08.790800
4252 04:46:08.791132 RX Vref 0 -> 0, step: 1
4253 04:46:08.791488
4254 04:46:08.794097 RX Delay -230 -> 252, step: 16
4255 04:46:08.800552 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4256 04:46:08.803700 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4257 04:46:08.807020 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4258 04:46:08.810550 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4259 04:46:08.813775 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4260 04:46:08.820496 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4261 04:46:08.824138 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4262 04:46:08.827466 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4263 04:46:08.830673 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4264 04:46:08.836666 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4265 04:46:08.840036 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4266 04:46:08.844017 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4267 04:46:08.846599 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4268 04:46:08.853334 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4269 04:46:08.857608 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4270 04:46:08.860101 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4271 04:46:08.860561 ==
4272 04:46:08.863243 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 04:46:08.867085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 04:46:08.869860 ==
4275 04:46:08.870429 DQS Delay:
4276 04:46:08.870798 DQS0 = 0, DQS1 = 0
4277 04:46:08.873188 DQM Delay:
4278 04:46:08.873666 DQM0 = 43, DQM1 = 36
4279 04:46:08.876074 DQ Delay:
4280 04:46:08.876571 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4281 04:46:08.879713 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4282 04:46:08.883509 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4283 04:46:08.886711 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4284 04:46:08.889485
4285 04:46:08.889904
4286 04:46:08.890233 ==
4287 04:46:08.893307 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 04:46:08.895994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 04:46:08.896413 ==
4290 04:46:08.896922
4291 04:46:08.897413
4292 04:46:08.899053 TX Vref Scan disable
4293 04:46:08.899511 == TX Byte 0 ==
4294 04:46:08.905620 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4295 04:46:08.909467 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4296 04:46:08.909881 == TX Byte 1 ==
4297 04:46:08.915613 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4298 04:46:08.919640 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4299 04:46:08.920172 ==
4300 04:46:08.922704 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 04:46:08.925643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 04:46:08.926155 ==
4303 04:46:08.929700
4304 04:46:08.930203
4305 04:46:08.930532 TX Vref Scan disable
4306 04:46:08.933425 == TX Byte 0 ==
4307 04:46:08.936237 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4308 04:46:08.942596 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4309 04:46:08.943111 == TX Byte 1 ==
4310 04:46:08.946112 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4311 04:46:08.952698 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4312 04:46:08.953213
4313 04:46:08.953548 [DATLAT]
4314 04:46:08.953851 Freq=600, CH0 RK1
4315 04:46:08.954146
4316 04:46:08.955709 DATLAT Default: 0x9
4317 04:46:08.956124 0, 0xFFFF, sum = 0
4318 04:46:08.959001 1, 0xFFFF, sum = 0
4319 04:46:08.962130 2, 0xFFFF, sum = 0
4320 04:46:08.962548 3, 0xFFFF, sum = 0
4321 04:46:08.965818 4, 0xFFFF, sum = 0
4322 04:46:08.966337 5, 0xFFFF, sum = 0
4323 04:46:08.969184 6, 0xFFFF, sum = 0
4324 04:46:08.969622 7, 0xFFFF, sum = 0
4325 04:46:08.972563 8, 0x0, sum = 1
4326 04:46:08.973082 9, 0x0, sum = 2
4327 04:46:08.975284 10, 0x0, sum = 3
4328 04:46:08.975747 11, 0x0, sum = 4
4329 04:46:08.976083 best_step = 9
4330 04:46:08.976389
4331 04:46:08.979062 ==
4332 04:46:08.982049 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 04:46:08.985385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 04:46:08.985919 ==
4335 04:46:08.986259 RX Vref Scan: 0
4336 04:46:08.986566
4337 04:46:08.988556 RX Vref 0 -> 0, step: 1
4338 04:46:08.988967
4339 04:46:08.991913 RX Delay -179 -> 252, step: 8
4340 04:46:08.998614 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4341 04:46:09.001954 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4342 04:46:09.005647 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4343 04:46:09.008225 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4344 04:46:09.011906 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4345 04:46:09.018121 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4346 04:46:09.021609 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4347 04:46:09.024839 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4348 04:46:09.028476 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4349 04:46:09.032000 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4350 04:46:09.038214 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4351 04:46:09.041558 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4352 04:46:09.044913 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4353 04:46:09.048017 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4354 04:46:09.055180 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4355 04:46:09.058104 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4356 04:46:09.058518 ==
4357 04:46:09.061271 Dram Type= 6, Freq= 0, CH_0, rank 1
4358 04:46:09.066700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4359 04:46:09.067128 ==
4360 04:46:09.067940 DQS Delay:
4361 04:46:09.068478 DQS0 = 0, DQS1 = 0
4362 04:46:09.070844 DQM Delay:
4363 04:46:09.071253 DQM0 = 43, DQM1 = 36
4364 04:46:09.071620 DQ Delay:
4365 04:46:09.074263 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4366 04:46:09.077448 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =48
4367 04:46:09.081655 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4368 04:46:09.084315 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4369 04:46:09.084998
4370 04:46:09.085458
4371 04:46:09.094022 [DQSOSCAuto] RK1, (LSB)MR18= 0x403a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4372 04:46:09.097176 CH0 RK1: MR19=808, MR18=403A
4373 04:46:09.103924 CH0_RK1: MR19=0x808, MR18=0x403A, DQSOSC=397, MR23=63, INC=166, DEC=110
4374 04:46:09.107767 [RxdqsGatingPostProcess] freq 600
4375 04:46:09.110464 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4376 04:46:09.113610 Pre-setting of DQS Precalculation
4377 04:46:09.120418 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4378 04:46:09.120733 ==
4379 04:46:09.123492 Dram Type= 6, Freq= 0, CH_1, rank 0
4380 04:46:09.126718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4381 04:46:09.127013 ==
4382 04:46:09.133391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4383 04:46:09.137081 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4384 04:46:09.141311 [CA 0] Center 36 (6~66) winsize 61
4385 04:46:09.144759 [CA 1] Center 35 (5~66) winsize 62
4386 04:46:09.147751 [CA 2] Center 35 (5~65) winsize 61
4387 04:46:09.151290 [CA 3] Center 34 (4~65) winsize 62
4388 04:46:09.154690 [CA 4] Center 34 (4~65) winsize 62
4389 04:46:09.157848 [CA 5] Center 34 (3~65) winsize 63
4390 04:46:09.158370
4391 04:46:09.161114 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4392 04:46:09.161529
4393 04:46:09.164578 [CATrainingPosCal] consider 1 rank data
4394 04:46:09.168258 u2DelayCellTimex100 = 270/100 ps
4395 04:46:09.170758 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4396 04:46:09.177786 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4397 04:46:09.181216 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4398 04:46:09.183858 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4399 04:46:09.187321 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4400 04:46:09.191088 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4401 04:46:09.191673
4402 04:46:09.194145 CA PerBit enable=1, Macro0, CA PI delay=34
4403 04:46:09.194560
4404 04:46:09.197074 [CBTSetCACLKResult] CA Dly = 34
4405 04:46:09.200246 CS Dly: 4 (0~35)
4406 04:46:09.200661 ==
4407 04:46:09.203960 Dram Type= 6, Freq= 0, CH_1, rank 1
4408 04:46:09.207425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 04:46:09.208014 ==
4410 04:46:09.213478 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4411 04:46:09.217272 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4412 04:46:09.221290 [CA 0] Center 35 (5~66) winsize 62
4413 04:46:09.224546 [CA 1] Center 36 (6~66) winsize 61
4414 04:46:09.228611 [CA 2] Center 34 (4~65) winsize 62
4415 04:46:09.230921 [CA 3] Center 33 (3~64) winsize 62
4416 04:46:09.234301 [CA 4] Center 34 (3~65) winsize 63
4417 04:46:09.237846 [CA 5] Center 33 (3~64) winsize 62
4418 04:46:09.238261
4419 04:46:09.240957 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4420 04:46:09.241371
4421 04:46:09.244219 [CATrainingPosCal] consider 2 rank data
4422 04:46:09.247868 u2DelayCellTimex100 = 270/100 ps
4423 04:46:09.251025 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4424 04:46:09.257793 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4425 04:46:09.260939 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4426 04:46:09.263936 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4427 04:46:09.267236 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4428 04:46:09.270479 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4429 04:46:09.270925
4430 04:46:09.273651 CA PerBit enable=1, Macro0, CA PI delay=33
4431 04:46:09.274071
4432 04:46:09.276914 [CBTSetCACLKResult] CA Dly = 33
4433 04:46:09.280985 CS Dly: 4 (0~36)
4434 04:46:09.281400
4435 04:46:09.284144 ----->DramcWriteLeveling(PI) begin...
4436 04:46:09.284567 ==
4437 04:46:09.287030 Dram Type= 6, Freq= 0, CH_1, rank 0
4438 04:46:09.290285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 04:46:09.290709 ==
4440 04:46:09.293975 Write leveling (Byte 0): 31 => 31
4441 04:46:09.296548 Write leveling (Byte 1): 27 => 27
4442 04:46:09.299947 DramcWriteLeveling(PI) end<-----
4443 04:46:09.300367
4444 04:46:09.300694 ==
4445 04:46:09.303122 Dram Type= 6, Freq= 0, CH_1, rank 0
4446 04:46:09.306321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4447 04:46:09.306741 ==
4448 04:46:09.310363 [Gating] SW mode calibration
4449 04:46:09.316879 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4450 04:46:09.323354 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4451 04:46:09.326644 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4452 04:46:09.332892 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4453 04:46:09.336024 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4454 04:46:09.339257 0 9 12 | B1->B0 | 2f2f 2d2d | 1 0 | (1 0) (1 0)
4455 04:46:09.346545 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 04:46:09.349273 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 04:46:09.352629 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 04:46:09.359152 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 04:46:09.362556 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 04:46:09.365902 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 04:46:09.372276 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4462 04:46:09.375996 0 10 12 | B1->B0 | 2e2e 3636 | 0 0 | (0 0) (0 0)
4463 04:46:09.379719 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 04:46:09.385863 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 04:46:09.389176 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 04:46:09.393021 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 04:46:09.398769 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 04:46:09.402459 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 04:46:09.405630 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 04:46:09.411913 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4471 04:46:09.415347 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 04:46:09.418727 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 04:46:09.425262 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 04:46:09.429261 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 04:46:09.432053 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 04:46:09.438435 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 04:46:09.442077 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 04:46:09.445072 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 04:46:09.451965 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 04:46:09.455244 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 04:46:09.458301 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 04:46:09.464572 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 04:46:09.467732 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 04:46:09.471574 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 04:46:09.477723 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4486 04:46:09.481115 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4487 04:46:09.484414 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4488 04:46:09.487574 Total UI for P1: 0, mck2ui 16
4489 04:46:09.490850 best dqsien dly found for B0: ( 0, 13, 10)
4490 04:46:09.497751 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 04:46:09.498375 Total UI for P1: 0, mck2ui 16
4492 04:46:09.504013 best dqsien dly found for B1: ( 0, 13, 14)
4493 04:46:09.507330 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4494 04:46:09.510947 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4495 04:46:09.511437
4496 04:46:09.514223 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4497 04:46:09.517058 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4498 04:46:09.520433 [Gating] SW calibration Done
4499 04:46:09.521001 ==
4500 04:46:09.524292 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 04:46:09.527294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 04:46:09.527897 ==
4503 04:46:09.530554 RX Vref Scan: 0
4504 04:46:09.531120
4505 04:46:09.533891 RX Vref 0 -> 0, step: 1
4506 04:46:09.534349
4507 04:46:09.534734 RX Delay -230 -> 252, step: 16
4508 04:46:09.540315 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4509 04:46:09.543913 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4510 04:46:09.546646 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4511 04:46:09.550127 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4512 04:46:09.556986 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4513 04:46:09.560123 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4514 04:46:09.563080 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4515 04:46:09.566691 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4516 04:46:09.573277 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4517 04:46:09.576841 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4518 04:46:09.580136 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4519 04:46:09.583307 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4520 04:46:09.589783 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4521 04:46:09.592785 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4522 04:46:09.596212 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4523 04:46:09.599598 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4524 04:46:09.600057 ==
4525 04:46:09.602832 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 04:46:09.609737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 04:46:09.610301 ==
4528 04:46:09.610671 DQS Delay:
4529 04:46:09.612752 DQS0 = 0, DQS1 = 0
4530 04:46:09.613212 DQM Delay:
4531 04:46:09.613577 DQM0 = 50, DQM1 = 42
4532 04:46:09.616139 DQ Delay:
4533 04:46:09.619203 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4534 04:46:09.622742 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4535 04:46:09.626044 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4536 04:46:09.629491 DQ12 =57, DQ13 =57, DQ14 =57, DQ15 =49
4537 04:46:09.630015
4538 04:46:09.630351
4539 04:46:09.630661 ==
4540 04:46:09.632400 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 04:46:09.635591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 04:46:09.636016 ==
4543 04:46:09.636350
4544 04:46:09.636657
4545 04:46:09.639352 TX Vref Scan disable
4546 04:46:09.642660 == TX Byte 0 ==
4547 04:46:09.646023 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4548 04:46:09.649100 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4549 04:46:09.652138 == TX Byte 1 ==
4550 04:46:09.655499 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4551 04:46:09.659357 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4552 04:46:09.659927 ==
4553 04:46:09.662437 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 04:46:09.668536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 04:46:09.669061 ==
4556 04:46:09.669403
4557 04:46:09.669725
4558 04:46:09.670025 TX Vref Scan disable
4559 04:46:09.672937 == TX Byte 0 ==
4560 04:46:09.675896 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4561 04:46:09.683181 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4562 04:46:09.683796 == TX Byte 1 ==
4563 04:46:09.686121 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4564 04:46:09.692492 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4565 04:46:09.692913
4566 04:46:09.693243 [DATLAT]
4567 04:46:09.693552 Freq=600, CH1 RK0
4568 04:46:09.693848
4569 04:46:09.695733 DATLAT Default: 0x9
4570 04:46:09.699489 0, 0xFFFF, sum = 0
4571 04:46:09.699958 1, 0xFFFF, sum = 0
4572 04:46:09.702615 2, 0xFFFF, sum = 0
4573 04:46:09.703180 3, 0xFFFF, sum = 0
4574 04:46:09.705848 4, 0xFFFF, sum = 0
4575 04:46:09.706432 5, 0xFFFF, sum = 0
4576 04:46:09.708762 6, 0xFFFF, sum = 0
4577 04:46:09.709129 7, 0xFFFF, sum = 0
4578 04:46:09.712672 8, 0x0, sum = 1
4579 04:46:09.713099 9, 0x0, sum = 2
4580 04:46:09.715549 10, 0x0, sum = 3
4581 04:46:09.716003 11, 0x0, sum = 4
4582 04:46:09.716377 best_step = 9
4583 04:46:09.716721
4584 04:46:09.719018 ==
4585 04:46:09.722693 Dram Type= 6, Freq= 0, CH_1, rank 0
4586 04:46:09.725643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 04:46:09.726229 ==
4588 04:46:09.726706 RX Vref Scan: 1
4589 04:46:09.727122
4590 04:46:09.728613 RX Vref 0 -> 0, step: 1
4591 04:46:09.729045
4592 04:46:09.732343 RX Delay -179 -> 252, step: 8
4593 04:46:09.732878
4594 04:46:09.735737 Set Vref, RX VrefLevel [Byte0]: 54
4595 04:46:09.738619 [Byte1]: 54
4596 04:46:09.739060
4597 04:46:09.742219 Final RX Vref Byte 0 = 54 to rank0
4598 04:46:09.745053 Final RX Vref Byte 1 = 54 to rank0
4599 04:46:09.748366 Final RX Vref Byte 0 = 54 to rank1
4600 04:46:09.751818 Final RX Vref Byte 1 = 54 to rank1==
4601 04:46:09.755059 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 04:46:09.761888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 04:46:09.762432 ==
4604 04:46:09.762885 DQS Delay:
4605 04:46:09.763308 DQS0 = 0, DQS1 = 0
4606 04:46:09.765480 DQM Delay:
4607 04:46:09.766017 DQM0 = 45, DQM1 = 36
4608 04:46:09.767928 DQ Delay:
4609 04:46:09.771569 DQ0 =52, DQ1 =40, DQ2 =32, DQ3 =44
4610 04:46:09.774840 DQ4 =40, DQ5 =52, DQ6 =60, DQ7 =40
4611 04:46:09.777576 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =32
4612 04:46:09.781479 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4613 04:46:09.782040
4614 04:46:09.782407
4615 04:46:09.787909 [DQSOSCAuto] RK0, (LSB)MR18= 0x314b, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4616 04:46:09.791677 CH1 RK0: MR19=808, MR18=314B
4617 04:46:09.797834 CH1_RK0: MR19=0x808, MR18=0x314B, DQSOSC=395, MR23=63, INC=168, DEC=112
4618 04:46:09.798257
4619 04:46:09.801591 ----->DramcWriteLeveling(PI) begin...
4620 04:46:09.802013 ==
4621 04:46:09.804520 Dram Type= 6, Freq= 0, CH_1, rank 1
4622 04:46:09.807833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 04:46:09.808351 ==
4624 04:46:09.811180 Write leveling (Byte 0): 28 => 28
4625 04:46:09.814484 Write leveling (Byte 1): 27 => 27
4626 04:46:09.817321 DramcWriteLeveling(PI) end<-----
4627 04:46:09.817783
4628 04:46:09.818149 ==
4629 04:46:09.821025 Dram Type= 6, Freq= 0, CH_1, rank 1
4630 04:46:09.824194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 04:46:09.827567 ==
4632 04:46:09.828186 [Gating] SW mode calibration
4633 04:46:09.837325 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4634 04:46:09.840941 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4635 04:46:09.843944 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4636 04:46:09.850786 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4637 04:46:09.853868 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4638 04:46:09.856929 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (1 1)
4639 04:46:09.864119 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4640 04:46:09.866980 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 04:46:09.870852 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 04:46:09.876873 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 04:46:09.880114 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 04:46:09.883620 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 04:46:09.890539 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4646 04:46:09.893541 0 10 12 | B1->B0 | 2e2e 3838 | 0 1 | (0 0) (0 0)
4647 04:46:09.896935 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 04:46:09.903666 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 04:46:09.906802 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 04:46:09.910414 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 04:46:09.916852 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 04:46:09.920059 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 04:46:09.923616 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4654 04:46:09.930256 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4655 04:46:09.933208 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 04:46:09.936228 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 04:46:09.942746 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 04:46:09.945994 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 04:46:09.949313 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 04:46:09.956298 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 04:46:09.960247 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 04:46:09.962600 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 04:46:09.969811 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 04:46:09.972242 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 04:46:09.975732 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 04:46:09.982516 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 04:46:09.985635 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 04:46:09.988869 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 04:46:09.995571 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 04:46:09.998787 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4671 04:46:10.002154 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 04:46:10.005116 Total UI for P1: 0, mck2ui 16
4673 04:46:10.008510 best dqsien dly found for B0: ( 0, 13, 12)
4674 04:46:10.012196 Total UI for P1: 0, mck2ui 16
4675 04:46:10.015038 best dqsien dly found for B1: ( 0, 13, 12)
4676 04:46:10.018342 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4677 04:46:10.024899 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4678 04:46:10.025468
4679 04:46:10.027962 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4680 04:46:10.031633 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4681 04:46:10.034944 [Gating] SW calibration Done
4682 04:46:10.035554 ==
4683 04:46:10.038108 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 04:46:10.041355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 04:46:10.041824 ==
4686 04:46:10.044839 RX Vref Scan: 0
4687 04:46:10.045302
4688 04:46:10.045665 RX Vref 0 -> 0, step: 1
4689 04:46:10.046005
4690 04:46:10.047796 RX Delay -230 -> 252, step: 16
4691 04:46:10.050834 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4692 04:46:10.057420 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4693 04:46:10.060714 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4694 04:46:10.063969 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4695 04:46:10.068257 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4696 04:46:10.074616 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4697 04:46:10.077403 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4698 04:46:10.080800 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4699 04:46:10.084043 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4700 04:46:10.091344 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4701 04:46:10.093891 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4702 04:46:10.097253 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4703 04:46:10.100302 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4704 04:46:10.107023 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4705 04:46:10.110634 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4706 04:46:10.114087 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4707 04:46:10.114629 ==
4708 04:46:10.117013 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 04:46:10.120646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 04:46:10.123659 ==
4711 04:46:10.124081 DQS Delay:
4712 04:46:10.124413 DQS0 = 0, DQS1 = 0
4713 04:46:10.126979 DQM Delay:
4714 04:46:10.127533 DQM0 = 41, DQM1 = 40
4715 04:46:10.130524 DQ Delay:
4716 04:46:10.133598 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4717 04:46:10.134139 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =33
4718 04:46:10.136728 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4719 04:46:10.143793 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4720 04:46:10.144322
4721 04:46:10.144659
4722 04:46:10.144966 ==
4723 04:46:10.147279 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 04:46:10.149964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 04:46:10.150481 ==
4726 04:46:10.150819
4727 04:46:10.151126
4728 04:46:10.153118 TX Vref Scan disable
4729 04:46:10.153538 == TX Byte 0 ==
4730 04:46:10.159318 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4731 04:46:10.163120 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4732 04:46:10.163588 == TX Byte 1 ==
4733 04:46:10.169375 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4734 04:46:10.172828 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4735 04:46:10.173257 ==
4736 04:46:10.176272 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 04:46:10.179520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 04:46:10.179945 ==
4739 04:46:10.182802
4740 04:46:10.183214
4741 04:46:10.183596 TX Vref Scan disable
4742 04:46:10.186028 == TX Byte 0 ==
4743 04:46:10.189425 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4744 04:46:10.196120 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4745 04:46:10.196544 == TX Byte 1 ==
4746 04:46:10.199480 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4747 04:46:10.206222 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4748 04:46:10.206771
4749 04:46:10.207244 [DATLAT]
4750 04:46:10.207649 Freq=600, CH1 RK1
4751 04:46:10.207959
4752 04:46:10.209337 DATLAT Default: 0x9
4753 04:46:10.209782 0, 0xFFFF, sum = 0
4754 04:46:10.212638 1, 0xFFFF, sum = 0
4755 04:46:10.215818 2, 0xFFFF, sum = 0
4756 04:46:10.216270 3, 0xFFFF, sum = 0
4757 04:46:10.219018 4, 0xFFFF, sum = 0
4758 04:46:10.219584 5, 0xFFFF, sum = 0
4759 04:46:10.222816 6, 0xFFFF, sum = 0
4760 04:46:10.223458 7, 0xFFFF, sum = 0
4761 04:46:10.226014 8, 0x0, sum = 1
4762 04:46:10.226709 9, 0x0, sum = 2
4763 04:46:10.229320 10, 0x0, sum = 3
4764 04:46:10.229966 11, 0x0, sum = 4
4765 04:46:10.230547 best_step = 9
4766 04:46:10.231015
4767 04:46:10.232506 ==
4768 04:46:10.235597 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 04:46:10.238967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 04:46:10.239423 ==
4771 04:46:10.239917 RX Vref Scan: 0
4772 04:46:10.240242
4773 04:46:10.242119 RX Vref 0 -> 0, step: 1
4774 04:46:10.242534
4775 04:46:10.245242 RX Delay -179 -> 252, step: 8
4776 04:46:10.251747 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4777 04:46:10.255200 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4778 04:46:10.258580 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4779 04:46:10.261702 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4780 04:46:10.268493 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4781 04:46:10.271813 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4782 04:46:10.275025 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4783 04:46:10.278042 iDelay=205, Bit 7, Center 40 (-115 ~ 196) 312
4784 04:46:10.281882 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4785 04:46:10.288286 iDelay=205, Bit 9, Center 28 (-123 ~ 180) 304
4786 04:46:10.291873 iDelay=205, Bit 10, Center 44 (-107 ~ 196) 304
4787 04:46:10.295095 iDelay=205, Bit 11, Center 32 (-123 ~ 188) 312
4788 04:46:10.298272 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4789 04:46:10.304705 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4790 04:46:10.308459 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4791 04:46:10.311544 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4792 04:46:10.312064 ==
4793 04:46:10.314709 Dram Type= 6, Freq= 0, CH_1, rank 1
4794 04:46:10.317890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4795 04:46:10.321112 ==
4796 04:46:10.321532 DQS Delay:
4797 04:46:10.321865 DQS0 = 0, DQS1 = 0
4798 04:46:10.325016 DQM Delay:
4799 04:46:10.325539 DQM0 = 41, DQM1 = 39
4800 04:46:10.325876 DQ Delay:
4801 04:46:10.327848 DQ0 =44, DQ1 =36, DQ2 =32, DQ3 =36
4802 04:46:10.331464 DQ4 =40, DQ5 =52, DQ6 =52, DQ7 =40
4803 04:46:10.334419 DQ8 =24, DQ9 =28, DQ10 =44, DQ11 =32
4804 04:46:10.337865 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4805 04:46:10.338390
4806 04:46:10.341461
4807 04:46:10.347799 [DQSOSCAuto] RK1, (LSB)MR18= 0x3359, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4808 04:46:10.350971 CH1 RK1: MR19=808, MR18=3359
4809 04:46:10.357667 CH1_RK1: MR19=0x808, MR18=0x3359, DQSOSC=393, MR23=63, INC=169, DEC=113
4810 04:46:10.361017 [RxdqsGatingPostProcess] freq 600
4811 04:46:10.364439 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4812 04:46:10.367507 Pre-setting of DQS Precalculation
4813 04:46:10.374362 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4814 04:46:10.380403 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4815 04:46:10.387277 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4816 04:46:10.387844
4817 04:46:10.388188
4818 04:46:10.390384 [Calibration Summary] 1200 Mbps
4819 04:46:10.390920 CH 0, Rank 0
4820 04:46:10.394061 SW Impedance : PASS
4821 04:46:10.396798 DUTY Scan : NO K
4822 04:46:10.397215 ZQ Calibration : PASS
4823 04:46:10.400303 Jitter Meter : NO K
4824 04:46:10.403728 CBT Training : PASS
4825 04:46:10.404244 Write leveling : PASS
4826 04:46:10.407305 RX DQS gating : PASS
4827 04:46:10.410771 RX DQ/DQS(RDDQC) : PASS
4828 04:46:10.411325 TX DQ/DQS : PASS
4829 04:46:10.414388 RX DATLAT : PASS
4830 04:46:10.416782 RX DQ/DQS(Engine): PASS
4831 04:46:10.417245 TX OE : NO K
4832 04:46:10.417613 All Pass.
4833 04:46:10.420347
4834 04:46:10.420900 CH 0, Rank 1
4835 04:46:10.423520 SW Impedance : PASS
4836 04:46:10.424069 DUTY Scan : NO K
4837 04:46:10.427478 ZQ Calibration : PASS
4838 04:46:10.430474 Jitter Meter : NO K
4839 04:46:10.431249 CBT Training : PASS
4840 04:46:10.433315 Write leveling : PASS
4841 04:46:10.433871 RX DQS gating : PASS
4842 04:46:10.436428 RX DQ/DQS(RDDQC) : PASS
4843 04:46:10.439822 TX DQ/DQS : PASS
4844 04:46:10.440382 RX DATLAT : PASS
4845 04:46:10.443635 RX DQ/DQS(Engine): PASS
4846 04:46:10.446351 TX OE : NO K
4847 04:46:10.446947 All Pass.
4848 04:46:10.447322
4849 04:46:10.447707 CH 1, Rank 0
4850 04:46:10.449714 SW Impedance : PASS
4851 04:46:10.452772 DUTY Scan : NO K
4852 04:46:10.453349 ZQ Calibration : PASS
4853 04:46:10.456091 Jitter Meter : NO K
4854 04:46:10.459773 CBT Training : PASS
4855 04:46:10.460327 Write leveling : PASS
4856 04:46:10.462867 RX DQS gating : PASS
4857 04:46:10.466581 RX DQ/DQS(RDDQC) : PASS
4858 04:46:10.467240 TX DQ/DQS : PASS
4859 04:46:10.469567 RX DATLAT : PASS
4860 04:46:10.472887 RX DQ/DQS(Engine): PASS
4861 04:46:10.473443 TX OE : NO K
4862 04:46:10.475744 All Pass.
4863 04:46:10.476205
4864 04:46:10.476568 CH 1, Rank 1
4865 04:46:10.479137 SW Impedance : PASS
4866 04:46:10.479662 DUTY Scan : NO K
4867 04:46:10.482748 ZQ Calibration : PASS
4868 04:46:10.485696 Jitter Meter : NO K
4869 04:46:10.486158 CBT Training : PASS
4870 04:46:10.489503 Write leveling : PASS
4871 04:46:10.492822 RX DQS gating : PASS
4872 04:46:10.493332 RX DQ/DQS(RDDQC) : PASS
4873 04:46:10.496102 TX DQ/DQS : PASS
4874 04:46:10.498963 RX DATLAT : PASS
4875 04:46:10.499450 RX DQ/DQS(Engine): PASS
4876 04:46:10.501736 TX OE : NO K
4877 04:46:10.502189 All Pass.
4878 04:46:10.502522
4879 04:46:10.505440 DramC Write-DBI off
4880 04:46:10.508819 PER_BANK_REFRESH: Hybrid Mode
4881 04:46:10.509234 TX_TRACKING: ON
4882 04:46:10.518562 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4883 04:46:10.522141 [FAST_K] Save calibration result to emmc
4884 04:46:10.525448 dramc_set_vcore_voltage set vcore to 662500
4885 04:46:10.528409 Read voltage for 933, 3
4886 04:46:10.528829 Vio18 = 0
4887 04:46:10.529167 Vcore = 662500
4888 04:46:10.531395 Vdram = 0
4889 04:46:10.531828 Vddq = 0
4890 04:46:10.532167 Vmddr = 0
4891 04:46:10.538036 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4892 04:46:10.541430 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4893 04:46:10.544483 MEM_TYPE=3, freq_sel=17
4894 04:46:10.548656 sv_algorithm_assistance_LP4_1600
4895 04:46:10.552591 ============ PULL DRAM RESETB DOWN ============
4896 04:46:10.558172 ========== PULL DRAM RESETB DOWN end =========
4897 04:46:10.561066 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4898 04:46:10.564625 ===================================
4899 04:46:10.568199 LPDDR4 DRAM CONFIGURATION
4900 04:46:10.571010 ===================================
4901 04:46:10.571550 EX_ROW_EN[0] = 0x0
4902 04:46:10.574282 EX_ROW_EN[1] = 0x0
4903 04:46:10.574698 LP4Y_EN = 0x0
4904 04:46:10.577773 WORK_FSP = 0x0
4905 04:46:10.578194 WL = 0x3
4906 04:46:10.580980 RL = 0x3
4907 04:46:10.581398 BL = 0x2
4908 04:46:10.584907 RPST = 0x0
4909 04:46:10.585326 RD_PRE = 0x0
4910 04:46:10.587630 WR_PRE = 0x1
4911 04:46:10.590888 WR_PST = 0x0
4912 04:46:10.591259 DBI_WR = 0x0
4913 04:46:10.594762 DBI_RD = 0x0
4914 04:46:10.595176 OTF = 0x1
4915 04:46:10.597392 ===================================
4916 04:46:10.600850 ===================================
4917 04:46:10.601279 ANA top config
4918 04:46:10.604079 ===================================
4919 04:46:10.607449 DLL_ASYNC_EN = 0
4920 04:46:10.610625 ALL_SLAVE_EN = 1
4921 04:46:10.614079 NEW_RANK_MODE = 1
4922 04:46:10.617013 DLL_IDLE_MODE = 1
4923 04:46:10.617430 LP45_APHY_COMB_EN = 1
4924 04:46:10.620743 TX_ODT_DIS = 1
4925 04:46:10.623710 NEW_8X_MODE = 1
4926 04:46:10.627088 ===================================
4927 04:46:10.630295 ===================================
4928 04:46:10.633515 data_rate = 1866
4929 04:46:10.637386 CKR = 1
4930 04:46:10.640401 DQ_P2S_RATIO = 8
4931 04:46:10.643237 ===================================
4932 04:46:10.643707 CA_P2S_RATIO = 8
4933 04:46:10.647022 DQ_CA_OPEN = 0
4934 04:46:10.650567 DQ_SEMI_OPEN = 0
4935 04:46:10.653203 CA_SEMI_OPEN = 0
4936 04:46:10.656840 CA_FULL_RATE = 0
4937 04:46:10.660149 DQ_CKDIV4_EN = 1
4938 04:46:10.660565 CA_CKDIV4_EN = 1
4939 04:46:10.663675 CA_PREDIV_EN = 0
4940 04:46:10.666396 PH8_DLY = 0
4941 04:46:10.670202 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4942 04:46:10.673094 DQ_AAMCK_DIV = 4
4943 04:46:10.676745 CA_AAMCK_DIV = 4
4944 04:46:10.677164 CA_ADMCK_DIV = 4
4945 04:46:10.680009 DQ_TRACK_CA_EN = 0
4946 04:46:10.683465 CA_PICK = 933
4947 04:46:10.686247 CA_MCKIO = 933
4948 04:46:10.690306 MCKIO_SEMI = 0
4949 04:46:10.693356 PLL_FREQ = 3732
4950 04:46:10.696421 DQ_UI_PI_RATIO = 32
4951 04:46:10.699915 CA_UI_PI_RATIO = 0
4952 04:46:10.703010 ===================================
4953 04:46:10.706598 ===================================
4954 04:46:10.707113 memory_type:LPDDR4
4955 04:46:10.709885 GP_NUM : 10
4956 04:46:10.710397 SRAM_EN : 1
4957 04:46:10.712741 MD32_EN : 0
4958 04:46:10.716040 ===================================
4959 04:46:10.719600 [ANA_INIT] >>>>>>>>>>>>>>
4960 04:46:10.722967 <<<<<< [CONFIGURE PHASE]: ANA_TX
4961 04:46:10.726258 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4962 04:46:10.729574 ===================================
4963 04:46:10.733026 data_rate = 1866,PCW = 0X8f00
4964 04:46:10.735803 ===================================
4965 04:46:10.739082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4966 04:46:10.742442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4967 04:46:10.749489 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4968 04:46:10.752324 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4969 04:46:10.755678 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4970 04:46:10.759069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4971 04:46:10.762097 [ANA_INIT] flow start
4972 04:46:10.766182 [ANA_INIT] PLL >>>>>>>>
4973 04:46:10.766751 [ANA_INIT] PLL <<<<<<<<
4974 04:46:10.769232 [ANA_INIT] MIDPI >>>>>>>>
4975 04:46:10.772047 [ANA_INIT] MIDPI <<<<<<<<
4976 04:46:10.775283 [ANA_INIT] DLL >>>>>>>>
4977 04:46:10.775753 [ANA_INIT] flow end
4978 04:46:10.778867 ============ LP4 DIFF to SE enter ============
4979 04:46:10.785370 ============ LP4 DIFF to SE exit ============
4980 04:46:10.785887 [ANA_INIT] <<<<<<<<<<<<<
4981 04:46:10.788804 [Flow] Enable top DCM control >>>>>
4982 04:46:10.792006 [Flow] Enable top DCM control <<<<<
4983 04:46:10.794833 Enable DLL master slave shuffle
4984 04:46:10.801775 ==============================================================
4985 04:46:10.804825 Gating Mode config
4986 04:46:10.807904 ==============================================================
4987 04:46:10.811259 Config description:
4988 04:46:10.821213 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4989 04:46:10.827906 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4990 04:46:10.830956 SELPH_MODE 0: By rank 1: By Phase
4991 04:46:10.837598 ==============================================================
4992 04:46:10.841174 GAT_TRACK_EN = 1
4993 04:46:10.844853 RX_GATING_MODE = 2
4994 04:46:10.847905 RX_GATING_TRACK_MODE = 2
4995 04:46:10.848326 SELPH_MODE = 1
4996 04:46:10.851204 PICG_EARLY_EN = 1
4997 04:46:10.854621 VALID_LAT_VALUE = 1
4998 04:46:10.860669 ==============================================================
4999 04:46:10.864164 Enter into Gating configuration >>>>
5000 04:46:10.867804 Exit from Gating configuration <<<<
5001 04:46:10.870554 Enter into DVFS_PRE_config >>>>>
5002 04:46:10.880700 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5003 04:46:10.884047 Exit from DVFS_PRE_config <<<<<
5004 04:46:10.887521 Enter into PICG configuration >>>>
5005 04:46:10.890763 Exit from PICG configuration <<<<
5006 04:46:10.893882 [RX_INPUT] configuration >>>>>
5007 04:46:10.897251 [RX_INPUT] configuration <<<<<
5008 04:46:10.903976 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5009 04:46:10.906921 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5010 04:46:10.913470 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5011 04:46:10.919983 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5012 04:46:10.926584 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5013 04:46:10.933282 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5014 04:46:10.936299 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5015 04:46:10.939423 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5016 04:46:10.942700 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5017 04:46:10.949866 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5018 04:46:10.953393 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5019 04:46:10.956380 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5020 04:46:10.959176 ===================================
5021 04:46:10.962684 LPDDR4 DRAM CONFIGURATION
5022 04:46:10.965741 ===================================
5023 04:46:10.969343 EX_ROW_EN[0] = 0x0
5024 04:46:10.969859 EX_ROW_EN[1] = 0x0
5025 04:46:10.972344 LP4Y_EN = 0x0
5026 04:46:10.972763 WORK_FSP = 0x0
5027 04:46:10.976276 WL = 0x3
5028 04:46:10.976780 RL = 0x3
5029 04:46:10.979281 BL = 0x2
5030 04:46:10.979740 RPST = 0x0
5031 04:46:10.982467 RD_PRE = 0x0
5032 04:46:10.982882 WR_PRE = 0x1
5033 04:46:10.985786 WR_PST = 0x0
5034 04:46:10.986202 DBI_WR = 0x0
5035 04:46:10.989289 DBI_RD = 0x0
5036 04:46:10.989799 OTF = 0x1
5037 04:46:10.992195 ===================================
5038 04:46:10.998604 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5039 04:46:11.001912 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5040 04:46:11.005264 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5041 04:46:11.008741 ===================================
5042 04:46:11.011899 LPDDR4 DRAM CONFIGURATION
5043 04:46:11.015027 ===================================
5044 04:46:11.018534 EX_ROW_EN[0] = 0x10
5045 04:46:11.019043 EX_ROW_EN[1] = 0x0
5046 04:46:11.021871 LP4Y_EN = 0x0
5047 04:46:11.022287 WORK_FSP = 0x0
5048 04:46:11.025427 WL = 0x3
5049 04:46:11.025904 RL = 0x3
5050 04:46:11.028066 BL = 0x2
5051 04:46:11.028483 RPST = 0x0
5052 04:46:11.031706 RD_PRE = 0x0
5053 04:46:11.032122 WR_PRE = 0x1
5054 04:46:11.035034 WR_PST = 0x0
5055 04:46:11.035586 DBI_WR = 0x0
5056 04:46:11.038320 DBI_RD = 0x0
5057 04:46:11.041810 OTF = 0x1
5058 04:46:11.045147 ===================================
5059 04:46:11.047810 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5060 04:46:11.053331 nWR fixed to 30
5061 04:46:11.056870 [ModeRegInit_LP4] CH0 RK0
5062 04:46:11.057289 [ModeRegInit_LP4] CH0 RK1
5063 04:46:11.060210 [ModeRegInit_LP4] CH1 RK0
5064 04:46:11.063291 [ModeRegInit_LP4] CH1 RK1
5065 04:46:11.063753 match AC timing 9
5066 04:46:11.070235 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5067 04:46:11.072934 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5068 04:46:11.076713 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5069 04:46:11.083264 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5070 04:46:11.086471 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5071 04:46:11.086988 ==
5072 04:46:11.089712 Dram Type= 6, Freq= 0, CH_0, rank 0
5073 04:46:11.093179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5074 04:46:11.093698 ==
5075 04:46:11.099551 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5076 04:46:11.106042 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5077 04:46:11.109580 [CA 0] Center 37 (7~68) winsize 62
5078 04:46:11.112963 [CA 1] Center 37 (7~68) winsize 62
5079 04:46:11.115697 [CA 2] Center 34 (4~65) winsize 62
5080 04:46:11.119187 [CA 3] Center 34 (4~65) winsize 62
5081 04:46:11.122591 [CA 4] Center 33 (2~64) winsize 63
5082 04:46:11.125572 [CA 5] Center 32 (2~63) winsize 62
5083 04:46:11.125993
5084 04:46:11.129817 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5085 04:46:11.130356
5086 04:46:11.132513 [CATrainingPosCal] consider 1 rank data
5087 04:46:11.135673 u2DelayCellTimex100 = 270/100 ps
5088 04:46:11.139320 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5089 04:46:11.142352 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5090 04:46:11.146284 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5091 04:46:11.151979 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5092 04:46:11.155641 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5093 04:46:11.158859 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5094 04:46:11.159278
5095 04:46:11.162468 CA PerBit enable=1, Macro0, CA PI delay=32
5096 04:46:11.162885
5097 04:46:11.165507 [CBTSetCACLKResult] CA Dly = 32
5098 04:46:11.165929 CS Dly: 6 (0~37)
5099 04:46:11.166261 ==
5100 04:46:11.168785 Dram Type= 6, Freq= 0, CH_0, rank 1
5101 04:46:11.175471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 04:46:11.175892 ==
5103 04:46:11.178401 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5104 04:46:11.185371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5105 04:46:11.188726 [CA 0] Center 38 (8~69) winsize 62
5106 04:46:11.192228 [CA 1] Center 37 (7~68) winsize 62
5107 04:46:11.194868 [CA 2] Center 34 (4~65) winsize 62
5108 04:46:11.198549 [CA 3] Center 34 (4~65) winsize 62
5109 04:46:11.201492 [CA 4] Center 33 (3~64) winsize 62
5110 04:46:11.205034 [CA 5] Center 33 (3~63) winsize 61
5111 04:46:11.205451
5112 04:46:11.208402 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5113 04:46:11.208840
5114 04:46:11.211560 [CATrainingPosCal] consider 2 rank data
5115 04:46:11.214746 u2DelayCellTimex100 = 270/100 ps
5116 04:46:11.218248 CA0 delay=38 (8~68),Diff = 5 PI (31 cell)
5117 04:46:11.224598 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5118 04:46:11.228174 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5119 04:46:11.231388 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5120 04:46:11.234803 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5121 04:46:11.238334 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5122 04:46:11.238848
5123 04:46:11.241674 CA PerBit enable=1, Macro0, CA PI delay=33
5124 04:46:11.242350
5125 04:46:11.244864 [CBTSetCACLKResult] CA Dly = 33
5126 04:46:11.247913 CS Dly: 7 (0~39)
5127 04:46:11.248329
5128 04:46:11.251560 ----->DramcWriteLeveling(PI) begin...
5129 04:46:11.252236 ==
5130 04:46:11.254351 Dram Type= 6, Freq= 0, CH_0, rank 0
5131 04:46:11.257939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 04:46:11.258469 ==
5133 04:46:11.260725 Write leveling (Byte 0): 33 => 33
5134 04:46:11.264067 Write leveling (Byte 1): 25 => 25
5135 04:46:11.267227 DramcWriteLeveling(PI) end<-----
5136 04:46:11.267815
5137 04:46:11.268286 ==
5138 04:46:11.270735 Dram Type= 6, Freq= 0, CH_0, rank 0
5139 04:46:11.274071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5140 04:46:11.274591 ==
5141 04:46:11.277467 [Gating] SW mode calibration
5142 04:46:11.283709 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5143 04:46:11.290955 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5144 04:46:11.293562 0 14 0 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
5145 04:46:11.300575 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5146 04:46:11.303838 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 04:46:11.307107 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5148 04:46:11.310002 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 04:46:11.316910 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 04:46:11.320371 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 04:46:11.323468 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 1)
5152 04:46:11.329871 0 15 0 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
5153 04:46:11.333735 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5154 04:46:11.336734 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 04:46:11.343469 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5156 04:46:11.346678 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 04:46:11.350005 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 04:46:11.356767 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5159 04:46:11.359908 0 15 28 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
5160 04:46:11.362856 1 0 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
5161 04:46:11.369429 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 04:46:11.373815 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 04:46:11.376409 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 04:46:11.382934 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 04:46:11.386246 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 04:46:11.389459 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 04:46:11.396148 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5168 04:46:11.398954 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5169 04:46:11.405902 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 04:46:11.409444 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 04:46:11.412531 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 04:46:11.419018 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 04:46:11.422086 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 04:46:11.425255 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 04:46:11.432000 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 04:46:11.435219 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 04:46:11.438900 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 04:46:11.445140 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 04:46:11.448728 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 04:46:11.452287 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 04:46:11.458555 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 04:46:11.461617 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 04:46:11.465353 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5184 04:46:11.471637 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 04:46:11.472157 Total UI for P1: 0, mck2ui 16
5186 04:46:11.478647 best dqsien dly found for B0: ( 1, 2, 28)
5187 04:46:11.479172 Total UI for P1: 0, mck2ui 16
5188 04:46:11.485305 best dqsien dly found for B1: ( 1, 2, 30)
5189 04:46:11.488061 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5190 04:46:11.491656 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5191 04:46:11.492075
5192 04:46:11.494513 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5193 04:46:11.497897 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5194 04:46:11.501741 [Gating] SW calibration Done
5195 04:46:11.502163 ==
5196 04:46:11.504560 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 04:46:11.507517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 04:46:11.508086 ==
5199 04:46:11.510780 RX Vref Scan: 0
5200 04:46:11.511197
5201 04:46:11.511563 RX Vref 0 -> 0, step: 1
5202 04:46:11.511878
5203 04:46:11.514370 RX Delay -80 -> 252, step: 8
5204 04:46:11.520812 iDelay=200, Bit 0, Center 107 (16 ~ 199) 184
5205 04:46:11.524217 iDelay=200, Bit 1, Center 107 (16 ~ 199) 184
5206 04:46:11.527358 iDelay=200, Bit 2, Center 99 (8 ~ 191) 184
5207 04:46:11.530501 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5208 04:46:11.534302 iDelay=200, Bit 4, Center 107 (16 ~ 199) 184
5209 04:46:11.537054 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5210 04:46:11.543647 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5211 04:46:11.547188 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5212 04:46:11.550425 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5213 04:46:11.553989 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5214 04:46:11.556536 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5215 04:46:11.563510 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5216 04:46:11.566823 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5217 04:46:11.570110 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5218 04:46:11.573603 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5219 04:46:11.576400 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5220 04:46:11.579914 ==
5221 04:46:11.580541 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 04:46:11.586725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 04:46:11.587283 ==
5224 04:46:11.587755 DQS Delay:
5225 04:46:11.589837 DQS0 = 0, DQS1 = 0
5226 04:46:11.590389 DQM Delay:
5227 04:46:11.593282 DQM0 = 103, DQM1 = 89
5228 04:46:11.593834 DQ Delay:
5229 04:46:11.596485 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5230 04:46:11.599894 DQ4 =107, DQ5 =91, DQ6 =107, DQ7 =107
5231 04:46:11.603248 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =87
5232 04:46:11.606507 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5233 04:46:11.607069
5234 04:46:11.607485
5235 04:46:11.607835 ==
5236 04:46:11.609425 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 04:46:11.612703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 04:46:11.613127 ==
5239 04:46:11.616032
5240 04:46:11.616544
5241 04:46:11.616876 TX Vref Scan disable
5242 04:46:11.619537 == TX Byte 0 ==
5243 04:46:11.623003 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5244 04:46:11.625831 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5245 04:46:11.629070 == TX Byte 1 ==
5246 04:46:11.632940 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5247 04:46:11.636476 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5248 04:46:11.639724 ==
5249 04:46:11.640291 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 04:46:11.646062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 04:46:11.646631 ==
5252 04:46:11.647112
5253 04:46:11.647652
5254 04:46:11.648953 TX Vref Scan disable
5255 04:46:11.649422 == TX Byte 0 ==
5256 04:46:11.655652 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5257 04:46:11.658670 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5258 04:46:11.659144 == TX Byte 1 ==
5259 04:46:11.665321 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5260 04:46:11.668907 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5261 04:46:11.669350
5262 04:46:11.669781 [DATLAT]
5263 04:46:11.671996 Freq=933, CH0 RK0
5264 04:46:11.672424
5265 04:46:11.672864 DATLAT Default: 0xd
5266 04:46:11.675257 0, 0xFFFF, sum = 0
5267 04:46:11.675747 1, 0xFFFF, sum = 0
5268 04:46:11.678734 2, 0xFFFF, sum = 0
5269 04:46:11.681708 3, 0xFFFF, sum = 0
5270 04:46:11.682238 4, 0xFFFF, sum = 0
5271 04:46:11.685063 5, 0xFFFF, sum = 0
5272 04:46:11.685611 6, 0xFFFF, sum = 0
5273 04:46:11.688277 7, 0xFFFF, sum = 0
5274 04:46:11.688723 8, 0xFFFF, sum = 0
5275 04:46:11.691921 9, 0xFFFF, sum = 0
5276 04:46:11.692451 10, 0x0, sum = 1
5277 04:46:11.695013 11, 0x0, sum = 2
5278 04:46:11.695618 12, 0x0, sum = 3
5279 04:46:11.698305 13, 0x0, sum = 4
5280 04:46:11.698838 best_step = 11
5281 04:46:11.699281
5282 04:46:11.699736 ==
5283 04:46:11.701707 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 04:46:11.704715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 04:46:11.705253 ==
5286 04:46:11.708650 RX Vref Scan: 1
5287 04:46:11.709168
5288 04:46:11.711619 RX Vref 0 -> 0, step: 1
5289 04:46:11.712035
5290 04:46:11.712365 RX Delay -61 -> 252, step: 4
5291 04:46:11.712672
5292 04:46:11.714860 Set Vref, RX VrefLevel [Byte0]: 57
5293 04:46:11.718313 [Byte1]: 49
5294 04:46:11.723250
5295 04:46:11.723846 Final RX Vref Byte 0 = 57 to rank0
5296 04:46:11.726457 Final RX Vref Byte 1 = 49 to rank0
5297 04:46:11.729637 Final RX Vref Byte 0 = 57 to rank1
5298 04:46:11.732897 Final RX Vref Byte 1 = 49 to rank1==
5299 04:46:11.736648 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 04:46:11.743086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 04:46:11.743731 ==
5302 04:46:11.744198 DQS Delay:
5303 04:46:11.745797 DQS0 = 0, DQS1 = 0
5304 04:46:11.746272 DQM Delay:
5305 04:46:11.746761 DQM0 = 103, DQM1 = 90
5306 04:46:11.748978 DQ Delay:
5307 04:46:11.752445 DQ0 =104, DQ1 =102, DQ2 =98, DQ3 =100
5308 04:46:11.755621 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =108
5309 04:46:11.758780 DQ8 =80, DQ9 =76, DQ10 =94, DQ11 =86
5310 04:46:11.762275 DQ12 =98, DQ13 =92, DQ14 =98, DQ15 =98
5311 04:46:11.762698
5312 04:46:11.763029
5313 04:46:11.768968 [DQSOSCAuto] RK0, (LSB)MR18= 0x1913, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5314 04:46:11.772186 CH0 RK0: MR19=505, MR18=1913
5315 04:46:11.778704 CH0_RK0: MR19=0x505, MR18=0x1913, DQSOSC=413, MR23=63, INC=63, DEC=42
5316 04:46:11.779229
5317 04:46:11.781980 ----->DramcWriteLeveling(PI) begin...
5318 04:46:11.782510 ==
5319 04:46:11.785352 Dram Type= 6, Freq= 0, CH_0, rank 1
5320 04:46:11.788491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 04:46:11.791603 ==
5322 04:46:11.792027 Write leveling (Byte 0): 30 => 30
5323 04:46:11.795499 Write leveling (Byte 1): 28 => 28
5324 04:46:11.798802 DramcWriteLeveling(PI) end<-----
5325 04:46:11.799331
5326 04:46:11.799715 ==
5327 04:46:11.801740 Dram Type= 6, Freq= 0, CH_0, rank 1
5328 04:46:11.808393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 04:46:11.808952 ==
5330 04:46:11.811770 [Gating] SW mode calibration
5331 04:46:11.817959 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5332 04:46:11.821546 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5333 04:46:11.827677 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
5334 04:46:11.831100 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 04:46:11.834454 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 04:46:11.840897 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 04:46:11.844484 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 04:46:11.847655 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 04:46:11.854546 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5340 04:46:11.858500 0 14 28 | B1->B0 | 3333 2c2c | 1 0 | (1 1) (1 0)
5341 04:46:11.861135 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
5342 04:46:11.867543 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5343 04:46:11.870827 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 04:46:11.874346 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 04:46:11.880357 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 04:46:11.883815 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 04:46:11.887390 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
5348 04:46:11.893624 0 15 28 | B1->B0 | 2525 3a3a | 1 0 | (0 0) (1 1)
5349 04:46:11.897075 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5350 04:46:11.900755 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 04:46:11.907100 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 04:46:11.910336 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 04:46:11.913407 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 04:46:11.920461 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 04:46:11.923988 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5356 04:46:11.926824 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5357 04:46:11.933242 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5358 04:46:11.937019 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 04:46:11.940073 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 04:46:11.946656 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 04:46:11.950049 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 04:46:11.953105 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 04:46:11.959519 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 04:46:11.963183 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 04:46:11.966516 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 04:46:11.973352 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 04:46:11.976564 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 04:46:11.980156 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 04:46:11.986363 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 04:46:11.989789 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 04:46:11.992637 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5372 04:46:11.999156 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5373 04:46:12.002768 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 04:46:12.006382 Total UI for P1: 0, mck2ui 16
5375 04:46:12.009273 best dqsien dly found for B0: ( 1, 2, 26)
5376 04:46:12.012547 Total UI for P1: 0, mck2ui 16
5377 04:46:12.016357 best dqsien dly found for B1: ( 1, 2, 28)
5378 04:46:12.019091 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5379 04:46:12.022124 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5380 04:46:12.022537
5381 04:46:12.025806 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5382 04:46:12.029166 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5383 04:46:12.032411 [Gating] SW calibration Done
5384 04:46:12.032824 ==
5385 04:46:12.035789 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 04:46:12.042210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 04:46:12.042707 ==
5388 04:46:12.043170 RX Vref Scan: 0
5389 04:46:12.043610
5390 04:46:12.045284 RX Vref 0 -> 0, step: 1
5391 04:46:12.045700
5392 04:46:12.049161 RX Delay -80 -> 252, step: 8
5393 04:46:12.052225 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5394 04:46:12.055718 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5395 04:46:12.058753 iDelay=200, Bit 2, Center 95 (8 ~ 183) 176
5396 04:46:12.062192 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5397 04:46:12.068825 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5398 04:46:12.071928 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5399 04:46:12.075266 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5400 04:46:12.078749 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5401 04:46:12.081934 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5402 04:46:12.084871 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5403 04:46:12.091792 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5404 04:46:12.095300 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5405 04:46:12.098889 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5406 04:46:12.101383 iDelay=200, Bit 13, Center 95 (8 ~ 183) 176
5407 04:46:12.104701 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5408 04:46:12.111451 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5409 04:46:12.111974 ==
5410 04:46:12.114626 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 04:46:12.117675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 04:46:12.118096 ==
5413 04:46:12.118428 DQS Delay:
5414 04:46:12.121457 DQS0 = 0, DQS1 = 0
5415 04:46:12.121987 DQM Delay:
5416 04:46:12.124304 DQM0 = 100, DQM1 = 88
5417 04:46:12.124720 DQ Delay:
5418 04:46:12.127459 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =99
5419 04:46:12.131125 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =107
5420 04:46:12.134505 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5421 04:46:12.137360 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =91
5422 04:46:12.137786
5423 04:46:12.138121
5424 04:46:12.138429 ==
5425 04:46:12.140808 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 04:46:12.147323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 04:46:12.147892 ==
5428 04:46:12.148231
5429 04:46:12.148538
5430 04:46:12.148832 TX Vref Scan disable
5431 04:46:12.151120 == TX Byte 0 ==
5432 04:46:12.154406 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5433 04:46:12.161059 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5434 04:46:12.161484 == TX Byte 1 ==
5435 04:46:12.164321 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5436 04:46:12.170893 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5437 04:46:12.171455 ==
5438 04:46:12.174153 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 04:46:12.177826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 04:46:12.178383 ==
5441 04:46:12.178752
5442 04:46:12.179090
5443 04:46:12.180519 TX Vref Scan disable
5444 04:46:12.180982 == TX Byte 0 ==
5445 04:46:12.187345 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5446 04:46:12.190947 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5447 04:46:12.191556 == TX Byte 1 ==
5448 04:46:12.197836 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5449 04:46:12.200436 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5450 04:46:12.200907
5451 04:46:12.201275 [DATLAT]
5452 04:46:12.203779 Freq=933, CH0 RK1
5453 04:46:12.204349
5454 04:46:12.204912 DATLAT Default: 0xb
5455 04:46:12.207293 0, 0xFFFF, sum = 0
5456 04:46:12.210742 1, 0xFFFF, sum = 0
5457 04:46:12.211282 2, 0xFFFF, sum = 0
5458 04:46:12.213324 3, 0xFFFF, sum = 0
5459 04:46:12.213751 4, 0xFFFF, sum = 0
5460 04:46:12.216581 5, 0xFFFF, sum = 0
5461 04:46:12.217008 6, 0xFFFF, sum = 0
5462 04:46:12.219842 7, 0xFFFF, sum = 0
5463 04:46:12.220266 8, 0xFFFF, sum = 0
5464 04:46:12.223660 9, 0xFFFF, sum = 0
5465 04:46:12.224084 10, 0x0, sum = 1
5466 04:46:12.226727 11, 0x0, sum = 2
5467 04:46:12.227329 12, 0x0, sum = 3
5468 04:46:12.230482 13, 0x0, sum = 4
5469 04:46:12.230905 best_step = 11
5470 04:46:12.231236
5471 04:46:12.231631 ==
5472 04:46:12.233414 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 04:46:12.236327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 04:46:12.236767 ==
5475 04:46:12.239952 RX Vref Scan: 0
5476 04:46:12.240386
5477 04:46:12.242967 RX Vref 0 -> 0, step: 1
5478 04:46:12.243438
5479 04:46:12.243828 RX Delay -61 -> 252, step: 4
5480 04:46:12.251600 iDelay=199, Bit 0, Center 100 (15 ~ 186) 172
5481 04:46:12.254643 iDelay=199, Bit 1, Center 102 (15 ~ 190) 176
5482 04:46:12.257611 iDelay=199, Bit 2, Center 96 (11 ~ 182) 172
5483 04:46:12.260933 iDelay=199, Bit 3, Center 98 (11 ~ 186) 176
5484 04:46:12.263983 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5485 04:46:12.270898 iDelay=199, Bit 5, Center 92 (7 ~ 178) 172
5486 04:46:12.274440 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5487 04:46:12.278043 iDelay=199, Bit 7, Center 108 (23 ~ 194) 172
5488 04:46:12.281193 iDelay=199, Bit 8, Center 80 (-5 ~ 166) 172
5489 04:46:12.284616 iDelay=199, Bit 9, Center 76 (-9 ~ 162) 172
5490 04:46:12.291269 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5491 04:46:12.293976 iDelay=199, Bit 11, Center 82 (-1 ~ 166) 168
5492 04:46:12.297258 iDelay=199, Bit 12, Center 94 (11 ~ 178) 168
5493 04:46:12.300514 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5494 04:46:12.303898 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5495 04:46:12.310486 iDelay=199, Bit 15, Center 94 (11 ~ 178) 168
5496 04:46:12.311018 ==
5497 04:46:12.314516 Dram Type= 6, Freq= 0, CH_0, rank 1
5498 04:46:12.317200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 04:46:12.317663 ==
5500 04:46:12.318027 DQS Delay:
5501 04:46:12.320461 DQS0 = 0, DQS1 = 0
5502 04:46:12.321020 DQM Delay:
5503 04:46:12.323326 DQM0 = 101, DQM1 = 89
5504 04:46:12.323832 DQ Delay:
5505 04:46:12.326913 DQ0 =100, DQ1 =102, DQ2 =96, DQ3 =98
5506 04:46:12.330105 DQ4 =104, DQ5 =92, DQ6 =110, DQ7 =108
5507 04:46:12.333855 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =82
5508 04:46:12.336542 DQ12 =94, DQ13 =96, DQ14 =102, DQ15 =94
5509 04:46:12.337106
5510 04:46:12.337480
5511 04:46:12.346649 [DQSOSCAuto] RK1, (LSB)MR18= 0x110d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5512 04:46:12.349475 CH0 RK1: MR19=505, MR18=110D
5513 04:46:12.353050 CH0_RK1: MR19=0x505, MR18=0x110D, DQSOSC=416, MR23=63, INC=62, DEC=41
5514 04:46:12.356495 [RxdqsGatingPostProcess] freq 933
5515 04:46:12.362937 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5516 04:46:12.366311 best DQS0 dly(2T, 0.5T) = (0, 10)
5517 04:46:12.369350 best DQS1 dly(2T, 0.5T) = (0, 10)
5518 04:46:12.373030 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5519 04:46:12.376328 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5520 04:46:12.379405 best DQS0 dly(2T, 0.5T) = (0, 10)
5521 04:46:12.382556 best DQS1 dly(2T, 0.5T) = (0, 10)
5522 04:46:12.385865 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5523 04:46:12.389469 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5524 04:46:12.392454 Pre-setting of DQS Precalculation
5525 04:46:12.395465 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5526 04:46:12.396028 ==
5527 04:46:12.399343 Dram Type= 6, Freq= 0, CH_1, rank 0
5528 04:46:12.402553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 04:46:12.405937 ==
5530 04:46:12.408794 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5531 04:46:12.415933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5532 04:46:12.419020 [CA 0] Center 36 (6~67) winsize 62
5533 04:46:12.422518 [CA 1] Center 36 (6~67) winsize 62
5534 04:46:12.425471 [CA 2] Center 34 (4~65) winsize 62
5535 04:46:12.429201 [CA 3] Center 34 (4~64) winsize 61
5536 04:46:12.432028 [CA 4] Center 34 (4~65) winsize 62
5537 04:46:12.435319 [CA 5] Center 34 (4~64) winsize 61
5538 04:46:12.435895
5539 04:46:12.438714 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5540 04:46:12.439155
5541 04:46:12.441877 [CATrainingPosCal] consider 1 rank data
5542 04:46:12.445141 u2DelayCellTimex100 = 270/100 ps
5543 04:46:12.448894 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5544 04:46:12.451959 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5545 04:46:12.455433 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5546 04:46:12.461697 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5547 04:46:12.465591 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5548 04:46:12.468392 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5549 04:46:12.468855
5550 04:46:12.471097 CA PerBit enable=1, Macro0, CA PI delay=34
5551 04:46:12.471551
5552 04:46:12.474576 [CBTSetCACLKResult] CA Dly = 34
5553 04:46:12.474997 CS Dly: 5 (0~36)
5554 04:46:12.478097 ==
5555 04:46:12.478628 Dram Type= 6, Freq= 0, CH_1, rank 1
5556 04:46:12.484856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 04:46:12.485400 ==
5558 04:46:12.488476 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5559 04:46:12.494250 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5560 04:46:12.498533 [CA 0] Center 36 (6~67) winsize 62
5561 04:46:12.501533 [CA 1] Center 36 (6~67) winsize 62
5562 04:46:12.504589 [CA 2] Center 34 (4~65) winsize 62
5563 04:46:12.507677 [CA 3] Center 33 (3~64) winsize 62
5564 04:46:12.510821 [CA 4] Center 34 (4~65) winsize 62
5565 04:46:12.514564 [CA 5] Center 33 (3~64) winsize 62
5566 04:46:12.515041
5567 04:46:12.517713 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5568 04:46:12.518157
5569 04:46:12.520837 [CATrainingPosCal] consider 2 rank data
5570 04:46:12.524425 u2DelayCellTimex100 = 270/100 ps
5571 04:46:12.531108 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5572 04:46:12.534272 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5573 04:46:12.537272 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5574 04:46:12.540854 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5575 04:46:12.544062 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5576 04:46:12.547776 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5577 04:46:12.548321
5578 04:46:12.550629 CA PerBit enable=1, Macro0, CA PI delay=34
5579 04:46:12.551113
5580 04:46:12.554620 [CBTSetCACLKResult] CA Dly = 34
5581 04:46:12.557162 CS Dly: 6 (0~38)
5582 04:46:12.557588
5583 04:46:12.560665 ----->DramcWriteLeveling(PI) begin...
5584 04:46:12.561133 ==
5585 04:46:12.563900 Dram Type= 6, Freq= 0, CH_1, rank 0
5586 04:46:12.566809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 04:46:12.567260 ==
5588 04:46:12.570304 Write leveling (Byte 0): 23 => 23
5589 04:46:12.573718 Write leveling (Byte 1): 27 => 27
5590 04:46:12.576594 DramcWriteLeveling(PI) end<-----
5591 04:46:12.577022
5592 04:46:12.577356 ==
5593 04:46:12.580369 Dram Type= 6, Freq= 0, CH_1, rank 0
5594 04:46:12.583559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5595 04:46:12.584090 ==
5596 04:46:12.586832 [Gating] SW mode calibration
5597 04:46:12.593094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5598 04:46:12.599679 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5599 04:46:12.603161 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5600 04:46:12.609720 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 04:46:12.612773 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 04:46:12.616474 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 04:46:12.623190 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 04:46:12.626124 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 04:46:12.628988 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5606 04:46:12.635679 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (1 0)
5607 04:46:12.639198 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 04:46:12.642659 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 04:46:12.648861 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 04:46:12.652106 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 04:46:12.655707 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 04:46:12.661896 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 04:46:12.665313 0 15 24 | B1->B0 | 2424 2929 | 0 1 | (0 0) (0 0)
5614 04:46:12.668571 0 15 28 | B1->B0 | 3333 3c3c | 0 1 | (0 0) (0 0)
5615 04:46:12.675265 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 04:46:12.678373 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 04:46:12.681565 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 04:46:12.688563 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 04:46:12.691683 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 04:46:12.694436 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 04:46:12.701990 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5622 04:46:12.704629 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5623 04:46:12.707536 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5624 04:46:12.714593 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 04:46:12.717608 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 04:46:12.720750 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 04:46:12.728130 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 04:46:12.731149 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 04:46:12.734819 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 04:46:12.740712 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 04:46:12.743852 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 04:46:12.747346 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 04:46:12.754423 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 04:46:12.757233 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 04:46:12.760873 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 04:46:12.767755 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 04:46:12.770731 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5638 04:46:12.774176 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5639 04:46:12.780619 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 04:46:12.784194 Total UI for P1: 0, mck2ui 16
5641 04:46:12.787275 best dqsien dly found for B0: ( 1, 2, 26)
5642 04:46:12.790812 Total UI for P1: 0, mck2ui 16
5643 04:46:12.793605 best dqsien dly found for B1: ( 1, 2, 26)
5644 04:46:12.797337 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5645 04:46:12.800386 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5646 04:46:12.800961
5647 04:46:12.803746 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5648 04:46:12.806787 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5649 04:46:12.810186 [Gating] SW calibration Done
5650 04:46:12.810764 ==
5651 04:46:12.813193 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 04:46:12.816551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 04:46:12.817030 ==
5654 04:46:12.820156 RX Vref Scan: 0
5655 04:46:12.820633
5656 04:46:12.823222 RX Vref 0 -> 0, step: 1
5657 04:46:12.823730
5658 04:46:12.824170 RX Delay -80 -> 252, step: 8
5659 04:46:12.829906 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5660 04:46:12.833588 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5661 04:46:12.836625 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5662 04:46:12.839918 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5663 04:46:12.843478 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5664 04:46:12.846446 iDelay=208, Bit 5, Center 103 (8 ~ 199) 192
5665 04:46:12.852854 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5666 04:46:12.856111 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5667 04:46:12.859730 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5668 04:46:12.863036 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5669 04:46:12.866113 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5670 04:46:12.872749 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5671 04:46:12.876532 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5672 04:46:12.879145 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5673 04:46:12.882731 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5674 04:46:12.886054 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5675 04:46:12.889205 ==
5676 04:46:12.892415 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 04:46:12.895722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 04:46:12.896144 ==
5679 04:46:12.896480 DQS Delay:
5680 04:46:12.899001 DQS0 = 0, DQS1 = 0
5681 04:46:12.899591 DQM Delay:
5682 04:46:12.902488 DQM0 = 97, DQM1 = 94
5683 04:46:12.903164 DQ Delay:
5684 04:46:12.905709 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5685 04:46:12.908679 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5686 04:46:12.911855 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5687 04:46:12.915471 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5688 04:46:12.915995
5689 04:46:12.916436
5690 04:46:12.916849 ==
5691 04:46:12.918356 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 04:46:12.925351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 04:46:12.925892 ==
5694 04:46:12.926339
5695 04:46:12.926807
5696 04:46:12.927248 TX Vref Scan disable
5697 04:46:12.928503 == TX Byte 0 ==
5698 04:46:12.931747 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5699 04:46:12.938858 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5700 04:46:12.939418 == TX Byte 1 ==
5701 04:46:12.941349 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5702 04:46:12.948032 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5703 04:46:12.948449 ==
5704 04:46:12.951100 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 04:46:12.954905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 04:46:12.955481 ==
5707 04:46:12.955823
5708 04:46:12.956128
5709 04:46:12.958063 TX Vref Scan disable
5710 04:46:12.961989 == TX Byte 0 ==
5711 04:46:12.964212 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5712 04:46:12.967662 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5713 04:46:12.971074 == TX Byte 1 ==
5714 04:46:12.974464 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5715 04:46:12.978048 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5716 04:46:12.978566
5717 04:46:12.978898 [DATLAT]
5718 04:46:12.981553 Freq=933, CH1 RK0
5719 04:46:12.982070
5720 04:46:12.984627 DATLAT Default: 0xd
5721 04:46:12.985038 0, 0xFFFF, sum = 0
5722 04:46:12.987864 1, 0xFFFF, sum = 0
5723 04:46:12.988386 2, 0xFFFF, sum = 0
5724 04:46:12.990877 3, 0xFFFF, sum = 0
5725 04:46:12.991441 4, 0xFFFF, sum = 0
5726 04:46:12.994665 5, 0xFFFF, sum = 0
5727 04:46:12.995188 6, 0xFFFF, sum = 0
5728 04:46:12.997332 7, 0xFFFF, sum = 0
5729 04:46:12.997852 8, 0xFFFF, sum = 0
5730 04:46:13.001307 9, 0xFFFF, sum = 0
5731 04:46:13.001833 10, 0x0, sum = 1
5732 04:46:13.004263 11, 0x0, sum = 2
5733 04:46:13.004684 12, 0x0, sum = 3
5734 04:46:13.007123 13, 0x0, sum = 4
5735 04:46:13.007615 best_step = 11
5736 04:46:13.008203
5737 04:46:13.008567 ==
5738 04:46:13.010583 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 04:46:13.016801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 04:46:13.017225 ==
5741 04:46:13.017559 RX Vref Scan: 1
5742 04:46:13.017868
5743 04:46:13.020364 RX Vref 0 -> 0, step: 1
5744 04:46:13.020786
5745 04:46:13.023346 RX Delay -61 -> 252, step: 4
5746 04:46:13.023811
5747 04:46:13.026792 Set Vref, RX VrefLevel [Byte0]: 54
5748 04:46:13.030169 [Byte1]: 54
5749 04:46:13.030610
5750 04:46:13.033082 Final RX Vref Byte 0 = 54 to rank0
5751 04:46:13.036740 Final RX Vref Byte 1 = 54 to rank0
5752 04:46:13.039926 Final RX Vref Byte 0 = 54 to rank1
5753 04:46:13.043115 Final RX Vref Byte 1 = 54 to rank1==
5754 04:46:13.046965 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 04:46:13.050402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 04:46:13.050926 ==
5757 04:46:13.053353 DQS Delay:
5758 04:46:13.053865 DQS0 = 0, DQS1 = 0
5759 04:46:13.056521 DQM Delay:
5760 04:46:13.056945 DQM0 = 97, DQM1 = 95
5761 04:46:13.057282 DQ Delay:
5762 04:46:13.060094 DQ0 =104, DQ1 =94, DQ2 =86, DQ3 =98
5763 04:46:13.063129 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =92
5764 04:46:13.066671 DQ8 =84, DQ9 =86, DQ10 =92, DQ11 =88
5765 04:46:13.073426 DQ12 =104, DQ13 =104, DQ14 =104, DQ15 =104
5766 04:46:13.073966
5767 04:46:13.074306
5768 04:46:13.079340 [DQSOSCAuto] RK0, (LSB)MR18= 0x717, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5769 04:46:13.082498 CH1 RK0: MR19=505, MR18=717
5770 04:46:13.089814 CH1_RK0: MR19=0x505, MR18=0x717, DQSOSC=414, MR23=63, INC=63, DEC=42
5771 04:46:13.090353
5772 04:46:13.092337 ----->DramcWriteLeveling(PI) begin...
5773 04:46:13.092768 ==
5774 04:46:13.095898 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 04:46:13.099266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 04:46:13.099736 ==
5777 04:46:13.102615 Write leveling (Byte 0): 27 => 27
5778 04:46:13.106016 Write leveling (Byte 1): 29 => 29
5779 04:46:13.108917 DramcWriteLeveling(PI) end<-----
5780 04:46:13.109376
5781 04:46:13.109743 ==
5782 04:46:13.112404 Dram Type= 6, Freq= 0, CH_1, rank 1
5783 04:46:13.116229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 04:46:13.116714 ==
5785 04:46:13.119326 [Gating] SW mode calibration
5786 04:46:13.126175 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5787 04:46:13.132517 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5788 04:46:13.135969 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 04:46:13.142112 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 04:46:13.145699 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 04:46:13.148430 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5792 04:46:13.155464 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 04:46:13.158314 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 04:46:13.161670 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5795 04:46:13.168269 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5796 04:46:13.172150 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 04:46:13.175409 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 04:46:13.181977 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 04:46:13.185441 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 04:46:13.189002 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 04:46:13.195192 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 04:46:13.198797 0 15 24 | B1->B0 | 2525 3434 | 0 1 | (0 0) (0 0)
5803 04:46:13.201380 0 15 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5804 04:46:13.207810 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 04:46:13.211078 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 04:46:13.214191 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 04:46:13.221153 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 04:46:13.224161 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 04:46:13.228012 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 04:46:13.234731 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5811 04:46:13.237421 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5812 04:46:13.241255 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 04:46:13.247796 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 04:46:13.250837 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 04:46:13.253915 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 04:46:13.260920 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 04:46:13.263696 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 04:46:13.267290 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 04:46:13.274389 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 04:46:13.277205 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 04:46:13.280041 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 04:46:13.286859 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 04:46:13.290459 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 04:46:13.293919 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 04:46:13.300070 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 04:46:13.303631 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5827 04:46:13.306891 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5828 04:46:13.313428 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 04:46:13.313992 Total UI for P1: 0, mck2ui 16
5830 04:46:13.319542 best dqsien dly found for B0: ( 1, 2, 26)
5831 04:46:13.319968 Total UI for P1: 0, mck2ui 16
5832 04:46:13.326438 best dqsien dly found for B1: ( 1, 2, 28)
5833 04:46:13.329181 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5834 04:46:13.332830 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5835 04:46:13.333347
5836 04:46:13.336566 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5837 04:46:13.339528 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5838 04:46:13.342673 [Gating] SW calibration Done
5839 04:46:13.343191 ==
5840 04:46:13.346150 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 04:46:13.349641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 04:46:13.350199 ==
5843 04:46:13.352902 RX Vref Scan: 0
5844 04:46:13.353461
5845 04:46:13.353838 RX Vref 0 -> 0, step: 1
5846 04:46:13.355520
5847 04:46:13.355984 RX Delay -80 -> 252, step: 8
5848 04:46:13.362316 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5849 04:46:13.365267 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5850 04:46:13.368945 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5851 04:46:13.372423 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5852 04:46:13.376375 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5853 04:46:13.378794 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5854 04:46:13.385608 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5855 04:46:13.389080 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5856 04:46:13.392049 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5857 04:46:13.395523 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5858 04:46:13.398677 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5859 04:46:13.401825 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5860 04:46:13.408388 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5861 04:46:13.411496 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5862 04:46:13.414775 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5863 04:46:13.418501 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5864 04:46:13.419274 ==
5865 04:46:13.422193 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 04:46:13.427845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 04:46:13.428428 ==
5868 04:46:13.428798 DQS Delay:
5869 04:46:13.431724 DQS0 = 0, DQS1 = 0
5870 04:46:13.432180 DQM Delay:
5871 04:46:13.432542 DQM0 = 97, DQM1 = 94
5872 04:46:13.434696 DQ Delay:
5873 04:46:13.438119 DQ0 =99, DQ1 =95, DQ2 =87, DQ3 =95
5874 04:46:13.441507 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5875 04:46:13.444300 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5876 04:46:13.447723 DQ12 =107, DQ13 =99, DQ14 =99, DQ15 =103
5877 04:46:13.448164
5878 04:46:13.448506
5879 04:46:13.448833 ==
5880 04:46:13.451140 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 04:46:13.454257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 04:46:13.454723 ==
5883 04:46:13.455095
5884 04:46:13.455444
5885 04:46:13.457592 TX Vref Scan disable
5886 04:46:13.461149 == TX Byte 0 ==
5887 04:46:13.464246 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5888 04:46:13.467318 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5889 04:46:13.470851 == TX Byte 1 ==
5890 04:46:13.474224 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5891 04:46:13.477690 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5892 04:46:13.478305 ==
5893 04:46:13.480753 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 04:46:13.487182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 04:46:13.487650 ==
5896 04:46:13.487981
5897 04:46:13.488289
5898 04:46:13.488580 TX Vref Scan disable
5899 04:46:13.491769 == TX Byte 0 ==
5900 04:46:13.494474 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5901 04:46:13.501351 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5902 04:46:13.501867 == TX Byte 1 ==
5903 04:46:13.504582 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5904 04:46:13.510742 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5905 04:46:13.511211
5906 04:46:13.511602 [DATLAT]
5907 04:46:13.511916 Freq=933, CH1 RK1
5908 04:46:13.512215
5909 04:46:13.513951 DATLAT Default: 0xb
5910 04:46:13.517256 0, 0xFFFF, sum = 0
5911 04:46:13.517770 1, 0xFFFF, sum = 0
5912 04:46:13.520466 2, 0xFFFF, sum = 0
5913 04:46:13.520893 3, 0xFFFF, sum = 0
5914 04:46:13.523924 4, 0xFFFF, sum = 0
5915 04:46:13.524343 5, 0xFFFF, sum = 0
5916 04:46:13.527344 6, 0xFFFF, sum = 0
5917 04:46:13.527806 7, 0xFFFF, sum = 0
5918 04:46:13.530181 8, 0xFFFF, sum = 0
5919 04:46:13.530604 9, 0xFFFF, sum = 0
5920 04:46:13.534061 10, 0x0, sum = 1
5921 04:46:13.534582 11, 0x0, sum = 2
5922 04:46:13.537494 12, 0x0, sum = 3
5923 04:46:13.538015 13, 0x0, sum = 4
5924 04:46:13.540483 best_step = 11
5925 04:46:13.540999
5926 04:46:13.541336 ==
5927 04:46:13.543588 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 04:46:13.547036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 04:46:13.547607 ==
5930 04:46:13.550549 RX Vref Scan: 0
5931 04:46:13.551060
5932 04:46:13.551429 RX Vref 0 -> 0, step: 1
5933 04:46:13.551746
5934 04:46:13.553132 RX Delay -53 -> 252, step: 4
5935 04:46:13.560076 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5936 04:46:13.563335 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5937 04:46:13.566899 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5938 04:46:13.570482 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5939 04:46:13.572953 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5940 04:46:13.579744 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5941 04:46:13.583029 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5942 04:46:13.586481 iDelay=199, Bit 7, Center 96 (3 ~ 190) 188
5943 04:46:13.589769 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5944 04:46:13.593410 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5945 04:46:13.599530 iDelay=199, Bit 10, Center 96 (7 ~ 186) 180
5946 04:46:13.602878 iDelay=199, Bit 11, Center 88 (-1 ~ 178) 180
5947 04:46:13.606164 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5948 04:46:13.609174 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5949 04:46:13.612486 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5950 04:46:13.619199 iDelay=199, Bit 15, Center 104 (15 ~ 194) 180
5951 04:46:13.619775 ==
5952 04:46:13.622235 Dram Type= 6, Freq= 0, CH_1, rank 1
5953 04:46:13.625692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5954 04:46:13.626108 ==
5955 04:46:13.626438 DQS Delay:
5956 04:46:13.629361 DQS0 = 0, DQS1 = 0
5957 04:46:13.629882 DQM Delay:
5958 04:46:13.632045 DQM0 = 97, DQM1 = 95
5959 04:46:13.632461 DQ Delay:
5960 04:46:13.635863 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5961 04:46:13.639621 DQ4 =98, DQ5 =106, DQ6 =106, DQ7 =96
5962 04:46:13.642519 DQ8 =82, DQ9 =84, DQ10 =96, DQ11 =88
5963 04:46:13.646055 DQ12 =104, DQ13 =102, DQ14 =102, DQ15 =104
5964 04:46:13.646571
5965 04:46:13.646906
5966 04:46:13.655109 [DQSOSCAuto] RK1, (LSB)MR18= 0x1026, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 416 ps
5967 04:46:13.658849 CH1 RK1: MR19=505, MR18=1026
5968 04:46:13.661655 CH1_RK1: MR19=0x505, MR18=0x1026, DQSOSC=409, MR23=63, INC=64, DEC=43
5969 04:46:13.665401 [RxdqsGatingPostProcess] freq 933
5970 04:46:13.672082 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5971 04:46:13.675729 best DQS0 dly(2T, 0.5T) = (0, 10)
5972 04:46:13.678808 best DQS1 dly(2T, 0.5T) = (0, 10)
5973 04:46:13.682097 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5974 04:46:13.685112 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5975 04:46:13.688454 best DQS0 dly(2T, 0.5T) = (0, 10)
5976 04:46:13.691519 best DQS1 dly(2T, 0.5T) = (0, 10)
5977 04:46:13.694773 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5978 04:46:13.698092 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5979 04:46:13.701105 Pre-setting of DQS Precalculation
5980 04:46:13.704558 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5981 04:46:13.711628 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5982 04:46:13.718315 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5983 04:46:13.720964
5984 04:46:13.721479
5985 04:46:13.721811 [Calibration Summary] 1866 Mbps
5986 04:46:13.724084 CH 0, Rank 0
5987 04:46:13.724497 SW Impedance : PASS
5988 04:46:13.727952 DUTY Scan : NO K
5989 04:46:13.730793 ZQ Calibration : PASS
5990 04:46:13.731245 Jitter Meter : NO K
5991 04:46:13.734888 CBT Training : PASS
5992 04:46:13.737788 Write leveling : PASS
5993 04:46:13.738204 RX DQS gating : PASS
5994 04:46:13.740832 RX DQ/DQS(RDDQC) : PASS
5995 04:46:13.744243 TX DQ/DQS : PASS
5996 04:46:13.744656 RX DATLAT : PASS
5997 04:46:13.747620 RX DQ/DQS(Engine): PASS
5998 04:46:13.750716 TX OE : NO K
5999 04:46:13.751234 All Pass.
6000 04:46:13.751738
6001 04:46:13.752140 CH 0, Rank 1
6002 04:46:13.754236 SW Impedance : PASS
6003 04:46:13.757896 DUTY Scan : NO K
6004 04:46:13.758403 ZQ Calibration : PASS
6005 04:46:13.760765 Jitter Meter : NO K
6006 04:46:13.763990 CBT Training : PASS
6007 04:46:13.764403 Write leveling : PASS
6008 04:46:13.767462 RX DQS gating : PASS
6009 04:46:13.770110 RX DQ/DQS(RDDQC) : PASS
6010 04:46:13.770637 TX DQ/DQS : PASS
6011 04:46:13.773608 RX DATLAT : PASS
6012 04:46:13.777021 RX DQ/DQS(Engine): PASS
6013 04:46:13.777517 TX OE : NO K
6014 04:46:13.780178 All Pass.
6015 04:46:13.780740
6016 04:46:13.781177 CH 1, Rank 0
6017 04:46:13.783402 SW Impedance : PASS
6018 04:46:13.783956 DUTY Scan : NO K
6019 04:46:13.786634 ZQ Calibration : PASS
6020 04:46:13.790510 Jitter Meter : NO K
6021 04:46:13.790993 CBT Training : PASS
6022 04:46:13.793637 Write leveling : PASS
6023 04:46:13.797091 RX DQS gating : PASS
6024 04:46:13.797572 RX DQ/DQS(RDDQC) : PASS
6025 04:46:13.800259 TX DQ/DQS : PASS
6026 04:46:13.800805 RX DATLAT : PASS
6027 04:46:13.803119 RX DQ/DQS(Engine): PASS
6028 04:46:13.806528 TX OE : NO K
6029 04:46:13.807093 All Pass.
6030 04:46:13.807627
6031 04:46:13.809627 CH 1, Rank 1
6032 04:46:13.810119 SW Impedance : PASS
6033 04:46:13.813497 DUTY Scan : NO K
6034 04:46:13.814008 ZQ Calibration : PASS
6035 04:46:13.816779 Jitter Meter : NO K
6036 04:46:13.819772 CBT Training : PASS
6037 04:46:13.820320 Write leveling : PASS
6038 04:46:13.823241 RX DQS gating : PASS
6039 04:46:13.826390 RX DQ/DQS(RDDQC) : PASS
6040 04:46:13.826951 TX DQ/DQS : PASS
6041 04:46:13.829580 RX DATLAT : PASS
6042 04:46:13.833164 RX DQ/DQS(Engine): PASS
6043 04:46:13.833667 TX OE : NO K
6044 04:46:13.836214 All Pass.
6045 04:46:13.836830
6046 04:46:13.837247 DramC Write-DBI off
6047 04:46:13.839232 PER_BANK_REFRESH: Hybrid Mode
6048 04:46:13.842673 TX_TRACKING: ON
6049 04:46:13.849366 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6050 04:46:13.852770 [FAST_K] Save calibration result to emmc
6051 04:46:13.859100 dramc_set_vcore_voltage set vcore to 650000
6052 04:46:13.859701 Read voltage for 400, 6
6053 04:46:13.860242 Vio18 = 0
6054 04:46:13.862138 Vcore = 650000
6055 04:46:13.862699 Vdram = 0
6056 04:46:13.863108 Vddq = 0
6057 04:46:13.865582 Vmddr = 0
6058 04:46:13.868759 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6059 04:46:13.875672 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6060 04:46:13.878826 MEM_TYPE=3, freq_sel=20
6061 04:46:13.879353 sv_algorithm_assistance_LP4_800
6062 04:46:13.885163 ============ PULL DRAM RESETB DOWN ============
6063 04:46:13.888852 ========== PULL DRAM RESETB DOWN end =========
6064 04:46:13.891701 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6065 04:46:13.894890 ===================================
6066 04:46:13.898514 LPDDR4 DRAM CONFIGURATION
6067 04:46:13.901884 ===================================
6068 04:46:13.905191 EX_ROW_EN[0] = 0x0
6069 04:46:13.905803 EX_ROW_EN[1] = 0x0
6070 04:46:13.908426 LP4Y_EN = 0x0
6071 04:46:13.909059 WORK_FSP = 0x0
6072 04:46:13.911644 WL = 0x2
6073 04:46:13.912272 RL = 0x2
6074 04:46:13.914667 BL = 0x2
6075 04:46:13.915094 RPST = 0x0
6076 04:46:13.918294 RD_PRE = 0x0
6077 04:46:13.918711 WR_PRE = 0x1
6078 04:46:13.921426 WR_PST = 0x0
6079 04:46:13.924557 DBI_WR = 0x0
6080 04:46:13.925005 DBI_RD = 0x0
6081 04:46:13.928044 OTF = 0x1
6082 04:46:13.931015 ===================================
6083 04:46:13.934397 ===================================
6084 04:46:13.934846 ANA top config
6085 04:46:13.937801 ===================================
6086 04:46:13.941153 DLL_ASYNC_EN = 0
6087 04:46:13.944563 ALL_SLAVE_EN = 1
6088 04:46:13.945008 NEW_RANK_MODE = 1
6089 04:46:13.947787 DLL_IDLE_MODE = 1
6090 04:46:13.951106 LP45_APHY_COMB_EN = 1
6091 04:46:13.954639 TX_ODT_DIS = 1
6092 04:46:13.955064 NEW_8X_MODE = 1
6093 04:46:13.957726 ===================================
6094 04:46:13.961443 ===================================
6095 04:46:13.964135 data_rate = 800
6096 04:46:13.967701 CKR = 1
6097 04:46:13.970657 DQ_P2S_RATIO = 4
6098 04:46:13.974126 ===================================
6099 04:46:13.977339 CA_P2S_RATIO = 4
6100 04:46:13.980960 DQ_CA_OPEN = 0
6101 04:46:13.983838 DQ_SEMI_OPEN = 1
6102 04:46:13.984279 CA_SEMI_OPEN = 1
6103 04:46:13.987616 CA_FULL_RATE = 0
6104 04:46:13.990512 DQ_CKDIV4_EN = 0
6105 04:46:13.993734 CA_CKDIV4_EN = 1
6106 04:46:13.997189 CA_PREDIV_EN = 0
6107 04:46:14.000161 PH8_DLY = 0
6108 04:46:14.000606 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6109 04:46:14.003724 DQ_AAMCK_DIV = 0
6110 04:46:14.006779 CA_AAMCK_DIV = 0
6111 04:46:14.010155 CA_ADMCK_DIV = 4
6112 04:46:14.013282 DQ_TRACK_CA_EN = 0
6113 04:46:14.016706 CA_PICK = 800
6114 04:46:14.020122 CA_MCKIO = 400
6115 04:46:14.020537 MCKIO_SEMI = 400
6116 04:46:14.023136 PLL_FREQ = 3016
6117 04:46:14.026592 DQ_UI_PI_RATIO = 32
6118 04:46:14.029922 CA_UI_PI_RATIO = 32
6119 04:46:14.033000 ===================================
6120 04:46:14.036386 ===================================
6121 04:46:14.039763 memory_type:LPDDR4
6122 04:46:14.043076 GP_NUM : 10
6123 04:46:14.043495 SRAM_EN : 1
6124 04:46:14.046179 MD32_EN : 0
6125 04:46:14.049734 ===================================
6126 04:46:14.050154 [ANA_INIT] >>>>>>>>>>>>>>
6127 04:46:14.052840 <<<<<< [CONFIGURE PHASE]: ANA_TX
6128 04:46:14.056454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6129 04:46:14.059400 ===================================
6130 04:46:14.063012 data_rate = 800,PCW = 0X7400
6131 04:46:14.065839 ===================================
6132 04:46:14.069309 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6133 04:46:14.075519 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6134 04:46:14.085899 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6135 04:46:14.092470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6136 04:46:14.095220 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6137 04:46:14.098502 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6138 04:46:14.101805 [ANA_INIT] flow start
6139 04:46:14.102140 [ANA_INIT] PLL >>>>>>>>
6140 04:46:14.105571 [ANA_INIT] PLL <<<<<<<<
6141 04:46:14.108264 [ANA_INIT] MIDPI >>>>>>>>
6142 04:46:14.108620 [ANA_INIT] MIDPI <<<<<<<<
6143 04:46:14.112177 [ANA_INIT] DLL >>>>>>>>
6144 04:46:14.115165 [ANA_INIT] flow end
6145 04:46:14.118396 ============ LP4 DIFF to SE enter ============
6146 04:46:14.121732 ============ LP4 DIFF to SE exit ============
6147 04:46:14.125272 [ANA_INIT] <<<<<<<<<<<<<
6148 04:46:14.128340 [Flow] Enable top DCM control >>>>>
6149 04:46:14.131602 [Flow] Enable top DCM control <<<<<
6150 04:46:14.135230 Enable DLL master slave shuffle
6151 04:46:14.138794 ==============================================================
6152 04:46:14.141324 Gating Mode config
6153 04:46:14.148062 ==============================================================
6154 04:46:14.148358 Config description:
6155 04:46:14.157956 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6156 04:46:14.164964 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6157 04:46:14.171895 SELPH_MODE 0: By rank 1: By Phase
6158 04:46:14.175282 ==============================================================
6159 04:46:14.178391 GAT_TRACK_EN = 0
6160 04:46:14.181484 RX_GATING_MODE = 2
6161 04:46:14.184855 RX_GATING_TRACK_MODE = 2
6162 04:46:14.188097 SELPH_MODE = 1
6163 04:46:14.191756 PICG_EARLY_EN = 1
6164 04:46:14.195112 VALID_LAT_VALUE = 1
6165 04:46:14.197632 ==============================================================
6166 04:46:14.201161 Enter into Gating configuration >>>>
6167 04:46:14.204697 Exit from Gating configuration <<<<
6168 04:46:14.207663 Enter into DVFS_PRE_config >>>>>
6169 04:46:14.220778 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6170 04:46:14.224304 Exit from DVFS_PRE_config <<<<<
6171 04:46:14.227285 Enter into PICG configuration >>>>
6172 04:46:14.230510 Exit from PICG configuration <<<<
6173 04:46:14.231115 [RX_INPUT] configuration >>>>>
6174 04:46:14.234129 [RX_INPUT] configuration <<<<<
6175 04:46:14.240497 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6176 04:46:14.246773 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6177 04:46:14.250637 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6178 04:46:14.256707 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6179 04:46:14.263536 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6180 04:46:14.270228 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6181 04:46:14.273460 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6182 04:46:14.276619 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6183 04:46:14.283350 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6184 04:46:14.286619 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6185 04:46:14.289991 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6186 04:46:14.296399 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6187 04:46:14.300490 ===================================
6188 04:46:14.300927 LPDDR4 DRAM CONFIGURATION
6189 04:46:14.303433 ===================================
6190 04:46:14.306660 EX_ROW_EN[0] = 0x0
6191 04:46:14.309627 EX_ROW_EN[1] = 0x0
6192 04:46:14.310045 LP4Y_EN = 0x0
6193 04:46:14.312890 WORK_FSP = 0x0
6194 04:46:14.313304 WL = 0x2
6195 04:46:14.315987 RL = 0x2
6196 04:46:14.316408 BL = 0x2
6197 04:46:14.319606 RPST = 0x0
6198 04:46:14.320143 RD_PRE = 0x0
6199 04:46:14.323169 WR_PRE = 0x1
6200 04:46:14.323687 WR_PST = 0x0
6201 04:46:14.326356 DBI_WR = 0x0
6202 04:46:14.326898 DBI_RD = 0x0
6203 04:46:14.329931 OTF = 0x1
6204 04:46:14.332898 ===================================
6205 04:46:14.335719 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6206 04:46:14.339263 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6207 04:46:14.345712 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6208 04:46:14.349806 ===================================
6209 04:46:14.350327 LPDDR4 DRAM CONFIGURATION
6210 04:46:14.352737 ===================================
6211 04:46:14.355935 EX_ROW_EN[0] = 0x10
6212 04:46:14.359128 EX_ROW_EN[1] = 0x0
6213 04:46:14.359659 LP4Y_EN = 0x0
6214 04:46:14.362932 WORK_FSP = 0x0
6215 04:46:14.363556 WL = 0x2
6216 04:46:14.366113 RL = 0x2
6217 04:46:14.366671 BL = 0x2
6218 04:46:14.368916 RPST = 0x0
6219 04:46:14.369507 RD_PRE = 0x0
6220 04:46:14.372678 WR_PRE = 0x1
6221 04:46:14.373232 WR_PST = 0x0
6222 04:46:14.375536 DBI_WR = 0x0
6223 04:46:14.375949 DBI_RD = 0x0
6224 04:46:14.378803 OTF = 0x1
6225 04:46:14.382314 ===================================
6226 04:46:14.389164 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6227 04:46:14.392533 nWR fixed to 30
6228 04:46:14.393055 [ModeRegInit_LP4] CH0 RK0
6229 04:46:14.396100 [ModeRegInit_LP4] CH0 RK1
6230 04:46:14.399443 [ModeRegInit_LP4] CH1 RK0
6231 04:46:14.402927 [ModeRegInit_LP4] CH1 RK1
6232 04:46:14.403494 match AC timing 19
6233 04:46:14.408998 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6234 04:46:14.411934 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6235 04:46:14.415610 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6236 04:46:14.421685 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6237 04:46:14.424957 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6238 04:46:14.425532 ==
6239 04:46:14.428664 Dram Type= 6, Freq= 0, CH_0, rank 0
6240 04:46:14.432216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6241 04:46:14.432635 ==
6242 04:46:14.439033 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6243 04:46:14.444924 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6244 04:46:14.448000 [CA 0] Center 36 (8~64) winsize 57
6245 04:46:14.451855 [CA 1] Center 36 (8~64) winsize 57
6246 04:46:14.454931 [CA 2] Center 36 (8~64) winsize 57
6247 04:46:14.455518 [CA 3] Center 36 (8~64) winsize 57
6248 04:46:14.458235 [CA 4] Center 36 (8~64) winsize 57
6249 04:46:14.461332 [CA 5] Center 36 (8~64) winsize 57
6250 04:46:14.461850
6251 04:46:14.468496 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6252 04:46:14.469015
6253 04:46:14.471494 [CATrainingPosCal] consider 1 rank data
6254 04:46:14.474866 u2DelayCellTimex100 = 270/100 ps
6255 04:46:14.478021 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 04:46:14.481272 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 04:46:14.484098 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 04:46:14.487816 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 04:46:14.491073 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 04:46:14.494562 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 04:46:14.495074
6262 04:46:14.497925 CA PerBit enable=1, Macro0, CA PI delay=36
6263 04:46:14.498443
6264 04:46:14.500993 [CBTSetCACLKResult] CA Dly = 36
6265 04:46:14.504392 CS Dly: 1 (0~32)
6266 04:46:14.504906 ==
6267 04:46:14.507530 Dram Type= 6, Freq= 0, CH_0, rank 1
6268 04:46:14.510907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 04:46:14.511329 ==
6270 04:46:14.517489 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6271 04:46:14.523819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6272 04:46:14.527299 [CA 0] Center 36 (8~64) winsize 57
6273 04:46:14.527764 [CA 1] Center 36 (8~64) winsize 57
6274 04:46:14.530447 [CA 2] Center 36 (8~64) winsize 57
6275 04:46:14.534228 [CA 3] Center 36 (8~64) winsize 57
6276 04:46:14.537437 [CA 4] Center 36 (8~64) winsize 57
6277 04:46:14.540517 [CA 5] Center 36 (8~64) winsize 57
6278 04:46:14.541038
6279 04:46:14.543534 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6280 04:46:14.543952
6281 04:46:14.550911 [CATrainingPosCal] consider 2 rank data
6282 04:46:14.551592 u2DelayCellTimex100 = 270/100 ps
6283 04:46:14.557168 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 04:46:14.560207 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 04:46:14.563697 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 04:46:14.566716 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 04:46:14.570049 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 04:46:14.573171 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 04:46:14.573588
6290 04:46:14.576717 CA PerBit enable=1, Macro0, CA PI delay=36
6291 04:46:14.577133
6292 04:46:14.579930 [CBTSetCACLKResult] CA Dly = 36
6293 04:46:14.583161 CS Dly: 1 (0~32)
6294 04:46:14.583630
6295 04:46:14.586713 ----->DramcWriteLeveling(PI) begin...
6296 04:46:14.587275 ==
6297 04:46:14.590109 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 04:46:14.593122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 04:46:14.593540 ==
6300 04:46:14.596240 Write leveling (Byte 0): 40 => 8
6301 04:46:14.599751 Write leveling (Byte 1): 40 => 8
6302 04:46:14.603323 DramcWriteLeveling(PI) end<-----
6303 04:46:14.603792
6304 04:46:14.604125 ==
6305 04:46:14.606601 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 04:46:14.609543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 04:46:14.609962 ==
6308 04:46:14.612780 [Gating] SW mode calibration
6309 04:46:14.620145 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6310 04:46:14.626619 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6311 04:46:14.629666 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6312 04:46:14.633093 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6313 04:46:14.639734 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6314 04:46:14.643213 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6315 04:46:14.645925 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 04:46:14.652634 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6317 04:46:14.655817 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6318 04:46:14.659413 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6319 04:46:14.665511 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6320 04:46:14.669285 Total UI for P1: 0, mck2ui 16
6321 04:46:14.672281 best dqsien dly found for B0: ( 0, 14, 24)
6322 04:46:14.675906 Total UI for P1: 0, mck2ui 16
6323 04:46:14.679174 best dqsien dly found for B1: ( 0, 14, 24)
6324 04:46:14.682007 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6325 04:46:14.685808 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6326 04:46:14.686368
6327 04:46:14.688900 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6328 04:46:14.692228 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6329 04:46:14.695336 [Gating] SW calibration Done
6330 04:46:14.695819 ==
6331 04:46:14.698527 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 04:46:14.702240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 04:46:14.705104 ==
6334 04:46:14.705538 RX Vref Scan: 0
6335 04:46:14.705979
6336 04:46:14.708553 RX Vref 0 -> 0, step: 1
6337 04:46:14.708989
6338 04:46:14.712292 RX Delay -410 -> 252, step: 16
6339 04:46:14.715459 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6340 04:46:14.718432 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6341 04:46:14.721842 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6342 04:46:14.728436 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6343 04:46:14.731484 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6344 04:46:14.735048 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6345 04:46:14.738201 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6346 04:46:14.744954 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6347 04:46:14.747780 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6348 04:46:14.751219 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6349 04:46:14.758018 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6350 04:46:14.761049 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6351 04:46:14.764503 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6352 04:46:14.768297 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6353 04:46:14.775051 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6354 04:46:14.777776 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6355 04:46:14.778287 ==
6356 04:46:14.780763 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 04:46:14.784320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 04:46:14.784742 ==
6359 04:46:14.787505 DQS Delay:
6360 04:46:14.787967 DQS0 = 35, DQS1 = 59
6361 04:46:14.790480 DQM Delay:
6362 04:46:14.790966 DQM0 = 5, DQM1 = 17
6363 04:46:14.791298 DQ Delay:
6364 04:46:14.793805 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6365 04:46:14.796886 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6366 04:46:14.800281 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6367 04:46:14.803889 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6368 04:46:14.804376
6369 04:46:14.804703
6370 04:46:14.805052 ==
6371 04:46:14.807047 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 04:46:14.813996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 04:46:14.814397 ==
6374 04:46:14.814659
6375 04:46:14.814878
6376 04:46:14.815086 TX Vref Scan disable
6377 04:46:14.817058 == TX Byte 0 ==
6378 04:46:14.820229 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6379 04:46:14.823302 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6380 04:46:14.826909 == TX Byte 1 ==
6381 04:46:14.829859 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6382 04:46:14.833682 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6383 04:46:14.834073 ==
6384 04:46:14.836588 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 04:46:14.843898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 04:46:14.844323 ==
6387 04:46:14.844652
6388 04:46:14.844957
6389 04:46:14.845249 TX Vref Scan disable
6390 04:46:14.846536 == TX Byte 0 ==
6391 04:46:14.849714 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 04:46:14.853038 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 04:46:14.856751 == TX Byte 1 ==
6394 04:46:14.859745 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 04:46:14.863261 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 04:46:14.866629
6397 04:46:14.867037 [DATLAT]
6398 04:46:14.867395 Freq=400, CH0 RK0
6399 04:46:14.867722
6400 04:46:14.869799 DATLAT Default: 0xf
6401 04:46:14.870317 0, 0xFFFF, sum = 0
6402 04:46:14.873269 1, 0xFFFF, sum = 0
6403 04:46:14.873789 2, 0xFFFF, sum = 0
6404 04:46:14.876400 3, 0xFFFF, sum = 0
6405 04:46:14.876950 4, 0xFFFF, sum = 0
6406 04:46:14.880094 5, 0xFFFF, sum = 0
6407 04:46:14.882987 6, 0xFFFF, sum = 0
6408 04:46:14.883713 7, 0xFFFF, sum = 0
6409 04:46:14.886094 8, 0xFFFF, sum = 0
6410 04:46:14.886514 9, 0xFFFF, sum = 0
6411 04:46:14.889386 10, 0xFFFF, sum = 0
6412 04:46:14.889806 11, 0xFFFF, sum = 0
6413 04:46:14.893222 12, 0xFFFF, sum = 0
6414 04:46:14.893759 13, 0x0, sum = 1
6415 04:46:14.896589 14, 0x0, sum = 2
6416 04:46:14.897105 15, 0x0, sum = 3
6417 04:46:14.899409 16, 0x0, sum = 4
6418 04:46:14.899932 best_step = 14
6419 04:46:14.900261
6420 04:46:14.900567 ==
6421 04:46:14.902907 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 04:46:14.906032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 04:46:14.909050 ==
6424 04:46:14.909464 RX Vref Scan: 1
6425 04:46:14.909792
6426 04:46:14.912460 RX Vref 0 -> 0, step: 1
6427 04:46:14.912873
6428 04:46:14.916498 RX Delay -359 -> 252, step: 8
6429 04:46:14.917044
6430 04:46:14.919096 Set Vref, RX VrefLevel [Byte0]: 57
6431 04:46:14.922818 [Byte1]: 49
6432 04:46:14.923334
6433 04:46:14.925822 Final RX Vref Byte 0 = 57 to rank0
6434 04:46:14.928847 Final RX Vref Byte 1 = 49 to rank0
6435 04:46:14.932724 Final RX Vref Byte 0 = 57 to rank1
6436 04:46:14.935484 Final RX Vref Byte 1 = 49 to rank1==
6437 04:46:14.939125 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 04:46:14.942482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 04:46:14.942996 ==
6440 04:46:14.945862 DQS Delay:
6441 04:46:14.946272 DQS0 = 44, DQS1 = 60
6442 04:46:14.948898 DQM Delay:
6443 04:46:14.949310 DQM0 = 10, DQM1 = 17
6444 04:46:14.952238 DQ Delay:
6445 04:46:14.952750 DQ0 =12, DQ1 =8, DQ2 =8, DQ3 =4
6446 04:46:14.955339 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6447 04:46:14.959267 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6448 04:46:14.962199 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6449 04:46:14.962678
6450 04:46:14.963008
6451 04:46:14.972381 [DQSOSCAuto] RK0, (LSB)MR18= 0x9b8e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6452 04:46:14.975198 CH0 RK0: MR19=C0C, MR18=9B8E
6453 04:46:14.982001 CH0_RK0: MR19=0xC0C, MR18=0x9B8E, DQSOSC=390, MR23=63, INC=388, DEC=258
6454 04:46:14.982513 ==
6455 04:46:14.985282 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 04:46:14.988497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 04:46:14.989007 ==
6458 04:46:14.992039 [Gating] SW mode calibration
6459 04:46:14.998360 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6460 04:46:15.005160 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6461 04:46:15.008503 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6462 04:46:15.011446 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6463 04:46:15.017659 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6464 04:46:15.021071 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6465 04:46:15.024924 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 04:46:15.031146 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6467 04:46:15.034767 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6468 04:46:15.037853 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 04:46:15.044975 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6470 04:46:15.045497 Total UI for P1: 0, mck2ui 16
6471 04:46:15.048079 best dqsien dly found for B0: ( 0, 14, 24)
6472 04:46:15.050830 Total UI for P1: 0, mck2ui 16
6473 04:46:15.054438 best dqsien dly found for B1: ( 0, 14, 24)
6474 04:46:15.060842 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6475 04:46:15.064038 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6476 04:46:15.064496
6477 04:46:15.067490 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6478 04:46:15.071030 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6479 04:46:15.074059 [Gating] SW calibration Done
6480 04:46:15.074518 ==
6481 04:46:15.077650 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 04:46:15.080839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 04:46:15.081355 ==
6484 04:46:15.083960 RX Vref Scan: 0
6485 04:46:15.084381
6486 04:46:15.084708 RX Vref 0 -> 0, step: 1
6487 04:46:15.085011
6488 04:46:15.087597 RX Delay -410 -> 252, step: 16
6489 04:46:15.093791 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6490 04:46:15.097419 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6491 04:46:15.100935 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6492 04:46:15.103639 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6493 04:46:15.110268 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6494 04:46:15.113375 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6495 04:46:15.116964 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6496 04:46:15.120025 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6497 04:46:15.127188 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6498 04:46:15.130158 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6499 04:46:15.133334 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6500 04:46:15.136779 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6501 04:46:15.143648 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6502 04:46:15.146853 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6503 04:46:15.149799 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6504 04:46:15.156200 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6505 04:46:15.156726 ==
6506 04:46:15.159409 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 04:46:15.162985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 04:46:15.163449 ==
6509 04:46:15.163787 DQS Delay:
6510 04:46:15.165998 DQS0 = 35, DQS1 = 59
6511 04:46:15.166443 DQM Delay:
6512 04:46:15.169627 DQM0 = 6, DQM1 = 17
6513 04:46:15.170043 DQ Delay:
6514 04:46:15.172754 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6515 04:46:15.176267 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6516 04:46:15.179519 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6517 04:46:15.183428 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6518 04:46:15.183975
6519 04:46:15.184375
6520 04:46:15.184720 ==
6521 04:46:15.186180 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 04:46:15.189125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 04:46:15.189544 ==
6524 04:46:15.190016
6525 04:46:15.190342
6526 04:46:15.192645 TX Vref Scan disable
6527 04:46:15.193160 == TX Byte 0 ==
6528 04:46:15.199332 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6529 04:46:15.202403 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6530 04:46:15.202816 == TX Byte 1 ==
6531 04:46:15.209224 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6532 04:46:15.212370 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6533 04:46:15.212804 ==
6534 04:46:15.215633 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 04:46:15.219222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 04:46:15.219886 ==
6537 04:46:15.220343
6538 04:46:15.220756
6539 04:46:15.222360 TX Vref Scan disable
6540 04:46:15.225915 == TX Byte 0 ==
6541 04:46:15.228970 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6542 04:46:15.232317 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6543 04:46:15.235506 == TX Byte 1 ==
6544 04:46:15.239057 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6545 04:46:15.242292 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6546 04:46:15.242824
6547 04:46:15.243346 [DATLAT]
6548 04:46:15.245795 Freq=400, CH0 RK1
6549 04:46:15.246339
6550 04:46:15.246862 DATLAT Default: 0xe
6551 04:46:15.248483 0, 0xFFFF, sum = 0
6552 04:46:15.248923 1, 0xFFFF, sum = 0
6553 04:46:15.251773 2, 0xFFFF, sum = 0
6554 04:46:15.255558 3, 0xFFFF, sum = 0
6555 04:46:15.256163 4, 0xFFFF, sum = 0
6556 04:46:15.258635 5, 0xFFFF, sum = 0
6557 04:46:15.259069 6, 0xFFFF, sum = 0
6558 04:46:15.261867 7, 0xFFFF, sum = 0
6559 04:46:15.262305 8, 0xFFFF, sum = 0
6560 04:46:15.265368 9, 0xFFFF, sum = 0
6561 04:46:15.265801 10, 0xFFFF, sum = 0
6562 04:46:15.268683 11, 0xFFFF, sum = 0
6563 04:46:15.269154 12, 0xFFFF, sum = 0
6564 04:46:15.271946 13, 0x0, sum = 1
6565 04:46:15.272386 14, 0x0, sum = 2
6566 04:46:15.274957 15, 0x0, sum = 3
6567 04:46:15.275417 16, 0x0, sum = 4
6568 04:46:15.278502 best_step = 14
6569 04:46:15.278922
6570 04:46:15.279254 ==
6571 04:46:15.281819 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 04:46:15.285201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 04:46:15.285623 ==
6574 04:46:15.288535 RX Vref Scan: 0
6575 04:46:15.288953
6576 04:46:15.289287 RX Vref 0 -> 0, step: 1
6577 04:46:15.289600
6578 04:46:15.291690 RX Delay -359 -> 252, step: 8
6579 04:46:15.299316 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6580 04:46:15.302351 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6581 04:46:15.305920 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6582 04:46:15.312371 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6583 04:46:15.315965 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6584 04:46:15.318961 iDelay=217, Bit 5, Center -40 (-279 ~ 200) 480
6585 04:46:15.322223 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6586 04:46:15.325497 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6587 04:46:15.331982 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6588 04:46:15.335272 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6589 04:46:15.338587 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6590 04:46:15.345154 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6591 04:46:15.348584 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6592 04:46:15.352283 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6593 04:46:15.355828 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6594 04:46:15.361717 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6595 04:46:15.362333 ==
6596 04:46:15.365113 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 04:46:15.368828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 04:46:15.369356 ==
6599 04:46:15.369895 DQS Delay:
6600 04:46:15.372198 DQS0 = 40, DQS1 = 60
6601 04:46:15.372688 DQM Delay:
6602 04:46:15.375480 DQM0 = 5, DQM1 = 14
6603 04:46:15.376057 DQ Delay:
6604 04:46:15.378329 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =0
6605 04:46:15.381575 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =8
6606 04:46:15.385036 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6607 04:46:15.388306 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6608 04:46:15.388910
6609 04:46:15.389499
6610 04:46:15.395041 [DQSOSCAuto] RK1, (LSB)MR18= 0x8d87, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
6611 04:46:15.398407 CH0 RK1: MR19=C0C, MR18=8D87
6612 04:46:15.404934 CH0_RK1: MR19=0xC0C, MR18=0x8D87, DQSOSC=392, MR23=63, INC=384, DEC=256
6613 04:46:15.407921 [RxdqsGatingPostProcess] freq 400
6614 04:46:15.414462 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6615 04:46:15.418205 best DQS0 dly(2T, 0.5T) = (0, 10)
6616 04:46:15.421086 best DQS1 dly(2T, 0.5T) = (0, 10)
6617 04:46:15.424762 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6618 04:46:15.427934 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6619 04:46:15.428450 best DQS0 dly(2T, 0.5T) = (0, 10)
6620 04:46:15.430946 best DQS1 dly(2T, 0.5T) = (0, 10)
6621 04:46:15.434468 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6622 04:46:15.437721 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6623 04:46:15.441186 Pre-setting of DQS Precalculation
6624 04:46:15.447703 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6625 04:46:15.448220 ==
6626 04:46:15.451004 Dram Type= 6, Freq= 0, CH_1, rank 0
6627 04:46:15.454220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 04:46:15.454636 ==
6629 04:46:15.461625 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6630 04:46:15.467804 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6631 04:46:15.470870 [CA 0] Center 36 (8~64) winsize 57
6632 04:46:15.474159 [CA 1] Center 36 (8~64) winsize 57
6633 04:46:15.474628 [CA 2] Center 36 (8~64) winsize 57
6634 04:46:15.477414 [CA 3] Center 36 (8~64) winsize 57
6635 04:46:15.480652 [CA 4] Center 36 (8~64) winsize 57
6636 04:46:15.484110 [CA 5] Center 36 (8~64) winsize 57
6637 04:46:15.484526
6638 04:46:15.490576 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6639 04:46:15.491096
6640 04:46:15.493656 [CATrainingPosCal] consider 1 rank data
6641 04:46:15.497157 u2DelayCellTimex100 = 270/100 ps
6642 04:46:15.500406 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 04:46:15.503297 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 04:46:15.506449 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 04:46:15.509969 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 04:46:15.513116 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 04:46:15.516771 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 04:46:15.517398
6649 04:46:15.519913 CA PerBit enable=1, Macro0, CA PI delay=36
6650 04:46:15.520588
6651 04:46:15.523045 [CBTSetCACLKResult] CA Dly = 36
6652 04:46:15.526531 CS Dly: 1 (0~32)
6653 04:46:15.527148 ==
6654 04:46:15.529954 Dram Type= 6, Freq= 0, CH_1, rank 1
6655 04:46:15.532675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 04:46:15.533253 ==
6657 04:46:15.539434 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6658 04:46:15.546215 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6659 04:46:15.549453 [CA 0] Center 36 (8~64) winsize 57
6660 04:46:15.552810 [CA 1] Center 36 (8~64) winsize 57
6661 04:46:15.553263 [CA 2] Center 36 (8~64) winsize 57
6662 04:46:15.556096 [CA 3] Center 36 (8~64) winsize 57
6663 04:46:15.559926 [CA 4] Center 36 (8~64) winsize 57
6664 04:46:15.562373 [CA 5] Center 36 (8~64) winsize 57
6665 04:46:15.562794
6666 04:46:15.565772 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6667 04:46:15.569366
6668 04:46:15.572683 [CATrainingPosCal] consider 2 rank data
6669 04:46:15.573108 u2DelayCellTimex100 = 270/100 ps
6670 04:46:15.579032 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 04:46:15.582654 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 04:46:15.586044 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 04:46:15.589188 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 04:46:15.591974 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 04:46:15.595395 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 04:46:15.595492
6677 04:46:15.598765 CA PerBit enable=1, Macro0, CA PI delay=36
6678 04:46:15.598852
6679 04:46:15.602084 [CBTSetCACLKResult] CA Dly = 36
6680 04:46:15.605590 CS Dly: 1 (0~32)
6681 04:46:15.605686
6682 04:46:15.608036 ----->DramcWriteLeveling(PI) begin...
6683 04:46:15.608132 ==
6684 04:46:15.612021 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 04:46:15.614709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 04:46:15.614820 ==
6687 04:46:15.618456 Write leveling (Byte 0): 40 => 8
6688 04:46:15.621251 Write leveling (Byte 1): 40 => 8
6689 04:46:15.624693 DramcWriteLeveling(PI) end<-----
6690 04:46:15.624922
6691 04:46:15.625070 ==
6692 04:46:15.627735 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 04:46:15.631315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 04:46:15.631498 ==
6695 04:46:15.634347 [Gating] SW mode calibration
6696 04:46:15.640989 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6697 04:46:15.647775 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6698 04:46:15.651215 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6699 04:46:15.657634 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6700 04:46:15.660988 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6701 04:46:15.664216 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6702 04:46:15.670916 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 04:46:15.674458 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6704 04:46:15.677869 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6705 04:46:15.684137 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6706 04:46:15.687661 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6707 04:46:15.690755 Total UI for P1: 0, mck2ui 16
6708 04:46:15.694411 best dqsien dly found for B0: ( 0, 14, 24)
6709 04:46:15.698153 Total UI for P1: 0, mck2ui 16
6710 04:46:15.701023 best dqsien dly found for B1: ( 0, 14, 24)
6711 04:46:15.704065 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6712 04:46:15.707845 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6713 04:46:15.708365
6714 04:46:15.710968 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6715 04:46:15.714083 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6716 04:46:15.717712 [Gating] SW calibration Done
6717 04:46:15.718231 ==
6718 04:46:15.720968 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 04:46:15.723637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 04:46:15.727473 ==
6721 04:46:15.727894 RX Vref Scan: 0
6722 04:46:15.728229
6723 04:46:15.730294 RX Vref 0 -> 0, step: 1
6724 04:46:15.730712
6725 04:46:15.734055 RX Delay -410 -> 252, step: 16
6726 04:46:15.737510 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6727 04:46:15.740072 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6728 04:46:15.743525 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6729 04:46:15.750415 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6730 04:46:15.753324 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6731 04:46:15.756728 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6732 04:46:15.763142 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6733 04:46:15.766826 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6734 04:46:15.769940 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6735 04:46:15.773190 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6736 04:46:15.779742 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6737 04:46:15.783472 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6738 04:46:15.786664 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6739 04:46:15.789862 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6740 04:46:15.796085 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6741 04:46:15.799935 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6742 04:46:15.800495 ==
6743 04:46:15.803128 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 04:46:15.806279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 04:46:15.806842 ==
6746 04:46:15.809436 DQS Delay:
6747 04:46:15.809998 DQS0 = 35, DQS1 = 51
6748 04:46:15.813254 DQM Delay:
6749 04:46:15.813728 DQM0 = 6, DQM1 = 14
6750 04:46:15.814101 DQ Delay:
6751 04:46:15.816135 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6752 04:46:15.819211 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6753 04:46:15.822410 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6754 04:46:15.826166 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =16
6755 04:46:15.826695
6756 04:46:15.827031
6757 04:46:15.827340 ==
6758 04:46:15.829485 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 04:46:15.835613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 04:46:15.836206 ==
6761 04:46:15.836556
6762 04:46:15.836863
6763 04:46:15.837159 TX Vref Scan disable
6764 04:46:15.838717 == TX Byte 0 ==
6765 04:46:15.842304 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 04:46:15.845963 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 04:46:15.848736 == TX Byte 1 ==
6768 04:46:15.853034 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 04:46:15.855275 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 04:46:15.859004 ==
6771 04:46:15.861699 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 04:46:15.865386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 04:46:15.865807 ==
6774 04:46:15.866144
6775 04:46:15.866496
6776 04:46:15.868175 TX Vref Scan disable
6777 04:46:15.868592 == TX Byte 0 ==
6778 04:46:15.871706 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 04:46:15.878439 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 04:46:15.878962 == TX Byte 1 ==
6781 04:46:15.881409 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 04:46:15.888620 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 04:46:15.889148
6784 04:46:15.889485 [DATLAT]
6785 04:46:15.889800 Freq=400, CH1 RK0
6786 04:46:15.890125
6787 04:46:15.891807 DATLAT Default: 0xf
6788 04:46:15.894897 0, 0xFFFF, sum = 0
6789 04:46:15.895467 1, 0xFFFF, sum = 0
6790 04:46:15.898557 2, 0xFFFF, sum = 0
6791 04:46:15.899254 3, 0xFFFF, sum = 0
6792 04:46:15.901241 4, 0xFFFF, sum = 0
6793 04:46:15.901769 5, 0xFFFF, sum = 0
6794 04:46:15.904803 6, 0xFFFF, sum = 0
6795 04:46:15.905355 7, 0xFFFF, sum = 0
6796 04:46:15.907988 8, 0xFFFF, sum = 0
6797 04:46:15.908414 9, 0xFFFF, sum = 0
6798 04:46:15.911492 10, 0xFFFF, sum = 0
6799 04:46:15.912028 11, 0xFFFF, sum = 0
6800 04:46:15.914684 12, 0xFFFF, sum = 0
6801 04:46:15.915108 13, 0x0, sum = 1
6802 04:46:15.917779 14, 0x0, sum = 2
6803 04:46:15.918202 15, 0x0, sum = 3
6804 04:46:15.921182 16, 0x0, sum = 4
6805 04:46:15.921712 best_step = 14
6806 04:46:15.922054
6807 04:46:15.922366 ==
6808 04:46:15.924137 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 04:46:15.931500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 04:46:15.932025 ==
6811 04:46:15.932363 RX Vref Scan: 1
6812 04:46:15.932678
6813 04:46:15.934305 RX Vref 0 -> 0, step: 1
6814 04:46:15.934720
6815 04:46:15.937934 RX Delay -343 -> 252, step: 8
6816 04:46:15.938352
6817 04:46:15.941420 Set Vref, RX VrefLevel [Byte0]: 54
6818 04:46:15.944910 [Byte1]: 54
6819 04:46:15.947312
6820 04:46:15.947778 Final RX Vref Byte 0 = 54 to rank0
6821 04:46:15.950859 Final RX Vref Byte 1 = 54 to rank0
6822 04:46:15.953764 Final RX Vref Byte 0 = 54 to rank1
6823 04:46:15.956817 Final RX Vref Byte 1 = 54 to rank1==
6824 04:46:15.960233 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 04:46:15.967030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 04:46:15.967578 ==
6827 04:46:15.967923 DQS Delay:
6828 04:46:15.970355 DQS0 = 44, DQS1 = 52
6829 04:46:15.970879 DQM Delay:
6830 04:46:15.971248 DQM0 = 10, DQM1 = 10
6831 04:46:15.973792 DQ Delay:
6832 04:46:15.977225 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6833 04:46:15.977749 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6834 04:46:15.980195 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6835 04:46:15.983852 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6836 04:46:15.987144
6837 04:46:15.987591
6838 04:46:15.993823 [DQSOSCAuto] RK0, (LSB)MR18= 0x688f, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6839 04:46:15.997133 CH1 RK0: MR19=C0C, MR18=688F
6840 04:46:16.003785 CH1_RK0: MR19=0xC0C, MR18=0x688F, DQSOSC=391, MR23=63, INC=386, DEC=257
6841 04:46:16.004310 ==
6842 04:46:16.006283 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 04:46:16.010008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 04:46:16.010533 ==
6845 04:46:16.012748 [Gating] SW mode calibration
6846 04:46:16.019652 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6847 04:46:16.025850 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6848 04:46:16.029398 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6849 04:46:16.032630 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6850 04:46:16.038971 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6851 04:46:16.042704 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6852 04:46:16.045851 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 04:46:16.052993 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6854 04:46:16.055520 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6855 04:46:16.059261 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6856 04:46:16.065371 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6857 04:46:16.069345 Total UI for P1: 0, mck2ui 16
6858 04:46:16.072455 best dqsien dly found for B0: ( 0, 14, 24)
6859 04:46:16.075847 Total UI for P1: 0, mck2ui 16
6860 04:46:16.079193 best dqsien dly found for B1: ( 0, 14, 24)
6861 04:46:16.082525 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6862 04:46:16.085781 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6863 04:46:16.086350
6864 04:46:16.088713 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6865 04:46:16.092248 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6866 04:46:16.095522 [Gating] SW calibration Done
6867 04:46:16.096167 ==
6868 04:46:16.098739 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 04:46:16.102191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 04:46:16.102769 ==
6871 04:46:16.105300 RX Vref Scan: 0
6872 04:46:16.105764
6873 04:46:16.108718 RX Vref 0 -> 0, step: 1
6874 04:46:16.109285
6875 04:46:16.109661 RX Delay -410 -> 252, step: 16
6876 04:46:16.115517 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6877 04:46:16.118913 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6878 04:46:16.121837 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6879 04:46:16.125463 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6880 04:46:16.131856 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6881 04:46:16.135694 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6882 04:46:16.138251 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6883 04:46:16.145223 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6884 04:46:16.148278 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6885 04:46:16.151859 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6886 04:46:16.155171 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6887 04:46:16.161190 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6888 04:46:16.164838 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6889 04:46:16.168004 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6890 04:46:16.171344 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6891 04:46:16.177932 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6892 04:46:16.178451 ==
6893 04:46:16.180909 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 04:46:16.184230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 04:46:16.184647 ==
6896 04:46:16.187767 DQS Delay:
6897 04:46:16.188280 DQS0 = 43, DQS1 = 51
6898 04:46:16.188660 DQM Delay:
6899 04:46:16.190916 DQM0 = 10, DQM1 = 13
6900 04:46:16.191342 DQ Delay:
6901 04:46:16.194670 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6902 04:46:16.197883 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6903 04:46:16.201609 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6904 04:46:16.204293 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6905 04:46:16.204807
6906 04:46:16.205135
6907 04:46:16.205441 ==
6908 04:46:16.207602 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 04:46:16.211009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 04:46:16.214085 ==
6911 04:46:16.214506
6912 04:46:16.214904
6913 04:46:16.215269 TX Vref Scan disable
6914 04:46:16.217292 == TX Byte 0 ==
6915 04:46:16.220959 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6916 04:46:16.223620 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6917 04:46:16.227167 == TX Byte 1 ==
6918 04:46:16.230276 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6919 04:46:16.233736 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6920 04:46:16.234261 ==
6921 04:46:16.237306 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 04:46:16.243790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 04:46:16.244325 ==
6924 04:46:16.244664
6925 04:46:16.244971
6926 04:46:16.245264 TX Vref Scan disable
6927 04:46:16.247253 == TX Byte 0 ==
6928 04:46:16.250586 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6929 04:46:16.253931 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6930 04:46:16.256766 == TX Byte 1 ==
6931 04:46:16.260141 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6932 04:46:16.263621 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6933 04:46:16.264038
6934 04:46:16.266642 [DATLAT]
6935 04:46:16.267164 Freq=400, CH1 RK1
6936 04:46:16.267562
6937 04:46:16.270361 DATLAT Default: 0xe
6938 04:46:16.270783 0, 0xFFFF, sum = 0
6939 04:46:16.273159 1, 0xFFFF, sum = 0
6940 04:46:16.273586 2, 0xFFFF, sum = 0
6941 04:46:16.276300 3, 0xFFFF, sum = 0
6942 04:46:16.276728 4, 0xFFFF, sum = 0
6943 04:46:16.279706 5, 0xFFFF, sum = 0
6944 04:46:16.280137 6, 0xFFFF, sum = 0
6945 04:46:16.282988 7, 0xFFFF, sum = 0
6946 04:46:16.283455 8, 0xFFFF, sum = 0
6947 04:46:16.286634 9, 0xFFFF, sum = 0
6948 04:46:16.289925 10, 0xFFFF, sum = 0
6949 04:46:16.290462 11, 0xFFFF, sum = 0
6950 04:46:16.293325 12, 0xFFFF, sum = 0
6951 04:46:16.293863 13, 0x0, sum = 1
6952 04:46:16.296642 14, 0x0, sum = 2
6953 04:46:16.297180 15, 0x0, sum = 3
6954 04:46:16.299781 16, 0x0, sum = 4
6955 04:46:16.300321 best_step = 14
6956 04:46:16.300770
6957 04:46:16.301189 ==
6958 04:46:16.303308 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 04:46:16.306248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 04:46:16.306784 ==
6961 04:46:16.309557 RX Vref Scan: 0
6962 04:46:16.310085
6963 04:46:16.313011 RX Vref 0 -> 0, step: 1
6964 04:46:16.313448
6965 04:46:16.313985 RX Delay -343 -> 252, step: 8
6966 04:46:16.321437 iDelay=217, Bit 0, Center -32 (-279 ~ 216) 496
6967 04:46:16.325031 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6968 04:46:16.328028 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6969 04:46:16.334866 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6970 04:46:16.337770 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6971 04:46:16.341804 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6972 04:46:16.344716 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6973 04:46:16.351576 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6974 04:46:16.354532 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6975 04:46:16.357874 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6976 04:46:16.361056 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6977 04:46:16.367542 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6978 04:46:16.370850 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6979 04:46:16.374384 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6980 04:46:16.377687 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6981 04:46:16.384305 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6982 04:46:16.384849 ==
6983 04:46:16.387034 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 04:46:16.390622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 04:46:16.391217 ==
6986 04:46:16.391717 DQS Delay:
6987 04:46:16.394051 DQS0 = 48, DQS1 = 52
6988 04:46:16.394594 DQM Delay:
6989 04:46:16.397541 DQM0 = 11, DQM1 = 10
6990 04:46:16.398086 DQ Delay:
6991 04:46:16.400704 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6992 04:46:16.403954 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6993 04:46:16.407198 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6994 04:46:16.410538 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6995 04:46:16.411080
6996 04:46:16.411615
6997 04:46:16.416966 [DQSOSCAuto] RK1, (LSB)MR18= 0x71a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
6998 04:46:16.420296 CH1 RK1: MR19=C0C, MR18=71A9
6999 04:46:16.426795 CH1_RK1: MR19=0xC0C, MR18=0x71A9, DQSOSC=388, MR23=63, INC=392, DEC=261
7000 04:46:16.430322 [RxdqsGatingPostProcess] freq 400
7001 04:46:16.436930 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7002 04:46:16.440265 best DQS0 dly(2T, 0.5T) = (0, 10)
7003 04:46:16.443826 best DQS1 dly(2T, 0.5T) = (0, 10)
7004 04:46:16.447188 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7005 04:46:16.449831 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7006 04:46:16.453357 best DQS0 dly(2T, 0.5T) = (0, 10)
7007 04:46:16.453781 best DQS1 dly(2T, 0.5T) = (0, 10)
7008 04:46:16.456899 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7009 04:46:16.459763 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7010 04:46:16.463492 Pre-setting of DQS Precalculation
7011 04:46:16.469678 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7012 04:46:16.476128 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7013 04:46:16.483019 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7014 04:46:16.483552
7015 04:46:16.483969
7016 04:46:16.485958 [Calibration Summary] 800 Mbps
7017 04:46:16.490075 CH 0, Rank 0
7018 04:46:16.490599 SW Impedance : PASS
7019 04:46:16.492627 DUTY Scan : NO K
7020 04:46:16.493049 ZQ Calibration : PASS
7021 04:46:16.496055 Jitter Meter : NO K
7022 04:46:16.499925 CBT Training : PASS
7023 04:46:16.500450 Write leveling : PASS
7024 04:46:16.503073 RX DQS gating : PASS
7025 04:46:16.506568 RX DQ/DQS(RDDQC) : PASS
7026 04:46:16.507080 TX DQ/DQS : PASS
7027 04:46:16.509690 RX DATLAT : PASS
7028 04:46:16.512683 RX DQ/DQS(Engine): PASS
7029 04:46:16.513110 TX OE : NO K
7030 04:46:16.516327 All Pass.
7031 04:46:16.516748
7032 04:46:16.517083 CH 0, Rank 1
7033 04:46:16.519217 SW Impedance : PASS
7034 04:46:16.519675 DUTY Scan : NO K
7035 04:46:16.522487 ZQ Calibration : PASS
7036 04:46:16.525737 Jitter Meter : NO K
7037 04:46:16.526160 CBT Training : PASS
7038 04:46:16.528964 Write leveling : NO K
7039 04:46:16.532407 RX DQS gating : PASS
7040 04:46:16.532829 RX DQ/DQS(RDDQC) : PASS
7041 04:46:16.535529 TX DQ/DQS : PASS
7042 04:46:16.538932 RX DATLAT : PASS
7043 04:46:16.539396 RX DQ/DQS(Engine): PASS
7044 04:46:16.542401 TX OE : NO K
7045 04:46:16.542827 All Pass.
7046 04:46:16.543169
7047 04:46:16.545594 CH 1, Rank 0
7048 04:46:16.546014 SW Impedance : PASS
7049 04:46:16.549030 DUTY Scan : NO K
7050 04:46:16.552184 ZQ Calibration : PASS
7051 04:46:16.552607 Jitter Meter : NO K
7052 04:46:16.555253 CBT Training : PASS
7053 04:46:16.558742 Write leveling : PASS
7054 04:46:16.559166 RX DQS gating : PASS
7055 04:46:16.562486 RX DQ/DQS(RDDQC) : PASS
7056 04:46:16.565193 TX DQ/DQS : PASS
7057 04:46:16.565617 RX DATLAT : PASS
7058 04:46:16.568746 RX DQ/DQS(Engine): PASS
7059 04:46:16.569209 TX OE : NO K
7060 04:46:16.571821 All Pass.
7061 04:46:16.572242
7062 04:46:16.572574 CH 1, Rank 1
7063 04:46:16.575509 SW Impedance : PASS
7064 04:46:16.575931 DUTY Scan : NO K
7065 04:46:16.578980 ZQ Calibration : PASS
7066 04:46:16.581914 Jitter Meter : NO K
7067 04:46:16.582436 CBT Training : PASS
7068 04:46:16.585068 Write leveling : NO K
7069 04:46:16.588563 RX DQS gating : PASS
7070 04:46:16.588986 RX DQ/DQS(RDDQC) : PASS
7071 04:46:16.591743 TX DQ/DQS : PASS
7072 04:46:16.595028 RX DATLAT : PASS
7073 04:46:16.595586 RX DQ/DQS(Engine): PASS
7074 04:46:16.598825 TX OE : NO K
7075 04:46:16.599343 All Pass.
7076 04:46:16.599792
7077 04:46:16.601529 DramC Write-DBI off
7078 04:46:16.605007 PER_BANK_REFRESH: Hybrid Mode
7079 04:46:16.605525 TX_TRACKING: ON
7080 04:46:16.614932 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7081 04:46:16.618198 [FAST_K] Save calibration result to emmc
7082 04:46:16.621439 dramc_set_vcore_voltage set vcore to 725000
7083 04:46:16.624801 Read voltage for 1600, 0
7084 04:46:16.625317 Vio18 = 0
7085 04:46:16.628343 Vcore = 725000
7086 04:46:16.628764 Vdram = 0
7087 04:46:16.629102 Vddq = 0
7088 04:46:16.629413 Vmddr = 0
7089 04:46:16.634498 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7090 04:46:16.637726 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7091 04:46:16.641338 MEM_TYPE=3, freq_sel=13
7092 04:46:16.644317 sv_algorithm_assistance_LP4_3733
7093 04:46:16.648369 ============ PULL DRAM RESETB DOWN ============
7094 04:46:16.654366 ========== PULL DRAM RESETB DOWN end =========
7095 04:46:16.657564 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7096 04:46:16.661171 ===================================
7097 04:46:16.664287 LPDDR4 DRAM CONFIGURATION
7098 04:46:16.667240 ===================================
7099 04:46:16.667708 EX_ROW_EN[0] = 0x0
7100 04:46:16.671059 EX_ROW_EN[1] = 0x0
7101 04:46:16.671638 LP4Y_EN = 0x0
7102 04:46:16.674392 WORK_FSP = 0x1
7103 04:46:16.674921 WL = 0x5
7104 04:46:16.677338 RL = 0x5
7105 04:46:16.680909 BL = 0x2
7106 04:46:16.681438 RPST = 0x0
7107 04:46:16.684153 RD_PRE = 0x0
7108 04:46:16.684579 WR_PRE = 0x1
7109 04:46:16.687658 WR_PST = 0x1
7110 04:46:16.688196 DBI_WR = 0x0
7111 04:46:16.690615 DBI_RD = 0x0
7112 04:46:16.691196 OTF = 0x1
7113 04:46:16.693751 ===================================
7114 04:46:16.696823 ===================================
7115 04:46:16.700033 ANA top config
7116 04:46:16.703643 ===================================
7117 04:46:16.704124 DLL_ASYNC_EN = 0
7118 04:46:16.707545 ALL_SLAVE_EN = 0
7119 04:46:16.710078 NEW_RANK_MODE = 1
7120 04:46:16.713410 DLL_IDLE_MODE = 1
7121 04:46:16.716746 LP45_APHY_COMB_EN = 1
7122 04:46:16.717169 TX_ODT_DIS = 0
7123 04:46:16.720066 NEW_8X_MODE = 1
7124 04:46:16.723211 ===================================
7125 04:46:16.726450 ===================================
7126 04:46:16.730410 data_rate = 3200
7127 04:46:16.733363 CKR = 1
7128 04:46:16.736618 DQ_P2S_RATIO = 8
7129 04:46:16.739669 ===================================
7130 04:46:16.742935 CA_P2S_RATIO = 8
7131 04:46:16.743411 DQ_CA_OPEN = 0
7132 04:46:16.746743 DQ_SEMI_OPEN = 0
7133 04:46:16.749977 CA_SEMI_OPEN = 0
7134 04:46:16.753511 CA_FULL_RATE = 0
7135 04:46:16.756511 DQ_CKDIV4_EN = 0
7136 04:46:16.759733 CA_CKDIV4_EN = 0
7137 04:46:16.760158 CA_PREDIV_EN = 0
7138 04:46:16.762653 PH8_DLY = 12
7139 04:46:16.765845 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7140 04:46:16.769250 DQ_AAMCK_DIV = 4
7141 04:46:16.772791 CA_AAMCK_DIV = 4
7142 04:46:16.775916 CA_ADMCK_DIV = 4
7143 04:46:16.776338 DQ_TRACK_CA_EN = 0
7144 04:46:16.779738 CA_PICK = 1600
7145 04:46:16.782875 CA_MCKIO = 1600
7146 04:46:16.786098 MCKIO_SEMI = 0
7147 04:46:16.789626 PLL_FREQ = 3068
7148 04:46:16.792909 DQ_UI_PI_RATIO = 32
7149 04:46:16.795599 CA_UI_PI_RATIO = 0
7150 04:46:16.799031 ===================================
7151 04:46:16.802757 ===================================
7152 04:46:16.803181 memory_type:LPDDR4
7153 04:46:16.805789 GP_NUM : 10
7154 04:46:16.809125 SRAM_EN : 1
7155 04:46:16.809552 MD32_EN : 0
7156 04:46:16.811952 ===================================
7157 04:46:16.815760 [ANA_INIT] >>>>>>>>>>>>>>
7158 04:46:16.818915 <<<<<< [CONFIGURE PHASE]: ANA_TX
7159 04:46:16.822243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7160 04:46:16.825690 ===================================
7161 04:46:16.828396 data_rate = 3200,PCW = 0X7600
7162 04:46:16.832082 ===================================
7163 04:46:16.835879 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7164 04:46:16.842640 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7165 04:46:16.845116 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7166 04:46:16.851599 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7167 04:46:16.855541 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7168 04:46:16.858496 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7169 04:46:16.859019 [ANA_INIT] flow start
7170 04:46:16.861738 [ANA_INIT] PLL >>>>>>>>
7171 04:46:16.864684 [ANA_INIT] PLL <<<<<<<<
7172 04:46:16.865108 [ANA_INIT] MIDPI >>>>>>>>
7173 04:46:16.868131 [ANA_INIT] MIDPI <<<<<<<<
7174 04:46:16.871335 [ANA_INIT] DLL >>>>>>>>
7175 04:46:16.871786 [ANA_INIT] DLL <<<<<<<<
7176 04:46:16.874968 [ANA_INIT] flow end
7177 04:46:16.878426 ============ LP4 DIFF to SE enter ============
7178 04:46:16.884593 ============ LP4 DIFF to SE exit ============
7179 04:46:16.885113 [ANA_INIT] <<<<<<<<<<<<<
7180 04:46:16.887793 [Flow] Enable top DCM control >>>>>
7181 04:46:16.891277 [Flow] Enable top DCM control <<<<<
7182 04:46:16.895012 Enable DLL master slave shuffle
7183 04:46:16.901102 ==============================================================
7184 04:46:16.901690 Gating Mode config
7185 04:46:16.908047 ==============================================================
7186 04:46:16.911267 Config description:
7187 04:46:16.920606 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7188 04:46:16.927174 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7189 04:46:16.930676 SELPH_MODE 0: By rank 1: By Phase
7190 04:46:16.937375 ==============================================================
7191 04:46:16.940558 GAT_TRACK_EN = 1
7192 04:46:16.943915 RX_GATING_MODE = 2
7193 04:46:16.947138 RX_GATING_TRACK_MODE = 2
7194 04:46:16.947750 SELPH_MODE = 1
7195 04:46:16.950312 PICG_EARLY_EN = 1
7196 04:46:16.953527 VALID_LAT_VALUE = 1
7197 04:46:16.960173 ==============================================================
7198 04:46:16.963529 Enter into Gating configuration >>>>
7199 04:46:16.966445 Exit from Gating configuration <<<<
7200 04:46:16.970156 Enter into DVFS_PRE_config >>>>>
7201 04:46:16.979828 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7202 04:46:16.983299 Exit from DVFS_PRE_config <<<<<
7203 04:46:16.986317 Enter into PICG configuration >>>>
7204 04:46:16.989608 Exit from PICG configuration <<<<
7205 04:46:16.993051 [RX_INPUT] configuration >>>>>
7206 04:46:16.996043 [RX_INPUT] configuration <<<<<
7207 04:46:16.999930 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7208 04:46:17.006343 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7209 04:46:17.012770 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7210 04:46:17.019334 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7211 04:46:17.025477 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7212 04:46:17.032163 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7213 04:46:17.035794 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7214 04:46:17.038923 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7215 04:46:17.042706 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7216 04:46:17.048474 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7217 04:46:17.052098 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7218 04:46:17.055203 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7219 04:46:17.059536 ===================================
7220 04:46:17.061823 LPDDR4 DRAM CONFIGURATION
7221 04:46:17.065026 ===================================
7222 04:46:17.065453 EX_ROW_EN[0] = 0x0
7223 04:46:17.068387 EX_ROW_EN[1] = 0x0
7224 04:46:17.071786 LP4Y_EN = 0x0
7225 04:46:17.072209 WORK_FSP = 0x1
7226 04:46:17.075002 WL = 0x5
7227 04:46:17.075594 RL = 0x5
7228 04:46:17.078760 BL = 0x2
7229 04:46:17.079180 RPST = 0x0
7230 04:46:17.081964 RD_PRE = 0x0
7231 04:46:17.082384 WR_PRE = 0x1
7232 04:46:17.084878 WR_PST = 0x1
7233 04:46:17.085301 DBI_WR = 0x0
7234 04:46:17.088057 DBI_RD = 0x0
7235 04:46:17.088481 OTF = 0x1
7236 04:46:17.091639 ===================================
7237 04:46:17.094998 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7238 04:46:17.101614 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7239 04:46:17.105047 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7240 04:46:17.108037 ===================================
7241 04:46:17.111524 LPDDR4 DRAM CONFIGURATION
7242 04:46:17.114670 ===================================
7243 04:46:17.117993 EX_ROW_EN[0] = 0x10
7244 04:46:17.118416 EX_ROW_EN[1] = 0x0
7245 04:46:17.121428 LP4Y_EN = 0x0
7246 04:46:17.121850 WORK_FSP = 0x1
7247 04:46:17.124731 WL = 0x5
7248 04:46:17.125167 RL = 0x5
7249 04:46:17.128118 BL = 0x2
7250 04:46:17.128540 RPST = 0x0
7251 04:46:17.130956 RD_PRE = 0x0
7252 04:46:17.131412 WR_PRE = 0x1
7253 04:46:17.134717 WR_PST = 0x1
7254 04:46:17.135137 DBI_WR = 0x0
7255 04:46:17.137769 DBI_RD = 0x0
7256 04:46:17.138284 OTF = 0x1
7257 04:46:17.141188 ===================================
7258 04:46:17.147516 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7259 04:46:17.147944 ==
7260 04:46:17.150813 Dram Type= 6, Freq= 0, CH_0, rank 0
7261 04:46:17.157515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7262 04:46:17.157940 ==
7263 04:46:17.158357 [Duty_Offset_Calibration]
7264 04:46:17.160670 B0:2 B1:0 CA:4
7265 04:46:17.161093
7266 04:46:17.164213 [DutyScan_Calibration_Flow] k_type=0
7267 04:46:17.173007
7268 04:46:17.173429 ==CLK 0==
7269 04:46:17.176007 Final CLK duty delay cell = -4
7270 04:46:17.178955 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7271 04:46:17.182560 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7272 04:46:17.185733 [-4] AVG Duty = 4922%(X100)
7273 04:46:17.186156
7274 04:46:17.189215 CH0 CLK Duty spec in!! Max-Min= 218%
7275 04:46:17.192130 [DutyScan_Calibration_Flow] ====Done====
7276 04:46:17.192599
7277 04:46:17.195638 [DutyScan_Calibration_Flow] k_type=1
7278 04:46:17.213405
7279 04:46:17.214019 ==DQS 0 ==
7280 04:46:17.216653 Final DQS duty delay cell = 0
7281 04:46:17.219592 [0] MAX Duty = 5218%(X100), DQS PI = 22
7282 04:46:17.222793 [0] MIN Duty = 5093%(X100), DQS PI = 10
7283 04:46:17.226356 [0] AVG Duty = 5155%(X100)
7284 04:46:17.226882
7285 04:46:17.227227 ==DQS 1 ==
7286 04:46:17.229086 Final DQS duty delay cell = 0
7287 04:46:17.232521 [0] MAX Duty = 5187%(X100), DQS PI = 2
7288 04:46:17.236021 [0] MIN Duty = 4969%(X100), DQS PI = 10
7289 04:46:17.239666 [0] AVG Duty = 5078%(X100)
7290 04:46:17.240087
7291 04:46:17.242646 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7292 04:46:17.243069
7293 04:46:17.245883 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7294 04:46:17.249598 [DutyScan_Calibration_Flow] ====Done====
7295 04:46:17.250123
7296 04:46:17.252009 [DutyScan_Calibration_Flow] k_type=3
7297 04:46:17.270151
7298 04:46:17.270734 ==DQM 0 ==
7299 04:46:17.273881 Final DQM duty delay cell = 0
7300 04:46:17.276983 [0] MAX Duty = 5124%(X100), DQS PI = 22
7301 04:46:17.279949 [0] MIN Duty = 4875%(X100), DQS PI = 54
7302 04:46:17.283919 [0] AVG Duty = 4999%(X100)
7303 04:46:17.284429
7304 04:46:17.284763 ==DQM 1 ==
7305 04:46:17.286801 Final DQM duty delay cell = 0
7306 04:46:17.289929 [0] MAX Duty = 5000%(X100), DQS PI = 4
7307 04:46:17.293272 [0] MIN Duty = 4844%(X100), DQS PI = 16
7308 04:46:17.296164 [0] AVG Duty = 4922%(X100)
7309 04:46:17.296644
7310 04:46:17.299889 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7311 04:46:17.300310
7312 04:46:17.303257 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7313 04:46:17.306071 [DutyScan_Calibration_Flow] ====Done====
7314 04:46:17.306490
7315 04:46:17.309954 [DutyScan_Calibration_Flow] k_type=2
7316 04:46:17.327461
7317 04:46:17.327895 ==DQ 0 ==
7318 04:46:17.330492 Final DQ duty delay cell = 0
7319 04:46:17.333863 [0] MAX Duty = 5156%(X100), DQS PI = 20
7320 04:46:17.336832 [0] MIN Duty = 4938%(X100), DQS PI = 12
7321 04:46:17.340214 [0] AVG Duty = 5047%(X100)
7322 04:46:17.340637
7323 04:46:17.340971 ==DQ 1 ==
7324 04:46:17.343278 Final DQ duty delay cell = 0
7325 04:46:17.346712 [0] MAX Duty = 5218%(X100), DQS PI = 2
7326 04:46:17.350251 [0] MIN Duty = 4938%(X100), DQS PI = 12
7327 04:46:17.350677 [0] AVG Duty = 5078%(X100)
7328 04:46:17.353303
7329 04:46:17.357016 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7330 04:46:17.357439
7331 04:46:17.360582 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7332 04:46:17.363456 [DutyScan_Calibration_Flow] ====Done====
7333 04:46:17.363886 ==
7334 04:46:17.366371 Dram Type= 6, Freq= 0, CH_1, rank 0
7335 04:46:17.369847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7336 04:46:17.370273 ==
7337 04:46:17.373176 [Duty_Offset_Calibration]
7338 04:46:17.373596 B0:0 B1:-1 CA:3
7339 04:46:17.373936
7340 04:46:17.376388 [DutyScan_Calibration_Flow] k_type=0
7341 04:46:17.386427
7342 04:46:17.386851 ==CLK 0==
7343 04:46:17.389665 Final CLK duty delay cell = -4
7344 04:46:17.392940 [-4] MAX Duty = 5000%(X100), DQS PI = 2
7345 04:46:17.396514 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7346 04:46:17.399281 [-4] AVG Duty = 4937%(X100)
7347 04:46:17.399386
7348 04:46:17.402845 CH1 CLK Duty spec in!! Max-Min= 125%
7349 04:46:17.405872 [DutyScan_Calibration_Flow] ====Done====
7350 04:46:17.405954
7351 04:46:17.409086 [DutyScan_Calibration_Flow] k_type=1
7352 04:46:17.425161
7353 04:46:17.425244 ==DQS 0 ==
7354 04:46:17.429259 Final DQS duty delay cell = 0
7355 04:46:17.432288 [0] MAX Duty = 5250%(X100), DQS PI = 28
7356 04:46:17.435922 [0] MIN Duty = 4938%(X100), DQS PI = 42
7357 04:46:17.438958 [0] AVG Duty = 5094%(X100)
7358 04:46:17.439523
7359 04:46:17.439893 ==DQS 1 ==
7360 04:46:17.442585 Final DQS duty delay cell = -4
7361 04:46:17.445864 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7362 04:46:17.448435 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7363 04:46:17.451803 [-4] AVG Duty = 4922%(X100)
7364 04:46:17.452219
7365 04:46:17.455472 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7366 04:46:17.455892
7367 04:46:17.458618 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7368 04:46:17.462438 [DutyScan_Calibration_Flow] ====Done====
7369 04:46:17.462891
7370 04:46:17.465319 [DutyScan_Calibration_Flow] k_type=3
7371 04:46:17.483290
7372 04:46:17.483848 ==DQM 0 ==
7373 04:46:17.486031 Final DQM duty delay cell = 0
7374 04:46:17.489625 [0] MAX Duty = 5062%(X100), DQS PI = 32
7375 04:46:17.493181 [0] MIN Duty = 4782%(X100), DQS PI = 38
7376 04:46:17.496202 [0] AVG Duty = 4922%(X100)
7377 04:46:17.496666
7378 04:46:17.497031 ==DQM 1 ==
7379 04:46:17.499528 Final DQM duty delay cell = 0
7380 04:46:17.502662 [0] MAX Duty = 5000%(X100), DQS PI = 32
7381 04:46:17.505863 [0] MIN Duty = 4813%(X100), DQS PI = 0
7382 04:46:17.509453 [0] AVG Duty = 4906%(X100)
7383 04:46:17.509875
7384 04:46:17.512649 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7385 04:46:17.513072
7386 04:46:17.515739 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7387 04:46:17.518990 [DutyScan_Calibration_Flow] ====Done====
7388 04:46:17.519439
7389 04:46:17.522046 [DutyScan_Calibration_Flow] k_type=2
7390 04:46:17.539156
7391 04:46:17.539623 ==DQ 0 ==
7392 04:46:17.542297 Final DQ duty delay cell = -4
7393 04:46:17.545736 [-4] MAX Duty = 4938%(X100), DQS PI = 16
7394 04:46:17.548699 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7395 04:46:17.552457 [-4] AVG Duty = 4875%(X100)
7396 04:46:17.552870
7397 04:46:17.553195 ==DQ 1 ==
7398 04:46:17.555534 Final DQ duty delay cell = 0
7399 04:46:17.558640 [0] MAX Duty = 5062%(X100), DQS PI = 32
7400 04:46:17.562365 [0] MIN Duty = 4875%(X100), DQS PI = 54
7401 04:46:17.565958 [0] AVG Duty = 4968%(X100)
7402 04:46:17.566390
7403 04:46:17.568757 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7404 04:46:17.569175
7405 04:46:17.571886 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7406 04:46:17.574968 [DutyScan_Calibration_Flow] ====Done====
7407 04:46:17.578186 nWR fixed to 30
7408 04:46:17.581758 [ModeRegInit_LP4] CH0 RK0
7409 04:46:17.582177 [ModeRegInit_LP4] CH0 RK1
7410 04:46:17.585614 [ModeRegInit_LP4] CH1 RK0
7411 04:46:17.588610 [ModeRegInit_LP4] CH1 RK1
7412 04:46:17.589031 match AC timing 5
7413 04:46:17.594961 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7414 04:46:17.598122 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7415 04:46:17.601310 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7416 04:46:17.607995 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7417 04:46:17.611656 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7418 04:46:17.614563 [MiockJmeterHQA]
7419 04:46:17.614977
7420 04:46:17.617782 [DramcMiockJmeter] u1RxGatingPI = 0
7421 04:46:17.618204 0 : 4365, 4140
7422 04:46:17.618548 4 : 4252, 4027
7423 04:46:17.621453 8 : 4363, 4138
7424 04:46:17.621877 12 : 4252, 4026
7425 04:46:17.625034 16 : 4253, 4026
7426 04:46:17.625589 20 : 4363, 4137
7427 04:46:17.627701 24 : 4363, 4138
7428 04:46:17.628127 28 : 4252, 4026
7429 04:46:17.628469 32 : 4252, 4027
7430 04:46:17.631398 36 : 4252, 4027
7431 04:46:17.631836 40 : 4252, 4026
7432 04:46:17.634431 44 : 4255, 4030
7433 04:46:17.634860 48 : 4363, 4138
7434 04:46:17.637636 52 : 4250, 4027
7435 04:46:17.638063 56 : 4250, 4027
7436 04:46:17.640988 60 : 4250, 4026
7437 04:46:17.641412 64 : 4252, 4030
7438 04:46:17.641791 68 : 4250, 4027
7439 04:46:17.644401 72 : 4361, 4137
7440 04:46:17.644841 76 : 4360, 4138
7441 04:46:17.647433 80 : 4250, 4027
7442 04:46:17.647862 84 : 4250, 4027
7443 04:46:17.650755 88 : 4250, 4027
7444 04:46:17.651280 92 : 4250, 4026
7445 04:46:17.654022 96 : 4252, 3343
7446 04:46:17.654459 100 : 4361, 0
7447 04:46:17.654800 104 : 4252, 0
7448 04:46:17.657630 108 : 4360, 0
7449 04:46:17.658060 112 : 4250, 0
7450 04:46:17.661113 116 : 4250, 0
7451 04:46:17.661540 120 : 4250, 0
7452 04:46:17.661878 124 : 4250, 0
7453 04:46:17.664778 128 : 4250, 0
7454 04:46:17.665205 132 : 4252, 0
7455 04:46:17.667115 136 : 4250, 0
7456 04:46:17.667575 140 : 4250, 0
7457 04:46:17.667919 144 : 4252, 0
7458 04:46:17.670670 148 : 4250, 0
7459 04:46:17.671101 152 : 4361, 0
7460 04:46:17.671608 156 : 4360, 0
7461 04:46:17.674143 160 : 4250, 0
7462 04:46:17.674668 164 : 4361, 0
7463 04:46:17.677936 168 : 4249, 0
7464 04:46:17.678364 172 : 4250, 0
7465 04:46:17.678709 176 : 4250, 0
7466 04:46:17.680422 180 : 4250, 0
7467 04:46:17.680854 184 : 4252, 0
7468 04:46:17.683893 188 : 4250, 0
7469 04:46:17.684326 192 : 4250, 0
7470 04:46:17.684667 196 : 4253, 0
7471 04:46:17.687255 200 : 4252, 0
7472 04:46:17.687745 204 : 4361, 0
7473 04:46:17.690631 208 : 4360, 0
7474 04:46:17.691153 212 : 4250, 0
7475 04:46:17.691563 216 : 4361, 0
7476 04:46:17.693625 220 : 4361, 304
7477 04:46:17.694053 224 : 4250, 3827
7478 04:46:17.697163 228 : 4250, 4027
7479 04:46:17.697693 232 : 4250, 4027
7480 04:46:17.700882 236 : 4250, 4027
7481 04:46:17.701310 240 : 4250, 4026
7482 04:46:17.703864 244 : 4361, 4138
7483 04:46:17.704294 248 : 4250, 4027
7484 04:46:17.707421 252 : 4249, 4027
7485 04:46:17.707949 256 : 4363, 4140
7486 04:46:17.710674 260 : 4250, 4027
7487 04:46:17.711209 264 : 4250, 4027
7488 04:46:17.711658 268 : 4363, 4140
7489 04:46:17.713966 272 : 4249, 4027
7490 04:46:17.714393 276 : 4250, 4026
7491 04:46:17.716509 280 : 4250, 4027
7492 04:46:17.716969 284 : 4252, 4030
7493 04:46:17.720312 288 : 4249, 4027
7494 04:46:17.720832 292 : 4250, 4026
7495 04:46:17.723635 296 : 4361, 4137
7496 04:46:17.724159 300 : 4250, 4027
7497 04:46:17.726648 304 : 4250, 4027
7498 04:46:17.727072 308 : 4361, 4137
7499 04:46:17.730208 312 : 4250, 4027
7500 04:46:17.730733 316 : 4250, 4027
7501 04:46:17.733088 320 : 4363, 4140
7502 04:46:17.733738 324 : 4249, 4027
7503 04:46:17.736256 328 : 4250, 4027
7504 04:46:17.736682 332 : 4250, 4024
7505 04:46:17.739830 336 : 4252, 2125
7506 04:46:17.740254
7507 04:46:17.740689 MIOCK jitter meter ch=0
7508 04:46:17.741026
7509 04:46:17.742674 1T = (336-100) = 236 dly cells
7510 04:46:17.749939 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7511 04:46:17.750462 ==
7512 04:46:17.753098 Dram Type= 6, Freq= 0, CH_0, rank 0
7513 04:46:17.756036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7514 04:46:17.756457 ==
7515 04:46:17.762672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7516 04:46:17.766069 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7517 04:46:17.772426 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7518 04:46:17.775698 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7519 04:46:17.785435 [CA 0] Center 43 (13~73) winsize 61
7520 04:46:17.789012 [CA 1] Center 42 (12~73) winsize 62
7521 04:46:17.792304 [CA 2] Center 37 (8~67) winsize 60
7522 04:46:17.795811 [CA 3] Center 37 (8~67) winsize 60
7523 04:46:17.798670 [CA 4] Center 36 (6~66) winsize 61
7524 04:46:17.801876 [CA 5] Center 35 (5~66) winsize 62
7525 04:46:17.802300
7526 04:46:17.805369 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7527 04:46:17.805791
7528 04:46:17.811736 [CATrainingPosCal] consider 1 rank data
7529 04:46:17.812161 u2DelayCellTimex100 = 275/100 ps
7530 04:46:17.818601 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7531 04:46:17.822305 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7532 04:46:17.825164 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7533 04:46:17.828172 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7534 04:46:17.831800 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7535 04:46:17.834739 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7536 04:46:17.835159
7537 04:46:17.838261 CA PerBit enable=1, Macro0, CA PI delay=35
7538 04:46:17.838680
7539 04:46:17.841582 [CBTSetCACLKResult] CA Dly = 35
7540 04:46:17.844609 CS Dly: 11 (0~42)
7541 04:46:17.847960 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7542 04:46:17.852185 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7543 04:46:17.852605 ==
7544 04:46:17.854677 Dram Type= 6, Freq= 0, CH_0, rank 1
7545 04:46:17.861463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 04:46:17.861885 ==
7547 04:46:17.864613 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7548 04:46:17.870932 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7549 04:46:17.874306 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7550 04:46:17.881244 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7551 04:46:17.889234 [CA 0] Center 44 (14~75) winsize 62
7552 04:46:17.892702 [CA 1] Center 44 (14~74) winsize 61
7553 04:46:17.895984 [CA 2] Center 39 (10~69) winsize 60
7554 04:46:17.899144 [CA 3] Center 39 (10~68) winsize 59
7555 04:46:17.902673 [CA 4] Center 37 (7~67) winsize 61
7556 04:46:17.905537 [CA 5] Center 36 (6~66) winsize 61
7557 04:46:17.906052
7558 04:46:17.908893 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7559 04:46:17.909410
7560 04:46:17.915485 [CATrainingPosCal] consider 2 rank data
7561 04:46:17.916012 u2DelayCellTimex100 = 275/100 ps
7562 04:46:17.922333 CA0 delay=43 (14~73),Diff = 7 PI (24 cell)
7563 04:46:17.925420 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7564 04:46:17.928482 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7565 04:46:17.931964 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7566 04:46:17.935095 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7567 04:46:17.938853 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7568 04:46:17.939413
7569 04:46:17.941982 CA PerBit enable=1, Macro0, CA PI delay=36
7570 04:46:17.942502
7571 04:46:17.945199 [CBTSetCACLKResult] CA Dly = 36
7572 04:46:17.948696 CS Dly: 11 (0~43)
7573 04:46:17.951351 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7574 04:46:17.955159 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7575 04:46:17.955734
7576 04:46:17.958473 ----->DramcWriteLeveling(PI) begin...
7577 04:46:17.962139 ==
7578 04:46:17.964628 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 04:46:17.968154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 04:46:17.968573 ==
7581 04:46:17.971307 Write leveling (Byte 0): 36 => 36
7582 04:46:17.974941 Write leveling (Byte 1): 25 => 25
7583 04:46:17.977996 DramcWriteLeveling(PI) end<-----
7584 04:46:17.978414
7585 04:46:17.978746 ==
7586 04:46:17.981429 Dram Type= 6, Freq= 0, CH_0, rank 0
7587 04:46:17.984441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7588 04:46:17.984957 ==
7589 04:46:17.987667 [Gating] SW mode calibration
7590 04:46:17.994415 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7591 04:46:18.000658 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7592 04:46:18.004463 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 04:46:18.008268 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 04:46:18.014009 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 04:46:18.017546 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7596 04:46:18.020590 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7597 04:46:18.027514 1 4 20 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
7598 04:46:18.030752 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 04:46:18.033849 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 04:46:18.040437 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 04:46:18.043534 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 04:46:18.047234 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
7603 04:46:18.053556 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7604 04:46:18.057257 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7605 04:46:18.060293 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
7606 04:46:18.066814 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7607 04:46:18.070335 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 04:46:18.073656 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 04:46:18.079912 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 04:46:18.083316 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7611 04:46:18.086435 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7612 04:46:18.093464 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7613 04:46:18.096310 1 6 20 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
7614 04:46:18.100107 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 04:46:18.105945 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 04:46:18.109622 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 04:46:18.112586 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 04:46:18.119630 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 04:46:18.122890 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7620 04:46:18.126123 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7621 04:46:18.132233 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7622 04:46:18.135589 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7623 04:46:18.138880 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 04:46:18.145574 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 04:46:18.148784 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 04:46:18.152279 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 04:46:18.158799 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 04:46:18.162024 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 04:46:18.164874 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 04:46:18.171475 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 04:46:18.174720 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 04:46:18.178605 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 04:46:18.184996 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 04:46:18.188471 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7635 04:46:18.194645 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7636 04:46:18.198044 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7637 04:46:18.201552 Total UI for P1: 0, mck2ui 16
7638 04:46:18.204658 best dqsien dly found for B0: ( 1, 9, 10)
7639 04:46:18.207766 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7640 04:46:18.211189 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7641 04:46:18.217644 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 04:46:18.221046 Total UI for P1: 0, mck2ui 16
7643 04:46:18.224006 best dqsien dly found for B1: ( 1, 9, 22)
7644 04:46:18.227467 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7645 04:46:18.231158 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7646 04:46:18.231739
7647 04:46:18.234024 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7648 04:46:18.237098 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7649 04:46:18.241111 [Gating] SW calibration Done
7650 04:46:18.241630 ==
7651 04:46:18.243956 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 04:46:18.247278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 04:46:18.250331 ==
7654 04:46:18.250756 RX Vref Scan: 0
7655 04:46:18.251093
7656 04:46:18.253890 RX Vref 0 -> 0, step: 1
7657 04:46:18.254314
7658 04:46:18.257144 RX Delay 0 -> 252, step: 8
7659 04:46:18.260010 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7660 04:46:18.263749 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7661 04:46:18.266951 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7662 04:46:18.270288 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7663 04:46:18.276937 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7664 04:46:18.279947 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7665 04:46:18.283430 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7666 04:46:18.286859 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7667 04:46:18.290602 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7668 04:46:18.296684 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7669 04:46:18.299918 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7670 04:46:18.303175 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7671 04:46:18.306631 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7672 04:46:18.313055 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7673 04:46:18.316422 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7674 04:46:18.319718 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7675 04:46:18.320182 ==
7676 04:46:18.322665 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 04:46:18.327082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 04:46:18.327701 ==
7679 04:46:18.329557 DQS Delay:
7680 04:46:18.330019 DQS0 = 0, DQS1 = 0
7681 04:46:18.332780 DQM Delay:
7682 04:46:18.333244 DQM0 = 131, DQM1 = 126
7683 04:46:18.333609 DQ Delay:
7684 04:46:18.339546 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7685 04:46:18.342597 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7686 04:46:18.345996 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
7687 04:46:18.349675 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7688 04:46:18.350186
7689 04:46:18.350521
7690 04:46:18.350830 ==
7691 04:46:18.352329 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 04:46:18.355769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 04:46:18.356279 ==
7694 04:46:18.356615
7695 04:46:18.356924
7696 04:46:18.358732 TX Vref Scan disable
7697 04:46:18.362504 == TX Byte 0 ==
7698 04:46:18.365764 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7699 04:46:18.368914 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7700 04:46:18.372233 == TX Byte 1 ==
7701 04:46:18.375321 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7702 04:46:18.379034 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7703 04:46:18.379609 ==
7704 04:46:18.382334 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 04:46:18.388765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 04:46:18.389318 ==
7707 04:46:18.403327
7708 04:46:18.406341 TX Vref early break, caculate TX vref
7709 04:46:18.409729 TX Vref=16, minBit 4, minWin=22, winSum=368
7710 04:46:18.413105 TX Vref=18, minBit 1, minWin=22, winSum=377
7711 04:46:18.415778 TX Vref=20, minBit 1, minWin=24, winSum=391
7712 04:46:18.418984 TX Vref=22, minBit 1, minWin=24, winSum=398
7713 04:46:18.422823 TX Vref=24, minBit 7, minWin=24, winSum=409
7714 04:46:18.429076 TX Vref=26, minBit 3, minWin=25, winSum=415
7715 04:46:18.432516 TX Vref=28, minBit 1, minWin=25, winSum=416
7716 04:46:18.435549 TX Vref=30, minBit 1, minWin=25, winSum=413
7717 04:46:18.439029 TX Vref=32, minBit 2, minWin=24, winSum=404
7718 04:46:18.442408 TX Vref=34, minBit 0, minWin=24, winSum=396
7719 04:46:18.445990 TX Vref=36, minBit 2, minWin=23, winSum=385
7720 04:46:18.452925 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 28
7721 04:46:18.453501
7722 04:46:18.455902 Final TX Range 0 Vref 28
7723 04:46:18.456369
7724 04:46:18.456734 ==
7725 04:46:18.458978 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 04:46:18.462734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 04:46:18.463294 ==
7728 04:46:18.463728
7729 04:46:18.465648
7730 04:46:18.466111 TX Vref Scan disable
7731 04:46:18.472236 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7732 04:46:18.472848 == TX Byte 0 ==
7733 04:46:18.475693 u2DelayCellOfst[0]=10 cells (3 PI)
7734 04:46:18.478719 u2DelayCellOfst[1]=14 cells (4 PI)
7735 04:46:18.482287 u2DelayCellOfst[2]=10 cells (3 PI)
7736 04:46:18.485408 u2DelayCellOfst[3]=10 cells (3 PI)
7737 04:46:18.488385 u2DelayCellOfst[4]=7 cells (2 PI)
7738 04:46:18.491628 u2DelayCellOfst[5]=0 cells (0 PI)
7739 04:46:18.494858 u2DelayCellOfst[6]=17 cells (5 PI)
7740 04:46:18.499315 u2DelayCellOfst[7]=14 cells (4 PI)
7741 04:46:18.502003 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7742 04:46:18.505742 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7743 04:46:18.508401 == TX Byte 1 ==
7744 04:46:18.511667 u2DelayCellOfst[8]=0 cells (0 PI)
7745 04:46:18.515131 u2DelayCellOfst[9]=0 cells (0 PI)
7746 04:46:18.518587 u2DelayCellOfst[10]=3 cells (1 PI)
7747 04:46:18.521782 u2DelayCellOfst[11]=0 cells (0 PI)
7748 04:46:18.524956 u2DelayCellOfst[12]=7 cells (2 PI)
7749 04:46:18.528381 u2DelayCellOfst[13]=7 cells (2 PI)
7750 04:46:18.528942 u2DelayCellOfst[14]=14 cells (4 PI)
7751 04:46:18.531952 u2DelayCellOfst[15]=7 cells (2 PI)
7752 04:46:18.537739 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7753 04:46:18.542000 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7754 04:46:18.542522 DramC Write-DBI on
7755 04:46:18.544685 ==
7756 04:46:18.547668 Dram Type= 6, Freq= 0, CH_0, rank 0
7757 04:46:18.551443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7758 04:46:18.551975 ==
7759 04:46:18.552315
7760 04:46:18.552639
7761 04:46:18.554555 TX Vref Scan disable
7762 04:46:18.554974 == TX Byte 0 ==
7763 04:46:18.561155 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7764 04:46:18.561682 == TX Byte 1 ==
7765 04:46:18.564679 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7766 04:46:18.567414 DramC Write-DBI off
7767 04:46:18.567843
7768 04:46:18.568175 [DATLAT]
7769 04:46:18.571225 Freq=1600, CH0 RK0
7770 04:46:18.571699
7771 04:46:18.572069 DATLAT Default: 0xf
7772 04:46:18.574038 0, 0xFFFF, sum = 0
7773 04:46:18.577271 1, 0xFFFF, sum = 0
7774 04:46:18.577698 2, 0xFFFF, sum = 0
7775 04:46:18.580485 3, 0xFFFF, sum = 0
7776 04:46:18.580913 4, 0xFFFF, sum = 0
7777 04:46:18.583957 5, 0xFFFF, sum = 0
7778 04:46:18.584385 6, 0xFFFF, sum = 0
7779 04:46:18.587050 7, 0xFFFF, sum = 0
7780 04:46:18.587526 8, 0xFFFF, sum = 0
7781 04:46:18.590748 9, 0xFFFF, sum = 0
7782 04:46:18.591318 10, 0xFFFF, sum = 0
7783 04:46:18.593871 11, 0xFFFF, sum = 0
7784 04:46:18.594405 12, 0xFFFF, sum = 0
7785 04:46:18.597317 13, 0xFFFF, sum = 0
7786 04:46:18.597888 14, 0x0, sum = 1
7787 04:46:18.600827 15, 0x0, sum = 2
7788 04:46:18.601360 16, 0x0, sum = 3
7789 04:46:18.603674 17, 0x0, sum = 4
7790 04:46:18.604207 best_step = 15
7791 04:46:18.604548
7792 04:46:18.604857 ==
7793 04:46:18.607439 Dram Type= 6, Freq= 0, CH_0, rank 0
7794 04:46:18.614004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7795 04:46:18.614541 ==
7796 04:46:18.614882 RX Vref Scan: 1
7797 04:46:18.615195
7798 04:46:18.616667 Set Vref Range= 24 -> 127
7799 04:46:18.617105
7800 04:46:18.620285 RX Vref 24 -> 127, step: 1
7801 04:46:18.620727
7802 04:46:18.624230 RX Delay 11 -> 252, step: 4
7803 04:46:18.624791
7804 04:46:18.627133 Set Vref, RX VrefLevel [Byte0]: 24
7805 04:46:18.629963 [Byte1]: 24
7806 04:46:18.630390
7807 04:46:18.633255 Set Vref, RX VrefLevel [Byte0]: 25
7808 04:46:18.636622 [Byte1]: 25
7809 04:46:18.637153
7810 04:46:18.639763 Set Vref, RX VrefLevel [Byte0]: 26
7811 04:46:18.643230 [Byte1]: 26
7812 04:46:18.646824
7813 04:46:18.647357 Set Vref, RX VrefLevel [Byte0]: 27
7814 04:46:18.650125 [Byte1]: 27
7815 04:46:18.653997
7816 04:46:18.654527 Set Vref, RX VrefLevel [Byte0]: 28
7817 04:46:18.657492 [Byte1]: 28
7818 04:46:18.661900
7819 04:46:18.662427 Set Vref, RX VrefLevel [Byte0]: 29
7820 04:46:18.665062 [Byte1]: 29
7821 04:46:18.669135
7822 04:46:18.669560 Set Vref, RX VrefLevel [Byte0]: 30
7823 04:46:18.672285 [Byte1]: 30
7824 04:46:18.676927
7825 04:46:18.677452 Set Vref, RX VrefLevel [Byte0]: 31
7826 04:46:18.680070 [Byte1]: 31
7827 04:46:18.684692
7828 04:46:18.685271 Set Vref, RX VrefLevel [Byte0]: 32
7829 04:46:18.688002 [Byte1]: 32
7830 04:46:18.692163
7831 04:46:18.692747 Set Vref, RX VrefLevel [Byte0]: 33
7832 04:46:18.695213 [Byte1]: 33
7833 04:46:18.700026
7834 04:46:18.700581 Set Vref, RX VrefLevel [Byte0]: 34
7835 04:46:18.703159 [Byte1]: 34
7836 04:46:18.708098
7837 04:46:18.708661 Set Vref, RX VrefLevel [Byte0]: 35
7838 04:46:18.711054 [Byte1]: 35
7839 04:46:18.714668
7840 04:46:18.715127 Set Vref, RX VrefLevel [Byte0]: 36
7841 04:46:18.717881 [Byte1]: 36
7842 04:46:18.722705
7843 04:46:18.723266 Set Vref, RX VrefLevel [Byte0]: 37
7844 04:46:18.725539 [Byte1]: 37
7845 04:46:18.730595
7846 04:46:18.731011 Set Vref, RX VrefLevel [Byte0]: 38
7847 04:46:18.733367 [Byte1]: 38
7848 04:46:18.737821
7849 04:46:18.738241 Set Vref, RX VrefLevel [Byte0]: 39
7850 04:46:18.741282 [Byte1]: 39
7851 04:46:18.745442
7852 04:46:18.745962 Set Vref, RX VrefLevel [Byte0]: 40
7853 04:46:18.749034 [Byte1]: 40
7854 04:46:18.753534
7855 04:46:18.754067 Set Vref, RX VrefLevel [Byte0]: 41
7856 04:46:18.756638 [Byte1]: 41
7857 04:46:18.761106
7858 04:46:18.761696 Set Vref, RX VrefLevel [Byte0]: 42
7859 04:46:18.763987 [Byte1]: 42
7860 04:46:18.768216
7861 04:46:18.768734 Set Vref, RX VrefLevel [Byte0]: 43
7862 04:46:18.771788 [Byte1]: 43
7863 04:46:18.775834
7864 04:46:18.776257 Set Vref, RX VrefLevel [Byte0]: 44
7865 04:46:18.779096 [Byte1]: 44
7866 04:46:18.783446
7867 04:46:18.783867 Set Vref, RX VrefLevel [Byte0]: 45
7868 04:46:18.787009 [Byte1]: 45
7869 04:46:18.791330
7870 04:46:18.791805 Set Vref, RX VrefLevel [Byte0]: 46
7871 04:46:18.794603 [Byte1]: 46
7872 04:46:18.798766
7873 04:46:18.799288 Set Vref, RX VrefLevel [Byte0]: 47
7874 04:46:18.802361 [Byte1]: 47
7875 04:46:18.806391
7876 04:46:18.806807 Set Vref, RX VrefLevel [Byte0]: 48
7877 04:46:18.809717 [Byte1]: 48
7878 04:46:18.813787
7879 04:46:18.814208 Set Vref, RX VrefLevel [Byte0]: 49
7880 04:46:18.817114 [Byte1]: 49
7881 04:46:18.821500
7882 04:46:18.821911 Set Vref, RX VrefLevel [Byte0]: 50
7883 04:46:18.824888 [Byte1]: 50
7884 04:46:18.829463
7885 04:46:18.829978 Set Vref, RX VrefLevel [Byte0]: 51
7886 04:46:18.832552 [Byte1]: 51
7887 04:46:18.836472
7888 04:46:18.836907 Set Vref, RX VrefLevel [Byte0]: 52
7889 04:46:18.839704 [Byte1]: 52
7890 04:46:18.844550
7891 04:46:18.845079 Set Vref, RX VrefLevel [Byte0]: 53
7892 04:46:18.847353 [Byte1]: 53
7893 04:46:18.852203
7894 04:46:18.852716 Set Vref, RX VrefLevel [Byte0]: 54
7895 04:46:18.855467 [Byte1]: 54
7896 04:46:18.859612
7897 04:46:18.860028 Set Vref, RX VrefLevel [Byte0]: 55
7898 04:46:18.862520 [Byte1]: 55
7899 04:46:18.867319
7900 04:46:18.867886 Set Vref, RX VrefLevel [Byte0]: 56
7901 04:46:18.870334 [Byte1]: 56
7902 04:46:18.874676
7903 04:46:18.875092 Set Vref, RX VrefLevel [Byte0]: 57
7904 04:46:18.877922 [Byte1]: 57
7905 04:46:18.881919
7906 04:46:18.882335 Set Vref, RX VrefLevel [Byte0]: 58
7907 04:46:18.885907 [Byte1]: 58
7908 04:46:18.889677
7909 04:46:18.890092 Set Vref, RX VrefLevel [Byte0]: 59
7910 04:46:18.893194 [Byte1]: 59
7911 04:46:18.897624
7912 04:46:18.898053 Set Vref, RX VrefLevel [Byte0]: 60
7913 04:46:18.900546 [Byte1]: 60
7914 04:46:18.905166
7915 04:46:18.905605 Set Vref, RX VrefLevel [Byte0]: 61
7916 04:46:18.908265 [Byte1]: 61
7917 04:46:18.913140
7918 04:46:18.913655 Set Vref, RX VrefLevel [Byte0]: 62
7919 04:46:18.916070 [Byte1]: 62
7920 04:46:18.920191
7921 04:46:18.920603 Set Vref, RX VrefLevel [Byte0]: 63
7922 04:46:18.923600 [Byte1]: 63
7923 04:46:18.927948
7924 04:46:18.928547 Set Vref, RX VrefLevel [Byte0]: 64
7925 04:46:18.931085 [Byte1]: 64
7926 04:46:18.935638
7927 04:46:18.936077 Set Vref, RX VrefLevel [Byte0]: 65
7928 04:46:18.938994 [Byte1]: 65
7929 04:46:18.942940
7930 04:46:18.943432 Set Vref, RX VrefLevel [Byte0]: 66
7931 04:46:18.946709 [Byte1]: 66
7932 04:46:18.950994
7933 04:46:18.951449 Set Vref, RX VrefLevel [Byte0]: 67
7934 04:46:18.954585 [Byte1]: 67
7935 04:46:18.958280
7936 04:46:18.958804 Set Vref, RX VrefLevel [Byte0]: 68
7937 04:46:18.962094 [Byte1]: 68
7938 04:46:18.966194
7939 04:46:18.966731 Set Vref, RX VrefLevel [Byte0]: 69
7940 04:46:18.969645 [Byte1]: 69
7941 04:46:18.973580
7942 04:46:18.974013 Set Vref, RX VrefLevel [Byte0]: 70
7943 04:46:18.976740 [Byte1]: 70
7944 04:46:18.980923
7945 04:46:18.981336 Set Vref, RX VrefLevel [Byte0]: 71
7946 04:46:18.984835 [Byte1]: 71
7947 04:46:18.989135
7948 04:46:18.989643 Set Vref, RX VrefLevel [Byte0]: 72
7949 04:46:18.992005 [Byte1]: 72
7950 04:46:18.996843
7951 04:46:18.997383 Set Vref, RX VrefLevel [Byte0]: 73
7952 04:46:19.000092 [Byte1]: 73
7953 04:46:19.004238
7954 04:46:19.004803 Set Vref, RX VrefLevel [Byte0]: 74
7955 04:46:19.007713 [Byte1]: 74
7956 04:46:19.011568
7957 04:46:19.012082 Set Vref, RX VrefLevel [Byte0]: 75
7958 04:46:19.015089 [Byte1]: 75
7959 04:46:19.019421
7960 04:46:19.019841 Final RX Vref Byte 0 = 57 to rank0
7961 04:46:19.022982 Final RX Vref Byte 1 = 62 to rank0
7962 04:46:19.026122 Final RX Vref Byte 0 = 57 to rank1
7963 04:46:19.029152 Final RX Vref Byte 1 = 62 to rank1==
7964 04:46:19.032423 Dram Type= 6, Freq= 0, CH_0, rank 0
7965 04:46:19.039054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7966 04:46:19.039654 ==
7967 04:46:19.040003 DQS Delay:
7968 04:46:19.042114 DQS0 = 0, DQS1 = 0
7969 04:46:19.042538 DQM Delay:
7970 04:46:19.045574 DQM0 = 128, DQM1 = 123
7971 04:46:19.045989 DQ Delay:
7972 04:46:19.048788 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7973 04:46:19.051940 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7974 04:46:19.055266 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =120
7975 04:46:19.058892 DQ12 =130, DQ13 =130, DQ14 =132, DQ15 =130
7976 04:46:19.059453
7977 04:46:19.059796
7978 04:46:19.060100
7979 04:46:19.062168 [DramC_TX_OE_Calibration] TA2
7980 04:46:19.066267 Original DQ_B0 (3 6) =30, OEN = 27
7981 04:46:19.068990 Original DQ_B1 (3 6) =30, OEN = 27
7982 04:46:19.071679 24, 0x0, End_B0=24 End_B1=24
7983 04:46:19.074969 25, 0x0, End_B0=25 End_B1=25
7984 04:46:19.075425 26, 0x0, End_B0=26 End_B1=26
7985 04:46:19.078510 27, 0x0, End_B0=27 End_B1=27
7986 04:46:19.081877 28, 0x0, End_B0=28 End_B1=28
7987 04:46:19.085130 29, 0x0, End_B0=29 End_B1=29
7988 04:46:19.085661 30, 0x0, End_B0=30 End_B1=30
7989 04:46:19.088791 31, 0x4141, End_B0=30 End_B1=30
7990 04:46:19.092041 Byte0 end_step=30 best_step=27
7991 04:46:19.095172 Byte1 end_step=30 best_step=27
7992 04:46:19.098189 Byte0 TX OE(2T, 0.5T) = (3, 3)
7993 04:46:19.101548 Byte1 TX OE(2T, 0.5T) = (3, 3)
7994 04:46:19.101964
7995 04:46:19.102289
7996 04:46:19.108611 [DQSOSCAuto] RK0, (LSB)MR18= 0x1713, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
7997 04:46:19.111901 CH0 RK0: MR19=303, MR18=1713
7998 04:46:19.117910 CH0_RK0: MR19=0x303, MR18=0x1713, DQSOSC=398, MR23=63, INC=23, DEC=15
7999 04:46:19.118328
8000 04:46:19.121347 ----->DramcWriteLeveling(PI) begin...
8001 04:46:19.121773 ==
8002 04:46:19.124617 Dram Type= 6, Freq= 0, CH_0, rank 1
8003 04:46:19.128084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 04:46:19.128602 ==
8005 04:46:19.131533 Write leveling (Byte 0): 35 => 35
8006 04:46:19.135044 Write leveling (Byte 1): 25 => 25
8007 04:46:19.137826 DramcWriteLeveling(PI) end<-----
8008 04:46:19.138359
8009 04:46:19.138693 ==
8010 04:46:19.141410 Dram Type= 6, Freq= 0, CH_0, rank 1
8011 04:46:19.147691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8012 04:46:19.148195 ==
8013 04:46:19.148529 [Gating] SW mode calibration
8014 04:46:19.158082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8015 04:46:19.160978 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8016 04:46:19.164518 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 04:46:19.171194 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 04:46:19.174260 1 4 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
8019 04:46:19.177590 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8020 04:46:19.184172 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8021 04:46:19.187435 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8022 04:46:19.191108 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8023 04:46:19.197111 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8024 04:46:19.200498 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 04:46:19.206979 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 04:46:19.210460 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8027 04:46:19.214000 1 5 12 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
8028 04:46:19.220575 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8029 04:46:19.223535 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8030 04:46:19.227073 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 04:46:19.233362 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 04:46:19.237045 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 04:46:19.240227 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8034 04:46:19.246952 1 6 8 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
8035 04:46:19.250063 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8036 04:46:19.253164 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8037 04:46:19.259629 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 04:46:19.263288 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 04:46:19.266626 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 04:46:19.273116 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 04:46:19.276006 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 04:46:19.280071 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8043 04:46:19.286424 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8044 04:46:19.289181 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8045 04:46:19.292353 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8046 04:46:19.299455 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 04:46:19.303008 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 04:46:19.305533 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 04:46:19.312730 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 04:46:19.316161 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 04:46:19.318960 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 04:46:19.325534 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 04:46:19.329079 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 04:46:19.331942 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 04:46:19.338761 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 04:46:19.342183 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 04:46:19.345794 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 04:46:19.352270 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8059 04:46:19.355192 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8060 04:46:19.358685 Total UI for P1: 0, mck2ui 16
8061 04:46:19.361945 best dqsien dly found for B0: ( 1, 9, 8)
8062 04:46:19.365581 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8063 04:46:19.368573 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8064 04:46:19.374787 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 04:46:19.378599 Total UI for P1: 0, mck2ui 16
8066 04:46:19.381728 best dqsien dly found for B1: ( 1, 9, 18)
8067 04:46:19.385021 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8068 04:46:19.388116 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8069 04:46:19.388558
8070 04:46:19.391142 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8071 04:46:19.395100 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8072 04:46:19.398040 [Gating] SW calibration Done
8073 04:46:19.398556 ==
8074 04:46:19.401871 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 04:46:19.404367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 04:46:19.407777 ==
8077 04:46:19.408191 RX Vref Scan: 0
8078 04:46:19.408556
8079 04:46:19.411213 RX Vref 0 -> 0, step: 1
8080 04:46:19.411783
8081 04:46:19.412120 RX Delay 0 -> 252, step: 8
8082 04:46:19.417996 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8083 04:46:19.420965 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8084 04:46:19.424544 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8085 04:46:19.427953 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8086 04:46:19.431003 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8087 04:46:19.438113 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8088 04:46:19.440786 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8089 04:46:19.444294 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8090 04:46:19.447473 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8091 04:46:19.454597 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8092 04:46:19.457645 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8093 04:46:19.460774 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8094 04:46:19.464156 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8095 04:46:19.467526 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8096 04:46:19.474041 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8097 04:46:19.477224 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8098 04:46:19.477658 ==
8099 04:46:19.480592 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 04:46:19.483675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 04:46:19.484113 ==
8102 04:46:19.487104 DQS Delay:
8103 04:46:19.487694 DQS0 = 0, DQS1 = 0
8104 04:46:19.488150 DQM Delay:
8105 04:46:19.490890 DQM0 = 132, DQM1 = 128
8106 04:46:19.491474 DQ Delay:
8107 04:46:19.493490 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8108 04:46:19.497014 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8109 04:46:19.503520 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8110 04:46:19.507206 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8111 04:46:19.507809
8112 04:46:19.508258
8113 04:46:19.508670 ==
8114 04:46:19.509969 Dram Type= 6, Freq= 0, CH_0, rank 1
8115 04:46:19.513945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8116 04:46:19.514487 ==
8117 04:46:19.514939
8118 04:46:19.515352
8119 04:46:19.516682 TX Vref Scan disable
8120 04:46:19.519837 == TX Byte 0 ==
8121 04:46:19.523511 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8122 04:46:19.526823 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8123 04:46:19.530113 == TX Byte 1 ==
8124 04:46:19.532935 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8125 04:46:19.536573 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8126 04:46:19.537052 ==
8127 04:46:19.540197 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 04:46:19.543539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 04:46:19.546143 ==
8130 04:46:19.559051
8131 04:46:19.562087 TX Vref early break, caculate TX vref
8132 04:46:19.565530 TX Vref=16, minBit 9, minWin=22, winSum=380
8133 04:46:19.568662 TX Vref=18, minBit 9, minWin=23, winSum=387
8134 04:46:19.572435 TX Vref=20, minBit 1, minWin=24, winSum=395
8135 04:46:19.575238 TX Vref=22, minBit 10, minWin=24, winSum=401
8136 04:46:19.581634 TX Vref=24, minBit 1, minWin=25, winSum=409
8137 04:46:19.585020 TX Vref=26, minBit 4, minWin=25, winSum=413
8138 04:46:19.588091 TX Vref=28, minBit 0, minWin=26, winSum=419
8139 04:46:19.591755 TX Vref=30, minBit 1, minWin=25, winSum=414
8140 04:46:19.595180 TX Vref=32, minBit 7, minWin=24, winSum=402
8141 04:46:19.598459 TX Vref=34, minBit 0, minWin=24, winSum=393
8142 04:46:19.604614 [TxChooseVref] Worse bit 0, Min win 26, Win sum 419, Final Vref 28
8143 04:46:19.605151
8144 04:46:19.607809 Final TX Range 0 Vref 28
8145 04:46:19.608245
8146 04:46:19.608683 ==
8147 04:46:19.611298 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 04:46:19.614742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 04:46:19.615286 ==
8150 04:46:19.615782
8151 04:46:19.616200
8152 04:46:19.617802 TX Vref Scan disable
8153 04:46:19.624365 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8154 04:46:19.624797 == TX Byte 0 ==
8155 04:46:19.627643 u2DelayCellOfst[0]=10 cells (3 PI)
8156 04:46:19.631158 u2DelayCellOfst[1]=14 cells (4 PI)
8157 04:46:19.634803 u2DelayCellOfst[2]=7 cells (2 PI)
8158 04:46:19.638212 u2DelayCellOfst[3]=10 cells (3 PI)
8159 04:46:19.641149 u2DelayCellOfst[4]=7 cells (2 PI)
8160 04:46:19.644274 u2DelayCellOfst[5]=0 cells (0 PI)
8161 04:46:19.647886 u2DelayCellOfst[6]=14 cells (4 PI)
8162 04:46:19.650843 u2DelayCellOfst[7]=14 cells (4 PI)
8163 04:46:19.654413 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8164 04:46:19.658394 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8165 04:46:19.661344 == TX Byte 1 ==
8166 04:46:19.663965 u2DelayCellOfst[8]=0 cells (0 PI)
8167 04:46:19.667476 u2DelayCellOfst[9]=0 cells (0 PI)
8168 04:46:19.670566 u2DelayCellOfst[10]=3 cells (1 PI)
8169 04:46:19.671028 u2DelayCellOfst[11]=0 cells (0 PI)
8170 04:46:19.674368 u2DelayCellOfst[12]=7 cells (2 PI)
8171 04:46:19.677571 u2DelayCellOfst[13]=10 cells (3 PI)
8172 04:46:19.680858 u2DelayCellOfst[14]=14 cells (4 PI)
8173 04:46:19.683835 u2DelayCellOfst[15]=10 cells (3 PI)
8174 04:46:19.690609 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8175 04:46:19.693909 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8176 04:46:19.694456 DramC Write-DBI on
8177 04:46:19.697573 ==
8178 04:46:19.698118 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 04:46:19.703926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 04:46:19.704466 ==
8181 04:46:19.704917
8182 04:46:19.705331
8183 04:46:19.707156 TX Vref Scan disable
8184 04:46:19.707755 == TX Byte 0 ==
8185 04:46:19.713484 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8186 04:46:19.714022 == TX Byte 1 ==
8187 04:46:19.717221 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8188 04:46:19.719916 DramC Write-DBI off
8189 04:46:19.720352
8190 04:46:19.720788 [DATLAT]
8191 04:46:19.723127 Freq=1600, CH0 RK1
8192 04:46:19.723597
8193 04:46:19.724034 DATLAT Default: 0xf
8194 04:46:19.727064 0, 0xFFFF, sum = 0
8195 04:46:19.727663 1, 0xFFFF, sum = 0
8196 04:46:19.730237 2, 0xFFFF, sum = 0
8197 04:46:19.730778 3, 0xFFFF, sum = 0
8198 04:46:19.733862 4, 0xFFFF, sum = 0
8199 04:46:19.736803 5, 0xFFFF, sum = 0
8200 04:46:19.737345 6, 0xFFFF, sum = 0
8201 04:46:19.739934 7, 0xFFFF, sum = 0
8202 04:46:19.740475 8, 0xFFFF, sum = 0
8203 04:46:19.743250 9, 0xFFFF, sum = 0
8204 04:46:19.743999 10, 0xFFFF, sum = 0
8205 04:46:19.746291 11, 0xFFFF, sum = 0
8206 04:46:19.746729 12, 0xFFFF, sum = 0
8207 04:46:19.749733 13, 0xFFFF, sum = 0
8208 04:46:19.750177 14, 0x0, sum = 1
8209 04:46:19.753377 15, 0x0, sum = 2
8210 04:46:19.753907 16, 0x0, sum = 3
8211 04:46:19.756187 17, 0x0, sum = 4
8212 04:46:19.756611 best_step = 15
8213 04:46:19.756968
8214 04:46:19.757280 ==
8215 04:46:19.760179 Dram Type= 6, Freq= 0, CH_0, rank 1
8216 04:46:19.763320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8217 04:46:19.766678 ==
8218 04:46:19.767442 RX Vref Scan: 0
8219 04:46:19.767802
8220 04:46:19.769416 RX Vref 0 -> 0, step: 1
8221 04:46:19.769834
8222 04:46:19.772901 RX Delay 19 -> 252, step: 4
8223 04:46:19.775776 iDelay=187, Bit 0, Center 126 (75 ~ 178) 104
8224 04:46:19.779697 iDelay=187, Bit 1, Center 130 (79 ~ 182) 104
8225 04:46:19.782506 iDelay=187, Bit 2, Center 124 (75 ~ 174) 100
8226 04:46:19.789113 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8227 04:46:19.792413 iDelay=187, Bit 4, Center 130 (83 ~ 178) 96
8228 04:46:19.795705 iDelay=187, Bit 5, Center 120 (67 ~ 174) 108
8229 04:46:19.798777 iDelay=187, Bit 6, Center 136 (87 ~ 186) 100
8230 04:46:19.802853 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8231 04:46:19.808732 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8232 04:46:19.812032 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8233 04:46:19.815590 iDelay=187, Bit 10, Center 126 (71 ~ 182) 112
8234 04:46:19.818881 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8235 04:46:19.821873 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8236 04:46:19.828728 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8237 04:46:19.832397 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8238 04:46:19.835693 iDelay=187, Bit 15, Center 128 (75 ~ 182) 108
8239 04:46:19.836253 ==
8240 04:46:19.838802 Dram Type= 6, Freq= 0, CH_0, rank 1
8241 04:46:19.842099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8242 04:46:19.845176 ==
8243 04:46:19.845637 DQS Delay:
8244 04:46:19.846000 DQS0 = 0, DQS1 = 0
8245 04:46:19.848213 DQM Delay:
8246 04:46:19.848668 DQM0 = 128, DQM1 = 123
8247 04:46:19.852017 DQ Delay:
8248 04:46:19.855413 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8249 04:46:19.858608 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =134
8250 04:46:19.861893 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8251 04:46:19.865013 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =128
8252 04:46:19.865457
8253 04:46:19.865780
8254 04:46:19.866100
8255 04:46:19.868440 [DramC_TX_OE_Calibration] TA2
8256 04:46:19.871572 Original DQ_B0 (3 6) =30, OEN = 27
8257 04:46:19.875246 Original DQ_B1 (3 6) =30, OEN = 27
8258 04:46:19.877919 24, 0x0, End_B0=24 End_B1=24
8259 04:46:19.878346 25, 0x0, End_B0=25 End_B1=25
8260 04:46:19.881118 26, 0x0, End_B0=26 End_B1=26
8261 04:46:19.884269 27, 0x0, End_B0=27 End_B1=27
8262 04:46:19.887825 28, 0x0, End_B0=28 End_B1=28
8263 04:46:19.891744 29, 0x0, End_B0=29 End_B1=29
8264 04:46:19.892263 30, 0x0, End_B0=30 End_B1=30
8265 04:46:19.894704 31, 0x4141, End_B0=30 End_B1=30
8266 04:46:19.898360 Byte0 end_step=30 best_step=27
8267 04:46:19.901184 Byte1 end_step=30 best_step=27
8268 04:46:19.904387 Byte0 TX OE(2T, 0.5T) = (3, 3)
8269 04:46:19.907858 Byte1 TX OE(2T, 0.5T) = (3, 3)
8270 04:46:19.908479
8271 04:46:19.909003
8272 04:46:19.914627 [DQSOSCAuto] RK1, (LSB)MR18= 0x1714, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8273 04:46:19.918157 CH0 RK1: MR19=303, MR18=1714
8274 04:46:19.923664 CH0_RK1: MR19=0x303, MR18=0x1714, DQSOSC=398, MR23=63, INC=23, DEC=15
8275 04:46:19.927245 [RxdqsGatingPostProcess] freq 1600
8276 04:46:19.933827 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8277 04:46:19.934327 best DQS0 dly(2T, 0.5T) = (1, 1)
8278 04:46:19.937135 best DQS1 dly(2T, 0.5T) = (1, 1)
8279 04:46:19.941093 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8280 04:46:19.943846 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8281 04:46:19.947192 best DQS0 dly(2T, 0.5T) = (1, 1)
8282 04:46:19.950637 best DQS1 dly(2T, 0.5T) = (1, 1)
8283 04:46:19.953499 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8284 04:46:19.957446 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8285 04:46:19.960409 Pre-setting of DQS Precalculation
8286 04:46:19.963777 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8287 04:46:19.964553 ==
8288 04:46:19.966968 Dram Type= 6, Freq= 0, CH_1, rank 0
8289 04:46:19.973492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8290 04:46:19.974109 ==
8291 04:46:19.976472 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8292 04:46:19.983129 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8293 04:46:19.986299 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8294 04:46:19.992797 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8295 04:46:20.000942 [CA 0] Center 42 (13~72) winsize 60
8296 04:46:20.003979 [CA 1] Center 42 (12~72) winsize 61
8297 04:46:20.007683 [CA 2] Center 38 (9~68) winsize 60
8298 04:46:20.010610 [CA 3] Center 37 (8~67) winsize 60
8299 04:46:20.014262 [CA 4] Center 38 (8~69) winsize 62
8300 04:46:20.017560 [CA 5] Center 37 (7~67) winsize 61
8301 04:46:20.017669
8302 04:46:20.021093 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8303 04:46:20.021316
8304 04:46:20.024060 [CATrainingPosCal] consider 1 rank data
8305 04:46:20.027596 u2DelayCellTimex100 = 275/100 ps
8306 04:46:20.031080 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8307 04:46:20.037536 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8308 04:46:20.041200 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8309 04:46:20.044216 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8310 04:46:20.047506 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8311 04:46:20.050898 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8312 04:46:20.051312
8313 04:46:20.054374 CA PerBit enable=1, Macro0, CA PI delay=37
8314 04:46:20.054787
8315 04:46:20.057786 [CBTSetCACLKResult] CA Dly = 37
8316 04:46:20.060685 CS Dly: 8 (0~39)
8317 04:46:20.063737 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8318 04:46:20.067423 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8319 04:46:20.067845 ==
8320 04:46:20.070291 Dram Type= 6, Freq= 0, CH_1, rank 1
8321 04:46:20.077144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8322 04:46:20.077563 ==
8323 04:46:20.080449 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8324 04:46:20.087474 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8325 04:46:20.090197 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8326 04:46:20.096504 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8327 04:46:20.104350 [CA 0] Center 42 (12~72) winsize 61
8328 04:46:20.107600 [CA 1] Center 43 (14~72) winsize 59
8329 04:46:20.110687 [CA 2] Center 38 (9~68) winsize 60
8330 04:46:20.113898 [CA 3] Center 37 (8~66) winsize 59
8331 04:46:20.117457 [CA 4] Center 37 (7~68) winsize 62
8332 04:46:20.120810 [CA 5] Center 37 (7~67) winsize 61
8333 04:46:20.121280
8334 04:46:20.124157 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8335 04:46:20.124577
8336 04:46:20.130706 [CATrainingPosCal] consider 2 rank data
8337 04:46:20.131126 u2DelayCellTimex100 = 275/100 ps
8338 04:46:20.137309 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8339 04:46:20.140428 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8340 04:46:20.144464 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8341 04:46:20.146898 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8342 04:46:20.150628 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8343 04:46:20.153533 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8344 04:46:20.154070
8345 04:46:20.156749 CA PerBit enable=1, Macro0, CA PI delay=37
8346 04:46:20.157168
8347 04:46:20.160060 [CBTSetCACLKResult] CA Dly = 37
8348 04:46:20.163833 CS Dly: 9 (0~42)
8349 04:46:20.167506 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8350 04:46:20.169990 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8351 04:46:20.170406
8352 04:46:20.173556 ----->DramcWriteLeveling(PI) begin...
8353 04:46:20.174150 ==
8354 04:46:20.176554 Dram Type= 6, Freq= 0, CH_1, rank 0
8355 04:46:20.183578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8356 04:46:20.184090 ==
8357 04:46:20.186487 Write leveling (Byte 0): 24 => 24
8358 04:46:20.189952 Write leveling (Byte 1): 28 => 28
8359 04:46:20.192875 DramcWriteLeveling(PI) end<-----
8360 04:46:20.193288
8361 04:46:20.193609 ==
8362 04:46:20.196393 Dram Type= 6, Freq= 0, CH_1, rank 0
8363 04:46:20.199443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8364 04:46:20.199861 ==
8365 04:46:20.202787 [Gating] SW mode calibration
8366 04:46:20.209330 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8367 04:46:20.216696 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8368 04:46:20.219855 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 04:46:20.222683 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 04:46:20.229657 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 04:46:20.232652 1 4 12 | B1->B0 | 2727 3333 | 0 1 | (1 1) (1 1)
8372 04:46:20.235670 1 4 16 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8373 04:46:20.242313 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 04:46:20.245757 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 04:46:20.249304 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 04:46:20.255656 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 04:46:20.258809 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 04:46:20.262133 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8379 04:46:20.268979 1 5 12 | B1->B0 | 3232 2424 | 1 0 | (1 0) (0 0)
8380 04:46:20.272379 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8381 04:46:20.275454 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 04:46:20.282601 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 04:46:20.285838 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 04:46:20.288696 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 04:46:20.294953 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 04:46:20.298165 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
8387 04:46:20.301724 1 6 12 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
8388 04:46:20.308472 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 04:46:20.311613 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 04:46:20.315510 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 04:46:20.321481 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 04:46:20.325749 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 04:46:20.328792 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 04:46:20.334730 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8395 04:46:20.338545 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8396 04:46:20.341543 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8397 04:46:20.347687 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 04:46:20.351235 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 04:46:20.354545 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 04:46:20.361504 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 04:46:20.364530 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 04:46:20.367737 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 04:46:20.371047 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 04:46:20.377470 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 04:46:20.380770 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 04:46:20.387803 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 04:46:20.391357 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 04:46:20.394254 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 04:46:20.401697 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 04:46:20.404318 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8411 04:46:20.407852 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8412 04:46:20.411196 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8413 04:46:20.414155 Total UI for P1: 0, mck2ui 16
8414 04:46:20.417755 best dqsien dly found for B0: ( 1, 9, 10)
8415 04:46:20.424807 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 04:46:20.427498 Total UI for P1: 0, mck2ui 16
8417 04:46:20.430693 best dqsien dly found for B1: ( 1, 9, 14)
8418 04:46:20.433541 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8419 04:46:20.437090 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8420 04:46:20.437645
8421 04:46:20.440321 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8422 04:46:20.443758 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8423 04:46:20.447034 [Gating] SW calibration Done
8424 04:46:20.447526 ==
8425 04:46:20.449947 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 04:46:20.453803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 04:46:20.456732 ==
8428 04:46:20.457190 RX Vref Scan: 0
8429 04:46:20.457556
8430 04:46:20.460592 RX Vref 0 -> 0, step: 1
8431 04:46:20.461152
8432 04:46:20.461520 RX Delay 0 -> 252, step: 8
8433 04:46:20.467309 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8434 04:46:20.470445 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8435 04:46:20.473347 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8436 04:46:20.476387 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8437 04:46:20.482999 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8438 04:46:20.486351 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8439 04:46:20.489871 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8440 04:46:20.493972 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8441 04:46:20.496847 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8442 04:46:20.503548 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8443 04:46:20.506638 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8444 04:46:20.509477 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8445 04:46:20.512844 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8446 04:46:20.516383 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8447 04:46:20.522638 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8448 04:46:20.525813 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8449 04:46:20.526273 ==
8450 04:46:20.529134 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 04:46:20.532831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 04:46:20.533387 ==
8453 04:46:20.535418 DQS Delay:
8454 04:46:20.535879 DQS0 = 0, DQS1 = 0
8455 04:46:20.539075 DQM Delay:
8456 04:46:20.539692 DQM0 = 135, DQM1 = 131
8457 04:46:20.540065 DQ Delay:
8458 04:46:20.542904 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8459 04:46:20.548823 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8460 04:46:20.552482 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8461 04:46:20.555600 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8462 04:46:20.556064
8463 04:46:20.556426
8464 04:46:20.556759 ==
8465 04:46:20.558443 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 04:46:20.561952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 04:46:20.562513 ==
8468 04:46:20.562876
8469 04:46:20.563408
8470 04:46:20.565563 TX Vref Scan disable
8471 04:46:20.568874 == TX Byte 0 ==
8472 04:46:20.572222 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8473 04:46:20.576031 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8474 04:46:20.578654 == TX Byte 1 ==
8475 04:46:20.581684 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8476 04:46:20.584986 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8477 04:46:20.585400 ==
8478 04:46:20.588692 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 04:46:20.595256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 04:46:20.595834 ==
8481 04:46:20.607056
8482 04:46:20.609991 TX Vref early break, caculate TX vref
8483 04:46:20.613551 TX Vref=16, minBit 8, minWin=21, winSum=368
8484 04:46:20.616473 TX Vref=18, minBit 8, minWin=22, winSum=378
8485 04:46:20.620007 TX Vref=20, minBit 5, minWin=23, winSum=389
8486 04:46:20.623145 TX Vref=22, minBit 8, minWin=23, winSum=397
8487 04:46:20.629890 TX Vref=24, minBit 9, minWin=24, winSum=404
8488 04:46:20.633190 TX Vref=26, minBit 6, minWin=25, winSum=417
8489 04:46:20.636344 TX Vref=28, minBit 0, minWin=25, winSum=418
8490 04:46:20.639448 TX Vref=30, minBit 9, minWin=24, winSum=413
8491 04:46:20.643081 TX Vref=32, minBit 11, minWin=23, winSum=403
8492 04:46:20.646353 TX Vref=34, minBit 0, minWin=23, winSum=392
8493 04:46:20.652978 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8494 04:46:20.653495
8495 04:46:20.655987 Final TX Range 0 Vref 28
8496 04:46:20.656403
8497 04:46:20.656731 ==
8498 04:46:20.658899 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 04:46:20.662616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 04:46:20.663134 ==
8501 04:46:20.663519
8502 04:46:20.665901
8503 04:46:20.666413 TX Vref Scan disable
8504 04:46:20.672246 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8505 04:46:20.672749 == TX Byte 0 ==
8506 04:46:20.675682 u2DelayCellOfst[0]=17 cells (5 PI)
8507 04:46:20.678562 u2DelayCellOfst[1]=10 cells (3 PI)
8508 04:46:20.682639 u2DelayCellOfst[2]=0 cells (0 PI)
8509 04:46:20.685307 u2DelayCellOfst[3]=7 cells (2 PI)
8510 04:46:20.688870 u2DelayCellOfst[4]=10 cells (3 PI)
8511 04:46:20.691798 u2DelayCellOfst[5]=17 cells (5 PI)
8512 04:46:20.695560 u2DelayCellOfst[6]=14 cells (4 PI)
8513 04:46:20.698649 u2DelayCellOfst[7]=7 cells (2 PI)
8514 04:46:20.701633 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8515 04:46:20.705578 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8516 04:46:20.708224 == TX Byte 1 ==
8517 04:46:20.711730 u2DelayCellOfst[8]=0 cells (0 PI)
8518 04:46:20.715076 u2DelayCellOfst[9]=7 cells (2 PI)
8519 04:46:20.718706 u2DelayCellOfst[10]=10 cells (3 PI)
8520 04:46:20.721943 u2DelayCellOfst[11]=7 cells (2 PI)
8521 04:46:20.724531 u2DelayCellOfst[12]=14 cells (4 PI)
8522 04:46:20.728112 u2DelayCellOfst[13]=17 cells (5 PI)
8523 04:46:20.731812 u2DelayCellOfst[14]=17 cells (5 PI)
8524 04:46:20.734881 u2DelayCellOfst[15]=21 cells (6 PI)
8525 04:46:20.737857 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8526 04:46:20.741388 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8527 04:46:20.744849 DramC Write-DBI on
8528 04:46:20.745404 ==
8529 04:46:20.748138 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 04:46:20.751282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 04:46:20.751794 ==
8532 04:46:20.752169
8533 04:46:20.752511
8534 04:46:20.754601 TX Vref Scan disable
8535 04:46:20.755155 == TX Byte 0 ==
8536 04:46:20.761202 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8537 04:46:20.761753 == TX Byte 1 ==
8538 04:46:20.767570 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8539 04:46:20.768113 DramC Write-DBI off
8540 04:46:20.768479
8541 04:46:20.768822 [DATLAT]
8542 04:46:20.770985 Freq=1600, CH1 RK0
8543 04:46:20.771483
8544 04:46:20.774558 DATLAT Default: 0xf
8545 04:46:20.775076 0, 0xFFFF, sum = 0
8546 04:46:20.777988 1, 0xFFFF, sum = 0
8547 04:46:20.778509 2, 0xFFFF, sum = 0
8548 04:46:20.780451 3, 0xFFFF, sum = 0
8549 04:46:20.780884 4, 0xFFFF, sum = 0
8550 04:46:20.784066 5, 0xFFFF, sum = 0
8551 04:46:20.784496 6, 0xFFFF, sum = 0
8552 04:46:20.787512 7, 0xFFFF, sum = 0
8553 04:46:20.787939 8, 0xFFFF, sum = 0
8554 04:46:20.790905 9, 0xFFFF, sum = 0
8555 04:46:20.791467 10, 0xFFFF, sum = 0
8556 04:46:20.794018 11, 0xFFFF, sum = 0
8557 04:46:20.794452 12, 0xFFFF, sum = 0
8558 04:46:20.796978 13, 0xFFFF, sum = 0
8559 04:46:20.797410 14, 0x0, sum = 1
8560 04:46:20.800667 15, 0x0, sum = 2
8561 04:46:20.801368 16, 0x0, sum = 3
8562 04:46:20.804048 17, 0x0, sum = 4
8563 04:46:20.804567 best_step = 15
8564 04:46:20.804900
8565 04:46:20.805211 ==
8566 04:46:20.807595 Dram Type= 6, Freq= 0, CH_1, rank 0
8567 04:46:20.813630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8568 04:46:20.814148 ==
8569 04:46:20.814489 RX Vref Scan: 1
8570 04:46:20.814802
8571 04:46:20.817219 Set Vref Range= 24 -> 127
8572 04:46:20.817750
8573 04:46:20.820175 RX Vref 24 -> 127, step: 1
8574 04:46:20.820684
8575 04:46:20.823437 RX Delay 19 -> 252, step: 4
8576 04:46:20.823859
8577 04:46:20.826968 Set Vref, RX VrefLevel [Byte0]: 24
8578 04:46:20.830374 [Byte1]: 24
8579 04:46:20.830888
8580 04:46:20.833071 Set Vref, RX VrefLevel [Byte0]: 25
8581 04:46:20.836674 [Byte1]: 25
8582 04:46:20.837190
8583 04:46:20.840053 Set Vref, RX VrefLevel [Byte0]: 26
8584 04:46:20.843165 [Byte1]: 26
8585 04:46:20.846309
8586 04:46:20.846742 Set Vref, RX VrefLevel [Byte0]: 27
8587 04:46:20.849432 [Byte1]: 27
8588 04:46:20.853922
8589 04:46:20.854436 Set Vref, RX VrefLevel [Byte0]: 28
8590 04:46:20.857126 [Byte1]: 28
8591 04:46:20.861348
8592 04:46:20.861863 Set Vref, RX VrefLevel [Byte0]: 29
8593 04:46:20.864880 [Byte1]: 29
8594 04:46:20.869144
8595 04:46:20.869658 Set Vref, RX VrefLevel [Byte0]: 30
8596 04:46:20.871945 [Byte1]: 30
8597 04:46:20.876394
8598 04:46:20.876814 Set Vref, RX VrefLevel [Byte0]: 31
8599 04:46:20.879913 [Byte1]: 31
8600 04:46:20.884214
8601 04:46:20.884634 Set Vref, RX VrefLevel [Byte0]: 32
8602 04:46:20.887533 [Byte1]: 32
8603 04:46:20.891846
8604 04:46:20.892362 Set Vref, RX VrefLevel [Byte0]: 33
8605 04:46:20.895175 [Byte1]: 33
8606 04:46:20.899436
8607 04:46:20.899951 Set Vref, RX VrefLevel [Byte0]: 34
8608 04:46:20.902586 [Byte1]: 34
8609 04:46:20.907109
8610 04:46:20.907649 Set Vref, RX VrefLevel [Byte0]: 35
8611 04:46:20.910248 [Byte1]: 35
8612 04:46:20.914413
8613 04:46:20.914927 Set Vref, RX VrefLevel [Byte0]: 36
8614 04:46:20.917908 [Byte1]: 36
8615 04:46:20.922321
8616 04:46:20.922989 Set Vref, RX VrefLevel [Byte0]: 37
8617 04:46:20.925325 [Byte1]: 37
8618 04:46:20.929641
8619 04:46:20.930063 Set Vref, RX VrefLevel [Byte0]: 38
8620 04:46:20.933381 [Byte1]: 38
8621 04:46:20.937392
8622 04:46:20.937902 Set Vref, RX VrefLevel [Byte0]: 39
8623 04:46:20.940267 [Byte1]: 39
8624 04:46:20.945028
8625 04:46:20.945545 Set Vref, RX VrefLevel [Byte0]: 40
8626 04:46:20.947965 [Byte1]: 40
8627 04:46:20.952338
8628 04:46:20.952758 Set Vref, RX VrefLevel [Byte0]: 41
8629 04:46:20.955726 [Byte1]: 41
8630 04:46:20.959816
8631 04:46:20.960333 Set Vref, RX VrefLevel [Byte0]: 42
8632 04:46:20.963837 [Byte1]: 42
8633 04:46:20.968230
8634 04:46:20.968748 Set Vref, RX VrefLevel [Byte0]: 43
8635 04:46:20.970493 [Byte1]: 43
8636 04:46:20.975237
8637 04:46:20.975664 Set Vref, RX VrefLevel [Byte0]: 44
8638 04:46:20.978639 [Byte1]: 44
8639 04:46:20.982861
8640 04:46:20.983295 Set Vref, RX VrefLevel [Byte0]: 45
8641 04:46:20.985812 [Byte1]: 45
8642 04:46:20.990759
8643 04:46:20.991274 Set Vref, RX VrefLevel [Byte0]: 46
8644 04:46:20.993300 [Byte1]: 46
8645 04:46:20.998056
8646 04:46:20.998568 Set Vref, RX VrefLevel [Byte0]: 47
8647 04:46:21.001042 [Byte1]: 47
8648 04:46:21.005454
8649 04:46:21.006081 Set Vref, RX VrefLevel [Byte0]: 48
8650 04:46:21.008625 [Byte1]: 48
8651 04:46:21.012889
8652 04:46:21.013398 Set Vref, RX VrefLevel [Byte0]: 49
8653 04:46:21.015979 [Byte1]: 49
8654 04:46:21.020647
8655 04:46:21.021157 Set Vref, RX VrefLevel [Byte0]: 50
8656 04:46:21.023940 [Byte1]: 50
8657 04:46:21.027846
8658 04:46:21.028269 Set Vref, RX VrefLevel [Byte0]: 51
8659 04:46:21.031060 [Byte1]: 51
8660 04:46:21.035682
8661 04:46:21.036102 Set Vref, RX VrefLevel [Byte0]: 52
8662 04:46:21.038649 [Byte1]: 52
8663 04:46:21.043079
8664 04:46:21.043526 Set Vref, RX VrefLevel [Byte0]: 53
8665 04:46:21.046217 [Byte1]: 53
8666 04:46:21.050846
8667 04:46:21.051268 Set Vref, RX VrefLevel [Byte0]: 54
8668 04:46:21.054201 [Byte1]: 54
8669 04:46:21.058329
8670 04:46:21.058841 Set Vref, RX VrefLevel [Byte0]: 55
8671 04:46:21.061758 [Byte1]: 55
8672 04:46:21.066176
8673 04:46:21.066693 Set Vref, RX VrefLevel [Byte0]: 56
8674 04:46:21.069053 [Byte1]: 56
8675 04:46:21.073139
8676 04:46:21.076502 Set Vref, RX VrefLevel [Byte0]: 57
8677 04:46:21.080017 [Byte1]: 57
8678 04:46:21.080439
8679 04:46:21.083673 Set Vref, RX VrefLevel [Byte0]: 58
8680 04:46:21.087302 [Byte1]: 58
8681 04:46:21.087897
8682 04:46:21.089854 Set Vref, RX VrefLevel [Byte0]: 59
8683 04:46:21.093558 [Byte1]: 59
8684 04:46:21.094093
8685 04:46:21.096767 Set Vref, RX VrefLevel [Byte0]: 60
8686 04:46:21.100046 [Byte1]: 60
8687 04:46:21.104162
8688 04:46:21.104677 Set Vref, RX VrefLevel [Byte0]: 61
8689 04:46:21.107092 [Byte1]: 61
8690 04:46:21.111242
8691 04:46:21.111799 Set Vref, RX VrefLevel [Byte0]: 62
8692 04:46:21.114428 [Byte1]: 62
8693 04:46:21.119000
8694 04:46:21.119559 Set Vref, RX VrefLevel [Byte0]: 63
8695 04:46:21.122612 [Byte1]: 63
8696 04:46:21.126606
8697 04:46:21.127029 Set Vref, RX VrefLevel [Byte0]: 64
8698 04:46:21.130263 [Byte1]: 64
8699 04:46:21.134080
8700 04:46:21.134593 Set Vref, RX VrefLevel [Byte0]: 65
8701 04:46:21.137327 [Byte1]: 65
8702 04:46:21.141931
8703 04:46:21.142663 Set Vref, RX VrefLevel [Byte0]: 66
8704 04:46:21.144632 [Byte1]: 66
8705 04:46:21.149149
8706 04:46:21.149567 Set Vref, RX VrefLevel [Byte0]: 67
8707 04:46:21.152151 [Byte1]: 67
8708 04:46:21.157190
8709 04:46:21.157706 Set Vref, RX VrefLevel [Byte0]: 68
8710 04:46:21.159962 [Byte1]: 68
8711 04:46:21.164440
8712 04:46:21.164858 Set Vref, RX VrefLevel [Byte0]: 69
8713 04:46:21.167808 [Byte1]: 69
8714 04:46:21.171664
8715 04:46:21.172099 Final RX Vref Byte 0 = 56 to rank0
8716 04:46:21.175645 Final RX Vref Byte 1 = 62 to rank0
8717 04:46:21.178732 Final RX Vref Byte 0 = 56 to rank1
8718 04:46:21.181662 Final RX Vref Byte 1 = 62 to rank1==
8719 04:46:21.184939 Dram Type= 6, Freq= 0, CH_1, rank 0
8720 04:46:21.191676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8721 04:46:21.192294 ==
8722 04:46:21.192780 DQS Delay:
8723 04:46:21.194764 DQS0 = 0, DQS1 = 0
8724 04:46:21.195277 DQM Delay:
8725 04:46:21.195797 DQM0 = 132, DQM1 = 130
8726 04:46:21.197865 DQ Delay:
8727 04:46:21.201840 DQ0 =142, DQ1 =128, DQ2 =118, DQ3 =130
8728 04:46:21.204644 DQ4 =130, DQ5 =142, DQ6 =146, DQ7 =126
8729 04:46:21.208124 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8730 04:46:21.211306 DQ12 =140, DQ13 =140, DQ14 =136, DQ15 =140
8731 04:46:21.211785
8732 04:46:21.212150
8733 04:46:21.212466
8734 04:46:21.214477 [DramC_TX_OE_Calibration] TA2
8735 04:46:21.217564 Original DQ_B0 (3 6) =30, OEN = 27
8736 04:46:21.221191 Original DQ_B1 (3 6) =30, OEN = 27
8737 04:46:21.224567 24, 0x0, End_B0=24 End_B1=24
8738 04:46:21.227793 25, 0x0, End_B0=25 End_B1=25
8739 04:46:21.228223 26, 0x0, End_B0=26 End_B1=26
8740 04:46:21.231067 27, 0x0, End_B0=27 End_B1=27
8741 04:46:21.234159 28, 0x0, End_B0=28 End_B1=28
8742 04:46:21.237780 29, 0x0, End_B0=29 End_B1=29
8743 04:46:21.241649 30, 0x0, End_B0=30 End_B1=30
8744 04:46:21.242215 31, 0x4141, End_B0=30 End_B1=30
8745 04:46:21.244093 Byte0 end_step=30 best_step=27
8746 04:46:21.247281 Byte1 end_step=30 best_step=27
8747 04:46:21.251202 Byte0 TX OE(2T, 0.5T) = (3, 3)
8748 04:46:21.254516 Byte1 TX OE(2T, 0.5T) = (3, 3)
8749 04:46:21.254943
8750 04:46:21.255277
8751 04:46:21.260282 [DQSOSCAuto] RK0, (LSB)MR18= 0x913, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 405 ps
8752 04:46:21.263800 CH1 RK0: MR19=303, MR18=913
8753 04:46:21.270865 CH1_RK0: MR19=0x303, MR18=0x913, DQSOSC=400, MR23=63, INC=23, DEC=15
8754 04:46:21.271430
8755 04:46:21.273689 ----->DramcWriteLeveling(PI) begin...
8756 04:46:21.274119 ==
8757 04:46:21.276921 Dram Type= 6, Freq= 0, CH_1, rank 1
8758 04:46:21.280441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8759 04:46:21.280865 ==
8760 04:46:21.283825 Write leveling (Byte 0): 25 => 25
8761 04:46:21.286691 Write leveling (Byte 1): 26 => 26
8762 04:46:21.290111 DramcWriteLeveling(PI) end<-----
8763 04:46:21.290631
8764 04:46:21.290968 ==
8765 04:46:21.294298 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 04:46:21.299930 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 04:46:21.300589 ==
8768 04:46:21.300951 [Gating] SW mode calibration
8769 04:46:21.310073 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8770 04:46:21.313279 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8771 04:46:21.319799 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 04:46:21.323216 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 04:46:21.326562 1 4 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8774 04:46:21.332842 1 4 12 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
8775 04:46:21.336646 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 04:46:21.339817 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 04:46:21.346294 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 04:46:21.349417 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 04:46:21.352457 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 04:46:21.359185 1 5 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8781 04:46:21.362480 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8782 04:46:21.365824 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8783 04:46:21.372370 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8784 04:46:21.375471 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 04:46:21.378807 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 04:46:21.385442 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 04:46:21.388847 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 04:46:21.392057 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8789 04:46:21.398657 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8790 04:46:21.402887 1 6 12 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
8791 04:46:21.405340 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 04:46:21.411992 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 04:46:21.415424 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 04:46:21.418598 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 04:46:21.424969 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 04:46:21.428697 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 04:46:21.431815 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8798 04:46:21.438387 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8799 04:46:21.442050 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8800 04:46:21.444898 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 04:46:21.451296 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 04:46:21.454680 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 04:46:21.458251 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 04:46:21.464725 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 04:46:21.467966 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 04:46:21.471505 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 04:46:21.477389 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 04:46:21.480762 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 04:46:21.484038 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 04:46:21.490654 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 04:46:21.494202 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 04:46:21.497451 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8813 04:46:21.504381 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8814 04:46:21.507198 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8815 04:46:21.510749 Total UI for P1: 0, mck2ui 16
8816 04:46:21.514403 best dqsien dly found for B0: ( 1, 9, 6)
8817 04:46:21.517181 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 04:46:21.520678 Total UI for P1: 0, mck2ui 16
8819 04:46:21.524205 best dqsien dly found for B1: ( 1, 9, 12)
8820 04:46:21.526944 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8821 04:46:21.530810 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8822 04:46:21.531324
8823 04:46:21.537306 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8824 04:46:21.540209 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8825 04:46:21.540633 [Gating] SW calibration Done
8826 04:46:21.543264 ==
8827 04:46:21.546862 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 04:46:21.550454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 04:46:21.550975 ==
8830 04:46:21.551315 RX Vref Scan: 0
8831 04:46:21.551667
8832 04:46:21.553551 RX Vref 0 -> 0, step: 1
8833 04:46:21.554003
8834 04:46:21.556521 RX Delay 0 -> 252, step: 8
8835 04:46:21.559837 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8836 04:46:21.563685 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8837 04:46:21.570142 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8838 04:46:21.572939 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8839 04:46:21.576414 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8840 04:46:21.579293 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8841 04:46:21.583021 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8842 04:46:21.589272 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8843 04:46:21.593246 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8844 04:46:21.596324 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8845 04:46:21.599188 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8846 04:46:21.602565 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8847 04:46:21.609268 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8848 04:46:21.612556 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8849 04:46:21.616113 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8850 04:46:21.619305 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8851 04:46:21.619854 ==
8852 04:46:21.622679 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 04:46:21.629384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 04:46:21.629808 ==
8855 04:46:21.630144 DQS Delay:
8856 04:46:21.631984 DQS0 = 0, DQS1 = 0
8857 04:46:21.632404 DQM Delay:
8858 04:46:21.635477 DQM0 = 135, DQM1 = 130
8859 04:46:21.635898 DQ Delay:
8860 04:46:21.638916 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8861 04:46:21.642078 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =135
8862 04:46:21.645098 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =127
8863 04:46:21.648873 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =139
8864 04:46:21.649389
8865 04:46:21.649728
8866 04:46:21.650046 ==
8867 04:46:21.652363 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 04:46:21.659020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 04:46:21.659586 ==
8870 04:46:21.659927
8871 04:46:21.660238
8872 04:46:21.660535 TX Vref Scan disable
8873 04:46:21.662422 == TX Byte 0 ==
8874 04:46:21.665572 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8875 04:46:21.672268 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8876 04:46:21.672784 == TX Byte 1 ==
8877 04:46:21.675084 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8878 04:46:21.682200 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8879 04:46:21.682721 ==
8880 04:46:21.685119 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 04:46:21.688574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 04:46:21.689095 ==
8883 04:46:21.702226
8884 04:46:21.705379 TX Vref early break, caculate TX vref
8885 04:46:21.708761 TX Vref=16, minBit 9, minWin=22, winSum=377
8886 04:46:21.712101 TX Vref=18, minBit 9, minWin=22, winSum=384
8887 04:46:21.714933 TX Vref=20, minBit 9, minWin=22, winSum=389
8888 04:46:21.718353 TX Vref=22, minBit 5, minWin=24, winSum=401
8889 04:46:21.721682 TX Vref=24, minBit 9, minWin=24, winSum=409
8890 04:46:21.728597 TX Vref=26, minBit 3, minWin=25, winSum=418
8891 04:46:21.731939 TX Vref=28, minBit 9, minWin=24, winSum=416
8892 04:46:21.735216 TX Vref=30, minBit 9, minWin=24, winSum=419
8893 04:46:21.738564 TX Vref=32, minBit 0, minWin=24, winSum=410
8894 04:46:21.741411 TX Vref=34, minBit 9, minWin=23, winSum=399
8895 04:46:21.748386 TX Vref=36, minBit 11, minWin=23, winSum=397
8896 04:46:21.751339 [TxChooseVref] Worse bit 3, Min win 25, Win sum 418, Final Vref 26
8897 04:46:21.751884
8898 04:46:21.754718 Final TX Range 0 Vref 26
8899 04:46:21.755184
8900 04:46:21.755760 ==
8901 04:46:21.758112 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 04:46:21.761052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 04:46:21.761476 ==
8904 04:46:21.764847
8905 04:46:21.765356
8906 04:46:21.765692 TX Vref Scan disable
8907 04:46:21.771337 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8908 04:46:21.771906 == TX Byte 0 ==
8909 04:46:21.774454 u2DelayCellOfst[0]=14 cells (4 PI)
8910 04:46:21.777780 u2DelayCellOfst[1]=10 cells (3 PI)
8911 04:46:21.780773 u2DelayCellOfst[2]=0 cells (0 PI)
8912 04:46:21.784306 u2DelayCellOfst[3]=3 cells (1 PI)
8913 04:46:21.787841 u2DelayCellOfst[4]=7 cells (2 PI)
8914 04:46:21.791165 u2DelayCellOfst[5]=14 cells (4 PI)
8915 04:46:21.794527 u2DelayCellOfst[6]=14 cells (4 PI)
8916 04:46:21.797605 u2DelayCellOfst[7]=3 cells (1 PI)
8917 04:46:21.800820 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8918 04:46:21.804138 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8919 04:46:21.808013 == TX Byte 1 ==
8920 04:46:21.811493 u2DelayCellOfst[8]=0 cells (0 PI)
8921 04:46:21.813986 u2DelayCellOfst[9]=0 cells (0 PI)
8922 04:46:21.817382 u2DelayCellOfst[10]=10 cells (3 PI)
8923 04:46:21.820934 u2DelayCellOfst[11]=7 cells (2 PI)
8924 04:46:21.824248 u2DelayCellOfst[12]=10 cells (3 PI)
8925 04:46:21.827312 u2DelayCellOfst[13]=14 cells (4 PI)
8926 04:46:21.827812 u2DelayCellOfst[14]=17 cells (5 PI)
8927 04:46:21.830480 u2DelayCellOfst[15]=17 cells (5 PI)
8928 04:46:21.837006 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8929 04:46:21.840692 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8930 04:46:21.843873 DramC Write-DBI on
8931 04:46:21.844389 ==
8932 04:46:21.847351 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 04:46:21.850179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 04:46:21.850698 ==
8935 04:46:21.851034
8936 04:46:21.851339
8937 04:46:21.854003 TX Vref Scan disable
8938 04:46:21.854421 == TX Byte 0 ==
8939 04:46:21.860343 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8940 04:46:21.860763 == TX Byte 1 ==
8941 04:46:21.863470 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8942 04:46:21.867230 DramC Write-DBI off
8943 04:46:21.867788
8944 04:46:21.868121 [DATLAT]
8945 04:46:21.870396 Freq=1600, CH1 RK1
8946 04:46:21.870907
8947 04:46:21.871239 DATLAT Default: 0xf
8948 04:46:21.873457 0, 0xFFFF, sum = 0
8949 04:46:21.873898 1, 0xFFFF, sum = 0
8950 04:46:21.876880 2, 0xFFFF, sum = 0
8951 04:46:21.877304 3, 0xFFFF, sum = 0
8952 04:46:21.880094 4, 0xFFFF, sum = 0
8953 04:46:21.883116 5, 0xFFFF, sum = 0
8954 04:46:21.883565 6, 0xFFFF, sum = 0
8955 04:46:21.886493 7, 0xFFFF, sum = 0
8956 04:46:21.886884 8, 0xFFFF, sum = 0
8957 04:46:21.890206 9, 0xFFFF, sum = 0
8958 04:46:21.890727 10, 0xFFFF, sum = 0
8959 04:46:21.893214 11, 0xFFFF, sum = 0
8960 04:46:21.893639 12, 0xFFFF, sum = 0
8961 04:46:21.896237 13, 0xFFFF, sum = 0
8962 04:46:21.896662 14, 0x0, sum = 1
8963 04:46:21.899811 15, 0x0, sum = 2
8964 04:46:21.900232 16, 0x0, sum = 3
8965 04:46:21.902858 17, 0x0, sum = 4
8966 04:46:21.903280 best_step = 15
8967 04:46:21.903662
8968 04:46:21.903973 ==
8969 04:46:21.905999 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 04:46:21.912873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 04:46:21.913294 ==
8972 04:46:21.913706 RX Vref Scan: 0
8973 04:46:21.914029
8974 04:46:21.915966 RX Vref 0 -> 0, step: 1
8975 04:46:21.916383
8976 04:46:21.919354 RX Delay 11 -> 252, step: 4
8977 04:46:21.922935 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8978 04:46:21.926313 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8979 04:46:21.928863 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8980 04:46:21.935984 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8981 04:46:21.939216 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8982 04:46:21.942380 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8983 04:46:21.945602 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8984 04:46:21.952600 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8985 04:46:21.955761 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8986 04:46:21.958937 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8987 04:46:21.962626 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8988 04:46:21.965434 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8989 04:46:21.972484 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8990 04:46:21.975341 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8991 04:46:21.978690 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8992 04:46:21.982342 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8993 04:46:21.982878 ==
8994 04:46:21.984990 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 04:46:21.991988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 04:46:21.992505 ==
8997 04:46:21.992843 DQS Delay:
8998 04:46:21.995025 DQS0 = 0, DQS1 = 0
8999 04:46:21.995592 DQM Delay:
9000 04:46:21.998947 DQM0 = 133, DQM1 = 128
9001 04:46:21.999521 DQ Delay:
9002 04:46:22.001690 DQ0 =136, DQ1 =132, DQ2 =120, DQ3 =130
9003 04:46:22.005029 DQ4 =130, DQ5 =144, DQ6 =142, DQ7 =130
9004 04:46:22.008382 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
9005 04:46:22.010965 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9006 04:46:22.011417
9007 04:46:22.011754
9008 04:46:22.012060
9009 04:46:22.014723 [DramC_TX_OE_Calibration] TA2
9010 04:46:22.018305 Original DQ_B0 (3 6) =30, OEN = 27
9011 04:46:22.021551 Original DQ_B1 (3 6) =30, OEN = 27
9012 04:46:22.024396 24, 0x0, End_B0=24 End_B1=24
9013 04:46:22.027624 25, 0x0, End_B0=25 End_B1=25
9014 04:46:22.028152 26, 0x0, End_B0=26 End_B1=26
9015 04:46:22.031196 27, 0x0, End_B0=27 End_B1=27
9016 04:46:22.034598 28, 0x0, End_B0=28 End_B1=28
9017 04:46:22.037319 29, 0x0, End_B0=29 End_B1=29
9018 04:46:22.041071 30, 0x0, End_B0=30 End_B1=30
9019 04:46:22.041596 31, 0x4141, End_B0=30 End_B1=30
9020 04:46:22.044407 Byte0 end_step=30 best_step=27
9021 04:46:22.047575 Byte1 end_step=30 best_step=27
9022 04:46:22.050715 Byte0 TX OE(2T, 0.5T) = (3, 3)
9023 04:46:22.054231 Byte1 TX OE(2T, 0.5T) = (3, 3)
9024 04:46:22.054791
9025 04:46:22.055165
9026 04:46:22.060624 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
9027 04:46:22.063944 CH1 RK1: MR19=303, MR18=F1D
9028 04:46:22.070618 CH1_RK1: MR19=0x303, MR18=0xF1D, DQSOSC=395, MR23=63, INC=23, DEC=15
9029 04:46:22.074507 [RxdqsGatingPostProcess] freq 1600
9030 04:46:22.080690 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9031 04:46:22.081158 best DQS0 dly(2T, 0.5T) = (1, 1)
9032 04:46:22.083760 best DQS1 dly(2T, 0.5T) = (1, 1)
9033 04:46:22.087461 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9034 04:46:22.090741 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9035 04:46:22.093929 best DQS0 dly(2T, 0.5T) = (1, 1)
9036 04:46:22.097170 best DQS1 dly(2T, 0.5T) = (1, 1)
9037 04:46:22.100519 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9038 04:46:22.103536 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9039 04:46:22.107507 Pre-setting of DQS Precalculation
9040 04:46:22.110418 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9041 04:46:22.120178 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9042 04:46:22.127654 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9043 04:46:22.128220
9044 04:46:22.128590
9045 04:46:22.129743 [Calibration Summary] 3200 Mbps
9046 04:46:22.130209 CH 0, Rank 0
9047 04:46:22.133888 SW Impedance : PASS
9048 04:46:22.134446 DUTY Scan : NO K
9049 04:46:22.136822 ZQ Calibration : PASS
9050 04:46:22.140013 Jitter Meter : NO K
9051 04:46:22.140569 CBT Training : PASS
9052 04:46:22.143281 Write leveling : PASS
9053 04:46:22.146249 RX DQS gating : PASS
9054 04:46:22.146717 RX DQ/DQS(RDDQC) : PASS
9055 04:46:22.149732 TX DQ/DQS : PASS
9056 04:46:22.153316 RX DATLAT : PASS
9057 04:46:22.153867 RX DQ/DQS(Engine): PASS
9058 04:46:22.156618 TX OE : PASS
9059 04:46:22.157048 All Pass.
9060 04:46:22.157612
9061 04:46:22.159568 CH 0, Rank 1
9062 04:46:22.160042 SW Impedance : PASS
9063 04:46:22.163468 DUTY Scan : NO K
9064 04:46:22.166292 ZQ Calibration : PASS
9065 04:46:22.166808 Jitter Meter : NO K
9066 04:46:22.169580 CBT Training : PASS
9067 04:46:22.172643 Write leveling : PASS
9068 04:46:22.173068 RX DQS gating : PASS
9069 04:46:22.176232 RX DQ/DQS(RDDQC) : PASS
9070 04:46:22.179645 TX DQ/DQS : PASS
9071 04:46:22.180208 RX DATLAT : PASS
9072 04:46:22.182335 RX DQ/DQS(Engine): PASS
9073 04:46:22.186446 TX OE : PASS
9074 04:46:22.186965 All Pass.
9075 04:46:22.187303
9076 04:46:22.187683 CH 1, Rank 0
9077 04:46:22.189168 SW Impedance : PASS
9078 04:46:22.192634 DUTY Scan : NO K
9079 04:46:22.193153 ZQ Calibration : PASS
9080 04:46:22.195936 Jitter Meter : NO K
9081 04:46:22.199184 CBT Training : PASS
9082 04:46:22.199634 Write leveling : PASS
9083 04:46:22.202045 RX DQS gating : PASS
9084 04:46:22.205846 RX DQ/DQS(RDDQC) : PASS
9085 04:46:22.206362 TX DQ/DQS : PASS
9086 04:46:22.209268 RX DATLAT : PASS
9087 04:46:22.209780 RX DQ/DQS(Engine): PASS
9088 04:46:22.212582 TX OE : PASS
9089 04:46:22.213008 All Pass.
9090 04:46:22.213340
9091 04:46:22.215445 CH 1, Rank 1
9092 04:46:22.215912 SW Impedance : PASS
9093 04:46:22.218874 DUTY Scan : NO K
9094 04:46:22.222005 ZQ Calibration : PASS
9095 04:46:22.222521 Jitter Meter : NO K
9096 04:46:22.226100 CBT Training : PASS
9097 04:46:22.228405 Write leveling : PASS
9098 04:46:22.228831 RX DQS gating : PASS
9099 04:46:22.231894 RX DQ/DQS(RDDQC) : PASS
9100 04:46:22.235161 TX DQ/DQS : PASS
9101 04:46:22.235666 RX DATLAT : PASS
9102 04:46:22.238780 RX DQ/DQS(Engine): PASS
9103 04:46:22.241894 TX OE : PASS
9104 04:46:22.242415 All Pass.
9105 04:46:22.242758
9106 04:46:22.245007 DramC Write-DBI on
9107 04:46:22.245431 PER_BANK_REFRESH: Hybrid Mode
9108 04:46:22.248145 TX_TRACKING: ON
9109 04:46:22.257953 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9110 04:46:22.264547 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9111 04:46:22.271269 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9112 04:46:22.274375 [FAST_K] Save calibration result to emmc
9113 04:46:22.278047 sync common calibartion params.
9114 04:46:22.280926 sync cbt_mode0:1, 1:1
9115 04:46:22.281338 dram_init: ddr_geometry: 2
9116 04:46:22.284677 dram_init: ddr_geometry: 2
9117 04:46:22.288148 dram_init: ddr_geometry: 2
9118 04:46:22.291340 0:dram_rank_size:100000000
9119 04:46:22.291818 1:dram_rank_size:100000000
9120 04:46:22.297933 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9121 04:46:22.300899 DFS_SHUFFLE_HW_MODE: ON
9122 04:46:22.304073 dramc_set_vcore_voltage set vcore to 725000
9123 04:46:22.307662 Read voltage for 1600, 0
9124 04:46:22.308074 Vio18 = 0
9125 04:46:22.308407 Vcore = 725000
9126 04:46:22.311081 Vdram = 0
9127 04:46:22.311623 Vddq = 0
9128 04:46:22.311958 Vmddr = 0
9129 04:46:22.314362 switch to 3200 Mbps bootup
9130 04:46:22.314775 [DramcRunTimeConfig]
9131 04:46:22.317692 PHYPLL
9132 04:46:22.318104 DPM_CONTROL_AFTERK: ON
9133 04:46:22.321215 PER_BANK_REFRESH: ON
9134 04:46:22.324055 REFRESH_OVERHEAD_REDUCTION: ON
9135 04:46:22.324567 CMD_PICG_NEW_MODE: OFF
9136 04:46:22.327425 XRTWTW_NEW_MODE: ON
9137 04:46:22.327965 XRTRTR_NEW_MODE: ON
9138 04:46:22.331190 TX_TRACKING: ON
9139 04:46:22.331663 RDSEL_TRACKING: OFF
9140 04:46:22.334041 DQS Precalculation for DVFS: ON
9141 04:46:22.337823 RX_TRACKING: OFF
9142 04:46:22.338336 HW_GATING DBG: ON
9143 04:46:22.340756 ZQCS_ENABLE_LP4: ON
9144 04:46:22.341270 RX_PICG_NEW_MODE: ON
9145 04:46:22.343914 TX_PICG_NEW_MODE: ON
9146 04:46:22.347219 ENABLE_RX_DCM_DPHY: ON
9147 04:46:22.350907 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9148 04:46:22.351470 DUMMY_READ_FOR_TRACKING: OFF
9149 04:46:22.353806 !!! SPM_CONTROL_AFTERK: OFF
9150 04:46:22.357147 !!! SPM could not control APHY
9151 04:46:22.360189 IMPEDANCE_TRACKING: ON
9152 04:46:22.360611 TEMP_SENSOR: ON
9153 04:46:22.363550 HW_SAVE_FOR_SR: OFF
9154 04:46:22.363971 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9155 04:46:22.370278 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9156 04:46:22.370795 Read ODT Tracking: ON
9157 04:46:22.373600 Refresh Rate DeBounce: ON
9158 04:46:22.374115 DFS_NO_QUEUE_FLUSH: ON
9159 04:46:22.376784 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9160 04:46:22.380046 ENABLE_DFS_RUNTIME_MRW: OFF
9161 04:46:22.383483 DDR_RESERVE_NEW_MODE: ON
9162 04:46:22.386987 MR_CBT_SWITCH_FREQ: ON
9163 04:46:22.387555 =========================
9164 04:46:22.406045 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9165 04:46:22.409561 dram_init: ddr_geometry: 2
9166 04:46:22.428125 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9167 04:46:22.432050 dram_init: dram init end (result: 0)
9168 04:46:22.437995 DRAM-K: Full calibration passed in 24380 msecs
9169 04:46:22.441323 MRC: failed to locate region type 0.
9170 04:46:22.441882 DRAM rank0 size:0x100000000,
9171 04:46:22.444409 DRAM rank1 size=0x100000000
9172 04:46:22.454410 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9173 04:46:22.460778 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9174 04:46:22.470647 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9175 04:46:22.477356 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9176 04:46:22.477826 DRAM rank0 size:0x100000000,
9177 04:46:22.480382 DRAM rank1 size=0x100000000
9178 04:46:22.480831 CBMEM:
9179 04:46:22.483928 IMD: root @ 0xfffff000 254 entries.
9180 04:46:22.486655 IMD: root @ 0xffffec00 62 entries.
9181 04:46:22.493769 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9182 04:46:22.497368 WARNING: RO_VPD is uninitialized or empty.
9183 04:46:22.500226 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9184 04:46:22.507893 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9185 04:46:22.520370 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9186 04:46:22.532150 BS: romstage times (exec / console): total (unknown) / 23914 ms
9187 04:46:22.532574
9188 04:46:22.532907
9189 04:46:22.542534 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9190 04:46:22.545413 ARM64: Exception handlers installed.
9191 04:46:22.549000 ARM64: Testing exception
9192 04:46:22.552339 ARM64: Done test exception
9193 04:46:22.552858 Enumerating buses...
9194 04:46:22.555321 Show all devs... Before device enumeration.
9195 04:46:22.558644 Root Device: enabled 1
9196 04:46:22.562263 CPU_CLUSTER: 0: enabled 1
9197 04:46:22.562778 CPU: 00: enabled 1
9198 04:46:22.564901 Compare with tree...
9199 04:46:22.565313 Root Device: enabled 1
9200 04:46:22.568798 CPU_CLUSTER: 0: enabled 1
9201 04:46:22.571964 CPU: 00: enabled 1
9202 04:46:22.572381 Root Device scanning...
9203 04:46:22.575000 scan_static_bus for Root Device
9204 04:46:22.578892 CPU_CLUSTER: 0 enabled
9205 04:46:22.581530 scan_static_bus for Root Device done
9206 04:46:22.585226 scan_bus: bus Root Device finished in 8 msecs
9207 04:46:22.585742 done
9208 04:46:22.591283 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9209 04:46:22.594570 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9210 04:46:22.601232 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9211 04:46:22.607482 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9212 04:46:22.608009 Allocating resources...
9213 04:46:22.611070 Reading resources...
9214 04:46:22.614521 Root Device read_resources bus 0 link: 0
9215 04:46:22.617562 DRAM rank0 size:0x100000000,
9216 04:46:22.618119 DRAM rank1 size=0x100000000
9217 04:46:22.624386 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9218 04:46:22.624905 CPU: 00 missing read_resources
9219 04:46:22.630601 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9220 04:46:22.634944 Root Device read_resources bus 0 link: 0 done
9221 04:46:22.637819 Done reading resources.
9222 04:46:22.640499 Show resources in subtree (Root Device)...After reading.
9223 04:46:22.644067 Root Device child on link 0 CPU_CLUSTER: 0
9224 04:46:22.647412 CPU_CLUSTER: 0 child on link 0 CPU: 00
9225 04:46:22.657146 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9226 04:46:22.657685 CPU: 00
9227 04:46:22.663618 Root Device assign_resources, bus 0 link: 0
9228 04:46:22.667670 CPU_CLUSTER: 0 missing set_resources
9229 04:46:22.670384 Root Device assign_resources, bus 0 link: 0 done
9230 04:46:22.670900 Done setting resources.
9231 04:46:22.677027 Show resources in subtree (Root Device)...After assigning values.
9232 04:46:22.680024 Root Device child on link 0 CPU_CLUSTER: 0
9233 04:46:22.686921 CPU_CLUSTER: 0 child on link 0 CPU: 00
9234 04:46:22.693365 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9235 04:46:22.696933 CPU: 00
9236 04:46:22.697448 Done allocating resources.
9237 04:46:22.703720 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9238 04:46:22.704241 Enabling resources...
9239 04:46:22.706940 done.
9240 04:46:22.710219 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9241 04:46:22.713663 Initializing devices...
9242 04:46:22.714179 Root Device init
9243 04:46:22.716759 init hardware done!
9244 04:46:22.717384 0x00000018: ctrlr->caps
9245 04:46:22.721015 52.000 MHz: ctrlr->f_max
9246 04:46:22.723899 0.400 MHz: ctrlr->f_min
9247 04:46:22.724425 0x40ff8080: ctrlr->voltages
9248 04:46:22.726838 sclk: 390625
9249 04:46:22.727384 Bus Width = 1
9250 04:46:22.729781 sclk: 390625
9251 04:46:22.730200 Bus Width = 1
9252 04:46:22.733771 Early init status = 3
9253 04:46:22.736652 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9254 04:46:22.740451 in-header: 03 fc 00 00 01 00 00 00
9255 04:46:22.743221 in-data: 00
9256 04:46:22.746233 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9257 04:46:22.751816 in-header: 03 fd 00 00 00 00 00 00
9258 04:46:22.755033 in-data:
9259 04:46:22.758583 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9260 04:46:22.761434 in-header: 03 fc 00 00 01 00 00 00
9261 04:46:22.764319 in-data: 00
9262 04:46:22.768218 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9263 04:46:22.772806 in-header: 03 fd 00 00 00 00 00 00
9264 04:46:22.776025 in-data:
9265 04:46:22.778987 [SSUSB] Setting up USB HOST controller...
9266 04:46:22.782787 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9267 04:46:22.786205 [SSUSB] phy power-on done.
9268 04:46:22.789093 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9269 04:46:22.796509 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9270 04:46:22.799276 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9271 04:46:22.805810 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9272 04:46:22.812980 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9273 04:46:22.819162 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9274 04:46:22.825940 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9275 04:46:22.832326 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9276 04:46:22.835656 SPM: binary array size = 0x9dc
9277 04:46:22.838739 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9278 04:46:22.845059 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9279 04:46:22.851974 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9280 04:46:22.858303 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9281 04:46:22.861296 configure_display: Starting display init
9282 04:46:22.895920 anx7625_power_on_init: Init interface.
9283 04:46:22.899278 anx7625_disable_pd_protocol: Disabled PD feature.
9284 04:46:22.902664 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9285 04:46:22.930633 anx7625_start_dp_work: Secure OCM version=00
9286 04:46:22.933476 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9287 04:46:22.948417 sp_tx_get_edid_block: EDID Block = 1
9288 04:46:23.051661 Extracted contents:
9289 04:46:23.054468 header: 00 ff ff ff ff ff ff 00
9290 04:46:23.058186 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9291 04:46:23.061193 version: 01 04
9292 04:46:23.064782 basic params: 95 1f 11 78 0a
9293 04:46:23.067538 chroma info: 76 90 94 55 54 90 27 21 50 54
9294 04:46:23.071123 established: 00 00 00
9295 04:46:23.076965 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9296 04:46:23.083625 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9297 04:46:23.087847 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9298 04:46:23.094093 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9299 04:46:23.100038 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9300 04:46:23.103908 extensions: 00
9301 04:46:23.104430 checksum: fb
9302 04:46:23.104764
9303 04:46:23.110543 Manufacturer: IVO Model 57d Serial Number 0
9304 04:46:23.111047 Made week 0 of 2020
9305 04:46:23.113997 EDID version: 1.4
9306 04:46:23.114530 Digital display
9307 04:46:23.117445 6 bits per primary color channel
9308 04:46:23.117974 DisplayPort interface
9309 04:46:23.119894 Maximum image size: 31 cm x 17 cm
9310 04:46:23.124002 Gamma: 220%
9311 04:46:23.124527 Check DPMS levels
9312 04:46:23.130188 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9313 04:46:23.133229 First detailed timing is preferred timing
9314 04:46:23.136899 Established timings supported:
9315 04:46:23.137425 Standard timings supported:
9316 04:46:23.139965 Detailed timings
9317 04:46:23.143119 Hex of detail: 383680a07038204018303c0035ae10000019
9318 04:46:23.149310 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9319 04:46:23.153104 0780 0798 07c8 0820 hborder 0
9320 04:46:23.156708 0438 043b 0447 0458 vborder 0
9321 04:46:23.159904 -hsync -vsync
9322 04:46:23.160370 Did detailed timing
9323 04:46:23.166590 Hex of detail: 000000000000000000000000000000000000
9324 04:46:23.169595 Manufacturer-specified data, tag 0
9325 04:46:23.172733 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9326 04:46:23.176070 ASCII string: InfoVision
9327 04:46:23.179322 Hex of detail: 000000fe00523134304e574635205248200a
9328 04:46:23.182450 ASCII string: R140NWF5 RH
9329 04:46:23.182872 Checksum
9330 04:46:23.185899 Checksum: 0xfb (valid)
9331 04:46:23.189115 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9332 04:46:23.192363 DSI data_rate: 832800000 bps
9333 04:46:23.198839 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9334 04:46:23.202310 anx7625_parse_edid: pixelclock(138800).
9335 04:46:23.205760 hactive(1920), hsync(48), hfp(24), hbp(88)
9336 04:46:23.208838 vactive(1080), vsync(12), vfp(3), vbp(17)
9337 04:46:23.212490 anx7625_dsi_config: config dsi.
9338 04:46:23.219000 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9339 04:46:23.232912 anx7625_dsi_config: success to config DSI
9340 04:46:23.236265 anx7625_dp_start: MIPI phy setup OK.
9341 04:46:23.240026 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9342 04:46:23.243472 mtk_ddp_mode_set invalid vrefresh 60
9343 04:46:23.246200 main_disp_path_setup
9344 04:46:23.246617 ovl_layer_smi_id_en
9345 04:46:23.250169 ovl_layer_smi_id_en
9346 04:46:23.250685 ccorr_config
9347 04:46:23.251021 aal_config
9348 04:46:23.253098 gamma_config
9349 04:46:23.253520 postmask_config
9350 04:46:23.256036 dither_config
9351 04:46:23.260040 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9352 04:46:23.266409 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9353 04:46:23.269262 Root Device init finished in 552 msecs
9354 04:46:23.273016 CPU_CLUSTER: 0 init
9355 04:46:23.279684 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9356 04:46:23.285977 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9357 04:46:23.286401 APU_MBOX 0x190000b0 = 0x10001
9358 04:46:23.289176 APU_MBOX 0x190001b0 = 0x10001
9359 04:46:23.292547 APU_MBOX 0x190005b0 = 0x10001
9360 04:46:23.295972 APU_MBOX 0x190006b0 = 0x10001
9361 04:46:23.302009 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9362 04:46:23.312164 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9363 04:46:23.324526 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9364 04:46:23.330713 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9365 04:46:23.343148 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9366 04:46:23.351509 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9367 04:46:23.354680 CPU_CLUSTER: 0 init finished in 81 msecs
9368 04:46:23.357959 Devices initialized
9369 04:46:23.361676 Show all devs... After init.
9370 04:46:23.362269 Root Device: enabled 1
9371 04:46:23.364835 CPU_CLUSTER: 0: enabled 1
9372 04:46:23.368503 CPU: 00: enabled 1
9373 04:46:23.371145 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9374 04:46:23.374588 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9375 04:46:23.378023 ELOG: NV offset 0x57f000 size 0x1000
9376 04:46:23.384606 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9377 04:46:23.392011 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9378 04:46:23.394562 ELOG: Event(17) added with size 13 at 2024-02-04 04:46:23 UTC
9379 04:46:23.401505 out: cmd=0x121: 03 db 21 01 00 00 00 00
9380 04:46:23.404451 in-header: 03 5a 00 00 2c 00 00 00
9381 04:46:23.414521 in-data: 05 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9382 04:46:23.420937 ELOG: Event(A1) added with size 10 at 2024-02-04 04:46:23 UTC
9383 04:46:23.427932 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9384 04:46:23.434814 ELOG: Event(A0) added with size 9 at 2024-02-04 04:46:23 UTC
9385 04:46:23.437908 elog_add_boot_reason: Logged dev mode boot
9386 04:46:23.443984 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9387 04:46:23.444484 Finalize devices...
9388 04:46:23.447469 Devices finalized
9389 04:46:23.451008 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9390 04:46:23.454021 Writing coreboot table at 0xffe64000
9391 04:46:23.457774 0. 000000000010a000-0000000000113fff: RAMSTAGE
9392 04:46:23.464208 1. 0000000040000000-00000000400fffff: RAM
9393 04:46:23.467441 2. 0000000040100000-000000004032afff: RAMSTAGE
9394 04:46:23.470760 3. 000000004032b000-00000000545fffff: RAM
9395 04:46:23.473765 4. 0000000054600000-000000005465ffff: BL31
9396 04:46:23.477175 5. 0000000054660000-00000000ffe63fff: RAM
9397 04:46:23.484311 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9398 04:46:23.487118 7. 0000000100000000-000000023fffffff: RAM
9399 04:46:23.490503 Passing 5 GPIOs to payload:
9400 04:46:23.493905 NAME | PORT | POLARITY | VALUE
9401 04:46:23.500398 EC in RW | 0x000000aa | low | undefined
9402 04:46:23.503498 EC interrupt | 0x00000005 | low | undefined
9403 04:46:23.506733 TPM interrupt | 0x000000ab | high | undefined
9404 04:46:23.513729 SD card detect | 0x00000011 | high | undefined
9405 04:46:23.516698 speaker enable | 0x00000093 | high | undefined
9406 04:46:23.520066 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9407 04:46:23.523301 in-header: 03 f9 00 00 02 00 00 00
9408 04:46:23.526933 in-data: 02 00
9409 04:46:23.530176 ADC[4]: Raw value=903694 ID=7
9410 04:46:23.532970 ADC[3]: Raw value=213916 ID=1
9411 04:46:23.533395 RAM Code: 0x71
9412 04:46:23.537467 ADC[6]: Raw value=75000 ID=0
9413 04:46:23.540694 ADC[5]: Raw value=213916 ID=1
9414 04:46:23.541228 SKU Code: 0x1
9415 04:46:23.546994 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 521
9416 04:46:23.547610 coreboot table: 964 bytes.
9417 04:46:23.549934 IMD ROOT 0. 0xfffff000 0x00001000
9418 04:46:23.553307 IMD SMALL 1. 0xffffe000 0x00001000
9419 04:46:23.556377 RO MCACHE 2. 0xffffc000 0x00001104
9420 04:46:23.559616 CONSOLE 3. 0xfff7c000 0x00080000
9421 04:46:23.562673 FMAP 4. 0xfff7b000 0x00000452
9422 04:46:23.566187 TIME STAMP 5. 0xfff7a000 0x00000910
9423 04:46:23.569158 VBOOT WORK 6. 0xfff66000 0x00014000
9424 04:46:23.573236 RAMOOPS 7. 0xffe66000 0x00100000
9425 04:46:23.575997 COREBOOT 8. 0xffe64000 0x00002000
9426 04:46:23.579179 IMD small region:
9427 04:46:23.582501 IMD ROOT 0. 0xffffec00 0x00000400
9428 04:46:23.586407 VPD 1. 0xffffeb80 0x0000006c
9429 04:46:23.589229 MMC STATUS 2. 0xffffeb60 0x00000004
9430 04:46:23.596047 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9431 04:46:23.596627 Probing TPM: done!
9432 04:46:23.599644 Connected to device vid:did:rid of 1ae0:0028:00
9433 04:46:23.611048 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9434 04:46:23.613945 Initialized TPM device CR50 revision 0
9435 04:46:23.617547 Checking cr50 for pending updates
9436 04:46:23.621413 Reading cr50 TPM mode
9437 04:46:23.630341 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9438 04:46:23.636684 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9439 04:46:23.676973 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9440 04:46:23.680525 Checking segment from ROM address 0x40100000
9441 04:46:23.683843 Checking segment from ROM address 0x4010001c
9442 04:46:23.690202 Loading segment from ROM address 0x40100000
9443 04:46:23.690729 code (compression=0)
9444 04:46:23.700267 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9445 04:46:23.706731 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9446 04:46:23.707261 it's not compressed!
9447 04:46:23.713445 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9448 04:46:23.720245 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9449 04:46:23.737327 Loading segment from ROM address 0x4010001c
9450 04:46:23.737856 Entry Point 0x80000000
9451 04:46:23.740413 Loaded segments
9452 04:46:23.743997 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9453 04:46:23.750389 Jumping to boot code at 0x80000000(0xffe64000)
9454 04:46:23.757266 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9455 04:46:23.763896 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9456 04:46:23.771941 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9457 04:46:23.775123 Checking segment from ROM address 0x40100000
9458 04:46:23.778346 Checking segment from ROM address 0x4010001c
9459 04:46:23.784973 Loading segment from ROM address 0x40100000
9460 04:46:23.785466 code (compression=1)
9461 04:46:23.791265 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9462 04:46:23.802132 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9463 04:46:23.802651 using LZMA
9464 04:46:23.810816 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9465 04:46:23.816611 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9466 04:46:23.820356 Loading segment from ROM address 0x4010001c
9467 04:46:23.820872 Entry Point 0x54601000
9468 04:46:23.823289 Loaded segments
9469 04:46:23.826820 NOTICE: MT8192 bl31_setup
9470 04:46:23.834107 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9471 04:46:23.837009 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9472 04:46:23.840108 WARNING: region 0:
9473 04:46:23.844018 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 04:46:23.844537 WARNING: region 1:
9475 04:46:23.850171 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9476 04:46:23.853445 WARNING: region 2:
9477 04:46:23.857036 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9478 04:46:23.860346 WARNING: region 3:
9479 04:46:23.863739 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9480 04:46:23.866844 WARNING: region 4:
9481 04:46:23.873710 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9482 04:46:23.874297 WARNING: region 5:
9483 04:46:23.876668 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 04:46:23.880292 WARNING: region 6:
9485 04:46:23.883433 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 04:46:23.886504 WARNING: region 7:
9487 04:46:23.890358 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9488 04:46:23.896695 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9489 04:46:23.899967 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9490 04:46:23.903461 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9491 04:46:23.909647 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9492 04:46:23.913193 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9493 04:46:23.919580 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9494 04:46:23.923462 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9495 04:46:23.926662 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9496 04:46:23.932702 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9497 04:46:23.936500 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9498 04:46:23.939722 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9499 04:46:23.946537 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9500 04:46:23.949846 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9501 04:46:23.956408 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9502 04:46:23.959811 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9503 04:46:23.962934 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9504 04:46:23.969553 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9505 04:46:23.972760 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9506 04:46:23.975920 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9507 04:46:23.982963 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9508 04:46:23.985945 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9509 04:46:23.992519 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9510 04:46:23.996645 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9511 04:46:23.999959 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9512 04:46:24.006128 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9513 04:46:24.009754 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9514 04:46:24.016004 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9515 04:46:24.019399 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9516 04:46:24.023029 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9517 04:46:24.029397 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9518 04:46:24.032552 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9519 04:46:24.039425 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9520 04:46:24.042546 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9521 04:46:24.046217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9522 04:46:24.049502 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9523 04:46:24.055874 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9524 04:46:24.059448 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9525 04:46:24.062591 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9526 04:46:24.066122 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9527 04:46:24.072788 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9528 04:46:24.075860 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9529 04:46:24.079473 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9530 04:46:24.082956 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9531 04:46:24.089606 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9532 04:46:24.093322 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9533 04:46:24.095756 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9534 04:46:24.099147 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9535 04:46:24.105684 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9536 04:46:24.109348 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9537 04:46:24.115759 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9538 04:46:24.118989 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9539 04:46:24.122107 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9540 04:46:24.128808 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9541 04:46:24.132180 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9542 04:46:24.138962 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9543 04:46:24.142341 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9544 04:46:24.149082 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9545 04:46:24.152283 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9546 04:46:24.155932 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9547 04:46:24.162318 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9548 04:46:24.165309 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9549 04:46:24.172098 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9550 04:46:24.175321 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9551 04:46:24.182644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9552 04:46:24.185473 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9553 04:46:24.192567 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9554 04:46:24.195823 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9555 04:46:24.198722 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9556 04:46:24.205785 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9557 04:46:24.209368 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9558 04:46:24.215758 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9559 04:46:24.218802 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9560 04:46:24.222868 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9561 04:46:24.228950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9562 04:46:24.232002 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9563 04:46:24.238394 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9564 04:46:24.241918 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9565 04:46:24.248629 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9566 04:46:24.252002 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9567 04:46:24.258421 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9568 04:46:24.261876 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9569 04:46:24.265348 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9570 04:46:24.271724 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9571 04:46:24.275505 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9572 04:46:24.281768 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9573 04:46:24.284944 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9574 04:46:24.291770 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9575 04:46:24.295117 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9576 04:46:24.302049 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9577 04:46:24.305492 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9578 04:46:24.308027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9579 04:46:24.315315 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9580 04:46:24.318305 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9581 04:46:24.325058 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9582 04:46:24.328021 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9583 04:46:24.334737 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9584 04:46:24.337749 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9585 04:46:24.341216 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9586 04:46:24.344247 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9587 04:46:24.351234 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9588 04:46:24.354846 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9589 04:46:24.357912 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9590 04:46:24.364459 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9591 04:46:24.368072 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9592 04:46:24.374539 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9593 04:46:24.377892 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9594 04:46:24.380968 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9595 04:46:24.387727 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9596 04:46:24.390704 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9597 04:46:24.397373 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9598 04:46:24.400778 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9599 04:46:24.404176 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9600 04:46:24.410905 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9601 04:46:24.414168 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9602 04:46:24.420812 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9603 04:46:24.424193 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9604 04:46:24.427602 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9605 04:46:24.433938 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9606 04:46:24.437920 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9607 04:46:24.440827 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9608 04:46:24.443825 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9609 04:46:24.450707 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9610 04:46:24.453994 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9611 04:46:24.457247 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9612 04:46:24.464664 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9613 04:46:24.467493 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9614 04:46:24.470168 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9615 04:46:24.476966 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9616 04:46:24.480585 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9617 04:46:24.486715 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9618 04:46:24.490655 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9619 04:46:24.493597 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9620 04:46:24.500174 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9621 04:46:24.503396 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9622 04:46:24.509985 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9623 04:46:24.513308 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9624 04:46:24.516957 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9625 04:46:24.523826 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9626 04:46:24.527102 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9627 04:46:24.530306 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9628 04:46:24.537157 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9629 04:46:24.539986 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9630 04:46:24.546954 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9631 04:46:24.550131 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9632 04:46:24.553731 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9633 04:46:24.559933 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9634 04:46:24.563479 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9635 04:46:24.569592 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9636 04:46:24.573371 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9637 04:46:24.576575 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9638 04:46:24.583463 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9639 04:46:24.587421 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9640 04:46:24.593276 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9641 04:46:24.597146 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9642 04:46:24.600195 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9643 04:46:24.606535 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9644 04:46:24.609616 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9645 04:46:24.616890 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9646 04:46:24.619413 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9647 04:46:24.623104 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9648 04:46:24.629671 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9649 04:46:24.632611 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9650 04:46:24.639946 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9651 04:46:24.642944 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9652 04:46:24.646158 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9653 04:46:24.652817 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9654 04:46:24.656387 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9655 04:46:24.663053 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9656 04:46:24.665771 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9657 04:46:24.669242 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9658 04:46:24.675996 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9659 04:46:24.678932 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9660 04:46:24.682413 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9661 04:46:24.689210 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9662 04:46:24.692381 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9663 04:46:24.699445 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9664 04:46:24.702630 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9665 04:46:24.705682 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9666 04:46:24.712065 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9667 04:46:24.715435 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9668 04:46:24.722682 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9669 04:46:24.725634 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9670 04:46:24.728963 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9671 04:46:24.735134 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9672 04:46:24.738941 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9673 04:46:24.745461 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9674 04:46:24.748766 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9675 04:46:24.751988 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9676 04:46:24.758300 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9677 04:46:24.761971 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9678 04:46:24.768167 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9679 04:46:24.771728 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9680 04:46:24.778273 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9681 04:46:24.781271 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9682 04:46:24.784653 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9683 04:46:24.791343 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9684 04:46:24.795024 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9685 04:46:24.801063 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9686 04:46:24.804408 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9687 04:46:24.810875 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9688 04:46:24.814446 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9689 04:46:24.818190 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9690 04:46:24.824189 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9691 04:46:24.827985 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9692 04:46:24.834295 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9693 04:46:24.837240 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9694 04:46:24.844180 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9695 04:46:24.847444 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9696 04:46:24.850791 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9697 04:46:24.857417 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9698 04:46:24.860533 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9699 04:46:24.867110 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9700 04:46:24.870408 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9701 04:46:24.877056 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9702 04:46:24.879916 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9703 04:46:24.883807 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9704 04:46:24.890110 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9705 04:46:24.893409 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9706 04:46:24.899827 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9707 04:46:24.903447 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9708 04:46:24.909635 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9709 04:46:24.913287 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9710 04:46:24.916663 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9711 04:46:24.923156 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9712 04:46:24.926267 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9713 04:46:24.933025 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9714 04:46:24.936408 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9715 04:46:24.943008 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9716 04:46:24.946048 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9717 04:46:24.949599 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9718 04:46:24.952767 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9719 04:46:24.958972 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9720 04:46:24.962636 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9721 04:46:24.965877 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9722 04:46:24.972314 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9723 04:46:24.975778 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9724 04:46:24.979043 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9725 04:46:24.985687 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9726 04:46:24.988567 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9727 04:46:24.992232 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9728 04:46:24.998800 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9729 04:46:25.001533 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9730 04:46:25.008564 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9731 04:46:25.011468 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9732 04:46:25.015025 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9733 04:46:25.021549 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9734 04:46:25.025087 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9735 04:46:25.031526 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9736 04:46:25.034534 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9737 04:46:25.038325 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9738 04:46:25.044915 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9739 04:46:25.047874 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9740 04:46:25.054474 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9741 04:46:25.057923 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9742 04:46:25.061145 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9743 04:46:25.067519 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9744 04:46:25.071305 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9745 04:46:25.074185 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9746 04:46:25.080673 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9747 04:46:25.084160 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9748 04:46:25.087477 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9749 04:46:25.094068 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9750 04:46:25.097780 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9751 04:46:25.100556 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9752 04:46:25.107271 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9753 04:46:25.110669 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9754 04:46:25.117406 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9755 04:46:25.120091 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9756 04:46:25.124045 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9757 04:46:25.130900 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9758 04:46:25.133533 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9759 04:46:25.136727 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9760 04:46:25.140242 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9761 04:46:25.143597 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9762 04:46:25.149790 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9763 04:46:25.153488 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9764 04:46:25.157099 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9765 04:46:25.163344 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9766 04:46:25.166661 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9767 04:46:25.169790 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9768 04:46:25.172875 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9769 04:46:25.179922 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9770 04:46:25.183027 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9771 04:46:25.189764 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9772 04:46:25.192563 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9773 04:46:25.196209 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9774 04:46:25.203462 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9775 04:46:25.205694 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9776 04:46:25.212644 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9777 04:46:25.216121 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9778 04:46:25.222440 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9779 04:46:25.225702 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9780 04:46:25.229774 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9781 04:46:25.235567 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9782 04:46:25.239251 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9783 04:46:25.245691 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9784 04:46:25.249047 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9785 04:46:25.252033 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9786 04:46:25.258912 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9787 04:46:25.262278 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9788 04:46:25.268617 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9789 04:46:25.272150 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9790 04:46:25.278623 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9791 04:46:25.281549 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9792 04:46:25.285269 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9793 04:46:25.291907 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9794 04:46:25.294642 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9795 04:46:25.301578 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9796 04:46:25.304815 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9797 04:46:25.311191 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9798 04:46:25.314561 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9799 04:46:25.317955 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9800 04:46:25.325224 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9801 04:46:25.327995 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9802 04:46:25.335009 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9803 04:46:25.337800 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9804 04:46:25.341453 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9805 04:46:25.348043 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9806 04:46:25.351126 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9807 04:46:25.357409 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9808 04:46:25.360827 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9809 04:46:25.364012 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9810 04:46:25.370638 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9811 04:46:25.373672 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9812 04:46:25.380959 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9813 04:46:25.383511 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9814 04:46:25.390651 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9815 04:46:25.394264 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9816 04:46:25.400670 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9817 04:46:25.403653 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9818 04:46:25.407170 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9819 04:46:25.413762 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9820 04:46:25.416940 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9821 04:46:25.423296 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9822 04:46:25.426585 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9823 04:46:25.430239 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9824 04:46:25.436750 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9825 04:46:25.439559 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9826 04:46:25.446508 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9827 04:46:25.449962 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9828 04:46:25.456738 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9829 04:46:25.459929 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9830 04:46:25.462903 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9831 04:46:25.469284 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9832 04:46:25.472530 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9833 04:46:25.479585 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9834 04:46:25.482305 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9835 04:46:25.485651 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9836 04:46:25.492553 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9837 04:46:25.495608 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9838 04:46:25.502881 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9839 04:46:25.505593 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9840 04:46:25.512698 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9841 04:46:25.515832 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9842 04:46:25.519152 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9843 04:46:25.525023 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9844 04:46:25.528345 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9845 04:46:25.535083 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9846 04:46:25.538160 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9847 04:46:25.544929 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9848 04:46:25.548609 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9849 04:46:25.552004 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9850 04:46:25.557960 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9851 04:46:25.561870 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9852 04:46:25.568416 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9853 04:46:25.571663 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9854 04:46:25.577757 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9855 04:46:25.581077 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9856 04:46:25.588262 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9857 04:46:25.590995 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9858 04:46:25.597979 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9859 04:46:25.601415 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9860 04:46:25.604410 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9861 04:46:25.610825 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9862 04:46:25.614530 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9863 04:46:25.621597 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9864 04:46:25.624460 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9865 04:46:25.630654 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9866 04:46:25.634476 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9867 04:46:25.640725 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9868 04:46:25.644446 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9869 04:46:25.647841 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9870 04:46:25.654199 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9871 04:46:25.657131 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9872 04:46:25.664641 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9873 04:46:25.667244 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9874 04:46:25.674189 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9875 04:46:25.676862 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9876 04:46:25.683507 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9877 04:46:25.686850 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9878 04:46:25.690651 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9879 04:46:25.696912 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9880 04:46:25.700395 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9881 04:46:25.706647 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9882 04:46:25.710404 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9883 04:46:25.716635 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9884 04:46:25.720125 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9885 04:46:25.726506 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9886 04:46:25.729917 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9887 04:46:25.733568 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9888 04:46:25.739753 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9889 04:46:25.742746 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9890 04:46:25.749363 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9891 04:46:25.752420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9892 04:46:25.760620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9893 04:46:25.762569 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9894 04:46:25.766049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9895 04:46:25.773267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9896 04:46:25.775730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9897 04:46:25.782235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9898 04:46:25.785794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9899 04:46:25.792500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9900 04:46:25.795299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9901 04:46:25.801851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9902 04:46:25.805078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9903 04:46:25.812072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9904 04:46:25.815428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9905 04:46:25.821895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9906 04:46:25.825578 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9907 04:46:25.831839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9908 04:46:25.835266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9909 04:46:25.841964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9910 04:46:25.845061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9911 04:46:25.851735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9912 04:46:25.855146 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9913 04:46:25.862024 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9914 04:46:25.864524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9915 04:46:25.871411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9916 04:46:25.874978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9917 04:46:25.881310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9918 04:46:25.887906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9919 04:46:25.891656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9920 04:46:25.897527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9921 04:46:25.901430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9922 04:46:25.904917 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9923 04:46:25.907743 INFO: [APUAPC] vio 0
9924 04:46:25.911470 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9925 04:46:25.917911 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9926 04:46:25.921821 INFO: [APUAPC] D0_APC_0: 0x400510
9927 04:46:25.924638 INFO: [APUAPC] D0_APC_1: 0x0
9928 04:46:25.928075 INFO: [APUAPC] D0_APC_2: 0x1540
9929 04:46:25.928732 INFO: [APUAPC] D0_APC_3: 0x0
9930 04:46:25.931150 INFO: [APUAPC] D1_APC_0: 0xffffffff
9931 04:46:25.937771 INFO: [APUAPC] D1_APC_1: 0xffffffff
9932 04:46:25.938326 INFO: [APUAPC] D1_APC_2: 0x3fffff
9933 04:46:25.940906 INFO: [APUAPC] D1_APC_3: 0x0
9934 04:46:25.944687 INFO: [APUAPC] D2_APC_0: 0xffffffff
9935 04:46:25.947741 INFO: [APUAPC] D2_APC_1: 0xffffffff
9936 04:46:25.951024 INFO: [APUAPC] D2_APC_2: 0x3fffff
9937 04:46:25.954256 INFO: [APUAPC] D2_APC_3: 0x0
9938 04:46:25.957815 INFO: [APUAPC] D3_APC_0: 0xffffffff
9939 04:46:25.960788 INFO: [APUAPC] D3_APC_1: 0xffffffff
9940 04:46:25.964530 INFO: [APUAPC] D3_APC_2: 0x3fffff
9941 04:46:25.968131 INFO: [APUAPC] D3_APC_3: 0x0
9942 04:46:25.970671 INFO: [APUAPC] D4_APC_0: 0xffffffff
9943 04:46:25.974445 INFO: [APUAPC] D4_APC_1: 0xffffffff
9944 04:46:25.977582 INFO: [APUAPC] D4_APC_2: 0x3fffff
9945 04:46:25.980703 INFO: [APUAPC] D4_APC_3: 0x0
9946 04:46:25.983646 INFO: [APUAPC] D5_APC_0: 0xffffffff
9947 04:46:25.986994 INFO: [APUAPC] D5_APC_1: 0xffffffff
9948 04:46:25.990434 INFO: [APUAPC] D5_APC_2: 0x3fffff
9949 04:46:25.993802 INFO: [APUAPC] D5_APC_3: 0x0
9950 04:46:25.997672 INFO: [APUAPC] D6_APC_0: 0xffffffff
9951 04:46:26.000146 INFO: [APUAPC] D6_APC_1: 0xffffffff
9952 04:46:26.004313 INFO: [APUAPC] D6_APC_2: 0x3fffff
9953 04:46:26.007096 INFO: [APUAPC] D6_APC_3: 0x0
9954 04:46:26.010544 INFO: [APUAPC] D7_APC_0: 0xffffffff
9955 04:46:26.013784 INFO: [APUAPC] D7_APC_1: 0xffffffff
9956 04:46:26.016943 INFO: [APUAPC] D7_APC_2: 0x3fffff
9957 04:46:26.020203 INFO: [APUAPC] D7_APC_3: 0x0
9958 04:46:26.023551 INFO: [APUAPC] D8_APC_0: 0xffffffff
9959 04:46:26.027024 INFO: [APUAPC] D8_APC_1: 0xffffffff
9960 04:46:26.030774 INFO: [APUAPC] D8_APC_2: 0x3fffff
9961 04:46:26.033654 INFO: [APUAPC] D8_APC_3: 0x0
9962 04:46:26.036750 INFO: [APUAPC] D9_APC_0: 0xffffffff
9963 04:46:26.040352 INFO: [APUAPC] D9_APC_1: 0xffffffff
9964 04:46:26.043334 INFO: [APUAPC] D9_APC_2: 0x3fffff
9965 04:46:26.046791 INFO: [APUAPC] D9_APC_3: 0x0
9966 04:46:26.050447 INFO: [APUAPC] D10_APC_0: 0xffffffff
9967 04:46:26.052983 INFO: [APUAPC] D10_APC_1: 0xffffffff
9968 04:46:26.056275 INFO: [APUAPC] D10_APC_2: 0x3fffff
9969 04:46:26.059453 INFO: [APUAPC] D10_APC_3: 0x0
9970 04:46:26.063096 INFO: [APUAPC] D11_APC_0: 0xffffffff
9971 04:46:26.066745 INFO: [APUAPC] D11_APC_1: 0xffffffff
9972 04:46:26.069367 INFO: [APUAPC] D11_APC_2: 0x3fffff
9973 04:46:26.073251 INFO: [APUAPC] D11_APC_3: 0x0
9974 04:46:26.075790 INFO: [APUAPC] D12_APC_0: 0xffffffff
9975 04:46:26.079328 INFO: [APUAPC] D12_APC_1: 0xffffffff
9976 04:46:26.082303 INFO: [APUAPC] D12_APC_2: 0x3fffff
9977 04:46:26.086134 INFO: [APUAPC] D12_APC_3: 0x0
9978 04:46:26.089232 INFO: [APUAPC] D13_APC_0: 0xffffffff
9979 04:46:26.092660 INFO: [APUAPC] D13_APC_1: 0xffffffff
9980 04:46:26.095953 INFO: [APUAPC] D13_APC_2: 0x3fffff
9981 04:46:26.099215 INFO: [APUAPC] D13_APC_3: 0x0
9982 04:46:26.102908 INFO: [APUAPC] D14_APC_0: 0xffffffff
9983 04:46:26.106260 INFO: [APUAPC] D14_APC_1: 0xffffffff
9984 04:46:26.109585 INFO: [APUAPC] D14_APC_2: 0x3fffff
9985 04:46:26.112490 INFO: [APUAPC] D14_APC_3: 0x0
9986 04:46:26.116054 INFO: [APUAPC] D15_APC_0: 0xffffffff
9987 04:46:26.119107 INFO: [APUAPC] D15_APC_1: 0xffffffff
9988 04:46:26.122910 INFO: [APUAPC] D15_APC_2: 0x3fffff
9989 04:46:26.126179 INFO: [APUAPC] D15_APC_3: 0x0
9990 04:46:26.129196 INFO: [APUAPC] APC_CON: 0x4
9991 04:46:26.133177 INFO: [NOCDAPC] D0_APC_0: 0x0
9992 04:46:26.136026 INFO: [NOCDAPC] D0_APC_1: 0x0
9993 04:46:26.138807 INFO: [NOCDAPC] D1_APC_0: 0x0
9994 04:46:26.142234 INFO: [NOCDAPC] D1_APC_1: 0xfff
9995 04:46:26.145385 INFO: [NOCDAPC] D2_APC_0: 0x0
9996 04:46:26.145836 INFO: [NOCDAPC] D2_APC_1: 0xfff
9997 04:46:26.148800 INFO: [NOCDAPC] D3_APC_0: 0x0
9998 04:46:26.152244 INFO: [NOCDAPC] D3_APC_1: 0xfff
9999 04:46:26.155532 INFO: [NOCDAPC] D4_APC_0: 0x0
10000 04:46:26.159057 INFO: [NOCDAPC] D4_APC_1: 0xfff
10001 04:46:26.162196 INFO: [NOCDAPC] D5_APC_0: 0x0
10002 04:46:26.165883 INFO: [NOCDAPC] D5_APC_1: 0xfff
10003 04:46:26.168861 INFO: [NOCDAPC] D6_APC_0: 0x0
10004 04:46:26.171950 INFO: [NOCDAPC] D6_APC_1: 0xfff
10005 04:46:26.175222 INFO: [NOCDAPC] D7_APC_0: 0x0
10006 04:46:26.178727 INFO: [NOCDAPC] D7_APC_1: 0xfff
10007 04:46:26.181529 INFO: [NOCDAPC] D8_APC_0: 0x0
10008 04:46:26.181968 INFO: [NOCDAPC] D8_APC_1: 0xfff
10009 04:46:26.185087 INFO: [NOCDAPC] D9_APC_0: 0x0
10010 04:46:26.188086 INFO: [NOCDAPC] D9_APC_1: 0xfff
10011 04:46:26.191641 INFO: [NOCDAPC] D10_APC_0: 0x0
10012 04:46:26.194739 INFO: [NOCDAPC] D10_APC_1: 0xfff
10013 04:46:26.198451 INFO: [NOCDAPC] D11_APC_0: 0x0
10014 04:46:26.202069 INFO: [NOCDAPC] D11_APC_1: 0xfff
10015 04:46:26.204608 INFO: [NOCDAPC] D12_APC_0: 0x0
10016 04:46:26.208922 INFO: [NOCDAPC] D12_APC_1: 0xfff
10017 04:46:26.211478 INFO: [NOCDAPC] D13_APC_0: 0x0
10018 04:46:26.214735 INFO: [NOCDAPC] D13_APC_1: 0xfff
10019 04:46:26.218218 INFO: [NOCDAPC] D14_APC_0: 0x0
10020 04:46:26.221454 INFO: [NOCDAPC] D14_APC_1: 0xfff
10021 04:46:26.225079 INFO: [NOCDAPC] D15_APC_0: 0x0
10022 04:46:26.227903 INFO: [NOCDAPC] D15_APC_1: 0xfff
10023 04:46:26.228455 INFO: [NOCDAPC] APC_CON: 0x4
10024 04:46:26.231389 INFO: [APUAPC] set_apusys_apc done
10025 04:46:26.234814 INFO: [DEVAPC] devapc_init done
10026 04:46:26.241252 INFO: GICv3 without legacy support detected.
10027 04:46:26.244712 INFO: ARM GICv3 driver initialized in EL3
10028 04:46:26.247983 INFO: Maximum SPI INTID supported: 639
10029 04:46:26.251198 INFO: BL31: Initializing runtime services
10030 04:46:26.257554 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10031 04:46:26.260807 INFO: SPM: enable CPC mode
10032 04:46:26.264467 INFO: mcdi ready for mcusys-off-idle and system suspend
10033 04:46:26.270690 INFO: BL31: Preparing for EL3 exit to normal world
10034 04:46:26.274235 INFO: Entry point address = 0x80000000
10035 04:46:26.277470 INFO: SPSR = 0x8
10036 04:46:26.281507
10037 04:46:26.281922
10038 04:46:26.282319
10039 04:46:26.284715 Starting depthcharge on Spherion...
10040 04:46:26.285285
10041 04:46:26.285632 Wipe memory regions:
10042 04:46:26.285945
10043 04:46:26.288482 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10044 04:46:26.288979 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10045 04:46:26.289382 Setting prompt string to ['asurada:']
10046 04:46:26.289789 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10047 04:46:26.290448 [0x00000040000000, 0x00000054600000)
10048 04:46:26.410455
10049 04:46:26.411063 [0x00000054660000, 0x00000080000000)
10050 04:46:26.670360
10051 04:46:26.670903 [0x000000821a7280, 0x000000ffe64000)
10052 04:46:27.414965
10053 04:46:27.415571 [0x00000100000000, 0x00000240000000)
10054 04:46:29.303586
10055 04:46:29.306227 Initializing XHCI USB controller at 0x11200000.
10056 04:46:30.344172
10057 04:46:30.347628 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10058 04:46:30.348120
10059 04:46:30.348490
10060 04:46:30.348831
10061 04:46:30.349684 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 04:46:30.451103 asurada: tftpboot 192.168.201.1 12699825/tftp-deploy-qo_ublru/kernel/image.itb 12699825/tftp-deploy-qo_ublru/kernel/cmdline
10064 04:46:30.451822 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10065 04:46:30.452386 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10066 04:46:30.456945 tftpboot 192.168.201.1 12699825/tftp-deploy-qo_ublru/kernel/image.ittp-deploy-qo_ublru/kernel/cmdline
10067 04:46:30.457617
10068 04:46:30.458035 Waiting for link
10069 04:46:30.617474
10070 04:46:30.617986 R8152: Initializing
10071 04:46:30.618326
10072 04:46:30.620153 Version 6 (ocp_data = 5c30)
10073 04:46:30.620579
10074 04:46:30.623568 R8152: Done initializing
10075 04:46:30.623987
10076 04:46:30.624320 Adding net device
10077 04:46:32.601312
10078 04:46:32.601831 done.
10079 04:46:32.602169
10080 04:46:32.602478 MAC: 00:24:32:30:7c:7b
10081 04:46:32.602775
10082 04:46:32.604366 Sending DHCP discover... done.
10083 04:46:32.604788
10084 04:46:35.849838 Waiting for reply... done.
10085 04:46:35.850413
10086 04:46:35.850796 Sending DHCP request... done.
10087 04:46:35.852785
10088 04:46:35.858731 Waiting for reply... done.
10089 04:46:35.859291
10090 04:46:35.859707 My ip is 192.168.201.14
10091 04:46:35.860050
10092 04:46:35.861523 The DHCP server ip is 192.168.201.1
10093 04:46:35.861986
10094 04:46:35.868079 TFTP server IP predefined by user: 192.168.201.1
10095 04:46:35.868553
10096 04:46:35.874543 Bootfile predefined by user: 12699825/tftp-deploy-qo_ublru/kernel/image.itb
10097 04:46:35.875065
10098 04:46:35.877743 Sending tftp read request... done.
10099 04:46:35.878162
10100 04:46:35.884607 Waiting for the transfer...
10101 04:46:35.885056
10102 04:46:36.594689 00000000 ################################################################
10103 04:46:36.595197
10104 04:46:37.310665 00080000 ################################################################
10105 04:46:37.311213
10106 04:46:38.036231 00100000 ################################################################
10107 04:46:38.036773
10108 04:46:38.759241 00180000 ################################################################
10109 04:46:38.759843
10110 04:46:39.470952 00200000 ################################################################
10111 04:46:39.471540
10112 04:46:40.192667 00280000 ################################################################
10113 04:46:40.193197
10114 04:46:40.911169 00300000 ################################################################
10115 04:46:40.911733
10116 04:46:41.637487 00380000 ################################################################
10117 04:46:41.638011
10118 04:46:42.334353 00400000 ################################################################
10119 04:46:42.334859
10120 04:46:43.014614 00480000 ################################################################
10121 04:46:43.014764
10122 04:46:43.725124 00500000 ################################################################
10123 04:46:43.725655
10124 04:46:44.441698 00580000 ################################################################
10125 04:46:44.442225
10126 04:46:45.146430 00600000 ################################################################
10127 04:46:45.147021
10128 04:46:45.859266 00680000 ################################################################
10129 04:46:45.859822
10130 04:46:46.561316 00700000 ################################################################
10131 04:46:46.561875
10132 04:46:47.281464 00780000 ################################################################
10133 04:46:47.281987
10134 04:46:47.990191 00800000 ################################################################
10135 04:46:47.990366
10136 04:46:48.674982 00880000 ################################################################
10137 04:46:48.675560
10138 04:46:49.389556 00900000 ################################################################
10139 04:46:49.390079
10140 04:46:50.078488 00980000 ################################################################
10141 04:46:50.079107
10142 04:46:50.797757 00a00000 ################################################################
10143 04:46:50.798277
10144 04:46:51.515281 00a80000 ################################################################
10145 04:46:51.515854
10146 04:46:52.223120 00b00000 ################################################################
10147 04:46:52.223672
10148 04:46:52.951862 00b80000 ################################################################
10149 04:46:52.952369
10150 04:46:53.672610 00c00000 ################################################################
10151 04:46:53.673160
10152 04:46:54.382183 00c80000 ################################################################
10153 04:46:54.382748
10154 04:46:55.093447 00d00000 ################################################################
10155 04:46:55.093970
10156 04:46:55.799393 00d80000 ################################################################
10157 04:46:55.799911
10158 04:46:56.493379 00e00000 ################################################################
10159 04:46:56.493887
10160 04:46:57.206924 00e80000 ################################################################
10161 04:46:57.207476
10162 04:46:57.916035 00f00000 ################################################################
10163 04:46:57.916548
10164 04:46:58.620126 00f80000 ################################################################
10165 04:46:58.620675
10166 04:46:59.333232 01000000 ################################################################
10167 04:46:59.333786
10168 04:47:00.012453 01080000 ################################################################
10169 04:47:00.012966
10170 04:47:00.717045 01100000 ################################################################
10171 04:47:00.717571
10172 04:47:01.409483 01180000 ################################################################
10173 04:47:01.410009
10174 04:47:02.110557 01200000 ################################################################
10175 04:47:02.111065
10176 04:47:02.816816 01280000 ################################################################
10177 04:47:02.817510
10178 04:47:03.518065 01300000 ################################################################
10179 04:47:03.518610
10180 04:47:04.227196 01380000 ################################################################
10181 04:47:04.227804
10182 04:47:04.949399 01400000 ################################################################
10183 04:47:04.950146
10184 04:47:05.661403 01480000 ################################################################
10185 04:47:05.661924
10186 04:47:06.373298 01500000 ################################################################
10187 04:47:06.373834
10188 04:47:07.086068 01580000 ################################################################
10189 04:47:07.086718
10190 04:47:07.799181 01600000 ################################################################
10191 04:47:07.799764
10192 04:47:08.502083 01680000 ################################################################
10193 04:47:08.502645
10194 04:47:09.211171 01700000 ################################################################
10195 04:47:09.211736
10196 04:47:09.910416 01780000 ################################################################
10197 04:47:09.911085
10198 04:47:10.612243 01800000 ################################################################
10199 04:47:10.612837
10200 04:47:11.341444 01880000 ################################################################
10201 04:47:11.342017
10202 04:47:12.052505 01900000 ################################################################
10203 04:47:12.053050
10204 04:47:12.774624 01980000 ################################################################
10205 04:47:12.775174
10206 04:47:13.493194 01a00000 ################################################################
10207 04:47:13.493732
10208 04:47:14.205352 01a80000 ################################################################
10209 04:47:14.205515
10210 04:47:14.904371 01b00000 ################################################################
10211 04:47:14.904903
10212 04:47:15.616368 01b80000 ################################################################
10213 04:47:15.616892
10214 04:47:16.327640 01c00000 ################################################################
10215 04:47:16.328161
10216 04:47:16.339833 01c80000 ## done.
10217 04:47:16.340259
10218 04:47:16.343119 The bootfile was 29894022 bytes long.
10219 04:47:16.343586
10220 04:47:16.345998 Sending tftp read request... done.
10221 04:47:16.346417
10222 04:47:16.349434 Waiting for the transfer...
10223 04:47:16.349937
10224 04:47:16.353130 00000000 # done.
10225 04:47:16.353687
10226 04:47:16.359312 Command line loaded dynamically from TFTP file: 12699825/tftp-deploy-qo_ublru/kernel/cmdline
10227 04:47:16.359782
10228 04:47:16.382491 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12699825/extract-nfsrootfs-wnf_mrip,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10229 04:47:16.383030
10230 04:47:16.383464 Loading FIT.
10231 04:47:16.383808
10232 04:47:16.386431 Image ramdisk-1 has 17796204 bytes.
10233 04:47:16.386959
10234 04:47:16.388895 Image fdt-1 has 47278 bytes.
10235 04:47:16.389316
10236 04:47:16.392389 Image kernel-1 has 12048508 bytes.
10237 04:47:16.392811
10238 04:47:16.402408 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10239 04:47:16.402939
10240 04:47:16.418698 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10241 04:47:16.419142
10242 04:47:16.425316 Choosing best match conf-1 for compat google,spherion-rev2.
10243 04:47:16.425739
10244 04:47:16.428511 Connected to device vid:did:rid of 1ae0:0028:00
10245 04:47:16.440776
10246 04:47:16.443813 tpm_get_response: command 0x17b, return code 0x0
10247 04:47:16.444240
10248 04:47:16.447210 ec_init: CrosEC protocol v3 supported (256, 248)
10249 04:47:16.452432
10250 04:47:16.455886 tpm_cleanup: add release locality here.
10251 04:47:16.456343
10252 04:47:16.456682 Shutting down all USB controllers.
10253 04:47:16.459410
10254 04:47:16.459975 Removing current net device
10255 04:47:16.460346
10256 04:47:16.465576 Exiting depthcharge with code 4 at timestamp: 79385281
10257 04:47:16.466105
10258 04:47:16.468747 LZMA decompressing kernel-1 to 0x821a6718
10259 04:47:16.469169
10260 04:47:16.471933 LZMA decompressing kernel-1 to 0x40000000
10261 04:47:17.971238
10262 04:47:17.971860 jumping to kernel
10263 04:47:17.973586 end: 2.2.4 bootloader-commands (duration 00:00:52) [common]
10264 04:47:17.974128 start: 2.2.5 auto-login-action (timeout 00:03:34) [common]
10265 04:47:17.974546 Setting prompt string to ['Linux version [0-9]']
10266 04:47:17.974929 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10267 04:47:17.975319 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10268 04:47:18.054384
10269 04:47:18.057754 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10270 04:47:18.061571 start: 2.2.5.1 login-action (timeout 00:03:34) [common]
10271 04:47:18.062045 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10272 04:47:18.062409 Setting prompt string to []
10273 04:47:18.062791 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10274 04:47:18.063143 Using line separator: #'\n'#
10275 04:47:18.063502 No login prompt set.
10276 04:47:18.063831 Parsing kernel messages
10277 04:47:18.064119 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10278 04:47:18.064620 [login-action] Waiting for messages, (timeout 00:03:34)
10279 04:47:18.080520 [ 0.000000] Linux version 6.1.75-cip14-rt8 (KernelCI@build-j97480-arm64-gcc-10-defconfig-arm64-chromebook-6n26j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024
10280 04:47:18.083762 [ 0.000000] random: crng init done
10281 04:47:18.090096 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10282 04:47:18.094315 [ 0.000000] efi: UEFI not found.
10283 04:47:18.100267 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10284 04:47:18.110480 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10285 04:47:18.120116 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10286 04:47:18.126866 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10287 04:47:18.133804 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10288 04:47:18.139965 [ 0.000000] printk: bootconsole [mtk8250] enabled
10289 04:47:18.146352 [ 0.000000] NUMA: No NUMA configuration found
10290 04:47:18.153088 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10291 04:47:18.159487 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10292 04:47:18.160032 [ 0.000000] Zone ranges:
10293 04:47:18.166467 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10294 04:47:18.169913 [ 0.000000] DMA32 empty
10295 04:47:18.176331 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10296 04:47:18.179422 [ 0.000000] Movable zone start for each node
10297 04:47:18.182622 [ 0.000000] Early memory node ranges
10298 04:47:18.189281 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10299 04:47:18.196051 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10300 04:47:18.202661 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10301 04:47:18.209198 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10302 04:47:18.216269 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10303 04:47:18.222507 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10304 04:47:18.278564 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10305 04:47:18.284922 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10306 04:47:18.291803 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10307 04:47:18.295021 [ 0.000000] psci: probing for conduit method from DT.
10308 04:47:18.301248 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10309 04:47:18.304826 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10310 04:47:18.311497 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10311 04:47:18.314712 [ 0.000000] psci: SMC Calling Convention v1.2
10312 04:47:18.321343 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10313 04:47:18.325115 [ 0.000000] Detected VIPT I-cache on CPU0
10314 04:47:18.331881 [ 0.000000] CPU features: detected: GIC system register CPU interface
10315 04:47:18.338281 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10316 04:47:18.344049 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10317 04:47:18.350962 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10318 04:47:18.360722 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10319 04:47:18.367143 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10320 04:47:18.370414 [ 0.000000] alternatives: applying boot alternatives
10321 04:47:18.377433 [ 0.000000] Fallback order for Node 0: 0
10322 04:47:18.383980 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10323 04:47:18.387518 [ 0.000000] Policy zone: Normal
10324 04:47:18.410496 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12699825/extract-nfsrootfs-wnf_mrip,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10325 04:47:18.420272 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10326 04:47:18.431307 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10327 04:47:18.440869 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10328 04:47:18.447171 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10329 04:47:18.451158 <6>[ 0.000000] software IO TLB: area num 8.
10330 04:47:18.507337 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10331 04:47:18.656123 <6>[ 0.000000] Memory: 7949808K/8385536K available (18048K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 616K bss, 402960K reserved, 32768K cma-reserved)
10332 04:47:18.663535 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10333 04:47:18.669691 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10334 04:47:18.673585 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10335 04:47:18.679312 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10336 04:47:18.685973 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10337 04:47:18.689174 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10338 04:47:18.699347 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10339 04:47:18.706149 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10340 04:47:18.712381 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10341 04:47:18.719146 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10342 04:47:18.722514 <6>[ 0.000000] GICv3: 608 SPIs implemented
10343 04:47:18.725462 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10344 04:47:18.732197 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10345 04:47:18.735803 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10346 04:47:18.741959 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10347 04:47:18.755549 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10348 04:47:18.768793 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10349 04:47:18.774974 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10350 04:47:18.783068 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10351 04:47:18.796249 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10352 04:47:18.803059 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10353 04:47:18.810008 <6>[ 0.009236] Console: colour dummy device 80x25
10354 04:47:18.819869 <6>[ 0.013973] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10355 04:47:18.826640 <6>[ 0.024415] pid_max: default: 32768 minimum: 301
10356 04:47:18.829559 <6>[ 0.029287] LSM: Security Framework initializing
10357 04:47:18.835880 <6>[ 0.034255] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10358 04:47:18.845768 <6>[ 0.042069] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10359 04:47:18.855641 <6>[ 0.051477] cblist_init_generic: Setting adjustable number of callback queues.
10360 04:47:18.862684 <6>[ 0.058921] cblist_init_generic: Setting shift to 3 and lim to 1.
10361 04:47:18.869050 <6>[ 0.065259] cblist_init_generic: Setting adjustable number of callback queues.
10362 04:47:18.875430 <6>[ 0.072687] cblist_init_generic: Setting shift to 3 and lim to 1.
10363 04:47:18.878641 <6>[ 0.079126] rcu: Hierarchical SRCU implementation.
10364 04:47:18.885571 <6>[ 0.079128] rcu: Max phase no-delay instances is 1000.
10365 04:47:18.892208 <6>[ 0.079152] printk: bootconsole [mtk8250] printing thread started
10366 04:47:18.899204 <6>[ 0.097474] EFI services will not be available.
10367 04:47:18.902559 <6>[ 0.097667] smp: Bringing up secondary CPUs ...
10368 04:47:18.908148 <6>[ 0.097945] Detected VIPT I-cache on CPU1
10369 04:47:18.915158 <6>[ 0.098000] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10370 04:47:18.921770 <6>[ 0.098024] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10371 04:47:18.931762 <6>[ 0.125920] Detected VIPT I-cache on CPU2
10372 04:47:18.937964 <6>[ 0.125966] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10373 04:47:18.948091 <6>[ 0.125981] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10374 04:47:18.951540 <6>[ 0.126234] Detected VIPT I-cache on CPU3
10375 04:47:18.958584 <6>[ 0.126280] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10376 04:47:18.964084 <6>[ 0.126294] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10377 04:47:18.967709 <6>[ 0.126602] CPU features: detected: Spectre-v4
10378 04:47:18.973904 <6>[ 0.126610] CPU features: detected: Spectre-BHB
10379 04:47:18.977818 <6>[ 0.126615] Detected PIPT I-cache on CPU4
10380 04:47:18.983867 <6>[ 0.126672] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10381 04:47:18.990937 <6>[ 0.126688] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10382 04:47:18.996960 <6>[ 0.126984] Detected PIPT I-cache on CPU5
10383 04:47:19.003870 <6>[ 0.127045] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10384 04:47:19.010361 <6>[ 0.127061] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10385 04:47:19.013647 <6>[ 0.127335] Detected PIPT I-cache on CPU6
10386 04:47:19.023757 <6>[ 0.127399] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10387 04:47:19.030192 <6>[ 0.127415] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10388 04:47:19.033538 <6>[ 0.127702] Detected PIPT I-cache on CPU7
10389 04:47:19.040516 <6>[ 0.127766] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10390 04:47:19.046593 <6>[ 0.127782] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10391 04:47:19.053173 <6>[ 0.127828] smp: Brought up 1 node, 8 CPUs
10392 04:47:19.056550 <6>[ 0.127833] SMP: Total of 8 processors activated.
10393 04:47:19.063054 <6>[ 0.127836] CPU features: detected: 32-bit EL0 Support
10394 04:47:19.069861 <6>[ 0.127838] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10395 04:47:19.076109 <6>[ 0.127841] CPU features: detected: Common not Private translations
10396 04:47:19.082726 <6>[ 0.127843] CPU features: detected: CRC32 instructions
10397 04:47:19.089655 <6>[ 0.127845] CPU features: detected: RCpc load-acquire (LDAPR)
10398 04:47:19.095847 <6>[ 0.127847] CPU features: detected: LSE atomic instructions
10399 04:47:19.099251 <6>[ 0.127848] CPU features: detected: Privileged Access Never
10400 04:47:19.105915 <6>[ 0.127850] CPU features: detected: RAS Extension Support
10401 04:47:19.112737 <6>[ 0.127853] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10402 04:47:19.115726 <6>[ 0.127920] CPU: All CPU(s) started at EL2
10403 04:47:19.122276 <6>[ 0.127922] alternatives: applying system-wide alternatives
10404 04:47:19.125465 <6>[ 0.141037] devtmpfs: initialized
10405 04:47:19.158349 �������B�͡�������*��ɥ������Bzɑ�Ɂ�b��ʲ�ѕͥjR�<6>[ 0.355949] <printk: console [ttyS0] printing thread started
10406 04:47:19.161896 6>[ 0.225625] pnp: PnP ACPI: disabled
10407 04:47:19.169880 <6>[ 0.355960] printk: console [ttyS0] enabled
10408 04:47:19.173406 <6>[ 0.355963] printk: bootconsole [mtk8250] disabled
10409 04:47:19.180167 <6>[ 0.365532] printk: bootconsole [mtk8250] printing thread stopped
10410 04:47:19.186262 <6>[ 0.366583] SuperH (H)SCI(F) driver initialized
10411 04:47:19.190250 <6>[ 0.367082] msm_serial: driver initialized
10412 04:47:19.199783 <6>[ 0.371840] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10413 04:47:19.206009 <6>[ 0.371871] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10414 04:47:19.218047 <6>[ 0.371900] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10415 04:47:19.223085 <6>[ 0.371929] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10416 04:47:19.232518 <6>[ 0.371950] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10417 04:47:19.245598 <6>[ 0.371978] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10418 04:47:19.257129 <6>[ 0.372006] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10419 04:47:19.261874 <6>[ 0.372119] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10420 04:47:19.265356 <6>[ 0.372149] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10421 04:47:19.273112 <6>[ 0.382642] loop: module loaded
10422 04:47:19.277828 <6>[ 0.385136] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10423 04:47:19.280813 <4>[ 0.402303] mtk-pmic-keys: Failed to locate of_node [id: -1]
10424 04:47:19.287507 <6>[ 0.403372] megasas: 07.719.03.00-rc1
10425 04:47:19.290634 <6>[ 0.412802] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10426 04:47:19.297398 <6>[ 0.420288] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10427 04:47:19.303837 <6>[ 0.432339] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10428 04:47:19.313955 <6>[ 0.485864] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10429 04:47:19.773375 <6>[ 0.970424] Freeing initrd memory: 17376K
10430 04:47:19.779880 <6>[ 0.976707] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10431 04:47:19.783229 <6>[ 0.981545] tun: Universal TUN/TAP device driver, 1.6
10432 04:47:19.786486 <6>[ 0.982296] thunder_xcv, ver 1.0
10433 04:47:19.789887 <6>[ 0.982313] thunder_bgx, ver 1.0
10434 04:47:19.792998 <6>[ 0.982329] nicpf, ver 1.0
10435 04:47:19.803291 <6>[ 0.983375] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10436 04:47:19.806439 <6>[ 0.983378] hns3: Copyright (c) 2017 Huawei Corporation.
10437 04:47:19.809576 <6>[ 0.983401] hclge is initializing
10438 04:47:19.815942 <6>[ 0.983419] e1000: Intel(R) PRO/1000 Network Driver
10439 04:47:19.823643 <6>[ 0.983420] e1000: Copyright (c) 1999-2006 Intel Corporation.
10440 04:47:19.827023 <6>[ 0.983439] e1000e: Intel(R) PRO/1000 Network Driver
10441 04:47:19.834071 <6>[ 0.983441] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10442 04:47:19.837384 <6>[ 0.983457] igb: Intel(R) Gigabit Ethernet Network Driver
10443 04:47:19.844052 <6>[ 0.983459] igb: Copyright (c) 2007-2014 Intel Corporation.
10444 04:47:19.850529 <6>[ 0.983472] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10445 04:47:19.857937 <6>[ 0.983474] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10446 04:47:19.861704 <6>[ 0.983766] sky2: driver version 1.30
10447 04:47:19.867794 <6>[ 0.984836] VFIO - User Level meta-driver version: 0.3
10448 04:47:19.874392 <6>[ 0.987648] usbcore: registered new interface driver usb-storage
10449 04:47:19.878209 <6>[ 0.987828] usbcore: registered new device driver onboard-usb-hub
10450 04:47:19.884356 <6>[ 0.990601] mt6397-rtc mt6359-rtc: registered as rtc0
10451 04:47:19.895587 <6>[ 0.990754] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-04T04:47:19 UTC (1707022039)
10452 04:47:19.898299 <6>[ 0.991371] i2c_dev: i2c /dev entries driver
10453 04:47:19.908289 <6>[ 0.998510] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10454 04:47:19.911436 <6>[ 1.013490] cpu cpu0: EM: created perf domain
10455 04:47:19.914404 <6>[ 1.013803] cpu cpu4: EM: created perf domain
10456 04:47:19.920947 <6>[ 1.015908] sdhci: Secure Digital Host Controller Interface driver
10457 04:47:19.927270 <6>[ 1.015910] sdhci: Copyright(c) Pierre Ossman
10458 04:47:19.934388 <6>[ 1.016251] Synopsys Designware Multimedia Card Interface Driver
10459 04:47:19.937007 <6>[ 1.016615] sdhci-pltfm: SDHCI platform and OF driver helper
10460 04:47:19.944069 <6>[ 1.020883] ledtrig-cpu: registered to indicate activity on CPUs
10461 04:47:19.947068 <6>[ 1.021540] mmc0: CQHCI version 5.10
10462 04:47:19.954257 <6>[ 1.021583] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10463 04:47:19.960520 <6>[ 1.021856] usbcore: registered new interface driver usbhid
10464 04:47:19.963754 <6>[ 1.021857] usbhid: USB HID core driver
10465 04:47:19.973471 <6>[ 1.021990] spi_master spi0: will run message pump with realtime priority
10466 04:47:19.983600 <6>[ 1.053982] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10467 04:47:19.996869 <6>[ 1.057006] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10468 04:47:20.003622 <6>[ 1.058597] cros-ec-spi spi0.0: Chrome EC device registered
10469 04:47:20.013820 <6>[ 1.072987] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10470 04:47:20.020457 <6>[ 1.074013] NET: Registered PF_PACKET protocol family
10471 04:47:20.023545 <6>[ 1.074096] 9pnet: Installing 9P2000 support
10472 04:47:20.026859 <5>[ 1.074155] Key type dns_resolver registered
10473 04:47:20.033254 <6>[ 1.074647] registered taskstats version 1
10474 04:47:20.036683 <5>[ 1.074661] Loading compiled-in X.509 certificates
10475 04:47:20.046265 <4>[ 1.091547] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10476 04:47:20.059437 <4>[ 1.091787] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10477 04:47:20.066247 <3>[ 1.091807] debugfs: File 'uA_load' in directory '/' already present!
10478 04:47:20.073412 <3>[ 1.091819] debugfs: File 'min_uV' in directory '/' already present!
10479 04:47:20.079685 <3>[ 1.091826] debugfs: File 'max_uV' in directory '/' already present!
10480 04:47:20.085950 <3>[ 1.091833] debugfs: File 'constraint_flags' in directory '/' already present!
10481 04:47:20.092468 <3>[ 1.095574] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10482 04:47:20.099503 <6>[ 1.104831] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10483 04:47:20.106279 <6>[ 1.105406] xhci-mtk 11200000.usb: xHCI Host Controller
10484 04:47:20.112800 <6>[ 1.105423] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10485 04:47:20.122760 <6>[ 1.105662] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10486 04:47:20.129039 <6>[ 1.105709] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10487 04:47:20.135646 <6>[ 1.105810] xhci-mtk 11200000.usb: xHCI Host Controller
10488 04:47:20.142167 <6>[ 1.105819] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10489 04:47:20.148685 <6>[ 1.105827] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10490 04:47:20.152627 <6>[ 1.106304] hub 1-0:1.0: USB hub found
10491 04:47:20.158706 <6>[ 1.106324] hub 1-0:1.0: 1 port detected
10492 04:47:20.165364 <6>[ 1.106537] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10493 04:47:20.168998 <6>[ 1.106922] hub 2-0:1.0: USB hub found
10494 04:47:20.175163 <6>[ 1.106938] hub 2-0:1.0: 1 port detected
10495 04:47:20.179476 <6>[ 1.110539] mtk-msdc 11f70000.mmc: Got CD GPIO
10496 04:47:20.182309 <6>[ 1.120337] mmc0: Command Queue Engine enabled
10497 04:47:20.188359 <6>[ 1.120349] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10498 04:47:20.195335 <6>[ 1.120887] mmcblk0: mmc0:0001 DA4128 116 GiB
10499 04:47:20.201882 <6>[ 1.124259] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10500 04:47:20.206091 <6>[ 1.125622] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10501 04:47:20.212235 <6>[ 1.126356] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10502 04:47:20.218461 <6>[ 1.127105] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10503 04:47:20.225186 <6>[ 1.128685] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10504 04:47:20.235301 <6>[ 1.128691] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10505 04:47:20.241999 <4>[ 1.128844] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10506 04:47:20.251256 <6>[ 1.129533] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10507 04:47:20.258422 <6>[ 1.129539] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10508 04:47:20.264709 <6>[ 1.129733] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10509 04:47:20.274462 <6>[ 1.129754] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10510 04:47:20.281287 <6>[ 1.129758] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10511 04:47:20.291479 <6>[ 1.129763] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10512 04:47:20.301478 <6>[ 1.131295] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10513 04:47:20.307735 <6>[ 1.131316] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10514 04:47:20.317740 <6>[ 1.131322] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10515 04:47:20.323898 <6>[ 1.131329] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10516 04:47:20.334060 <6>[ 1.131335] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10517 04:47:20.340531 <6>[ 1.131342] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10518 04:47:20.350355 <6>[ 1.131349] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10519 04:47:20.357569 <6>[ 1.131356] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10520 04:47:20.367474 <6>[ 1.131362] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10521 04:47:20.374316 <6>[ 1.131369] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10522 04:47:20.383292 <6>[ 1.131375] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10523 04:47:20.390145 <6>[ 1.131382] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10524 04:47:20.399979 <6>[ 1.131388] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10525 04:47:20.407047 <6>[ 1.131395] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10526 04:47:20.416445 <6>[ 1.131401] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10527 04:47:20.423110 <6>[ 1.131981] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10528 04:47:20.429685 <6>[ 1.132930] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10529 04:47:20.436419 <6>[ 1.133670] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10530 04:47:20.442985 <6>[ 1.134446] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10531 04:47:20.449096 <6>[ 1.135191] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10532 04:47:20.459064 <6>[ 1.135408] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10533 04:47:20.465848 <6>[ 1.135424] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10534 04:47:20.475506 <6>[ 1.135430] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10535 04:47:20.485405 <6>[ 1.135436] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10536 04:47:20.495345 <6>[ 1.135442] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10537 04:47:20.505889 <6>[ 1.135447] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10538 04:47:20.515058 <6>[ 1.135453] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10539 04:47:20.522122 <6>[ 1.135458] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10540 04:47:20.532288 <6>[ 1.135463] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10541 04:47:20.541646 <6>[ 1.135470] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10542 04:47:20.552117 <6>[ 1.135475] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10543 04:47:20.561650 <6>[ 1.136053] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10544 04:47:20.568397 <6>[ 1.146152] Trying to probe devices needed for running init ...
10545 04:47:20.574560 <6>[ 1.493724] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10546 04:47:20.578379 <6>[ 1.520228] hub 2-1:1.0: USB hub found
10547 04:47:20.581470 <6>[ 1.520545] hub 2-1:1.0: 3 ports detected
10548 04:47:20.584461 <6>[ 1.522904] hub 2-1:1.0: USB hub found
10549 04:47:20.591309 <6>[ 1.523208] hub 2-1:1.0: 3 ports detected
10550 04:47:20.598070 <6>[ 1.641527] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10551 04:47:20.601648 <6>[ 1.794310] hub 1-1:1.0: USB hub found
10552 04:47:20.604594 <6>[ 1.794630] hub 1-1:1.0: 4 ports detected
10553 04:47:20.611286 <6>[ 1.797615] hub 1-1:1.0: USB hub found
10554 04:47:20.614249 <6>[ 1.797939] hub 1-1:1.0: 4 ports detected
10555 04:47:20.681367 <6>[ 1.873704] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10556 04:47:20.916982 <6>[ 2.109696] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10557 04:47:21.041936 <6>[ 2.237681] hub 1-1.4:1.0: USB hub found
10558 04:47:21.045321 <6>[ 2.238136] hub 1-1.4:1.0: 2 ports detected
10559 04:47:21.048969 <6>[ 2.242304] hub 1-1.4:1.0: USB hub found
10560 04:47:21.054997 <6>[ 2.242656] hub 1-1.4:1.0: 2 ports detected
10561 04:47:21.337308 <6>[ 2.529665] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10562 04:47:21.521175 <6>[ 2.713666] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10563 04:47:32.241515 <6>[ 13.442716] ALSA device list:
10564 04:47:32.248066 <6>[ 13.442738] No soundcards found.
10565 04:47:32.251345 <6>[ 13.447126] Freeing unused kernel memory: 8448K
10566 04:47:32.255115 <6>[ 13.447275] Run /init as init process
10567 04:47:32.257793 Loading, please wait...
10568 04:47:32.278172 Starting version 247.3-7+deb11u2
10569 04:47:32.516093 <6>[ 13.709668] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10570 04:47:32.522965 <6>[ 13.709751] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10571 04:47:32.532023 <6>[ 13.709767] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10572 04:47:32.538794 <6>[ 13.711578] usbcore: registered new device driver r8152-cfgselector
10573 04:47:32.551595 <3>[ 13.746725] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10574 04:47:32.558112 <3>[ 13.746796] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10575 04:47:32.568418 <3>[ 13.746810] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10576 04:47:32.575198 <6>[ 13.747647] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10577 04:47:32.581510 <3>[ 13.760217] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10578 04:47:32.591299 <3>[ 13.760243] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10579 04:47:32.598046 <3>[ 13.760250] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10580 04:47:32.607550 <3>[ 13.760256] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10581 04:47:32.613979 <3>[ 13.760261] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10582 04:47:32.621122 <6>[ 13.771008] remoteproc remoteproc0: scp is available
10583 04:47:32.624239 <6>[ 13.771109] remoteproc remoteproc0: powering up scp
10584 04:47:32.634514 <6>[ 13.771115] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10585 04:47:32.640684 <6>[ 13.771140] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10586 04:47:32.647815 <3>[ 13.791154] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10587 04:47:32.654466 <4>[ 13.792050] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10588 04:47:32.664199 <3>[ 13.795727] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10589 04:47:32.671422 <3>[ 13.795741] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10590 04:47:32.677677 <3>[ 13.795744] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10591 04:47:32.688355 <4>[ 13.795773] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10592 04:47:32.695156 <3>[ 13.807357] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10593 04:47:32.702260 <3>[ 13.807376] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10594 04:47:32.712031 <3>[ 13.807380] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10595 04:47:32.718347 <3>[ 13.807385] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10596 04:47:32.728721 <3>[ 13.807388] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10597 04:47:32.735178 <3>[ 13.807421] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10598 04:47:32.738148 <6>[ 13.822913] mc: Linux media interface: v0.10
10599 04:47:32.748200 <6>[ 13.832711] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10600 04:47:32.754588 <6>[ 13.846906] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10601 04:47:32.761509 <6>[ 13.846919] pci_bus 0000:00: root bus resource [bus 00-ff]
10602 04:47:32.767929 <6>[ 13.846925] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10603 04:47:32.777638 <6>[ 13.846930] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10604 04:47:32.784474 <6>[ 13.846974] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10605 04:47:32.791348 <6>[ 13.846994] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10606 04:47:32.794694 <6>[ 13.847103] pci 0000:00:00.0: supports D1 D2
10607 04:47:32.800586 <6>[ 13.847106] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10608 04:47:32.810486 <6>[ 13.849327] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10609 04:47:32.817070 <6>[ 13.850157] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10610 04:47:32.823970 <6>[ 13.850189] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10611 04:47:32.830551 <6>[ 13.850207] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10612 04:47:32.837345 <6>[ 13.850215] videodev: Linux video capture interface: v2.00
10613 04:47:32.843756 <6>[ 13.850222] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10614 04:47:32.851073 <6>[ 13.850336] pci 0000:01:00.0: supports D1 D2
10615 04:47:32.857410 <6>[ 13.850341] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10616 04:47:32.863544 <4>[ 13.863679] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10617 04:47:32.870462 <4>[ 13.863679] Fallback method does not support PEC.
10618 04:47:32.876803 <6>[ 13.865684] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10619 04:47:32.883710 <6>[ 13.865723] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10620 04:47:32.893162 <6>[ 13.865727] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10621 04:47:32.900028 <6>[ 13.865734] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10622 04:47:32.909858 <6>[ 13.865747] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10623 04:47:32.916690 <6>[ 13.865761] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10624 04:47:32.923129 <6>[ 13.865774] pci 0000:00:00.0: PCI bridge to [bus 01]
10625 04:47:32.930275 <6>[ 13.865780] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10626 04:47:32.936176 <6>[ 13.866092] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10627 04:47:32.943033 <6>[ 13.866817] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10628 04:47:32.949343 <6>[ 13.867061] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10629 04:47:32.956295 <3>[ 13.880504] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10630 04:47:32.963483 <6>[ 13.896410] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10631 04:47:32.972272 <6>[ 13.896439] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10632 04:47:32.979183 <6>[ 13.896449] remoteproc remoteproc0: remote processor scp is now up
10633 04:47:32.989607 <3>[ 13.905028] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10634 04:47:32.999054 <6>[ 13.905967] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10635 04:47:33.005542 <6>[ 13.906261] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10636 04:47:33.015195 <6>[ 13.909335] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10637 04:47:33.025329 <6>[ 13.910032] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10638 04:47:33.032115 <6>[ 13.910087] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10639 04:47:33.042054 <6>[ 13.918491] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10640 04:47:33.048481 <4>[ 13.932878] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10641 04:47:33.058472 <4>[ 13.932889] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10642 04:47:33.065488 <5>[ 13.936594] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10643 04:47:33.071909 <5>[ 13.951477] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10644 04:47:33.082062 <5>[ 13.951715] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10645 04:47:33.091330 <4>[ 13.951775] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10646 04:47:33.094387 <6>[ 13.951783] cfg80211: failed to load regulatory.db
10647 04:47:33.098166 <6>[ 13.953926] Bluetooth: Core ver 2.22
10648 04:47:33.104220 <6>[ 13.953981] NET: Registered PF_BLUETOOTH protocol family
10649 04:47:33.111252 <6>[ 13.953982] Bluetooth: HCI device and connection manager initialized
10650 04:47:33.117346 <6>[ 13.954001] Bluetooth: HCI socket layer initialized
10651 04:47:33.120529 <6>[ 13.954004] Bluetooth: L2CAP socket layer initialized
10652 04:47:33.127309 <6>[ 13.954010] Bluetooth: SCO socket layer initialized
10653 04:47:33.134094 <6>[ 13.975547] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10654 04:47:33.147215 <6>[ 13.976763] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10655 04:47:33.150705 <6>[ 13.976919] usbcore: registered new interface driver uvcvideo
10656 04:47:33.157591 <6>[ 13.989759] r8152 2-1.3:1.0 eth0: v1.12.13
10657 04:47:33.160916 <6>[ 13.989878] usbcore: registered new interface driver r8152
10658 04:47:33.166806 <6>[ 14.016958] usbcore: registered new interface driver cdc_ether
10659 04:47:33.174096 <6>[ 14.017718] usbcore: registered new interface driver btusb
10660 04:47:33.180644 <6>[ 14.018139] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10661 04:47:33.190133 <4>[ 14.018741] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10662 04:47:33.197315 <3>[ 14.018759] Bluetooth: hci0: Failed to load firmware file (-2)
10663 04:47:33.203698 <3>[ 14.018763] Bluetooth: hci0: Failed to set up firmware (-2)
10664 04:47:33.213324 <4>[ 14.018767] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10665 04:47:33.219975 <6>[ 14.030438] usbcore: registered new interface driver r8153_ecm
10666 04:47:33.226730 <6>[ 14.055169] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10667 04:47:33.233631 <6>[ 14.057965] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10668 04:47:33.239938 <6>[ 14.058072] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10669 04:47:33.242841 <6>[ 14.077557] mt7921e 0000:01:00.0: ASIC revision: 79610010
10670 04:47:33.253318 <6>[ 14.172946] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10671 04:47:33.253945 <6>[ 14.172946]
10672 04:47:33.263280 <6>[ 14.438952] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10673 04:47:33.266385 Begin: Loading essential drivers ... done.
10674 04:47:33.272848 Begin: Running /scripts/init-premount ... done.
10675 04:47:33.279136 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10676 04:47:33.285934 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10677 04:47:33.292461 Device /sys/class/net/enx002432307c7b found
10678 04:47:33.292963 done.
10679 04:47:33.329091 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10680 04:47:34.096346 <6>[ 15.294881] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10681 04:47:34.356298 <6>[ 15.557241] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10682 04:47:35.289626 IP-Config: no response after 2 secs - giving up
10683 04:47:35.336185 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:a1 mtu 1500 DHCP
10684 04:47:36.047885 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10685 04:47:36.055182 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10686 04:47:36.061203 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10687 04:47:36.068013 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10688 04:47:36.074543 host : mt8192-asurada-spherion-r0-cbg-2
10689 04:47:36.081404 domain : lava-rack
10690 04:47:36.087612 rootserver: 192.168.201.1 rootpath:
10691 04:47:36.088203 filename :
10692 04:47:36.181918 done.
10693 04:47:36.190730 Begin: Running /scripts/nfs-bottom ... done.
10694 04:47:36.208918 Begin: Running /scripts/init-bottom ... done.
10695 04:47:37.487944 <6>[ 18.685496] NET: Registered PF_INET6 protocol family
10696 04:47:37.491758 <6>[ 18.687806] Segment Routing with IPv6
10697 04:47:37.497474 <6>[ 18.687855] In-situ OAM (IOAM) with IPv6
10698 04:47:37.627281 <30>[ 18.807410] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10699 04:47:37.631090 <30>[ 18.808422] systemd[1]: Detected architecture arm64.
10700 04:47:37.631628
10701 04:47:37.637413 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10702 04:47:37.637832
10703 04:47:37.655836 <30>[ 18.856592] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10704 04:47:38.618967 <30>[ 19.816073] systemd[1]: Queued start job for default target Graphical Interface.
10705 04:47:38.653922 [[0;32m OK [<30>[ 19.852043] systemd[1]: Created slice system-getty.slice.
10706 04:47:38.657108 0m] Created slice [0;1;39msystem-getty.slice[0m.
10707 04:47:38.676536 [[0;32m OK [0m] Created slic<30>[ 19.875167] systemd[1]: Created slice system-modprobe.slice.
10708 04:47:38.679946 e [0;1;39msystem-modprobe.slice[0m.
10709 04:47:38.700383 [[0;32m OK [0m] Created slic<30>[ 19.899038] systemd[1]: Created slice system-serial\x2dgetty.slice.
10710 04:47:38.707251 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10711 04:47:38.724954 [[0;32m OK [0m] Created slic<30>[ 19.923484] systemd[1]: Created slice User and Session Slice.
10712 04:47:38.728267 e [0;1;39mUser and Session Slice[0m.
10713 04:47:38.751597 [[0;32m OK [0m] Started [0;<30>[ 19.946511] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10714 04:47:38.754633 1;39mDispatch Password …ts to Console Directory Watch[0m.
10715 04:47:38.779446 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 19.973884] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10716 04:47:38.782149 sword R…uests to Wall Directory Watch[0m.
10717 04:47:38.806734 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 19.997833] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10718 04:47:38.812912 <30>[ 19.998025] systemd[1]: Reached target Local Encrypted Volumes.
10719 04:47:38.816014 l Encrypted Volumes[0m.
10720 04:47:38.835738 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 20.033858] systemd[1]: Reached target Paths.
10721 04:47:38.836278 s[0m.
10722 04:47:38.858598 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 20.053686] systemd[1]: Reached target Remote File Systems.
10723 04:47:38.859105 te File Systems[0m.
10724 04:47:38.880195 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 20.078073] systemd[1]: Reached target Slices.
10725 04:47:38.880740 es[0m.
10726 04:47:38.899843 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 20.097842] systemd[1]: Reached target Swap.
10727 04:47:38.900437 [0m.
10728 04:47:38.920246 [[0;32m OK [0m] Listening on<30>[ 20.118618] systemd[1]: Listening on initctl Compatibility Named Pipe.
10729 04:47:38.926899 [0;1;39minitctl Compatibility Named Pipe[0m.
10730 04:47:38.946628 [[0;32m OK [<30>[ 20.144388] systemd[1]: Listening on Journal Audit Socket.
10731 04:47:38.949676 0m] Listening on [0;1;39mJournal Audit Socket[0m.
10732 04:47:38.968872 [[0;32m OK [0m] Listening on<30>[ 20.167344] systemd[1]: Listening on Journal Socket (/dev/log).
10733 04:47:38.972608 [0;1;39mJournal Socket (/dev/log)[0m.
10734 04:47:38.992211 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 20.190262] systemd[1]: Listening on Journal Socket.
10735 04:47:38.995808 l Socket[0m.
10736 04:47:39.013477 [[0;32m OK [0m] Listening on<30>[ 20.211554] systemd[1]: Listening on Network Service Netlink Socket.
10737 04:47:39.019568 [0;1;39mNetwork Service Netlink Socket[0m.
10738 04:47:39.038767 [[0;32m OK [<30>[ 20.237048] systemd[1]: Listening on udev Control Socket.
10739 04:47:39.041701 0m] Listening on [0;1;39mudev Control Socket[0m.
10740 04:47:39.060121 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 20.258114] systemd[1]: Listening on udev Kernel Socket.
10741 04:47:39.063003 ernel Socket[0m.
10742 04:47:39.110847 Mounting [0;1;39mHuge Pages File Syste<30>[ 20.305794] systemd[1]: Mounting Huge Pages File System...
10743 04:47:39.111431 m[0m...
10744 04:47:39.135459 Mounting [0;1;39mPOSIX Message Queue F<30>[ 20.330329] systemd[1]: Mounting POSIX Message Queue File System...
10745 04:47:39.135918 ile System[0m...
10746 04:47:39.161053 Mounting [0;1;39mKerne<30>[ 20.359299] systemd[1]: Mounting Kernel Debug File System...
10747 04:47:39.164161 l Debug File System[0m...
10748 04:47:39.186746 <30>[ 20.382468] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10749 04:47:39.235476 Starting [0;1;39mCreate list of st…o<30>[ 20.430333] systemd[1]: Starting Create list of static device nodes for the current kernel...
10750 04:47:39.238245 des for the current kernel[0m...
10751 04:47:39.264441 Starting [0;1;39mLoad <30>[ 20.462736] systemd[1]: Starting Load Kernel Module configfs...
10752 04:47:39.267749 Kernel Module configfs[0m...
10753 04:47:39.295051 Starting [0;1;39mLoad Kernel Module dr<30>[ 20.490289] systemd[1]: Starting Load Kernel Module drm...
10754 04:47:39.295601 m[0m...
10755 04:47:39.316704 Starting [0;1;39mLoad <30>[ 20.514727] systemd[1]: Starting Load Kernel Module fuse...
10756 04:47:39.319463 Kernel Module fuse[0m...
10757 04:47:39.346779 <30>[ 20.541678] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10758 04:47:39.359080 Startin<6>[ 20.559995] fuse: init (API version 7.37)
10759 04:47:39.366042 <30>[ 20.560747] systemd[1]: Starting Journal Service...
10760 04:47:39.369507 g [0;1;39mJournal Service[0m...
10761 04:47:39.396152 Starting [0;1;39mLoad Kernel Modules[<30>[ 20.594448] systemd[1]: Starting Load Kernel Modules...
10762 04:47:39.399323 0m...
10763 04:47:39.421928 Startin<30>[ 20.620753] systemd[1]: Starting Remount Root and Kernel File Systems...
10764 04:47:39.428445 g [0;1;39mRemount Root and Kernel File Systems[0m...
10765 04:47:39.470777 Starting [0;1;39mColdplug All udev Dev<30>[ 20.666209] systemd[1]: Starting Coldplug All udev Devices...
10766 04:47:39.470988 ices[0m...
10767 04:47:39.487984 <30>[ 20.689276] systemd[1]: Mounted Huge Pages File System.
10768 04:47:39.494048 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10769 04:47:39.512529 [[0;32m OK [0m] Mounted [0;<30>[ 20.711070] systemd[1]: Mounted POSIX Message Queue File System.
10770 04:47:39.515682 1;39mPOSIX Message Queue File System[0m.
10771 04:47:39.535904 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<30>[ 20.734026] systemd[1]: Mounted Kernel Debug File System.
10772 04:47:39.546320 g File System[0<3>[ 20.737531] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10773 04:47:39.549115 m.
10774 04:47:39.562701 <3>[ 20.760684] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10775 04:47:39.576451 [[0;32m OK [0m] Finished [0<30>[ 20.771680] systemd[1]: Finished Create list of static device nodes for the current kernel.
10776 04:47:39.582829 ;1;39mCreate list of st… nodes for the current kernel[0m.
10777 04:47:39.598779 <3>[ 20.795518] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10778 04:47:39.607485 <30>[ 20.808336] systemd[1]: modprobe@configfs.service: Succeeded.
10779 04:47:39.615194 <30>[ 20.810259] systemd[1]: Finished Load Kernel Module configfs.
10780 04:47:39.628176 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 20.824963] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10781 04:47:39.631451 l Module configfs[0m.
10782 04:47:39.649992 [[0;32m OK [<30>[ 20.847183] systemd[1]: modprobe@drm.service: Succeeded.
10783 04:47:39.659587 0m] Finished [0<3>[ 20.847321] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10784 04:47:39.662829 <30>[ 20.848150] systemd[1]: Finished Load Kernel Module drm.
10785 04:47:39.666266 ;1;39mLoad Kernel Module drm[0m.
10786 04:47:39.683174 <3>[ 20.878168] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10787 04:47:39.694782 [[0;32m OK [<30>[ 20.891621] systemd[1]: modprobe@fuse.service: Succeeded.
10788 04:47:39.701404 0m] Finished [0<30>[ 20.892588] systemd[1]: Finished Load Kernel Module fuse.
10789 04:47:39.710957 ;1;39mLoad Kerne<3>[ 20.902846] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10790 04:47:39.711566 l Module fuse[0m.
10791 04:47:39.733884 [[0;32m OK [0m] Finished [0<30>[ 20.931877] systemd[1]: Finished Load Kernel Modules.
10792 04:47:39.743616 ;1;39mLoad Kerne<3>[ 20.933164] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10793 04:47:39.744343 l Modules[0m.
10794 04:47:39.759253 <3>[ 20.954622] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10795 04:47:39.770165 [[0;32m OK [<30>[ 20.968069] systemd[1]: Finished Remount Root and Kernel File Systems.
10796 04:47:39.776715 0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10797 04:47:39.783433 <3>[ 20.980043] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10798 04:47:39.783982
10799 04:47:39.828533 [[0;32m OK [0m] Started [0;<30>[ 21.026534] systemd[1]: Started Journal Service.
10800 04:47:39.829073 1;39mJournal Service[0m.
10801 04:47:39.853349 Mounting [0;1;39mFUSE Control File System[0m...
10802 04:47:39.873858 Mounting [0;1;39mKernel Configuration File System[0m...
10803 04:47:39.941253 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10804 04:47:39.961796 Starting [0;1;39mLoad/Save Random Seed[0m...
10805 04:47:39.980164 Starting [0;1;39mApply Kernel Variables[0m...
10806 04:47:40.003787 Starting [0;1;39mCreate System Users[0m...
10807 04:47:40.015425 <46>[ 21.209561] systemd-journald[294]: Received client request to flush runtime journal.
10808 04:47:40.031865 <4>[ 21.218249] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10809 04:47:40.038418 <3>[ 21.218260] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10810 04:47:40.044696 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10811 04:47:40.068473 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10812 04:47:40.079334 See 'systemctl status systemd-udev-trigger.service' for details.
10813 04:47:40.097200 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10814 04:47:40.114103 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10815 04:47:40.134720 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10816 04:47:41.445554 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10817 04:47:41.467926 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10818 04:47:41.513088 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10819 04:47:41.629947 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10820 04:47:41.643821 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10821 04:47:41.660447 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10822 04:47:41.720206 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10823 04:47:41.744108 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10824 04:47:41.941708 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10825 04:47:42.009723 Starting [0;1;39mNetwork Service[0m...
10826 04:47:42.187200 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10827 04:47:42.400900 Starting [0;1;39mNetwork Time Synchronization[0m...
10828 04:47:42.437824 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10829 04:47:42.577694 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10830 04:47:42.747817 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10831 04:47:42.763968 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10832 04:47:42.797896 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10833 04:47:42.815686 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10834 04:47:42.835135 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10835 04:47:42.891294 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10836 04:47:42.928588 Starting [0;1;39mNetwork Name Resolution[0m...
10837 04:47:42.950253 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10838 04:47:42.967574 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10839 04:47:42.989454 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10840 04:47:43.008476 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10841 04:47:43.028535 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10842 04:47:43.050925 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10843 04:47:43.068059 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10844 04:47:43.087073 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10845 04:47:43.116204 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10846 04:47:43.139734 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10847 04:47:43.164514 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10848 04:47:43.201669 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10849 04:47:43.215632 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10850 04:47:43.243392 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10851 04:47:43.256420 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10852 04:47:43.272459 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10853 04:47:43.326313 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10854 04:47:43.481910 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10855 04:47:43.613064 Starting [0;1;39mUser Login Management[0m...
10856 04:47:43.841986 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10857 04:47:43.860675 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10858 04:47:43.878814 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10859 04:47:43.938909 Starting [0;1;39mPermit User Sessions[0m...
10860 04:47:43.966934 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10861 04:47:43.985421 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10862 04:47:44.004760 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10863 04:47:44.049542 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10864 04:47:44.066938 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10865 04:47:44.083453 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10866 04:47:44.102308 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10867 04:47:44.121576 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10868 04:47:44.176721 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10869 04:47:44.228839 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10870 04:47:44.311084
10871 04:47:44.311666
10872 04:47:44.314209 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10873 04:47:44.314627
10874 04:47:44.317395 debian-bullseye-arm64 login: root (automatic login)
10875 04:47:44.317852
10876 04:47:44.318263
10877 04:47:44.741454 Linux debian-bullseye-arm64 6.1.75-cip14-rt8 #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024 aarch64
10878 04:47:44.741958
10879 04:47:44.747808 The programs included with the Debian GNU/Linux system are free software;
10880 04:47:44.754753 the exact distribution terms for each program are described in the
10881 04:47:44.757947 individual files in /usr/share/doc/*/copyright.
10882 04:47:44.758367
10883 04:47:44.764443 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10884 04:47:44.767645 permitted by applicable law.
10885 04:47:45.872236 Matched prompt #10: / #
10887 04:47:45.873385 Setting prompt string to ['/ #']
10888 04:47:45.873817 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10890 04:47:45.874782 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10891 04:47:45.875227 start: 2.2.6 expect-shell-connection (timeout 00:03:06) [common]
10892 04:47:45.875662 Setting prompt string to ['/ #']
10893 04:47:45.875979 Forcing a shell prompt, looking for ['/ #']
10895 04:47:45.926791 / #
10896 04:47:45.927507 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10897 04:47:45.928040 Waiting using forced prompt support (timeout 00:02:30)
10898 04:47:45.933848
10899 04:47:45.934801 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10900 04:47:45.935344 start: 2.2.7 export-device-env (timeout 00:03:06) [common]
10902 04:47:46.036789 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12699825/extract-nfsrootfs-wnf_mrip'
10903 04:47:46.043233 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12699825/extract-nfsrootfs-wnf_mrip'
10905 04:47:46.144975 / # export NFS_SERVER_IP='192.168.201.1'
10906 04:47:46.151500 export NFS_SERVER_IP='192.168.201.1'
10907 04:47:46.152438 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10908 04:47:46.153000 end: 2.2 depthcharge-retry (duration 00:01:55) [common]
10909 04:47:46.153496 end: 2 depthcharge-action (duration 00:01:55) [common]
10910 04:47:46.153992 start: 3 lava-test-retry (timeout 00:07:23) [common]
10911 04:47:46.154459 start: 3.1 lava-test-shell (timeout 00:07:23) [common]
10912 04:47:46.154923 Using namespace: common
10914 04:47:46.256180 / # #
10915 04:47:46.256350 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10916 04:47:46.262283 #
10917 04:47:46.262641 Using /lava-12699825
10919 04:47:46.363265 / # export SHELL=/bin/bash
10920 04:47:46.370117 export SHELL=/bin/bash
10922 04:47:46.471905 / # . /lava-12699825/environment
10923 04:47:46.478605 . /lava-12699825/environment
10925 04:47:46.588167 / # /lava-12699825/bin/lava-test-runner /lava-12699825/0
10926 04:47:46.588808 Test shell timeout: 10s (minimum of the action and connection timeout)
10927 04:47:46.595072 /lava-12699825/bin/lava-test-runner /lava-12699825/0
10928 04:47:46.944562 + export TESTRUN_ID=0_timesync-off
10929 04:47:46.948236 + TESTRUN_ID=0_timesync-off
10930 04:47:46.951530 + cd /lava-12699825/0/tests/0_timesync-off
10931 04:47:46.954486 ++ cat uuid
10932 04:47:46.963279 + UUID=12699825_1.6.2.3.1
10933 04:47:46.963737 + set +x
10934 04:47:46.969668 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12699825_1.6.2.3.1>
10935 04:47:46.970363 Received signal: <STARTRUN> 0_timesync-off 12699825_1.6.2.3.1
10936 04:47:46.970734 Starting test lava.0_timesync-off (12699825_1.6.2.3.1)
10937 04:47:46.971147 Skipping test definition patterns.
10938 04:47:46.973369 + systemctl stop systemd-timesyncd
10939 04:47:47.054963 + set +x
10940 04:47:47.058256 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12699825_1.6.2.3.1>
10941 04:47:47.058960 Received signal: <ENDRUN> 0_timesync-off 12699825_1.6.2.3.1
10942 04:47:47.059446 Ending use of test pattern.
10943 04:47:47.059783 Ending test lava.0_timesync-off (12699825_1.6.2.3.1), duration 0.09
10945 04:47:47.161893 + export TESTRUN_ID=1_kselftest-rtc
10946 04:47:47.165052 + TESTRUN_ID=1_kselftest-rtc
10947 04:47:47.168043 + cd /lava-12699825/0/tests/1_kselftest-rtc
10948 04:47:47.171531 ++ cat uuid
10949 04:47:47.182510 + UUID=12699825_1.6.2.3.5
10950 04:47:47.182933 + set +x
10951 04:47:47.188972 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 12699825_1.6.2.3.5>
10952 04:47:47.189657 Received signal: <STARTRUN> 1_kselftest-rtc 12699825_1.6.2.3.5
10953 04:47:47.190008 Starting test lava.1_kselftest-rtc (12699825_1.6.2.3.5)
10954 04:47:47.190391 Skipping test definition patterns.
10955 04:47:47.192267 + cd ./automated/linux/kselftest/
10956 04:47:47.218631 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10957 04:47:47.280636 INFO: install_deps skipped
10958 04:47:47.411759 --2024-02-04 04:47:47-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10959 04:47:47.424123 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10960 04:47:47.557974 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10961 04:47:47.691519 HTTP request sent, awaiting response... 200 OK
10962 04:47:47.694455 Length: 2966368 (2.8M) [application/octet-stream]
10963 04:47:47.697664 Saving to: 'kselftest.tar.xz'
10964 04:47:47.697866
10965 04:47:47.697930
10966 04:47:47.956895 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10967 04:47:48.223638 kselftest.tar.xz 1%[ ] 44.98K 167KB/s
10968 04:47:48.543601 kselftest.tar.xz 7%[> ] 219.84K 406KB/s
10969 04:47:48.892149 kselftest.tar.xz 26%[====> ] 761.91K 878KB/s
10970 04:47:48.950056 kselftest.tar.xz 53%[=========> ] 1.50M 1.23MB/s
10971 04:47:48.956602 kselftest.tar.xz 100%[===================>] 2.83M 2.21MB/s in 1.3s
10972 04:47:48.957023
10973 04:47:49.215037 2024-02-04 04:47:49 (2.21 MB/s) - 'kselftest.tar.xz' saved [2966368/2966368]
10974 04:47:49.215588
10975 04:47:56.521681 skiplist:
10976 04:47:56.524956 ========================================
10977 04:47:56.528116 ========================================
10978 04:47:56.592092 rtc:rtctest
10979 04:47:56.617366 ============== Tests to run ===============
10980 04:47:56.620869 rtc:rtctest
10981 04:47:56.623773 ===========End Tests to run ===============
10982 04:47:56.628524 shardfile-rtc pass
10983 04:47:56.754428 <12>[ 37.954598] kselftest: Running tests in rtc
10984 04:47:56.762221 TAP version 13
10985 04:47:56.778644 1..1
10986 04:47:56.816488 # selftests: rtc: rtctest
10987 04:47:57.288747 # TAP version 13
10988 04:47:57.289258 # 1..8
10989 04:47:57.292026 # # Starting 8 tests from 2 test cases.
10990 04:47:57.295315 # # RUN rtc.date_read ...
10991 04:47:57.302352 # # rtctest.c:49:date_read:Current RTC date/time is 04/02/2024 04:47:56.
10992 04:47:57.305343 # # OK rtc.date_read
10993 04:47:57.308852 # ok 1 rtc.date_read
10994 04:47:57.312053 # # RUN rtc.date_read_loop ...
10995 04:47:57.321589 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
10996 04:48:02.570040 <6>[ 43.773925] vpu: disabling
10997 04:48:02.573485 <6>[ 43.774048] vproc2: disabling
10998 04:48:02.576096 <6>[ 43.774103] vproc1: disabling
10999 04:48:02.579660 <6>[ 43.774157] vaud18: disabling
11000 04:48:02.582556 <6>[ 43.774411] vsram_others: disabling
11001 04:48:02.586247 <6>[ 43.774592] va09: disabling
11002 04:48:02.589448 <6>[ 43.774671] vsram_md: disabling
11003 04:48:02.593145 <6>[ 43.774805] Vgpu: disabling
11004 04:48:27.263691 # # rtctest.c:115:date_read_loop:Performed 2649 RTC time reads.
11005 04:48:27.266632 # # OK rtc.date_read_loop
11006 04:48:27.270573 # ok 2 rtc.date_read_loop
11007 04:48:27.273607 # # RUN rtc.uie_read ...
11008 04:48:30.243567 # # OK rtc.uie_read
11009 04:48:30.246811 # ok 3 rtc.uie_read
11010 04:48:30.249400 # # RUN rtc.uie_select ...
11011 04:48:33.242834 # # OK rtc.uie_select
11012 04:48:33.245809 # ok 4 rtc.uie_select
11013 04:48:33.248717 # # RUN rtc.alarm_alm_set ...
11014 04:48:33.255350 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 04:48:36.
11015 04:48:33.259234 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11016 04:48:33.265159 # # alarm_alm_set: Test terminated by assertion
11017 04:48:33.268889 # # FAIL rtc.alarm_alm_set
11018 04:48:33.271840 # not ok 5 rtc.alarm_alm_set
11019 04:48:33.275281 # # RUN rtc.alarm_wkalm_set ...
11020 04:48:33.281988 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 04/02/2024 04:48:36.
11021 04:48:36.244961 # # OK rtc.alarm_wkalm_set
11022 04:48:36.245531 # ok 6 rtc.alarm_wkalm_set
11023 04:48:36.251261 # # RUN rtc.alarm_alm_set_minute ...
11024 04:48:36.254967 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 04:49:00.
11025 04:48:36.261254 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11026 04:48:36.267761 # # alarm_alm_set_minute: Test terminated by assertion
11027 04:48:36.271526 # # FAIL rtc.alarm_alm_set_minute
11028 04:48:36.274997 # not ok 7 rtc.alarm_alm_set_minute
11029 04:48:36.278145 # # RUN rtc.alarm_wkalm_set_minute ...
11030 04:48:36.284813 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 04/02/2024 04:49:00.
11031 04:49:00.242724 # # OK rtc.alarm_wkalm_set_minute
11032 04:49:00.245732 # ok 8 rtc.alarm_wkalm_set_minute
11033 04:49:00.249134 # # FAILED: 6 / 8 tests passed.
11034 04:49:00.252330 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11035 04:49:00.255877 not ok 1 selftests: rtc: rtctest # exit=1
11036 04:49:00.911730 rtc_rtctest_rtc_date_read pass
11037 04:49:00.914610 rtc_rtctest_rtc_date_read_loop pass
11038 04:49:00.918110 rtc_rtctest_rtc_uie_read pass
11039 04:49:00.921491 rtc_rtctest_rtc_uie_select pass
11040 04:49:00.924669 rtc_rtctest_rtc_alarm_alm_set fail
11041 04:49:00.928233 rtc_rtctest_rtc_alarm_wkalm_set pass
11042 04:49:00.931755 rtc_rtctest_rtc_alarm_alm_set_minute fail
11043 04:49:00.934522 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11044 04:49:00.937951 rtc_rtctest fail
11045 04:49:00.944651 + ../../utils/send-to-lava.sh ./output/result.txt
11046 04:49:01.043892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11047 04:49:01.044682 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11049 04:49:01.114191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11050 04:49:01.114950 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11052 04:49:01.185758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11053 04:49:01.186458 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11055 04:49:01.249129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11056 04:49:01.249943 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11058 04:49:01.321380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11059 04:49:01.322177 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11061 04:49:01.392564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11062 04:49:01.393260 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11064 04:49:01.463118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11065 04:49:01.463978 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11067 04:49:01.536894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11068 04:49:01.537710 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11070 04:49:01.607343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11071 04:49:01.608131 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11073 04:49:01.675175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11074 04:49:01.675773 + set +x
11075 04:49:01.676388 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11077 04:49:01.682396 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 12699825_1.6.2.3.5>
11078 04:49:01.683136 Received signal: <ENDRUN> 1_kselftest-rtc 12699825_1.6.2.3.5
11079 04:49:01.683658 Ending use of test pattern.
11080 04:49:01.683984 Ending test lava.1_kselftest-rtc (12699825_1.6.2.3.5), duration 74.49
11082 04:49:01.685350 ok: lava_test_shell seems to have completed
11083 04:49:01.686028 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11084 04:49:01.686460 end: 3.1 lava-test-shell (duration 00:01:16) [common]
11085 04:49:01.686870 end: 3 lava-test-retry (duration 00:01:16) [common]
11086 04:49:01.687302 start: 4 finalize (timeout 00:06:08) [common]
11087 04:49:01.687768 start: 4.1 power-off (timeout 00:00:30) [common]
11088 04:49:01.688513 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11089 04:49:01.791488 >> Command sent successfully.
11090 04:49:01.793757 Returned 0 in 0 seconds
11091 04:49:01.894158 end: 4.1 power-off (duration 00:00:00) [common]
11093 04:49:01.894502 start: 4.2 read-feedback (timeout 00:06:07) [common]
11095 04:49:01.895045 Listened to connection for namespace 'common' for up to 1s
11096 04:49:02.895647 Finalising connection for namespace 'common'
11097 04:49:02.896269 Disconnecting from shell: Finalise
11098 04:49:02.896648 / #
11099 04:49:02.997980 end: 4.2 read-feedback (duration 00:00:01) [common]
11100 04:49:02.998750 end: 4 finalize (duration 00:00:01) [common]
11101 04:49:02.999356 Cleaning after the job
11102 04:49:02.999940 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/ramdisk
11103 04:49:03.013641 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/kernel
11104 04:49:03.047048 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/dtb
11105 04:49:03.047329 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/nfsrootfs
11106 04:49:03.135174 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699825/tftp-deploy-qo_ublru/modules
11107 04:49:03.142032 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12699825
11108 04:49:03.771351 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12699825
11109 04:49:03.771542 Job finished correctly