Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 14
- Kernel Errors: 38
1 04:43:06.940654 lava-dispatcher, installed at version: 2023.10
2 04:43:06.940889 start: 0 validate
3 04:43:06.941027 Start time: 2024-02-04 04:43:06.941019+00:00 (UTC)
4 04:43:06.941138 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:43:06.941270 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 04:43:07.202988 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:43:07.203735 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:43:07.475080 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:43:07.475847 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:43:07.746281 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:43:07.747073 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 04:43:08.018074 Using caching service: 'http://localhost/cache/?uri=%s'
13 04:43:08.018858 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 04:43:08.296782 validate duration: 1.36
16 04:43:08.298081 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:43:08.298648 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:43:08.299162 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:43:08.299801 Not decompressing ramdisk as can be used compressed.
20 04:43:08.300297 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 04:43:08.300693 saving as /var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/ramdisk/initrd.cpio.gz
22 04:43:08.301100 total size: 4665395 (4 MB)
23 04:43:08.306706 progress 0 % (0 MB)
24 04:43:08.314722 progress 5 % (0 MB)
25 04:43:08.321545 progress 10 % (0 MB)
26 04:43:08.326242 progress 15 % (0 MB)
27 04:43:08.329854 progress 20 % (0 MB)
28 04:43:08.332857 progress 25 % (1 MB)
29 04:43:08.335720 progress 30 % (1 MB)
30 04:43:08.338089 progress 35 % (1 MB)
31 04:43:08.340458 progress 40 % (1 MB)
32 04:43:08.342744 progress 45 % (2 MB)
33 04:43:08.344784 progress 50 % (2 MB)
34 04:43:08.346683 progress 55 % (2 MB)
35 04:43:08.348450 progress 60 % (2 MB)
36 04:43:08.350217 progress 65 % (2 MB)
37 04:43:08.351840 progress 70 % (3 MB)
38 04:43:08.353425 progress 75 % (3 MB)
39 04:43:08.354991 progress 80 % (3 MB)
40 04:43:08.356726 progress 85 % (3 MB)
41 04:43:08.358193 progress 90 % (4 MB)
42 04:43:08.359615 progress 95 % (4 MB)
43 04:43:08.361020 progress 100 % (4 MB)
44 04:43:08.361180 4 MB downloaded in 0.06 s (74.03 MB/s)
45 04:43:08.361339 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:43:08.361590 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:43:08.361681 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:43:08.361768 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:43:08.361909 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 04:43:08.361984 saving as /var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/kernel/Image
52 04:43:08.362047 total size: 51597824 (49 MB)
53 04:43:08.362111 No compression specified
54 04:43:08.363216 progress 0 % (0 MB)
55 04:43:08.376552 progress 5 % (2 MB)
56 04:43:08.389992 progress 10 % (4 MB)
57 04:43:08.403255 progress 15 % (7 MB)
58 04:43:08.416583 progress 20 % (9 MB)
59 04:43:08.429875 progress 25 % (12 MB)
60 04:43:08.443143 progress 30 % (14 MB)
61 04:43:08.456512 progress 35 % (17 MB)
62 04:43:08.469909 progress 40 % (19 MB)
63 04:43:08.483518 progress 45 % (22 MB)
64 04:43:08.497278 progress 50 % (24 MB)
65 04:43:08.510650 progress 55 % (27 MB)
66 04:43:08.523948 progress 60 % (29 MB)
67 04:43:08.537370 progress 65 % (32 MB)
68 04:43:08.550655 progress 70 % (34 MB)
69 04:43:08.563930 progress 75 % (36 MB)
70 04:43:08.577302 progress 80 % (39 MB)
71 04:43:08.590783 progress 85 % (41 MB)
72 04:43:08.604202 progress 90 % (44 MB)
73 04:43:08.617675 progress 95 % (46 MB)
74 04:43:08.630676 progress 100 % (49 MB)
75 04:43:08.630879 49 MB downloaded in 0.27 s (183.04 MB/s)
76 04:43:08.631028 end: 1.2.1 http-download (duration 00:00:00) [common]
78 04:43:08.631259 end: 1.2 download-retry (duration 00:00:00) [common]
79 04:43:08.631345 start: 1.3 download-retry (timeout 00:10:00) [common]
80 04:43:08.631434 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 04:43:08.631573 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 04:43:08.631642 saving as /var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/dtb/mt8192-asurada-spherion-r0.dtb
83 04:43:08.631704 total size: 47278 (0 MB)
84 04:43:08.631765 No compression specified
85 04:43:08.632905 progress 69 % (0 MB)
86 04:43:08.633175 progress 100 % (0 MB)
87 04:43:08.633327 0 MB downloaded in 0.00 s (27.81 MB/s)
88 04:43:08.633446 end: 1.3.1 http-download (duration 00:00:00) [common]
90 04:43:08.633663 end: 1.3 download-retry (duration 00:00:00) [common]
91 04:43:08.633750 start: 1.4 download-retry (timeout 00:10:00) [common]
92 04:43:08.633831 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 04:43:08.633941 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 04:43:08.634008 saving as /var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/nfsrootfs/full.rootfs.tar
95 04:43:08.634067 total size: 200813988 (191 MB)
96 04:43:08.634131 Using unxz to decompress xz
97 04:43:08.638258 progress 0 % (0 MB)
98 04:43:09.161464 progress 5 % (9 MB)
99 04:43:09.685433 progress 10 % (19 MB)
100 04:43:10.287207 progress 15 % (28 MB)
101 04:43:10.667779 progress 20 % (38 MB)
102 04:43:11.004007 progress 25 % (47 MB)
103 04:43:11.611715 progress 30 % (57 MB)
104 04:43:12.177123 progress 35 % (67 MB)
105 04:43:12.782764 progress 40 % (76 MB)
106 04:43:13.335849 progress 45 % (86 MB)
107 04:43:13.919219 progress 50 % (95 MB)
108 04:43:14.547430 progress 55 % (105 MB)
109 04:43:15.202298 progress 60 % (114 MB)
110 04:43:15.318535 progress 65 % (124 MB)
111 04:43:15.456188 progress 70 % (134 MB)
112 04:43:15.551569 progress 75 % (143 MB)
113 04:43:15.621469 progress 80 % (153 MB)
114 04:43:15.689606 progress 85 % (162 MB)
115 04:43:15.789670 progress 90 % (172 MB)
116 04:43:16.063397 progress 95 % (181 MB)
117 04:43:16.631966 progress 100 % (191 MB)
118 04:43:16.637123 191 MB downloaded in 8.00 s (23.93 MB/s)
119 04:43:16.637377 end: 1.4.1 http-download (duration 00:00:08) [common]
121 04:43:16.637627 end: 1.4 download-retry (duration 00:00:08) [common]
122 04:43:16.637714 start: 1.5 download-retry (timeout 00:09:52) [common]
123 04:43:16.637799 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 04:43:16.637953 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 04:43:16.638023 saving as /var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/modules/modules.tar
126 04:43:16.638083 total size: 8633524 (8 MB)
127 04:43:16.638145 Using unxz to decompress xz
128 04:43:16.642516 progress 0 % (0 MB)
129 04:43:16.663323 progress 5 % (0 MB)
130 04:43:16.687650 progress 10 % (0 MB)
131 04:43:16.711844 progress 15 % (1 MB)
132 04:43:16.736119 progress 20 % (1 MB)
133 04:43:16.761144 progress 25 % (2 MB)
134 04:43:16.790108 progress 30 % (2 MB)
135 04:43:16.815796 progress 35 % (2 MB)
136 04:43:16.839450 progress 40 % (3 MB)
137 04:43:16.863385 progress 45 % (3 MB)
138 04:43:16.889042 progress 50 % (4 MB)
139 04:43:16.914464 progress 55 % (4 MB)
140 04:43:16.942057 progress 60 % (4 MB)
141 04:43:16.968466 progress 65 % (5 MB)
142 04:43:16.993771 progress 70 % (5 MB)
143 04:43:17.016962 progress 75 % (6 MB)
144 04:43:17.044494 progress 80 % (6 MB)
145 04:43:17.070890 progress 85 % (7 MB)
146 04:43:17.098780 progress 90 % (7 MB)
147 04:43:17.128862 progress 95 % (7 MB)
148 04:43:17.157378 progress 100 % (8 MB)
149 04:43:17.162969 8 MB downloaded in 0.52 s (15.69 MB/s)
150 04:43:17.163212 end: 1.5.1 http-download (duration 00:00:01) [common]
152 04:43:17.163469 end: 1.5 download-retry (duration 00:00:01) [common]
153 04:43:17.163561 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 04:43:17.163656 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 04:43:20.662795 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12699811/extract-nfsrootfs-gta4j95_
156 04:43:20.663013 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 04:43:20.663153 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 04:43:20.663379 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm
159 04:43:20.663568 makedir: /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin
160 04:43:20.663714 makedir: /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/tests
161 04:43:20.663851 makedir: /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/results
162 04:43:20.663994 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-add-keys
163 04:43:20.664199 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-add-sources
164 04:43:20.664392 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-background-process-start
165 04:43:20.664575 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-background-process-stop
166 04:43:20.664772 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-common-functions
167 04:43:20.664901 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-echo-ipv4
168 04:43:20.665028 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-install-packages
169 04:43:20.665151 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-installed-packages
170 04:43:20.665273 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-os-build
171 04:43:20.665396 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-probe-channel
172 04:43:20.665518 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-probe-ip
173 04:43:20.665639 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-target-ip
174 04:43:20.665759 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-target-mac
175 04:43:20.665880 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-target-storage
176 04:43:20.666003 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-test-case
177 04:43:20.666128 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-test-event
178 04:43:20.666249 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-test-feedback
179 04:43:20.666371 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-test-raise
180 04:43:20.666492 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-test-reference
181 04:43:20.666614 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-test-runner
182 04:43:20.666736 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-test-set
183 04:43:20.666857 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-test-shell
184 04:43:20.666981 Updating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-add-keys (debian)
185 04:43:20.667131 Updating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-add-sources (debian)
186 04:43:20.667270 Updating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-install-packages (debian)
187 04:43:20.667405 Updating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-installed-packages (debian)
188 04:43:20.667540 Updating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/bin/lava-os-build (debian)
189 04:43:20.667659 Creating /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/environment
190 04:43:20.667755 LAVA metadata
191 04:43:20.667823 - LAVA_JOB_ID=12699811
192 04:43:20.667883 - LAVA_DISPATCHER_IP=192.168.201.1
193 04:43:20.667981 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 04:43:20.668044 skipped lava-vland-overlay
195 04:43:20.668115 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 04:43:20.668203 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 04:43:20.668262 skipped lava-multinode-overlay
198 04:43:20.668333 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 04:43:20.668408 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 04:43:20.668478 Loading test definitions
201 04:43:20.668563 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 04:43:20.668631 Using /lava-12699811 at stage 0
203 04:43:20.668954 uuid=12699811_1.6.2.3.1 testdef=None
204 04:43:20.669040 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 04:43:20.669122 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 04:43:20.669565 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 04:43:20.669777 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 04:43:20.670322 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 04:43:20.670544 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 04:43:20.671067 runner path: /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/0/tests/0_timesync-off test_uuid 12699811_1.6.2.3.1
213 04:43:20.671217 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 04:43:20.671434 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 04:43:20.671505 Using /lava-12699811 at stage 0
217 04:43:20.671599 Fetching tests from https://github.com/kernelci/test-definitions.git
218 04:43:20.671675 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/0/tests/1_kselftest-tpm2'
219 04:43:25.418126 Running '/usr/bin/git checkout kernelci.org
220 04:43:25.565626 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 04:43:25.566379 uuid=12699811_1.6.2.3.5 testdef=None
222 04:43:25.566551 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 04:43:25.566834 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 04:43:25.567603 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 04:43:25.567864 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 04:43:25.568873 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 04:43:25.569134 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 04:43:25.570556 runner path: /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/0/tests/1_kselftest-tpm2 test_uuid 12699811_1.6.2.3.5
232 04:43:25.570657 BOARD='mt8192-asurada-spherion-r0'
233 04:43:25.570735 BRANCH='cip-gitlab'
234 04:43:25.570816 SKIPFILE='/dev/null'
235 04:43:25.570894 SKIP_INSTALL='True'
236 04:43:25.570971 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 04:43:25.571071 TST_CASENAME=''
238 04:43:25.571167 TST_CMDFILES='tpm2'
239 04:43:25.571369 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 04:43:25.571728 Creating lava-test-runner.conf files
242 04:43:25.571831 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12699811/lava-overlay-9domqgkm/lava-12699811/0 for stage 0
243 04:43:25.571972 - 0_timesync-off
244 04:43:25.572076 - 1_kselftest-tpm2
245 04:43:25.572221 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 04:43:25.572352 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 04:43:32.951326 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 04:43:32.951495 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 04:43:32.951602 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 04:43:32.951704 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 04:43:32.951797 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 04:43:33.071699 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 04:43:33.072095 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 04:43:33.072215 extracting modules file /var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699811/extract-nfsrootfs-gta4j95_
255 04:43:33.293363 extracting modules file /var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699811/extract-overlay-ramdisk-qk3vvptz/ramdisk
256 04:43:33.518761 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 04:43:33.518923 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 04:43:33.519015 [common] Applying overlay to NFS
259 04:43:33.519082 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699811/compress-overlay-hhnbploq/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12699811/extract-nfsrootfs-gta4j95_
260 04:43:34.432328 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 04:43:34.432499 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 04:43:34.432595 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 04:43:34.432687 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 04:43:34.432887 Building ramdisk /var/lib/lava/dispatcher/tmp/12699811/extract-overlay-ramdisk-qk3vvptz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12699811/extract-overlay-ramdisk-qk3vvptz/ramdisk
265 04:43:34.767742 >> 119436 blocks
266 04:43:36.692229 rename /var/lib/lava/dispatcher/tmp/12699811/extract-overlay-ramdisk-qk3vvptz/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/ramdisk/ramdisk.cpio.gz
267 04:43:36.692678 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 04:43:36.692813 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 04:43:36.692916 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 04:43:36.693022 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/kernel/Image'
271 04:43:48.905154 Returned 0 in 12 seconds
272 04:43:49.006161 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/kernel/image.itb
273 04:43:49.411257 output: FIT description: Kernel Image image with one or more FDT blobs
274 04:43:49.411644 output: Created: Sun Feb 4 04:43:49 2024
275 04:43:49.411718 output: Image 0 (kernel-1)
276 04:43:49.411782 output: Description:
277 04:43:49.411844 output: Created: Sun Feb 4 04:43:49 2024
278 04:43:49.411905 output: Type: Kernel Image
279 04:43:49.411965 output: Compression: lzma compressed
280 04:43:49.412024 output: Data Size: 12048508 Bytes = 11766.12 KiB = 11.49 MiB
281 04:43:49.412084 output: Architecture: AArch64
282 04:43:49.412140 output: OS: Linux
283 04:43:49.412194 output: Load Address: 0x00000000
284 04:43:49.412249 output: Entry Point: 0x00000000
285 04:43:49.412305 output: Hash algo: crc32
286 04:43:49.412361 output: Hash value: 3b31d50c
287 04:43:49.412413 output: Image 1 (fdt-1)
288 04:43:49.412465 output: Description: mt8192-asurada-spherion-r0
289 04:43:49.412516 output: Created: Sun Feb 4 04:43:49 2024
290 04:43:49.412567 output: Type: Flat Device Tree
291 04:43:49.412619 output: Compression: uncompressed
292 04:43:49.412670 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 04:43:49.412748 output: Architecture: AArch64
294 04:43:49.412815 output: Hash algo: crc32
295 04:43:49.412866 output: Hash value: cc4352de
296 04:43:49.412917 output: Image 2 (ramdisk-1)
297 04:43:49.412968 output: Description: unavailable
298 04:43:49.413018 output: Created: Sun Feb 4 04:43:49 2024
299 04:43:49.413069 output: Type: RAMDisk Image
300 04:43:49.413120 output: Compression: Unknown Compression
301 04:43:49.413171 output: Data Size: 17800695 Bytes = 17383.49 KiB = 16.98 MiB
302 04:43:49.413222 output: Architecture: AArch64
303 04:43:49.413272 output: OS: Linux
304 04:43:49.413323 output: Load Address: unavailable
305 04:43:49.413374 output: Entry Point: unavailable
306 04:43:49.413424 output: Hash algo: crc32
307 04:43:49.413475 output: Hash value: 0405da18
308 04:43:49.413526 output: Default Configuration: 'conf-1'
309 04:43:49.413577 output: Configuration 0 (conf-1)
310 04:43:49.413628 output: Description: mt8192-asurada-spherion-r0
311 04:43:49.413678 output: Kernel: kernel-1
312 04:43:49.413729 output: Init Ramdisk: ramdisk-1
313 04:43:49.413780 output: FDT: fdt-1
314 04:43:49.413830 output: Loadables: kernel-1
315 04:43:49.413880 output:
316 04:43:49.414079 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 04:43:49.414175 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 04:43:49.414288 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 04:43:49.414376 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 04:43:49.414453 No LXC device requested
321 04:43:49.414531 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 04:43:49.414613 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 04:43:49.414693 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 04:43:49.414758 Checking files for TFTP limit of 4294967296 bytes.
325 04:43:49.415247 end: 1 tftp-deploy (duration 00:00:41) [common]
326 04:43:49.415350 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 04:43:49.415441 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 04:43:49.415563 substitutions:
329 04:43:49.415632 - {DTB}: 12699811/tftp-deploy-eb0jq5zd/dtb/mt8192-asurada-spherion-r0.dtb
330 04:43:49.415696 - {INITRD}: 12699811/tftp-deploy-eb0jq5zd/ramdisk/ramdisk.cpio.gz
331 04:43:49.415755 - {KERNEL}: 12699811/tftp-deploy-eb0jq5zd/kernel/Image
332 04:43:49.415812 - {LAVA_MAC}: None
333 04:43:49.415868 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12699811/extract-nfsrootfs-gta4j95_
334 04:43:49.415924 - {NFS_SERVER_IP}: 192.168.201.1
335 04:43:49.415977 - {PRESEED_CONFIG}: None
336 04:43:49.416032 - {PRESEED_LOCAL}: None
337 04:43:49.416086 - {RAMDISK}: 12699811/tftp-deploy-eb0jq5zd/ramdisk/ramdisk.cpio.gz
338 04:43:49.416140 - {ROOT_PART}: None
339 04:43:49.416193 - {ROOT}: None
340 04:43:49.416246 - {SERVER_IP}: 192.168.201.1
341 04:43:49.416299 - {TEE}: None
342 04:43:49.416351 Parsed boot commands:
343 04:43:49.416403 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 04:43:49.416585 Parsed boot commands: tftpboot 192.168.201.1 12699811/tftp-deploy-eb0jq5zd/kernel/image.itb 12699811/tftp-deploy-eb0jq5zd/kernel/cmdline
345 04:43:49.416671 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 04:43:49.416789 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 04:43:49.416880 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 04:43:49.416965 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 04:43:49.417037 Not connected, no need to disconnect.
350 04:43:49.417109 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 04:43:49.417185 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 04:43:49.417249 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 04:43:49.421372 Setting prompt string to ['lava-test: # ']
354 04:43:49.421772 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 04:43:49.421890 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 04:43:49.422014 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 04:43:49.422135 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 04:43:49.422375 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 04:43:54.573813 >> Command sent successfully.
360 04:43:54.585409 Returned 0 in 5 seconds
361 04:43:54.686895 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 04:43:54.688504 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 04:43:54.689133 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 04:43:54.689701 Setting prompt string to 'Starting depthcharge on Spherion...'
366 04:43:54.690121 Changing prompt to 'Starting depthcharge on Spherion...'
367 04:43:54.690639 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 04:43:54.692046 [Enter `^Ec?' for help]
369 04:43:54.859534
370 04:43:54.860125
371 04:43:54.860573 F0: 102B 0000
372 04:43:54.860978
373 04:43:54.863308 F3: 1001 0000 [0200]
374 04:43:54.863852
375 04:43:54.864343 F3: 1001 0000
376 04:43:54.864856
377 04:43:54.865310 F7: 102D 0000
378 04:43:54.865750
379 04:43:54.866797 F1: 0000 0000
380 04:43:54.867276
381 04:43:54.867763 V0: 0000 0000 [0001]
382 04:43:54.868335
383 04:43:54.870983 00: 0007 8000
384 04:43:54.871487
385 04:43:54.871973 01: 0000 0000
386 04:43:54.872437
387 04:43:54.872983 BP: 0C00 0209 [0000]
388 04:43:54.873435
389 04:43:54.874295 G0: 1182 0000
390 04:43:54.874705
391 04:43:54.875149 EC: 0000 0021 [4000]
392 04:43:54.875583
393 04:43:54.878678 S7: 0000 0000 [0000]
394 04:43:54.879156
395 04:43:54.879639 CC: 0000 0000 [0001]
396 04:43:54.880095
397 04:43:54.880910 T0: 0000 0040 [010F]
398 04:43:54.881318
399 04:43:54.881765 Jump to BL
400 04:43:54.882199
401 04:43:54.906797
402 04:43:54.907370
403 04:43:54.907865
404 04:43:54.913856 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 04:43:54.916846 ARM64: Exception handlers installed.
406 04:43:54.920358 ARM64: Testing exception
407 04:43:54.924033 ARM64: Done test exception
408 04:43:54.930130 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 04:43:54.940302 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 04:43:54.947465 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 04:43:54.957484 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 04:43:54.963906 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 04:43:54.974957 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 04:43:54.985263 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 04:43:54.992117 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 04:43:55.009738 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 04:43:55.013734 WDT: Last reset was cold boot
418 04:43:55.016071 SPI1(PAD0) initialized at 2873684 Hz
419 04:43:55.019581 SPI5(PAD0) initialized at 992727 Hz
420 04:43:55.023115 VBOOT: Loading verstage.
421 04:43:55.029642 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 04:43:55.033311 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 04:43:55.036363 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 04:43:55.039888 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 04:43:55.047576 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 04:43:55.053916 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 04:43:55.064338 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 04:43:55.064947
429 04:43:55.065439
430 04:43:55.076594 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 04:43:55.078269 ARM64: Exception handlers installed.
432 04:43:55.082174 ARM64: Testing exception
433 04:43:55.082752 ARM64: Done test exception
434 04:43:55.088085 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 04:43:55.092507 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 04:43:55.105691 Probing TPM: . done!
437 04:43:55.106265 TPM ready after 0 ms
438 04:43:55.112628 Connected to device vid:did:rid of 1ae0:0028:00
439 04:43:55.118995 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 04:43:55.123241 Initialized TPM device CR50 revision 0
441 04:43:55.172968 tlcl_send_startup: Startup return code is 0
442 04:43:55.173535 TPM: setup succeeded
443 04:43:55.184773 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 04:43:55.193952 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 04:43:55.203723 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 04:43:55.212608 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 04:43:55.216259 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 04:43:55.219343 in-header: 03 07 00 00 08 00 00 00
449 04:43:55.222728 in-data: aa e4 47 04 13 02 00 00
450 04:43:55.226280 Chrome EC: UHEPI supported
451 04:43:55.232751 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 04:43:55.236484 in-header: 03 9d 00 00 08 00 00 00
453 04:43:55.239594 in-data: 10 20 20 08 00 00 00 00
454 04:43:55.240056 Phase 1
455 04:43:55.243050 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 04:43:55.249860 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 04:43:55.256535 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 04:43:55.259277 Recovery requested (1009000e)
459 04:43:55.263249 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 04:43:55.271590 tlcl_extend: response is 0
461 04:43:55.279203 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 04:43:55.285196 tlcl_extend: response is 0
463 04:43:55.291252 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 04:43:55.312520 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 04:43:55.319384 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 04:43:55.319952
467 04:43:55.320328
468 04:43:55.328591 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 04:43:55.332237 ARM64: Exception handlers installed.
470 04:43:55.335784 ARM64: Testing exception
471 04:43:55.336356 ARM64: Done test exception
472 04:43:55.358019 pmic_efuse_setting: Set efuses in 11 msecs
473 04:43:55.361187 pmwrap_interface_init: Select PMIF_VLD_RDY
474 04:43:55.367864 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 04:43:55.371145 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 04:43:55.378682 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 04:43:55.381611 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 04:43:55.385426 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 04:43:55.392792 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 04:43:55.396306 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 04:43:55.400359 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 04:43:55.406745 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 04:43:55.409462 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 04:43:55.416937 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 04:43:55.419866 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 04:43:55.422903 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 04:43:55.431092 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 04:43:55.436425 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 04:43:55.442571 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 04:43:55.446401 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 04:43:55.453437 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 04:43:55.457200 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 04:43:55.464203 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 04:43:55.470780 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 04:43:55.474538 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 04:43:55.480746 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 04:43:55.486899 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 04:43:55.491416 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 04:43:55.497234 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 04:43:55.503722 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 04:43:55.506779 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 04:43:55.510775 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 04:43:55.517202 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 04:43:55.520348 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 04:43:55.526900 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 04:43:55.530458 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 04:43:55.537324 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 04:43:55.539965 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 04:43:55.546694 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 04:43:55.553959 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 04:43:55.557067 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 04:43:55.560840 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 04:43:55.566469 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 04:43:55.570369 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 04:43:55.574173 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 04:43:55.581107 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 04:43:55.583029 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 04:43:55.586877 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 04:43:55.594058 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 04:43:55.597060 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 04:43:55.600301 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 04:43:55.603539 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 04:43:55.610013 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 04:43:55.614583 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 04:43:55.620090 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 04:43:55.630366 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 04:43:55.633329 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 04:43:55.643735 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 04:43:55.651086 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 04:43:55.653316 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 04:43:55.660112 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 04:43:55.663709 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 04:43:55.670617 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 04:43:55.677575 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 04:43:55.680937 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 04:43:55.683337 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 04:43:55.694692 [RTC]rtc_get_frequency_meter,154: input=15, output=765
538 04:43:55.704338 [RTC]rtc_get_frequency_meter,154: input=23, output=948
539 04:43:55.713948 [RTC]rtc_get_frequency_meter,154: input=19, output=857
540 04:43:55.724049 [RTC]rtc_get_frequency_meter,154: input=17, output=810
541 04:43:55.733917 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 04:43:55.742598 [RTC]rtc_get_frequency_meter,154: input=16, output=787
543 04:43:55.752751 [RTC]rtc_get_frequency_meter,154: input=17, output=810
544 04:43:55.754701 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 04:43:55.762809 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 04:43:55.765691 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 04:43:55.769228 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 04:43:55.775558 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 04:43:55.779522 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 04:43:55.783050 ADC[4]: Raw value=670432 ID=5
551 04:43:55.783616 ADC[3]: Raw value=212917 ID=1
552 04:43:55.785478 RAM Code: 0x51
553 04:43:55.788623 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 04:43:55.795653 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 04:43:55.803324 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 04:43:55.808779 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 04:43:55.812127 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 04:43:55.815676 in-header: 03 07 00 00 08 00 00 00
559 04:43:55.818765 in-data: aa e4 47 04 13 02 00 00
560 04:43:55.822302 Chrome EC: UHEPI supported
561 04:43:55.829367 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 04:43:55.832182 in-header: 03 d5 00 00 08 00 00 00
563 04:43:55.835227 in-data: 98 20 60 08 00 00 00 00
564 04:43:55.838680 MRC: failed to locate region type 0.
565 04:43:55.845308 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 04:43:55.849713 DRAM-K: Running full calibration
567 04:43:55.851835 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 04:43:55.855456 header.status = 0x0
569 04:43:55.858656 header.version = 0x6 (expected: 0x6)
570 04:43:55.862769 header.size = 0xd00 (expected: 0xd00)
571 04:43:55.863343 header.flags = 0x0
572 04:43:55.868456 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 04:43:55.887572 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
574 04:43:55.894085 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 04:43:55.897212 dram_init: ddr_geometry: 0
576 04:43:55.897678 [EMI] MDL number = 0
577 04:43:55.900597 [EMI] Get MDL freq = 0
578 04:43:55.905252 dram_init: ddr_type: 0
579 04:43:55.905818 is_discrete_lpddr4: 1
580 04:43:55.907797 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 04:43:55.908375
582 04:43:55.908803
583 04:43:55.911381 [Bian_co] ETT version 0.0.0.1
584 04:43:55.914710 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 04:43:55.915180
586 04:43:55.922317 dramc_set_vcore_voltage set vcore to 650000
587 04:43:55.922891 Read voltage for 800, 4
588 04:43:55.925564 Vio18 = 0
589 04:43:55.926048 Vcore = 650000
590 04:43:55.926422 Vdram = 0
591 04:43:55.926768 Vddq = 0
592 04:43:55.928033 Vmddr = 0
593 04:43:55.928498 dram_init: config_dvfs: 1
594 04:43:55.935539 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 04:43:55.942227 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 04:43:55.944886 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 04:43:55.948691 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 04:43:55.951566 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 04:43:55.954516 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 04:43:55.958356 MEM_TYPE=3, freq_sel=18
601 04:43:55.961645 sv_algorithm_assistance_LP4_1600
602 04:43:55.964611 ============ PULL DRAM RESETB DOWN ============
603 04:43:55.968270 ========== PULL DRAM RESETB DOWN end =========
604 04:43:55.974865 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 04:43:55.978192 ===================================
606 04:43:55.978658 LPDDR4 DRAM CONFIGURATION
607 04:43:55.981927 ===================================
608 04:43:55.985674 EX_ROW_EN[0] = 0x0
609 04:43:55.986145 EX_ROW_EN[1] = 0x0
610 04:43:55.988090 LP4Y_EN = 0x0
611 04:43:55.988555 WORK_FSP = 0x0
612 04:43:55.991620 WL = 0x2
613 04:43:55.995301 RL = 0x2
614 04:43:55.995865 BL = 0x2
615 04:43:55.998314 RPST = 0x0
616 04:43:55.998772 RD_PRE = 0x0
617 04:43:56.001267 WR_PRE = 0x1
618 04:43:56.001725 WR_PST = 0x0
619 04:43:56.004928 DBI_WR = 0x0
620 04:43:56.005388 DBI_RD = 0x0
621 04:43:56.008448 OTF = 0x1
622 04:43:56.011916 ===================================
623 04:43:56.015800 ===================================
624 04:43:56.016543 ANA top config
625 04:43:56.017780 ===================================
626 04:43:56.021249 DLL_ASYNC_EN = 0
627 04:43:56.024587 ALL_SLAVE_EN = 1
628 04:43:56.025196 NEW_RANK_MODE = 1
629 04:43:56.027971 DLL_IDLE_MODE = 1
630 04:43:56.031302 LP45_APHY_COMB_EN = 1
631 04:43:56.034758 TX_ODT_DIS = 1
632 04:43:56.037852 NEW_8X_MODE = 1
633 04:43:56.038426 ===================================
634 04:43:56.041568 ===================================
635 04:43:56.044570 data_rate = 1600
636 04:43:56.047498 CKR = 1
637 04:43:56.051594 DQ_P2S_RATIO = 8
638 04:43:56.054074 ===================================
639 04:43:56.057567 CA_P2S_RATIO = 8
640 04:43:56.061169 DQ_CA_OPEN = 0
641 04:43:56.064686 DQ_SEMI_OPEN = 0
642 04:43:56.065296 CA_SEMI_OPEN = 0
643 04:43:56.067852 CA_FULL_RATE = 0
644 04:43:56.070888 DQ_CKDIV4_EN = 1
645 04:43:56.074677 CA_CKDIV4_EN = 1
646 04:43:56.077850 CA_PREDIV_EN = 0
647 04:43:56.078326 PH8_DLY = 0
648 04:43:56.080778 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 04:43:56.084899 DQ_AAMCK_DIV = 4
650 04:43:56.087887 CA_AAMCK_DIV = 4
651 04:43:56.091253 CA_ADMCK_DIV = 4
652 04:43:56.094774 DQ_TRACK_CA_EN = 0
653 04:43:56.098558 CA_PICK = 800
654 04:43:56.099187 CA_MCKIO = 800
655 04:43:56.100926 MCKIO_SEMI = 0
656 04:43:56.104507 PLL_FREQ = 3068
657 04:43:56.107782 DQ_UI_PI_RATIO = 32
658 04:43:56.111051 CA_UI_PI_RATIO = 0
659 04:43:56.114410 ===================================
660 04:43:56.117970 ===================================
661 04:43:56.121237 memory_type:LPDDR4
662 04:43:56.121805 GP_NUM : 10
663 04:43:56.124519 SRAM_EN : 1
664 04:43:56.125135 MD32_EN : 0
665 04:43:56.128062 ===================================
666 04:43:56.131744 [ANA_INIT] >>>>>>>>>>>>>>
667 04:43:56.134348 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 04:43:56.137721 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 04:43:56.140987 ===================================
670 04:43:56.144762 data_rate = 1600,PCW = 0X7600
671 04:43:56.147634 ===================================
672 04:43:56.151075 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 04:43:56.154672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 04:43:56.161482 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 04:43:56.164681 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 04:43:56.167799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 04:43:56.173986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 04:43:56.174559 [ANA_INIT] flow start
679 04:43:56.178281 [ANA_INIT] PLL >>>>>>>>
680 04:43:56.178752 [ANA_INIT] PLL <<<<<<<<
681 04:43:56.181131 [ANA_INIT] MIDPI >>>>>>>>
682 04:43:56.184136 [ANA_INIT] MIDPI <<<<<<<<
683 04:43:56.188469 [ANA_INIT] DLL >>>>>>>>
684 04:43:56.189130 [ANA_INIT] flow end
685 04:43:56.190737 ============ LP4 DIFF to SE enter ============
686 04:43:56.197213 ============ LP4 DIFF to SE exit ============
687 04:43:56.197678 [ANA_INIT] <<<<<<<<<<<<<
688 04:43:56.200602 [Flow] Enable top DCM control >>>>>
689 04:43:56.203993 [Flow] Enable top DCM control <<<<<
690 04:43:56.207327 Enable DLL master slave shuffle
691 04:43:56.214057 ==============================================================
692 04:43:56.214633 Gating Mode config
693 04:43:56.220863 ==============================================================
694 04:43:56.224416 Config description:
695 04:43:56.233887 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 04:43:56.241415 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 04:43:56.244162 SELPH_MODE 0: By rank 1: By Phase
698 04:43:56.251231 ==============================================================
699 04:43:56.254072 GAT_TRACK_EN = 1
700 04:43:56.254661 RX_GATING_MODE = 2
701 04:43:56.258009 RX_GATING_TRACK_MODE = 2
702 04:43:56.260533 SELPH_MODE = 1
703 04:43:56.264106 PICG_EARLY_EN = 1
704 04:43:56.267097 VALID_LAT_VALUE = 1
705 04:43:56.274126 ==============================================================
706 04:43:56.277234 Enter into Gating configuration >>>>
707 04:43:56.280833 Exit from Gating configuration <<<<
708 04:43:56.283730 Enter into DVFS_PRE_config >>>>>
709 04:43:56.293874 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 04:43:56.297064 Exit from DVFS_PRE_config <<<<<
711 04:43:56.301254 Enter into PICG configuration >>>>
712 04:43:56.303967 Exit from PICG configuration <<<<
713 04:43:56.307238 [RX_INPUT] configuration >>>>>
714 04:43:56.310416 [RX_INPUT] configuration <<<<<
715 04:43:56.313705 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 04:43:56.320669 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 04:43:56.327169 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 04:43:56.330460 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 04:43:56.337488 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 04:43:56.344336 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 04:43:56.347482 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 04:43:56.350609 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 04:43:56.357135 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 04:43:56.360511 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 04:43:56.363389 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 04:43:56.370873 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 04:43:56.374289 ===================================
728 04:43:56.374854 LPDDR4 DRAM CONFIGURATION
729 04:43:56.378050 ===================================
730 04:43:56.380360 EX_ROW_EN[0] = 0x0
731 04:43:56.380882 EX_ROW_EN[1] = 0x0
732 04:43:56.384773 LP4Y_EN = 0x0
733 04:43:56.387395 WORK_FSP = 0x0
734 04:43:56.387960 WL = 0x2
735 04:43:56.390487 RL = 0x2
736 04:43:56.391049 BL = 0x2
737 04:43:56.393341 RPST = 0x0
738 04:43:56.393921 RD_PRE = 0x0
739 04:43:56.397373 WR_PRE = 0x1
740 04:43:56.397936 WR_PST = 0x0
741 04:43:56.400607 DBI_WR = 0x0
742 04:43:56.401116 DBI_RD = 0x0
743 04:43:56.403762 OTF = 0x1
744 04:43:56.407008 ===================================
745 04:43:56.410537 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 04:43:56.414303 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 04:43:56.420046 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 04:43:56.424149 ===================================
749 04:43:56.424756 LPDDR4 DRAM CONFIGURATION
750 04:43:56.426999 ===================================
751 04:43:56.430573 EX_ROW_EN[0] = 0x10
752 04:43:56.431139 EX_ROW_EN[1] = 0x0
753 04:43:56.433061 LP4Y_EN = 0x0
754 04:43:56.437004 WORK_FSP = 0x0
755 04:43:56.437749 WL = 0x2
756 04:43:56.441626 RL = 0x2
757 04:43:56.442086 BL = 0x2
758 04:43:56.443439 RPST = 0x0
759 04:43:56.443900 RD_PRE = 0x0
760 04:43:56.447276 WR_PRE = 0x1
761 04:43:56.447840 WR_PST = 0x0
762 04:43:56.450795 DBI_WR = 0x0
763 04:43:56.451361 DBI_RD = 0x0
764 04:43:56.453332 OTF = 0x1
765 04:43:56.456406 ===================================
766 04:43:56.460879 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 04:43:56.466303 nWR fixed to 40
768 04:43:56.468695 [ModeRegInit_LP4] CH0 RK0
769 04:43:56.469212 [ModeRegInit_LP4] CH0 RK1
770 04:43:56.472520 [ModeRegInit_LP4] CH1 RK0
771 04:43:56.475531 [ModeRegInit_LP4] CH1 RK1
772 04:43:56.476088 match AC timing 12
773 04:43:56.482183 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 04:43:56.485548 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 04:43:56.489221 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 04:43:56.495706 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 04:43:56.499260 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 04:43:56.499857 [EMI DOE] emi_dcm 0
779 04:43:56.506399 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 04:43:56.506971 ==
781 04:43:56.508835 Dram Type= 6, Freq= 0, CH_0, rank 0
782 04:43:56.511840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 04:43:56.512303 ==
784 04:43:56.518967 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 04:43:56.525534 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 04:43:56.533243 [CA 0] Center 37 (7~68) winsize 62
787 04:43:56.536090 [CA 1] Center 37 (7~68) winsize 62
788 04:43:56.539486 [CA 2] Center 35 (4~66) winsize 63
789 04:43:56.543050 [CA 3] Center 35 (4~66) winsize 63
790 04:43:56.546173 [CA 4] Center 34 (4~65) winsize 62
791 04:43:56.549108 [CA 5] Center 33 (3~64) winsize 62
792 04:43:56.549594
793 04:43:56.552581 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 04:43:56.553105
795 04:43:56.556014 [CATrainingPosCal] consider 1 rank data
796 04:43:56.559354 u2DelayCellTimex100 = 270/100 ps
797 04:43:56.562948 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 04:43:56.566060 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 04:43:56.573142 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
800 04:43:56.576702 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 04:43:56.579217 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
802 04:43:56.583676 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 04:43:56.584140
804 04:43:56.586751 CA PerBit enable=1, Macro0, CA PI delay=33
805 04:43:56.587315
806 04:43:56.589493 [CBTSetCACLKResult] CA Dly = 33
807 04:43:56.589951 CS Dly: 5 (0~36)
808 04:43:56.592772 ==
809 04:43:56.595947 Dram Type= 6, Freq= 0, CH_0, rank 1
810 04:43:56.599624 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 04:43:56.600103 ==
812 04:43:56.602512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 04:43:56.609383 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 04:43:56.618918 [CA 0] Center 37 (7~68) winsize 62
815 04:43:56.621916 [CA 1] Center 37 (7~68) winsize 62
816 04:43:56.626267 [CA 2] Center 35 (5~66) winsize 62
817 04:43:56.629181 [CA 3] Center 35 (5~66) winsize 62
818 04:43:56.632279 [CA 4] Center 33 (3~64) winsize 62
819 04:43:56.635852 [CA 5] Center 34 (3~65) winsize 63
820 04:43:56.636419
821 04:43:56.638954 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 04:43:56.639523
823 04:43:56.641869 [CATrainingPosCal] consider 2 rank data
824 04:43:56.646821 u2DelayCellTimex100 = 270/100 ps
825 04:43:56.649014 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 04:43:56.652273 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 04:43:56.659027 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 04:43:56.662619 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
829 04:43:56.666432 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
830 04:43:56.668655 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 04:43:56.669239
832 04:43:56.672195 CA PerBit enable=1, Macro0, CA PI delay=33
833 04:43:56.672659
834 04:43:56.675358 [CBTSetCACLKResult] CA Dly = 33
835 04:43:56.675920 CS Dly: 5 (0~37)
836 04:43:56.676295
837 04:43:56.678889 ----->DramcWriteLeveling(PI) begin...
838 04:43:56.682826 ==
839 04:43:56.685160 Dram Type= 6, Freq= 0, CH_0, rank 0
840 04:43:56.688880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 04:43:56.689356 ==
842 04:43:56.692448 Write leveling (Byte 0): 28 => 28
843 04:43:56.695610 Write leveling (Byte 1): 28 => 28
844 04:43:56.699237 DramcWriteLeveling(PI) end<-----
845 04:43:56.699705
846 04:43:56.700072 ==
847 04:43:56.702032 Dram Type= 6, Freq= 0, CH_0, rank 0
848 04:43:56.705437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 04:43:56.705905 ==
850 04:43:56.708493 [Gating] SW mode calibration
851 04:43:56.715114 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 04:43:56.718801 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 04:43:56.726383 0 6 0 | B1->B0 | 3232 3030 | 1 1 | (1 1) (1 0)
854 04:43:56.728566 0 6 4 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
855 04:43:56.731823 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 04:43:56.738689 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 04:43:56.741549 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 04:43:56.745720 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 04:43:56.752389 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 04:43:56.755777 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 04:43:56.758912 0 7 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
862 04:43:56.765228 0 7 4 | B1->B0 | 3a3a 4242 | 0 0 | (0 0) (0 0)
863 04:43:56.769135 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 04:43:56.771735 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 04:43:56.778479 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 04:43:56.781641 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 04:43:56.785323 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 04:43:56.791572 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 04:43:56.795116 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 04:43:56.798759 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
871 04:43:56.805014 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 04:43:56.808507 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 04:43:56.811787 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 04:43:56.815227 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 04:43:56.821887 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 04:43:56.825593 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 04:43:56.828426 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 04:43:56.835983 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 04:43:56.839011 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 04:43:56.841894 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 04:43:56.849665 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 04:43:56.853012 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 04:43:56.855940 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 04:43:56.862117 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 04:43:56.865493 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
886 04:43:56.868610 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
887 04:43:56.873174 Total UI for P1: 0, mck2ui 16
888 04:43:56.875883 best dqsien dly found for B1: ( 0, 10, 0)
889 04:43:56.882891 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
890 04:43:56.883453 Total UI for P1: 0, mck2ui 16
891 04:43:56.888432 best dqsien dly found for B0: ( 0, 10, 2)
892 04:43:56.892696 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
893 04:43:56.895607 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
894 04:43:56.896306
895 04:43:56.898723 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
896 04:43:56.902274 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
897 04:43:56.905791 [Gating] SW calibration Done
898 04:43:56.906351 ==
899 04:43:56.909246 Dram Type= 6, Freq= 0, CH_0, rank 0
900 04:43:56.912530 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
901 04:43:56.913052 ==
902 04:43:56.913428 RX Vref Scan: 0
903 04:43:56.913779
904 04:43:56.915998 RX Vref 0 -> 0, step: 1
905 04:43:56.916460
906 04:43:56.919555 RX Delay -130 -> 252, step: 16
907 04:43:56.922893 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
908 04:43:56.926639 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
909 04:43:56.932932 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
910 04:43:56.935746 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
911 04:43:56.940250 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
912 04:43:56.943047 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
913 04:43:56.946443 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
914 04:43:56.953318 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
915 04:43:56.957223 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
916 04:43:56.959351 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
917 04:43:56.962844 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
918 04:43:56.966485 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
919 04:43:56.973348 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
920 04:43:56.976582 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
921 04:43:56.980057 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
922 04:43:56.983240 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
923 04:43:56.983711 ==
924 04:43:56.986089 Dram Type= 6, Freq= 0, CH_0, rank 0
925 04:43:56.992843 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
926 04:43:56.993438 ==
927 04:43:56.993852 DQS Delay:
928 04:43:56.994219 DQS0 = 0, DQS1 = 0
929 04:43:56.996676 DQM Delay:
930 04:43:56.997198 DQM0 = 81, DQM1 = 74
931 04:43:57.000498 DQ Delay:
932 04:43:57.004365 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
933 04:43:57.005004 DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93
934 04:43:57.005788 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
935 04:43:57.010224 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
936 04:43:57.012448
937 04:43:57.012959
938 04:43:57.013330 ==
939 04:43:57.016225 Dram Type= 6, Freq= 0, CH_0, rank 0
940 04:43:57.019224 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
941 04:43:57.019689 ==
942 04:43:57.020058
943 04:43:57.020398
944 04:43:57.022715 TX Vref Scan disable
945 04:43:57.023301 == TX Byte 0 ==
946 04:43:57.029070 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
947 04:43:57.032484 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
948 04:43:57.033003 == TX Byte 1 ==
949 04:43:57.039689 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
950 04:43:57.042595 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
951 04:43:57.043063 ==
952 04:43:57.045922 Dram Type= 6, Freq= 0, CH_0, rank 0
953 04:43:57.049675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
954 04:43:57.050147 ==
955 04:43:57.062860 TX Vref=22, minBit 0, minWin=27, winSum=443
956 04:43:57.065853 TX Vref=24, minBit 2, minWin=27, winSum=448
957 04:43:57.070373 TX Vref=26, minBit 4, minWin=27, winSum=451
958 04:43:57.073272 TX Vref=28, minBit 4, minWin=27, winSum=452
959 04:43:57.076773 TX Vref=30, minBit 4, minWin=27, winSum=453
960 04:43:57.080231 TX Vref=32, minBit 1, minWin=27, winSum=451
961 04:43:57.086196 [TxChooseVref] Worse bit 4, Min win 27, Win sum 453, Final Vref 30
962 04:43:57.086763
963 04:43:57.088936 Final TX Range 1 Vref 30
964 04:43:57.089406
965 04:43:57.089771 ==
966 04:43:57.092207 Dram Type= 6, Freq= 0, CH_0, rank 0
967 04:43:57.095792 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
968 04:43:57.096267 ==
969 04:43:57.096653
970 04:43:57.099874
971 04:43:57.100438 TX Vref Scan disable
972 04:43:57.102902 == TX Byte 0 ==
973 04:43:57.106421 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
974 04:43:57.110659 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
975 04:43:57.113268 == TX Byte 1 ==
976 04:43:57.116559 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
977 04:43:57.120455 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
978 04:43:57.121084
979 04:43:57.123285 [DATLAT]
980 04:43:57.123749 Freq=800, CH0 RK0
981 04:43:57.124121
982 04:43:57.126728 DATLAT Default: 0xa
983 04:43:57.127190 0, 0xFFFF, sum = 0
984 04:43:57.129083 1, 0xFFFF, sum = 0
985 04:43:57.129568 2, 0xFFFF, sum = 0
986 04:43:57.132865 3, 0xFFFF, sum = 0
987 04:43:57.133440 4, 0xFFFF, sum = 0
988 04:43:57.135951 5, 0xFFFF, sum = 0
989 04:43:57.136522 6, 0xFFFF, sum = 0
990 04:43:57.139467 7, 0xFFFF, sum = 0
991 04:43:57.139939 8, 0x0, sum = 1
992 04:43:57.143252 9, 0x0, sum = 2
993 04:43:57.143825 10, 0x0, sum = 3
994 04:43:57.146900 11, 0x0, sum = 4
995 04:43:57.147482 best_step = 9
996 04:43:57.147851
997 04:43:57.148197 ==
998 04:43:57.149483 Dram Type= 6, Freq= 0, CH_0, rank 0
999 04:43:57.155963 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1000 04:43:57.156431 ==
1001 04:43:57.156851 RX Vref Scan: 1
1002 04:43:57.157348
1003 04:43:57.159276 Set Vref Range= 32 -> 127
1004 04:43:57.159737
1005 04:43:57.163056 RX Vref 32 -> 127, step: 1
1006 04:43:57.163624
1007 04:43:57.164000 RX Delay -95 -> 252, step: 8
1008 04:43:57.164348
1009 04:43:57.166361 Set Vref, RX VrefLevel [Byte0]: 32
1010 04:43:57.169320 [Byte1]: 32
1011 04:43:57.173280
1012 04:43:57.173847 Set Vref, RX VrefLevel [Byte0]: 33
1013 04:43:57.176127 [Byte1]: 33
1014 04:43:57.180426
1015 04:43:57.181042 Set Vref, RX VrefLevel [Byte0]: 34
1016 04:43:57.184402 [Byte1]: 34
1017 04:43:57.189304
1018 04:43:57.189862 Set Vref, RX VrefLevel [Byte0]: 35
1019 04:43:57.191597 [Byte1]: 35
1020 04:43:57.196197
1021 04:43:57.197018 Set Vref, RX VrefLevel [Byte0]: 36
1022 04:43:57.199864 [Byte1]: 36
1023 04:43:57.204103
1024 04:43:57.204662 Set Vref, RX VrefLevel [Byte0]: 37
1025 04:43:57.207451 [Byte1]: 37
1026 04:43:57.211303
1027 04:43:57.211754 Set Vref, RX VrefLevel [Byte0]: 38
1028 04:43:57.216035 [Byte1]: 38
1029 04:43:57.218660
1030 04:43:57.219111 Set Vref, RX VrefLevel [Byte0]: 39
1031 04:43:57.221862 [Byte1]: 39
1032 04:43:57.226442
1033 04:43:57.226989 Set Vref, RX VrefLevel [Byte0]: 40
1034 04:43:57.229644 [Byte1]: 40
1035 04:43:57.234292
1036 04:43:57.234840 Set Vref, RX VrefLevel [Byte0]: 41
1037 04:43:57.237530 [Byte1]: 41
1038 04:43:57.241388
1039 04:43:57.241840 Set Vref, RX VrefLevel [Byte0]: 42
1040 04:43:57.244938 [Byte1]: 42
1041 04:43:57.249120
1042 04:43:57.249668 Set Vref, RX VrefLevel [Byte0]: 43
1043 04:43:57.253346 [Byte1]: 43
1044 04:43:57.256879
1045 04:43:57.257428 Set Vref, RX VrefLevel [Byte0]: 44
1046 04:43:57.260089 [Byte1]: 44
1047 04:43:57.264376
1048 04:43:57.264977 Set Vref, RX VrefLevel [Byte0]: 45
1049 04:43:57.268020 [Byte1]: 45
1050 04:43:57.271908
1051 04:43:57.272453 Set Vref, RX VrefLevel [Byte0]: 46
1052 04:43:57.275158 [Byte1]: 46
1053 04:43:57.280018
1054 04:43:57.280570 Set Vref, RX VrefLevel [Byte0]: 47
1055 04:43:57.282924 [Byte1]: 47
1056 04:43:57.287669
1057 04:43:57.288219 Set Vref, RX VrefLevel [Byte0]: 48
1058 04:43:57.290838 [Byte1]: 48
1059 04:43:57.294400
1060 04:43:57.294864 Set Vref, RX VrefLevel [Byte0]: 49
1061 04:43:57.298258 [Byte1]: 49
1062 04:43:57.302319
1063 04:43:57.302854 Set Vref, RX VrefLevel [Byte0]: 50
1064 04:43:57.305640 [Byte1]: 50
1065 04:43:57.310107
1066 04:43:57.310559 Set Vref, RX VrefLevel [Byte0]: 51
1067 04:43:57.313402 [Byte1]: 51
1068 04:43:57.317780
1069 04:43:57.318275 Set Vref, RX VrefLevel [Byte0]: 52
1070 04:43:57.320813 [Byte1]: 52
1071 04:43:57.325505
1072 04:43:57.326121 Set Vref, RX VrefLevel [Byte0]: 53
1073 04:43:57.328804 [Byte1]: 53
1074 04:43:57.333581
1075 04:43:57.334123 Set Vref, RX VrefLevel [Byte0]: 54
1076 04:43:57.336345 [Byte1]: 54
1077 04:43:57.340103
1078 04:43:57.340549 Set Vref, RX VrefLevel [Byte0]: 55
1079 04:43:57.344265 [Byte1]: 55
1080 04:43:57.347702
1081 04:43:57.348167 Set Vref, RX VrefLevel [Byte0]: 56
1082 04:43:57.351426 [Byte1]: 56
1083 04:43:57.355447
1084 04:43:57.355993 Set Vref, RX VrefLevel [Byte0]: 57
1085 04:43:57.358537 [Byte1]: 57
1086 04:43:57.362910
1087 04:43:57.363467 Set Vref, RX VrefLevel [Byte0]: 58
1088 04:43:57.366335 [Byte1]: 58
1089 04:43:57.370762
1090 04:43:57.371323 Set Vref, RX VrefLevel [Byte0]: 59
1091 04:43:57.373748 [Byte1]: 59
1092 04:43:57.378501
1093 04:43:57.379061 Set Vref, RX VrefLevel [Byte0]: 60
1094 04:43:57.382155 [Byte1]: 60
1095 04:43:57.385707
1096 04:43:57.386315 Set Vref, RX VrefLevel [Byte0]: 61
1097 04:43:57.389843 [Byte1]: 61
1098 04:43:57.393178
1099 04:43:57.393635 Set Vref, RX VrefLevel [Byte0]: 62
1100 04:43:57.396840 [Byte1]: 62
1101 04:43:57.401206
1102 04:43:57.401665 Set Vref, RX VrefLevel [Byte0]: 63
1103 04:43:57.404362 [Byte1]: 63
1104 04:43:57.408839
1105 04:43:57.409382 Set Vref, RX VrefLevel [Byte0]: 64
1106 04:43:57.411889 [Byte1]: 64
1107 04:43:57.416376
1108 04:43:57.416975 Set Vref, RX VrefLevel [Byte0]: 65
1109 04:43:57.419765 [Byte1]: 65
1110 04:43:57.424204
1111 04:43:57.424768 Set Vref, RX VrefLevel [Byte0]: 66
1112 04:43:57.427176 [Byte1]: 66
1113 04:43:57.431716
1114 04:43:57.432266 Set Vref, RX VrefLevel [Byte0]: 67
1115 04:43:57.435045 [Byte1]: 67
1116 04:43:57.439286
1117 04:43:57.439838 Set Vref, RX VrefLevel [Byte0]: 68
1118 04:43:57.442527 [Byte1]: 68
1119 04:43:57.446750
1120 04:43:57.447302 Set Vref, RX VrefLevel [Byte0]: 69
1121 04:43:57.451267 [Byte1]: 69
1122 04:43:57.454251
1123 04:43:57.454814 Set Vref, RX VrefLevel [Byte0]: 70
1124 04:43:57.457926 [Byte1]: 70
1125 04:43:57.462149
1126 04:43:57.462707 Set Vref, RX VrefLevel [Byte0]: 71
1127 04:43:57.465361 [Byte1]: 71
1128 04:43:57.469332
1129 04:43:57.469889 Set Vref, RX VrefLevel [Byte0]: 72
1130 04:43:57.472496 [Byte1]: 72
1131 04:43:57.477490
1132 04:43:57.478051 Final RX Vref Byte 0 = 52 to rank0
1133 04:43:57.480841 Final RX Vref Byte 1 = 54 to rank0
1134 04:43:57.483901 Final RX Vref Byte 0 = 52 to rank1
1135 04:43:57.486851 Final RX Vref Byte 1 = 54 to rank1==
1136 04:43:57.490074 Dram Type= 6, Freq= 0, CH_0, rank 0
1137 04:43:57.497020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1138 04:43:57.497645 ==
1139 04:43:57.498016 DQS Delay:
1140 04:43:57.498373 DQS0 = 0, DQS1 = 0
1141 04:43:57.500575 DQM Delay:
1142 04:43:57.501066 DQM0 = 83, DQM1 = 73
1143 04:43:57.504269 DQ Delay:
1144 04:43:57.507300 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1145 04:43:57.510372 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1146 04:43:57.514618 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1147 04:43:57.517018 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1148 04:43:57.517479
1149 04:43:57.517841
1150 04:43:57.523476 [DQSOSCAuto] RK0, (LSB)MR18= 0x3232, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1151 04:43:57.526750 CH0 RK0: MR19=606, MR18=3232
1152 04:43:57.534544 CH0_RK0: MR19=0x606, MR18=0x3232, DQSOSC=397, MR23=63, INC=93, DEC=62
1153 04:43:57.535109
1154 04:43:57.536577 ----->DramcWriteLeveling(PI) begin...
1155 04:43:57.537080 ==
1156 04:43:57.540585 Dram Type= 6, Freq= 0, CH_0, rank 1
1157 04:43:57.543688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1158 04:43:57.544249 ==
1159 04:43:57.547422 Write leveling (Byte 0): 31 => 31
1160 04:43:57.550596 Write leveling (Byte 1): 27 => 27
1161 04:43:57.554107 DramcWriteLeveling(PI) end<-----
1162 04:43:57.554667
1163 04:43:57.555029 ==
1164 04:43:57.556505 Dram Type= 6, Freq= 0, CH_0, rank 1
1165 04:43:57.560285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1166 04:43:57.560772 ==
1167 04:43:57.565648 [Gating] SW mode calibration
1168 04:43:57.570946 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1169 04:43:57.576886 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1170 04:43:57.580562 0 6 0 | B1->B0 | 3232 3232 | 1 0 | (1 0) (0 0)
1171 04:43:57.583625 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 04:43:57.590002 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 04:43:57.593853 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 04:43:57.597275 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 04:43:57.603365 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 04:43:57.607129 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 04:43:57.609854 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 04:43:57.617231 0 7 0 | B1->B0 | 2525 2e2e | 0 1 | (0 0) (0 0)
1179 04:43:57.620084 0 7 4 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
1180 04:43:57.623644 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1181 04:43:57.630878 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1182 04:43:57.634095 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 04:43:57.637095 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 04:43:57.645694 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 04:43:57.648281 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 04:43:57.650607 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 04:43:57.653953 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1188 04:43:57.659964 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1189 04:43:57.664233 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 04:43:57.667470 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 04:43:57.673671 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 04:43:57.676954 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 04:43:57.680405 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 04:43:57.686768 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 04:43:57.690117 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 04:43:57.693944 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 04:43:57.700431 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 04:43:57.703929 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 04:43:57.707895 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 04:43:57.714027 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 04:43:57.716762 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 04:43:57.720118 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1203 04:43:57.727174 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 04:43:57.727821 Total UI for P1: 0, mck2ui 16
1205 04:43:57.730482 best dqsien dly found for B0: ( 0, 10, 0)
1206 04:43:57.733435 Total UI for P1: 0, mck2ui 16
1207 04:43:57.736882 best dqsien dly found for B1: ( 0, 10, 0)
1208 04:43:57.740872 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1209 04:43:57.743857 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1210 04:43:57.746948
1211 04:43:57.750490 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1212 04:43:57.754361 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1213 04:43:57.756957 [Gating] SW calibration Done
1214 04:43:57.757413 ==
1215 04:43:57.760512 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 04:43:57.763740 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1217 04:43:57.764195 ==
1218 04:43:57.764550 RX Vref Scan: 0
1219 04:43:57.764931
1220 04:43:57.767137 RX Vref 0 -> 0, step: 1
1221 04:43:57.767588
1222 04:43:57.770154 RX Delay -130 -> 252, step: 16
1223 04:43:57.774028 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1224 04:43:57.776840 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1225 04:43:57.783677 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1226 04:43:57.827600 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1227 04:43:57.828264 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1228 04:43:57.829301 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1229 04:43:57.829693 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1230 04:43:57.830132 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1231 04:43:57.830536 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1232 04:43:57.830878 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1233 04:43:57.831191 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1234 04:43:57.831568 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1235 04:43:57.831888 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1236 04:43:57.832196 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1237 04:43:57.848384 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1238 04:43:57.849100 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1239 04:43:57.849820 ==
1240 04:43:57.850188 Dram Type= 6, Freq= 0, CH_0, rank 1
1241 04:43:57.850692 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1242 04:43:57.851042 ==
1243 04:43:57.851362 DQS Delay:
1244 04:43:57.851673 DQS0 = 0, DQS1 = 0
1245 04:43:57.852455 DQM Delay:
1246 04:43:57.852902 DQM0 = 81, DQM1 = 72
1247 04:43:57.853233 DQ Delay:
1248 04:43:57.854813 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
1249 04:43:57.855267 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1250 04:43:57.858533 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1251 04:43:57.861782 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
1252 04:43:57.862249
1253 04:43:57.862603
1254 04:43:57.862937 ==
1255 04:43:57.865011 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 04:43:57.868837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1257 04:43:57.872086 ==
1258 04:43:57.872634
1259 04:43:57.873061
1260 04:43:57.873402 TX Vref Scan disable
1261 04:43:57.875808 == TX Byte 0 ==
1262 04:43:57.879069 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1263 04:43:57.882705 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1264 04:43:57.885377 == TX Byte 1 ==
1265 04:43:57.888473 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1266 04:43:57.892103 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1267 04:43:57.895635 ==
1268 04:43:57.896200 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 04:43:57.902320 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1270 04:43:57.902882 ==
1271 04:43:57.914478 TX Vref=22, minBit 8, minWin=27, winSum=445
1272 04:43:57.918038 TX Vref=24, minBit 14, minWin=27, winSum=452
1273 04:43:57.921333 TX Vref=26, minBit 14, minWin=27, winSum=451
1274 04:43:57.924984 TX Vref=28, minBit 2, minWin=28, winSum=455
1275 04:43:57.928075 TX Vref=30, minBit 1, minWin=28, winSum=457
1276 04:43:57.934615 TX Vref=32, minBit 2, minWin=28, winSum=459
1277 04:43:57.937910 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 32
1278 04:43:57.938462
1279 04:43:57.942601 Final TX Range 1 Vref 32
1280 04:43:57.943162
1281 04:43:57.943522 ==
1282 04:43:57.944537 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 04:43:57.947897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1284 04:43:57.948450 ==
1285 04:43:57.950915
1286 04:43:57.951459
1287 04:43:57.951820 TX Vref Scan disable
1288 04:43:57.954694 == TX Byte 0 ==
1289 04:43:57.959078 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1290 04:43:57.960992 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1291 04:43:57.965363 == TX Byte 1 ==
1292 04:43:57.969236 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1293 04:43:57.974864 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1294 04:43:57.975321
1295 04:43:57.975678 [DATLAT]
1296 04:43:57.976010 Freq=800, CH0 RK1
1297 04:43:57.976334
1298 04:43:57.977441 DATLAT Default: 0x9
1299 04:43:57.977892 0, 0xFFFF, sum = 0
1300 04:43:57.981134 1, 0xFFFF, sum = 0
1301 04:43:57.981693 2, 0xFFFF, sum = 0
1302 04:43:57.984794 3, 0xFFFF, sum = 0
1303 04:43:57.985354 4, 0xFFFF, sum = 0
1304 04:43:57.987708 5, 0xFFFF, sum = 0
1305 04:43:57.991047 6, 0xFFFF, sum = 0
1306 04:43:57.991505 7, 0xFFFF, sum = 0
1307 04:43:57.991888 8, 0x0, sum = 1
1308 04:43:57.995077 9, 0x0, sum = 2
1309 04:43:57.995640 10, 0x0, sum = 3
1310 04:43:57.997657 11, 0x0, sum = 4
1311 04:43:57.998115 best_step = 9
1312 04:43:57.998601
1313 04:43:57.998944 ==
1314 04:43:58.001059 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 04:43:58.007645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1316 04:43:58.008200 ==
1317 04:43:58.008562 RX Vref Scan: 0
1318 04:43:58.008947
1319 04:43:58.011639 RX Vref 0 -> 0, step: 1
1320 04:43:58.012090
1321 04:43:58.014466 RX Delay -111 -> 252, step: 8
1322 04:43:58.018116 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1323 04:43:58.021562 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1324 04:43:58.027988 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1325 04:43:58.031478 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1326 04:43:58.034533 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1327 04:43:58.037802 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1328 04:43:58.041360 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1329 04:43:58.045115 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1330 04:43:58.051404 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1331 04:43:58.055700 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1332 04:43:58.058216 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1333 04:43:58.061109 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1334 04:43:58.067920 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1335 04:43:58.071069 iDelay=217, Bit 13, Center 76 (-39 ~ 192) 232
1336 04:43:58.075227 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1337 04:43:58.078235 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1338 04:43:58.078799 ==
1339 04:43:58.081326 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 04:43:58.084629 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1341 04:43:58.087940 ==
1342 04:43:58.088666 DQS Delay:
1343 04:43:58.089110 DQS0 = 0, DQS1 = 0
1344 04:43:58.090938 DQM Delay:
1345 04:43:58.091389 DQM0 = 85, DQM1 = 73
1346 04:43:58.094297 DQ Delay:
1347 04:43:58.097750 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1348 04:43:58.098216 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1349 04:43:58.100901 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =64
1350 04:43:58.105201 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1351 04:43:58.107801
1352 04:43:58.108364
1353 04:43:58.114781 [DQSOSCAuto] RK1, (LSB)MR18= 0x4141, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1354 04:43:58.117682 CH0 RK1: MR19=606, MR18=4141
1355 04:43:58.124521 CH0_RK1: MR19=0x606, MR18=0x4141, DQSOSC=393, MR23=63, INC=95, DEC=63
1356 04:43:58.127581 [RxdqsGatingPostProcess] freq 800
1357 04:43:58.131083 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1358 04:43:58.134776 Pre-setting of DQS Precalculation
1359 04:43:58.137634 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1360 04:43:58.140800 ==
1361 04:43:58.144222 Dram Type= 6, Freq= 0, CH_1, rank 0
1362 04:43:58.148017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1363 04:43:58.148583 ==
1364 04:43:58.150780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1365 04:43:58.157499 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1366 04:43:58.167090 [CA 0] Center 37 (6~68) winsize 63
1367 04:43:58.170463 [CA 1] Center 37 (6~68) winsize 63
1368 04:43:58.173704 [CA 2] Center 34 (4~65) winsize 62
1369 04:43:58.177294 [CA 3] Center 34 (4~65) winsize 62
1370 04:43:58.181129 [CA 4] Center 33 (3~64) winsize 62
1371 04:43:58.183807 [CA 5] Center 33 (3~64) winsize 62
1372 04:43:58.184081
1373 04:43:58.187289 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1374 04:43:58.187560
1375 04:43:58.190933 [CATrainingPosCal] consider 1 rank data
1376 04:43:58.193843 u2DelayCellTimex100 = 270/100 ps
1377 04:43:58.197018 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1378 04:43:58.200745 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1379 04:43:58.207143 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1380 04:43:58.210383 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1381 04:43:58.213572 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1382 04:43:58.218185 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1383 04:43:58.218733
1384 04:43:58.220877 CA PerBit enable=1, Macro0, CA PI delay=33
1385 04:43:58.221425
1386 04:43:58.223865 [CBTSetCACLKResult] CA Dly = 33
1387 04:43:58.224415 CS Dly: 5 (0~36)
1388 04:43:58.227585 ==
1389 04:43:58.228131 Dram Type= 6, Freq= 0, CH_1, rank 1
1390 04:43:58.233909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1391 04:43:58.234445 ==
1392 04:43:58.237508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1393 04:43:58.243881 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1394 04:43:58.253488 [CA 0] Center 37 (6~68) winsize 63
1395 04:43:58.256771 [CA 1] Center 37 (6~68) winsize 63
1396 04:43:58.259970 [CA 2] Center 34 (4~65) winsize 62
1397 04:43:58.263189 [CA 3] Center 34 (4~65) winsize 62
1398 04:43:58.266094 [CA 4] Center 33 (3~64) winsize 62
1399 04:43:58.269910 [CA 5] Center 33 (3~64) winsize 62
1400 04:43:58.270359
1401 04:43:58.273333 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1402 04:43:58.273884
1403 04:43:58.276506 [CATrainingPosCal] consider 2 rank data
1404 04:43:58.280088 u2DelayCellTimex100 = 270/100 ps
1405 04:43:58.283155 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1406 04:43:58.286489 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1407 04:43:58.293398 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1408 04:43:58.296856 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1409 04:43:58.300430 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1410 04:43:58.303769 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1411 04:43:58.304322
1412 04:43:58.307096 CA PerBit enable=1, Macro0, CA PI delay=33
1413 04:43:58.307652
1414 04:43:58.309419 [CBTSetCACLKResult] CA Dly = 33
1415 04:43:58.309876 CS Dly: 5 (0~36)
1416 04:43:58.310232
1417 04:43:58.313138 ----->DramcWriteLeveling(PI) begin...
1418 04:43:58.316476 ==
1419 04:43:58.319755 Dram Type= 6, Freq= 0, CH_1, rank 0
1420 04:43:58.323250 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1421 04:43:58.323820 ==
1422 04:43:58.326395 Write leveling (Byte 0): 24 => 24
1423 04:43:58.330438 Write leveling (Byte 1): 25 => 25
1424 04:43:58.333402 DramcWriteLeveling(PI) end<-----
1425 04:43:58.333860
1426 04:43:58.334220 ==
1427 04:43:58.336940 Dram Type= 6, Freq= 0, CH_1, rank 0
1428 04:43:58.340547 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1429 04:43:58.341152 ==
1430 04:43:58.343430 [Gating] SW mode calibration
1431 04:43:58.350278 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1432 04:43:58.353661 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1433 04:43:58.359526 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
1434 04:43:58.362793 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1435 04:43:58.366491 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1436 04:43:58.373139 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1437 04:43:58.376178 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1438 04:43:58.379567 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1439 04:43:58.386153 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 04:43:58.389898 0 6 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1441 04:43:58.392450 0 7 0 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
1442 04:43:58.399474 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1443 04:43:58.402996 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1444 04:43:58.405769 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1445 04:43:58.412520 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1446 04:43:58.416005 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1447 04:43:58.419123 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1448 04:43:58.425427 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1449 04:43:58.429864 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1450 04:43:58.432928 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1451 04:43:58.439356 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1452 04:43:58.442041 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1453 04:43:58.445480 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 04:43:58.452342 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 04:43:58.455608 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 04:43:58.459223 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 04:43:58.466289 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 04:43:58.468835 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 04:43:58.472235 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 04:43:58.478573 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 04:43:58.482801 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 04:43:58.486108 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 04:43:58.492411 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 04:43:58.495684 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1465 04:43:58.498625 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1466 04:43:58.502273 Total UI for P1: 0, mck2ui 16
1467 04:43:58.505915 best dqsien dly found for B0: ( 0, 9, 28)
1468 04:43:58.509090 Total UI for P1: 0, mck2ui 16
1469 04:43:58.514079 best dqsien dly found for B1: ( 0, 9, 30)
1470 04:43:58.515578 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1471 04:43:58.518929 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1472 04:43:58.519493
1473 04:43:58.522025 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1474 04:43:58.529335 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1475 04:43:58.529881 [Gating] SW calibration Done
1476 04:43:58.530247 ==
1477 04:43:58.532838 Dram Type= 6, Freq= 0, CH_1, rank 0
1478 04:43:58.539575 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1479 04:43:58.540163 ==
1480 04:43:58.540537 RX Vref Scan: 0
1481 04:43:58.540909
1482 04:43:58.542109 RX Vref 0 -> 0, step: 1
1483 04:43:58.542599
1484 04:43:58.545724 RX Delay -130 -> 252, step: 16
1485 04:43:58.548884 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1486 04:43:58.552162 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1487 04:43:58.556094 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1488 04:43:58.561822 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1489 04:43:58.565610 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1490 04:43:58.568778 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1491 04:43:58.573496 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1492 04:43:58.576041 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1493 04:43:58.582184 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1494 04:43:58.585941 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1495 04:43:58.588944 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1496 04:43:58.591976 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1497 04:43:58.595245 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1498 04:43:58.601982 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1499 04:43:58.605575 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1500 04:43:58.608449 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1501 04:43:58.608950 ==
1502 04:43:58.612471 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 04:43:58.615399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1504 04:43:58.615861 ==
1505 04:43:58.619712 DQS Delay:
1506 04:43:58.620267 DQS0 = 0, DQS1 = 0
1507 04:43:58.622027 DQM Delay:
1508 04:43:58.622485 DQM0 = 81, DQM1 = 74
1509 04:43:58.622845 DQ Delay:
1510 04:43:58.626359 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1511 04:43:58.628935 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1512 04:43:58.632903 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1513 04:43:58.635298 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1514 04:43:58.635857
1515 04:43:58.636215
1516 04:43:58.636552 ==
1517 04:43:58.639301 Dram Type= 6, Freq= 0, CH_1, rank 0
1518 04:43:58.645387 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1519 04:43:58.645955 ==
1520 04:43:58.646322
1521 04:43:58.646654
1522 04:43:58.646974 TX Vref Scan disable
1523 04:43:58.649414 == TX Byte 0 ==
1524 04:43:58.652693 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1525 04:43:58.656127 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1526 04:43:58.659267 == TX Byte 1 ==
1527 04:43:58.662732 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1528 04:43:58.665934 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1529 04:43:58.669268 ==
1530 04:43:58.672629 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 04:43:58.675426 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1532 04:43:58.675885 ==
1533 04:43:58.688588 TX Vref=22, minBit 3, minWin=27, winSum=448
1534 04:43:58.692019 TX Vref=24, minBit 3, minWin=27, winSum=449
1535 04:43:58.694429 TX Vref=26, minBit 0, minWin=28, winSum=452
1536 04:43:58.698896 TX Vref=28, minBit 0, minWin=28, winSum=460
1537 04:43:58.701805 TX Vref=30, minBit 0, minWin=28, winSum=457
1538 04:43:58.708108 TX Vref=32, minBit 0, minWin=28, winSum=457
1539 04:43:58.711480 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 28
1540 04:43:58.712103
1541 04:43:58.715062 Final TX Range 1 Vref 28
1542 04:43:58.715535
1543 04:43:58.716052 ==
1544 04:43:58.717742 Dram Type= 6, Freq= 0, CH_1, rank 0
1545 04:43:58.721208 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1546 04:43:58.721680 ==
1547 04:43:58.722160
1548 04:43:58.724983
1549 04:43:58.725448 TX Vref Scan disable
1550 04:43:58.728573 == TX Byte 0 ==
1551 04:43:58.731665 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1552 04:43:58.735098 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1553 04:43:58.738577 == TX Byte 1 ==
1554 04:43:58.741325 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1555 04:43:58.745316 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1556 04:43:58.748227
1557 04:43:58.748855 [DATLAT]
1558 04:43:58.749341 Freq=800, CH1 RK0
1559 04:43:58.749796
1560 04:43:58.751191 DATLAT Default: 0xa
1561 04:43:58.751663 0, 0xFFFF, sum = 0
1562 04:43:58.754819 1, 0xFFFF, sum = 0
1563 04:43:58.755401 2, 0xFFFF, sum = 0
1564 04:43:58.758134 3, 0xFFFF, sum = 0
1565 04:43:58.758612 4, 0xFFFF, sum = 0
1566 04:43:58.761919 5, 0xFFFF, sum = 0
1567 04:43:58.762396 6, 0xFFFF, sum = 0
1568 04:43:58.765039 7, 0xFFFF, sum = 0
1569 04:43:58.765519 8, 0x0, sum = 1
1570 04:43:58.768618 9, 0x0, sum = 2
1571 04:43:58.769251 10, 0x0, sum = 3
1572 04:43:58.771572 11, 0x0, sum = 4
1573 04:43:58.772152 best_step = 9
1574 04:43:58.772639
1575 04:43:58.773135 ==
1576 04:43:58.775398 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 04:43:58.781970 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1578 04:43:58.782543 ==
1579 04:43:58.783030 RX Vref Scan: 1
1580 04:43:58.783480
1581 04:43:58.784778 Set Vref Range= 32 -> 127
1582 04:43:58.785248
1583 04:43:58.788407 RX Vref 32 -> 127, step: 1
1584 04:43:58.789041
1585 04:43:58.789526 RX Delay -111 -> 252, step: 8
1586 04:43:58.791713
1587 04:43:58.792302 Set Vref, RX VrefLevel [Byte0]: 32
1588 04:43:58.794453 [Byte1]: 32
1589 04:43:58.798537
1590 04:43:58.799004 Set Vref, RX VrefLevel [Byte0]: 33
1591 04:43:58.802451 [Byte1]: 33
1592 04:43:58.807198
1593 04:43:58.807670 Set Vref, RX VrefLevel [Byte0]: 34
1594 04:43:58.809895 [Byte1]: 34
1595 04:43:58.814255
1596 04:43:58.814725 Set Vref, RX VrefLevel [Byte0]: 35
1597 04:43:58.817568 [Byte1]: 35
1598 04:43:58.821592
1599 04:43:58.822063 Set Vref, RX VrefLevel [Byte0]: 36
1600 04:43:58.824924 [Byte1]: 36
1601 04:43:58.829585
1602 04:43:58.830043 Set Vref, RX VrefLevel [Byte0]: 37
1603 04:43:58.833325 [Byte1]: 37
1604 04:43:58.838309
1605 04:43:58.838747 Set Vref, RX VrefLevel [Byte0]: 38
1606 04:43:58.841037 [Byte1]: 38
1607 04:43:58.844846
1608 04:43:58.845319 Set Vref, RX VrefLevel [Byte0]: 39
1609 04:43:58.848678 [Byte1]: 39
1610 04:43:58.853158
1611 04:43:58.853723 Set Vref, RX VrefLevel [Byte0]: 40
1612 04:43:58.857047 [Byte1]: 40
1613 04:43:58.860360
1614 04:43:58.860986 Set Vref, RX VrefLevel [Byte0]: 41
1615 04:43:58.863842 [Byte1]: 41
1616 04:43:58.868246
1617 04:43:58.868870 Set Vref, RX VrefLevel [Byte0]: 42
1618 04:43:58.871642 [Byte1]: 42
1619 04:43:58.875533
1620 04:43:58.876106 Set Vref, RX VrefLevel [Byte0]: 43
1621 04:43:58.878991 [Byte1]: 43
1622 04:43:58.883186
1623 04:43:58.883757 Set Vref, RX VrefLevel [Byte0]: 44
1624 04:43:58.886648 [Byte1]: 44
1625 04:43:58.891631
1626 04:43:58.892189 Set Vref, RX VrefLevel [Byte0]: 45
1627 04:43:58.894329 [Byte1]: 45
1628 04:43:58.898817
1629 04:43:58.899365 Set Vref, RX VrefLevel [Byte0]: 46
1630 04:43:58.902065 [Byte1]: 46
1631 04:43:58.906007
1632 04:43:58.906579 Set Vref, RX VrefLevel [Byte0]: 47
1633 04:43:58.910151 [Byte1]: 47
1634 04:43:58.913567
1635 04:43:58.914022 Set Vref, RX VrefLevel [Byte0]: 48
1636 04:43:58.917571 [Byte1]: 48
1637 04:43:58.921553
1638 04:43:58.922109 Set Vref, RX VrefLevel [Byte0]: 49
1639 04:43:58.924449 [Byte1]: 49
1640 04:43:58.929185
1641 04:43:58.929756 Set Vref, RX VrefLevel [Byte0]: 50
1642 04:43:58.932208 [Byte1]: 50
1643 04:43:58.936699
1644 04:43:58.937299 Set Vref, RX VrefLevel [Byte0]: 51
1645 04:43:58.940203 [Byte1]: 51
1646 04:43:58.944575
1647 04:43:58.945182 Set Vref, RX VrefLevel [Byte0]: 52
1648 04:43:58.947817 [Byte1]: 52
1649 04:43:58.952009
1650 04:43:58.952566 Set Vref, RX VrefLevel [Byte0]: 53
1651 04:43:58.955710 [Byte1]: 53
1652 04:43:58.959836
1653 04:43:58.960388 Set Vref, RX VrefLevel [Byte0]: 54
1654 04:43:58.962632 [Byte1]: 54
1655 04:43:58.967891
1656 04:43:58.968445 Set Vref, RX VrefLevel [Byte0]: 55
1657 04:43:58.974226 [Byte1]: 55
1658 04:43:58.974784
1659 04:43:58.977094 Set Vref, RX VrefLevel [Byte0]: 56
1660 04:43:58.980420 [Byte1]: 56
1661 04:43:58.981008
1662 04:43:58.984371 Set Vref, RX VrefLevel [Byte0]: 57
1663 04:43:58.986873 [Byte1]: 57
1664 04:43:58.990248
1665 04:43:58.990798 Set Vref, RX VrefLevel [Byte0]: 58
1666 04:43:58.993584 [Byte1]: 58
1667 04:43:58.997909
1668 04:43:58.998460 Set Vref, RX VrefLevel [Byte0]: 59
1669 04:43:59.001228 [Byte1]: 59
1670 04:43:59.005386
1671 04:43:59.005970 Set Vref, RX VrefLevel [Byte0]: 60
1672 04:43:59.009085 [Byte1]: 60
1673 04:43:59.013071
1674 04:43:59.013624 Set Vref, RX VrefLevel [Byte0]: 61
1675 04:43:59.016909 [Byte1]: 61
1676 04:43:59.021272
1677 04:43:59.021884 Set Vref, RX VrefLevel [Byte0]: 62
1678 04:43:59.024263 [Byte1]: 62
1679 04:43:59.028400
1680 04:43:59.029007 Set Vref, RX VrefLevel [Byte0]: 63
1681 04:43:59.031833 [Byte1]: 63
1682 04:43:59.036234
1683 04:43:59.036831 Set Vref, RX VrefLevel [Byte0]: 64
1684 04:43:59.039474 [Byte1]: 64
1685 04:43:59.043934
1686 04:43:59.044516 Set Vref, RX VrefLevel [Byte0]: 65
1687 04:43:59.046879 [Byte1]: 65
1688 04:43:59.051394
1689 04:43:59.051938 Set Vref, RX VrefLevel [Byte0]: 66
1690 04:43:59.055798 [Byte1]: 66
1691 04:43:59.059344
1692 04:43:59.059894 Set Vref, RX VrefLevel [Byte0]: 67
1693 04:43:59.062291 [Byte1]: 67
1694 04:43:59.066872
1695 04:43:59.067428 Set Vref, RX VrefLevel [Byte0]: 68
1696 04:43:59.069838 [Byte1]: 68
1697 04:43:59.074917
1698 04:43:59.075465 Set Vref, RX VrefLevel [Byte0]: 69
1699 04:43:59.078897 [Byte1]: 69
1700 04:43:59.082000
1701 04:43:59.082549 Set Vref, RX VrefLevel [Byte0]: 70
1702 04:43:59.085496 [Byte1]: 70
1703 04:43:59.089842
1704 04:43:59.090389 Set Vref, RX VrefLevel [Byte0]: 71
1705 04:43:59.093191 [Byte1]: 71
1706 04:43:59.097096
1707 04:43:59.097548 Set Vref, RX VrefLevel [Byte0]: 72
1708 04:43:59.100422 [Byte1]: 72
1709 04:43:59.105315
1710 04:43:59.105762 Set Vref, RX VrefLevel [Byte0]: 73
1711 04:43:59.108149 [Byte1]: 73
1712 04:43:59.113140
1713 04:43:59.113692 Set Vref, RX VrefLevel [Byte0]: 74
1714 04:43:59.116200 [Byte1]: 74
1715 04:43:59.120504
1716 04:43:59.121095 Set Vref, RX VrefLevel [Byte0]: 75
1717 04:43:59.124244 [Byte1]: 75
1718 04:43:59.128568
1719 04:43:59.129161 Set Vref, RX VrefLevel [Byte0]: 76
1720 04:43:59.131337 [Byte1]: 76
1721 04:43:59.135875
1722 04:43:59.136424 Set Vref, RX VrefLevel [Byte0]: 77
1723 04:43:59.139180 [Byte1]: 77
1724 04:43:59.144274
1725 04:43:59.144863 Set Vref, RX VrefLevel [Byte0]: 78
1726 04:43:59.146241 [Byte1]: 78
1727 04:43:59.150806
1728 04:43:59.151347 Final RX Vref Byte 0 = 59 to rank0
1729 04:43:59.154495 Final RX Vref Byte 1 = 56 to rank0
1730 04:43:59.157434 Final RX Vref Byte 0 = 59 to rank1
1731 04:43:59.161289 Final RX Vref Byte 1 = 56 to rank1==
1732 04:43:59.163828 Dram Type= 6, Freq= 0, CH_1, rank 0
1733 04:43:59.171336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1734 04:43:59.171911 ==
1735 04:43:59.172280 DQS Delay:
1736 04:43:59.172617 DQS0 = 0, DQS1 = 0
1737 04:43:59.173822 DQM Delay:
1738 04:43:59.174273 DQM0 = 81, DQM1 = 74
1739 04:43:59.177685 DQ Delay:
1740 04:43:59.180676 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1741 04:43:59.184198 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =80
1742 04:43:59.187351 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1743 04:43:59.190708 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
1744 04:43:59.191267
1745 04:43:59.191631
1746 04:43:59.197154 [DQSOSCAuto] RK0, (LSB)MR18= 0x5050, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1747 04:43:59.200628 CH1 RK0: MR19=606, MR18=5050
1748 04:43:59.207499 CH1_RK0: MR19=0x606, MR18=0x5050, DQSOSC=389, MR23=63, INC=97, DEC=65
1749 04:43:59.208073
1750 04:43:59.211253 ----->DramcWriteLeveling(PI) begin...
1751 04:43:59.211823 ==
1752 04:43:59.214253 Dram Type= 6, Freq= 0, CH_1, rank 1
1753 04:43:59.218865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1754 04:43:59.219429 ==
1755 04:43:59.220751 Write leveling (Byte 0): 28 => 28
1756 04:43:59.223773 Write leveling (Byte 1): 26 => 26
1757 04:43:59.227518 DramcWriteLeveling(PI) end<-----
1758 04:43:59.228080
1759 04:43:59.228442 ==
1760 04:43:59.230623 Dram Type= 6, Freq= 0, CH_1, rank 1
1761 04:43:59.234435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1762 04:43:59.235002 ==
1763 04:43:59.238145 [Gating] SW mode calibration
1764 04:43:59.244830 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1765 04:43:59.251127 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1766 04:43:59.253988 0 6 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
1767 04:43:59.257172 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1768 04:43:59.263751 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1769 04:43:59.268391 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1770 04:43:59.270651 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1771 04:43:59.277424 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1772 04:43:59.280669 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1773 04:43:59.283922 0 6 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1774 04:43:59.290889 0 7 0 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
1775 04:43:59.294140 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1776 04:43:59.297429 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1777 04:43:59.303943 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1778 04:43:59.308148 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1779 04:43:59.311125 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1780 04:43:59.317337 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1781 04:43:59.320272 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1782 04:43:59.324088 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 04:43:59.330829 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 04:43:59.333596 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 04:43:59.337128 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 04:43:59.340229 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 04:43:59.348142 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 04:43:59.351037 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 04:43:59.353988 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 04:43:59.360243 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 04:43:59.363817 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 04:43:59.367003 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 04:43:59.374139 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 04:43:59.377614 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1795 04:43:59.380638 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1796 04:43:59.387244 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1797 04:43:59.390653 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1798 04:43:59.393953 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1799 04:43:59.397632 Total UI for P1: 0, mck2ui 16
1800 04:43:59.400477 best dqsien dly found for B0: ( 0, 9, 28)
1801 04:43:59.403555 Total UI for P1: 0, mck2ui 16
1802 04:43:59.407747 best dqsien dly found for B1: ( 0, 9, 28)
1803 04:43:59.410623 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1804 04:43:59.414344 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1805 04:43:59.414797
1806 04:43:59.420609 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1807 04:43:59.423290 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1808 04:43:59.423745 [Gating] SW calibration Done
1809 04:43:59.427302 ==
1810 04:43:59.430241 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 04:43:59.433642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1812 04:43:59.434096 ==
1813 04:43:59.434454 RX Vref Scan: 0
1814 04:43:59.434784
1815 04:43:59.436940 RX Vref 0 -> 0, step: 1
1816 04:43:59.437397
1817 04:43:59.440347 RX Delay -130 -> 252, step: 16
1818 04:43:59.443894 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1819 04:43:59.446919 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1820 04:43:59.453515 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1821 04:43:59.457113 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1822 04:43:59.460447 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1823 04:43:59.463446 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1824 04:43:59.467604 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1825 04:43:59.473982 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1826 04:43:59.477272 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1827 04:43:59.480386 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1828 04:43:59.483617 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1829 04:43:59.486919 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1830 04:43:59.493351 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1831 04:43:59.496978 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1832 04:43:59.501043 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1833 04:43:59.503319 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1834 04:43:59.503792 ==
1835 04:43:59.506847 Dram Type= 6, Freq= 0, CH_1, rank 1
1836 04:43:59.513545 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1837 04:43:59.514089 ==
1838 04:43:59.514574 DQS Delay:
1839 04:43:59.515062 DQS0 = 0, DQS1 = 0
1840 04:43:59.516741 DQM Delay:
1841 04:43:59.517221 DQM0 = 85, DQM1 = 75
1842 04:43:59.520129 DQ Delay:
1843 04:43:59.523194 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1844 04:43:59.523665 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1845 04:43:59.526531 DQ8 =53, DQ9 =69, DQ10 =69, DQ11 =69
1846 04:43:59.530031 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1847 04:43:59.533708
1848 04:43:59.534172
1849 04:43:59.534651 ==
1850 04:43:59.537046 Dram Type= 6, Freq= 0, CH_1, rank 1
1851 04:43:59.540298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1852 04:43:59.540823 ==
1853 04:43:59.541326
1854 04:43:59.541884
1855 04:43:59.543618 TX Vref Scan disable
1856 04:43:59.544076 == TX Byte 0 ==
1857 04:43:59.550724 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1858 04:43:59.554069 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1859 04:43:59.554634 == TX Byte 1 ==
1860 04:43:59.560230 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1861 04:43:59.563705 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1862 04:43:59.564162 ==
1863 04:43:59.567046 Dram Type= 6, Freq= 0, CH_1, rank 1
1864 04:43:59.570289 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1865 04:43:59.570752 ==
1866 04:43:59.584438 TX Vref=22, minBit 0, minWin=27, winSum=448
1867 04:43:59.588133 TX Vref=24, minBit 0, minWin=27, winSum=450
1868 04:43:59.590307 TX Vref=26, minBit 3, minWin=28, winSum=454
1869 04:43:59.594202 TX Vref=28, minBit 0, minWin=28, winSum=458
1870 04:43:59.597300 TX Vref=30, minBit 9, minWin=27, winSum=454
1871 04:43:59.599975 TX Vref=32, minBit 9, minWin=27, winSum=454
1872 04:43:59.607070 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1873 04:43:59.607530
1874 04:43:59.610486 Final TX Range 1 Vref 28
1875 04:43:59.611042
1876 04:43:59.611404 ==
1877 04:43:59.614473 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 04:43:59.617478 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1879 04:43:59.617938 ==
1880 04:43:59.618296
1881 04:43:59.620831
1882 04:43:59.621285 TX Vref Scan disable
1883 04:43:59.623418 == TX Byte 0 ==
1884 04:43:59.627293 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1885 04:43:59.635131 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1886 04:43:59.635882 == TX Byte 1 ==
1887 04:43:59.638427 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1888 04:43:59.643382 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1889 04:43:59.643907
1890 04:43:59.644271 [DATLAT]
1891 04:43:59.644609 Freq=800, CH1 RK1
1892 04:43:59.645031
1893 04:43:59.647303 DATLAT Default: 0x9
1894 04:43:59.647758 0, 0xFFFF, sum = 0
1895 04:43:59.650188 1, 0xFFFF, sum = 0
1896 04:43:59.650652 2, 0xFFFF, sum = 0
1897 04:43:59.653970 3, 0xFFFF, sum = 0
1898 04:43:59.656795 4, 0xFFFF, sum = 0
1899 04:43:59.657358 5, 0xFFFF, sum = 0
1900 04:43:59.660287 6, 0xFFFF, sum = 0
1901 04:43:59.660813 7, 0xFFFF, sum = 0
1902 04:43:59.661222 8, 0x0, sum = 1
1903 04:43:59.663789 9, 0x0, sum = 2
1904 04:43:59.664257 10, 0x0, sum = 3
1905 04:43:59.666910 11, 0x0, sum = 4
1906 04:43:59.667377 best_step = 9
1907 04:43:59.667740
1908 04:43:59.668077 ==
1909 04:43:59.670426 Dram Type= 6, Freq= 0, CH_1, rank 1
1910 04:43:59.676822 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1911 04:43:59.677342 ==
1912 04:43:59.677707 RX Vref Scan: 0
1913 04:43:59.678047
1914 04:43:59.680614 RX Vref 0 -> 0, step: 1
1915 04:43:59.681115
1916 04:43:59.683560 RX Delay -111 -> 252, step: 8
1917 04:43:59.687296 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1918 04:43:59.690454 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1919 04:43:59.696851 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1920 04:43:59.700000 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1921 04:43:59.703160 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1922 04:43:59.706648 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1923 04:43:59.710359 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1924 04:43:59.717481 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1925 04:43:59.720284 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1926 04:43:59.723334 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1927 04:43:59.727619 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1928 04:43:59.730081 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1929 04:43:59.737122 iDelay=217, Bit 12, Center 88 (-31 ~ 208) 240
1930 04:43:59.740477 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1931 04:43:59.744310 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1932 04:43:59.747497 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1933 04:43:59.748047 ==
1934 04:43:59.749935 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 04:43:59.757070 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1936 04:43:59.757634 ==
1937 04:43:59.758002 DQS Delay:
1938 04:43:59.759983 DQS0 = 0, DQS1 = 0
1939 04:43:59.760437 DQM Delay:
1940 04:43:59.760822 DQM0 = 83, DQM1 = 75
1941 04:43:59.763334 DQ Delay:
1942 04:43:59.766196 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1943 04:43:59.769806 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1944 04:43:59.773528 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1945 04:43:59.776418 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1946 04:43:59.776922
1947 04:43:59.777288
1948 04:43:59.783202 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b3b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1949 04:43:59.786873 CH1 RK1: MR19=606, MR18=3B3B
1950 04:43:59.793058 CH1_RK1: MR19=0x606, MR18=0x3B3B, DQSOSC=394, MR23=63, INC=95, DEC=63
1951 04:43:59.796362 [RxdqsGatingPostProcess] freq 800
1952 04:43:59.799725 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1953 04:43:59.803006 Pre-setting of DQS Precalculation
1954 04:43:59.810976 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1955 04:43:59.816253 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1956 04:43:59.823491 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1957 04:43:59.824040
1958 04:43:59.824399
1959 04:43:59.825806 [Calibration Summary] 1600 Mbps
1960 04:43:59.826263 CH 0, Rank 0
1961 04:43:59.829731 SW Impedance : PASS
1962 04:43:59.833602 DUTY Scan : NO K
1963 04:43:59.834154 ZQ Calibration : PASS
1964 04:43:59.836195 Jitter Meter : NO K
1965 04:43:59.839476 CBT Training : PASS
1966 04:43:59.840026 Write leveling : PASS
1967 04:43:59.843199 RX DQS gating : PASS
1968 04:43:59.846413 RX DQ/DQS(RDDQC) : PASS
1969 04:43:59.847020 TX DQ/DQS : PASS
1970 04:43:59.849165 RX DATLAT : PASS
1971 04:43:59.852943 RX DQ/DQS(Engine): PASS
1972 04:43:59.853501 TX OE : NO K
1973 04:43:59.853871 All Pass.
1974 04:43:59.854205
1975 04:43:59.856155 CH 0, Rank 1
1976 04:43:59.859495 SW Impedance : PASS
1977 04:43:59.860052 DUTY Scan : NO K
1978 04:43:59.862258 ZQ Calibration : PASS
1979 04:43:59.865517 Jitter Meter : NO K
1980 04:43:59.865976 CBT Training : PASS
1981 04:43:59.869250 Write leveling : PASS
1982 04:43:59.869815 RX DQS gating : PASS
1983 04:43:59.872729 RX DQ/DQS(RDDQC) : PASS
1984 04:43:59.875815 TX DQ/DQS : PASS
1985 04:43:59.876368 RX DATLAT : PASS
1986 04:43:59.879191 RX DQ/DQS(Engine): PASS
1987 04:43:59.882923 TX OE : NO K
1988 04:43:59.883343 All Pass.
1989 04:43:59.883690
1990 04:43:59.884115 CH 1, Rank 0
1991 04:43:59.886605 SW Impedance : PASS
1992 04:43:59.889396 DUTY Scan : NO K
1993 04:43:59.889947 ZQ Calibration : PASS
1994 04:43:59.892167 Jitter Meter : NO K
1995 04:43:59.895779 CBT Training : PASS
1996 04:43:59.896240 Write leveling : PASS
1997 04:43:59.898601 RX DQS gating : PASS
1998 04:43:59.902030 RX DQ/DQS(RDDQC) : PASS
1999 04:43:59.902491 TX DQ/DQS : PASS
2000 04:43:59.905737 RX DATLAT : PASS
2001 04:43:59.908765 RX DQ/DQS(Engine): PASS
2002 04:43:59.909280 TX OE : NO K
2003 04:43:59.909650 All Pass.
2004 04:43:59.911947
2005 04:43:59.912492 CH 1, Rank 1
2006 04:43:59.915636 SW Impedance : PASS
2007 04:43:59.916187 DUTY Scan : NO K
2008 04:43:59.918674 ZQ Calibration : PASS
2009 04:43:59.919132 Jitter Meter : NO K
2010 04:43:59.922582 CBT Training : PASS
2011 04:43:59.925279 Write leveling : PASS
2012 04:43:59.925755 RX DQS gating : PASS
2013 04:43:59.929817 RX DQ/DQS(RDDQC) : PASS
2014 04:43:59.932896 TX DQ/DQS : PASS
2015 04:43:59.933370 RX DATLAT : PASS
2016 04:43:59.935288 RX DQ/DQS(Engine): PASS
2017 04:43:59.939329 TX OE : NO K
2018 04:43:59.939898 All Pass.
2019 04:43:59.940385
2020 04:43:59.942485 DramC Write-DBI off
2021 04:43:59.943053 PER_BANK_REFRESH: Hybrid Mode
2022 04:43:59.945282 TX_TRACKING: ON
2023 04:43:59.948425 [GetDramInforAfterCalByMRR] Vendor 6.
2024 04:43:59.952793 [GetDramInforAfterCalByMRR] Revision 606.
2025 04:43:59.956286 [GetDramInforAfterCalByMRR] Revision 2 0.
2026 04:43:59.956904 MR0 0x3939
2027 04:43:59.960344 MR8 0x1111
2028 04:43:59.961884 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2029 04:43:59.962355
2030 04:43:59.962831 MR0 0x3939
2031 04:43:59.963282 MR8 0x1111
2032 04:43:59.968888 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2033 04:43:59.969342
2034 04:43:59.975308 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2035 04:43:59.978789 [FAST_K] Save calibration result to emmc
2036 04:43:59.982660 [FAST_K] Save calibration result to emmc
2037 04:43:59.985648 dram_init: config_dvfs: 1
2038 04:43:59.988913 dramc_set_vcore_voltage set vcore to 662500
2039 04:43:59.992795 Read voltage for 1200, 2
2040 04:43:59.993343 Vio18 = 0
2041 04:43:59.996147 Vcore = 662500
2042 04:43:59.996696 Vdram = 0
2043 04:43:59.997141 Vddq = 0
2044 04:43:59.997478 Vmddr = 0
2045 04:44:00.001897 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2046 04:44:00.008608 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2047 04:44:00.009179 MEM_TYPE=3, freq_sel=15
2048 04:44:00.011926 sv_algorithm_assistance_LP4_1600
2049 04:44:00.015075 ============ PULL DRAM RESETB DOWN ============
2050 04:44:00.021969 ========== PULL DRAM RESETB DOWN end =========
2051 04:44:00.025054 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2052 04:44:00.028591 ===================================
2053 04:44:00.032331 LPDDR4 DRAM CONFIGURATION
2054 04:44:00.036181 ===================================
2055 04:44:00.036799 EX_ROW_EN[0] = 0x0
2056 04:44:00.038861 EX_ROW_EN[1] = 0x0
2057 04:44:00.039410 LP4Y_EN = 0x0
2058 04:44:00.042154 WORK_FSP = 0x0
2059 04:44:00.045184 WL = 0x4
2060 04:44:00.045733 RL = 0x4
2061 04:44:00.048904 BL = 0x2
2062 04:44:00.049605 RPST = 0x0
2063 04:44:00.053016 RD_PRE = 0x0
2064 04:44:00.053569 WR_PRE = 0x1
2065 04:44:00.055300 WR_PST = 0x0
2066 04:44:00.055750 DBI_WR = 0x0
2067 04:44:00.058720 DBI_RD = 0x0
2068 04:44:00.059270 OTF = 0x1
2069 04:44:00.062327 ===================================
2070 04:44:00.064963 ===================================
2071 04:44:00.068885 ANA top config
2072 04:44:00.072553 ===================================
2073 04:44:00.073168 DLL_ASYNC_EN = 0
2074 04:44:00.074848 ALL_SLAVE_EN = 0
2075 04:44:00.079710 NEW_RANK_MODE = 1
2076 04:44:00.081874 DLL_IDLE_MODE = 1
2077 04:44:00.082422 LP45_APHY_COMB_EN = 1
2078 04:44:00.085227 TX_ODT_DIS = 1
2079 04:44:00.088814 NEW_8X_MODE = 1
2080 04:44:00.092758 ===================================
2081 04:44:00.096536 ===================================
2082 04:44:00.098926 data_rate = 2400
2083 04:44:00.101523 CKR = 1
2084 04:44:00.102093 DQ_P2S_RATIO = 8
2085 04:44:00.105304 ===================================
2086 04:44:00.108461 CA_P2S_RATIO = 8
2087 04:44:00.112332 DQ_CA_OPEN = 0
2088 04:44:00.115108 DQ_SEMI_OPEN = 0
2089 04:44:00.119033 CA_SEMI_OPEN = 0
2090 04:44:00.122536 CA_FULL_RATE = 0
2091 04:44:00.123089 DQ_CKDIV4_EN = 0
2092 04:44:00.125218 CA_CKDIV4_EN = 0
2093 04:44:00.128875 CA_PREDIV_EN = 0
2094 04:44:00.132128 PH8_DLY = 17
2095 04:44:00.135969 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2096 04:44:00.139326 DQ_AAMCK_DIV = 4
2097 04:44:00.139879 CA_AAMCK_DIV = 4
2098 04:44:00.142720 CA_ADMCK_DIV = 4
2099 04:44:00.145452 DQ_TRACK_CA_EN = 0
2100 04:44:00.149376 CA_PICK = 1200
2101 04:44:00.153019 CA_MCKIO = 1200
2102 04:44:00.155462 MCKIO_SEMI = 0
2103 04:44:00.158603 PLL_FREQ = 2366
2104 04:44:00.159061 DQ_UI_PI_RATIO = 32
2105 04:44:00.162079 CA_UI_PI_RATIO = 0
2106 04:44:00.165047 ===================================
2107 04:44:00.168876 ===================================
2108 04:44:00.171810 memory_type:LPDDR4
2109 04:44:00.175441 GP_NUM : 10
2110 04:44:00.175895 SRAM_EN : 1
2111 04:44:00.178643 MD32_EN : 0
2112 04:44:00.181989 ===================================
2113 04:44:00.186571 [ANA_INIT] >>>>>>>>>>>>>>
2114 04:44:00.187120 <<<<<< [CONFIGURE PHASE]: ANA_TX
2115 04:44:00.188475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2116 04:44:00.192243 ===================================
2117 04:44:00.195747 data_rate = 2400,PCW = 0X5b00
2118 04:44:00.198780 ===================================
2119 04:44:00.201628 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2120 04:44:00.208683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2121 04:44:00.215668 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2122 04:44:00.218799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2123 04:44:00.221977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2124 04:44:00.225476 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2125 04:44:00.228248 [ANA_INIT] flow start
2126 04:44:00.228733 [ANA_INIT] PLL >>>>>>>>
2127 04:44:00.232032 [ANA_INIT] PLL <<<<<<<<
2128 04:44:00.235557 [ANA_INIT] MIDPI >>>>>>>>
2129 04:44:00.236131 [ANA_INIT] MIDPI <<<<<<<<
2130 04:44:00.239142 [ANA_INIT] DLL >>>>>>>>
2131 04:44:00.241855 [ANA_INIT] DLL <<<<<<<<
2132 04:44:00.242313 [ANA_INIT] flow end
2133 04:44:00.248464 ============ LP4 DIFF to SE enter ============
2134 04:44:00.252054 ============ LP4 DIFF to SE exit ============
2135 04:44:00.255098 [ANA_INIT] <<<<<<<<<<<<<
2136 04:44:00.258451 [Flow] Enable top DCM control >>>>>
2137 04:44:00.259013 [Flow] Enable top DCM control <<<<<
2138 04:44:00.262621 Enable DLL master slave shuffle
2139 04:44:00.269338 ==============================================================
2140 04:44:00.271937 Gating Mode config
2141 04:44:00.275019 ==============================================================
2142 04:44:00.278239 Config description:
2143 04:44:00.288304 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2144 04:44:00.295673 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2145 04:44:00.299072 SELPH_MODE 0: By rank 1: By Phase
2146 04:44:00.305317 ==============================================================
2147 04:44:00.308788 GAT_TRACK_EN = 1
2148 04:44:00.311660 RX_GATING_MODE = 2
2149 04:44:00.316004 RX_GATING_TRACK_MODE = 2
2150 04:44:00.316554 SELPH_MODE = 1
2151 04:44:00.318230 PICG_EARLY_EN = 1
2152 04:44:00.322020 VALID_LAT_VALUE = 1
2153 04:44:00.328476 ==============================================================
2154 04:44:00.332401 Enter into Gating configuration >>>>
2155 04:44:00.334927 Exit from Gating configuration <<<<
2156 04:44:00.338608 Enter into DVFS_PRE_config >>>>>
2157 04:44:00.348557 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2158 04:44:00.351469 Exit from DVFS_PRE_config <<<<<
2159 04:44:00.355271 Enter into PICG configuration >>>>
2160 04:44:00.359056 Exit from PICG configuration <<<<
2161 04:44:00.361116 [RX_INPUT] configuration >>>>>
2162 04:44:00.365515 [RX_INPUT] configuration <<<<<
2163 04:44:00.367781 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2164 04:44:00.374897 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2165 04:44:00.381447 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2166 04:44:00.388416 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2167 04:44:00.394587 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2168 04:44:00.398126 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2169 04:44:00.404259 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2170 04:44:00.407582 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2171 04:44:00.411992 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2172 04:44:00.414259 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2173 04:44:00.420945 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2174 04:44:00.425065 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2175 04:44:00.427641 ===================================
2176 04:44:00.431178 LPDDR4 DRAM CONFIGURATION
2177 04:44:00.434472 ===================================
2178 04:44:00.434936 EX_ROW_EN[0] = 0x0
2179 04:44:00.438401 EX_ROW_EN[1] = 0x0
2180 04:44:00.438953 LP4Y_EN = 0x0
2181 04:44:00.441345 WORK_FSP = 0x0
2182 04:44:00.441897 WL = 0x4
2183 04:44:00.444669 RL = 0x4
2184 04:44:00.445274 BL = 0x2
2185 04:44:00.448322 RPST = 0x0
2186 04:44:00.448936 RD_PRE = 0x0
2187 04:44:00.451040 WR_PRE = 0x1
2188 04:44:00.451499 WR_PST = 0x0
2189 04:44:00.454136 DBI_WR = 0x0
2190 04:44:00.454624 DBI_RD = 0x0
2191 04:44:00.457902 OTF = 0x1
2192 04:44:00.461019 ===================================
2193 04:44:00.464416 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2194 04:44:00.468251 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2195 04:44:00.475258 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2196 04:44:00.477705 ===================================
2197 04:44:00.478168 LPDDR4 DRAM CONFIGURATION
2198 04:44:00.481053 ===================================
2199 04:44:00.484383 EX_ROW_EN[0] = 0x10
2200 04:44:00.488185 EX_ROW_EN[1] = 0x0
2201 04:44:00.488775 LP4Y_EN = 0x0
2202 04:44:00.491459 WORK_FSP = 0x0
2203 04:44:00.492009 WL = 0x4
2204 04:44:00.493847 RL = 0x4
2205 04:44:00.494306 BL = 0x2
2206 04:44:00.498298 RPST = 0x0
2207 04:44:00.498864 RD_PRE = 0x0
2208 04:44:00.500906 WR_PRE = 0x1
2209 04:44:00.501366 WR_PST = 0x0
2210 04:44:00.503679 DBI_WR = 0x0
2211 04:44:00.504389 DBI_RD = 0x0
2212 04:44:00.507675 OTF = 0x1
2213 04:44:00.510836 ===================================
2214 04:44:00.517588 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2215 04:44:00.518128 ==
2216 04:44:00.520895 Dram Type= 6, Freq= 0, CH_0, rank 0
2217 04:44:00.524646 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2218 04:44:00.525258 ==
2219 04:44:00.527575 [Duty_Offset_Calibration]
2220 04:44:00.528118 B0:0 B1:2 CA:1
2221 04:44:00.528482
2222 04:44:00.531467 [DutyScan_Calibration_Flow] k_type=0
2223 04:44:00.541497
2224 04:44:00.542053 ==CLK 0==
2225 04:44:00.544938 Final CLK duty delay cell = 0
2226 04:44:00.547964 [0] MAX Duty = 5093%(X100), DQS PI = 12
2227 04:44:00.551716 [0] MIN Duty = 4938%(X100), DQS PI = 54
2228 04:44:00.552284 [0] AVG Duty = 5015%(X100)
2229 04:44:00.554696
2230 04:44:00.557697 CH0 CLK Duty spec in!! Max-Min= 155%
2231 04:44:00.561446 [DutyScan_Calibration_Flow] ====Done====
2232 04:44:00.562001
2233 04:44:00.565040 [DutyScan_Calibration_Flow] k_type=1
2234 04:44:00.581583
2235 04:44:00.582151 ==DQS 0 ==
2236 04:44:00.583530 Final DQS duty delay cell = 0
2237 04:44:00.587439 [0] MAX Duty = 5125%(X100), DQS PI = 28
2238 04:44:00.591124 [0] MIN Duty = 5031%(X100), DQS PI = 6
2239 04:44:00.591685 [0] AVG Duty = 5078%(X100)
2240 04:44:00.593619
2241 04:44:00.594079 ==DQS 1 ==
2242 04:44:00.597314 Final DQS duty delay cell = 0
2243 04:44:00.600348 [0] MAX Duty = 5062%(X100), DQS PI = 58
2244 04:44:00.603641 [0] MIN Duty = 4906%(X100), DQS PI = 16
2245 04:44:00.607553 [0] AVG Duty = 4984%(X100)
2246 04:44:00.608014
2247 04:44:00.610240 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2248 04:44:00.610812
2249 04:44:00.613350 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2250 04:44:00.616891 [DutyScan_Calibration_Flow] ====Done====
2251 04:44:00.617431
2252 04:44:00.620680 [DutyScan_Calibration_Flow] k_type=3
2253 04:44:00.636757
2254 04:44:00.637302 ==DQM 0 ==
2255 04:44:00.640138 Final DQM duty delay cell = 0
2256 04:44:00.644276 [0] MAX Duty = 5156%(X100), DQS PI = 22
2257 04:44:00.646580 [0] MIN Duty = 4969%(X100), DQS PI = 54
2258 04:44:00.647133 [0] AVG Duty = 5062%(X100)
2259 04:44:00.650970
2260 04:44:00.651519 ==DQM 1 ==
2261 04:44:00.656151 Final DQM duty delay cell = 0
2262 04:44:00.657278 [0] MAX Duty = 4969%(X100), DQS PI = 52
2263 04:44:00.660195 [0] MIN Duty = 4844%(X100), DQS PI = 0
2264 04:44:00.660790 [0] AVG Duty = 4906%(X100)
2265 04:44:00.663275
2266 04:44:00.666734 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2267 04:44:00.667285
2268 04:44:00.670024 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2269 04:44:00.673548 [DutyScan_Calibration_Flow] ====Done====
2270 04:44:00.674100
2271 04:44:00.676738 [DutyScan_Calibration_Flow] k_type=2
2272 04:44:00.691942
2273 04:44:00.692491 ==DQ 0 ==
2274 04:44:00.695897 Final DQ duty delay cell = -4
2275 04:44:00.699122 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2276 04:44:00.701837 [-4] MIN Duty = 4813%(X100), DQS PI = 6
2277 04:44:00.705053 [-4] AVG Duty = 4937%(X100)
2278 04:44:00.705756
2279 04:44:00.706161 ==DQ 1 ==
2280 04:44:00.707807 Final DQ duty delay cell = -4
2281 04:44:00.711566 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2282 04:44:00.715520 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2283 04:44:00.718368 [-4] AVG Duty = 4969%(X100)
2284 04:44:00.718824
2285 04:44:00.721262 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2286 04:44:00.721712
2287 04:44:00.725269 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2288 04:44:00.728158 [DutyScan_Calibration_Flow] ====Done====
2289 04:44:00.728607 ==
2290 04:44:00.731752 Dram Type= 6, Freq= 0, CH_1, rank 0
2291 04:44:00.734995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2292 04:44:00.735551 ==
2293 04:44:00.738344 [Duty_Offset_Calibration]
2294 04:44:00.738896 B0:0 B1:4 CA:-5
2295 04:44:00.739257
2296 04:44:00.741476 [DutyScan_Calibration_Flow] k_type=0
2297 04:44:00.751869
2298 04:44:00.752415 ==CLK 0==
2299 04:44:00.755340 Final CLK duty delay cell = 0
2300 04:44:00.758858 [0] MAX Duty = 5094%(X100), DQS PI = 24
2301 04:44:00.762893 [0] MIN Duty = 4875%(X100), DQS PI = 48
2302 04:44:00.763466 [0] AVG Duty = 4984%(X100)
2303 04:44:00.765614
2304 04:44:00.766208 CH1 CLK Duty spec in!! Max-Min= 219%
2305 04:44:00.772057 [DutyScan_Calibration_Flow] ====Done====
2306 04:44:00.772645
2307 04:44:00.775297 [DutyScan_Calibration_Flow] k_type=1
2308 04:44:00.791006
2309 04:44:00.791569 ==DQS 0 ==
2310 04:44:00.794006 Final DQS duty delay cell = 0
2311 04:44:00.797773 [0] MAX Duty = 5125%(X100), DQS PI = 16
2312 04:44:00.800937 [0] MIN Duty = 4875%(X100), DQS PI = 40
2313 04:44:00.803828 [0] AVG Duty = 5000%(X100)
2314 04:44:00.804299
2315 04:44:00.804741 ==DQS 1 ==
2316 04:44:00.807985 Final DQS duty delay cell = -4
2317 04:44:00.810932 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2318 04:44:00.813857 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2319 04:44:00.817795 [-4] AVG Duty = 4953%(X100)
2320 04:44:00.818299
2321 04:44:00.820481 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2322 04:44:00.821007
2323 04:44:00.824427 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2324 04:44:00.827100 [DutyScan_Calibration_Flow] ====Done====
2325 04:44:00.827573
2326 04:44:00.830922 [DutyScan_Calibration_Flow] k_type=3
2327 04:44:00.846405
2328 04:44:00.846957 ==DQM 0 ==
2329 04:44:00.849414 Final DQM duty delay cell = -4
2330 04:44:00.853444 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2331 04:44:00.856084 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2332 04:44:00.860004 [-4] AVG Duty = 4969%(X100)
2333 04:44:00.860557
2334 04:44:00.860968 ==DQM 1 ==
2335 04:44:00.863206 Final DQM duty delay cell = -4
2336 04:44:00.866037 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2337 04:44:00.869483 [-4] MIN Duty = 4906%(X100), DQS PI = 56
2338 04:44:00.872774 [-4] AVG Duty = 4984%(X100)
2339 04:44:00.873324
2340 04:44:00.877408 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2341 04:44:00.877864
2342 04:44:00.879800 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2343 04:44:00.882713 [DutyScan_Calibration_Flow] ====Done====
2344 04:44:00.883265
2345 04:44:00.886133 [DutyScan_Calibration_Flow] k_type=2
2346 04:44:00.903248
2347 04:44:00.903920 ==DQ 0 ==
2348 04:44:00.906580 Final DQ duty delay cell = 0
2349 04:44:00.909395 [0] MAX Duty = 5062%(X100), DQS PI = 0
2350 04:44:00.912858 [0] MIN Duty = 4969%(X100), DQS PI = 42
2351 04:44:00.913411 [0] AVG Duty = 5015%(X100)
2352 04:44:00.913776
2353 04:44:00.916650 ==DQ 1 ==
2354 04:44:00.919306 Final DQ duty delay cell = 0
2355 04:44:00.922816 [0] MAX Duty = 5000%(X100), DQS PI = 6
2356 04:44:00.926172 [0] MIN Duty = 4875%(X100), DQS PI = 0
2357 04:44:00.926628 [0] AVG Duty = 4937%(X100)
2358 04:44:00.926985
2359 04:44:00.929942 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2360 04:44:00.930391
2361 04:44:00.932404 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2362 04:44:00.939551 [DutyScan_Calibration_Flow] ====Done====
2363 04:44:00.942997 nWR fixed to 30
2364 04:44:00.943444 [ModeRegInit_LP4] CH0 RK0
2365 04:44:00.945957 [ModeRegInit_LP4] CH0 RK1
2366 04:44:00.948959 [ModeRegInit_LP4] CH1 RK0
2367 04:44:00.949271 [ModeRegInit_LP4] CH1 RK1
2368 04:44:00.952486 match AC timing 6
2369 04:44:00.955630 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2370 04:44:00.959828 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2371 04:44:00.966471 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2372 04:44:00.969074 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2373 04:44:00.975997 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2374 04:44:00.976319 ==
2375 04:44:00.979185 Dram Type= 6, Freq= 0, CH_0, rank 0
2376 04:44:00.982871 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2377 04:44:00.983195 ==
2378 04:44:00.989047 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2379 04:44:00.992280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2380 04:44:01.002373 [CA 0] Center 39 (9~70) winsize 62
2381 04:44:01.006209 [CA 1] Center 39 (8~70) winsize 63
2382 04:44:01.008758 [CA 2] Center 36 (5~67) winsize 63
2383 04:44:01.012759 [CA 3] Center 35 (4~66) winsize 63
2384 04:44:01.017210 [CA 4] Center 34 (3~65) winsize 63
2385 04:44:01.019161 [CA 5] Center 33 (3~64) winsize 62
2386 04:44:01.019612
2387 04:44:01.022296 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2388 04:44:01.022820
2389 04:44:01.025905 [CATrainingPosCal] consider 1 rank data
2390 04:44:01.028855 u2DelayCellTimex100 = 270/100 ps
2391 04:44:01.032432 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2392 04:44:01.035918 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2393 04:44:01.042074 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2394 04:44:01.046412 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2395 04:44:01.048992 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2396 04:44:01.052378 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2397 04:44:01.052874
2398 04:44:01.056245 CA PerBit enable=1, Macro0, CA PI delay=33
2399 04:44:01.056702
2400 04:44:01.059448 [CBTSetCACLKResult] CA Dly = 33
2401 04:44:01.059996 CS Dly: 7 (0~38)
2402 04:44:01.060355 ==
2403 04:44:01.062605 Dram Type= 6, Freq= 0, CH_0, rank 1
2404 04:44:01.069323 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2405 04:44:01.069780 ==
2406 04:44:01.072857 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2407 04:44:01.079082 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2408 04:44:01.087999 [CA 0] Center 39 (9~70) winsize 62
2409 04:44:01.091511 [CA 1] Center 39 (8~70) winsize 63
2410 04:44:01.095506 [CA 2] Center 35 (5~66) winsize 62
2411 04:44:01.098035 [CA 3] Center 35 (4~66) winsize 63
2412 04:44:01.101282 [CA 4] Center 33 (3~64) winsize 62
2413 04:44:01.104526 [CA 5] Center 34 (3~65) winsize 63
2414 04:44:01.105395
2415 04:44:01.108669 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2416 04:44:01.109158
2417 04:44:01.111104 [CATrainingPosCal] consider 2 rank data
2418 04:44:01.114933 u2DelayCellTimex100 = 270/100 ps
2419 04:44:01.118089 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2420 04:44:01.121278 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2421 04:44:01.127942 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2422 04:44:01.131338 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2423 04:44:01.134985 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2424 04:44:01.137598 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2425 04:44:01.138050
2426 04:44:01.141037 CA PerBit enable=1, Macro0, CA PI delay=33
2427 04:44:01.141492
2428 04:44:01.144371 [CBTSetCACLKResult] CA Dly = 33
2429 04:44:01.145062 CS Dly: 7 (0~39)
2430 04:44:01.145500
2431 04:44:01.147998 ----->DramcWriteLeveling(PI) begin...
2432 04:44:01.151276 ==
2433 04:44:01.154765 Dram Type= 6, Freq= 0, CH_0, rank 0
2434 04:44:01.157736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2435 04:44:01.158291 ==
2436 04:44:01.161534 Write leveling (Byte 0): 28 => 28
2437 04:44:01.164477 Write leveling (Byte 1): 26 => 26
2438 04:44:01.167727 DramcWriteLeveling(PI) end<-----
2439 04:44:01.168182
2440 04:44:01.168535 ==
2441 04:44:01.171466 Dram Type= 6, Freq= 0, CH_0, rank 0
2442 04:44:01.174488 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2443 04:44:01.175054 ==
2444 04:44:01.178118 [Gating] SW mode calibration
2445 04:44:01.184735 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2446 04:44:01.187643 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2447 04:44:01.196108 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2448 04:44:01.197431 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2449 04:44:01.201928 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2450 04:44:01.207237 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2451 04:44:01.210890 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2452 04:44:01.214776 0 11 20 | B1->B0 | 3232 2a2a | 0 0 | (0 1) (0 0)
2453 04:44:01.221338 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2454 04:44:01.224894 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2455 04:44:01.228271 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2456 04:44:01.234326 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2457 04:44:01.238922 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2458 04:44:01.241366 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2459 04:44:01.247830 0 12 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2460 04:44:01.251501 0 12 20 | B1->B0 | 3636 3f3f | 0 1 | (0 0) (0 0)
2461 04:44:01.254136 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2462 04:44:01.262056 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2463 04:44:01.263976 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2464 04:44:01.267299 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2465 04:44:01.274291 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2466 04:44:01.278159 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2467 04:44:01.280982 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2468 04:44:01.288437 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2469 04:44:01.290948 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2470 04:44:01.294205 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 04:44:01.301168 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 04:44:01.304647 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 04:44:01.307329 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 04:44:01.310951 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 04:44:01.317571 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 04:44:01.321860 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 04:44:01.324087 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 04:44:01.331275 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 04:44:01.335383 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 04:44:01.337426 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2481 04:44:01.344731 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2482 04:44:01.347849 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2483 04:44:01.350718 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2484 04:44:01.357696 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2485 04:44:01.361717 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2486 04:44:01.364782 Total UI for P1: 0, mck2ui 16
2487 04:44:01.367455 best dqsien dly found for B0: ( 0, 15, 18)
2488 04:44:01.371548 Total UI for P1: 0, mck2ui 16
2489 04:44:01.374664 best dqsien dly found for B1: ( 0, 15, 18)
2490 04:44:01.377249 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2491 04:44:01.380613 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2492 04:44:01.381093
2493 04:44:01.384191 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2494 04:44:01.387918 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2495 04:44:01.390892 [Gating] SW calibration Done
2496 04:44:01.391444 ==
2497 04:44:01.394304 Dram Type= 6, Freq= 0, CH_0, rank 0
2498 04:44:01.397247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2499 04:44:01.401234 ==
2500 04:44:01.401831 RX Vref Scan: 0
2501 04:44:01.402193
2502 04:44:01.404204 RX Vref 0 -> 0, step: 1
2503 04:44:01.404676
2504 04:44:01.405090 RX Delay -40 -> 252, step: 8
2505 04:44:01.410888 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2506 04:44:01.414446 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2507 04:44:01.417423 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2508 04:44:01.420553 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2509 04:44:01.424521 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2510 04:44:01.430797 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2511 04:44:01.434365 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2512 04:44:01.437356 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2513 04:44:01.441331 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2514 04:44:01.444792 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2515 04:44:01.451025 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2516 04:44:01.454695 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2517 04:44:01.458015 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2518 04:44:01.460694 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2519 04:44:01.464144 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2520 04:44:01.471183 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2521 04:44:01.471735 ==
2522 04:44:01.474465 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 04:44:01.477417 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2524 04:44:01.477884 ==
2525 04:44:01.478292 DQS Delay:
2526 04:44:01.480911 DQS0 = 0, DQS1 = 0
2527 04:44:01.481367 DQM Delay:
2528 04:44:01.484623 DQM0 = 115, DQM1 = 106
2529 04:44:01.485204 DQ Delay:
2530 04:44:01.487160 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2531 04:44:01.491267 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2532 04:44:01.493808 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2533 04:44:01.498223 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2534 04:44:01.498772
2535 04:44:01.500963
2536 04:44:01.501539 ==
2537 04:44:01.505441 Dram Type= 6, Freq= 0, CH_0, rank 0
2538 04:44:01.507598 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2539 04:44:01.508054 ==
2540 04:44:01.508411
2541 04:44:01.508775
2542 04:44:01.510729 TX Vref Scan disable
2543 04:44:01.511178 == TX Byte 0 ==
2544 04:44:01.516831 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2545 04:44:01.521679 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2546 04:44:01.522134 == TX Byte 1 ==
2547 04:44:01.529694 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2548 04:44:01.530716 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2549 04:44:01.531104 ==
2550 04:44:01.533910 Dram Type= 6, Freq= 0, CH_0, rank 0
2551 04:44:01.537660 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2552 04:44:01.538212 ==
2553 04:44:01.550099 TX Vref=22, minBit 10, minWin=24, winSum=416
2554 04:44:01.552928 TX Vref=24, minBit 10, minWin=25, winSum=421
2555 04:44:01.556289 TX Vref=26, minBit 8, minWin=26, winSum=431
2556 04:44:01.559295 TX Vref=28, minBit 8, minWin=26, winSum=430
2557 04:44:01.563354 TX Vref=30, minBit 10, minWin=25, winSum=433
2558 04:44:01.569644 TX Vref=32, minBit 9, minWin=26, winSum=435
2559 04:44:01.573653 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 32
2560 04:44:01.574207
2561 04:44:01.576540 Final TX Range 1 Vref 32
2562 04:44:01.577127
2563 04:44:01.577487 ==
2564 04:44:01.579750 Dram Type= 6, Freq= 0, CH_0, rank 0
2565 04:44:01.583225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2566 04:44:01.583792 ==
2567 04:44:01.585940
2568 04:44:01.586389
2569 04:44:01.586746 TX Vref Scan disable
2570 04:44:01.589712 == TX Byte 0 ==
2571 04:44:01.592796 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2572 04:44:01.596513 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2573 04:44:01.599755 == TX Byte 1 ==
2574 04:44:01.602639 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2575 04:44:01.606011 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2576 04:44:01.606613
2577 04:44:01.609949 [DATLAT]
2578 04:44:01.610558 Freq=1200, CH0 RK0
2579 04:44:01.611041
2580 04:44:01.613014 DATLAT Default: 0xd
2581 04:44:01.613470 0, 0xFFFF, sum = 0
2582 04:44:01.615922 1, 0xFFFF, sum = 0
2583 04:44:01.616549 2, 0xFFFF, sum = 0
2584 04:44:01.619429 3, 0xFFFF, sum = 0
2585 04:44:01.622386 4, 0xFFFF, sum = 0
2586 04:44:01.622849 5, 0xFFFF, sum = 0
2587 04:44:01.625994 6, 0xFFFF, sum = 0
2588 04:44:01.626559 7, 0xFFFF, sum = 0
2589 04:44:01.629702 8, 0xFFFF, sum = 0
2590 04:44:01.630164 9, 0xFFFF, sum = 0
2591 04:44:01.632484 10, 0xFFFF, sum = 0
2592 04:44:01.633000 11, 0x0, sum = 1
2593 04:44:01.635824 12, 0x0, sum = 2
2594 04:44:01.636284 13, 0x0, sum = 3
2595 04:44:01.640067 14, 0x0, sum = 4
2596 04:44:01.640635 best_step = 12
2597 04:44:01.641061
2598 04:44:01.641400 ==
2599 04:44:01.642563 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 04:44:01.646275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2601 04:44:01.646832 ==
2602 04:44:01.651226 RX Vref Scan: 1
2603 04:44:01.651812
2604 04:44:01.652740 Set Vref Range= 32 -> 127
2605 04:44:01.653137
2606 04:44:01.653475 RX Vref 32 -> 127, step: 1
2607 04:44:01.653800
2608 04:44:01.656012 RX Delay -21 -> 252, step: 4
2609 04:44:01.656463
2610 04:44:01.659586 Set Vref, RX VrefLevel [Byte0]: 32
2611 04:44:01.662791 [Byte1]: 32
2612 04:44:01.666081
2613 04:44:01.666534 Set Vref, RX VrefLevel [Byte0]: 33
2614 04:44:01.669293 [Byte1]: 33
2615 04:44:01.674438
2616 04:44:01.674990 Set Vref, RX VrefLevel [Byte0]: 34
2617 04:44:01.677633 [Byte1]: 34
2618 04:44:01.682437
2619 04:44:01.682993 Set Vref, RX VrefLevel [Byte0]: 35
2620 04:44:01.685685 [Byte1]: 35
2621 04:44:01.689727
2622 04:44:01.690280 Set Vref, RX VrefLevel [Byte0]: 36
2623 04:44:01.692888 [Byte1]: 36
2624 04:44:01.697942
2625 04:44:01.698562 Set Vref, RX VrefLevel [Byte0]: 37
2626 04:44:01.701585 [Byte1]: 37
2627 04:44:01.705827
2628 04:44:01.706407 Set Vref, RX VrefLevel [Byte0]: 38
2629 04:44:01.709306 [Byte1]: 38
2630 04:44:01.713406
2631 04:44:01.713859 Set Vref, RX VrefLevel [Byte0]: 39
2632 04:44:01.716475 [Byte1]: 39
2633 04:44:01.721390
2634 04:44:01.721947 Set Vref, RX VrefLevel [Byte0]: 40
2635 04:44:01.724518 [Byte1]: 40
2636 04:44:01.729351
2637 04:44:01.729900 Set Vref, RX VrefLevel [Byte0]: 41
2638 04:44:01.732591 [Byte1]: 41
2639 04:44:01.737613
2640 04:44:01.738169 Set Vref, RX VrefLevel [Byte0]: 42
2641 04:44:01.740693 [Byte1]: 42
2642 04:44:01.745661
2643 04:44:01.746216 Set Vref, RX VrefLevel [Byte0]: 43
2644 04:44:01.748881 [Byte1]: 43
2645 04:44:01.753392
2646 04:44:01.753947 Set Vref, RX VrefLevel [Byte0]: 44
2647 04:44:01.756391 [Byte1]: 44
2648 04:44:01.762533
2649 04:44:01.763086 Set Vref, RX VrefLevel [Byte0]: 45
2650 04:44:01.764410 [Byte1]: 45
2651 04:44:01.769243
2652 04:44:01.769792 Set Vref, RX VrefLevel [Byte0]: 46
2653 04:44:01.772695 [Byte1]: 46
2654 04:44:01.777853
2655 04:44:01.778405 Set Vref, RX VrefLevel [Byte0]: 47
2656 04:44:01.780372 [Byte1]: 47
2657 04:44:01.785090
2658 04:44:01.785633 Set Vref, RX VrefLevel [Byte0]: 48
2659 04:44:01.788323 [Byte1]: 48
2660 04:44:01.793428
2661 04:44:01.793977 Set Vref, RX VrefLevel [Byte0]: 49
2662 04:44:01.796109 [Byte1]: 49
2663 04:44:01.801435
2664 04:44:01.801982 Set Vref, RX VrefLevel [Byte0]: 50
2665 04:44:01.803969 [Byte1]: 50
2666 04:44:01.808991
2667 04:44:01.809470 Set Vref, RX VrefLevel [Byte0]: 51
2668 04:44:01.811784 [Byte1]: 51
2669 04:44:01.816877
2670 04:44:01.817350 Set Vref, RX VrefLevel [Byte0]: 52
2671 04:44:01.819680 [Byte1]: 52
2672 04:44:01.825718
2673 04:44:01.826279 Set Vref, RX VrefLevel [Byte0]: 53
2674 04:44:01.828303 [Byte1]: 53
2675 04:44:01.832448
2676 04:44:01.833052 Set Vref, RX VrefLevel [Byte0]: 54
2677 04:44:01.835928 [Byte1]: 54
2678 04:44:01.840602
2679 04:44:01.841197 Set Vref, RX VrefLevel [Byte0]: 55
2680 04:44:01.843536 [Byte1]: 55
2681 04:44:01.848334
2682 04:44:01.848936 Set Vref, RX VrefLevel [Byte0]: 56
2683 04:44:01.851870 [Byte1]: 56
2684 04:44:01.856487
2685 04:44:01.857094 Set Vref, RX VrefLevel [Byte0]: 57
2686 04:44:01.859449 [Byte1]: 57
2687 04:44:01.864316
2688 04:44:01.864927 Set Vref, RX VrefLevel [Byte0]: 58
2689 04:44:01.867246 [Byte1]: 58
2690 04:44:01.871649
2691 04:44:01.872124 Set Vref, RX VrefLevel [Byte0]: 59
2692 04:44:01.875668 [Byte1]: 59
2693 04:44:01.881812
2694 04:44:01.882365 Set Vref, RX VrefLevel [Byte0]: 60
2695 04:44:01.883151 [Byte1]: 60
2696 04:44:01.887862
2697 04:44:01.888432 Set Vref, RX VrefLevel [Byte0]: 61
2698 04:44:01.891009 [Byte1]: 61
2699 04:44:01.895796
2700 04:44:01.896356 Set Vref, RX VrefLevel [Byte0]: 62
2701 04:44:01.899321 [Byte1]: 62
2702 04:44:01.904318
2703 04:44:01.904916 Set Vref, RX VrefLevel [Byte0]: 63
2704 04:44:01.907148 [Byte1]: 63
2705 04:44:01.911904
2706 04:44:01.912563 Set Vref, RX VrefLevel [Byte0]: 64
2707 04:44:01.914933 [Byte1]: 64
2708 04:44:01.920055
2709 04:44:01.920608 Set Vref, RX VrefLevel [Byte0]: 65
2710 04:44:01.922640 [Byte1]: 65
2711 04:44:01.927216
2712 04:44:01.927687 Final RX Vref Byte 0 = 51 to rank0
2713 04:44:01.930647 Final RX Vref Byte 1 = 48 to rank0
2714 04:44:01.934139 Final RX Vref Byte 0 = 51 to rank1
2715 04:44:01.937543 Final RX Vref Byte 1 = 48 to rank1==
2716 04:44:01.940846 Dram Type= 6, Freq= 0, CH_0, rank 0
2717 04:44:01.948124 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2718 04:44:01.948906 ==
2719 04:44:01.949303 DQS Delay:
2720 04:44:01.949651 DQS0 = 0, DQS1 = 0
2721 04:44:01.950476 DQM Delay:
2722 04:44:01.950864 DQM0 = 114, DQM1 = 105
2723 04:44:01.954162 DQ Delay:
2724 04:44:01.957815 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2725 04:44:01.961373 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2726 04:44:01.964911 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2727 04:44:01.967685 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2728 04:44:01.968322
2729 04:44:01.968751
2730 04:44:01.974848 [DQSOSCAuto] RK0, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2731 04:44:01.977335 CH0 RK0: MR19=404, MR18=606
2732 04:44:01.984664 CH0_RK0: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
2733 04:44:01.985261
2734 04:44:01.989563 ----->DramcWriteLeveling(PI) begin...
2735 04:44:01.990130 ==
2736 04:44:01.991709 Dram Type= 6, Freq= 0, CH_0, rank 1
2737 04:44:01.996648 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2738 04:44:01.997249 ==
2739 04:44:01.998296 Write leveling (Byte 0): 27 => 27
2740 04:44:02.001261 Write leveling (Byte 1): 25 => 25
2741 04:44:02.005180 DramcWriteLeveling(PI) end<-----
2742 04:44:02.005726
2743 04:44:02.006083 ==
2744 04:44:02.007546 Dram Type= 6, Freq= 0, CH_0, rank 1
2745 04:44:02.011318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2746 04:44:02.014187 ==
2747 04:44:02.014647 [Gating] SW mode calibration
2748 04:44:02.021042 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2749 04:44:02.027579 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2750 04:44:02.030888 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2751 04:44:02.037765 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2752 04:44:02.041966 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2753 04:44:02.044288 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2754 04:44:02.051278 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
2755 04:44:02.053987 0 11 20 | B1->B0 | 2c2c 2424 | 1 0 | (0 0) (0 0)
2756 04:44:02.057597 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2757 04:44:02.064325 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2758 04:44:02.067674 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2759 04:44:02.071106 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2760 04:44:02.077415 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2761 04:44:02.081360 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2762 04:44:02.084259 0 12 16 | B1->B0 | 2828 3939 | 0 0 | (0 0) (0 0)
2763 04:44:02.087359 0 12 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2764 04:44:02.093986 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2765 04:44:02.097038 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2766 04:44:02.100625 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2767 04:44:02.107977 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2768 04:44:02.110698 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2769 04:44:02.113870 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2770 04:44:02.121027 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2771 04:44:02.123743 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2772 04:44:02.127217 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2773 04:44:02.134349 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 04:44:02.137608 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 04:44:02.140548 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 04:44:02.147117 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 04:44:02.150240 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 04:44:02.154185 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 04:44:02.160807 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 04:44:02.163844 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 04:44:02.167122 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 04:44:02.173694 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 04:44:02.177074 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 04:44:02.180172 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 04:44:02.187904 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 04:44:02.190323 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2787 04:44:02.193532 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2788 04:44:02.197261 Total UI for P1: 0, mck2ui 16
2789 04:44:02.200548 best dqsien dly found for B0: ( 0, 15, 16)
2790 04:44:02.206930 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2791 04:44:02.207484 Total UI for P1: 0, mck2ui 16
2792 04:44:02.210384 best dqsien dly found for B1: ( 0, 15, 18)
2793 04:44:02.217214 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2794 04:44:02.219964 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2795 04:44:02.220522
2796 04:44:02.223755 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2797 04:44:02.227301 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2798 04:44:02.230847 [Gating] SW calibration Done
2799 04:44:02.231417 ==
2800 04:44:02.234198 Dram Type= 6, Freq= 0, CH_0, rank 1
2801 04:44:02.236812 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2802 04:44:02.237284 ==
2803 04:44:02.240444 RX Vref Scan: 0
2804 04:44:02.241054
2805 04:44:02.241424 RX Vref 0 -> 0, step: 1
2806 04:44:02.241765
2807 04:44:02.243461 RX Delay -40 -> 252, step: 8
2808 04:44:02.247619 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2809 04:44:02.253948 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2810 04:44:02.257118 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2811 04:44:02.260269 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2812 04:44:02.263384 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2813 04:44:02.266874 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2814 04:44:02.273672 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2815 04:44:02.276482 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2816 04:44:02.280642 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2817 04:44:02.283759 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2818 04:44:02.286731 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2819 04:44:02.290182 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2820 04:44:02.297545 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2821 04:44:02.300179 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2822 04:44:02.303938 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2823 04:44:02.306855 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2824 04:44:02.307399 ==
2825 04:44:02.310152 Dram Type= 6, Freq= 0, CH_0, rank 1
2826 04:44:02.317193 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2827 04:44:02.317743 ==
2828 04:44:02.318103 DQS Delay:
2829 04:44:02.319996 DQS0 = 0, DQS1 = 0
2830 04:44:02.320446 DQM Delay:
2831 04:44:02.323152 DQM0 = 115, DQM1 = 106
2832 04:44:02.323616 DQ Delay:
2833 04:44:02.326762 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111
2834 04:44:02.330036 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2835 04:44:02.333421 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2836 04:44:02.336417 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2837 04:44:02.337019
2838 04:44:02.337382
2839 04:44:02.337716 ==
2840 04:44:02.340355 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 04:44:02.343079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2842 04:44:02.346663 ==
2843 04:44:02.347220
2844 04:44:02.347579
2845 04:44:02.347910 TX Vref Scan disable
2846 04:44:02.350075 == TX Byte 0 ==
2847 04:44:02.353201 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2848 04:44:02.356905 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2849 04:44:02.360350 == TX Byte 1 ==
2850 04:44:02.363282 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2851 04:44:02.366662 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2852 04:44:02.369425 ==
2853 04:44:02.369876 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 04:44:02.377456 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2855 04:44:02.378032 ==
2856 04:44:02.387471 TX Vref=22, minBit 8, minWin=25, winSum=416
2857 04:44:02.391613 TX Vref=24, minBit 9, minWin=25, winSum=424
2858 04:44:02.394350 TX Vref=26, minBit 1, minWin=26, winSum=427
2859 04:44:02.397590 TX Vref=28, minBit 8, minWin=26, winSum=429
2860 04:44:02.400899 TX Vref=30, minBit 10, minWin=25, winSum=430
2861 04:44:02.407454 TX Vref=32, minBit 8, minWin=26, winSum=433
2862 04:44:02.411136 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 32
2863 04:44:02.411688
2864 04:44:02.414128 Final TX Range 1 Vref 32
2865 04:44:02.414681
2866 04:44:02.415233 ==
2867 04:44:02.417461 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 04:44:02.420892 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2869 04:44:02.421444 ==
2870 04:44:02.425108
2871 04:44:02.425657
2872 04:44:02.426018 TX Vref Scan disable
2873 04:44:02.427213 == TX Byte 0 ==
2874 04:44:02.431119 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2875 04:44:02.434340 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2876 04:44:02.437790 == TX Byte 1 ==
2877 04:44:02.442128 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2878 04:44:02.444653 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2879 04:44:02.445163
2880 04:44:02.447740 [DATLAT]
2881 04:44:02.448291 Freq=1200, CH0 RK1
2882 04:44:02.448658
2883 04:44:02.450886 DATLAT Default: 0xc
2884 04:44:02.451441 0, 0xFFFF, sum = 0
2885 04:44:02.454278 1, 0xFFFF, sum = 0
2886 04:44:02.454744 2, 0xFFFF, sum = 0
2887 04:44:02.458460 3, 0xFFFF, sum = 0
2888 04:44:02.459017 4, 0xFFFF, sum = 0
2889 04:44:02.461322 5, 0xFFFF, sum = 0
2890 04:44:02.461787 6, 0xFFFF, sum = 0
2891 04:44:02.464539 7, 0xFFFF, sum = 0
2892 04:44:02.465155 8, 0xFFFF, sum = 0
2893 04:44:02.468054 9, 0xFFFF, sum = 0
2894 04:44:02.471003 10, 0xFFFF, sum = 0
2895 04:44:02.471464 11, 0x0, sum = 1
2896 04:44:02.474208 12, 0x0, sum = 2
2897 04:44:02.474766 13, 0x0, sum = 3
2898 04:44:02.475135 14, 0x0, sum = 4
2899 04:44:02.477006 best_step = 12
2900 04:44:02.477459
2901 04:44:02.477818 ==
2902 04:44:02.480931 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 04:44:02.484574 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2904 04:44:02.485179 ==
2905 04:44:02.488172 RX Vref Scan: 0
2906 04:44:02.488774
2907 04:44:02.489154 RX Vref 0 -> 0, step: 1
2908 04:44:02.490369
2909 04:44:02.490819 RX Delay -21 -> 252, step: 4
2910 04:44:02.497811 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2911 04:44:02.501510 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2912 04:44:02.504596 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2913 04:44:02.507677 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2914 04:44:02.511168 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2915 04:44:02.517525 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2916 04:44:02.520598 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2917 04:44:02.523890 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2918 04:44:02.527341 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2919 04:44:02.531485 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2920 04:44:02.537934 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2921 04:44:02.541329 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2922 04:44:02.544641 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2923 04:44:02.547496 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2924 04:44:02.551831 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2925 04:44:02.557330 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2926 04:44:02.557898 ==
2927 04:44:02.561684 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 04:44:02.564360 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2929 04:44:02.564959 ==
2930 04:44:02.565333 DQS Delay:
2931 04:44:02.567554 DQS0 = 0, DQS1 = 0
2932 04:44:02.568013 DQM Delay:
2933 04:44:02.570550 DQM0 = 115, DQM1 = 105
2934 04:44:02.571012 DQ Delay:
2935 04:44:02.574773 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2936 04:44:02.577181 DQ4 =116, DQ5 =108, DQ6 =124, DQ7 =124
2937 04:44:02.580910 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2938 04:44:02.583595 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2939 04:44:02.584058
2940 04:44:02.584419
2941 04:44:02.594286 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2942 04:44:02.597641 CH0 RK1: MR19=404, MR18=F0F
2943 04:44:02.601339 CH0_RK1: MR19=0x404, MR18=0xF0F, DQSOSC=404, MR23=63, INC=40, DEC=26
2944 04:44:02.603968 [RxdqsGatingPostProcess] freq 1200
2945 04:44:02.611577 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2946 04:44:02.613970 Pre-setting of DQS Precalculation
2947 04:44:02.617036 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2948 04:44:02.621173 ==
2949 04:44:02.621725 Dram Type= 6, Freq= 0, CH_1, rank 0
2950 04:44:02.627377 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2951 04:44:02.627934 ==
2952 04:44:02.630667 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2953 04:44:02.637837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2954 04:44:02.645806 [CA 0] Center 37 (7~68) winsize 62
2955 04:44:02.649679 [CA 1] Center 37 (7~68) winsize 62
2956 04:44:02.653104 [CA 2] Center 34 (4~65) winsize 62
2957 04:44:02.656105 [CA 3] Center 33 (3~64) winsize 62
2958 04:44:02.659738 [CA 4] Center 32 (2~63) winsize 62
2959 04:44:02.662959 [CA 5] Center 32 (1~63) winsize 63
2960 04:44:02.663511
2961 04:44:02.666315 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2962 04:44:02.666867
2963 04:44:02.668821 [CATrainingPosCal] consider 1 rank data
2964 04:44:02.672593 u2DelayCellTimex100 = 270/100 ps
2965 04:44:02.676966 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2966 04:44:02.679405 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2967 04:44:02.686036 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2968 04:44:02.689363 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2969 04:44:02.692403 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2970 04:44:02.696386 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2971 04:44:02.697025
2972 04:44:02.699965 CA PerBit enable=1, Macro0, CA PI delay=32
2973 04:44:02.700517
2974 04:44:02.702105 [CBTSetCACLKResult] CA Dly = 32
2975 04:44:02.702572 CS Dly: 5 (0~36)
2976 04:44:02.705627 ==
2977 04:44:02.706179 Dram Type= 6, Freq= 0, CH_1, rank 1
2978 04:44:02.712826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2979 04:44:02.713385 ==
2980 04:44:02.716001 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2981 04:44:02.722615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2982 04:44:02.731609 [CA 0] Center 37 (6~68) winsize 63
2983 04:44:02.735238 [CA 1] Center 37 (7~68) winsize 62
2984 04:44:02.738015 [CA 2] Center 33 (3~64) winsize 62
2985 04:44:02.741686 [CA 3] Center 33 (3~64) winsize 62
2986 04:44:02.745371 [CA 4] Center 32 (2~63) winsize 62
2987 04:44:02.748063 [CA 5] Center 32 (1~63) winsize 63
2988 04:44:02.748616
2989 04:44:02.751496 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2990 04:44:02.752046
2991 04:44:02.754894 [CATrainingPosCal] consider 2 rank data
2992 04:44:02.758615 u2DelayCellTimex100 = 270/100 ps
2993 04:44:02.761750 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2994 04:44:02.764561 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2995 04:44:02.770922 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2996 04:44:02.775174 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2997 04:44:02.777809 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2998 04:44:02.781024 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2999 04:44:02.781486
3000 04:44:02.784652 CA PerBit enable=1, Macro0, CA PI delay=32
3001 04:44:02.785183
3002 04:44:02.787918 [CBTSetCACLKResult] CA Dly = 32
3003 04:44:02.788468 CS Dly: 6 (0~38)
3004 04:44:02.788924
3005 04:44:02.792132 ----->DramcWriteLeveling(PI) begin...
3006 04:44:02.794969 ==
3007 04:44:02.795521 Dram Type= 6, Freq= 0, CH_1, rank 0
3008 04:44:02.801764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3009 04:44:02.802321 ==
3010 04:44:02.804302 Write leveling (Byte 0): 21 => 21
3011 04:44:02.808083 Write leveling (Byte 1): 23 => 23
3012 04:44:02.812095 DramcWriteLeveling(PI) end<-----
3013 04:44:02.812646
3014 04:44:02.813123 ==
3015 04:44:02.814728 Dram Type= 6, Freq= 0, CH_1, rank 0
3016 04:44:02.817482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3017 04:44:02.817944 ==
3018 04:44:02.821943 [Gating] SW mode calibration
3019 04:44:02.828874 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3020 04:44:02.830859 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3021 04:44:02.838122 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3022 04:44:02.841384 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3023 04:44:02.845253 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3024 04:44:02.851218 0 11 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3025 04:44:02.854790 0 11 16 | B1->B0 | 3232 2a2a | 1 1 | (1 1) (1 0)
3026 04:44:02.859985 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3027 04:44:02.864840 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3028 04:44:02.867884 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3029 04:44:02.870991 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3030 04:44:02.877690 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3031 04:44:02.882345 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3032 04:44:02.884302 0 12 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3033 04:44:02.891427 0 12 16 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
3034 04:44:02.894779 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3035 04:44:02.898861 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3036 04:44:02.904562 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3037 04:44:02.907938 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3038 04:44:02.911321 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3039 04:44:02.917278 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3040 04:44:02.920505 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3041 04:44:02.924460 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3042 04:44:02.931408 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3043 04:44:02.934387 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3044 04:44:02.937494 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 04:44:02.941375 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 04:44:02.947372 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 04:44:02.951786 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 04:44:02.954816 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 04:44:02.960860 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 04:44:02.964947 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 04:44:02.969413 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 04:44:02.974292 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 04:44:02.977502 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 04:44:02.980995 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 04:44:02.987817 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 04:44:02.991134 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3057 04:44:02.994472 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3058 04:44:03.001124 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3059 04:44:03.001680 Total UI for P1: 0, mck2ui 16
3060 04:44:03.007758 best dqsien dly found for B0: ( 0, 15, 16)
3061 04:44:03.010838 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3062 04:44:03.014145 Total UI for P1: 0, mck2ui 16
3063 04:44:03.017324 best dqsien dly found for B1: ( 0, 15, 18)
3064 04:44:03.020815 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3065 04:44:03.023703 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3066 04:44:03.024186
3067 04:44:03.027492 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3068 04:44:03.030685 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3069 04:44:03.034382 [Gating] SW calibration Done
3070 04:44:03.034993 ==
3071 04:44:03.037333 Dram Type= 6, Freq= 0, CH_1, rank 0
3072 04:44:03.040378 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3073 04:44:03.044237 ==
3074 04:44:03.044887 RX Vref Scan: 0
3075 04:44:03.045439
3076 04:44:03.047634 RX Vref 0 -> 0, step: 1
3077 04:44:03.048089
3078 04:44:03.050947 RX Delay -40 -> 252, step: 8
3079 04:44:03.054142 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3080 04:44:03.058018 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3081 04:44:03.061213 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3082 04:44:03.065141 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3083 04:44:03.071066 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3084 04:44:03.073709 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3085 04:44:03.077635 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3086 04:44:03.081054 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3087 04:44:03.084485 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3088 04:44:03.087403 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3089 04:44:03.094177 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3090 04:44:03.097666 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3091 04:44:03.100434 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3092 04:44:03.104065 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3093 04:44:03.107923 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3094 04:44:03.114413 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3095 04:44:03.114957 ==
3096 04:44:03.117914 Dram Type= 6, Freq= 0, CH_1, rank 0
3097 04:44:03.120598 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3098 04:44:03.121122 ==
3099 04:44:03.121491 DQS Delay:
3100 04:44:03.125130 DQS0 = 0, DQS1 = 0
3101 04:44:03.125680 DQM Delay:
3102 04:44:03.127077 DQM0 = 116, DQM1 = 107
3103 04:44:03.127536 DQ Delay:
3104 04:44:03.130824 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3105 04:44:03.133587 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3106 04:44:03.137142 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3107 04:44:03.140765 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3108 04:44:03.141322
3109 04:44:03.144347
3110 04:44:03.144949 ==
3111 04:44:03.147210 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 04:44:03.150446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3113 04:44:03.150994 ==
3114 04:44:03.151359
3115 04:44:03.151696
3116 04:44:03.153602 TX Vref Scan disable
3117 04:44:03.154062 == TX Byte 0 ==
3118 04:44:03.156759 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3119 04:44:03.164116 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3120 04:44:03.164670 == TX Byte 1 ==
3121 04:44:03.168249 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3122 04:44:03.173819 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3123 04:44:03.174279 ==
3124 04:44:03.177554 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 04:44:03.181326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3126 04:44:03.181933 ==
3127 04:44:03.193077 TX Vref=22, minBit 0, minWin=25, winSum=413
3128 04:44:03.195816 TX Vref=24, minBit 10, minWin=25, winSum=422
3129 04:44:03.198773 TX Vref=26, minBit 0, minWin=26, winSum=424
3130 04:44:03.202683 TX Vref=28, minBit 15, minWin=25, winSum=427
3131 04:44:03.206291 TX Vref=30, minBit 0, minWin=26, winSum=427
3132 04:44:03.212526 TX Vref=32, minBit 3, minWin=26, winSum=431
3133 04:44:03.216416 [TxChooseVref] Worse bit 3, Min win 26, Win sum 431, Final Vref 32
3134 04:44:03.217054
3135 04:44:03.219749 Final TX Range 1 Vref 32
3136 04:44:03.220210
3137 04:44:03.220577 ==
3138 04:44:03.222448 Dram Type= 6, Freq= 0, CH_1, rank 0
3139 04:44:03.225922 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3140 04:44:03.226399 ==
3141 04:44:03.229599
3142 04:44:03.230178
3143 04:44:03.230562 TX Vref Scan disable
3144 04:44:03.233481 == TX Byte 0 ==
3145 04:44:03.236193 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3146 04:44:03.238797 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3147 04:44:03.242505 == TX Byte 1 ==
3148 04:44:03.245448 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3149 04:44:03.249270 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3150 04:44:03.252203
3151 04:44:03.252659 [DATLAT]
3152 04:44:03.253062 Freq=1200, CH1 RK0
3153 04:44:03.253405
3154 04:44:03.255543 DATLAT Default: 0xd
3155 04:44:03.256096 0, 0xFFFF, sum = 0
3156 04:44:03.259332 1, 0xFFFF, sum = 0
3157 04:44:03.259890 2, 0xFFFF, sum = 0
3158 04:44:03.262793 3, 0xFFFF, sum = 0
3159 04:44:03.263350 4, 0xFFFF, sum = 0
3160 04:44:03.265334 5, 0xFFFF, sum = 0
3161 04:44:03.269136 6, 0xFFFF, sum = 0
3162 04:44:03.269600 7, 0xFFFF, sum = 0
3163 04:44:03.272544 8, 0xFFFF, sum = 0
3164 04:44:03.273039 9, 0xFFFF, sum = 0
3165 04:44:03.275611 10, 0xFFFF, sum = 0
3166 04:44:03.276095 11, 0x0, sum = 1
3167 04:44:03.279359 12, 0x0, sum = 2
3168 04:44:03.279914 13, 0x0, sum = 3
3169 04:44:03.280328 14, 0x0, sum = 4
3170 04:44:03.281836 best_step = 12
3171 04:44:03.282361
3172 04:44:03.282729 ==
3173 04:44:03.286215 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 04:44:03.289508 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3175 04:44:03.290059 ==
3176 04:44:03.292478 RX Vref Scan: 1
3177 04:44:03.293074
3178 04:44:03.295271 Set Vref Range= 32 -> 127
3179 04:44:03.295733
3180 04:44:03.296092 RX Vref 32 -> 127, step: 1
3181 04:44:03.296425
3182 04:44:03.298769 RX Delay -29 -> 252, step: 4
3183 04:44:03.299318
3184 04:44:03.302655 Set Vref, RX VrefLevel [Byte0]: 32
3185 04:44:03.305726 [Byte1]: 32
3186 04:44:03.309040
3187 04:44:03.309761 Set Vref, RX VrefLevel [Byte0]: 33
3188 04:44:03.312829 [Byte1]: 33
3189 04:44:03.317248
3190 04:44:03.317817 Set Vref, RX VrefLevel [Byte0]: 34
3191 04:44:03.320353 [Byte1]: 34
3192 04:44:03.324885
3193 04:44:03.325428 Set Vref, RX VrefLevel [Byte0]: 35
3194 04:44:03.328754 [Byte1]: 35
3195 04:44:03.332838
3196 04:44:03.333382 Set Vref, RX VrefLevel [Byte0]: 36
3197 04:44:03.336556 [Byte1]: 36
3198 04:44:03.341148
3199 04:44:03.341699 Set Vref, RX VrefLevel [Byte0]: 37
3200 04:44:03.344508 [Byte1]: 37
3201 04:44:03.348836
3202 04:44:03.349295 Set Vref, RX VrefLevel [Byte0]: 38
3203 04:44:03.352142 [Byte1]: 38
3204 04:44:03.357053
3205 04:44:03.357603 Set Vref, RX VrefLevel [Byte0]: 39
3206 04:44:03.359765 [Byte1]: 39
3207 04:44:03.365139
3208 04:44:03.365694 Set Vref, RX VrefLevel [Byte0]: 40
3209 04:44:03.367900 [Byte1]: 40
3210 04:44:03.372325
3211 04:44:03.372813 Set Vref, RX VrefLevel [Byte0]: 41
3212 04:44:03.377077 [Byte1]: 41
3213 04:44:03.380785
3214 04:44:03.381336 Set Vref, RX VrefLevel [Byte0]: 42
3215 04:44:03.384069 [Byte1]: 42
3216 04:44:03.388919
3217 04:44:03.389470 Set Vref, RX VrefLevel [Byte0]: 43
3218 04:44:03.392209 [Byte1]: 43
3219 04:44:03.397212
3220 04:44:03.397765 Set Vref, RX VrefLevel [Byte0]: 44
3221 04:44:03.400262 [Byte1]: 44
3222 04:44:03.404385
3223 04:44:03.404968 Set Vref, RX VrefLevel [Byte0]: 45
3224 04:44:03.407858 [Byte1]: 45
3225 04:44:03.413355
3226 04:44:03.413906 Set Vref, RX VrefLevel [Byte0]: 46
3227 04:44:03.415860 [Byte1]: 46
3228 04:44:03.420284
3229 04:44:03.420959 Set Vref, RX VrefLevel [Byte0]: 47
3230 04:44:03.424145 [Byte1]: 47
3231 04:44:03.428360
3232 04:44:03.428977 Set Vref, RX VrefLevel [Byte0]: 48
3233 04:44:03.432039 [Byte1]: 48
3234 04:44:03.436877
3235 04:44:03.437421 Set Vref, RX VrefLevel [Byte0]: 49
3236 04:44:03.439595 [Byte1]: 49
3237 04:44:03.445010
3238 04:44:03.445559 Set Vref, RX VrefLevel [Byte0]: 50
3239 04:44:03.447950 [Byte1]: 50
3240 04:44:03.452586
3241 04:44:03.453187 Set Vref, RX VrefLevel [Byte0]: 51
3242 04:44:03.455900 [Byte1]: 51
3243 04:44:03.460189
3244 04:44:03.460772 Set Vref, RX VrefLevel [Byte0]: 52
3245 04:44:03.463738 [Byte1]: 52
3246 04:44:03.468677
3247 04:44:03.469268 Set Vref, RX VrefLevel [Byte0]: 53
3248 04:44:03.471398 [Byte1]: 53
3249 04:44:03.476614
3250 04:44:03.477207 Set Vref, RX VrefLevel [Byte0]: 54
3251 04:44:03.479432 [Byte1]: 54
3252 04:44:03.484145
3253 04:44:03.484696 Set Vref, RX VrefLevel [Byte0]: 55
3254 04:44:03.488005 [Byte1]: 55
3255 04:44:03.492597
3256 04:44:03.493193 Set Vref, RX VrefLevel [Byte0]: 56
3257 04:44:03.495910 [Byte1]: 56
3258 04:44:03.500804
3259 04:44:03.501355 Set Vref, RX VrefLevel [Byte0]: 57
3260 04:44:03.503297 [Byte1]: 57
3261 04:44:03.508702
3262 04:44:03.509292 Set Vref, RX VrefLevel [Byte0]: 58
3263 04:44:03.511545 [Byte1]: 58
3264 04:44:03.516273
3265 04:44:03.516863 Set Vref, RX VrefLevel [Byte0]: 59
3266 04:44:03.519393 [Byte1]: 59
3267 04:44:03.523946
3268 04:44:03.524497 Set Vref, RX VrefLevel [Byte0]: 60
3269 04:44:03.527478 [Byte1]: 60
3270 04:44:03.531975
3271 04:44:03.532600 Set Vref, RX VrefLevel [Byte0]: 61
3272 04:44:03.534797 [Byte1]: 61
3273 04:44:03.540194
3274 04:44:03.540812 Set Vref, RX VrefLevel [Byte0]: 62
3275 04:44:03.543285 [Byte1]: 62
3276 04:44:03.548187
3277 04:44:03.548771 Set Vref, RX VrefLevel [Byte0]: 63
3278 04:44:03.551844 [Byte1]: 63
3279 04:44:03.555583
3280 04:44:03.556136 Set Vref, RX VrefLevel [Byte0]: 64
3281 04:44:03.561089 [Byte1]: 64
3282 04:44:03.563837
3283 04:44:03.564400 Set Vref, RX VrefLevel [Byte0]: 65
3284 04:44:03.567004 [Byte1]: 65
3285 04:44:03.572027
3286 04:44:03.572578 Set Vref, RX VrefLevel [Byte0]: 66
3287 04:44:03.574675 [Byte1]: 66
3288 04:44:03.579924
3289 04:44:03.580477 Final RX Vref Byte 0 = 52 to rank0
3290 04:44:03.582874 Final RX Vref Byte 1 = 48 to rank0
3291 04:44:03.586380 Final RX Vref Byte 0 = 52 to rank1
3292 04:44:03.589792 Final RX Vref Byte 1 = 48 to rank1==
3293 04:44:03.593334 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 04:44:03.599538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3295 04:44:03.600093 ==
3296 04:44:03.600458 DQS Delay:
3297 04:44:03.600842 DQS0 = 0, DQS1 = 0
3298 04:44:03.603424 DQM Delay:
3299 04:44:03.603973 DQM0 = 115, DQM1 = 105
3300 04:44:03.606562 DQ Delay:
3301 04:44:03.610151 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3302 04:44:03.612624 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3303 04:44:03.616244 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =98
3304 04:44:03.619403 DQ12 =112, DQ13 =116, DQ14 =114, DQ15 =112
3305 04:44:03.619865
3306 04:44:03.620227
3307 04:44:03.626006 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
3308 04:44:03.629941 CH1 RK0: MR19=404, MR18=1B1B
3309 04:44:03.636801 CH1_RK0: MR19=0x404, MR18=0x1B1B, DQSOSC=399, MR23=63, INC=41, DEC=27
3310 04:44:03.637354
3311 04:44:03.639806 ----->DramcWriteLeveling(PI) begin...
3312 04:44:03.640365 ==
3313 04:44:03.642997 Dram Type= 6, Freq= 0, CH_1, rank 1
3314 04:44:03.646489 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3315 04:44:03.647053 ==
3316 04:44:03.650105 Write leveling (Byte 0): 20 => 20
3317 04:44:03.653191 Write leveling (Byte 1): 20 => 20
3318 04:44:03.656184 DramcWriteLeveling(PI) end<-----
3319 04:44:03.656779
3320 04:44:03.657156 ==
3321 04:44:03.659364 Dram Type= 6, Freq= 0, CH_1, rank 1
3322 04:44:03.667146 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3323 04:44:03.667704 ==
3324 04:44:03.668068 [Gating] SW mode calibration
3325 04:44:03.675788 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3326 04:44:03.679712 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3327 04:44:03.682702 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3328 04:44:03.689584 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3329 04:44:03.694102 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3330 04:44:03.696471 0 11 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
3331 04:44:03.702711 0 11 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
3332 04:44:03.706733 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3333 04:44:03.709100 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3334 04:44:03.716087 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3335 04:44:03.719324 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3336 04:44:03.722862 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3337 04:44:03.730240 0 12 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3338 04:44:03.733151 0 12 12 | B1->B0 | 2424 3c3c | 0 1 | (0 0) (0 0)
3339 04:44:03.736086 0 12 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3340 04:44:03.742887 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3341 04:44:03.745787 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3342 04:44:03.749457 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3343 04:44:03.756170 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3344 04:44:03.759065 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3345 04:44:03.763094 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3346 04:44:03.766215 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3347 04:44:03.772490 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3348 04:44:03.776201 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3349 04:44:03.779269 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3350 04:44:03.786321 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3351 04:44:03.790009 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3352 04:44:03.792557 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3353 04:44:03.799947 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 04:44:03.802733 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3355 04:44:03.806154 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 04:44:03.812524 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 04:44:03.817636 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 04:44:03.820115 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3359 04:44:03.826312 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3360 04:44:03.829272 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3361 04:44:03.832461 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3362 04:44:03.840800 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3363 04:44:03.842570 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3364 04:44:03.846263 Total UI for P1: 0, mck2ui 16
3365 04:44:03.849398 best dqsien dly found for B0: ( 0, 15, 12)
3366 04:44:03.852693 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3367 04:44:03.855736 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3368 04:44:03.859305 Total UI for P1: 0, mck2ui 16
3369 04:44:03.862777 best dqsien dly found for B1: ( 0, 15, 18)
3370 04:44:03.869161 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3371 04:44:03.872879 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3372 04:44:03.873376
3373 04:44:03.876472 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3374 04:44:03.880114 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3375 04:44:03.882751 [Gating] SW calibration Done
3376 04:44:03.883211 ==
3377 04:44:03.886401 Dram Type= 6, Freq= 0, CH_1, rank 1
3378 04:44:03.889931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3379 04:44:03.890495 ==
3380 04:44:03.892905 RX Vref Scan: 0
3381 04:44:03.893360
3382 04:44:03.893720 RX Vref 0 -> 0, step: 1
3383 04:44:03.894057
3384 04:44:03.896124 RX Delay -40 -> 252, step: 8
3385 04:44:03.899709 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3386 04:44:03.903414 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3387 04:44:03.909309 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3388 04:44:03.912841 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3389 04:44:03.916040 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3390 04:44:03.919591 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3391 04:44:03.922693 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3392 04:44:03.929408 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3393 04:44:03.933001 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3394 04:44:03.935940 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3395 04:44:03.939310 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3396 04:44:03.943155 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3397 04:44:03.949945 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3398 04:44:03.953276 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3399 04:44:03.956853 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3400 04:44:03.960897 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3401 04:44:03.961447 ==
3402 04:44:03.962814 Dram Type= 6, Freq= 0, CH_1, rank 1
3403 04:44:03.969177 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3404 04:44:03.969726 ==
3405 04:44:03.970087 DQS Delay:
3406 04:44:03.972624 DQS0 = 0, DQS1 = 0
3407 04:44:03.973188 DQM Delay:
3408 04:44:03.973556 DQM0 = 116, DQM1 = 106
3409 04:44:03.976157 DQ Delay:
3410 04:44:03.979271 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3411 04:44:03.983140 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3412 04:44:03.986297 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =103
3413 04:44:03.989162 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3414 04:44:03.989611
3415 04:44:03.989964
3416 04:44:03.990325 ==
3417 04:44:03.992842 Dram Type= 6, Freq= 0, CH_1, rank 1
3418 04:44:03.996667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3419 04:44:03.997274 ==
3420 04:44:03.999686
3421 04:44:04.000228
3422 04:44:04.000579 TX Vref Scan disable
3423 04:44:04.003360 == TX Byte 0 ==
3424 04:44:04.005971 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3425 04:44:04.009738 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3426 04:44:04.012779 == TX Byte 1 ==
3427 04:44:04.016332 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3428 04:44:04.019181 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3429 04:44:04.019734 ==
3430 04:44:04.022841 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 04:44:04.028938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3432 04:44:04.029390 ==
3433 04:44:04.039623 TX Vref=22, minBit 9, minWin=25, winSum=421
3434 04:44:04.042914 TX Vref=24, minBit 9, minWin=25, winSum=425
3435 04:44:04.046170 TX Vref=26, minBit 11, minWin=25, winSum=427
3436 04:44:04.049402 TX Vref=28, minBit 9, minWin=26, winSum=433
3437 04:44:04.053096 TX Vref=30, minBit 9, minWin=26, winSum=434
3438 04:44:04.060307 TX Vref=32, minBit 9, minWin=26, winSum=430
3439 04:44:04.063033 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3440 04:44:04.063589
3441 04:44:04.067213 Final TX Range 1 Vref 30
3442 04:44:04.067762
3443 04:44:04.068117 ==
3444 04:44:04.070088 Dram Type= 6, Freq= 0, CH_1, rank 1
3445 04:44:04.072584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3446 04:44:04.073176 ==
3447 04:44:04.076432
3448 04:44:04.077066
3449 04:44:04.077430 TX Vref Scan disable
3450 04:44:04.079866 == TX Byte 0 ==
3451 04:44:04.083372 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3452 04:44:04.086636 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3453 04:44:04.089346 == TX Byte 1 ==
3454 04:44:04.092508 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3455 04:44:04.096088 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3456 04:44:04.099331
3457 04:44:04.099875 [DATLAT]
3458 04:44:04.100234 Freq=1200, CH1 RK1
3459 04:44:04.100570
3460 04:44:04.102880 DATLAT Default: 0xc
3461 04:44:04.103425 0, 0xFFFF, sum = 0
3462 04:44:04.105794 1, 0xFFFF, sum = 0
3463 04:44:04.106254 2, 0xFFFF, sum = 0
3464 04:44:04.109516 3, 0xFFFF, sum = 0
3465 04:44:04.110071 4, 0xFFFF, sum = 0
3466 04:44:04.113506 5, 0xFFFF, sum = 0
3467 04:44:04.116685 6, 0xFFFF, sum = 0
3468 04:44:04.117291 7, 0xFFFF, sum = 0
3469 04:44:04.119182 8, 0xFFFF, sum = 0
3470 04:44:04.119718 9, 0xFFFF, sum = 0
3471 04:44:04.123847 10, 0xFFFF, sum = 0
3472 04:44:04.124362 11, 0x0, sum = 1
3473 04:44:04.126263 12, 0x0, sum = 2
3474 04:44:04.126730 13, 0x0, sum = 3
3475 04:44:04.127104 14, 0x0, sum = 4
3476 04:44:04.129350 best_step = 12
3477 04:44:04.129807
3478 04:44:04.130168 ==
3479 04:44:04.132491 Dram Type= 6, Freq= 0, CH_1, rank 1
3480 04:44:04.137088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3481 04:44:04.137641 ==
3482 04:44:04.139432 RX Vref Scan: 0
3483 04:44:04.139982
3484 04:44:04.140345 RX Vref 0 -> 0, step: 1
3485 04:44:04.143110
3486 04:44:04.143685 RX Delay -29 -> 252, step: 4
3487 04:44:04.150060 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3488 04:44:04.153063 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3489 04:44:04.156502 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3490 04:44:04.160073 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3491 04:44:04.163129 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3492 04:44:04.170220 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3493 04:44:04.173446 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3494 04:44:04.176330 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3495 04:44:04.180371 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3496 04:44:04.183573 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3497 04:44:04.189601 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3498 04:44:04.193146 iDelay=199, Bit 11, Center 96 (31 ~ 162) 132
3499 04:44:04.196666 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3500 04:44:04.200180 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3501 04:44:04.202980 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3502 04:44:04.209676 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3503 04:44:04.210231 ==
3504 04:44:04.212801 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 04:44:04.216580 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3506 04:44:04.217198 ==
3507 04:44:04.217602 DQS Delay:
3508 04:44:04.219836 DQS0 = 0, DQS1 = 0
3509 04:44:04.220296 DQM Delay:
3510 04:44:04.222955 DQM0 = 114, DQM1 = 103
3511 04:44:04.223414 DQ Delay:
3512 04:44:04.226390 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3513 04:44:04.229546 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3514 04:44:04.232911 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =96
3515 04:44:04.236242 DQ12 =114, DQ13 =112, DQ14 =112, DQ15 =112
3516 04:44:04.236846
3517 04:44:04.237222
3518 04:44:04.246086 [DQSOSCAuto] RK1, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3519 04:44:04.249626 CH1 RK1: MR19=404, MR18=808
3520 04:44:04.253301 CH1_RK1: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26
3521 04:44:04.256416 [RxdqsGatingPostProcess] freq 1200
3522 04:44:04.263273 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3523 04:44:04.266167 Pre-setting of DQS Precalculation
3524 04:44:04.269374 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3525 04:44:04.279692 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3526 04:44:04.286542 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3527 04:44:04.287094
3528 04:44:04.287458
3529 04:44:04.289198 [Calibration Summary] 2400 Mbps
3530 04:44:04.289658 CH 0, Rank 0
3531 04:44:04.292746 SW Impedance : PASS
3532 04:44:04.293210 DUTY Scan : NO K
3533 04:44:04.296141 ZQ Calibration : PASS
3534 04:44:04.299600 Jitter Meter : NO K
3535 04:44:04.300153 CBT Training : PASS
3536 04:44:04.302611 Write leveling : PASS
3537 04:44:04.305662 RX DQS gating : PASS
3538 04:44:04.306270 RX DQ/DQS(RDDQC) : PASS
3539 04:44:04.309211 TX DQ/DQS : PASS
3540 04:44:04.312267 RX DATLAT : PASS
3541 04:44:04.312985 RX DQ/DQS(Engine): PASS
3542 04:44:04.315733 TX OE : NO K
3543 04:44:04.316194 All Pass.
3544 04:44:04.316697
3545 04:44:04.319221 CH 0, Rank 1
3546 04:44:04.319702 SW Impedance : PASS
3547 04:44:04.323385 DUTY Scan : NO K
3548 04:44:04.325737 ZQ Calibration : PASS
3549 04:44:04.326198 Jitter Meter : NO K
3550 04:44:04.329015 CBT Training : PASS
3551 04:44:04.332911 Write leveling : PASS
3552 04:44:04.333490 RX DQS gating : PASS
3553 04:44:04.335740 RX DQ/DQS(RDDQC) : PASS
3554 04:44:04.336217 TX DQ/DQS : PASS
3555 04:44:04.338891 RX DATLAT : PASS
3556 04:44:04.342641 RX DQ/DQS(Engine): PASS
3557 04:44:04.343222 TX OE : NO K
3558 04:44:04.345567 All Pass.
3559 04:44:04.346042
3560 04:44:04.346524 CH 1, Rank 0
3561 04:44:04.349887 SW Impedance : PASS
3562 04:44:04.350465 DUTY Scan : NO K
3563 04:44:04.352459 ZQ Calibration : PASS
3564 04:44:04.356175 Jitter Meter : NO K
3565 04:44:04.356799 CBT Training : PASS
3566 04:44:04.359135 Write leveling : PASS
3567 04:44:04.362908 RX DQS gating : PASS
3568 04:44:04.363490 RX DQ/DQS(RDDQC) : PASS
3569 04:44:04.366660 TX DQ/DQS : PASS
3570 04:44:04.369630 RX DATLAT : PASS
3571 04:44:04.370127 RX DQ/DQS(Engine): PASS
3572 04:44:04.372131 TX OE : NO K
3573 04:44:04.372611 All Pass.
3574 04:44:04.373125
3575 04:44:04.376815 CH 1, Rank 1
3576 04:44:04.377388 SW Impedance : PASS
3577 04:44:04.379425 DUTY Scan : NO K
3578 04:44:04.382818 ZQ Calibration : PASS
3579 04:44:04.383293 Jitter Meter : NO K
3580 04:44:04.385451 CBT Training : PASS
3581 04:44:04.385928 Write leveling : PASS
3582 04:44:04.389027 RX DQS gating : PASS
3583 04:44:04.392502 RX DQ/DQS(RDDQC) : PASS
3584 04:44:04.393140 TX DQ/DQS : PASS
3585 04:44:04.395535 RX DATLAT : PASS
3586 04:44:04.399223 RX DQ/DQS(Engine): PASS
3587 04:44:04.399809 TX OE : NO K
3588 04:44:04.402131 All Pass.
3589 04:44:04.402713
3590 04:44:04.403205 DramC Write-DBI off
3591 04:44:04.405415 PER_BANK_REFRESH: Hybrid Mode
3592 04:44:04.409094 TX_TRACKING: ON
3593 04:44:04.415708 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3594 04:44:04.419680 [FAST_K] Save calibration result to emmc
3595 04:44:04.422664 dramc_set_vcore_voltage set vcore to 650000
3596 04:44:04.425307 Read voltage for 600, 5
3597 04:44:04.425946 Vio18 = 0
3598 04:44:04.428701 Vcore = 650000
3599 04:44:04.429318 Vdram = 0
3600 04:44:04.429694 Vddq = 0
3601 04:44:04.432446 Vmddr = 0
3602 04:44:04.435747 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3603 04:44:04.442386 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3604 04:44:04.442968 MEM_TYPE=3, freq_sel=19
3605 04:44:04.445759 sv_algorithm_assistance_LP4_1600
3606 04:44:04.452359 ============ PULL DRAM RESETB DOWN ============
3607 04:44:04.456267 ========== PULL DRAM RESETB DOWN end =========
3608 04:44:04.459226 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3609 04:44:04.462256 ===================================
3610 04:44:04.465840 LPDDR4 DRAM CONFIGURATION
3611 04:44:04.469350 ===================================
3612 04:44:04.469902 EX_ROW_EN[0] = 0x0
3613 04:44:04.472773 EX_ROW_EN[1] = 0x0
3614 04:44:04.475840 LP4Y_EN = 0x0
3615 04:44:04.476405 WORK_FSP = 0x0
3616 04:44:04.479305 WL = 0x2
3617 04:44:04.479860 RL = 0x2
3618 04:44:04.482429 BL = 0x2
3619 04:44:04.482890 RPST = 0x0
3620 04:44:04.486066 RD_PRE = 0x0
3621 04:44:04.486616 WR_PRE = 0x1
3622 04:44:04.489245 WR_PST = 0x0
3623 04:44:04.489795 DBI_WR = 0x0
3624 04:44:04.492065 DBI_RD = 0x0
3625 04:44:04.492628 OTF = 0x1
3626 04:44:04.495873 ===================================
3627 04:44:04.499116 ===================================
3628 04:44:04.501963 ANA top config
3629 04:44:04.505392 ===================================
3630 04:44:04.505943 DLL_ASYNC_EN = 0
3631 04:44:04.509323 ALL_SLAVE_EN = 1
3632 04:44:04.512162 NEW_RANK_MODE = 1
3633 04:44:04.515226 DLL_IDLE_MODE = 1
3634 04:44:04.519297 LP45_APHY_COMB_EN = 1
3635 04:44:04.519917 TX_ODT_DIS = 1
3636 04:44:04.522406 NEW_8X_MODE = 1
3637 04:44:04.524853 ===================================
3638 04:44:04.528455 ===================================
3639 04:44:04.532341 data_rate = 1200
3640 04:44:04.536049 CKR = 1
3641 04:44:04.538855 DQ_P2S_RATIO = 8
3642 04:44:04.542224 ===================================
3643 04:44:04.542777 CA_P2S_RATIO = 8
3644 04:44:04.545095 DQ_CA_OPEN = 0
3645 04:44:04.548214 DQ_SEMI_OPEN = 0
3646 04:44:04.551687 CA_SEMI_OPEN = 0
3647 04:44:04.554994 CA_FULL_RATE = 0
3648 04:44:04.558216 DQ_CKDIV4_EN = 1
3649 04:44:04.558765 CA_CKDIV4_EN = 1
3650 04:44:04.561722 CA_PREDIV_EN = 0
3651 04:44:04.564930 PH8_DLY = 0
3652 04:44:04.568529 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3653 04:44:04.571697 DQ_AAMCK_DIV = 4
3654 04:44:04.574372 CA_AAMCK_DIV = 4
3655 04:44:04.578892 CA_ADMCK_DIV = 4
3656 04:44:04.579448 DQ_TRACK_CA_EN = 0
3657 04:44:04.581429 CA_PICK = 600
3658 04:44:04.584749 CA_MCKIO = 600
3659 04:44:04.588823 MCKIO_SEMI = 0
3660 04:44:04.591760 PLL_FREQ = 2288
3661 04:44:04.594905 DQ_UI_PI_RATIO = 32
3662 04:44:04.597856 CA_UI_PI_RATIO = 0
3663 04:44:04.601387 ===================================
3664 04:44:04.601938 ===================================
3665 04:44:04.605282 memory_type:LPDDR4
3666 04:44:04.608384 GP_NUM : 10
3667 04:44:04.609189 SRAM_EN : 1
3668 04:44:04.611669 MD32_EN : 0
3669 04:44:04.614627 ===================================
3670 04:44:04.618111 [ANA_INIT] >>>>>>>>>>>>>>
3671 04:44:04.621811 <<<<<< [CONFIGURE PHASE]: ANA_TX
3672 04:44:04.624356 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3673 04:44:04.627566 ===================================
3674 04:44:04.631153 data_rate = 1200,PCW = 0X5800
3675 04:44:04.631614 ===================================
3676 04:44:04.637614 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3677 04:44:04.641159 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3678 04:44:04.648647 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3679 04:44:04.651719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3680 04:44:04.655121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3681 04:44:04.657969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3682 04:44:04.661084 [ANA_INIT] flow start
3683 04:44:04.664398 [ANA_INIT] PLL >>>>>>>>
3684 04:44:04.665001 [ANA_INIT] PLL <<<<<<<<
3685 04:44:04.668156 [ANA_INIT] MIDPI >>>>>>>>
3686 04:44:04.671292 [ANA_INIT] MIDPI <<<<<<<<
3687 04:44:04.671845 [ANA_INIT] DLL >>>>>>>>
3688 04:44:04.674129 [ANA_INIT] flow end
3689 04:44:04.677389 ============ LP4 DIFF to SE enter ============
3690 04:44:04.684638 ============ LP4 DIFF to SE exit ============
3691 04:44:04.685248 [ANA_INIT] <<<<<<<<<<<<<
3692 04:44:04.687668 [Flow] Enable top DCM control >>>>>
3693 04:44:04.691162 [Flow] Enable top DCM control <<<<<
3694 04:44:04.694040 Enable DLL master slave shuffle
3695 04:44:04.700547 ==============================================================
3696 04:44:04.701141 Gating Mode config
3697 04:44:04.707547 ==============================================================
3698 04:44:04.710764 Config description:
3699 04:44:04.717708 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3700 04:44:04.726498 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3701 04:44:04.730129 SELPH_MODE 0: By rank 1: By Phase
3702 04:44:04.737087 ==============================================================
3703 04:44:04.740354 GAT_TRACK_EN = 1
3704 04:44:04.740961 RX_GATING_MODE = 2
3705 04:44:04.744457 RX_GATING_TRACK_MODE = 2
3706 04:44:04.746982 SELPH_MODE = 1
3707 04:44:04.750088 PICG_EARLY_EN = 1
3708 04:44:04.754091 VALID_LAT_VALUE = 1
3709 04:44:04.760388 ==============================================================
3710 04:44:04.763677 Enter into Gating configuration >>>>
3711 04:44:04.766762 Exit from Gating configuration <<<<
3712 04:44:04.770087 Enter into DVFS_PRE_config >>>>>
3713 04:44:04.779912 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3714 04:44:04.783838 Exit from DVFS_PRE_config <<<<<
3715 04:44:04.786972 Enter into PICG configuration >>>>
3716 04:44:04.789717 Exit from PICG configuration <<<<
3717 04:44:04.793397 [RX_INPUT] configuration >>>>>
3718 04:44:04.796993 [RX_INPUT] configuration <<<<<
3719 04:44:04.800611 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3720 04:44:04.807621 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3721 04:44:04.813536 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3722 04:44:04.819317 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3723 04:44:04.822771 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3724 04:44:04.830269 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3725 04:44:04.833406 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3726 04:44:04.839459 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3727 04:44:04.842664 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3728 04:44:04.846136 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3729 04:44:04.849235 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3730 04:44:04.856376 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3731 04:44:04.859698 ===================================
3732 04:44:04.860303 LPDDR4 DRAM CONFIGURATION
3733 04:44:04.862627 ===================================
3734 04:44:04.866129 EX_ROW_EN[0] = 0x0
3735 04:44:04.869179 EX_ROW_EN[1] = 0x0
3736 04:44:04.869755 LP4Y_EN = 0x0
3737 04:44:04.872658 WORK_FSP = 0x0
3738 04:44:04.873296 WL = 0x2
3739 04:44:04.876557 RL = 0x2
3740 04:44:04.877099 BL = 0x2
3741 04:44:04.879667 RPST = 0x0
3742 04:44:04.880239 RD_PRE = 0x0
3743 04:44:04.882303 WR_PRE = 0x1
3744 04:44:04.882773 WR_PST = 0x0
3745 04:44:04.886245 DBI_WR = 0x0
3746 04:44:04.886819 DBI_RD = 0x0
3747 04:44:04.889007 OTF = 0x1
3748 04:44:04.892415 ===================================
3749 04:44:04.895955 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3750 04:44:04.899591 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3751 04:44:04.905702 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3752 04:44:04.909715 ===================================
3753 04:44:04.910289 LPDDR4 DRAM CONFIGURATION
3754 04:44:04.914005 ===================================
3755 04:44:04.915139 EX_ROW_EN[0] = 0x10
3756 04:44:04.918996 EX_ROW_EN[1] = 0x0
3757 04:44:04.919574 LP4Y_EN = 0x0
3758 04:44:04.922108 WORK_FSP = 0x0
3759 04:44:04.922578 WL = 0x2
3760 04:44:04.925645 RL = 0x2
3761 04:44:04.926258 BL = 0x2
3762 04:44:04.928843 RPST = 0x0
3763 04:44:04.929325 RD_PRE = 0x0
3764 04:44:04.931991 WR_PRE = 0x1
3765 04:44:04.932566 WR_PST = 0x0
3766 04:44:04.935469 DBI_WR = 0x0
3767 04:44:04.936042 DBI_RD = 0x0
3768 04:44:04.939303 OTF = 0x1
3769 04:44:04.942242 ===================================
3770 04:44:04.950748 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3771 04:44:04.952370 nWR fixed to 30
3772 04:44:04.955908 [ModeRegInit_LP4] CH0 RK0
3773 04:44:04.956461 [ModeRegInit_LP4] CH0 RK1
3774 04:44:04.958350 [ModeRegInit_LP4] CH1 RK0
3775 04:44:04.961850 [ModeRegInit_LP4] CH1 RK1
3776 04:44:04.962308 match AC timing 16
3777 04:44:04.968292 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3778 04:44:04.972194 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3779 04:44:04.975015 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3780 04:44:04.981616 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3781 04:44:04.986142 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3782 04:44:04.986701 ==
3783 04:44:04.988222 Dram Type= 6, Freq= 0, CH_0, rank 0
3784 04:44:04.991917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3785 04:44:04.992508 ==
3786 04:44:04.998377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3787 04:44:05.004988 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3788 04:44:05.008167 [CA 0] Center 35 (5~66) winsize 62
3789 04:44:05.011288 [CA 1] Center 35 (5~66) winsize 62
3790 04:44:05.014615 [CA 2] Center 34 (4~65) winsize 62
3791 04:44:05.017979 [CA 3] Center 34 (4~65) winsize 62
3792 04:44:05.021988 [CA 4] Center 33 (3~64) winsize 62
3793 04:44:05.025182 [CA 5] Center 33 (3~64) winsize 62
3794 04:44:05.025741
3795 04:44:05.027873 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3796 04:44:05.028342
3797 04:44:05.031346 [CATrainingPosCal] consider 1 rank data
3798 04:44:05.034694 u2DelayCellTimex100 = 270/100 ps
3799 04:44:05.037927 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3800 04:44:05.041806 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3801 04:44:05.044417 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3802 04:44:05.047937 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3803 04:44:05.055496 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3804 04:44:05.057765 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3805 04:44:05.058223
3806 04:44:05.060767 CA PerBit enable=1, Macro0, CA PI delay=33
3807 04:44:05.061324
3808 04:44:05.064346 [CBTSetCACLKResult] CA Dly = 33
3809 04:44:05.064954 CS Dly: 5 (0~36)
3810 04:44:05.065323 ==
3811 04:44:05.068024 Dram Type= 6, Freq= 0, CH_0, rank 1
3812 04:44:05.073933 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3813 04:44:05.074515 ==
3814 04:44:05.077684 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3815 04:44:05.084132 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3816 04:44:05.087646 [CA 0] Center 36 (6~66) winsize 61
3817 04:44:05.090441 [CA 1] Center 35 (5~66) winsize 62
3818 04:44:05.094089 [CA 2] Center 34 (4~65) winsize 62
3819 04:44:05.097557 [CA 3] Center 34 (4~65) winsize 62
3820 04:44:05.101579 [CA 4] Center 33 (3~64) winsize 62
3821 04:44:05.104229 [CA 5] Center 33 (3~64) winsize 62
3822 04:44:05.104856
3823 04:44:05.107978 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3824 04:44:05.108432
3825 04:44:05.110242 [CATrainingPosCal] consider 2 rank data
3826 04:44:05.114260 u2DelayCellTimex100 = 270/100 ps
3827 04:44:05.117164 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3828 04:44:05.120187 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3829 04:44:05.123893 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3830 04:44:05.130873 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3831 04:44:05.134424 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3832 04:44:05.136836 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3833 04:44:05.137297
3834 04:44:05.140406 CA PerBit enable=1, Macro0, CA PI delay=33
3835 04:44:05.141036
3836 04:44:05.143957 [CBTSetCACLKResult] CA Dly = 33
3837 04:44:05.144503 CS Dly: 5 (0~36)
3838 04:44:05.144963
3839 04:44:05.148300 ----->DramcWriteLeveling(PI) begin...
3840 04:44:05.150861 ==
3841 04:44:05.151411 Dram Type= 6, Freq= 0, CH_0, rank 0
3842 04:44:05.157583 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3843 04:44:05.158135 ==
3844 04:44:05.160928 Write leveling (Byte 0): 30 => 30
3845 04:44:05.163852 Write leveling (Byte 1): 29 => 29
3846 04:44:05.167200 DramcWriteLeveling(PI) end<-----
3847 04:44:05.167749
3848 04:44:05.168119 ==
3849 04:44:05.170351 Dram Type= 6, Freq= 0, CH_0, rank 0
3850 04:44:05.175632 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3851 04:44:05.176194 ==
3852 04:44:05.177521 [Gating] SW mode calibration
3853 04:44:05.183958 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3854 04:44:05.187088 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3855 04:44:05.193776 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3856 04:44:05.196511 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3857 04:44:05.200177 0 5 8 | B1->B0 | 3030 2f2f | 0 0 | (1 0) (0 0)
3858 04:44:05.206651 0 5 12 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
3859 04:44:05.209787 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3860 04:44:05.213203 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3861 04:44:05.219715 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3862 04:44:05.223199 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3863 04:44:05.226325 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3864 04:44:05.232802 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3865 04:44:05.236328 0 6 8 | B1->B0 | 2727 3232 | 0 1 | (0 0) (0 0)
3866 04:44:05.239822 0 6 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3867 04:44:05.246639 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3868 04:44:05.249517 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3869 04:44:05.253311 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3870 04:44:05.260076 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3871 04:44:05.263406 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3872 04:44:05.266306 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3873 04:44:05.272968 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3874 04:44:05.276323 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3875 04:44:05.279347 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 04:44:05.285845 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 04:44:05.290374 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 04:44:05.293310 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 04:44:05.299645 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 04:44:05.303493 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3881 04:44:05.306357 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 04:44:05.312283 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 04:44:05.315650 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3884 04:44:05.319115 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 04:44:05.326347 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3886 04:44:05.329299 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3887 04:44:05.333184 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3888 04:44:05.338836 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3889 04:44:05.342018 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3890 04:44:05.345419 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3891 04:44:05.349052 Total UI for P1: 0, mck2ui 16
3892 04:44:05.352137 best dqsien dly found for B0: ( 0, 9, 10)
3893 04:44:05.355460 Total UI for P1: 0, mck2ui 16
3894 04:44:05.358990 best dqsien dly found for B1: ( 0, 9, 8)
3895 04:44:05.361710 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3896 04:44:05.365268 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3897 04:44:05.365720
3898 04:44:05.372007 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3899 04:44:05.375339 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3900 04:44:05.375933 [Gating] SW calibration Done
3901 04:44:05.378684 ==
3902 04:44:05.381704 Dram Type= 6, Freq= 0, CH_0, rank 0
3903 04:44:05.385369 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3904 04:44:05.385821 ==
3905 04:44:05.386180 RX Vref Scan: 0
3906 04:44:05.386512
3907 04:44:05.388270 RX Vref 0 -> 0, step: 1
3908 04:44:05.388762
3909 04:44:05.391763 RX Delay -230 -> 252, step: 16
3910 04:44:05.394682 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
3911 04:44:05.397870 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3912 04:44:05.405365 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3913 04:44:05.408400 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
3914 04:44:05.411453 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3915 04:44:05.414087 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
3916 04:44:05.421096 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3917 04:44:05.424589 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3918 04:44:05.428082 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3919 04:44:05.431778 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3920 04:44:05.434201 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
3921 04:44:05.440973 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3922 04:44:05.444276 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3923 04:44:05.447393 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3924 04:44:05.450564 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3925 04:44:05.458437 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3926 04:44:05.458529 ==
3927 04:44:05.460574 Dram Type= 6, Freq= 0, CH_0, rank 0
3928 04:44:05.464066 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3929 04:44:05.464148 ==
3930 04:44:05.464211 DQS Delay:
3931 04:44:05.467396 DQS0 = 0, DQS1 = 0
3932 04:44:05.467476 DQM Delay:
3933 04:44:05.470945 DQM0 = 43, DQM1 = 34
3934 04:44:05.471026 DQ Delay:
3935 04:44:05.474443 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
3936 04:44:05.476954 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3937 04:44:05.480487 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
3938 04:44:05.483696 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3939 04:44:05.483780
3940 04:44:05.483844
3941 04:44:05.483902 ==
3942 04:44:05.487512 Dram Type= 6, Freq= 0, CH_0, rank 0
3943 04:44:05.490493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3944 04:44:05.493917 ==
3945 04:44:05.493998
3946 04:44:05.494062
3947 04:44:05.494122 TX Vref Scan disable
3948 04:44:05.497033 == TX Byte 0 ==
3949 04:44:05.501209 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3950 04:44:05.506773 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3951 04:44:05.506858 == TX Byte 1 ==
3952 04:44:05.511060 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3953 04:44:05.517308 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3954 04:44:05.517401 ==
3955 04:44:05.520033 Dram Type= 6, Freq= 0, CH_0, rank 0
3956 04:44:05.523414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3957 04:44:05.523495 ==
3958 04:44:05.523558
3959 04:44:05.523617
3960 04:44:05.526740 TX Vref Scan disable
3961 04:44:05.529867 == TX Byte 0 ==
3962 04:44:05.534179 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3963 04:44:05.536510 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3964 04:44:05.539944 == TX Byte 1 ==
3965 04:44:05.543461 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3966 04:44:05.546936 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3967 04:44:05.547047
3968 04:44:05.547158 [DATLAT]
3969 04:44:05.549504 Freq=600, CH0 RK0
3970 04:44:05.549584
3971 04:44:05.553706 DATLAT Default: 0x9
3972 04:44:05.553789 0, 0xFFFF, sum = 0
3973 04:44:05.556320 1, 0xFFFF, sum = 0
3974 04:44:05.556402 2, 0xFFFF, sum = 0
3975 04:44:05.559655 3, 0xFFFF, sum = 0
3976 04:44:05.559736 4, 0xFFFF, sum = 0
3977 04:44:05.562805 5, 0xFFFF, sum = 0
3978 04:44:05.562886 6, 0xFFFF, sum = 0
3979 04:44:05.566149 7, 0x0, sum = 1
3980 04:44:05.566230 8, 0x0, sum = 2
3981 04:44:05.569669 9, 0x0, sum = 3
3982 04:44:05.569750 10, 0x0, sum = 4
3983 04:44:05.569815 best_step = 8
3984 04:44:05.569874
3985 04:44:05.573434 ==
3986 04:44:05.576695 Dram Type= 6, Freq= 0, CH_0, rank 0
3987 04:44:05.579765 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3988 04:44:05.579850 ==
3989 04:44:05.579915 RX Vref Scan: 1
3990 04:44:05.579974
3991 04:44:05.582640 RX Vref 0 -> 0, step: 1
3992 04:44:05.582720
3993 04:44:05.586501 RX Delay -195 -> 252, step: 8
3994 04:44:05.586581
3995 04:44:05.589746 Set Vref, RX VrefLevel [Byte0]: 51
3996 04:44:05.593084 [Byte1]: 48
3997 04:44:05.593165
3998 04:44:05.596195 Final RX Vref Byte 0 = 51 to rank0
3999 04:44:05.599415 Final RX Vref Byte 1 = 48 to rank0
4000 04:44:05.602909 Final RX Vref Byte 0 = 51 to rank1
4001 04:44:05.605679 Final RX Vref Byte 1 = 48 to rank1==
4002 04:44:05.609896 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 04:44:05.612449 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4004 04:44:05.615949 ==
4005 04:44:05.616073 DQS Delay:
4006 04:44:05.616171 DQS0 = 0, DQS1 = 0
4007 04:44:05.619995 DQM Delay:
4008 04:44:05.620075 DQM0 = 40, DQM1 = 30
4009 04:44:05.623223 DQ Delay:
4010 04:44:05.625947 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =40
4011 04:44:05.626027 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4012 04:44:05.628948 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4013 04:44:05.632626 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4014 04:44:05.635725
4015 04:44:05.635805
4016 04:44:05.642423 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f4f, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
4017 04:44:05.645471 CH0 RK0: MR19=808, MR18=4F4F
4018 04:44:05.652075 CH0_RK0: MR19=0x808, MR18=0x4F4F, DQSOSC=394, MR23=63, INC=168, DEC=112
4019 04:44:05.652157
4020 04:44:05.655304 ----->DramcWriteLeveling(PI) begin...
4021 04:44:05.655386 ==
4022 04:44:05.658549 Dram Type= 6, Freq= 0, CH_0, rank 1
4023 04:44:05.662531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4024 04:44:05.662612 ==
4025 04:44:05.665973 Write leveling (Byte 0): 33 => 33
4026 04:44:05.668624 Write leveling (Byte 1): 29 => 29
4027 04:44:05.672652 DramcWriteLeveling(PI) end<-----
4028 04:44:05.672744
4029 04:44:05.672809 ==
4030 04:44:05.675552 Dram Type= 6, Freq= 0, CH_0, rank 1
4031 04:44:05.678744 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4032 04:44:05.678824 ==
4033 04:44:05.682467 [Gating] SW mode calibration
4034 04:44:05.688597 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4035 04:44:05.696011 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4036 04:44:05.698758 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 04:44:05.706091 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4038 04:44:05.708572 0 5 8 | B1->B0 | 3030 3030 | 0 1 | (0 1) (1 0)
4039 04:44:05.712446 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 04:44:05.718440 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 04:44:05.721749 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 04:44:05.725182 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 04:44:05.731566 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 04:44:05.734806 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 04:44:05.738314 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 04:44:05.744522 0 6 8 | B1->B0 | 2a2a 3838 | 0 1 | (0 0) (0 0)
4047 04:44:05.747850 0 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4048 04:44:05.751594 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 04:44:05.754745 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 04:44:05.761176 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 04:44:05.764537 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 04:44:05.767882 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 04:44:05.774401 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 04:44:05.777495 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 04:44:05.780859 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4056 04:44:05.788181 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 04:44:05.791091 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 04:44:05.794372 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 04:44:05.801126 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 04:44:05.804123 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 04:44:05.807626 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 04:44:05.814727 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 04:44:05.817493 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 04:44:05.821365 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 04:44:05.827647 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 04:44:05.830680 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 04:44:05.834466 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 04:44:05.840964 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 04:44:05.844801 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 04:44:05.847363 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4071 04:44:05.854190 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 04:44:05.854272 Total UI for P1: 0, mck2ui 16
4073 04:44:05.861299 best dqsien dly found for B0: ( 0, 9, 8)
4074 04:44:05.861382 Total UI for P1: 0, mck2ui 16
4075 04:44:05.867296 best dqsien dly found for B1: ( 0, 9, 8)
4076 04:44:05.870538 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4077 04:44:05.873978 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4078 04:44:05.874058
4079 04:44:05.877384 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4080 04:44:05.880448 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4081 04:44:05.883890 [Gating] SW calibration Done
4082 04:44:05.883971 ==
4083 04:44:05.887376 Dram Type= 6, Freq= 0, CH_0, rank 1
4084 04:44:05.890756 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4085 04:44:05.890838 ==
4086 04:44:05.894640 RX Vref Scan: 0
4087 04:44:05.894797
4088 04:44:05.894870 RX Vref 0 -> 0, step: 1
4089 04:44:05.894936
4090 04:44:05.896967 RX Delay -230 -> 252, step: 16
4091 04:44:05.903909 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4092 04:44:05.907171 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4093 04:44:05.910417 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4094 04:44:05.913701 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4095 04:44:05.916980 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4096 04:44:05.923955 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4097 04:44:05.927863 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4098 04:44:05.930790 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4099 04:44:05.934355 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4100 04:44:05.940527 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4101 04:44:05.944173 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4102 04:44:05.948149 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4103 04:44:05.950348 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4104 04:44:05.957005 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4105 04:44:05.960407 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4106 04:44:05.963530 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4107 04:44:05.963784 ==
4108 04:44:05.966784 Dram Type= 6, Freq= 0, CH_0, rank 1
4109 04:44:05.970121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4110 04:44:05.970404 ==
4111 04:44:05.973780 DQS Delay:
4112 04:44:05.974107 DQS0 = 0, DQS1 = 0
4113 04:44:05.976550 DQM Delay:
4114 04:44:05.976801 DQM0 = 43, DQM1 = 33
4115 04:44:05.976990 DQ Delay:
4116 04:44:05.980572 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4117 04:44:05.983421 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4118 04:44:05.986828 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4119 04:44:05.991064 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4120 04:44:05.991576
4121 04:44:05.991899
4122 04:44:05.994586 ==
4123 04:44:05.997426 Dram Type= 6, Freq= 0, CH_0, rank 1
4124 04:44:06.000400 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4125 04:44:06.000944 ==
4126 04:44:06.001279
4127 04:44:06.001581
4128 04:44:06.003712 TX Vref Scan disable
4129 04:44:06.004226 == TX Byte 0 ==
4130 04:44:06.010595 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4131 04:44:06.013544 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4132 04:44:06.013961 == TX Byte 1 ==
4133 04:44:06.020792 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4134 04:44:06.023185 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4135 04:44:06.023597 ==
4136 04:44:06.027550 Dram Type= 6, Freq= 0, CH_0, rank 1
4137 04:44:06.030735 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4138 04:44:06.031168 ==
4139 04:44:06.031720
4140 04:44:06.032048
4141 04:44:06.034112 TX Vref Scan disable
4142 04:44:06.037433 == TX Byte 0 ==
4143 04:44:06.039827 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4144 04:44:06.043212 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4145 04:44:06.046979 == TX Byte 1 ==
4146 04:44:06.049617 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4147 04:44:06.052936 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4148 04:44:06.056684
4149 04:44:06.057338 [DATLAT]
4150 04:44:06.057775 Freq=600, CH0 RK1
4151 04:44:06.058094
4152 04:44:06.059978 DATLAT Default: 0x8
4153 04:44:06.060384 0, 0xFFFF, sum = 0
4154 04:44:06.063645 1, 0xFFFF, sum = 0
4155 04:44:06.064163 2, 0xFFFF, sum = 0
4156 04:44:06.067398 3, 0xFFFF, sum = 0
4157 04:44:06.067917 4, 0xFFFF, sum = 0
4158 04:44:06.069101 5, 0xFFFF, sum = 0
4159 04:44:06.072742 6, 0xFFFF, sum = 0
4160 04:44:06.073164 7, 0x0, sum = 1
4161 04:44:06.073498 8, 0x0, sum = 2
4162 04:44:06.076510 9, 0x0, sum = 3
4163 04:44:06.076968 10, 0x0, sum = 4
4164 04:44:06.079909 best_step = 8
4165 04:44:06.080320
4166 04:44:06.080644 ==
4167 04:44:06.082910 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 04:44:06.086627 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4169 04:44:06.087046 ==
4170 04:44:06.089272 RX Vref Scan: 0
4171 04:44:06.089704
4172 04:44:06.090031 RX Vref 0 -> 0, step: 1
4173 04:44:06.090336
4174 04:44:06.093392 RX Delay -195 -> 252, step: 8
4175 04:44:06.099775 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4176 04:44:06.103417 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4177 04:44:06.106635 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4178 04:44:06.109707 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4179 04:44:06.116803 iDelay=205, Bit 4, Center 48 (-107 ~ 204) 312
4180 04:44:06.120159 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4181 04:44:06.122958 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4182 04:44:06.127158 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4183 04:44:06.129538 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4184 04:44:06.137317 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4185 04:44:06.140647 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4186 04:44:06.144109 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4187 04:44:06.146728 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4188 04:44:06.153199 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4189 04:44:06.157263 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4190 04:44:06.159663 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4191 04:44:06.160186 ==
4192 04:44:06.163189 Dram Type= 6, Freq= 0, CH_0, rank 1
4193 04:44:06.166458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4194 04:44:06.169515 ==
4195 04:44:06.169928 DQS Delay:
4196 04:44:06.170254 DQS0 = 0, DQS1 = 0
4197 04:44:06.172859 DQM Delay:
4198 04:44:06.173375 DQM0 = 42, DQM1 = 33
4199 04:44:06.176642 DQ Delay:
4200 04:44:06.179068 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4201 04:44:06.179498 DQ4 =48, DQ5 =32, DQ6 =48, DQ7 =48
4202 04:44:06.182661 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4203 04:44:06.189600 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4204 04:44:06.190013
4205 04:44:06.190338
4206 04:44:06.196046 [DQSOSCAuto] RK1, (LSB)MR18= 0x6161, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4207 04:44:06.199784 CH0 RK1: MR19=808, MR18=6161
4208 04:44:06.205619 CH0_RK1: MR19=0x808, MR18=0x6161, DQSOSC=391, MR23=63, INC=171, DEC=114
4209 04:44:06.209779 [RxdqsGatingPostProcess] freq 600
4210 04:44:06.212599 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4211 04:44:06.215338 Pre-setting of DQS Precalculation
4212 04:44:06.222628 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4213 04:44:06.223145 ==
4214 04:44:06.226513 Dram Type= 6, Freq= 0, CH_1, rank 0
4215 04:44:06.228800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4216 04:44:06.229218 ==
4217 04:44:06.235621 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4218 04:44:06.241949 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4219 04:44:06.245304 [CA 0] Center 35 (5~66) winsize 62
4220 04:44:06.249786 [CA 1] Center 35 (4~66) winsize 63
4221 04:44:06.252581 [CA 2] Center 33 (3~64) winsize 62
4222 04:44:06.255476 [CA 3] Center 33 (3~64) winsize 62
4223 04:44:06.259291 [CA 4] Center 33 (2~64) winsize 63
4224 04:44:06.262459 [CA 5] Center 33 (2~64) winsize 63
4225 04:44:06.262870
4226 04:44:06.265362 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4227 04:44:06.265869
4228 04:44:06.268824 [CATrainingPosCal] consider 1 rank data
4229 04:44:06.272461 u2DelayCellTimex100 = 270/100 ps
4230 04:44:06.275358 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4231 04:44:06.278802 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4232 04:44:06.282249 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4233 04:44:06.285503 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4234 04:44:06.288874 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4235 04:44:06.291839 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4236 04:44:06.292290
4237 04:44:06.295695 CA PerBit enable=1, Macro0, CA PI delay=33
4238 04:44:06.298935
4239 04:44:06.299389 [CBTSetCACLKResult] CA Dly = 33
4240 04:44:06.302701 CS Dly: 5 (0~36)
4241 04:44:06.303207 ==
4242 04:44:06.305165 Dram Type= 6, Freq= 0, CH_1, rank 1
4243 04:44:06.309243 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4244 04:44:06.309746 ==
4245 04:44:06.315124 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4246 04:44:06.321748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4247 04:44:06.324758 [CA 0] Center 35 (4~66) winsize 63
4248 04:44:06.328102 [CA 1] Center 34 (4~65) winsize 62
4249 04:44:06.331296 [CA 2] Center 33 (3~64) winsize 62
4250 04:44:06.334408 [CA 3] Center 33 (3~64) winsize 62
4251 04:44:06.338045 [CA 4] Center 33 (2~64) winsize 63
4252 04:44:06.340975 [CA 5] Center 32 (2~63) winsize 62
4253 04:44:06.341385
4254 04:44:06.344619 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4255 04:44:06.345175
4256 04:44:06.348664 [CATrainingPosCal] consider 2 rank data
4257 04:44:06.351888 u2DelayCellTimex100 = 270/100 ps
4258 04:44:06.355098 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4259 04:44:06.357653 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4260 04:44:06.361670 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4261 04:44:06.364628 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4262 04:44:06.367846 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4263 04:44:06.374767 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4264 04:44:06.375280
4265 04:44:06.377522 CA PerBit enable=1, Macro0, CA PI delay=32
4266 04:44:06.377973
4267 04:44:06.381472 [CBTSetCACLKResult] CA Dly = 32
4268 04:44:06.381988 CS Dly: 5 (0~36)
4269 04:44:06.382362
4270 04:44:06.384163 ----->DramcWriteLeveling(PI) begin...
4271 04:44:06.384764 ==
4272 04:44:06.388187 Dram Type= 6, Freq= 0, CH_1, rank 0
4273 04:44:06.394084 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4274 04:44:06.394647 ==
4275 04:44:06.397361 Write leveling (Byte 0): 28 => 28
4276 04:44:06.397918 Write leveling (Byte 1): 28 => 28
4277 04:44:06.400769 DramcWriteLeveling(PI) end<-----
4278 04:44:06.401322
4279 04:44:06.401685 ==
4280 04:44:06.404116 Dram Type= 6, Freq= 0, CH_1, rank 0
4281 04:44:06.410812 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4282 04:44:06.411392 ==
4283 04:44:06.414253 [Gating] SW mode calibration
4284 04:44:06.421954 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4285 04:44:06.424109 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4286 04:44:06.430353 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4287 04:44:06.434523 0 5 4 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
4288 04:44:06.437010 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4289 04:44:06.443718 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4290 04:44:06.447326 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4291 04:44:06.450588 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4292 04:44:06.457241 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4293 04:44:06.460666 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4294 04:44:06.463821 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4295 04:44:06.470599 0 6 4 | B1->B0 | 2424 2b2b | 0 1 | (0 0) (1 1)
4296 04:44:06.474798 0 6 8 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
4297 04:44:06.476790 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 04:44:06.480049 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 04:44:06.486776 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 04:44:06.490273 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4301 04:44:06.493647 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4302 04:44:06.499947 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4303 04:44:06.503805 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4304 04:44:06.506851 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4305 04:44:06.513322 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 04:44:06.516955 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 04:44:06.520080 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 04:44:06.526650 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 04:44:06.530063 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 04:44:06.533197 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 04:44:06.540246 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 04:44:06.542809 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 04:44:06.546528 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 04:44:06.553720 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 04:44:06.556530 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 04:44:06.560049 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 04:44:06.567506 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 04:44:06.570195 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 04:44:06.572884 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4320 04:44:06.579715 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4321 04:44:06.583288 Total UI for P1: 0, mck2ui 16
4322 04:44:06.586055 best dqsien dly found for B0: ( 0, 9, 4)
4323 04:44:06.586512 Total UI for P1: 0, mck2ui 16
4324 04:44:06.592964 best dqsien dly found for B1: ( 0, 9, 6)
4325 04:44:06.597264 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4326 04:44:06.599523 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4327 04:44:06.600080
4328 04:44:06.603153 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4329 04:44:06.606539 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4330 04:44:06.610183 [Gating] SW calibration Done
4331 04:44:06.610742 ==
4332 04:44:06.613255 Dram Type= 6, Freq= 0, CH_1, rank 0
4333 04:44:06.615801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4334 04:44:06.616358 ==
4335 04:44:06.619722 RX Vref Scan: 0
4336 04:44:06.620273
4337 04:44:06.620634 RX Vref 0 -> 0, step: 1
4338 04:44:06.621033
4339 04:44:06.623252 RX Delay -230 -> 252, step: 16
4340 04:44:06.629695 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4341 04:44:06.632535 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4342 04:44:06.635750 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4343 04:44:06.639249 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4344 04:44:06.643390 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4345 04:44:06.649022 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4346 04:44:06.652757 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4347 04:44:06.656097 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4348 04:44:06.660167 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4349 04:44:06.665702 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4350 04:44:06.670412 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4351 04:44:06.672787 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4352 04:44:06.675599 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4353 04:44:06.682478 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4354 04:44:06.685534 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4355 04:44:06.689205 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4356 04:44:06.689764 ==
4357 04:44:06.692848 Dram Type= 6, Freq= 0, CH_1, rank 0
4358 04:44:06.695365 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4359 04:44:06.698688 ==
4360 04:44:06.699142 DQS Delay:
4361 04:44:06.699495 DQS0 = 0, DQS1 = 0
4362 04:44:06.701759 DQM Delay:
4363 04:44:06.702165 DQM0 = 38, DQM1 = 30
4364 04:44:06.705318 DQ Delay:
4365 04:44:06.705727 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4366 04:44:06.708480 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4367 04:44:06.712438 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4368 04:44:06.715407 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4369 04:44:06.715813
4370 04:44:06.718133
4371 04:44:06.718615 ==
4372 04:44:06.721428 Dram Type= 6, Freq= 0, CH_1, rank 0
4373 04:44:06.725417 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4374 04:44:06.725953 ==
4375 04:44:06.726398
4376 04:44:06.726715
4377 04:44:06.728957 TX Vref Scan disable
4378 04:44:06.729369 == TX Byte 0 ==
4379 04:44:06.735425 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4380 04:44:06.738948 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4381 04:44:06.739465 == TX Byte 1 ==
4382 04:44:06.744866 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4383 04:44:06.748141 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4384 04:44:06.748558 ==
4385 04:44:06.752020 Dram Type= 6, Freq= 0, CH_1, rank 0
4386 04:44:06.754938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4387 04:44:06.755353 ==
4388 04:44:06.755680
4389 04:44:06.755987
4390 04:44:06.758213 TX Vref Scan disable
4391 04:44:06.762367 == TX Byte 0 ==
4392 04:44:06.765435 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4393 04:44:06.768153 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4394 04:44:06.772300 == TX Byte 1 ==
4395 04:44:06.775166 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4396 04:44:06.777837 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4397 04:44:06.781225
4398 04:44:06.781635 [DATLAT]
4399 04:44:06.781965 Freq=600, CH1 RK0
4400 04:44:06.782274
4401 04:44:06.784744 DATLAT Default: 0x9
4402 04:44:06.785268 0, 0xFFFF, sum = 0
4403 04:44:06.788203 1, 0xFFFF, sum = 0
4404 04:44:06.788784 2, 0xFFFF, sum = 0
4405 04:44:06.791376 3, 0xFFFF, sum = 0
4406 04:44:06.791894 4, 0xFFFF, sum = 0
4407 04:44:06.794710 5, 0xFFFF, sum = 0
4408 04:44:06.795227 6, 0xFFFF, sum = 0
4409 04:44:06.798430 7, 0x0, sum = 1
4410 04:44:06.798945 8, 0x0, sum = 2
4411 04:44:06.801499 9, 0x0, sum = 3
4412 04:44:06.801921 10, 0x0, sum = 4
4413 04:44:06.807260 best_step = 8
4414 04:44:06.807771
4415 04:44:06.808100 ==
4416 04:44:06.809039 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 04:44:06.811656 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4418 04:44:06.812083 ==
4419 04:44:06.816224 RX Vref Scan: 1
4420 04:44:06.816858
4421 04:44:06.817198 RX Vref 0 -> 0, step: 1
4422 04:44:06.817505
4423 04:44:06.818144 RX Delay -195 -> 252, step: 8
4424 04:44:06.818467
4425 04:44:06.821139 Set Vref, RX VrefLevel [Byte0]: 52
4426 04:44:06.825341 [Byte1]: 48
4427 04:44:06.828172
4428 04:44:06.828684 Final RX Vref Byte 0 = 52 to rank0
4429 04:44:06.831742 Final RX Vref Byte 1 = 48 to rank0
4430 04:44:06.834664 Final RX Vref Byte 0 = 52 to rank1
4431 04:44:06.838317 Final RX Vref Byte 1 = 48 to rank1==
4432 04:44:06.841777 Dram Type= 6, Freq= 0, CH_1, rank 0
4433 04:44:06.847908 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4434 04:44:06.848425 ==
4435 04:44:06.848804 DQS Delay:
4436 04:44:06.851173 DQS0 = 0, DQS1 = 0
4437 04:44:06.851584 DQM Delay:
4438 04:44:06.851903 DQM0 = 37, DQM1 = 30
4439 04:44:06.854804 DQ Delay:
4440 04:44:06.857964 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4441 04:44:06.862214 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4442 04:44:06.864766 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4443 04:44:06.868263 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4444 04:44:06.868825
4445 04:44:06.869161
4446 04:44:06.874767 [DQSOSCAuto] RK0, (LSB)MR18= 0x7070, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4447 04:44:06.877557 CH1 RK0: MR19=808, MR18=7070
4448 04:44:06.884550 CH1_RK0: MR19=0x808, MR18=0x7070, DQSOSC=388, MR23=63, INC=174, DEC=116
4449 04:44:06.885117
4450 04:44:06.888534 ----->DramcWriteLeveling(PI) begin...
4451 04:44:06.889103 ==
4452 04:44:06.891398 Dram Type= 6, Freq= 0, CH_1, rank 1
4453 04:44:06.895456 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4454 04:44:06.895979 ==
4455 04:44:06.897921 Write leveling (Byte 0): 28 => 28
4456 04:44:06.901700 Write leveling (Byte 1): 27 => 27
4457 04:44:06.904775 DramcWriteLeveling(PI) end<-----
4458 04:44:06.905297
4459 04:44:06.905627 ==
4460 04:44:06.907609 Dram Type= 6, Freq= 0, CH_1, rank 1
4461 04:44:06.911821 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4462 04:44:06.912340 ==
4463 04:44:06.915575 [Gating] SW mode calibration
4464 04:44:06.921116 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4465 04:44:06.927987 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4466 04:44:06.931370 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4467 04:44:06.938608 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4468 04:44:06.943644 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
4469 04:44:06.944592 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 04:44:06.947686 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 04:44:06.953943 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 04:44:06.957541 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 04:44:06.960654 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 04:44:06.967051 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 04:44:06.970518 0 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4476 04:44:06.973848 0 6 8 | B1->B0 | 3838 4242 | 0 0 | (0 0) (0 0)
4477 04:44:06.980599 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 04:44:06.983767 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 04:44:06.987206 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 04:44:06.993670 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 04:44:06.996696 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 04:44:07.000975 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4483 04:44:07.007272 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4484 04:44:07.009733 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 04:44:07.013369 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 04:44:07.020253 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 04:44:07.022869 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 04:44:07.026089 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 04:44:07.033028 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 04:44:07.036151 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 04:44:07.040004 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 04:44:07.047234 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 04:44:07.049386 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 04:44:07.052758 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 04:44:07.059784 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 04:44:07.063258 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 04:44:07.066651 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 04:44:07.072721 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 04:44:07.075715 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4500 04:44:07.078941 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 04:44:07.082491 Total UI for P1: 0, mck2ui 16
4502 04:44:07.085814 best dqsien dly found for B0: ( 0, 9, 4)
4503 04:44:07.088854 Total UI for P1: 0, mck2ui 16
4504 04:44:07.092472 best dqsien dly found for B1: ( 0, 9, 4)
4505 04:44:07.095915 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4506 04:44:07.100031 best DQS1 dly(MCK, UI, PI) = (0, 9, 4)
4507 04:44:07.100271
4508 04:44:07.105446 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4509 04:44:07.108976 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 4)
4510 04:44:07.112535 [Gating] SW calibration Done
4511 04:44:07.112691 ==
4512 04:44:07.115922 Dram Type= 6, Freq= 0, CH_1, rank 1
4513 04:44:07.119113 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4514 04:44:07.119271 ==
4515 04:44:07.119396 RX Vref Scan: 0
4516 04:44:07.119511
4517 04:44:07.122105 RX Vref 0 -> 0, step: 1
4518 04:44:07.122261
4519 04:44:07.126160 RX Delay -230 -> 252, step: 16
4520 04:44:07.129392 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4521 04:44:07.136173 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4522 04:44:07.138337 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4523 04:44:07.142289 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4524 04:44:07.145645 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4525 04:44:07.148852 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4526 04:44:07.155566 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4527 04:44:07.158650 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4528 04:44:07.162911 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4529 04:44:07.165871 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4530 04:44:07.171947 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4531 04:44:07.175450 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4532 04:44:07.178276 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4533 04:44:07.182406 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4534 04:44:07.188812 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4535 04:44:07.192741 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4536 04:44:07.193201 ==
4537 04:44:07.195122 Dram Type= 6, Freq= 0, CH_1, rank 1
4538 04:44:07.198518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4539 04:44:07.199077 ==
4540 04:44:07.201428 DQS Delay:
4541 04:44:07.201882 DQS0 = 0, DQS1 = 0
4542 04:44:07.202243 DQM Delay:
4543 04:44:07.205504 DQM0 = 39, DQM1 = 34
4544 04:44:07.206059 DQ Delay:
4545 04:44:07.208774 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4546 04:44:07.212432 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4547 04:44:07.215408 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4548 04:44:07.218647 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4549 04:44:07.219160
4550 04:44:07.219604
4551 04:44:07.219949 ==
4552 04:44:07.223138 Dram Type= 6, Freq= 0, CH_1, rank 1
4553 04:44:07.229539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4554 04:44:07.230094 ==
4555 04:44:07.230460
4556 04:44:07.230795
4557 04:44:07.231118 TX Vref Scan disable
4558 04:44:07.231990 == TX Byte 0 ==
4559 04:44:07.235752 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4560 04:44:07.241999 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4561 04:44:07.242550 == TX Byte 1 ==
4562 04:44:07.246036 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4563 04:44:07.252112 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4564 04:44:07.252659 ==
4565 04:44:07.255642 Dram Type= 6, Freq= 0, CH_1, rank 1
4566 04:44:07.258810 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4567 04:44:07.259274 ==
4568 04:44:07.259642
4569 04:44:07.259978
4570 04:44:07.262320 TX Vref Scan disable
4571 04:44:07.265555 == TX Byte 0 ==
4572 04:44:07.268129 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4573 04:44:07.271556 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4574 04:44:07.275226 == TX Byte 1 ==
4575 04:44:07.278470 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4576 04:44:07.281721 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4577 04:44:07.282183
4578 04:44:07.282543 [DATLAT]
4579 04:44:07.285086 Freq=600, CH1 RK1
4580 04:44:07.285811
4581 04:44:07.288232 DATLAT Default: 0x8
4582 04:44:07.288831 0, 0xFFFF, sum = 0
4583 04:44:07.292266 1, 0xFFFF, sum = 0
4584 04:44:07.292870 2, 0xFFFF, sum = 0
4585 04:44:07.294417 3, 0xFFFF, sum = 0
4586 04:44:07.294880 4, 0xFFFF, sum = 0
4587 04:44:07.298471 5, 0xFFFF, sum = 0
4588 04:44:07.299035 6, 0xFFFF, sum = 0
4589 04:44:07.301442 7, 0x0, sum = 1
4590 04:44:07.302004 8, 0x0, sum = 2
4591 04:44:07.304586 9, 0x0, sum = 3
4592 04:44:07.305198 10, 0x0, sum = 4
4593 04:44:07.305579 best_step = 8
4594 04:44:07.308092
4595 04:44:07.308645 ==
4596 04:44:07.311331 Dram Type= 6, Freq= 0, CH_1, rank 1
4597 04:44:07.314414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4598 04:44:07.314968 ==
4599 04:44:07.315334 RX Vref Scan: 0
4600 04:44:07.315672
4601 04:44:07.317472 RX Vref 0 -> 0, step: 1
4602 04:44:07.317926
4603 04:44:07.321072 RX Delay -195 -> 252, step: 8
4604 04:44:07.327224 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4605 04:44:07.330717 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4606 04:44:07.333875 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4607 04:44:07.337924 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4608 04:44:07.344686 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4609 04:44:07.347393 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4610 04:44:07.351599 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4611 04:44:07.353746 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4612 04:44:07.357581 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4613 04:44:07.363838 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4614 04:44:07.368010 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4615 04:44:07.370553 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4616 04:44:07.373666 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4617 04:44:07.380223 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4618 04:44:07.385070 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4619 04:44:07.387133 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4620 04:44:07.387589 ==
4621 04:44:07.390051 Dram Type= 6, Freq= 0, CH_1, rank 1
4622 04:44:07.397388 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4623 04:44:07.397952 ==
4624 04:44:07.398314 DQS Delay:
4625 04:44:07.398645 DQS0 = 0, DQS1 = 0
4626 04:44:07.400623 DQM Delay:
4627 04:44:07.401226 DQM0 = 37, DQM1 = 29
4628 04:44:07.403542 DQ Delay:
4629 04:44:07.407686 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4630 04:44:07.410938 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4631 04:44:07.413515 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4632 04:44:07.417255 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4633 04:44:07.417811
4634 04:44:07.418170
4635 04:44:07.424087 [DQSOSCAuto] RK1, (LSB)MR18= 0x6161, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4636 04:44:07.426739 CH1 RK1: MR19=808, MR18=6161
4637 04:44:07.433129 CH1_RK1: MR19=0x808, MR18=0x6161, DQSOSC=391, MR23=63, INC=171, DEC=114
4638 04:44:07.436445 [RxdqsGatingPostProcess] freq 600
4639 04:44:07.439412 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4640 04:44:07.443331 Pre-setting of DQS Precalculation
4641 04:44:07.449595 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4642 04:44:07.456309 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4643 04:44:07.462924 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4644 04:44:07.463387
4645 04:44:07.463749
4646 04:44:07.466472 [Calibration Summary] 1200 Mbps
4647 04:44:07.466932 CH 0, Rank 0
4648 04:44:07.469900 SW Impedance : PASS
4649 04:44:07.472852 DUTY Scan : NO K
4650 04:44:07.473397 ZQ Calibration : PASS
4651 04:44:07.476292 Jitter Meter : NO K
4652 04:44:07.479160 CBT Training : PASS
4653 04:44:07.479750 Write leveling : PASS
4654 04:44:07.483673 RX DQS gating : PASS
4655 04:44:07.486621 RX DQ/DQS(RDDQC) : PASS
4656 04:44:07.487174 TX DQ/DQS : PASS
4657 04:44:07.491046 RX DATLAT : PASS
4658 04:44:07.492991 RX DQ/DQS(Engine): PASS
4659 04:44:07.493451 TX OE : NO K
4660 04:44:07.493835 All Pass.
4661 04:44:07.496649
4662 04:44:07.497241 CH 0, Rank 1
4663 04:44:07.499587 SW Impedance : PASS
4664 04:44:07.500137 DUTY Scan : NO K
4665 04:44:07.503141 ZQ Calibration : PASS
4666 04:44:07.505657 Jitter Meter : NO K
4667 04:44:07.506175 CBT Training : PASS
4668 04:44:07.509217 Write leveling : PASS
4669 04:44:07.509674 RX DQS gating : PASS
4670 04:44:07.512936 RX DQ/DQS(RDDQC) : PASS
4671 04:44:07.515651 TX DQ/DQS : PASS
4672 04:44:07.516119 RX DATLAT : PASS
4673 04:44:07.519356 RX DQ/DQS(Engine): PASS
4674 04:44:07.522868 TX OE : NO K
4675 04:44:07.523335 All Pass.
4676 04:44:07.523699
4677 04:44:07.524036 CH 1, Rank 0
4678 04:44:07.525617 SW Impedance : PASS
4679 04:44:07.529227 DUTY Scan : NO K
4680 04:44:07.529776 ZQ Calibration : PASS
4681 04:44:07.533178 Jitter Meter : NO K
4682 04:44:07.535921 CBT Training : PASS
4683 04:44:07.536473 Write leveling : PASS
4684 04:44:07.539123 RX DQS gating : PASS
4685 04:44:07.542856 RX DQ/DQS(RDDQC) : PASS
4686 04:44:07.543405 TX DQ/DQS : PASS
4687 04:44:07.545762 RX DATLAT : PASS
4688 04:44:07.548618 RX DQ/DQS(Engine): PASS
4689 04:44:07.549118 TX OE : NO K
4690 04:44:07.552244 All Pass.
4691 04:44:07.552702
4692 04:44:07.553127 CH 1, Rank 1
4693 04:44:07.555453 SW Impedance : PASS
4694 04:44:07.555908 DUTY Scan : NO K
4695 04:44:07.558715 ZQ Calibration : PASS
4696 04:44:07.562152 Jitter Meter : NO K
4697 04:44:07.562610 CBT Training : PASS
4698 04:44:07.565196 Write leveling : PASS
4699 04:44:07.565680 RX DQS gating : PASS
4700 04:44:07.568899 RX DQ/DQS(RDDQC) : PASS
4701 04:44:07.572113 TX DQ/DQS : PASS
4702 04:44:07.572529 RX DATLAT : PASS
4703 04:44:07.575500 RX DQ/DQS(Engine): PASS
4704 04:44:07.578599 TX OE : NO K
4705 04:44:07.579273 All Pass.
4706 04:44:07.579863
4707 04:44:07.581891 DramC Write-DBI off
4708 04:44:07.582307 PER_BANK_REFRESH: Hybrid Mode
4709 04:44:07.585964 TX_TRACKING: ON
4710 04:44:07.595496 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4711 04:44:07.598605 [FAST_K] Save calibration result to emmc
4712 04:44:07.601668 dramc_set_vcore_voltage set vcore to 662500
4713 04:44:07.602176 Read voltage for 933, 3
4714 04:44:07.605574 Vio18 = 0
4715 04:44:07.606083 Vcore = 662500
4716 04:44:07.606411 Vdram = 0
4717 04:44:07.608425 Vddq = 0
4718 04:44:07.608924 Vmddr = 0
4719 04:44:07.614902 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4720 04:44:07.618367 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4721 04:44:07.622339 MEM_TYPE=3, freq_sel=17
4722 04:44:07.625513 sv_algorithm_assistance_LP4_1600
4723 04:44:07.628236 ============ PULL DRAM RESETB DOWN ============
4724 04:44:07.632109 ========== PULL DRAM RESETB DOWN end =========
4725 04:44:07.638224 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4726 04:44:07.642551 ===================================
4727 04:44:07.642969 LPDDR4 DRAM CONFIGURATION
4728 04:44:07.644892 ===================================
4729 04:44:07.648268 EX_ROW_EN[0] = 0x0
4730 04:44:07.651670 EX_ROW_EN[1] = 0x0
4731 04:44:07.652175 LP4Y_EN = 0x0
4732 04:44:07.655052 WORK_FSP = 0x0
4733 04:44:07.655557 WL = 0x3
4734 04:44:07.659870 RL = 0x3
4735 04:44:07.660393 BL = 0x2
4736 04:44:07.661279 RPST = 0x0
4737 04:44:07.661646 RD_PRE = 0x0
4738 04:44:07.665281 WR_PRE = 0x1
4739 04:44:07.665789 WR_PST = 0x0
4740 04:44:07.667912 DBI_WR = 0x0
4741 04:44:07.668328 DBI_RD = 0x0
4742 04:44:07.672021 OTF = 0x1
4743 04:44:07.674574 ===================================
4744 04:44:07.677752 ===================================
4745 04:44:07.678171 ANA top config
4746 04:44:07.681488 ===================================
4747 04:44:07.684440 DLL_ASYNC_EN = 0
4748 04:44:07.687606 ALL_SLAVE_EN = 1
4749 04:44:07.690818 NEW_RANK_MODE = 1
4750 04:44:07.691236 DLL_IDLE_MODE = 1
4751 04:44:07.694530 LP45_APHY_COMB_EN = 1
4752 04:44:07.697948 TX_ODT_DIS = 1
4753 04:44:07.701121 NEW_8X_MODE = 1
4754 04:44:07.704764 ===================================
4755 04:44:07.708667 ===================================
4756 04:44:07.711482 data_rate = 1866
4757 04:44:07.712020 CKR = 1
4758 04:44:07.714650 DQ_P2S_RATIO = 8
4759 04:44:07.718018 ===================================
4760 04:44:07.720817 CA_P2S_RATIO = 8
4761 04:44:07.724695 DQ_CA_OPEN = 0
4762 04:44:07.727320 DQ_SEMI_OPEN = 0
4763 04:44:07.731166 CA_SEMI_OPEN = 0
4764 04:44:07.731688 CA_FULL_RATE = 0
4765 04:44:07.734229 DQ_CKDIV4_EN = 1
4766 04:44:07.737684 CA_CKDIV4_EN = 1
4767 04:44:07.740580 CA_PREDIV_EN = 0
4768 04:44:07.744613 PH8_DLY = 0
4769 04:44:07.747528 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4770 04:44:07.748086 DQ_AAMCK_DIV = 4
4771 04:44:07.750791 CA_AAMCK_DIV = 4
4772 04:44:07.754324 CA_ADMCK_DIV = 4
4773 04:44:07.756870 DQ_TRACK_CA_EN = 0
4774 04:44:07.760524 CA_PICK = 933
4775 04:44:07.764226 CA_MCKIO = 933
4776 04:44:07.767304 MCKIO_SEMI = 0
4777 04:44:07.767869 PLL_FREQ = 3732
4778 04:44:07.770066 DQ_UI_PI_RATIO = 32
4779 04:44:07.773514 CA_UI_PI_RATIO = 0
4780 04:44:07.776932 ===================================
4781 04:44:07.780515 ===================================
4782 04:44:07.783814 memory_type:LPDDR4
4783 04:44:07.787288 GP_NUM : 10
4784 04:44:07.787846 SRAM_EN : 1
4785 04:44:07.789805 MD32_EN : 0
4786 04:44:07.793961 ===================================
4787 04:44:07.794517 [ANA_INIT] >>>>>>>>>>>>>>
4788 04:44:07.796573 <<<<<< [CONFIGURE PHASE]: ANA_TX
4789 04:44:07.800675 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4790 04:44:07.804286 ===================================
4791 04:44:07.806976 data_rate = 1866,PCW = 0X8f00
4792 04:44:07.809986 ===================================
4793 04:44:07.813185 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4794 04:44:07.819863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4795 04:44:07.826664 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4796 04:44:07.830291 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4797 04:44:07.833006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4798 04:44:07.835897 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4799 04:44:07.839481 [ANA_INIT] flow start
4800 04:44:07.840105 [ANA_INIT] PLL >>>>>>>>
4801 04:44:07.843755 [ANA_INIT] PLL <<<<<<<<
4802 04:44:07.846350 [ANA_INIT] MIDPI >>>>>>>>
4803 04:44:07.846951 [ANA_INIT] MIDPI <<<<<<<<
4804 04:44:07.849626 [ANA_INIT] DLL >>>>>>>>
4805 04:44:07.852613 [ANA_INIT] flow end
4806 04:44:07.856218 ============ LP4 DIFF to SE enter ============
4807 04:44:07.860237 ============ LP4 DIFF to SE exit ============
4808 04:44:07.863180 [ANA_INIT] <<<<<<<<<<<<<
4809 04:44:07.866504 [Flow] Enable top DCM control >>>>>
4810 04:44:07.869010 [Flow] Enable top DCM control <<<<<
4811 04:44:07.873209 Enable DLL master slave shuffle
4812 04:44:07.879253 ==============================================================
4813 04:44:07.879795 Gating Mode config
4814 04:44:07.885396 ==============================================================
4815 04:44:07.885854 Config description:
4816 04:44:07.896186 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4817 04:44:07.902369 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4818 04:44:07.909462 SELPH_MODE 0: By rank 1: By Phase
4819 04:44:07.912081 ==============================================================
4820 04:44:07.915669 GAT_TRACK_EN = 1
4821 04:44:07.919290 RX_GATING_MODE = 2
4822 04:44:07.922557 RX_GATING_TRACK_MODE = 2
4823 04:44:07.925447 SELPH_MODE = 1
4824 04:44:07.929119 PICG_EARLY_EN = 1
4825 04:44:07.932507 VALID_LAT_VALUE = 1
4826 04:44:07.935452 ==============================================================
4827 04:44:07.938334 Enter into Gating configuration >>>>
4828 04:44:07.941820 Exit from Gating configuration <<<<
4829 04:44:07.945295 Enter into DVFS_PRE_config >>>>>
4830 04:44:07.959675 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4831 04:44:07.961811 Exit from DVFS_PRE_config <<<<<
4832 04:44:07.966018 Enter into PICG configuration >>>>
4833 04:44:07.969010 Exit from PICG configuration <<<<
4834 04:44:07.969471 [RX_INPUT] configuration >>>>>
4835 04:44:07.972560 [RX_INPUT] configuration <<<<<
4836 04:44:07.978673 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4837 04:44:07.981415 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4838 04:44:07.988884 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4839 04:44:07.995765 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4840 04:44:08.001861 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4841 04:44:08.008300 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4842 04:44:08.011689 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4843 04:44:08.014978 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4844 04:44:08.021836 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4845 04:44:08.025230 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4846 04:44:08.028257 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4847 04:44:08.031370 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4848 04:44:08.034903 ===================================
4849 04:44:08.038249 LPDDR4 DRAM CONFIGURATION
4850 04:44:08.041523 ===================================
4851 04:44:08.044828 EX_ROW_EN[0] = 0x0
4852 04:44:08.045301 EX_ROW_EN[1] = 0x0
4853 04:44:08.048047 LP4Y_EN = 0x0
4854 04:44:08.048514 WORK_FSP = 0x0
4855 04:44:08.051202 WL = 0x3
4856 04:44:08.051672 RL = 0x3
4857 04:44:08.055045 BL = 0x2
4858 04:44:08.055616 RPST = 0x0
4859 04:44:08.058697 RD_PRE = 0x0
4860 04:44:08.059267 WR_PRE = 0x1
4861 04:44:08.061123 WR_PST = 0x0
4862 04:44:08.065147 DBI_WR = 0x0
4863 04:44:08.065615 DBI_RD = 0x0
4864 04:44:08.067807 OTF = 0x1
4865 04:44:08.071468 ===================================
4866 04:44:08.074516 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4867 04:44:08.077946 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4868 04:44:08.081043 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4869 04:44:08.084571 ===================================
4870 04:44:08.088025 LPDDR4 DRAM CONFIGURATION
4871 04:44:08.090725 ===================================
4872 04:44:08.094188 EX_ROW_EN[0] = 0x10
4873 04:44:08.094645 EX_ROW_EN[1] = 0x0
4874 04:44:08.097815 LP4Y_EN = 0x0
4875 04:44:08.098271 WORK_FSP = 0x0
4876 04:44:08.101104 WL = 0x3
4877 04:44:08.101657 RL = 0x3
4878 04:44:08.105182 BL = 0x2
4879 04:44:08.105736 RPST = 0x0
4880 04:44:08.107794 RD_PRE = 0x0
4881 04:44:08.108346 WR_PRE = 0x1
4882 04:44:08.110973 WR_PST = 0x0
4883 04:44:08.113965 DBI_WR = 0x0
4884 04:44:08.114418 DBI_RD = 0x0
4885 04:44:08.118019 OTF = 0x1
4886 04:44:08.120773 ===================================
4887 04:44:08.124452 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4888 04:44:08.129086 nWR fixed to 30
4889 04:44:08.132787 [ModeRegInit_LP4] CH0 RK0
4890 04:44:08.133312 [ModeRegInit_LP4] CH0 RK1
4891 04:44:08.136006 [ModeRegInit_LP4] CH1 RK0
4892 04:44:08.139710 [ModeRegInit_LP4] CH1 RK1
4893 04:44:08.140166 match AC timing 8
4894 04:44:08.147570 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4895 04:44:08.150012 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4896 04:44:08.152615 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4897 04:44:08.159578 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4898 04:44:08.162451 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4899 04:44:08.163016 ==
4900 04:44:08.166327 Dram Type= 6, Freq= 0, CH_0, rank 0
4901 04:44:08.169119 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4902 04:44:08.169583 ==
4903 04:44:08.175858 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4904 04:44:08.182440 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4905 04:44:08.185987 [CA 0] Center 38 (8~69) winsize 62
4906 04:44:08.189373 [CA 1] Center 38 (8~69) winsize 62
4907 04:44:08.192276 [CA 2] Center 36 (6~67) winsize 62
4908 04:44:08.195524 [CA 3] Center 36 (6~66) winsize 61
4909 04:44:08.199358 [CA 4] Center 35 (4~66) winsize 63
4910 04:44:08.203787 [CA 5] Center 34 (4~65) winsize 62
4911 04:44:08.204342
4912 04:44:08.205402 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4913 04:44:08.205803
4914 04:44:08.209116 [CATrainingPosCal] consider 1 rank data
4915 04:44:08.212510 u2DelayCellTimex100 = 270/100 ps
4916 04:44:08.216239 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4917 04:44:08.219406 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4918 04:44:08.223186 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4919 04:44:08.225451 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4920 04:44:08.228862 CA4 delay=35 (4~66),Diff = 1 PI (6 cell)
4921 04:44:08.235921 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4922 04:44:08.236476
4923 04:44:08.238643 CA PerBit enable=1, Macro0, CA PI delay=34
4924 04:44:08.239174
4925 04:44:08.242425 [CBTSetCACLKResult] CA Dly = 34
4926 04:44:08.243111 CS Dly: 7 (0~38)
4927 04:44:08.243490 ==
4928 04:44:08.245559 Dram Type= 6, Freq= 0, CH_0, rank 1
4929 04:44:08.249161 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4930 04:44:08.252223 ==
4931 04:44:08.255285 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4932 04:44:08.262376 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4933 04:44:08.265415 [CA 0] Center 38 (8~69) winsize 62
4934 04:44:08.268316 [CA 1] Center 38 (7~69) winsize 63
4935 04:44:08.271848 [CA 2] Center 36 (5~67) winsize 63
4936 04:44:08.276553 [CA 3] Center 35 (5~66) winsize 62
4937 04:44:08.279106 [CA 4] Center 34 (4~64) winsize 61
4938 04:44:08.281829 [CA 5] Center 34 (4~65) winsize 62
4939 04:44:08.282286
4940 04:44:08.285619 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4941 04:44:08.286075
4942 04:44:08.289278 [CATrainingPosCal] consider 2 rank data
4943 04:44:08.291449 u2DelayCellTimex100 = 270/100 ps
4944 04:44:08.295004 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4945 04:44:08.298233 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4946 04:44:08.301384 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4947 04:44:08.308618 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4948 04:44:08.311775 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4949 04:44:08.314808 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4950 04:44:08.315357
4951 04:44:08.318293 CA PerBit enable=1, Macro0, CA PI delay=34
4952 04:44:08.318748
4953 04:44:08.321897 [CBTSetCACLKResult] CA Dly = 34
4954 04:44:08.322445 CS Dly: 7 (0~39)
4955 04:44:08.322814
4956 04:44:08.324441 ----->DramcWriteLeveling(PI) begin...
4957 04:44:08.324948 ==
4958 04:44:08.327904 Dram Type= 6, Freq= 0, CH_0, rank 0
4959 04:44:08.334927 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4960 04:44:08.335481 ==
4961 04:44:08.337887 Write leveling (Byte 0): 29 => 29
4962 04:44:08.341363 Write leveling (Byte 1): 28 => 28
4963 04:44:08.341824 DramcWriteLeveling(PI) end<-----
4964 04:44:08.344772
4965 04:44:08.345230 ==
4966 04:44:08.348399 Dram Type= 6, Freq= 0, CH_0, rank 0
4967 04:44:08.351856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4968 04:44:08.352417 ==
4969 04:44:08.354957 [Gating] SW mode calibration
4970 04:44:08.361450 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4971 04:44:08.364895 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4972 04:44:08.371399 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4973 04:44:08.374850 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4974 04:44:08.377986 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4975 04:44:08.384036 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4976 04:44:08.387908 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4977 04:44:08.390946 0 10 20 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
4978 04:44:08.398301 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4979 04:44:08.400907 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4980 04:44:08.404432 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4981 04:44:08.411531 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4982 04:44:08.413990 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4983 04:44:08.418052 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4984 04:44:08.424378 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4985 04:44:08.427796 0 11 20 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4986 04:44:08.431105 0 11 24 | B1->B0 | 3534 4141 | 1 1 | (1 1) (0 0)
4987 04:44:08.437749 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4988 04:44:08.440893 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4989 04:44:08.443896 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4990 04:44:08.450701 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4991 04:44:08.453926 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4992 04:44:08.457831 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4993 04:44:08.464193 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4994 04:44:08.467227 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4995 04:44:08.470875 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4996 04:44:08.477148 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4997 04:44:08.480341 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4998 04:44:08.483783 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 04:44:08.490545 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5000 04:44:08.493705 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 04:44:08.497106 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5002 04:44:08.503703 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5003 04:44:08.507165 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 04:44:08.510997 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5005 04:44:08.516863 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5006 04:44:08.520846 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5007 04:44:08.523050 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 04:44:08.530320 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5009 04:44:08.533481 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5010 04:44:08.536408 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5011 04:44:08.539483 Total UI for P1: 0, mck2ui 16
5012 04:44:08.543012 best dqsien dly found for B0: ( 0, 14, 18)
5013 04:44:08.549984 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5014 04:44:08.550557 Total UI for P1: 0, mck2ui 16
5015 04:44:08.556446 best dqsien dly found for B1: ( 0, 14, 24)
5016 04:44:08.560419 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5017 04:44:08.563377 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
5018 04:44:08.563928
5019 04:44:08.566116 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5020 04:44:08.570541 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 24)
5021 04:44:08.573047 [Gating] SW calibration Done
5022 04:44:08.573503 ==
5023 04:44:08.576134 Dram Type= 6, Freq= 0, CH_0, rank 0
5024 04:44:08.580488 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5025 04:44:08.581104 ==
5026 04:44:08.582683 RX Vref Scan: 0
5027 04:44:08.583157
5028 04:44:08.583635 RX Vref 0 -> 0, step: 1
5029 04:44:08.584089
5030 04:44:08.586282 RX Delay -80 -> 252, step: 8
5031 04:44:08.589209 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5032 04:44:08.596648 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5033 04:44:08.599247 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5034 04:44:08.602981 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5035 04:44:08.606094 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5036 04:44:08.609300 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5037 04:44:08.612856 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5038 04:44:08.619137 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5039 04:44:08.622156 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5040 04:44:08.625613 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5041 04:44:08.629907 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5042 04:44:08.632530 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5043 04:44:08.638828 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5044 04:44:08.642511 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5045 04:44:08.645924 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5046 04:44:08.648917 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5047 04:44:08.649388 ==
5048 04:44:08.653222 Dram Type= 6, Freq= 0, CH_0, rank 0
5049 04:44:08.655772 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5050 04:44:08.659643 ==
5051 04:44:08.660110 DQS Delay:
5052 04:44:08.660587 DQS0 = 0, DQS1 = 0
5053 04:44:08.662081 DQM Delay:
5054 04:44:08.662547 DQM0 = 95, DQM1 = 86
5055 04:44:08.665838 DQ Delay:
5056 04:44:08.669266 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5057 04:44:08.672418 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =103
5058 04:44:08.675150 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5059 04:44:08.678910 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5060 04:44:08.679444
5061 04:44:08.679886
5062 04:44:08.680293 ==
5063 04:44:08.683323 Dram Type= 6, Freq= 0, CH_0, rank 0
5064 04:44:08.685544 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5065 04:44:08.685974 ==
5066 04:44:08.686415
5067 04:44:08.686833
5068 04:44:08.688478 TX Vref Scan disable
5069 04:44:08.688950 == TX Byte 0 ==
5070 04:44:08.695234 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5071 04:44:08.698711 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5072 04:44:08.699243 == TX Byte 1 ==
5073 04:44:08.705868 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5074 04:44:08.709060 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5075 04:44:08.709590 ==
5076 04:44:08.711932 Dram Type= 6, Freq= 0, CH_0, rank 0
5077 04:44:08.715168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5078 04:44:08.715601 ==
5079 04:44:08.716037
5080 04:44:08.718294
5081 04:44:08.718820 TX Vref Scan disable
5082 04:44:08.721568 == TX Byte 0 ==
5083 04:44:08.725449 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5084 04:44:08.728199 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5085 04:44:08.731540 == TX Byte 1 ==
5086 04:44:08.734754 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5087 04:44:08.737911 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5088 04:44:08.742145
5089 04:44:08.742668 [DATLAT]
5090 04:44:08.743114 Freq=933, CH0 RK0
5091 04:44:08.743531
5092 04:44:08.744466 DATLAT Default: 0xd
5093 04:44:08.744970 0, 0xFFFF, sum = 0
5094 04:44:08.747930 1, 0xFFFF, sum = 0
5095 04:44:08.748352 2, 0xFFFF, sum = 0
5096 04:44:08.751731 3, 0xFFFF, sum = 0
5097 04:44:08.752252 4, 0xFFFF, sum = 0
5098 04:44:08.755021 5, 0xFFFF, sum = 0
5099 04:44:08.758308 6, 0xFFFF, sum = 0
5100 04:44:08.758821 7, 0xFFFF, sum = 0
5101 04:44:08.761013 8, 0xFFFF, sum = 0
5102 04:44:08.761435 9, 0xFFFF, sum = 0
5103 04:44:08.765101 10, 0x0, sum = 1
5104 04:44:08.765626 11, 0x0, sum = 2
5105 04:44:08.765969 12, 0x0, sum = 3
5106 04:44:08.767995 13, 0x0, sum = 4
5107 04:44:08.768460 best_step = 11
5108 04:44:08.768877
5109 04:44:08.771195 ==
5110 04:44:08.771746 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 04:44:08.777991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5112 04:44:08.778546 ==
5113 04:44:08.778912 RX Vref Scan: 1
5114 04:44:08.779250
5115 04:44:08.781402 RX Vref 0 -> 0, step: 1
5116 04:44:08.781894
5117 04:44:08.784292 RX Delay -69 -> 252, step: 4
5118 04:44:08.784857
5119 04:44:08.787984 Set Vref, RX VrefLevel [Byte0]: 51
5120 04:44:08.790911 [Byte1]: 48
5121 04:44:08.791458
5122 04:44:08.794298 Final RX Vref Byte 0 = 51 to rank0
5123 04:44:08.798023 Final RX Vref Byte 1 = 48 to rank0
5124 04:44:08.801640 Final RX Vref Byte 0 = 51 to rank1
5125 04:44:08.804592 Final RX Vref Byte 1 = 48 to rank1==
5126 04:44:08.807908 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 04:44:08.811115 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5128 04:44:08.813962 ==
5129 04:44:08.814434 DQS Delay:
5130 04:44:08.814914 DQS0 = 0, DQS1 = 0
5131 04:44:08.818844 DQM Delay:
5132 04:44:08.819409 DQM0 = 96, DQM1 = 86
5133 04:44:08.820942 DQ Delay:
5134 04:44:08.824037 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =92
5135 04:44:08.828444 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =102
5136 04:44:08.829073 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =78
5137 04:44:08.834173 DQ12 =94, DQ13 =92, DQ14 =100, DQ15 =98
5138 04:44:08.834812
5139 04:44:08.835297
5140 04:44:08.840798 [DQSOSCAuto] RK0, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5141 04:44:08.844226 CH0 RK0: MR19=505, MR18=2222
5142 04:44:08.851184 CH0_RK0: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5143 04:44:08.851757
5144 04:44:08.853978 ----->DramcWriteLeveling(PI) begin...
5145 04:44:08.854561 ==
5146 04:44:08.857435 Dram Type= 6, Freq= 0, CH_0, rank 1
5147 04:44:08.860793 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5148 04:44:08.861371 ==
5149 04:44:08.864184 Write leveling (Byte 0): 29 => 29
5150 04:44:08.867381 Write leveling (Byte 1): 23 => 23
5151 04:44:08.870713 DramcWriteLeveling(PI) end<-----
5152 04:44:08.871284
5153 04:44:08.871765 ==
5154 04:44:08.874225 Dram Type= 6, Freq= 0, CH_0, rank 1
5155 04:44:08.877219 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5156 04:44:08.877698 ==
5157 04:44:08.880857 [Gating] SW mode calibration
5158 04:44:08.887849 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5159 04:44:08.893944 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5160 04:44:08.897117 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 04:44:08.904219 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 04:44:08.907113 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 04:44:08.910533 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 04:44:08.914998 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 04:44:08.920513 0 10 20 | B1->B0 | 3131 2e2e | 1 1 | (1 1) (1 1)
5166 04:44:08.923409 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 04:44:08.927196 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 04:44:08.933652 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 04:44:08.937626 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 04:44:08.940433 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 04:44:08.946832 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 04:44:08.950411 0 11 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5173 04:44:08.954145 0 11 20 | B1->B0 | 3232 3636 | 0 0 | (0 0) (1 1)
5174 04:44:08.961113 0 11 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5175 04:44:08.965924 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 04:44:08.966899 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 04:44:08.973554 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 04:44:08.976695 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 04:44:08.979935 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 04:44:08.986743 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5181 04:44:08.990122 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 04:44:08.993267 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 04:44:09.000031 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 04:44:09.003368 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 04:44:09.006623 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 04:44:09.012792 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 04:44:09.016138 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 04:44:09.019983 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 04:44:09.026060 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 04:44:09.029456 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 04:44:09.033146 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 04:44:09.039874 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 04:44:09.043174 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 04:44:09.046892 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 04:44:09.052913 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 04:44:09.057018 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 04:44:09.059367 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5198 04:44:09.066495 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 04:44:09.067049 Total UI for P1: 0, mck2ui 16
5200 04:44:09.073476 best dqsien dly found for B0: ( 0, 14, 20)
5201 04:44:09.074025 Total UI for P1: 0, mck2ui 16
5202 04:44:09.079616 best dqsien dly found for B1: ( 0, 14, 22)
5203 04:44:09.082568 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5204 04:44:09.086408 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5205 04:44:09.086868
5206 04:44:09.090016 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5207 04:44:09.092588 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5208 04:44:09.096130 [Gating] SW calibration Done
5209 04:44:09.096677 ==
5210 04:44:09.099224 Dram Type= 6, Freq= 0, CH_0, rank 1
5211 04:44:09.102332 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5212 04:44:09.102887 ==
5213 04:44:09.105813 RX Vref Scan: 0
5214 04:44:09.106368
5215 04:44:09.106734 RX Vref 0 -> 0, step: 1
5216 04:44:09.107077
5217 04:44:09.108859 RX Delay -80 -> 252, step: 8
5218 04:44:09.112588 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5219 04:44:09.119035 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5220 04:44:09.122289 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5221 04:44:09.125684 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5222 04:44:09.128874 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5223 04:44:09.132579 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5224 04:44:09.135431 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5225 04:44:09.143217 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5226 04:44:09.145550 iDelay=208, Bit 8, Center 79 (-8 ~ 167) 176
5227 04:44:09.148930 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5228 04:44:09.152282 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5229 04:44:09.156586 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5230 04:44:09.158801 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5231 04:44:09.165390 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5232 04:44:09.169420 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5233 04:44:09.172322 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5234 04:44:09.172913 ==
5235 04:44:09.175538 Dram Type= 6, Freq= 0, CH_0, rank 1
5236 04:44:09.178630 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5237 04:44:09.179179 ==
5238 04:44:09.182211 DQS Delay:
5239 04:44:09.182817 DQS0 = 0, DQS1 = 0
5240 04:44:09.183258 DQM Delay:
5241 04:44:09.185168 DQM0 = 97, DQM1 = 88
5242 04:44:09.185624 DQ Delay:
5243 04:44:09.189113 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5244 04:44:09.192807 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5245 04:44:09.195797 DQ8 =79, DQ9 =71, DQ10 =91, DQ11 =83
5246 04:44:09.198838 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5247 04:44:09.199387
5248 04:44:09.199757
5249 04:44:09.202414 ==
5250 04:44:09.202875 Dram Type= 6, Freq= 0, CH_0, rank 1
5251 04:44:09.208599 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5252 04:44:09.209195 ==
5253 04:44:09.209567
5254 04:44:09.209907
5255 04:44:09.211886 TX Vref Scan disable
5256 04:44:09.212445 == TX Byte 0 ==
5257 04:44:09.215047 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5258 04:44:09.221847 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5259 04:44:09.222413 == TX Byte 1 ==
5260 04:44:09.225215 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5261 04:44:09.231800 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5262 04:44:09.232347 ==
5263 04:44:09.235175 Dram Type= 6, Freq= 0, CH_0, rank 1
5264 04:44:09.238252 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5265 04:44:09.238719 ==
5266 04:44:09.239087
5267 04:44:09.239429
5268 04:44:09.241539 TX Vref Scan disable
5269 04:44:09.244516 == TX Byte 0 ==
5270 04:44:09.248032 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5271 04:44:09.251829 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5272 04:44:09.254870 == TX Byte 1 ==
5273 04:44:09.257976 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5274 04:44:09.261692 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5275 04:44:09.262158
5276 04:44:09.264830 [DATLAT]
5277 04:44:09.265380 Freq=933, CH0 RK1
5278 04:44:09.265746
5279 04:44:09.268199 DATLAT Default: 0xb
5280 04:44:09.268788 0, 0xFFFF, sum = 0
5281 04:44:09.271220 1, 0xFFFF, sum = 0
5282 04:44:09.271685 2, 0xFFFF, sum = 0
5283 04:44:09.275153 3, 0xFFFF, sum = 0
5284 04:44:09.275708 4, 0xFFFF, sum = 0
5285 04:44:09.278148 5, 0xFFFF, sum = 0
5286 04:44:09.278708 6, 0xFFFF, sum = 0
5287 04:44:09.281658 7, 0xFFFF, sum = 0
5288 04:44:09.282212 8, 0xFFFF, sum = 0
5289 04:44:09.284819 9, 0xFFFF, sum = 0
5290 04:44:09.285376 10, 0x0, sum = 1
5291 04:44:09.287985 11, 0x0, sum = 2
5292 04:44:09.288538 12, 0x0, sum = 3
5293 04:44:09.291555 13, 0x0, sum = 4
5294 04:44:09.292112 best_step = 11
5295 04:44:09.292480
5296 04:44:09.292864 ==
5297 04:44:09.295266 Dram Type= 6, Freq= 0, CH_0, rank 1
5298 04:44:09.300957 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5299 04:44:09.301521 ==
5300 04:44:09.301890 RX Vref Scan: 0
5301 04:44:09.302233
5302 04:44:09.304700 RX Vref 0 -> 0, step: 1
5303 04:44:09.305297
5304 04:44:09.308486 RX Delay -69 -> 252, step: 4
5305 04:44:09.311271 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5306 04:44:09.314488 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5307 04:44:09.321476 iDelay=203, Bit 2, Center 98 (7 ~ 190) 184
5308 04:44:09.324131 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5309 04:44:09.327467 iDelay=203, Bit 4, Center 100 (7 ~ 194) 188
5310 04:44:09.330612 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5311 04:44:09.334524 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5312 04:44:09.337434 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5313 04:44:09.343941 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5314 04:44:09.347460 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5315 04:44:09.350953 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5316 04:44:09.354118 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5317 04:44:09.357336 iDelay=203, Bit 12, Center 92 (3 ~ 182) 180
5318 04:44:09.364100 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5319 04:44:09.367368 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5320 04:44:09.370467 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5321 04:44:09.371028 ==
5322 04:44:09.374143 Dram Type= 6, Freq= 0, CH_0, rank 1
5323 04:44:09.378880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5324 04:44:09.379433 ==
5325 04:44:09.380142 DQS Delay:
5326 04:44:09.380510 DQS0 = 0, DQS1 = 0
5327 04:44:09.383414 DQM Delay:
5328 04:44:09.383868 DQM0 = 97, DQM1 = 86
5329 04:44:09.384227 DQ Delay:
5330 04:44:09.387027 DQ0 =92, DQ1 =98, DQ2 =98, DQ3 =92
5331 04:44:09.390404 DQ4 =100, DQ5 =90, DQ6 =104, DQ7 =108
5332 04:44:09.394178 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5333 04:44:09.397383 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =96
5334 04:44:09.397941
5335 04:44:09.399953
5336 04:44:09.407529 [DQSOSCAuto] RK1, (LSB)MR18= 0x2828, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5337 04:44:09.410663 CH0 RK1: MR19=505, MR18=2828
5338 04:44:09.417135 CH0_RK1: MR19=0x505, MR18=0x2828, DQSOSC=409, MR23=63, INC=64, DEC=43
5339 04:44:09.420571 [RxdqsGatingPostProcess] freq 933
5340 04:44:09.424117 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5341 04:44:09.426609 Pre-setting of DQS Precalculation
5342 04:44:09.433371 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5343 04:44:09.433938 ==
5344 04:44:09.436566 Dram Type= 6, Freq= 0, CH_1, rank 0
5345 04:44:09.440221 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5346 04:44:09.440852 ==
5347 04:44:09.446577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5348 04:44:09.449877 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5349 04:44:09.454055 [CA 0] Center 37 (7~68) winsize 62
5350 04:44:09.458633 [CA 1] Center 37 (6~68) winsize 63
5351 04:44:09.460518 [CA 2] Center 34 (4~65) winsize 62
5352 04:44:09.463865 [CA 3] Center 34 (4~65) winsize 62
5353 04:44:09.467868 [CA 4] Center 33 (2~64) winsize 63
5354 04:44:09.470496 [CA 5] Center 33 (3~64) winsize 62
5355 04:44:09.471054
5356 04:44:09.473788 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5357 04:44:09.474363
5358 04:44:09.476883 [CATrainingPosCal] consider 1 rank data
5359 04:44:09.480050 u2DelayCellTimex100 = 270/100 ps
5360 04:44:09.483469 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5361 04:44:09.490105 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5362 04:44:09.493567 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5363 04:44:09.496931 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5364 04:44:09.499776 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5365 04:44:09.503738 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5366 04:44:09.504301
5367 04:44:09.506501 CA PerBit enable=1, Macro0, CA PI delay=33
5368 04:44:09.506957
5369 04:44:09.510322 [CBTSetCACLKResult] CA Dly = 33
5370 04:44:09.513155 CS Dly: 5 (0~36)
5371 04:44:09.513713 ==
5372 04:44:09.516875 Dram Type= 6, Freq= 0, CH_1, rank 1
5373 04:44:09.520519 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5374 04:44:09.521124 ==
5375 04:44:09.526220 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5376 04:44:09.529833 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5377 04:44:09.534412 [CA 0] Center 37 (6~68) winsize 63
5378 04:44:09.536625 [CA 1] Center 37 (6~68) winsize 63
5379 04:44:09.540232 [CA 2] Center 34 (4~65) winsize 62
5380 04:44:09.543457 [CA 3] Center 34 (4~65) winsize 62
5381 04:44:09.547518 [CA 4] Center 33 (2~64) winsize 63
5382 04:44:09.549977 [CA 5] Center 33 (2~64) winsize 63
5383 04:44:09.550470
5384 04:44:09.553671 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5385 04:44:09.554128
5386 04:44:09.557462 [CATrainingPosCal] consider 2 rank data
5387 04:44:09.560147 u2DelayCellTimex100 = 270/100 ps
5388 04:44:09.563375 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5389 04:44:09.570543 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5390 04:44:09.573924 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5391 04:44:09.576574 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5392 04:44:09.581116 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5393 04:44:09.583109 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5394 04:44:09.583563
5395 04:44:09.586376 CA PerBit enable=1, Macro0, CA PI delay=33
5396 04:44:09.586836
5397 04:44:09.589863 [CBTSetCACLKResult] CA Dly = 33
5398 04:44:09.594040 CS Dly: 5 (0~37)
5399 04:44:09.594603
5400 04:44:09.596542 ----->DramcWriteLeveling(PI) begin...
5401 04:44:09.597046 ==
5402 04:44:09.600239 Dram Type= 6, Freq= 0, CH_1, rank 0
5403 04:44:09.603358 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5404 04:44:09.603917 ==
5405 04:44:09.606454 Write leveling (Byte 0): 21 => 21
5406 04:44:09.609528 Write leveling (Byte 1): 22 => 22
5407 04:44:09.613047 DramcWriteLeveling(PI) end<-----
5408 04:44:09.613599
5409 04:44:09.613961 ==
5410 04:44:09.616799 Dram Type= 6, Freq= 0, CH_1, rank 0
5411 04:44:09.619890 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5412 04:44:09.620449 ==
5413 04:44:09.623195 [Gating] SW mode calibration
5414 04:44:09.629974 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5415 04:44:09.636009 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5416 04:44:09.639535 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5417 04:44:09.642959 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5418 04:44:09.649416 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5419 04:44:09.652623 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5420 04:44:09.656377 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5421 04:44:09.662741 0 10 20 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
5422 04:44:09.665855 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5423 04:44:09.668823 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5424 04:44:09.675773 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5425 04:44:09.679549 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5426 04:44:09.682160 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5427 04:44:09.688950 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5428 04:44:09.692350 0 11 16 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5429 04:44:09.696174 0 11 20 | B1->B0 | 2929 4444 | 0 0 | (0 0) (0 0)
5430 04:44:09.702489 0 11 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5431 04:44:09.706134 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5432 04:44:09.709462 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5433 04:44:09.715210 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5434 04:44:09.719119 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5435 04:44:09.721861 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5436 04:44:09.729107 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5437 04:44:09.731897 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5438 04:44:09.735969 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 04:44:09.742098 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 04:44:09.746069 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 04:44:09.748052 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 04:44:09.755854 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 04:44:09.758568 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 04:44:09.761728 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 04:44:09.768620 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 04:44:09.771687 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 04:44:09.775186 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 04:44:09.781534 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 04:44:09.784663 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 04:44:09.788259 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 04:44:09.795585 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 04:44:09.798128 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5453 04:44:09.802030 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5454 04:44:09.804400 Total UI for P1: 0, mck2ui 16
5455 04:44:09.807593 best dqsien dly found for B0: ( 0, 14, 16)
5456 04:44:09.814719 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5457 04:44:09.815294 Total UI for P1: 0, mck2ui 16
5458 04:44:09.820788 best dqsien dly found for B1: ( 0, 14, 18)
5459 04:44:09.824830 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5460 04:44:09.827543 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5461 04:44:09.828018
5462 04:44:09.830770 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5463 04:44:09.834270 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5464 04:44:09.837470 [Gating] SW calibration Done
5465 04:44:09.837981 ==
5466 04:44:09.841084 Dram Type= 6, Freq= 0, CH_1, rank 0
5467 04:44:09.844082 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5468 04:44:09.844545 ==
5469 04:44:09.847300 RX Vref Scan: 0
5470 04:44:09.847756
5471 04:44:09.848116 RX Vref 0 -> 0, step: 1
5472 04:44:09.848455
5473 04:44:09.850658 RX Delay -80 -> 252, step: 8
5474 04:44:09.854198 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5475 04:44:09.860842 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5476 04:44:09.863842 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5477 04:44:09.867917 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5478 04:44:09.870735 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5479 04:44:09.873781 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5480 04:44:09.880915 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5481 04:44:09.884801 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5482 04:44:09.887090 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5483 04:44:09.890751 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5484 04:44:09.893700 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5485 04:44:09.900695 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5486 04:44:09.904300 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5487 04:44:09.907610 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5488 04:44:09.911001 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5489 04:44:09.914049 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5490 04:44:09.914633 ==
5491 04:44:09.917337 Dram Type= 6, Freq= 0, CH_1, rank 0
5492 04:44:09.923780 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5493 04:44:09.924381 ==
5494 04:44:09.924970 DQS Delay:
5495 04:44:09.927119 DQS0 = 0, DQS1 = 0
5496 04:44:09.927594 DQM Delay:
5497 04:44:09.927959 DQM0 = 96, DQM1 = 88
5498 04:44:09.930416 DQ Delay:
5499 04:44:09.933825 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =91
5500 04:44:09.937238 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =95
5501 04:44:09.940312 DQ8 =71, DQ9 =79, DQ10 =87, DQ11 =79
5502 04:44:09.943625 DQ12 =99, DQ13 =99, DQ14 =91, DQ15 =103
5503 04:44:09.944175
5504 04:44:09.944537
5505 04:44:09.944943 ==
5506 04:44:09.947861 Dram Type= 6, Freq= 0, CH_1, rank 0
5507 04:44:09.950314 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5508 04:44:09.950780 ==
5509 04:44:09.951147
5510 04:44:09.951486
5511 04:44:09.953241 TX Vref Scan disable
5512 04:44:09.957016 == TX Byte 0 ==
5513 04:44:09.960302 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5514 04:44:09.964050 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5515 04:44:09.966929 == TX Byte 1 ==
5516 04:44:09.970048 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5517 04:44:09.973438 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5518 04:44:09.973898 ==
5519 04:44:09.977134 Dram Type= 6, Freq= 0, CH_1, rank 0
5520 04:44:09.980026 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5521 04:44:09.983320 ==
5522 04:44:09.983752
5523 04:44:09.984218
5524 04:44:09.984867 TX Vref Scan disable
5525 04:44:09.986878 == TX Byte 0 ==
5526 04:44:09.990962 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5527 04:44:09.996361 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5528 04:44:09.996931 == TX Byte 1 ==
5529 04:44:10.000612 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5530 04:44:10.007023 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5531 04:44:10.007618
5532 04:44:10.008115 [DATLAT]
5533 04:44:10.008577 Freq=933, CH1 RK0
5534 04:44:10.009062
5535 04:44:10.009875 DATLAT Default: 0xd
5536 04:44:10.010281 0, 0xFFFF, sum = 0
5537 04:44:10.014131 1, 0xFFFF, sum = 0
5538 04:44:10.017029 2, 0xFFFF, sum = 0
5539 04:44:10.017613 3, 0xFFFF, sum = 0
5540 04:44:10.020164 4, 0xFFFF, sum = 0
5541 04:44:10.020790 5, 0xFFFF, sum = 0
5542 04:44:10.022975 6, 0xFFFF, sum = 0
5543 04:44:10.023564 7, 0xFFFF, sum = 0
5544 04:44:10.027423 8, 0xFFFF, sum = 0
5545 04:44:10.027908 9, 0xFFFF, sum = 0
5546 04:44:10.029508 10, 0x0, sum = 1
5547 04:44:10.029992 11, 0x0, sum = 2
5548 04:44:10.033685 12, 0x0, sum = 3
5549 04:44:10.034278 13, 0x0, sum = 4
5550 04:44:10.034777 best_step = 11
5551 04:44:10.036927
5552 04:44:10.037437 ==
5553 04:44:10.039724 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 04:44:10.043344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5555 04:44:10.043821 ==
5556 04:44:10.044310 RX Vref Scan: 1
5557 04:44:10.044811
5558 04:44:10.046137 RX Vref 0 -> 0, step: 1
5559 04:44:10.046609
5560 04:44:10.050203 RX Delay -69 -> 252, step: 4
5561 04:44:10.050834
5562 04:44:10.053636 Set Vref, RX VrefLevel [Byte0]: 52
5563 04:44:10.057833 [Byte1]: 48
5564 04:44:10.058309
5565 04:44:10.061426 Final RX Vref Byte 0 = 52 to rank0
5566 04:44:10.062566 Final RX Vref Byte 1 = 48 to rank0
5567 04:44:10.066429 Final RX Vref Byte 0 = 52 to rank1
5568 04:44:10.069204 Final RX Vref Byte 1 = 48 to rank1==
5569 04:44:10.073634 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 04:44:10.079026 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5571 04:44:10.079591 ==
5572 04:44:10.080081 DQS Delay:
5573 04:44:10.080535 DQS0 = 0, DQS1 = 0
5574 04:44:10.082716 DQM Delay:
5575 04:44:10.083298 DQM0 = 94, DQM1 = 87
5576 04:44:10.085739 DQ Delay:
5577 04:44:10.089474 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =90
5578 04:44:10.092637 DQ4 =92, DQ5 =104, DQ6 =102, DQ7 =92
5579 04:44:10.096444 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =80
5580 04:44:10.099752 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5581 04:44:10.100330
5582 04:44:10.100927
5583 04:44:10.105950 [DQSOSCAuto] RK0, (LSB)MR18= 0x3737, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5584 04:44:10.109477 CH1 RK0: MR19=505, MR18=3737
5585 04:44:10.116262 CH1_RK0: MR19=0x505, MR18=0x3737, DQSOSC=404, MR23=63, INC=66, DEC=44
5586 04:44:10.116895
5587 04:44:10.119247 ----->DramcWriteLeveling(PI) begin...
5588 04:44:10.119831 ==
5589 04:44:10.122496 Dram Type= 6, Freq= 0, CH_1, rank 1
5590 04:44:10.126068 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5591 04:44:10.126612 ==
5592 04:44:10.131089 Write leveling (Byte 0): 26 => 26
5593 04:44:10.132772 Write leveling (Byte 1): 26 => 26
5594 04:44:10.135685 DramcWriteLeveling(PI) end<-----
5595 04:44:10.136265
5596 04:44:10.136882 ==
5597 04:44:10.139060 Dram Type= 6, Freq= 0, CH_1, rank 1
5598 04:44:10.142251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5599 04:44:10.142830 ==
5600 04:44:10.146497 [Gating] SW mode calibration
5601 04:44:10.152532 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5602 04:44:10.158976 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5603 04:44:10.162530 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 04:44:10.168876 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 04:44:10.172651 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 04:44:10.176891 0 10 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5607 04:44:10.182495 0 10 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
5608 04:44:10.185121 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5609 04:44:10.188767 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 04:44:10.195119 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 04:44:10.198363 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 04:44:10.202236 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 04:44:10.208947 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 04:44:10.211882 0 11 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5615 04:44:10.215663 0 11 16 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
5616 04:44:10.221660 0 11 20 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
5617 04:44:10.225782 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5618 04:44:10.228206 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 04:44:10.234722 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 04:44:10.239263 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 04:44:10.242645 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 04:44:10.245635 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5623 04:44:10.251573 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5624 04:44:10.255750 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5625 04:44:10.258464 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 04:44:10.265647 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 04:44:10.268524 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 04:44:10.272066 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 04:44:10.279513 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 04:44:10.281374 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 04:44:10.285373 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 04:44:10.291603 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 04:44:10.294367 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 04:44:10.298365 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 04:44:10.304557 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 04:44:10.307902 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 04:44:10.311135 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 04:44:10.318232 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 04:44:10.321011 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5640 04:44:10.324940 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5641 04:44:10.327591 Total UI for P1: 0, mck2ui 16
5642 04:44:10.331303 best dqsien dly found for B0: ( 0, 14, 16)
5643 04:44:10.337926 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 04:44:10.338389 Total UI for P1: 0, mck2ui 16
5645 04:44:10.344498 best dqsien dly found for B1: ( 0, 14, 20)
5646 04:44:10.347767 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5647 04:44:10.351253 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5648 04:44:10.351803
5649 04:44:10.353911 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5650 04:44:10.357411 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5651 04:44:10.360964 [Gating] SW calibration Done
5652 04:44:10.361437 ==
5653 04:44:10.363975 Dram Type= 6, Freq= 0, CH_1, rank 1
5654 04:44:10.367415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5655 04:44:10.368025 ==
5656 04:44:10.371246 RX Vref Scan: 0
5657 04:44:10.371824
5658 04:44:10.372317 RX Vref 0 -> 0, step: 1
5659 04:44:10.374597
5660 04:44:10.375064 RX Delay -80 -> 252, step: 8
5661 04:44:10.380905 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5662 04:44:10.384289 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5663 04:44:10.387676 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5664 04:44:10.391288 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5665 04:44:10.394145 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5666 04:44:10.397217 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5667 04:44:10.404199 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5668 04:44:10.407759 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5669 04:44:10.410744 iDelay=208, Bit 8, Center 71 (-32 ~ 175) 208
5670 04:44:10.414440 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5671 04:44:10.416958 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5672 04:44:10.424016 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5673 04:44:10.426588 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5674 04:44:10.430025 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5675 04:44:10.433251 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5676 04:44:10.436512 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5677 04:44:10.437045 ==
5678 04:44:10.439885 Dram Type= 6, Freq= 0, CH_1, rank 1
5679 04:44:10.447117 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5680 04:44:10.447696 ==
5681 04:44:10.448190 DQS Delay:
5682 04:44:10.450225 DQS0 = 0, DQS1 = 0
5683 04:44:10.450702 DQM Delay:
5684 04:44:10.453042 DQM0 = 97, DQM1 = 86
5685 04:44:10.453498 DQ Delay:
5686 04:44:10.456757 DQ0 =107, DQ1 =87, DQ2 =87, DQ3 =91
5687 04:44:10.460335 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =91
5688 04:44:10.463209 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =79
5689 04:44:10.466200 DQ12 =91, DQ13 =99, DQ14 =95, DQ15 =91
5690 04:44:10.466751
5691 04:44:10.467115
5692 04:44:10.467449 ==
5693 04:44:10.470079 Dram Type= 6, Freq= 0, CH_1, rank 1
5694 04:44:10.473095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5695 04:44:10.473552 ==
5696 04:44:10.473911
5697 04:44:10.474340
5698 04:44:10.476552 TX Vref Scan disable
5699 04:44:10.480423 == TX Byte 0 ==
5700 04:44:10.483338 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5701 04:44:10.486447 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5702 04:44:10.489996 == TX Byte 1 ==
5703 04:44:10.492967 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5704 04:44:10.496107 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5705 04:44:10.496671 ==
5706 04:44:10.500093 Dram Type= 6, Freq= 0, CH_1, rank 1
5707 04:44:10.506748 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5708 04:44:10.507316 ==
5709 04:44:10.507683
5710 04:44:10.508022
5711 04:44:10.508344 TX Vref Scan disable
5712 04:44:10.510113 == TX Byte 0 ==
5713 04:44:10.512911 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5714 04:44:10.520638 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5715 04:44:10.521253 == TX Byte 1 ==
5716 04:44:10.523607 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5717 04:44:10.526698 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5718 04:44:10.530191
5719 04:44:10.530766 [DATLAT]
5720 04:44:10.531264 Freq=933, CH1 RK1
5721 04:44:10.531726
5722 04:44:10.533036 DATLAT Default: 0xb
5723 04:44:10.533513 0, 0xFFFF, sum = 0
5724 04:44:10.536675 1, 0xFFFF, sum = 0
5725 04:44:10.537310 2, 0xFFFF, sum = 0
5726 04:44:10.539794 3, 0xFFFF, sum = 0
5727 04:44:10.543307 4, 0xFFFF, sum = 0
5728 04:44:10.544067 5, 0xFFFF, sum = 0
5729 04:44:10.546678 6, 0xFFFF, sum = 0
5730 04:44:10.547260 7, 0xFFFF, sum = 0
5731 04:44:10.550402 8, 0xFFFF, sum = 0
5732 04:44:10.550984 9, 0xFFFF, sum = 0
5733 04:44:10.553016 10, 0x0, sum = 1
5734 04:44:10.553736 11, 0x0, sum = 2
5735 04:44:10.556556 12, 0x0, sum = 3
5736 04:44:10.557089 13, 0x0, sum = 4
5737 04:44:10.557582 best_step = 11
5738 04:44:10.558037
5739 04:44:10.559724 ==
5740 04:44:10.563248 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 04:44:10.566665 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5742 04:44:10.567245 ==
5743 04:44:10.567736 RX Vref Scan: 0
5744 04:44:10.568190
5745 04:44:10.569731 RX Vref 0 -> 0, step: 1
5746 04:44:10.570207
5747 04:44:10.573257 RX Delay -77 -> 252, step: 4
5748 04:44:10.576244 iDelay=203, Bit 0, Center 96 (7 ~ 186) 180
5749 04:44:10.583038 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5750 04:44:10.586852 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5751 04:44:10.590387 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5752 04:44:10.593653 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5753 04:44:10.595943 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5754 04:44:10.604037 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5755 04:44:10.607271 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5756 04:44:10.610176 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5757 04:44:10.612614 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5758 04:44:10.616154 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5759 04:44:10.622639 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5760 04:44:10.626461 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5761 04:44:10.629510 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5762 04:44:10.632608 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5763 04:44:10.635579 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5764 04:44:10.636054 ==
5765 04:44:10.639849 Dram Type= 6, Freq= 0, CH_1, rank 1
5766 04:44:10.646219 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5767 04:44:10.646771 ==
5768 04:44:10.647137 DQS Delay:
5769 04:44:10.647475 DQS0 = 0, DQS1 = 0
5770 04:44:10.649115 DQM Delay:
5771 04:44:10.649569 DQM0 = 95, DQM1 = 87
5772 04:44:10.652382 DQ Delay:
5773 04:44:10.655688 DQ0 =96, DQ1 =90, DQ2 =88, DQ3 =92
5774 04:44:10.659420 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5775 04:44:10.662438 DQ8 =74, DQ9 =76, DQ10 =86, DQ11 =80
5776 04:44:10.665316 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5777 04:44:10.665865
5778 04:44:10.666226
5779 04:44:10.671968 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5780 04:44:10.675891 CH1 RK1: MR19=505, MR18=2323
5781 04:44:10.682134 CH1_RK1: MR19=0x505, MR18=0x2323, DQSOSC=410, MR23=63, INC=64, DEC=42
5782 04:44:10.685989 [RxdqsGatingPostProcess] freq 933
5783 04:44:10.688757 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5784 04:44:10.691930 Pre-setting of DQS Precalculation
5785 04:44:10.698450 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5786 04:44:10.705660 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5787 04:44:10.712264 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5788 04:44:10.712882
5789 04:44:10.713252
5790 04:44:10.715372 [Calibration Summary] 1866 Mbps
5791 04:44:10.718114 CH 0, Rank 0
5792 04:44:10.718675 SW Impedance : PASS
5793 04:44:10.722985 DUTY Scan : NO K
5794 04:44:10.723537 ZQ Calibration : PASS
5795 04:44:10.724761 Jitter Meter : NO K
5796 04:44:10.728146 CBT Training : PASS
5797 04:44:10.728599 Write leveling : PASS
5798 04:44:10.731931 RX DQS gating : PASS
5799 04:44:10.735949 RX DQ/DQS(RDDQC) : PASS
5800 04:44:10.736499 TX DQ/DQS : PASS
5801 04:44:10.739271 RX DATLAT : PASS
5802 04:44:10.741956 RX DQ/DQS(Engine): PASS
5803 04:44:10.742414 TX OE : NO K
5804 04:44:10.745136 All Pass.
5805 04:44:10.745688
5806 04:44:10.746049 CH 0, Rank 1
5807 04:44:10.748102 SW Impedance : PASS
5808 04:44:10.748649 DUTY Scan : NO K
5809 04:44:10.751728 ZQ Calibration : PASS
5810 04:44:10.754404 Jitter Meter : NO K
5811 04:44:10.754866 CBT Training : PASS
5812 04:44:10.757753 Write leveling : PASS
5813 04:44:10.761031 RX DQS gating : PASS
5814 04:44:10.761489 RX DQ/DQS(RDDQC) : PASS
5815 04:44:10.764924 TX DQ/DQS : PASS
5816 04:44:10.768284 RX DATLAT : PASS
5817 04:44:10.768903 RX DQ/DQS(Engine): PASS
5818 04:44:10.771333 TX OE : NO K
5819 04:44:10.771886 All Pass.
5820 04:44:10.772243
5821 04:44:10.774983 CH 1, Rank 0
5822 04:44:10.775549 SW Impedance : PASS
5823 04:44:10.778058 DUTY Scan : NO K
5824 04:44:10.781364 ZQ Calibration : PASS
5825 04:44:10.781818 Jitter Meter : NO K
5826 04:44:10.784755 CBT Training : PASS
5827 04:44:10.787681 Write leveling : PASS
5828 04:44:10.788226 RX DQS gating : PASS
5829 04:44:10.792159 RX DQ/DQS(RDDQC) : PASS
5830 04:44:10.792779 TX DQ/DQS : PASS
5831 04:44:10.794093 RX DATLAT : PASS
5832 04:44:10.797760 RX DQ/DQS(Engine): PASS
5833 04:44:10.798215 TX OE : NO K
5834 04:44:10.800775 All Pass.
5835 04:44:10.801358
5836 04:44:10.801721 CH 1, Rank 1
5837 04:44:10.804255 SW Impedance : PASS
5838 04:44:10.804865 DUTY Scan : NO K
5839 04:44:10.807957 ZQ Calibration : PASS
5840 04:44:10.810768 Jitter Meter : NO K
5841 04:44:10.811318 CBT Training : PASS
5842 04:44:10.813819 Write leveling : PASS
5843 04:44:10.819259 RX DQS gating : PASS
5844 04:44:10.819807 RX DQ/DQS(RDDQC) : PASS
5845 04:44:10.820524 TX DQ/DQS : PASS
5846 04:44:10.824522 RX DATLAT : PASS
5847 04:44:10.825141 RX DQ/DQS(Engine): PASS
5848 04:44:10.827448 TX OE : NO K
5849 04:44:10.828013 All Pass.
5850 04:44:10.828382
5851 04:44:10.830681 DramC Write-DBI off
5852 04:44:10.833729 PER_BANK_REFRESH: Hybrid Mode
5853 04:44:10.834271 TX_TRACKING: ON
5854 04:44:10.844065 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5855 04:44:10.847054 [FAST_K] Save calibration result to emmc
5856 04:44:10.850418 dramc_set_vcore_voltage set vcore to 650000
5857 04:44:10.853977 Read voltage for 400, 6
5858 04:44:10.854527 Vio18 = 0
5859 04:44:10.854891 Vcore = 650000
5860 04:44:10.857317 Vdram = 0
5861 04:44:10.857891 Vddq = 0
5862 04:44:10.858261 Vmddr = 0
5863 04:44:10.863944 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5864 04:44:10.867011 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5865 04:44:10.869693 MEM_TYPE=3, freq_sel=20
5866 04:44:10.873457 sv_algorithm_assistance_LP4_800
5867 04:44:10.876609 ============ PULL DRAM RESETB DOWN ============
5868 04:44:10.880041 ========== PULL DRAM RESETB DOWN end =========
5869 04:44:10.886840 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5870 04:44:10.889924 ===================================
5871 04:44:10.892677 LPDDR4 DRAM CONFIGURATION
5872 04:44:10.896328 ===================================
5873 04:44:10.896411 EX_ROW_EN[0] = 0x0
5874 04:44:10.899556 EX_ROW_EN[1] = 0x0
5875 04:44:10.899640 LP4Y_EN = 0x0
5876 04:44:10.902981 WORK_FSP = 0x0
5877 04:44:10.903063 WL = 0x2
5878 04:44:10.905869 RL = 0x2
5879 04:44:10.905951 BL = 0x2
5880 04:44:10.909477 RPST = 0x0
5881 04:44:10.909561 RD_PRE = 0x0
5882 04:44:10.912540 WR_PRE = 0x1
5883 04:44:10.912622 WR_PST = 0x0
5884 04:44:10.915705 DBI_WR = 0x0
5885 04:44:10.915787 DBI_RD = 0x0
5886 04:44:10.919624 OTF = 0x1
5887 04:44:10.922364 ===================================
5888 04:44:10.926261 ===================================
5889 04:44:10.926349 ANA top config
5890 04:44:10.929629 ===================================
5891 04:44:10.932201 DLL_ASYNC_EN = 0
5892 04:44:10.935666 ALL_SLAVE_EN = 1
5893 04:44:10.939754 NEW_RANK_MODE = 1
5894 04:44:10.943843 DLL_IDLE_MODE = 1
5895 04:44:10.943923 LP45_APHY_COMB_EN = 1
5896 04:44:10.945913 TX_ODT_DIS = 1
5897 04:44:10.949327 NEW_8X_MODE = 1
5898 04:44:10.952368 ===================================
5899 04:44:10.956255 ===================================
5900 04:44:10.959537 data_rate = 800
5901 04:44:10.962875 CKR = 1
5902 04:44:10.963288 DQ_P2S_RATIO = 4
5903 04:44:10.965734 ===================================
5904 04:44:10.969724 CA_P2S_RATIO = 4
5905 04:44:10.972203 DQ_CA_OPEN = 0
5906 04:44:10.976066 DQ_SEMI_OPEN = 1
5907 04:44:10.979082 CA_SEMI_OPEN = 1
5908 04:44:10.982858 CA_FULL_RATE = 0
5909 04:44:10.983326 DQ_CKDIV4_EN = 0
5910 04:44:10.985861 CA_CKDIV4_EN = 1
5911 04:44:10.989534 CA_PREDIV_EN = 0
5912 04:44:10.992502 PH8_DLY = 0
5913 04:44:10.995824 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5914 04:44:10.999098 DQ_AAMCK_DIV = 0
5915 04:44:10.999662 CA_AAMCK_DIV = 0
5916 04:44:11.003153 CA_ADMCK_DIV = 4
5917 04:44:11.005506 DQ_TRACK_CA_EN = 0
5918 04:44:11.009420 CA_PICK = 800
5919 04:44:11.012210 CA_MCKIO = 400
5920 04:44:11.015797 MCKIO_SEMI = 400
5921 04:44:11.019081 PLL_FREQ = 3016
5922 04:44:11.022263 DQ_UI_PI_RATIO = 32
5923 04:44:11.022734 CA_UI_PI_RATIO = 32
5924 04:44:11.026235 ===================================
5925 04:44:11.028617 ===================================
5926 04:44:11.035128 memory_type:LPDDR4
5927 04:44:11.036128 GP_NUM : 10
5928 04:44:11.036555 SRAM_EN : 1
5929 04:44:11.040018 MD32_EN : 0
5930 04:44:11.042255 ===================================
5931 04:44:11.045136 [ANA_INIT] >>>>>>>>>>>>>>
5932 04:44:11.049601 <<<<<< [CONFIGURE PHASE]: ANA_TX
5933 04:44:11.052332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5934 04:44:11.055043 ===================================
5935 04:44:11.055515 data_rate = 800,PCW = 0X7400
5936 04:44:11.058257 ===================================
5937 04:44:11.061998 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5938 04:44:11.069193 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5939 04:44:11.081425 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5940 04:44:11.085281 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5941 04:44:11.087974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5942 04:44:11.091465 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5943 04:44:11.094528 [ANA_INIT] flow start
5944 04:44:11.095017 [ANA_INIT] PLL >>>>>>>>
5945 04:44:11.098534 [ANA_INIT] PLL <<<<<<<<
5946 04:44:11.101666 [ANA_INIT] MIDPI >>>>>>>>
5947 04:44:11.102233 [ANA_INIT] MIDPI <<<<<<<<
5948 04:44:11.104761 [ANA_INIT] DLL >>>>>>>>
5949 04:44:11.108470 [ANA_INIT] flow end
5950 04:44:11.112858 ============ LP4 DIFF to SE enter ============
5951 04:44:11.115023 ============ LP4 DIFF to SE exit ============
5952 04:44:11.118055 [ANA_INIT] <<<<<<<<<<<<<
5953 04:44:11.121000 [Flow] Enable top DCM control >>>>>
5954 04:44:11.126713 [Flow] Enable top DCM control <<<<<
5955 04:44:11.127731 Enable DLL master slave shuffle
5956 04:44:11.134810 ==============================================================
5957 04:44:11.135364 Gating Mode config
5958 04:44:11.141017 ==============================================================
5959 04:44:11.141569 Config description:
5960 04:44:11.150957 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5961 04:44:11.157240 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5962 04:44:11.167176 SELPH_MODE 0: By rank 1: By Phase
5963 04:44:11.169100 ==============================================================
5964 04:44:11.172947 GAT_TRACK_EN = 0
5965 04:44:11.175127 RX_GATING_MODE = 2
5966 04:44:11.177744 RX_GATING_TRACK_MODE = 2
5967 04:44:11.180766 SELPH_MODE = 1
5968 04:44:11.184954 PICG_EARLY_EN = 1
5969 04:44:11.187054 VALID_LAT_VALUE = 1
5970 04:44:11.193679 ==============================================================
5971 04:44:11.197716 Enter into Gating configuration >>>>
5972 04:44:11.200438 Exit from Gating configuration <<<<
5973 04:44:11.201036 Enter into DVFS_PRE_config >>>>>
5974 04:44:11.214446 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5975 04:44:11.217654 Exit from DVFS_PRE_config <<<<<
5976 04:44:11.220161 Enter into PICG configuration >>>>
5977 04:44:11.223605 Exit from PICG configuration <<<<
5978 04:44:11.224155 [RX_INPUT] configuration >>>>>
5979 04:44:11.227297 [RX_INPUT] configuration <<<<<
5980 04:44:11.234223 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5981 04:44:11.236944 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5982 04:44:11.243670 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5983 04:44:11.250112 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5984 04:44:11.257264 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5985 04:44:11.263382 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5986 04:44:11.266585 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5987 04:44:11.270076 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5988 04:44:11.276134 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5989 04:44:11.281585 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5990 04:44:11.282963 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5991 04:44:11.292331 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5992 04:44:11.293336 ===================================
5993 04:44:11.293744 LPDDR4 DRAM CONFIGURATION
5994 04:44:11.296034 ===================================
5995 04:44:11.301006 EX_ROW_EN[0] = 0x0
5996 04:44:11.301557 EX_ROW_EN[1] = 0x0
5997 04:44:11.302540 LP4Y_EN = 0x0
5998 04:44:11.306598 WORK_FSP = 0x0
5999 04:44:11.307153 WL = 0x2
6000 04:44:11.309820 RL = 0x2
6001 04:44:11.310369 BL = 0x2
6002 04:44:11.312611 RPST = 0x0
6003 04:44:11.313229 RD_PRE = 0x0
6004 04:44:11.316596 WR_PRE = 0x1
6005 04:44:11.317201 WR_PST = 0x0
6006 04:44:11.319490 DBI_WR = 0x0
6007 04:44:11.320039 DBI_RD = 0x0
6008 04:44:11.323293 OTF = 0x1
6009 04:44:11.325607 ===================================
6010 04:44:11.329593 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6011 04:44:11.333133 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6012 04:44:11.339157 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6013 04:44:11.342139 ===================================
6014 04:44:11.342696 LPDDR4 DRAM CONFIGURATION
6015 04:44:11.345513 ===================================
6016 04:44:11.349260 EX_ROW_EN[0] = 0x10
6017 04:44:11.352327 EX_ROW_EN[1] = 0x0
6018 04:44:11.352936 LP4Y_EN = 0x0
6019 04:44:11.355953 WORK_FSP = 0x0
6020 04:44:11.356521 WL = 0x2
6021 04:44:11.359033 RL = 0x2
6022 04:44:11.359557 BL = 0x2
6023 04:44:11.362720 RPST = 0x0
6024 04:44:11.363268 RD_PRE = 0x0
6025 04:44:11.365536 WR_PRE = 0x1
6026 04:44:11.365992 WR_PST = 0x0
6027 04:44:11.368876 DBI_WR = 0x0
6028 04:44:11.369334 DBI_RD = 0x0
6029 04:44:11.371921 OTF = 0x1
6030 04:44:11.375373 ===================================
6031 04:44:11.382247 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6032 04:44:11.385352 nWR fixed to 30
6033 04:44:11.385901 [ModeRegInit_LP4] CH0 RK0
6034 04:44:11.388686 [ModeRegInit_LP4] CH0 RK1
6035 04:44:11.392394 [ModeRegInit_LP4] CH1 RK0
6036 04:44:11.395539 [ModeRegInit_LP4] CH1 RK1
6037 04:44:11.395993 match AC timing 18
6038 04:44:11.399747 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6039 04:44:11.405440 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6040 04:44:11.408867 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6041 04:44:11.415290 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6042 04:44:11.418228 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6043 04:44:11.418791 ==
6044 04:44:11.421880 Dram Type= 6, Freq= 0, CH_0, rank 0
6045 04:44:11.424702 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6046 04:44:11.425197 ==
6047 04:44:11.432343 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6048 04:44:11.437834 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6049 04:44:11.441067 [CA 0] Center 36 (8~64) winsize 57
6050 04:44:11.444828 [CA 1] Center 36 (8~64) winsize 57
6051 04:44:11.445386 [CA 2] Center 36 (8~64) winsize 57
6052 04:44:11.448814 [CA 3] Center 36 (8~64) winsize 57
6053 04:44:11.451252 [CA 4] Center 36 (8~64) winsize 57
6054 04:44:11.454426 [CA 5] Center 36 (8~64) winsize 57
6055 04:44:11.454884
6056 04:44:11.458101 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6057 04:44:11.458704
6058 04:44:11.464756 [CATrainingPosCal] consider 1 rank data
6059 04:44:11.465334 u2DelayCellTimex100 = 270/100 ps
6060 04:44:11.471401 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6061 04:44:11.475403 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6062 04:44:11.477482 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6063 04:44:11.481180 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6064 04:44:11.485264 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6065 04:44:11.488304 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6066 04:44:11.488802
6067 04:44:11.491482 CA PerBit enable=1, Macro0, CA PI delay=36
6068 04:44:11.492047
6069 04:44:11.494463 [CBTSetCACLKResult] CA Dly = 36
6070 04:44:11.497514 CS Dly: 1 (0~32)
6071 04:44:11.497984 ==
6072 04:44:11.501397 Dram Type= 6, Freq= 0, CH_0, rank 1
6073 04:44:11.504517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6074 04:44:11.505134 ==
6075 04:44:11.511061 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6076 04:44:11.514140 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6077 04:44:11.517418 [CA 0] Center 36 (8~64) winsize 57
6078 04:44:11.520773 [CA 1] Center 36 (8~64) winsize 57
6079 04:44:11.524016 [CA 2] Center 36 (8~64) winsize 57
6080 04:44:11.528143 [CA 3] Center 36 (8~64) winsize 57
6081 04:44:11.530652 [CA 4] Center 36 (8~64) winsize 57
6082 04:44:11.533955 [CA 5] Center 36 (8~64) winsize 57
6083 04:44:11.534518
6084 04:44:11.537239 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6085 04:44:11.537730
6086 04:44:11.540657 [CATrainingPosCal] consider 2 rank data
6087 04:44:11.543979 u2DelayCellTimex100 = 270/100 ps
6088 04:44:11.548249 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6089 04:44:11.550569 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6090 04:44:11.557676 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6091 04:44:11.560554 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6092 04:44:11.564049 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6093 04:44:11.566684 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6094 04:44:11.567154
6095 04:44:11.570759 CA PerBit enable=1, Macro0, CA PI delay=36
6096 04:44:11.571328
6097 04:44:11.574129 [CBTSetCACLKResult] CA Dly = 36
6098 04:44:11.574694 CS Dly: 1 (0~32)
6099 04:44:11.575180
6100 04:44:11.576844 ----->DramcWriteLeveling(PI) begin...
6101 04:44:11.580671 ==
6102 04:44:11.583712 Dram Type= 6, Freq= 0, CH_0, rank 0
6103 04:44:11.587020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6104 04:44:11.587635 ==
6105 04:44:11.590570 Write leveling (Byte 0): 32 => 0
6106 04:44:11.593090 Write leveling (Byte 1): 32 => 0
6107 04:44:11.596637 DramcWriteLeveling(PI) end<-----
6108 04:44:11.597237
6109 04:44:11.597602 ==
6110 04:44:11.600331 Dram Type= 6, Freq= 0, CH_0, rank 0
6111 04:44:11.603126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6112 04:44:11.603584 ==
6113 04:44:11.607042 [Gating] SW mode calibration
6114 04:44:11.613301 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6115 04:44:11.619626 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6116 04:44:11.623165 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6117 04:44:11.626593 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6118 04:44:11.633346 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6119 04:44:11.636176 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6120 04:44:11.640129 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6121 04:44:11.646391 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6122 04:44:11.649556 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6123 04:44:11.652782 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6124 04:44:11.659350 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6125 04:44:11.659890 Total UI for P1: 0, mck2ui 16
6126 04:44:11.666164 best dqsien dly found for B0: ( 0, 10, 16)
6127 04:44:11.666717 Total UI for P1: 0, mck2ui 16
6128 04:44:11.669774 best dqsien dly found for B1: ( 0, 10, 24)
6129 04:44:11.675743 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6130 04:44:11.679331 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6131 04:44:11.679892
6132 04:44:11.683085 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6133 04:44:11.685844 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6134 04:44:11.689228 [Gating] SW calibration Done
6135 04:44:11.689683 ==
6136 04:44:11.692396 Dram Type= 6, Freq= 0, CH_0, rank 0
6137 04:44:11.695637 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6138 04:44:11.696207 ==
6139 04:44:11.699240 RX Vref Scan: 0
6140 04:44:11.699788
6141 04:44:11.700151 RX Vref 0 -> 0, step: 1
6142 04:44:11.700489
6143 04:44:11.701865 RX Delay -410 -> 252, step: 16
6144 04:44:11.708681 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6145 04:44:11.712677 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6146 04:44:11.715523 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6147 04:44:11.718782 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6148 04:44:11.725672 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6149 04:44:11.729377 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6150 04:44:11.732285 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6151 04:44:11.736373 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6152 04:44:11.742356 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6153 04:44:11.745608 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6154 04:44:11.749186 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6155 04:44:11.752086 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6156 04:44:11.758154 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6157 04:44:11.761863 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6158 04:44:11.765197 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6159 04:44:11.771723 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6160 04:44:11.772275 ==
6161 04:44:11.775483 Dram Type= 6, Freq= 0, CH_0, rank 0
6162 04:44:11.778968 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6163 04:44:11.779523 ==
6164 04:44:11.779884 DQS Delay:
6165 04:44:11.782137 DQS0 = 43, DQS1 = 59
6166 04:44:11.782687 DQM Delay:
6167 04:44:11.784598 DQM0 = 5, DQM1 = 16
6168 04:44:11.785111 DQ Delay:
6169 04:44:11.788019 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6170 04:44:11.791587 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6171 04:44:11.794824 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6172 04:44:11.798222 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6173 04:44:11.798783
6174 04:44:11.799141
6175 04:44:11.799473 ==
6176 04:44:11.801563 Dram Type= 6, Freq= 0, CH_0, rank 0
6177 04:44:11.804880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6178 04:44:11.805435 ==
6179 04:44:11.805796
6180 04:44:11.806130
6181 04:44:11.808961 TX Vref Scan disable
6182 04:44:11.809516 == TX Byte 0 ==
6183 04:44:11.814655 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6184 04:44:11.817763 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6185 04:44:11.818220 == TX Byte 1 ==
6186 04:44:11.825136 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6187 04:44:11.828274 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6188 04:44:11.828853 ==
6189 04:44:11.831536 Dram Type= 6, Freq= 0, CH_0, rank 0
6190 04:44:11.834693 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6191 04:44:11.835252 ==
6192 04:44:11.835607
6193 04:44:11.835934
6194 04:44:11.837861 TX Vref Scan disable
6195 04:44:11.840930 == TX Byte 0 ==
6196 04:44:11.844524 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6197 04:44:11.847950 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6198 04:44:11.851246 == TX Byte 1 ==
6199 04:44:11.854417 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6200 04:44:11.857735 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6201 04:44:11.858197
6202 04:44:11.858555 [DATLAT]
6203 04:44:11.860758 Freq=400, CH0 RK0
6204 04:44:11.861457
6205 04:44:11.863960 DATLAT Default: 0xf
6206 04:44:11.864411 0, 0xFFFF, sum = 0
6207 04:44:11.868239 1, 0xFFFF, sum = 0
6208 04:44:11.868847 2, 0xFFFF, sum = 0
6209 04:44:11.871396 3, 0xFFFF, sum = 0
6210 04:44:11.871961 4, 0xFFFF, sum = 0
6211 04:44:11.874611 5, 0xFFFF, sum = 0
6212 04:44:11.875176 6, 0xFFFF, sum = 0
6213 04:44:11.877553 7, 0xFFFF, sum = 0
6214 04:44:11.878016 8, 0xFFFF, sum = 0
6215 04:44:11.880367 9, 0xFFFF, sum = 0
6216 04:44:11.880868 10, 0xFFFF, sum = 0
6217 04:44:11.884198 11, 0xFFFF, sum = 0
6218 04:44:11.884661 12, 0x0, sum = 1
6219 04:44:11.887746 13, 0x0, sum = 2
6220 04:44:11.888248 14, 0x0, sum = 3
6221 04:44:11.890663 15, 0x0, sum = 4
6222 04:44:11.891123 best_step = 13
6223 04:44:11.891484
6224 04:44:11.891818 ==
6225 04:44:11.893646 Dram Type= 6, Freq= 0, CH_0, rank 0
6226 04:44:11.901645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6227 04:44:11.902199 ==
6228 04:44:11.902564 RX Vref Scan: 1
6229 04:44:11.902898
6230 04:44:11.904006 RX Vref 0 -> 0, step: 1
6231 04:44:11.904462
6232 04:44:11.907685 RX Delay -359 -> 252, step: 8
6233 04:44:11.908243
6234 04:44:11.910073 Set Vref, RX VrefLevel [Byte0]: 51
6235 04:44:11.914558 [Byte1]: 48
6236 04:44:11.917307
6237 04:44:11.917862 Final RX Vref Byte 0 = 51 to rank0
6238 04:44:11.920540 Final RX Vref Byte 1 = 48 to rank0
6239 04:44:11.923495 Final RX Vref Byte 0 = 51 to rank1
6240 04:44:11.926981 Final RX Vref Byte 1 = 48 to rank1==
6241 04:44:11.930277 Dram Type= 6, Freq= 0, CH_0, rank 0
6242 04:44:11.937300 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6243 04:44:11.937862 ==
6244 04:44:11.938230 DQS Delay:
6245 04:44:11.940627 DQS0 = 52, DQS1 = 68
6246 04:44:11.941237 DQM Delay:
6247 04:44:11.941605 DQM0 = 9, DQM1 = 16
6248 04:44:11.944045 DQ Delay:
6249 04:44:11.947942 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6250 04:44:11.948399 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6251 04:44:11.949691 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6252 04:44:11.953629 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6253 04:44:11.954202
6254 04:44:11.956660
6255 04:44:11.963223 [DQSOSCAuto] RK0, (LSB)MR18= 0x9999, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
6256 04:44:11.966658 CH0 RK0: MR19=C0C, MR18=9999
6257 04:44:11.973061 CH0_RK0: MR19=0xC0C, MR18=0x9999, DQSOSC=390, MR23=63, INC=388, DEC=258
6258 04:44:11.973620 ==
6259 04:44:11.977408 Dram Type= 6, Freq= 0, CH_0, rank 1
6260 04:44:11.980486 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6261 04:44:11.981106 ==
6262 04:44:11.982803 [Gating] SW mode calibration
6263 04:44:11.989224 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6264 04:44:11.996250 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6265 04:44:11.999302 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6266 04:44:12.002821 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6267 04:44:12.009169 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6268 04:44:12.012513 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6269 04:44:12.015965 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 04:44:12.022835 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 04:44:12.026040 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 04:44:12.029202 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6273 04:44:12.036277 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 04:44:12.036874 Total UI for P1: 0, mck2ui 16
6275 04:44:12.039537 best dqsien dly found for B0: ( 0, 10, 16)
6276 04:44:12.042663 Total UI for P1: 0, mck2ui 16
6277 04:44:12.045703 best dqsien dly found for B1: ( 0, 10, 16)
6278 04:44:12.052208 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6279 04:44:12.055853 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6280 04:44:12.056408
6281 04:44:12.059996 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6282 04:44:12.061875 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6283 04:44:12.065655 [Gating] SW calibration Done
6284 04:44:12.066112 ==
6285 04:44:12.069068 Dram Type= 6, Freq= 0, CH_0, rank 1
6286 04:44:12.072862 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6287 04:44:12.073323 ==
6288 04:44:12.075331 RX Vref Scan: 0
6289 04:44:12.075779
6290 04:44:12.076136 RX Vref 0 -> 0, step: 1
6291 04:44:12.076468
6292 04:44:12.078849 RX Delay -410 -> 252, step: 16
6293 04:44:12.085609 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6294 04:44:12.089064 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6295 04:44:12.092416 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6296 04:44:12.095424 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6297 04:44:12.102210 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6298 04:44:12.105288 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6299 04:44:12.108911 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6300 04:44:12.112583 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6301 04:44:12.118139 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6302 04:44:12.121841 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6303 04:44:12.125085 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6304 04:44:12.128439 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6305 04:44:12.135207 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6306 04:44:12.138261 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6307 04:44:12.141413 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6308 04:44:12.148311 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6309 04:44:12.148893 ==
6310 04:44:12.152004 Dram Type= 6, Freq= 0, CH_0, rank 1
6311 04:44:12.154693 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6312 04:44:12.155245 ==
6313 04:44:12.155611 DQS Delay:
6314 04:44:12.157968 DQS0 = 43, DQS1 = 59
6315 04:44:12.158517 DQM Delay:
6316 04:44:12.161226 DQM0 = 7, DQM1 = 15
6317 04:44:12.161777 DQ Delay:
6318 04:44:12.164772 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6319 04:44:12.168320 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6320 04:44:12.171724 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6321 04:44:12.174728 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6322 04:44:12.175281
6323 04:44:12.175644
6324 04:44:12.175981 ==
6325 04:44:12.177992 Dram Type= 6, Freq= 0, CH_0, rank 1
6326 04:44:12.181387 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6327 04:44:12.181843 ==
6328 04:44:12.182203
6329 04:44:12.182536
6330 04:44:12.184602 TX Vref Scan disable
6331 04:44:12.185220 == TX Byte 0 ==
6332 04:44:12.191583 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6333 04:44:12.194667 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6334 04:44:12.195126 == TX Byte 1 ==
6335 04:44:12.200834 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6336 04:44:12.204396 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6337 04:44:12.205001 ==
6338 04:44:12.207582 Dram Type= 6, Freq= 0, CH_0, rank 1
6339 04:44:12.210637 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6340 04:44:12.211196 ==
6341 04:44:12.211559
6342 04:44:12.211891
6343 04:44:12.213886 TX Vref Scan disable
6344 04:44:12.217414 == TX Byte 0 ==
6345 04:44:12.220637 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6346 04:44:12.224241 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6347 04:44:12.227570 == TX Byte 1 ==
6348 04:44:12.230521 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6349 04:44:12.234187 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6350 04:44:12.234638
6351 04:44:12.234991 [DATLAT]
6352 04:44:12.237632 Freq=400, CH0 RK1
6353 04:44:12.238100
6354 04:44:12.238455 DATLAT Default: 0xd
6355 04:44:12.240353 0, 0xFFFF, sum = 0
6356 04:44:12.240968 1, 0xFFFF, sum = 0
6357 04:44:12.243736 2, 0xFFFF, sum = 0
6358 04:44:12.246865 3, 0xFFFF, sum = 0
6359 04:44:12.247328 4, 0xFFFF, sum = 0
6360 04:44:12.250879 5, 0xFFFF, sum = 0
6361 04:44:12.251336 6, 0xFFFF, sum = 0
6362 04:44:12.253662 7, 0xFFFF, sum = 0
6363 04:44:12.254118 8, 0xFFFF, sum = 0
6364 04:44:12.257422 9, 0xFFFF, sum = 0
6365 04:44:12.257883 10, 0xFFFF, sum = 0
6366 04:44:12.260981 11, 0xFFFF, sum = 0
6367 04:44:12.261438 12, 0x0, sum = 1
6368 04:44:12.263830 13, 0x0, sum = 2
6369 04:44:12.264485 14, 0x0, sum = 3
6370 04:44:12.267053 15, 0x0, sum = 4
6371 04:44:12.267511 best_step = 13
6372 04:44:12.267865
6373 04:44:12.268192 ==
6374 04:44:12.270377 Dram Type= 6, Freq= 0, CH_0, rank 1
6375 04:44:12.273392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6376 04:44:12.273707 ==
6377 04:44:12.277239 RX Vref Scan: 0
6378 04:44:12.277651
6379 04:44:12.281527 RX Vref 0 -> 0, step: 1
6380 04:44:12.281942
6381 04:44:12.283368 RX Delay -359 -> 252, step: 8
6382 04:44:12.286923 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6383 04:44:12.293678 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6384 04:44:12.296617 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6385 04:44:12.300082 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6386 04:44:12.307030 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6387 04:44:12.310497 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6388 04:44:12.313345 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6389 04:44:12.316563 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6390 04:44:12.320187 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6391 04:44:12.326305 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6392 04:44:12.329366 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6393 04:44:12.333145 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6394 04:44:12.339750 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6395 04:44:12.343713 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6396 04:44:12.346463 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6397 04:44:12.349789 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6398 04:44:12.352629 ==
6399 04:44:12.353124 Dram Type= 6, Freq= 0, CH_0, rank 1
6400 04:44:12.360416 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6401 04:44:12.361026 ==
6402 04:44:12.361388 DQS Delay:
6403 04:44:12.362967 DQS0 = 52, DQS1 = 64
6404 04:44:12.363629 DQM Delay:
6405 04:44:12.366270 DQM0 = 10, DQM1 = 13
6406 04:44:12.366718 DQ Delay:
6407 04:44:12.369466 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6408 04:44:12.373041 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6409 04:44:12.375710 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6410 04:44:12.379230 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6411 04:44:12.379786
6412 04:44:12.380141
6413 04:44:12.386226 [DQSOSCAuto] RK1, (LSB)MR18= 0xbaba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6414 04:44:12.388968 CH0 RK1: MR19=C0C, MR18=BABA
6415 04:44:12.395490 CH0_RK1: MR19=0xC0C, MR18=0xBABA, DQSOSC=386, MR23=63, INC=396, DEC=264
6416 04:44:12.398858 [RxdqsGatingPostProcess] freq 400
6417 04:44:12.405890 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6418 04:44:12.406445 Pre-setting of DQS Precalculation
6419 04:44:12.412803 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6420 04:44:12.413521 ==
6421 04:44:12.415588 Dram Type= 6, Freq= 0, CH_1, rank 0
6422 04:44:12.418661 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6423 04:44:12.419211 ==
6424 04:44:12.425905 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6425 04:44:12.431810 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6426 04:44:12.435159 [CA 0] Center 36 (8~64) winsize 57
6427 04:44:12.439414 [CA 1] Center 36 (8~64) winsize 57
6428 04:44:12.442876 [CA 2] Center 36 (8~64) winsize 57
6429 04:44:12.445094 [CA 3] Center 36 (8~64) winsize 57
6430 04:44:12.445822 [CA 4] Center 36 (8~64) winsize 57
6431 04:44:12.448416 [CA 5] Center 36 (8~64) winsize 57
6432 04:44:12.449018
6433 04:44:12.455544 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6434 04:44:12.456094
6435 04:44:12.458742 [CATrainingPosCal] consider 1 rank data
6436 04:44:12.462038 u2DelayCellTimex100 = 270/100 ps
6437 04:44:12.465135 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6438 04:44:12.468899 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6439 04:44:12.471523 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6440 04:44:12.475587 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6441 04:44:12.478086 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6442 04:44:12.481179 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6443 04:44:12.481630
6444 04:44:12.485235 CA PerBit enable=1, Macro0, CA PI delay=36
6445 04:44:12.485771
6446 04:44:12.487718 [CBTSetCACLKResult] CA Dly = 36
6447 04:44:12.491554 CS Dly: 1 (0~32)
6448 04:44:12.492003 ==
6449 04:44:12.494718 Dram Type= 6, Freq= 0, CH_1, rank 1
6450 04:44:12.498292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6451 04:44:12.498743 ==
6452 04:44:12.505407 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6453 04:44:12.511647 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6454 04:44:12.514533 [CA 0] Center 36 (8~64) winsize 57
6455 04:44:12.515081 [CA 1] Center 36 (8~64) winsize 57
6456 04:44:12.518252 [CA 2] Center 36 (8~64) winsize 57
6457 04:44:12.521094 [CA 3] Center 36 (8~64) winsize 57
6458 04:44:12.524205 [CA 4] Center 36 (8~64) winsize 57
6459 04:44:12.529294 [CA 5] Center 36 (8~64) winsize 57
6460 04:44:12.529841
6461 04:44:12.531200 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6462 04:44:12.531664
6463 04:44:12.534741 [CATrainingPosCal] consider 2 rank data
6464 04:44:12.538112 u2DelayCellTimex100 = 270/100 ps
6465 04:44:12.541275 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6466 04:44:12.547390 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6467 04:44:12.551232 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6468 04:44:12.554181 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6469 04:44:12.557345 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6470 04:44:12.561451 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6471 04:44:12.562000
6472 04:44:12.563741 CA PerBit enable=1, Macro0, CA PI delay=36
6473 04:44:12.564354
6474 04:44:12.567919 [CBTSetCACLKResult] CA Dly = 36
6475 04:44:12.571168 CS Dly: 1 (0~32)
6476 04:44:12.571716
6477 04:44:12.574473 ----->DramcWriteLeveling(PI) begin...
6478 04:44:12.575028 ==
6479 04:44:12.577331 Dram Type= 6, Freq= 0, CH_1, rank 0
6480 04:44:12.582374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6481 04:44:12.582925 ==
6482 04:44:12.583973 Write leveling (Byte 0): 32 => 0
6483 04:44:12.587257 Write leveling (Byte 1): 32 => 0
6484 04:44:12.590256 DramcWriteLeveling(PI) end<-----
6485 04:44:12.590719
6486 04:44:12.591070 ==
6487 04:44:12.593521 Dram Type= 6, Freq= 0, CH_1, rank 0
6488 04:44:12.597093 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6489 04:44:12.597663 ==
6490 04:44:12.600392 [Gating] SW mode calibration
6491 04:44:12.607494 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6492 04:44:12.613534 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6493 04:44:12.616764 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6494 04:44:12.620243 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 04:44:12.627421 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6496 04:44:12.629845 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 04:44:12.634380 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 04:44:12.640689 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 04:44:12.645264 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 04:44:12.646581 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6501 04:44:12.653041 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 04:44:12.653498 Total UI for P1: 0, mck2ui 16
6503 04:44:12.659879 best dqsien dly found for B0: ( 0, 10, 16)
6504 04:44:12.660430 Total UI for P1: 0, mck2ui 16
6505 04:44:12.666206 best dqsien dly found for B1: ( 0, 10, 16)
6506 04:44:12.669472 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6507 04:44:12.673272 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6508 04:44:12.673828
6509 04:44:12.676749 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6510 04:44:12.680010 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6511 04:44:12.684982 [Gating] SW calibration Done
6512 04:44:12.685529 ==
6513 04:44:12.686240 Dram Type= 6, Freq= 0, CH_1, rank 0
6514 04:44:12.689540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6515 04:44:12.690094 ==
6516 04:44:12.693348 RX Vref Scan: 0
6517 04:44:12.693800
6518 04:44:12.694155 RX Vref 0 -> 0, step: 1
6519 04:44:12.697354
6520 04:44:12.697806 RX Delay -410 -> 252, step: 16
6521 04:44:12.703348 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6522 04:44:12.706168 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6523 04:44:12.709328 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6524 04:44:12.712489 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6525 04:44:12.719738 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6526 04:44:12.723087 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6527 04:44:12.726965 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6528 04:44:12.730147 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6529 04:44:12.737070 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6530 04:44:12.739330 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6531 04:44:12.742564 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6532 04:44:12.749549 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6533 04:44:12.752812 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6534 04:44:12.756235 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6535 04:44:12.759436 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6536 04:44:12.765877 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6537 04:44:12.766621 ==
6538 04:44:12.768601 Dram Type= 6, Freq= 0, CH_1, rank 0
6539 04:44:12.772364 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6540 04:44:12.772998 ==
6541 04:44:12.773408 DQS Delay:
6542 04:44:12.775838 DQS0 = 43, DQS1 = 59
6543 04:44:12.776388 DQM Delay:
6544 04:44:12.778784 DQM0 = 6, DQM1 = 14
6545 04:44:12.779235 DQ Delay:
6546 04:44:12.782289 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6547 04:44:12.785611 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6548 04:44:12.789125 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6549 04:44:12.792427 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6550 04:44:12.792917
6551 04:44:12.793278
6552 04:44:12.793609 ==
6553 04:44:12.795668 Dram Type= 6, Freq= 0, CH_1, rank 0
6554 04:44:12.798856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6555 04:44:12.799429 ==
6556 04:44:12.799790
6557 04:44:12.800122
6558 04:44:12.802754 TX Vref Scan disable
6559 04:44:12.805045 == TX Byte 0 ==
6560 04:44:12.808591 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6561 04:44:12.812956 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6562 04:44:12.815405 == TX Byte 1 ==
6563 04:44:12.819118 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6564 04:44:12.822038 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6565 04:44:12.822583 ==
6566 04:44:12.825670 Dram Type= 6, Freq= 0, CH_1, rank 0
6567 04:44:12.828647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6568 04:44:12.831809 ==
6569 04:44:12.832264
6570 04:44:12.832652
6571 04:44:12.833191 TX Vref Scan disable
6572 04:44:12.835261 == TX Byte 0 ==
6573 04:44:12.838876 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6574 04:44:12.841478 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6575 04:44:12.845113 == TX Byte 1 ==
6576 04:44:12.848469 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6577 04:44:12.851983 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6578 04:44:12.852443
6579 04:44:12.855278 [DATLAT]
6580 04:44:12.855835 Freq=400, CH1 RK0
6581 04:44:12.856201
6582 04:44:12.858089 DATLAT Default: 0xf
6583 04:44:12.858542 0, 0xFFFF, sum = 0
6584 04:44:12.861189 1, 0xFFFF, sum = 0
6585 04:44:12.861751 2, 0xFFFF, sum = 0
6586 04:44:12.865167 3, 0xFFFF, sum = 0
6587 04:44:12.865734 4, 0xFFFF, sum = 0
6588 04:44:12.867578 5, 0xFFFF, sum = 0
6589 04:44:12.868054 6, 0xFFFF, sum = 0
6590 04:44:12.870977 7, 0xFFFF, sum = 0
6591 04:44:12.871441 8, 0xFFFF, sum = 0
6592 04:44:12.874938 9, 0xFFFF, sum = 0
6593 04:44:12.875503 10, 0xFFFF, sum = 0
6594 04:44:12.878181 11, 0xFFFF, sum = 0
6595 04:44:12.881011 12, 0x0, sum = 1
6596 04:44:12.881477 13, 0x0, sum = 2
6597 04:44:12.881848 14, 0x0, sum = 3
6598 04:44:12.885033 15, 0x0, sum = 4
6599 04:44:12.885495 best_step = 13
6600 04:44:12.885853
6601 04:44:12.886184 ==
6602 04:44:12.888447 Dram Type= 6, Freq= 0, CH_1, rank 0
6603 04:44:12.894724 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6604 04:44:12.895281 ==
6605 04:44:12.895644 RX Vref Scan: 1
6606 04:44:12.895980
6607 04:44:12.898191 RX Vref 0 -> 0, step: 1
6608 04:44:12.898750
6609 04:44:12.901053 RX Delay -359 -> 252, step: 8
6610 04:44:12.901507
6611 04:44:12.905170 Set Vref, RX VrefLevel [Byte0]: 52
6612 04:44:12.908450 [Byte1]: 48
6613 04:44:12.911161
6614 04:44:12.911716 Final RX Vref Byte 0 = 52 to rank0
6615 04:44:12.914685 Final RX Vref Byte 1 = 48 to rank0
6616 04:44:12.917974 Final RX Vref Byte 0 = 52 to rank1
6617 04:44:12.921105 Final RX Vref Byte 1 = 48 to rank1==
6618 04:44:12.924602 Dram Type= 6, Freq= 0, CH_1, rank 0
6619 04:44:12.930841 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6620 04:44:12.931391 ==
6621 04:44:12.931752 DQS Delay:
6622 04:44:12.934808 DQS0 = 48, DQS1 = 64
6623 04:44:12.935365 DQM Delay:
6624 04:44:12.935728 DQM0 = 9, DQM1 = 17
6625 04:44:12.938022 DQ Delay:
6626 04:44:12.941270 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6627 04:44:12.941749 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6628 04:44:12.944502 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =8
6629 04:44:12.947536 DQ12 =24, DQ13 =28, DQ14 =24, DQ15 =28
6630 04:44:12.948306
6631 04:44:12.951444
6632 04:44:12.957294 [DQSOSCAuto] RK0, (LSB)MR18= 0xd6d6, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6633 04:44:12.960496 CH1 RK0: MR19=C0C, MR18=D6D6
6634 04:44:12.967148 CH1_RK0: MR19=0xC0C, MR18=0xD6D6, DQSOSC=383, MR23=63, INC=402, DEC=268
6635 04:44:12.967916 ==
6636 04:44:12.970459 Dram Type= 6, Freq= 0, CH_1, rank 1
6637 04:44:12.974216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6638 04:44:12.974767 ==
6639 04:44:12.977949 [Gating] SW mode calibration
6640 04:44:12.984630 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6641 04:44:12.991124 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6642 04:44:12.994853 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6643 04:44:12.997774 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6644 04:44:13.003704 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6645 04:44:13.006530 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6646 04:44:13.010922 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6647 04:44:13.017361 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6648 04:44:13.020607 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6649 04:44:13.023493 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6650 04:44:13.026837 Total UI for P1: 0, mck2ui 16
6651 04:44:13.030155 best dqsien dly found for B0: ( 0, 10, 8)
6652 04:44:13.037295 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6653 04:44:13.037858 Total UI for P1: 0, mck2ui 16
6654 04:44:13.043016 best dqsien dly found for B1: ( 0, 10, 16)
6655 04:44:13.046689 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6656 04:44:13.050095 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6657 04:44:13.050650
6658 04:44:13.053394 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6659 04:44:13.056921 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6660 04:44:13.059794 [Gating] SW calibration Done
6661 04:44:13.060316 ==
6662 04:44:13.063074 Dram Type= 6, Freq= 0, CH_1, rank 1
6663 04:44:13.066120 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6664 04:44:13.066579 ==
6665 04:44:13.069282 RX Vref Scan: 0
6666 04:44:13.069738
6667 04:44:13.070098 RX Vref 0 -> 0, step: 1
6668 04:44:13.070459
6669 04:44:13.073244 RX Delay -410 -> 252, step: 16
6670 04:44:13.079126 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6671 04:44:13.083164 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6672 04:44:13.085771 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6673 04:44:13.089240 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6674 04:44:13.096284 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6675 04:44:13.099025 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6676 04:44:13.102849 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6677 04:44:13.105584 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6678 04:44:13.112895 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6679 04:44:13.115609 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6680 04:44:13.119335 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6681 04:44:13.122413 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6682 04:44:13.129158 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6683 04:44:13.132283 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6684 04:44:13.135621 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6685 04:44:13.142697 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6686 04:44:13.143272 ==
6687 04:44:13.145513 Dram Type= 6, Freq= 0, CH_1, rank 1
6688 04:44:13.148956 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6689 04:44:13.149514 ==
6690 04:44:13.149909 DQS Delay:
6691 04:44:13.152179 DQS0 = 35, DQS1 = 59
6692 04:44:13.152629 DQM Delay:
6693 04:44:13.156113 DQM0 = 2, DQM1 = 18
6694 04:44:13.156692 DQ Delay:
6695 04:44:13.158351 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6696 04:44:13.162553 DQ4 =0, DQ5 =8, DQ6 =8, DQ7 =0
6697 04:44:13.165335 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6698 04:44:13.168600 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6699 04:44:13.169289
6700 04:44:13.169841
6701 04:44:13.170197 ==
6702 04:44:13.172048 Dram Type= 6, Freq= 0, CH_1, rank 1
6703 04:44:13.175877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6704 04:44:13.176425 ==
6705 04:44:13.176843
6706 04:44:13.177190
6707 04:44:13.178914 TX Vref Scan disable
6708 04:44:13.179377 == TX Byte 0 ==
6709 04:44:13.184995 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6710 04:44:13.188767 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6711 04:44:13.189229 == TX Byte 1 ==
6712 04:44:13.195145 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6713 04:44:13.198118 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6714 04:44:13.198574 ==
6715 04:44:13.201374 Dram Type= 6, Freq= 0, CH_1, rank 1
6716 04:44:13.204581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6717 04:44:13.205093 ==
6718 04:44:13.205456
6719 04:44:13.205792
6720 04:44:13.208542 TX Vref Scan disable
6721 04:44:13.209038 == TX Byte 0 ==
6722 04:44:13.215327 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6723 04:44:13.218915 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6724 04:44:13.219514 == TX Byte 1 ==
6725 04:44:13.225145 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6726 04:44:13.228340 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6727 04:44:13.228830
6728 04:44:13.229198 [DATLAT]
6729 04:44:13.232217 Freq=400, CH1 RK1
6730 04:44:13.232828
6731 04:44:13.233200 DATLAT Default: 0xd
6732 04:44:13.234939 0, 0xFFFF, sum = 0
6733 04:44:13.235507 1, 0xFFFF, sum = 0
6734 04:44:13.237894 2, 0xFFFF, sum = 0
6735 04:44:13.238357 3, 0xFFFF, sum = 0
6736 04:44:13.241551 4, 0xFFFF, sum = 0
6737 04:44:13.242123 5, 0xFFFF, sum = 0
6738 04:44:13.245064 6, 0xFFFF, sum = 0
6739 04:44:13.245629 7, 0xFFFF, sum = 0
6740 04:44:13.248344 8, 0xFFFF, sum = 0
6741 04:44:13.250946 9, 0xFFFF, sum = 0
6742 04:44:13.251408 10, 0xFFFF, sum = 0
6743 04:44:13.254515 11, 0xFFFF, sum = 0
6744 04:44:13.255077 12, 0x0, sum = 1
6745 04:44:13.257682 13, 0x0, sum = 2
6746 04:44:13.258246 14, 0x0, sum = 3
6747 04:44:13.261214 15, 0x0, sum = 4
6748 04:44:13.261781 best_step = 13
6749 04:44:13.262142
6750 04:44:13.262474 ==
6751 04:44:13.264683 Dram Type= 6, Freq= 0, CH_1, rank 1
6752 04:44:13.267601 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6753 04:44:13.268158 ==
6754 04:44:13.271212 RX Vref Scan: 0
6755 04:44:13.271666
6756 04:44:13.274551 RX Vref 0 -> 0, step: 1
6757 04:44:13.275113
6758 04:44:13.275475 RX Delay -359 -> 252, step: 8
6759 04:44:13.282833 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6760 04:44:13.286183 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6761 04:44:13.289988 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6762 04:44:13.293141 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6763 04:44:13.300108 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6764 04:44:13.302719 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6765 04:44:13.306349 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6766 04:44:13.312673 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6767 04:44:13.315968 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6768 04:44:13.319672 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6769 04:44:13.322506 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6770 04:44:13.329629 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6771 04:44:13.332048 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6772 04:44:13.335447 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6773 04:44:13.339323 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6774 04:44:13.345919 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6775 04:44:13.346479 ==
6776 04:44:13.348796 Dram Type= 6, Freq= 0, CH_1, rank 1
6777 04:44:13.352880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6778 04:44:13.353434 ==
6779 04:44:13.353795 DQS Delay:
6780 04:44:13.355888 DQS0 = 44, DQS1 = 64
6781 04:44:13.356442 DQM Delay:
6782 04:44:13.359141 DQM0 = 5, DQM1 = 15
6783 04:44:13.359698 DQ Delay:
6784 04:44:13.362226 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6785 04:44:13.366134 DQ4 =4, DQ5 =16, DQ6 =12, DQ7 =4
6786 04:44:13.368944 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6787 04:44:13.372591 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6788 04:44:13.373187
6789 04:44:13.373549
6790 04:44:13.378608 [DQSOSCAuto] RK1, (LSB)MR18= 0xa3a3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6791 04:44:13.382609 CH1 RK1: MR19=C0C, MR18=A3A3
6792 04:44:13.388604 CH1_RK1: MR19=0xC0C, MR18=0xA3A3, DQSOSC=389, MR23=63, INC=390, DEC=260
6793 04:44:13.393326 [RxdqsGatingPostProcess] freq 400
6794 04:44:13.399708 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6795 04:44:13.402323 Pre-setting of DQS Precalculation
6796 04:44:13.405028 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6797 04:44:13.412056 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6798 04:44:13.418470 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6799 04:44:13.419030
6800 04:44:13.422277
6801 04:44:13.422731 [Calibration Summary] 800 Mbps
6802 04:44:13.425096 CH 0, Rank 0
6803 04:44:13.425657 SW Impedance : PASS
6804 04:44:13.428803 DUTY Scan : NO K
6805 04:44:13.431572 ZQ Calibration : PASS
6806 04:44:13.432138 Jitter Meter : NO K
6807 04:44:13.436067 CBT Training : PASS
6808 04:44:13.438393 Write leveling : PASS
6809 04:44:13.439093 RX DQS gating : PASS
6810 04:44:13.441200 RX DQ/DQS(RDDQC) : PASS
6811 04:44:13.444546 TX DQ/DQS : PASS
6812 04:44:13.445033 RX DATLAT : PASS
6813 04:44:13.448073 RX DQ/DQS(Engine): PASS
6814 04:44:13.451307 TX OE : NO K
6815 04:44:13.451767 All Pass.
6816 04:44:13.452129
6817 04:44:13.452466 CH 0, Rank 1
6818 04:44:13.455052 SW Impedance : PASS
6819 04:44:13.457857 DUTY Scan : NO K
6820 04:44:13.458413 ZQ Calibration : PASS
6821 04:44:13.461615 Jitter Meter : NO K
6822 04:44:13.464985 CBT Training : PASS
6823 04:44:13.465535 Write leveling : NO K
6824 04:44:13.468019 RX DQS gating : PASS
6825 04:44:13.471850 RX DQ/DQS(RDDQC) : PASS
6826 04:44:13.472311 TX DQ/DQS : PASS
6827 04:44:13.474260 RX DATLAT : PASS
6828 04:44:13.474717 RX DQ/DQS(Engine): PASS
6829 04:44:13.478348 TX OE : NO K
6830 04:44:13.478900 All Pass.
6831 04:44:13.479261
6832 04:44:13.481325 CH 1, Rank 0
6833 04:44:13.481781 SW Impedance : PASS
6834 04:44:13.484139 DUTY Scan : NO K
6835 04:44:13.487411 ZQ Calibration : PASS
6836 04:44:13.487867 Jitter Meter : NO K
6837 04:44:13.490942 CBT Training : PASS
6838 04:44:13.494434 Write leveling : PASS
6839 04:44:13.494885 RX DQS gating : PASS
6840 04:44:13.498785 RX DQ/DQS(RDDQC) : PASS
6841 04:44:13.501195 TX DQ/DQS : PASS
6842 04:44:13.501657 RX DATLAT : PASS
6843 04:44:13.505214 RX DQ/DQS(Engine): PASS
6844 04:44:13.507731 TX OE : NO K
6845 04:44:13.508190 All Pass.
6846 04:44:13.508551
6847 04:44:13.508949 CH 1, Rank 1
6848 04:44:13.511718 SW Impedance : PASS
6849 04:44:13.515132 DUTY Scan : NO K
6850 04:44:13.515680 ZQ Calibration : PASS
6851 04:44:13.517915 Jitter Meter : NO K
6852 04:44:13.521095 CBT Training : PASS
6853 04:44:13.521645 Write leveling : NO K
6854 04:44:13.524572 RX DQS gating : PASS
6855 04:44:13.528038 RX DQ/DQS(RDDQC) : PASS
6856 04:44:13.528593 TX DQ/DQS : PASS
6857 04:44:13.531409 RX DATLAT : PASS
6858 04:44:13.531957 RX DQ/DQS(Engine): PASS
6859 04:44:13.534053 TX OE : NO K
6860 04:44:13.534631 All Pass.
6861 04:44:13.535014
6862 04:44:13.537439 DramC Write-DBI off
6863 04:44:13.541067 PER_BANK_REFRESH: Hybrid Mode
6864 04:44:13.541661 TX_TRACKING: ON
6865 04:44:13.551132 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6866 04:44:13.554380 [FAST_K] Save calibration result to emmc
6867 04:44:13.557954 dramc_set_vcore_voltage set vcore to 725000
6868 04:44:13.561515 Read voltage for 1600, 0
6869 04:44:13.561972 Vio18 = 0
6870 04:44:13.563930 Vcore = 725000
6871 04:44:13.564382 Vdram = 0
6872 04:44:13.564782 Vddq = 0
6873 04:44:13.565129 Vmddr = 0
6874 04:44:13.570558 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6875 04:44:13.577093 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6876 04:44:13.577593 MEM_TYPE=3, freq_sel=13
6877 04:44:13.580073 sv_algorithm_assistance_LP4_3733
6878 04:44:13.583801 ============ PULL DRAM RESETB DOWN ============
6879 04:44:13.590176 ========== PULL DRAM RESETB DOWN end =========
6880 04:44:13.593426 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6881 04:44:13.596930 ===================================
6882 04:44:13.600476 LPDDR4 DRAM CONFIGURATION
6883 04:44:13.603982 ===================================
6884 04:44:13.604548 EX_ROW_EN[0] = 0x0
6885 04:44:13.607532 EX_ROW_EN[1] = 0x0
6886 04:44:13.608085 LP4Y_EN = 0x0
6887 04:44:13.610217 WORK_FSP = 0x1
6888 04:44:13.613972 WL = 0x5
6889 04:44:13.614527 RL = 0x5
6890 04:44:13.616321 BL = 0x2
6891 04:44:13.616801 RPST = 0x0
6892 04:44:13.620413 RD_PRE = 0x0
6893 04:44:13.621014 WR_PRE = 0x1
6894 04:44:13.624076 WR_PST = 0x1
6895 04:44:13.624636 DBI_WR = 0x0
6896 04:44:13.627889 DBI_RD = 0x0
6897 04:44:13.628442 OTF = 0x1
6898 04:44:13.630071 ===================================
6899 04:44:13.633702 ===================================
6900 04:44:13.637202 ANA top config
6901 04:44:13.640215 ===================================
6902 04:44:13.640807 DLL_ASYNC_EN = 0
6903 04:44:13.642874 ALL_SLAVE_EN = 0
6904 04:44:13.646825 NEW_RANK_MODE = 1
6905 04:44:13.649742 DLL_IDLE_MODE = 1
6906 04:44:13.652836 LP45_APHY_COMB_EN = 1
6907 04:44:13.653381 TX_ODT_DIS = 0
6908 04:44:13.656750 NEW_8X_MODE = 1
6909 04:44:13.659625 ===================================
6910 04:44:13.662896 ===================================
6911 04:44:13.666610 data_rate = 3200
6912 04:44:13.669634 CKR = 1
6913 04:44:13.672837 DQ_P2S_RATIO = 8
6914 04:44:13.676131 ===================================
6915 04:44:13.676585 CA_P2S_RATIO = 8
6916 04:44:13.679485 DQ_CA_OPEN = 0
6917 04:44:13.682546 DQ_SEMI_OPEN = 0
6918 04:44:13.686723 CA_SEMI_OPEN = 0
6919 04:44:13.690560 CA_FULL_RATE = 0
6920 04:44:13.692931 DQ_CKDIV4_EN = 0
6921 04:44:13.693390 CA_CKDIV4_EN = 0
6922 04:44:13.696131 CA_PREDIV_EN = 0
6923 04:44:13.699630 PH8_DLY = 12
6924 04:44:13.702727 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6925 04:44:13.706029 DQ_AAMCK_DIV = 4
6926 04:44:13.709294 CA_AAMCK_DIV = 4
6927 04:44:13.713624 CA_ADMCK_DIV = 4
6928 04:44:13.714183 DQ_TRACK_CA_EN = 0
6929 04:44:13.715487 CA_PICK = 1600
6930 04:44:13.719389 CA_MCKIO = 1600
6931 04:44:13.723155 MCKIO_SEMI = 0
6932 04:44:13.725878 PLL_FREQ = 3068
6933 04:44:13.729167 DQ_UI_PI_RATIO = 32
6934 04:44:13.732797 CA_UI_PI_RATIO = 0
6935 04:44:13.735676 ===================================
6936 04:44:13.739384 ===================================
6937 04:44:13.739943 memory_type:LPDDR4
6938 04:44:13.742401 GP_NUM : 10
6939 04:44:13.746154 SRAM_EN : 1
6940 04:44:13.746728 MD32_EN : 0
6941 04:44:13.749053 ===================================
6942 04:44:13.751988 [ANA_INIT] >>>>>>>>>>>>>>
6943 04:44:13.755925 <<<<<< [CONFIGURE PHASE]: ANA_TX
6944 04:44:13.758738 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6945 04:44:13.762755 ===================================
6946 04:44:13.765667 data_rate = 3200,PCW = 0X7600
6947 04:44:13.769324 ===================================
6948 04:44:13.772168 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6949 04:44:13.776090 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6950 04:44:13.783047 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6951 04:44:13.785410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6952 04:44:13.789060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6953 04:44:13.792062 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6954 04:44:13.795396 [ANA_INIT] flow start
6955 04:44:13.798659 [ANA_INIT] PLL >>>>>>>>
6956 04:44:13.799221 [ANA_INIT] PLL <<<<<<<<
6957 04:44:13.801708 [ANA_INIT] MIDPI >>>>>>>>
6958 04:44:13.805493 [ANA_INIT] MIDPI <<<<<<<<
6959 04:44:13.808373 [ANA_INIT] DLL >>>>>>>>
6960 04:44:13.808875 [ANA_INIT] DLL <<<<<<<<
6961 04:44:13.811877 [ANA_INIT] flow end
6962 04:44:13.815894 ============ LP4 DIFF to SE enter ============
6963 04:44:13.818695 ============ LP4 DIFF to SE exit ============
6964 04:44:13.822094 [ANA_INIT] <<<<<<<<<<<<<
6965 04:44:13.825410 [Flow] Enable top DCM control >>>>>
6966 04:44:13.828792 [Flow] Enable top DCM control <<<<<
6967 04:44:13.831673 Enable DLL master slave shuffle
6968 04:44:13.838069 ==============================================================
6969 04:44:13.838625 Gating Mode config
6970 04:44:13.844890 ==============================================================
6971 04:44:13.845448 Config description:
6972 04:44:13.855210 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6973 04:44:13.861694 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6974 04:44:13.868127 SELPH_MODE 0: By rank 1: By Phase
6975 04:44:13.871602 ==============================================================
6976 04:44:13.874233 GAT_TRACK_EN = 1
6977 04:44:13.877927 RX_GATING_MODE = 2
6978 04:44:13.881159 RX_GATING_TRACK_MODE = 2
6979 04:44:13.884280 SELPH_MODE = 1
6980 04:44:13.887704 PICG_EARLY_EN = 1
6981 04:44:13.890955 VALID_LAT_VALUE = 1
6982 04:44:13.897874 ==============================================================
6983 04:44:13.901178 Enter into Gating configuration >>>>
6984 04:44:13.904225 Exit from Gating configuration <<<<
6985 04:44:13.907726 Enter into DVFS_PRE_config >>>>>
6986 04:44:13.917216 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6987 04:44:13.920736 Exit from DVFS_PRE_config <<<<<
6988 04:44:13.924876 Enter into PICG configuration >>>>
6989 04:44:13.927543 Exit from PICG configuration <<<<
6990 04:44:13.930687 [RX_INPUT] configuration >>>>>
6991 04:44:13.931239 [RX_INPUT] configuration <<<<<
6992 04:44:13.937648 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6993 04:44:13.943662 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6994 04:44:13.947169 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6995 04:44:13.954134 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6996 04:44:13.960228 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6997 04:44:13.967759 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6998 04:44:13.970809 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6999 04:44:13.973523 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7000 04:44:13.980354 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7001 04:44:13.984101 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7002 04:44:13.987006 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7003 04:44:13.993492 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7004 04:44:13.996392 ===================================
7005 04:44:13.996895 LPDDR4 DRAM CONFIGURATION
7006 04:44:14.000194 ===================================
7007 04:44:14.003566 EX_ROW_EN[0] = 0x0
7008 04:44:14.006757 EX_ROW_EN[1] = 0x0
7009 04:44:14.007311 LP4Y_EN = 0x0
7010 04:44:14.009823 WORK_FSP = 0x1
7011 04:44:14.010276 WL = 0x5
7012 04:44:14.013199 RL = 0x5
7013 04:44:14.013762 BL = 0x2
7014 04:44:14.016995 RPST = 0x0
7015 04:44:14.017452 RD_PRE = 0x0
7016 04:44:14.019976 WR_PRE = 0x1
7017 04:44:14.020531 WR_PST = 0x1
7018 04:44:14.023474 DBI_WR = 0x0
7019 04:44:14.024027 DBI_RD = 0x0
7020 04:44:14.026338 OTF = 0x1
7021 04:44:14.030715 ===================================
7022 04:44:14.033621 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7023 04:44:14.036254 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7024 04:44:14.042514 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7025 04:44:14.046410 ===================================
7026 04:44:14.046968 LPDDR4 DRAM CONFIGURATION
7027 04:44:14.049668 ===================================
7028 04:44:14.052596 EX_ROW_EN[0] = 0x10
7029 04:44:14.056269 EX_ROW_EN[1] = 0x0
7030 04:44:14.056867 LP4Y_EN = 0x0
7031 04:44:14.059674 WORK_FSP = 0x1
7032 04:44:14.060227 WL = 0x5
7033 04:44:14.062576 RL = 0x5
7034 04:44:14.063029 BL = 0x2
7035 04:44:14.065869 RPST = 0x0
7036 04:44:14.066323 RD_PRE = 0x0
7037 04:44:14.069589 WR_PRE = 0x1
7038 04:44:14.070049 WR_PST = 0x1
7039 04:44:14.072811 DBI_WR = 0x0
7040 04:44:14.073572 DBI_RD = 0x0
7041 04:44:14.075719 OTF = 0x1
7042 04:44:14.080129 ===================================
7043 04:44:14.086143 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7044 04:44:14.086699 ==
7045 04:44:14.089017 Dram Type= 6, Freq= 0, CH_0, rank 0
7046 04:44:14.092396 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7047 04:44:14.092965 ==
7048 04:44:14.096000 [Duty_Offset_Calibration]
7049 04:44:14.096572 B0:0 B1:2 CA:1
7050 04:44:14.097109
7051 04:44:14.098857 [DutyScan_Calibration_Flow] k_type=0
7052 04:44:14.109866
7053 04:44:14.110436 ==CLK 0==
7054 04:44:14.113084 Final CLK duty delay cell = 0
7055 04:44:14.116304 [0] MAX Duty = 5187%(X100), DQS PI = 24
7056 04:44:14.119515 [0] MIN Duty = 4938%(X100), DQS PI = 54
7057 04:44:14.119989 [0] AVG Duty = 5062%(X100)
7058 04:44:14.122590
7059 04:44:14.126135 CH0 CLK Duty spec in!! Max-Min= 249%
7060 04:44:14.129684 [DutyScan_Calibration_Flow] ====Done====
7061 04:44:14.130258
7062 04:44:14.132537 [DutyScan_Calibration_Flow] k_type=1
7063 04:44:14.150577
7064 04:44:14.151165 ==DQS 0 ==
7065 04:44:14.153187 Final DQS duty delay cell = 0
7066 04:44:14.156308 [0] MAX Duty = 5156%(X100), DQS PI = 34
7067 04:44:14.159521 [0] MIN Duty = 5031%(X100), DQS PI = 12
7068 04:44:14.162890 [0] AVG Duty = 5093%(X100)
7069 04:44:14.163465
7070 04:44:14.163952 ==DQS 1 ==
7071 04:44:14.166363 Final DQS duty delay cell = 0
7072 04:44:14.169482 [0] MAX Duty = 5031%(X100), DQS PI = 2
7073 04:44:14.172612 [0] MIN Duty = 4876%(X100), DQS PI = 16
7074 04:44:14.176264 [0] AVG Duty = 4953%(X100)
7075 04:44:14.176767
7076 04:44:14.179282 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7077 04:44:14.179756
7078 04:44:14.182991 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7079 04:44:14.186436 [DutyScan_Calibration_Flow] ====Done====
7080 04:44:14.187007
7081 04:44:14.189585 [DutyScan_Calibration_Flow] k_type=3
7082 04:44:14.207099
7083 04:44:14.207665 ==DQM 0 ==
7084 04:44:14.210123 Final DQM duty delay cell = 0
7085 04:44:14.214473 [0] MAX Duty = 5187%(X100), DQS PI = 22
7086 04:44:14.216765 [0] MIN Duty = 4907%(X100), DQS PI = 44
7087 04:44:14.220487 [0] AVG Duty = 5047%(X100)
7088 04:44:14.221090
7089 04:44:14.221458 ==DQM 1 ==
7090 04:44:14.224013 Final DQM duty delay cell = 0
7091 04:44:14.226655 [0] MAX Duty = 5000%(X100), DQS PI = 2
7092 04:44:14.230286 [0] MIN Duty = 4813%(X100), DQS PI = 12
7093 04:44:14.233489 [0] AVG Duty = 4906%(X100)
7094 04:44:14.234048
7095 04:44:14.237221 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7096 04:44:14.237677
7097 04:44:14.239976 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7098 04:44:14.243029 [DutyScan_Calibration_Flow] ====Done====
7099 04:44:14.243486
7100 04:44:14.246437 [DutyScan_Calibration_Flow] k_type=2
7101 04:44:14.263245
7102 04:44:14.263818 ==DQ 0 ==
7103 04:44:14.266386 Final DQ duty delay cell = 0
7104 04:44:14.269800 [0] MAX Duty = 5218%(X100), DQS PI = 18
7105 04:44:14.273261 [0] MIN Duty = 4938%(X100), DQS PI = 56
7106 04:44:14.273734 [0] AVG Duty = 5078%(X100)
7107 04:44:14.276072
7108 04:44:14.276537 ==DQ 1 ==
7109 04:44:14.279682 Final DQ duty delay cell = -4
7110 04:44:14.283703 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7111 04:44:14.286544 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7112 04:44:14.289565 [-4] AVG Duty = 4953%(X100)
7113 04:44:14.290037
7114 04:44:14.292639 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7115 04:44:14.293167
7116 04:44:14.295919 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7117 04:44:14.300052 [DutyScan_Calibration_Flow] ====Done====
7118 04:44:14.300524 ==
7119 04:44:14.302757 Dram Type= 6, Freq= 0, CH_1, rank 0
7120 04:44:14.307029 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7121 04:44:14.307607 ==
7122 04:44:14.309319 [Duty_Offset_Calibration]
7123 04:44:14.309791 B0:0 B1:4 CA:-5
7124 04:44:14.310274
7125 04:44:14.312782 [DutyScan_Calibration_Flow] k_type=0
7126 04:44:14.324197
7127 04:44:14.324801 ==CLK 0==
7128 04:44:14.327403 Final CLK duty delay cell = 0
7129 04:44:14.330370 [0] MAX Duty = 5156%(X100), DQS PI = 22
7130 04:44:14.334293 [0] MIN Duty = 4906%(X100), DQS PI = 52
7131 04:44:14.336590 [0] AVG Duty = 5031%(X100)
7132 04:44:14.337105
7133 04:44:14.340519 CH1 CLK Duty spec in!! Max-Min= 250%
7134 04:44:14.343684 [DutyScan_Calibration_Flow] ====Done====
7135 04:44:14.344247
7136 04:44:14.346592 [DutyScan_Calibration_Flow] k_type=1
7137 04:44:14.364244
7138 04:44:14.364896 ==DQS 0 ==
7139 04:44:14.366622 Final DQS duty delay cell = 0
7140 04:44:14.369415 [0] MAX Duty = 5156%(X100), DQS PI = 18
7141 04:44:14.373248 [0] MIN Duty = 4907%(X100), DQS PI = 42
7142 04:44:14.376369 [0] AVG Duty = 5031%(X100)
7143 04:44:14.376870
7144 04:44:14.377243 ==DQS 1 ==
7145 04:44:14.379401 Final DQS duty delay cell = -4
7146 04:44:14.382739 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7147 04:44:14.386097 [-4] MIN Duty = 4844%(X100), DQS PI = 42
7148 04:44:14.388818 [-4] AVG Duty = 4922%(X100)
7149 04:44:14.389383
7150 04:44:14.391990 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7151 04:44:14.392449
7152 04:44:14.395816 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7153 04:44:14.399522 [DutyScan_Calibration_Flow] ====Done====
7154 04:44:14.400087
7155 04:44:14.402172 [DutyScan_Calibration_Flow] k_type=3
7156 04:44:14.418584
7157 04:44:14.419149 ==DQM 0 ==
7158 04:44:14.421803 Final DQM duty delay cell = -4
7159 04:44:14.425090 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7160 04:44:14.428914 [-4] MIN Duty = 4751%(X100), DQS PI = 46
7161 04:44:14.432113 [-4] AVG Duty = 4922%(X100)
7162 04:44:14.432670
7163 04:44:14.433083 ==DQM 1 ==
7164 04:44:14.434985 Final DQM duty delay cell = -4
7165 04:44:14.438515 [-4] MAX Duty = 5062%(X100), DQS PI = 16
7166 04:44:14.441816 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7167 04:44:14.445420 [-4] AVG Duty = 4984%(X100)
7168 04:44:14.445992
7169 04:44:14.448636 CH1 DQM 0 Duty spec in!! Max-Min= 342%
7170 04:44:14.449248
7171 04:44:14.451441 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7172 04:44:14.456442 [DutyScan_Calibration_Flow] ====Done====
7173 04:44:14.457074
7174 04:44:14.458460 [DutyScan_Calibration_Flow] k_type=2
7175 04:44:14.476653
7176 04:44:14.477256 ==DQ 0 ==
7177 04:44:14.479565 Final DQ duty delay cell = 0
7178 04:44:14.482966 [0] MAX Duty = 5093%(X100), DQS PI = 4
7179 04:44:14.486222 [0] MIN Duty = 4938%(X100), DQS PI = 48
7180 04:44:14.486796 [0] AVG Duty = 5015%(X100)
7181 04:44:14.487286
7182 04:44:14.489564 ==DQ 1 ==
7183 04:44:14.493018 Final DQ duty delay cell = 0
7184 04:44:14.495801 [0] MAX Duty = 5031%(X100), DQS PI = 4
7185 04:44:14.499405 [0] MIN Duty = 4876%(X100), DQS PI = 30
7186 04:44:14.499988 [0] AVG Duty = 4953%(X100)
7187 04:44:14.500481
7188 04:44:14.502602 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7189 04:44:14.503077
7190 04:44:14.506621 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7191 04:44:14.512877 [DutyScan_Calibration_Flow] ====Done====
7192 04:44:14.516026 nWR fixed to 30
7193 04:44:14.516603 [ModeRegInit_LP4] CH0 RK0
7194 04:44:14.520345 [ModeRegInit_LP4] CH0 RK1
7195 04:44:14.522663 [ModeRegInit_LP4] CH1 RK0
7196 04:44:14.523254 [ModeRegInit_LP4] CH1 RK1
7197 04:44:14.526261 match AC timing 4
7198 04:44:14.529939 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7199 04:44:14.532647 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7200 04:44:14.539232 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7201 04:44:14.542559 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7202 04:44:14.549996 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7203 04:44:14.550573 [MiockJmeterHQA]
7204 04:44:14.551060
7205 04:44:14.552287 [DramcMiockJmeter] u1RxGatingPI = 0
7206 04:44:14.555905 0 : 4368, 4140
7207 04:44:14.556480 4 : 4363, 4137
7208 04:44:14.557025 8 : 4252, 4027
7209 04:44:14.559527 12 : 4362, 4137
7210 04:44:14.560004 16 : 4252, 4027
7211 04:44:14.562833 20 : 4253, 4026
7212 04:44:14.563415 24 : 4252, 4027
7213 04:44:14.565906 28 : 4363, 4137
7214 04:44:14.566492 32 : 4363, 4138
7215 04:44:14.569339 36 : 4252, 4027
7216 04:44:14.569919 40 : 4252, 4026
7217 04:44:14.570417 44 : 4252, 4027
7218 04:44:14.572666 48 : 4253, 4027
7219 04:44:14.573181 52 : 4255, 4029
7220 04:44:14.575975 56 : 4363, 4137
7221 04:44:14.576679 60 : 4252, 4027
7222 04:44:14.578612 64 : 4253, 4026
7223 04:44:14.579081 68 : 4249, 4027
7224 04:44:14.579451 72 : 4253, 4029
7225 04:44:14.582433 76 : 4250, 4027
7226 04:44:14.583013 80 : 4360, 4137
7227 04:44:14.586015 84 : 4360, 4138
7228 04:44:14.586583 88 : 4249, 4027
7229 04:44:14.588670 92 : 4250, 4026
7230 04:44:14.589192 96 : 4249, 4027
7231 04:44:14.592388 100 : 4249, 2367
7232 04:44:14.593051 104 : 4250, 0
7233 04:44:14.593437 108 : 4250, 0
7234 04:44:14.595317 112 : 4360, 0
7235 04:44:14.595779 116 : 4249, 0
7236 04:44:14.598890 120 : 4250, 0
7237 04:44:14.599463 124 : 4250, 0
7238 04:44:14.599836 128 : 4252, 0
7239 04:44:14.602293 132 : 4361, 0
7240 04:44:14.602859 136 : 4360, 0
7241 04:44:14.605316 140 : 4250, 0
7242 04:44:14.605778 144 : 4361, 0
7243 04:44:14.606148 148 : 4360, 0
7244 04:44:14.609004 152 : 4250, 0
7245 04:44:14.609471 156 : 4250, 0
7246 04:44:14.609843 160 : 4250, 0
7247 04:44:14.612016 164 : 4250, 0
7248 04:44:14.612585 168 : 4250, 0
7249 04:44:14.615425 172 : 4249, 0
7250 04:44:14.615989 176 : 4250, 0
7251 04:44:14.616361 180 : 4250, 0
7252 04:44:14.619603 184 : 4250, 0
7253 04:44:14.620190 188 : 4360, 0
7254 04:44:14.622603 192 : 4250, 0
7255 04:44:14.623167 196 : 4361, 0
7256 04:44:14.623539 200 : 4249, 0
7257 04:44:14.625389 204 : 4250, 0
7258 04:44:14.625852 208 : 4250, 0
7259 04:44:14.628511 212 : 4249, 0
7260 04:44:14.629112 216 : 4250, 0
7261 04:44:14.629485 220 : 4250, 788
7262 04:44:14.632175 224 : 4249, 4018
7263 04:44:14.632785 228 : 4250, 4027
7264 04:44:14.635429 232 : 4250, 4027
7265 04:44:14.636000 236 : 4250, 4026
7266 04:44:14.638647 240 : 4250, 4027
7267 04:44:14.639213 244 : 4249, 4027
7268 04:44:14.642465 248 : 4360, 4137
7269 04:44:14.643030 252 : 4250, 4026
7270 04:44:14.645285 256 : 4250, 4027
7271 04:44:14.645854 260 : 4361, 4137
7272 04:44:14.646226 264 : 4250, 4027
7273 04:44:14.648497 268 : 4249, 4027
7274 04:44:14.649105 272 : 4360, 4138
7275 04:44:14.652028 276 : 4250, 4027
7276 04:44:14.652594 280 : 4249, 4027
7277 04:44:14.655577 284 : 4250, 4026
7278 04:44:14.656144 288 : 4250, 4026
7279 04:44:14.659007 292 : 4250, 4027
7280 04:44:14.659586 296 : 4249, 4027
7281 04:44:14.661864 300 : 4362, 4137
7282 04:44:14.662325 304 : 4250, 4026
7283 04:44:14.665477 308 : 4250, 4027
7284 04:44:14.666040 312 : 4361, 4137
7285 04:44:14.668782 316 : 4249, 4027
7286 04:44:14.669356 320 : 4250, 4027
7287 04:44:14.671817 324 : 4361, 4137
7288 04:44:14.672376 328 : 4249, 4027
7289 04:44:14.672790 332 : 4250, 4027
7290 04:44:14.674849 336 : 4250, 3767
7291 04:44:14.675314 340 : 4250, 1864
7292 04:44:14.675682
7293 04:44:14.678525 MIOCK jitter meter ch=0
7294 04:44:14.678979
7295 04:44:14.682324 1T = (340-104) = 236 dly cells
7296 04:44:14.688382 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7297 04:44:14.689001 ==
7298 04:44:14.692430 Dram Type= 6, Freq= 0, CH_0, rank 0
7299 04:44:14.694836 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7300 04:44:14.695317 ==
7301 04:44:14.702273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7302 04:44:14.705254 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7303 04:44:14.708327 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7304 04:44:14.715133 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7305 04:44:14.723160 [CA 0] Center 42 (12~73) winsize 62
7306 04:44:14.726930 [CA 1] Center 42 (12~73) winsize 62
7307 04:44:14.729663 [CA 2] Center 39 (9~69) winsize 61
7308 04:44:14.732927 [CA 3] Center 38 (9~68) winsize 60
7309 04:44:14.736559 [CA 4] Center 37 (7~67) winsize 61
7310 04:44:14.740376 [CA 5] Center 36 (6~66) winsize 61
7311 04:44:14.740958
7312 04:44:14.742962 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7313 04:44:14.743513
7314 04:44:14.746114 [CATrainingPosCal] consider 1 rank data
7315 04:44:14.749635 u2DelayCellTimex100 = 275/100 ps
7316 04:44:14.756745 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7317 04:44:14.759882 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7318 04:44:14.762615 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7319 04:44:14.766368 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7320 04:44:14.770726 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7321 04:44:14.773117 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7322 04:44:14.773705
7323 04:44:14.776401 CA PerBit enable=1, Macro0, CA PI delay=36
7324 04:44:14.777035
7325 04:44:14.779095 [CBTSetCACLKResult] CA Dly = 36
7326 04:44:14.782794 CS Dly: 10 (0~41)
7327 04:44:14.786563 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7328 04:44:14.789872 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7329 04:44:14.790435 ==
7330 04:44:14.792450 Dram Type= 6, Freq= 0, CH_0, rank 1
7331 04:44:14.799316 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7332 04:44:14.799878 ==
7333 04:44:14.802629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7334 04:44:14.809206 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7335 04:44:14.812402 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7336 04:44:14.818922 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7337 04:44:14.825822 [CA 0] Center 42 (12~73) winsize 62
7338 04:44:14.829456 [CA 1] Center 41 (11~72) winsize 62
7339 04:44:14.832639 [CA 2] Center 38 (8~68) winsize 61
7340 04:44:14.835657 [CA 3] Center 37 (7~67) winsize 61
7341 04:44:14.838943 [CA 4] Center 35 (5~65) winsize 61
7342 04:44:14.842760 [CA 5] Center 35 (5~66) winsize 62
7343 04:44:14.843321
7344 04:44:14.846252 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7345 04:44:14.846703
7346 04:44:14.849074 [CATrainingPosCal] consider 2 rank data
7347 04:44:14.852678 u2DelayCellTimex100 = 275/100 ps
7348 04:44:14.856068 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7349 04:44:14.862204 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
7350 04:44:14.865854 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7351 04:44:14.868896 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7352 04:44:14.872327 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7353 04:44:14.875516 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7354 04:44:14.876068
7355 04:44:14.878978 CA PerBit enable=1, Macro0, CA PI delay=36
7356 04:44:14.879430
7357 04:44:14.882480 [CBTSetCACLKResult] CA Dly = 36
7358 04:44:14.885398 CS Dly: 11 (0~43)
7359 04:44:14.889030 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7360 04:44:14.892499 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7361 04:44:14.892990
7362 04:44:14.895497 ----->DramcWriteLeveling(PI) begin...
7363 04:44:14.895951 ==
7364 04:44:14.899302 Dram Type= 6, Freq= 0, CH_0, rank 0
7365 04:44:14.905761 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7366 04:44:14.906211 ==
7367 04:44:14.908819 Write leveling (Byte 0): 28 => 28
7368 04:44:14.909272 Write leveling (Byte 1): 26 => 26
7369 04:44:14.912450 DramcWriteLeveling(PI) end<-----
7370 04:44:14.913056
7371 04:44:14.915612 ==
7372 04:44:14.916161 Dram Type= 6, Freq= 0, CH_0, rank 0
7373 04:44:14.921708 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7374 04:44:14.922397 ==
7375 04:44:14.924903 [Gating] SW mode calibration
7376 04:44:14.932315 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7377 04:44:14.934803 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7378 04:44:14.941572 0 12 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7379 04:44:14.945023 0 12 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7380 04:44:14.948818 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7381 04:44:14.955038 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7382 04:44:14.959266 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7383 04:44:14.961968 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7384 04:44:14.968293 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7385 04:44:14.972042 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7386 04:44:14.974996 0 13 0 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (1 0)
7387 04:44:14.981471 0 13 4 | B1->B0 | 3434 2525 | 0 0 | (0 1) (1 0)
7388 04:44:14.985686 0 13 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7389 04:44:14.988514 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7390 04:44:14.995047 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7391 04:44:14.998631 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7392 04:44:15.001391 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7393 04:44:15.008148 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7394 04:44:15.011441 0 14 0 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7395 04:44:15.015322 0 14 4 | B1->B0 | 3131 4545 | 0 0 | (0 0) (0 0)
7396 04:44:15.018075 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7397 04:44:15.024561 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7398 04:44:15.028069 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7399 04:44:15.032250 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7400 04:44:15.037752 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7401 04:44:15.041651 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7402 04:44:15.044789 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7403 04:44:15.051956 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7404 04:44:15.054424 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7405 04:44:15.057878 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7406 04:44:15.064793 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7407 04:44:15.067819 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7408 04:44:15.071949 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7409 04:44:15.077734 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7410 04:44:15.081378 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7411 04:44:15.084988 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7412 04:44:15.091239 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 04:44:15.095098 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7414 04:44:15.098009 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7415 04:44:15.106340 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7416 04:44:15.107759 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7417 04:44:15.111676 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7418 04:44:15.118826 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7419 04:44:15.121040 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7420 04:44:15.124862 Total UI for P1: 0, mck2ui 16
7421 04:44:15.127952 best dqsien dly found for B0: ( 1, 1, 2)
7422 04:44:15.131737 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7423 04:44:15.135307 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7424 04:44:15.137820 Total UI for P1: 0, mck2ui 16
7425 04:44:15.141615 best dqsien dly found for B1: ( 1, 1, 6)
7426 04:44:15.145623 best DQS0 dly(MCK, UI, PI) = (1, 1, 2)
7427 04:44:15.151101 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7428 04:44:15.151666
7429 04:44:15.154229 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 2)
7430 04:44:15.158150 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7431 04:44:15.160778 [Gating] SW calibration Done
7432 04:44:15.161343 ==
7433 04:44:15.164165 Dram Type= 6, Freq= 0, CH_0, rank 0
7434 04:44:15.167423 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7435 04:44:15.167989 ==
7436 04:44:15.168362 RX Vref Scan: 0
7437 04:44:15.170849
7438 04:44:15.171407 RX Vref 0 -> 0, step: 1
7439 04:44:15.171781
7440 04:44:15.174235 RX Delay 0 -> 252, step: 8
7441 04:44:15.177212 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7442 04:44:15.180186 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7443 04:44:15.186982 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7444 04:44:15.190527 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7445 04:44:15.193558 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7446 04:44:15.197074 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7447 04:44:15.200369 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7448 04:44:15.206702 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
7449 04:44:15.210963 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7450 04:44:15.213740 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7451 04:44:15.217406 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7452 04:44:15.220235 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7453 04:44:15.228385 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7454 04:44:15.230319 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7455 04:44:15.233734 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7456 04:44:15.237110 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7457 04:44:15.237685 ==
7458 04:44:15.240010 Dram Type= 6, Freq= 0, CH_0, rank 0
7459 04:44:15.246526 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7460 04:44:15.247197 ==
7461 04:44:15.247571 DQS Delay:
7462 04:44:15.251228 DQS0 = 0, DQS1 = 0
7463 04:44:15.251852 DQM Delay:
7464 04:44:15.254000 DQM0 = 130, DQM1 = 124
7465 04:44:15.254455 DQ Delay:
7466 04:44:15.256887 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7467 04:44:15.260098 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7468 04:44:15.263719 DQ8 =115, DQ9 =107, DQ10 =119, DQ11 =115
7469 04:44:15.266490 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7470 04:44:15.267049
7471 04:44:15.267415
7472 04:44:15.267747 ==
7473 04:44:15.269915 Dram Type= 6, Freq= 0, CH_0, rank 0
7474 04:44:15.276307 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7475 04:44:15.276941 ==
7476 04:44:15.277339
7477 04:44:15.277676
7478 04:44:15.277994 TX Vref Scan disable
7479 04:44:15.280270 == TX Byte 0 ==
7480 04:44:15.282729 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7481 04:44:15.290328 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7482 04:44:15.290882 == TX Byte 1 ==
7483 04:44:15.293068 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7484 04:44:15.299674 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7485 04:44:15.300293 ==
7486 04:44:15.303289 Dram Type= 6, Freq= 0, CH_0, rank 0
7487 04:44:15.306330 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7488 04:44:15.306786 ==
7489 04:44:15.318852
7490 04:44:15.321805 TX Vref early break, caculate TX vref
7491 04:44:15.326268 TX Vref=16, minBit 8, minWin=21, winSum=374
7492 04:44:15.328817 TX Vref=18, minBit 9, minWin=22, winSum=383
7493 04:44:15.332025 TX Vref=20, minBit 8, minWin=23, winSum=391
7494 04:44:15.335399 TX Vref=22, minBit 8, minWin=23, winSum=396
7495 04:44:15.338960 TX Vref=24, minBit 9, minWin=24, winSum=410
7496 04:44:15.345369 TX Vref=26, minBit 8, minWin=25, winSum=414
7497 04:44:15.349590 TX Vref=28, minBit 8, minWin=24, winSum=415
7498 04:44:15.351574 TX Vref=30, minBit 1, minWin=25, winSum=413
7499 04:44:15.355738 TX Vref=32, minBit 6, minWin=24, winSum=399
7500 04:44:15.359080 TX Vref=34, minBit 8, minWin=23, winSum=393
7501 04:44:15.365078 [TxChooseVref] Worse bit 8, Min win 25, Win sum 414, Final Vref 26
7502 04:44:15.365634
7503 04:44:15.368555 Final TX Range 0 Vref 26
7504 04:44:15.369257
7505 04:44:15.369624 ==
7506 04:44:15.371843 Dram Type= 6, Freq= 0, CH_0, rank 0
7507 04:44:15.375326 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7508 04:44:15.375782 ==
7509 04:44:15.376140
7510 04:44:15.376469
7511 04:44:15.377854 TX Vref Scan disable
7512 04:44:15.384876 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7513 04:44:15.385332 == TX Byte 0 ==
7514 04:44:15.388055 u2DelayCellOfst[0]=14 cells (4 PI)
7515 04:44:15.391335 u2DelayCellOfst[1]=21 cells (6 PI)
7516 04:44:15.394924 u2DelayCellOfst[2]=17 cells (5 PI)
7517 04:44:15.398159 u2DelayCellOfst[3]=14 cells (4 PI)
7518 04:44:15.401929 u2DelayCellOfst[4]=10 cells (3 PI)
7519 04:44:15.404661 u2DelayCellOfst[5]=0 cells (0 PI)
7520 04:44:15.408122 u2DelayCellOfst[6]=21 cells (6 PI)
7521 04:44:15.412128 u2DelayCellOfst[7]=17 cells (5 PI)
7522 04:44:15.414721 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7523 04:44:15.417907 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7524 04:44:15.422136 == TX Byte 1 ==
7525 04:44:15.424963 u2DelayCellOfst[8]=3 cells (1 PI)
7526 04:44:15.425522 u2DelayCellOfst[9]=0 cells (0 PI)
7527 04:44:15.427964 u2DelayCellOfst[10]=10 cells (3 PI)
7528 04:44:15.431779 u2DelayCellOfst[11]=3 cells (1 PI)
7529 04:44:15.434676 u2DelayCellOfst[12]=17 cells (5 PI)
7530 04:44:15.438531 u2DelayCellOfst[13]=14 cells (4 PI)
7531 04:44:15.441388 u2DelayCellOfst[14]=21 cells (6 PI)
7532 04:44:15.444695 u2DelayCellOfst[15]=17 cells (5 PI)
7533 04:44:15.447848 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7534 04:44:15.454446 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7535 04:44:15.455022 DramC Write-DBI on
7536 04:44:15.455390 ==
7537 04:44:15.457604 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 04:44:15.464528 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7539 04:44:15.465141 ==
7540 04:44:15.465509
7541 04:44:15.465843
7542 04:44:15.466159 TX Vref Scan disable
7543 04:44:15.468779 == TX Byte 0 ==
7544 04:44:15.471590 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7545 04:44:15.474481 == TX Byte 1 ==
7546 04:44:15.478175 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7547 04:44:15.481490 DramC Write-DBI off
7548 04:44:15.481960
7549 04:44:15.482321 [DATLAT]
7550 04:44:15.482658 Freq=1600, CH0 RK0
7551 04:44:15.482988
7552 04:44:15.485283 DATLAT Default: 0xf
7553 04:44:15.485737 0, 0xFFFF, sum = 0
7554 04:44:15.488369 1, 0xFFFF, sum = 0
7555 04:44:15.492016 2, 0xFFFF, sum = 0
7556 04:44:15.492578 3, 0xFFFF, sum = 0
7557 04:44:15.494660 4, 0xFFFF, sum = 0
7558 04:44:15.495221 5, 0xFFFF, sum = 0
7559 04:44:15.497752 6, 0xFFFF, sum = 0
7560 04:44:15.498218 7, 0xFFFF, sum = 0
7561 04:44:15.501445 8, 0xFFFF, sum = 0
7562 04:44:15.501908 9, 0xFFFF, sum = 0
7563 04:44:15.505218 10, 0xFFFF, sum = 0
7564 04:44:15.505682 11, 0xFFFF, sum = 0
7565 04:44:15.508403 12, 0xFFF, sum = 0
7566 04:44:15.509016 13, 0x0, sum = 1
7567 04:44:15.511715 14, 0x0, sum = 2
7568 04:44:15.512269 15, 0x0, sum = 3
7569 04:44:15.514934 16, 0x0, sum = 4
7570 04:44:15.515490 best_step = 14
7571 04:44:15.515852
7572 04:44:15.516185 ==
7573 04:44:15.518303 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 04:44:15.522352 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7575 04:44:15.522813 ==
7576 04:44:15.524877 RX Vref Scan: 1
7577 04:44:15.525333
7578 04:44:15.528528 Set Vref Range= 24 -> 127
7579 04:44:15.529142
7580 04:44:15.529508 RX Vref 24 -> 127, step: 1
7581 04:44:15.531857
7582 04:44:15.532417 RX Delay 11 -> 252, step: 4
7583 04:44:15.532856
7584 04:44:15.535303 Set Vref, RX VrefLevel [Byte0]: 24
7585 04:44:15.538225 [Byte1]: 24
7586 04:44:15.541423
7587 04:44:15.541878 Set Vref, RX VrefLevel [Byte0]: 25
7588 04:44:15.545389 [Byte1]: 25
7589 04:44:15.549063
7590 04:44:15.549609 Set Vref, RX VrefLevel [Byte0]: 26
7591 04:44:15.552988 [Byte1]: 26
7592 04:44:15.557509
7593 04:44:15.558059 Set Vref, RX VrefLevel [Byte0]: 27
7594 04:44:15.560121 [Byte1]: 27
7595 04:44:15.564226
7596 04:44:15.564812 Set Vref, RX VrefLevel [Byte0]: 28
7597 04:44:15.568114 [Byte1]: 28
7598 04:44:15.572162
7599 04:44:15.572751 Set Vref, RX VrefLevel [Byte0]: 29
7600 04:44:15.576178 [Byte1]: 29
7601 04:44:15.580165
7602 04:44:15.580758 Set Vref, RX VrefLevel [Byte0]: 30
7603 04:44:15.582469 [Byte1]: 30
7604 04:44:15.587225
7605 04:44:15.587712 Set Vref, RX VrefLevel [Byte0]: 31
7606 04:44:15.590891 [Byte1]: 31
7607 04:44:15.595150
7608 04:44:15.595703 Set Vref, RX VrefLevel [Byte0]: 32
7609 04:44:15.598789 [Byte1]: 32
7610 04:44:15.602815
7611 04:44:15.603363 Set Vref, RX VrefLevel [Byte0]: 33
7612 04:44:15.605600 [Byte1]: 33
7613 04:44:15.610280
7614 04:44:15.610839 Set Vref, RX VrefLevel [Byte0]: 34
7615 04:44:15.613253 [Byte1]: 34
7616 04:44:15.617693
7617 04:44:15.618234 Set Vref, RX VrefLevel [Byte0]: 35
7618 04:44:15.621258 [Byte1]: 35
7619 04:44:15.625644
7620 04:44:15.626189 Set Vref, RX VrefLevel [Byte0]: 36
7621 04:44:15.628373 [Byte1]: 36
7622 04:44:15.632514
7623 04:44:15.633064 Set Vref, RX VrefLevel [Byte0]: 37
7624 04:44:15.636235 [Byte1]: 37
7625 04:44:15.640323
7626 04:44:15.640851 Set Vref, RX VrefLevel [Byte0]: 38
7627 04:44:15.644153 [Byte1]: 38
7628 04:44:15.648168
7629 04:44:15.648776 Set Vref, RX VrefLevel [Byte0]: 39
7630 04:44:15.651426 [Byte1]: 39
7631 04:44:15.656190
7632 04:44:15.656653 Set Vref, RX VrefLevel [Byte0]: 40
7633 04:44:15.659890 [Byte1]: 40
7634 04:44:15.663829
7635 04:44:15.664382 Set Vref, RX VrefLevel [Byte0]: 41
7636 04:44:15.666456 [Byte1]: 41
7637 04:44:15.671303
7638 04:44:15.671853 Set Vref, RX VrefLevel [Byte0]: 42
7639 04:44:15.674697 [Byte1]: 42
7640 04:44:15.678722
7641 04:44:15.679271 Set Vref, RX VrefLevel [Byte0]: 43
7642 04:44:15.682379 [Byte1]: 43
7643 04:44:15.686145
7644 04:44:15.686603 Set Vref, RX VrefLevel [Byte0]: 44
7645 04:44:15.690001 [Byte1]: 44
7646 04:44:15.694294
7647 04:44:15.694842 Set Vref, RX VrefLevel [Byte0]: 45
7648 04:44:15.697166 [Byte1]: 45
7649 04:44:15.701244
7650 04:44:15.701795 Set Vref, RX VrefLevel [Byte0]: 46
7651 04:44:15.705525 [Byte1]: 46
7652 04:44:15.709460
7653 04:44:15.710017 Set Vref, RX VrefLevel [Byte0]: 47
7654 04:44:15.712688 [Byte1]: 47
7655 04:44:15.716588
7656 04:44:15.717197 Set Vref, RX VrefLevel [Byte0]: 48
7657 04:44:15.719841 [Byte1]: 48
7658 04:44:15.724450
7659 04:44:15.725113 Set Vref, RX VrefLevel [Byte0]: 49
7660 04:44:15.727286 [Byte1]: 49
7661 04:44:15.732146
7662 04:44:15.732810 Set Vref, RX VrefLevel [Byte0]: 50
7663 04:44:15.735176 [Byte1]: 50
7664 04:44:15.740862
7665 04:44:15.741408 Set Vref, RX VrefLevel [Byte0]: 51
7666 04:44:15.742501 [Byte1]: 51
7667 04:44:15.747015
7668 04:44:15.747569 Set Vref, RX VrefLevel [Byte0]: 52
7669 04:44:15.751267 [Byte1]: 52
7670 04:44:15.754230
7671 04:44:15.754689 Set Vref, RX VrefLevel [Byte0]: 53
7672 04:44:15.758396 [Byte1]: 53
7673 04:44:15.762585
7674 04:44:15.763137 Set Vref, RX VrefLevel [Byte0]: 54
7675 04:44:15.765488 [Byte1]: 54
7676 04:44:15.770431
7677 04:44:15.770995 Set Vref, RX VrefLevel [Byte0]: 55
7678 04:44:15.773513 [Byte1]: 55
7679 04:44:15.777458
7680 04:44:15.778008 Set Vref, RX VrefLevel [Byte0]: 56
7681 04:44:15.780858 [Byte1]: 56
7682 04:44:15.785960
7683 04:44:15.786418 Set Vref, RX VrefLevel [Byte0]: 57
7684 04:44:15.788503 [Byte1]: 57
7685 04:44:15.795541
7686 04:44:15.796148 Set Vref, RX VrefLevel [Byte0]: 58
7687 04:44:15.796962 [Byte1]: 58
7688 04:44:15.800557
7689 04:44:15.801186 Set Vref, RX VrefLevel [Byte0]: 59
7690 04:44:15.803545 [Byte1]: 59
7691 04:44:15.808257
7692 04:44:15.808761 Set Vref, RX VrefLevel [Byte0]: 60
7693 04:44:15.811787 [Byte1]: 60
7694 04:44:15.816078
7695 04:44:15.816651 Set Vref, RX VrefLevel [Byte0]: 61
7696 04:44:15.818820 [Byte1]: 61
7697 04:44:15.823109
7698 04:44:15.823945 Set Vref, RX VrefLevel [Byte0]: 62
7699 04:44:15.826865 [Byte1]: 62
7700 04:44:15.831239
7701 04:44:15.831811 Set Vref, RX VrefLevel [Byte0]: 63
7702 04:44:15.833688 [Byte1]: 63
7703 04:44:15.838572
7704 04:44:15.839126 Set Vref, RX VrefLevel [Byte0]: 64
7705 04:44:15.841468 [Byte1]: 64
7706 04:44:15.845794
7707 04:44:15.846350 Set Vref, RX VrefLevel [Byte0]: 65
7708 04:44:15.849633 [Byte1]: 65
7709 04:44:15.853699
7710 04:44:15.854248 Set Vref, RX VrefLevel [Byte0]: 66
7711 04:44:15.856634 [Byte1]: 66
7712 04:44:15.861169
7713 04:44:15.861715 Set Vref, RX VrefLevel [Byte0]: 67
7714 04:44:15.865075 [Byte1]: 67
7715 04:44:15.868558
7716 04:44:15.869151 Set Vref, RX VrefLevel [Byte0]: 68
7717 04:44:15.871922 [Byte1]: 68
7718 04:44:15.876400
7719 04:44:15.877022 Set Vref, RX VrefLevel [Byte0]: 69
7720 04:44:15.880141 [Byte1]: 69
7721 04:44:15.884020
7722 04:44:15.884474 Set Vref, RX VrefLevel [Byte0]: 70
7723 04:44:15.887080 [Byte1]: 70
7724 04:44:15.892060
7725 04:44:15.892608 Set Vref, RX VrefLevel [Byte0]: 71
7726 04:44:15.894909 [Byte1]: 71
7727 04:44:15.900427
7728 04:44:15.901054 Set Vref, RX VrefLevel [Byte0]: 72
7729 04:44:15.902946 [Byte1]: 72
7730 04:44:15.906747
7731 04:44:15.907205 Final RX Vref Byte 0 = 53 to rank0
7732 04:44:15.910369 Final RX Vref Byte 1 = 56 to rank0
7733 04:44:15.913739 Final RX Vref Byte 0 = 53 to rank1
7734 04:44:15.916951 Final RX Vref Byte 1 = 56 to rank1==
7735 04:44:15.920561 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 04:44:15.927172 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7737 04:44:15.927731 ==
7738 04:44:15.928099 DQS Delay:
7739 04:44:15.928437 DQS0 = 0, DQS1 = 0
7740 04:44:15.931042 DQM Delay:
7741 04:44:15.931496 DQM0 = 127, DQM1 = 121
7742 04:44:15.933907 DQ Delay:
7743 04:44:15.936570 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =124
7744 04:44:15.939899 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7745 04:44:15.943237 DQ8 =110, DQ9 =104, DQ10 =122, DQ11 =112
7746 04:44:15.946742 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7747 04:44:15.947294
7748 04:44:15.947656
7749 04:44:15.947993
7750 04:44:15.949842 [DramC_TX_OE_Calibration] TA2
7751 04:44:15.953687 Original DQ_B0 (3 6) =30, OEN = 27
7752 04:44:15.956601 Original DQ_B1 (3 6) =30, OEN = 27
7753 04:44:15.960558 24, 0x0, End_B0=24 End_B1=24
7754 04:44:15.961158 25, 0x0, End_B0=25 End_B1=25
7755 04:44:15.963244 26, 0x0, End_B0=26 End_B1=26
7756 04:44:15.966942 27, 0x0, End_B0=27 End_B1=27
7757 04:44:15.970001 28, 0x0, End_B0=28 End_B1=28
7758 04:44:15.973558 29, 0x0, End_B0=29 End_B1=29
7759 04:44:15.974114 30, 0x0, End_B0=30 End_B1=30
7760 04:44:15.977073 31, 0x4141, End_B0=30 End_B1=30
7761 04:44:15.980017 Byte0 end_step=30 best_step=27
7762 04:44:15.983167 Byte1 end_step=30 best_step=27
7763 04:44:15.987128 Byte0 TX OE(2T, 0.5T) = (3, 3)
7764 04:44:15.989525 Byte1 TX OE(2T, 0.5T) = (3, 3)
7765 04:44:15.989997
7766 04:44:15.990470
7767 04:44:15.997091 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7768 04:44:16.000500 CH0 RK0: MR19=303, MR18=1C1C
7769 04:44:16.007371 CH0_RK0: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
7770 04:44:16.007928
7771 04:44:16.009116 ----->DramcWriteLeveling(PI) begin...
7772 04:44:16.009595 ==
7773 04:44:16.012897 Dram Type= 6, Freq= 0, CH_0, rank 1
7774 04:44:16.016246 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7775 04:44:16.016863 ==
7776 04:44:16.020684 Write leveling (Byte 0): 28 => 28
7777 04:44:16.023175 Write leveling (Byte 1): 28 => 28
7778 04:44:16.026065 DramcWriteLeveling(PI) end<-----
7779 04:44:16.026537
7780 04:44:16.027012 ==
7781 04:44:16.029404 Dram Type= 6, Freq= 0, CH_0, rank 1
7782 04:44:16.032233 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7783 04:44:16.032743 ==
7784 04:44:16.036305 [Gating] SW mode calibration
7785 04:44:16.042836 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7786 04:44:16.049093 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7787 04:44:16.052495 0 12 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7788 04:44:16.059237 0 12 4 | B1->B0 | 2323 3434 | 0 1 | (1 1) (1 1)
7789 04:44:16.062711 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7790 04:44:16.065585 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7791 04:44:16.072638 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7792 04:44:16.075199 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7793 04:44:16.079218 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7794 04:44:16.085017 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7795 04:44:16.088428 0 13 0 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
7796 04:44:16.092027 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
7797 04:44:16.098440 0 13 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7798 04:44:16.102659 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7799 04:44:16.105487 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7800 04:44:16.112877 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7801 04:44:16.114969 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7802 04:44:16.118363 0 13 28 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7803 04:44:16.125226 0 14 0 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7804 04:44:16.128872 0 14 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7805 04:44:16.131712 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7806 04:44:16.138230 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7807 04:44:16.142415 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7808 04:44:16.145146 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7809 04:44:16.151582 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7810 04:44:16.155814 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7811 04:44:16.158254 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7812 04:44:16.164752 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7813 04:44:16.168410 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7814 04:44:16.171142 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7815 04:44:16.175048 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7816 04:44:16.182213 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7817 04:44:16.185580 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7818 04:44:16.191493 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7819 04:44:16.194731 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7820 04:44:16.198092 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7821 04:44:16.204569 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7822 04:44:16.208231 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7823 04:44:16.211155 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 04:44:16.215237 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7825 04:44:16.221137 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7826 04:44:16.224289 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7827 04:44:16.227393 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7828 04:44:16.234113 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7829 04:44:16.237529 Total UI for P1: 0, mck2ui 16
7830 04:44:16.240769 best dqsien dly found for B0: ( 1, 0, 30)
7831 04:44:16.243998 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7832 04:44:16.247627 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7833 04:44:16.251027 Total UI for P1: 0, mck2ui 16
7834 04:44:16.254682 best dqsien dly found for B1: ( 1, 1, 4)
7835 04:44:16.257052 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7836 04:44:16.260946 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7837 04:44:16.261496
7838 04:44:16.267072 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7839 04:44:16.270704 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7840 04:44:16.273876 [Gating] SW calibration Done
7841 04:44:16.274416 ==
7842 04:44:16.276933 Dram Type= 6, Freq= 0, CH_0, rank 1
7843 04:44:16.280641 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7844 04:44:16.281242 ==
7845 04:44:16.281613 RX Vref Scan: 0
7846 04:44:16.281958
7847 04:44:16.283669 RX Vref 0 -> 0, step: 1
7848 04:44:16.284124
7849 04:44:16.287864 RX Delay 0 -> 252, step: 8
7850 04:44:16.290777 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7851 04:44:16.294007 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7852 04:44:16.300436 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7853 04:44:16.303650 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7854 04:44:16.307409 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7855 04:44:16.310723 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7856 04:44:16.313734 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7857 04:44:16.321381 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7858 04:44:16.323821 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7859 04:44:16.326865 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7860 04:44:16.330638 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7861 04:44:16.333424 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7862 04:44:16.340648 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7863 04:44:16.343510 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7864 04:44:16.346832 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7865 04:44:16.351431 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7866 04:44:16.351989 ==
7867 04:44:16.353210 Dram Type= 6, Freq= 0, CH_0, rank 1
7868 04:44:16.360021 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7869 04:44:16.360579 ==
7870 04:44:16.361007 DQS Delay:
7871 04:44:16.361352 DQS0 = 0, DQS1 = 0
7872 04:44:16.363009 DQM Delay:
7873 04:44:16.363464 DQM0 = 131, DQM1 = 124
7874 04:44:16.366469 DQ Delay:
7875 04:44:16.370681 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
7876 04:44:16.373653 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7877 04:44:16.376960 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7878 04:44:16.380230 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7879 04:44:16.380826
7880 04:44:16.381202
7881 04:44:16.381537 ==
7882 04:44:16.383003 Dram Type= 6, Freq= 0, CH_0, rank 1
7883 04:44:16.386249 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7884 04:44:16.389614 ==
7885 04:44:16.390083
7886 04:44:16.390562
7887 04:44:16.391012 TX Vref Scan disable
7888 04:44:16.393091 == TX Byte 0 ==
7889 04:44:16.396426 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7890 04:44:16.400155 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7891 04:44:16.403007 == TX Byte 1 ==
7892 04:44:16.407433 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7893 04:44:16.409956 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7894 04:44:16.410527 ==
7895 04:44:16.413318 Dram Type= 6, Freq= 0, CH_0, rank 1
7896 04:44:16.419585 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7897 04:44:16.420070 ==
7898 04:44:16.433311
7899 04:44:16.436324 TX Vref early break, caculate TX vref
7900 04:44:16.439208 TX Vref=16, minBit 1, minWin=22, winSum=384
7901 04:44:16.442801 TX Vref=18, minBit 1, minWin=23, winSum=390
7902 04:44:16.445842 TX Vref=20, minBit 1, minWin=24, winSum=400
7903 04:44:16.448812 TX Vref=22, minBit 1, minWin=23, winSum=402
7904 04:44:16.453028 TX Vref=24, minBit 1, minWin=24, winSum=414
7905 04:44:16.458813 TX Vref=26, minBit 2, minWin=25, winSum=421
7906 04:44:16.462318 TX Vref=28, minBit 8, minWin=25, winSum=420
7907 04:44:16.465767 TX Vref=30, minBit 6, minWin=25, winSum=416
7908 04:44:16.468826 TX Vref=32, minBit 8, minWin=24, winSum=407
7909 04:44:16.471879 TX Vref=34, minBit 0, minWin=24, winSum=403
7910 04:44:16.475595 TX Vref=36, minBit 1, minWin=23, winSum=388
7911 04:44:16.481913 [TxChooseVref] Worse bit 2, Min win 25, Win sum 421, Final Vref 26
7912 04:44:16.482466
7913 04:44:16.485656 Final TX Range 0 Vref 26
7914 04:44:16.486110
7915 04:44:16.486471 ==
7916 04:44:16.488302 Dram Type= 6, Freq= 0, CH_0, rank 1
7917 04:44:16.492677 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7918 04:44:16.493306 ==
7919 04:44:16.495575
7920 04:44:16.496023
7921 04:44:16.496378 TX Vref Scan disable
7922 04:44:16.501938 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7923 04:44:16.502496 == TX Byte 0 ==
7924 04:44:16.505042 u2DelayCellOfst[0]=14 cells (4 PI)
7925 04:44:16.509067 u2DelayCellOfst[1]=17 cells (5 PI)
7926 04:44:16.511417 u2DelayCellOfst[2]=14 cells (4 PI)
7927 04:44:16.514973 u2DelayCellOfst[3]=14 cells (4 PI)
7928 04:44:16.519335 u2DelayCellOfst[4]=10 cells (3 PI)
7929 04:44:16.521286 u2DelayCellOfst[5]=0 cells (0 PI)
7930 04:44:16.524772 u2DelayCellOfst[6]=17 cells (5 PI)
7931 04:44:16.528894 u2DelayCellOfst[7]=17 cells (5 PI)
7932 04:44:16.531660 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7933 04:44:16.535899 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7934 04:44:16.538234 == TX Byte 1 ==
7935 04:44:16.541394 u2DelayCellOfst[8]=3 cells (1 PI)
7936 04:44:16.545145 u2DelayCellOfst[9]=0 cells (0 PI)
7937 04:44:16.548050 u2DelayCellOfst[10]=10 cells (3 PI)
7938 04:44:16.551765 u2DelayCellOfst[11]=7 cells (2 PI)
7939 04:44:16.554905 u2DelayCellOfst[12]=14 cells (4 PI)
7940 04:44:16.557733 u2DelayCellOfst[13]=17 cells (5 PI)
7941 04:44:16.558185 u2DelayCellOfst[14]=17 cells (5 PI)
7942 04:44:16.561672 u2DelayCellOfst[15]=14 cells (4 PI)
7943 04:44:16.568010 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7944 04:44:16.571808 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7945 04:44:16.574898 DramC Write-DBI on
7946 04:44:16.575473 ==
7947 04:44:16.578489 Dram Type= 6, Freq= 0, CH_0, rank 1
7948 04:44:16.581137 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7949 04:44:16.581689 ==
7950 04:44:16.582051
7951 04:44:16.582383
7952 04:44:16.584545 TX Vref Scan disable
7953 04:44:16.585229 == TX Byte 0 ==
7954 04:44:16.591296 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7955 04:44:16.591773 == TX Byte 1 ==
7956 04:44:16.593969 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7957 04:44:16.597717 DramC Write-DBI off
7958 04:44:16.598271
7959 04:44:16.598750 [DATLAT]
7960 04:44:16.600686 Freq=1600, CH0 RK1
7961 04:44:16.601195
7962 04:44:16.601676 DATLAT Default: 0xe
7963 04:44:16.603907 0, 0xFFFF, sum = 0
7964 04:44:16.604388 1, 0xFFFF, sum = 0
7965 04:44:16.607589 2, 0xFFFF, sum = 0
7966 04:44:16.608066 3, 0xFFFF, sum = 0
7967 04:44:16.610829 4, 0xFFFF, sum = 0
7968 04:44:16.613951 5, 0xFFFF, sum = 0
7969 04:44:16.614430 6, 0xFFFF, sum = 0
7970 04:44:16.617230 7, 0xFFFF, sum = 0
7971 04:44:16.617712 8, 0xFFFF, sum = 0
7972 04:44:16.621164 9, 0xFFFF, sum = 0
7973 04:44:16.621644 10, 0xFFFF, sum = 0
7974 04:44:16.623873 11, 0xFFFF, sum = 0
7975 04:44:16.624368 12, 0xCFFF, sum = 0
7976 04:44:16.627423 13, 0x0, sum = 1
7977 04:44:16.627996 14, 0x0, sum = 2
7978 04:44:16.630785 15, 0x0, sum = 3
7979 04:44:16.631266 16, 0x0, sum = 4
7980 04:44:16.633944 best_step = 14
7981 04:44:16.634414
7982 04:44:16.634889 ==
7983 04:44:16.637542 Dram Type= 6, Freq= 0, CH_0, rank 1
7984 04:44:16.642315 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7985 04:44:16.642881 ==
7986 04:44:16.643371 RX Vref Scan: 0
7987 04:44:16.643826
7988 04:44:16.644630 RX Vref 0 -> 0, step: 1
7989 04:44:16.645074
7990 04:44:16.647448 RX Delay 11 -> 252, step: 4
7991 04:44:16.650141 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7992 04:44:16.657427 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7993 04:44:16.660942 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7994 04:44:16.664122 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7995 04:44:16.667793 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7996 04:44:16.670285 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7997 04:44:16.677333 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7998 04:44:16.680644 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7999 04:44:16.683881 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
8000 04:44:16.686803 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
8001 04:44:16.690103 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8002 04:44:16.697017 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8003 04:44:16.700112 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8004 04:44:16.704111 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
8005 04:44:16.706953 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8006 04:44:16.714532 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8007 04:44:16.715080 ==
8008 04:44:16.717096 Dram Type= 6, Freq= 0, CH_0, rank 1
8009 04:44:16.720441 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8010 04:44:16.721060 ==
8011 04:44:16.721427 DQS Delay:
8012 04:44:16.724327 DQS0 = 0, DQS1 = 0
8013 04:44:16.724932 DQM Delay:
8014 04:44:16.726796 DQM0 = 128, DQM1 = 120
8015 04:44:16.727365 DQ Delay:
8016 04:44:16.730459 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
8017 04:44:16.733442 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8018 04:44:16.736663 DQ8 =108, DQ9 =108, DQ10 =122, DQ11 =112
8019 04:44:16.739950 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
8020 04:44:16.740403
8021 04:44:16.740818
8022 04:44:16.741170
8023 04:44:16.743173 [DramC_TX_OE_Calibration] TA2
8024 04:44:16.746285 Original DQ_B0 (3 6) =30, OEN = 27
8025 04:44:16.749757 Original DQ_B1 (3 6) =30, OEN = 27
8026 04:44:16.753060 24, 0x0, End_B0=24 End_B1=24
8027 04:44:16.756801 25, 0x0, End_B0=25 End_B1=25
8028 04:44:16.757377 26, 0x0, End_B0=26 End_B1=26
8029 04:44:16.759894 27, 0x0, End_B0=27 End_B1=27
8030 04:44:16.763690 28, 0x0, End_B0=28 End_B1=28
8031 04:44:16.766931 29, 0x0, End_B0=29 End_B1=29
8032 04:44:16.770088 30, 0x0, End_B0=30 End_B1=30
8033 04:44:16.770669 31, 0x4141, End_B0=30 End_B1=30
8034 04:44:16.773294 Byte0 end_step=30 best_step=27
8035 04:44:16.776289 Byte1 end_step=30 best_step=27
8036 04:44:16.779976 Byte0 TX OE(2T, 0.5T) = (3, 3)
8037 04:44:16.783246 Byte1 TX OE(2T, 0.5T) = (3, 3)
8038 04:44:16.783818
8039 04:44:16.784302
8040 04:44:16.789525 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8041 04:44:16.793145 CH0 RK1: MR19=303, MR18=2020
8042 04:44:16.799593 CH0_RK1: MR19=0x303, MR18=0x2020, DQSOSC=393, MR23=63, INC=23, DEC=15
8043 04:44:16.803218 [RxdqsGatingPostProcess] freq 1600
8044 04:44:16.809292 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8045 04:44:16.812779 Pre-setting of DQS Precalculation
8046 04:44:16.816199 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8047 04:44:16.816795 ==
8048 04:44:16.819706 Dram Type= 6, Freq= 0, CH_1, rank 0
8049 04:44:16.822932 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8050 04:44:16.823483 ==
8051 04:44:16.829378 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8052 04:44:16.832859 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8053 04:44:16.839375 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8054 04:44:16.842398 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8055 04:44:16.852151 [CA 0] Center 41 (11~71) winsize 61
8056 04:44:16.854951 [CA 1] Center 40 (10~70) winsize 61
8057 04:44:16.858174 [CA 2] Center 36 (6~66) winsize 61
8058 04:44:16.862813 [CA 3] Center 35 (6~65) winsize 60
8059 04:44:16.865148 [CA 4] Center 33 (3~63) winsize 61
8060 04:44:16.868599 [CA 5] Center 33 (4~63) winsize 60
8061 04:44:16.869291
8062 04:44:16.871978 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8063 04:44:16.872658
8064 04:44:16.874738 [CATrainingPosCal] consider 1 rank data
8065 04:44:16.877846 u2DelayCellTimex100 = 275/100 ps
8066 04:44:16.884826 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8067 04:44:16.888973 CA1 delay=40 (10~70),Diff = 7 PI (24 cell)
8068 04:44:16.891219 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
8069 04:44:16.895375 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8070 04:44:16.897646 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
8071 04:44:16.901897 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8072 04:44:16.902448
8073 04:44:16.904526 CA PerBit enable=1, Macro0, CA PI delay=33
8074 04:44:16.905142
8075 04:44:16.907514 [CBTSetCACLKResult] CA Dly = 33
8076 04:44:16.911165 CS Dly: 9 (0~40)
8077 04:44:16.914552 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8078 04:44:16.918126 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8079 04:44:16.918678 ==
8080 04:44:16.920849 Dram Type= 6, Freq= 0, CH_1, rank 1
8081 04:44:16.928110 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8082 04:44:16.928661 ==
8083 04:44:16.931227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8084 04:44:16.935262 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8085 04:44:16.941619 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8086 04:44:16.946956 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8087 04:44:16.955006 [CA 0] Center 40 (10~71) winsize 62
8088 04:44:16.957517 [CA 1] Center 40 (10~71) winsize 62
8089 04:44:16.961516 [CA 2] Center 36 (7~66) winsize 60
8090 04:44:16.965360 [CA 3] Center 36 (7~65) winsize 59
8091 04:44:16.967528 [CA 4] Center 34 (5~64) winsize 60
8092 04:44:16.971316 [CA 5] Center 34 (4~64) winsize 61
8093 04:44:16.971866
8094 04:44:16.975026 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8095 04:44:16.975579
8096 04:44:16.977114 [CATrainingPosCal] consider 2 rank data
8097 04:44:16.981194 u2DelayCellTimex100 = 275/100 ps
8098 04:44:16.983651 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8099 04:44:16.990535 CA1 delay=40 (10~70),Diff = 7 PI (24 cell)
8100 04:44:16.994792 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8101 04:44:16.997462 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8102 04:44:17.000671 CA4 delay=34 (5~63),Diff = 1 PI (3 cell)
8103 04:44:17.003993 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8104 04:44:17.004561
8105 04:44:17.007435 CA PerBit enable=1, Macro0, CA PI delay=33
8106 04:44:17.007888
8107 04:44:17.011255 [CBTSetCACLKResult] CA Dly = 33
8108 04:44:17.013956 CS Dly: 9 (0~41)
8109 04:44:17.017356 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8110 04:44:17.020472 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8111 04:44:17.021071
8112 04:44:17.024338 ----->DramcWriteLeveling(PI) begin...
8113 04:44:17.024961 ==
8114 04:44:17.027072 Dram Type= 6, Freq= 0, CH_1, rank 0
8115 04:44:17.033772 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8116 04:44:17.034339 ==
8117 04:44:17.036943 Write leveling (Byte 0): 22 => 22
8118 04:44:17.037399 Write leveling (Byte 1): 20 => 20
8119 04:44:17.040617 DramcWriteLeveling(PI) end<-----
8120 04:44:17.041110
8121 04:44:17.044231 ==
8122 04:44:17.044679 Dram Type= 6, Freq= 0, CH_1, rank 0
8123 04:44:17.050363 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8124 04:44:17.050925 ==
8125 04:44:17.053457 [Gating] SW mode calibration
8126 04:44:17.060312 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8127 04:44:17.064091 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8128 04:44:17.069841 0 12 0 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
8129 04:44:17.073369 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8130 04:44:17.076760 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8131 04:44:17.083689 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8132 04:44:17.086742 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8133 04:44:17.089859 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8134 04:44:17.096419 0 12 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8135 04:44:17.100132 0 12 28 | B1->B0 | 3434 2323 | 1 1 | (1 1) (1 0)
8136 04:44:17.103210 0 13 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
8137 04:44:17.109887 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8138 04:44:17.112930 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8139 04:44:17.116617 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8140 04:44:17.124162 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8141 04:44:17.125901 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8142 04:44:17.129628 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8143 04:44:17.136330 0 13 28 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
8144 04:44:17.139814 0 14 0 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
8145 04:44:17.143390 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8146 04:44:17.149855 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8147 04:44:17.153093 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8148 04:44:17.156175 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8149 04:44:17.163027 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8150 04:44:17.165971 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8151 04:44:17.169742 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8152 04:44:17.176161 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8153 04:44:17.179004 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8154 04:44:17.182927 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 04:44:17.189625 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 04:44:17.193899 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 04:44:17.196571 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 04:44:17.199451 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8159 04:44:17.205805 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8160 04:44:17.209664 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8161 04:44:17.212511 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 04:44:17.219416 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 04:44:17.222500 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8164 04:44:17.225969 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8165 04:44:17.232148 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8166 04:44:17.235645 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8167 04:44:17.238960 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8168 04:44:17.245390 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8169 04:44:17.248783 Total UI for P1: 0, mck2ui 16
8170 04:44:17.253121 best dqsien dly found for B0: ( 1, 0, 26)
8171 04:44:17.256144 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8172 04:44:17.258331 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8173 04:44:17.262184 Total UI for P1: 0, mck2ui 16
8174 04:44:17.265110 best dqsien dly found for B1: ( 1, 1, 2)
8175 04:44:17.268952 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8176 04:44:17.272188 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8177 04:44:17.275618
8178 04:44:17.279596 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8179 04:44:17.281563 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8180 04:44:17.285051 [Gating] SW calibration Done
8181 04:44:17.285599 ==
8182 04:44:17.289069 Dram Type= 6, Freq= 0, CH_1, rank 0
8183 04:44:17.291646 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8184 04:44:17.292244 ==
8185 04:44:17.292614 RX Vref Scan: 0
8186 04:44:17.294525
8187 04:44:17.294974 RX Vref 0 -> 0, step: 1
8188 04:44:17.295332
8189 04:44:17.297942 RX Delay 0 -> 252, step: 8
8190 04:44:17.301599 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8191 04:44:17.304783 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8192 04:44:17.311967 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8193 04:44:17.314988 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8194 04:44:17.318478 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8195 04:44:17.321965 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8196 04:44:17.325022 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8197 04:44:17.330946 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8198 04:44:17.334715 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8199 04:44:17.339394 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8200 04:44:17.341695 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8201 04:44:17.344531 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8202 04:44:17.351494 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8203 04:44:17.354610 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8204 04:44:17.357647 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8205 04:44:17.361650 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8206 04:44:17.362203 ==
8207 04:44:17.364461 Dram Type= 6, Freq= 0, CH_1, rank 0
8208 04:44:17.371302 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8209 04:44:17.371855 ==
8210 04:44:17.372218 DQS Delay:
8211 04:44:17.374447 DQS0 = 0, DQS1 = 0
8212 04:44:17.374994 DQM Delay:
8213 04:44:17.375357 DQM0 = 129, DQM1 = 126
8214 04:44:17.377979 DQ Delay:
8215 04:44:17.380867 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8216 04:44:17.385225 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8217 04:44:17.388549 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8218 04:44:17.391252 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8219 04:44:17.391969
8220 04:44:17.392603
8221 04:44:17.393044 ==
8222 04:44:17.394564 Dram Type= 6, Freq= 0, CH_1, rank 0
8223 04:44:17.400827 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8224 04:44:17.401286 ==
8225 04:44:17.401649
8226 04:44:17.401983
8227 04:44:17.402303 TX Vref Scan disable
8228 04:44:17.404479 == TX Byte 0 ==
8229 04:44:17.407829 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8230 04:44:17.410550 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8231 04:44:17.414171 == TX Byte 1 ==
8232 04:44:17.417898 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8233 04:44:17.425473 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8234 04:44:17.426028 ==
8235 04:44:17.427275 Dram Type= 6, Freq= 0, CH_1, rank 0
8236 04:44:17.430601 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8237 04:44:17.431153 ==
8238 04:44:17.442767
8239 04:44:17.446009 TX Vref early break, caculate TX vref
8240 04:44:17.449033 TX Vref=16, minBit 1, minWin=21, winSum=368
8241 04:44:17.452443 TX Vref=18, minBit 1, minWin=22, winSum=379
8242 04:44:17.456025 TX Vref=20, minBit 3, minWin=22, winSum=385
8243 04:44:17.459256 TX Vref=22, minBit 3, minWin=22, winSum=395
8244 04:44:17.462641 TX Vref=24, minBit 3, minWin=23, winSum=403
8245 04:44:17.468931 TX Vref=26, minBit 1, minWin=24, winSum=413
8246 04:44:17.472537 TX Vref=28, minBit 1, minWin=24, winSum=414
8247 04:44:17.475776 TX Vref=30, minBit 3, minWin=24, winSum=404
8248 04:44:17.479433 TX Vref=32, minBit 3, minWin=23, winSum=396
8249 04:44:17.482468 TX Vref=34, minBit 1, minWin=23, winSum=392
8250 04:44:17.489532 [TxChooseVref] Worse bit 1, Min win 24, Win sum 414, Final Vref 28
8251 04:44:17.490074
8252 04:44:17.492223 Final TX Range 0 Vref 28
8253 04:44:17.492765
8254 04:44:17.493229 ==
8255 04:44:17.495442 Dram Type= 6, Freq= 0, CH_1, rank 0
8256 04:44:17.498853 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8257 04:44:17.499321 ==
8258 04:44:17.499687
8259 04:44:17.500145
8260 04:44:17.502051 TX Vref Scan disable
8261 04:44:17.508587 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8262 04:44:17.509094 == TX Byte 0 ==
8263 04:44:17.511979 u2DelayCellOfst[0]=17 cells (5 PI)
8264 04:44:17.515505 u2DelayCellOfst[1]=14 cells (4 PI)
8265 04:44:17.519128 u2DelayCellOfst[2]=0 cells (0 PI)
8266 04:44:17.522214 u2DelayCellOfst[3]=10 cells (3 PI)
8267 04:44:17.525322 u2DelayCellOfst[4]=10 cells (3 PI)
8268 04:44:17.529096 u2DelayCellOfst[5]=17 cells (5 PI)
8269 04:44:17.532409 u2DelayCellOfst[6]=17 cells (5 PI)
8270 04:44:17.534997 u2DelayCellOfst[7]=7 cells (2 PI)
8271 04:44:17.538050 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8272 04:44:17.541290 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8273 04:44:17.544981 == TX Byte 1 ==
8274 04:44:17.547910 u2DelayCellOfst[8]=0 cells (0 PI)
8275 04:44:17.548430 u2DelayCellOfst[9]=7 cells (2 PI)
8276 04:44:17.551398 u2DelayCellOfst[10]=10 cells (3 PI)
8277 04:44:17.554749 u2DelayCellOfst[11]=7 cells (2 PI)
8278 04:44:17.558774 u2DelayCellOfst[12]=17 cells (5 PI)
8279 04:44:17.561550 u2DelayCellOfst[13]=17 cells (5 PI)
8280 04:44:17.565061 u2DelayCellOfst[14]=17 cells (5 PI)
8281 04:44:17.567969 u2DelayCellOfst[15]=21 cells (6 PI)
8282 04:44:17.571324 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8283 04:44:17.577873 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8284 04:44:17.578412 DramC Write-DBI on
8285 04:44:17.578774 ==
8286 04:44:17.582903 Dram Type= 6, Freq= 0, CH_1, rank 0
8287 04:44:17.587763 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8288 04:44:17.588319 ==
8289 04:44:17.588686
8290 04:44:17.589084
8291 04:44:17.589410 TX Vref Scan disable
8292 04:44:17.591449 == TX Byte 0 ==
8293 04:44:17.595160 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8294 04:44:17.598467 == TX Byte 1 ==
8295 04:44:17.601826 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8296 04:44:17.605587 DramC Write-DBI off
8297 04:44:17.606135
8298 04:44:17.606498 [DATLAT]
8299 04:44:17.606835 Freq=1600, CH1 RK0
8300 04:44:17.607159
8301 04:44:17.608334 DATLAT Default: 0xf
8302 04:44:17.608928 0, 0xFFFF, sum = 0
8303 04:44:17.612313 1, 0xFFFF, sum = 0
8304 04:44:17.612828 2, 0xFFFF, sum = 0
8305 04:44:17.615023 3, 0xFFFF, sum = 0
8306 04:44:17.618268 4, 0xFFFF, sum = 0
8307 04:44:17.618829 5, 0xFFFF, sum = 0
8308 04:44:17.621984 6, 0xFFFF, sum = 0
8309 04:44:17.622539 7, 0xFFFF, sum = 0
8310 04:44:17.624649 8, 0xFFFF, sum = 0
8311 04:44:17.625141 9, 0xFFFF, sum = 0
8312 04:44:17.628970 10, 0xFFFF, sum = 0
8313 04:44:17.629528 11, 0xFFFF, sum = 0
8314 04:44:17.631371 12, 0xFFF, sum = 0
8315 04:44:17.631831 13, 0x0, sum = 1
8316 04:44:17.635565 14, 0x0, sum = 2
8317 04:44:17.636125 15, 0x0, sum = 3
8318 04:44:17.638347 16, 0x0, sum = 4
8319 04:44:17.638810 best_step = 14
8320 04:44:17.639172
8321 04:44:17.639509 ==
8322 04:44:17.641396 Dram Type= 6, Freq= 0, CH_1, rank 0
8323 04:44:17.645488 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8324 04:44:17.648862 ==
8325 04:44:17.649411 RX Vref Scan: 1
8326 04:44:17.649776
8327 04:44:17.651262 Set Vref Range= 24 -> 127
8328 04:44:17.651717
8329 04:44:17.655076 RX Vref 24 -> 127, step: 1
8330 04:44:17.655630
8331 04:44:17.655998 RX Delay 3 -> 252, step: 4
8332 04:44:17.656336
8333 04:44:17.657963 Set Vref, RX VrefLevel [Byte0]: 24
8334 04:44:17.661042 [Byte1]: 24
8335 04:44:17.665026
8336 04:44:17.665573 Set Vref, RX VrefLevel [Byte0]: 25
8337 04:44:17.668315 [Byte1]: 25
8338 04:44:17.672700
8339 04:44:17.673295 Set Vref, RX VrefLevel [Byte0]: 26
8340 04:44:17.675915 [Byte1]: 26
8341 04:44:17.680765
8342 04:44:17.681320 Set Vref, RX VrefLevel [Byte0]: 27
8343 04:44:17.683407 [Byte1]: 27
8344 04:44:17.688230
8345 04:44:17.688833 Set Vref, RX VrefLevel [Byte0]: 28
8346 04:44:17.691597 [Byte1]: 28
8347 04:44:17.695761
8348 04:44:17.696221 Set Vref, RX VrefLevel [Byte0]: 29
8349 04:44:17.699381 [Byte1]: 29
8350 04:44:17.703899
8351 04:44:17.704448 Set Vref, RX VrefLevel [Byte0]: 30
8352 04:44:17.706787 [Byte1]: 30
8353 04:44:17.710752
8354 04:44:17.711206 Set Vref, RX VrefLevel [Byte0]: 31
8355 04:44:17.714880 [Byte1]: 31
8356 04:44:17.718768
8357 04:44:17.719316 Set Vref, RX VrefLevel [Byte0]: 32
8358 04:44:17.721999 [Byte1]: 32
8359 04:44:17.725973
8360 04:44:17.726429 Set Vref, RX VrefLevel [Byte0]: 33
8361 04:44:17.729690 [Byte1]: 33
8362 04:44:17.734762
8363 04:44:17.735212 Set Vref, RX VrefLevel [Byte0]: 34
8364 04:44:17.737333 [Byte1]: 34
8365 04:44:17.741364
8366 04:44:17.741814 Set Vref, RX VrefLevel [Byte0]: 35
8367 04:44:17.744810 [Byte1]: 35
8368 04:44:17.749342
8369 04:44:17.749768 Set Vref, RX VrefLevel [Byte0]: 36
8370 04:44:17.752437 [Byte1]: 36
8371 04:44:17.757554
8372 04:44:17.758056 Set Vref, RX VrefLevel [Byte0]: 37
8373 04:44:17.760358 [Byte1]: 37
8374 04:44:17.764820
8375 04:44:17.765270 Set Vref, RX VrefLevel [Byte0]: 38
8376 04:44:17.768515 [Byte1]: 38
8377 04:44:17.772540
8378 04:44:17.773135 Set Vref, RX VrefLevel [Byte0]: 39
8379 04:44:17.775539 [Byte1]: 39
8380 04:44:17.779872
8381 04:44:17.780474 Set Vref, RX VrefLevel [Byte0]: 40
8382 04:44:17.783900 [Byte1]: 40
8383 04:44:17.787968
8384 04:44:17.788420 Set Vref, RX VrefLevel [Byte0]: 41
8385 04:44:17.791101 [Byte1]: 41
8386 04:44:17.795314
8387 04:44:17.795801 Set Vref, RX VrefLevel [Byte0]: 42
8388 04:44:17.798308 [Byte1]: 42
8389 04:44:17.802526
8390 04:44:17.802983 Set Vref, RX VrefLevel [Byte0]: 43
8391 04:44:17.806693 [Byte1]: 43
8392 04:44:17.811000
8393 04:44:17.811551 Set Vref, RX VrefLevel [Byte0]: 44
8394 04:44:17.814033 [Byte1]: 44
8395 04:44:17.818548
8396 04:44:17.819106 Set Vref, RX VrefLevel [Byte0]: 45
8397 04:44:17.821646 [Byte1]: 45
8398 04:44:17.826645
8399 04:44:17.827213 Set Vref, RX VrefLevel [Byte0]: 46
8400 04:44:17.829195 [Byte1]: 46
8401 04:44:17.834269
8402 04:44:17.834829 Set Vref, RX VrefLevel [Byte0]: 47
8403 04:44:17.836843 [Byte1]: 47
8404 04:44:17.841089
8405 04:44:17.841657 Set Vref, RX VrefLevel [Byte0]: 48
8406 04:44:17.844256 [Byte1]: 48
8407 04:44:17.849552
8408 04:44:17.850101 Set Vref, RX VrefLevel [Byte0]: 49
8409 04:44:17.852019 [Byte1]: 49
8410 04:44:17.856377
8411 04:44:17.856976 Set Vref, RX VrefLevel [Byte0]: 50
8412 04:44:17.859780 [Byte1]: 50
8413 04:44:17.864353
8414 04:44:17.864944 Set Vref, RX VrefLevel [Byte0]: 51
8415 04:44:17.867873 [Byte1]: 51
8416 04:44:17.871724
8417 04:44:17.872176 Set Vref, RX VrefLevel [Byte0]: 52
8418 04:44:17.875505 [Byte1]: 52
8419 04:44:17.879850
8420 04:44:17.880389 Set Vref, RX VrefLevel [Byte0]: 53
8421 04:44:17.882650 [Byte1]: 53
8422 04:44:17.887553
8423 04:44:17.888096 Set Vref, RX VrefLevel [Byte0]: 54
8424 04:44:17.890476 [Byte1]: 54
8425 04:44:17.894912
8426 04:44:17.895739 Set Vref, RX VrefLevel [Byte0]: 55
8427 04:44:17.897704 [Byte1]: 55
8428 04:44:17.902658
8429 04:44:17.903207 Set Vref, RX VrefLevel [Byte0]: 56
8430 04:44:17.905731 [Byte1]: 56
8431 04:44:17.910065
8432 04:44:17.910741 Set Vref, RX VrefLevel [Byte0]: 57
8433 04:44:17.914155 [Byte1]: 57
8434 04:44:17.917755
8435 04:44:17.918227 Set Vref, RX VrefLevel [Byte0]: 58
8436 04:44:17.921271 [Byte1]: 58
8437 04:44:17.926336
8438 04:44:17.926882 Set Vref, RX VrefLevel [Byte0]: 59
8439 04:44:17.928840 [Byte1]: 59
8440 04:44:17.933351
8441 04:44:17.933897 Set Vref, RX VrefLevel [Byte0]: 60
8442 04:44:17.936134 [Byte1]: 60
8443 04:44:17.940549
8444 04:44:17.941165 Set Vref, RX VrefLevel [Byte0]: 61
8445 04:44:17.944121 [Byte1]: 61
8446 04:44:17.948903
8447 04:44:17.949462 Set Vref, RX VrefLevel [Byte0]: 62
8448 04:44:17.951770 [Byte1]: 62
8449 04:44:17.957659
8450 04:44:17.958201 Set Vref, RX VrefLevel [Byte0]: 63
8451 04:44:17.959238 [Byte1]: 63
8452 04:44:17.963671
8453 04:44:17.964221 Set Vref, RX VrefLevel [Byte0]: 64
8454 04:44:17.966869 [Byte1]: 64
8455 04:44:17.971505
8456 04:44:17.972056 Set Vref, RX VrefLevel [Byte0]: 65
8457 04:44:17.974321 [Byte1]: 65
8458 04:44:17.979394
8459 04:44:17.979953 Set Vref, RX VrefLevel [Byte0]: 66
8460 04:44:17.982232 [Byte1]: 66
8461 04:44:17.986629
8462 04:44:17.987180 Set Vref, RX VrefLevel [Byte0]: 67
8463 04:44:17.989648 [Byte1]: 67
8464 04:44:17.994348
8465 04:44:17.994908 Set Vref, RX VrefLevel [Byte0]: 68
8466 04:44:17.997911 [Byte1]: 68
8467 04:44:18.001540
8468 04:44:18.002103 Set Vref, RX VrefLevel [Byte0]: 69
8469 04:44:18.004884 [Byte1]: 69
8470 04:44:18.009895
8471 04:44:18.010453 Set Vref, RX VrefLevel [Byte0]: 70
8472 04:44:18.012478 [Byte1]: 70
8473 04:44:18.017221
8474 04:44:18.017780 Set Vref, RX VrefLevel [Byte0]: 71
8475 04:44:18.020781 [Byte1]: 71
8476 04:44:18.024979
8477 04:44:18.025434 Set Vref, RX VrefLevel [Byte0]: 72
8478 04:44:18.027907 [Byte1]: 72
8479 04:44:18.032180
8480 04:44:18.032638 Final RX Vref Byte 0 = 64 to rank0
8481 04:44:18.036298 Final RX Vref Byte 1 = 54 to rank0
8482 04:44:18.039241 Final RX Vref Byte 0 = 64 to rank1
8483 04:44:18.042652 Final RX Vref Byte 1 = 54 to rank1==
8484 04:44:18.046152 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 04:44:18.053606 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8486 04:44:18.054176 ==
8487 04:44:18.054543 DQS Delay:
8488 04:44:18.054882 DQS0 = 0, DQS1 = 0
8489 04:44:18.055693 DQM Delay:
8490 04:44:18.056065 DQM0 = 127, DQM1 = 124
8491 04:44:18.059407 DQ Delay:
8492 04:44:18.063065 DQ0 =130, DQ1 =122, DQ2 =116, DQ3 =126
8493 04:44:18.066179 DQ4 =128, DQ5 =138, DQ6 =136, DQ7 =126
8494 04:44:18.069077 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8495 04:44:18.072529 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134
8496 04:44:18.073138
8497 04:44:18.073519
8498 04:44:18.073858
8499 04:44:18.076109 [DramC_TX_OE_Calibration] TA2
8500 04:44:18.079126 Original DQ_B0 (3 6) =30, OEN = 27
8501 04:44:18.082744 Original DQ_B1 (3 6) =30, OEN = 27
8502 04:44:18.086110 24, 0x0, End_B0=24 End_B1=24
8503 04:44:18.086676 25, 0x0, End_B0=25 End_B1=25
8504 04:44:18.089150 26, 0x0, End_B0=26 End_B1=26
8505 04:44:18.092082 27, 0x0, End_B0=27 End_B1=27
8506 04:44:18.095392 28, 0x0, End_B0=28 End_B1=28
8507 04:44:18.098748 29, 0x0, End_B0=29 End_B1=29
8508 04:44:18.099217 30, 0x0, End_B0=30 End_B1=30
8509 04:44:18.102682 31, 0x4141, End_B0=30 End_B1=30
8510 04:44:18.105100 Byte0 end_step=30 best_step=27
8511 04:44:18.108599 Byte1 end_step=30 best_step=27
8512 04:44:18.112218 Byte0 TX OE(2T, 0.5T) = (3, 3)
8513 04:44:18.115710 Byte1 TX OE(2T, 0.5T) = (3, 3)
8514 04:44:18.116263
8515 04:44:18.116631
8516 04:44:18.121789 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8517 04:44:18.125361 CH1 RK0: MR19=303, MR18=2626
8518 04:44:18.132330 CH1_RK0: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
8519 04:44:18.132927
8520 04:44:18.135384 ----->DramcWriteLeveling(PI) begin...
8521 04:44:18.135946 ==
8522 04:44:18.138673 Dram Type= 6, Freq= 0, CH_1, rank 1
8523 04:44:18.141678 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8524 04:44:18.142234 ==
8525 04:44:18.144954 Write leveling (Byte 0): 22 => 22
8526 04:44:18.149038 Write leveling (Byte 1): 20 => 20
8527 04:44:18.151524 DramcWriteLeveling(PI) end<-----
8528 04:44:18.152076
8529 04:44:18.152439 ==
8530 04:44:18.154975 Dram Type= 6, Freq= 0, CH_1, rank 1
8531 04:44:18.157734 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8532 04:44:18.158197 ==
8533 04:44:18.161263 [Gating] SW mode calibration
8534 04:44:18.168163 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8535 04:44:18.174764 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8536 04:44:18.177676 0 12 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8537 04:44:18.184865 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8538 04:44:18.188752 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8539 04:44:18.191283 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8540 04:44:18.198818 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8541 04:44:18.201784 0 12 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8542 04:44:18.204824 0 12 24 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 1)
8543 04:44:18.211059 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8544 04:44:18.215362 0 13 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8545 04:44:18.217331 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8546 04:44:18.224195 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8547 04:44:18.227711 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8548 04:44:18.231355 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8549 04:44:18.237443 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8550 04:44:18.241205 0 13 24 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8551 04:44:18.244634 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8552 04:44:18.250885 0 14 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8553 04:44:18.253897 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8554 04:44:18.257685 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8555 04:44:18.263898 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8556 04:44:18.267453 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8557 04:44:18.270931 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8558 04:44:18.276859 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8559 04:44:18.280468 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8560 04:44:18.284089 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8561 04:44:18.290287 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8562 04:44:18.293668 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8563 04:44:18.297295 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8564 04:44:18.303358 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8565 04:44:18.307205 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8566 04:44:18.310481 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8567 04:44:18.316675 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8568 04:44:18.319588 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8569 04:44:18.323160 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8570 04:44:18.329872 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8571 04:44:18.333582 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8572 04:44:18.336136 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8573 04:44:18.340031 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8574 04:44:18.346916 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8575 04:44:18.350319 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8576 04:44:18.353105 Total UI for P1: 0, mck2ui 16
8577 04:44:18.356536 best dqsien dly found for B0: ( 1, 0, 22)
8578 04:44:18.359932 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8579 04:44:18.365991 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8580 04:44:18.370248 Total UI for P1: 0, mck2ui 16
8581 04:44:18.373091 best dqsien dly found for B1: ( 1, 0, 30)
8582 04:44:18.376906 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8583 04:44:18.379828 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8584 04:44:18.380393
8585 04:44:18.383162 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8586 04:44:18.386459 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8587 04:44:18.389085 [Gating] SW calibration Done
8588 04:44:18.389546 ==
8589 04:44:18.393166 Dram Type= 6, Freq= 0, CH_1, rank 1
8590 04:44:18.395653 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8591 04:44:18.396118 ==
8592 04:44:18.398823 RX Vref Scan: 0
8593 04:44:18.399284
8594 04:44:18.402555 RX Vref 0 -> 0, step: 1
8595 04:44:18.403019
8596 04:44:18.403386 RX Delay 0 -> 252, step: 8
8597 04:44:18.409056 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8598 04:44:18.412534 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8599 04:44:18.415917 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8600 04:44:18.420079 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8601 04:44:18.422797 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8602 04:44:18.429386 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8603 04:44:18.432349 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8604 04:44:18.435415 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8605 04:44:18.440608 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8606 04:44:18.442126 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8607 04:44:18.449352 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8608 04:44:18.452398 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8609 04:44:18.455447 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8610 04:44:18.458852 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8611 04:44:18.465584 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8612 04:44:18.468591 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8613 04:44:18.469174 ==
8614 04:44:18.472549 Dram Type= 6, Freq= 0, CH_1, rank 1
8615 04:44:18.474974 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8616 04:44:18.475440 ==
8617 04:44:18.475811 DQS Delay:
8618 04:44:18.478579 DQS0 = 0, DQS1 = 0
8619 04:44:18.479135 DQM Delay:
8620 04:44:18.481844 DQM0 = 130, DQM1 = 125
8621 04:44:18.482304 DQ Delay:
8622 04:44:18.484917 DQ0 =131, DQ1 =131, DQ2 =119, DQ3 =127
8623 04:44:18.487991 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =127
8624 04:44:18.491651 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8625 04:44:18.498563 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8626 04:44:18.499113
8627 04:44:18.499483
8628 04:44:18.499824 ==
8629 04:44:18.501276 Dram Type= 6, Freq= 0, CH_1, rank 1
8630 04:44:18.504552 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8631 04:44:18.505067 ==
8632 04:44:18.505437
8633 04:44:18.505778
8634 04:44:18.507977 TX Vref Scan disable
8635 04:44:18.508437 == TX Byte 0 ==
8636 04:44:18.515205 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8637 04:44:18.517916 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8638 04:44:18.518379 == TX Byte 1 ==
8639 04:44:18.525120 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8640 04:44:18.528271 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8641 04:44:18.528877 ==
8642 04:44:18.531720 Dram Type= 6, Freq= 0, CH_1, rank 1
8643 04:44:18.534813 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8644 04:44:18.535372 ==
8645 04:44:18.550303
8646 04:44:18.552613 TX Vref early break, caculate TX vref
8647 04:44:18.556142 TX Vref=16, minBit 3, minWin=22, winSum=379
8648 04:44:18.559692 TX Vref=18, minBit 0, minWin=23, winSum=388
8649 04:44:18.562267 TX Vref=20, minBit 0, minWin=24, winSum=400
8650 04:44:18.565694 TX Vref=22, minBit 0, minWin=24, winSum=405
8651 04:44:18.569290 TX Vref=24, minBit 0, minWin=25, winSum=417
8652 04:44:18.576227 TX Vref=26, minBit 0, minWin=25, winSum=418
8653 04:44:18.578897 TX Vref=28, minBit 0, minWin=25, winSum=420
8654 04:44:18.583307 TX Vref=30, minBit 0, minWin=24, winSum=411
8655 04:44:18.586386 TX Vref=32, minBit 1, minWin=24, winSum=409
8656 04:44:18.588896 TX Vref=34, minBit 0, minWin=22, winSum=401
8657 04:44:18.592370 TX Vref=36, minBit 5, minWin=21, winSum=393
8658 04:44:18.598788 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8659 04:44:18.599254
8660 04:44:18.601943 Final TX Range 0 Vref 28
8661 04:44:18.602470
8662 04:44:18.602849 ==
8663 04:44:18.605389 Dram Type= 6, Freq= 0, CH_1, rank 1
8664 04:44:18.609014 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8665 04:44:18.609478 ==
8666 04:44:18.609844
8667 04:44:18.612102
8668 04:44:18.612623 TX Vref Scan disable
8669 04:44:18.618748 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8670 04:44:18.619286 == TX Byte 0 ==
8671 04:44:18.622449 u2DelayCellOfst[0]=14 cells (4 PI)
8672 04:44:18.625252 u2DelayCellOfst[1]=7 cells (2 PI)
8673 04:44:18.628786 u2DelayCellOfst[2]=0 cells (0 PI)
8674 04:44:18.633138 u2DelayCellOfst[3]=7 cells (2 PI)
8675 04:44:18.635469 u2DelayCellOfst[4]=7 cells (2 PI)
8676 04:44:18.638884 u2DelayCellOfst[5]=10 cells (3 PI)
8677 04:44:18.642085 u2DelayCellOfst[6]=14 cells (4 PI)
8678 04:44:18.645488 u2DelayCellOfst[7]=3 cells (1 PI)
8679 04:44:18.649244 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8680 04:44:18.651945 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8681 04:44:18.655527 == TX Byte 1 ==
8682 04:44:18.659061 u2DelayCellOfst[8]=0 cells (0 PI)
8683 04:44:18.661691 u2DelayCellOfst[9]=7 cells (2 PI)
8684 04:44:18.662112 u2DelayCellOfst[10]=10 cells (3 PI)
8685 04:44:18.665238 u2DelayCellOfst[11]=3 cells (1 PI)
8686 04:44:18.668619 u2DelayCellOfst[12]=14 cells (4 PI)
8687 04:44:18.672367 u2DelayCellOfst[13]=17 cells (5 PI)
8688 04:44:18.674891 u2DelayCellOfst[14]=17 cells (5 PI)
8689 04:44:18.678821 u2DelayCellOfst[15]=17 cells (5 PI)
8690 04:44:18.685241 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8691 04:44:18.689366 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8692 04:44:18.689927 DramC Write-DBI on
8693 04:44:18.690298 ==
8694 04:44:18.691316 Dram Type= 6, Freq= 0, CH_1, rank 1
8695 04:44:18.698299 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8696 04:44:18.698875 ==
8697 04:44:18.699250
8698 04:44:18.699595
8699 04:44:18.699923 TX Vref Scan disable
8700 04:44:18.703191 == TX Byte 0 ==
8701 04:44:18.706819 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8702 04:44:18.708792 == TX Byte 1 ==
8703 04:44:18.712477 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8704 04:44:18.715589 DramC Write-DBI off
8705 04:44:18.716149
8706 04:44:18.716514 [DATLAT]
8707 04:44:18.716921 Freq=1600, CH1 RK1
8708 04:44:18.717265
8709 04:44:18.719604 DATLAT Default: 0xe
8710 04:44:18.720160 0, 0xFFFF, sum = 0
8711 04:44:18.722032 1, 0xFFFF, sum = 0
8712 04:44:18.725162 2, 0xFFFF, sum = 0
8713 04:44:18.725629 3, 0xFFFF, sum = 0
8714 04:44:18.729381 4, 0xFFFF, sum = 0
8715 04:44:18.729943 5, 0xFFFF, sum = 0
8716 04:44:18.733101 6, 0xFFFF, sum = 0
8717 04:44:18.733666 7, 0xFFFF, sum = 0
8718 04:44:18.736449 8, 0xFFFF, sum = 0
8719 04:44:18.737068 9, 0xFFFF, sum = 0
8720 04:44:18.738542 10, 0xFFFF, sum = 0
8721 04:44:18.739010 11, 0xFFFF, sum = 0
8722 04:44:18.741940 12, 0xF7F, sum = 0
8723 04:44:18.742504 13, 0x0, sum = 1
8724 04:44:18.745450 14, 0x0, sum = 2
8725 04:44:18.746014 15, 0x0, sum = 3
8726 04:44:18.748440 16, 0x0, sum = 4
8727 04:44:18.748934 best_step = 14
8728 04:44:18.749301
8729 04:44:18.749637 ==
8730 04:44:18.752009 Dram Type= 6, Freq= 0, CH_1, rank 1
8731 04:44:18.756207 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8732 04:44:18.759149 ==
8733 04:44:18.759700 RX Vref Scan: 0
8734 04:44:18.760067
8735 04:44:18.762771 RX Vref 0 -> 0, step: 1
8736 04:44:18.763236
8737 04:44:18.763606 RX Delay 3 -> 252, step: 4
8738 04:44:18.769225 iDelay=195, Bit 0, Center 130 (79 ~ 182) 104
8739 04:44:18.772469 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8740 04:44:18.775982 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8741 04:44:18.779737 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8742 04:44:18.785335 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8743 04:44:18.789481 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8744 04:44:18.792502 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8745 04:44:18.795836 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8746 04:44:18.798872 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8747 04:44:18.801912 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
8748 04:44:18.808993 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8749 04:44:18.812689 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8750 04:44:18.815404 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8751 04:44:18.819267 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8752 04:44:18.825193 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8753 04:44:18.828616 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8754 04:44:18.829205 ==
8755 04:44:18.832423 Dram Type= 6, Freq= 0, CH_1, rank 1
8756 04:44:18.835744 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8757 04:44:18.836306 ==
8758 04:44:18.839485 DQS Delay:
8759 04:44:18.840033 DQS0 = 0, DQS1 = 0
8760 04:44:18.840401 DQM Delay:
8761 04:44:18.842425 DQM0 = 127, DQM1 = 122
8762 04:44:18.842977 DQ Delay:
8763 04:44:18.844923 DQ0 =130, DQ1 =122, DQ2 =118, DQ3 =124
8764 04:44:18.848806 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =124
8765 04:44:18.855112 DQ8 =106, DQ9 =108, DQ10 =124, DQ11 =114
8766 04:44:18.859248 DQ12 =130, DQ13 =132, DQ14 =134, DQ15 =132
8767 04:44:18.859810
8768 04:44:18.860176
8769 04:44:18.860517
8770 04:44:18.862892 [DramC_TX_OE_Calibration] TA2
8771 04:44:18.865229 Original DQ_B0 (3 6) =30, OEN = 27
8772 04:44:18.868465 Original DQ_B1 (3 6) =30, OEN = 27
8773 04:44:18.869088 24, 0x0, End_B0=24 End_B1=24
8774 04:44:18.871830 25, 0x0, End_B0=25 End_B1=25
8775 04:44:18.875008 26, 0x0, End_B0=26 End_B1=26
8776 04:44:18.878741 27, 0x0, End_B0=27 End_B1=27
8777 04:44:18.879305 28, 0x0, End_B0=28 End_B1=28
8778 04:44:18.882582 29, 0x0, End_B0=29 End_B1=29
8779 04:44:18.884808 30, 0x0, End_B0=30 End_B1=30
8780 04:44:18.888937 31, 0x4141, End_B0=30 End_B1=30
8781 04:44:18.891589 Byte0 end_step=30 best_step=27
8782 04:44:18.894504 Byte1 end_step=30 best_step=27
8783 04:44:18.894966 Byte0 TX OE(2T, 0.5T) = (3, 3)
8784 04:44:18.898013 Byte1 TX OE(2T, 0.5T) = (3, 3)
8785 04:44:18.898583
8786 04:44:18.898951
8787 04:44:18.907710 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8788 04:44:18.912106 CH1 RK1: MR19=303, MR18=1D1D
8789 04:44:18.914137 CH1_RK1: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
8790 04:44:18.917631 [RxdqsGatingPostProcess] freq 1600
8791 04:44:18.924896 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8792 04:44:18.927974 Pre-setting of DQS Precalculation
8793 04:44:18.930949 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8794 04:44:18.941011 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8795 04:44:18.947290 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8796 04:44:18.947836
8797 04:44:18.948199
8798 04:44:18.950532 [Calibration Summary] 3200 Mbps
8799 04:44:18.950991 CH 0, Rank 0
8800 04:44:18.954140 SW Impedance : PASS
8801 04:44:18.954690 DUTY Scan : NO K
8802 04:44:18.958038 ZQ Calibration : PASS
8803 04:44:18.961492 Jitter Meter : NO K
8804 04:44:18.962043 CBT Training : PASS
8805 04:44:18.964583 Write leveling : PASS
8806 04:44:18.967469 RX DQS gating : PASS
8807 04:44:18.968018 RX DQ/DQS(RDDQC) : PASS
8808 04:44:18.971507 TX DQ/DQS : PASS
8809 04:44:18.974345 RX DATLAT : PASS
8810 04:44:18.974808 RX DQ/DQS(Engine): PASS
8811 04:44:18.977713 TX OE : PASS
8812 04:44:18.978267 All Pass.
8813 04:44:18.978632
8814 04:44:18.980596 CH 0, Rank 1
8815 04:44:18.981198 SW Impedance : PASS
8816 04:44:18.983892 DUTY Scan : NO K
8817 04:44:18.987171 ZQ Calibration : PASS
8818 04:44:18.987728 Jitter Meter : NO K
8819 04:44:18.990920 CBT Training : PASS
8820 04:44:18.993965 Write leveling : PASS
8821 04:44:18.994517 RX DQS gating : PASS
8822 04:44:18.997694 RX DQ/DQS(RDDQC) : PASS
8823 04:44:19.001037 TX DQ/DQS : PASS
8824 04:44:19.001586 RX DATLAT : PASS
8825 04:44:19.004826 RX DQ/DQS(Engine): PASS
8826 04:44:19.007152 TX OE : PASS
8827 04:44:19.007707 All Pass.
8828 04:44:19.008069
8829 04:44:19.008410 CH 1, Rank 0
8830 04:44:19.011149 SW Impedance : PASS
8831 04:44:19.013917 DUTY Scan : NO K
8832 04:44:19.014379 ZQ Calibration : PASS
8833 04:44:19.016962 Jitter Meter : NO K
8834 04:44:19.017426 CBT Training : PASS
8835 04:44:19.020184 Write leveling : PASS
8836 04:44:19.023977 RX DQS gating : PASS
8837 04:44:19.024763 RX DQ/DQS(RDDQC) : PASS
8838 04:44:19.026793 TX DQ/DQS : PASS
8839 04:44:19.030361 RX DATLAT : PASS
8840 04:44:19.030924 RX DQ/DQS(Engine): PASS
8841 04:44:19.033298 TX OE : PASS
8842 04:44:19.033761 All Pass.
8843 04:44:19.034125
8844 04:44:19.037092 CH 1, Rank 1
8845 04:44:19.037652 SW Impedance : PASS
8846 04:44:19.039953 DUTY Scan : NO K
8847 04:44:19.043485 ZQ Calibration : PASS
8848 04:44:19.044049 Jitter Meter : NO K
8849 04:44:19.046829 CBT Training : PASS
8850 04:44:19.049944 Write leveling : PASS
8851 04:44:19.050408 RX DQS gating : PASS
8852 04:44:19.053302 RX DQ/DQS(RDDQC) : PASS
8853 04:44:19.056683 TX DQ/DQS : PASS
8854 04:44:19.057196 RX DATLAT : PASS
8855 04:44:19.059515 RX DQ/DQS(Engine): PASS
8856 04:44:19.063440 TX OE : PASS
8857 04:44:19.063905 All Pass.
8858 04:44:19.064272
8859 04:44:19.064614 DramC Write-DBI on
8860 04:44:19.067399 PER_BANK_REFRESH: Hybrid Mode
8861 04:44:19.069937 TX_TRACKING: ON
8862 04:44:19.077475 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8863 04:44:19.086920 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8864 04:44:19.093188 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8865 04:44:19.096890 [FAST_K] Save calibration result to emmc
8866 04:44:19.099649 sync common calibartion params.
8867 04:44:19.102881 sync cbt_mode0:0, 1:0
8868 04:44:19.103672 dram_init: ddr_geometry: 0
8869 04:44:19.106892 dram_init: ddr_geometry: 0
8870 04:44:19.110359 dram_init: ddr_geometry: 0
8871 04:44:19.110924 0:dram_rank_size:80000000
8872 04:44:19.113502 1:dram_rank_size:80000000
8873 04:44:19.119592 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8874 04:44:19.120140 DFS_SHUFFLE_HW_MODE: ON
8875 04:44:19.126442 dramc_set_vcore_voltage set vcore to 725000
8876 04:44:19.127011 Read voltage for 1600, 0
8877 04:44:19.129537 Vio18 = 0
8878 04:44:19.129999 Vcore = 725000
8879 04:44:19.130363 Vdram = 0
8880 04:44:19.132928 Vddq = 0
8881 04:44:19.133388 Vmddr = 0
8882 04:44:19.136251 switch to 3200 Mbps bootup
8883 04:44:19.136751 [DramcRunTimeConfig]
8884 04:44:19.137130 PHYPLL
8885 04:44:19.140988 DPM_CONTROL_AFTERK: ON
8886 04:44:19.143335 PER_BANK_REFRESH: ON
8887 04:44:19.143888 REFRESH_OVERHEAD_REDUCTION: ON
8888 04:44:19.146140 CMD_PICG_NEW_MODE: OFF
8889 04:44:19.149042 XRTWTW_NEW_MODE: ON
8890 04:44:19.149500 XRTRTR_NEW_MODE: ON
8891 04:44:19.152780 TX_TRACKING: ON
8892 04:44:19.153242 RDSEL_TRACKING: OFF
8893 04:44:19.155736 DQS Precalculation for DVFS: ON
8894 04:44:19.156192 RX_TRACKING: OFF
8895 04:44:19.160415 HW_GATING DBG: ON
8896 04:44:19.161017 ZQCS_ENABLE_LP4: ON
8897 04:44:19.162468 RX_PICG_NEW_MODE: ON
8898 04:44:19.165922 TX_PICG_NEW_MODE: ON
8899 04:44:19.166520 ENABLE_RX_DCM_DPHY: ON
8900 04:44:19.168926 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8901 04:44:19.172848 DUMMY_READ_FOR_TRACKING: OFF
8902 04:44:19.177171 !!! SPM_CONTROL_AFTERK: OFF
8903 04:44:19.177861 !!! SPM could not control APHY
8904 04:44:19.178925 IMPEDANCE_TRACKING: ON
8905 04:44:19.182356 TEMP_SENSOR: ON
8906 04:44:19.182816 HW_SAVE_FOR_SR: OFF
8907 04:44:19.186171 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8908 04:44:19.188902 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8909 04:44:19.192872 Read ODT Tracking: ON
8910 04:44:19.193443 Refresh Rate DeBounce: ON
8911 04:44:19.195435 DFS_NO_QUEUE_FLUSH: ON
8912 04:44:19.199697 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8913 04:44:19.202545 ENABLE_DFS_RUNTIME_MRW: OFF
8914 04:44:19.203006 DDR_RESERVE_NEW_MODE: ON
8915 04:44:19.208381 MR_CBT_SWITCH_FREQ: ON
8916 04:44:19.209372 =========================
8917 04:44:19.226799 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8918 04:44:19.231005 dram_init: ddr_geometry: 0
8919 04:44:19.248323 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8920 04:44:19.251454 dram_init: dram init end (result: 0)
8921 04:44:19.257894 DRAM-K: Full calibration passed in 23399 msecs
8922 04:44:19.262203 MRC: failed to locate region type 0.
8923 04:44:19.262664 DRAM rank0 size:0x80000000,
8924 04:44:19.264382 DRAM rank1 size=0x80000000
8925 04:44:19.274969 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8926 04:44:19.281451 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8927 04:44:19.288278 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8928 04:44:19.295807 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8929 04:44:19.298350 DRAM rank0 size:0x80000000,
8930 04:44:19.302058 DRAM rank1 size=0x80000000
8931 04:44:19.302768 CBMEM:
8932 04:44:19.304132 IMD: root @ 0xfffff000 254 entries.
8933 04:44:19.307795 IMD: root @ 0xffffec00 62 entries.
8934 04:44:19.311583 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8935 04:44:19.314517 WARNING: RO_VPD is uninitialized or empty.
8936 04:44:19.320693 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8937 04:44:19.327783 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8938 04:44:19.340630 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8939 04:44:19.352350 BS: romstage times (exec / console): total (unknown) / 22943 ms
8940 04:44:19.352969
8941 04:44:19.353345
8942 04:44:19.362051 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8943 04:44:19.365224 ARM64: Exception handlers installed.
8944 04:44:19.368761 ARM64: Testing exception
8945 04:44:19.371747 ARM64: Done test exception
8946 04:44:19.372447 Enumerating buses...
8947 04:44:19.374932 Show all devs... Before device enumeration.
8948 04:44:19.379059 Root Device: enabled 1
8949 04:44:19.381532 CPU_CLUSTER: 0: enabled 1
8950 04:44:19.381991 CPU: 00: enabled 1
8951 04:44:19.385417 Compare with tree...
8952 04:44:19.385877 Root Device: enabled 1
8953 04:44:19.388420 CPU_CLUSTER: 0: enabled 1
8954 04:44:19.391480 CPU: 00: enabled 1
8955 04:44:19.391944 Root Device scanning...
8956 04:44:19.395026 scan_static_bus for Root Device
8957 04:44:19.398172 CPU_CLUSTER: 0 enabled
8958 04:44:19.401652 scan_static_bus for Root Device done
8959 04:44:19.404639 scan_bus: bus Root Device finished in 8 msecs
8960 04:44:19.405370 done
8961 04:44:19.411884 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8962 04:44:19.414553 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8963 04:44:19.421231 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8964 04:44:19.426069 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8965 04:44:19.427967 Allocating resources...
8966 04:44:19.432226 Reading resources...
8967 04:44:19.434481 Root Device read_resources bus 0 link: 0
8968 04:44:19.434939 DRAM rank0 size:0x80000000,
8969 04:44:19.438500 DRAM rank1 size=0x80000000
8970 04:44:19.441473 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8971 04:44:19.444701 CPU: 00 missing read_resources
8972 04:44:19.451717 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8973 04:44:19.455053 Root Device read_resources bus 0 link: 0 done
8974 04:44:19.455612 Done reading resources.
8975 04:44:19.461342 Show resources in subtree (Root Device)...After reading.
8976 04:44:19.464085 Root Device child on link 0 CPU_CLUSTER: 0
8977 04:44:19.467682 CPU_CLUSTER: 0 child on link 0 CPU: 00
8978 04:44:19.477963 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8979 04:44:19.478579 CPU: 00
8980 04:44:19.481669 Root Device assign_resources, bus 0 link: 0
8981 04:44:19.484758 CPU_CLUSTER: 0 missing set_resources
8982 04:44:19.491355 Root Device assign_resources, bus 0 link: 0 done
8983 04:44:19.491927 Done setting resources.
8984 04:44:19.497442 Show resources in subtree (Root Device)...After assigning values.
8985 04:44:19.501070 Root Device child on link 0 CPU_CLUSTER: 0
8986 04:44:19.504023 CPU_CLUSTER: 0 child on link 0 CPU: 00
8987 04:44:19.514058 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8988 04:44:19.514647 CPU: 00
8989 04:44:19.517387 Done allocating resources.
8990 04:44:19.524419 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8991 04:44:19.525053 Enabling resources...
8992 04:44:19.525428 done.
8993 04:44:19.530555 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8994 04:44:19.531117 Initializing devices...
8995 04:44:19.534435 Root Device init
8996 04:44:19.534996 init hardware done!
8997 04:44:19.537762 0x00000018: ctrlr->caps
8998 04:44:19.540557 52.000 MHz: ctrlr->f_max
8999 04:44:19.541158 0.400 MHz: ctrlr->f_min
9000 04:44:19.544369 0x40ff8080: ctrlr->voltages
9001 04:44:19.547391 sclk: 390625
9002 04:44:19.547939 Bus Width = 1
9003 04:44:19.548303 sclk: 390625
9004 04:44:19.550854 Bus Width = 1
9005 04:44:19.551404 Early init status = 3
9006 04:44:19.557034 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9007 04:44:19.560560 in-header: 03 fc 00 00 01 00 00 00
9008 04:44:19.561173 in-data: 00
9009 04:44:19.567674 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9010 04:44:19.570644 in-header: 03 fd 00 00 00 00 00 00
9011 04:44:19.574465 in-data:
9012 04:44:19.577241 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9013 04:44:19.580483 in-header: 03 fc 00 00 01 00 00 00
9014 04:44:19.584599 in-data: 00
9015 04:44:19.587872 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9016 04:44:19.591889 in-header: 03 fd 00 00 00 00 00 00
9017 04:44:19.595296 in-data:
9018 04:44:19.598586 [SSUSB] Setting up USB HOST controller...
9019 04:44:19.601963 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9020 04:44:19.605610 [SSUSB] phy power-on done.
9021 04:44:19.608510 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9022 04:44:19.615299 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9023 04:44:19.618420 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9024 04:44:19.625325 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9025 04:44:19.631883 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9026 04:44:19.638195 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9027 04:44:19.645161 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9028 04:44:19.651415 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9029 04:44:19.655563 SPM: binary array size = 0x9dc
9030 04:44:19.658124 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9031 04:44:19.664511 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9032 04:44:19.672310 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9033 04:44:19.679050 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9034 04:44:19.680977 configure_display: Starting display init
9035 04:44:19.714938 anx7625_power_on_init: Init interface.
9036 04:44:19.718479 anx7625_disable_pd_protocol: Disabled PD feature.
9037 04:44:19.721597 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9038 04:44:19.749909 anx7625_start_dp_work: Secure OCM version=00
9039 04:44:19.753275 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9040 04:44:19.767901 sp_tx_get_edid_block: EDID Block = 1
9041 04:44:19.870058 Extracted contents:
9042 04:44:19.873630 header: 00 ff ff ff ff ff ff 00
9043 04:44:19.876229 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9044 04:44:19.879804 version: 01 04
9045 04:44:19.883610 basic params: 95 1f 11 78 0a
9046 04:44:19.886680 chroma info: 76 90 94 55 54 90 27 21 50 54
9047 04:44:19.890339 established: 00 00 00
9048 04:44:19.896488 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9049 04:44:19.901403 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9050 04:44:19.907478 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9051 04:44:19.913117 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9052 04:44:19.919656 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9053 04:44:19.923755 extensions: 00
9054 04:44:19.924215 checksum: fb
9055 04:44:19.924581
9056 04:44:19.926787 Manufacturer: IVO Model 57d Serial Number 0
9057 04:44:19.930363 Made week 0 of 2020
9058 04:44:19.930926 EDID version: 1.4
9059 04:44:19.933223 Digital display
9060 04:44:19.936261 6 bits per primary color channel
9061 04:44:19.936878 DisplayPort interface
9062 04:44:19.939223 Maximum image size: 31 cm x 17 cm
9063 04:44:19.943338 Gamma: 220%
9064 04:44:19.943898 Check DPMS levels
9065 04:44:19.946703 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9066 04:44:19.953431 First detailed timing is preferred timing
9067 04:44:19.953999 Established timings supported:
9068 04:44:19.955928 Standard timings supported:
9069 04:44:19.959127 Detailed timings
9070 04:44:19.962639 Hex of detail: 383680a07038204018303c0035ae10000019
9071 04:44:19.966095 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9072 04:44:19.972990 0780 0798 07c8 0820 hborder 0
9073 04:44:19.976490 0438 043b 0447 0458 vborder 0
9074 04:44:19.980076 -hsync -vsync
9075 04:44:19.980637 Did detailed timing
9076 04:44:19.986240 Hex of detail: 000000000000000000000000000000000000
9077 04:44:19.989309 Manufacturer-specified data, tag 0
9078 04:44:19.992846 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9079 04:44:19.996170 ASCII string: InfoVision
9080 04:44:19.999740 Hex of detail: 000000fe00523134304e574635205248200a
9081 04:44:20.002809 ASCII string: R140NWF5 RH
9082 04:44:20.003374 Checksum
9083 04:44:20.006056 Checksum: 0xfb (valid)
9084 04:44:20.009106 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9085 04:44:20.013138 DSI data_rate: 832800000 bps
9086 04:44:20.019055 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9087 04:44:20.023057 anx7625_parse_edid: pixelclock(138800).
9088 04:44:20.026008 hactive(1920), hsync(48), hfp(24), hbp(88)
9089 04:44:20.029121 vactive(1080), vsync(12), vfp(3), vbp(17)
9090 04:44:20.032497 anx7625_dsi_config: config dsi.
9091 04:44:20.039836 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9092 04:44:20.052538 anx7625_dsi_config: success to config DSI
9093 04:44:20.056056 anx7625_dp_start: MIPI phy setup OK.
9094 04:44:20.058611 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9095 04:44:20.063352 mtk_ddp_mode_set invalid vrefresh 60
9096 04:44:20.064960 main_disp_path_setup
9097 04:44:20.065433 ovl_layer_smi_id_en
9098 04:44:20.068620 ovl_layer_smi_id_en
9099 04:44:20.069237 ccorr_config
9100 04:44:20.069725 aal_config
9101 04:44:20.072114 gamma_config
9102 04:44:20.072684 postmask_config
9103 04:44:20.075401 dither_config
9104 04:44:20.078502 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9105 04:44:20.085408 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9106 04:44:20.088233 Root Device init finished in 551 msecs
9107 04:44:20.092191 CPU_CLUSTER: 0 init
9108 04:44:20.098452 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9109 04:44:20.104805 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9110 04:44:20.105462 APU_MBOX 0x190000b0 = 0x10001
9111 04:44:20.108341 APU_MBOX 0x190001b0 = 0x10001
9112 04:44:20.111772 APU_MBOX 0x190005b0 = 0x10001
9113 04:44:20.114374 APU_MBOX 0x190006b0 = 0x10001
9114 04:44:20.121248 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9115 04:44:20.131052 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9116 04:44:20.144875 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9117 04:44:20.150238 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9118 04:44:20.162043 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9119 04:44:20.171179 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9120 04:44:20.174687 CPU_CLUSTER: 0 init finished in 81 msecs
9121 04:44:20.177774 Devices initialized
9122 04:44:20.181529 Show all devs... After init.
9123 04:44:20.182092 Root Device: enabled 1
9124 04:44:20.183801 CPU_CLUSTER: 0: enabled 1
9125 04:44:20.187441 CPU: 00: enabled 1
9126 04:44:20.190452 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9127 04:44:20.193796 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9128 04:44:20.197010 ELOG: NV offset 0x57f000 size 0x1000
9129 04:44:20.203997 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9130 04:44:20.211029 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9131 04:44:20.214630 ELOG: Event(17) added with size 13 at 2024-02-04 04:44:22 UTC
9132 04:44:20.221719 out: cmd=0x121: 03 db 21 01 00 00 00 00
9133 04:44:20.224938 in-header: 03 16 00 00 2c 00 00 00
9134 04:44:20.233739 in-data: 4d 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9135 04:44:20.240212 ELOG: Event(A1) added with size 10 at 2024-02-04 04:44:22 UTC
9136 04:44:20.247040 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9137 04:44:20.253256 ELOG: Event(A0) added with size 9 at 2024-02-04 04:44:22 UTC
9138 04:44:20.256778 elog_add_boot_reason: Logged dev mode boot
9139 04:44:20.263764 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9140 04:44:20.264323 Finalize devices...
9141 04:44:20.266833 Devices finalized
9142 04:44:20.270132 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9143 04:44:20.273359 Writing coreboot table at 0xffe64000
9144 04:44:20.277173 0. 000000000010a000-0000000000113fff: RAMSTAGE
9145 04:44:20.284066 1. 0000000040000000-00000000400fffff: RAM
9146 04:44:20.286477 2. 0000000040100000-000000004032afff: RAMSTAGE
9147 04:44:20.290015 3. 000000004032b000-00000000545fffff: RAM
9148 04:44:20.293949 4. 0000000054600000-000000005465ffff: BL31
9149 04:44:20.296477 5. 0000000054660000-00000000ffe63fff: RAM
9150 04:44:20.303294 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9151 04:44:20.306019 7. 0000000100000000-000000013fffffff: RAM
9152 04:44:20.309128 Passing 5 GPIOs to payload:
9153 04:44:20.312806 NAME | PORT | POLARITY | VALUE
9154 04:44:20.320022 EC in RW | 0x000000aa | low | undefined
9155 04:44:20.322972 EC interrupt | 0x00000005 | low | undefined
9156 04:44:20.326850 TPM interrupt | 0x000000ab | high | undefined
9157 04:44:20.332842 SD card detect | 0x00000011 | high | undefined
9158 04:44:20.336344 speaker enable | 0x00000093 | high | undefined
9159 04:44:20.339185 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9160 04:44:20.342519 in-header: 03 f8 00 00 02 00 00 00
9161 04:44:20.346026 in-data: 03 00
9162 04:44:20.349089 ADC[4]: Raw value=668958 ID=5
9163 04:44:20.349549 ADC[3]: Raw value=212549 ID=1
9164 04:44:20.352750 RAM Code: 0x51
9165 04:44:20.356063 ADC[6]: Raw value=74410 ID=0
9166 04:44:20.358970 ADC[5]: Raw value=211812 ID=1
9167 04:44:20.359450 SKU Code: 0x1
9168 04:44:20.365452 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d55
9169 04:44:20.365971 coreboot table: 964 bytes.
9170 04:44:20.369097 IMD ROOT 0. 0xfffff000 0x00001000
9171 04:44:20.372493 IMD SMALL 1. 0xffffe000 0x00001000
9172 04:44:20.375625 RO MCACHE 2. 0xffffc000 0x00001104
9173 04:44:20.378902 CONSOLE 3. 0xfff7c000 0x00080000
9174 04:44:20.382452 FMAP 4. 0xfff7b000 0x00000452
9175 04:44:20.386187 TIME STAMP 5. 0xfff7a000 0x00000910
9176 04:44:20.388630 VBOOT WORK 6. 0xfff66000 0x00014000
9177 04:44:20.392149 RAMOOPS 7. 0xffe66000 0x00100000
9178 04:44:20.395599 COREBOOT 8. 0xffe64000 0x00002000
9179 04:44:20.399437 IMD small region:
9180 04:44:20.402392 IMD ROOT 0. 0xffffec00 0x00000400
9181 04:44:20.405685 VPD 1. 0xffffeb80 0x0000006c
9182 04:44:20.408842 MMC STATUS 2. 0xffffeb60 0x00000004
9183 04:44:20.412229 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9184 04:44:20.415396 Probing TPM: done!
9185 04:44:20.419558 Connected to device vid:did:rid of 1ae0:0028:00
9186 04:44:20.430256 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9187 04:44:20.434020 Initialized TPM device CR50 revision 0
9188 04:44:20.437453 Checking cr50 for pending updates
9189 04:44:20.441326 Reading cr50 TPM mode
9190 04:44:20.449494 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9191 04:44:20.455904 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9192 04:44:20.495688 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9193 04:44:20.499004 Checking segment from ROM address 0x40100000
9194 04:44:20.502154 Checking segment from ROM address 0x4010001c
9195 04:44:20.508645 Loading segment from ROM address 0x40100000
9196 04:44:20.509385 code (compression=0)
9197 04:44:20.519452 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9198 04:44:20.526763 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9199 04:44:20.527318 it's not compressed!
9200 04:44:20.533132 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9201 04:44:20.535552 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9202 04:44:20.556000 Loading segment from ROM address 0x4010001c
9203 04:44:20.556554 Entry Point 0x80000000
9204 04:44:20.559489 Loaded segments
9205 04:44:20.563771 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9206 04:44:20.569643 Jumping to boot code at 0x80000000(0xffe64000)
9207 04:44:20.576645 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9208 04:44:20.582799 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9209 04:44:20.591220 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9210 04:44:20.594500 Checking segment from ROM address 0x40100000
9211 04:44:20.597351 Checking segment from ROM address 0x4010001c
9212 04:44:20.603879 Loading segment from ROM address 0x40100000
9213 04:44:20.604437 code (compression=1)
9214 04:44:20.610304 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9215 04:44:20.620526 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9216 04:44:20.621145 using LZMA
9217 04:44:20.629026 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9218 04:44:20.636156 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9219 04:44:20.638916 Loading segment from ROM address 0x4010001c
9220 04:44:20.639382 Entry Point 0x54601000
9221 04:44:20.641903 Loaded segments
9222 04:44:20.645420 NOTICE: MT8192 bl31_setup
9223 04:44:20.652172 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9224 04:44:20.656075 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9225 04:44:20.659601 WARNING: region 0:
9226 04:44:20.662710 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9227 04:44:20.663275 WARNING: region 1:
9228 04:44:20.671167 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9229 04:44:20.673181 WARNING: region 2:
9230 04:44:20.675843 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9231 04:44:20.679165 WARNING: region 3:
9232 04:44:20.682830 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9233 04:44:20.685512 WARNING: region 4:
9234 04:44:20.692885 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9235 04:44:20.693454 WARNING: region 5:
9236 04:44:20.695772 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9237 04:44:20.699350 WARNING: region 6:
9238 04:44:20.703184 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9239 04:44:20.705820 WARNING: region 7:
9240 04:44:20.709012 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9241 04:44:20.716407 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9242 04:44:20.719309 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9243 04:44:20.723440 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9244 04:44:20.729603 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9245 04:44:20.732043 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9246 04:44:20.735408 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9247 04:44:20.741942 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9248 04:44:20.745252 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9249 04:44:20.751901 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9250 04:44:20.756138 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9251 04:44:20.758577 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9252 04:44:20.765404 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9253 04:44:20.768385 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9254 04:44:20.773459 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9255 04:44:20.780598 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9256 04:44:20.783366 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9257 04:44:20.789153 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9258 04:44:20.792482 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9259 04:44:20.795126 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9260 04:44:20.802200 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9261 04:44:20.805594 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9262 04:44:20.809051 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9263 04:44:20.815632 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9264 04:44:20.819423 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9265 04:44:20.825485 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9266 04:44:20.828846 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9267 04:44:20.835316 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9268 04:44:20.838896 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9269 04:44:20.841931 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9270 04:44:20.849254 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9271 04:44:20.852197 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9272 04:44:20.855315 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9273 04:44:20.862920 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9274 04:44:20.865065 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9275 04:44:20.868818 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9276 04:44:20.871965 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9277 04:44:20.878925 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9278 04:44:20.882101 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9279 04:44:20.885139 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9280 04:44:20.888796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9281 04:44:20.895662 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9282 04:44:20.899432 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9283 04:44:20.902493 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9284 04:44:20.906689 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9285 04:44:20.912150 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9286 04:44:20.915421 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9287 04:44:20.918808 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9288 04:44:20.921926 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9289 04:44:20.929023 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9290 04:44:20.932211 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9291 04:44:20.939059 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9292 04:44:20.941981 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9293 04:44:20.949083 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9294 04:44:20.952097 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9295 04:44:20.956038 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9296 04:44:20.961751 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9297 04:44:20.965809 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9298 04:44:20.972062 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9299 04:44:20.976103 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9300 04:44:20.982369 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9301 04:44:20.985460 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9302 04:44:20.988810 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9303 04:44:20.995537 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9304 04:44:20.998394 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9305 04:44:21.005371 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9306 04:44:21.008411 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9307 04:44:21.015831 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9308 04:44:21.020187 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9309 04:44:21.022348 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9310 04:44:21.029166 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9311 04:44:21.031908 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9312 04:44:21.038941 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9313 04:44:21.042920 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9314 04:44:21.048687 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9315 04:44:21.052114 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9316 04:44:21.055347 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9317 04:44:21.061769 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9318 04:44:21.065410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9319 04:44:21.072374 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9320 04:44:21.076314 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9321 04:44:21.082507 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9322 04:44:21.085920 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9323 04:44:21.091930 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9324 04:44:21.095818 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9325 04:44:21.098859 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9326 04:44:21.106184 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9327 04:44:21.108521 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9328 04:44:21.115731 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9329 04:44:21.118987 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9330 04:44:21.122141 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9331 04:44:21.129428 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9332 04:44:21.132961 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9333 04:44:21.139439 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9334 04:44:21.142435 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9335 04:44:21.149520 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9336 04:44:21.151476 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9337 04:44:21.155117 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9338 04:44:21.162292 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9339 04:44:21.165665 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9340 04:44:21.168534 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9341 04:44:21.172354 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9342 04:44:21.179461 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9343 04:44:21.181890 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9344 04:44:21.188565 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9345 04:44:21.191807 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9346 04:44:21.196200 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9347 04:44:21.201959 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9348 04:44:21.205654 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9349 04:44:21.212059 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9350 04:44:21.215423 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9351 04:44:21.218397 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9352 04:44:21.224665 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9353 04:44:21.227925 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9354 04:44:21.235534 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9355 04:44:21.238744 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9356 04:44:21.242207 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9357 04:44:21.248809 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9358 04:44:21.253190 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9359 04:44:21.255293 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9360 04:44:21.262491 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9361 04:44:21.266687 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9362 04:44:21.268191 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9363 04:44:21.271361 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9364 04:44:21.277861 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9365 04:44:21.281749 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9366 04:44:21.284614 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9367 04:44:21.291936 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9368 04:44:21.294391 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9369 04:44:21.301119 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9370 04:44:21.305374 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9371 04:44:21.308563 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9372 04:44:21.314618 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9373 04:44:21.318124 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9374 04:44:21.321668 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9375 04:44:21.328551 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9376 04:44:21.331636 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9377 04:44:21.338792 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9378 04:44:21.341437 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9379 04:44:21.345425 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9380 04:44:21.351833 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9381 04:44:21.354500 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9382 04:44:21.362514 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9383 04:44:21.364861 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9384 04:44:21.368444 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9385 04:44:21.375818 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9386 04:44:21.379354 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9387 04:44:21.381482 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9388 04:44:21.388086 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9389 04:44:21.391243 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9390 04:44:21.398762 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9391 04:44:21.401281 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9392 04:44:21.404438 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9393 04:44:21.411197 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9394 04:44:21.414642 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9395 04:44:21.421218 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9396 04:44:21.424368 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9397 04:44:21.427811 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9398 04:44:21.434533 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9399 04:44:21.438322 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9400 04:44:21.444697 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9401 04:44:21.448180 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9402 04:44:21.450981 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9403 04:44:21.457658 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9404 04:44:21.461130 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9405 04:44:21.467674 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9406 04:44:21.470989 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9407 04:44:21.474474 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9408 04:44:21.481604 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9409 04:44:21.484963 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9410 04:44:21.488331 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9411 04:44:21.494155 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9412 04:44:21.497829 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9413 04:44:21.504315 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9414 04:44:21.507143 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9415 04:44:21.510632 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9416 04:44:21.517234 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9417 04:44:21.520541 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9418 04:44:21.527978 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9419 04:44:21.530775 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9420 04:44:21.534284 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9421 04:44:21.540887 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9422 04:44:21.543905 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9423 04:44:21.550401 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9424 04:44:21.554400 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9425 04:44:21.556980 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9426 04:44:21.563812 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9427 04:44:21.567770 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9428 04:44:21.573964 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9429 04:44:21.577181 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9430 04:44:21.581065 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9431 04:44:21.587813 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9432 04:44:21.590266 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9433 04:44:21.596861 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9434 04:44:21.600182 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9435 04:44:21.606397 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9436 04:44:21.610048 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9437 04:44:21.613532 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9438 04:44:21.619297 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9439 04:44:21.623368 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9440 04:44:21.629532 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9441 04:44:21.633099 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9442 04:44:21.639664 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9443 04:44:21.642682 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9444 04:44:21.646356 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9445 04:44:21.653237 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9446 04:44:21.656075 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9447 04:44:21.663110 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9448 04:44:21.666062 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9449 04:44:21.672945 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9450 04:44:21.676068 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9451 04:44:21.679797 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9452 04:44:21.685664 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9453 04:44:21.689196 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9454 04:44:21.695666 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9455 04:44:21.699024 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9456 04:44:21.702693 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9457 04:44:21.708951 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9458 04:44:21.712408 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9459 04:44:21.718777 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9460 04:44:21.721745 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9461 04:44:21.728493 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9462 04:44:21.732021 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9463 04:44:21.735344 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9464 04:44:21.742142 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9465 04:44:21.745358 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9466 04:44:21.752656 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9467 04:44:21.755749 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9468 04:44:21.761833 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9469 04:44:21.765280 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9470 04:44:21.768157 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9471 04:44:21.771877 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9472 04:44:21.778266 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9473 04:44:21.781916 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9474 04:44:21.785618 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9475 04:44:21.788438 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9476 04:44:21.795167 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9477 04:44:21.799164 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9478 04:44:21.806020 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9479 04:44:21.808661 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9480 04:44:21.811400 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9481 04:44:21.818705 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9482 04:44:21.821475 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9483 04:44:21.824809 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9484 04:44:21.831422 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9485 04:44:21.834752 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9486 04:44:21.841200 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9487 04:44:21.844703 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9488 04:44:21.848112 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9489 04:44:21.854464 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9490 04:44:21.858762 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9491 04:44:21.861917 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9492 04:44:21.868045 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9493 04:44:21.871842 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9494 04:44:21.875129 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9495 04:44:21.881698 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9496 04:44:21.884337 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9497 04:44:21.891155 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9498 04:44:21.894441 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9499 04:44:21.897752 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9500 04:44:21.905456 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9501 04:44:21.907485 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9502 04:44:21.911033 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9503 04:44:21.917175 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9504 04:44:21.920519 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9505 04:44:21.928183 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9506 04:44:21.931155 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9507 04:44:21.933376 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9508 04:44:21.941045 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9509 04:44:21.943772 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9510 04:44:21.947466 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9511 04:44:21.950740 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9512 04:44:21.957323 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9513 04:44:21.960210 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9514 04:44:21.963767 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9515 04:44:21.966933 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9516 04:44:21.973419 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9517 04:44:21.976663 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9518 04:44:21.980485 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9519 04:44:21.983590 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9520 04:44:21.991095 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9521 04:44:21.994157 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9522 04:44:21.997409 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9523 04:44:22.004286 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9524 04:44:22.006474 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9525 04:44:22.013077 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9526 04:44:22.016747 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9527 04:44:22.021048 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9528 04:44:22.026980 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9529 04:44:22.029397 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9530 04:44:22.036699 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9531 04:44:22.039512 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9532 04:44:22.043171 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9533 04:44:22.050027 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9534 04:44:22.052840 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9535 04:44:22.060303 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9536 04:44:22.062621 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9537 04:44:22.069345 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9538 04:44:22.073182 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9539 04:44:22.075852 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9540 04:44:22.082520 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9541 04:44:22.086146 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9542 04:44:22.092902 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9543 04:44:22.095733 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9544 04:44:22.102577 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9545 04:44:22.105941 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9546 04:44:22.109548 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9547 04:44:22.116204 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9548 04:44:22.118685 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9549 04:44:22.125581 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9550 04:44:22.128928 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9551 04:44:22.133679 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9552 04:44:22.139139 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9553 04:44:22.142435 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9554 04:44:22.149172 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9555 04:44:22.152206 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9556 04:44:22.155676 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9557 04:44:22.161927 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9558 04:44:22.165219 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9559 04:44:22.172101 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9560 04:44:22.175301 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9561 04:44:22.181307 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9562 04:44:22.185195 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9563 04:44:22.189356 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9564 04:44:22.196583 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9565 04:44:22.198169 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9566 04:44:22.205213 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9567 04:44:22.208621 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9568 04:44:22.211220 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9569 04:44:22.218447 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9570 04:44:22.222344 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9571 04:44:22.227962 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9572 04:44:22.231296 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9573 04:44:22.234831 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9574 04:44:22.241471 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9575 04:44:22.244958 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9576 04:44:22.251206 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9577 04:44:22.255065 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9578 04:44:22.257353 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9579 04:44:22.264568 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9580 04:44:22.268857 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9581 04:44:22.274401 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9582 04:44:22.277821 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9583 04:44:22.284059 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9584 04:44:22.287476 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9585 04:44:22.293729 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9586 04:44:22.297016 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9587 04:44:22.300661 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9588 04:44:22.307925 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9589 04:44:22.310699 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9590 04:44:22.317134 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9591 04:44:22.321593 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9592 04:44:22.323580 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9593 04:44:22.330302 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9594 04:44:22.335264 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9595 04:44:22.340407 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9596 04:44:22.344343 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9597 04:44:22.351527 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9598 04:44:22.354060 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9599 04:44:22.356543 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9600 04:44:22.363324 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9601 04:44:22.366912 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9602 04:44:22.373264 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9603 04:44:22.376647 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9604 04:44:22.383788 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9605 04:44:22.386687 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9606 04:44:22.393268 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9607 04:44:22.396625 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9608 04:44:22.400137 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9609 04:44:22.406361 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9610 04:44:22.409437 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9611 04:44:22.416458 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9612 04:44:22.419450 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9613 04:44:22.426334 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9614 04:44:22.429750 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9615 04:44:22.436074 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9616 04:44:22.439680 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9617 04:44:22.445673 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9618 04:44:22.449366 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9619 04:44:22.452298 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9620 04:44:22.458613 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9621 04:44:22.462351 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9622 04:44:22.468981 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9623 04:44:22.472516 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9624 04:44:22.478457 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9625 04:44:22.482121 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9626 04:44:22.485469 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9627 04:44:22.492183 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9628 04:44:22.495284 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9629 04:44:22.501942 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9630 04:44:22.505196 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9631 04:44:22.512045 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9632 04:44:22.514704 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9633 04:44:22.522574 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9634 04:44:22.524975 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9635 04:44:22.528850 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9636 04:44:22.535052 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9637 04:44:22.538081 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9638 04:44:22.544393 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9639 04:44:22.548017 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9640 04:44:22.554479 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9641 04:44:22.557694 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9642 04:44:22.560821 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9643 04:44:22.567864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9644 04:44:22.571135 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9645 04:44:22.577451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9646 04:44:22.580504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9647 04:44:22.587335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9648 04:44:22.590664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9649 04:44:22.597200 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9650 04:44:22.601236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9651 04:44:22.607342 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9652 04:44:22.610569 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9653 04:44:22.617182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9654 04:44:22.620205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9655 04:44:22.627202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9656 04:44:22.631654 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9657 04:44:22.637431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9658 04:44:22.640453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9659 04:44:22.647504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9660 04:44:22.650398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9661 04:44:22.656791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9662 04:44:22.660318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9663 04:44:22.667349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9664 04:44:22.670763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9665 04:44:22.677228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9666 04:44:22.680581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9667 04:44:22.686745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9668 04:44:22.690336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9669 04:44:22.697533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9670 04:44:22.700592 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9671 04:44:22.706306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9672 04:44:22.709785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9673 04:44:22.716121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9674 04:44:22.719631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9675 04:44:22.723342 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9676 04:44:22.725814 INFO: [APUAPC] vio 0
9677 04:44:22.732512 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9678 04:44:22.735810 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9679 04:44:22.739549 INFO: [APUAPC] D0_APC_0: 0x400510
9680 04:44:22.742583 INFO: [APUAPC] D0_APC_1: 0x0
9681 04:44:22.746111 INFO: [APUAPC] D0_APC_2: 0x1540
9682 04:44:22.749331 INFO: [APUAPC] D0_APC_3: 0x0
9683 04:44:22.752687 INFO: [APUAPC] D1_APC_0: 0xffffffff
9684 04:44:22.756504 INFO: [APUAPC] D1_APC_1: 0xffffffff
9685 04:44:22.759576 INFO: [APUAPC] D1_APC_2: 0x3fffff
9686 04:44:22.762376 INFO: [APUAPC] D1_APC_3: 0x0
9687 04:44:22.766247 INFO: [APUAPC] D2_APC_0: 0xffffffff
9688 04:44:22.769486 INFO: [APUAPC] D2_APC_1: 0xffffffff
9689 04:44:22.772101 INFO: [APUAPC] D2_APC_2: 0x3fffff
9690 04:44:22.775557 INFO: [APUAPC] D2_APC_3: 0x0
9691 04:44:22.779372 INFO: [APUAPC] D3_APC_0: 0xffffffff
9692 04:44:22.781859 INFO: [APUAPC] D3_APC_1: 0xffffffff
9693 04:44:22.785180 INFO: [APUAPC] D3_APC_2: 0x3fffff
9694 04:44:22.785644 INFO: [APUAPC] D3_APC_3: 0x0
9695 04:44:22.792217 INFO: [APUAPC] D4_APC_0: 0xffffffff
9696 04:44:22.796046 INFO: [APUAPC] D4_APC_1: 0xffffffff
9697 04:44:22.798704 INFO: [APUAPC] D4_APC_2: 0x3fffff
9698 04:44:22.799307 INFO: [APUAPC] D4_APC_3: 0x0
9699 04:44:22.801882 INFO: [APUAPC] D5_APC_0: 0xffffffff
9700 04:44:22.808464 INFO: [APUAPC] D5_APC_1: 0xffffffff
9701 04:44:22.812128 INFO: [APUAPC] D5_APC_2: 0x3fffff
9702 04:44:22.812592 INFO: [APUAPC] D5_APC_3: 0x0
9703 04:44:22.815001 INFO: [APUAPC] D6_APC_0: 0xffffffff
9704 04:44:22.818729 INFO: [APUAPC] D6_APC_1: 0xffffffff
9705 04:44:22.821552 INFO: [APUAPC] D6_APC_2: 0x3fffff
9706 04:44:22.825026 INFO: [APUAPC] D6_APC_3: 0x0
9707 04:44:22.828443 INFO: [APUAPC] D7_APC_0: 0xffffffff
9708 04:44:22.831767 INFO: [APUAPC] D7_APC_1: 0xffffffff
9709 04:44:22.835590 INFO: [APUAPC] D7_APC_2: 0x3fffff
9710 04:44:22.838857 INFO: [APUAPC] D7_APC_3: 0x0
9711 04:44:22.841968 INFO: [APUAPC] D8_APC_0: 0xffffffff
9712 04:44:22.844861 INFO: [APUAPC] D8_APC_1: 0xffffffff
9713 04:44:22.848313 INFO: [APUAPC] D8_APC_2: 0x3fffff
9714 04:44:22.852229 INFO: [APUAPC] D8_APC_3: 0x0
9715 04:44:22.855293 INFO: [APUAPC] D9_APC_0: 0xffffffff
9716 04:44:22.858251 INFO: [APUAPC] D9_APC_1: 0xffffffff
9717 04:44:22.862484 INFO: [APUAPC] D9_APC_2: 0x3fffff
9718 04:44:22.864766 INFO: [APUAPC] D9_APC_3: 0x0
9719 04:44:22.867845 INFO: [APUAPC] D10_APC_0: 0xffffffff
9720 04:44:22.871589 INFO: [APUAPC] D10_APC_1: 0xffffffff
9721 04:44:22.874490 INFO: [APUAPC] D10_APC_2: 0x3fffff
9722 04:44:22.877997 INFO: [APUAPC] D10_APC_3: 0x0
9723 04:44:22.881338 INFO: [APUAPC] D11_APC_0: 0xffffffff
9724 04:44:22.886103 INFO: [APUAPC] D11_APC_1: 0xffffffff
9725 04:44:22.887609 INFO: [APUAPC] D11_APC_2: 0x3fffff
9726 04:44:22.891958 INFO: [APUAPC] D11_APC_3: 0x0
9727 04:44:22.894911 INFO: [APUAPC] D12_APC_0: 0xffffffff
9728 04:44:22.898301 INFO: [APUAPC] D12_APC_1: 0xffffffff
9729 04:44:22.901517 INFO: [APUAPC] D12_APC_2: 0x3fffff
9730 04:44:22.904895 INFO: [APUAPC] D12_APC_3: 0x0
9731 04:44:22.908143 INFO: [APUAPC] D13_APC_0: 0xffffffff
9732 04:44:22.911729 INFO: [APUAPC] D13_APC_1: 0xffffffff
9733 04:44:22.914516 INFO: [APUAPC] D13_APC_2: 0x3fffff
9734 04:44:22.918288 INFO: [APUAPC] D13_APC_3: 0x0
9735 04:44:22.921405 INFO: [APUAPC] D14_APC_0: 0xffffffff
9736 04:44:22.924187 INFO: [APUAPC] D14_APC_1: 0xffffffff
9737 04:44:22.927680 INFO: [APUAPC] D14_APC_2: 0x3fffff
9738 04:44:22.930796 INFO: [APUAPC] D14_APC_3: 0x0
9739 04:44:22.934354 INFO: [APUAPC] D15_APC_0: 0xffffffff
9740 04:44:22.937547 INFO: [APUAPC] D15_APC_1: 0xffffffff
9741 04:44:22.941070 INFO: [APUAPC] D15_APC_2: 0x3fffff
9742 04:44:22.945337 INFO: [APUAPC] D15_APC_3: 0x0
9743 04:44:22.948233 INFO: [APUAPC] APC_CON: 0x4
9744 04:44:22.950897 INFO: [NOCDAPC] D0_APC_0: 0x0
9745 04:44:22.954080 INFO: [NOCDAPC] D0_APC_1: 0x0
9746 04:44:22.957245 INFO: [NOCDAPC] D1_APC_0: 0x0
9747 04:44:22.960817 INFO: [NOCDAPC] D1_APC_1: 0xfff
9748 04:44:22.963781 INFO: [NOCDAPC] D2_APC_0: 0x0
9749 04:44:22.967429 INFO: [NOCDAPC] D2_APC_1: 0xfff
9750 04:44:22.967888 INFO: [NOCDAPC] D3_APC_0: 0x0
9751 04:44:22.970670 INFO: [NOCDAPC] D3_APC_1: 0xfff
9752 04:44:22.974012 INFO: [NOCDAPC] D4_APC_0: 0x0
9753 04:44:22.977264 INFO: [NOCDAPC] D4_APC_1: 0xfff
9754 04:44:22.980160 INFO: [NOCDAPC] D5_APC_0: 0x0
9755 04:44:22.984374 INFO: [NOCDAPC] D5_APC_1: 0xfff
9756 04:44:22.987417 INFO: [NOCDAPC] D6_APC_0: 0x0
9757 04:44:22.991101 INFO: [NOCDAPC] D6_APC_1: 0xfff
9758 04:44:22.994066 INFO: [NOCDAPC] D7_APC_0: 0x0
9759 04:44:22.997795 INFO: [NOCDAPC] D7_APC_1: 0xfff
9760 04:44:23.000182 INFO: [NOCDAPC] D8_APC_0: 0x0
9761 04:44:23.003866 INFO: [NOCDAPC] D8_APC_1: 0xfff
9762 04:44:23.004417 INFO: [NOCDAPC] D9_APC_0: 0x0
9763 04:44:23.006738 INFO: [NOCDAPC] D9_APC_1: 0xfff
9764 04:44:23.010470 INFO: [NOCDAPC] D10_APC_0: 0x0
9765 04:44:23.014185 INFO: [NOCDAPC] D10_APC_1: 0xfff
9766 04:44:23.016704 INFO: [NOCDAPC] D11_APC_0: 0x0
9767 04:44:23.021345 INFO: [NOCDAPC] D11_APC_1: 0xfff
9768 04:44:23.023355 INFO: [NOCDAPC] D12_APC_0: 0x0
9769 04:44:23.027718 INFO: [NOCDAPC] D12_APC_1: 0xfff
9770 04:44:23.030407 INFO: [NOCDAPC] D13_APC_0: 0x0
9771 04:44:23.033943 INFO: [NOCDAPC] D13_APC_1: 0xfff
9772 04:44:23.037036 INFO: [NOCDAPC] D14_APC_0: 0x0
9773 04:44:23.040236 INFO: [NOCDAPC] D14_APC_1: 0xfff
9774 04:44:23.043866 INFO: [NOCDAPC] D15_APC_0: 0x0
9775 04:44:23.046607 INFO: [NOCDAPC] D15_APC_1: 0xfff
9776 04:44:23.050409 INFO: [NOCDAPC] APC_CON: 0x4
9777 04:44:23.054418 INFO: [APUAPC] set_apusys_apc done
9778 04:44:23.054976 INFO: [DEVAPC] devapc_init done
9779 04:44:23.059684 INFO: GICv3 without legacy support detected.
9780 04:44:23.063300 INFO: ARM GICv3 driver initialized in EL3
9781 04:44:23.066657 INFO: Maximum SPI INTID supported: 639
9782 04:44:23.069607 INFO: BL31: Initializing runtime services
9783 04:44:23.076413 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9784 04:44:23.079938 INFO: SPM: enable CPC mode
9785 04:44:23.083248 INFO: mcdi ready for mcusys-off-idle and system suspend
9786 04:44:23.089696 INFO: BL31: Preparing for EL3 exit to normal world
9787 04:44:23.092873 INFO: Entry point address = 0x80000000
9788 04:44:23.095888 INFO: SPSR = 0x8
9789 04:44:23.101901
9790 04:44:23.102456
9791 04:44:23.102834
9792 04:44:23.104003 Starting depthcharge on Spherion...
9793 04:44:23.104457
9794 04:44:23.104869 Wipe memory regions:
9795 04:44:23.105214
9796 04:44:23.107806 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9797 04:44:23.108349 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9798 04:44:23.108841 Setting prompt string to ['asurada:']
9799 04:44:23.109293 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9800 04:44:23.110251 [0x00000040000000, 0x00000054600000)
9801 04:44:23.229410
9802 04:44:23.229961 [0x00000054660000, 0x00000080000000)
9803 04:44:23.489881
9804 04:44:23.490418 [0x000000821a7280, 0x000000ffe64000)
9805 04:44:24.234829
9806 04:44:24.235378 [0x00000100000000, 0x00000140000000)
9807 04:44:24.616391
9808 04:44:24.619565 Initializing XHCI USB controller at 0x11200000.
9809 04:44:25.656961
9810 04:44:25.660533 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9811 04:44:25.661312
9812 04:44:25.661700
9813 04:44:25.662042
9814 04:44:25.662856 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9816 04:44:25.764318 asurada: tftpboot 192.168.201.1 12699811/tftp-deploy-eb0jq5zd/kernel/image.itb 12699811/tftp-deploy-eb0jq5zd/kernel/cmdline
9817 04:44:25.765020 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9818 04:44:25.765651 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9819 04:44:25.769765 tftpboot 192.168.201.1 12699811/tftp-deploy-eb0jq5zd/kernel/image.ittp-deploy-eb0jq5zd/kernel/cmdline
9820 04:44:25.770232
9821 04:44:25.770592 Waiting for link
9822 04:44:25.930440
9823 04:44:25.930990 R8152: Initializing
9824 04:44:25.931357
9825 04:44:25.933989 Version 9 (ocp_data = 6010)
9826 04:44:25.934444
9827 04:44:25.937487 R8152: Done initializing
9828 04:44:25.938034
9829 04:44:25.938398 Adding net device
9830 04:44:27.902432
9831 04:44:27.902981 done.
9832 04:44:27.903345
9833 04:44:27.903687 MAC: 00:e0:4c:68:03:bd
9834 04:44:27.904015
9835 04:44:27.905728 Sending DHCP discover... done.
9836 04:44:27.906182
9837 04:44:27.908940 Waiting for reply... done.
9838 04:44:27.909392
9839 04:44:27.912961 Sending DHCP request... done.
9840 04:44:27.913409
9841 04:44:27.915470 Waiting for reply... done.
9842 04:44:27.915923
9843 04:44:27.916281 My ip is 192.168.201.16
9844 04:44:27.916615
9845 04:44:27.918608 The DHCP server ip is 192.168.201.1
9846 04:44:27.919064
9847 04:44:27.923180 TFTP server IP predefined by user: 192.168.201.1
9848 04:44:27.926804
9849 04:44:27.932574 Bootfile predefined by user: 12699811/tftp-deploy-eb0jq5zd/kernel/image.itb
9850 04:44:27.933200
9851 04:44:27.933577 Sending tftp read request... done.
9852 04:44:27.933920
9853 04:44:27.941737 Waiting for the transfer...
9854 04:44:27.942192
9855 04:44:28.261457 00000000 ################################################################
9856 04:44:28.261603
9857 04:44:28.542040 00080000 ################################################################
9858 04:44:28.542178
9859 04:44:28.827919 00100000 ################################################################
9860 04:44:28.828083
9861 04:44:29.101006 00180000 ################################################################
9862 04:44:29.101141
9863 04:44:29.370763 00200000 ################################################################
9864 04:44:29.370897
9865 04:44:29.651379 00280000 ################################################################
9866 04:44:29.651559
9867 04:44:29.920145 00300000 ################################################################
9868 04:44:29.920280
9869 04:44:30.204407 00380000 ################################################################
9870 04:44:30.204548
9871 04:44:30.475019 00400000 ################################################################
9872 04:44:30.475175
9873 04:44:30.749305 00480000 ################################################################
9874 04:44:30.749446
9875 04:44:31.007158 00500000 ################################################################
9876 04:44:31.007296
9877 04:44:31.288159 00580000 ################################################################
9878 04:44:31.288295
9879 04:44:31.551699 00600000 ################################################################
9880 04:44:31.551843
9881 04:44:31.817835 00680000 ################################################################
9882 04:44:31.817969
9883 04:44:32.112883 00700000 ################################################################
9884 04:44:32.113020
9885 04:44:32.384607 00780000 ################################################################
9886 04:44:32.384782
9887 04:44:32.659194 00800000 ################################################################
9888 04:44:32.659332
9889 04:44:32.936554 00880000 ################################################################
9890 04:44:32.936696
9891 04:44:33.216293 00900000 ################################################################
9892 04:44:33.216438
9893 04:44:33.492291 00980000 ################################################################
9894 04:44:33.492424
9895 04:44:33.774758 00a00000 ################################################################
9896 04:44:33.774891
9897 04:44:34.041082 00a80000 ################################################################
9898 04:44:34.041219
9899 04:44:34.322313 00b00000 ################################################################
9900 04:44:34.322453
9901 04:44:34.594727 00b80000 ################################################################
9902 04:44:34.594863
9903 04:44:34.881680 00c00000 ################################################################
9904 04:44:34.881815
9905 04:44:35.165576 00c80000 ################################################################
9906 04:44:35.165722
9907 04:44:35.447634 00d00000 ################################################################
9908 04:44:35.447770
9909 04:44:35.716528 00d80000 ################################################################
9910 04:44:35.716667
9911 04:44:35.999070 00e00000 ################################################################
9912 04:44:35.999206
9913 04:44:36.264541 00e80000 ################################################################
9914 04:44:36.264679
9915 04:44:36.551417 00f00000 ################################################################
9916 04:44:36.551571
9917 04:44:36.845986 00f80000 ################################################################
9918 04:44:36.846144
9919 04:44:37.132593 01000000 ################################################################
9920 04:44:37.132780
9921 04:44:37.411582 01080000 ################################################################
9922 04:44:37.411723
9923 04:44:37.708821 01100000 ################################################################
9924 04:44:37.708960
9925 04:44:37.971312 01180000 ################################################################
9926 04:44:37.971446
9927 04:44:38.251897 01200000 ################################################################
9928 04:44:38.252040
9929 04:44:38.525622 01280000 ################################################################
9930 04:44:38.525764
9931 04:44:38.798711 01300000 ################################################################
9932 04:44:38.798844
9933 04:44:39.085860 01380000 ################################################################
9934 04:44:39.085995
9935 04:44:39.361292 01400000 ################################################################
9936 04:44:39.361428
9937 04:44:39.627245 01480000 ################################################################
9938 04:44:39.627379
9939 04:44:39.877871 01500000 ################################################################
9940 04:44:39.878005
9941 04:44:40.167907 01580000 ################################################################
9942 04:44:40.168045
9943 04:44:40.462245 01600000 ################################################################
9944 04:44:40.462388
9945 04:44:40.721952 01680000 ################################################################
9946 04:44:40.722099
9947 04:44:40.973342 01700000 ################################################################
9948 04:44:40.973473
9949 04:44:41.265351 01780000 ################################################################
9950 04:44:41.265481
9951 04:44:41.559143 01800000 ################################################################
9952 04:44:41.559279
9953 04:44:41.842563 01880000 ################################################################
9954 04:44:41.842701
9955 04:44:42.107954 01900000 ################################################################
9956 04:44:42.108085
9957 04:44:42.372343 01980000 ################################################################
9958 04:44:42.372465
9959 04:44:42.623587 01a00000 ################################################################
9960 04:44:42.623733
9961 04:44:42.897300 01a80000 ################################################################
9962 04:44:42.897437
9963 04:44:43.180557 01b00000 ################################################################
9964 04:44:43.180694
9965 04:44:43.441289 01b80000 ################################################################
9966 04:44:43.441429
9967 04:44:43.691340 01c00000 ################################################################
9968 04:44:43.691489
9969 04:44:43.699298 01c80000 ## done.
9970 04:44:43.699408
9971 04:44:43.703392 The bootfile was 29898514 bytes long.
9972 04:44:43.703559
9973 04:44:43.703637 Sending tftp read request... done.
9974 04:44:43.706303
9975 04:44:43.706503 Waiting for the transfer...
9976 04:44:43.706609
9977 04:44:43.709656 00000000 # done.
9978 04:44:43.709750
9979 04:44:43.716074 Command line loaded dynamically from TFTP file: 12699811/tftp-deploy-eb0jq5zd/kernel/cmdline
9980 04:44:43.716260
9981 04:44:43.739180 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12699811/extract-nfsrootfs-gta4j95_,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9982 04:44:43.739445
9983 04:44:43.739626 Loading FIT.
9984 04:44:43.739782
9985 04:44:43.743383 Image ramdisk-1 has 17800695 bytes.
9986 04:44:43.743572
9987 04:44:43.746550 Image fdt-1 has 47278 bytes.
9988 04:44:43.746860
9989 04:44:43.749400 Image kernel-1 has 12048508 bytes.
9990 04:44:43.749714
9991 04:44:43.759354 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9992 04:44:43.759795
9993 04:44:43.776450 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9994 04:44:43.777262
9995 04:44:43.783139 Choosing best match conf-1 for compat google,spherion-rev3.
9996 04:44:43.783699
9997 04:44:43.789206 Connected to device vid:did:rid of 1ae0:0028:00
9998 04:44:43.796815
9999 04:44:43.799627 tpm_get_response: command 0x17b, return code 0x0
10000 04:44:43.800086
10001 04:44:43.803181 ec_init: CrosEC protocol v3 supported (256, 248)
10002 04:44:43.806955
10003 04:44:43.810456 tpm_cleanup: add release locality here.
10004 04:44:43.810916
10005 04:44:43.811276 Shutting down all USB controllers.
10006 04:44:43.813741
10007 04:44:43.814195 Removing current net device
10008 04:44:43.814557
10009 04:44:43.820460 Exiting depthcharge with code 4 at timestamp: 48910051
10010 04:44:43.820976
10011 04:44:43.824295 LZMA decompressing kernel-1 to 0x821a6718
10012 04:44:43.824802
10013 04:44:43.827181 LZMA decompressing kernel-1 to 0x40000000
10014 04:44:45.324873
10015 04:44:45.325418 jumping to kernel
10016 04:44:45.327105 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10017 04:44:45.327640 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10018 04:44:45.328067 Setting prompt string to ['Linux version [0-9]']
10019 04:44:45.328448 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10020 04:44:45.328865 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10021 04:44:45.374750
10022 04:44:45.378041 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10023 04:44:45.381977 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10024 04:44:45.382316 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10025 04:44:45.382520 Setting prompt string to []
10026 04:44:45.382731 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10027 04:44:45.382930 Using line separator: #'\n'#
10028 04:44:45.383095 No login prompt set.
10029 04:44:45.383267 Parsing kernel messages
10030 04:44:45.383421 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10031 04:44:45.383695 [login-action] Waiting for messages, (timeout 00:04:04)
10032 04:44:45.401378 [ 0.000000] Linux version 6.1.75-cip14-rt8 (KernelCI@build-j97480-arm64-gcc-10-defconfig-arm64-chromebook-6n26j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024
10033 04:44:45.405339 [ 0.000000] random: crng init done
10034 04:44:45.412048 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10035 04:44:45.415439 [ 0.000000] efi: UEFI not found.
10036 04:44:45.422019 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10037 04:44:45.431430 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10038 04:44:45.441432 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10039 04:44:45.448101 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10040 04:44:45.454603 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10041 04:44:45.460769 [ 0.000000] printk: bootconsole [mtk8250] enabled
10042 04:44:45.468316 [ 0.000000] NUMA: No NUMA configuration found
10043 04:44:45.474874 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10044 04:44:45.480889 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10045 04:44:45.481443 [ 0.000000] Zone ranges:
10046 04:44:45.488041 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10047 04:44:45.491647 [ 0.000000] DMA32 empty
10048 04:44:45.497912 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10049 04:44:45.500569 [ 0.000000] Movable zone start for each node
10050 04:44:45.504834 [ 0.000000] Early memory node ranges
10051 04:44:45.511033 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10052 04:44:45.517141 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10053 04:44:45.523910 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10054 04:44:45.531638 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10055 04:44:45.537230 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10056 04:44:45.543350 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10057 04:44:45.573679 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10058 04:44:45.580331 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10059 04:44:45.588143 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10060 04:44:45.590232 [ 0.000000] psci: probing for conduit method from DT.
10061 04:44:45.597340 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10062 04:44:45.599827 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10063 04:44:45.607662 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10064 04:44:45.609481 [ 0.000000] psci: SMC Calling Convention v1.2
10065 04:44:45.616603 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10066 04:44:45.619672 [ 0.000000] Detected VIPT I-cache on CPU0
10067 04:44:45.626171 [ 0.000000] CPU features: detected: GIC system register CPU interface
10068 04:44:45.633576 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10069 04:44:45.640165 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10070 04:44:45.646970 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10071 04:44:45.655928 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10072 04:44:45.663266 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10073 04:44:45.666295 [ 0.000000] alternatives: applying boot alternatives
10074 04:44:45.673227 [ 0.000000] Fallback order for Node 0: 0
10075 04:44:45.679559 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10076 04:44:45.682290 [ 0.000000] Policy zone: Normal
10077 04:44:45.705681 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12699811/extract-nfsrootfs-gta4j95_,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10078 04:44:45.715363 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10079 04:44:45.725489 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10080 04:44:45.732307 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10081 04:44:45.738796 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10082 04:44:45.745085 <6>[ 0.000000] software IO TLB: area num 8.
10083 04:44:45.801097 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10084 04:44:45.880926 <6>[ 0.000000] Memory: 3835396K/4191232K available (18048K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 616K bss, 323068K reserved, 32768K cma-reserved)
10085 04:44:45.887497 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10086 04:44:45.894911 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10087 04:44:45.897632 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10088 04:44:45.904037 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10089 04:44:45.911441 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10090 04:44:45.913974 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10091 04:44:45.924043 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10092 04:44:45.931244 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10093 04:44:45.936695 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10094 04:44:45.943481 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10095 04:44:45.946673 <6>[ 0.000000] GICv3: 608 SPIs implemented
10096 04:44:45.950923 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10097 04:44:45.957816 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10098 04:44:45.959708 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10099 04:44:45.967080 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10100 04:44:45.980067 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10101 04:44:45.993278 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10102 04:44:45.999878 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10103 04:44:46.008184 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10104 04:44:46.020820 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10105 04:44:46.027248 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10106 04:44:46.034255 <6>[ 0.009235] Console: colour dummy device 80x25
10107 04:44:46.043876 <6>[ 0.013979] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10108 04:44:46.050401 <6>[ 0.024421] pid_max: default: 32768 minimum: 301
10109 04:44:46.054895 <6>[ 0.029291] LSM: Security Framework initializing
10110 04:44:46.060944 <6>[ 0.034203] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10111 04:44:46.071193 <6>[ 0.041856] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10112 04:44:46.077342 <6>[ 0.051060] cblist_init_generic: Setting adjustable number of callback queues.
10113 04:44:46.083674 <6>[ 0.058503] cblist_init_generic: Setting shift to 3 and lim to 1.
10114 04:44:46.093230 <6>[ 0.064842] cblist_init_generic: Setting adjustable number of callback queues.
10115 04:44:46.097127 <6>[ 0.072269] cblist_init_generic: Setting shift to 3 and lim to 1.
10116 04:44:46.103288 <6>[ 0.078707] rcu: Hierarchical SRCU implementation.
10117 04:44:46.109975 <6>[ 0.078709] rcu: Max phase no-delay instances is 1000.
10118 04:44:46.116583 <6>[ 0.078733] printk: bootconsole [mtk8250] printing thread started
10119 04:44:46.123254 <6>[ 0.097033] EFI services will not be available.
10120 04:44:46.126617 <6>[ 0.097235] smp: Bringing up secondary CPUs ...
10121 04:44:46.130386 <6>[ 0.097544] Detected VIPT I-cache on CPU1
10122 04:44:46.139859 <6>[ 0.097612] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10123 04:44:46.146188 <6>[ 0.097641] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10124 04:44:46.155266 <6>[ 0.125542] Detected VIPT I-cache on CPU2
10125 04:44:46.161837 <6>[ 0.125589] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10126 04:44:46.168179 <6>[ 0.125605] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10127 04:44:46.176580 <6>[ 0.125855] Detected VIPT I-cache on CPU3
10128 04:44:46.181418 <6>[ 0.125901] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10129 04:44:46.188364 <6>[ 0.125914] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10130 04:44:46.191459 <6>[ 0.126224] CPU features: detected: Spectre-v4
10131 04:44:46.197515 <6>[ 0.126231] CPU features: detected: Spectre-BHB
10132 04:44:46.200961 <6>[ 0.126235] Detected PIPT I-cache on CPU4
10133 04:44:46.208258 <6>[ 0.126294] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10134 04:44:46.214217 <6>[ 0.126311] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10135 04:44:46.221612 <6>[ 0.126601] Detected PIPT I-cache on CPU5
10136 04:44:46.227706 <6>[ 0.126661] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10137 04:44:46.234142 <6>[ 0.126677] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10138 04:44:46.237890 <6>[ 0.126947] Detected PIPT I-cache on CPU6
10139 04:44:46.247336 <6>[ 0.127008] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10140 04:44:46.254157 <6>[ 0.127024] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10141 04:44:46.257279 <6>[ 0.127316] Detected PIPT I-cache on CPU7
10142 04:44:46.264074 <6>[ 0.127378] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10143 04:44:46.272350 <6>[ 0.127394] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10144 04:44:46.275975 <6>[ 0.127439] smp: Brought up 1 node, 8 CPUs
10145 04:44:46.280355 <6>[ 0.127444] SMP: Total of 8 processors activated.
10146 04:44:46.287248 <6>[ 0.127446] CPU features: detected: 32-bit EL0 Support
10147 04:44:46.293484 <6>[ 0.127449] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10148 04:44:46.300503 <6>[ 0.127451] CPU features: detected: Common not Private translations
10149 04:44:46.306530 <6>[ 0.127453] CPU features: detected: CRC32 instructions
10150 04:44:46.313516 <6>[ 0.127455] CPU features: detected: RCpc load-acquire (LDAPR)
10151 04:44:46.316372 <6>[ 0.127457] CPU features: detected: LSE atomic instructions
10152 04:44:46.323709 <6>[ 0.127458] CPU features: detected: Privileged Access Never
10153 04:44:46.330819 <6>[ 0.127460] CPU features: detected: RAS Extension Support
10154 04:44:46.337126 <6>[ 0.127463] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10155 04:44:46.339800 <6>[ 0.127529] CPU: All CPU(s) started at EL2
10156 04:44:46.362369 �7��ͽ�ɍ��
10157 04:44:46.372605 ɍ�}���}��չѕ�5R����r������e5�"�ͭ��սх́"�ս�}�r�r�j��<<6>[ 0.347871] printk: console [ttyS0] printing thread started
10158 04:44:46.378621 6><6>[ 0.347900] printk: console [ttyS0] enabled
10159 04:44:46.385618 [ 0.220006] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10160 04:44:46.392337 <6>[ 0.347903] printk: bootconsole [mtk8250] disabled
10161 04:44:46.400214 <6>[ 0.365278] printk: bootconsole [mtk8250] printing thread stopped
10162 04:44:46.403247 <6>[ 0.366566] SuperH (H)SCI(F) driver initialized
10163 04:44:46.409710 <6>[ 0.367066] msm_serial: driver initialized
10164 04:44:46.415848 <6>[ 0.371718] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10165 04:44:46.426127 <6>[ 0.371748] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10166 04:44:46.432874 <6>[ 0.371778] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10167 04:44:46.442269 <6>[ 0.371807] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10168 04:44:46.453547 <6>[ 0.371829] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10169 04:44:46.465397 <6>[ 0.371866] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10170 04:44:46.476451 <6>[ 0.371895] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10171 04:44:46.481139 <6>[ 0.372023] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10172 04:44:46.486475 <6>[ 0.372052] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10173 04:44:46.491888 <6>[ 0.382927] loop: module loaded
10174 04:44:46.497149 <6>[ 0.385479] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10175 04:44:46.500144 <4>[ 0.401938] mtk-pmic-keys: Failed to locate of_node [id: -1]
10176 04:44:46.505653 <6>[ 0.402918] megasas: 07.719.03.00-rc1
10177 04:44:46.511040 <6>[ 0.415282] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10178 04:44:46.516789 <6>[ 0.415383] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10179 04:44:46.524552 <6>[ 0.427390] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10180 04:44:46.533306 <6>[ 0.480636] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10181 04:44:46.984546 <6>[ 0.957600] Freeing initrd memory: 17380K
10182 04:44:46.991307 <6>[ 0.963455] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10183 04:44:46.994671 <6>[ 0.968261] tun: Universal TUN/TAP device driver, 1.6
10184 04:44:47.000747 <6>[ 0.969023] thunder_xcv, ver 1.0
10185 04:44:47.001985 <6>[ 0.969047] thunder_bgx, ver 1.0
10186 04:44:47.005223 <6>[ 0.969061] nicpf, ver 1.0
10187 04:44:47.011750 <6>[ 0.970120] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10188 04:44:47.017743 <6>[ 0.970124] hns3: Copyright (c) 2017 Huawei Corporation.
10189 04:44:47.021291 <6>[ 0.970152] hclge is initializing
10190 04:44:47.028372 <6>[ 0.970166] e1000: Intel(R) PRO/1000 Network Driver
10191 04:44:47.031664 <6>[ 0.970168] e1000: Copyright (c) 1999-2006 Intel Corporation.
10192 04:44:47.039089 <6>[ 0.970184] e1000e: Intel(R) PRO/1000 Network Driver
10193 04:44:47.045950 <6>[ 0.970186] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10194 04:44:47.048915 <6>[ 0.970203] igb: Intel(R) Gigabit Ethernet Network Driver
10195 04:44:47.055832 <6>[ 0.970205] igb: Copyright (c) 2007-2014 Intel Corporation.
10196 04:44:47.063514 <6>[ 0.970221] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10197 04:44:47.069667 <6>[ 0.970223] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10198 04:44:47.073546 <6>[ 0.970511] sky2: driver version 1.30
10199 04:44:47.076263 <6>[ 0.971573] VFIO - User Level meta-driver version: 0.3
10200 04:44:47.082705 <6>[ 0.974372] usbcore: registered new interface driver usb-storage
10201 04:44:47.089644 <6>[ 0.974555] usbcore: registered new device driver onboard-usb-hub
10202 04:44:47.096318 <6>[ 0.977360] mt6397-rtc mt6359-rtc: registered as rtc0
10203 04:44:47.106259 <6>[ 0.977519] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-04T04:44:49 UTC (1707021889)
10204 04:44:47.109387 <6>[ 0.978136] i2c_dev: i2c /dev entries driver
10205 04:44:47.117511 <6>[ 0.985315] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10206 04:44:47.123104 <6>[ 1.000274] cpu cpu0: EM: created perf domain
10207 04:44:47.125780 <6>[ 1.000575] cpu cpu4: EM: created perf domain
10208 04:44:47.133079 <6>[ 1.002380] sdhci: Secure Digital Host Controller Interface driver
10209 04:44:47.135750 <6>[ 1.002381] sdhci: Copyright(c) Pierre Ossman
10210 04:44:47.143198 <6>[ 1.002690] Synopsys Designware Multimedia Card Interface Driver
10211 04:44:47.149661 <6>[ 1.003012] sdhci-pltfm: SDHCI platform and OF driver helper
10212 04:44:47.155937 <6>[ 1.007377] ledtrig-cpu: registered to indicate activity on CPUs
10213 04:44:47.159559 <6>[ 1.008047] mmc0: CQHCI version 5.10
10214 04:44:47.165952 <6>[ 1.008079] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10215 04:44:47.172533 <6>[ 1.008327] usbcore: registered new interface driver usbhid
10216 04:44:47.175683 <6>[ 1.008328] usbhid: USB HID core driver
10217 04:44:47.182566 <6>[ 1.008436] spi_master spi0: will run message pump with realtime priority
10218 04:44:47.195902 <6>[ 1.036578] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10219 04:44:47.209407 <6>[ 1.038804] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10220 04:44:47.216342 <6>[ 1.039698] cros-ec-spi spi0.0: Chrome EC device registered
10221 04:44:47.225326 <6>[ 1.051448] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10222 04:44:47.229161 <6>[ 1.052291] NET: Registered PF_PACKET protocol family
10223 04:44:47.235110 <6>[ 1.052359] 9pnet: Installing 9P2000 support
10224 04:44:47.238432 <5>[ 1.052392] Key type dns_resolver registered
10225 04:44:47.242597 <6>[ 1.052864] registered taskstats version 1
10226 04:44:47.248764 <5>[ 1.052879] Loading compiled-in X.509 certificates
10227 04:44:47.259316 <4>[ 1.067846] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10228 04:44:47.268702 <4>[ 1.068068] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10229 04:44:47.276063 <3>[ 1.068078] debugfs: File 'uA_load' in directory '/' already present!
10230 04:44:47.282139 <3>[ 1.068085] debugfs: File 'min_uV' in directory '/' already present!
10231 04:44:47.288630 <3>[ 1.068088] debugfs: File 'max_uV' in directory '/' already present!
10232 04:44:47.294874 <3>[ 1.068091] debugfs: File 'constraint_flags' in directory '/' already present!
10233 04:44:47.305273 <3>[ 1.070110] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10234 04:44:47.311339 <6>[ 1.077716] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10235 04:44:47.318966 <6>[ 1.078321] xhci-mtk 11200000.usb: xHCI Host Controller
10236 04:44:47.324827 <6>[ 1.078339] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10237 04:44:47.334959 <6>[ 1.078564] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10238 04:44:47.341292 <6>[ 1.078611] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10239 04:44:47.344822 <6>[ 1.078716] xhci-mtk 11200000.usb: xHCI Host Controller
10240 04:44:47.351529 <6>[ 1.078725] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10241 04:44:47.361597 <6>[ 1.078733] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10242 04:44:47.364908 <6>[ 1.079291] hub 1-0:1.0: USB hub found
10243 04:44:47.368213 <6>[ 1.079317] hub 1-0:1.0: 1 port detected
10244 04:44:47.378215 <6>[ 1.079563] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10245 04:44:47.381646 <6>[ 1.079843] hub 2-0:1.0: USB hub found
10246 04:44:47.384462 <6>[ 1.079878] hub 2-0:1.0: 1 port detected
10247 04:44:47.391372 <6>[ 1.083130] mtk-msdc 11f70000.mmc: Got CD GPIO
10248 04:44:47.397401 <6>[ 1.097446] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10249 04:44:47.404096 <6>[ 1.097455] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10250 04:44:47.413879 <4>[ 1.097606] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10251 04:44:47.417674 <6>[ 1.097607] mmc0: Command Queue Engine enabled
10252 04:44:47.424473 <6>[ 1.097617] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10253 04:44:47.430831 <6>[ 1.098171] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10254 04:44:47.437769 <6>[ 1.098244] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10255 04:44:47.447700 <6>[ 1.098248] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10256 04:44:47.454326 <6>[ 1.098386] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10257 04:44:47.461031 <6>[ 1.098401] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10258 04:44:47.471049 <6>[ 1.098406] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10259 04:44:47.480670 <6>[ 1.098415] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10260 04:44:47.486997 <6>[ 1.100633] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10261 04:44:47.497225 <6>[ 1.100659] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10262 04:44:47.504138 <6>[ 1.100665] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10263 04:44:47.513774 <6>[ 1.100672] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10264 04:44:47.520165 <6>[ 1.100679] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10265 04:44:47.529909 <6>[ 1.100686] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10266 04:44:47.537104 <6>[ 1.100692] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10267 04:44:47.547306 <6>[ 1.100699] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10268 04:44:47.554176 <6>[ 1.100705] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10269 04:44:47.563054 <6>[ 1.100712] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10270 04:44:47.569672 <6>[ 1.100719] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10271 04:44:47.580463 <6>[ 1.100726] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10272 04:44:47.586591 <6>[ 1.100737] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10273 04:44:47.596147 <6>[ 1.100744] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10274 04:44:47.602571 <6>[ 1.100750] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10275 04:44:47.609950 <6>[ 1.101335] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10276 04:44:47.616175 <6>[ 1.101750] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10277 04:44:47.622468 <6>[ 1.102326] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10278 04:44:47.629336 <6>[ 1.102954] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10279 04:44:47.635805 <6>[ 1.103610] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10280 04:44:47.642609 <6>[ 1.103631] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10281 04:44:47.649414 <6>[ 1.104336] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10282 04:44:47.652087 <6>[ 1.104608] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10283 04:44:47.661770 <6>[ 1.104729] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10284 04:44:47.672298 <6>[ 1.104752] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10285 04:44:47.682107 <6>[ 1.104758] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10286 04:44:47.691853 <6>[ 1.104763] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10287 04:44:47.699186 <6>[ 1.104769] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10288 04:44:47.708888 <6>[ 1.104775] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10289 04:44:47.718592 <6>[ 1.104781] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10290 04:44:47.728855 <6>[ 1.104786] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10291 04:44:47.738005 <6>[ 1.104791] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10292 04:44:47.747997 <6>[ 1.104799] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10293 04:44:47.758360 <6>[ 1.104804] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10294 04:44:47.764397 <6>[ 1.105367] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10295 04:44:47.771898 <6>[ 1.105749] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10296 04:44:47.777409 <6>[ 1.116642] Trying to probe devices needed for running init ...
10297 04:44:47.784334 <6>[ 1.496024] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10298 04:44:47.787328 <6>[ 1.648849] hub 1-1:1.0: USB hub found
10299 04:44:47.794535 <6>[ 1.649242] hub 1-1:1.0: 4 ports detected
10300 04:44:47.797034 <6>[ 1.652986] hub 1-1:1.0: USB hub found
10301 04:44:47.801136 <6>[ 1.653374] hub 1-1:1.0: 4 ports detected
10302 04:44:47.807290 <6>[ 1.780151] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10303 04:44:47.832667 <6>[ 1.805167] hub 2-1:1.0: USB hub found
10304 04:44:47.836316 <6>[ 1.805586] hub 2-1:1.0: 3 ports detected
10305 04:44:47.839592 <6>[ 1.808787] hub 2-1:1.0: USB hub found
10306 04:44:47.842049 <6>[ 1.809140] hub 2-1:1.0: 3 ports detected
10307 04:44:47.995745 <6>[ 1.964146] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10308 04:44:48.117731 <6>[ 2.091222] hub 1-1.4:1.0: USB hub found
10309 04:44:48.119482 <6>[ 2.091579] hub 1-1.4:1.0: 2 ports detected
10310 04:44:48.123724 <6>[ 2.094210] hub 1-1.4:1.0: USB hub found
10311 04:44:48.129610 <6>[ 2.094534] hub 1-1.4:1.0: 2 ports detected
10312 04:44:48.199988 <6>[ 2.168258] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10313 04:44:48.411781 <6>[ 2.380144] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10314 04:44:48.595579 <6>[ 2.564141] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10315 04:44:59.432242 <6>[ 13.409161] ALSA device list:
10316 04:44:59.438997 <6>[ 13.409182] No soundcards found.
10317 04:44:59.441829 <6>[ 13.413421] Freeing unused kernel memory: 8448K
10318 04:44:59.445316 <6>[ 13.413572] Run /init as init process
10319 04:44:59.449559 Loading, please wait...
10320 04:44:59.468636 Starting version 247.3-7+deb11u2
10321 04:44:59.682973 <6>[ 13.654546] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10322 04:44:59.689599 <6>[ 13.654675] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10323 04:44:59.699820 <6>[ 13.654694] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10324 04:44:59.705249 <6>[ 13.664921] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10325 04:44:59.715782 <6>[ 13.689771] remoteproc remoteproc0: scp is available
10326 04:44:59.722089 <6>[ 13.689852] remoteproc remoteproc0: powering up scp
10327 04:44:59.728599 <6>[ 13.689857] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10328 04:44:59.734657 <6>[ 13.689877] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10329 04:44:59.741405 <6>[ 13.696741] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10330 04:44:59.751079 <3>[ 13.701986] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10331 04:44:59.758628 <3>[ 13.702023] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10332 04:44:59.765357 <3>[ 13.702035] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10333 04:44:59.775417 <4>[ 13.723313] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10334 04:44:59.778512 <4>[ 13.723313] Fallback method does not support PEC.
10335 04:44:59.789704 <3>[ 13.724197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10336 04:44:59.796023 <3>[ 13.724233] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10337 04:44:59.806038 <3>[ 13.724241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10338 04:44:59.812375 <3>[ 13.724251] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10339 04:44:59.819286 <3>[ 13.724258] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10340 04:44:59.829097 <3>[ 13.724619] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10341 04:44:59.835921 <3>[ 13.725786] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10342 04:44:59.846125 <3>[ 13.725798] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10343 04:44:59.852435 <3>[ 13.725804] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10344 04:44:59.862272 <3>[ 13.730254] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10345 04:44:59.868570 <3>[ 13.730276] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10346 04:44:59.878676 <3>[ 13.730283] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10347 04:44:59.885402 <3>[ 13.730294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10348 04:44:59.895180 <3>[ 13.730303] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10349 04:44:59.901768 <4>[ 13.730560] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10350 04:44:59.905698 <6>[ 13.732343] mc: Linux media interface: v0.10
10351 04:44:59.914831 <3>[ 13.732472] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10352 04:44:59.922197 <4>[ 13.732544] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10353 04:44:59.928413 <3>[ 13.744300] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10354 04:44:59.934947 <6>[ 13.749652] videodev: Linux video capture interface: v2.00
10355 04:44:59.941121 <6>[ 13.749771] usbcore: registered new device driver r8152-cfgselector
10356 04:44:59.950941 <3>[ 13.772055] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10357 04:44:59.957648 <6>[ 13.773528] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10358 04:44:59.965043 <6>[ 13.773553] pci_bus 0000:00: root bus resource [bus 00-ff]
10359 04:44:59.971862 <6>[ 13.773566] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10360 04:44:59.980859 <6>[ 13.773571] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10361 04:44:59.987439 <6>[ 13.773650] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10362 04:44:59.993953 <6>[ 13.773679] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10363 04:44:59.997173 <6>[ 13.773805] pci 0000:00:00.0: supports D1 D2
10364 04:45:00.004846 <6>[ 13.773809] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10365 04:45:00.013983 <6>[ 13.776554] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10366 04:45:00.021420 <6>[ 13.776740] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10367 04:45:00.027465 <6>[ 13.776774] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10368 04:45:00.034080 <6>[ 13.776795] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10369 04:45:00.044131 <6>[ 13.776824] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10370 04:45:00.047144 <6>[ 13.776946] pci 0000:01:00.0: supports D1 D2
10371 04:45:00.053385 <6>[ 13.776949] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10372 04:45:00.061320 <6>[ 13.787959] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10373 04:45:00.069917 <6>[ 13.788014] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10374 04:45:00.076396 <6>[ 13.788021] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10375 04:45:00.082917 <6>[ 13.788034] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10376 04:45:00.094109 <6>[ 13.788050] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10377 04:45:00.099958 <6>[ 13.788065] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10378 04:45:00.106692 <6>[ 13.788082] pci 0000:00:00.0: PCI bridge to [bus 01]
10379 04:45:00.113665 <6>[ 13.788089] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10380 04:45:00.119773 <6>[ 13.788354] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10381 04:45:00.126340 <6>[ 13.790428] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10382 04:45:00.132885 <6>[ 13.790790] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10383 04:45:00.139900 <6>[ 13.815209] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10384 04:45:00.149134 <6>[ 13.815237] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10385 04:45:00.156104 <6>[ 13.815244] remoteproc remoteproc0: remote processor scp is now up
10386 04:45:00.165452 <6>[ 13.816909] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10387 04:45:00.172972 <6>[ 13.817188] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10388 04:45:00.182806 <6>[ 13.838793] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10389 04:45:00.192442 <6>[ 13.840287] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10390 04:45:00.198639 <5>[ 13.861781] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10391 04:45:00.208626 <6>[ 13.861810] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10392 04:45:00.214934 <6>[ 13.867333] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10393 04:45:00.225008 <4>[ 13.875647] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10394 04:45:00.231854 <4>[ 13.875673] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10395 04:45:00.238874 <5>[ 13.878707] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10396 04:45:00.248099 <5>[ 13.878910] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10397 04:45:00.254754 <4>[ 13.878973] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10398 04:45:00.261440 <6>[ 13.878977] cfg80211: failed to load regulatory.db
10399 04:45:00.264916 <6>[ 13.883541] Bluetooth: Core ver 2.22
10400 04:45:00.271239 <6>[ 13.884107] NET: Registered PF_BLUETOOTH protocol family
10401 04:45:00.277641 <6>[ 13.884120] Bluetooth: HCI device and connection manager initialized
10402 04:45:00.281288 <6>[ 13.884279] Bluetooth: HCI socket layer initialized
10403 04:45:00.288004 <6>[ 13.884323] Bluetooth: L2CAP socket layer initialized
10404 04:45:00.295202 <6>[ 13.884412] Bluetooth: SCO socket layer initialized
10405 04:45:00.301838 <6>[ 13.888970] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10406 04:45:00.310876 <6>[ 13.890129] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10407 04:45:00.317349 <6>[ 13.890272] usbcore: registered new interface driver uvcvideo
10408 04:45:00.324684 <6>[ 13.933362] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10409 04:45:00.330741 <6>[ 13.935968] r8152 2-1.3:1.0 eth0: v1.12.13
10410 04:45:00.333945 <6>[ 13.936034] usbcore: registered new interface driver r8152
10411 04:45:00.340912 <6>[ 13.939722] usbcore: registered new interface driver btusb
10412 04:45:00.350972 <4>[ 13.940559] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10413 04:45:00.358539 <3>[ 13.940569] Bluetooth: hci0: Failed to load firmware file (-2)
10414 04:45:00.364467 <3>[ 13.940573] Bluetooth: hci0: Failed to set up firmware (-2)
10415 04:45:00.374291 <4>[ 13.940576] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10416 04:45:00.380261 <6>[ 13.962402] usbcore: registered new interface driver cdc_ether
10417 04:45:00.387101 <6>[ 13.976197] usbcore: registered new interface driver r8153_ecm
10418 04:45:00.394977 <6>[ 13.989630] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10419 04:45:00.399370 <6>[ 13.989727] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10420 04:45:00.406333 Begin: Loading e<6>[ 14.000509] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10421 04:45:00.413932 <6>[ 14.008081] mt7921e 0000:01:00.0: ASIC revision: 79610010
10422 04:45:00.420656 <6>[ 14.103023] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10423 04:45:00.422892 <6>[ 14.103023]
10424 04:45:00.429108 <6>[ 14.362915] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10425 04:45:00.432557 ssential drivers ... done.
10426 04:45:00.439235 Begin: Running /scripts/init-premount ... done.
10427 04:45:00.445964 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10428 04:45:00.452385 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10429 04:45:00.456720 Device /sys/class/net/enx00e04c6803bd found
10430 04:45:00.458857 done.
10431 04:45:00.465476 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10432 04:45:01.222768 <6>[ 15.196418] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10433 04:45:01.500478 IP-Config: no response after 2 secs - giving up
10434 04:45:01.535275 IP-Config: wlp1s0 hardware address 74:4c:a1:92:35:3b mtu 1500 DHCP
10435 04:45:01.639208 <6>[ 15.612885] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10436 04:45:02.257850 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10437 04:45:02.269368 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10438 04:45:02.276868 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10439 04:45:02.282668 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10440 04:45:02.288680 host : mt8192-asurada-spherion-r0-cbg-4
10441 04:45:02.295838 domain : lava-rack
10442 04:45:02.302163 rootserver: 192.168.201.1 rootpath:
10443 04:45:02.302406 filename :
10444 04:45:02.410572 done.
10445 04:45:02.417805 Begin: Running /scripts/nfs-bottom ... done.
10446 04:45:02.432230 Begin: Running /scripts/init-bottom ... done.
10447 04:45:03.592862 <6>[ 17.565690] NET: Registered PF_INET6 protocol family
10448 04:45:03.595139 <6>[ 17.567663] Segment Routing with IPv6
10449 04:45:03.601989 <6>[ 17.567687] In-situ OAM (IOAM) with IPv6
10450 04:45:03.714584 <30>[ 17.670836] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10451 04:45:03.718119 <30>[ 17.671724] systemd[1]: Detected architecture arm64.
10452 04:45:03.718743
10453 04:45:03.725070 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10454 04:45:03.725622
10455 04:45:03.743646 <30>[ 17.718977] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10456 04:45:04.537585 <30>[ 18.510464] systemd[1]: Queued start job for default target Graphical Interface.
10457 04:45:04.568949 [[0;32m OK [<30>[ 18.542510] systemd[1]: Created slice system-getty.slice.
10458 04:45:04.571980 0m] Created slice [0;1;39msystem-getty.slice[0m.
10459 04:45:04.591272 [[0;32m OK [0m] Created slic<30>[ 18.565465] systemd[1]: Created slice system-modprobe.slice.
10460 04:45:04.594597 e [0;1;39msystem-modprobe.slice[0m.
10461 04:45:04.615271 [[0;32m OK [0m] Created slic<30>[ 18.589360] systemd[1]: Created slice system-serial\x2dgetty.slice.
10462 04:45:04.622051 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10463 04:45:04.640882 [[0;32m OK [0m] Created slic<30>[ 18.613929] systemd[1]: Created slice User and Session Slice.
10464 04:45:04.643344 e [0;1;39mUser and Session Slice[0m.
10465 04:45:04.667141 [[0;32m OK [0m] Started [0;<30>[ 18.636974] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10466 04:45:04.669657 1;39mDispatch Password …ts to Console Directory Watch[0m.
10467 04:45:04.693879 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 18.664357] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10468 04:45:04.697257 sword R…uests to Wall Directory Watch[0m.
10469 04:45:04.721056 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 18.688388] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10470 04:45:04.728008 <30>[ 18.688576] systemd[1]: Reached target Local Encrypted Volumes.
10471 04:45:04.731917 l Encrypted Volumes[0m.
10472 04:45:04.750206 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 18.724265] systemd[1]: Reached target Paths.
10473 04:45:04.750765 s[0m.
10474 04:45:04.773531 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 18.744163] systemd[1]: Reached target Remote File Systems.
10475 04:45:04.774076 te File Systems[0m.
10476 04:45:04.796153 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 18.768529] systemd[1]: Reached target Slices.
10477 04:45:04.796758 es[0m.
10478 04:45:04.814550 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 18.788175] systemd[1]: Reached target Swap.
10479 04:45:04.815124 [0m.
10480 04:45:04.838627 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 18.808618] systemd[1]: Listening on initctl Compatibility Named Pipe.
10481 04:45:04.841004 l Compatibility Named Pipe[0m.
10482 04:45:04.850952 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 18.824737] systemd[1]: Listening on Journal Audit Socket.
10483 04:45:04.854384 l Audit Socket[0m.
10484 04:45:04.875855 [[0;32m OK [0m] Listening on<30>[ 18.849531] systemd[1]: Listening on Journal Socket (/dev/log).
10485 04:45:04.879333 [0;1;39mJournal Socket (/dev/log)[0m.
10486 04:45:04.899324 [[0;32m OK [0m] Listening on<30>[ 18.873400] systemd[1]: Listening on Journal Socket.
10487 04:45:04.903577 [0;1;39mJournal Socket[0m.
10488 04:45:04.920104 [[0;32m OK [0m] Listening on<30>[ 18.893861] systemd[1]: Listening on Network Service Netlink Socket.
10489 04:45:04.926689 [0;1;39mNetwork Service Netlink Socket[0m.
10490 04:45:04.946626 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 18.920213] systemd[1]: Listening on udev Control Socket.
10491 04:45:04.949441 ontrol Socket[0m.
10492 04:45:04.970417 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 18.944664] systemd[1]: Listening on udev Kernel Socket.
10493 04:45:04.975517 ernel Socket[0m.
10494 04:45:05.029919 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.000642] systemd[1]: Mounting Huge Pages File System...
10495 04:45:05.030454 m[0m...
10496 04:45:05.054263 Mounting [0;1;39mPOSIX Message Queue F<30>[ 19.024544] systemd[1]: Mounting POSIX Message Queue File System...
10497 04:45:05.054839 ile System[0m...
10498 04:45:05.077777 Mountin<30>[ 19.051002] systemd[1]: Mounting Kernel Debug File System...
10499 04:45:05.080402 g [0;1;39mKernel Debug File System[0m...
10500 04:45:05.102661 <30>[ 19.072557] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10501 04:45:05.111883 <30>[ 19.077927] systemd[1]: Starting Create list of static device nodes for the current kernel...
10502 04:45:05.118012 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10503 04:45:05.143767 Starting [0;1;39mLoad <30>[ 19.117046] systemd[1]: Starting Load Kernel Module configfs...
10504 04:45:05.146304 Kernel Module configfs[0m...
10505 04:45:05.169906 Starting [0;1;39mLoad Kernel Module dr<30>[ 19.140770] systemd[1]: Starting Load Kernel Module drm...
10506 04:45:05.170463 m[0m...
10507 04:45:05.193830 Starting [0;1;39mLoad Kernel Module fu<30>[ 19.164649] systemd[1]: Starting Load Kernel Module fuse...
10508 04:45:05.194376 se[0m...
10509 04:45:05.227065 <6>[ 19.203029] fuse: init (API version 7.37)
10510 04:45:05.236584 <30>[ 19.203252] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10511 04:45:05.283181 Starting [0;1;39mJourn<30>[ 19.256904] systemd[1]: Starting Journal Service...
10512 04:45:05.283743 al Service[0m...
10513 04:45:05.312970 Startin<30>[ 19.286784] systemd[1]: Starting Load Kernel Modules...
10514 04:45:05.316181 g [0;1;39mLoad Kernel Modules[0m...
10515 04:45:05.339364 Starting [0;1;39mRemou<30>[ 19.313187] systemd[1]: Starting Remount Root and Kernel File Systems...
10516 04:45:05.345361 nt Root and Kernel File Systems[0m...
10517 04:45:05.367674 Starting [0;1;39mColdp<30>[ 19.341808] systemd[1]: Starting Coldplug All udev Devices...
10518 04:45:05.371492 lug All udev Devices[0m...
10519 04:45:05.396178 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages <30>[ 19.368399] systemd[1]: Mounted Huge Pages File System.
10520 04:45:05.397942 File System[0m.
10521 04:45:05.409971 <3>[ 19.381259] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10522 04:45:05.420018 [[0;32m OK [0m] Mounted [0;<30>[ 19.393174] systemd[1]: Mounted POSIX Message Queue File System.
10523 04:45:05.422633 1;39mPOSIX Message Queue File System[0m.
10524 04:45:05.437532 <3>[ 19.409777] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10525 04:45:05.447451 [[0;32m OK [0m] Mounted [0;<30>[ 19.421741] systemd[1]: Mounted Kernel Debug File System.
10526 04:45:05.450809 1;39mKernel Debug File System[0m.
10527 04:45:05.473695 <3>[ 19.444446] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10528 04:45:05.484653 <30>[ 19.449098] systemd[1]: Finished Create list of static device nodes for the current kernel.
10529 04:45:05.491192 <3>[ 19.464380] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10530 04:45:05.501358 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10531 04:45:05.514689 <3>[ 19.486731] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10532 04:45:05.522976 <30>[ 19.498589] systemd[1]: modprobe@configfs.service: Succeeded.
10533 04:45:05.529466 <30>[ 19.499813] systemd[1]: Finished Load Kernel Module configfs.
10534 04:45:05.539607 <3>[ 19.510715] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10535 04:45:05.546138 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10536 04:45:05.561344 <3>[ 19.534508] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10537 04:45:05.573647 [[0;32m OK [<30>[ 19.546077] systemd[1]: modprobe@drm.service: Succeeded.
10538 04:45:05.576672 0m] Finished [0<30>[ 19.546748] systemd[1]: Finished Load Kernel Module drm.
10539 04:45:05.587408 <3>[ 19.556494] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10540 04:45:05.590014 ;1;39mLoad Kernel Module drm[0m.
10541 04:45:05.605975 <3>[ 19.577839] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10542 04:45:05.615134 <30>[ 19.590647] systemd[1]: modprobe@fuse.service: Succeeded.
10543 04:45:05.621680 <30>[ 19.591848] systemd[1]: Finished Load Kernel Module fuse.
10544 04:45:05.629001 <3>[ 19.597157] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10545 04:45:05.635681 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10546 04:45:05.660467 [[0;32m OK [0m] Finished [0<30>[ 19.633561] systemd[1]: Finished Load Kernel Modules.
10547 04:45:05.663137 ;1;39mLoad Kernel Modules[0m.
10548 04:45:05.682306 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 19.656649] systemd[1]: Started Journal Service.
10549 04:45:05.686394 vice[0m.
10550 04:45:05.710412 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10551 04:45:05.778847 Mounting [0;1;39mFUSE Control File System[0m...
10552 04:45:05.803133 Mounting [0;1;39mKernel Configuration File System[0m...
10553 04:45:05.833613 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10554 04:45:05.858998 Starting [0;1;39mLoad/Save Random Seed[0m...
10555 04:45:05.880110 Starting [0;1;39mApply Kernel Variables[0m...
10556 04:45:05.897675 <46>[ 19.870873] systemd-journald[306]: Received client request to flush runtime journal.
10557 04:45:05.910248 Starting [0;1;39mCreate System Users[0m...
10558 04:45:05.932688 <4>[ 19.899584] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10559 04:45:05.942258 <3>[ 19.899604] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10560 04:45:05.948868 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10561 04:45:05.966519 See 'systemctl status systemd-udev-trigger.service' for details.
10562 04:45:05.983807 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10563 04:45:05.998768 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10564 04:45:06.015930 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10565 04:45:06.659523 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10566 04:45:07.313908 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10567 04:45:07.342942 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10568 04:45:07.412574 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10569 04:45:07.484018 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10570 04:45:07.502606 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10571 04:45:07.523138 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10572 04:45:07.563817 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10573 04:45:07.590664 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10574 04:45:07.762119 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10575 04:45:07.816837 Starting [0;1;39mNetwork Service[0m...
10576 04:45:07.879159 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10577 04:45:07.940828 Starting [0;1;39mNetwork Time Synchronization[0m...
10578 04:45:07.960349 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10579 04:45:08.161820 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10580 04:45:08.188567 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10581 04:45:08.222180 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10582 04:45:08.438197 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10583 04:45:08.458038 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10584 04:45:08.508075 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10585 04:45:08.527909 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10586 04:45:08.562427 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10587 04:45:08.615951 Starting [0;1;39mNetwork Name Resolution[0m...
10588 04:45:08.635833 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10589 04:45:08.651561 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10590 04:45:08.673750 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10591 04:45:08.692447 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10592 04:45:08.713991 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10593 04:45:08.727874 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10594 04:45:08.747250 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10595 04:45:09.445731 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10596 04:45:09.472057 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10597 04:45:09.800543 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10598 04:45:09.824146 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10599 04:45:09.841671 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10600 04:45:09.867617 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10601 04:45:09.886085 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10602 04:45:09.901909 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10603 04:45:09.962993 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10604 04:45:10.078281 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10605 04:45:10.170385 Starting [0;1;39mUser Login Management[0m...
10606 04:45:10.524593 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10607 04:45:10.535925 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10608 04:45:10.552929 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10609 04:45:10.594727 Starting [0;1;39mPermit User Sessions[0m...
10610 04:45:10.617708 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10611 04:45:10.638989 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10612 04:45:10.700671 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10613 04:45:10.717611 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10614 04:45:10.735086 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10615 04:45:10.751278 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10616 04:45:10.757916 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10617 04:45:10.774223 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10618 04:45:10.830753 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10619 04:45:10.880086 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10620 04:45:10.948377
10621 04:45:10.948553
10622 04:45:10.951583 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10623 04:45:10.951720
10624 04:45:10.954464 debian-bullseye-arm64 login: root (automatic login)
10625 04:45:10.954610
10626 04:45:10.954707
10627 04:45:11.304601 Linux debian-bullseye-arm64 6.1.75-cip14-rt8 #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024 aarch64
10628 04:45:11.305212
10629 04:45:11.310203 The programs included with the Debian GNU/Linux system are free software;
10630 04:45:11.317280 the exact distribution terms for each program are described in the
10631 04:45:11.320117 individual files in /usr/share/doc/*/copyright.
10632 04:45:11.320207
10633 04:45:11.326952 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10634 04:45:11.329759 permitted by applicable law.
10635 04:45:12.207079 Matched prompt #10: / #
10637 04:45:12.207370 Setting prompt string to ['/ #']
10638 04:45:12.207468 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10640 04:45:12.207674 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10641 04:45:12.207769 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
10642 04:45:12.207842 Setting prompt string to ['/ #']
10643 04:45:12.207905 Forcing a shell prompt, looking for ['/ #']
10645 04:45:12.258331 / #
10646 04:45:12.259077 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10647 04:45:12.259673 Waiting using forced prompt support (timeout 00:02:30)
10648 04:45:12.265150
10649 04:45:12.266082 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10650 04:45:12.266618 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
10652 04:45:12.368023 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12699811/extract-nfsrootfs-gta4j95_'
10653 04:45:12.375234 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12699811/extract-nfsrootfs-gta4j95_'
10655 04:45:12.476847 / # export NFS_SERVER_IP='192.168.201.1'
10656 04:45:12.483171 export NFS_SERVER_IP='192.168.201.1'
10657 04:45:12.483723 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10658 04:45:12.483985 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
10659 04:45:12.484208 end: 2 depthcharge-action (duration 00:01:23) [common]
10660 04:45:12.484425 start: 3 lava-test-retry (timeout 00:07:56) [common]
10661 04:45:12.484641 start: 3.1 lava-test-shell (timeout 00:07:56) [common]
10662 04:45:12.484854 Using namespace: common
10664 04:45:12.585623 / # #
10665 04:45:12.586335 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10666 04:45:12.592698 #
10667 04:45:12.593617 Using /lava-12699811
10669 04:45:12.695036 / # export SHELL=/bin/bash
10670 04:45:12.701803 export SHELL=/bin/bash
10672 04:45:12.803427 / # . /lava-12699811/environment
10673 04:45:12.811079 . /lava-12699811/environment
10675 04:45:12.918290 / # /lava-12699811/bin/lava-test-runner /lava-12699811/0
10676 04:45:12.918910 Test shell timeout: 10s (minimum of the action and connection timeout)
10677 04:45:12.924653 /lava-12699811/bin/lava-test-runner /lava-12699811/0
10678 04:45:13.196801 + export TESTRUN_ID=0_timesync-off
10679 04:45:13.200081 + TESTRUN_ID=0_timesync-off
10680 04:45:13.204452 + cd /lava-12699811/0/tests/0_timesync-off
10681 04:45:13.207095 ++ cat uuid
10682 04:45:13.210395 + UUID=12699811_1.6.2.3.1
10683 04:45:13.210476 + set +x
10684 04:45:13.217781 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12699811_1.6.2.3.1>
10685 04:45:13.218044 Received signal: <STARTRUN> 0_timesync-off 12699811_1.6.2.3.1
10686 04:45:13.218122 Starting test lava.0_timesync-off (12699811_1.6.2.3.1)
10687 04:45:13.218215 Skipping test definition patterns.
10688 04:45:13.220307 + systemctl stop systemd-timesyncd
10689 04:45:13.276908 + set +x
10690 04:45:13.279401 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12699811_1.6.2.3.1>
10691 04:45:13.280082 Received signal: <ENDRUN> 0_timesync-off 12699811_1.6.2.3.1
10692 04:45:13.280508 Ending use of test pattern.
10693 04:45:13.280881 Ending test lava.0_timesync-off (12699811_1.6.2.3.1), duration 0.06
10695 04:45:13.341069 + export TESTRUN_ID=1_kselftest-tpm2
10696 04:45:13.344594 + TESTRUN_ID=1_kselftest-tpm2
10697 04:45:13.350430 + cd /lava-12699811/0/tests/1_kselftest-tpm2
10698 04:45:13.350539 ++ cat uuid
10699 04:45:13.353781 + UUID=12699811_1.6.2.3.5
10700 04:45:13.353864 + set +x
10701 04:45:13.356968 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 12699811_1.6.2.3.5>
10702 04:45:13.357254 Received signal: <STARTRUN> 1_kselftest-tpm2 12699811_1.6.2.3.5
10703 04:45:13.357325 Starting test lava.1_kselftest-tpm2 (12699811_1.6.2.3.5)
10704 04:45:13.357404 Skipping test definition patterns.
10705 04:45:13.360320 + cd ./automated/linux/kselftest/
10706 04:45:13.390840 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10707 04:45:13.412892 INFO: install_deps skipped
10708 04:45:13.525076 --2024-02-04 04:45:13-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10709 04:45:13.543541 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10710 04:45:13.677067 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10711 04:45:13.809679 HTTP request sent, awaiting response... 200 OK
10712 04:45:13.813274 Length: 2966368 (2.8M) [application/octet-stream]
10713 04:45:13.816915 Saving to: 'kselftest.tar.xz'
10714 04:45:13.817472
10715 04:45:13.817841
10716 04:45:14.076704 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10717 04:45:14.344397 kselftest.tar.xz 1%[ ] 47.81K 180KB/s
10718 04:45:14.807148 kselftest.tar.xz 7%[> ] 217.50K 408KB/s
10719 04:45:15.079499 kselftest.tar.xz 29%[====> ] 845.34K 849KB/s
10720 04:45:15.153293 kselftest.tar.xz 82%[===============> ] 2.35M 1.85MB/s
10721 04:45:15.159067 kselftest.tar.xz 100%[===================>] 2.83M 2.11MB/s in 1.3s
10722 04:45:15.159684
10723 04:45:15.415844 2024-02-04 04:45:15 (2.11 MB/s) - 'kselftest.tar.xz' saved [2966368/2966368]
10724 04:45:15.416001
10725 04:45:21.571808 skiplist:
10726 04:45:21.575074 ========================================
10727 04:45:21.578623 ========================================
10728 04:45:21.629729 tpm2:test_smoke.sh
10729 04:45:21.632814 tpm2:test_space.sh
10730 04:45:21.650784 ============== Tests to run ===============
10731 04:45:21.654102 tpm2:test_smoke.sh
10732 04:45:21.654622 tpm2:test_space.sh
10733 04:45:21.657246 ===========End Tests to run ===============
10734 04:45:21.660269 shardfile-tpm2 pass
10735 04:45:21.776618 <12>[ 35.755301] kselftest: Running tests in tpm2
10736 04:45:21.785262 TAP version 13
10737 04:45:21.798380 1..2
10738 04:45:21.834054 # selftests: tpm2: test_smoke.sh
10739 04:45:23.338735 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
10740 04:45:23.341364 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
10741 04:45:23.348264 # Exception ignored in: <function Client.__del__ at 0xffff9a318d30>
10742 04:45:23.351507 # Traceback (most recent call last):
10743 04:45:23.361383 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10744 04:45:23.361981 # if self.tpm:
10745 04:45:23.368044 # AttributeError: 'Client' object has no attribute 'tpm'
10746 04:45:23.372000 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
10747 04:45:23.377930 # Exception ignored in: <function Client.__del__ at 0xffff9a318d30>
10748 04:45:23.381299 # Traceback (most recent call last):
10749 04:45:23.391891 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10750 04:45:23.394525 # if self.tpm:
10751 04:45:23.398152 # AttributeError: 'Client' object has no attribute 'tpm'
10752 04:45:23.405368 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
10753 04:45:23.411150 # Exception ignored in: <function Client.__del__ at 0xffff9a318d30>
10754 04:45:23.415143 # Traceback (most recent call last):
10755 04:45:23.424467 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10756 04:45:23.425092 # if self.tpm:
10757 04:45:23.431643 # AttributeError: 'Client' object has no attribute 'tpm'
10758 04:45:23.434478 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
10759 04:45:23.442106 # Exception ignored in: <function Client.__del__ at 0xffff9a318d30>
10760 04:45:23.444125 # Traceback (most recent call last):
10761 04:45:23.453913 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10762 04:45:23.457592 # if self.tpm:
10763 04:45:23.461148 # AttributeError: 'Client' object has no attribute 'tpm'
10764 04:45:23.467518 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
10765 04:45:23.471049 # Exception ignored in: <function Client.__del__ at 0xffff9a318d30>
10766 04:45:23.474157 # Traceback (most recent call last):
10767 04:45:23.483710 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10768 04:45:23.487157 # if self.tpm:
10769 04:45:23.490845 # AttributeError: 'Client' object has no attribute 'tpm'
10770 04:45:23.497311 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
10771 04:45:23.503787 # Exception ignored in: <function Client.__del__ at 0xffff9a318d30>
10772 04:45:23.507528 # Traceback (most recent call last):
10773 04:45:23.514522 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10774 04:45:23.518637 # if self.tpm:
10775 04:45:23.524252 # AttributeError: 'Client' object has no attribute 'tpm'
10776 04:45:23.527443 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
10777 04:45:23.533810 # Exception ignored in: <function Client.__del__ at 0xffff9a318d30>
10778 04:45:23.537321 # Traceback (most recent call last):
10779 04:45:23.547656 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10780 04:45:23.548245 # if self.tpm:
10781 04:45:23.554005 # AttributeError: 'Client' object has no attribute 'tpm'
10782 04:45:23.561376 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
10783 04:45:23.567050 # Exception ignored in: <function Client.__del__ at 0xffff9a318d30>
10784 04:45:23.571456 # Traceback (most recent call last):
10785 04:45:23.577357 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10786 04:45:23.580154 # if self.tpm:
10787 04:45:23.587289 # AttributeError: 'Client' object has no attribute 'tpm'
10788 04:45:23.587883 #
10789 04:45:23.593496 # ======================================================================
10790 04:45:23.597223 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
10791 04:45:23.603494 # ----------------------------------------------------------------------
10792 04:45:23.612235 # Traceback (most recent call last):
10793 04:45:23.620165 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
10794 04:45:23.623560 # self.root_key = self.client.create_root_key()
10795 04:45:23.633158 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
10796 04:45:23.640206 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
10797 04:45:23.649601 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
10798 04:45:23.650155 # raise ProtocolError(cc, rc)
10799 04:45:23.656182 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
10800 04:45:23.656770 #
10801 04:45:23.664702 # ======================================================================
10802 04:45:23.669555 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
10803 04:45:23.676264 # ----------------------------------------------------------------------
10804 04:45:23.679726 # Traceback (most recent call last):
10805 04:45:23.689242 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10806 04:45:23.693175 # self.client = tpm2.Client()
10807 04:45:23.703277 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10808 04:45:23.706611 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10809 04:45:23.713008 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10810 04:45:23.713558 #
10811 04:45:23.718814 # ======================================================================
10812 04:45:23.722247 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
10813 04:45:23.729229 # ----------------------------------------------------------------------
10814 04:45:23.732216 # Traceback (most recent call last):
10815 04:45:23.742824 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10816 04:45:23.745509 # self.client = tpm2.Client()
10817 04:45:23.756180 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10818 04:45:23.762039 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10819 04:45:23.766753 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10820 04:45:23.767222 #
10821 04:45:23.771726 # ======================================================================
10822 04:45:23.778680 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
10823 04:45:23.785639 # ----------------------------------------------------------------------
10824 04:45:23.788573 # Traceback (most recent call last):
10825 04:45:23.799274 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10826 04:45:23.799836 # self.client = tpm2.Client()
10827 04:45:23.808837 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10828 04:45:23.815104 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10829 04:45:23.818961 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10830 04:45:23.821986 #
10831 04:45:23.828620 # ======================================================================
10832 04:45:23.831840 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
10833 04:45:23.838179 # ----------------------------------------------------------------------
10834 04:45:23.841321 # Traceback (most recent call last):
10835 04:45:23.851514 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10836 04:45:23.855375 # self.client = tpm2.Client()
10837 04:45:23.864532 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10838 04:45:23.871056 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10839 04:45:23.877155 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10840 04:45:23.877889 #
10841 04:45:23.881198 # ======================================================================
10842 04:45:23.888373 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
10843 04:45:23.894945 # ----------------------------------------------------------------------
10844 04:45:23.897411 # Traceback (most recent call last):
10845 04:45:23.904792 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10846 04:45:23.907971 # self.client = tpm2.Client()
10847 04:45:23.918995 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10848 04:45:23.922971 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10849 04:45:23.930130 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10850 04:45:23.930689 #
10851 04:45:23.934584 # ======================================================================
10852 04:45:23.939932 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
10853 04:45:23.947305 # ----------------------------------------------------------------------
10854 04:45:23.951233 # Traceback (most recent call last):
10855 04:45:23.960978 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10856 04:45:23.964898 # self.client = tpm2.Client()
10857 04:45:23.972185 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10858 04:45:23.978595 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10859 04:45:23.982127 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10860 04:45:23.985478 #
10861 04:45:23.988162 # ======================================================================
10862 04:45:23.995113 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
10863 04:45:24.001226 # ----------------------------------------------------------------------
10864 04:45:24.005848 # Traceback (most recent call last):
10865 04:45:24.014946 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10866 04:45:24.018599 # self.client = tpm2.Client()
10867 04:45:24.027885 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10868 04:45:24.034394 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10869 04:45:24.038165 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10870 04:45:24.038633 #
10871 04:45:24.044881 # ======================================================================
10872 04:45:24.053273 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
10873 04:45:24.058246 # ----------------------------------------------------------------------
10874 04:45:24.060288 # Traceback (most recent call last):
10875 04:45:24.071109 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10876 04:45:24.074926 # self.client = tpm2.Client()
10877 04:45:24.083830 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10878 04:45:24.087634 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10879 04:45:24.093884 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10880 04:45:24.094441 #
10881 04:45:24.100866 # ----------------------------------------------------------------------
10882 04:45:24.101437 # Ran 9 tests in 0.045s
10883 04:45:24.103924 #
10884 04:45:24.104476 # FAILED (errors=9)
10885 04:45:24.107017 # test_async (tpm2_tests.AsyncTest) ... ok
10886 04:45:24.113429 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
10887 04:45:24.113972 #
10888 04:45:24.120198 # ----------------------------------------------------------------------
10889 04:45:24.124048 # Ran 2 tests in 0.028s
10890 04:45:24.124597 #
10891 04:45:24.125014 # OK
10892 04:45:24.126828 ok 1 selftests: tpm2: test_smoke.sh
10893 04:45:24.130796 # selftests: tpm2: test_space.sh
10894 04:45:24.133449 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
10895 04:45:24.140227 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
10896 04:45:24.143364 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
10897 04:45:24.146968 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
10898 04:45:24.150010 #
10899 04:45:24.153487 # ======================================================================
10900 04:45:24.160947 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
10901 04:45:24.166558 # ----------------------------------------------------------------------
10902 04:45:24.169519 # Traceback (most recent call last):
10903 04:45:24.180010 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
10904 04:45:24.183056 # root1 = space1.create_root_key()
10905 04:45:24.193106 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
10906 04:45:24.199768 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
10907 04:45:24.209839 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
10908 04:45:24.212879 # raise ProtocolError(cc, rc)
10909 04:45:24.220198 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
10910 04:45:24.220789 #
10911 04:45:24.225782 # ======================================================================
10912 04:45:24.229538 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
10913 04:45:24.236151 # ----------------------------------------------------------------------
10914 04:45:24.240360 # Traceback (most recent call last):
10915 04:45:24.249333 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
10916 04:45:24.252306 # space1.create_root_key()
10917 04:45:24.265791 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
10918 04:45:24.269556 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
10919 04:45:24.278862 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
10920 04:45:24.283287 # raise ProtocolError(cc, rc)
10921 04:45:24.289119 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
10922 04:45:24.289748 #
10923 04:45:24.296809 # ======================================================================
10924 04:45:24.299507 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
10925 04:45:24.305987 # ----------------------------------------------------------------------
10926 04:45:24.309159 # Traceback (most recent call last):
10927 04:45:24.319391 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
10928 04:45:24.322926 # root1 = space1.create_root_key()
10929 04:45:24.335420 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
10930 04:45:24.338678 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
10931 04:45:24.349109 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
10932 04:45:24.352486 # raise ProtocolError(cc, rc)
10933 04:45:24.358959 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
10934 04:45:24.359489 #
10935 04:45:24.365265 # ======================================================================
10936 04:45:24.368770 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
10937 04:45:24.375709 # ----------------------------------------------------------------------
10938 04:45:24.378268 # Traceback (most recent call last):
10939 04:45:24.391786 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
10940 04:45:24.395014 # root1 = space1.create_root_key()
10941 04:45:24.404862 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
10942 04:45:24.411416 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
10943 04:45:24.421424 # File "/lava-12699811/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
10944 04:45:24.424920 # raise ProtocolError(cc, rc)
10945 04:45:24.431674 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
10946 04:45:24.432150 #
10947 04:45:24.438646 # ----------------------------------------------------------------------
10948 04:45:24.439123 # Ran 4 tests in 0.064s
10949 04:45:24.439561 #
10950 04:45:24.441518 # FAILED (errors=4)
10951 04:45:24.444867 not ok 2 selftests: tpm2: test_space.sh # exit=1
10952 04:45:24.460430 tpm2_test_smoke_sh pass
10953 04:45:24.464028 tpm2_test_space_sh fail
10954 04:45:24.477515 + ../../utils/send-to-lava.sh ./output/result.txt
10955 04:45:24.549979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
10956 04:45:24.550791 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
10958 04:45:24.597612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
10959 04:45:24.597999 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
10961 04:45:24.646948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
10962 04:45:24.647217 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
10964 04:45:24.650184 + set +x
10965 04:45:24.654564 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 12699811_1.6.2.3.5>
10966 04:45:24.654937 Received signal: <ENDRUN> 1_kselftest-tpm2 12699811_1.6.2.3.5
10967 04:45:24.655056 Ending use of test pattern.
10968 04:45:24.655162 Ending test lava.1_kselftest-tpm2 (12699811_1.6.2.3.5), duration 11.30
10970 04:45:24.656631 <LAVA_TEST_RUNNER EXIT>
10971 04:45:24.656926 ok: lava_test_shell seems to have completed
10972 04:45:24.657084 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
10973 04:45:24.657210 end: 3.1 lava-test-shell (duration 00:00:12) [common]
10974 04:45:24.657360 end: 3 lava-test-retry (duration 00:00:12) [common]
10975 04:45:24.657486 start: 4 finalize (timeout 00:07:44) [common]
10976 04:45:24.657617 start: 4.1 power-off (timeout 00:00:30) [common]
10977 04:45:24.657943 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10978 04:45:24.738409 >> Command sent successfully.
10979 04:45:24.743668 Returned 0 in 0 seconds
10980 04:45:24.844876 end: 4.1 power-off (duration 00:00:00) [common]
10982 04:45:24.846705 start: 4.2 read-feedback (timeout 00:07:43) [common]
10983 04:45:24.848131 Listened to connection for namespace 'common' for up to 1s
10984 04:45:25.848931 Finalising connection for namespace 'common'
10985 04:45:25.849727 Disconnecting from shell: Finalise
10986 04:45:25.850303 / #
10987 04:45:25.951473 end: 4.2 read-feedback (duration 00:00:01) [common]
10988 04:45:25.952220 end: 4 finalize (duration 00:00:01) [common]
10989 04:45:25.953140 Cleaning after the job
10990 04:45:25.953928 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/ramdisk
10991 04:45:25.973355 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/kernel
10992 04:45:26.004887 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/dtb
10993 04:45:26.005158 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/nfsrootfs
10994 04:45:26.097599 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699811/tftp-deploy-eb0jq5zd/modules
10995 04:45:26.105038 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12699811
10996 04:45:26.738904 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12699811
10997 04:45:26.739084 Job finished correctly