Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 14
- Kernel Errors: 33
1 04:40:15.815129 lava-dispatcher, installed at version: 2023.10
2 04:40:15.815440 start: 0 validate
3 04:40:15.815587 Start time: 2024-02-04 04:40:15.815574+00:00 (UTC)
4 04:40:15.815723 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:40:15.815861 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 04:40:16.083439 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:40:16.083620 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:40:35.350916 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:40:35.351601 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:40:35.614505 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:40:35.615082 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 04:40:36.135947 Using caching service: 'http://localhost/cache/?uri=%s'
13 04:40:36.136122 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 04:40:39.137862 validate duration: 23.32
16 04:40:39.138183 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:40:39.138282 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:40:39.138374 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:40:39.138499 Not decompressing ramdisk as can be used compressed.
20 04:40:39.138587 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/initrd.cpio.gz
21 04:40:39.138703 saving as /var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/ramdisk/initrd.cpio.gz
22 04:40:39.138814 total size: 4665398 (4 MB)
23 04:40:39.405188 progress 0 % (0 MB)
24 04:40:39.406820 progress 5 % (0 MB)
25 04:40:39.408129 progress 10 % (0 MB)
26 04:40:39.409415 progress 15 % (0 MB)
27 04:40:39.410816 progress 20 % (0 MB)
28 04:40:39.412149 progress 25 % (1 MB)
29 04:40:39.413527 progress 30 % (1 MB)
30 04:40:39.414807 progress 35 % (1 MB)
31 04:40:39.416264 progress 40 % (1 MB)
32 04:40:39.417862 progress 45 % (2 MB)
33 04:40:39.419332 progress 50 % (2 MB)
34 04:40:39.420700 progress 55 % (2 MB)
35 04:40:39.422112 progress 60 % (2 MB)
36 04:40:39.423553 progress 65 % (2 MB)
37 04:40:39.424883 progress 70 % (3 MB)
38 04:40:39.426309 progress 75 % (3 MB)
39 04:40:39.427779 progress 80 % (3 MB)
40 04:40:39.429435 progress 85 % (3 MB)
41 04:40:39.430888 progress 90 % (4 MB)
42 04:40:39.432146 progress 95 % (4 MB)
43 04:40:39.433412 progress 100 % (4 MB)
44 04:40:39.433579 4 MB downloaded in 0.29 s (15.09 MB/s)
45 04:40:39.433736 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:40:39.433981 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:40:39.434069 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:40:39.434159 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:40:39.434300 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 04:40:39.434374 saving as /var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/kernel/Image
52 04:40:39.434435 total size: 51597824 (49 MB)
53 04:40:39.434497 No compression specified
54 04:40:39.435631 progress 0 % (0 MB)
55 04:40:39.449094 progress 5 % (2 MB)
56 04:40:39.462845 progress 10 % (4 MB)
57 04:40:39.476832 progress 15 % (7 MB)
58 04:40:39.490979 progress 20 % (9 MB)
59 04:40:39.506262 progress 25 % (12 MB)
60 04:40:39.520814 progress 30 % (14 MB)
61 04:40:39.534552 progress 35 % (17 MB)
62 04:40:39.548160 progress 40 % (19 MB)
63 04:40:39.561958 progress 45 % (22 MB)
64 04:40:39.575747 progress 50 % (24 MB)
65 04:40:39.589687 progress 55 % (27 MB)
66 04:40:39.603190 progress 60 % (29 MB)
67 04:40:39.616852 progress 65 % (32 MB)
68 04:40:39.630587 progress 70 % (34 MB)
69 04:40:39.644159 progress 75 % (36 MB)
70 04:40:39.657834 progress 80 % (39 MB)
71 04:40:39.671558 progress 85 % (41 MB)
72 04:40:39.685250 progress 90 % (44 MB)
73 04:40:39.698812 progress 95 % (46 MB)
74 04:40:39.712222 progress 100 % (49 MB)
75 04:40:39.712483 49 MB downloaded in 0.28 s (176.98 MB/s)
76 04:40:39.712642 end: 1.2.1 http-download (duration 00:00:00) [common]
78 04:40:39.712877 end: 1.2 download-retry (duration 00:00:00) [common]
79 04:40:39.712971 start: 1.3 download-retry (timeout 00:09:59) [common]
80 04:40:39.713059 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 04:40:39.713201 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 04:40:39.713272 saving as /var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/dtb/mt8192-asurada-spherion-r0.dtb
83 04:40:39.713333 total size: 47278 (0 MB)
84 04:40:39.713395 No compression specified
85 04:40:39.714558 progress 69 % (0 MB)
86 04:40:39.714839 progress 100 % (0 MB)
87 04:40:39.714999 0 MB downloaded in 0.00 s (27.11 MB/s)
88 04:40:39.715124 end: 1.3.1 http-download (duration 00:00:00) [common]
90 04:40:39.715349 end: 1.3 download-retry (duration 00:00:00) [common]
91 04:40:39.715435 start: 1.4 download-retry (timeout 00:09:59) [common]
92 04:40:39.715520 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 04:40:39.715638 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/full.rootfs.tar.xz
94 04:40:39.715707 saving as /var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/nfsrootfs/full.rootfs.tar
95 04:40:39.715769 total size: 89451516 (85 MB)
96 04:40:39.715831 Using unxz to decompress xz
97 04:40:39.720048 progress 0 % (0 MB)
98 04:40:39.958247 progress 5 % (4 MB)
99 04:40:40.194866 progress 10 % (8 MB)
100 04:40:40.469808 progress 15 % (12 MB)
101 04:40:40.679840 progress 20 % (17 MB)
102 04:40:40.779062 progress 25 % (21 MB)
103 04:40:41.051627 progress 30 % (25 MB)
104 04:40:41.363193 progress 35 % (29 MB)
105 04:40:41.648399 progress 40 % (34 MB)
106 04:40:41.933243 progress 45 % (38 MB)
107 04:40:42.202953 progress 50 % (42 MB)
108 04:40:42.489605 progress 55 % (46 MB)
109 04:40:42.759344 progress 60 % (51 MB)
110 04:40:43.045351 progress 65 % (55 MB)
111 04:40:43.370454 progress 70 % (59 MB)
112 04:40:43.694520 progress 75 % (64 MB)
113 04:40:44.020815 progress 80 % (68 MB)
114 04:40:44.299828 progress 85 % (72 MB)
115 04:40:44.535722 progress 90 % (76 MB)
116 04:40:44.800956 progress 95 % (81 MB)
117 04:40:45.071919 progress 100 % (85 MB)
118 04:40:45.078502 85 MB downloaded in 5.36 s (15.91 MB/s)
119 04:40:45.078781 end: 1.4.1 http-download (duration 00:00:05) [common]
121 04:40:45.079065 end: 1.4 download-retry (duration 00:00:05) [common]
122 04:40:45.079158 start: 1.5 download-retry (timeout 00:09:54) [common]
123 04:40:45.079247 start: 1.5.1 http-download (timeout 00:09:54) [common]
124 04:40:45.079419 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 04:40:45.079493 saving as /var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/modules/modules.tar
126 04:40:45.079557 total size: 8633524 (8 MB)
127 04:40:45.079623 Using unxz to decompress xz
128 04:40:45.084124 progress 0 % (0 MB)
129 04:40:45.105878 progress 5 % (0 MB)
130 04:40:45.130263 progress 10 % (0 MB)
131 04:40:45.155891 progress 15 % (1 MB)
132 04:40:45.180819 progress 20 % (1 MB)
133 04:40:45.206379 progress 25 % (2 MB)
134 04:40:45.234619 progress 30 % (2 MB)
135 04:40:45.259508 progress 35 % (2 MB)
136 04:40:45.284647 progress 40 % (3 MB)
137 04:40:45.310242 progress 45 % (3 MB)
138 04:40:45.337567 progress 50 % (4 MB)
139 04:40:45.363761 progress 55 % (4 MB)
140 04:40:45.392621 progress 60 % (4 MB)
141 04:40:45.418973 progress 65 % (5 MB)
142 04:40:45.444549 progress 70 % (5 MB)
143 04:40:45.468319 progress 75 % (6 MB)
144 04:40:45.495858 progress 80 % (6 MB)
145 04:40:45.522246 progress 85 % (7 MB)
146 04:40:45.549541 progress 90 % (7 MB)
147 04:40:45.580015 progress 95 % (7 MB)
148 04:40:45.609018 progress 100 % (8 MB)
149 04:40:45.614676 8 MB downloaded in 0.54 s (15.39 MB/s)
150 04:40:45.614947 end: 1.5.1 http-download (duration 00:00:01) [common]
152 04:40:45.615219 end: 1.5 download-retry (duration 00:00:01) [common]
153 04:40:45.615312 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 04:40:45.615413 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 04:40:47.384954 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12699810/extract-nfsrootfs-ogidnyo1
156 04:40:47.385194 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 04:40:47.385298 start: 1.6.2 lava-overlay (timeout 00:09:52) [common]
158 04:40:47.385467 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur
159 04:40:47.385639 makedir: /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin
160 04:40:47.385752 makedir: /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/tests
161 04:40:47.385857 makedir: /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/results
162 04:40:47.385963 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-add-keys
163 04:40:47.386111 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-add-sources
164 04:40:47.386248 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-background-process-start
165 04:40:47.386378 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-background-process-stop
166 04:40:47.386512 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-common-functions
167 04:40:47.386639 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-echo-ipv4
168 04:40:47.386766 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-install-packages
169 04:40:47.386891 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-installed-packages
170 04:40:47.387016 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-os-build
171 04:40:47.387147 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-probe-channel
172 04:40:47.387275 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-probe-ip
173 04:40:47.387401 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-target-ip
174 04:40:47.387527 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-target-mac
175 04:40:47.387652 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-target-storage
176 04:40:47.387780 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-test-case
177 04:40:47.387906 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-test-event
178 04:40:47.388032 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-test-feedback
179 04:40:47.388157 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-test-raise
180 04:40:47.388289 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-test-reference
181 04:40:47.388417 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-test-runner
182 04:40:47.388543 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-test-set
183 04:40:47.388669 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-test-shell
184 04:40:47.388797 Updating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-install-packages (oe)
185 04:40:47.388958 Updating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/bin/lava-installed-packages (oe)
186 04:40:47.389082 Creating /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/environment
187 04:40:47.389188 LAVA metadata
188 04:40:47.389260 - LAVA_JOB_ID=12699810
189 04:40:47.389324 - LAVA_DISPATCHER_IP=192.168.201.1
190 04:40:47.389425 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:52) [common]
191 04:40:47.389764 skipped lava-vland-overlay
192 04:40:47.389851 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 04:40:47.389934 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
194 04:40:47.389998 skipped lava-multinode-overlay
195 04:40:47.390071 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 04:40:47.390150 start: 1.6.2.3 test-definition (timeout 00:09:52) [common]
197 04:40:47.390224 Loading test definitions
198 04:40:47.390315 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:52) [common]
199 04:40:47.390386 Using /lava-12699810 at stage 0
200 04:40:47.390701 uuid=12699810_1.6.2.3.1 testdef=None
201 04:40:47.390795 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 04:40:47.390880 start: 1.6.2.3.2 test-overlay (timeout 00:09:52) [common]
203 04:40:47.391370 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 04:40:47.391589 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:52) [common]
206 04:40:47.392206 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 04:40:47.392445 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
209 04:40:47.393096 runner path: /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/0/tests/0_lc-compliance test_uuid 12699810_1.6.2.3.1
210 04:40:47.393250 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 04:40:47.393457 Creating lava-test-runner.conf files
213 04:40:47.393581 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12699810/lava-overlay-72a69eur/lava-12699810/0 for stage 0
214 04:40:47.393711 - 0_lc-compliance
215 04:40:47.393838 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 04:40:47.393982 start: 1.6.2.4 compress-overlay (timeout 00:09:52) [common]
217 04:40:47.400014 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 04:40:47.400123 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
219 04:40:47.400239 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 04:40:47.400325 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 04:40:47.400435 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
222 04:40:47.524179 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 04:40:47.524587 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 04:40:47.524713 extracting modules file /var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699810/extract-nfsrootfs-ogidnyo1
225 04:40:47.755045 extracting modules file /var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699810/extract-overlay-ramdisk-bo6imd4s/ramdisk
226 04:40:47.990773 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 04:40:47.990936 start: 1.6.5 apply-overlay-tftp (timeout 00:09:51) [common]
228 04:40:47.991038 [common] Applying overlay to NFS
229 04:40:47.991110 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699810/compress-overlay-60fta4qt/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12699810/extract-nfsrootfs-ogidnyo1
230 04:40:47.997845 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 04:40:47.997979 start: 1.6.6 configure-preseed-file (timeout 00:09:51) [common]
232 04:40:47.998074 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 04:40:47.998162 start: 1.6.7 compress-ramdisk (timeout 00:09:51) [common]
234 04:40:47.998243 Building ramdisk /var/lib/lava/dispatcher/tmp/12699810/extract-overlay-ramdisk-bo6imd4s/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12699810/extract-overlay-ramdisk-bo6imd4s/ramdisk
235 04:40:48.331882 >> 119436 blocks
236 04:40:50.298496 rename /var/lib/lava/dispatcher/tmp/12699810/extract-overlay-ramdisk-bo6imd4s/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/ramdisk/ramdisk.cpio.gz
237 04:40:50.298984 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 04:40:50.299114 start: 1.6.8 prepare-kernel (timeout 00:09:49) [common]
239 04:40:50.299229 start: 1.6.8.1 prepare-fit (timeout 00:09:49) [common]
240 04:40:50.299341 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/kernel/Image'
241 04:41:04.311983 Returned 0 in 14 seconds
242 04:41:04.412694 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/kernel/image.itb
243 04:41:04.774008 output: FIT description: Kernel Image image with one or more FDT blobs
244 04:41:04.774401 output: Created: Sun Feb 4 04:41:04 2024
245 04:41:04.774473 output: Image 0 (kernel-1)
246 04:41:04.774536 output: Description:
247 04:41:04.774639 output: Created: Sun Feb 4 04:41:04 2024
248 04:41:04.774697 output: Type: Kernel Image
249 04:41:04.774754 output: Compression: lzma compressed
250 04:41:04.774830 output: Data Size: 12048508 Bytes = 11766.12 KiB = 11.49 MiB
251 04:41:04.774906 output: Architecture: AArch64
252 04:41:04.774965 output: OS: Linux
253 04:41:04.775026 output: Load Address: 0x00000000
254 04:41:04.775103 output: Entry Point: 0x00000000
255 04:41:04.775177 output: Hash algo: crc32
256 04:41:04.775234 output: Hash value: 3b31d50c
257 04:41:04.775291 output: Image 1 (fdt-1)
258 04:41:04.775359 output: Description: mt8192-asurada-spherion-r0
259 04:41:04.775427 output: Created: Sun Feb 4 04:41:04 2024
260 04:41:04.775479 output: Type: Flat Device Tree
261 04:41:04.775533 output: Compression: uncompressed
262 04:41:04.775601 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
263 04:41:04.775669 output: Architecture: AArch64
264 04:41:04.775722 output: Hash algo: crc32
265 04:41:04.775775 output: Hash value: cc4352de
266 04:41:04.775827 output: Image 2 (ramdisk-1)
267 04:41:04.775910 output: Description: unavailable
268 04:41:04.775963 output: Created: Sun Feb 4 04:41:04 2024
269 04:41:04.776015 output: Type: RAMDisk Image
270 04:41:04.776068 output: Compression: Unknown Compression
271 04:41:04.776120 output: Data Size: 17803571 Bytes = 17386.30 KiB = 16.98 MiB
272 04:41:04.776204 output: Architecture: AArch64
273 04:41:04.776256 output: OS: Linux
274 04:41:04.776308 output: Load Address: unavailable
275 04:41:04.776360 output: Entry Point: unavailable
276 04:41:04.776441 output: Hash algo: crc32
277 04:41:04.776494 output: Hash value: 5789aa53
278 04:41:04.776546 output: Default Configuration: 'conf-1'
279 04:41:04.776598 output: Configuration 0 (conf-1)
280 04:41:04.776650 output: Description: mt8192-asurada-spherion-r0
281 04:41:04.776731 output: Kernel: kernel-1
282 04:41:04.776784 output: Init Ramdisk: ramdisk-1
283 04:41:04.776836 output: FDT: fdt-1
284 04:41:04.776888 output: Loadables: kernel-1
285 04:41:04.776956 output:
286 04:41:04.777181 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 04:41:04.777311 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 04:41:04.777418 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
289 04:41:04.777554 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
290 04:41:04.777635 No LXC device requested
291 04:41:04.777717 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 04:41:04.777859 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
293 04:41:04.777938 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 04:41:04.778009 Checking files for TFTP limit of 4294967296 bytes.
295 04:41:04.778605 end: 1 tftp-deploy (duration 00:00:26) [common]
296 04:41:04.778709 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 04:41:04.778803 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 04:41:04.778960 substitutions:
299 04:41:04.779026 - {DTB}: 12699810/tftp-deploy-swjqm2qw/dtb/mt8192-asurada-spherion-r0.dtb
300 04:41:04.779091 - {INITRD}: 12699810/tftp-deploy-swjqm2qw/ramdisk/ramdisk.cpio.gz
301 04:41:04.779189 - {KERNEL}: 12699810/tftp-deploy-swjqm2qw/kernel/Image
302 04:41:04.779246 - {LAVA_MAC}: None
303 04:41:04.779303 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12699810/extract-nfsrootfs-ogidnyo1
304 04:41:04.779373 - {NFS_SERVER_IP}: 192.168.201.1
305 04:41:04.779442 - {PRESEED_CONFIG}: None
306 04:41:04.779496 - {PRESEED_LOCAL}: None
307 04:41:04.779550 - {RAMDISK}: 12699810/tftp-deploy-swjqm2qw/ramdisk/ramdisk.cpio.gz
308 04:41:04.779603 - {ROOT_PART}: None
309 04:41:04.779689 - {ROOT}: None
310 04:41:04.779744 - {SERVER_IP}: 192.168.201.1
311 04:41:04.779798 - {TEE}: None
312 04:41:04.779852 Parsed boot commands:
313 04:41:04.779936 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 04:41:04.780122 Parsed boot commands: tftpboot 192.168.201.1 12699810/tftp-deploy-swjqm2qw/kernel/image.itb 12699810/tftp-deploy-swjqm2qw/kernel/cmdline
315 04:41:04.780240 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 04:41:04.780326 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 04:41:04.780432 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 04:41:04.780520 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 04:41:04.780596 Not connected, no need to disconnect.
320 04:41:04.780670 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 04:41:04.780771 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 04:41:04.780836 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
323 04:41:04.785075 Setting prompt string to ['lava-test: # ']
324 04:41:04.785530 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 04:41:04.785640 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 04:41:04.785773 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 04:41:04.785913 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 04:41:04.786158 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
329 04:41:09.919809 >> Command sent successfully.
330 04:41:09.922499 Returned 0 in 5 seconds
331 04:41:10.022913 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 04:41:10.023249 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 04:41:10.023370 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 04:41:10.023483 Setting prompt string to 'Starting depthcharge on Spherion...'
336 04:41:10.023569 Changing prompt to 'Starting depthcharge on Spherion...'
337 04:41:10.023638 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 04:41:10.023899 [Enter `^Ec?' for help]
339 04:41:10.196920
340 04:41:10.197148
341 04:41:10.197277 F0: 102B 0000
342 04:41:10.197395
343 04:41:10.197503 F3: 1001 0000 [0200]
344 04:41:10.197650
345 04:41:10.200698 F3: 1001 0000
346 04:41:10.200812
347 04:41:10.200879 F7: 102D 0000
348 04:41:10.200963
349 04:41:10.201075 F1: 0000 0000
350 04:41:10.201179
351 04:41:10.204255 V0: 0000 0000 [0001]
352 04:41:10.204401
353 04:41:10.204498 00: 0007 8000
354 04:41:10.204591
355 04:41:10.208025 01: 0000 0000
356 04:41:10.208128
357 04:41:10.208193 BP: 0C00 0209 [0000]
358 04:41:10.208272
359 04:41:10.208362 G0: 1182 0000
360 04:41:10.211866
361 04:41:10.212001 EC: 0000 0021 [4000]
362 04:41:10.212071
363 04:41:10.215441 S7: 0000 0000 [0000]
364 04:41:10.215553
365 04:41:10.215626 CC: 0000 0000 [0001]
366 04:41:10.215690
367 04:41:10.218940 T0: 0000 0040 [010F]
368 04:41:10.219042
369 04:41:10.219112 Jump to BL
370 04:41:10.219176
371 04:41:10.243633
372 04:41:10.243798
373 04:41:10.243877
374 04:41:10.250605 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 04:41:10.254194 ARM64: Exception handlers installed.
376 04:41:10.257846 ARM64: Testing exception
377 04:41:10.261382 ARM64: Done test exception
378 04:41:10.268666 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 04:41:10.279415 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 04:41:10.286100 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 04:41:10.296262 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 04:41:10.302961 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 04:41:10.309466 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 04:41:10.320449 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 04:41:10.327214 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 04:41:10.346266 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 04:41:10.349682 WDT: Last reset was cold boot
388 04:41:10.352916 SPI1(PAD0) initialized at 2873684 Hz
389 04:41:10.356355 SPI5(PAD0) initialized at 992727 Hz
390 04:41:10.359484 VBOOT: Loading verstage.
391 04:41:10.366471 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 04:41:10.369593 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 04:41:10.373172 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 04:41:10.376216 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 04:41:10.383725 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 04:41:10.390257 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 04:41:10.401269 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
398 04:41:10.401427
399 04:41:10.401520
400 04:41:10.411291 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 04:41:10.414560 ARM64: Exception handlers installed.
402 04:41:10.418105 ARM64: Testing exception
403 04:41:10.418227 ARM64: Done test exception
404 04:41:10.424423 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 04:41:10.427850 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 04:41:10.442276 Probing TPM: . done!
407 04:41:10.442448 TPM ready after 0 ms
408 04:41:10.449295 Connected to device vid:did:rid of 1ae0:0028:00
409 04:41:10.456115 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
410 04:41:10.495173 Initialized TPM device CR50 revision 0
411 04:41:10.506916 tlcl_send_startup: Startup return code is 0
412 04:41:10.507109 TPM: setup succeeded
413 04:41:10.518026 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 04:41:10.526958 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 04:41:10.538725 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 04:41:10.547947 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 04:41:10.551527 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 04:41:10.556408 in-header: 03 07 00 00 08 00 00 00
419 04:41:10.559808 in-data: aa e4 47 04 13 02 00 00
420 04:41:10.563340 Chrome EC: UHEPI supported
421 04:41:10.570337 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 04:41:10.574088 in-header: 03 9d 00 00 08 00 00 00
423 04:41:10.578055 in-data: 10 20 20 08 00 00 00 00
424 04:41:10.578211 Phase 1
425 04:41:10.581251 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 04:41:10.588212 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 04:41:10.595336 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 04:41:10.598945 Recovery requested (1009000e)
429 04:41:10.604885 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 04:41:10.610101 tlcl_extend: response is 0
431 04:41:10.618337 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 04:41:10.623747 tlcl_extend: response is 0
433 04:41:10.630659 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 04:41:10.651736 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
435 04:41:10.659141 BS: bootblock times (exec / console): total (unknown) / 149 ms
436 04:41:10.659371
437 04:41:10.659507
438 04:41:10.669293 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 04:41:10.669546 ARM64: Exception handlers installed.
440 04:41:10.672935 ARM64: Testing exception
441 04:41:10.676508 ARM64: Done test exception
442 04:41:10.696794 pmic_efuse_setting: Set efuses in 11 msecs
443 04:41:10.701080 pmwrap_interface_init: Select PMIF_VLD_RDY
444 04:41:10.704744 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 04:41:10.712500 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 04:41:10.715910 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 04:41:10.719966 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 04:41:10.723464 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 04:41:10.731167 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 04:41:10.734675 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 04:41:10.738465 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 04:41:10.745015 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 04:41:10.748334 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 04:41:10.755287 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 04:41:10.758347 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 04:41:10.761983 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 04:41:10.768606 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 04:41:10.775341 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 04:41:10.778516 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 04:41:10.784991 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 04:41:10.791855 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 04:41:10.798862 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 04:41:10.802530 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 04:41:10.809698 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 04:41:10.813727 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 04:41:10.820498 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 04:41:10.823713 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 04:41:10.830915 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 04:41:10.837593 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 04:41:10.840993 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 04:41:10.844237 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 04:41:10.851083 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 04:41:10.854767 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 04:41:10.862278 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 04:41:10.865651 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 04:41:10.869299 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 04:41:10.876949 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 04:41:10.880913 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 04:41:10.884168 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 04:41:10.891184 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 04:41:10.894468 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 04:41:10.901028 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 04:41:10.904495 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 04:41:10.907836 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 04:41:10.914502 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 04:41:10.917630 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 04:41:10.920903 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 04:41:10.927689 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 04:41:10.931238 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 04:41:10.934377 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 04:41:10.938053 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 04:41:10.944641 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 04:41:10.947785 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 04:41:10.951256 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 04:41:10.957718 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 04:41:10.967980 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 04:41:10.971243 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 04:41:10.981113 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 04:41:10.987946 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 04:41:10.994550 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 04:41:10.998006 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 04:41:11.001068 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 04:41:11.009318 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x27
504 04:41:11.016001 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 04:41:11.019087 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
506 04:41:11.022598 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 04:41:11.033862 [RTC]rtc_get_frequency_meter,154: input=15, output=794
508 04:41:11.037214 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
509 04:41:11.043779 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
510 04:41:11.046858 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
511 04:41:11.050358 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
512 04:41:11.053642 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
513 04:41:11.056914 ADC[4]: Raw value=899260 ID=7
514 04:41:11.060419 ADC[3]: Raw value=213070 ID=1
515 04:41:11.063716 RAM Code: 0x71
516 04:41:11.066987 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
517 04:41:11.070364 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
518 04:41:11.080958 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
519 04:41:11.087411 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
520 04:41:11.090624 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
521 04:41:11.094224 in-header: 03 07 00 00 08 00 00 00
522 04:41:11.097423 in-data: aa e4 47 04 13 02 00 00
523 04:41:11.100863 Chrome EC: UHEPI supported
524 04:41:11.104314 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
525 04:41:11.108532 in-header: 03 d5 00 00 08 00 00 00
526 04:41:11.112163 in-data: 98 20 60 08 00 00 00 00
527 04:41:11.116026 MRC: failed to locate region type 0.
528 04:41:11.123483 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
529 04:41:11.126538 DRAM-K: Running full calibration
530 04:41:11.133407 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
531 04:41:11.133608 header.status = 0x0
532 04:41:11.136575 header.version = 0x6 (expected: 0x6)
533 04:41:11.139927 header.size = 0xd00 (expected: 0xd00)
534 04:41:11.143609 header.flags = 0x0
535 04:41:11.147196 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
536 04:41:11.165905 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
537 04:41:11.172752 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
538 04:41:11.175988 dram_init: ddr_geometry: 2
539 04:41:11.179225 [EMI] MDL number = 2
540 04:41:11.179403 [EMI] Get MDL freq = 0
541 04:41:11.182575 dram_init: ddr_type: 0
542 04:41:11.182736 is_discrete_lpddr4: 1
543 04:41:11.185877 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
544 04:41:11.186056
545 04:41:11.186184
546 04:41:11.189005 [Bian_co] ETT version 0.0.0.1
547 04:41:11.195677 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
548 04:41:11.195889
549 04:41:11.199217 dramc_set_vcore_voltage set vcore to 650000
550 04:41:11.202285 Read voltage for 800, 4
551 04:41:11.202413 Vio18 = 0
552 04:41:11.202506 Vcore = 650000
553 04:41:11.205617 Vdram = 0
554 04:41:11.205742 Vddq = 0
555 04:41:11.205836 Vmddr = 0
556 04:41:11.209165 dram_init: config_dvfs: 1
557 04:41:11.212517 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
558 04:41:11.219160 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
559 04:41:11.222652 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
560 04:41:11.225971 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
561 04:41:11.229250 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
562 04:41:11.232344 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
563 04:41:11.235942 MEM_TYPE=3, freq_sel=18
564 04:41:11.239127 sv_algorithm_assistance_LP4_1600
565 04:41:11.242321 ============ PULL DRAM RESETB DOWN ============
566 04:41:11.246250 ========== PULL DRAM RESETB DOWN end =========
567 04:41:11.253306 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
568 04:41:11.257032 ===================================
569 04:41:11.257165 LPDDR4 DRAM CONFIGURATION
570 04:41:11.260690 ===================================
571 04:41:11.264295 EX_ROW_EN[0] = 0x0
572 04:41:11.264419 EX_ROW_EN[1] = 0x0
573 04:41:11.268595 LP4Y_EN = 0x0
574 04:41:11.268730 WORK_FSP = 0x0
575 04:41:11.272009 WL = 0x2
576 04:41:11.272129 RL = 0x2
577 04:41:11.272200 BL = 0x2
578 04:41:11.275704 RPST = 0x0
579 04:41:11.275809 RD_PRE = 0x0
580 04:41:11.279635 WR_PRE = 0x1
581 04:41:11.279757 WR_PST = 0x0
582 04:41:11.283283 DBI_WR = 0x0
583 04:41:11.283397 DBI_RD = 0x0
584 04:41:11.287078 OTF = 0x1
585 04:41:11.290317 ===================================
586 04:41:11.294166 ===================================
587 04:41:11.294300 ANA top config
588 04:41:11.297736 ===================================
589 04:41:11.297861 DLL_ASYNC_EN = 0
590 04:41:11.302144 ALL_SLAVE_EN = 1
591 04:41:11.305601 NEW_RANK_MODE = 1
592 04:41:11.309137 DLL_IDLE_MODE = 1
593 04:41:11.309263 LP45_APHY_COMB_EN = 1
594 04:41:11.313053 TX_ODT_DIS = 1
595 04:41:11.316795 NEW_8X_MODE = 1
596 04:41:11.316924 ===================================
597 04:41:11.320240 ===================================
598 04:41:11.323973 data_rate = 1600
599 04:41:11.327737 CKR = 1
600 04:41:11.331525 DQ_P2S_RATIO = 8
601 04:41:11.334829 ===================================
602 04:41:11.334995 CA_P2S_RATIO = 8
603 04:41:11.338123 DQ_CA_OPEN = 0
604 04:41:11.341278 DQ_SEMI_OPEN = 0
605 04:41:11.344864 CA_SEMI_OPEN = 0
606 04:41:11.347881 CA_FULL_RATE = 0
607 04:41:11.351514 DQ_CKDIV4_EN = 1
608 04:41:11.351649 CA_CKDIV4_EN = 1
609 04:41:11.354651 CA_PREDIV_EN = 0
610 04:41:11.358236 PH8_DLY = 0
611 04:41:11.361313 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
612 04:41:11.364907 DQ_AAMCK_DIV = 4
613 04:41:11.365043 CA_AAMCK_DIV = 4
614 04:41:11.367936 CA_ADMCK_DIV = 4
615 04:41:11.371147 DQ_TRACK_CA_EN = 0
616 04:41:11.374609 CA_PICK = 800
617 04:41:11.377978 CA_MCKIO = 800
618 04:41:11.381366 MCKIO_SEMI = 0
619 04:41:11.384774 PLL_FREQ = 3068
620 04:41:11.384896 DQ_UI_PI_RATIO = 32
621 04:41:11.388187 CA_UI_PI_RATIO = 0
622 04:41:11.391172 ===================================
623 04:41:11.394626 ===================================
624 04:41:11.397767 memory_type:LPDDR4
625 04:41:11.401359 GP_NUM : 10
626 04:41:11.401528 SRAM_EN : 1
627 04:41:11.404510 MD32_EN : 0
628 04:41:11.408007 ===================================
629 04:41:11.411294 [ANA_INIT] >>>>>>>>>>>>>>
630 04:41:11.411444 <<<<<< [CONFIGURE PHASE]: ANA_TX
631 04:41:11.414705 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
632 04:41:11.417708 ===================================
633 04:41:11.421083 data_rate = 1600,PCW = 0X7600
634 04:41:11.424382 ===================================
635 04:41:11.428050 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
636 04:41:11.434396 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
637 04:41:11.441213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
638 04:41:11.444474 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
639 04:41:11.447831 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
640 04:41:11.451544 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
641 04:41:11.455042 [ANA_INIT] flow start
642 04:41:11.455176 [ANA_INIT] PLL >>>>>>>>
643 04:41:11.458318 [ANA_INIT] PLL <<<<<<<<
644 04:41:11.462255 [ANA_INIT] MIDPI >>>>>>>>
645 04:41:11.462445 [ANA_INIT] MIDPI <<<<<<<<
646 04:41:11.466303 [ANA_INIT] DLL >>>>>>>>
647 04:41:11.466416 [ANA_INIT] flow end
648 04:41:11.469738 ============ LP4 DIFF to SE enter ============
649 04:41:11.473326 ============ LP4 DIFF to SE exit ============
650 04:41:11.477379 [ANA_INIT] <<<<<<<<<<<<<
651 04:41:11.481276 [Flow] Enable top DCM control >>>>>
652 04:41:11.484746 [Flow] Enable top DCM control <<<<<
653 04:41:11.488918 Enable DLL master slave shuffle
654 04:41:11.492580 ==============================================================
655 04:41:11.492723 Gating Mode config
656 04:41:11.499937 ==============================================================
657 04:41:11.503085 Config description:
658 04:41:11.510586 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
659 04:41:11.517635 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
660 04:41:11.521275 SELPH_MODE 0: By rank 1: By Phase
661 04:41:11.528473 ==============================================================
662 04:41:11.532377 GAT_TRACK_EN = 1
663 04:41:11.536076 RX_GATING_MODE = 2
664 04:41:11.536210 RX_GATING_TRACK_MODE = 2
665 04:41:11.539614 SELPH_MODE = 1
666 04:41:11.543454 PICG_EARLY_EN = 1
667 04:41:11.546983 VALID_LAT_VALUE = 1
668 04:41:11.550596 ==============================================================
669 04:41:11.553910 Enter into Gating configuration >>>>
670 04:41:11.557506 Exit from Gating configuration <<<<
671 04:41:11.561294 Enter into DVFS_PRE_config >>>>>
672 04:41:11.572412 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
673 04:41:11.576212 Exit from DVFS_PRE_config <<<<<
674 04:41:11.579734 Enter into PICG configuration >>>>
675 04:41:11.583470 Exit from PICG configuration <<<<
676 04:41:11.583604 [RX_INPUT] configuration >>>>>
677 04:41:11.586910 [RX_INPUT] configuration <<<<<
678 04:41:11.594572 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
679 04:41:11.598163 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
680 04:41:11.605543 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
681 04:41:11.609343 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
682 04:41:11.616559 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
683 04:41:11.624018 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
684 04:41:11.627914 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
685 04:41:11.631666 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
686 04:41:11.635328 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
687 04:41:11.638909 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
688 04:41:11.642500 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
689 04:41:11.649770 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
690 04:41:11.649929 ===================================
691 04:41:11.653750 LPDDR4 DRAM CONFIGURATION
692 04:41:11.657404 ===================================
693 04:41:11.657595 EX_ROW_EN[0] = 0x0
694 04:41:11.661117 EX_ROW_EN[1] = 0x0
695 04:41:11.661260 LP4Y_EN = 0x0
696 04:41:11.664615 WORK_FSP = 0x0
697 04:41:11.664759 WL = 0x2
698 04:41:11.668298 RL = 0x2
699 04:41:11.668452 BL = 0x2
700 04:41:11.671935 RPST = 0x0
701 04:41:11.672045 RD_PRE = 0x0
702 04:41:11.675747 WR_PRE = 0x1
703 04:41:11.675899 WR_PST = 0x0
704 04:41:11.679272 DBI_WR = 0x0
705 04:41:11.679437 DBI_RD = 0x0
706 04:41:11.683136 OTF = 0x1
707 04:41:11.683257 ===================================
708 04:41:11.690396 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
709 04:41:11.694012 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
710 04:41:11.697575 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
711 04:41:11.701267 ===================================
712 04:41:11.704659 LPDDR4 DRAM CONFIGURATION
713 04:41:11.704813 ===================================
714 04:41:11.708163 EX_ROW_EN[0] = 0x10
715 04:41:11.711702 EX_ROW_EN[1] = 0x0
716 04:41:11.711862 LP4Y_EN = 0x0
717 04:41:11.715590 WORK_FSP = 0x0
718 04:41:11.715709 WL = 0x2
719 04:41:11.715779 RL = 0x2
720 04:41:11.719571 BL = 0x2
721 04:41:11.719686 RPST = 0x0
722 04:41:11.723145 RD_PRE = 0x0
723 04:41:11.723249 WR_PRE = 0x1
724 04:41:11.726807 WR_PST = 0x0
725 04:41:11.726931 DBI_WR = 0x0
726 04:41:11.730535 DBI_RD = 0x0
727 04:41:11.730644 OTF = 0x1
728 04:41:11.734084 ===================================
729 04:41:11.740908 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
730 04:41:11.744915 nWR fixed to 40
731 04:41:11.745087 [ModeRegInit_LP4] CH0 RK0
732 04:41:11.748458 [ModeRegInit_LP4] CH0 RK1
733 04:41:11.752367 [ModeRegInit_LP4] CH1 RK0
734 04:41:11.752540 [ModeRegInit_LP4] CH1 RK1
735 04:41:11.756221 match AC timing 13
736 04:41:11.759884 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
737 04:41:11.763720 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
738 04:41:11.767669 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
739 04:41:11.775266 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
740 04:41:11.778629 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
741 04:41:11.778784 [EMI DOE] emi_dcm 0
742 04:41:11.782527 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
743 04:41:11.782661 ==
744 04:41:11.786129 Dram Type= 6, Freq= 0, CH_0, rank 0
745 04:41:11.789752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
746 04:41:11.789895 ==
747 04:41:11.797065 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
748 04:41:11.804096 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
749 04:41:11.811684 [CA 0] Center 38 (7~69) winsize 63
750 04:41:11.815159 [CA 1] Center 37 (7~68) winsize 62
751 04:41:11.818392 [CA 2] Center 35 (5~66) winsize 62
752 04:41:11.821794 [CA 3] Center 35 (5~66) winsize 62
753 04:41:11.825045 [CA 4] Center 34 (4~65) winsize 62
754 04:41:11.828597 [CA 5] Center 34 (4~65) winsize 62
755 04:41:11.828725
756 04:41:11.831887 [CmdBusTrainingLP45] Vref(ca) range 1: 34
757 04:41:11.831997
758 04:41:11.835107 [CATrainingPosCal] consider 1 rank data
759 04:41:11.838220 u2DelayCellTimex100 = 270/100 ps
760 04:41:11.841664 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
761 04:41:11.844948 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
762 04:41:11.851731 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
763 04:41:11.855252 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
764 04:41:11.858293 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
765 04:41:11.861653 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
766 04:41:11.861777
767 04:41:11.865230 CA PerBit enable=1, Macro0, CA PI delay=34
768 04:41:11.865339
769 04:41:11.868456 [CBTSetCACLKResult] CA Dly = 34
770 04:41:11.868556 CS Dly: 6 (0~37)
771 04:41:11.868626 ==
772 04:41:11.871717 Dram Type= 6, Freq= 0, CH_0, rank 1
773 04:41:11.878339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 04:41:11.878481 ==
775 04:41:11.881947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
776 04:41:11.888234 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
777 04:41:11.898003 [CA 0] Center 38 (7~69) winsize 63
778 04:41:11.901504 [CA 1] Center 37 (7~68) winsize 62
779 04:41:11.904784 [CA 2] Center 35 (5~66) winsize 62
780 04:41:11.908278 [CA 3] Center 35 (5~66) winsize 62
781 04:41:11.911260 [CA 4] Center 34 (4~65) winsize 62
782 04:41:11.914720 [CA 5] Center 34 (4~65) winsize 62
783 04:41:11.914910
784 04:41:11.917930 [CmdBusTrainingLP45] Vref(ca) range 1: 32
785 04:41:11.918027
786 04:41:11.921229 [CATrainingPosCal] consider 2 rank data
787 04:41:11.924750 u2DelayCellTimex100 = 270/100 ps
788 04:41:11.927962 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
789 04:41:11.931369 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
790 04:41:11.938112 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
791 04:41:11.941162 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
792 04:41:11.944690 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
793 04:41:11.948113 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
794 04:41:11.948244
795 04:41:11.951098 CA PerBit enable=1, Macro0, CA PI delay=34
796 04:41:11.951210
797 04:41:11.954586 [CBTSetCACLKResult] CA Dly = 34
798 04:41:11.954709 CS Dly: 6 (0~38)
799 04:41:11.957860
800 04:41:11.961146 ----->DramcWriteLeveling(PI) begin...
801 04:41:11.961269 ==
802 04:41:11.964625 Dram Type= 6, Freq= 0, CH_0, rank 0
803 04:41:11.968020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 04:41:11.968135 ==
805 04:41:11.971179 Write leveling (Byte 0): 33 => 33
806 04:41:11.974645 Write leveling (Byte 1): 29 => 29
807 04:41:11.977859 DramcWriteLeveling(PI) end<-----
808 04:41:11.977964
809 04:41:11.978066 ==
810 04:41:11.981391 Dram Type= 6, Freq= 0, CH_0, rank 0
811 04:41:11.984631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
812 04:41:11.984726 ==
813 04:41:11.987805 [Gating] SW mode calibration
814 04:41:11.994510 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
815 04:41:11.997869 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
816 04:41:12.004560 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
817 04:41:12.008116 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
818 04:41:12.011255 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
819 04:41:12.017965 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 04:41:12.021395 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 04:41:12.024471 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 04:41:12.031333 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 04:41:12.034549 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 04:41:12.038131 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 04:41:12.041867 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 04:41:12.049426 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 04:41:12.052796 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 04:41:12.056391 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 04:41:12.059421 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 04:41:12.067080 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 04:41:12.070526 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 04:41:12.073782 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 04:41:12.077026 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
834 04:41:12.083818 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
835 04:41:12.086650 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
836 04:41:12.090214 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 04:41:12.096895 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 04:41:12.100425 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 04:41:12.103600 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 04:41:12.110305 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 04:41:12.113430 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 04:41:12.116923 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 04:41:12.123546 0 9 12 | B1->B0 | 2727 3030 | 1 0 | (0 0) (1 1)
844 04:41:12.127064 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
845 04:41:12.130237 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
846 04:41:12.136770 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
847 04:41:12.140275 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
848 04:41:12.143422 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 04:41:12.150184 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
850 04:41:12.153626 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
851 04:41:12.157055 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
852 04:41:12.163670 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 04:41:12.166675 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 04:41:12.170267 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 04:41:12.176797 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 04:41:12.179991 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 04:41:12.183470 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 04:41:12.186685 0 11 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
859 04:41:12.193485 0 11 12 | B1->B0 | 3535 3e3e | 0 0 | (0 0) (0 0)
860 04:41:12.196713 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
861 04:41:12.199861 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 04:41:12.206746 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 04:41:12.210358 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 04:41:12.213392 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 04:41:12.220160 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 04:41:12.223322 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 04:41:12.226802 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
868 04:41:12.233470 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
869 04:41:12.237104 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 04:41:12.240348 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 04:41:12.247003 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 04:41:12.250434 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 04:41:12.253602 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 04:41:12.260346 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 04:41:12.263945 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 04:41:12.267005 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 04:41:12.270314 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 04:41:12.277015 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 04:41:12.280325 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 04:41:12.283645 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 04:41:12.290161 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 04:41:12.293471 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 04:41:12.297088 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
884 04:41:12.300279 Total UI for P1: 0, mck2ui 16
885 04:41:12.303851 best dqsien dly found for B0: ( 0, 14, 10)
886 04:41:12.310414 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 04:41:12.310594 Total UI for P1: 0, mck2ui 16
888 04:41:12.316914 best dqsien dly found for B1: ( 0, 14, 12)
889 04:41:12.320257 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
890 04:41:12.323484 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
891 04:41:12.323609
892 04:41:12.327139 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
893 04:41:12.330230 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
894 04:41:12.333684 [Gating] SW calibration Done
895 04:41:12.333814 ==
896 04:41:12.336906 Dram Type= 6, Freq= 0, CH_0, rank 0
897 04:41:12.340547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 04:41:12.340684 ==
899 04:41:12.343779 RX Vref Scan: 0
900 04:41:12.343880
901 04:41:12.343951 RX Vref 0 -> 0, step: 1
902 04:41:12.344014
903 04:41:12.347237 RX Delay -130 -> 252, step: 16
904 04:41:12.350401 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
905 04:41:12.357128 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
906 04:41:12.360542 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
907 04:41:12.363592 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
908 04:41:12.367257 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
909 04:41:12.370500 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
910 04:41:12.377312 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
911 04:41:12.380457 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
912 04:41:12.383847 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
913 04:41:12.387437 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
914 04:41:12.390621 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
915 04:41:12.397172 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
916 04:41:12.400786 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
917 04:41:12.403969 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
918 04:41:12.407416 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
919 04:41:12.410778 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
920 04:41:12.410907 ==
921 04:41:12.413988 Dram Type= 6, Freq= 0, CH_0, rank 0
922 04:41:12.420382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 04:41:12.420534 ==
924 04:41:12.420610 DQS Delay:
925 04:41:12.423852 DQS0 = 0, DQS1 = 0
926 04:41:12.423955 DQM Delay:
927 04:41:12.427106 DQM0 = 81, DQM1 = 70
928 04:41:12.427201 DQ Delay:
929 04:41:12.430603 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
930 04:41:12.433771 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
931 04:41:12.437333 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
932 04:41:12.440392 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
933 04:41:12.440542
934 04:41:12.440618
935 04:41:12.440680 ==
936 04:41:12.444425 Dram Type= 6, Freq= 0, CH_0, rank 0
937 04:41:12.448077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
938 04:41:12.448211 ==
939 04:41:12.448289
940 04:41:12.448351
941 04:41:12.451340 TX Vref Scan disable
942 04:41:12.451463 == TX Byte 0 ==
943 04:41:12.457880 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
944 04:41:12.461378 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
945 04:41:12.461533 == TX Byte 1 ==
946 04:41:12.468083 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
947 04:41:12.471279 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
948 04:41:12.471398 ==
949 04:41:12.474858 Dram Type= 6, Freq= 0, CH_0, rank 0
950 04:41:12.477923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
951 04:41:12.478088 ==
952 04:41:12.491754 TX Vref=22, minBit 11, minWin=26, winSum=436
953 04:41:12.495050 TX Vref=24, minBit 3, minWin=27, winSum=441
954 04:41:12.498543 TX Vref=26, minBit 7, minWin=27, winSum=445
955 04:41:12.501807 TX Vref=28, minBit 10, minWin=26, winSum=438
956 04:41:12.505276 TX Vref=30, minBit 9, minWin=27, winSum=442
957 04:41:12.511947 TX Vref=32, minBit 2, minWin=27, winSum=439
958 04:41:12.515298 [TxChooseVref] Worse bit 7, Min win 27, Win sum 445, Final Vref 26
959 04:41:12.515422
960 04:41:12.518639 Final TX Range 1 Vref 26
961 04:41:12.518762
962 04:41:12.518851 ==
963 04:41:12.522041 Dram Type= 6, Freq= 0, CH_0, rank 0
964 04:41:12.525122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
965 04:41:12.525218 ==
966 04:41:12.528614
967 04:41:12.528716
968 04:41:12.528809 TX Vref Scan disable
969 04:41:12.532259 == TX Byte 0 ==
970 04:41:12.535351 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
971 04:41:12.538503 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
972 04:41:12.541981 == TX Byte 1 ==
973 04:41:12.545252 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
974 04:41:12.548659 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
975 04:41:12.552174
976 04:41:12.552343 [DATLAT]
977 04:41:12.552442 Freq=800, CH0 RK0
978 04:41:12.552530
979 04:41:12.555339 DATLAT Default: 0xa
980 04:41:12.555427 0, 0xFFFF, sum = 0
981 04:41:12.558869 1, 0xFFFF, sum = 0
982 04:41:12.558980 2, 0xFFFF, sum = 0
983 04:41:12.561950 3, 0xFFFF, sum = 0
984 04:41:12.562062 4, 0xFFFF, sum = 0
985 04:41:12.565248 5, 0xFFFF, sum = 0
986 04:41:12.565374 6, 0xFFFF, sum = 0
987 04:41:12.568656 7, 0xFFFF, sum = 0
988 04:41:12.572001 8, 0xFFFF, sum = 0
989 04:41:12.572132 9, 0x0, sum = 1
990 04:41:12.572206 10, 0x0, sum = 2
991 04:41:12.575443 11, 0x0, sum = 3
992 04:41:12.575540 12, 0x0, sum = 4
993 04:41:12.579003 best_step = 10
994 04:41:12.579133
995 04:41:12.579204 ==
996 04:41:12.582211 Dram Type= 6, Freq= 0, CH_0, rank 0
997 04:41:12.585305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 04:41:12.585450 ==
999 04:41:12.588760 RX Vref Scan: 1
1000 04:41:12.588878
1001 04:41:12.588966 Set Vref Range= 32 -> 127
1002 04:41:12.589045
1003 04:41:12.592283 RX Vref 32 -> 127, step: 1
1004 04:41:12.592384
1005 04:41:12.595483 RX Delay -111 -> 252, step: 8
1006 04:41:12.595577
1007 04:41:12.599127 Set Vref, RX VrefLevel [Byte0]: 32
1008 04:41:12.602049 [Byte1]: 32
1009 04:41:12.602170
1010 04:41:12.605292 Set Vref, RX VrefLevel [Byte0]: 33
1011 04:41:12.608684 [Byte1]: 33
1012 04:41:12.612692
1013 04:41:12.612831 Set Vref, RX VrefLevel [Byte0]: 34
1014 04:41:12.615841 [Byte1]: 34
1015 04:41:12.620147
1016 04:41:12.620304 Set Vref, RX VrefLevel [Byte0]: 35
1017 04:41:12.623388 [Byte1]: 35
1018 04:41:12.627916
1019 04:41:12.628062 Set Vref, RX VrefLevel [Byte0]: 36
1020 04:41:12.631085 [Byte1]: 36
1021 04:41:12.635427
1022 04:41:12.635555 Set Vref, RX VrefLevel [Byte0]: 37
1023 04:41:12.638770 [Byte1]: 37
1024 04:41:12.643172
1025 04:41:12.643340 Set Vref, RX VrefLevel [Byte0]: 38
1026 04:41:12.646442 [Byte1]: 38
1027 04:41:12.650936
1028 04:41:12.651066 Set Vref, RX VrefLevel [Byte0]: 39
1029 04:41:12.654084 [Byte1]: 39
1030 04:41:12.658298
1031 04:41:12.658427 Set Vref, RX VrefLevel [Byte0]: 40
1032 04:41:12.661596 [Byte1]: 40
1033 04:41:12.666277
1034 04:41:12.666412 Set Vref, RX VrefLevel [Byte0]: 41
1035 04:41:12.669275 [Byte1]: 41
1036 04:41:12.673639
1037 04:41:12.673776 Set Vref, RX VrefLevel [Byte0]: 42
1038 04:41:12.677110 [Byte1]: 42
1039 04:41:12.681183
1040 04:41:12.681338 Set Vref, RX VrefLevel [Byte0]: 43
1041 04:41:12.684788 [Byte1]: 43
1042 04:41:12.689063
1043 04:41:12.689217 Set Vref, RX VrefLevel [Byte0]: 44
1044 04:41:12.692137 [Byte1]: 44
1045 04:41:12.696718
1046 04:41:12.696849 Set Vref, RX VrefLevel [Byte0]: 45
1047 04:41:12.699937 [Byte1]: 45
1048 04:41:12.704392
1049 04:41:12.704558 Set Vref, RX VrefLevel [Byte0]: 46
1050 04:41:12.707769 [Byte1]: 46
1051 04:41:12.712214
1052 04:41:12.712353 Set Vref, RX VrefLevel [Byte0]: 47
1053 04:41:12.715550 [Byte1]: 47
1054 04:41:12.719996
1055 04:41:12.720148 Set Vref, RX VrefLevel [Byte0]: 48
1056 04:41:12.723177 [Byte1]: 48
1057 04:41:12.727744
1058 04:41:12.727878 Set Vref, RX VrefLevel [Byte0]: 49
1059 04:41:12.731375 [Byte1]: 49
1060 04:41:12.735018
1061 04:41:12.735153 Set Vref, RX VrefLevel [Byte0]: 50
1062 04:41:12.738441 [Byte1]: 50
1063 04:41:12.742518
1064 04:41:12.742645 Set Vref, RX VrefLevel [Byte0]: 51
1065 04:41:12.745523 [Byte1]: 51
1066 04:41:12.749965
1067 04:41:12.750089 Set Vref, RX VrefLevel [Byte0]: 52
1068 04:41:12.753355 [Byte1]: 52
1069 04:41:12.757751
1070 04:41:12.757885 Set Vref, RX VrefLevel [Byte0]: 53
1071 04:41:12.760967 [Byte1]: 53
1072 04:41:12.765397
1073 04:41:12.765529 Set Vref, RX VrefLevel [Byte0]: 54
1074 04:41:12.768591 [Byte1]: 54
1075 04:41:12.773246
1076 04:41:12.773372 Set Vref, RX VrefLevel [Byte0]: 55
1077 04:41:12.776306 [Byte1]: 55
1078 04:41:12.780682
1079 04:41:12.780816 Set Vref, RX VrefLevel [Byte0]: 56
1080 04:41:12.783786 [Byte1]: 56
1081 04:41:12.788312
1082 04:41:12.788432 Set Vref, RX VrefLevel [Byte0]: 57
1083 04:41:12.791529 [Byte1]: 57
1084 04:41:12.795949
1085 04:41:12.796053 Set Vref, RX VrefLevel [Byte0]: 58
1086 04:41:12.799387 [Byte1]: 58
1087 04:41:12.803577
1088 04:41:12.803696 Set Vref, RX VrefLevel [Byte0]: 59
1089 04:41:12.806620 [Byte1]: 59
1090 04:41:12.811332
1091 04:41:12.811453 Set Vref, RX VrefLevel [Byte0]: 60
1092 04:41:12.814536 [Byte1]: 60
1093 04:41:12.818814
1094 04:41:12.818922 Set Vref, RX VrefLevel [Byte0]: 61
1095 04:41:12.822187 [Byte1]: 61
1096 04:41:12.826529
1097 04:41:12.826654 Set Vref, RX VrefLevel [Byte0]: 62
1098 04:41:12.829958 [Byte1]: 62
1099 04:41:12.834123
1100 04:41:12.834246 Set Vref, RX VrefLevel [Byte0]: 63
1101 04:41:12.837335 [Byte1]: 63
1102 04:41:12.841738
1103 04:41:12.841862 Set Vref, RX VrefLevel [Byte0]: 64
1104 04:41:12.845298 [Byte1]: 64
1105 04:41:12.849685
1106 04:41:12.849814 Set Vref, RX VrefLevel [Byte0]: 65
1107 04:41:12.852694 [Byte1]: 65
1108 04:41:12.857388
1109 04:41:12.857543 Set Vref, RX VrefLevel [Byte0]: 66
1110 04:41:12.860268 [Byte1]: 66
1111 04:41:12.864723
1112 04:41:12.864848 Set Vref, RX VrefLevel [Byte0]: 67
1113 04:41:12.867890 [Byte1]: 67
1114 04:41:12.872352
1115 04:41:12.872485 Set Vref, RX VrefLevel [Byte0]: 68
1116 04:41:12.875879 [Byte1]: 68
1117 04:41:12.880297
1118 04:41:12.880422 Set Vref, RX VrefLevel [Byte0]: 69
1119 04:41:12.883345 [Byte1]: 69
1120 04:41:12.887711
1121 04:41:12.887830 Set Vref, RX VrefLevel [Byte0]: 70
1122 04:41:12.891080 [Byte1]: 70
1123 04:41:12.895355
1124 04:41:12.895481 Set Vref, RX VrefLevel [Byte0]: 71
1125 04:41:12.898695 [Byte1]: 71
1126 04:41:12.903133
1127 04:41:12.903268 Set Vref, RX VrefLevel [Byte0]: 72
1128 04:41:12.906483 [Byte1]: 72
1129 04:41:12.910516
1130 04:41:12.910651 Set Vref, RX VrefLevel [Byte0]: 73
1131 04:41:12.913826 [Byte1]: 73
1132 04:41:12.918073
1133 04:41:12.918195 Set Vref, RX VrefLevel [Byte0]: 74
1134 04:41:12.921675 [Byte1]: 74
1135 04:41:12.926003
1136 04:41:12.926123 Set Vref, RX VrefLevel [Byte0]: 75
1137 04:41:12.929157 [Byte1]: 75
1138 04:41:12.933623
1139 04:41:12.933744 Set Vref, RX VrefLevel [Byte0]: 76
1140 04:41:12.936973 [Byte1]: 76
1141 04:41:12.941338
1142 04:41:12.941488 Set Vref, RX VrefLevel [Byte0]: 77
1143 04:41:12.944614 [Byte1]: 77
1144 04:41:12.948976
1145 04:41:12.949129 Set Vref, RX VrefLevel [Byte0]: 78
1146 04:41:12.952315 [Byte1]: 78
1147 04:41:12.956380
1148 04:41:12.956521 Set Vref, RX VrefLevel [Byte0]: 79
1149 04:41:12.959841 [Byte1]: 79
1150 04:41:12.964140
1151 04:41:12.964255 Final RX Vref Byte 0 = 62 to rank0
1152 04:41:12.967541 Final RX Vref Byte 1 = 55 to rank0
1153 04:41:12.970795 Final RX Vref Byte 0 = 62 to rank1
1154 04:41:12.974313 Final RX Vref Byte 1 = 55 to rank1==
1155 04:41:12.977366 Dram Type= 6, Freq= 0, CH_0, rank 0
1156 04:41:12.984132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 04:41:12.984289 ==
1158 04:41:12.984370 DQS Delay:
1159 04:41:12.984432 DQS0 = 0, DQS1 = 0
1160 04:41:12.987599 DQM Delay:
1161 04:41:12.987695 DQM0 = 82, DQM1 = 67
1162 04:41:12.990805 DQ Delay:
1163 04:41:12.994203 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1164 04:41:12.994350 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1165 04:41:12.997321 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1166 04:41:13.000703 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1167 04:41:13.004065
1168 04:41:13.004183
1169 04:41:13.010995 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d2c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
1170 04:41:13.014323 CH0 RK0: MR19=606, MR18=2D2C
1171 04:41:13.020847 CH0_RK0: MR19=0x606, MR18=0x2D2C, DQSOSC=398, MR23=63, INC=93, DEC=62
1172 04:41:13.020988
1173 04:41:13.024497 ----->DramcWriteLeveling(PI) begin...
1174 04:41:13.024667 ==
1175 04:41:13.027718 Dram Type= 6, Freq= 0, CH_0, rank 1
1176 04:41:13.031236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1177 04:41:13.031385 ==
1178 04:41:13.034379 Write leveling (Byte 0): 32 => 32
1179 04:41:13.037812 Write leveling (Byte 1): 31 => 31
1180 04:41:13.040922 DramcWriteLeveling(PI) end<-----
1181 04:41:13.041036
1182 04:41:13.041109 ==
1183 04:41:13.044079 Dram Type= 6, Freq= 0, CH_0, rank 1
1184 04:41:13.047465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1185 04:41:13.047604 ==
1186 04:41:13.050836 [Gating] SW mode calibration
1187 04:41:13.057654 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1188 04:41:13.064294 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1189 04:41:13.067624 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1190 04:41:13.070800 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1191 04:41:13.077453 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1192 04:41:13.080728 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 04:41:13.084275 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 04:41:13.090793 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 04:41:13.094261 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 04:41:13.097490 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 04:41:13.104233 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 04:41:13.107509 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 04:41:13.110490 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 04:41:13.117038 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 04:41:13.120692 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 04:41:13.164508 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 04:41:13.164882 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 04:41:13.164977 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 04:41:13.165045 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 04:41:13.165107 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 04:41:13.165167 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1208 04:41:13.165239 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 04:41:13.165300 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 04:41:13.165357 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 04:41:13.165414 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 04:41:13.197159 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 04:41:13.197526 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 04:41:13.197614 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 04:41:13.197691 0 9 8 | B1->B0 | 2323 2b2b | 1 0 | (1 1) (0 0)
1216 04:41:13.197766 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1217 04:41:13.198016 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 04:41:13.198084 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 04:41:13.198145 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 04:41:13.204706 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 04:41:13.208124 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 04:41:13.211509 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
1223 04:41:13.218258 0 10 8 | B1->B0 | 2e2e 2929 | 1 0 | (1 0) (0 0)
1224 04:41:13.221638 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1225 04:41:13.224818 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 04:41:13.231384 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 04:41:13.235002 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 04:41:13.238240 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 04:41:13.244849 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 04:41:13.248354 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1231 04:41:13.251341 0 11 8 | B1->B0 | 3535 3b3b | 0 0 | (0 0) (0 0)
1232 04:41:13.254961 0 11 12 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
1233 04:41:13.261679 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 04:41:13.264799 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 04:41:13.268284 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 04:41:13.274733 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 04:41:13.278911 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 04:41:13.282563 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1239 04:41:13.286628 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1240 04:41:13.289903 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1241 04:41:13.297261 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 04:41:13.300672 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 04:41:13.303798 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 04:41:13.310889 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 04:41:13.314381 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 04:41:13.317693 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 04:41:13.320717 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 04:41:13.327630 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 04:41:13.330676 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 04:41:13.334124 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 04:41:13.340689 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 04:41:13.343999 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 04:41:13.347556 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 04:41:13.354127 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1255 04:41:13.357660 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1256 04:41:13.360848 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 04:41:13.364098 Total UI for P1: 0, mck2ui 16
1258 04:41:13.367693 best dqsien dly found for B0: ( 0, 14, 6)
1259 04:41:13.371163 Total UI for P1: 0, mck2ui 16
1260 04:41:13.374277 best dqsien dly found for B1: ( 0, 14, 8)
1261 04:41:13.377659 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1262 04:41:13.381110 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1263 04:41:13.381230
1264 04:41:13.384245 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1265 04:41:13.390947 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1266 04:41:13.391096 [Gating] SW calibration Done
1267 04:41:13.391172 ==
1268 04:41:13.394570 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 04:41:13.400998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 04:41:13.401173 ==
1271 04:41:13.401257 RX Vref Scan: 0
1272 04:41:13.401322
1273 04:41:13.404386 RX Vref 0 -> 0, step: 1
1274 04:41:13.404481
1275 04:41:13.407754 RX Delay -130 -> 252, step: 16
1276 04:41:13.411126 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1277 04:41:13.414166 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1278 04:41:13.417687 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1279 04:41:13.424499 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1280 04:41:13.427707 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1281 04:41:13.430945 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1282 04:41:13.434117 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1283 04:41:13.437649 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1284 04:41:13.440690 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1285 04:41:13.447458 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1286 04:41:13.451087 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1287 04:41:13.454060 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1288 04:41:13.457453 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1289 04:41:13.464182 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1290 04:41:13.467338 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1291 04:41:13.470860 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1292 04:41:13.470975 ==
1293 04:41:13.474108 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 04:41:13.477180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 04:41:13.477290 ==
1296 04:41:13.480643 DQS Delay:
1297 04:41:13.480747 DQS0 = 0, DQS1 = 0
1298 04:41:13.483938 DQM Delay:
1299 04:41:13.484042 DQM0 = 80, DQM1 = 69
1300 04:41:13.484111 DQ Delay:
1301 04:41:13.487406 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =69
1302 04:41:13.490410 DQ4 =85, DQ5 =61, DQ6 =93, DQ7 =93
1303 04:41:13.493958 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1304 04:41:13.497259 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1305 04:41:13.497375
1306 04:41:13.497448
1307 04:41:13.500431 ==
1308 04:41:13.503914 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 04:41:13.507069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 04:41:13.507204 ==
1311 04:41:13.507277
1312 04:41:13.507341
1313 04:41:13.510455 TX Vref Scan disable
1314 04:41:13.510551 == TX Byte 0 ==
1315 04:41:13.513890 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1316 04:41:13.520644 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1317 04:41:13.520779 == TX Byte 1 ==
1318 04:41:13.523933 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1319 04:41:13.530425 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1320 04:41:13.530580 ==
1321 04:41:13.533939 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 04:41:13.537249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 04:41:13.537398 ==
1324 04:41:13.550183 TX Vref=22, minBit 13, minWin=26, winSum=435
1325 04:41:13.553405 TX Vref=24, minBit 1, minWin=27, winSum=439
1326 04:41:13.556941 TX Vref=26, minBit 1, minWin=27, winSum=438
1327 04:41:13.559947 TX Vref=28, minBit 1, minWin=27, winSum=440
1328 04:41:13.563477 TX Vref=30, minBit 11, minWin=26, winSum=440
1329 04:41:13.570256 TX Vref=32, minBit 15, minWin=26, winSum=437
1330 04:41:13.573440 [TxChooseVref] Worse bit 1, Min win 27, Win sum 440, Final Vref 28
1331 04:41:13.573619
1332 04:41:13.576964 Final TX Range 1 Vref 28
1333 04:41:13.577073
1334 04:41:13.577142 ==
1335 04:41:13.580097 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 04:41:13.583332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 04:41:13.586827 ==
1338 04:41:13.586938
1339 04:41:13.587006
1340 04:41:13.587067 TX Vref Scan disable
1341 04:41:13.590457 == TX Byte 0 ==
1342 04:41:13.593699 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1343 04:41:13.600536 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1344 04:41:13.600679 == TX Byte 1 ==
1345 04:41:13.603675 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1346 04:41:13.610336 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1347 04:41:13.610517
1348 04:41:13.610618 [DATLAT]
1349 04:41:13.610707 Freq=800, CH0 RK1
1350 04:41:13.610794
1351 04:41:13.613765 DATLAT Default: 0xa
1352 04:41:13.613878 0, 0xFFFF, sum = 0
1353 04:41:13.616831 1, 0xFFFF, sum = 0
1354 04:41:13.616962 2, 0xFFFF, sum = 0
1355 04:41:13.620424 3, 0xFFFF, sum = 0
1356 04:41:13.620543 4, 0xFFFF, sum = 0
1357 04:41:13.623822 5, 0xFFFF, sum = 0
1358 04:41:13.626876 6, 0xFFFF, sum = 0
1359 04:41:13.626986 7, 0xFFFF, sum = 0
1360 04:41:13.630254 8, 0xFFFF, sum = 0
1361 04:41:13.630359 9, 0x0, sum = 1
1362 04:41:13.630428 10, 0x0, sum = 2
1363 04:41:13.633442 11, 0x0, sum = 3
1364 04:41:13.633586 12, 0x0, sum = 4
1365 04:41:13.636858 best_step = 10
1366 04:41:13.636973
1367 04:41:13.637043 ==
1368 04:41:13.640437 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 04:41:13.643754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 04:41:13.643866 ==
1371 04:41:13.647164 RX Vref Scan: 0
1372 04:41:13.647267
1373 04:41:13.647335 RX Vref 0 -> 0, step: 1
1374 04:41:13.647416
1375 04:41:13.650188 RX Delay -111 -> 252, step: 8
1376 04:41:13.657150 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1377 04:41:13.660581 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1378 04:41:13.663974 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1379 04:41:13.667198 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1380 04:41:13.670374 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1381 04:41:13.677188 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1382 04:41:13.680277 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1383 04:41:13.683872 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1384 04:41:13.687103 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1385 04:41:13.690209 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1386 04:41:13.696990 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1387 04:41:13.700464 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1388 04:41:13.703730 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1389 04:41:13.707080 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1390 04:41:13.713844 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1391 04:41:13.717135 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1392 04:41:13.717260 ==
1393 04:41:13.720463 Dram Type= 6, Freq= 0, CH_0, rank 1
1394 04:41:13.723665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 04:41:13.723777 ==
1396 04:41:13.723848 DQS Delay:
1397 04:41:13.727187 DQS0 = 0, DQS1 = 0
1398 04:41:13.727283 DQM Delay:
1399 04:41:13.730245 DQM0 = 79, DQM1 = 70
1400 04:41:13.730343 DQ Delay:
1401 04:41:13.733748 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1402 04:41:13.737184 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =92
1403 04:41:13.740213 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1404 04:41:13.743658 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =80
1405 04:41:13.743784
1406 04:41:13.743881
1407 04:41:13.753646 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a25, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1408 04:41:13.753842 CH0 RK1: MR19=606, MR18=4A25
1409 04:41:13.760177 CH0_RK1: MR19=0x606, MR18=0x4A25, DQSOSC=391, MR23=63, INC=96, DEC=64
1410 04:41:13.763799 [RxdqsGatingPostProcess] freq 800
1411 04:41:13.770161 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1412 04:41:13.773771 Pre-setting of DQS Precalculation
1413 04:41:13.776857 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1414 04:41:13.776976 ==
1415 04:41:13.780468 Dram Type= 6, Freq= 0, CH_1, rank 0
1416 04:41:13.783593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1417 04:41:13.787235 ==
1418 04:41:13.790387 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1419 04:41:13.796692 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1420 04:41:13.805578 [CA 0] Center 36 (6~66) winsize 61
1421 04:41:13.808718 [CA 1] Center 36 (6~67) winsize 62
1422 04:41:13.812288 [CA 2] Center 34 (4~64) winsize 61
1423 04:41:13.815465 [CA 3] Center 34 (4~64) winsize 61
1424 04:41:13.818763 [CA 4] Center 35 (5~65) winsize 61
1425 04:41:13.822357 [CA 5] Center 33 (3~64) winsize 62
1426 04:41:13.822546
1427 04:41:13.825428 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1428 04:41:13.825546
1429 04:41:13.828853 [CATrainingPosCal] consider 1 rank data
1430 04:41:13.832178 u2DelayCellTimex100 = 270/100 ps
1431 04:41:13.835667 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1432 04:41:13.838867 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1433 04:41:13.845307 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1434 04:41:13.849057 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1435 04:41:13.852292 CA4 delay=35 (5~65),Diff = 2 PI (14 cell)
1436 04:41:13.855631 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1437 04:41:13.855760
1438 04:41:13.858709 CA PerBit enable=1, Macro0, CA PI delay=33
1439 04:41:13.858809
1440 04:41:13.862035 [CBTSetCACLKResult] CA Dly = 33
1441 04:41:13.862139 CS Dly: 5 (0~36)
1442 04:41:13.865353 ==
1443 04:41:13.865491 Dram Type= 6, Freq= 0, CH_1, rank 1
1444 04:41:13.871934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 04:41:13.872104 ==
1446 04:41:13.875353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1447 04:41:13.882183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1448 04:41:13.891642 [CA 0] Center 36 (6~67) winsize 62
1449 04:41:13.895200 [CA 1] Center 36 (6~67) winsize 62
1450 04:41:13.898320 [CA 2] Center 35 (5~65) winsize 61
1451 04:41:13.901580 [CA 3] Center 33 (3~64) winsize 62
1452 04:41:13.905145 [CA 4] Center 34 (4~65) winsize 62
1453 04:41:13.908333 [CA 5] Center 33 (3~64) winsize 62
1454 04:41:13.908463
1455 04:41:13.911475 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1456 04:41:13.911590
1457 04:41:13.915107 [CATrainingPosCal] consider 2 rank data
1458 04:41:13.918331 u2DelayCellTimex100 = 270/100 ps
1459 04:41:13.921520 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1460 04:41:13.925007 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1461 04:41:13.931615 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1462 04:41:13.934886 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1463 04:41:13.938453 CA4 delay=35 (5~65),Diff = 2 PI (14 cell)
1464 04:41:13.942238 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1465 04:41:13.942368
1466 04:41:13.946174 CA PerBit enable=1, Macro0, CA PI delay=33
1467 04:41:13.946295
1468 04:41:13.949709 [CBTSetCACLKResult] CA Dly = 33
1469 04:41:13.949816 CS Dly: 6 (0~38)
1470 04:41:13.949889
1471 04:41:13.953343 ----->DramcWriteLeveling(PI) begin...
1472 04:41:13.953453 ==
1473 04:41:13.956990 Dram Type= 6, Freq= 0, CH_1, rank 0
1474 04:41:13.960941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 04:41:13.961068 ==
1476 04:41:13.964956 Write leveling (Byte 0): 28 => 28
1477 04:41:13.968668 Write leveling (Byte 1): 28 => 28
1478 04:41:13.968791 DramcWriteLeveling(PI) end<-----
1479 04:41:13.972512
1480 04:41:13.972631 ==
1481 04:41:13.972702 Dram Type= 6, Freq= 0, CH_1, rank 0
1482 04:41:13.979116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1483 04:41:13.979254 ==
1484 04:41:13.982318 [Gating] SW mode calibration
1485 04:41:13.988969 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1486 04:41:13.992035 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1487 04:41:13.998715 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1488 04:41:14.002375 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1489 04:41:14.005489 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 04:41:14.012306 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 04:41:14.015476 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 04:41:14.018714 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 04:41:14.022351 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 04:41:14.029032 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 04:41:14.032477 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 04:41:14.035568 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 04:41:14.042375 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 04:41:14.045661 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 04:41:14.049158 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 04:41:14.055750 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 04:41:14.058719 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 04:41:14.062100 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 04:41:14.068691 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 04:41:14.072248 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 04:41:14.075623 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1506 04:41:14.082257 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 04:41:14.085455 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 04:41:14.088921 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 04:41:14.095345 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 04:41:14.098717 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 04:41:14.102189 0 9 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1512 04:41:14.108868 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 04:41:14.112135 0 9 8 | B1->B0 | 2727 2929 | 0 0 | (0 0) (0 0)
1514 04:41:14.115672 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 04:41:14.122153 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 04:41:14.125729 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 04:41:14.128921 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 04:41:14.132115 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 04:41:14.138934 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 04:41:14.141985 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1521 04:41:14.145457 0 10 8 | B1->B0 | 2b2b 2e2e | 0 0 | (0 0) (1 0)
1522 04:41:14.152124 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 04:41:14.155587 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 04:41:14.158548 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 04:41:14.165354 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 04:41:14.168744 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 04:41:14.172162 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 04:41:14.178714 0 11 4 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
1529 04:41:14.182100 0 11 8 | B1->B0 | 3535 3636 | 1 1 | (0 0) (0 0)
1530 04:41:14.185080 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 04:41:14.192103 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 04:41:14.195259 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 04:41:14.198445 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 04:41:14.205077 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 04:41:14.208730 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 04:41:14.211987 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 04:41:14.218718 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1538 04:41:14.221896 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 04:41:14.225584 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 04:41:14.231889 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 04:41:14.235535 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 04:41:14.238554 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 04:41:14.241949 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 04:41:14.248864 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 04:41:14.252150 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 04:41:14.255410 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 04:41:14.261939 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 04:41:14.265340 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 04:41:14.268702 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 04:41:14.275182 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 04:41:14.278522 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 04:41:14.282206 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 04:41:14.289135 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1554 04:41:14.289302 Total UI for P1: 0, mck2ui 16
1555 04:41:14.295245 best dqsien dly found for B1: ( 0, 14, 6)
1556 04:41:14.298667 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 04:41:14.302267 Total UI for P1: 0, mck2ui 16
1558 04:41:14.305454 best dqsien dly found for B0: ( 0, 14, 8)
1559 04:41:14.308599 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1560 04:41:14.311977 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1561 04:41:14.312123
1562 04:41:14.315313 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1563 04:41:14.318788 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1564 04:41:14.322006 [Gating] SW calibration Done
1565 04:41:14.322126 ==
1566 04:41:14.325154 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 04:41:14.328930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 04:41:14.329052 ==
1569 04:41:14.331929 RX Vref Scan: 0
1570 04:41:14.332019
1571 04:41:14.335412 RX Vref 0 -> 0, step: 1
1572 04:41:14.335516
1573 04:41:14.335587 RX Delay -130 -> 252, step: 16
1574 04:41:14.342285 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1575 04:41:14.345281 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1576 04:41:14.348689 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1577 04:41:14.352187 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1578 04:41:14.355302 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1579 04:41:14.361922 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1580 04:41:14.365136 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1581 04:41:14.368574 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1582 04:41:14.371995 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1583 04:41:14.375175 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1584 04:41:14.382104 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1585 04:41:14.385285 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1586 04:41:14.388572 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1587 04:41:14.392086 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1588 04:41:14.395397 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1589 04:41:14.401855 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1590 04:41:14.402001 ==
1591 04:41:14.405181 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 04:41:14.408548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 04:41:14.408683 ==
1594 04:41:14.408757 DQS Delay:
1595 04:41:14.411785 DQS0 = 0, DQS1 = 0
1596 04:41:14.411885 DQM Delay:
1597 04:41:14.415302 DQM0 = 81, DQM1 = 70
1598 04:41:14.415404 DQ Delay:
1599 04:41:14.418640 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1600 04:41:14.421869 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1601 04:41:14.425427 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1602 04:41:14.428614 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1603 04:41:14.428728
1604 04:41:14.428797
1605 04:41:14.428859 ==
1606 04:41:14.431842 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 04:41:14.435397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 04:41:14.435507 ==
1609 04:41:14.438382
1610 04:41:14.438511
1611 04:41:14.438581 TX Vref Scan disable
1612 04:41:14.441808 == TX Byte 0 ==
1613 04:41:14.445318 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1614 04:41:14.448498 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1615 04:41:14.451866 == TX Byte 1 ==
1616 04:41:14.455454 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1617 04:41:14.458456 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1618 04:41:14.458588 ==
1619 04:41:14.461952 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 04:41:14.468625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 04:41:14.468770 ==
1622 04:41:14.480279 TX Vref=22, minBit 1, minWin=26, winSum=439
1623 04:41:14.483787 TX Vref=24, minBit 0, minWin=27, winSum=441
1624 04:41:14.486877 TX Vref=26, minBit 4, minWin=27, winSum=443
1625 04:41:14.490359 TX Vref=28, minBit 1, minWin=27, winSum=444
1626 04:41:14.493530 TX Vref=30, minBit 0, minWin=27, winSum=447
1627 04:41:14.496757 TX Vref=32, minBit 5, minWin=27, winSum=447
1628 04:41:14.503508 [TxChooseVref] Worse bit 0, Min win 27, Win sum 447, Final Vref 30
1629 04:41:14.503678
1630 04:41:14.506944 Final TX Range 1 Vref 30
1631 04:41:14.507049
1632 04:41:14.507119 ==
1633 04:41:14.510116 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 04:41:14.513469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 04:41:14.513608 ==
1636 04:41:14.513706
1637 04:41:14.517289
1638 04:41:14.517391 TX Vref Scan disable
1639 04:41:14.520702 == TX Byte 0 ==
1640 04:41:14.523855 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1641 04:41:14.527214 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1642 04:41:14.530712 == TX Byte 1 ==
1643 04:41:14.533844 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1644 04:41:14.537057 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1645 04:41:14.537158
1646 04:41:14.540646 [DATLAT]
1647 04:41:14.540752 Freq=800, CH1 RK0
1648 04:41:14.540817
1649 04:41:14.544028 DATLAT Default: 0xa
1650 04:41:14.544128 0, 0xFFFF, sum = 0
1651 04:41:14.547349 1, 0xFFFF, sum = 0
1652 04:41:14.547454 2, 0xFFFF, sum = 0
1653 04:41:14.550502 3, 0xFFFF, sum = 0
1654 04:41:14.550636 4, 0xFFFF, sum = 0
1655 04:41:14.553863 5, 0xFFFF, sum = 0
1656 04:41:14.553981 6, 0xFFFF, sum = 0
1657 04:41:14.557227 7, 0xFFFF, sum = 0
1658 04:41:14.557372 8, 0xFFFF, sum = 0
1659 04:41:14.560410 9, 0x0, sum = 1
1660 04:41:14.560553 10, 0x0, sum = 2
1661 04:41:14.564011 11, 0x0, sum = 3
1662 04:41:14.564131 12, 0x0, sum = 4
1663 04:41:14.567215 best_step = 10
1664 04:41:14.567327
1665 04:41:14.567428 ==
1666 04:41:14.570661 Dram Type= 6, Freq= 0, CH_1, rank 0
1667 04:41:14.573794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1668 04:41:14.573915 ==
1669 04:41:14.577271 RX Vref Scan: 1
1670 04:41:14.577384
1671 04:41:14.577455 Set Vref Range= 32 -> 127
1672 04:41:14.577564
1673 04:41:14.580412 RX Vref 32 -> 127, step: 1
1674 04:41:14.580529
1675 04:41:14.583853 RX Delay -111 -> 252, step: 8
1676 04:41:14.583950
1677 04:41:14.587254 Set Vref, RX VrefLevel [Byte0]: 32
1678 04:41:14.590662 [Byte1]: 32
1679 04:41:14.590772
1680 04:41:14.594157 Set Vref, RX VrefLevel [Byte0]: 33
1681 04:41:14.597331 [Byte1]: 33
1682 04:41:14.600849
1683 04:41:14.600988 Set Vref, RX VrefLevel [Byte0]: 34
1684 04:41:14.603893 [Byte1]: 34
1685 04:41:14.608312
1686 04:41:14.608435 Set Vref, RX VrefLevel [Byte0]: 35
1687 04:41:14.611537 [Byte1]: 35
1688 04:41:14.615872
1689 04:41:14.615990 Set Vref, RX VrefLevel [Byte0]: 36
1690 04:41:14.619265 [Byte1]: 36
1691 04:41:14.623604
1692 04:41:14.623727 Set Vref, RX VrefLevel [Byte0]: 37
1693 04:41:14.627098 [Byte1]: 37
1694 04:41:14.631293
1695 04:41:14.631414 Set Vref, RX VrefLevel [Byte0]: 38
1696 04:41:14.634655 [Byte1]: 38
1697 04:41:14.638955
1698 04:41:14.639076 Set Vref, RX VrefLevel [Byte0]: 39
1699 04:41:14.642185 [Byte1]: 39
1700 04:41:14.646538
1701 04:41:14.646653 Set Vref, RX VrefLevel [Byte0]: 40
1702 04:41:14.650006 [Byte1]: 40
1703 04:41:14.653995
1704 04:41:14.654110 Set Vref, RX VrefLevel [Byte0]: 41
1705 04:41:14.657277 [Byte1]: 41
1706 04:41:14.661728
1707 04:41:14.661850 Set Vref, RX VrefLevel [Byte0]: 42
1708 04:41:14.664945 [Byte1]: 42
1709 04:41:14.669651
1710 04:41:14.669775 Set Vref, RX VrefLevel [Byte0]: 43
1711 04:41:14.672785 [Byte1]: 43
1712 04:41:14.676988
1713 04:41:14.677112 Set Vref, RX VrefLevel [Byte0]: 44
1714 04:41:14.680219 [Byte1]: 44
1715 04:41:14.684799
1716 04:41:14.684923 Set Vref, RX VrefLevel [Byte0]: 45
1717 04:41:14.688184 [Byte1]: 45
1718 04:41:14.692379
1719 04:41:14.692493 Set Vref, RX VrefLevel [Byte0]: 46
1720 04:41:14.695652 [Byte1]: 46
1721 04:41:14.700018
1722 04:41:14.700139 Set Vref, RX VrefLevel [Byte0]: 47
1723 04:41:14.703564 [Byte1]: 47
1724 04:41:14.707798
1725 04:41:14.707914 Set Vref, RX VrefLevel [Byte0]: 48
1726 04:41:14.710868 [Byte1]: 48
1727 04:41:14.715368
1728 04:41:14.715491 Set Vref, RX VrefLevel [Byte0]: 49
1729 04:41:14.718789 [Byte1]: 49
1730 04:41:14.723246
1731 04:41:14.723386 Set Vref, RX VrefLevel [Byte0]: 50
1732 04:41:14.726247 [Byte1]: 50
1733 04:41:14.730634
1734 04:41:14.730774 Set Vref, RX VrefLevel [Byte0]: 51
1735 04:41:14.733812 [Byte1]: 51
1736 04:41:14.738395
1737 04:41:14.738571 Set Vref, RX VrefLevel [Byte0]: 52
1738 04:41:14.741518 [Byte1]: 52
1739 04:41:14.745870
1740 04:41:14.746006 Set Vref, RX VrefLevel [Byte0]: 53
1741 04:41:14.752283 [Byte1]: 53
1742 04:41:14.752433
1743 04:41:14.755860 Set Vref, RX VrefLevel [Byte0]: 54
1744 04:41:14.759061 [Byte1]: 54
1745 04:41:14.759202
1746 04:41:14.762507 Set Vref, RX VrefLevel [Byte0]: 55
1747 04:41:14.765648 [Byte1]: 55
1748 04:41:14.765771
1749 04:41:14.769245 Set Vref, RX VrefLevel [Byte0]: 56
1750 04:41:14.772368 [Byte1]: 56
1751 04:41:14.776402
1752 04:41:14.776533 Set Vref, RX VrefLevel [Byte0]: 57
1753 04:41:14.779877 [Byte1]: 57
1754 04:41:14.784250
1755 04:41:14.784391 Set Vref, RX VrefLevel [Byte0]: 58
1756 04:41:14.787415 [Byte1]: 58
1757 04:41:14.791670
1758 04:41:14.791799 Set Vref, RX VrefLevel [Byte0]: 59
1759 04:41:14.794992 [Byte1]: 59
1760 04:41:14.799392
1761 04:41:14.799535 Set Vref, RX VrefLevel [Byte0]: 60
1762 04:41:14.802833 [Byte1]: 60
1763 04:41:14.807008
1764 04:41:14.807150 Set Vref, RX VrefLevel [Byte0]: 61
1765 04:41:14.810231 [Byte1]: 61
1766 04:41:14.814969
1767 04:41:14.815123 Set Vref, RX VrefLevel [Byte0]: 62
1768 04:41:14.818296 [Byte1]: 62
1769 04:41:14.822583
1770 04:41:14.822702 Set Vref, RX VrefLevel [Byte0]: 63
1771 04:41:14.825610 [Byte1]: 63
1772 04:41:14.829976
1773 04:41:14.830090 Set Vref, RX VrefLevel [Byte0]: 64
1774 04:41:14.833215 [Byte1]: 64
1775 04:41:14.837902
1776 04:41:14.838017 Set Vref, RX VrefLevel [Byte0]: 65
1777 04:41:14.841136 [Byte1]: 65
1778 04:41:14.845457
1779 04:41:14.845596 Set Vref, RX VrefLevel [Byte0]: 66
1780 04:41:14.848655 [Byte1]: 66
1781 04:41:14.852897
1782 04:41:14.853040 Set Vref, RX VrefLevel [Byte0]: 67
1783 04:41:14.856120 [Byte1]: 67
1784 04:41:14.860527
1785 04:41:14.860655 Set Vref, RX VrefLevel [Byte0]: 68
1786 04:41:14.864298 [Byte1]: 68
1787 04:41:14.868147
1788 04:41:14.868276 Set Vref, RX VrefLevel [Byte0]: 69
1789 04:41:14.871613 [Byte1]: 69
1790 04:41:14.876077
1791 04:41:14.876210 Set Vref, RX VrefLevel [Byte0]: 70
1792 04:41:14.879169 [Byte1]: 70
1793 04:41:14.883506
1794 04:41:14.883643 Set Vref, RX VrefLevel [Byte0]: 71
1795 04:41:14.887112 [Byte1]: 71
1796 04:41:14.891088
1797 04:41:14.891219 Set Vref, RX VrefLevel [Byte0]: 72
1798 04:41:14.894599 [Byte1]: 72
1799 04:41:14.898967
1800 04:41:14.899103 Set Vref, RX VrefLevel [Byte0]: 73
1801 04:41:14.902200 [Byte1]: 73
1802 04:41:14.906664
1803 04:41:14.906816 Final RX Vref Byte 0 = 60 to rank0
1804 04:41:14.909734 Final RX Vref Byte 1 = 55 to rank0
1805 04:41:14.913208 Final RX Vref Byte 0 = 60 to rank1
1806 04:41:14.916456 Final RX Vref Byte 1 = 55 to rank1==
1807 04:41:14.919589 Dram Type= 6, Freq= 0, CH_1, rank 0
1808 04:41:14.926613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 04:41:14.926750 ==
1810 04:41:14.926822 DQS Delay:
1811 04:41:14.926886 DQS0 = 0, DQS1 = 0
1812 04:41:14.929647 DQM Delay:
1813 04:41:14.929729 DQM0 = 81, DQM1 = 71
1814 04:41:14.933209 DQ Delay:
1815 04:41:14.936423 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1816 04:41:14.936527 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1817 04:41:14.939943 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1818 04:41:14.946611 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1819 04:41:14.946752
1820 04:41:14.946825
1821 04:41:14.953394 [DQSOSCAuto] RK0, (LSB)MR18= 0x151f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
1822 04:41:14.956602 CH1 RK0: MR19=606, MR18=151F
1823 04:41:14.963313 CH1_RK0: MR19=0x606, MR18=0x151F, DQSOSC=402, MR23=63, INC=91, DEC=60
1824 04:41:14.963479
1825 04:41:14.966485 ----->DramcWriteLeveling(PI) begin...
1826 04:41:14.966606 ==
1827 04:41:14.969983 Dram Type= 6, Freq= 0, CH_1, rank 1
1828 04:41:14.973157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1829 04:41:14.973280 ==
1830 04:41:14.976693 Write leveling (Byte 0): 26 => 26
1831 04:41:14.979950 Write leveling (Byte 1): 28 => 28
1832 04:41:14.983108 DramcWriteLeveling(PI) end<-----
1833 04:41:14.983234
1834 04:41:14.983318 ==
1835 04:41:14.986748 Dram Type= 6, Freq= 0, CH_1, rank 1
1836 04:41:14.989735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1837 04:41:14.989838 ==
1838 04:41:14.993307 [Gating] SW mode calibration
1839 04:41:14.999683 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1840 04:41:15.006406 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1841 04:41:15.009896 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1842 04:41:15.012907 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1843 04:41:15.019647 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 04:41:15.022875 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 04:41:15.026449 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 04:41:15.033161 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 04:41:15.036560 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 04:41:15.039833 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 04:41:15.046156 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 04:41:15.049426 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 04:41:15.053036 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 04:41:15.059558 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 04:41:15.062993 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 04:41:15.066124 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 04:41:15.073023 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 04:41:15.076173 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 04:41:15.079481 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 04:41:15.086032 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1859 04:41:15.089422 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1860 04:41:15.092729 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 04:41:15.096305 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 04:41:15.102796 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 04:41:15.106302 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 04:41:15.109384 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 04:41:15.116091 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 04:41:15.119794 0 9 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1867 04:41:15.122718 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1868 04:41:15.129619 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1869 04:41:15.132790 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1870 04:41:15.136312 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1871 04:41:15.142704 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1872 04:41:15.146251 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1873 04:41:15.149648 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 04:41:15.155942 0 10 4 | B1->B0 | 3232 2c2c | 0 0 | (0 1) (1 0)
1875 04:41:15.159501 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1876 04:41:15.162869 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 04:41:15.169363 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 04:41:15.172823 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 04:41:15.176370 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 04:41:15.182756 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 04:41:15.186206 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1882 04:41:15.189506 0 11 4 | B1->B0 | 2424 3636 | 0 1 | (0 0) (0 0)
1883 04:41:15.192831 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1884 04:41:15.199489 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 04:41:15.202913 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 04:41:15.205980 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 04:41:15.212642 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 04:41:15.216324 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 04:41:15.219514 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1890 04:41:15.226094 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1891 04:41:15.229463 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 04:41:15.232952 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 04:41:15.239465 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 04:41:15.242677 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 04:41:15.245912 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 04:41:15.252754 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 04:41:15.255952 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 04:41:15.259274 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 04:41:15.265945 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 04:41:15.269172 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 04:41:15.272723 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 04:41:15.279323 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 04:41:15.282666 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 04:41:15.286012 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 04:41:15.292709 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 04:41:15.296179 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1907 04:41:15.299197 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 04:41:15.302565 Total UI for P1: 0, mck2ui 16
1909 04:41:15.305900 best dqsien dly found for B0: ( 0, 14, 4)
1910 04:41:15.309067 Total UI for P1: 0, mck2ui 16
1911 04:41:15.312553 best dqsien dly found for B1: ( 0, 14, 6)
1912 04:41:15.315947 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1913 04:41:15.319203 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1914 04:41:15.319319
1915 04:41:15.322409 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1916 04:41:15.325891 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1917 04:41:15.329435 [Gating] SW calibration Done
1918 04:41:15.329570 ==
1919 04:41:15.332616 Dram Type= 6, Freq= 0, CH_1, rank 1
1920 04:41:15.339070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1921 04:41:15.339215 ==
1922 04:41:15.339290 RX Vref Scan: 0
1923 04:41:15.339370
1924 04:41:15.342887 RX Vref 0 -> 0, step: 1
1925 04:41:15.342976
1926 04:41:15.346063 RX Delay -130 -> 252, step: 16
1927 04:41:15.349327 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1928 04:41:15.352799 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1929 04:41:15.356226 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1930 04:41:15.359365 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1931 04:41:15.366101 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1932 04:41:15.369315 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1933 04:41:15.372866 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1934 04:41:15.376409 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1935 04:41:15.379484 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1936 04:41:15.383053 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1937 04:41:15.389869 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1938 04:41:15.393074 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1939 04:41:15.396316 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1940 04:41:15.399570 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1941 04:41:15.406544 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1942 04:41:15.409916 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1943 04:41:15.410042 ==
1944 04:41:15.412914 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 04:41:15.416397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 04:41:15.416520 ==
1947 04:41:15.416591 DQS Delay:
1948 04:41:15.419882 DQS0 = 0, DQS1 = 0
1949 04:41:15.420004 DQM Delay:
1950 04:41:15.423123 DQM0 = 77, DQM1 = 74
1951 04:41:15.423251 DQ Delay:
1952 04:41:15.426356 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1953 04:41:15.429822 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1954 04:41:15.433101 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1955 04:41:15.436320 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
1956 04:41:15.436429
1957 04:41:15.436500
1958 04:41:15.436567 ==
1959 04:41:15.439771 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 04:41:15.443057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 04:41:15.443154 ==
1962 04:41:15.446409
1963 04:41:15.446523
1964 04:41:15.446619 TX Vref Scan disable
1965 04:41:15.449783 == TX Byte 0 ==
1966 04:41:15.453119 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1967 04:41:15.456668 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1968 04:41:15.459642 == TX Byte 1 ==
1969 04:41:15.463091 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1970 04:41:15.466637 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1971 04:41:15.466782 ==
1972 04:41:15.469773 Dram Type= 6, Freq= 0, CH_1, rank 1
1973 04:41:15.476325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1974 04:41:15.476497 ==
1975 04:41:15.488326 TX Vref=22, minBit 0, minWin=28, winSum=451
1976 04:41:15.491711 TX Vref=24, minBit 3, minWin=28, winSum=456
1977 04:41:15.494916 TX Vref=26, minBit 1, minWin=28, winSum=456
1978 04:41:15.498325 TX Vref=28, minBit 1, minWin=28, winSum=462
1979 04:41:15.501857 TX Vref=30, minBit 1, minWin=28, winSum=464
1980 04:41:15.505103 TX Vref=32, minBit 1, minWin=27, winSum=461
1981 04:41:15.511511 [TxChooseVref] Worse bit 1, Min win 28, Win sum 464, Final Vref 30
1982 04:41:15.511656
1983 04:41:15.514782 Final TX Range 1 Vref 30
1984 04:41:15.514884
1985 04:41:15.514974 ==
1986 04:41:15.518275 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 04:41:15.521692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 04:41:15.521801 ==
1989 04:41:15.524945
1990 04:41:15.525043
1991 04:41:15.525134 TX Vref Scan disable
1992 04:41:15.528187 == TX Byte 0 ==
1993 04:41:15.531396 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1994 04:41:15.538163 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1995 04:41:15.538303 == TX Byte 1 ==
1996 04:41:15.541628 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1997 04:41:15.548286 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1998 04:41:15.548491
1999 04:41:15.548669 [DATLAT]
2000 04:41:15.548774 Freq=800, CH1 RK1
2001 04:41:15.548887
2002 04:41:15.551328 DATLAT Default: 0xa
2003 04:41:15.551427 0, 0xFFFF, sum = 0
2004 04:41:15.554690 1, 0xFFFF, sum = 0
2005 04:41:15.557969 2, 0xFFFF, sum = 0
2006 04:41:15.558134 3, 0xFFFF, sum = 0
2007 04:41:15.561331 4, 0xFFFF, sum = 0
2008 04:41:15.561467 5, 0xFFFF, sum = 0
2009 04:41:15.564802 6, 0xFFFF, sum = 0
2010 04:41:15.564897 7, 0xFFFF, sum = 0
2011 04:41:15.567967 8, 0xFFFF, sum = 0
2012 04:41:15.568060 9, 0x0, sum = 1
2013 04:41:15.568150 10, 0x0, sum = 2
2014 04:41:15.571326 11, 0x0, sum = 3
2015 04:41:15.571417 12, 0x0, sum = 4
2016 04:41:15.574502 best_step = 10
2017 04:41:15.574647
2018 04:41:15.574739 ==
2019 04:41:15.577875 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 04:41:15.581151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 04:41:15.581286 ==
2022 04:41:15.584524 RX Vref Scan: 0
2023 04:41:15.584653
2024 04:41:15.584745 RX Vref 0 -> 0, step: 1
2025 04:41:15.588070
2026 04:41:15.588173 RX Delay -111 -> 252, step: 8
2027 04:41:15.594874 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2028 04:41:15.598359 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2029 04:41:15.601887 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2030 04:41:15.604939 iDelay=209, Bit 3, Center 76 (-47 ~ 200) 248
2031 04:41:15.608541 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2032 04:41:15.615136 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2033 04:41:15.618530 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2034 04:41:15.621898 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2035 04:41:15.625292 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2036 04:41:15.628632 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2037 04:41:15.635303 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2038 04:41:15.638562 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2039 04:41:15.641814 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2040 04:41:15.645094 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2041 04:41:15.648335 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2042 04:41:15.655265 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2043 04:41:15.655413 ==
2044 04:41:15.658310 Dram Type= 6, Freq= 0, CH_1, rank 1
2045 04:41:15.661719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2046 04:41:15.661840 ==
2047 04:41:15.661924 DQS Delay:
2048 04:41:15.664979 DQS0 = 0, DQS1 = 0
2049 04:41:15.665072 DQM Delay:
2050 04:41:15.668709 DQM0 = 78, DQM1 = 74
2051 04:41:15.668808 DQ Delay:
2052 04:41:15.671843 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =76
2053 04:41:15.674965 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2054 04:41:15.678339 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =68
2055 04:41:15.681565 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2056 04:41:15.681681
2057 04:41:15.681754
2058 04:41:15.691579 [DQSOSCAuto] RK1, (LSB)MR18= 0x273e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2059 04:41:15.691734 CH1 RK1: MR19=606, MR18=273E
2060 04:41:15.698224 CH1_RK1: MR19=0x606, MR18=0x273E, DQSOSC=394, MR23=63, INC=95, DEC=63
2061 04:41:15.701683 [RxdqsGatingPostProcess] freq 800
2062 04:41:15.708102 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2063 04:41:15.711484 Pre-setting of DQS Precalculation
2064 04:41:15.714873 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2065 04:41:15.721885 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2066 04:41:15.728324 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2067 04:41:15.728474
2068 04:41:15.731629
2069 04:41:15.731728 [Calibration Summary] 1600 Mbps
2070 04:41:15.734974 CH 0, Rank 0
2071 04:41:15.735076 SW Impedance : PASS
2072 04:41:15.738203 DUTY Scan : NO K
2073 04:41:15.741822 ZQ Calibration : PASS
2074 04:41:15.741946 Jitter Meter : NO K
2075 04:41:15.744906 CBT Training : PASS
2076 04:41:15.748131 Write leveling : PASS
2077 04:41:15.748236 RX DQS gating : PASS
2078 04:41:15.751643 RX DQ/DQS(RDDQC) : PASS
2079 04:41:15.755265 TX DQ/DQS : PASS
2080 04:41:15.755374 RX DATLAT : PASS
2081 04:41:15.758460 RX DQ/DQS(Engine): PASS
2082 04:41:15.758626 TX OE : NO K
2083 04:41:15.761656 All Pass.
2084 04:41:15.761753
2085 04:41:15.761820 CH 0, Rank 1
2086 04:41:15.765105 SW Impedance : PASS
2087 04:41:15.765203 DUTY Scan : NO K
2088 04:41:15.768273 ZQ Calibration : PASS
2089 04:41:15.771854 Jitter Meter : NO K
2090 04:41:15.771963 CBT Training : PASS
2091 04:41:15.775097 Write leveling : PASS
2092 04:41:15.778278 RX DQS gating : PASS
2093 04:41:15.778387 RX DQ/DQS(RDDQC) : PASS
2094 04:41:15.781443 TX DQ/DQS : PASS
2095 04:41:15.785011 RX DATLAT : PASS
2096 04:41:15.785149 RX DQ/DQS(Engine): PASS
2097 04:41:15.788209 TX OE : NO K
2098 04:41:15.788308 All Pass.
2099 04:41:15.788374
2100 04:41:15.791703 CH 1, Rank 0
2101 04:41:15.791805 SW Impedance : PASS
2102 04:41:15.794856 DUTY Scan : NO K
2103 04:41:15.798410 ZQ Calibration : PASS
2104 04:41:15.798517 Jitter Meter : NO K
2105 04:41:15.801608 CBT Training : PASS
2106 04:41:15.801706 Write leveling : PASS
2107 04:41:15.804876 RX DQS gating : PASS
2108 04:41:15.808313 RX DQ/DQS(RDDQC) : PASS
2109 04:41:15.808424 TX DQ/DQS : PASS
2110 04:41:15.811648 RX DATLAT : PASS
2111 04:41:15.815091 RX DQ/DQS(Engine): PASS
2112 04:41:15.815204 TX OE : NO K
2113 04:41:15.818248 All Pass.
2114 04:41:15.818347
2115 04:41:15.818431 CH 1, Rank 1
2116 04:41:15.821644 SW Impedance : PASS
2117 04:41:15.821771 DUTY Scan : NO K
2118 04:41:15.824913 ZQ Calibration : PASS
2119 04:41:15.828419 Jitter Meter : NO K
2120 04:41:15.828530 CBT Training : PASS
2121 04:41:15.831925 Write leveling : PASS
2122 04:41:15.835318 RX DQS gating : PASS
2123 04:41:15.835460 RX DQ/DQS(RDDQC) : PASS
2124 04:41:15.838566 TX DQ/DQS : PASS
2125 04:41:15.838665 RX DATLAT : PASS
2126 04:41:15.841748 RX DQ/DQS(Engine): PASS
2127 04:41:15.845164 TX OE : NO K
2128 04:41:15.845287 All Pass.
2129 04:41:15.845357
2130 04:41:15.848463 DramC Write-DBI off
2131 04:41:15.848564 PER_BANK_REFRESH: Hybrid Mode
2132 04:41:15.851950 TX_TRACKING: ON
2133 04:41:15.855070 [GetDramInforAfterCalByMRR] Vendor 6.
2134 04:41:15.858532 [GetDramInforAfterCalByMRR] Revision 606.
2135 04:41:15.861887 [GetDramInforAfterCalByMRR] Revision 2 0.
2136 04:41:15.862012 MR0 0x3b3b
2137 04:41:15.865085 MR8 0x5151
2138 04:41:15.868639 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2139 04:41:15.868782
2140 04:41:15.868853 MR0 0x3b3b
2141 04:41:15.871479 MR8 0x5151
2142 04:41:15.874923 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2143 04:41:15.875066
2144 04:41:15.881900 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2145 04:41:15.885115 [FAST_K] Save calibration result to emmc
2146 04:41:15.891871 [FAST_K] Save calibration result to emmc
2147 04:41:15.892013 dram_init: config_dvfs: 1
2148 04:41:15.894901 dramc_set_vcore_voltage set vcore to 662500
2149 04:41:15.898490 Read voltage for 1200, 2
2150 04:41:15.898598 Vio18 = 0
2151 04:41:15.901597 Vcore = 662500
2152 04:41:15.901693 Vdram = 0
2153 04:41:15.901776 Vddq = 0
2154 04:41:15.904995 Vmddr = 0
2155 04:41:15.908282 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2156 04:41:15.915202 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2157 04:41:15.915344 MEM_TYPE=3, freq_sel=15
2158 04:41:15.918300 sv_algorithm_assistance_LP4_1600
2159 04:41:15.924891 ============ PULL DRAM RESETB DOWN ============
2160 04:41:15.928141 ========== PULL DRAM RESETB DOWN end =========
2161 04:41:15.931480 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2162 04:41:15.935089 ===================================
2163 04:41:15.938162 LPDDR4 DRAM CONFIGURATION
2164 04:41:15.941796 ===================================
2165 04:41:15.941915 EX_ROW_EN[0] = 0x0
2166 04:41:15.945151 EX_ROW_EN[1] = 0x0
2167 04:41:15.948341 LP4Y_EN = 0x0
2168 04:41:15.948457 WORK_FSP = 0x0
2169 04:41:15.951663 WL = 0x4
2170 04:41:15.951767 RL = 0x4
2171 04:41:15.954952 BL = 0x2
2172 04:41:15.955057 RPST = 0x0
2173 04:41:15.958083 RD_PRE = 0x0
2174 04:41:15.958181 WR_PRE = 0x1
2175 04:41:15.961569 WR_PST = 0x0
2176 04:41:15.961683 DBI_WR = 0x0
2177 04:41:15.964998 DBI_RD = 0x0
2178 04:41:15.965100 OTF = 0x1
2179 04:41:15.968390 ===================================
2180 04:41:15.971556 ===================================
2181 04:41:15.975152 ANA top config
2182 04:41:15.978274 ===================================
2183 04:41:15.978388 DLL_ASYNC_EN = 0
2184 04:41:15.981464 ALL_SLAVE_EN = 0
2185 04:41:15.984990 NEW_RANK_MODE = 1
2186 04:41:15.988237 DLL_IDLE_MODE = 1
2187 04:41:15.991357 LP45_APHY_COMB_EN = 1
2188 04:41:15.991465 TX_ODT_DIS = 1
2189 04:41:15.994929 NEW_8X_MODE = 1
2190 04:41:15.997986 ===================================
2191 04:41:16.001471 ===================================
2192 04:41:16.004655 data_rate = 2400
2193 04:41:16.008296 CKR = 1
2194 04:41:16.011477 DQ_P2S_RATIO = 8
2195 04:41:16.014892 ===================================
2196 04:41:16.015008 CA_P2S_RATIO = 8
2197 04:41:16.018156 DQ_CA_OPEN = 0
2198 04:41:16.021692 DQ_SEMI_OPEN = 0
2199 04:41:16.024977 CA_SEMI_OPEN = 0
2200 04:41:16.028187 CA_FULL_RATE = 0
2201 04:41:16.031361 DQ_CKDIV4_EN = 0
2202 04:41:16.031471 CA_CKDIV4_EN = 0
2203 04:41:16.034785 CA_PREDIV_EN = 0
2204 04:41:16.038016 PH8_DLY = 17
2205 04:41:16.041487 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2206 04:41:16.044998 DQ_AAMCK_DIV = 4
2207 04:41:16.048354 CA_AAMCK_DIV = 4
2208 04:41:16.048474 CA_ADMCK_DIV = 4
2209 04:41:16.051252 DQ_TRACK_CA_EN = 0
2210 04:41:16.054529 CA_PICK = 1200
2211 04:41:16.058368 CA_MCKIO = 1200
2212 04:41:16.061414 MCKIO_SEMI = 0
2213 04:41:16.064611 PLL_FREQ = 2366
2214 04:41:16.067846 DQ_UI_PI_RATIO = 32
2215 04:41:16.067959 CA_UI_PI_RATIO = 0
2216 04:41:16.071306 ===================================
2217 04:41:16.074791 ===================================
2218 04:41:16.078131 memory_type:LPDDR4
2219 04:41:16.081387 GP_NUM : 10
2220 04:41:16.081530 SRAM_EN : 1
2221 04:41:16.084573 MD32_EN : 0
2222 04:41:16.088050 ===================================
2223 04:41:16.091247 [ANA_INIT] >>>>>>>>>>>>>>
2224 04:41:16.094474 <<<<<< [CONFIGURE PHASE]: ANA_TX
2225 04:41:16.098049 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2226 04:41:16.101571 ===================================
2227 04:41:16.101683 data_rate = 2400,PCW = 0X5b00
2228 04:41:16.104822 ===================================
2229 04:41:16.108080 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2230 04:41:16.114689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2231 04:41:16.121298 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2232 04:41:16.124850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2233 04:41:16.128026 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2234 04:41:16.131247 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2235 04:41:16.134518 [ANA_INIT] flow start
2236 04:41:16.134636 [ANA_INIT] PLL >>>>>>>>
2237 04:41:16.137747 [ANA_INIT] PLL <<<<<<<<
2238 04:41:16.141292 [ANA_INIT] MIDPI >>>>>>>>
2239 04:41:16.144452 [ANA_INIT] MIDPI <<<<<<<<
2240 04:41:16.144563 [ANA_INIT] DLL >>>>>>>>
2241 04:41:16.148079 [ANA_INIT] DLL <<<<<<<<
2242 04:41:16.151188 [ANA_INIT] flow end
2243 04:41:16.154744 ============ LP4 DIFF to SE enter ============
2244 04:41:16.158159 ============ LP4 DIFF to SE exit ============
2245 04:41:16.161156 [ANA_INIT] <<<<<<<<<<<<<
2246 04:41:16.164497 [Flow] Enable top DCM control >>>>>
2247 04:41:16.168083 [Flow] Enable top DCM control <<<<<
2248 04:41:16.171335 Enable DLL master slave shuffle
2249 04:41:16.174741 ==============================================================
2250 04:41:16.177726 Gating Mode config
2251 04:41:16.181302 ==============================================================
2252 04:41:16.184582 Config description:
2253 04:41:16.194576 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2254 04:41:16.201275 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2255 04:41:16.204746 SELPH_MODE 0: By rank 1: By Phase
2256 04:41:16.211367 ==============================================================
2257 04:41:16.214508 GAT_TRACK_EN = 1
2258 04:41:16.217998 RX_GATING_MODE = 2
2259 04:41:16.221103 RX_GATING_TRACK_MODE = 2
2260 04:41:16.224712 SELPH_MODE = 1
2261 04:41:16.224836 PICG_EARLY_EN = 1
2262 04:41:16.227881 VALID_LAT_VALUE = 1
2263 04:41:16.234933 ==============================================================
2264 04:41:16.238007 Enter into Gating configuration >>>>
2265 04:41:16.241253 Exit from Gating configuration <<<<
2266 04:41:16.244987 Enter into DVFS_PRE_config >>>>>
2267 04:41:16.254904 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2268 04:41:16.258221 Exit from DVFS_PRE_config <<<<<
2269 04:41:16.261292 Enter into PICG configuration >>>>
2270 04:41:16.264852 Exit from PICG configuration <<<<
2271 04:41:16.268322 [RX_INPUT] configuration >>>>>
2272 04:41:16.271293 [RX_INPUT] configuration <<<<<
2273 04:41:16.274869 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2274 04:41:16.281656 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2275 04:41:16.288079 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2276 04:41:16.294681 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2277 04:41:16.298304 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2278 04:41:16.304614 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2279 04:41:16.308281 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2280 04:41:16.314809 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2281 04:41:16.318230 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2282 04:41:16.321417 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2283 04:41:16.324787 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2284 04:41:16.331359 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2285 04:41:16.335096 ===================================
2286 04:41:16.335232 LPDDR4 DRAM CONFIGURATION
2287 04:41:16.338327 ===================================
2288 04:41:16.341354 EX_ROW_EN[0] = 0x0
2289 04:41:16.344991 EX_ROW_EN[1] = 0x0
2290 04:41:16.345103 LP4Y_EN = 0x0
2291 04:41:16.348063 WORK_FSP = 0x0
2292 04:41:16.348182 WL = 0x4
2293 04:41:16.351516 RL = 0x4
2294 04:41:16.351608 BL = 0x2
2295 04:41:16.354804 RPST = 0x0
2296 04:41:16.354896 RD_PRE = 0x0
2297 04:41:16.358295 WR_PRE = 0x1
2298 04:41:16.358397 WR_PST = 0x0
2299 04:41:16.361653 DBI_WR = 0x0
2300 04:41:16.361768 DBI_RD = 0x0
2301 04:41:16.364863 OTF = 0x1
2302 04:41:16.368101 ===================================
2303 04:41:16.371569 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2304 04:41:16.375126 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2305 04:41:16.381626 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2306 04:41:16.385129 ===================================
2307 04:41:16.385242 LPDDR4 DRAM CONFIGURATION
2308 04:41:16.388304 ===================================
2309 04:41:16.391846 EX_ROW_EN[0] = 0x10
2310 04:41:16.391963 EX_ROW_EN[1] = 0x0
2311 04:41:16.394997 LP4Y_EN = 0x0
2312 04:41:16.395098 WORK_FSP = 0x0
2313 04:41:16.398503 WL = 0x4
2314 04:41:16.401778 RL = 0x4
2315 04:41:16.401890 BL = 0x2
2316 04:41:16.404900 RPST = 0x0
2317 04:41:16.404998 RD_PRE = 0x0
2318 04:41:16.408405 WR_PRE = 0x1
2319 04:41:16.408508 WR_PST = 0x0
2320 04:41:16.411545 DBI_WR = 0x0
2321 04:41:16.411645 DBI_RD = 0x0
2322 04:41:16.415121 OTF = 0x1
2323 04:41:16.418264 ===================================
2324 04:41:16.421547 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2325 04:41:16.424975 ==
2326 04:41:16.428497 Dram Type= 6, Freq= 0, CH_0, rank 0
2327 04:41:16.431648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2328 04:41:16.431758 ==
2329 04:41:16.434890 [Duty_Offset_Calibration]
2330 04:41:16.435001 B0:2 B1:0 CA:3
2331 04:41:16.435070
2332 04:41:16.438435 [DutyScan_Calibration_Flow] k_type=0
2333 04:41:16.447909
2334 04:41:16.448063 ==CLK 0==
2335 04:41:16.451155 Final CLK duty delay cell = 0
2336 04:41:16.454301 [0] MAX Duty = 5062%(X100), DQS PI = 28
2337 04:41:16.457696 [0] MIN Duty = 4875%(X100), DQS PI = 58
2338 04:41:16.457818 [0] AVG Duty = 4968%(X100)
2339 04:41:16.461143
2340 04:41:16.464377 CH0 CLK Duty spec in!! Max-Min= 187%
2341 04:41:16.467776 [DutyScan_Calibration_Flow] ====Done====
2342 04:41:16.467898
2343 04:41:16.471158 [DutyScan_Calibration_Flow] k_type=1
2344 04:41:16.486131
2345 04:41:16.486288 ==DQS 0 ==
2346 04:41:16.489695 Final DQS duty delay cell = 0
2347 04:41:16.492950 [0] MAX Duty = 5093%(X100), DQS PI = 28
2348 04:41:16.496162 [0] MIN Duty = 4907%(X100), DQS PI = 48
2349 04:41:16.499408 [0] AVG Duty = 5000%(X100)
2350 04:41:16.499521
2351 04:41:16.499590 ==DQS 1 ==
2352 04:41:16.503047 Final DQS duty delay cell = -4
2353 04:41:16.506296 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2354 04:41:16.509626 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2355 04:41:16.512879 [-4] AVG Duty = 4953%(X100)
2356 04:41:16.512993
2357 04:41:16.515972 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2358 04:41:16.516089
2359 04:41:16.519623 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2360 04:41:16.522700 [DutyScan_Calibration_Flow] ====Done====
2361 04:41:16.522819
2362 04:41:16.525915 [DutyScan_Calibration_Flow] k_type=3
2363 04:41:16.543686
2364 04:41:16.543866 ==DQM 0 ==
2365 04:41:16.547297 Final DQM duty delay cell = 0
2366 04:41:16.550492 [0] MAX Duty = 5124%(X100), DQS PI = 28
2367 04:41:16.553683 [0] MIN Duty = 4876%(X100), DQS PI = 48
2368 04:41:16.557250 [0] AVG Duty = 5000%(X100)
2369 04:41:16.557362
2370 04:41:16.557429 ==DQM 1 ==
2371 04:41:16.560404 Final DQM duty delay cell = 4
2372 04:41:16.563852 [4] MAX Duty = 5124%(X100), DQS PI = 50
2373 04:41:16.567180 [4] MIN Duty = 5000%(X100), DQS PI = 32
2374 04:41:16.570274 [4] AVG Duty = 5062%(X100)
2375 04:41:16.570380
2376 04:41:16.574015 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2377 04:41:16.574124
2378 04:41:16.577115 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2379 04:41:16.580414 [DutyScan_Calibration_Flow] ====Done====
2380 04:41:16.580524
2381 04:41:16.583820 [DutyScan_Calibration_Flow] k_type=2
2382 04:41:16.598842
2383 04:41:16.598988 ==DQ 0 ==
2384 04:41:16.602164 Final DQ duty delay cell = -4
2385 04:41:16.605432 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2386 04:41:16.608870 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2387 04:41:16.611955 [-4] AVG Duty = 4969%(X100)
2388 04:41:16.612096
2389 04:41:16.612167 ==DQ 1 ==
2390 04:41:16.615499 Final DQ duty delay cell = -4
2391 04:41:16.618599 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2392 04:41:16.621900 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2393 04:41:16.625399 [-4] AVG Duty = 4938%(X100)
2394 04:41:16.625553
2395 04:41:16.628617 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2396 04:41:16.628712
2397 04:41:16.632099 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2398 04:41:16.635366 [DutyScan_Calibration_Flow] ====Done====
2399 04:41:16.635473 ==
2400 04:41:16.638781 Dram Type= 6, Freq= 0, CH_1, rank 0
2401 04:41:16.642073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2402 04:41:16.642181 ==
2403 04:41:16.645288 [Duty_Offset_Calibration]
2404 04:41:16.645397 B0:1 B1:-2 CA:0
2405 04:41:16.645466
2406 04:41:16.648867 [DutyScan_Calibration_Flow] k_type=0
2407 04:41:16.659523
2408 04:41:16.659697 ==CLK 0==
2409 04:41:16.662638 Final CLK duty delay cell = 0
2410 04:41:16.666196 [0] MAX Duty = 5031%(X100), DQS PI = 16
2411 04:41:16.669351 [0] MIN Duty = 4844%(X100), DQS PI = 58
2412 04:41:16.669527 [0] AVG Duty = 4937%(X100)
2413 04:41:16.672787
2414 04:41:16.676080 CH1 CLK Duty spec in!! Max-Min= 187%
2415 04:41:16.679296 [DutyScan_Calibration_Flow] ====Done====
2416 04:41:16.679416
2417 04:41:16.682583 [DutyScan_Calibration_Flow] k_type=1
2418 04:41:16.697937
2419 04:41:16.698090 ==DQS 0 ==
2420 04:41:16.701193 Final DQS duty delay cell = -4
2421 04:41:16.704663 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2422 04:41:16.708051 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2423 04:41:16.711040 [-4] AVG Duty = 4969%(X100)
2424 04:41:16.711151
2425 04:41:16.711222 ==DQS 1 ==
2426 04:41:16.714687 Final DQS duty delay cell = 0
2427 04:41:16.717772 [0] MAX Duty = 5093%(X100), DQS PI = 0
2428 04:41:16.721096 [0] MIN Duty = 4844%(X100), DQS PI = 26
2429 04:41:16.724633 [0] AVG Duty = 4968%(X100)
2430 04:41:16.724746
2431 04:41:16.727775 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2432 04:41:16.727874
2433 04:41:16.731135 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2434 04:41:16.734726 [DutyScan_Calibration_Flow] ====Done====
2435 04:41:16.734839
2436 04:41:16.737681 [DutyScan_Calibration_Flow] k_type=3
2437 04:41:16.754651
2438 04:41:16.754803 ==DQM 0 ==
2439 04:41:16.757707 Final DQM duty delay cell = 0
2440 04:41:16.761309 [0] MAX Duty = 5000%(X100), DQS PI = 24
2441 04:41:16.764570 [0] MIN Duty = 4844%(X100), DQS PI = 52
2442 04:41:16.764684 [0] AVG Duty = 4922%(X100)
2443 04:41:16.768174
2444 04:41:16.768277 ==DQM 1 ==
2445 04:41:16.771281 Final DQM duty delay cell = 0
2446 04:41:16.774445 [0] MAX Duty = 5031%(X100), DQS PI = 34
2447 04:41:16.778071 [0] MIN Duty = 4907%(X100), DQS PI = 4
2448 04:41:16.778182 [0] AVG Duty = 4969%(X100)
2449 04:41:16.781303
2450 04:41:16.784421 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2451 04:41:16.784527
2452 04:41:16.787668 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2453 04:41:16.790874 [DutyScan_Calibration_Flow] ====Done====
2454 04:41:16.790990
2455 04:41:16.794337 [DutyScan_Calibration_Flow] k_type=2
2456 04:41:16.811162
2457 04:41:16.811345 ==DQ 0 ==
2458 04:41:16.814472 Final DQ duty delay cell = 0
2459 04:41:16.817627 [0] MAX Duty = 5093%(X100), DQS PI = 20
2460 04:41:16.820885 [0] MIN Duty = 4938%(X100), DQS PI = 54
2461 04:41:16.821039 [0] AVG Duty = 5015%(X100)
2462 04:41:16.824586
2463 04:41:16.824718 ==DQ 1 ==
2464 04:41:16.827684 Final DQ duty delay cell = 0
2465 04:41:16.831078 [0] MAX Duty = 5125%(X100), DQS PI = 36
2466 04:41:16.834537 [0] MIN Duty = 4969%(X100), DQS PI = 26
2467 04:41:16.834647 [0] AVG Duty = 5047%(X100)
2468 04:41:16.834717
2469 04:41:16.837835 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2470 04:41:16.840964
2471 04:41:16.844507 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2472 04:41:16.847621 [DutyScan_Calibration_Flow] ====Done====
2473 04:41:16.851220 nWR fixed to 30
2474 04:41:16.851339 [ModeRegInit_LP4] CH0 RK0
2475 04:41:16.854241 [ModeRegInit_LP4] CH0 RK1
2476 04:41:16.857518 [ModeRegInit_LP4] CH1 RK0
2477 04:41:16.857640 [ModeRegInit_LP4] CH1 RK1
2478 04:41:16.861081 match AC timing 7
2479 04:41:16.864356 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2480 04:41:16.867625 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2481 04:41:16.874521 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2482 04:41:16.877740 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2483 04:41:16.884334 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2484 04:41:16.884460 ==
2485 04:41:16.887758 Dram Type= 6, Freq= 0, CH_0, rank 0
2486 04:41:16.890952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2487 04:41:16.891041 ==
2488 04:41:16.897497 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2489 04:41:16.904059 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2490 04:41:16.911194 [CA 0] Center 40 (10~71) winsize 62
2491 04:41:16.914281 [CA 1] Center 39 (9~70) winsize 62
2492 04:41:16.917822 [CA 2] Center 36 (6~66) winsize 61
2493 04:41:16.921161 [CA 3] Center 35 (5~66) winsize 62
2494 04:41:16.924309 [CA 4] Center 34 (4~65) winsize 62
2495 04:41:16.927769 [CA 5] Center 33 (3~64) winsize 62
2496 04:41:16.927901
2497 04:41:16.931030 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2498 04:41:16.931122
2499 04:41:16.934151 [CATrainingPosCal] consider 1 rank data
2500 04:41:16.937776 u2DelayCellTimex100 = 270/100 ps
2501 04:41:16.940907 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2502 04:41:16.947711 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2503 04:41:16.950938 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2504 04:41:16.954176 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 04:41:16.957534 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2506 04:41:16.961233 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2507 04:41:16.961377
2508 04:41:16.964322 CA PerBit enable=1, Macro0, CA PI delay=33
2509 04:41:16.964409
2510 04:41:16.967570 [CBTSetCACLKResult] CA Dly = 33
2511 04:41:16.967659 CS Dly: 7 (0~38)
2512 04:41:16.971066 ==
2513 04:41:16.974390 Dram Type= 6, Freq= 0, CH_0, rank 1
2514 04:41:16.977512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 04:41:16.977596 ==
2516 04:41:16.980914 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2517 04:41:16.987541 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2518 04:41:16.997161 [CA 0] Center 40 (10~70) winsize 61
2519 04:41:17.000576 [CA 1] Center 39 (9~70) winsize 62
2520 04:41:17.003616 [CA 2] Center 35 (5~66) winsize 62
2521 04:41:17.006946 [CA 3] Center 35 (5~66) winsize 62
2522 04:41:17.010469 [CA 4] Center 34 (4~65) winsize 62
2523 04:41:17.013767 [CA 5] Center 33 (3~63) winsize 61
2524 04:41:17.013858
2525 04:41:17.017064 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2526 04:41:17.017157
2527 04:41:17.020445 [CATrainingPosCal] consider 2 rank data
2528 04:41:17.024067 u2DelayCellTimex100 = 270/100 ps
2529 04:41:17.027287 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2530 04:41:17.033487 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2531 04:41:17.036991 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2532 04:41:17.040408 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2533 04:41:17.043882 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2534 04:41:17.047244 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2535 04:41:17.047336
2536 04:41:17.050427 CA PerBit enable=1, Macro0, CA PI delay=33
2537 04:41:17.050513
2538 04:41:17.053634 [CBTSetCACLKResult] CA Dly = 33
2539 04:41:17.053711 CS Dly: 8 (0~40)
2540 04:41:17.053773
2541 04:41:17.060540 ----->DramcWriteLeveling(PI) begin...
2542 04:41:17.060650 ==
2543 04:41:17.063512 Dram Type= 6, Freq= 0, CH_0, rank 0
2544 04:41:17.066929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2545 04:41:17.067059 ==
2546 04:41:17.070293 Write leveling (Byte 0): 31 => 31
2547 04:41:17.073551 Write leveling (Byte 1): 30 => 30
2548 04:41:17.077057 DramcWriteLeveling(PI) end<-----
2549 04:41:17.077157
2550 04:41:17.077226 ==
2551 04:41:17.080172 Dram Type= 6, Freq= 0, CH_0, rank 0
2552 04:41:17.083779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2553 04:41:17.083878 ==
2554 04:41:17.086822 [Gating] SW mode calibration
2555 04:41:17.093617 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2556 04:41:17.100172 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2557 04:41:17.103759 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2558 04:41:17.107046 0 15 4 | B1->B0 | 2525 3333 | 0 1 | (0 0) (1 1)
2559 04:41:17.113606 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2560 04:41:17.116955 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2561 04:41:17.120288 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2562 04:41:17.123528 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2563 04:41:17.130363 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2564 04:41:17.133401 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2565 04:41:17.136718 1 0 0 | B1->B0 | 3333 2d2d | 1 1 | (1 0) (1 0)
2566 04:41:17.143544 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2567 04:41:17.146992 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2568 04:41:17.149986 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2569 04:41:17.156789 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2570 04:41:17.160333 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2571 04:41:17.163616 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 04:41:17.169867 1 0 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2573 04:41:17.173290 1 1 0 | B1->B0 | 2828 3333 | 0 0 | (0 0) (1 1)
2574 04:41:17.176861 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2575 04:41:17.183425 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 04:41:17.186673 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 04:41:17.189817 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 04:41:17.196577 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 04:41:17.200206 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 04:41:17.203320 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2581 04:41:17.210132 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2582 04:41:17.213423 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2583 04:41:17.216755 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 04:41:17.223437 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 04:41:17.226591 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 04:41:17.229989 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 04:41:17.236685 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 04:41:17.239881 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 04:41:17.243351 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 04:41:17.246681 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 04:41:17.253366 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 04:41:17.256638 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 04:41:17.260124 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 04:41:17.266566 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 04:41:17.270103 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 04:41:17.273445 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 04:41:17.279971 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2598 04:41:17.283164 Total UI for P1: 0, mck2ui 16
2599 04:41:17.286574 best dqsien dly found for B0: ( 1, 3, 30)
2600 04:41:17.290247 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2601 04:41:17.293396 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 04:41:17.296888 Total UI for P1: 0, mck2ui 16
2603 04:41:17.300097 best dqsien dly found for B1: ( 1, 4, 2)
2604 04:41:17.303278 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2605 04:41:17.306867 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2606 04:41:17.306991
2607 04:41:17.310131 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2608 04:41:17.316783 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2609 04:41:17.316898 [Gating] SW calibration Done
2610 04:41:17.316972 ==
2611 04:41:17.319959 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 04:41:17.326812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 04:41:17.326929 ==
2614 04:41:17.327000 RX Vref Scan: 0
2615 04:41:17.327063
2616 04:41:17.329922 RX Vref 0 -> 0, step: 1
2617 04:41:17.330033
2618 04:41:17.333438 RX Delay -40 -> 252, step: 8
2619 04:41:17.336816 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2620 04:41:17.340072 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2621 04:41:17.343282 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2622 04:41:17.350288 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2623 04:41:17.353455 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2624 04:41:17.356560 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2625 04:41:17.359901 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2626 04:41:17.363317 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2627 04:41:17.366645 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2628 04:41:17.373261 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2629 04:41:17.376720 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2630 04:41:17.379756 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2631 04:41:17.383156 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2632 04:41:17.386565 iDelay=200, Bit 13, Center 103 (32 ~ 175) 144
2633 04:41:17.393212 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2634 04:41:17.396655 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2635 04:41:17.396769 ==
2636 04:41:17.399825 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 04:41:17.403025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 04:41:17.403114 ==
2639 04:41:17.406601 DQS Delay:
2640 04:41:17.406696 DQS0 = 0, DQS1 = 0
2641 04:41:17.406800 DQM Delay:
2642 04:41:17.409641 DQM0 = 112, DQM1 = 101
2643 04:41:17.409725 DQ Delay:
2644 04:41:17.413277 DQ0 =111, DQ1 =115, DQ2 =111, DQ3 =107
2645 04:41:17.416540 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
2646 04:41:17.419793 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2647 04:41:17.423766 DQ12 =111, DQ13 =103, DQ14 =115, DQ15 =111
2648 04:41:17.426543
2649 04:41:17.426637
2650 04:41:17.426723 ==
2651 04:41:17.430045 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 04:41:17.433203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 04:41:17.433293 ==
2654 04:41:17.433393
2655 04:41:17.433506
2656 04:41:17.436537 TX Vref Scan disable
2657 04:41:17.436629 == TX Byte 0 ==
2658 04:41:17.443259 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2659 04:41:17.446724 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2660 04:41:17.446829 == TX Byte 1 ==
2661 04:41:17.453296 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2662 04:41:17.456462 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2663 04:41:17.456559 ==
2664 04:41:17.459958 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 04:41:17.463195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 04:41:17.463326 ==
2667 04:41:17.475533 TX Vref=22, minBit 12, minWin=25, winSum=416
2668 04:41:17.479077 TX Vref=24, minBit 4, minWin=26, winSum=427
2669 04:41:17.482238 TX Vref=26, minBit 4, minWin=26, winSum=433
2670 04:41:17.485733 TX Vref=28, minBit 10, minWin=26, winSum=433
2671 04:41:17.489232 TX Vref=30, minBit 5, minWin=27, winSum=441
2672 04:41:17.495598 TX Vref=32, minBit 12, minWin=26, winSum=433
2673 04:41:17.499211 [TxChooseVref] Worse bit 5, Min win 27, Win sum 441, Final Vref 30
2674 04:41:17.499315
2675 04:41:17.502395 Final TX Range 1 Vref 30
2676 04:41:17.502481
2677 04:41:17.502565 ==
2678 04:41:17.505645 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 04:41:17.508885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 04:41:17.508985 ==
2681 04:41:17.512233
2682 04:41:17.512352
2683 04:41:17.512440 TX Vref Scan disable
2684 04:41:17.515451 == TX Byte 0 ==
2685 04:41:17.519040 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2686 04:41:17.522215 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2687 04:41:17.525824 == TX Byte 1 ==
2688 04:41:17.529001 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2689 04:41:17.532465 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2690 04:41:17.535547
2691 04:41:17.535649 [DATLAT]
2692 04:41:17.535737 Freq=1200, CH0 RK0
2693 04:41:17.535818
2694 04:41:17.539284 DATLAT Default: 0xd
2695 04:41:17.539375 0, 0xFFFF, sum = 0
2696 04:41:17.542276 1, 0xFFFF, sum = 0
2697 04:41:17.542357 2, 0xFFFF, sum = 0
2698 04:41:17.545781 3, 0xFFFF, sum = 0
2699 04:41:17.545864 4, 0xFFFF, sum = 0
2700 04:41:17.549265 5, 0xFFFF, sum = 0
2701 04:41:17.549354 6, 0xFFFF, sum = 0
2702 04:41:17.552552 7, 0xFFFF, sum = 0
2703 04:41:17.555541 8, 0xFFFF, sum = 0
2704 04:41:17.555630 9, 0xFFFF, sum = 0
2705 04:41:17.558861 10, 0xFFFF, sum = 0
2706 04:41:17.558968 11, 0xFFFF, sum = 0
2707 04:41:17.562446 12, 0x0, sum = 1
2708 04:41:17.562548 13, 0x0, sum = 2
2709 04:41:17.565694 14, 0x0, sum = 3
2710 04:41:17.565789 15, 0x0, sum = 4
2711 04:41:17.565858 best_step = 13
2712 04:41:17.565918
2713 04:41:17.568818 ==
2714 04:41:17.572475 Dram Type= 6, Freq= 0, CH_0, rank 0
2715 04:41:17.575524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2716 04:41:17.575611 ==
2717 04:41:17.575675 RX Vref Scan: 1
2718 04:41:17.575743
2719 04:41:17.578872 Set Vref Range= 32 -> 127
2720 04:41:17.578949
2721 04:41:17.582347 RX Vref 32 -> 127, step: 1
2722 04:41:17.582429
2723 04:41:17.585464 RX Delay -37 -> 252, step: 4
2724 04:41:17.585552
2725 04:41:17.588758 Set Vref, RX VrefLevel [Byte0]: 32
2726 04:41:17.592221 [Byte1]: 32
2727 04:41:17.592324
2728 04:41:17.595591 Set Vref, RX VrefLevel [Byte0]: 33
2729 04:41:17.598740 [Byte1]: 33
2730 04:41:17.602389
2731 04:41:17.602488 Set Vref, RX VrefLevel [Byte0]: 34
2732 04:41:17.605448 [Byte1]: 34
2733 04:41:17.610077
2734 04:41:17.610183 Set Vref, RX VrefLevel [Byte0]: 35
2735 04:41:17.613327 [Byte1]: 35
2736 04:41:17.618202
2737 04:41:17.618337 Set Vref, RX VrefLevel [Byte0]: 36
2738 04:41:17.621403 [Byte1]: 36
2739 04:41:17.626196
2740 04:41:17.626332 Set Vref, RX VrefLevel [Byte0]: 37
2741 04:41:17.629742 [Byte1]: 37
2742 04:41:17.634138
2743 04:41:17.634263 Set Vref, RX VrefLevel [Byte0]: 38
2744 04:41:17.637628 [Byte1]: 38
2745 04:41:17.642469
2746 04:41:17.642576 Set Vref, RX VrefLevel [Byte0]: 39
2747 04:41:17.645627 [Byte1]: 39
2748 04:41:17.650293
2749 04:41:17.650403 Set Vref, RX VrefLevel [Byte0]: 40
2750 04:41:17.653493 [Byte1]: 40
2751 04:41:17.658141
2752 04:41:17.658246 Set Vref, RX VrefLevel [Byte0]: 41
2753 04:41:17.661466 [Byte1]: 41
2754 04:41:17.666413
2755 04:41:17.666542 Set Vref, RX VrefLevel [Byte0]: 42
2756 04:41:17.669388 [Byte1]: 42
2757 04:41:17.674308
2758 04:41:17.674426 Set Vref, RX VrefLevel [Byte0]: 43
2759 04:41:17.677644 [Byte1]: 43
2760 04:41:17.682415
2761 04:41:17.682541 Set Vref, RX VrefLevel [Byte0]: 44
2762 04:41:17.685618 [Byte1]: 44
2763 04:41:17.690291
2764 04:41:17.690378 Set Vref, RX VrefLevel [Byte0]: 45
2765 04:41:17.693397 [Byte1]: 45
2766 04:41:17.698264
2767 04:41:17.698359 Set Vref, RX VrefLevel [Byte0]: 46
2768 04:41:17.701428 [Byte1]: 46
2769 04:41:17.706310
2770 04:41:17.706413 Set Vref, RX VrefLevel [Byte0]: 47
2771 04:41:17.709498 [Byte1]: 47
2772 04:41:17.714121
2773 04:41:17.714217 Set Vref, RX VrefLevel [Byte0]: 48
2774 04:41:17.717648 [Byte1]: 48
2775 04:41:17.722328
2776 04:41:17.722423 Set Vref, RX VrefLevel [Byte0]: 49
2777 04:41:17.725494 [Byte1]: 49
2778 04:41:17.730266
2779 04:41:17.730362 Set Vref, RX VrefLevel [Byte0]: 50
2780 04:41:17.733467 [Byte1]: 50
2781 04:41:17.738103
2782 04:41:17.738204 Set Vref, RX VrefLevel [Byte0]: 51
2783 04:41:17.741403 [Byte1]: 51
2784 04:41:17.746301
2785 04:41:17.746404 Set Vref, RX VrefLevel [Byte0]: 52
2786 04:41:17.749451 [Byte1]: 52
2787 04:41:17.754170
2788 04:41:17.754275 Set Vref, RX VrefLevel [Byte0]: 53
2789 04:41:17.757705 [Byte1]: 53
2790 04:41:17.762136
2791 04:41:17.762231 Set Vref, RX VrefLevel [Byte0]: 54
2792 04:41:17.765679 [Byte1]: 54
2793 04:41:17.770462
2794 04:41:17.770565 Set Vref, RX VrefLevel [Byte0]: 55
2795 04:41:17.773647 [Byte1]: 55
2796 04:41:17.778304
2797 04:41:17.778399 Set Vref, RX VrefLevel [Byte0]: 56
2798 04:41:17.781679 [Byte1]: 56
2799 04:41:17.786277
2800 04:41:17.786380 Set Vref, RX VrefLevel [Byte0]: 57
2801 04:41:17.789789 [Byte1]: 57
2802 04:41:17.794164
2803 04:41:17.794256 Set Vref, RX VrefLevel [Byte0]: 58
2804 04:41:17.797659 [Byte1]: 58
2805 04:41:17.802277
2806 04:41:17.802367 Set Vref, RX VrefLevel [Byte0]: 59
2807 04:41:17.805545 [Byte1]: 59
2808 04:41:17.810106
2809 04:41:17.810241 Set Vref, RX VrefLevel [Byte0]: 60
2810 04:41:17.813734 [Byte1]: 60
2811 04:41:17.818282
2812 04:41:17.818400 Set Vref, RX VrefLevel [Byte0]: 61
2813 04:41:17.821522 [Byte1]: 61
2814 04:41:17.826272
2815 04:41:17.826389 Set Vref, RX VrefLevel [Byte0]: 62
2816 04:41:17.829759 [Byte1]: 62
2817 04:41:17.834122
2818 04:41:17.834235 Set Vref, RX VrefLevel [Byte0]: 63
2819 04:41:17.837661 [Byte1]: 63
2820 04:41:17.842147
2821 04:41:17.842259 Set Vref, RX VrefLevel [Byte0]: 64
2822 04:41:17.845686 [Byte1]: 64
2823 04:41:17.850039
2824 04:41:17.850155 Set Vref, RX VrefLevel [Byte0]: 65
2825 04:41:17.853690 [Byte1]: 65
2826 04:41:17.858136
2827 04:41:17.858268 Set Vref, RX VrefLevel [Byte0]: 66
2828 04:41:17.861677 [Byte1]: 66
2829 04:41:17.866241
2830 04:41:17.866365 Set Vref, RX VrefLevel [Byte0]: 67
2831 04:41:17.869364 [Byte1]: 67
2832 04:41:17.874160
2833 04:41:17.874277 Set Vref, RX VrefLevel [Byte0]: 68
2834 04:41:17.877634 [Byte1]: 68
2835 04:41:17.882096
2836 04:41:17.882206 Set Vref, RX VrefLevel [Byte0]: 69
2837 04:41:17.885241 [Byte1]: 69
2838 04:41:17.890232
2839 04:41:17.890346 Set Vref, RX VrefLevel [Byte0]: 70
2840 04:41:17.893524 [Byte1]: 70
2841 04:41:17.898274
2842 04:41:17.898452 Set Vref, RX VrefLevel [Byte0]: 71
2843 04:41:17.901699 [Byte1]: 71
2844 04:41:17.906305
2845 04:41:17.906437 Set Vref, RX VrefLevel [Byte0]: 72
2846 04:41:17.909452 [Byte1]: 72
2847 04:41:17.914177
2848 04:41:17.914312 Set Vref, RX VrefLevel [Byte0]: 73
2849 04:41:17.917355 [Byte1]: 73
2850 04:41:17.922245
2851 04:41:17.922351 Set Vref, RX VrefLevel [Byte0]: 74
2852 04:41:17.925627 [Byte1]: 74
2853 04:41:17.930228
2854 04:41:17.930340 Final RX Vref Byte 0 = 62 to rank0
2855 04:41:17.933545 Final RX Vref Byte 1 = 46 to rank0
2856 04:41:17.936960 Final RX Vref Byte 0 = 62 to rank1
2857 04:41:17.940123 Final RX Vref Byte 1 = 46 to rank1==
2858 04:41:17.943241 Dram Type= 6, Freq= 0, CH_0, rank 0
2859 04:41:17.949951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2860 04:41:17.950038 ==
2861 04:41:17.950104 DQS Delay:
2862 04:41:17.950168 DQS0 = 0, DQS1 = 0
2863 04:41:17.953376 DQM Delay:
2864 04:41:17.953445 DQM0 = 112, DQM1 = 98
2865 04:41:17.956855 DQ Delay:
2866 04:41:17.959966 DQ0 =112, DQ1 =112, DQ2 =112, DQ3 =108
2867 04:41:17.963155 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2868 04:41:17.966580 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =92
2869 04:41:17.970041 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2870 04:41:17.970120
2871 04:41:17.970187
2872 04:41:17.976408 [DQSOSCAuto] RK0, (LSB)MR18= 0x101, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
2873 04:41:17.979898 CH0 RK0: MR19=404, MR18=101
2874 04:41:17.986423 CH0_RK0: MR19=0x404, MR18=0x101, DQSOSC=409, MR23=63, INC=39, DEC=26
2875 04:41:17.986546
2876 04:41:17.990042 ----->DramcWriteLeveling(PI) begin...
2877 04:41:17.990166 ==
2878 04:41:17.993092 Dram Type= 6, Freq= 0, CH_0, rank 1
2879 04:41:17.996622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 04:41:17.996720 ==
2881 04:41:17.999696 Write leveling (Byte 0): 31 => 31
2882 04:41:18.003277 Write leveling (Byte 1): 29 => 29
2883 04:41:18.006448 DramcWriteLeveling(PI) end<-----
2884 04:41:18.006529
2885 04:41:18.006593 ==
2886 04:41:18.009921 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 04:41:18.016356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 04:41:18.016453 ==
2889 04:41:18.016522 [Gating] SW mode calibration
2890 04:41:18.026514 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2891 04:41:18.030074 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2892 04:41:18.033273 0 15 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
2893 04:41:18.040109 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 04:41:18.043320 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 04:41:18.046421 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 04:41:18.053280 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 04:41:18.056378 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 04:41:18.059926 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
2899 04:41:18.066459 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
2900 04:41:18.069914 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2901 04:41:18.073093 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 04:41:18.079802 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 04:41:18.083111 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 04:41:18.086512 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 04:41:18.093278 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 04:41:18.096685 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2907 04:41:18.100076 1 0 28 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
2908 04:41:18.103206 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2909 04:41:18.110099 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 04:41:18.113228 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 04:41:18.116546 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 04:41:18.123485 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 04:41:18.126533 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 04:41:18.129803 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 04:41:18.136755 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2916 04:41:18.139774 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2917 04:41:18.143523 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 04:41:18.150030 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 04:41:18.153480 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 04:41:18.156648 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 04:41:18.163137 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 04:41:18.166587 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 04:41:18.170185 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 04:41:18.176707 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 04:41:18.180028 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 04:41:18.183129 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 04:41:18.189829 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 04:41:18.193310 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 04:41:18.196468 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 04:41:18.203263 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 04:41:18.206374 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2932 04:41:18.209975 Total UI for P1: 0, mck2ui 16
2933 04:41:18.213181 best dqsien dly found for B0: ( 1, 3, 26)
2934 04:41:18.216586 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2935 04:41:18.220009 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 04:41:18.223209 Total UI for P1: 0, mck2ui 16
2937 04:41:18.226754 best dqsien dly found for B1: ( 1, 3, 30)
2938 04:41:18.229901 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2939 04:41:18.233344 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2940 04:41:18.233458
2941 04:41:18.239882 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2942 04:41:18.243197 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2943 04:41:18.246638 [Gating] SW calibration Done
2944 04:41:18.246729 ==
2945 04:41:18.249976 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 04:41:18.253360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 04:41:18.253457 ==
2948 04:41:18.253539 RX Vref Scan: 0
2949 04:41:18.253604
2950 04:41:18.256566 RX Vref 0 -> 0, step: 1
2951 04:41:18.256687
2952 04:41:18.259962 RX Delay -40 -> 252, step: 8
2953 04:41:18.263465 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2954 04:41:18.266518 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2955 04:41:18.273127 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2956 04:41:18.276631 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2957 04:41:18.279964 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2958 04:41:18.283246 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2959 04:41:18.286716 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2960 04:41:18.289801 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2961 04:41:18.296466 iDelay=200, Bit 8, Center 87 (16 ~ 159) 144
2962 04:41:18.299613 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2963 04:41:18.303164 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2964 04:41:18.306696 iDelay=200, Bit 11, Center 91 (24 ~ 159) 136
2965 04:41:18.309954 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2966 04:41:18.316567 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2967 04:41:18.319707 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2968 04:41:18.322985 iDelay=200, Bit 15, Center 107 (40 ~ 175) 136
2969 04:41:18.323076 ==
2970 04:41:18.326515 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 04:41:18.329605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 04:41:18.329703 ==
2973 04:41:18.333290 DQS Delay:
2974 04:41:18.333378 DQS0 = 0, DQS1 = 0
2975 04:41:18.336448 DQM Delay:
2976 04:41:18.336538 DQM0 = 111, DQM1 = 99
2977 04:41:18.336604 DQ Delay:
2978 04:41:18.343198 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2979 04:41:18.346566 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2980 04:41:18.349981 DQ8 =87, DQ9 =83, DQ10 =103, DQ11 =91
2981 04:41:18.353252 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =107
2982 04:41:18.353343
2983 04:41:18.353409
2984 04:41:18.353470 ==
2985 04:41:18.356448 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 04:41:18.359606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 04:41:18.359693 ==
2988 04:41:18.359760
2989 04:41:18.359821
2990 04:41:18.363242 TX Vref Scan disable
2991 04:41:18.363329 == TX Byte 0 ==
2992 04:41:18.369727 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2993 04:41:18.373120 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2994 04:41:18.373220 == TX Byte 1 ==
2995 04:41:18.379561 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2996 04:41:18.382787 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2997 04:41:18.382899 ==
2998 04:41:18.386226 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 04:41:18.389727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 04:41:18.389844 ==
3001 04:41:18.402905 TX Vref=22, minBit 2, minWin=26, winSum=429
3002 04:41:18.406069 TX Vref=24, minBit 2, minWin=26, winSum=432
3003 04:41:18.409597 TX Vref=26, minBit 5, minWin=26, winSum=438
3004 04:41:18.412828 TX Vref=28, minBit 1, minWin=27, winSum=439
3005 04:41:18.416286 TX Vref=30, minBit 5, minWin=27, winSum=445
3006 04:41:18.419429 TX Vref=32, minBit 1, minWin=27, winSum=441
3007 04:41:18.426296 [TxChooseVref] Worse bit 5, Min win 27, Win sum 445, Final Vref 30
3008 04:41:18.426396
3009 04:41:18.429727 Final TX Range 1 Vref 30
3010 04:41:18.429805
3011 04:41:18.429868 ==
3012 04:41:18.432802 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 04:41:18.436424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 04:41:18.436514 ==
3015 04:41:18.436582
3016 04:41:18.436645
3017 04:41:18.439520 TX Vref Scan disable
3018 04:41:18.443160 == TX Byte 0 ==
3019 04:41:18.446357 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3020 04:41:18.449950 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3021 04:41:18.453039 == TX Byte 1 ==
3022 04:41:18.456646 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3023 04:41:18.459709 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3024 04:41:18.459828
3025 04:41:18.463123 [DATLAT]
3026 04:41:18.463235 Freq=1200, CH0 RK1
3027 04:41:18.463330
3028 04:41:18.466563 DATLAT Default: 0xd
3029 04:41:18.466666 0, 0xFFFF, sum = 0
3030 04:41:18.469928 1, 0xFFFF, sum = 0
3031 04:41:18.470009 2, 0xFFFF, sum = 0
3032 04:41:18.473244 3, 0xFFFF, sum = 0
3033 04:41:18.473350 4, 0xFFFF, sum = 0
3034 04:41:18.476653 5, 0xFFFF, sum = 0
3035 04:41:18.476738 6, 0xFFFF, sum = 0
3036 04:41:18.479903 7, 0xFFFF, sum = 0
3037 04:41:18.480012 8, 0xFFFF, sum = 0
3038 04:41:18.483023 9, 0xFFFF, sum = 0
3039 04:41:18.483129 10, 0xFFFF, sum = 0
3040 04:41:18.486425 11, 0xFFFF, sum = 0
3041 04:41:18.486504 12, 0x0, sum = 1
3042 04:41:18.489964 13, 0x0, sum = 2
3043 04:41:18.490051 14, 0x0, sum = 3
3044 04:41:18.493194 15, 0x0, sum = 4
3045 04:41:18.493297 best_step = 13
3046 04:41:18.493391
3047 04:41:18.493486 ==
3048 04:41:18.496328 Dram Type= 6, Freq= 0, CH_0, rank 1
3049 04:41:18.503299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 04:41:18.503404 ==
3051 04:41:18.503472 RX Vref Scan: 0
3052 04:41:18.503533
3053 04:41:18.506503 RX Vref 0 -> 0, step: 1
3054 04:41:18.506605
3055 04:41:18.509616 RX Delay -37 -> 252, step: 4
3056 04:41:18.513262 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3057 04:41:18.516364 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3058 04:41:18.523077 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3059 04:41:18.526197 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3060 04:41:18.529643 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3061 04:41:18.532838 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3062 04:41:18.536457 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3063 04:41:18.542834 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3064 04:41:18.546172 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3065 04:41:18.549594 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3066 04:41:18.553140 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3067 04:41:18.556253 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3068 04:41:18.562892 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3069 04:41:18.566449 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3070 04:41:18.569606 iDelay=195, Bit 14, Center 110 (43 ~ 178) 136
3071 04:41:18.573029 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3072 04:41:18.573148 ==
3073 04:41:18.576137 Dram Type= 6, Freq= 0, CH_0, rank 1
3074 04:41:18.579746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 04:41:18.583160 ==
3076 04:41:18.583314 DQS Delay:
3077 04:41:18.583382 DQS0 = 0, DQS1 = 0
3078 04:41:18.586247 DQM Delay:
3079 04:41:18.586335 DQM0 = 111, DQM1 = 98
3080 04:41:18.589735 DQ Delay:
3081 04:41:18.592849 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3082 04:41:18.596399 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3083 04:41:18.599500 DQ8 =88, DQ9 =80, DQ10 =100, DQ11 =90
3084 04:41:18.603113 DQ12 =108, DQ13 =106, DQ14 =110, DQ15 =108
3085 04:41:18.603202
3086 04:41:18.603269
3087 04:41:18.609613 [DQSOSCAuto] RK1, (LSB)MR18= 0x17fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 401 ps
3088 04:41:18.613239 CH0 RK1: MR19=403, MR18=17FE
3089 04:41:18.619643 CH0_RK1: MR19=0x403, MR18=0x17FE, DQSOSC=401, MR23=63, INC=40, DEC=27
3090 04:41:18.623024 [RxdqsGatingPostProcess] freq 1200
3091 04:41:18.629857 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3092 04:41:18.629997 best DQS0 dly(2T, 0.5T) = (0, 11)
3093 04:41:18.633037 best DQS1 dly(2T, 0.5T) = (0, 12)
3094 04:41:18.636199 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3095 04:41:18.639653 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3096 04:41:18.642849 best DQS0 dly(2T, 0.5T) = (0, 11)
3097 04:41:18.646097 best DQS1 dly(2T, 0.5T) = (0, 11)
3098 04:41:18.649627 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3099 04:41:18.652819 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3100 04:41:18.656045 Pre-setting of DQS Precalculation
3101 04:41:18.659524 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3102 04:41:18.662930 ==
3103 04:41:18.666317 Dram Type= 6, Freq= 0, CH_1, rank 0
3104 04:41:18.669603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 04:41:18.669697 ==
3106 04:41:18.673128 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3107 04:41:18.679634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3108 04:41:18.688768 [CA 0] Center 37 (8~67) winsize 60
3109 04:41:18.691941 [CA 1] Center 37 (7~68) winsize 62
3110 04:41:18.695354 [CA 2] Center 34 (4~64) winsize 61
3111 04:41:18.698690 [CA 3] Center 33 (3~64) winsize 62
3112 04:41:18.701789 [CA 4] Center 34 (4~64) winsize 61
3113 04:41:18.705381 [CA 5] Center 33 (3~63) winsize 61
3114 04:41:18.705499
3115 04:41:18.708638 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3116 04:41:18.708714
3117 04:41:18.711895 [CATrainingPosCal] consider 1 rank data
3118 04:41:18.715194 u2DelayCellTimex100 = 270/100 ps
3119 04:41:18.718637 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3120 04:41:18.722236 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3121 04:41:18.728905 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3122 04:41:18.732077 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3123 04:41:18.735333 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3124 04:41:18.738848 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3125 04:41:18.738937
3126 04:41:18.741958 CA PerBit enable=1, Macro0, CA PI delay=33
3127 04:41:18.742044
3128 04:41:18.745194 [CBTSetCACLKResult] CA Dly = 33
3129 04:41:18.745280 CS Dly: 6 (0~37)
3130 04:41:18.745347 ==
3131 04:41:18.748737 Dram Type= 6, Freq= 0, CH_1, rank 1
3132 04:41:18.755526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 04:41:18.755650 ==
3134 04:41:18.758592 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3135 04:41:18.765593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3136 04:41:18.774141 [CA 0] Center 37 (7~68) winsize 62
3137 04:41:18.777413 [CA 1] Center 37 (7~68) winsize 62
3138 04:41:18.780929 [CA 2] Center 34 (4~65) winsize 62
3139 04:41:18.784175 [CA 3] Center 33 (3~64) winsize 62
3140 04:41:18.787613 [CA 4] Center 34 (4~65) winsize 62
3141 04:41:18.790653 [CA 5] Center 33 (2~64) winsize 63
3142 04:41:18.790742
3143 04:41:18.794227 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3144 04:41:18.794320
3145 04:41:18.797655 [CATrainingPosCal] consider 2 rank data
3146 04:41:18.800645 u2DelayCellTimex100 = 270/100 ps
3147 04:41:18.804178 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3148 04:41:18.807583 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3149 04:41:18.814253 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 04:41:18.817481 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3151 04:41:18.821026 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3152 04:41:18.824099 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3153 04:41:18.824212
3154 04:41:18.827374 CA PerBit enable=1, Macro0, CA PI delay=33
3155 04:41:18.827501
3156 04:41:18.830955 [CBTSetCACLKResult] CA Dly = 33
3157 04:41:18.831056 CS Dly: 7 (0~40)
3158 04:41:18.831145
3159 04:41:18.834209 ----->DramcWriteLeveling(PI) begin...
3160 04:41:18.837522 ==
3161 04:41:18.840779 Dram Type= 6, Freq= 0, CH_1, rank 0
3162 04:41:18.844048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 04:41:18.844145 ==
3164 04:41:18.847561 Write leveling (Byte 0): 26 => 26
3165 04:41:18.850725 Write leveling (Byte 1): 28 => 28
3166 04:41:18.854382 DramcWriteLeveling(PI) end<-----
3167 04:41:18.854473
3168 04:41:18.854540 ==
3169 04:41:18.857589 Dram Type= 6, Freq= 0, CH_1, rank 0
3170 04:41:18.861164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3171 04:41:18.861252 ==
3172 04:41:18.864220 [Gating] SW mode calibration
3173 04:41:18.871101 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3174 04:41:18.874432 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3175 04:41:18.881100 0 15 0 | B1->B0 | 2d2d 2928 | 0 1 | (0 0) (0 0)
3176 04:41:18.884303 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 04:41:18.887674 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 04:41:18.894319 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 04:41:18.897333 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 04:41:18.900741 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 04:41:18.907637 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 0)
3182 04:41:18.910752 0 15 28 | B1->B0 | 2929 2b2b | 0 0 | (0 1) (0 0)
3183 04:41:18.914399 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 04:41:18.920889 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 04:41:18.924246 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 04:41:18.927598 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 04:41:18.934082 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 04:41:18.937677 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 04:41:18.940668 1 0 24 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
3190 04:41:18.947484 1 0 28 | B1->B0 | 4141 3d3c | 0 1 | (0 0) (0 0)
3191 04:41:18.950787 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3192 04:41:18.954200 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 04:41:18.961054 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 04:41:18.964247 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 04:41:18.967384 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 04:41:18.970646 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 04:41:18.977419 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 04:41:18.980659 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3199 04:41:18.984337 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3200 04:41:18.990618 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 04:41:18.994066 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 04:41:18.997464 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 04:41:19.004245 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 04:41:19.007291 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 04:41:19.010921 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 04:41:19.017517 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 04:41:19.020817 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 04:41:19.023888 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 04:41:19.030750 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 04:41:19.034274 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 04:41:19.037505 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 04:41:19.044216 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 04:41:19.047508 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 04:41:19.051091 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3215 04:41:19.054459 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 04:41:19.057630 Total UI for P1: 0, mck2ui 16
3217 04:41:19.061188 best dqsien dly found for B0: ( 1, 3, 28)
3218 04:41:19.064325 Total UI for P1: 0, mck2ui 16
3219 04:41:19.067588 best dqsien dly found for B1: ( 1, 3, 28)
3220 04:41:19.070964 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3221 04:41:19.077849 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3222 04:41:19.077962
3223 04:41:19.080851 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3224 04:41:19.084471 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3225 04:41:19.087614 [Gating] SW calibration Done
3226 04:41:19.087705 ==
3227 04:41:19.091188 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 04:41:19.094337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 04:41:19.094427 ==
3230 04:41:19.094496 RX Vref Scan: 0
3231 04:41:19.097344
3232 04:41:19.097431 RX Vref 0 -> 0, step: 1
3233 04:41:19.097527
3234 04:41:19.100729 RX Delay -40 -> 252, step: 8
3235 04:41:19.104218 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3236 04:41:19.107459 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3237 04:41:19.114211 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3238 04:41:19.117537 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3239 04:41:19.120641 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3240 04:41:19.123842 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3241 04:41:19.127344 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3242 04:41:19.134027 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3243 04:41:19.137349 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3244 04:41:19.140563 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3245 04:41:19.144094 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3246 04:41:19.147256 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3247 04:41:19.154029 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3248 04:41:19.157171 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3249 04:41:19.160671 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3250 04:41:19.163766 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3251 04:41:19.163864 ==
3252 04:41:19.167074 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 04:41:19.173852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 04:41:19.173981 ==
3255 04:41:19.174074 DQS Delay:
3256 04:41:19.174166 DQS0 = 0, DQS1 = 0
3257 04:41:19.177180 DQM Delay:
3258 04:41:19.177264 DQM0 = 113, DQM1 = 106
3259 04:41:19.180610 DQ Delay:
3260 04:41:19.183771 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =115
3261 04:41:19.187433 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3262 04:41:19.190476 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3263 04:41:19.193619 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3264 04:41:19.193732
3265 04:41:19.193825
3266 04:41:19.193915 ==
3267 04:41:19.197318 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 04:41:19.200677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 04:41:19.200784 ==
3270 04:41:19.200865
3271 04:41:19.200962
3272 04:41:19.203732 TX Vref Scan disable
3273 04:41:19.207403 == TX Byte 0 ==
3274 04:41:19.210518 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3275 04:41:19.214263 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3276 04:41:19.217288 == TX Byte 1 ==
3277 04:41:19.221004 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3278 04:41:19.224266 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3279 04:41:19.224394 ==
3280 04:41:19.227654 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 04:41:19.230958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 04:41:19.234065 ==
3283 04:41:19.244126 TX Vref=22, minBit 11, minWin=23, winSum=405
3284 04:41:19.247276 TX Vref=24, minBit 11, minWin=24, winSum=414
3285 04:41:19.250808 TX Vref=26, minBit 9, minWin=25, winSum=416
3286 04:41:19.254056 TX Vref=28, minBit 9, minWin=25, winSum=421
3287 04:41:19.257269 TX Vref=30, minBit 9, minWin=25, winSum=425
3288 04:41:19.263867 TX Vref=32, minBit 9, minWin=25, winSum=420
3289 04:41:19.267280 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 30
3290 04:41:19.267400
3291 04:41:19.270626 Final TX Range 1 Vref 30
3292 04:41:19.270722
3293 04:41:19.270820 ==
3294 04:41:19.274180 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 04:41:19.277346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 04:41:19.280529 ==
3297 04:41:19.280622
3298 04:41:19.280704
3299 04:41:19.280784 TX Vref Scan disable
3300 04:41:19.284144 == TX Byte 0 ==
3301 04:41:19.287530 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3302 04:41:19.290550 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3303 04:41:19.294180 == TX Byte 1 ==
3304 04:41:19.297391 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3305 04:41:19.300874 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3306 04:41:19.303939
3307 04:41:19.304046 [DATLAT]
3308 04:41:19.304145 Freq=1200, CH1 RK0
3309 04:41:19.304245
3310 04:41:19.307526 DATLAT Default: 0xd
3311 04:41:19.307633 0, 0xFFFF, sum = 0
3312 04:41:19.310580 1, 0xFFFF, sum = 0
3313 04:41:19.310701 2, 0xFFFF, sum = 0
3314 04:41:19.313864 3, 0xFFFF, sum = 0
3315 04:41:19.313941 4, 0xFFFF, sum = 0
3316 04:41:19.317606 5, 0xFFFF, sum = 0
3317 04:41:19.320722 6, 0xFFFF, sum = 0
3318 04:41:19.320828 7, 0xFFFF, sum = 0
3319 04:41:19.324295 8, 0xFFFF, sum = 0
3320 04:41:19.324404 9, 0xFFFF, sum = 0
3321 04:41:19.327528 10, 0xFFFF, sum = 0
3322 04:41:19.327634 11, 0xFFFF, sum = 0
3323 04:41:19.330737 12, 0x0, sum = 1
3324 04:41:19.330839 13, 0x0, sum = 2
3325 04:41:19.333787 14, 0x0, sum = 3
3326 04:41:19.333868 15, 0x0, sum = 4
3327 04:41:19.333951 best_step = 13
3328 04:41:19.337463
3329 04:41:19.337548 ==
3330 04:41:19.340487 Dram Type= 6, Freq= 0, CH_1, rank 0
3331 04:41:19.343968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3332 04:41:19.344087 ==
3333 04:41:19.344183 RX Vref Scan: 1
3334 04:41:19.344272
3335 04:41:19.347127 Set Vref Range= 32 -> 127
3336 04:41:19.347237
3337 04:41:19.350692 RX Vref 32 -> 127, step: 1
3338 04:41:19.350776
3339 04:41:19.353695 RX Delay -21 -> 252, step: 4
3340 04:41:19.353775
3341 04:41:19.357279 Set Vref, RX VrefLevel [Byte0]: 32
3342 04:41:19.360574 [Byte1]: 32
3343 04:41:19.360675
3344 04:41:19.363640 Set Vref, RX VrefLevel [Byte0]: 33
3345 04:41:19.367273 [Byte1]: 33
3346 04:41:19.370588
3347 04:41:19.370698 Set Vref, RX VrefLevel [Byte0]: 34
3348 04:41:19.373739 [Byte1]: 34
3349 04:41:19.378418
3350 04:41:19.378517 Set Vref, RX VrefLevel [Byte0]: 35
3351 04:41:19.381856 [Byte1]: 35
3352 04:41:19.386452
3353 04:41:19.386528 Set Vref, RX VrefLevel [Byte0]: 36
3354 04:41:19.389614 [Byte1]: 36
3355 04:41:19.394418
3356 04:41:19.394500 Set Vref, RX VrefLevel [Byte0]: 37
3357 04:41:19.397598 [Byte1]: 37
3358 04:41:19.402071
3359 04:41:19.402165 Set Vref, RX VrefLevel [Byte0]: 38
3360 04:41:19.405434 [Byte1]: 38
3361 04:41:19.410168
3362 04:41:19.410284 Set Vref, RX VrefLevel [Byte0]: 39
3363 04:41:19.413386 [Byte1]: 39
3364 04:41:19.417842
3365 04:41:19.417955 Set Vref, RX VrefLevel [Byte0]: 40
3366 04:41:19.421405 [Byte1]: 40
3367 04:41:19.425903
3368 04:41:19.426009 Set Vref, RX VrefLevel [Byte0]: 41
3369 04:41:19.429088 [Byte1]: 41
3370 04:41:19.433715
3371 04:41:19.433819 Set Vref, RX VrefLevel [Byte0]: 42
3372 04:41:19.437391 [Byte1]: 42
3373 04:41:19.441731
3374 04:41:19.441825 Set Vref, RX VrefLevel [Byte0]: 43
3375 04:41:19.445191 [Byte1]: 43
3376 04:41:19.449841
3377 04:41:19.449922 Set Vref, RX VrefLevel [Byte0]: 44
3378 04:41:19.452837 [Byte1]: 44
3379 04:41:19.457586
3380 04:41:19.457714 Set Vref, RX VrefLevel [Byte0]: 45
3381 04:41:19.461266 [Byte1]: 45
3382 04:41:19.465391
3383 04:41:19.465515 Set Vref, RX VrefLevel [Byte0]: 46
3384 04:41:19.469070 [Byte1]: 46
3385 04:41:19.473645
3386 04:41:19.473739 Set Vref, RX VrefLevel [Byte0]: 47
3387 04:41:19.476660 [Byte1]: 47
3388 04:41:19.481443
3389 04:41:19.481553 Set Vref, RX VrefLevel [Byte0]: 48
3390 04:41:19.484621 [Byte1]: 48
3391 04:41:19.489118
3392 04:41:19.489311 Set Vref, RX VrefLevel [Byte0]: 49
3393 04:41:19.492489 [Byte1]: 49
3394 04:41:19.497364
3395 04:41:19.497503 Set Vref, RX VrefLevel [Byte0]: 50
3396 04:41:19.500722 [Byte1]: 50
3397 04:41:19.505283
3398 04:41:19.505381 Set Vref, RX VrefLevel [Byte0]: 51
3399 04:41:19.508374 [Byte1]: 51
3400 04:41:19.512952
3401 04:41:19.513052 Set Vref, RX VrefLevel [Byte0]: 52
3402 04:41:19.516217 [Byte1]: 52
3403 04:41:19.521014
3404 04:41:19.521156 Set Vref, RX VrefLevel [Byte0]: 53
3405 04:41:19.524113 [Byte1]: 53
3406 04:41:19.529075
3407 04:41:19.529196 Set Vref, RX VrefLevel [Byte0]: 54
3408 04:41:19.532133 [Byte1]: 54
3409 04:41:19.536674
3410 04:41:19.536767 Set Vref, RX VrefLevel [Byte0]: 55
3411 04:41:19.540256 [Byte1]: 55
3412 04:41:19.544607
3413 04:41:19.544718 Set Vref, RX VrefLevel [Byte0]: 56
3414 04:41:19.548146 [Byte1]: 56
3415 04:41:19.552801
3416 04:41:19.552907 Set Vref, RX VrefLevel [Byte0]: 57
3417 04:41:19.555987 [Byte1]: 57
3418 04:41:19.560511
3419 04:41:19.560621 Set Vref, RX VrefLevel [Byte0]: 58
3420 04:41:19.563840 [Byte1]: 58
3421 04:41:19.568488
3422 04:41:19.568586 Set Vref, RX VrefLevel [Byte0]: 59
3423 04:41:19.572018 [Byte1]: 59
3424 04:41:19.576367
3425 04:41:19.576476 Set Vref, RX VrefLevel [Byte0]: 60
3426 04:41:19.579733 [Byte1]: 60
3427 04:41:19.584492
3428 04:41:19.584595 Set Vref, RX VrefLevel [Byte0]: 61
3429 04:41:19.587731 [Byte1]: 61
3430 04:41:19.592233
3431 04:41:19.592346 Set Vref, RX VrefLevel [Byte0]: 62
3432 04:41:19.595728 [Byte1]: 62
3433 04:41:19.600189
3434 04:41:19.600312 Set Vref, RX VrefLevel [Byte0]: 63
3435 04:41:19.603652 [Byte1]: 63
3436 04:41:19.608309
3437 04:41:19.608423 Set Vref, RX VrefLevel [Byte0]: 64
3438 04:41:19.611380 [Byte1]: 64
3439 04:41:19.615893
3440 04:41:19.616017 Set Vref, RX VrefLevel [Byte0]: 65
3441 04:41:19.619203 [Byte1]: 65
3442 04:41:19.624194
3443 04:41:19.624333 Set Vref, RX VrefLevel [Byte0]: 66
3444 04:41:19.627125 [Byte1]: 66
3445 04:41:19.631888
3446 04:41:19.632029 Final RX Vref Byte 0 = 54 to rank0
3447 04:41:19.635507 Final RX Vref Byte 1 = 53 to rank0
3448 04:41:19.638855 Final RX Vref Byte 0 = 54 to rank1
3449 04:41:19.642143 Final RX Vref Byte 1 = 53 to rank1==
3450 04:41:19.645338 Dram Type= 6, Freq= 0, CH_1, rank 0
3451 04:41:19.648391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 04:41:19.651997 ==
3453 04:41:19.652100 DQS Delay:
3454 04:41:19.652201 DQS0 = 0, DQS1 = 0
3455 04:41:19.655445 DQM Delay:
3456 04:41:19.655560 DQM0 = 114, DQM1 = 106
3457 04:41:19.658523 DQ Delay:
3458 04:41:19.662156 DQ0 =120, DQ1 =108, DQ2 =104, DQ3 =112
3459 04:41:19.665380 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =112
3460 04:41:19.668430 DQ8 =94, DQ9 =98, DQ10 =106, DQ11 =102
3461 04:41:19.671972 DQ12 =114, DQ13 =112, DQ14 =112, DQ15 =112
3462 04:41:19.672078
3463 04:41:19.672159
3464 04:41:19.678522 [DQSOSCAuto] RK0, (LSB)MR18= 0xedf4, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 417 ps
3465 04:41:19.681990 CH1 RK0: MR19=303, MR18=EDF4
3466 04:41:19.688706 CH1_RK0: MR19=0x303, MR18=0xEDF4, DQSOSC=415, MR23=63, INC=38, DEC=25
3467 04:41:19.688831
3468 04:41:19.691804 ----->DramcWriteLeveling(PI) begin...
3469 04:41:19.691896 ==
3470 04:41:19.695143 Dram Type= 6, Freq= 0, CH_1, rank 1
3471 04:41:19.698336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3472 04:41:19.701808 ==
3473 04:41:19.701930 Write leveling (Byte 0): 26 => 26
3474 04:41:19.705018 Write leveling (Byte 1): 28 => 28
3475 04:41:19.708465 DramcWriteLeveling(PI) end<-----
3476 04:41:19.708557
3477 04:41:19.708645 ==
3478 04:41:19.711619 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 04:41:19.718292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 04:41:19.718417 ==
3481 04:41:19.718501 [Gating] SW mode calibration
3482 04:41:19.728361 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3483 04:41:19.731681 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3484 04:41:19.738281 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 04:41:19.741559 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 04:41:19.744825 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 04:41:19.748205 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 04:41:19.755044 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 04:41:19.758296 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 04:41:19.761691 0 15 24 | B1->B0 | 3333 2525 | 1 0 | (1 0) (0 0)
3491 04:41:19.768301 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
3492 04:41:19.771615 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 04:41:19.774965 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 04:41:19.781484 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 04:41:19.784950 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 04:41:19.788516 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 04:41:19.795226 1 0 20 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
3498 04:41:19.798376 1 0 24 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
3499 04:41:19.801718 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3500 04:41:19.808542 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 04:41:19.811633 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 04:41:19.815111 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 04:41:19.821446 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 04:41:19.824750 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 04:41:19.828205 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 04:41:19.834924 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3507 04:41:19.838077 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3508 04:41:19.841464 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 04:41:19.844969 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 04:41:19.851445 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 04:41:19.854774 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 04:41:19.857893 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 04:41:19.864908 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 04:41:19.867836 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 04:41:19.871292 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 04:41:19.877700 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 04:41:19.881128 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 04:41:19.884362 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 04:41:19.890909 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 04:41:19.894337 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 04:41:19.897569 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3522 04:41:19.904260 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3523 04:41:19.907732 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 04:41:19.911298 Total UI for P1: 0, mck2ui 16
3525 04:41:19.914349 best dqsien dly found for B0: ( 1, 3, 22)
3526 04:41:19.917560 Total UI for P1: 0, mck2ui 16
3527 04:41:19.920723 best dqsien dly found for B1: ( 1, 3, 24)
3528 04:41:19.924221 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3529 04:41:19.927684 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3530 04:41:19.927784
3531 04:41:19.930857 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3532 04:41:19.934101 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3533 04:41:19.937305 [Gating] SW calibration Done
3534 04:41:19.937420 ==
3535 04:41:19.940797 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 04:41:19.947458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 04:41:19.947563 ==
3538 04:41:19.947635 RX Vref Scan: 0
3539 04:41:19.947697
3540 04:41:19.950906 RX Vref 0 -> 0, step: 1
3541 04:41:19.950995
3542 04:41:19.954126 RX Delay -40 -> 252, step: 8
3543 04:41:19.957359 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3544 04:41:19.960657 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3545 04:41:19.964127 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3546 04:41:19.967107 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3547 04:41:19.974050 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3548 04:41:19.977239 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3549 04:41:19.980663 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3550 04:41:19.984255 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3551 04:41:19.987322 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3552 04:41:19.993826 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3553 04:41:19.997268 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3554 04:41:20.000350 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3555 04:41:20.003814 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3556 04:41:20.007225 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3557 04:41:20.013723 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3558 04:41:20.016899 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3559 04:41:20.017026 ==
3560 04:41:20.020514 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 04:41:20.023678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 04:41:20.023822 ==
3563 04:41:20.027047 DQS Delay:
3564 04:41:20.027193 DQS0 = 0, DQS1 = 0
3565 04:41:20.027302 DQM Delay:
3566 04:41:20.030467 DQM0 = 110, DQM1 = 108
3567 04:41:20.030571 DQ Delay:
3568 04:41:20.033772 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3569 04:41:20.036932 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3570 04:41:20.040060 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3571 04:41:20.046801 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =115
3572 04:41:20.046919
3573 04:41:20.047014
3574 04:41:20.047102 ==
3575 04:41:20.050347 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 04:41:20.053334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 04:41:20.053434 ==
3578 04:41:20.053512
3579 04:41:20.053616
3580 04:41:20.056698 TX Vref Scan disable
3581 04:41:20.056795 == TX Byte 0 ==
3582 04:41:20.063420 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3583 04:41:20.066742 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3584 04:41:20.066853 == TX Byte 1 ==
3585 04:41:20.073609 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3586 04:41:20.076684 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3587 04:41:20.076792 ==
3588 04:41:20.080133 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 04:41:20.083322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 04:41:20.083411 ==
3591 04:41:20.096053 TX Vref=22, minBit 9, minWin=25, winSum=424
3592 04:41:20.099486 TX Vref=24, minBit 9, minWin=25, winSum=428
3593 04:41:20.102682 TX Vref=26, minBit 8, minWin=26, winSum=431
3594 04:41:20.106231 TX Vref=28, minBit 8, minWin=26, winSum=434
3595 04:41:20.109340 TX Vref=30, minBit 3, minWin=26, winSum=434
3596 04:41:20.116070 TX Vref=32, minBit 1, minWin=25, winSum=431
3597 04:41:20.119194 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
3598 04:41:20.119297
3599 04:41:20.122503 Final TX Range 1 Vref 28
3600 04:41:20.122592
3601 04:41:20.122672 ==
3602 04:41:20.125870 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 04:41:20.129571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 04:41:20.129664 ==
3605 04:41:20.132540
3606 04:41:20.132665
3607 04:41:20.132736 TX Vref Scan disable
3608 04:41:20.135935 == TX Byte 0 ==
3609 04:41:20.139176 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3610 04:41:20.145693 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3611 04:41:20.145808 == TX Byte 1 ==
3612 04:41:20.149250 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3613 04:41:20.155773 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3614 04:41:20.155884
3615 04:41:20.155955 [DATLAT]
3616 04:41:20.156017 Freq=1200, CH1 RK1
3617 04:41:20.156077
3618 04:41:20.158901 DATLAT Default: 0xd
3619 04:41:20.158989 0, 0xFFFF, sum = 0
3620 04:41:20.162498 1, 0xFFFF, sum = 0
3621 04:41:20.165690 2, 0xFFFF, sum = 0
3622 04:41:20.165788 3, 0xFFFF, sum = 0
3623 04:41:20.168716 4, 0xFFFF, sum = 0
3624 04:41:20.168815 5, 0xFFFF, sum = 0
3625 04:41:20.172339 6, 0xFFFF, sum = 0
3626 04:41:20.172433 7, 0xFFFF, sum = 0
3627 04:41:20.175557 8, 0xFFFF, sum = 0
3628 04:41:20.175644 9, 0xFFFF, sum = 0
3629 04:41:20.178775 10, 0xFFFF, sum = 0
3630 04:41:20.178862 11, 0xFFFF, sum = 0
3631 04:41:20.182285 12, 0x0, sum = 1
3632 04:41:20.182373 13, 0x0, sum = 2
3633 04:41:20.185362 14, 0x0, sum = 3
3634 04:41:20.185484 15, 0x0, sum = 4
3635 04:41:20.188833 best_step = 13
3636 04:41:20.188932
3637 04:41:20.188999 ==
3638 04:41:20.192063 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 04:41:20.195228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 04:41:20.195319 ==
3641 04:41:20.195387 RX Vref Scan: 0
3642 04:41:20.198674
3643 04:41:20.198787 RX Vref 0 -> 0, step: 1
3644 04:41:20.198874
3645 04:41:20.202102 RX Delay -21 -> 252, step: 4
3646 04:41:20.208953 iDelay=195, Bit 0, Center 112 (39 ~ 186) 148
3647 04:41:20.211968 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3648 04:41:20.215557 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3649 04:41:20.218583 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3650 04:41:20.222103 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3651 04:41:20.225236 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3652 04:41:20.232093 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3653 04:41:20.235604 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3654 04:41:20.238674 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3655 04:41:20.241903 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3656 04:41:20.245204 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3657 04:41:20.252106 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3658 04:41:20.255016 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3659 04:41:20.258728 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3660 04:41:20.261989 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3661 04:41:20.268647 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3662 04:41:20.268774 ==
3663 04:41:20.271802 Dram Type= 6, Freq= 0, CH_1, rank 1
3664 04:41:20.275281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3665 04:41:20.275399 ==
3666 04:41:20.275496 DQS Delay:
3667 04:41:20.278538 DQS0 = 0, DQS1 = 0
3668 04:41:20.278623 DQM Delay:
3669 04:41:20.281769 DQM0 = 110, DQM1 = 109
3670 04:41:20.281854 DQ Delay:
3671 04:41:20.285321 DQ0 =112, DQ1 =108, DQ2 =100, DQ3 =108
3672 04:41:20.288514 DQ4 =110, DQ5 =120, DQ6 =120, DQ7 =108
3673 04:41:20.291591 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =104
3674 04:41:20.295068 DQ12 =116, DQ13 =116, DQ14 =118, DQ15 =116
3675 04:41:20.295173
3676 04:41:20.295242
3677 04:41:20.305076 [DQSOSCAuto] RK1, (LSB)MR18= 0xf808, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3678 04:41:20.308122 CH1 RK1: MR19=304, MR18=F808
3679 04:41:20.314643 CH1_RK1: MR19=0x304, MR18=0xF808, DQSOSC=406, MR23=63, INC=39, DEC=26
3680 04:41:20.314748 [RxdqsGatingPostProcess] freq 1200
3681 04:41:20.321242 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3682 04:41:20.324593 best DQS0 dly(2T, 0.5T) = (0, 11)
3683 04:41:20.327920 best DQS1 dly(2T, 0.5T) = (0, 11)
3684 04:41:20.331288 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3685 04:41:20.334592 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3686 04:41:20.338060 best DQS0 dly(2T, 0.5T) = (0, 11)
3687 04:41:20.341184 best DQS1 dly(2T, 0.5T) = (0, 11)
3688 04:41:20.344634 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3689 04:41:20.347743 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3690 04:41:20.351322 Pre-setting of DQS Precalculation
3691 04:41:20.354565 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3692 04:41:20.361114 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3693 04:41:20.371191 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3694 04:41:20.371356
3695 04:41:20.371457
3696 04:41:20.371555 [Calibration Summary] 2400 Mbps
3697 04:41:20.374260 CH 0, Rank 0
3698 04:41:20.377577 SW Impedance : PASS
3699 04:41:20.377655 DUTY Scan : NO K
3700 04:41:20.381105 ZQ Calibration : PASS
3701 04:41:20.381214 Jitter Meter : NO K
3702 04:41:20.384081 CBT Training : PASS
3703 04:41:20.387667 Write leveling : PASS
3704 04:41:20.387750 RX DQS gating : PASS
3705 04:41:20.390835 RX DQ/DQS(RDDQC) : PASS
3706 04:41:20.393997 TX DQ/DQS : PASS
3707 04:41:20.394077 RX DATLAT : PASS
3708 04:41:20.397389 RX DQ/DQS(Engine): PASS
3709 04:41:20.401084 TX OE : NO K
3710 04:41:20.401169 All Pass.
3711 04:41:20.401242
3712 04:41:20.401302 CH 0, Rank 1
3713 04:41:20.404295 SW Impedance : PASS
3714 04:41:20.407457 DUTY Scan : NO K
3715 04:41:20.407538 ZQ Calibration : PASS
3716 04:41:20.410648 Jitter Meter : NO K
3717 04:41:20.414175 CBT Training : PASS
3718 04:41:20.414262 Write leveling : PASS
3719 04:41:20.417250 RX DQS gating : PASS
3720 04:41:20.420627 RX DQ/DQS(RDDQC) : PASS
3721 04:41:20.420714 TX DQ/DQS : PASS
3722 04:41:20.424192 RX DATLAT : PASS
3723 04:41:20.424299 RX DQ/DQS(Engine): PASS
3724 04:41:20.427792 TX OE : NO K
3725 04:41:20.427922 All Pass.
3726 04:41:20.428046
3727 04:41:20.431046 CH 1, Rank 0
3728 04:41:20.431148 SW Impedance : PASS
3729 04:41:20.434398 DUTY Scan : NO K
3730 04:41:20.437831 ZQ Calibration : PASS
3731 04:41:20.437938 Jitter Meter : NO K
3732 04:41:20.440868 CBT Training : PASS
3733 04:41:20.444093 Write leveling : PASS
3734 04:41:20.444198 RX DQS gating : PASS
3735 04:41:20.447592 RX DQ/DQS(RDDQC) : PASS
3736 04:41:20.450770 TX DQ/DQS : PASS
3737 04:41:20.450874 RX DATLAT : PASS
3738 04:41:20.454333 RX DQ/DQS(Engine): PASS
3739 04:41:20.457734 TX OE : NO K
3740 04:41:20.457823 All Pass.
3741 04:41:20.457917
3742 04:41:20.457994 CH 1, Rank 1
3743 04:41:20.460636 SW Impedance : PASS
3744 04:41:20.464283 DUTY Scan : NO K
3745 04:41:20.464388 ZQ Calibration : PASS
3746 04:41:20.467387 Jitter Meter : NO K
3747 04:41:20.470468 CBT Training : PASS
3748 04:41:20.470578 Write leveling : PASS
3749 04:41:20.473975 RX DQS gating : PASS
3750 04:41:20.477234 RX DQ/DQS(RDDQC) : PASS
3751 04:41:20.477362 TX DQ/DQS : PASS
3752 04:41:20.480591 RX DATLAT : PASS
3753 04:41:20.480741 RX DQ/DQS(Engine): PASS
3754 04:41:20.483888 TX OE : NO K
3755 04:41:20.483992 All Pass.
3756 04:41:20.484088
3757 04:41:20.487163 DramC Write-DBI off
3758 04:41:20.490451 PER_BANK_REFRESH: Hybrid Mode
3759 04:41:20.490543 TX_TRACKING: ON
3760 04:41:20.500420 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3761 04:41:20.503766 [FAST_K] Save calibration result to emmc
3762 04:41:20.507323 dramc_set_vcore_voltage set vcore to 650000
3763 04:41:20.510664 Read voltage for 600, 5
3764 04:41:20.510772 Vio18 = 0
3765 04:41:20.513853 Vcore = 650000
3766 04:41:20.513940 Vdram = 0
3767 04:41:20.514005 Vddq = 0
3768 04:41:20.514065 Vmddr = 0
3769 04:41:20.520367 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3770 04:41:20.526984 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3771 04:41:20.527109 MEM_TYPE=3, freq_sel=19
3772 04:41:20.530220 sv_algorithm_assistance_LP4_1600
3773 04:41:20.533456 ============ PULL DRAM RESETB DOWN ============
3774 04:41:20.540192 ========== PULL DRAM RESETB DOWN end =========
3775 04:41:20.543470 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3776 04:41:20.546806 ===================================
3777 04:41:20.549896 LPDDR4 DRAM CONFIGURATION
3778 04:41:20.553442 ===================================
3779 04:41:20.553614 EX_ROW_EN[0] = 0x0
3780 04:41:20.556661 EX_ROW_EN[1] = 0x0
3781 04:41:20.556776 LP4Y_EN = 0x0
3782 04:41:20.559829 WORK_FSP = 0x0
3783 04:41:20.563071 WL = 0x2
3784 04:41:20.563195 RL = 0x2
3785 04:41:20.566552 BL = 0x2
3786 04:41:20.566671 RPST = 0x0
3787 04:41:20.569688 RD_PRE = 0x0
3788 04:41:20.569813 WR_PRE = 0x1
3789 04:41:20.573240 WR_PST = 0x0
3790 04:41:20.573358 DBI_WR = 0x0
3791 04:41:20.576453 DBI_RD = 0x0
3792 04:41:20.576566 OTF = 0x1
3793 04:41:20.579700 ===================================
3794 04:41:20.582990 ===================================
3795 04:41:20.586398 ANA top config
3796 04:41:20.589887 ===================================
3797 04:41:20.589991 DLL_ASYNC_EN = 0
3798 04:41:20.592937 ALL_SLAVE_EN = 1
3799 04:41:20.596245 NEW_RANK_MODE = 1
3800 04:41:20.599450 DLL_IDLE_MODE = 1
3801 04:41:20.599550 LP45_APHY_COMB_EN = 1
3802 04:41:20.602781 TX_ODT_DIS = 1
3803 04:41:20.606387 NEW_8X_MODE = 1
3804 04:41:20.609389 ===================================
3805 04:41:20.612788 ===================================
3806 04:41:20.616100 data_rate = 1200
3807 04:41:20.619197 CKR = 1
3808 04:41:20.622795 DQ_P2S_RATIO = 8
3809 04:41:20.625998 ===================================
3810 04:41:20.626128 CA_P2S_RATIO = 8
3811 04:41:20.629270 DQ_CA_OPEN = 0
3812 04:41:20.632555 DQ_SEMI_OPEN = 0
3813 04:41:20.635952 CA_SEMI_OPEN = 0
3814 04:41:20.639271 CA_FULL_RATE = 0
3815 04:41:20.642705 DQ_CKDIV4_EN = 1
3816 04:41:20.642837 CA_CKDIV4_EN = 1
3817 04:41:20.645793 CA_PREDIV_EN = 0
3818 04:41:20.649282 PH8_DLY = 0
3819 04:41:20.652267 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3820 04:41:20.655584 DQ_AAMCK_DIV = 4
3821 04:41:20.658875 CA_AAMCK_DIV = 4
3822 04:41:20.662074 CA_ADMCK_DIV = 4
3823 04:41:20.662201 DQ_TRACK_CA_EN = 0
3824 04:41:20.665498 CA_PICK = 600
3825 04:41:20.668902 CA_MCKIO = 600
3826 04:41:20.672444 MCKIO_SEMI = 0
3827 04:41:20.675519 PLL_FREQ = 2288
3828 04:41:20.679020 DQ_UI_PI_RATIO = 32
3829 04:41:20.682315 CA_UI_PI_RATIO = 0
3830 04:41:20.685419 ===================================
3831 04:41:20.688669 ===================================
3832 04:41:20.688785 memory_type:LPDDR4
3833 04:41:20.691792 GP_NUM : 10
3834 04:41:20.695366 SRAM_EN : 1
3835 04:41:20.695481 MD32_EN : 0
3836 04:41:20.698463 ===================================
3837 04:41:20.701729 [ANA_INIT] >>>>>>>>>>>>>>
3838 04:41:20.705332 <<<<<< [CONFIGURE PHASE]: ANA_TX
3839 04:41:20.708395 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3840 04:41:20.711972 ===================================
3841 04:41:20.715199 data_rate = 1200,PCW = 0X5800
3842 04:41:20.718519 ===================================
3843 04:41:20.721901 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3844 04:41:20.725099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3845 04:41:20.731525 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3846 04:41:20.734914 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3847 04:41:20.738187 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3848 04:41:20.741403 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3849 04:41:20.744764 [ANA_INIT] flow start
3850 04:41:20.748241 [ANA_INIT] PLL >>>>>>>>
3851 04:41:20.748362 [ANA_INIT] PLL <<<<<<<<
3852 04:41:20.751360 [ANA_INIT] MIDPI >>>>>>>>
3853 04:41:20.755014 [ANA_INIT] MIDPI <<<<<<<<
3854 04:41:20.758217 [ANA_INIT] DLL >>>>>>>>
3855 04:41:20.758336 [ANA_INIT] flow end
3856 04:41:20.761353 ============ LP4 DIFF to SE enter ============
3857 04:41:20.767949 ============ LP4 DIFF to SE exit ============
3858 04:41:20.768080 [ANA_INIT] <<<<<<<<<<<<<
3859 04:41:20.771291 [Flow] Enable top DCM control >>>>>
3860 04:41:20.774639 [Flow] Enable top DCM control <<<<<
3861 04:41:20.777830 Enable DLL master slave shuffle
3862 04:41:20.784574 ==============================================================
3863 04:41:20.784707 Gating Mode config
3864 04:41:20.791177 ==============================================================
3865 04:41:20.794710 Config description:
3866 04:41:20.804554 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3867 04:41:20.810954 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3868 04:41:20.814640 SELPH_MODE 0: By rank 1: By Phase
3869 04:41:20.821257 ==============================================================
3870 04:41:20.824301 GAT_TRACK_EN = 1
3871 04:41:20.824398 RX_GATING_MODE = 2
3872 04:41:20.827857 RX_GATING_TRACK_MODE = 2
3873 04:41:20.831246 SELPH_MODE = 1
3874 04:41:20.834407 PICG_EARLY_EN = 1
3875 04:41:20.837470 VALID_LAT_VALUE = 1
3876 04:41:20.844277 ==============================================================
3877 04:41:20.847378 Enter into Gating configuration >>>>
3878 04:41:20.850917 Exit from Gating configuration <<<<
3879 04:41:20.854260 Enter into DVFS_PRE_config >>>>>
3880 04:41:20.863783 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3881 04:41:20.867322 Exit from DVFS_PRE_config <<<<<
3882 04:41:20.870469 Enter into PICG configuration >>>>
3883 04:41:20.874024 Exit from PICG configuration <<<<
3884 04:41:20.877447 [RX_INPUT] configuration >>>>>
3885 04:41:20.880572 [RX_INPUT] configuration <<<<<
3886 04:41:20.883996 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3887 04:41:20.890584 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3888 04:41:20.897368 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3889 04:41:20.900546 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3890 04:41:20.907274 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3891 04:41:20.913787 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3892 04:41:20.917037 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3893 04:41:20.923626 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3894 04:41:20.927195 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3895 04:41:20.930437 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3896 04:41:20.933826 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3897 04:41:20.940462 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3898 04:41:20.943639 ===================================
3899 04:41:20.943736 LPDDR4 DRAM CONFIGURATION
3900 04:41:20.947046 ===================================
3901 04:41:20.950420 EX_ROW_EN[0] = 0x0
3902 04:41:20.953685 EX_ROW_EN[1] = 0x0
3903 04:41:20.953776 LP4Y_EN = 0x0
3904 04:41:20.956926 WORK_FSP = 0x0
3905 04:41:20.957011 WL = 0x2
3906 04:41:20.960182 RL = 0x2
3907 04:41:20.960295 BL = 0x2
3908 04:41:20.963758 RPST = 0x0
3909 04:41:20.963872 RD_PRE = 0x0
3910 04:41:20.966973 WR_PRE = 0x1
3911 04:41:20.967084 WR_PST = 0x0
3912 04:41:20.970427 DBI_WR = 0x0
3913 04:41:20.970545 DBI_RD = 0x0
3914 04:41:20.973729 OTF = 0x1
3915 04:41:20.976874 ===================================
3916 04:41:20.980182 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3917 04:41:20.983554 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3918 04:41:20.990206 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3919 04:41:20.993399 ===================================
3920 04:41:20.993530 LPDDR4 DRAM CONFIGURATION
3921 04:41:20.996882 ===================================
3922 04:41:21.000101 EX_ROW_EN[0] = 0x10
3923 04:41:21.000215 EX_ROW_EN[1] = 0x0
3924 04:41:21.003663 LP4Y_EN = 0x0
3925 04:41:21.006807 WORK_FSP = 0x0
3926 04:41:21.006927 WL = 0x2
3927 04:41:21.010268 RL = 0x2
3928 04:41:21.010350 BL = 0x2
3929 04:41:21.013628 RPST = 0x0
3930 04:41:21.013707 RD_PRE = 0x0
3931 04:41:21.016821 WR_PRE = 0x1
3932 04:41:21.016932 WR_PST = 0x0
3933 04:41:21.020112 DBI_WR = 0x0
3934 04:41:21.020209 DBI_RD = 0x0
3935 04:41:21.023640 OTF = 0x1
3936 04:41:21.026916 ===================================
3937 04:41:21.033389 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3938 04:41:21.036676 nWR fixed to 30
3939 04:41:21.036790 [ModeRegInit_LP4] CH0 RK0
3940 04:41:21.039815 [ModeRegInit_LP4] CH0 RK1
3941 04:41:21.043296 [ModeRegInit_LP4] CH1 RK0
3942 04:41:21.043406 [ModeRegInit_LP4] CH1 RK1
3943 04:41:21.046542 match AC timing 17
3944 04:41:21.050080 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3945 04:41:21.053136 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3946 04:41:21.060067 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3947 04:41:21.063057 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3948 04:41:21.069960 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3949 04:41:21.070053 ==
3950 04:41:21.073257 Dram Type= 6, Freq= 0, CH_0, rank 0
3951 04:41:21.076587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 04:41:21.076690 ==
3953 04:41:21.082865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3954 04:41:21.089699 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3955 04:41:21.092784 [CA 0] Center 37 (7~67) winsize 61
3956 04:41:21.096421 [CA 1] Center 36 (6~67) winsize 62
3957 04:41:21.099405 [CA 2] Center 35 (5~65) winsize 61
3958 04:41:21.103110 [CA 3] Center 35 (5~65) winsize 61
3959 04:41:21.106190 [CA 4] Center 34 (4~65) winsize 62
3960 04:41:21.109395 [CA 5] Center 34 (4~64) winsize 61
3961 04:41:21.109486
3962 04:41:21.113058 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3963 04:41:21.113140
3964 04:41:21.116152 [CATrainingPosCal] consider 1 rank data
3965 04:41:21.119538 u2DelayCellTimex100 = 270/100 ps
3966 04:41:21.122770 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3967 04:41:21.126239 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3968 04:41:21.129423 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3969 04:41:21.132642 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3970 04:41:21.136048 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3971 04:41:21.139143 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3972 04:41:21.139215
3973 04:41:21.145991 CA PerBit enable=1, Macro0, CA PI delay=34
3974 04:41:21.146063
3975 04:41:21.146126 [CBTSetCACLKResult] CA Dly = 34
3976 04:41:21.149138 CS Dly: 5 (0~36)
3977 04:41:21.149230 ==
3978 04:41:21.152366 Dram Type= 6, Freq= 0, CH_0, rank 1
3979 04:41:21.155977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 04:41:21.156049 ==
3981 04:41:21.162594 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3982 04:41:21.169150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3983 04:41:21.172338 [CA 0] Center 37 (7~67) winsize 61
3984 04:41:21.175921 [CA 1] Center 36 (6~67) winsize 62
3985 04:41:21.179025 [CA 2] Center 35 (5~65) winsize 61
3986 04:41:21.182623 [CA 3] Center 35 (5~65) winsize 61
3987 04:41:21.185748 [CA 4] Center 34 (3~65) winsize 63
3988 04:41:21.188739 [CA 5] Center 34 (3~65) winsize 63
3989 04:41:21.188849
3990 04:41:21.192306 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3991 04:41:21.192416
3992 04:41:21.195473 [CATrainingPosCal] consider 2 rank data
3993 04:41:21.199043 u2DelayCellTimex100 = 270/100 ps
3994 04:41:21.202002 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3995 04:41:21.205448 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3996 04:41:21.209019 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3997 04:41:21.212271 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3998 04:41:21.215428 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3999 04:41:21.219031 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4000 04:41:21.222162
4001 04:41:21.225361 CA PerBit enable=1, Macro0, CA PI delay=34
4002 04:41:21.225498
4003 04:41:21.228901 [CBTSetCACLKResult] CA Dly = 34
4004 04:41:21.229004 CS Dly: 5 (0~37)
4005 04:41:21.229072
4006 04:41:21.232051 ----->DramcWriteLeveling(PI) begin...
4007 04:41:21.232152 ==
4008 04:41:21.235210 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 04:41:21.238771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4010 04:41:21.241821 ==
4011 04:41:21.245105 Write leveling (Byte 0): 32 => 32
4012 04:41:21.245214 Write leveling (Byte 1): 32 => 32
4013 04:41:21.248531 DramcWriteLeveling(PI) end<-----
4014 04:41:21.248638
4015 04:41:21.248732 ==
4016 04:41:21.251704 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 04:41:21.258580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 04:41:21.258698 ==
4019 04:41:21.261827 [Gating] SW mode calibration
4020 04:41:21.268403 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4021 04:41:21.271779 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4022 04:41:21.278244 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4023 04:41:21.281627 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4024 04:41:21.284707 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 04:41:21.291389 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4026 04:41:21.294757 0 9 16 | B1->B0 | 3131 2d2d | 1 1 | (1 1) (1 0)
4027 04:41:21.297996 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 04:41:21.304853 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 04:41:21.307877 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 04:41:21.311362 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 04:41:21.317782 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 04:41:21.321101 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 04:41:21.324634 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4034 04:41:21.331238 0 10 16 | B1->B0 | 2929 4141 | 0 0 | (0 0) (0 0)
4035 04:41:21.334599 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 04:41:21.337726 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 04:41:21.344380 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 04:41:21.347572 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 04:41:21.351200 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 04:41:21.357580 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 04:41:21.360807 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 04:41:21.364279 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4043 04:41:21.370777 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 04:41:21.374121 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 04:41:21.377398 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 04:41:21.384011 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 04:41:21.387496 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 04:41:21.390539 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 04:41:21.394349 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 04:41:21.400414 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 04:41:21.403991 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 04:41:21.407221 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 04:41:21.413943 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 04:41:21.417423 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 04:41:21.420308 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 04:41:21.427263 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 04:41:21.430267 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 04:41:21.433859 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4059 04:41:21.437066 Total UI for P1: 0, mck2ui 16
4060 04:41:21.440501 best dqsien dly found for B0: ( 0, 13, 14)
4061 04:41:21.447060 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 04:41:21.447183 Total UI for P1: 0, mck2ui 16
4063 04:41:21.453794 best dqsien dly found for B1: ( 0, 13, 16)
4064 04:41:21.456937 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4065 04:41:21.460140 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4066 04:41:21.460252
4067 04:41:21.463623 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4068 04:41:21.466923 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4069 04:41:21.470604 [Gating] SW calibration Done
4070 04:41:21.470723 ==
4071 04:41:21.473587 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 04:41:21.477035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 04:41:21.477156 ==
4074 04:41:21.480173 RX Vref Scan: 0
4075 04:41:21.480294
4076 04:41:21.480389 RX Vref 0 -> 0, step: 1
4077 04:41:21.483703
4078 04:41:21.483812 RX Delay -230 -> 252, step: 16
4079 04:41:21.490009 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4080 04:41:21.493471 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4081 04:41:21.497028 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4082 04:41:21.500245 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4083 04:41:21.506720 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4084 04:41:21.510206 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4085 04:41:21.513363 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4086 04:41:21.516924 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4087 04:41:21.520407 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4088 04:41:21.526944 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4089 04:41:21.530078 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4090 04:41:21.533609 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4091 04:41:21.536862 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4092 04:41:21.543246 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4093 04:41:21.546819 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4094 04:41:21.549808 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4095 04:41:21.549922 ==
4096 04:41:21.553418 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 04:41:21.556654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 04:41:21.559843 ==
4099 04:41:21.559957 DQS Delay:
4100 04:41:21.560053 DQS0 = 0, DQS1 = 0
4101 04:41:21.562949 DQM Delay:
4102 04:41:21.563057 DQM0 = 37, DQM1 = 29
4103 04:41:21.566476 DQ Delay:
4104 04:41:21.566587 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4105 04:41:21.569605 DQ4 =33, DQ5 =25, DQ6 =57, DQ7 =49
4106 04:41:21.572929 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4107 04:41:21.576313 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4108 04:41:21.579513
4109 04:41:21.579624
4110 04:41:21.579722 ==
4111 04:41:21.583076 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 04:41:21.586230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 04:41:21.586342 ==
4114 04:41:21.586439
4115 04:41:21.586532
4116 04:41:21.589421 TX Vref Scan disable
4117 04:41:21.589541 == TX Byte 0 ==
4118 04:41:21.596170 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4119 04:41:21.599421 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4120 04:41:21.599533 == TX Byte 1 ==
4121 04:41:21.606181 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4122 04:41:21.609546 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4123 04:41:21.609666 ==
4124 04:41:21.612695 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 04:41:21.615887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 04:41:21.616004 ==
4127 04:41:21.616103
4128 04:41:21.616197
4129 04:41:21.619537 TX Vref Scan disable
4130 04:41:21.622620 == TX Byte 0 ==
4131 04:41:21.626039 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4132 04:41:21.629201 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4133 04:41:21.632748 == TX Byte 1 ==
4134 04:41:21.636123 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4135 04:41:21.639267 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4136 04:41:21.642631
4137 04:41:21.642747 [DATLAT]
4138 04:41:21.642844 Freq=600, CH0 RK0
4139 04:41:21.642940
4140 04:41:21.645900 DATLAT Default: 0x9
4141 04:41:21.646015 0, 0xFFFF, sum = 0
4142 04:41:21.649159 1, 0xFFFF, sum = 0
4143 04:41:21.649272 2, 0xFFFF, sum = 0
4144 04:41:21.652219 3, 0xFFFF, sum = 0
4145 04:41:21.655779 4, 0xFFFF, sum = 0
4146 04:41:21.655898 5, 0xFFFF, sum = 0
4147 04:41:21.659005 6, 0xFFFF, sum = 0
4148 04:41:21.659121 7, 0xFFFF, sum = 0
4149 04:41:21.662270 8, 0x0, sum = 1
4150 04:41:21.662388 9, 0x0, sum = 2
4151 04:41:21.662489 10, 0x0, sum = 3
4152 04:41:21.665390 11, 0x0, sum = 4
4153 04:41:21.665508 best_step = 9
4154 04:41:21.665607
4155 04:41:21.665701 ==
4156 04:41:21.669018 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 04:41:21.675354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 04:41:21.675491 ==
4159 04:41:21.675592 RX Vref Scan: 1
4160 04:41:21.675685
4161 04:41:21.678714 RX Vref 0 -> 0, step: 1
4162 04:41:21.678825
4163 04:41:21.681876 RX Delay -195 -> 252, step: 8
4164 04:41:21.681985
4165 04:41:21.685134 Set Vref, RX VrefLevel [Byte0]: 62
4166 04:41:21.688561 [Byte1]: 46
4167 04:41:21.688674
4168 04:41:21.692096 Final RX Vref Byte 0 = 62 to rank0
4169 04:41:21.695295 Final RX Vref Byte 1 = 46 to rank0
4170 04:41:21.698594 Final RX Vref Byte 0 = 62 to rank1
4171 04:41:21.702083 Final RX Vref Byte 1 = 46 to rank1==
4172 04:41:21.705156 Dram Type= 6, Freq= 0, CH_0, rank 0
4173 04:41:21.708491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 04:41:21.708604 ==
4175 04:41:21.711868 DQS Delay:
4176 04:41:21.711983 DQS0 = 0, DQS1 = 0
4177 04:41:21.714873 DQM Delay:
4178 04:41:21.714983 DQM0 = 36, DQM1 = 29
4179 04:41:21.715080 DQ Delay:
4180 04:41:21.718414 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4181 04:41:21.721493 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =48
4182 04:41:21.724770 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4183 04:41:21.728281 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4184 04:41:21.728395
4185 04:41:21.731402
4186 04:41:21.738356 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4187 04:41:21.741307 CH0 RK0: MR19=808, MR18=3F3E
4188 04:41:21.748245 CH0_RK0: MR19=0x808, MR18=0x3F3E, DQSOSC=397, MR23=63, INC=166, DEC=110
4189 04:41:21.748365
4190 04:41:21.751454 ----->DramcWriteLeveling(PI) begin...
4191 04:41:21.751566 ==
4192 04:41:21.754624 Dram Type= 6, Freq= 0, CH_0, rank 1
4193 04:41:21.757946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 04:41:21.758061 ==
4195 04:41:21.761246 Write leveling (Byte 0): 32 => 32
4196 04:41:21.764669 Write leveling (Byte 1): 32 => 32
4197 04:41:21.767851 DramcWriteLeveling(PI) end<-----
4198 04:41:21.767967
4199 04:41:21.768065 ==
4200 04:41:21.771369 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 04:41:21.774592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 04:41:21.774710 ==
4203 04:41:21.778080 [Gating] SW mode calibration
4204 04:41:21.784556 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4205 04:41:21.791069 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4206 04:41:21.794323 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4207 04:41:21.797768 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 04:41:21.804243 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 04:41:21.807449 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 1)
4210 04:41:21.810951 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
4211 04:41:21.817357 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 04:41:21.820861 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 04:41:21.824070 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 04:41:21.830800 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 04:41:21.834054 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 04:41:21.837335 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 04:41:21.844119 0 10 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
4218 04:41:21.847316 0 10 16 | B1->B0 | 3636 4545 | 1 0 | (1 1) (0 0)
4219 04:41:21.850558 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 04:41:21.856900 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 04:41:21.860261 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 04:41:21.863667 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 04:41:21.870429 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 04:41:21.873638 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 04:41:21.876833 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4226 04:41:21.883629 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4227 04:41:21.887003 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 04:41:21.890139 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 04:41:21.896912 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 04:41:21.900137 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 04:41:21.903380 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 04:41:21.910007 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 04:41:21.913300 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 04:41:21.916839 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 04:41:21.923110 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 04:41:21.926737 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 04:41:21.929911 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 04:41:21.936305 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 04:41:21.939766 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 04:41:21.943095 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 04:41:21.949588 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4242 04:41:21.949709 Total UI for P1: 0, mck2ui 16
4243 04:41:21.956140 best dqsien dly found for B0: ( 0, 13, 10)
4244 04:41:21.959725 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4245 04:41:21.962704 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 04:41:21.966239 Total UI for P1: 0, mck2ui 16
4247 04:41:21.969561 best dqsien dly found for B1: ( 0, 13, 16)
4248 04:41:21.972675 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4249 04:41:21.976065 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4250 04:41:21.976179
4251 04:41:21.982745 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4252 04:41:21.985949 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4253 04:41:21.989438 [Gating] SW calibration Done
4254 04:41:21.989577 ==
4255 04:41:21.992591 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 04:41:21.996254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 04:41:21.996368 ==
4258 04:41:21.996464 RX Vref Scan: 0
4259 04:41:21.996556
4260 04:41:21.999440 RX Vref 0 -> 0, step: 1
4261 04:41:21.999564
4262 04:41:22.002519 RX Delay -230 -> 252, step: 16
4263 04:41:22.006163 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4264 04:41:22.009172 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4265 04:41:22.015836 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4266 04:41:22.018930 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4267 04:41:22.022314 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4268 04:41:22.025850 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4269 04:41:22.032291 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4270 04:41:22.035518 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4271 04:41:22.039130 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4272 04:41:22.042392 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4273 04:41:22.048784 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4274 04:41:22.052050 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4275 04:41:22.055507 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4276 04:41:22.058634 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4277 04:41:22.065656 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4278 04:41:22.068855 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4279 04:41:22.068974 ==
4280 04:41:22.072345 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 04:41:22.075314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 04:41:22.075438 ==
4283 04:41:22.075534 DQS Delay:
4284 04:41:22.078568 DQS0 = 0, DQS1 = 0
4285 04:41:22.078677 DQM Delay:
4286 04:41:22.081882 DQM0 = 35, DQM1 = 31
4287 04:41:22.082005 DQ Delay:
4288 04:41:22.085154 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4289 04:41:22.088561 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4290 04:41:22.091928 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4291 04:41:22.095080 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4292 04:41:22.095207
4293 04:41:22.095304
4294 04:41:22.095395 ==
4295 04:41:22.098555 Dram Type= 6, Freq= 0, CH_0, rank 1
4296 04:41:22.101763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4297 04:41:22.105193 ==
4298 04:41:22.105310
4299 04:41:22.105407
4300 04:41:22.105540 TX Vref Scan disable
4301 04:41:22.108558 == TX Byte 0 ==
4302 04:41:22.111668 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4303 04:41:22.118499 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4304 04:41:22.118622 == TX Byte 1 ==
4305 04:41:22.121489 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4306 04:41:22.128389 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4307 04:41:22.128525 ==
4308 04:41:22.131430 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 04:41:22.134709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 04:41:22.134838 ==
4311 04:41:22.134934
4312 04:41:22.135026
4313 04:41:22.138062 TX Vref Scan disable
4314 04:41:22.141588 == TX Byte 0 ==
4315 04:41:22.144795 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4316 04:41:22.148051 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4317 04:41:22.151637 == TX Byte 1 ==
4318 04:41:22.154884 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4319 04:41:22.158113 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4320 04:41:22.158224
4321 04:41:22.158318 [DATLAT]
4322 04:41:22.161550 Freq=600, CH0 RK1
4323 04:41:22.161656
4324 04:41:22.161749 DATLAT Default: 0x9
4325 04:41:22.164621 0, 0xFFFF, sum = 0
4326 04:41:22.168061 1, 0xFFFF, sum = 0
4327 04:41:22.168174 2, 0xFFFF, sum = 0
4328 04:41:22.171564 3, 0xFFFF, sum = 0
4329 04:41:22.171674 4, 0xFFFF, sum = 0
4330 04:41:22.174737 5, 0xFFFF, sum = 0
4331 04:41:22.174854 6, 0xFFFF, sum = 0
4332 04:41:22.177891 7, 0xFFFF, sum = 0
4333 04:41:22.178003 8, 0x0, sum = 1
4334 04:41:22.181376 9, 0x0, sum = 2
4335 04:41:22.181498 10, 0x0, sum = 3
4336 04:41:22.181608 11, 0x0, sum = 4
4337 04:41:22.184599 best_step = 9
4338 04:41:22.184703
4339 04:41:22.184797 ==
4340 04:41:22.187874 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 04:41:22.191387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 04:41:22.191498 ==
4343 04:41:22.194348 RX Vref Scan: 0
4344 04:41:22.194454
4345 04:41:22.197668 RX Vref 0 -> 0, step: 1
4346 04:41:22.197774
4347 04:41:22.197866 RX Delay -195 -> 252, step: 8
4348 04:41:22.205547 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4349 04:41:22.208659 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4350 04:41:22.211939 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4351 04:41:22.215221 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4352 04:41:22.221852 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4353 04:41:22.225289 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4354 04:41:22.228442 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4355 04:41:22.231931 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4356 04:41:22.238508 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4357 04:41:22.241852 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4358 04:41:22.245108 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4359 04:41:22.248641 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4360 04:41:22.251884 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4361 04:41:22.258312 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4362 04:41:22.261782 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4363 04:41:22.264930 iDelay=205, Bit 15, Center 32 (-123 ~ 188) 312
4364 04:41:22.265040 ==
4365 04:41:22.268412 Dram Type= 6, Freq= 0, CH_0, rank 1
4366 04:41:22.275099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 04:41:22.275241 ==
4368 04:41:22.275344 DQS Delay:
4369 04:41:22.275443 DQS0 = 0, DQS1 = 0
4370 04:41:22.278600 DQM Delay:
4371 04:41:22.278714 DQM0 = 34, DQM1 = 28
4372 04:41:22.281854 DQ Delay:
4373 04:41:22.284902 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4374 04:41:22.284978 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4375 04:41:22.288506 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
4376 04:41:22.294883 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =32
4377 04:41:22.294980
4378 04:41:22.295047
4379 04:41:22.301433 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4380 04:41:22.305034 CH0 RK1: MR19=808, MR18=6E3D
4381 04:41:22.311638 CH0_RK1: MR19=0x808, MR18=0x6E3D, DQSOSC=389, MR23=63, INC=173, DEC=115
4382 04:41:22.315068 [RxdqsGatingPostProcess] freq 600
4383 04:41:22.318053 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4384 04:41:22.321626 Pre-setting of DQS Precalculation
4385 04:41:22.328260 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4386 04:41:22.328364 ==
4387 04:41:22.331425 Dram Type= 6, Freq= 0, CH_1, rank 0
4388 04:41:22.334666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 04:41:22.334760 ==
4390 04:41:22.341528 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4391 04:41:22.344743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4392 04:41:22.349168 [CA 0] Center 35 (5~66) winsize 62
4393 04:41:22.352491 [CA 1] Center 36 (6~66) winsize 61
4394 04:41:22.355867 [CA 2] Center 34 (4~65) winsize 62
4395 04:41:22.358842 [CA 3] Center 34 (3~65) winsize 63
4396 04:41:22.362485 [CA 4] Center 34 (4~65) winsize 62
4397 04:41:22.365618 [CA 5] Center 33 (3~64) winsize 62
4398 04:41:22.365711
4399 04:41:22.369262 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4400 04:41:22.369369
4401 04:41:22.372311 [CATrainingPosCal] consider 1 rank data
4402 04:41:22.375839 u2DelayCellTimex100 = 270/100 ps
4403 04:41:22.378934 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4404 04:41:22.382380 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4405 04:41:22.388841 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4406 04:41:22.392321 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4407 04:41:22.395653 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4408 04:41:22.398816 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4409 04:41:22.398936
4410 04:41:22.402265 CA PerBit enable=1, Macro0, CA PI delay=33
4411 04:41:22.402378
4412 04:41:22.405630 [CBTSetCACLKResult] CA Dly = 33
4413 04:41:22.405742 CS Dly: 5 (0~36)
4414 04:41:22.408805 ==
4415 04:41:22.412072 Dram Type= 6, Freq= 0, CH_1, rank 1
4416 04:41:22.415224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 04:41:22.415334 ==
4418 04:41:22.418590 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4419 04:41:22.425301 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4420 04:41:22.429268 [CA 0] Center 36 (6~66) winsize 61
4421 04:41:22.432507 [CA 1] Center 36 (6~66) winsize 61
4422 04:41:22.435994 [CA 2] Center 34 (4~65) winsize 62
4423 04:41:22.439183 [CA 3] Center 34 (3~65) winsize 63
4424 04:41:22.442589 [CA 4] Center 34 (4~65) winsize 62
4425 04:41:22.445789 [CA 5] Center 33 (3~64) winsize 62
4426 04:41:22.445900
4427 04:41:22.449185 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4428 04:41:22.449293
4429 04:41:22.452558 [CATrainingPosCal] consider 2 rank data
4430 04:41:22.455639 u2DelayCellTimex100 = 270/100 ps
4431 04:41:22.458810 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4432 04:41:22.465514 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4433 04:41:22.468875 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4434 04:41:22.472270 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4435 04:41:22.475474 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4436 04:41:22.479159 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4437 04:41:22.479278
4438 04:41:22.482164 CA PerBit enable=1, Macro0, CA PI delay=33
4439 04:41:22.482272
4440 04:41:22.485344 [CBTSetCACLKResult] CA Dly = 33
4441 04:41:22.485456 CS Dly: 5 (0~37)
4442 04:41:22.489005
4443 04:41:22.492121 ----->DramcWriteLeveling(PI) begin...
4444 04:41:22.492233 ==
4445 04:41:22.495379 Dram Type= 6, Freq= 0, CH_1, rank 0
4446 04:41:22.498757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4447 04:41:22.498869 ==
4448 04:41:22.502073 Write leveling (Byte 0): 30 => 30
4449 04:41:22.505280 Write leveling (Byte 1): 30 => 30
4450 04:41:22.508829 DramcWriteLeveling(PI) end<-----
4451 04:41:22.508940
4452 04:41:22.509036 ==
4453 04:41:22.511899 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 04:41:22.515487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 04:41:22.515602 ==
4456 04:41:22.518617 [Gating] SW mode calibration
4457 04:41:22.525188 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4458 04:41:22.531869 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4459 04:41:22.535436 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4460 04:41:22.538467 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4461 04:41:22.545199 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4462 04:41:22.548485 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
4463 04:41:22.551927 0 9 16 | B1->B0 | 2525 2525 | 0 1 | (0 0) (1 0)
4464 04:41:22.558360 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 04:41:22.561591 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 04:41:22.565041 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 04:41:22.571775 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 04:41:22.575194 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 04:41:22.578474 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 04:41:22.584765 0 10 12 | B1->B0 | 3030 2f2f | 0 1 | (0 0) (0 0)
4471 04:41:22.588469 0 10 16 | B1->B0 | 4444 3d3d | 0 0 | (0 0) (0 0)
4472 04:41:22.591708 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 04:41:22.598040 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 04:41:22.601428 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 04:41:22.604538 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 04:41:22.608169 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 04:41:22.614527 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 04:41:22.617927 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4479 04:41:22.621077 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 04:41:22.627883 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 04:41:22.631084 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 04:41:22.634465 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 04:41:22.640929 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 04:41:22.644507 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 04:41:22.647654 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 04:41:22.654318 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 04:41:22.657576 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 04:41:22.661130 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 04:41:22.667333 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 04:41:22.670830 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 04:41:22.674075 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 04:41:22.680538 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 04:41:22.683800 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 04:41:22.687406 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 04:41:22.694084 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 04:41:22.697133 Total UI for P1: 0, mck2ui 16
4497 04:41:22.700376 best dqsien dly found for B0: ( 0, 13, 14)
4498 04:41:22.703929 Total UI for P1: 0, mck2ui 16
4499 04:41:22.707151 best dqsien dly found for B1: ( 0, 13, 14)
4500 04:41:22.710336 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4501 04:41:22.713795 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4502 04:41:22.713914
4503 04:41:22.717205 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4504 04:41:22.720524 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4505 04:41:22.723859 [Gating] SW calibration Done
4506 04:41:22.723971 ==
4507 04:41:22.726885 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 04:41:22.730202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 04:41:22.730342 ==
4510 04:41:22.733924 RX Vref Scan: 0
4511 04:41:22.734036
4512 04:41:22.737051 RX Vref 0 -> 0, step: 1
4513 04:41:22.737157
4514 04:41:22.737252 RX Delay -230 -> 252, step: 16
4515 04:41:22.743594 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4516 04:41:22.746740 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4517 04:41:22.750186 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4518 04:41:22.753585 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4519 04:41:22.760140 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4520 04:41:22.763423 iDelay=218, Bit 5, Center 41 (-134 ~ 217) 352
4521 04:41:22.766628 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4522 04:41:22.770228 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4523 04:41:22.773383 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4524 04:41:22.780139 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4525 04:41:22.783553 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4526 04:41:22.786668 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4527 04:41:22.790135 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4528 04:41:22.796487 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4529 04:41:22.800016 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4530 04:41:22.803106 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4531 04:41:22.803230 ==
4532 04:41:22.806609 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 04:41:22.813217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 04:41:22.813345 ==
4535 04:41:22.813442 DQS Delay:
4536 04:41:22.813577 DQS0 = 0, DQS1 = 0
4537 04:41:22.816555 DQM Delay:
4538 04:41:22.816663 DQM0 = 37, DQM1 = 30
4539 04:41:22.819759 DQ Delay:
4540 04:41:22.823056 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4541 04:41:22.826288 DQ4 =33, DQ5 =41, DQ6 =49, DQ7 =33
4542 04:41:22.826399 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4543 04:41:22.833226 DQ12 =41, DQ13 =41, DQ14 =33, DQ15 =33
4544 04:41:22.833340
4545 04:41:22.833437
4546 04:41:22.833538 ==
4547 04:41:22.836269 Dram Type= 6, Freq= 0, CH_1, rank 0
4548 04:41:22.839608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4549 04:41:22.839721 ==
4550 04:41:22.839818
4551 04:41:22.839911
4552 04:41:22.842930 TX Vref Scan disable
4553 04:41:22.843040 == TX Byte 0 ==
4554 04:41:22.849372 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4555 04:41:22.853038 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4556 04:41:22.853150 == TX Byte 1 ==
4557 04:41:22.859711 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4558 04:41:22.862827 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4559 04:41:22.862940 ==
4560 04:41:22.866229 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 04:41:22.869385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 04:41:22.869501 ==
4563 04:41:22.869599
4564 04:41:22.869691
4565 04:41:22.872643 TX Vref Scan disable
4566 04:41:22.876266 == TX Byte 0 ==
4567 04:41:22.879539 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4568 04:41:22.885829 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4569 04:41:22.885943 == TX Byte 1 ==
4570 04:41:22.889350 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4571 04:41:22.895801 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4572 04:41:22.895915
4573 04:41:22.896011 [DATLAT]
4574 04:41:22.896105 Freq=600, CH1 RK0
4575 04:41:22.896198
4576 04:41:22.899030 DATLAT Default: 0x9
4577 04:41:22.899139 0, 0xFFFF, sum = 0
4578 04:41:22.902559 1, 0xFFFF, sum = 0
4579 04:41:22.905834 2, 0xFFFF, sum = 0
4580 04:41:22.905945 3, 0xFFFF, sum = 0
4581 04:41:22.909052 4, 0xFFFF, sum = 0
4582 04:41:22.909164 5, 0xFFFF, sum = 0
4583 04:41:22.912541 6, 0xFFFF, sum = 0
4584 04:41:22.912651 7, 0xFFFF, sum = 0
4585 04:41:22.915996 8, 0x0, sum = 1
4586 04:41:22.916107 9, 0x0, sum = 2
4587 04:41:22.916206 10, 0x0, sum = 3
4588 04:41:22.918931 11, 0x0, sum = 4
4589 04:41:22.919042 best_step = 9
4590 04:41:22.919137
4591 04:41:22.919229 ==
4592 04:41:22.922488 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 04:41:22.929105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 04:41:22.929221 ==
4595 04:41:22.929318 RX Vref Scan: 1
4596 04:41:22.929412
4597 04:41:22.932116 RX Vref 0 -> 0, step: 1
4598 04:41:22.932226
4599 04:41:22.935786 RX Delay -195 -> 252, step: 8
4600 04:41:22.935897
4601 04:41:22.938954 Set Vref, RX VrefLevel [Byte0]: 54
4602 04:41:22.942072 [Byte1]: 53
4603 04:41:22.942182
4604 04:41:22.945457 Final RX Vref Byte 0 = 54 to rank0
4605 04:41:22.948803 Final RX Vref Byte 1 = 53 to rank0
4606 04:41:22.952135 Final RX Vref Byte 0 = 54 to rank1
4607 04:41:22.955353 Final RX Vref Byte 1 = 53 to rank1==
4608 04:41:22.958846 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 04:41:22.961904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 04:41:22.962017 ==
4611 04:41:22.965365 DQS Delay:
4612 04:41:22.965481 DQS0 = 0, DQS1 = 0
4613 04:41:22.968679 DQM Delay:
4614 04:41:22.968788 DQM0 = 37, DQM1 = 27
4615 04:41:22.968884 DQ Delay:
4616 04:41:22.971949 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4617 04:41:22.975485 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =36
4618 04:41:22.978658 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4619 04:41:22.982172 DQ12 =36, DQ13 =36, DQ14 =32, DQ15 =36
4620 04:41:22.982284
4621 04:41:22.982379
4622 04:41:22.991853 [DQSOSCAuto] RK0, (LSB)MR18= 0x2431, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4623 04:41:22.995054 CH1 RK0: MR19=808, MR18=2431
4624 04:41:23.001796 CH1_RK0: MR19=0x808, MR18=0x2431, DQSOSC=400, MR23=63, INC=163, DEC=109
4625 04:41:23.001915
4626 04:41:23.005049 ----->DramcWriteLeveling(PI) begin...
4627 04:41:23.005162 ==
4628 04:41:23.008348 Dram Type= 6, Freq= 0, CH_1, rank 1
4629 04:41:23.011925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 04:41:23.012038 ==
4631 04:41:23.015082 Write leveling (Byte 0): 31 => 31
4632 04:41:23.018416 Write leveling (Byte 1): 31 => 31
4633 04:41:23.021573 DramcWriteLeveling(PI) end<-----
4634 04:41:23.021685
4635 04:41:23.021781 ==
4636 04:41:23.025013 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 04:41:23.028285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 04:41:23.028399 ==
4639 04:41:23.031834 [Gating] SW mode calibration
4640 04:41:23.038218 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4641 04:41:23.045134 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4642 04:41:23.048440 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4643 04:41:23.051878 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4644 04:41:23.058295 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4645 04:41:23.061664 0 9 12 | B1->B0 | 3232 2a2a | 1 0 | (1 0) (0 0)
4646 04:41:23.065317 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4647 04:41:23.071478 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 04:41:23.075110 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 04:41:23.077960 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 04:41:23.084759 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 04:41:23.088112 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 04:41:23.091281 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
4653 04:41:23.098143 0 10 12 | B1->B0 | 3131 4343 | 0 1 | (0 0) (0 0)
4654 04:41:23.101377 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4655 04:41:23.104569 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 04:41:23.111301 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 04:41:23.114490 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 04:41:23.118066 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 04:41:23.124717 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 04:41:23.128098 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 04:41:23.131338 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 04:41:23.134863 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4663 04:41:23.141200 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 04:41:23.144497 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 04:41:23.148017 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 04:41:23.154573 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 04:41:23.157816 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 04:41:23.161156 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 04:41:23.167784 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 04:41:23.170796 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 04:41:23.174127 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 04:41:23.181222 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 04:41:23.184122 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 04:41:23.187652 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 04:41:23.194310 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 04:41:23.197320 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 04:41:23.200911 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 04:41:23.204281 Total UI for P1: 0, mck2ui 16
4679 04:41:23.207522 best dqsien dly found for B0: ( 0, 13, 10)
4680 04:41:23.210732 Total UI for P1: 0, mck2ui 16
4681 04:41:23.214274 best dqsien dly found for B1: ( 0, 13, 10)
4682 04:41:23.217416 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4683 04:41:23.223974 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4684 04:41:23.224240
4685 04:41:23.227538 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4686 04:41:23.230543 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4687 04:41:23.233625 [Gating] SW calibration Done
4688 04:41:23.233781 ==
4689 04:41:23.237188 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 04:41:23.240208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 04:41:23.240352 ==
4692 04:41:23.243418 RX Vref Scan: 0
4693 04:41:23.243548
4694 04:41:23.243649 RX Vref 0 -> 0, step: 1
4695 04:41:23.243742
4696 04:41:23.246868 RX Delay -230 -> 252, step: 16
4697 04:41:23.250119 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4698 04:41:23.256721 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4699 04:41:23.260113 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4700 04:41:23.263505 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4701 04:41:23.266673 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4702 04:41:23.273430 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4703 04:41:23.276732 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4704 04:41:23.279780 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4705 04:41:23.283072 iDelay=218, Bit 8, Center 9 (-166 ~ 185) 352
4706 04:41:23.286734 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4707 04:41:23.293118 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4708 04:41:23.296682 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4709 04:41:23.299815 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4710 04:41:23.303114 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4711 04:41:23.309689 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4712 04:41:23.313170 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4713 04:41:23.313285 ==
4714 04:41:23.316383 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 04:41:23.319643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 04:41:23.319736 ==
4717 04:41:23.322855 DQS Delay:
4718 04:41:23.322938 DQS0 = 0, DQS1 = 0
4719 04:41:23.326394 DQM Delay:
4720 04:41:23.326476 DQM0 = 35, DQM1 = 29
4721 04:41:23.326541 DQ Delay:
4722 04:41:23.329635 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4723 04:41:23.332797 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4724 04:41:23.336037 DQ8 =9, DQ9 =17, DQ10 =33, DQ11 =25
4725 04:41:23.339648 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =33
4726 04:41:23.339731
4727 04:41:23.339796
4728 04:41:23.339857 ==
4729 04:41:23.342889 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 04:41:23.349514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 04:41:23.349634 ==
4732 04:41:23.349731
4733 04:41:23.349823
4734 04:41:23.349912 TX Vref Scan disable
4735 04:41:23.353434 == TX Byte 0 ==
4736 04:41:23.356561 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4737 04:41:23.363262 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4738 04:41:23.363395 == TX Byte 1 ==
4739 04:41:23.366455 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4740 04:41:23.373288 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4741 04:41:23.373410 ==
4742 04:41:23.376659 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 04:41:23.379877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 04:41:23.379992 ==
4745 04:41:23.380088
4746 04:41:23.380180
4747 04:41:23.383040 TX Vref Scan disable
4748 04:41:23.383156 == TX Byte 0 ==
4749 04:41:23.389902 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4750 04:41:23.392914 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4751 04:41:23.396554 == TX Byte 1 ==
4752 04:41:23.399850 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4753 04:41:23.403260 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4754 04:41:23.403374
4755 04:41:23.403466 [DATLAT]
4756 04:41:23.406342 Freq=600, CH1 RK1
4757 04:41:23.406445
4758 04:41:23.406533 DATLAT Default: 0x9
4759 04:41:23.409468 0, 0xFFFF, sum = 0
4760 04:41:23.412988 1, 0xFFFF, sum = 0
4761 04:41:23.413097 2, 0xFFFF, sum = 0
4762 04:41:23.416271 3, 0xFFFF, sum = 0
4763 04:41:23.416393 4, 0xFFFF, sum = 0
4764 04:41:23.419425 5, 0xFFFF, sum = 0
4765 04:41:23.419533 6, 0xFFFF, sum = 0
4766 04:41:23.423010 7, 0xFFFF, sum = 0
4767 04:41:23.423096 8, 0x0, sum = 1
4768 04:41:23.426091 9, 0x0, sum = 2
4769 04:41:23.426175 10, 0x0, sum = 3
4770 04:41:23.426245 11, 0x0, sum = 4
4771 04:41:23.429320 best_step = 9
4772 04:41:23.429429
4773 04:41:23.429535 ==
4774 04:41:23.432529 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 04:41:23.436259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 04:41:23.436381 ==
4777 04:41:23.439413 RX Vref Scan: 0
4778 04:41:23.439495
4779 04:41:23.442439 RX Vref 0 -> 0, step: 1
4780 04:41:23.442521
4781 04:41:23.442613 RX Delay -211 -> 252, step: 8
4782 04:41:23.450439 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4783 04:41:23.453726 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4784 04:41:23.456889 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4785 04:41:23.460090 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4786 04:41:23.467157 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4787 04:41:23.470091 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4788 04:41:23.473465 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4789 04:41:23.476742 iDelay=205, Bit 7, Center 28 (-131 ~ 188) 320
4790 04:41:23.483395 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4791 04:41:23.486568 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4792 04:41:23.489926 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4793 04:41:23.493468 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4794 04:41:23.496878 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4795 04:41:23.503336 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4796 04:41:23.506747 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4797 04:41:23.509823 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4798 04:41:23.509960 ==
4799 04:41:23.513237 Dram Type= 6, Freq= 0, CH_1, rank 1
4800 04:41:23.519931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4801 04:41:23.520040 ==
4802 04:41:23.520134 DQS Delay:
4803 04:41:23.520226 DQS0 = 0, DQS1 = 0
4804 04:41:23.523240 DQM Delay:
4805 04:41:23.523344 DQM0 = 35, DQM1 = 30
4806 04:41:23.526505 DQ Delay:
4807 04:41:23.529774 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4808 04:41:23.533113 DQ4 =32, DQ5 =48, DQ6 =44, DQ7 =28
4809 04:41:23.536323 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =28
4810 04:41:23.539823 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4811 04:41:23.539928
4812 04:41:23.540019
4813 04:41:23.546335 [DQSOSCAuto] RK1, (LSB)MR18= 0x3857, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4814 04:41:23.549582 CH1 RK1: MR19=808, MR18=3857
4815 04:41:23.556201 CH1_RK1: MR19=0x808, MR18=0x3857, DQSOSC=393, MR23=63, INC=169, DEC=113
4816 04:41:23.559570 [RxdqsGatingPostProcess] freq 600
4817 04:41:23.562863 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4818 04:41:23.566390 Pre-setting of DQS Precalculation
4819 04:41:23.572905 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4820 04:41:23.579599 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4821 04:41:23.586340 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4822 04:41:23.586461
4823 04:41:23.586554
4824 04:41:23.589607 [Calibration Summary] 1200 Mbps
4825 04:41:23.589730 CH 0, Rank 0
4826 04:41:23.592724 SW Impedance : PASS
4827 04:41:23.595902 DUTY Scan : NO K
4828 04:41:23.596009 ZQ Calibration : PASS
4829 04:41:23.599495 Jitter Meter : NO K
4830 04:41:23.602500 CBT Training : PASS
4831 04:41:23.602607 Write leveling : PASS
4832 04:41:23.606146 RX DQS gating : PASS
4833 04:41:23.609397 RX DQ/DQS(RDDQC) : PASS
4834 04:41:23.609536 TX DQ/DQS : PASS
4835 04:41:23.612633 RX DATLAT : PASS
4836 04:41:23.616110 RX DQ/DQS(Engine): PASS
4837 04:41:23.616215 TX OE : NO K
4838 04:41:23.616306 All Pass.
4839 04:41:23.619249
4840 04:41:23.619381 CH 0, Rank 1
4841 04:41:23.622632 SW Impedance : PASS
4842 04:41:23.622738 DUTY Scan : NO K
4843 04:41:23.625724 ZQ Calibration : PASS
4844 04:41:23.629137 Jitter Meter : NO K
4845 04:41:23.629216 CBT Training : PASS
4846 04:41:23.632304 Write leveling : PASS
4847 04:41:23.632390 RX DQS gating : PASS
4848 04:41:23.635936 RX DQ/DQS(RDDQC) : PASS
4849 04:41:23.639060 TX DQ/DQS : PASS
4850 04:41:23.639136 RX DATLAT : PASS
4851 04:41:23.642346 RX DQ/DQS(Engine): PASS
4852 04:41:23.645932 TX OE : NO K
4853 04:41:23.646013 All Pass.
4854 04:41:23.646077
4855 04:41:23.646136 CH 1, Rank 0
4856 04:41:23.649193 SW Impedance : PASS
4857 04:41:23.652222 DUTY Scan : NO K
4858 04:41:23.652313 ZQ Calibration : PASS
4859 04:41:23.655665 Jitter Meter : NO K
4860 04:41:23.659254 CBT Training : PASS
4861 04:41:23.659383 Write leveling : PASS
4862 04:41:23.662345 RX DQS gating : PASS
4863 04:41:23.665768 RX DQ/DQS(RDDQC) : PASS
4864 04:41:23.665879 TX DQ/DQS : PASS
4865 04:41:23.668993 RX DATLAT : PASS
4866 04:41:23.672223 RX DQ/DQS(Engine): PASS
4867 04:41:23.672329 TX OE : NO K
4868 04:41:23.672422 All Pass.
4869 04:41:23.675773
4870 04:41:23.675886 CH 1, Rank 1
4871 04:41:23.678974 SW Impedance : PASS
4872 04:41:23.679076 DUTY Scan : NO K
4873 04:41:23.682233 ZQ Calibration : PASS
4874 04:41:23.682313 Jitter Meter : NO K
4875 04:41:23.685666 CBT Training : PASS
4876 04:41:23.688850 Write leveling : PASS
4877 04:41:23.688942 RX DQS gating : PASS
4878 04:41:23.692326 RX DQ/DQS(RDDQC) : PASS
4879 04:41:23.695624 TX DQ/DQS : PASS
4880 04:41:23.695730 RX DATLAT : PASS
4881 04:41:23.698741 RX DQ/DQS(Engine): PASS
4882 04:41:23.702381 TX OE : NO K
4883 04:41:23.702471 All Pass.
4884 04:41:23.702538
4885 04:41:23.705496 DramC Write-DBI off
4886 04:41:23.705611 PER_BANK_REFRESH: Hybrid Mode
4887 04:41:23.709250 TX_TRACKING: ON
4888 04:41:23.715534 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4889 04:41:23.722152 [FAST_K] Save calibration result to emmc
4890 04:41:23.725395 dramc_set_vcore_voltage set vcore to 662500
4891 04:41:23.725506 Read voltage for 933, 3
4892 04:41:23.728813 Vio18 = 0
4893 04:41:23.728923 Vcore = 662500
4894 04:41:23.729024 Vdram = 0
4895 04:41:23.732281 Vddq = 0
4896 04:41:23.732385 Vmddr = 0
4897 04:41:23.735416 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4898 04:41:23.742217 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4899 04:41:23.745732 MEM_TYPE=3, freq_sel=17
4900 04:41:23.748680 sv_algorithm_assistance_LP4_1600
4901 04:41:23.752047 ============ PULL DRAM RESETB DOWN ============
4902 04:41:23.755433 ========== PULL DRAM RESETB DOWN end =========
4903 04:41:23.758893 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4904 04:41:23.761978 ===================================
4905 04:41:23.765382 LPDDR4 DRAM CONFIGURATION
4906 04:41:23.768510 ===================================
4907 04:41:23.772077 EX_ROW_EN[0] = 0x0
4908 04:41:23.772189 EX_ROW_EN[1] = 0x0
4909 04:41:23.775201 LP4Y_EN = 0x0
4910 04:41:23.775327 WORK_FSP = 0x0
4911 04:41:23.778749 WL = 0x3
4912 04:41:23.778856 RL = 0x3
4913 04:41:23.781998 BL = 0x2
4914 04:41:23.782078 RPST = 0x0
4915 04:41:23.785224 RD_PRE = 0x0
4916 04:41:23.785325 WR_PRE = 0x1
4917 04:41:23.788754 WR_PST = 0x0
4918 04:41:23.792218 DBI_WR = 0x0
4919 04:41:23.792322 DBI_RD = 0x0
4920 04:41:23.795274 OTF = 0x1
4921 04:41:23.798621 ===================================
4922 04:41:23.802000 ===================================
4923 04:41:23.802107 ANA top config
4924 04:41:23.805389 ===================================
4925 04:41:23.808600 DLL_ASYNC_EN = 0
4926 04:41:23.808685 ALL_SLAVE_EN = 1
4927 04:41:23.811876 NEW_RANK_MODE = 1
4928 04:41:23.815103 DLL_IDLE_MODE = 1
4929 04:41:23.818339 LP45_APHY_COMB_EN = 1
4930 04:41:23.821827 TX_ODT_DIS = 1
4931 04:41:23.821905 NEW_8X_MODE = 1
4932 04:41:23.824919 ===================================
4933 04:41:23.828455 ===================================
4934 04:41:23.831577 data_rate = 1866
4935 04:41:23.835188 CKR = 1
4936 04:41:23.838348 DQ_P2S_RATIO = 8
4937 04:41:23.841495 ===================================
4938 04:41:23.845179 CA_P2S_RATIO = 8
4939 04:41:23.848316 DQ_CA_OPEN = 0
4940 04:41:23.848402 DQ_SEMI_OPEN = 0
4941 04:41:23.851562 CA_SEMI_OPEN = 0
4942 04:41:23.854980 CA_FULL_RATE = 0
4943 04:41:23.858282 DQ_CKDIV4_EN = 1
4944 04:41:23.861727 CA_CKDIV4_EN = 1
4945 04:41:23.864812 CA_PREDIV_EN = 0
4946 04:41:23.864895 PH8_DLY = 0
4947 04:41:23.868159 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4948 04:41:23.871443 DQ_AAMCK_DIV = 4
4949 04:41:23.874811 CA_AAMCK_DIV = 4
4950 04:41:23.878397 CA_ADMCK_DIV = 4
4951 04:41:23.881454 DQ_TRACK_CA_EN = 0
4952 04:41:23.881560 CA_PICK = 933
4953 04:41:23.884756 CA_MCKIO = 933
4954 04:41:23.887985 MCKIO_SEMI = 0
4955 04:41:23.891557 PLL_FREQ = 3732
4956 04:41:23.894862 DQ_UI_PI_RATIO = 32
4957 04:41:23.898291 CA_UI_PI_RATIO = 0
4958 04:41:23.901602 ===================================
4959 04:41:23.904717 ===================================
4960 04:41:23.904799 memory_type:LPDDR4
4961 04:41:23.908089 GP_NUM : 10
4962 04:41:23.911129 SRAM_EN : 1
4963 04:41:23.911210 MD32_EN : 0
4964 04:41:23.914707 ===================================
4965 04:41:23.917782 [ANA_INIT] >>>>>>>>>>>>>>
4966 04:41:23.921225 <<<<<< [CONFIGURE PHASE]: ANA_TX
4967 04:41:23.924509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4968 04:41:23.927774 ===================================
4969 04:41:23.931031 data_rate = 1866,PCW = 0X8f00
4970 04:41:23.934481 ===================================
4971 04:41:23.937909 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4972 04:41:23.941128 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4973 04:41:23.947588 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4974 04:41:23.951237 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4975 04:41:23.957720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4976 04:41:23.960961 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4977 04:41:23.961113 [ANA_INIT] flow start
4978 04:41:23.964290 [ANA_INIT] PLL >>>>>>>>
4979 04:41:23.967645 [ANA_INIT] PLL <<<<<<<<
4980 04:41:23.967748 [ANA_INIT] MIDPI >>>>>>>>
4981 04:41:23.970977 [ANA_INIT] MIDPI <<<<<<<<
4982 04:41:23.974353 [ANA_INIT] DLL >>>>>>>>
4983 04:41:23.974457 [ANA_INIT] flow end
4984 04:41:23.980856 ============ LP4 DIFF to SE enter ============
4985 04:41:23.984334 ============ LP4 DIFF to SE exit ============
4986 04:41:23.984428 [ANA_INIT] <<<<<<<<<<<<<
4987 04:41:23.987501 [Flow] Enable top DCM control >>>>>
4988 04:41:23.990785 [Flow] Enable top DCM control <<<<<
4989 04:41:23.994249 Enable DLL master slave shuffle
4990 04:41:24.000767 ==============================================================
4991 04:41:24.004188 Gating Mode config
4992 04:41:24.007226 ==============================================================
4993 04:41:24.010758 Config description:
4994 04:41:24.020819 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4995 04:41:24.027193 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4996 04:41:24.030670 SELPH_MODE 0: By rank 1: By Phase
4997 04:41:24.037173 ==============================================================
4998 04:41:24.040397 GAT_TRACK_EN = 1
4999 04:41:24.043706 RX_GATING_MODE = 2
5000 04:41:24.047075 RX_GATING_TRACK_MODE = 2
5001 04:41:24.047158 SELPH_MODE = 1
5002 04:41:24.050524 PICG_EARLY_EN = 1
5003 04:41:24.053821 VALID_LAT_VALUE = 1
5004 04:41:24.060464 ==============================================================
5005 04:41:24.063745 Enter into Gating configuration >>>>
5006 04:41:24.067004 Exit from Gating configuration <<<<
5007 04:41:24.070440 Enter into DVFS_PRE_config >>>>>
5008 04:41:24.080107 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5009 04:41:24.083463 Exit from DVFS_PRE_config <<<<<
5010 04:41:24.086734 Enter into PICG configuration >>>>
5011 04:41:24.090072 Exit from PICG configuration <<<<
5012 04:41:24.093471 [RX_INPUT] configuration >>>>>
5013 04:41:24.097129 [RX_INPUT] configuration <<<<<
5014 04:41:24.100304 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5015 04:41:24.106985 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5016 04:41:24.113412 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5017 04:41:24.120312 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5018 04:41:24.123450 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5019 04:41:24.130126 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5020 04:41:24.136485 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5021 04:41:24.140122 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5022 04:41:24.143312 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5023 04:41:24.146495 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5024 04:41:24.149850 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5025 04:41:24.156524 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5026 04:41:24.159682 ===================================
5027 04:41:24.163189 LPDDR4 DRAM CONFIGURATION
5028 04:41:24.166658 ===================================
5029 04:41:24.166742 EX_ROW_EN[0] = 0x0
5030 04:41:24.169709 EX_ROW_EN[1] = 0x0
5031 04:41:24.169792 LP4Y_EN = 0x0
5032 04:41:24.173122 WORK_FSP = 0x0
5033 04:41:24.173204 WL = 0x3
5034 04:41:24.176357 RL = 0x3
5035 04:41:24.176468 BL = 0x2
5036 04:41:24.179734 RPST = 0x0
5037 04:41:24.179864 RD_PRE = 0x0
5038 04:41:24.183117 WR_PRE = 0x1
5039 04:41:24.183220 WR_PST = 0x0
5040 04:41:24.186449 DBI_WR = 0x0
5041 04:41:24.186553 DBI_RD = 0x0
5042 04:41:24.189865 OTF = 0x1
5043 04:41:24.193163 ===================================
5044 04:41:24.196344 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5045 04:41:24.199814 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5046 04:41:24.206240 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5047 04:41:24.209700 ===================================
5048 04:41:24.209784 LPDDR4 DRAM CONFIGURATION
5049 04:41:24.212877 ===================================
5050 04:41:24.216488 EX_ROW_EN[0] = 0x10
5051 04:41:24.219565 EX_ROW_EN[1] = 0x0
5052 04:41:24.219648 LP4Y_EN = 0x0
5053 04:41:24.223172 WORK_FSP = 0x0
5054 04:41:24.223254 WL = 0x3
5055 04:41:24.226390 RL = 0x3
5056 04:41:24.226471 BL = 0x2
5057 04:41:24.229604 RPST = 0x0
5058 04:41:24.229686 RD_PRE = 0x0
5059 04:41:24.232801 WR_PRE = 0x1
5060 04:41:24.232883 WR_PST = 0x0
5061 04:41:24.236473 DBI_WR = 0x0
5062 04:41:24.236555 DBI_RD = 0x0
5063 04:41:24.239637 OTF = 0x1
5064 04:41:24.242738 ===================================
5065 04:41:24.249546 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5066 04:41:24.253021 nWR fixed to 30
5067 04:41:24.253104 [ModeRegInit_LP4] CH0 RK0
5068 04:41:24.256364 [ModeRegInit_LP4] CH0 RK1
5069 04:41:24.259769 [ModeRegInit_LP4] CH1 RK0
5070 04:41:24.263059 [ModeRegInit_LP4] CH1 RK1
5071 04:41:24.263163 match AC timing 9
5072 04:41:24.269569 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5073 04:41:24.272723 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5074 04:41:24.276265 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5075 04:41:24.283053 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5076 04:41:24.286174 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5077 04:41:24.286249 ==
5078 04:41:24.289401 Dram Type= 6, Freq= 0, CH_0, rank 0
5079 04:41:24.292592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 04:41:24.292688 ==
5081 04:41:24.299387 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5082 04:41:24.305770 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5083 04:41:24.309171 [CA 0] Center 38 (7~69) winsize 63
5084 04:41:24.312477 [CA 1] Center 38 (8~69) winsize 62
5085 04:41:24.315853 [CA 2] Center 35 (5~66) winsize 62
5086 04:41:24.319209 [CA 3] Center 34 (4~65) winsize 62
5087 04:41:24.322449 [CA 4] Center 34 (4~65) winsize 62
5088 04:41:24.325817 [CA 5] Center 34 (4~64) winsize 61
5089 04:41:24.325916
5090 04:41:24.329230 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5091 04:41:24.329304
5092 04:41:24.332275 [CATrainingPosCal] consider 1 rank data
5093 04:41:24.335497 u2DelayCellTimex100 = 270/100 ps
5094 04:41:24.338760 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5095 04:41:24.342302 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5096 04:41:24.345406 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5097 04:41:24.349179 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5098 04:41:24.352570 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5099 04:41:24.355628 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5100 04:41:24.355750
5101 04:41:24.362374 CA PerBit enable=1, Macro0, CA PI delay=34
5102 04:41:24.362473
5103 04:41:24.365502 [CBTSetCACLKResult] CA Dly = 34
5104 04:41:24.365631 CS Dly: 7 (0~38)
5105 04:41:24.365733 ==
5106 04:41:24.368697 Dram Type= 6, Freq= 0, CH_0, rank 1
5107 04:41:24.372244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 04:41:24.372353 ==
5109 04:41:24.378684 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5110 04:41:24.385369 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5111 04:41:24.388654 [CA 0] Center 38 (8~69) winsize 62
5112 04:41:24.392192 [CA 1] Center 38 (8~69) winsize 62
5113 04:41:24.395294 [CA 2] Center 35 (5~66) winsize 62
5114 04:41:24.398796 [CA 3] Center 35 (4~66) winsize 63
5115 04:41:24.402195 [CA 4] Center 34 (4~65) winsize 62
5116 04:41:24.405432 [CA 5] Center 33 (3~64) winsize 62
5117 04:41:24.405561
5118 04:41:24.408541 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5119 04:41:24.408682
5120 04:41:24.411762 [CATrainingPosCal] consider 2 rank data
5121 04:41:24.415055 u2DelayCellTimex100 = 270/100 ps
5122 04:41:24.418591 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5123 04:41:24.422095 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5124 04:41:24.425356 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5125 04:41:24.428597 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5126 04:41:24.431990 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5127 04:41:24.438446 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5128 04:41:24.438787
5129 04:41:24.441843 CA PerBit enable=1, Macro0, CA PI delay=34
5130 04:41:24.442151
5131 04:41:24.445289 [CBTSetCACLKResult] CA Dly = 34
5132 04:41:24.445720 CS Dly: 7 (0~39)
5133 04:41:24.446089
5134 04:41:24.448531 ----->DramcWriteLeveling(PI) begin...
5135 04:41:24.448912 ==
5136 04:41:24.451908 Dram Type= 6, Freq= 0, CH_0, rank 0
5137 04:41:24.458484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5138 04:41:24.458912 ==
5139 04:41:24.461990 Write leveling (Byte 0): 31 => 31
5140 04:41:24.462403 Write leveling (Byte 1): 31 => 31
5141 04:41:24.465234 DramcWriteLeveling(PI) end<-----
5142 04:41:24.465756
5143 04:41:24.466177 ==
5144 04:41:24.468561 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 04:41:24.475067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 04:41:24.475598 ==
5147 04:41:24.478590 [Gating] SW mode calibration
5148 04:41:24.485010 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5149 04:41:24.488316 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5150 04:41:24.495041 0 14 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5151 04:41:24.498306 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5152 04:41:24.501663 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 04:41:24.508420 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 04:41:24.511566 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 04:41:24.515074 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 04:41:24.521689 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 04:41:24.524807 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5158 04:41:24.528118 0 15 0 | B1->B0 | 3333 2929 | 0 0 | (0 0) (1 1)
5159 04:41:24.534752 0 15 4 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
5160 04:41:24.538001 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 04:41:24.541471 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 04:41:24.544891 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 04:41:24.551570 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 04:41:24.554659 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 04:41:24.558052 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5166 04:41:24.564774 1 0 0 | B1->B0 | 2a2a 3e3e | 0 0 | (0 0) (0 0)
5167 04:41:24.568081 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5168 04:41:24.571464 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 04:41:24.577857 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 04:41:24.581113 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 04:41:24.584473 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 04:41:24.591937 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 04:41:24.594569 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 04:41:24.597695 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5175 04:41:24.604628 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5176 04:41:24.607761 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 04:41:24.611192 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 04:41:24.618032 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 04:41:24.621295 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 04:41:24.624347 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 04:41:24.631266 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 04:41:24.634621 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 04:41:24.637836 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 04:41:24.644397 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 04:41:24.647895 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 04:41:24.651177 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 04:41:24.657897 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 04:41:24.660993 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 04:41:24.664422 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 04:41:24.671204 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5191 04:41:24.674456 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5192 04:41:24.677806 Total UI for P1: 0, mck2ui 16
5193 04:41:24.680924 best dqsien dly found for B0: ( 1, 3, 0)
5194 04:41:24.684244 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 04:41:24.687676 Total UI for P1: 0, mck2ui 16
5196 04:41:24.690888 best dqsien dly found for B1: ( 1, 3, 4)
5197 04:41:24.694223 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5198 04:41:24.697535 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5199 04:41:24.697932
5200 04:41:24.701134 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5201 04:41:24.704319 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5202 04:41:24.707524 [Gating] SW calibration Done
5203 04:41:24.707912 ==
5204 04:41:24.711034 Dram Type= 6, Freq= 0, CH_0, rank 0
5205 04:41:24.717397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5206 04:41:24.717880 ==
5207 04:41:24.718231 RX Vref Scan: 0
5208 04:41:24.718567
5209 04:41:24.720645 RX Vref 0 -> 0, step: 1
5210 04:41:24.721062
5211 04:41:24.724008 RX Delay -80 -> 252, step: 8
5212 04:41:24.727318 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5213 04:41:24.730766 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5214 04:41:24.733900 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5215 04:41:24.737531 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5216 04:41:24.740624 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5217 04:41:24.747437 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5218 04:41:24.750578 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5219 04:41:24.754075 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5220 04:41:24.757538 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5221 04:41:24.760711 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5222 04:41:24.767232 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5223 04:41:24.770378 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5224 04:41:24.773933 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5225 04:41:24.777343 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5226 04:41:24.780393 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5227 04:41:24.787167 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5228 04:41:24.787621 ==
5229 04:41:24.790593 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 04:41:24.793852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 04:41:24.794236 ==
5232 04:41:24.794569 DQS Delay:
5233 04:41:24.797136 DQS0 = 0, DQS1 = 0
5234 04:41:24.797553 DQM Delay:
5235 04:41:24.800253 DQM0 = 95, DQM1 = 83
5236 04:41:24.800620 DQ Delay:
5237 04:41:24.803580 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5238 04:41:24.806816 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5239 04:41:24.810000 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5240 04:41:24.813229 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5241 04:41:24.813733
5242 04:41:24.814105
5243 04:41:24.814474 ==
5244 04:41:24.816495 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 04:41:24.820177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 04:41:24.823360 ==
5247 04:41:24.823803
5248 04:41:24.824168
5249 04:41:24.824499 TX Vref Scan disable
5250 04:41:24.826569 == TX Byte 0 ==
5251 04:41:24.830077 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5252 04:41:24.833333 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5253 04:41:24.836657 == TX Byte 1 ==
5254 04:41:24.840043 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5255 04:41:24.843289 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5256 04:41:24.846459 ==
5257 04:41:24.849926 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 04:41:24.853243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 04:41:24.853778 ==
5260 04:41:24.854146
5261 04:41:24.854542
5262 04:41:24.856300 TX Vref Scan disable
5263 04:41:24.856791 == TX Byte 0 ==
5264 04:41:24.863270 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5265 04:41:24.866291 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5266 04:41:24.866924 == TX Byte 1 ==
5267 04:41:24.873213 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5268 04:41:24.876463 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5269 04:41:24.876912
5270 04:41:24.877259 [DATLAT]
5271 04:41:24.879667 Freq=933, CH0 RK0
5272 04:41:24.880083
5273 04:41:24.880463 DATLAT Default: 0xd
5274 04:41:24.883173 0, 0xFFFF, sum = 0
5275 04:41:24.883616 1, 0xFFFF, sum = 0
5276 04:41:24.886664 2, 0xFFFF, sum = 0
5277 04:41:24.887197 3, 0xFFFF, sum = 0
5278 04:41:24.889798 4, 0xFFFF, sum = 0
5279 04:41:24.890239 5, 0xFFFF, sum = 0
5280 04:41:24.892878 6, 0xFFFF, sum = 0
5281 04:41:24.893337 7, 0xFFFF, sum = 0
5282 04:41:24.896605 8, 0xFFFF, sum = 0
5283 04:41:24.897195 9, 0xFFFF, sum = 0
5284 04:41:24.899594 10, 0x0, sum = 1
5285 04:41:24.900171 11, 0x0, sum = 2
5286 04:41:24.902990 12, 0x0, sum = 3
5287 04:41:24.903566 13, 0x0, sum = 4
5288 04:41:24.906100 best_step = 11
5289 04:41:24.906534
5290 04:41:24.906906 ==
5291 04:41:24.909894 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 04:41:24.912981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 04:41:24.913526 ==
5294 04:41:24.916134 RX Vref Scan: 1
5295 04:41:24.916679
5296 04:41:24.917035 RX Vref 0 -> 0, step: 1
5297 04:41:24.917371
5298 04:41:24.919614 RX Delay -69 -> 252, step: 4
5299 04:41:24.920046
5300 04:41:24.922950 Set Vref, RX VrefLevel [Byte0]: 62
5301 04:41:24.926216 [Byte1]: 46
5302 04:41:24.930281
5303 04:41:24.930718 Final RX Vref Byte 0 = 62 to rank0
5304 04:41:24.933649 Final RX Vref Byte 1 = 46 to rank0
5305 04:41:24.937197 Final RX Vref Byte 0 = 62 to rank1
5306 04:41:24.940420 Final RX Vref Byte 1 = 46 to rank1==
5307 04:41:24.943712 Dram Type= 6, Freq= 0, CH_0, rank 0
5308 04:41:24.950323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 04:41:24.950768 ==
5310 04:41:24.951158 DQS Delay:
5311 04:41:24.951503 DQS0 = 0, DQS1 = 0
5312 04:41:24.953596 DQM Delay:
5313 04:41:24.954162 DQM0 = 95, DQM1 = 82
5314 04:41:24.957006 DQ Delay:
5315 04:41:24.960196 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5316 04:41:24.963649 DQ4 =96, DQ5 =86, DQ6 =102, DQ7 =106
5317 04:41:24.967036 DQ8 =74, DQ9 =70, DQ10 =82, DQ11 =78
5318 04:41:24.970491 DQ12 =86, DQ13 =86, DQ14 =96, DQ15 =90
5319 04:41:24.970951
5320 04:41:24.971326
5321 04:41:24.976907 [DQSOSCAuto] RK0, (LSB)MR18= 0x1110, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5322 04:41:24.980034 CH0 RK0: MR19=505, MR18=1110
5323 04:41:24.986863 CH0_RK0: MR19=0x505, MR18=0x1110, DQSOSC=416, MR23=63, INC=62, DEC=41
5324 04:41:24.987298
5325 04:41:24.989870 ----->DramcWriteLeveling(PI) begin...
5326 04:41:24.990339 ==
5327 04:41:24.993562 Dram Type= 6, Freq= 0, CH_0, rank 1
5328 04:41:24.996550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 04:41:24.997036 ==
5330 04:41:24.999980 Write leveling (Byte 0): 32 => 32
5331 04:41:25.003484 Write leveling (Byte 1): 31 => 31
5332 04:41:25.006559 DramcWriteLeveling(PI) end<-----
5333 04:41:25.007073
5334 04:41:25.007574 ==
5335 04:41:25.009948 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 04:41:25.013426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 04:41:25.013989 ==
5338 04:41:25.016655 [Gating] SW mode calibration
5339 04:41:25.023197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5340 04:41:25.029697 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5341 04:41:25.032957 0 14 0 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
5342 04:41:25.039811 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 04:41:25.043087 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 04:41:25.046384 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 04:41:25.052613 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 04:41:25.056030 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 04:41:25.059179 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 04:41:25.066202 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
5349 04:41:25.069187 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
5350 04:41:25.072882 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 04:41:25.079278 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 04:41:25.082671 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 04:41:25.085985 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 04:41:25.092459 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 04:41:25.095818 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 04:41:25.098934 0 15 28 | B1->B0 | 2525 3737 | 1 0 | (0 0) (0 0)
5357 04:41:25.105867 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5358 04:41:25.109109 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 04:41:25.112213 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 04:41:25.118791 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 04:41:25.121917 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 04:41:25.125520 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 04:41:25.131903 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 04:41:25.135317 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5365 04:41:25.138758 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5366 04:41:25.145026 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 04:41:25.148367 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 04:41:25.151695 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 04:41:25.158581 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 04:41:25.161898 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 04:41:25.165099 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 04:41:25.171756 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 04:41:25.175109 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 04:41:25.178242 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 04:41:25.185087 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 04:41:25.188449 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 04:41:25.191785 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 04:41:25.198097 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 04:41:25.201591 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 04:41:25.205039 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5381 04:41:25.211498 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 04:41:25.211922 Total UI for P1: 0, mck2ui 16
5383 04:41:25.218009 best dqsien dly found for B0: ( 1, 2, 28)
5384 04:41:25.218433 Total UI for P1: 0, mck2ui 16
5385 04:41:25.221236 best dqsien dly found for B1: ( 1, 2, 30)
5386 04:41:25.224637 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5387 04:41:25.231247 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5388 04:41:25.231671
5389 04:41:25.234466 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5390 04:41:25.237983 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5391 04:41:25.240969 [Gating] SW calibration Done
5392 04:41:25.241469 ==
5393 04:41:25.244461 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 04:41:25.247490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 04:41:25.247572 ==
5396 04:41:25.250626 RX Vref Scan: 0
5397 04:41:25.250707
5398 04:41:25.250771 RX Vref 0 -> 0, step: 1
5399 04:41:25.250832
5400 04:41:25.253813 RX Delay -80 -> 252, step: 8
5401 04:41:25.257117 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5402 04:41:25.264143 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5403 04:41:25.267396 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5404 04:41:25.270642 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5405 04:41:25.273895 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5406 04:41:25.277322 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5407 04:41:25.280259 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5408 04:41:25.286979 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5409 04:41:25.290471 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5410 04:41:25.293668 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5411 04:41:25.296809 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5412 04:41:25.300138 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5413 04:41:25.306970 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5414 04:41:25.310336 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5415 04:41:25.313746 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5416 04:41:25.316580 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5417 04:41:25.316662 ==
5418 04:41:25.320317 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 04:41:25.326619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 04:41:25.326702 ==
5421 04:41:25.326769 DQS Delay:
5422 04:41:25.326831 DQS0 = 0, DQS1 = 0
5423 04:41:25.330143 DQM Delay:
5424 04:41:25.330225 DQM0 = 91, DQM1 = 81
5425 04:41:25.333425 DQ Delay:
5426 04:41:25.336619 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5427 04:41:25.340062 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5428 04:41:25.343210 DQ8 =71, DQ9 =63, DQ10 =87, DQ11 =71
5429 04:41:25.346212 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5430 04:41:25.346294
5431 04:41:25.346359
5432 04:41:25.346419 ==
5433 04:41:25.349601 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 04:41:25.352890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 04:41:25.352973 ==
5436 04:41:25.353038
5437 04:41:25.353098
5438 04:41:25.356503 TX Vref Scan disable
5439 04:41:25.356622 == TX Byte 0 ==
5440 04:41:25.363022 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5441 04:41:25.366299 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5442 04:41:25.366380 == TX Byte 1 ==
5443 04:41:25.372719 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5444 04:41:25.376035 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5445 04:41:25.376116 ==
5446 04:41:25.379209 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 04:41:25.382495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 04:41:25.385891 ==
5449 04:41:25.385973
5450 04:41:25.386037
5451 04:41:25.386096 TX Vref Scan disable
5452 04:41:25.389366 == TX Byte 0 ==
5453 04:41:25.392884 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5454 04:41:25.399393 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5455 04:41:25.399473 == TX Byte 1 ==
5456 04:41:25.402542 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5457 04:41:25.409242 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5458 04:41:25.409348
5459 04:41:25.409440 [DATLAT]
5460 04:41:25.409560 Freq=933, CH0 RK1
5461 04:41:25.409619
5462 04:41:25.412710 DATLAT Default: 0xb
5463 04:41:25.412790 0, 0xFFFF, sum = 0
5464 04:41:25.415855 1, 0xFFFF, sum = 0
5465 04:41:25.419381 2, 0xFFFF, sum = 0
5466 04:41:25.419463 3, 0xFFFF, sum = 0
5467 04:41:25.422572 4, 0xFFFF, sum = 0
5468 04:41:25.422654 5, 0xFFFF, sum = 0
5469 04:41:25.426128 6, 0xFFFF, sum = 0
5470 04:41:25.426211 7, 0xFFFF, sum = 0
5471 04:41:25.429331 8, 0xFFFF, sum = 0
5472 04:41:25.429442 9, 0xFFFF, sum = 0
5473 04:41:25.432512 10, 0x0, sum = 1
5474 04:41:25.432621 11, 0x0, sum = 2
5475 04:41:25.435809 12, 0x0, sum = 3
5476 04:41:25.435891 13, 0x0, sum = 4
5477 04:41:25.435956 best_step = 11
5478 04:41:25.436016
5479 04:41:25.439015 ==
5480 04:41:25.442746 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 04:41:25.445693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 04:41:25.445775 ==
5483 04:41:25.445839 RX Vref Scan: 0
5484 04:41:25.445899
5485 04:41:25.448843 RX Vref 0 -> 0, step: 1
5486 04:41:25.448924
5487 04:41:25.452260 RX Delay -77 -> 252, step: 4
5488 04:41:25.458954 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5489 04:41:25.462110 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5490 04:41:25.465543 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5491 04:41:25.468634 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5492 04:41:25.472215 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5493 04:41:25.475449 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5494 04:41:25.481833 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5495 04:41:25.485059 iDelay=199, Bit 7, Center 102 (7 ~ 198) 192
5496 04:41:25.488337 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5497 04:41:25.491744 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5498 04:41:25.495106 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5499 04:41:25.501812 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5500 04:41:25.505007 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5501 04:41:25.508269 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5502 04:41:25.511618 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5503 04:41:25.514750 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5504 04:41:25.514909 ==
5505 04:41:25.518050 Dram Type= 6, Freq= 0, CH_0, rank 1
5506 04:41:25.524810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 04:41:25.524892 ==
5508 04:41:25.524957 DQS Delay:
5509 04:41:25.528329 DQS0 = 0, DQS1 = 0
5510 04:41:25.528436 DQM Delay:
5511 04:41:25.531620 DQM0 = 92, DQM1 = 84
5512 04:41:25.531731 DQ Delay:
5513 04:41:25.534727 DQ0 =88, DQ1 =94, DQ2 =88, DQ3 =88
5514 04:41:25.538173 DQ4 =90, DQ5 =82, DQ6 =104, DQ7 =102
5515 04:41:25.541405 DQ8 =76, DQ9 =66, DQ10 =86, DQ11 =76
5516 04:41:25.544738 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5517 04:41:25.544819
5518 04:41:25.544883
5519 04:41:25.551257 [DQSOSCAuto] RK1, (LSB)MR18= 0x3316, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 405 ps
5520 04:41:25.554641 CH0 RK1: MR19=505, MR18=3316
5521 04:41:25.561372 CH0_RK1: MR19=0x505, MR18=0x3316, DQSOSC=405, MR23=63, INC=66, DEC=44
5522 04:41:25.564672 [RxdqsGatingPostProcess] freq 933
5523 04:41:25.571397 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5524 04:41:25.571478 best DQS0 dly(2T, 0.5T) = (0, 11)
5525 04:41:25.574536 best DQS1 dly(2T, 0.5T) = (0, 11)
5526 04:41:25.577855 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5527 04:41:25.581290 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5528 04:41:25.584788 best DQS0 dly(2T, 0.5T) = (0, 10)
5529 04:41:25.587940 best DQS1 dly(2T, 0.5T) = (0, 10)
5530 04:41:25.591262 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5531 04:41:25.594461 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5532 04:41:25.597896 Pre-setting of DQS Precalculation
5533 04:41:25.601306 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5534 04:41:25.604543 ==
5535 04:41:25.607613 Dram Type= 6, Freq= 0, CH_1, rank 0
5536 04:41:25.611283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 04:41:25.611369 ==
5538 04:41:25.614521 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5539 04:41:25.621158 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5540 04:41:25.624922 [CA 0] Center 37 (7~68) winsize 62
5541 04:41:25.627920 [CA 1] Center 37 (7~68) winsize 62
5542 04:41:25.631193 [CA 2] Center 34 (5~64) winsize 60
5543 04:41:25.634628 [CA 3] Center 34 (5~64) winsize 60
5544 04:41:25.637752 [CA 4] Center 34 (5~64) winsize 60
5545 04:41:25.641391 [CA 5] Center 34 (4~64) winsize 61
5546 04:41:25.641499
5547 04:41:25.644546 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5548 04:41:25.644631
5549 04:41:25.647986 [CATrainingPosCal] consider 1 rank data
5550 04:41:25.651230 u2DelayCellTimex100 = 270/100 ps
5551 04:41:25.654380 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5552 04:41:25.660901 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5553 04:41:25.664462 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5554 04:41:25.667518 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5555 04:41:25.671160 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5556 04:41:25.674285 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5557 04:41:25.674454
5558 04:41:25.677379 CA PerBit enable=1, Macro0, CA PI delay=34
5559 04:41:25.677509
5560 04:41:25.680883 [CBTSetCACLKResult] CA Dly = 34
5561 04:41:25.684334 CS Dly: 6 (0~37)
5562 04:41:25.684417 ==
5563 04:41:25.687469 Dram Type= 6, Freq= 0, CH_1, rank 1
5564 04:41:25.690667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 04:41:25.690750 ==
5566 04:41:25.697307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5567 04:41:25.700456 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5568 04:41:25.704594 [CA 0] Center 38 (8~68) winsize 61
5569 04:41:25.707985 [CA 1] Center 37 (7~68) winsize 62
5570 04:41:25.711242 [CA 2] Center 35 (5~65) winsize 61
5571 04:41:25.714647 [CA 3] Center 34 (4~64) winsize 61
5572 04:41:25.717884 [CA 4] Center 35 (5~65) winsize 61
5573 04:41:25.721153 [CA 5] Center 34 (4~64) winsize 61
5574 04:41:25.721234
5575 04:41:25.724472 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5576 04:41:25.724553
5577 04:41:25.728169 [CATrainingPosCal] consider 2 rank data
5578 04:41:25.731361 u2DelayCellTimex100 = 270/100 ps
5579 04:41:25.734657 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5580 04:41:25.741258 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5581 04:41:25.744480 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5582 04:41:25.747905 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5583 04:41:25.751120 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5584 04:41:25.754648 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5585 04:41:25.754729
5586 04:41:25.757650 CA PerBit enable=1, Macro0, CA PI delay=34
5587 04:41:25.757731
5588 04:41:25.761228 [CBTSetCACLKResult] CA Dly = 34
5589 04:41:25.761334 CS Dly: 7 (0~39)
5590 04:41:25.764524
5591 04:41:25.767604 ----->DramcWriteLeveling(PI) begin...
5592 04:41:25.767687 ==
5593 04:41:25.770892 Dram Type= 6, Freq= 0, CH_1, rank 0
5594 04:41:25.774314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5595 04:41:25.774396 ==
5596 04:41:25.777651 Write leveling (Byte 0): 26 => 26
5597 04:41:25.780826 Write leveling (Byte 1): 26 => 26
5598 04:41:25.784343 DramcWriteLeveling(PI) end<-----
5599 04:41:25.784425
5600 04:41:25.784489 ==
5601 04:41:25.787591 Dram Type= 6, Freq= 0, CH_1, rank 0
5602 04:41:25.790741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 04:41:25.790823 ==
5604 04:41:25.794292 [Gating] SW mode calibration
5605 04:41:25.801001 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5606 04:41:25.807529 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5607 04:41:25.810979 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5608 04:41:25.814016 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 04:41:25.820754 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 04:41:25.824170 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 04:41:25.827327 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 04:41:25.834183 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 04:41:25.837345 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5614 04:41:25.840736 0 14 28 | B1->B0 | 3030 2f2f | 0 1 | (0 1) (1 0)
5615 04:41:25.847191 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
5616 04:41:25.850895 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 04:41:25.854120 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 04:41:25.860544 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 04:41:25.863691 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 04:41:25.867362 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 04:41:25.873846 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 04:41:25.876919 0 15 28 | B1->B0 | 2f2e 3232 | 1 0 | (0 0) (0 0)
5623 04:41:25.880221 1 0 0 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
5624 04:41:25.886714 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 04:41:25.890326 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 04:41:25.893582 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 04:41:25.897029 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 04:41:25.903587 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 04:41:25.906916 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 04:41:25.913335 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5631 04:41:25.916715 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 04:41:25.919883 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 04:41:25.923230 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 04:41:25.930122 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 04:41:25.933166 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 04:41:25.936367 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 04:41:25.943446 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 04:41:25.946305 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 04:41:25.949754 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 04:41:25.956246 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 04:41:25.959671 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 04:41:25.963011 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 04:41:25.969485 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 04:41:25.972906 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 04:41:25.976210 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 04:41:25.983154 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5647 04:41:25.986291 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 04:41:25.989399 Total UI for P1: 0, mck2ui 16
5649 04:41:25.993117 best dqsien dly found for B0: ( 1, 2, 28)
5650 04:41:25.996223 Total UI for P1: 0, mck2ui 16
5651 04:41:25.999547 best dqsien dly found for B1: ( 1, 2, 28)
5652 04:41:26.002915 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5653 04:41:26.006222 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5654 04:41:26.006298
5655 04:41:26.009337 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5656 04:41:26.012837 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5657 04:41:26.016039 [Gating] SW calibration Done
5658 04:41:26.016117 ==
5659 04:41:26.019298 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 04:41:26.022896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 04:41:26.026006 ==
5662 04:41:26.026088 RX Vref Scan: 0
5663 04:41:26.026154
5664 04:41:26.029573 RX Vref 0 -> 0, step: 1
5665 04:41:26.029656
5666 04:41:26.032942 RX Delay -80 -> 252, step: 8
5667 04:41:26.036206 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5668 04:41:26.039455 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5669 04:41:26.042627 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5670 04:41:26.046042 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5671 04:41:26.049163 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5672 04:41:26.056076 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5673 04:41:26.059434 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5674 04:41:26.062609 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5675 04:41:26.065742 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5676 04:41:26.069062 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5677 04:41:26.075594 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5678 04:41:26.079282 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5679 04:41:26.082487 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5680 04:41:26.085787 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5681 04:41:26.089056 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5682 04:41:26.095486 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5683 04:41:26.095592 ==
5684 04:41:26.099054 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 04:41:26.102312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 04:41:26.102418 ==
5687 04:41:26.102508 DQS Delay:
5688 04:41:26.105409 DQS0 = 0, DQS1 = 0
5689 04:41:26.105548 DQM Delay:
5690 04:41:26.108921 DQM0 = 94, DQM1 = 87
5691 04:41:26.109002 DQ Delay:
5692 04:41:26.112184 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5693 04:41:26.115474 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5694 04:41:26.118550 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5695 04:41:26.121927 DQ12 =99, DQ13 =91, DQ14 =91, DQ15 =91
5696 04:41:26.122007
5697 04:41:26.122071
5698 04:41:26.122130 ==
5699 04:41:26.125227 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 04:41:26.128541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 04:41:26.131770 ==
5702 04:41:26.131850
5703 04:41:26.131914
5704 04:41:26.131973 TX Vref Scan disable
5705 04:41:26.135238 == TX Byte 0 ==
5706 04:41:26.138284 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5707 04:41:26.141873 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5708 04:41:26.145122 == TX Byte 1 ==
5709 04:41:26.148550 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5710 04:41:26.151536 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5711 04:41:26.155041 ==
5712 04:41:26.155127 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 04:41:26.161457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 04:41:26.161579 ==
5715 04:41:26.161644
5716 04:41:26.161705
5717 04:41:26.164789 TX Vref Scan disable
5718 04:41:26.164872 == TX Byte 0 ==
5719 04:41:26.171432 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5720 04:41:26.174673 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5721 04:41:26.174755 == TX Byte 1 ==
5722 04:41:26.181255 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5723 04:41:26.184908 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5724 04:41:26.185023
5725 04:41:26.185117 [DATLAT]
5726 04:41:26.188276 Freq=933, CH1 RK0
5727 04:41:26.188392
5728 04:41:26.188485 DATLAT Default: 0xd
5729 04:41:26.191133 0, 0xFFFF, sum = 0
5730 04:41:26.191244 1, 0xFFFF, sum = 0
5731 04:41:26.194390 2, 0xFFFF, sum = 0
5732 04:41:26.194487 3, 0xFFFF, sum = 0
5733 04:41:26.198054 4, 0xFFFF, sum = 0
5734 04:41:26.198129 5, 0xFFFF, sum = 0
5735 04:41:26.201327 6, 0xFFFF, sum = 0
5736 04:41:26.204575 7, 0xFFFF, sum = 0
5737 04:41:26.204675 8, 0xFFFF, sum = 0
5738 04:41:26.207798 9, 0xFFFF, sum = 0
5739 04:41:26.207898 10, 0x0, sum = 1
5740 04:41:26.207987 11, 0x0, sum = 2
5741 04:41:26.211034 12, 0x0, sum = 3
5742 04:41:26.211107 13, 0x0, sum = 4
5743 04:41:26.214564 best_step = 11
5744 04:41:26.214667
5745 04:41:26.214757 ==
5746 04:41:26.218053 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 04:41:26.221307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 04:41:26.221414 ==
5749 04:41:26.224560 RX Vref Scan: 1
5750 04:41:26.224658
5751 04:41:26.224747 RX Vref 0 -> 0, step: 1
5752 04:41:26.227843
5753 04:41:26.227940 RX Delay -69 -> 252, step: 4
5754 04:41:26.228028
5755 04:41:26.231132 Set Vref, RX VrefLevel [Byte0]: 54
5756 04:41:26.234235 [Byte1]: 53
5757 04:41:26.238908
5758 04:41:26.238990 Final RX Vref Byte 0 = 54 to rank0
5759 04:41:26.242213 Final RX Vref Byte 1 = 53 to rank0
5760 04:41:26.245352 Final RX Vref Byte 0 = 54 to rank1
5761 04:41:26.248769 Final RX Vref Byte 1 = 53 to rank1==
5762 04:41:26.252226 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 04:41:26.258803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 04:41:26.258931 ==
5765 04:41:26.258996 DQS Delay:
5766 04:41:26.259071 DQS0 = 0, DQS1 = 0
5767 04:41:26.262153 DQM Delay:
5768 04:41:26.262236 DQM0 = 96, DQM1 = 88
5769 04:41:26.265224 DQ Delay:
5770 04:41:26.268501 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =94
5771 04:41:26.271734 DQ4 =92, DQ5 =106, DQ6 =108, DQ7 =94
5772 04:41:26.275049 DQ8 =78, DQ9 =82, DQ10 =88, DQ11 =82
5773 04:41:26.278603 DQ12 =94, DQ13 =94, DQ14 =94, DQ15 =94
5774 04:41:26.278686
5775 04:41:26.278750
5776 04:41:26.285155 [DQSOSCAuto] RK0, (LSB)MR18= 0x50e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 420 ps
5777 04:41:26.288452 CH1 RK0: MR19=505, MR18=50E
5778 04:41:26.295020 CH1_RK0: MR19=0x505, MR18=0x50E, DQSOSC=417, MR23=63, INC=62, DEC=41
5779 04:41:26.295102
5780 04:41:26.298595 ----->DramcWriteLeveling(PI) begin...
5781 04:41:26.298678 ==
5782 04:41:26.301789 Dram Type= 6, Freq= 0, CH_1, rank 1
5783 04:41:26.305051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 04:41:26.305134 ==
5785 04:41:26.308365 Write leveling (Byte 0): 24 => 24
5786 04:41:26.311541 Write leveling (Byte 1): 29 => 29
5787 04:41:26.314879 DramcWriteLeveling(PI) end<-----
5788 04:41:26.314963
5789 04:41:26.315068 ==
5790 04:41:26.318166 Dram Type= 6, Freq= 0, CH_1, rank 1
5791 04:41:26.321398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 04:41:26.321536 ==
5793 04:41:26.324929 [Gating] SW mode calibration
5794 04:41:26.331388 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5795 04:41:26.338165 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5796 04:41:26.341462 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5797 04:41:26.348341 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 04:41:26.351384 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 04:41:26.354688 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 04:41:26.361508 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 04:41:26.364733 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 04:41:26.368163 0 14 24 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
5803 04:41:26.374783 0 14 28 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
5804 04:41:26.378047 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5805 04:41:26.381607 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 04:41:26.384555 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 04:41:26.391103 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 04:41:26.394461 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 04:41:26.397890 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 04:41:26.404301 0 15 24 | B1->B0 | 2727 3535 | 0 1 | (0 0) (0 0)
5811 04:41:26.407537 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5812 04:41:26.411161 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 04:41:26.417946 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 04:41:26.421126 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 04:41:26.424441 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 04:41:26.431157 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 04:41:26.434385 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 04:41:26.437671 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5819 04:41:26.444118 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5820 04:41:26.447763 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 04:41:26.451162 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 04:41:26.457809 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 04:41:26.461053 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 04:41:26.464306 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 04:41:26.470938 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 04:41:26.474268 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 04:41:26.477400 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 04:41:26.484232 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 04:41:26.487341 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 04:41:26.490584 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 04:41:26.497297 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 04:41:26.500506 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 04:41:26.504176 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 04:41:26.510556 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5835 04:41:26.513755 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 04:41:26.517067 Total UI for P1: 0, mck2ui 16
5837 04:41:26.520355 best dqsien dly found for B0: ( 1, 2, 24)
5838 04:41:26.523580 Total UI for P1: 0, mck2ui 16
5839 04:41:26.526855 best dqsien dly found for B1: ( 1, 2, 24)
5840 04:41:26.530183 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5841 04:41:26.533870 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5842 04:41:26.533953
5843 04:41:26.536882 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5844 04:41:26.540256 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5845 04:41:26.543448 [Gating] SW calibration Done
5846 04:41:26.543531 ==
5847 04:41:26.547061 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 04:41:26.550065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 04:41:26.553323 ==
5850 04:41:26.553405 RX Vref Scan: 0
5851 04:41:26.553469
5852 04:41:26.556696 RX Vref 0 -> 0, step: 1
5853 04:41:26.556778
5854 04:41:26.560278 RX Delay -80 -> 252, step: 8
5855 04:41:26.563560 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5856 04:41:26.566840 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5857 04:41:26.570290 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5858 04:41:26.573537 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5859 04:41:26.576804 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5860 04:41:26.583735 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5861 04:41:26.586843 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5862 04:41:26.590140 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5863 04:41:26.593442 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5864 04:41:26.596803 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5865 04:41:26.600235 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5866 04:41:26.606744 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5867 04:41:26.610051 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5868 04:41:26.613288 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5869 04:41:26.616685 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5870 04:41:26.619834 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5871 04:41:26.619934 ==
5872 04:41:26.623205 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 04:41:26.630022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 04:41:26.630105 ==
5875 04:41:26.630170 DQS Delay:
5876 04:41:26.633323 DQS0 = 0, DQS1 = 0
5877 04:41:26.633406 DQM Delay:
5878 04:41:26.636634 DQM0 = 94, DQM1 = 89
5879 04:41:26.636717 DQ Delay:
5880 04:41:26.639715 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5881 04:41:26.643338 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5882 04:41:26.646579 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =83
5883 04:41:26.649645 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =99
5884 04:41:26.649728
5885 04:41:26.649794
5886 04:41:26.649854 ==
5887 04:41:26.653169 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 04:41:26.656541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 04:41:26.656625 ==
5890 04:41:26.656690
5891 04:41:26.656750
5892 04:41:26.659555 TX Vref Scan disable
5893 04:41:26.663158 == TX Byte 0 ==
5894 04:41:26.666051 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5895 04:41:26.669382 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5896 04:41:26.672710 == TX Byte 1 ==
5897 04:41:26.676036 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5898 04:41:26.679282 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5899 04:41:26.679365 ==
5900 04:41:26.683017 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 04:41:26.689422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 04:41:26.689555 ==
5903 04:41:26.689620
5904 04:41:26.689680
5905 04:41:26.689736 TX Vref Scan disable
5906 04:41:26.693470 == TX Byte 0 ==
5907 04:41:26.696642 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5908 04:41:26.703127 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5909 04:41:26.703208 == TX Byte 1 ==
5910 04:41:26.706498 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5911 04:41:26.713243 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5912 04:41:26.713351
5913 04:41:26.713446 [DATLAT]
5914 04:41:26.713559 Freq=933, CH1 RK1
5915 04:41:26.713619
5916 04:41:26.716368 DATLAT Default: 0xb
5917 04:41:26.716471 0, 0xFFFF, sum = 0
5918 04:41:26.719885 1, 0xFFFF, sum = 0
5919 04:41:26.719968 2, 0xFFFF, sum = 0
5920 04:41:26.723460 3, 0xFFFF, sum = 0
5921 04:41:26.726613 4, 0xFFFF, sum = 0
5922 04:41:26.726696 5, 0xFFFF, sum = 0
5923 04:41:26.729794 6, 0xFFFF, sum = 0
5924 04:41:26.729902 7, 0xFFFF, sum = 0
5925 04:41:26.732995 8, 0xFFFF, sum = 0
5926 04:41:26.733104 9, 0xFFFF, sum = 0
5927 04:41:26.736358 10, 0x0, sum = 1
5928 04:41:26.736440 11, 0x0, sum = 2
5929 04:41:26.739910 12, 0x0, sum = 3
5930 04:41:26.739992 13, 0x0, sum = 4
5931 04:41:26.740058 best_step = 11
5932 04:41:26.740118
5933 04:41:26.743060 ==
5934 04:41:26.746370 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 04:41:26.749493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 04:41:26.749606 ==
5937 04:41:26.749683 RX Vref Scan: 0
5938 04:41:26.749743
5939 04:41:26.753054 RX Vref 0 -> 0, step: 1
5940 04:41:26.753160
5941 04:41:26.756391 RX Delay -69 -> 252, step: 4
5942 04:41:26.762795 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5943 04:41:26.766273 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5944 04:41:26.769370 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5945 04:41:26.773026 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5946 04:41:26.776309 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5947 04:41:26.779548 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5948 04:41:26.786156 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5949 04:41:26.789298 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5950 04:41:26.792984 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5951 04:41:26.796253 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5952 04:41:26.799530 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5953 04:41:26.805790 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5954 04:41:26.809374 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5955 04:41:26.812634 iDelay=203, Bit 13, Center 100 (7 ~ 194) 188
5956 04:41:26.816319 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5957 04:41:26.819664 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5958 04:41:26.819745 ==
5959 04:41:26.822787 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 04:41:26.829263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 04:41:26.829345 ==
5962 04:41:26.829409 DQS Delay:
5963 04:41:26.829483 DQS0 = 0, DQS1 = 0
5964 04:41:26.832750 DQM Delay:
5965 04:41:26.832830 DQM0 = 91, DQM1 = 90
5966 04:41:26.835932 DQ Delay:
5967 04:41:26.839095 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5968 04:41:26.842497 DQ4 =90, DQ5 =102, DQ6 =102, DQ7 =88
5969 04:41:26.845857 DQ8 =78, DQ9 =80, DQ10 =92, DQ11 =82
5970 04:41:26.849030 DQ12 =98, DQ13 =100, DQ14 =96, DQ15 =96
5971 04:41:26.849111
5972 04:41:26.849175
5973 04:41:26.855846 [DQSOSCAuto] RK1, (LSB)MR18= 0x1023, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5974 04:41:26.859255 CH1 RK1: MR19=505, MR18=1023
5975 04:41:26.865772 CH1_RK1: MR19=0x505, MR18=0x1023, DQSOSC=410, MR23=63, INC=64, DEC=42
5976 04:41:26.869032 [RxdqsGatingPostProcess] freq 933
5977 04:41:26.872372 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5978 04:41:26.875862 best DQS0 dly(2T, 0.5T) = (0, 10)
5979 04:41:26.879247 best DQS1 dly(2T, 0.5T) = (0, 10)
5980 04:41:26.882607 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5981 04:41:26.885859 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5982 04:41:26.889178 best DQS0 dly(2T, 0.5T) = (0, 10)
5983 04:41:26.892328 best DQS1 dly(2T, 0.5T) = (0, 10)
5984 04:41:26.895491 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5985 04:41:26.898780 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5986 04:41:26.902062 Pre-setting of DQS Precalculation
5987 04:41:26.905728 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5988 04:41:26.915528 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5989 04:41:26.922209 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5990 04:41:26.922290
5991 04:41:26.922354
5992 04:41:26.925610 [Calibration Summary] 1866 Mbps
5993 04:41:26.925691 CH 0, Rank 0
5994 04:41:26.928764 SW Impedance : PASS
5995 04:41:26.928845 DUTY Scan : NO K
5996 04:41:26.932028 ZQ Calibration : PASS
5997 04:41:26.935257 Jitter Meter : NO K
5998 04:41:26.935337 CBT Training : PASS
5999 04:41:26.938488 Write leveling : PASS
6000 04:41:26.941763 RX DQS gating : PASS
6001 04:41:26.941844 RX DQ/DQS(RDDQC) : PASS
6002 04:41:26.945193 TX DQ/DQS : PASS
6003 04:41:26.948406 RX DATLAT : PASS
6004 04:41:26.948486 RX DQ/DQS(Engine): PASS
6005 04:41:26.951797 TX OE : NO K
6006 04:41:26.951878 All Pass.
6007 04:41:26.951942
6008 04:41:26.955155 CH 0, Rank 1
6009 04:41:26.955236 SW Impedance : PASS
6010 04:41:26.958284 DUTY Scan : NO K
6011 04:41:26.961794 ZQ Calibration : PASS
6012 04:41:26.961889 Jitter Meter : NO K
6013 04:41:26.964766 CBT Training : PASS
6014 04:41:26.968219 Write leveling : PASS
6015 04:41:26.968300 RX DQS gating : PASS
6016 04:41:26.971686 RX DQ/DQS(RDDQC) : PASS
6017 04:41:26.971810 TX DQ/DQS : PASS
6018 04:41:26.974825 RX DATLAT : PASS
6019 04:41:26.978106 RX DQ/DQS(Engine): PASS
6020 04:41:26.978187 TX OE : NO K
6021 04:41:26.981659 All Pass.
6022 04:41:26.981766
6023 04:41:26.981862 CH 1, Rank 0
6024 04:41:26.984920 SW Impedance : PASS
6025 04:41:26.984997 DUTY Scan : NO K
6026 04:41:26.988151 ZQ Calibration : PASS
6027 04:41:26.991635 Jitter Meter : NO K
6028 04:41:26.991719 CBT Training : PASS
6029 04:41:26.994825 Write leveling : PASS
6030 04:41:26.998103 RX DQS gating : PASS
6031 04:41:26.998184 RX DQ/DQS(RDDQC) : PASS
6032 04:41:27.001454 TX DQ/DQS : PASS
6033 04:41:27.004816 RX DATLAT : PASS
6034 04:41:27.004896 RX DQ/DQS(Engine): PASS
6035 04:41:27.008127 TX OE : NO K
6036 04:41:27.008208 All Pass.
6037 04:41:27.008272
6038 04:41:27.011356 CH 1, Rank 1
6039 04:41:27.011437 SW Impedance : PASS
6040 04:41:27.014570 DUTY Scan : NO K
6041 04:41:27.018366 ZQ Calibration : PASS
6042 04:41:27.018446 Jitter Meter : NO K
6043 04:41:27.021239 CBT Training : PASS
6044 04:41:27.024819 Write leveling : PASS
6045 04:41:27.024899 RX DQS gating : PASS
6046 04:41:27.028163 RX DQ/DQS(RDDQC) : PASS
6047 04:41:27.028243 TX DQ/DQS : PASS
6048 04:41:27.031400 RX DATLAT : PASS
6049 04:41:27.034727 RX DQ/DQS(Engine): PASS
6050 04:41:27.034808 TX OE : NO K
6051 04:41:27.037737 All Pass.
6052 04:41:27.037848
6053 04:41:27.037940 DramC Write-DBI off
6054 04:41:27.041050 PER_BANK_REFRESH: Hybrid Mode
6055 04:41:27.044639 TX_TRACKING: ON
6056 04:41:27.050896 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6057 04:41:27.054552 [FAST_K] Save calibration result to emmc
6058 04:41:27.061120 dramc_set_vcore_voltage set vcore to 650000
6059 04:41:27.061200 Read voltage for 400, 6
6060 04:41:27.061265 Vio18 = 0
6061 04:41:27.064369 Vcore = 650000
6062 04:41:27.064449 Vdram = 0
6063 04:41:27.064513 Vddq = 0
6064 04:41:27.067559 Vmddr = 0
6065 04:41:27.070835 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6066 04:41:27.077497 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6067 04:41:27.080815 MEM_TYPE=3, freq_sel=20
6068 04:41:27.080896 sv_algorithm_assistance_LP4_800
6069 04:41:27.087293 ============ PULL DRAM RESETB DOWN ============
6070 04:41:27.090979 ========== PULL DRAM RESETB DOWN end =========
6071 04:41:27.094034 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6072 04:41:27.097237 ===================================
6073 04:41:27.100872 LPDDR4 DRAM CONFIGURATION
6074 04:41:27.104048 ===================================
6075 04:41:27.107290 EX_ROW_EN[0] = 0x0
6076 04:41:27.107372 EX_ROW_EN[1] = 0x0
6077 04:41:27.110551 LP4Y_EN = 0x0
6078 04:41:27.110633 WORK_FSP = 0x0
6079 04:41:27.114041 WL = 0x2
6080 04:41:27.114146 RL = 0x2
6081 04:41:27.117209 BL = 0x2
6082 04:41:27.117291 RPST = 0x0
6083 04:41:27.120528 RD_PRE = 0x0
6084 04:41:27.120610 WR_PRE = 0x1
6085 04:41:27.123982 WR_PST = 0x0
6086 04:41:27.124090 DBI_WR = 0x0
6087 04:41:27.127471 DBI_RD = 0x0
6088 04:41:27.127552 OTF = 0x1
6089 04:41:27.130667 ===================================
6090 04:41:27.134072 ===================================
6091 04:41:27.137250 ANA top config
6092 04:41:27.140712 ===================================
6093 04:41:27.143807 DLL_ASYNC_EN = 0
6094 04:41:27.143888 ALL_SLAVE_EN = 1
6095 04:41:27.147066 NEW_RANK_MODE = 1
6096 04:41:27.150322 DLL_IDLE_MODE = 1
6097 04:41:27.153548 LP45_APHY_COMB_EN = 1
6098 04:41:27.156807 TX_ODT_DIS = 1
6099 04:41:27.156888 NEW_8X_MODE = 1
6100 04:41:27.160140 ===================================
6101 04:41:27.163383 ===================================
6102 04:41:27.167063 data_rate = 800
6103 04:41:27.170216 CKR = 1
6104 04:41:27.173303 DQ_P2S_RATIO = 4
6105 04:41:27.176882 ===================================
6106 04:41:27.180243 CA_P2S_RATIO = 4
6107 04:41:27.183408 DQ_CA_OPEN = 0
6108 04:41:27.183489 DQ_SEMI_OPEN = 1
6109 04:41:27.186691 CA_SEMI_OPEN = 1
6110 04:41:27.190097 CA_FULL_RATE = 0
6111 04:41:27.193576 DQ_CKDIV4_EN = 0
6112 04:41:27.196626 CA_CKDIV4_EN = 1
6113 04:41:27.196706 CA_PREDIV_EN = 0
6114 04:41:27.200042 PH8_DLY = 0
6115 04:41:27.203423 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6116 04:41:27.206787 DQ_AAMCK_DIV = 0
6117 04:41:27.210149 CA_AAMCK_DIV = 0
6118 04:41:27.213353 CA_ADMCK_DIV = 4
6119 04:41:27.213460 DQ_TRACK_CA_EN = 0
6120 04:41:27.216677 CA_PICK = 800
6121 04:41:27.219861 CA_MCKIO = 400
6122 04:41:27.223152 MCKIO_SEMI = 400
6123 04:41:27.226590 PLL_FREQ = 3016
6124 04:41:27.230033 DQ_UI_PI_RATIO = 32
6125 04:41:27.233245 CA_UI_PI_RATIO = 32
6126 04:41:27.236534 ===================================
6127 04:41:27.239908 ===================================
6128 04:41:27.239997 memory_type:LPDDR4
6129 04:41:27.243102 GP_NUM : 10
6130 04:41:27.246306 SRAM_EN : 1
6131 04:41:27.246386 MD32_EN : 0
6132 04:41:27.249544 ===================================
6133 04:41:27.253218 [ANA_INIT] >>>>>>>>>>>>>>
6134 04:41:27.256450 <<<<<< [CONFIGURE PHASE]: ANA_TX
6135 04:41:27.259643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6136 04:41:27.263052 ===================================
6137 04:41:27.266136 data_rate = 800,PCW = 0X7400
6138 04:41:27.269775 ===================================
6139 04:41:27.272912 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6140 04:41:27.276198 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6141 04:41:27.289457 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6142 04:41:27.292833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6143 04:41:27.295864 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6144 04:41:27.299122 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6145 04:41:27.302784 [ANA_INIT] flow start
6146 04:41:27.305981 [ANA_INIT] PLL >>>>>>>>
6147 04:41:27.306062 [ANA_INIT] PLL <<<<<<<<
6148 04:41:27.309073 [ANA_INIT] MIDPI >>>>>>>>
6149 04:41:27.312544 [ANA_INIT] MIDPI <<<<<<<<
6150 04:41:27.312624 [ANA_INIT] DLL >>>>>>>>
6151 04:41:27.315804 [ANA_INIT] flow end
6152 04:41:27.319004 ============ LP4 DIFF to SE enter ============
6153 04:41:27.325815 ============ LP4 DIFF to SE exit ============
6154 04:41:27.325897 [ANA_INIT] <<<<<<<<<<<<<
6155 04:41:27.329015 [Flow] Enable top DCM control >>>>>
6156 04:41:27.332396 [Flow] Enable top DCM control <<<<<
6157 04:41:27.335654 Enable DLL master slave shuffle
6158 04:41:27.342348 ==============================================================
6159 04:41:27.342429 Gating Mode config
6160 04:41:27.348706 ==============================================================
6161 04:41:27.352313 Config description:
6162 04:41:27.362110 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6163 04:41:27.368948 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6164 04:41:27.372308 SELPH_MODE 0: By rank 1: By Phase
6165 04:41:27.378706 ==============================================================
6166 04:41:27.382008 GAT_TRACK_EN = 0
6167 04:41:27.382092 RX_GATING_MODE = 2
6168 04:41:27.385513 RX_GATING_TRACK_MODE = 2
6169 04:41:27.388779 SELPH_MODE = 1
6170 04:41:27.392063 PICG_EARLY_EN = 1
6171 04:41:27.395283 VALID_LAT_VALUE = 1
6172 04:41:27.401893 ==============================================================
6173 04:41:27.405038 Enter into Gating configuration >>>>
6174 04:41:27.408587 Exit from Gating configuration <<<<
6175 04:41:27.411929 Enter into DVFS_PRE_config >>>>>
6176 04:41:27.421995 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6177 04:41:27.425273 Exit from DVFS_PRE_config <<<<<
6178 04:41:27.428579 Enter into PICG configuration >>>>
6179 04:41:27.431747 Exit from PICG configuration <<<<
6180 04:41:27.435350 [RX_INPUT] configuration >>>>>
6181 04:41:27.438542 [RX_INPUT] configuration <<<<<
6182 04:41:27.441845 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6183 04:41:27.448406 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6184 04:41:27.455072 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6185 04:41:27.458282 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6186 04:41:27.465222 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6187 04:41:27.471758 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6188 04:41:27.474953 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6189 04:41:27.481700 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6190 04:41:27.484788 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6191 04:41:27.488149 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6192 04:41:27.491300 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6193 04:41:27.498284 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6194 04:41:27.501530 ===================================
6195 04:41:27.501602 LPDDR4 DRAM CONFIGURATION
6196 04:41:27.504636 ===================================
6197 04:41:27.507856 EX_ROW_EN[0] = 0x0
6198 04:41:27.511207 EX_ROW_EN[1] = 0x0
6199 04:41:27.511281 LP4Y_EN = 0x0
6200 04:41:27.514531 WORK_FSP = 0x0
6201 04:41:27.514599 WL = 0x2
6202 04:41:27.518137 RL = 0x2
6203 04:41:27.518211 BL = 0x2
6204 04:41:27.521059 RPST = 0x0
6205 04:41:27.521134 RD_PRE = 0x0
6206 04:41:27.524504 WR_PRE = 0x1
6207 04:41:27.524576 WR_PST = 0x0
6208 04:41:27.527831 DBI_WR = 0x0
6209 04:41:27.527907 DBI_RD = 0x0
6210 04:41:27.531041 OTF = 0x1
6211 04:41:27.534364 ===================================
6212 04:41:27.537905 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6213 04:41:27.541123 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6214 04:41:27.547807 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6215 04:41:27.551257 ===================================
6216 04:41:27.551329 LPDDR4 DRAM CONFIGURATION
6217 04:41:27.554480 ===================================
6218 04:41:27.557854 EX_ROW_EN[0] = 0x10
6219 04:41:27.560970 EX_ROW_EN[1] = 0x0
6220 04:41:27.561037 LP4Y_EN = 0x0
6221 04:41:27.564455 WORK_FSP = 0x0
6222 04:41:27.564530 WL = 0x2
6223 04:41:27.567570 RL = 0x2
6224 04:41:27.567644 BL = 0x2
6225 04:41:27.570990 RPST = 0x0
6226 04:41:27.571062 RD_PRE = 0x0
6227 04:41:27.574577 WR_PRE = 0x1
6228 04:41:27.574646 WR_PST = 0x0
6229 04:41:27.577855 DBI_WR = 0x0
6230 04:41:27.577924 DBI_RD = 0x0
6231 04:41:27.581201 OTF = 0x1
6232 04:41:27.584078 ===================================
6233 04:41:27.590828 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6234 04:41:27.594124 nWR fixed to 30
6235 04:41:27.594204 [ModeRegInit_LP4] CH0 RK0
6236 04:41:27.597343 [ModeRegInit_LP4] CH0 RK1
6237 04:41:27.600815 [ModeRegInit_LP4] CH1 RK0
6238 04:41:27.604124 [ModeRegInit_LP4] CH1 RK1
6239 04:41:27.604198 match AC timing 19
6240 04:41:27.607547 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6241 04:41:27.614113 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6242 04:41:27.617284 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6243 04:41:27.620668 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6244 04:41:27.627551 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6245 04:41:27.627633 ==
6246 04:41:27.630531 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 04:41:27.633803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 04:41:27.633885 ==
6249 04:41:27.640625 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6250 04:41:27.646934 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6251 04:41:27.650637 [CA 0] Center 36 (8~64) winsize 57
6252 04:41:27.650719 [CA 1] Center 36 (8~64) winsize 57
6253 04:41:27.653948 [CA 2] Center 36 (8~64) winsize 57
6254 04:41:27.657166 [CA 3] Center 36 (8~64) winsize 57
6255 04:41:27.660711 [CA 4] Center 36 (8~64) winsize 57
6256 04:41:27.663984 [CA 5] Center 36 (8~64) winsize 57
6257 04:41:27.664065
6258 04:41:27.667318 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6259 04:41:27.667399
6260 04:41:27.673751 [CATrainingPosCal] consider 1 rank data
6261 04:41:27.673832 u2DelayCellTimex100 = 270/100 ps
6262 04:41:27.677245 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 04:41:27.683667 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 04:41:27.687042 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 04:41:27.690185 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 04:41:27.693411 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 04:41:27.696902 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 04:41:27.696983
6269 04:41:27.700100 CA PerBit enable=1, Macro0, CA PI delay=36
6270 04:41:27.700180
6271 04:41:27.703364 [CBTSetCACLKResult] CA Dly = 36
6272 04:41:27.706910 CS Dly: 1 (0~32)
6273 04:41:27.706991 ==
6274 04:41:27.710022 Dram Type= 6, Freq= 0, CH_0, rank 1
6275 04:41:27.713234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 04:41:27.713315 ==
6277 04:41:27.720066 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6278 04:41:27.723400 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6279 04:41:27.726546 [CA 0] Center 36 (8~64) winsize 57
6280 04:41:27.730002 [CA 1] Center 36 (8~64) winsize 57
6281 04:41:27.733099 [CA 2] Center 36 (8~64) winsize 57
6282 04:41:27.736409 [CA 3] Center 36 (8~64) winsize 57
6283 04:41:27.739755 [CA 4] Center 36 (8~64) winsize 57
6284 04:41:27.742943 [CA 5] Center 36 (8~64) winsize 57
6285 04:41:27.743024
6286 04:41:27.746323 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6287 04:41:27.746404
6288 04:41:27.749722 [CATrainingPosCal] consider 2 rank data
6289 04:41:27.753102 u2DelayCellTimex100 = 270/100 ps
6290 04:41:27.756441 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 04:41:27.759563 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 04:41:27.762934 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 04:41:27.769429 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 04:41:27.772808 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 04:41:27.776512 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 04:41:27.776629
6297 04:41:27.779731 CA PerBit enable=1, Macro0, CA PI delay=36
6298 04:41:27.779809
6299 04:41:27.782857 [CBTSetCACLKResult] CA Dly = 36
6300 04:41:27.782926 CS Dly: 1 (0~32)
6301 04:41:27.782993
6302 04:41:27.786211 ----->DramcWriteLeveling(PI) begin...
6303 04:41:27.786288 ==
6304 04:41:27.789366 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 04:41:27.795886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 04:41:27.795973 ==
6307 04:41:27.799208 Write leveling (Byte 0): 40 => 8
6308 04:41:27.802696 Write leveling (Byte 1): 40 => 8
6309 04:41:27.802776 DramcWriteLeveling(PI) end<-----
6310 04:41:27.805968
6311 04:41:27.806035 ==
6312 04:41:27.809534 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 04:41:27.812774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 04:41:27.812850 ==
6315 04:41:27.816043 [Gating] SW mode calibration
6316 04:41:27.822432 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6317 04:41:27.825733 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6318 04:41:27.832725 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6319 04:41:27.836030 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6320 04:41:27.839198 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6321 04:41:27.845839 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6322 04:41:27.849245 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 04:41:27.852510 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 04:41:27.859229 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 04:41:27.862322 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 04:41:27.865607 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6327 04:41:27.869189 Total UI for P1: 0, mck2ui 16
6328 04:41:27.872154 best dqsien dly found for B0: ( 0, 14, 24)
6329 04:41:27.875478 Total UI for P1: 0, mck2ui 16
6330 04:41:27.878904 best dqsien dly found for B1: ( 0, 14, 24)
6331 04:41:27.882077 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6332 04:41:27.885709 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6333 04:41:27.885830
6334 04:41:27.892295 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6335 04:41:27.895573 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6336 04:41:27.898873 [Gating] SW calibration Done
6337 04:41:27.898953 ==
6338 04:41:27.902223 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 04:41:27.905617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 04:41:27.905699 ==
6341 04:41:27.905762 RX Vref Scan: 0
6342 04:41:27.905822
6343 04:41:27.908760 RX Vref 0 -> 0, step: 1
6344 04:41:27.908839
6345 04:41:27.912001 RX Delay -410 -> 252, step: 16
6346 04:41:27.915626 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6347 04:41:27.922191 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6348 04:41:27.925378 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6349 04:41:27.928690 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6350 04:41:27.932297 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6351 04:41:27.938572 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6352 04:41:27.942014 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6353 04:41:27.945226 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6354 04:41:27.948664 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6355 04:41:27.955346 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6356 04:41:27.958610 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6357 04:41:27.961814 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6358 04:41:27.965079 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6359 04:41:27.971810 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6360 04:41:27.975173 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6361 04:41:27.978591 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6362 04:41:27.978674 ==
6363 04:41:27.981847 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 04:41:27.985244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 04:41:27.988268 ==
6366 04:41:27.988373 DQS Delay:
6367 04:41:27.988465 DQS0 = 59, DQS1 = 59
6368 04:41:27.991946 DQM Delay:
6369 04:41:27.992026 DQM0 = 18, DQM1 = 10
6370 04:41:27.995080 DQ Delay:
6371 04:41:27.998323 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6372 04:41:28.001582 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6373 04:41:28.001662 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6374 04:41:28.004867 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6375 04:41:28.004946
6376 04:41:28.008431
6377 04:41:28.008511 ==
6378 04:41:28.011562 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 04:41:28.014850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 04:41:28.014935 ==
6381 04:41:28.014998
6382 04:41:28.015057
6383 04:41:28.018297 TX Vref Scan disable
6384 04:41:28.018377 == TX Byte 0 ==
6385 04:41:28.021511 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 04:41:28.028090 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 04:41:28.028171 == TX Byte 1 ==
6388 04:41:28.031576 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 04:41:28.038137 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 04:41:28.038218 ==
6391 04:41:28.041286 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 04:41:28.044914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 04:41:28.045005 ==
6394 04:41:28.045125
6395 04:41:28.045212
6396 04:41:28.047875 TX Vref Scan disable
6397 04:41:28.047958 == TX Byte 0 ==
6398 04:41:28.051265 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6399 04:41:28.057879 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6400 04:41:28.057960 == TX Byte 1 ==
6401 04:41:28.061238 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 04:41:28.068094 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 04:41:28.068176
6404 04:41:28.068240 [DATLAT]
6405 04:41:28.068299 Freq=400, CH0 RK0
6406 04:41:28.071436
6407 04:41:28.071516 DATLAT Default: 0xf
6408 04:41:28.074622 0, 0xFFFF, sum = 0
6409 04:41:28.074705 1, 0xFFFF, sum = 0
6410 04:41:28.077863 2, 0xFFFF, sum = 0
6411 04:41:28.077945 3, 0xFFFF, sum = 0
6412 04:41:28.081253 4, 0xFFFF, sum = 0
6413 04:41:28.081355 5, 0xFFFF, sum = 0
6414 04:41:28.084393 6, 0xFFFF, sum = 0
6415 04:41:28.084501 7, 0xFFFF, sum = 0
6416 04:41:28.087878 8, 0xFFFF, sum = 0
6417 04:41:28.087957 9, 0xFFFF, sum = 0
6418 04:41:28.091196 10, 0xFFFF, sum = 0
6419 04:41:28.091274 11, 0xFFFF, sum = 0
6420 04:41:28.094641 12, 0xFFFF, sum = 0
6421 04:41:28.094722 13, 0x0, sum = 1
6422 04:41:28.097594 14, 0x0, sum = 2
6423 04:41:28.097671 15, 0x0, sum = 3
6424 04:41:28.100990 16, 0x0, sum = 4
6425 04:41:28.101093 best_step = 14
6426 04:41:28.101189
6427 04:41:28.101276 ==
6428 04:41:28.104242 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 04:41:28.110864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 04:41:28.110948 ==
6431 04:41:28.111013 RX Vref Scan: 1
6432 04:41:28.111076
6433 04:41:28.114513 RX Vref 0 -> 0, step: 1
6434 04:41:28.114594
6435 04:41:28.117652 RX Delay -359 -> 252, step: 8
6436 04:41:28.117759
6437 04:41:28.120882 Set Vref, RX VrefLevel [Byte0]: 62
6438 04:41:28.124268 [Byte1]: 46
6439 04:41:28.124350
6440 04:41:28.127410 Final RX Vref Byte 0 = 62 to rank0
6441 04:41:28.130711 Final RX Vref Byte 1 = 46 to rank0
6442 04:41:28.134439 Final RX Vref Byte 0 = 62 to rank1
6443 04:41:28.137510 Final RX Vref Byte 1 = 46 to rank1==
6444 04:41:28.140905 Dram Type= 6, Freq= 0, CH_0, rank 0
6445 04:41:28.144173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 04:41:28.147427 ==
6447 04:41:28.147508 DQS Delay:
6448 04:41:28.147572 DQS0 = 60, DQS1 = 68
6449 04:41:28.150588 DQM Delay:
6450 04:41:28.150668 DQM0 = 14, DQM1 = 13
6451 04:41:28.154279 DQ Delay:
6452 04:41:28.157354 DQ0 =12, DQ1 =16, DQ2 =16, DQ3 =8
6453 04:41:28.157484 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6454 04:41:28.160537 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6455 04:41:28.163921 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6456 04:41:28.164002
6457 04:41:28.167301
6458 04:41:28.173814 [DQSOSCAuto] RK0, (LSB)MR18= 0x8785, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6459 04:41:28.177032 CH0 RK0: MR19=C0C, MR18=8785
6460 04:41:28.184057 CH0_RK0: MR19=0xC0C, MR18=0x8785, DQSOSC=392, MR23=63, INC=384, DEC=256
6461 04:41:28.184138 ==
6462 04:41:28.187056 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 04:41:28.190363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 04:41:28.190444 ==
6465 04:41:28.193947 [Gating] SW mode calibration
6466 04:41:28.200359 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6467 04:41:28.207100 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6468 04:41:28.210419 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6469 04:41:28.213671 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6470 04:41:28.220160 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6471 04:41:28.223578 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 04:41:28.226759 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 04:41:28.233560 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 04:41:28.236919 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 04:41:28.240043 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 04:41:28.246798 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 04:41:28.246877 Total UI for P1: 0, mck2ui 16
6478 04:41:28.250141 best dqsien dly found for B0: ( 0, 14, 24)
6479 04:41:28.253175 Total UI for P1: 0, mck2ui 16
6480 04:41:28.256478 best dqsien dly found for B1: ( 0, 14, 24)
6481 04:41:28.263069 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6482 04:41:28.266587 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6483 04:41:28.266660
6484 04:41:28.269891 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6485 04:41:28.273127 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6486 04:41:28.276282 [Gating] SW calibration Done
6487 04:41:28.276352 ==
6488 04:41:28.279607 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 04:41:28.282887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 04:41:28.282974 ==
6491 04:41:28.286450 RX Vref Scan: 0
6492 04:41:28.286532
6493 04:41:28.286596 RX Vref 0 -> 0, step: 1
6494 04:41:28.286656
6495 04:41:28.289786 RX Delay -410 -> 252, step: 16
6496 04:41:28.296444 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6497 04:41:28.299593 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6498 04:41:28.302812 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6499 04:41:28.306221 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6500 04:41:28.312658 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6501 04:41:28.316249 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6502 04:41:28.319374 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6503 04:41:28.322855 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6504 04:41:28.329200 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6505 04:41:28.332643 iDelay=230, Bit 9, Center -67 (-314 ~ 181) 496
6506 04:41:28.336040 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6507 04:41:28.339333 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6508 04:41:28.345921 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6509 04:41:28.349032 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6510 04:41:28.352271 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6511 04:41:28.355684 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6512 04:41:28.358850 ==
6513 04:41:28.362353 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 04:41:28.365645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 04:41:28.365715 ==
6516 04:41:28.365776 DQS Delay:
6517 04:41:28.368879 DQS0 = 59, DQS1 = 67
6518 04:41:28.368945 DQM Delay:
6519 04:41:28.372290 DQM0 = 16, DQM1 = 17
6520 04:41:28.372357 DQ Delay:
6521 04:41:28.375395 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6522 04:41:28.378722 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6523 04:41:28.382272 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6524 04:41:28.385516 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6525 04:41:28.385601
6526 04:41:28.385663
6527 04:41:28.385721 ==
6528 04:41:28.388860 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 04:41:28.392122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 04:41:28.392190 ==
6531 04:41:28.392256
6532 04:41:28.392313
6533 04:41:28.395718 TX Vref Scan disable
6534 04:41:28.395786 == TX Byte 0 ==
6535 04:41:28.402234 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6536 04:41:28.405548 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6537 04:41:28.405627 == TX Byte 1 ==
6538 04:41:28.412168 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6539 04:41:28.415401 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6540 04:41:28.415469 ==
6541 04:41:28.419039 Dram Type= 6, Freq= 0, CH_0, rank 1
6542 04:41:28.422346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6543 04:41:28.422425 ==
6544 04:41:28.422486
6545 04:41:28.422542
6546 04:41:28.425633 TX Vref Scan disable
6547 04:41:28.425702 == TX Byte 0 ==
6548 04:41:28.432073 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6549 04:41:28.435221 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6550 04:41:28.435293 == TX Byte 1 ==
6551 04:41:28.442148 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6552 04:41:28.445357 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6553 04:41:28.445453
6554 04:41:28.445557 [DATLAT]
6555 04:41:28.448736 Freq=400, CH0 RK1
6556 04:41:28.448804
6557 04:41:28.448870 DATLAT Default: 0xe
6558 04:41:28.451951 0, 0xFFFF, sum = 0
6559 04:41:28.452022 1, 0xFFFF, sum = 0
6560 04:41:28.455431 2, 0xFFFF, sum = 0
6561 04:41:28.455519 3, 0xFFFF, sum = 0
6562 04:41:28.458864 4, 0xFFFF, sum = 0
6563 04:41:28.458934 5, 0xFFFF, sum = 0
6564 04:41:28.462124 6, 0xFFFF, sum = 0
6565 04:41:28.462194 7, 0xFFFF, sum = 0
6566 04:41:28.465191 8, 0xFFFF, sum = 0
6567 04:41:28.465257 9, 0xFFFF, sum = 0
6568 04:41:28.468970 10, 0xFFFF, sum = 0
6569 04:41:28.472113 11, 0xFFFF, sum = 0
6570 04:41:28.472183 12, 0xFFFF, sum = 0
6571 04:41:28.475287 13, 0x0, sum = 1
6572 04:41:28.475357 14, 0x0, sum = 2
6573 04:41:28.478792 15, 0x0, sum = 3
6574 04:41:28.478861 16, 0x0, sum = 4
6575 04:41:28.478928 best_step = 14
6576 04:41:28.478985
6577 04:41:28.481696 ==
6578 04:41:28.485347 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 04:41:28.488430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 04:41:28.488512 ==
6581 04:41:28.488576 RX Vref Scan: 0
6582 04:41:28.488635
6583 04:41:28.491659 RX Vref 0 -> 0, step: 1
6584 04:41:28.491728
6585 04:41:28.495030 RX Delay -359 -> 252, step: 8
6586 04:41:28.501911 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6587 04:41:28.505536 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6588 04:41:28.508921 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6589 04:41:28.515296 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6590 04:41:28.518440 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6591 04:41:28.521775 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6592 04:41:28.525102 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6593 04:41:28.531880 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6594 04:41:28.534997 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6595 04:41:28.538263 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6596 04:41:28.541502 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6597 04:41:28.548466 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6598 04:41:28.551557 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6599 04:41:28.554843 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6600 04:41:28.558435 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6601 04:41:28.564857 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6602 04:41:28.564941 ==
6603 04:41:28.568123 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 04:41:28.571491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 04:41:28.571565 ==
6606 04:41:28.571636 DQS Delay:
6607 04:41:28.574895 DQS0 = 60, DQS1 = 72
6608 04:41:28.574965 DQM Delay:
6609 04:41:28.578085 DQM0 = 11, DQM1 = 16
6610 04:41:28.578155 DQ Delay:
6611 04:41:28.581379 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6612 04:41:28.584509 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6613 04:41:28.588127 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6614 04:41:28.591327 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6615 04:41:28.591402
6616 04:41:28.591464
6617 04:41:28.597992 [DQSOSCAuto] RK1, (LSB)MR18= 0xd188, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 384 ps
6618 04:41:28.601175 CH0 RK1: MR19=C0C, MR18=D188
6619 04:41:28.607785 CH0_RK1: MR19=0xC0C, MR18=0xD188, DQSOSC=384, MR23=63, INC=400, DEC=267
6620 04:41:28.611006 [RxdqsGatingPostProcess] freq 400
6621 04:41:28.617860 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6622 04:41:28.621351 best DQS0 dly(2T, 0.5T) = (0, 10)
6623 04:41:28.621448 best DQS1 dly(2T, 0.5T) = (0, 10)
6624 04:41:28.624586 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6625 04:41:28.627946 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6626 04:41:28.630925 best DQS0 dly(2T, 0.5T) = (0, 10)
6627 04:41:28.634505 best DQS1 dly(2T, 0.5T) = (0, 10)
6628 04:41:28.637771 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6629 04:41:28.641249 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6630 04:41:28.644239 Pre-setting of DQS Precalculation
6631 04:41:28.651065 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6632 04:41:28.651141 ==
6633 04:41:28.654253 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 04:41:28.657433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 04:41:28.657519 ==
6636 04:41:28.664379 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6637 04:41:28.670731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6638 04:41:28.670806 [CA 0] Center 36 (8~64) winsize 57
6639 04:41:28.674259 [CA 1] Center 36 (8~64) winsize 57
6640 04:41:28.677555 [CA 2] Center 36 (8~64) winsize 57
6641 04:41:28.680764 [CA 3] Center 36 (8~64) winsize 57
6642 04:41:28.683991 [CA 4] Center 36 (8~64) winsize 57
6643 04:41:28.687362 [CA 5] Center 36 (8~64) winsize 57
6644 04:41:28.687442
6645 04:41:28.690595 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6646 04:41:28.690665
6647 04:41:28.694127 [CATrainingPosCal] consider 1 rank data
6648 04:41:28.697393 u2DelayCellTimex100 = 270/100 ps
6649 04:41:28.700776 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 04:41:28.703841 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 04:41:28.710835 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 04:41:28.714102 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 04:41:28.717413 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 04:41:28.720775 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 04:41:28.720848
6656 04:41:28.723816 CA PerBit enable=1, Macro0, CA PI delay=36
6657 04:41:28.723888
6658 04:41:28.727290 [CBTSetCACLKResult] CA Dly = 36
6659 04:41:28.727361 CS Dly: 1 (0~32)
6660 04:41:28.730502 ==
6661 04:41:28.730572 Dram Type= 6, Freq= 0, CH_1, rank 1
6662 04:41:28.737325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 04:41:28.737410 ==
6664 04:41:28.740424 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6665 04:41:28.747219 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6666 04:41:28.750435 [CA 0] Center 36 (8~64) winsize 57
6667 04:41:28.753992 [CA 1] Center 36 (8~64) winsize 57
6668 04:41:28.756946 [CA 2] Center 36 (8~64) winsize 57
6669 04:41:28.760498 [CA 3] Center 36 (8~64) winsize 57
6670 04:41:28.763856 [CA 4] Center 36 (8~64) winsize 57
6671 04:41:28.766846 [CA 5] Center 36 (8~64) winsize 57
6672 04:41:28.766963
6673 04:41:28.770324 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6674 04:41:28.770477
6675 04:41:28.773486 [CATrainingPosCal] consider 2 rank data
6676 04:41:28.776712 u2DelayCellTimex100 = 270/100 ps
6677 04:41:28.780040 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 04:41:28.783595 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 04:41:28.787023 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 04:41:28.790297 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 04:41:28.793601 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 04:41:28.800149 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 04:41:28.800299
6684 04:41:28.803322 CA PerBit enable=1, Macro0, CA PI delay=36
6685 04:41:28.803401
6686 04:41:28.806626 [CBTSetCACLKResult] CA Dly = 36
6687 04:41:28.806698 CS Dly: 1 (0~32)
6688 04:41:28.806766
6689 04:41:28.810095 ----->DramcWriteLeveling(PI) begin...
6690 04:41:28.810174 ==
6691 04:41:28.813650 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 04:41:28.819972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 04:41:28.820063 ==
6694 04:41:28.820151 Write leveling (Byte 0): 40 => 8
6695 04:41:28.823352 Write leveling (Byte 1): 40 => 8
6696 04:41:28.826792 DramcWriteLeveling(PI) end<-----
6697 04:41:28.826877
6698 04:41:28.826943 ==
6699 04:41:28.830090 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 04:41:28.836713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 04:41:28.836798 ==
6702 04:41:28.839817 [Gating] SW mode calibration
6703 04:41:28.846859 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6704 04:41:28.850262 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6705 04:41:28.856689 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6706 04:41:28.859921 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6707 04:41:28.863090 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6708 04:41:28.869943 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6709 04:41:28.872944 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 04:41:28.876582 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 04:41:28.882922 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 04:41:28.886055 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 04:41:28.889489 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6714 04:41:28.892825 Total UI for P1: 0, mck2ui 16
6715 04:41:28.896209 best dqsien dly found for B0: ( 0, 14, 24)
6716 04:41:28.899398 Total UI for P1: 0, mck2ui 16
6717 04:41:28.902665 best dqsien dly found for B1: ( 0, 14, 24)
6718 04:41:28.906112 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6719 04:41:28.909346 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6720 04:41:28.909451
6721 04:41:28.913090 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6722 04:41:28.919477 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6723 04:41:28.919562 [Gating] SW calibration Done
6724 04:41:28.919630 ==
6725 04:41:28.922762 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 04:41:28.929755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 04:41:28.929839 ==
6728 04:41:28.929906 RX Vref Scan: 0
6729 04:41:28.929981
6730 04:41:28.932882 RX Vref 0 -> 0, step: 1
6731 04:41:28.932965
6732 04:41:28.936056 RX Delay -410 -> 252, step: 16
6733 04:41:28.939276 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6734 04:41:28.942797 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6735 04:41:28.949266 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6736 04:41:28.952500 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6737 04:41:28.955846 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6738 04:41:28.959442 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6739 04:41:28.966081 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6740 04:41:28.969328 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6741 04:41:28.972527 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6742 04:41:28.975641 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6743 04:41:28.982428 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6744 04:41:28.985743 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6745 04:41:28.989221 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6746 04:41:28.995657 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6747 04:41:28.998923 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6748 04:41:29.002172 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6749 04:41:29.002255 ==
6750 04:41:29.005349 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 04:41:29.009166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 04:41:29.009250 ==
6753 04:41:29.012273 DQS Delay:
6754 04:41:29.012356 DQS0 = 51, DQS1 = 67
6755 04:41:29.015512 DQM Delay:
6756 04:41:29.015593 DQM0 = 12, DQM1 = 19
6757 04:41:29.018958 DQ Delay:
6758 04:41:29.019039 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6759 04:41:29.022096 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6760 04:41:29.025261 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6761 04:41:29.028647 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6762 04:41:29.028728
6763 04:41:29.028792
6764 04:41:29.028850 ==
6765 04:41:29.032168 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 04:41:29.038597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 04:41:29.038683 ==
6768 04:41:29.038751
6769 04:41:29.038813
6770 04:41:29.041897 TX Vref Scan disable
6771 04:41:29.041995 == TX Byte 0 ==
6772 04:41:29.045209 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 04:41:29.048820 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 04:41:29.051965 == TX Byte 1 ==
6775 04:41:29.055288 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 04:41:29.058686 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 04:41:29.062208 ==
6778 04:41:29.062290 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 04:41:29.068900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 04:41:29.068983 ==
6781 04:41:29.069048
6782 04:41:29.069108
6783 04:41:29.072192 TX Vref Scan disable
6784 04:41:29.072274 == TX Byte 0 ==
6785 04:41:29.075343 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 04:41:29.078883 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 04:41:29.082063 == TX Byte 1 ==
6788 04:41:29.085200 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 04:41:29.088493 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 04:41:29.091772
6791 04:41:29.091854 [DATLAT]
6792 04:41:29.091919 Freq=400, CH1 RK0
6793 04:41:29.091980
6794 04:41:29.095454 DATLAT Default: 0xf
6795 04:41:29.095536 0, 0xFFFF, sum = 0
6796 04:41:29.098656 1, 0xFFFF, sum = 0
6797 04:41:29.098740 2, 0xFFFF, sum = 0
6798 04:41:29.101785 3, 0xFFFF, sum = 0
6799 04:41:29.101868 4, 0xFFFF, sum = 0
6800 04:41:29.105043 5, 0xFFFF, sum = 0
6801 04:41:29.108572 6, 0xFFFF, sum = 0
6802 04:41:29.108657 7, 0xFFFF, sum = 0
6803 04:41:29.111854 8, 0xFFFF, sum = 0
6804 04:41:29.111938 9, 0xFFFF, sum = 0
6805 04:41:29.115145 10, 0xFFFF, sum = 0
6806 04:41:29.115252 11, 0xFFFF, sum = 0
6807 04:41:29.118512 12, 0xFFFF, sum = 0
6808 04:41:29.118658 13, 0x0, sum = 1
6809 04:41:29.121589 14, 0x0, sum = 2
6810 04:41:29.121708 15, 0x0, sum = 3
6811 04:41:29.124960 16, 0x0, sum = 4
6812 04:41:29.125069 best_step = 14
6813 04:41:29.125161
6814 04:41:29.125262 ==
6815 04:41:29.128342 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 04:41:29.131475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 04:41:29.131552 ==
6818 04:41:29.135121 RX Vref Scan: 1
6819 04:41:29.135204
6820 04:41:29.138153 RX Vref 0 -> 0, step: 1
6821 04:41:29.138235
6822 04:41:29.138299 RX Delay -375 -> 252, step: 8
6823 04:41:29.141657
6824 04:41:29.141739 Set Vref, RX VrefLevel [Byte0]: 54
6825 04:41:29.145047 [Byte1]: 53
6826 04:41:29.150804
6827 04:41:29.150886 Final RX Vref Byte 0 = 54 to rank0
6828 04:41:29.153948 Final RX Vref Byte 1 = 53 to rank0
6829 04:41:29.157220 Final RX Vref Byte 0 = 54 to rank1
6830 04:41:29.160449 Final RX Vref Byte 1 = 53 to rank1==
6831 04:41:29.163860 Dram Type= 6, Freq= 0, CH_1, rank 0
6832 04:41:29.170392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 04:41:29.170476 ==
6834 04:41:29.170541 DQS Delay:
6835 04:41:29.174057 DQS0 = 52, DQS1 = 64
6836 04:41:29.174140 DQM Delay:
6837 04:41:29.174205 DQM0 = 9, DQM1 = 10
6838 04:41:29.177355 DQ Delay:
6839 04:41:29.180615 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6840 04:41:29.180698 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6841 04:41:29.183968 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6842 04:41:29.187312 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6843 04:41:29.187395
6844 04:41:29.187460
6845 04:41:29.197076 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6846 04:41:29.200313 CH1 RK0: MR19=C0C, MR18=5D71
6847 04:41:29.206775 CH1_RK0: MR19=0xC0C, MR18=0x5D71, DQSOSC=395, MR23=63, INC=378, DEC=252
6848 04:41:29.206880 ==
6849 04:41:29.210099 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 04:41:29.213610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 04:41:29.213732 ==
6852 04:41:29.216791 [Gating] SW mode calibration
6853 04:41:29.223451 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6854 04:41:29.226649 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6855 04:41:29.233732 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6856 04:41:29.237089 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6857 04:41:29.240332 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6858 04:41:29.246968 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6859 04:41:29.250198 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 04:41:29.253465 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 04:41:29.260015 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 04:41:29.263418 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 04:41:29.266726 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6864 04:41:29.270063 Total UI for P1: 0, mck2ui 16
6865 04:41:29.273318 best dqsien dly found for B0: ( 0, 14, 24)
6866 04:41:29.276499 Total UI for P1: 0, mck2ui 16
6867 04:41:29.279851 best dqsien dly found for B1: ( 0, 14, 24)
6868 04:41:29.283130 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6869 04:41:29.286489 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6870 04:41:29.290131
6871 04:41:29.293239 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6872 04:41:29.296475 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6873 04:41:29.300099 [Gating] SW calibration Done
6874 04:41:29.300202 ==
6875 04:41:29.303153 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 04:41:29.306659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 04:41:29.306764 ==
6878 04:41:29.306862 RX Vref Scan: 0
6879 04:41:29.306954
6880 04:41:29.309946 RX Vref 0 -> 0, step: 1
6881 04:41:29.310046
6882 04:41:29.313247 RX Delay -410 -> 252, step: 16
6883 04:41:29.316520 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6884 04:41:29.323257 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6885 04:41:29.326291 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6886 04:41:29.329771 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6887 04:41:29.333165 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6888 04:41:29.339726 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6889 04:41:29.342989 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6890 04:41:29.346285 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6891 04:41:29.349531 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6892 04:41:29.356383 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6893 04:41:29.359709 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6894 04:41:29.363103 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6895 04:41:29.366332 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6896 04:41:29.373000 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6897 04:41:29.376006 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6898 04:41:29.379518 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6899 04:41:29.379637 ==
6900 04:41:29.382793 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 04:41:29.389178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 04:41:29.389294 ==
6903 04:41:29.389395 DQS Delay:
6904 04:41:29.392692 DQS0 = 59, DQS1 = 59
6905 04:41:29.392774 DQM Delay:
6906 04:41:29.392841 DQM0 = 19, DQM1 = 14
6907 04:41:29.395785 DQ Delay:
6908 04:41:29.399244 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6909 04:41:29.402625 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6910 04:41:29.402728 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6911 04:41:29.406103 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6912 04:41:29.409236
6913 04:41:29.409338
6914 04:41:29.409435 ==
6915 04:41:29.412456 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 04:41:29.415937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 04:41:29.416026 ==
6918 04:41:29.416093
6919 04:41:29.416155
6920 04:41:29.419175 TX Vref Scan disable
6921 04:41:29.419260 == TX Byte 0 ==
6922 04:41:29.422408 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6923 04:41:29.429290 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6924 04:41:29.429377 == TX Byte 1 ==
6925 04:41:29.432568 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6926 04:41:29.439033 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6927 04:41:29.439146 ==
6928 04:41:29.442271 Dram Type= 6, Freq= 0, CH_1, rank 1
6929 04:41:29.445683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6930 04:41:29.445797 ==
6931 04:41:29.445909
6932 04:41:29.446019
6933 04:41:29.449141 TX Vref Scan disable
6934 04:41:29.449247 == TX Byte 0 ==
6935 04:41:29.455594 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6936 04:41:29.458856 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6937 04:41:29.458974 == TX Byte 1 ==
6938 04:41:29.462143 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6939 04:41:29.468831 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6940 04:41:29.468941
6941 04:41:29.469036 [DATLAT]
6942 04:41:29.472153 Freq=400, CH1 RK1
6943 04:41:29.472260
6944 04:41:29.472354 DATLAT Default: 0xe
6945 04:41:29.475192 0, 0xFFFF, sum = 0
6946 04:41:29.475301 1, 0xFFFF, sum = 0
6947 04:41:29.478404 2, 0xFFFF, sum = 0
6948 04:41:29.478522 3, 0xFFFF, sum = 0
6949 04:41:29.481717 4, 0xFFFF, sum = 0
6950 04:41:29.481833 5, 0xFFFF, sum = 0
6951 04:41:29.485042 6, 0xFFFF, sum = 0
6952 04:41:29.485155 7, 0xFFFF, sum = 0
6953 04:41:29.488544 8, 0xFFFF, sum = 0
6954 04:41:29.488631 9, 0xFFFF, sum = 0
6955 04:41:29.491655 10, 0xFFFF, sum = 0
6956 04:41:29.491772 11, 0xFFFF, sum = 0
6957 04:41:29.494991 12, 0xFFFF, sum = 0
6958 04:41:29.498400 13, 0x0, sum = 1
6959 04:41:29.498516 14, 0x0, sum = 2
6960 04:41:29.498623 15, 0x0, sum = 3
6961 04:41:29.501709 16, 0x0, sum = 4
6962 04:41:29.501820 best_step = 14
6963 04:41:29.501914
6964 04:41:29.502004 ==
6965 04:41:29.504759 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 04:41:29.511572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 04:41:29.511693 ==
6968 04:41:29.511799 RX Vref Scan: 0
6969 04:41:29.511901
6970 04:41:29.514652 RX Vref 0 -> 0, step: 1
6971 04:41:29.514768
6972 04:41:29.517963 RX Delay -359 -> 252, step: 8
6973 04:41:29.524822 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6974 04:41:29.528351 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6975 04:41:29.531499 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6976 04:41:29.534709 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6977 04:41:29.541528 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6978 04:41:29.544521 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6979 04:41:29.548099 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6980 04:41:29.554778 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6981 04:41:29.558075 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6982 04:41:29.561080 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6983 04:41:29.564493 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6984 04:41:29.571309 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6985 04:41:29.574543 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6986 04:41:29.577735 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6987 04:41:29.581105 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6988 04:41:29.588004 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6989 04:41:29.588089 ==
6990 04:41:29.591175 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 04:41:29.594467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 04:41:29.594543 ==
6993 04:41:29.594617 DQS Delay:
6994 04:41:29.597793 DQS0 = 60, DQS1 = 64
6995 04:41:29.597869 DQM Delay:
6996 04:41:29.601245 DQM0 = 12, DQM1 = 10
6997 04:41:29.601317 DQ Delay:
6998 04:41:29.604138 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6999 04:41:29.607472 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7000 04:41:29.610938 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7001 04:41:29.613985 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7002 04:41:29.614094
7003 04:41:29.614187
7004 04:41:29.620935 [DQSOSCAuto] RK1, (LSB)MR18= 0x83b4, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
7005 04:41:29.624202 CH1 RK1: MR19=C0C, MR18=83B4
7006 04:41:29.630973 CH1_RK1: MR19=0xC0C, MR18=0x83B4, DQSOSC=387, MR23=63, INC=394, DEC=262
7007 04:41:29.634296 [RxdqsGatingPostProcess] freq 400
7008 04:41:29.640743 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7009 04:41:29.644073 best DQS0 dly(2T, 0.5T) = (0, 10)
7010 04:41:29.647397 best DQS1 dly(2T, 0.5T) = (0, 10)
7011 04:41:29.650655 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7012 04:41:29.653911 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7013 04:41:29.653993 best DQS0 dly(2T, 0.5T) = (0, 10)
7014 04:41:29.657437 best DQS1 dly(2T, 0.5T) = (0, 10)
7015 04:41:29.660743 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7016 04:41:29.663997 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7017 04:41:29.667340 Pre-setting of DQS Precalculation
7018 04:41:29.673586 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7019 04:41:29.680275 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7020 04:41:29.686899 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7021 04:41:29.686985
7022 04:41:29.687049
7023 04:41:29.690203 [Calibration Summary] 800 Mbps
7024 04:41:29.690286 CH 0, Rank 0
7025 04:41:29.693421 SW Impedance : PASS
7026 04:41:29.697181 DUTY Scan : NO K
7027 04:41:29.697302 ZQ Calibration : PASS
7028 04:41:29.700322 Jitter Meter : NO K
7029 04:41:29.703366 CBT Training : PASS
7030 04:41:29.703483 Write leveling : PASS
7031 04:41:29.706829 RX DQS gating : PASS
7032 04:41:29.709824 RX DQ/DQS(RDDQC) : PASS
7033 04:41:29.709943 TX DQ/DQS : PASS
7034 04:41:29.713267 RX DATLAT : PASS
7035 04:41:29.716742 RX DQ/DQS(Engine): PASS
7036 04:41:29.716856 TX OE : NO K
7037 04:41:29.720101 All Pass.
7038 04:41:29.720218
7039 04:41:29.720321 CH 0, Rank 1
7040 04:41:29.723519 SW Impedance : PASS
7041 04:41:29.723602 DUTY Scan : NO K
7042 04:41:29.726458 ZQ Calibration : PASS
7043 04:41:29.729884 Jitter Meter : NO K
7044 04:41:29.729989 CBT Training : PASS
7045 04:41:29.733202 Write leveling : NO K
7046 04:41:29.736540 RX DQS gating : PASS
7047 04:41:29.736649 RX DQ/DQS(RDDQC) : PASS
7048 04:41:29.739416 TX DQ/DQS : PASS
7049 04:41:29.742714 RX DATLAT : PASS
7050 04:41:29.742792 RX DQ/DQS(Engine): PASS
7051 04:41:29.746103 TX OE : NO K
7052 04:41:29.746175 All Pass.
7053 04:41:29.746240
7054 04:41:29.749618 CH 1, Rank 0
7055 04:41:29.749694 SW Impedance : PASS
7056 04:41:29.752982 DUTY Scan : NO K
7057 04:41:29.753081 ZQ Calibration : PASS
7058 04:41:29.756187 Jitter Meter : NO K
7059 04:41:29.759328 CBT Training : PASS
7060 04:41:29.759426 Write leveling : PASS
7061 04:41:29.762659 RX DQS gating : PASS
7062 04:41:29.766202 RX DQ/DQS(RDDQC) : PASS
7063 04:41:29.766275 TX DQ/DQS : PASS
7064 04:41:29.769583 RX DATLAT : PASS
7065 04:41:29.772502 RX DQ/DQS(Engine): PASS
7066 04:41:29.772601 TX OE : NO K
7067 04:41:29.775783 All Pass.
7068 04:41:29.775882
7069 04:41:29.775972 CH 1, Rank 1
7070 04:41:29.779019 SW Impedance : PASS
7071 04:41:29.779122 DUTY Scan : NO K
7072 04:41:29.782502 ZQ Calibration : PASS
7073 04:41:29.785666 Jitter Meter : NO K
7074 04:41:29.785747 CBT Training : PASS
7075 04:41:29.789240 Write leveling : NO K
7076 04:41:29.792518 RX DQS gating : PASS
7077 04:41:29.792597 RX DQ/DQS(RDDQC) : PASS
7078 04:41:29.795755 TX DQ/DQS : PASS
7079 04:41:29.799060 RX DATLAT : PASS
7080 04:41:29.799159 RX DQ/DQS(Engine): PASS
7081 04:41:29.802470 TX OE : NO K
7082 04:41:29.802568 All Pass.
7083 04:41:29.802659
7084 04:41:29.805834 DramC Write-DBI off
7085 04:41:29.809042 PER_BANK_REFRESH: Hybrid Mode
7086 04:41:29.809144 TX_TRACKING: ON
7087 04:41:29.819109 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7088 04:41:29.822376 [FAST_K] Save calibration result to emmc
7089 04:41:29.825754 dramc_set_vcore_voltage set vcore to 725000
7090 04:41:29.829062 Read voltage for 1600, 0
7091 04:41:29.829163 Vio18 = 0
7092 04:41:29.829255 Vcore = 725000
7093 04:41:29.832288 Vdram = 0
7094 04:41:29.832395 Vddq = 0
7095 04:41:29.832501 Vmddr = 0
7096 04:41:29.838979 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7097 04:41:29.841858 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7098 04:41:29.845119 MEM_TYPE=3, freq_sel=13
7099 04:41:29.848756 sv_algorithm_assistance_LP4_3733
7100 04:41:29.851806 ============ PULL DRAM RESETB DOWN ============
7101 04:41:29.855444 ========== PULL DRAM RESETB DOWN end =========
7102 04:41:29.861843 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7103 04:41:29.865147 ===================================
7104 04:41:29.868369 LPDDR4 DRAM CONFIGURATION
7105 04:41:29.872013 ===================================
7106 04:41:29.872108 EX_ROW_EN[0] = 0x0
7107 04:41:29.875089 EX_ROW_EN[1] = 0x0
7108 04:41:29.875184 LP4Y_EN = 0x0
7109 04:41:29.878717 WORK_FSP = 0x1
7110 04:41:29.878820 WL = 0x5
7111 04:41:29.881964 RL = 0x5
7112 04:41:29.882049 BL = 0x2
7113 04:41:29.885004 RPST = 0x0
7114 04:41:29.885107 RD_PRE = 0x0
7115 04:41:29.888387 WR_PRE = 0x1
7116 04:41:29.888505 WR_PST = 0x1
7117 04:41:29.891678 DBI_WR = 0x0
7118 04:41:29.891790 DBI_RD = 0x0
7119 04:41:29.895108 OTF = 0x1
7120 04:41:29.898465 ===================================
7121 04:41:29.901571 ===================================
7122 04:41:29.901680 ANA top config
7123 04:41:29.904966 ===================================
7124 04:41:29.908129 DLL_ASYNC_EN = 0
7125 04:41:29.911404 ALL_SLAVE_EN = 0
7126 04:41:29.914803 NEW_RANK_MODE = 1
7127 04:41:29.914878 DLL_IDLE_MODE = 1
7128 04:41:29.918123 LP45_APHY_COMB_EN = 1
7129 04:41:29.921576 TX_ODT_DIS = 0
7130 04:41:29.924726 NEW_8X_MODE = 1
7131 04:41:29.927885 ===================================
7132 04:41:29.931523 ===================================
7133 04:41:29.934530 data_rate = 3200
7134 04:41:29.937759 CKR = 1
7135 04:41:29.937841 DQ_P2S_RATIO = 8
7136 04:41:29.941184 ===================================
7137 04:41:29.944295 CA_P2S_RATIO = 8
7138 04:41:29.947599 DQ_CA_OPEN = 0
7139 04:41:29.950939 DQ_SEMI_OPEN = 0
7140 04:41:29.954391 CA_SEMI_OPEN = 0
7141 04:41:29.957703 CA_FULL_RATE = 0
7142 04:41:29.957782 DQ_CKDIV4_EN = 0
7143 04:41:29.961070 CA_CKDIV4_EN = 0
7144 04:41:29.964411 CA_PREDIV_EN = 0
7145 04:41:29.967414 PH8_DLY = 12
7146 04:41:29.970673 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7147 04:41:29.973915 DQ_AAMCK_DIV = 4
7148 04:41:29.973990 CA_AAMCK_DIV = 4
7149 04:41:29.977556 CA_ADMCK_DIV = 4
7150 04:41:29.980575 DQ_TRACK_CA_EN = 0
7151 04:41:29.984170 CA_PICK = 1600
7152 04:41:29.987168 CA_MCKIO = 1600
7153 04:41:29.990546 MCKIO_SEMI = 0
7154 04:41:29.994146 PLL_FREQ = 3068
7155 04:41:29.997453 DQ_UI_PI_RATIO = 32
7156 04:41:29.997545 CA_UI_PI_RATIO = 0
7157 04:41:30.000501 ===================================
7158 04:41:30.004009 ===================================
7159 04:41:30.007292 memory_type:LPDDR4
7160 04:41:30.010394 GP_NUM : 10
7161 04:41:30.010500 SRAM_EN : 1
7162 04:41:30.013711 MD32_EN : 0
7163 04:41:30.017206 ===================================
7164 04:41:30.020465 [ANA_INIT] >>>>>>>>>>>>>>
7165 04:41:30.023721 <<<<<< [CONFIGURE PHASE]: ANA_TX
7166 04:41:30.026985 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7167 04:41:30.030275 ===================================
7168 04:41:30.030355 data_rate = 3200,PCW = 0X7600
7169 04:41:30.033633 ===================================
7170 04:41:30.037095 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7171 04:41:30.043562 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7172 04:41:30.050076 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7173 04:41:30.053536 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7174 04:41:30.056825 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7175 04:41:30.060295 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7176 04:41:30.063450 [ANA_INIT] flow start
7177 04:41:30.066557 [ANA_INIT] PLL >>>>>>>>
7178 04:41:30.066657 [ANA_INIT] PLL <<<<<<<<
7179 04:41:30.070039 [ANA_INIT] MIDPI >>>>>>>>
7180 04:41:30.073464 [ANA_INIT] MIDPI <<<<<<<<
7181 04:41:30.073571 [ANA_INIT] DLL >>>>>>>>
7182 04:41:30.076734 [ANA_INIT] DLL <<<<<<<<
7183 04:41:30.080053 [ANA_INIT] flow end
7184 04:41:30.083539 ============ LP4 DIFF to SE enter ============
7185 04:41:30.086681 ============ LP4 DIFF to SE exit ============
7186 04:41:30.089977 [ANA_INIT] <<<<<<<<<<<<<
7187 04:41:30.093437 [Flow] Enable top DCM control >>>>>
7188 04:41:30.096708 [Flow] Enable top DCM control <<<<<
7189 04:41:30.100050 Enable DLL master slave shuffle
7190 04:41:30.103394 ==============================================================
7191 04:41:30.106543 Gating Mode config
7192 04:41:30.113054 ==============================================================
7193 04:41:30.113164 Config description:
7194 04:41:30.123107 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7195 04:41:30.129863 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7196 04:41:30.133029 SELPH_MODE 0: By rank 1: By Phase
7197 04:41:30.139463 ==============================================================
7198 04:41:30.142756 GAT_TRACK_EN = 1
7199 04:41:30.146028 RX_GATING_MODE = 2
7200 04:41:30.149494 RX_GATING_TRACK_MODE = 2
7201 04:41:30.152806 SELPH_MODE = 1
7202 04:41:30.156091 PICG_EARLY_EN = 1
7203 04:41:30.159446 VALID_LAT_VALUE = 1
7204 04:41:30.162768 ==============================================================
7205 04:41:30.166214 Enter into Gating configuration >>>>
7206 04:41:30.169676 Exit from Gating configuration <<<<
7207 04:41:30.172799 Enter into DVFS_PRE_config >>>>>
7208 04:41:30.186365 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7209 04:41:30.186459 Exit from DVFS_PRE_config <<<<<
7210 04:41:30.189323 Enter into PICG configuration >>>>
7211 04:41:30.192557 Exit from PICG configuration <<<<
7212 04:41:30.195762 [RX_INPUT] configuration >>>>>
7213 04:41:30.199080 [RX_INPUT] configuration <<<<<
7214 04:41:30.205835 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7215 04:41:30.209120 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7216 04:41:30.215626 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7217 04:41:30.222258 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7218 04:41:30.229136 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7219 04:41:30.235522 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7220 04:41:30.238968 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7221 04:41:30.242099 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7222 04:41:30.245636 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7223 04:41:30.252430 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7224 04:41:30.255331 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7225 04:41:30.258646 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7226 04:41:30.262054 ===================================
7227 04:41:30.265397 LPDDR4 DRAM CONFIGURATION
7228 04:41:30.268825 ===================================
7229 04:41:30.272182 EX_ROW_EN[0] = 0x0
7230 04:41:30.272263 EX_ROW_EN[1] = 0x0
7231 04:41:30.275232 LP4Y_EN = 0x0
7232 04:41:30.275311 WORK_FSP = 0x1
7233 04:41:30.278647 WL = 0x5
7234 04:41:30.278755 RL = 0x5
7235 04:41:30.282201 BL = 0x2
7236 04:41:30.282291 RPST = 0x0
7237 04:41:30.285256 RD_PRE = 0x0
7238 04:41:30.285341 WR_PRE = 0x1
7239 04:41:30.288485 WR_PST = 0x1
7240 04:41:30.288610 DBI_WR = 0x0
7241 04:41:30.292085 DBI_RD = 0x0
7242 04:41:30.292197 OTF = 0x1
7243 04:41:30.295184 ===================================
7244 04:41:30.301862 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7245 04:41:30.305186 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7246 04:41:30.308309 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7247 04:41:30.311522 ===================================
7248 04:41:30.315048 LPDDR4 DRAM CONFIGURATION
7249 04:41:30.318432 ===================================
7250 04:41:30.321595 EX_ROW_EN[0] = 0x10
7251 04:41:30.321672 EX_ROW_EN[1] = 0x0
7252 04:41:30.324836 LP4Y_EN = 0x0
7253 04:41:30.324911 WORK_FSP = 0x1
7254 04:41:30.328334 WL = 0x5
7255 04:41:30.328434 RL = 0x5
7256 04:41:30.331491 BL = 0x2
7257 04:41:30.331594 RPST = 0x0
7258 04:41:30.334974 RD_PRE = 0x0
7259 04:41:30.335075 WR_PRE = 0x1
7260 04:41:30.338245 WR_PST = 0x1
7261 04:41:30.338322 DBI_WR = 0x0
7262 04:41:30.341613 DBI_RD = 0x0
7263 04:41:30.341726 OTF = 0x1
7264 04:41:30.344672 ===================================
7265 04:41:30.351475 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7266 04:41:30.351571 ==
7267 04:41:30.354656 Dram Type= 6, Freq= 0, CH_0, rank 0
7268 04:41:30.361316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7269 04:41:30.361426 ==
7270 04:41:30.361535 [Duty_Offset_Calibration]
7271 04:41:30.364867 B0:2 B1:0 CA:3
7272 04:41:30.364941
7273 04:41:30.368098 [DutyScan_Calibration_Flow] k_type=0
7274 04:41:30.377263
7275 04:41:30.377365 ==CLK 0==
7276 04:41:30.380556 Final CLK duty delay cell = 0
7277 04:41:30.383530 [0] MAX Duty = 5031%(X100), DQS PI = 12
7278 04:41:30.387251 [0] MIN Duty = 4907%(X100), DQS PI = 6
7279 04:41:30.387327 [0] AVG Duty = 4969%(X100)
7280 04:41:30.390501
7281 04:41:30.393903 CH0 CLK Duty spec in!! Max-Min= 124%
7282 04:41:30.397087 [DutyScan_Calibration_Flow] ====Done====
7283 04:41:30.397191
7284 04:41:30.400320 [DutyScan_Calibration_Flow] k_type=1
7285 04:41:30.417075
7286 04:41:30.417179 ==DQS 0 ==
7287 04:41:30.420040 Final DQS duty delay cell = 0
7288 04:41:30.423284 [0] MAX Duty = 5125%(X100), DQS PI = 30
7289 04:41:30.426617 [0] MIN Duty = 4907%(X100), DQS PI = 0
7290 04:41:30.430314 [0] AVG Duty = 5016%(X100)
7291 04:41:30.430446
7292 04:41:30.430572 ==DQS 1 ==
7293 04:41:30.433636 Final DQS duty delay cell = 0
7294 04:41:30.436744 [0] MAX Duty = 5156%(X100), DQS PI = 32
7295 04:41:30.440269 [0] MIN Duty = 5031%(X100), DQS PI = 12
7296 04:41:30.443672 [0] AVG Duty = 5093%(X100)
7297 04:41:30.443838
7298 04:41:30.446901 CH0 DQS 0 Duty spec in!! Max-Min= 218%
7299 04:41:30.447176
7300 04:41:30.450073 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7301 04:41:30.453023 [DutyScan_Calibration_Flow] ====Done====
7302 04:41:30.453095
7303 04:41:30.456474 [DutyScan_Calibration_Flow] k_type=3
7304 04:41:30.474585
7305 04:41:30.474666 ==DQM 0 ==
7306 04:41:30.477896 Final DQM duty delay cell = 0
7307 04:41:30.481230 [0] MAX Duty = 5187%(X100), DQS PI = 32
7308 04:41:30.484572 [0] MIN Duty = 4875%(X100), DQS PI = 0
7309 04:41:30.488018 [0] AVG Duty = 5031%(X100)
7310 04:41:30.488099
7311 04:41:30.488163 ==DQM 1 ==
7312 04:41:30.490991 Final DQM duty delay cell = 4
7313 04:41:30.494276 [4] MAX Duty = 5187%(X100), DQS PI = 60
7314 04:41:30.497883 [4] MIN Duty = 5031%(X100), DQS PI = 20
7315 04:41:30.501221 [4] AVG Duty = 5109%(X100)
7316 04:41:30.501354
7317 04:41:30.504584 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7318 04:41:30.504694
7319 04:41:30.507728 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7320 04:41:30.511306 [DutyScan_Calibration_Flow] ====Done====
7321 04:41:30.511474
7322 04:41:30.513999 [DutyScan_Calibration_Flow] k_type=2
7323 04:41:30.530758
7324 04:41:30.530959 ==DQ 0 ==
7325 04:41:30.534104 Final DQ duty delay cell = -4
7326 04:41:30.537360 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7327 04:41:30.540863 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7328 04:41:30.544173 [-4] AVG Duty = 4953%(X100)
7329 04:41:30.544273
7330 04:41:30.544362 ==DQ 1 ==
7331 04:41:30.547338 Final DQ duty delay cell = 0
7332 04:41:30.550585 [0] MAX Duty = 5156%(X100), DQS PI = 60
7333 04:41:30.553865 [0] MIN Duty = 5000%(X100), DQS PI = 16
7334 04:41:30.557231 [0] AVG Duty = 5078%(X100)
7335 04:41:30.557303
7336 04:41:30.560634 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7337 04:41:30.560708
7338 04:41:30.564004 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7339 04:41:30.567314 [DutyScan_Calibration_Flow] ====Done====
7340 04:41:30.567410 ==
7341 04:41:30.570355 Dram Type= 6, Freq= 0, CH_1, rank 0
7342 04:41:30.573950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7343 04:41:30.574057 ==
7344 04:41:30.576977 [Duty_Offset_Calibration]
7345 04:41:30.577100 B0:1 B1:-2 CA:1
7346 04:41:30.577202
7347 04:41:30.580329 [DutyScan_Calibration_Flow] k_type=0
7348 04:41:30.591267
7349 04:41:30.591355 ==CLK 0==
7350 04:41:30.594619 Final CLK duty delay cell = 0
7351 04:41:30.597735 [0] MAX Duty = 5062%(X100), DQS PI = 20
7352 04:41:30.601081 [0] MIN Duty = 4844%(X100), DQS PI = 58
7353 04:41:30.604400 [0] AVG Duty = 4953%(X100)
7354 04:41:30.604504
7355 04:41:30.607788 CH1 CLK Duty spec in!! Max-Min= 218%
7356 04:41:30.611181 [DutyScan_Calibration_Flow] ====Done====
7357 04:41:30.611288
7358 04:41:30.614102 [DutyScan_Calibration_Flow] k_type=1
7359 04:41:30.630716
7360 04:41:30.630802 ==DQS 0 ==
7361 04:41:30.634374 Final DQS duty delay cell = 0
7362 04:41:30.637643 [0] MAX Duty = 5187%(X100), DQS PI = 24
7363 04:41:30.640792 [0] MIN Duty = 5031%(X100), DQS PI = 54
7364 04:41:30.644138 [0] AVG Duty = 5109%(X100)
7365 04:41:30.644242
7366 04:41:30.644329 ==DQS 1 ==
7367 04:41:30.647450 Final DQS duty delay cell = 0
7368 04:41:30.650763 [0] MAX Duty = 5124%(X100), DQS PI = 62
7369 04:41:30.654114 [0] MIN Duty = 4844%(X100), DQS PI = 24
7370 04:41:30.657567 [0] AVG Duty = 4984%(X100)
7371 04:41:30.657678
7372 04:41:30.660811 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7373 04:41:30.660911
7374 04:41:30.663796 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7375 04:41:30.667121 [DutyScan_Calibration_Flow] ====Done====
7376 04:41:30.667287
7377 04:41:30.670508 [DutyScan_Calibration_Flow] k_type=3
7378 04:41:30.687604
7379 04:41:30.687711 ==DQM 0 ==
7380 04:41:30.690988 Final DQM duty delay cell = 0
7381 04:41:30.694444 [0] MAX Duty = 5031%(X100), DQS PI = 26
7382 04:41:30.697709 [0] MIN Duty = 4813%(X100), DQS PI = 56
7383 04:41:30.701173 [0] AVG Duty = 4922%(X100)
7384 04:41:30.701253
7385 04:41:30.701317 ==DQM 1 ==
7386 04:41:30.704307 Final DQM duty delay cell = 0
7387 04:41:30.707900 [0] MAX Duty = 5062%(X100), DQS PI = 34
7388 04:41:30.711403 [0] MIN Duty = 4875%(X100), DQS PI = 24
7389 04:41:30.714348 [0] AVG Duty = 4968%(X100)
7390 04:41:30.714491
7391 04:41:30.717656 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7392 04:41:30.717790
7393 04:41:30.720722 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7394 04:41:30.724183 [DutyScan_Calibration_Flow] ====Done====
7395 04:41:30.724362
7396 04:41:30.727533 [DutyScan_Calibration_Flow] k_type=2
7397 04:41:30.744566
7398 04:41:30.744835 ==DQ 0 ==
7399 04:41:30.747770 Final DQ duty delay cell = 0
7400 04:41:30.751490 [0] MAX Duty = 5093%(X100), DQS PI = 22
7401 04:41:30.754689 [0] MIN Duty = 4907%(X100), DQS PI = 46
7402 04:41:30.755004 [0] AVG Duty = 5000%(X100)
7403 04:41:30.758135
7404 04:41:30.758466 ==DQ 1 ==
7405 04:41:30.761126 Final DQ duty delay cell = 0
7406 04:41:30.764335 [0] MAX Duty = 5125%(X100), DQS PI = 34
7407 04:41:30.767938 [0] MIN Duty = 4969%(X100), DQS PI = 24
7408 04:41:30.768286 [0] AVG Duty = 5047%(X100)
7409 04:41:30.771109
7410 04:41:30.774216 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7411 04:41:30.774475
7412 04:41:30.777843 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7413 04:41:30.781121 [DutyScan_Calibration_Flow] ====Done====
7414 04:41:30.784376 nWR fixed to 30
7415 04:41:30.784703 [ModeRegInit_LP4] CH0 RK0
7416 04:41:30.787877 [ModeRegInit_LP4] CH0 RK1
7417 04:41:30.790919 [ModeRegInit_LP4] CH1 RK0
7418 04:41:30.794319 [ModeRegInit_LP4] CH1 RK1
7419 04:41:30.794688 match AC timing 5
7420 04:41:30.801066 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7421 04:41:30.803926 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7422 04:41:30.807338 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7423 04:41:30.813974 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7424 04:41:30.817387 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7425 04:41:30.817722 [MiockJmeterHQA]
7426 04:41:30.818015
7427 04:41:30.820866 [DramcMiockJmeter] u1RxGatingPI = 0
7428 04:41:30.823836 0 : 4254, 4029
7429 04:41:30.824187 4 : 4257, 4031
7430 04:41:30.827150 8 : 4260, 4031
7431 04:41:30.827500 12 : 4257, 4029
7432 04:41:30.830573 16 : 4258, 4030
7433 04:41:30.830930 20 : 4257, 4029
7434 04:41:30.831250 24 : 4258, 4029
7435 04:41:30.833744 28 : 4257, 4029
7436 04:41:30.834020 32 : 4257, 4030
7437 04:41:30.837268 36 : 4257, 4029
7438 04:41:30.837658 40 : 4257, 4029
7439 04:41:30.840364 44 : 4252, 4027
7440 04:41:30.840745 48 : 4368, 4143
7441 04:41:30.843882 52 : 4257, 4030
7442 04:41:30.844231 56 : 4368, 4140
7443 04:41:30.844560 60 : 4363, 4137
7444 04:41:30.847184 64 : 4252, 4029
7445 04:41:30.847538 68 : 4258, 4030
7446 04:41:30.850240 72 : 4255, 4029
7447 04:41:30.850612 76 : 4255, 4029
7448 04:41:30.853639 80 : 4255, 4029
7449 04:41:30.853921 84 : 4252, 4029
7450 04:41:30.854186 88 : 4253, 4029
7451 04:41:30.857247 92 : 4255, 4029
7452 04:41:30.857513 96 : 4252, 4029
7453 04:41:30.860239 100 : 4255, 4029
7454 04:41:30.860482 104 : 4252, 3636
7455 04:41:30.863453 108 : 4253, 3
7456 04:41:30.863800 112 : 4255, 0
7457 04:41:30.864097 116 : 4252, 0
7458 04:41:30.866808 120 : 4365, 0
7459 04:41:30.867143 124 : 4252, 0
7460 04:41:30.870402 128 : 4255, 0
7461 04:41:30.870689 132 : 4363, 0
7462 04:41:30.870946 136 : 4254, 0
7463 04:41:30.873761 140 : 4255, 0
7464 04:41:30.874106 144 : 4363, 0
7465 04:41:30.877068 148 : 4363, 0
7466 04:41:30.877417 152 : 4252, 0
7467 04:41:30.877725 156 : 4363, 0
7468 04:41:30.880349 160 : 4365, 0
7469 04:41:30.880697 164 : 4255, 0
7470 04:41:30.883554 168 : 4252, 0
7471 04:41:30.883890 172 : 4252, 0
7472 04:41:30.884192 176 : 4252, 0
7473 04:41:30.886703 180 : 4258, 0
7474 04:41:30.887026 184 : 4252, 0
7475 04:41:30.887311 188 : 4254, 0
7476 04:41:30.890341 192 : 4363, 0
7477 04:41:30.890730 196 : 4252, 0
7478 04:41:30.893290 200 : 4254, 0
7479 04:41:30.893647 204 : 4252, 0
7480 04:41:30.893886 208 : 4255, 0
7481 04:41:30.896659 212 : 4252, 0
7482 04:41:30.897009 216 : 4255, 0
7483 04:41:30.900115 220 : 4258, 0
7484 04:41:30.900200 224 : 4363, 0
7485 04:41:30.900267 228 : 4254, 0
7486 04:41:30.903221 232 : 4255, 0
7487 04:41:30.903306 236 : 4253, 1209
7488 04:41:30.906390 240 : 4252, 4029
7489 04:41:30.906475 244 : 4257, 4032
7490 04:41:30.910078 248 : 4361, 4137
7491 04:41:30.910160 252 : 4366, 4140
7492 04:41:30.912979 256 : 4363, 4140
7493 04:41:30.913090 260 : 4252, 4027
7494 04:41:30.916293 264 : 4365, 4140
7495 04:41:30.916373 268 : 4365, 4139
7496 04:41:30.916447 272 : 4252, 4029
7497 04:41:30.919595 276 : 4255, 4029
7498 04:41:30.919670 280 : 4365, 4140
7499 04:41:30.923015 284 : 4250, 4026
7500 04:41:30.923100 288 : 4363, 4139
7501 04:41:30.926168 292 : 4252, 4030
7502 04:41:30.926278 296 : 4255, 4029
7503 04:41:30.929620 300 : 4254, 4029
7504 04:41:30.929695 304 : 4250, 4027
7505 04:41:30.932768 308 : 4258, 4032
7506 04:41:30.932842 312 : 4253, 4027
7507 04:41:30.936094 316 : 4255, 4030
7508 04:41:30.936170 320 : 4255, 4029
7509 04:41:30.939488 324 : 4252, 4029
7510 04:41:30.939564 328 : 4257, 4032
7511 04:41:30.942916 332 : 4255, 4029
7512 04:41:30.943002 336 : 4253, 4029
7513 04:41:30.943076 340 : 4252, 4029
7514 04:41:30.945985 344 : 4257, 4032
7515 04:41:30.946057 348 : 4252, 4029
7516 04:41:30.949333 352 : 4254, 4020
7517 04:41:30.949407 356 : 4252, 2884
7518 04:41:30.953027 360 : 4252, 0
7519 04:41:30.953129
7520 04:41:30.953204 MIOCK jitter meter ch=0
7521 04:41:30.956298
7522 04:41:30.956431 1T = (360-108) = 252 dly cells
7523 04:41:30.962783 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7524 04:41:30.962861 ==
7525 04:41:30.966233 Dram Type= 6, Freq= 0, CH_0, rank 0
7526 04:41:30.969485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 04:41:30.969590 ==
7528 04:41:30.975699 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7529 04:41:30.979440 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7530 04:41:30.985979 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7531 04:41:30.988908 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7532 04:41:30.999672 [CA 0] Center 43 (13~74) winsize 62
7533 04:41:31.002828 [CA 1] Center 43 (13~74) winsize 62
7534 04:41:31.006137 [CA 2] Center 39 (10~68) winsize 59
7535 04:41:31.009897 [CA 3] Center 39 (10~68) winsize 59
7536 04:41:31.013019 [CA 4] Center 36 (7~66) winsize 60
7537 04:41:31.016708 [CA 5] Center 36 (7~66) winsize 60
7538 04:41:31.017278
7539 04:41:31.019935 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7540 04:41:31.020400
7541 04:41:31.023246 [CATrainingPosCal] consider 1 rank data
7542 04:41:31.026716 u2DelayCellTimex100 = 258/100 ps
7543 04:41:31.030299 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7544 04:41:31.037346 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7545 04:41:31.040282 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7546 04:41:31.043445 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7547 04:41:31.046738 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7548 04:41:31.050260 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7549 04:41:31.050725
7550 04:41:31.053461 CA PerBit enable=1, Macro0, CA PI delay=36
7551 04:41:31.053952
7552 04:41:31.057047 [CBTSetCACLKResult] CA Dly = 36
7553 04:41:31.059970 CS Dly: 11 (0~42)
7554 04:41:31.063265 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7555 04:41:31.066351 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7556 04:41:31.066820 ==
7557 04:41:31.069739 Dram Type= 6, Freq= 0, CH_0, rank 1
7558 04:41:31.076790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7559 04:41:31.077365 ==
7560 04:41:31.079886 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7561 04:41:31.086240 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7562 04:41:31.089844 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7563 04:41:31.095954 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7564 04:41:31.104061 [CA 0] Center 44 (14~75) winsize 62
7565 04:41:31.107210 [CA 1] Center 43 (13~74) winsize 62
7566 04:41:31.110241 [CA 2] Center 39 (10~69) winsize 60
7567 04:41:31.113633 [CA 3] Center 39 (10~69) winsize 60
7568 04:41:31.116862 [CA 4] Center 37 (8~67) winsize 60
7569 04:41:31.120413 [CA 5] Center 37 (7~67) winsize 61
7570 04:41:31.120904
7571 04:41:31.123733 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7572 04:41:31.124202
7573 04:41:31.130453 [CATrainingPosCal] consider 2 rank data
7574 04:41:31.130921 u2DelayCellTimex100 = 258/100 ps
7575 04:41:31.137291 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7576 04:41:31.140389 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7577 04:41:31.143658 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7578 04:41:31.146857 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7579 04:41:31.150082 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7580 04:41:31.154199 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7581 04:41:31.154770
7582 04:41:31.157320 CA PerBit enable=1, Macro0, CA PI delay=36
7583 04:41:31.157940
7584 04:41:31.160565 [CBTSetCACLKResult] CA Dly = 36
7585 04:41:31.163670 CS Dly: 11 (0~42)
7586 04:41:31.167057 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7587 04:41:31.170455 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7588 04:41:31.171018
7589 04:41:31.173770 ----->DramcWriteLeveling(PI) begin...
7590 04:41:31.174340 ==
7591 04:41:31.176864 Dram Type= 6, Freq= 0, CH_0, rank 0
7592 04:41:31.183249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 04:41:31.183716 ==
7594 04:41:31.186887 Write leveling (Byte 0): 35 => 35
7595 04:41:31.190235 Write leveling (Byte 1): 29 => 29
7596 04:41:31.190737 DramcWriteLeveling(PI) end<-----
7597 04:41:31.193391
7598 04:41:31.193881 ==
7599 04:41:31.196555 Dram Type= 6, Freq= 0, CH_0, rank 0
7600 04:41:31.200047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7601 04:41:31.200532 ==
7602 04:41:31.203279 [Gating] SW mode calibration
7603 04:41:31.209999 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7604 04:41:31.213347 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7605 04:41:31.219891 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 04:41:31.223103 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 04:41:31.226593 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 04:41:31.233001 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 04:41:31.236670 1 4 16 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
7610 04:41:31.239991 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7611 04:41:31.246414 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 04:41:31.249635 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 04:41:31.253150 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7614 04:41:31.259701 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7615 04:41:31.262771 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7616 04:41:31.266157 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7617 04:41:31.272946 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
7618 04:41:31.276391 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
7619 04:41:31.279612 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7620 04:41:31.286008 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 04:41:31.289280 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 04:41:31.292681 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 04:41:31.299159 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 04:41:31.302463 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7625 04:41:31.306092 1 6 16 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7626 04:41:31.312372 1 6 20 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7627 04:41:31.315649 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7628 04:41:31.318909 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 04:41:31.325638 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 04:41:31.328813 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 04:41:31.332329 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 04:41:31.338665 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 04:41:31.342271 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7634 04:41:31.345538 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7635 04:41:31.352260 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7636 04:41:31.355584 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 04:41:31.358646 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 04:41:31.365100 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 04:41:31.368491 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 04:41:31.371931 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 04:41:31.378690 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 04:41:31.382122 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 04:41:31.384959 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 04:41:31.388343 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 04:41:31.395219 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 04:41:31.398479 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 04:41:31.401847 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 04:41:31.408329 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 04:41:31.411713 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7650 04:41:31.414890 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7651 04:41:31.418113 Total UI for P1: 0, mck2ui 16
7652 04:41:31.421667 best dqsien dly found for B0: ( 1, 9, 16)
7653 04:41:31.428133 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7654 04:41:31.431543 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 04:41:31.435054 Total UI for P1: 0, mck2ui 16
7656 04:41:31.437965 best dqsien dly found for B1: ( 1, 9, 24)
7657 04:41:31.441442 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7658 04:41:31.444758 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7659 04:41:31.444861
7660 04:41:31.448161 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7661 04:41:31.454631 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7662 04:41:31.454727 [Gating] SW calibration Done
7663 04:41:31.454828 ==
7664 04:41:31.458023 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 04:41:31.464476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 04:41:31.464585 ==
7667 04:41:31.464680 RX Vref Scan: 0
7668 04:41:31.464777
7669 04:41:31.467972 RX Vref 0 -> 0, step: 1
7670 04:41:31.468048
7671 04:41:31.471345 RX Delay 0 -> 252, step: 8
7672 04:41:31.474395 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7673 04:41:31.477984 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7674 04:41:31.481006 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7675 04:41:31.487793 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7676 04:41:31.490918 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7677 04:41:31.494187 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7678 04:41:31.497917 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7679 04:41:31.501181 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7680 04:41:31.504535 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7681 04:41:31.511027 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7682 04:41:31.514092 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7683 04:41:31.517366 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7684 04:41:31.520822 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7685 04:41:31.527171 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7686 04:41:31.530779 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7687 04:41:31.534124 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7688 04:41:31.534208 ==
7689 04:41:31.537406 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 04:41:31.540618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 04:41:31.540701 ==
7692 04:41:31.544347 DQS Delay:
7693 04:41:31.544430 DQS0 = 0, DQS1 = 0
7694 04:41:31.547524 DQM Delay:
7695 04:41:31.547607 DQM0 = 127, DQM1 = 123
7696 04:41:31.547672 DQ Delay:
7697 04:41:31.554074 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7698 04:41:31.557172 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =139
7699 04:41:31.560625 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7700 04:41:31.563815 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7701 04:41:31.563898
7702 04:41:31.563963
7703 04:41:31.564023 ==
7704 04:41:31.567496 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 04:41:31.570654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 04:41:31.570733 ==
7707 04:41:31.570799
7708 04:41:31.570860
7709 04:41:31.573782 TX Vref Scan disable
7710 04:41:31.577152 == TX Byte 0 ==
7711 04:41:31.580566 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7712 04:41:31.583611 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7713 04:41:31.586955 == TX Byte 1 ==
7714 04:41:31.590331 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7715 04:41:31.593705 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7716 04:41:31.593786 ==
7717 04:41:31.597146 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 04:41:31.603658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 04:41:31.603742 ==
7720 04:41:31.616844
7721 04:41:31.620433 TX Vref early break, caculate TX vref
7722 04:41:31.623406 TX Vref=16, minBit 4, minWin=21, winSum=359
7723 04:41:31.627055 TX Vref=18, minBit 8, minWin=22, winSum=375
7724 04:41:31.630173 TX Vref=20, minBit 8, minWin=22, winSum=382
7725 04:41:31.633399 TX Vref=22, minBit 8, minWin=23, winSum=395
7726 04:41:31.636797 TX Vref=24, minBit 4, minWin=24, winSum=398
7727 04:41:31.643416 TX Vref=26, minBit 4, minWin=24, winSum=408
7728 04:41:31.646681 TX Vref=28, minBit 4, minWin=24, winSum=407
7729 04:41:31.650234 TX Vref=30, minBit 8, minWin=24, winSum=401
7730 04:41:31.653499 TX Vref=32, minBit 0, minWin=24, winSum=393
7731 04:41:31.656979 TX Vref=34, minBit 8, minWin=22, winSum=387
7732 04:41:31.660293 TX Vref=36, minBit 8, minWin=21, winSum=369
7733 04:41:31.666751 [TxChooseVref] Worse bit 4, Min win 24, Win sum 408, Final Vref 26
7734 04:41:31.666851
7735 04:41:31.669857 Final TX Range 0 Vref 26
7736 04:41:31.669928
7737 04:41:31.669988 ==
7738 04:41:31.673344 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 04:41:31.676727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 04:41:31.676831 ==
7741 04:41:31.676922
7742 04:41:31.677026
7743 04:41:31.679825 TX Vref Scan disable
7744 04:41:31.686434 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7745 04:41:31.686515 == TX Byte 0 ==
7746 04:41:31.690184 u2DelayCellOfst[0]=15 cells (4 PI)
7747 04:41:31.693375 u2DelayCellOfst[1]=18 cells (5 PI)
7748 04:41:31.696698 u2DelayCellOfst[2]=11 cells (3 PI)
7749 04:41:31.700165 u2DelayCellOfst[3]=15 cells (4 PI)
7750 04:41:31.703178 u2DelayCellOfst[4]=7 cells (2 PI)
7751 04:41:31.706604 u2DelayCellOfst[5]=0 cells (0 PI)
7752 04:41:31.709859 u2DelayCellOfst[6]=22 cells (6 PI)
7753 04:41:31.713228 u2DelayCellOfst[7]=18 cells (5 PI)
7754 04:41:31.716242 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7755 04:41:31.719754 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7756 04:41:31.723176 == TX Byte 1 ==
7757 04:41:31.726540 u2DelayCellOfst[8]=0 cells (0 PI)
7758 04:41:31.729779 u2DelayCellOfst[9]=0 cells (0 PI)
7759 04:41:31.729958 u2DelayCellOfst[10]=7 cells (2 PI)
7760 04:41:31.732631 u2DelayCellOfst[11]=7 cells (2 PI)
7761 04:41:31.736034 u2DelayCellOfst[12]=11 cells (3 PI)
7762 04:41:31.739457 u2DelayCellOfst[13]=11 cells (3 PI)
7763 04:41:31.742897 u2DelayCellOfst[14]=15 cells (4 PI)
7764 04:41:31.746079 u2DelayCellOfst[15]=11 cells (3 PI)
7765 04:41:31.752559 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7766 04:41:31.756226 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7767 04:41:31.756615 DramC Write-DBI on
7768 04:41:31.757037 ==
7769 04:41:31.759576 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 04:41:31.766301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 04:41:31.766825 ==
7772 04:41:31.767314
7773 04:41:31.767851
7774 04:41:31.768331 TX Vref Scan disable
7775 04:41:31.770335 == TX Byte 0 ==
7776 04:41:31.773690 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7777 04:41:31.777191 == TX Byte 1 ==
7778 04:41:31.780242 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7779 04:41:31.783698 DramC Write-DBI off
7780 04:41:31.784261
7781 04:41:31.784664 [DATLAT]
7782 04:41:31.784981 Freq=1600, CH0 RK0
7783 04:41:31.785315
7784 04:41:31.786799 DATLAT Default: 0xf
7785 04:41:31.790244 0, 0xFFFF, sum = 0
7786 04:41:31.790749 1, 0xFFFF, sum = 0
7787 04:41:31.793342 2, 0xFFFF, sum = 0
7788 04:41:31.794017 3, 0xFFFF, sum = 0
7789 04:41:31.796775 4, 0xFFFF, sum = 0
7790 04:41:31.797340 5, 0xFFFF, sum = 0
7791 04:41:31.800094 6, 0xFFFF, sum = 0
7792 04:41:31.800697 7, 0xFFFF, sum = 0
7793 04:41:31.803485 8, 0xFFFF, sum = 0
7794 04:41:31.803922 9, 0xFFFF, sum = 0
7795 04:41:31.806981 10, 0xFFFF, sum = 0
7796 04:41:31.807548 11, 0xFFFF, sum = 0
7797 04:41:31.810148 12, 0xFFFF, sum = 0
7798 04:41:31.810585 13, 0xEFFF, sum = 0
7799 04:41:31.813804 14, 0x0, sum = 1
7800 04:41:31.814239 15, 0x0, sum = 2
7801 04:41:31.817082 16, 0x0, sum = 3
7802 04:41:31.817549 17, 0x0, sum = 4
7803 04:41:31.820263 best_step = 15
7804 04:41:31.820688
7805 04:41:31.821119 ==
7806 04:41:31.823476 Dram Type= 6, Freq= 0, CH_0, rank 0
7807 04:41:31.826751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7808 04:41:31.827186 ==
7809 04:41:31.830020 RX Vref Scan: 1
7810 04:41:31.830461
7811 04:41:31.830892 Set Vref Range= 24 -> 127
7812 04:41:31.831306
7813 04:41:31.833212 RX Vref 24 -> 127, step: 1
7814 04:41:31.833810
7815 04:41:31.836942 RX Delay 11 -> 252, step: 4
7816 04:41:31.837371
7817 04:41:31.840035 Set Vref, RX VrefLevel [Byte0]: 24
7818 04:41:31.843649 [Byte1]: 24
7819 04:41:31.844210
7820 04:41:31.846991 Set Vref, RX VrefLevel [Byte0]: 25
7821 04:41:31.850056 [Byte1]: 25
7822 04:41:31.853433
7823 04:41:31.854119 Set Vref, RX VrefLevel [Byte0]: 26
7824 04:41:31.856572 [Byte1]: 26
7825 04:41:31.860745
7826 04:41:31.861307 Set Vref, RX VrefLevel [Byte0]: 27
7827 04:41:31.864183 [Byte1]: 27
7828 04:41:31.868705
7829 04:41:31.869251 Set Vref, RX VrefLevel [Byte0]: 28
7830 04:41:31.871925 [Byte1]: 28
7831 04:41:31.876204
7832 04:41:31.876627 Set Vref, RX VrefLevel [Byte0]: 29
7833 04:41:31.879583 [Byte1]: 29
7834 04:41:31.883730
7835 04:41:31.884274 Set Vref, RX VrefLevel [Byte0]: 30
7836 04:41:31.887148 [Byte1]: 30
7837 04:41:31.891370
7838 04:41:31.891785 Set Vref, RX VrefLevel [Byte0]: 31
7839 04:41:31.894549 [Byte1]: 31
7840 04:41:31.899148
7841 04:41:31.899693 Set Vref, RX VrefLevel [Byte0]: 32
7842 04:41:31.902216 [Byte1]: 32
7843 04:41:31.906366
7844 04:41:31.906993 Set Vref, RX VrefLevel [Byte0]: 33
7845 04:41:31.909717 [Byte1]: 33
7846 04:41:31.914464
7847 04:41:31.914945 Set Vref, RX VrefLevel [Byte0]: 34
7848 04:41:31.917769 [Byte1]: 34
7849 04:41:31.922071
7850 04:41:31.922709 Set Vref, RX VrefLevel [Byte0]: 35
7851 04:41:31.925277 [Byte1]: 35
7852 04:41:31.929592
7853 04:41:31.930107 Set Vref, RX VrefLevel [Byte0]: 36
7854 04:41:31.932723 [Byte1]: 36
7855 04:41:31.937126
7856 04:41:31.937701 Set Vref, RX VrefLevel [Byte0]: 37
7857 04:41:31.940560 [Byte1]: 37
7858 04:41:31.944551
7859 04:41:31.945018 Set Vref, RX VrefLevel [Byte0]: 38
7860 04:41:31.951080 [Byte1]: 38
7861 04:41:31.951581
7862 04:41:31.954468 Set Vref, RX VrefLevel [Byte0]: 39
7863 04:41:31.957719 [Byte1]: 39
7864 04:41:31.958134
7865 04:41:31.961079 Set Vref, RX VrefLevel [Byte0]: 40
7866 04:41:31.964839 [Byte1]: 40
7867 04:41:31.965378
7868 04:41:31.967505 Set Vref, RX VrefLevel [Byte0]: 41
7869 04:41:31.970794 [Byte1]: 41
7870 04:41:31.975528
7871 04:41:31.976034 Set Vref, RX VrefLevel [Byte0]: 42
7872 04:41:31.978784 [Byte1]: 42
7873 04:41:31.982653
7874 04:41:31.983099 Set Vref, RX VrefLevel [Byte0]: 43
7875 04:41:31.986093 [Byte1]: 43
7876 04:41:31.990320
7877 04:41:31.990829 Set Vref, RX VrefLevel [Byte0]: 44
7878 04:41:31.993535 [Byte1]: 44
7879 04:41:31.998011
7880 04:41:31.998432 Set Vref, RX VrefLevel [Byte0]: 45
7881 04:41:32.001319 [Byte1]: 45
7882 04:41:32.005634
7883 04:41:32.006139 Set Vref, RX VrefLevel [Byte0]: 46
7884 04:41:32.009042 [Byte1]: 46
7885 04:41:32.013213
7886 04:41:32.013725 Set Vref, RX VrefLevel [Byte0]: 47
7887 04:41:32.016404 [Byte1]: 47
7888 04:41:32.020907
7889 04:41:32.021501 Set Vref, RX VrefLevel [Byte0]: 48
7890 04:41:32.023994 [Byte1]: 48
7891 04:41:32.028506
7892 04:41:32.028968 Set Vref, RX VrefLevel [Byte0]: 49
7893 04:41:32.031781 [Byte1]: 49
7894 04:41:32.036218
7895 04:41:32.036676 Set Vref, RX VrefLevel [Byte0]: 50
7896 04:41:32.039464 [Byte1]: 50
7897 04:41:32.043857
7898 04:41:32.044317 Set Vref, RX VrefLevel [Byte0]: 51
7899 04:41:32.050212 [Byte1]: 51
7900 04:41:32.050760
7901 04:41:32.053359 Set Vref, RX VrefLevel [Byte0]: 52
7902 04:41:32.057006 [Byte1]: 52
7903 04:41:32.057625
7904 04:41:32.059957 Set Vref, RX VrefLevel [Byte0]: 53
7905 04:41:32.063584 [Byte1]: 53
7906 04:41:32.064155
7907 04:41:32.066527 Set Vref, RX VrefLevel [Byte0]: 54
7908 04:41:32.070166 [Byte1]: 54
7909 04:41:32.074396
7910 04:41:32.074958 Set Vref, RX VrefLevel [Byte0]: 55
7911 04:41:32.077388 [Byte1]: 55
7912 04:41:32.081840
7913 04:41:32.082265 Set Vref, RX VrefLevel [Byte0]: 56
7914 04:41:32.085150 [Byte1]: 56
7915 04:41:32.089513
7916 04:41:32.090077 Set Vref, RX VrefLevel [Byte0]: 57
7917 04:41:32.092617 [Byte1]: 57
7918 04:41:32.097224
7919 04:41:32.097842 Set Vref, RX VrefLevel [Byte0]: 58
7920 04:41:32.100217 [Byte1]: 58
7921 04:41:32.104428
7922 04:41:32.104985 Set Vref, RX VrefLevel [Byte0]: 59
7923 04:41:32.107853 [Byte1]: 59
7924 04:41:32.112043
7925 04:41:32.112502 Set Vref, RX VrefLevel [Byte0]: 60
7926 04:41:32.115591 [Byte1]: 60
7927 04:41:32.120200
7928 04:41:32.120774 Set Vref, RX VrefLevel [Byte0]: 61
7929 04:41:32.123124 [Byte1]: 61
7930 04:41:32.127574
7931 04:41:32.128033 Set Vref, RX VrefLevel [Byte0]: 62
7932 04:41:32.130600 [Byte1]: 62
7933 04:41:32.135295
7934 04:41:32.135855 Set Vref, RX VrefLevel [Byte0]: 63
7935 04:41:32.138333 [Byte1]: 63
7936 04:41:32.142745
7937 04:41:32.143208 Set Vref, RX VrefLevel [Byte0]: 64
7938 04:41:32.145870 [Byte1]: 64
7939 04:41:32.150296
7940 04:41:32.150772 Set Vref, RX VrefLevel [Byte0]: 65
7941 04:41:32.153568 [Byte1]: 65
7942 04:41:32.157969
7943 04:41:32.158426 Set Vref, RX VrefLevel [Byte0]: 66
7944 04:41:32.161099 [Byte1]: 66
7945 04:41:32.165562
7946 04:41:32.166123 Set Vref, RX VrefLevel [Byte0]: 67
7947 04:41:32.168969 [Byte1]: 67
7948 04:41:32.173211
7949 04:41:32.173669 Set Vref, RX VrefLevel [Byte0]: 68
7950 04:41:32.176598 [Byte1]: 68
7951 04:41:32.180614
7952 04:41:32.181106 Set Vref, RX VrefLevel [Byte0]: 69
7953 04:41:32.183982 [Byte1]: 69
7954 04:41:32.188635
7955 04:41:32.189164 Set Vref, RX VrefLevel [Byte0]: 70
7956 04:41:32.191661 [Byte1]: 70
7957 04:41:32.195718
7958 04:41:32.196142 Set Vref, RX VrefLevel [Byte0]: 71
7959 04:41:32.199345 [Byte1]: 71
7960 04:41:32.203655
7961 04:41:32.204145 Set Vref, RX VrefLevel [Byte0]: 72
7962 04:41:32.206904 [Byte1]: 72
7963 04:41:32.211214
7964 04:41:32.211628 Set Vref, RX VrefLevel [Byte0]: 73
7965 04:41:32.214129 [Byte1]: 73
7966 04:41:32.218887
7967 04:41:32.219305 Set Vref, RX VrefLevel [Byte0]: 74
7968 04:41:32.222169 [Byte1]: 74
7969 04:41:32.226053
7970 04:41:32.226494 Set Vref, RX VrefLevel [Byte0]: 75
7971 04:41:32.229400 [Byte1]: 75
7972 04:41:32.233986
7973 04:41:32.234471 Set Vref, RX VrefLevel [Byte0]: 76
7974 04:41:32.237114 [Byte1]: 76
7975 04:41:32.241829
7976 04:41:32.242395 Set Vref, RX VrefLevel [Byte0]: 77
7977 04:41:32.248450 [Byte1]: 77
7978 04:41:32.249021
7979 04:41:32.251370 Set Vref, RX VrefLevel [Byte0]: 78
7980 04:41:32.254766 [Byte1]: 78
7981 04:41:32.255258
7982 04:41:32.258120 Final RX Vref Byte 0 = 64 to rank0
7983 04:41:32.261062 Final RX Vref Byte 1 = 62 to rank0
7984 04:41:32.264841 Final RX Vref Byte 0 = 64 to rank1
7985 04:41:32.267786 Final RX Vref Byte 1 = 62 to rank1==
7986 04:41:32.271397 Dram Type= 6, Freq= 0, CH_0, rank 0
7987 04:41:32.274775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 04:41:32.275365 ==
7989 04:41:32.277872 DQS Delay:
7990 04:41:32.278447 DQS0 = 0, DQS1 = 0
7991 04:41:32.278856 DQM Delay:
7992 04:41:32.281099 DQM0 = 126, DQM1 = 119
7993 04:41:32.281610 DQ Delay:
7994 04:41:32.284253 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7995 04:41:32.291349 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7996 04:41:32.294002 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7997 04:41:32.297570 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
7998 04:41:32.298048
7999 04:41:32.298414
8000 04:41:32.298756
8001 04:41:32.301138 [DramC_TX_OE_Calibration] TA2
8002 04:41:32.304446 Original DQ_B0 (3 6) =30, OEN = 27
8003 04:41:32.307637 Original DQ_B1 (3 6) =30, OEN = 27
8004 04:41:32.308206 24, 0x0, End_B0=24 End_B1=24
8005 04:41:32.310726 25, 0x0, End_B0=25 End_B1=25
8006 04:41:32.313898 26, 0x0, End_B0=26 End_B1=26
8007 04:41:32.317201 27, 0x0, End_B0=27 End_B1=27
8008 04:41:32.317794 28, 0x0, End_B0=28 End_B1=28
8009 04:41:32.321120 29, 0x0, End_B0=29 End_B1=29
8010 04:41:32.323885 30, 0x0, End_B0=30 End_B1=30
8011 04:41:32.327051 31, 0x4141, End_B0=30 End_B1=30
8012 04:41:32.330564 Byte0 end_step=30 best_step=27
8013 04:41:32.333767 Byte1 end_step=30 best_step=27
8014 04:41:32.334235 Byte0 TX OE(2T, 0.5T) = (3, 3)
8015 04:41:32.337100 Byte1 TX OE(2T, 0.5T) = (3, 3)
8016 04:41:32.337662
8017 04:41:32.338042
8018 04:41:32.347177 [DQSOSCAuto] RK0, (LSB)MR18= 0x1413, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8019 04:41:32.350107 CH0 RK0: MR19=303, MR18=1413
8020 04:41:32.353435 CH0_RK0: MR19=0x303, MR18=0x1413, DQSOSC=399, MR23=63, INC=23, DEC=15
8021 04:41:32.357136
8022 04:41:32.360222 ----->DramcWriteLeveling(PI) begin...
8023 04:41:32.360790 ==
8024 04:41:32.363579 Dram Type= 6, Freq= 0, CH_0, rank 1
8025 04:41:32.367155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 04:41:32.367688 ==
8027 04:41:32.370092 Write leveling (Byte 0): 34 => 34
8028 04:41:32.373518 Write leveling (Byte 1): 28 => 28
8029 04:41:32.376755 DramcWriteLeveling(PI) end<-----
8030 04:41:32.377200
8031 04:41:32.377755 ==
8032 04:41:32.380280 Dram Type= 6, Freq= 0, CH_0, rank 1
8033 04:41:32.383645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8034 04:41:32.384067 ==
8035 04:41:32.386566 [Gating] SW mode calibration
8036 04:41:32.393372 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8037 04:41:32.399825 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8038 04:41:32.403256 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 04:41:32.406678 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 04:41:32.412999 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 04:41:32.416333 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8042 04:41:32.420097 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8043 04:41:32.425846 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8044 04:41:32.429553 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 04:41:32.432873 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 04:41:32.439503 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 04:41:32.443025 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 04:41:32.446003 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8049 04:41:32.452731 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8050 04:41:32.456299 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8051 04:41:32.459385 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 04:41:32.466224 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 04:41:32.469813 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 04:41:32.472844 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 04:41:32.479414 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 04:41:32.482369 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8057 04:41:32.485549 1 6 12 | B1->B0 | 2424 3f3f | 0 0 | (0 0) (0 0)
8058 04:41:32.492160 1 6 16 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
8059 04:41:32.495548 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 04:41:32.498934 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 04:41:32.505809 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 04:41:32.508909 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 04:41:32.512403 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 04:41:32.518800 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 04:41:32.522237 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8066 04:41:32.525451 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8067 04:41:32.532298 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 04:41:32.535263 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 04:41:32.538614 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 04:41:32.545555 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 04:41:32.548427 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 04:41:32.552073 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 04:41:32.558887 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 04:41:32.561622 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 04:41:32.565003 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 04:41:32.571571 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 04:41:32.575373 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 04:41:32.578105 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 04:41:32.585241 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 04:41:32.588424 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8081 04:41:32.591770 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8082 04:41:32.598315 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8083 04:41:32.598889 Total UI for P1: 0, mck2ui 16
8084 04:41:32.604874 best dqsien dly found for B0: ( 1, 9, 10)
8085 04:41:32.607909 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 04:41:32.611798 Total UI for P1: 0, mck2ui 16
8087 04:41:32.615185 best dqsien dly found for B1: ( 1, 9, 16)
8088 04:41:32.618167 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8089 04:41:32.621295 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8090 04:41:32.621798
8091 04:41:32.624501 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8092 04:41:32.627911 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8093 04:41:32.631489 [Gating] SW calibration Done
8094 04:41:32.632049 ==
8095 04:41:32.634688 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 04:41:32.638020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 04:41:32.638489 ==
8098 04:41:32.641137 RX Vref Scan: 0
8099 04:41:32.641623
8100 04:41:32.644773 RX Vref 0 -> 0, step: 1
8101 04:41:32.645331
8102 04:41:32.645750 RX Delay 0 -> 252, step: 8
8103 04:41:32.651327 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8104 04:41:32.654246 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8105 04:41:32.657578 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8106 04:41:32.661164 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8107 04:41:32.664065 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8108 04:41:32.670976 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8109 04:41:32.674100 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8110 04:41:32.677380 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8111 04:41:32.680984 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8112 04:41:32.687513 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8113 04:41:32.690856 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8114 04:41:32.693777 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8115 04:41:32.697223 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8116 04:41:32.700527 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8117 04:41:32.706771 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8118 04:41:32.710147 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8119 04:41:32.710569 ==
8120 04:41:32.713425 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 04:41:32.717297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 04:41:32.717901 ==
8123 04:41:32.720817 DQS Delay:
8124 04:41:32.721340 DQS0 = 0, DQS1 = 0
8125 04:41:32.721740 DQM Delay:
8126 04:41:32.723836 DQM0 = 128, DQM1 = 121
8127 04:41:32.724252 DQ Delay:
8128 04:41:32.727027 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8129 04:41:32.730266 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8130 04:41:32.736844 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8131 04:41:32.739926 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8132 04:41:32.740364
8133 04:41:32.740803
8134 04:41:32.741242 ==
8135 04:41:32.743646 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 04:41:32.746662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 04:41:32.747098 ==
8138 04:41:32.747552
8139 04:41:32.747969
8140 04:41:32.749902 TX Vref Scan disable
8141 04:41:32.750333 == TX Byte 0 ==
8142 04:41:32.757037 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8143 04:41:32.760073 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8144 04:41:32.763582 == TX Byte 1 ==
8145 04:41:32.766654 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8146 04:41:32.770067 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8147 04:41:32.770546 ==
8148 04:41:32.772942 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 04:41:32.776427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 04:41:32.776864 ==
8151 04:41:32.791873
8152 04:41:32.794607 TX Vref early break, caculate TX vref
8153 04:41:32.797937 TX Vref=16, minBit 0, minWin=22, winSum=366
8154 04:41:32.801403 TX Vref=18, minBit 8, minWin=22, winSum=374
8155 04:41:32.804631 TX Vref=20, minBit 7, minWin=23, winSum=386
8156 04:41:32.808160 TX Vref=22, minBit 0, minWin=24, winSum=392
8157 04:41:32.811507 TX Vref=24, minBit 8, minWin=23, winSum=400
8158 04:41:32.817986 TX Vref=26, minBit 8, minWin=24, winSum=406
8159 04:41:32.821554 TX Vref=28, minBit 0, minWin=25, winSum=409
8160 04:41:32.824773 TX Vref=30, minBit 8, minWin=24, winSum=404
8161 04:41:32.827926 TX Vref=32, minBit 8, minWin=23, winSum=401
8162 04:41:32.831656 TX Vref=34, minBit 8, minWin=22, winSum=386
8163 04:41:32.838130 [TxChooseVref] Worse bit 0, Min win 25, Win sum 409, Final Vref 28
8164 04:41:32.838678
8165 04:41:32.841160 Final TX Range 0 Vref 28
8166 04:41:32.841642
8167 04:41:32.841983 ==
8168 04:41:32.844628 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 04:41:32.847669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 04:41:32.848119 ==
8171 04:41:32.848573
8172 04:41:32.848999
8173 04:41:32.851051 TX Vref Scan disable
8174 04:41:32.857765 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8175 04:41:32.858205 == TX Byte 0 ==
8176 04:41:32.860920 u2DelayCellOfst[0]=11 cells (3 PI)
8177 04:41:32.864461 u2DelayCellOfst[1]=15 cells (4 PI)
8178 04:41:32.867938 u2DelayCellOfst[2]=11 cells (3 PI)
8179 04:41:32.871251 u2DelayCellOfst[3]=7 cells (2 PI)
8180 04:41:32.874342 u2DelayCellOfst[4]=7 cells (2 PI)
8181 04:41:32.877275 u2DelayCellOfst[5]=0 cells (0 PI)
8182 04:41:32.880903 u2DelayCellOfst[6]=18 cells (5 PI)
8183 04:41:32.884381 u2DelayCellOfst[7]=18 cells (5 PI)
8184 04:41:32.887669 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8185 04:41:32.890617 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8186 04:41:32.893988 == TX Byte 1 ==
8187 04:41:32.897649 u2DelayCellOfst[8]=0 cells (0 PI)
8188 04:41:32.898226 u2DelayCellOfst[9]=3 cells (1 PI)
8189 04:41:32.900682 u2DelayCellOfst[10]=7 cells (2 PI)
8190 04:41:32.904288 u2DelayCellOfst[11]=3 cells (1 PI)
8191 04:41:32.907394 u2DelayCellOfst[12]=15 cells (4 PI)
8192 04:41:32.910566 u2DelayCellOfst[13]=11 cells (3 PI)
8193 04:41:32.914134 u2DelayCellOfst[14]=15 cells (4 PI)
8194 04:41:32.917197 u2DelayCellOfst[15]=15 cells (4 PI)
8195 04:41:32.920682 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8196 04:41:32.927194 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8197 04:41:32.927651 DramC Write-DBI on
8198 04:41:32.928100 ==
8199 04:41:32.930456 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 04:41:32.933957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 04:41:32.937388 ==
8202 04:41:32.937949
8203 04:41:32.938403
8204 04:41:32.938826 TX Vref Scan disable
8205 04:41:32.940557 == TX Byte 0 ==
8206 04:41:32.944285 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8207 04:41:32.947523 == TX Byte 1 ==
8208 04:41:32.950758 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8209 04:41:32.954106 DramC Write-DBI off
8210 04:41:32.954547
8211 04:41:32.954996 [DATLAT]
8212 04:41:32.955422 Freq=1600, CH0 RK1
8213 04:41:32.955840
8214 04:41:32.957267 DATLAT Default: 0xf
8215 04:41:32.957742 0, 0xFFFF, sum = 0
8216 04:41:32.960434 1, 0xFFFF, sum = 0
8217 04:41:32.963875 2, 0xFFFF, sum = 0
8218 04:41:32.964372 3, 0xFFFF, sum = 0
8219 04:41:32.967174 4, 0xFFFF, sum = 0
8220 04:41:32.967708 5, 0xFFFF, sum = 0
8221 04:41:32.970519 6, 0xFFFF, sum = 0
8222 04:41:32.970942 7, 0xFFFF, sum = 0
8223 04:41:32.973788 8, 0xFFFF, sum = 0
8224 04:41:32.974229 9, 0xFFFF, sum = 0
8225 04:41:32.977219 10, 0xFFFF, sum = 0
8226 04:41:32.977783 11, 0xFFFF, sum = 0
8227 04:41:32.980338 12, 0xFFFF, sum = 0
8228 04:41:32.980764 13, 0xCFFF, sum = 0
8229 04:41:32.983812 14, 0x0, sum = 1
8230 04:41:32.984339 15, 0x0, sum = 2
8231 04:41:32.987042 16, 0x0, sum = 3
8232 04:41:32.987468 17, 0x0, sum = 4
8233 04:41:32.990307 best_step = 15
8234 04:41:32.990747
8235 04:41:32.991083 ==
8236 04:41:32.993623 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 04:41:32.996819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 04:41:32.997253 ==
8239 04:41:33.000463 RX Vref Scan: 0
8240 04:41:33.000882
8241 04:41:33.001216 RX Vref 0 -> 0, step: 1
8242 04:41:33.001577
8243 04:41:33.003743 RX Delay 3 -> 252, step: 4
8244 04:41:33.007181 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8245 04:41:33.013777 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8246 04:41:33.017001 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8247 04:41:33.020291 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8248 04:41:33.023903 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8249 04:41:33.027131 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8250 04:41:33.033601 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8251 04:41:33.036672 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8252 04:41:33.039939 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8253 04:41:33.043476 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8254 04:41:33.046887 iDelay=191, Bit 10, Center 118 (63 ~ 174) 112
8255 04:41:33.053377 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8256 04:41:33.056899 iDelay=191, Bit 12, Center 122 (67 ~ 178) 112
8257 04:41:33.060172 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8258 04:41:33.063611 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8259 04:41:33.070178 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8260 04:41:33.070712 ==
8261 04:41:33.073461 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 04:41:33.077012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 04:41:33.077583 ==
8264 04:41:33.078014 DQS Delay:
8265 04:41:33.079972 DQS0 = 0, DQS1 = 0
8266 04:41:33.080500 DQM Delay:
8267 04:41:33.083242 DQM0 = 124, DQM1 = 117
8268 04:41:33.083662 DQ Delay:
8269 04:41:33.086643 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8270 04:41:33.090142 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8271 04:41:33.093414 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8272 04:41:33.096444 DQ12 =122, DQ13 =122, DQ14 =128, DQ15 =124
8273 04:41:33.096963
8274 04:41:33.097295
8275 04:41:33.099559
8276 04:41:33.100132 [DramC_TX_OE_Calibration] TA2
8277 04:41:33.102707 Original DQ_B0 (3 6) =30, OEN = 27
8278 04:41:33.106198 Original DQ_B1 (3 6) =30, OEN = 27
8279 04:41:33.109548 24, 0x0, End_B0=24 End_B1=24
8280 04:41:33.113133 25, 0x0, End_B0=25 End_B1=25
8281 04:41:33.116188 26, 0x0, End_B0=26 End_B1=26
8282 04:41:33.116702 27, 0x0, End_B0=27 End_B1=27
8283 04:41:33.119423 28, 0x0, End_B0=28 End_B1=28
8284 04:41:33.122621 29, 0x0, End_B0=29 End_B1=29
8285 04:41:33.125991 30, 0x0, End_B0=30 End_B1=30
8286 04:41:33.129446 31, 0x4141, End_B0=30 End_B1=30
8287 04:41:33.130081 Byte0 end_step=30 best_step=27
8288 04:41:33.132687 Byte1 end_step=30 best_step=27
8289 04:41:33.135738 Byte0 TX OE(2T, 0.5T) = (3, 3)
8290 04:41:33.139353 Byte1 TX OE(2T, 0.5T) = (3, 3)
8291 04:41:33.139774
8292 04:41:33.140160
8293 04:41:33.148984 [DQSOSCAuto] RK1, (LSB)MR18= 0x2310, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8294 04:41:33.149502 CH0 RK1: MR19=303, MR18=2310
8295 04:41:33.155842 CH0_RK1: MR19=0x303, MR18=0x2310, DQSOSC=392, MR23=63, INC=24, DEC=16
8296 04:41:33.159291 [RxdqsGatingPostProcess] freq 1600
8297 04:41:33.165617 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8298 04:41:33.168962 best DQS0 dly(2T, 0.5T) = (1, 1)
8299 04:41:33.172334 best DQS1 dly(2T, 0.5T) = (1, 1)
8300 04:41:33.175493 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8301 04:41:33.179062 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8302 04:41:33.179585 best DQS0 dly(2T, 0.5T) = (1, 1)
8303 04:41:33.181997 best DQS1 dly(2T, 0.5T) = (1, 1)
8304 04:41:33.185548 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8305 04:41:33.188685 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8306 04:41:33.191923 Pre-setting of DQS Precalculation
8307 04:41:33.198756 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8308 04:41:33.199249 ==
8309 04:41:33.201935 Dram Type= 6, Freq= 0, CH_1, rank 0
8310 04:41:33.205217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 04:41:33.205673 ==
8312 04:41:33.211940 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8313 04:41:33.215236 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8314 04:41:33.218520 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8315 04:41:33.224822 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8316 04:41:33.234193 [CA 0] Center 41 (12~70) winsize 59
8317 04:41:33.237075 [CA 1] Center 42 (12~72) winsize 61
8318 04:41:33.240614 [CA 2] Center 37 (8~66) winsize 59
8319 04:41:33.243624 [CA 3] Center 37 (8~66) winsize 59
8320 04:41:33.247056 [CA 4] Center 37 (8~67) winsize 60
8321 04:41:33.250550 [CA 5] Center 36 (7~66) winsize 60
8322 04:41:33.251208
8323 04:41:33.253735 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8324 04:41:33.254159
8325 04:41:33.257312 [CATrainingPosCal] consider 1 rank data
8326 04:41:33.260267 u2DelayCellTimex100 = 258/100 ps
8327 04:41:33.263660 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8328 04:41:33.270292 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8329 04:41:33.273588 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8330 04:41:33.276738 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8331 04:41:33.280401 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8332 04:41:33.283563 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8333 04:41:33.283982
8334 04:41:33.286776 CA PerBit enable=1, Macro0, CA PI delay=36
8335 04:41:33.287196
8336 04:41:33.290280 [CBTSetCACLKResult] CA Dly = 36
8337 04:41:33.293698 CS Dly: 10 (0~41)
8338 04:41:33.296946 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8339 04:41:33.300022 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8340 04:41:33.300468 ==
8341 04:41:33.303224 Dram Type= 6, Freq= 0, CH_1, rank 1
8342 04:41:33.306637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 04:41:33.310175 ==
8344 04:41:33.313512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8345 04:41:33.316715 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8346 04:41:33.323475 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8347 04:41:33.329730 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8348 04:41:33.336983 [CA 0] Center 42 (13~71) winsize 59
8349 04:41:33.340260 [CA 1] Center 42 (13~72) winsize 60
8350 04:41:33.343741 [CA 2] Center 37 (8~67) winsize 60
8351 04:41:33.346940 [CA 3] Center 37 (7~67) winsize 61
8352 04:41:33.350160 [CA 4] Center 38 (8~68) winsize 61
8353 04:41:33.353362 [CA 5] Center 37 (7~67) winsize 61
8354 04:41:33.353808
8355 04:41:33.356817 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8356 04:41:33.357328
8357 04:41:33.360016 [CATrainingPosCal] consider 2 rank data
8358 04:41:33.363438 u2DelayCellTimex100 = 258/100 ps
8359 04:41:33.366915 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8360 04:41:33.373323 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8361 04:41:33.376845 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8362 04:41:33.380040 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8363 04:41:33.383550 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8364 04:41:33.386885 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8365 04:41:33.387304
8366 04:41:33.390092 CA PerBit enable=1, Macro0, CA PI delay=36
8367 04:41:33.390509
8368 04:41:33.393534 [CBTSetCACLKResult] CA Dly = 36
8369 04:41:33.396733 CS Dly: 11 (0~43)
8370 04:41:33.399782 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8371 04:41:33.403142 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8372 04:41:33.403690
8373 04:41:33.406622 ----->DramcWriteLeveling(PI) begin...
8374 04:41:33.407040 ==
8375 04:41:33.409851 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 04:41:33.416464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 04:41:33.416882 ==
8378 04:41:33.419730 Write leveling (Byte 0): 23 => 23
8379 04:41:33.422955 Write leveling (Byte 1): 30 => 30
8380 04:41:33.423371 DramcWriteLeveling(PI) end<-----
8381 04:41:33.423701
8382 04:41:33.426297 ==
8383 04:41:33.429578 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 04:41:33.433078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 04:41:33.433528 ==
8386 04:41:33.436417 [Gating] SW mode calibration
8387 04:41:33.442906 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8388 04:41:33.446028 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8389 04:41:33.452873 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 04:41:33.456050 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 04:41:33.459547 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 04:41:33.465904 1 4 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8393 04:41:33.469423 1 4 16 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 1)
8394 04:41:33.472323 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 04:41:33.479122 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 04:41:33.482372 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 04:41:33.485839 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 04:41:33.492346 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 04:41:33.495635 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 04:41:33.498860 1 5 12 | B1->B0 | 3232 3333 | 0 1 | (0 0) (1 0)
8401 04:41:33.505666 1 5 16 | B1->B0 | 2424 2424 | 0 0 | (0 1) (0 0)
8402 04:41:33.508789 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 04:41:33.512364 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 04:41:33.518625 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 04:41:33.522322 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 04:41:33.525547 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 04:41:33.532228 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 04:41:33.535540 1 6 12 | B1->B0 | 3232 2a29 | 0 1 | (1 1) (0 0)
8409 04:41:33.538803 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 04:41:33.545372 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 04:41:33.548472 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 04:41:33.551791 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 04:41:33.558263 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 04:41:33.561392 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 04:41:33.564703 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 04:41:33.571206 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8417 04:41:33.574598 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8418 04:41:33.578310 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 04:41:33.584987 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 04:41:33.587884 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 04:41:33.591345 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 04:41:33.597896 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 04:41:33.601435 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 04:41:33.604500 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 04:41:33.611123 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 04:41:33.614458 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 04:41:33.618015 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 04:41:33.624751 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 04:41:33.628018 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 04:41:33.631070 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 04:41:33.637674 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 04:41:33.640879 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 04:41:33.644362 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8434 04:41:33.651009 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 04:41:33.651431 Total UI for P1: 0, mck2ui 16
8436 04:41:33.654163 best dqsien dly found for B0: ( 1, 9, 16)
8437 04:41:33.657398 Total UI for P1: 0, mck2ui 16
8438 04:41:33.661170 best dqsien dly found for B1: ( 1, 9, 16)
8439 04:41:33.667475 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8440 04:41:33.670744 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8441 04:41:33.671234
8442 04:41:33.674175 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8443 04:41:33.677093 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8444 04:41:33.680478 [Gating] SW calibration Done
8445 04:41:33.680896 ==
8446 04:41:33.683710 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 04:41:33.687164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 04:41:33.687587 ==
8449 04:41:33.690580 RX Vref Scan: 0
8450 04:41:33.691005
8451 04:41:33.691570 RX Vref 0 -> 0, step: 1
8452 04:41:33.691925
8453 04:41:33.694012 RX Delay 0 -> 252, step: 8
8454 04:41:33.696960 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8455 04:41:33.703518 iDelay=208, Bit 1, Center 123 (64 ~ 183) 120
8456 04:41:33.706915 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8457 04:41:33.710270 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8458 04:41:33.713588 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8459 04:41:33.716760 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8460 04:41:33.723544 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8461 04:41:33.726712 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8462 04:41:33.729859 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8463 04:41:33.733251 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8464 04:41:33.736751 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8465 04:41:33.743204 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8466 04:41:33.746810 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8467 04:41:33.749813 iDelay=208, Bit 13, Center 131 (72 ~ 191) 120
8468 04:41:33.753347 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8469 04:41:33.760106 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8470 04:41:33.760535 ==
8471 04:41:33.763263 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 04:41:33.766554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 04:41:33.766982 ==
8474 04:41:33.767320 DQS Delay:
8475 04:41:33.769843 DQS0 = 0, DQS1 = 0
8476 04:41:33.770271 DQM Delay:
8477 04:41:33.773003 DQM0 = 132, DQM1 = 125
8478 04:41:33.773429 DQ Delay:
8479 04:41:33.776230 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8480 04:41:33.779911 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8481 04:41:33.783047 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8482 04:41:33.786266 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8483 04:41:33.786693
8484 04:41:33.787031
8485 04:41:33.789723 ==
8486 04:41:33.792919 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 04:41:33.795731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 04:41:33.795813 ==
8489 04:41:33.795879
8490 04:41:33.795939
8491 04:41:33.799155 TX Vref Scan disable
8492 04:41:33.799238 == TX Byte 0 ==
8493 04:41:33.805724 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8494 04:41:33.808826 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8495 04:41:33.808909 == TX Byte 1 ==
8496 04:41:33.815762 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8497 04:41:33.818978 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8498 04:41:33.819065 ==
8499 04:41:33.822258 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 04:41:33.825375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 04:41:33.825457 ==
8502 04:41:33.839321
8503 04:41:33.842608 TX Vref early break, caculate TX vref
8504 04:41:33.845852 TX Vref=16, minBit 8, minWin=21, winSum=357
8505 04:41:33.849106 TX Vref=18, minBit 9, minWin=21, winSum=364
8506 04:41:33.852624 TX Vref=20, minBit 1, minWin=23, winSum=379
8507 04:41:33.855848 TX Vref=22, minBit 11, minWin=22, winSum=383
8508 04:41:33.859173 TX Vref=24, minBit 8, minWin=22, winSum=395
8509 04:41:33.865640 TX Vref=26, minBit 5, minWin=24, winSum=404
8510 04:41:33.869074 TX Vref=28, minBit 5, minWin=24, winSum=409
8511 04:41:33.872596 TX Vref=30, minBit 0, minWin=24, winSum=403
8512 04:41:33.876000 TX Vref=32, minBit 9, minWin=23, winSum=394
8513 04:41:33.879102 TX Vref=34, minBit 5, minWin=22, winSum=386
8514 04:41:33.885718 [TxChooseVref] Worse bit 5, Min win 24, Win sum 409, Final Vref 28
8515 04:41:33.885875
8516 04:41:33.888778 Final TX Range 0 Vref 28
8517 04:41:33.888860
8518 04:41:33.888925 ==
8519 04:41:33.892070 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 04:41:33.895405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 04:41:33.895488 ==
8522 04:41:33.895553
8523 04:41:33.895614
8524 04:41:33.898849 TX Vref Scan disable
8525 04:41:33.905637 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8526 04:41:33.905723 == TX Byte 0 ==
8527 04:41:33.908728 u2DelayCellOfst[0]=18 cells (5 PI)
8528 04:41:33.912159 u2DelayCellOfst[1]=15 cells (4 PI)
8529 04:41:33.915683 u2DelayCellOfst[2]=0 cells (0 PI)
8530 04:41:33.918593 u2DelayCellOfst[3]=3 cells (1 PI)
8531 04:41:33.922042 u2DelayCellOfst[4]=7 cells (2 PI)
8532 04:41:33.925301 u2DelayCellOfst[5]=22 cells (6 PI)
8533 04:41:33.928673 u2DelayCellOfst[6]=18 cells (5 PI)
8534 04:41:33.932273 u2DelayCellOfst[7]=3 cells (1 PI)
8535 04:41:33.935488 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8536 04:41:33.938698 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8537 04:41:33.942200 == TX Byte 1 ==
8538 04:41:33.942283 u2DelayCellOfst[8]=0 cells (0 PI)
8539 04:41:33.945219 u2DelayCellOfst[9]=7 cells (2 PI)
8540 04:41:33.948862 u2DelayCellOfst[10]=15 cells (4 PI)
8541 04:41:33.952222 u2DelayCellOfst[11]=7 cells (2 PI)
8542 04:41:33.955459 u2DelayCellOfst[12]=15 cells (4 PI)
8543 04:41:33.958598 u2DelayCellOfst[13]=18 cells (5 PI)
8544 04:41:33.961853 u2DelayCellOfst[14]=22 cells (6 PI)
8545 04:41:33.965144 u2DelayCellOfst[15]=18 cells (5 PI)
8546 04:41:33.968518 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8547 04:41:33.975118 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8548 04:41:33.975216 DramC Write-DBI on
8549 04:41:33.975302 ==
8550 04:41:33.978395 Dram Type= 6, Freq= 0, CH_1, rank 0
8551 04:41:33.981814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8552 04:41:33.985138 ==
8553 04:41:33.985214
8554 04:41:33.985296
8555 04:41:33.985400 TX Vref Scan disable
8556 04:41:33.988624 == TX Byte 0 ==
8557 04:41:33.991976 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8558 04:41:33.995146 == TX Byte 1 ==
8559 04:41:33.998722 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8560 04:41:34.001825 DramC Write-DBI off
8561 04:41:34.001901
8562 04:41:34.001983 [DATLAT]
8563 04:41:34.002065 Freq=1600, CH1 RK0
8564 04:41:34.002142
8565 04:41:34.005108 DATLAT Default: 0xf
8566 04:41:34.005189 0, 0xFFFF, sum = 0
8567 04:41:34.008509 1, 0xFFFF, sum = 0
8568 04:41:34.011625 2, 0xFFFF, sum = 0
8569 04:41:34.011704 3, 0xFFFF, sum = 0
8570 04:41:34.015218 4, 0xFFFF, sum = 0
8571 04:41:34.015295 5, 0xFFFF, sum = 0
8572 04:41:34.018369 6, 0xFFFF, sum = 0
8573 04:41:34.018449 7, 0xFFFF, sum = 0
8574 04:41:34.021625 8, 0xFFFF, sum = 0
8575 04:41:34.021702 9, 0xFFFF, sum = 0
8576 04:41:34.025339 10, 0xFFFF, sum = 0
8577 04:41:34.025428 11, 0xFFFF, sum = 0
8578 04:41:34.028399 12, 0xFFFF, sum = 0
8579 04:41:34.028482 13, 0x8FFF, sum = 0
8580 04:41:34.031849 14, 0x0, sum = 1
8581 04:41:34.031932 15, 0x0, sum = 2
8582 04:41:34.035223 16, 0x0, sum = 3
8583 04:41:34.035307 17, 0x0, sum = 4
8584 04:41:34.038451 best_step = 15
8585 04:41:34.038533
8586 04:41:34.038598 ==
8587 04:41:34.041669 Dram Type= 6, Freq= 0, CH_1, rank 0
8588 04:41:34.044967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8589 04:41:34.045051 ==
8590 04:41:34.048356 RX Vref Scan: 1
8591 04:41:34.048431
8592 04:41:34.048511 Set Vref Range= 24 -> 127
8593 04:41:34.048593
8594 04:41:34.051627 RX Vref 24 -> 127, step: 1
8595 04:41:34.051704
8596 04:41:34.054934 RX Delay 11 -> 252, step: 4
8597 04:41:34.055007
8598 04:41:34.058159 Set Vref, RX VrefLevel [Byte0]: 24
8599 04:41:34.061400 [Byte1]: 24
8600 04:41:34.061496
8601 04:41:34.064708 Set Vref, RX VrefLevel [Byte0]: 25
8602 04:41:34.068016 [Byte1]: 25
8603 04:41:34.071343
8604 04:41:34.071416 Set Vref, RX VrefLevel [Byte0]: 26
8605 04:41:34.074605 [Byte1]: 26
8606 04:41:34.079127
8607 04:41:34.079200 Set Vref, RX VrefLevel [Byte0]: 27
8608 04:41:34.082456 [Byte1]: 27
8609 04:41:34.086562
8610 04:41:34.086637 Set Vref, RX VrefLevel [Byte0]: 28
8611 04:41:34.089821 [Byte1]: 28
8612 04:41:34.094340
8613 04:41:34.094414 Set Vref, RX VrefLevel [Byte0]: 29
8614 04:41:34.097669 [Byte1]: 29
8615 04:41:34.101725
8616 04:41:34.101797 Set Vref, RX VrefLevel [Byte0]: 30
8617 04:41:34.105301 [Byte1]: 30
8618 04:41:34.109443
8619 04:41:34.109558 Set Vref, RX VrefLevel [Byte0]: 31
8620 04:41:34.112670 [Byte1]: 31
8621 04:41:34.117273
8622 04:41:34.117353 Set Vref, RX VrefLevel [Byte0]: 32
8623 04:41:34.120399 [Byte1]: 32
8624 04:41:34.124802
8625 04:41:34.124876 Set Vref, RX VrefLevel [Byte0]: 33
8626 04:41:34.127936 [Byte1]: 33
8627 04:41:34.132369
8628 04:41:34.132445 Set Vref, RX VrefLevel [Byte0]: 34
8629 04:41:34.135775 [Byte1]: 34
8630 04:41:34.140152
8631 04:41:34.140230 Set Vref, RX VrefLevel [Byte0]: 35
8632 04:41:34.143248 [Byte1]: 35
8633 04:41:34.147438
8634 04:41:34.147513 Set Vref, RX VrefLevel [Byte0]: 36
8635 04:41:34.150986 [Byte1]: 36
8636 04:41:34.155055
8637 04:41:34.155134 Set Vref, RX VrefLevel [Byte0]: 37
8638 04:41:34.158452 [Byte1]: 37
8639 04:41:34.162822
8640 04:41:34.162899 Set Vref, RX VrefLevel [Byte0]: 38
8641 04:41:34.166125 [Byte1]: 38
8642 04:41:34.170305
8643 04:41:34.170384 Set Vref, RX VrefLevel [Byte0]: 39
8644 04:41:34.173528 [Byte1]: 39
8645 04:41:34.178183
8646 04:41:34.178261 Set Vref, RX VrefLevel [Byte0]: 40
8647 04:41:34.181435 [Byte1]: 40
8648 04:41:34.185396
8649 04:41:34.185541 Set Vref, RX VrefLevel [Byte0]: 41
8650 04:41:34.188743 [Byte1]: 41
8651 04:41:34.193243
8652 04:41:34.193320 Set Vref, RX VrefLevel [Byte0]: 42
8653 04:41:34.196476 [Byte1]: 42
8654 04:41:34.200955
8655 04:41:34.201027 Set Vref, RX VrefLevel [Byte0]: 43
8656 04:41:34.204350 [Byte1]: 43
8657 04:41:34.208460
8658 04:41:34.208540 Set Vref, RX VrefLevel [Byte0]: 44
8659 04:41:34.211706 [Byte1]: 44
8660 04:41:34.215917
8661 04:41:34.215987 Set Vref, RX VrefLevel [Byte0]: 45
8662 04:41:34.219342 [Byte1]: 45
8663 04:41:34.223701
8664 04:41:34.223777 Set Vref, RX VrefLevel [Byte0]: 46
8665 04:41:34.227037 [Byte1]: 46
8666 04:41:34.231188
8667 04:41:34.231263 Set Vref, RX VrefLevel [Byte0]: 47
8668 04:41:34.234747 [Byte1]: 47
8669 04:41:34.238823
8670 04:41:34.238905 Set Vref, RX VrefLevel [Byte0]: 48
8671 04:41:34.242403 [Byte1]: 48
8672 04:41:34.246343
8673 04:41:34.246430 Set Vref, RX VrefLevel [Byte0]: 49
8674 04:41:34.249926 [Byte1]: 49
8675 04:41:34.253940
8676 04:41:34.254016 Set Vref, RX VrefLevel [Byte0]: 50
8677 04:41:34.260462 [Byte1]: 50
8678 04:41:34.260541
8679 04:41:34.263871 Set Vref, RX VrefLevel [Byte0]: 51
8680 04:41:34.267233 [Byte1]: 51
8681 04:41:34.267307
8682 04:41:34.270726 Set Vref, RX VrefLevel [Byte0]: 52
8683 04:41:34.273740 [Byte1]: 52
8684 04:41:34.277176
8685 04:41:34.277252 Set Vref, RX VrefLevel [Byte0]: 53
8686 04:41:34.280495 [Byte1]: 53
8687 04:41:34.284532
8688 04:41:34.284613 Set Vref, RX VrefLevel [Byte0]: 54
8689 04:41:34.288000 [Byte1]: 54
8690 04:41:34.292290
8691 04:41:34.292366 Set Vref, RX VrefLevel [Byte0]: 55
8692 04:41:34.295572 [Byte1]: 55
8693 04:41:34.299769
8694 04:41:34.299848 Set Vref, RX VrefLevel [Byte0]: 56
8695 04:41:34.303218 [Byte1]: 56
8696 04:41:34.307573
8697 04:41:34.307659 Set Vref, RX VrefLevel [Byte0]: 57
8698 04:41:34.310929 [Byte1]: 57
8699 04:41:34.314898
8700 04:41:34.314976 Set Vref, RX VrefLevel [Byte0]: 58
8701 04:41:34.318487 [Byte1]: 58
8702 04:41:34.322469
8703 04:41:34.322548 Set Vref, RX VrefLevel [Byte0]: 59
8704 04:41:34.325892 [Byte1]: 59
8705 04:41:34.330385
8706 04:41:34.330465 Set Vref, RX VrefLevel [Byte0]: 60
8707 04:41:34.333617 [Byte1]: 60
8708 04:41:34.337596
8709 04:41:34.337671 Set Vref, RX VrefLevel [Byte0]: 61
8710 04:41:34.341238 [Byte1]: 61
8711 04:41:34.345327
8712 04:41:34.345403 Set Vref, RX VrefLevel [Byte0]: 62
8713 04:41:34.348688 [Byte1]: 62
8714 04:41:34.353224
8715 04:41:34.353300 Set Vref, RX VrefLevel [Byte0]: 63
8716 04:41:34.356149 [Byte1]: 63
8717 04:41:34.360842
8718 04:41:34.360917 Set Vref, RX VrefLevel [Byte0]: 64
8719 04:41:34.364077 [Byte1]: 64
8720 04:41:34.368120
8721 04:41:34.368196 Set Vref, RX VrefLevel [Byte0]: 65
8722 04:41:34.371392 [Byte1]: 65
8723 04:41:34.375896
8724 04:41:34.375971 Set Vref, RX VrefLevel [Byte0]: 66
8725 04:41:34.379323 [Byte1]: 66
8726 04:41:34.383640
8727 04:41:34.383718 Set Vref, RX VrefLevel [Byte0]: 67
8728 04:41:34.386844 [Byte1]: 67
8729 04:41:34.391027
8730 04:41:34.391106 Set Vref, RX VrefLevel [Byte0]: 68
8731 04:41:34.394416 [Byte1]: 68
8732 04:41:34.398868
8733 04:41:34.398944 Set Vref, RX VrefLevel [Byte0]: 69
8734 04:41:34.402198 [Byte1]: 69
8735 04:41:34.406530
8736 04:41:34.406617 Set Vref, RX VrefLevel [Byte0]: 70
8737 04:41:34.409768 [Byte1]: 70
8738 04:41:34.413891
8739 04:41:34.413967 Set Vref, RX VrefLevel [Byte0]: 71
8740 04:41:34.417150 [Byte1]: 71
8741 04:41:34.421470
8742 04:41:34.421586 Final RX Vref Byte 0 = 56 to rank0
8743 04:41:34.425028 Final RX Vref Byte 1 = 53 to rank0
8744 04:41:34.428180 Final RX Vref Byte 0 = 56 to rank1
8745 04:41:34.431602 Final RX Vref Byte 1 = 53 to rank1==
8746 04:41:34.434860 Dram Type= 6, Freq= 0, CH_1, rank 0
8747 04:41:34.441341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 04:41:34.441421 ==
8749 04:41:34.441558 DQS Delay:
8750 04:41:34.441639 DQS0 = 0, DQS1 = 0
8751 04:41:34.444653 DQM Delay:
8752 04:41:34.444728 DQM0 = 131, DQM1 = 123
8753 04:41:34.448266 DQ Delay:
8754 04:41:34.451663 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =130
8755 04:41:34.454625 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =126
8756 04:41:34.458252 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8757 04:41:34.461483 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8758 04:41:34.461559
8759 04:41:34.461641
8760 04:41:34.461723
8761 04:41:34.464755 [DramC_TX_OE_Calibration] TA2
8762 04:41:34.468023 Original DQ_B0 (3 6) =30, OEN = 27
8763 04:41:34.471413 Original DQ_B1 (3 6) =30, OEN = 27
8764 04:41:34.474831 24, 0x0, End_B0=24 End_B1=24
8765 04:41:34.474907 25, 0x0, End_B0=25 End_B1=25
8766 04:41:34.478120 26, 0x0, End_B0=26 End_B1=26
8767 04:41:34.481221 27, 0x0, End_B0=27 End_B1=27
8768 04:41:34.484522 28, 0x0, End_B0=28 End_B1=28
8769 04:41:34.487760 29, 0x0, End_B0=29 End_B1=29
8770 04:41:34.487839 30, 0x0, End_B0=30 End_B1=30
8771 04:41:34.491044 31, 0x4141, End_B0=30 End_B1=30
8772 04:41:34.494588 Byte0 end_step=30 best_step=27
8773 04:41:34.497891 Byte1 end_step=30 best_step=27
8774 04:41:34.501015 Byte0 TX OE(2T, 0.5T) = (3, 3)
8775 04:41:34.504316 Byte1 TX OE(2T, 0.5T) = (3, 3)
8776 04:41:34.504402
8777 04:41:34.504488
8778 04:41:34.511132 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8779 04:41:34.514561 CH1 RK0: MR19=303, MR18=A0F
8780 04:41:34.521197 CH1_RK0: MR19=0x303, MR18=0xA0F, DQSOSC=402, MR23=63, INC=22, DEC=15
8781 04:41:34.521284
8782 04:41:34.524176 ----->DramcWriteLeveling(PI) begin...
8783 04:41:34.524260 ==
8784 04:41:34.527526 Dram Type= 6, Freq= 0, CH_1, rank 1
8785 04:41:34.530770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8786 04:41:34.530850 ==
8787 04:41:34.534325 Write leveling (Byte 0): 24 => 24
8788 04:41:34.537350 Write leveling (Byte 1): 26 => 26
8789 04:41:34.540682 DramcWriteLeveling(PI) end<-----
8790 04:41:34.540761
8791 04:41:34.540844 ==
8792 04:41:34.544109 Dram Type= 6, Freq= 0, CH_1, rank 1
8793 04:41:34.547476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8794 04:41:34.547554 ==
8795 04:41:34.550890 [Gating] SW mode calibration
8796 04:41:34.557509 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8797 04:41:34.563948 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8798 04:41:34.567591 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 04:41:34.570906 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 04:41:34.577425 1 4 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8801 04:41:34.580819 1 4 12 | B1->B0 | 3030 3434 | 0 1 | (1 1) (1 1)
8802 04:41:34.584140 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 04:41:34.590634 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 04:41:34.593896 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 04:41:34.596986 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 04:41:34.603646 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 04:41:34.606989 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 04:41:34.610200 1 5 8 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8809 04:41:34.616980 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8810 04:41:34.620140 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 04:41:34.623515 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 04:41:34.630161 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 04:41:34.633334 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 04:41:34.636953 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 04:41:34.643332 1 6 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8816 04:41:34.646625 1 6 8 | B1->B0 | 2626 4646 | 0 0 | (1 1) (0 0)
8817 04:41:34.649874 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8818 04:41:34.656525 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 04:41:34.659738 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 04:41:34.663467 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 04:41:34.670006 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 04:41:34.673085 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 04:41:34.676482 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 04:41:34.683095 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8825 04:41:34.686355 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8826 04:41:34.689680 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 04:41:34.696019 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 04:41:34.699337 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 04:41:34.702676 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 04:41:34.709555 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 04:41:34.712555 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 04:41:34.716126 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 04:41:34.722543 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 04:41:34.725905 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 04:41:34.729252 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 04:41:34.736089 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 04:41:34.739379 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 04:41:34.742580 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 04:41:34.749392 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 04:41:34.752760 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8841 04:41:34.756045 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8842 04:41:34.762646 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 04:41:34.762725 Total UI for P1: 0, mck2ui 16
8844 04:41:34.769405 best dqsien dly found for B0: ( 1, 9, 10)
8845 04:41:34.769505 Total UI for P1: 0, mck2ui 16
8846 04:41:34.775809 best dqsien dly found for B1: ( 1, 9, 10)
8847 04:41:34.779055 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8848 04:41:34.782509 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8849 04:41:34.782585
8850 04:41:34.785647 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8851 04:41:34.789188 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8852 04:41:34.792411 [Gating] SW calibration Done
8853 04:41:34.792488 ==
8854 04:41:34.795521 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 04:41:34.799105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 04:41:34.799186 ==
8857 04:41:34.802276 RX Vref Scan: 0
8858 04:41:34.802358
8859 04:41:34.802441 RX Vref 0 -> 0, step: 1
8860 04:41:34.802520
8861 04:41:34.805382 RX Delay 0 -> 252, step: 8
8862 04:41:34.808750 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8863 04:41:34.815507 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8864 04:41:34.818445 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8865 04:41:34.822041 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8866 04:41:34.825431 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8867 04:41:34.828467 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8868 04:41:34.835266 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8869 04:41:34.838770 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8870 04:41:34.841891 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8871 04:41:34.845116 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8872 04:41:34.848502 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8873 04:41:34.855021 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8874 04:41:34.858675 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8875 04:41:34.862015 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8876 04:41:34.865015 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8877 04:41:34.871701 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8878 04:41:34.871781 ==
8879 04:41:34.875006 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 04:41:34.878157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 04:41:34.878238 ==
8882 04:41:34.878327 DQS Delay:
8883 04:41:34.881573 DQS0 = 0, DQS1 = 0
8884 04:41:34.881666 DQM Delay:
8885 04:41:34.884869 DQM0 = 132, DQM1 = 128
8886 04:41:34.884942 DQ Delay:
8887 04:41:34.888114 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8888 04:41:34.891635 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8889 04:41:34.894714 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8890 04:41:34.898107 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8891 04:41:34.898193
8892 04:41:34.898277
8893 04:41:34.901447 ==
8894 04:41:34.901562 Dram Type= 6, Freq= 0, CH_1, rank 1
8895 04:41:34.908193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8896 04:41:34.908275 ==
8897 04:41:34.908341
8898 04:41:34.908408
8899 04:41:34.911471 TX Vref Scan disable
8900 04:41:34.911542 == TX Byte 0 ==
8901 04:41:34.914634 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8902 04:41:34.921310 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8903 04:41:34.921387 == TX Byte 1 ==
8904 04:41:34.924612 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8905 04:41:34.931312 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8906 04:41:34.931391 ==
8907 04:41:34.934715 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 04:41:34.937915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 04:41:34.937992 ==
8910 04:41:34.950866
8911 04:41:34.954111 TX Vref early break, caculate TX vref
8912 04:41:34.957339 TX Vref=16, minBit 0, minWin=23, winSum=385
8913 04:41:34.961038 TX Vref=18, minBit 0, minWin=24, winSum=395
8914 04:41:34.964341 TX Vref=20, minBit 1, minWin=24, winSum=407
8915 04:41:34.967643 TX Vref=22, minBit 0, minWin=25, winSum=411
8916 04:41:34.970841 TX Vref=24, minBit 0, minWin=25, winSum=422
8917 04:41:34.977649 TX Vref=26, minBit 0, minWin=25, winSum=424
8918 04:41:34.980715 TX Vref=28, minBit 5, minWin=25, winSum=426
8919 04:41:34.984074 TX Vref=30, minBit 0, minWin=25, winSum=421
8920 04:41:34.987314 TX Vref=32, minBit 5, minWin=24, winSum=419
8921 04:41:34.990576 TX Vref=34, minBit 1, minWin=23, winSum=403
8922 04:41:34.997363 [TxChooseVref] Worse bit 5, Min win 25, Win sum 426, Final Vref 28
8923 04:41:34.997449
8924 04:41:35.000714 Final TX Range 0 Vref 28
8925 04:41:35.000787
8926 04:41:35.000857 ==
8927 04:41:35.003875 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 04:41:35.007122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 04:41:35.007207 ==
8930 04:41:35.007271
8931 04:41:35.007331
8932 04:41:35.010656 TX Vref Scan disable
8933 04:41:35.017104 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8934 04:41:35.017180 == TX Byte 0 ==
8935 04:41:35.020618 u2DelayCellOfst[0]=18 cells (5 PI)
8936 04:41:35.023615 u2DelayCellOfst[1]=11 cells (3 PI)
8937 04:41:35.027215 u2DelayCellOfst[2]=0 cells (0 PI)
8938 04:41:35.030270 u2DelayCellOfst[3]=7 cells (2 PI)
8939 04:41:35.033648 u2DelayCellOfst[4]=7 cells (2 PI)
8940 04:41:35.037042 u2DelayCellOfst[5]=22 cells (6 PI)
8941 04:41:35.040593 u2DelayCellOfst[6]=18 cells (5 PI)
8942 04:41:35.040665 u2DelayCellOfst[7]=7 cells (2 PI)
8943 04:41:35.046970 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8944 04:41:35.050104 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8945 04:41:35.053590 == TX Byte 1 ==
8946 04:41:35.053666 u2DelayCellOfst[8]=0 cells (0 PI)
8947 04:41:35.057039 u2DelayCellOfst[9]=7 cells (2 PI)
8948 04:41:35.060244 u2DelayCellOfst[10]=15 cells (4 PI)
8949 04:41:35.063593 u2DelayCellOfst[11]=7 cells (2 PI)
8950 04:41:35.066873 u2DelayCellOfst[12]=18 cells (5 PI)
8951 04:41:35.070326 u2DelayCellOfst[13]=18 cells (5 PI)
8952 04:41:35.073562 u2DelayCellOfst[14]=22 cells (6 PI)
8953 04:41:35.076677 u2DelayCellOfst[15]=22 cells (6 PI)
8954 04:41:35.080023 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8955 04:41:35.086778 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8956 04:41:35.086862 DramC Write-DBI on
8957 04:41:35.086928 ==
8958 04:41:35.090039 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 04:41:35.093335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 04:41:35.096593 ==
8961 04:41:35.096671
8962 04:41:35.096733
8963 04:41:35.096791 TX Vref Scan disable
8964 04:41:35.100195 == TX Byte 0 ==
8965 04:41:35.103504 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8966 04:41:35.106652 == TX Byte 1 ==
8967 04:41:35.110127 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8968 04:41:35.113270 DramC Write-DBI off
8969 04:41:35.113343
8970 04:41:35.113412 [DATLAT]
8971 04:41:35.113471 Freq=1600, CH1 RK1
8972 04:41:35.113568
8973 04:41:35.116676 DATLAT Default: 0xf
8974 04:41:35.119902 0, 0xFFFF, sum = 0
8975 04:41:35.119974 1, 0xFFFF, sum = 0
8976 04:41:35.123177 2, 0xFFFF, sum = 0
8977 04:41:35.123248 3, 0xFFFF, sum = 0
8978 04:41:35.126416 4, 0xFFFF, sum = 0
8979 04:41:35.126490 5, 0xFFFF, sum = 0
8980 04:41:35.129672 6, 0xFFFF, sum = 0
8981 04:41:35.129752 7, 0xFFFF, sum = 0
8982 04:41:35.133148 8, 0xFFFF, sum = 0
8983 04:41:35.133219 9, 0xFFFF, sum = 0
8984 04:41:35.136599 10, 0xFFFF, sum = 0
8985 04:41:35.136675 11, 0xFFFF, sum = 0
8986 04:41:35.139755 12, 0xFFFF, sum = 0
8987 04:41:35.139832 13, 0x8FFF, sum = 0
8988 04:41:35.143021 14, 0x0, sum = 1
8989 04:41:35.143094 15, 0x0, sum = 2
8990 04:41:35.146554 16, 0x0, sum = 3
8991 04:41:35.146627 17, 0x0, sum = 4
8992 04:41:35.149759 best_step = 15
8993 04:41:35.149831
8994 04:41:35.149898 ==
8995 04:41:35.153011 Dram Type= 6, Freq= 0, CH_1, rank 1
8996 04:41:35.156382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8997 04:41:35.156456 ==
8998 04:41:35.159754 RX Vref Scan: 0
8999 04:41:35.159827
9000 04:41:35.159887 RX Vref 0 -> 0, step: 1
9001 04:41:35.159943
9002 04:41:35.163259 RX Delay 11 -> 252, step: 4
9003 04:41:35.169747 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9004 04:41:35.172988 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9005 04:41:35.176140 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9006 04:41:35.179672 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9007 04:41:35.183038 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9008 04:41:35.186266 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9009 04:41:35.192952 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9010 04:41:35.196295 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9011 04:41:35.199547 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9012 04:41:35.202734 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9013 04:41:35.205963 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9014 04:41:35.212769 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9015 04:41:35.216059 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9016 04:41:35.219288 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
9017 04:41:35.222544 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9018 04:41:35.229581 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9019 04:41:35.229655 ==
9020 04:41:35.232623 Dram Type= 6, Freq= 0, CH_1, rank 1
9021 04:41:35.235952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9022 04:41:35.236037 ==
9023 04:41:35.236117 DQS Delay:
9024 04:41:35.239151 DQS0 = 0, DQS1 = 0
9025 04:41:35.239224 DQM Delay:
9026 04:41:35.242780 DQM0 = 129, DQM1 = 125
9027 04:41:35.242849 DQ Delay:
9028 04:41:35.245951 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =126
9029 04:41:35.249258 DQ4 =126, DQ5 =140, DQ6 =142, DQ7 =124
9030 04:41:35.252604 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9031 04:41:35.256200 DQ12 =132, DQ13 =134, DQ14 =132, DQ15 =136
9032 04:41:35.256279
9033 04:41:35.256344
9034 04:41:35.256403
9035 04:41:35.259395 [DramC_TX_OE_Calibration] TA2
9036 04:41:35.262833 Original DQ_B0 (3 6) =30, OEN = 27
9037 04:41:35.266269 Original DQ_B1 (3 6) =30, OEN = 27
9038 04:41:35.269312 24, 0x0, End_B0=24 End_B1=24
9039 04:41:35.272504 25, 0x0, End_B0=25 End_B1=25
9040 04:41:35.272579 26, 0x0, End_B0=26 End_B1=26
9041 04:41:35.276141 27, 0x0, End_B0=27 End_B1=27
9042 04:41:35.279218 28, 0x0, End_B0=28 End_B1=28
9043 04:41:35.282444 29, 0x0, End_B0=29 End_B1=29
9044 04:41:35.285694 30, 0x0, End_B0=30 End_B1=30
9045 04:41:35.285799 31, 0x4545, End_B0=30 End_B1=30
9046 04:41:35.289145 Byte0 end_step=30 best_step=27
9047 04:41:35.292307 Byte1 end_step=30 best_step=27
9048 04:41:35.295860 Byte0 TX OE(2T, 0.5T) = (3, 3)
9049 04:41:35.299089 Byte1 TX OE(2T, 0.5T) = (3, 3)
9050 04:41:35.299171
9051 04:41:35.299245
9052 04:41:35.305771 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9053 04:41:35.309091 CH1 RK1: MR19=303, MR18=F1B
9054 04:41:35.315734 CH1_RK1: MR19=0x303, MR18=0xF1B, DQSOSC=396, MR23=63, INC=23, DEC=15
9055 04:41:35.319072 [RxdqsGatingPostProcess] freq 1600
9056 04:41:35.325354 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9057 04:41:35.328566 best DQS0 dly(2T, 0.5T) = (1, 1)
9058 04:41:35.328648 best DQS1 dly(2T, 0.5T) = (1, 1)
9059 04:41:35.331884 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9060 04:41:35.335201 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9061 04:41:35.338491 best DQS0 dly(2T, 0.5T) = (1, 1)
9062 04:41:35.342043 best DQS1 dly(2T, 0.5T) = (1, 1)
9063 04:41:35.345359 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9064 04:41:35.348545 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9065 04:41:35.352103 Pre-setting of DQS Precalculation
9066 04:41:35.355392 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9067 04:41:35.365045 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9068 04:41:35.371647 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9069 04:41:35.371730
9070 04:41:35.371808
9071 04:41:35.375253 [Calibration Summary] 3200 Mbps
9072 04:41:35.375325 CH 0, Rank 0
9073 04:41:35.378197 SW Impedance : PASS
9074 04:41:35.378266 DUTY Scan : NO K
9075 04:41:35.381670 ZQ Calibration : PASS
9076 04:41:35.385141 Jitter Meter : NO K
9077 04:41:35.385211 CBT Training : PASS
9078 04:41:35.388430 Write leveling : PASS
9079 04:41:35.391506 RX DQS gating : PASS
9080 04:41:35.391586 RX DQ/DQS(RDDQC) : PASS
9081 04:41:35.394963 TX DQ/DQS : PASS
9082 04:41:35.398173 RX DATLAT : PASS
9083 04:41:35.398250 RX DQ/DQS(Engine): PASS
9084 04:41:35.401637 TX OE : PASS
9085 04:41:35.401708 All Pass.
9086 04:41:35.401775
9087 04:41:35.404943 CH 0, Rank 1
9088 04:41:35.405015 SW Impedance : PASS
9089 04:41:35.408326 DUTY Scan : NO K
9090 04:41:35.411576 ZQ Calibration : PASS
9091 04:41:35.411657 Jitter Meter : NO K
9092 04:41:35.414883 CBT Training : PASS
9093 04:41:35.418071 Write leveling : PASS
9094 04:41:35.418152 RX DQS gating : PASS
9095 04:41:35.421444 RX DQ/DQS(RDDQC) : PASS
9096 04:41:35.424700 TX DQ/DQS : PASS
9097 04:41:35.424781 RX DATLAT : PASS
9098 04:41:35.427948 RX DQ/DQS(Engine): PASS
9099 04:41:35.428059 TX OE : PASS
9100 04:41:35.431216 All Pass.
9101 04:41:35.431296
9102 04:41:35.431361 CH 1, Rank 0
9103 04:41:35.434549 SW Impedance : PASS
9104 04:41:35.434629 DUTY Scan : NO K
9105 04:41:35.437884 ZQ Calibration : PASS
9106 04:41:35.441238 Jitter Meter : NO K
9107 04:41:35.441344 CBT Training : PASS
9108 04:41:35.444489 Write leveling : PASS
9109 04:41:35.447811 RX DQS gating : PASS
9110 04:41:35.447892 RX DQ/DQS(RDDQC) : PASS
9111 04:41:35.451087 TX DQ/DQS : PASS
9112 04:41:35.454604 RX DATLAT : PASS
9113 04:41:35.454685 RX DQ/DQS(Engine): PASS
9114 04:41:35.457689 TX OE : PASS
9115 04:41:35.457774 All Pass.
9116 04:41:35.457838
9117 04:41:35.461393 CH 1, Rank 1
9118 04:41:35.461480 SW Impedance : PASS
9119 04:41:35.464760 DUTY Scan : NO K
9120 04:41:35.467930 ZQ Calibration : PASS
9121 04:41:35.468011 Jitter Meter : NO K
9122 04:41:35.471254 CBT Training : PASS
9123 04:41:35.474446 Write leveling : PASS
9124 04:41:35.474526 RX DQS gating : PASS
9125 04:41:35.477877 RX DQ/DQS(RDDQC) : PASS
9126 04:41:35.480878 TX DQ/DQS : PASS
9127 04:41:35.480959 RX DATLAT : PASS
9128 04:41:35.484484 RX DQ/DQS(Engine): PASS
9129 04:41:35.484565 TX OE : PASS
9130 04:41:35.487692 All Pass.
9131 04:41:35.487773
9132 04:41:35.487838 DramC Write-DBI on
9133 04:41:35.491138 PER_BANK_REFRESH: Hybrid Mode
9134 04:41:35.494527 TX_TRACKING: ON
9135 04:41:35.500606 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9136 04:41:35.510766 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9137 04:41:35.517174 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9138 04:41:35.520595 [FAST_K] Save calibration result to emmc
9139 04:41:35.523985 sync common calibartion params.
9140 04:41:35.527173 sync cbt_mode0:1, 1:1
9141 04:41:35.527277 dram_init: ddr_geometry: 2
9142 04:41:35.530289 dram_init: ddr_geometry: 2
9143 04:41:35.533847 dram_init: ddr_geometry: 2
9144 04:41:35.533949 0:dram_rank_size:100000000
9145 04:41:35.537015 1:dram_rank_size:100000000
9146 04:41:35.543564 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9147 04:41:35.546852 DFS_SHUFFLE_HW_MODE: ON
9148 04:41:35.550101 dramc_set_vcore_voltage set vcore to 725000
9149 04:41:35.550172 Read voltage for 1600, 0
9150 04:41:35.553411 Vio18 = 0
9151 04:41:35.553526 Vcore = 725000
9152 04:41:35.553597 Vdram = 0
9153 04:41:35.557043 Vddq = 0
9154 04:41:35.557117 Vmddr = 0
9155 04:41:35.560176 switch to 3200 Mbps bootup
9156 04:41:35.560247 [DramcRunTimeConfig]
9157 04:41:35.560308 PHYPLL
9158 04:41:35.563381 DPM_CONTROL_AFTERK: ON
9159 04:41:35.566787 PER_BANK_REFRESH: ON
9160 04:41:35.566861 REFRESH_OVERHEAD_REDUCTION: ON
9161 04:41:35.570251 CMD_PICG_NEW_MODE: OFF
9162 04:41:35.573519 XRTWTW_NEW_MODE: ON
9163 04:41:35.573630 XRTRTR_NEW_MODE: ON
9164 04:41:35.576833 TX_TRACKING: ON
9165 04:41:35.576935 RDSEL_TRACKING: OFF
9166 04:41:35.580230 DQS Precalculation for DVFS: ON
9167 04:41:35.580342 RX_TRACKING: OFF
9168 04:41:35.583521 HW_GATING DBG: ON
9169 04:41:35.586557 ZQCS_ENABLE_LP4: ON
9170 04:41:35.586662 RX_PICG_NEW_MODE: ON
9171 04:41:35.590121 TX_PICG_NEW_MODE: ON
9172 04:41:35.590205 ENABLE_RX_DCM_DPHY: ON
9173 04:41:35.593272 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9174 04:41:35.596726 DUMMY_READ_FOR_TRACKING: OFF
9175 04:41:35.600159 !!! SPM_CONTROL_AFTERK: OFF
9176 04:41:35.603351 !!! SPM could not control APHY
9177 04:41:35.603452 IMPEDANCE_TRACKING: ON
9178 04:41:35.606565 TEMP_SENSOR: ON
9179 04:41:35.606669 HW_SAVE_FOR_SR: OFF
9180 04:41:35.610058 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9181 04:41:35.613277 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9182 04:41:35.616531 Read ODT Tracking: ON
9183 04:41:35.616637 Refresh Rate DeBounce: ON
9184 04:41:35.619732 DFS_NO_QUEUE_FLUSH: ON
9185 04:41:35.623087 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9186 04:41:35.626616 ENABLE_DFS_RUNTIME_MRW: OFF
9187 04:41:35.629922 DDR_RESERVE_NEW_MODE: ON
9188 04:41:35.629999 MR_CBT_SWITCH_FREQ: ON
9189 04:41:35.633105 =========================
9190 04:41:35.651375 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9191 04:41:35.654689 dram_init: ddr_geometry: 2
9192 04:41:35.672750 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9193 04:41:35.676478 dram_init: dram init end (result: 0)
9194 04:41:35.683131 DRAM-K: Full calibration passed in 24545 msecs
9195 04:41:35.686036 MRC: failed to locate region type 0.
9196 04:41:35.686110 DRAM rank0 size:0x100000000,
9197 04:41:35.689356 DRAM rank1 size=0x100000000
9198 04:41:35.699420 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9199 04:41:35.706211 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9200 04:41:35.712664 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9201 04:41:35.719176 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9202 04:41:35.722583 DRAM rank0 size:0x100000000,
9203 04:41:35.725890 DRAM rank1 size=0x100000000
9204 04:41:35.725968 CBMEM:
9205 04:41:35.729457 IMD: root @ 0xfffff000 254 entries.
9206 04:41:35.732677 IMD: root @ 0xffffec00 62 entries.
9207 04:41:35.735941 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9208 04:41:35.739151 WARNING: RO_VPD is uninitialized or empty.
9209 04:41:35.745802 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9210 04:41:35.753074 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9211 04:41:35.765648 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9212 04:41:35.777051 BS: romstage times (exec / console): total (unknown) / 24012 ms
9213 04:41:35.777138
9214 04:41:35.777202
9215 04:41:35.787135 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9216 04:41:35.790369 ARM64: Exception handlers installed.
9217 04:41:35.793593 ARM64: Testing exception
9218 04:41:35.796757 ARM64: Done test exception
9219 04:41:35.796847 Enumerating buses...
9220 04:41:35.800512 Show all devs... Before device enumeration.
9221 04:41:35.803798 Root Device: enabled 1
9222 04:41:35.807059 CPU_CLUSTER: 0: enabled 1
9223 04:41:35.807138 CPU: 00: enabled 1
9224 04:41:35.810258 Compare with tree...
9225 04:41:35.810331 Root Device: enabled 1
9226 04:41:35.813776 CPU_CLUSTER: 0: enabled 1
9227 04:41:35.816998 CPU: 00: enabled 1
9228 04:41:35.817075 Root Device scanning...
9229 04:41:35.820153 scan_static_bus for Root Device
9230 04:41:35.823408 CPU_CLUSTER: 0 enabled
9231 04:41:35.826783 scan_static_bus for Root Device done
9232 04:41:35.830043 scan_bus: bus Root Device finished in 8 msecs
9233 04:41:35.830120 done
9234 04:41:35.836706 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9235 04:41:35.840077 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9236 04:41:35.846565 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9237 04:41:35.850252 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9238 04:41:35.853337 Allocating resources...
9239 04:41:35.856616 Reading resources...
9240 04:41:35.859955 Root Device read_resources bus 0 link: 0
9241 04:41:35.860036 DRAM rank0 size:0x100000000,
9242 04:41:35.863179 DRAM rank1 size=0x100000000
9243 04:41:35.866364 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9244 04:41:35.869832 CPU: 00 missing read_resources
9245 04:41:35.876476 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9246 04:41:35.879676 Root Device read_resources bus 0 link: 0 done
9247 04:41:35.879755 Done reading resources.
9248 04:41:35.886125 Show resources in subtree (Root Device)...After reading.
9249 04:41:35.889470 Root Device child on link 0 CPU_CLUSTER: 0
9250 04:41:35.892816 CPU_CLUSTER: 0 child on link 0 CPU: 00
9251 04:41:35.902529 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9252 04:41:35.902617 CPU: 00
9253 04:41:35.905861 Root Device assign_resources, bus 0 link: 0
9254 04:41:35.909548 CPU_CLUSTER: 0 missing set_resources
9255 04:41:35.916042 Root Device assign_resources, bus 0 link: 0 done
9256 04:41:35.916131 Done setting resources.
9257 04:41:35.922703 Show resources in subtree (Root Device)...After assigning values.
9258 04:41:35.925959 Root Device child on link 0 CPU_CLUSTER: 0
9259 04:41:35.929231 CPU_CLUSTER: 0 child on link 0 CPU: 00
9260 04:41:35.939243 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9261 04:41:35.939330 CPU: 00
9262 04:41:35.942494 Done allocating resources.
9263 04:41:35.949361 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9264 04:41:35.949440 Enabling resources...
9265 04:41:35.949546 done.
9266 04:41:35.955798 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9267 04:41:35.955877 Initializing devices...
9268 04:41:35.958949 Root Device init
9269 04:41:35.962408 init hardware done!
9270 04:41:35.962486 0x00000018: ctrlr->caps
9271 04:41:35.965752 52.000 MHz: ctrlr->f_max
9272 04:41:35.965830 0.400 MHz: ctrlr->f_min
9273 04:41:35.969137 0x40ff8080: ctrlr->voltages
9274 04:41:35.972375 sclk: 390625
9275 04:41:35.972475 Bus Width = 1
9276 04:41:35.972564 sclk: 390625
9277 04:41:35.975466 Bus Width = 1
9278 04:41:35.975540 Early init status = 3
9279 04:41:35.982067 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9280 04:41:35.985683 in-header: 03 fc 00 00 01 00 00 00
9281 04:41:35.989040 in-data: 00
9282 04:41:35.992088 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9283 04:41:35.997311 in-header: 03 fd 00 00 00 00 00 00
9284 04:41:36.000602 in-data:
9285 04:41:36.003922 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9286 04:41:36.008132 in-header: 03 fc 00 00 01 00 00 00
9287 04:41:36.011407 in-data: 00
9288 04:41:36.014661 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9289 04:41:36.020403 in-header: 03 fd 00 00 00 00 00 00
9290 04:41:36.023534 in-data:
9291 04:41:36.026922 [SSUSB] Setting up USB HOST controller...
9292 04:41:36.030302 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9293 04:41:36.034026 [SSUSB] phy power-on done.
9294 04:41:36.037309 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9295 04:41:36.043781 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9296 04:41:36.047234 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9297 04:41:36.053422 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9298 04:41:36.060023 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9299 04:41:36.066917 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9300 04:41:36.073368 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9301 04:41:36.079948 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9302 04:41:36.083469 SPM: binary array size = 0x9dc
9303 04:41:36.086572 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9304 04:41:36.093108 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9305 04:41:36.099996 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9306 04:41:36.106521 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9307 04:41:36.109824 configure_display: Starting display init
9308 04:41:36.143626 anx7625_power_on_init: Init interface.
9309 04:41:36.146838 anx7625_disable_pd_protocol: Disabled PD feature.
9310 04:41:36.150396 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9311 04:41:36.178180 anx7625_start_dp_work: Secure OCM version=00
9312 04:41:36.181374 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9313 04:41:36.196041 sp_tx_get_edid_block: EDID Block = 1
9314 04:41:36.298886 Extracted contents:
9315 04:41:36.302146 header: 00 ff ff ff ff ff ff 00
9316 04:41:36.305439 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9317 04:41:36.308759 version: 01 04
9318 04:41:36.311835 basic params: 95 1f 11 78 0a
9319 04:41:36.315592 chroma info: 76 90 94 55 54 90 27 21 50 54
9320 04:41:36.318739 established: 00 00 00
9321 04:41:36.325257 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9322 04:41:36.328466 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9323 04:41:36.335155 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9324 04:41:36.341865 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9325 04:41:36.348353 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9326 04:41:36.351715 extensions: 00
9327 04:41:36.351797 checksum: fb
9328 04:41:36.351863
9329 04:41:36.354876 Manufacturer: IVO Model 57d Serial Number 0
9330 04:41:36.358143 Made week 0 of 2020
9331 04:41:36.361472 EDID version: 1.4
9332 04:41:36.361576 Digital display
9333 04:41:36.365079 6 bits per primary color channel
9334 04:41:36.365162 DisplayPort interface
9335 04:41:36.368355 Maximum image size: 31 cm x 17 cm
9336 04:41:36.371618 Gamma: 220%
9337 04:41:36.371698 Check DPMS levels
9338 04:41:36.374553 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9339 04:41:36.381261 First detailed timing is preferred timing
9340 04:41:36.381346 Established timings supported:
9341 04:41:36.384813 Standard timings supported:
9342 04:41:36.388170 Detailed timings
9343 04:41:36.391289 Hex of detail: 383680a07038204018303c0035ae10000019
9344 04:41:36.398074 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9345 04:41:36.401470 0780 0798 07c8 0820 hborder 0
9346 04:41:36.404667 0438 043b 0447 0458 vborder 0
9347 04:41:36.407968 -hsync -vsync
9348 04:41:36.408051 Did detailed timing
9349 04:41:36.414438 Hex of detail: 000000000000000000000000000000000000
9350 04:41:36.417857 Manufacturer-specified data, tag 0
9351 04:41:36.421181 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9352 04:41:36.424413 ASCII string: InfoVision
9353 04:41:36.427548 Hex of detail: 000000fe00523134304e574635205248200a
9354 04:41:36.430989 ASCII string: R140NWF5 RH
9355 04:41:36.431069 Checksum
9356 04:41:36.434152 Checksum: 0xfb (valid)
9357 04:41:36.437721 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9358 04:41:36.440769 DSI data_rate: 832800000 bps
9359 04:41:36.447392 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9360 04:41:36.450740 anx7625_parse_edid: pixelclock(138800).
9361 04:41:36.453972 hactive(1920), hsync(48), hfp(24), hbp(88)
9362 04:41:36.457493 vactive(1080), vsync(12), vfp(3), vbp(17)
9363 04:41:36.460844 anx7625_dsi_config: config dsi.
9364 04:41:36.467443 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9365 04:41:36.480855 anx7625_dsi_config: success to config DSI
9366 04:41:36.484046 anx7625_dp_start: MIPI phy setup OK.
9367 04:41:36.487500 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9368 04:41:36.490927 mtk_ddp_mode_set invalid vrefresh 60
9369 04:41:36.494100 main_disp_path_setup
9370 04:41:36.494175 ovl_layer_smi_id_en
9371 04:41:36.497377 ovl_layer_smi_id_en
9372 04:41:36.497499 ccorr_config
9373 04:41:36.497604 aal_config
9374 04:41:36.500622 gamma_config
9375 04:41:36.500725 postmask_config
9376 04:41:36.503750 dither_config
9377 04:41:36.507081 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9378 04:41:36.513849 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9379 04:41:36.517189 Root Device init finished in 554 msecs
9380 04:41:36.520385 CPU_CLUSTER: 0 init
9381 04:41:36.527060 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9382 04:41:36.530462 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9383 04:41:36.533835 APU_MBOX 0x190000b0 = 0x10001
9384 04:41:36.537123 APU_MBOX 0x190001b0 = 0x10001
9385 04:41:36.540352 APU_MBOX 0x190005b0 = 0x10001
9386 04:41:36.543960 APU_MBOX 0x190006b0 = 0x10001
9387 04:41:36.547081 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9388 04:41:36.559675 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9389 04:41:36.572430 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9390 04:41:36.578993 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9391 04:41:36.590259 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9392 04:41:36.599581 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9393 04:41:36.602860 CPU_CLUSTER: 0 init finished in 81 msecs
9394 04:41:36.606106 Devices initialized
9395 04:41:36.609682 Show all devs... After init.
9396 04:41:36.609765 Root Device: enabled 1
9397 04:41:36.612996 CPU_CLUSTER: 0: enabled 1
9398 04:41:36.615945 CPU: 00: enabled 1
9399 04:41:36.619241 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9400 04:41:36.622951 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9401 04:41:36.626117 ELOG: NV offset 0x57f000 size 0x1000
9402 04:41:36.632813 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9403 04:41:36.639154 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9404 04:41:36.642397 ELOG: Event(17) added with size 13 at 2024-02-04 04:41:38 UTC
9405 04:41:36.649203 out: cmd=0x121: 03 db 21 01 00 00 00 00
9406 04:41:36.652452 in-header: 03 7b 00 00 2c 00 00 00
9407 04:41:36.662455 in-data: e4 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9408 04:41:36.668829 ELOG: Event(A1) added with size 10 at 2024-02-04 04:41:38 UTC
9409 04:41:36.675706 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9410 04:41:36.682229 ELOG: Event(A0) added with size 9 at 2024-02-04 04:41:38 UTC
9411 04:41:36.685840 elog_add_boot_reason: Logged dev mode boot
9412 04:41:36.692585 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9413 04:41:36.692668 Finalize devices...
9414 04:41:36.695697 Devices finalized
9415 04:41:36.699162 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9416 04:41:36.702272 Writing coreboot table at 0xffe64000
9417 04:41:36.705965 0. 000000000010a000-0000000000113fff: RAMSTAGE
9418 04:41:36.708901 1. 0000000040000000-00000000400fffff: RAM
9419 04:41:36.715590 2. 0000000040100000-000000004032afff: RAMSTAGE
9420 04:41:36.719213 3. 000000004032b000-00000000545fffff: RAM
9421 04:41:36.722457 4. 0000000054600000-000000005465ffff: BL31
9422 04:41:36.725745 5. 0000000054660000-00000000ffe63fff: RAM
9423 04:41:36.732181 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9424 04:41:36.735504 7. 0000000100000000-000000023fffffff: RAM
9425 04:41:36.739030 Passing 5 GPIOs to payload:
9426 04:41:36.742250 NAME | PORT | POLARITY | VALUE
9427 04:41:36.749036 EC in RW | 0x000000aa | low | undefined
9428 04:41:36.751985 EC interrupt | 0x00000005 | low | undefined
9429 04:41:36.755187 TPM interrupt | 0x000000ab | high | undefined
9430 04:41:36.761847 SD card detect | 0x00000011 | high | undefined
9431 04:41:36.765135 speaker enable | 0x00000093 | high | undefined
9432 04:41:36.768507 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9433 04:41:36.772188 in-header: 03 f9 00 00 02 00 00 00
9434 04:41:36.775235 in-data: 02 00
9435 04:41:36.775317 ADC[4]: Raw value=896300 ID=7
9436 04:41:36.778784 ADC[3]: Raw value=213440 ID=1
9437 04:41:36.781822 RAM Code: 0x71
9438 04:41:36.785105 ADC[6]: Raw value=74722 ID=0
9439 04:41:36.785218 ADC[5]: Raw value=211960 ID=1
9440 04:41:36.788347 SKU Code: 0x1
9441 04:41:36.791844 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 81d2
9442 04:41:36.795044 coreboot table: 964 bytes.
9443 04:41:36.798242 IMD ROOT 0. 0xfffff000 0x00001000
9444 04:41:36.801810 IMD SMALL 1. 0xffffe000 0x00001000
9445 04:41:36.805137 RO MCACHE 2. 0xffffc000 0x00001104
9446 04:41:36.808346 CONSOLE 3. 0xfff7c000 0x00080000
9447 04:41:36.811645 FMAP 4. 0xfff7b000 0x00000452
9448 04:41:36.815164 TIME STAMP 5. 0xfff7a000 0x00000910
9449 04:41:36.818354 VBOOT WORK 6. 0xfff66000 0x00014000
9450 04:41:36.821370 RAMOOPS 7. 0xffe66000 0x00100000
9451 04:41:36.824808 COREBOOT 8. 0xffe64000 0x00002000
9452 04:41:36.828012 IMD small region:
9453 04:41:36.831384 IMD ROOT 0. 0xffffec00 0x00000400
9454 04:41:36.834567 VPD 1. 0xffffeb80 0x0000006c
9455 04:41:36.837835 MMC STATUS 2. 0xffffeb60 0x00000004
9456 04:41:36.841602 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9457 04:41:36.844730 Probing TPM: done!
9458 04:41:36.848366 Connected to device vid:did:rid of 1ae0:0028:00
9459 04:41:36.858601 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9460 04:41:36.862169 Initialized TPM device CR50 revision 0
9461 04:41:36.865652 Checking cr50 for pending updates
9462 04:41:36.869417 Reading cr50 TPM mode
9463 04:41:36.878077 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9464 04:41:36.884529 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9465 04:41:36.924687 read SPI 0x3990ec 0x4f1b0: 34858 us, 9295 KB/s, 74.360 Mbps
9466 04:41:36.928221 Checking segment from ROM address 0x40100000
9467 04:41:36.931394 Checking segment from ROM address 0x4010001c
9468 04:41:36.937858 Loading segment from ROM address 0x40100000
9469 04:41:36.937942 code (compression=0)
9470 04:41:36.948157 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9471 04:41:36.954663 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9472 04:41:36.954747 it's not compressed!
9473 04:41:36.961359 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9474 04:41:36.964587 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9475 04:41:36.984970 Loading segment from ROM address 0x4010001c
9476 04:41:36.985053 Entry Point 0x80000000
9477 04:41:36.988587 Loaded segments
9478 04:41:36.991860 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9479 04:41:36.998324 Jumping to boot code at 0x80000000(0xffe64000)
9480 04:41:37.005308 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9481 04:41:37.011658 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9482 04:41:37.019685 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9483 04:41:37.022811 Checking segment from ROM address 0x40100000
9484 04:41:37.026424 Checking segment from ROM address 0x4010001c
9485 04:41:37.032860 Loading segment from ROM address 0x40100000
9486 04:41:37.032943 code (compression=1)
9487 04:41:37.039477 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9488 04:41:37.049182 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9489 04:41:37.049265 using LZMA
9490 04:41:37.058109 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9491 04:41:37.064639 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9492 04:41:37.068001 Loading segment from ROM address 0x4010001c
9493 04:41:37.068084 Entry Point 0x54601000
9494 04:41:37.071610 Loaded segments
9495 04:41:37.074689 NOTICE: MT8192 bl31_setup
9496 04:41:37.081489 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9497 04:41:37.084845 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9498 04:41:37.088231 WARNING: region 0:
9499 04:41:37.091489 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 04:41:37.091572 WARNING: region 1:
9501 04:41:37.098120 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9502 04:41:37.101835 WARNING: region 2:
9503 04:41:37.104982 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9504 04:41:37.108309 WARNING: region 3:
9505 04:41:37.111822 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9506 04:41:37.114913 WARNING: region 4:
9507 04:41:37.121597 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9508 04:41:37.121722 WARNING: region 5:
9509 04:41:37.124705 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9510 04:41:37.128403 WARNING: region 6:
9511 04:41:37.131623 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 04:41:37.131731 WARNING: region 7:
9513 04:41:37.138109 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 04:41:37.144968 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9515 04:41:37.148124 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9516 04:41:37.151546 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9517 04:41:37.158444 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9518 04:41:37.161626 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9519 04:41:37.164916 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9520 04:41:37.171599 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9521 04:41:37.174949 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9522 04:41:37.178265 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9523 04:41:37.184893 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9524 04:41:37.188332 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9525 04:41:37.194918 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9526 04:41:37.198213 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9527 04:41:37.201425 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9528 04:41:37.208136 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9529 04:41:37.211793 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9530 04:41:37.214960 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9531 04:41:37.221455 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9532 04:41:37.225011 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9533 04:41:37.231631 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9534 04:41:37.235052 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9535 04:41:37.238284 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9536 04:41:37.244823 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9537 04:41:37.248120 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9538 04:41:37.255218 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9539 04:41:37.258646 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9540 04:41:37.261764 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9541 04:41:37.268224 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9542 04:41:37.271780 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9543 04:41:37.274937 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9544 04:41:37.281683 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9545 04:41:37.285099 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9546 04:41:37.291689 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9547 04:41:37.294849 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9548 04:41:37.298323 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9549 04:41:37.301636 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9550 04:41:37.304922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9551 04:41:37.311579 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9552 04:41:37.314830 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9553 04:41:37.318407 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9554 04:41:37.321798 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9555 04:41:37.328305 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9556 04:41:37.331694 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9557 04:41:37.335269 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9558 04:41:37.338273 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9559 04:41:37.345087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9560 04:41:37.348095 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9561 04:41:37.351729 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9562 04:41:37.358242 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9563 04:41:37.361446 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9564 04:41:37.368019 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9565 04:41:37.371545 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9566 04:41:37.374829 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9567 04:41:37.381538 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9568 04:41:37.384897 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9569 04:41:37.391311 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9570 04:41:37.394985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9571 04:41:37.401310 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9572 04:41:37.404986 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9573 04:41:37.408098 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9574 04:41:37.414820 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9575 04:41:37.418043 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9576 04:41:37.424776 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9577 04:41:37.428077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9578 04:41:37.434644 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9579 04:41:37.437954 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9580 04:41:37.444662 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9581 04:41:37.448229 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9582 04:41:37.451489 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9583 04:41:37.458239 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9584 04:41:37.461386 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9585 04:41:37.468024 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9586 04:41:37.471288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9587 04:41:37.474855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9588 04:41:37.481356 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9589 04:41:37.484601 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9590 04:41:37.491422 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9591 04:41:37.494813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9592 04:41:37.501337 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9593 04:41:37.504581 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9594 04:41:37.511480 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9595 04:41:37.514698 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9596 04:41:37.518025 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9597 04:41:37.524847 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9598 04:41:37.528209 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9599 04:41:37.534789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9600 04:41:37.538078 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9601 04:41:37.544734 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9602 04:41:37.547990 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9603 04:41:37.551612 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9604 04:41:37.558009 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9605 04:41:37.561197 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9606 04:41:37.568085 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9607 04:41:37.571153 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9608 04:41:37.577810 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9609 04:41:37.581344 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9610 04:41:37.584711 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9611 04:41:37.591102 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9612 04:41:37.594393 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9613 04:41:37.597884 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9614 04:41:37.601138 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9615 04:41:37.607499 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9616 04:41:37.611134 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9617 04:41:37.617717 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9618 04:41:37.621109 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9619 04:41:37.623971 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9620 04:41:37.630925 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9621 04:41:37.634114 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9622 04:41:37.640593 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9623 04:41:37.644404 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9624 04:41:37.647487 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9625 04:41:37.654191 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9626 04:41:37.657209 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9627 04:41:37.663704 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9628 04:41:37.666969 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9629 04:41:37.670440 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9630 04:41:37.677168 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9631 04:41:37.680375 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9632 04:41:37.683670 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9633 04:41:37.690247 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9634 04:41:37.693382 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9635 04:41:37.697063 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9636 04:41:37.700309 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9637 04:41:37.706761 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9638 04:41:37.710372 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9639 04:41:37.713458 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9640 04:41:37.720408 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9641 04:41:37.723696 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9642 04:41:37.730475 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9643 04:41:37.733750 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9644 04:41:37.737285 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9645 04:41:37.743857 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9646 04:41:37.747137 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9647 04:41:37.753776 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9648 04:41:37.757129 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9649 04:41:37.760412 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9650 04:41:37.766909 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9651 04:41:37.770183 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9652 04:41:37.774053 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9653 04:41:37.780411 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9654 04:41:37.783681 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9655 04:41:37.790355 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9656 04:41:37.793699 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9657 04:41:37.796976 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9658 04:41:37.803867 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9659 04:41:37.807025 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9660 04:41:37.810338 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9661 04:41:37.817165 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9662 04:41:37.820575 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9663 04:41:37.827314 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9664 04:41:37.830144 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9665 04:41:37.833795 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9666 04:41:37.840357 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9667 04:41:37.844112 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9668 04:41:37.850348 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9669 04:41:37.854078 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9670 04:41:37.857028 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9671 04:41:37.864008 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9672 04:41:37.867176 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9673 04:41:37.870501 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9674 04:41:37.877028 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9675 04:41:37.880345 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9676 04:41:37.886897 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9677 04:41:37.890620 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9678 04:41:37.893788 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9679 04:41:37.900260 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9680 04:41:37.903699 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9681 04:41:37.910521 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9682 04:41:37.913775 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9683 04:41:37.917037 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9684 04:41:37.923481 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9685 04:41:37.927009 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9686 04:41:37.933466 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9687 04:41:37.937122 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9688 04:41:37.940319 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9689 04:41:37.946988 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9690 04:41:37.950071 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9691 04:41:37.957071 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9692 04:41:37.960234 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9693 04:41:37.963461 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9694 04:41:37.970258 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9695 04:41:37.973624 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9696 04:41:37.976732 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9697 04:41:37.983435 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9698 04:41:37.986549 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9699 04:41:37.993174 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9700 04:41:37.996703 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9701 04:41:38.000025 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9702 04:41:38.006439 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9703 04:41:38.009880 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9704 04:41:38.016444 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9705 04:41:38.019771 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9706 04:41:38.026481 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9707 04:41:38.029684 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9708 04:41:38.032935 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9709 04:41:38.039778 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9710 04:41:38.042897 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9711 04:41:38.049747 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9712 04:41:38.053109 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9713 04:41:38.056352 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9714 04:41:38.062981 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9715 04:41:38.066309 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9716 04:41:38.072837 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9717 04:41:38.076217 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9718 04:41:38.082815 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9719 04:41:38.086230 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9720 04:41:38.089426 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9721 04:41:38.095973 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9722 04:41:38.099543 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9723 04:41:38.106080 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9724 04:41:38.109247 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9725 04:41:38.112652 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9726 04:41:38.119714 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9727 04:41:38.122806 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9728 04:41:38.129272 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9729 04:41:38.132793 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9730 04:41:38.136063 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9731 04:41:38.142609 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9732 04:41:38.146140 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9733 04:41:38.152518 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9734 04:41:38.156138 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9735 04:41:38.162906 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9736 04:41:38.166053 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9737 04:41:38.169213 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9738 04:41:38.176110 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9739 04:41:38.179264 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9740 04:41:38.185870 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9741 04:41:38.189174 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9742 04:41:38.192454 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9743 04:41:38.199162 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9744 04:41:38.202535 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9745 04:41:38.205625 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9746 04:41:38.208998 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9747 04:41:38.215482 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9748 04:41:38.218723 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9749 04:41:38.222068 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9750 04:41:38.228711 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9751 04:41:38.231985 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9752 04:41:38.235336 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9753 04:41:38.242016 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9754 04:41:38.245370 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9755 04:41:38.251950 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9756 04:41:38.255128 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9757 04:41:38.258701 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9758 04:41:38.265211 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9759 04:41:38.268444 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9760 04:41:38.275313 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9761 04:41:38.278576 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9762 04:41:38.281820 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9763 04:41:38.288355 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9764 04:41:38.291715 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9765 04:41:38.294866 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9766 04:41:38.301736 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9767 04:41:38.305072 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9768 04:41:38.308199 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9769 04:41:38.314951 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9770 04:41:38.317956 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9771 04:41:38.324429 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9772 04:41:38.327609 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9773 04:41:38.331006 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9774 04:41:38.337877 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9775 04:41:38.341075 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9776 04:41:38.347799 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9777 04:41:38.351000 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9778 04:41:38.354037 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9779 04:41:38.360869 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9780 04:41:38.364037 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9781 04:41:38.367650 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9782 04:41:38.374269 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9783 04:41:38.377404 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9784 04:41:38.380768 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9785 04:41:38.384054 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9786 04:41:38.391094 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9787 04:41:38.394044 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9788 04:41:38.397439 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9789 04:41:38.400784 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9790 04:41:38.407528 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9791 04:41:38.410775 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9792 04:41:38.413875 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9793 04:41:38.417348 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9794 04:41:38.423815 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9795 04:41:38.427002 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9796 04:41:38.430620 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9797 04:41:38.436949 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9798 04:41:38.440371 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9799 04:41:38.447056 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9800 04:41:38.450443 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9801 04:41:38.453812 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9802 04:41:38.460146 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9803 04:41:38.463442 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9804 04:41:38.470055 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9805 04:41:38.473334 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9806 04:41:38.476711 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9807 04:41:38.483462 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9808 04:41:38.486671 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9809 04:41:38.493171 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9810 04:41:38.496796 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9811 04:41:38.500067 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9812 04:41:38.506485 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9813 04:41:38.509710 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9814 04:41:38.516408 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9815 04:41:38.519681 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9816 04:41:38.526639 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9817 04:41:38.530054 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9818 04:41:38.536399 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9819 04:41:38.539964 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9820 04:41:38.543252 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9821 04:41:38.549937 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9822 04:41:38.553137 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9823 04:41:38.556534 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9824 04:41:38.563239 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9825 04:41:38.566582 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9826 04:41:38.572976 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9827 04:41:38.576273 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9828 04:41:38.579565 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9829 04:41:38.586325 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9830 04:41:38.589453 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9831 04:41:38.596204 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9832 04:41:38.599668 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9833 04:41:38.606185 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9834 04:41:38.609625 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9835 04:41:38.612871 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9836 04:41:38.619266 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9837 04:41:38.622526 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9838 04:41:38.629211 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9839 04:41:38.632542 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9840 04:41:38.636033 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9841 04:41:38.642551 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9842 04:41:38.646047 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9843 04:41:38.652488 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9844 04:41:38.655796 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9845 04:41:38.659013 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9846 04:41:38.665491 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9847 04:41:38.669292 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9848 04:41:38.675817 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9849 04:41:38.679086 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9850 04:41:38.685627 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9851 04:41:38.688992 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9852 04:41:38.692046 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9853 04:41:38.699060 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9854 04:41:38.702387 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9855 04:41:38.709004 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9856 04:41:38.712258 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9857 04:41:38.715661 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9858 04:41:38.722241 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9859 04:41:38.725452 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9860 04:41:38.732074 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9861 04:41:38.735331 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9862 04:41:38.738570 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9863 04:41:38.745042 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9864 04:41:38.748664 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9865 04:41:38.755159 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9866 04:41:38.758209 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9867 04:41:38.761825 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9868 04:41:38.768370 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9869 04:41:38.771856 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9870 04:41:38.778160 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9871 04:41:38.781408 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9872 04:41:38.788463 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9873 04:41:38.791609 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9874 04:41:38.798093 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9875 04:41:38.801394 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9876 04:41:38.804836 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9877 04:41:38.811500 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9878 04:41:38.814626 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9879 04:41:38.821528 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9880 04:41:38.824591 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9881 04:41:38.831152 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9882 04:41:38.834607 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9883 04:41:38.841246 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9884 04:41:38.844461 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9885 04:41:38.847685 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9886 04:41:38.854233 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9887 04:41:38.857420 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9888 04:41:38.864589 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9889 04:41:38.867770 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9890 04:41:38.874239 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9891 04:41:38.877633 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9892 04:41:38.881079 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9893 04:41:38.887507 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9894 04:41:38.890900 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9895 04:41:38.897388 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9896 04:41:38.900936 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9897 04:41:38.907472 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9898 04:41:38.910742 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9899 04:41:38.917448 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9900 04:41:38.920841 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9901 04:41:38.924337 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9902 04:41:38.930628 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9903 04:41:38.933785 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9904 04:41:38.940487 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9905 04:41:38.943786 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9906 04:41:38.950419 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9907 04:41:38.954027 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9908 04:41:38.957029 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9909 04:41:38.963810 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9910 04:41:38.967207 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9911 04:41:38.973765 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9912 04:41:38.976996 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9913 04:41:38.983658 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9914 04:41:38.986814 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9915 04:41:38.990158 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9916 04:41:38.997022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9917 04:41:39.000136 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9918 04:41:39.006806 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9919 04:41:39.010050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9920 04:41:39.016727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9921 04:41:39.019891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9922 04:41:39.026455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9923 04:41:39.029784 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9924 04:41:39.036265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9925 04:41:39.039955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9926 04:41:39.046282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9927 04:41:39.049724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9928 04:41:39.056335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9929 04:41:39.059593 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9930 04:41:39.066368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9931 04:41:39.069469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9932 04:41:39.076175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9933 04:41:39.079555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9934 04:41:39.085978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9935 04:41:39.089687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9936 04:41:39.096334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9937 04:41:39.099497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9938 04:41:39.105975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9939 04:41:39.109345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9940 04:41:39.115953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9941 04:41:39.119208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9942 04:41:39.126066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9943 04:41:39.129249 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9944 04:41:39.135802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9945 04:41:39.139123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9946 04:41:39.145830 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9947 04:41:39.149038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9948 04:41:39.152631 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9949 04:41:39.155874 INFO: [APUAPC] vio 0
9950 04:41:39.162436 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9951 04:41:39.165512 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9952 04:41:39.168811 INFO: [APUAPC] D0_APC_0: 0x400510
9953 04:41:39.172390 INFO: [APUAPC] D0_APC_1: 0x0
9954 04:41:39.175611 INFO: [APUAPC] D0_APC_2: 0x1540
9955 04:41:39.178926 INFO: [APUAPC] D0_APC_3: 0x0
9956 04:41:39.182154 INFO: [APUAPC] D1_APC_0: 0xffffffff
9957 04:41:39.185466 INFO: [APUAPC] D1_APC_1: 0xffffffff
9958 04:41:39.188717 INFO: [APUAPC] D1_APC_2: 0x3fffff
9959 04:41:39.188800 INFO: [APUAPC] D1_APC_3: 0x0
9960 04:41:39.192295 INFO: [APUAPC] D2_APC_0: 0xffffffff
9961 04:41:39.198749 INFO: [APUAPC] D2_APC_1: 0xffffffff
9962 04:41:39.202211 INFO: [APUAPC] D2_APC_2: 0x3fffff
9963 04:41:39.202294 INFO: [APUAPC] D2_APC_3: 0x0
9964 04:41:39.205472 INFO: [APUAPC] D3_APC_0: 0xffffffff
9965 04:41:39.208714 INFO: [APUAPC] D3_APC_1: 0xffffffff
9966 04:41:39.212176 INFO: [APUAPC] D3_APC_2: 0x3fffff
9967 04:41:39.215308 INFO: [APUAPC] D3_APC_3: 0x0
9968 04:41:39.218758 INFO: [APUAPC] D4_APC_0: 0xffffffff
9969 04:41:39.222035 INFO: [APUAPC] D4_APC_1: 0xffffffff
9970 04:41:39.225210 INFO: [APUAPC] D4_APC_2: 0x3fffff
9971 04:41:39.228692 INFO: [APUAPC] D4_APC_3: 0x0
9972 04:41:39.232186 INFO: [APUAPC] D5_APC_0: 0xffffffff
9973 04:41:39.235242 INFO: [APUAPC] D5_APC_1: 0xffffffff
9974 04:41:39.238437 INFO: [APUAPC] D5_APC_2: 0x3fffff
9975 04:41:39.241810 INFO: [APUAPC] D5_APC_3: 0x0
9976 04:41:39.245129 INFO: [APUAPC] D6_APC_0: 0xffffffff
9977 04:41:39.248423 INFO: [APUAPC] D6_APC_1: 0xffffffff
9978 04:41:39.251646 INFO: [APUAPC] D6_APC_2: 0x3fffff
9979 04:41:39.254983 INFO: [APUAPC] D6_APC_3: 0x0
9980 04:41:39.258502 INFO: [APUAPC] D7_APC_0: 0xffffffff
9981 04:41:39.261806 INFO: [APUAPC] D7_APC_1: 0xffffffff
9982 04:41:39.265003 INFO: [APUAPC] D7_APC_2: 0x3fffff
9983 04:41:39.268184 INFO: [APUAPC] D7_APC_3: 0x0
9984 04:41:39.271561 INFO: [APUAPC] D8_APC_0: 0xffffffff
9985 04:41:39.274868 INFO: [APUAPC] D8_APC_1: 0xffffffff
9986 04:41:39.278124 INFO: [APUAPC] D8_APC_2: 0x3fffff
9987 04:41:39.281338 INFO: [APUAPC] D8_APC_3: 0x0
9988 04:41:39.285101 INFO: [APUAPC] D9_APC_0: 0xffffffff
9989 04:41:39.288372 INFO: [APUAPC] D9_APC_1: 0xffffffff
9990 04:41:39.291609 INFO: [APUAPC] D9_APC_2: 0x3fffff
9991 04:41:39.294703 INFO: [APUAPC] D9_APC_3: 0x0
9992 04:41:39.298234 INFO: [APUAPC] D10_APC_0: 0xffffffff
9993 04:41:39.301340 INFO: [APUAPC] D10_APC_1: 0xffffffff
9994 04:41:39.304813 INFO: [APUAPC] D10_APC_2: 0x3fffff
9995 04:41:39.307919 INFO: [APUAPC] D10_APC_3: 0x0
9996 04:41:39.311382 INFO: [APUAPC] D11_APC_0: 0xffffffff
9997 04:41:39.314539 INFO: [APUAPC] D11_APC_1: 0xffffffff
9998 04:41:39.317989 INFO: [APUAPC] D11_APC_2: 0x3fffff
9999 04:41:39.321108 INFO: [APUAPC] D11_APC_3: 0x0
10000 04:41:39.324489 INFO: [APUAPC] D12_APC_0: 0xffffffff
10001 04:41:39.328075 INFO: [APUAPC] D12_APC_1: 0xffffffff
10002 04:41:39.331479 INFO: [APUAPC] D12_APC_2: 0x3fffff
10003 04:41:39.334926 INFO: [APUAPC] D12_APC_3: 0x0
10004 04:41:39.337974 INFO: [APUAPC] D13_APC_0: 0xffffffff
10005 04:41:39.341335 INFO: [APUAPC] D13_APC_1: 0xffffffff
10006 04:41:39.344869 INFO: [APUAPC] D13_APC_2: 0x3fffff
10007 04:41:39.348306 INFO: [APUAPC] D13_APC_3: 0x0
10008 04:41:39.351388 INFO: [APUAPC] D14_APC_0: 0xffffffff
10009 04:41:39.354580 INFO: [APUAPC] D14_APC_1: 0xffffffff
10010 04:41:39.357968 INFO: [APUAPC] D14_APC_2: 0x3fffff
10011 04:41:39.361278 INFO: [APUAPC] D14_APC_3: 0x0
10012 04:41:39.364488 INFO: [APUAPC] D15_APC_0: 0xffffffff
10013 04:41:39.367914 INFO: [APUAPC] D15_APC_1: 0xffffffff
10014 04:41:39.371075 INFO: [APUAPC] D15_APC_2: 0x3fffff
10015 04:41:39.374303 INFO: [APUAPC] D15_APC_3: 0x0
10016 04:41:39.378015 INFO: [APUAPC] APC_CON: 0x4
10017 04:41:39.380949 INFO: [NOCDAPC] D0_APC_0: 0x0
10018 04:41:39.384419 INFO: [NOCDAPC] D0_APC_1: 0x0
10019 04:41:39.387585 INFO: [NOCDAPC] D1_APC_0: 0x0
10020 04:41:39.387668 INFO: [NOCDAPC] D1_APC_1: 0xfff
10021 04:41:39.390962 INFO: [NOCDAPC] D2_APC_0: 0x0
10022 04:41:39.394203 INFO: [NOCDAPC] D2_APC_1: 0xfff
10023 04:41:39.397471 INFO: [NOCDAPC] D3_APC_0: 0x0
10024 04:41:39.401179 INFO: [NOCDAPC] D3_APC_1: 0xfff
10025 04:41:39.404558 INFO: [NOCDAPC] D4_APC_0: 0x0
10026 04:41:39.407705 INFO: [NOCDAPC] D4_APC_1: 0xfff
10027 04:41:39.410828 INFO: [NOCDAPC] D5_APC_0: 0x0
10028 04:41:39.414225 INFO: [NOCDAPC] D5_APC_1: 0xfff
10029 04:41:39.417719 INFO: [NOCDAPC] D6_APC_0: 0x0
10030 04:41:39.420791 INFO: [NOCDAPC] D6_APC_1: 0xfff
10031 04:41:39.420903 INFO: [NOCDAPC] D7_APC_0: 0x0
10032 04:41:39.423990 INFO: [NOCDAPC] D7_APC_1: 0xfff
10033 04:41:39.427340 INFO: [NOCDAPC] D8_APC_0: 0x0
10034 04:41:39.430711 INFO: [NOCDAPC] D8_APC_1: 0xfff
10035 04:41:39.434204 INFO: [NOCDAPC] D9_APC_0: 0x0
10036 04:41:39.437330 INFO: [NOCDAPC] D9_APC_1: 0xfff
10037 04:41:39.440688 INFO: [NOCDAPC] D10_APC_0: 0x0
10038 04:41:39.444145 INFO: [NOCDAPC] D10_APC_1: 0xfff
10039 04:41:39.447176 INFO: [NOCDAPC] D11_APC_0: 0x0
10040 04:41:39.450710 INFO: [NOCDAPC] D11_APC_1: 0xfff
10041 04:41:39.454106 INFO: [NOCDAPC] D12_APC_0: 0x0
10042 04:41:39.457331 INFO: [NOCDAPC] D12_APC_1: 0xfff
10043 04:41:39.460327 INFO: [NOCDAPC] D13_APC_0: 0x0
10044 04:41:39.463684 INFO: [NOCDAPC] D13_APC_1: 0xfff
10045 04:41:39.463768 INFO: [NOCDAPC] D14_APC_0: 0x0
10046 04:41:39.467036 INFO: [NOCDAPC] D14_APC_1: 0xfff
10047 04:41:39.470688 INFO: [NOCDAPC] D15_APC_0: 0x0
10048 04:41:39.473686 INFO: [NOCDAPC] D15_APC_1: 0xfff
10049 04:41:39.476962 INFO: [NOCDAPC] APC_CON: 0x4
10050 04:41:39.480281 INFO: [APUAPC] set_apusys_apc done
10051 04:41:39.483964 INFO: [DEVAPC] devapc_init done
10052 04:41:39.487219 INFO: GICv3 without legacy support detected.
10053 04:41:39.493586 INFO: ARM GICv3 driver initialized in EL3
10054 04:41:39.496978 INFO: Maximum SPI INTID supported: 639
10055 04:41:39.500346 INFO: BL31: Initializing runtime services
10056 04:41:39.507012 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10057 04:41:39.507095 INFO: SPM: enable CPC mode
10058 04:41:39.513455 INFO: mcdi ready for mcusys-off-idle and system suspend
10059 04:41:39.516836 INFO: BL31: Preparing for EL3 exit to normal world
10060 04:41:39.523460 INFO: Entry point address = 0x80000000
10061 04:41:39.523543 INFO: SPSR = 0x8
10062 04:41:39.529659
10063 04:41:39.529770
10064 04:41:39.529835
10065 04:41:39.533075 Starting depthcharge on Spherion...
10066 04:41:39.533187
10067 04:41:39.533252 Wipe memory regions:
10068 04:41:39.533312
10069 04:41:39.533984 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10070 04:41:39.534086 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10071 04:41:39.534202 Setting prompt string to ['asurada:']
10072 04:41:39.534317 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10073 04:41:39.536268 [0x00000040000000, 0x00000054600000)
10074 04:41:39.658501
10075 04:41:39.658636 [0x00000054660000, 0x00000080000000)
10076 04:41:39.918775
10077 04:41:39.918930 [0x000000821a7280, 0x000000ffe64000)
10078 04:41:40.663178
10079 04:41:40.663323 [0x00000100000000, 0x00000240000000)
10080 04:41:42.551938
10081 04:41:42.555310 Initializing XHCI USB controller at 0x11200000.
10082 04:41:43.593373
10083 04:41:43.596427 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10084 04:41:43.596544
10085 04:41:43.596639
10086 04:41:43.596730
10087 04:41:43.597044 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10089 04:41:43.697394 asurada: tftpboot 192.168.201.1 12699810/tftp-deploy-swjqm2qw/kernel/image.itb 12699810/tftp-deploy-swjqm2qw/kernel/cmdline
10090 04:41:43.697589 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10091 04:41:43.697678 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10092 04:41:43.701895 tftpboot 192.168.201.1 12699810/tftp-deploy-swjqm2qw/kernel/image.itbtp-deploy-swjqm2qw/kernel/cmdline
10093 04:41:43.701981
10094 04:41:43.702047 Waiting for link
10095 04:41:43.862267
10096 04:41:43.862405 R8152: Initializing
10097 04:41:43.862478
10098 04:41:43.865577 Version 6 (ocp_data = 5c30)
10099 04:41:43.865662
10100 04:41:43.869005 R8152: Done initializing
10101 04:41:43.869090
10102 04:41:43.869157 Adding net device
10103 04:41:45.845873
10104 04:41:45.846022 done.
10105 04:41:45.846098
10106 04:41:45.846160 MAC: 00:24:32:30:78:ff
10107 04:41:45.846218
10108 04:41:45.848972 Sending DHCP discover... done.
10109 04:41:45.849058
10110 04:41:45.852455 Waiting for reply... done.
10111 04:41:45.852541
10112 04:41:45.855657 Sending DHCP request... done.
10113 04:41:45.855770
10114 04:41:45.855851 Waiting for reply... done.
10115 04:41:45.855913
10116 04:41:45.859076 My ip is 192.168.201.21
10117 04:41:45.859158
10118 04:41:45.862168 The DHCP server ip is 192.168.201.1
10119 04:41:45.862247
10120 04:41:45.865644 TFTP server IP predefined by user: 192.168.201.1
10121 04:41:45.865716
10122 04:41:45.872234 Bootfile predefined by user: 12699810/tftp-deploy-swjqm2qw/kernel/image.itb
10123 04:41:45.872316
10124 04:41:45.875527 Sending tftp read request... done.
10125 04:41:45.875602
10126 04:41:45.879111 Waiting for the transfer...
10127 04:41:45.879194
10128 04:41:46.398079 00000000 ################################################################
10129 04:41:46.398246
10130 04:41:46.917136 00080000 ################################################################
10131 04:41:46.917310
10132 04:41:47.442358 00100000 ################################################################
10133 04:41:47.442504
10134 04:41:47.957859 00180000 ################################################################
10135 04:41:47.957997
10136 04:41:48.474009 00200000 ################################################################
10137 04:41:48.474181
10138 04:41:49.003062 00280000 ################################################################
10139 04:41:49.003203
10140 04:41:49.530102 00300000 ################################################################
10141 04:41:49.530252
10142 04:41:50.052623 00380000 ################################################################
10143 04:41:50.052769
10144 04:41:50.579934 00400000 ################################################################
10145 04:41:50.580121
10146 04:41:51.102985 00480000 ################################################################
10147 04:41:51.103127
10148 04:41:51.619889 00500000 ################################################################
10149 04:41:51.620026
10150 04:41:52.144648 00580000 ################################################################
10151 04:41:52.144788
10152 04:41:52.666370 00600000 ################################################################
10153 04:41:52.666507
10154 04:41:53.190388 00680000 ################################################################
10155 04:41:53.190563
10156 04:41:53.833781 00700000 ################################################################
10157 04:41:53.834401
10158 04:41:54.545090 00780000 ################################################################
10159 04:41:54.545737
10160 04:41:55.244399 00800000 ################################################################
10161 04:41:55.244913
10162 04:41:55.809070 00880000 ################################################################
10163 04:41:55.809209
10164 04:41:56.377372 00900000 ################################################################
10165 04:41:56.377562
10166 04:41:57.048453 00980000 ################################################################
10167 04:41:57.048590
10168 04:41:57.575988 00a00000 ################################################################
10169 04:41:57.576121
10170 04:41:58.210792 00a80000 ################################################################
10171 04:41:58.211302
10172 04:41:58.872468 00b00000 ################################################################
10173 04:41:58.872839
10174 04:41:59.578771 00b80000 ################################################################
10175 04:41:59.579337
10176 04:42:00.317546 00c00000 ################################################################
10177 04:42:00.318085
10178 04:42:01.069812 00c80000 ################################################################
10179 04:42:01.070353
10180 04:42:01.820841 00d00000 ################################################################
10181 04:42:01.821533
10182 04:42:02.572245 00d80000 ################################################################
10183 04:42:02.572770
10184 04:42:03.265426 00e00000 ################################################################
10185 04:42:03.266016
10186 04:42:04.002753 00e80000 ################################################################
10187 04:42:04.003283
10188 04:42:04.714530 00f00000 ################################################################
10189 04:42:04.715063
10190 04:42:05.473190 00f80000 ################################################################
10191 04:42:05.473745
10192 04:42:06.212000 01000000 ################################################################
10193 04:42:06.212537
10194 04:42:06.933616 01080000 ################################################################
10195 04:42:06.934113
10196 04:42:07.565099 01100000 ################################################################
10197 04:42:07.565705
10198 04:42:08.261629 01180000 ################################################################
10199 04:42:08.262166
10200 04:42:08.980019 01200000 ################################################################
10201 04:42:08.980530
10202 04:42:09.711192 01280000 ################################################################
10203 04:42:09.711557
10204 04:42:10.352497 01300000 ################################################################
10205 04:42:10.352691
10206 04:42:10.946201 01380000 ################################################################
10207 04:42:10.946381
10208 04:42:11.479691 01400000 ################################################################
10209 04:42:11.479838
10210 04:42:12.128340 01480000 ################################################################
10211 04:42:12.128850
10212 04:42:12.761739 01500000 ################################################################
10213 04:42:12.761981
10214 04:42:13.347616 01580000 ################################################################
10215 04:42:13.347763
10216 04:42:13.923658 01600000 ################################################################
10217 04:42:13.923812
10218 04:42:14.451486 01680000 ################################################################
10219 04:42:14.451662
10220 04:42:14.987962 01700000 ################################################################
10221 04:42:14.988127
10222 04:42:15.580232 01780000 ################################################################
10223 04:42:15.580373
10224 04:42:16.138363 01800000 ################################################################
10225 04:42:16.138499
10226 04:42:16.681354 01880000 ################################################################
10227 04:42:16.681520
10228 04:42:17.205153 01900000 ################################################################
10229 04:42:17.205299
10230 04:42:17.752011 01980000 ################################################################
10231 04:42:17.752155
10232 04:42:18.386215 01a00000 ################################################################
10233 04:42:18.386349
10234 04:42:19.053036 01a80000 ################################################################
10235 04:42:19.053588
10236 04:42:19.738860 01b00000 ################################################################
10237 04:42:19.739368
10238 04:42:20.443676 01b80000 ################################################################
10239 04:42:20.444397
10240 04:42:21.100422 01c00000 ################################################################
10241 04:42:21.100629
10242 04:42:21.121415 01c80000 ### done.
10243 04:42:21.121760
10244 04:42:21.124623 The bootfile was 29901390 bytes long.
10245 04:42:21.124932
10246 04:42:21.127792 Sending tftp read request... done.
10247 04:42:21.128181
10248 04:42:21.131140 Waiting for the transfer...
10249 04:42:21.131570
10250 04:42:21.132008 00000000 # done.
10251 04:42:21.132377
10252 04:42:21.141025 Command line loaded dynamically from TFTP file: 12699810/tftp-deploy-swjqm2qw/kernel/cmdline
10253 04:42:21.141448
10254 04:42:21.160944 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12699810/extract-nfsrootfs-ogidnyo1,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10255 04:42:21.161378
10256 04:42:21.164273 Loading FIT.
10257 04:42:21.164708
10258 04:42:21.167902 Image ramdisk-1 has 17803571 bytes.
10259 04:42:21.168321
10260 04:42:21.168678 Image fdt-1 has 47278 bytes.
10261 04:42:21.168984
10262 04:42:21.171015 Image kernel-1 has 12048508 bytes.
10263 04:42:21.171425
10264 04:42:21.180937 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10265 04:42:21.181382
10266 04:42:21.197344 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10267 04:42:21.197894
10268 04:42:21.204058 Choosing best match conf-1 for compat google,spherion-rev2.
10269 04:42:21.207732
10270 04:42:21.212553 Connected to device vid:did:rid of 1ae0:0028:00
10271 04:42:21.220396
10272 04:42:21.223915 tpm_get_response: command 0x17b, return code 0x0
10273 04:42:21.224396
10274 04:42:21.226968 ec_init: CrosEC protocol v3 supported (256, 248)
10275 04:42:21.231538
10276 04:42:21.234761 tpm_cleanup: add release locality here.
10277 04:42:21.235179
10278 04:42:21.235688 Shutting down all USB controllers.
10279 04:42:21.238120
10280 04:42:21.238740 Removing current net device
10281 04:42:21.239086
10282 04:42:21.244677 Exiting depthcharge with code 4 at timestamp: 70997292
10283 04:42:21.245094
10284 04:42:21.248082 LZMA decompressing kernel-1 to 0x821a6718
10285 04:42:21.248499
10286 04:42:21.251341 LZMA decompressing kernel-1 to 0x40000000
10287 04:42:22.749659
10288 04:42:22.750069 jumping to kernel
10289 04:42:22.751304 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10290 04:42:22.751680 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10291 04:42:22.751965 Setting prompt string to ['Linux version [0-9]']
10292 04:42:22.752235 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10293 04:42:22.752497 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10294 04:42:22.831478
10295 04:42:22.834594 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10296 04:42:22.838049 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10297 04:42:22.838142 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10298 04:42:22.838213 Setting prompt string to []
10299 04:42:22.838289 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10300 04:42:22.838360 Using line separator: #'\n'#
10301 04:42:22.838417 No login prompt set.
10302 04:42:22.838478 Parsing kernel messages
10303 04:42:22.838531 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10304 04:42:22.838633 [login-action] Waiting for messages, (timeout 00:03:42)
10305 04:42:22.857666 [ 0.000000] Linux version 6.1.75-cip14-rt8 (KernelCI@build-j97480-arm64-gcc-10-defconfig-arm64-chromebook-6n26j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024
10306 04:42:22.860976 [ 0.000000] random: crng init done
10307 04:42:22.867851 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10308 04:42:22.870911 [ 0.000000] efi: UEFI not found.
10309 04:42:22.877740 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10310 04:42:22.887476 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10311 04:42:22.897253 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10312 04:42:22.903776 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10313 04:42:22.910491 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10314 04:42:22.917350 [ 0.000000] printk: bootconsole [mtk8250] enabled
10315 04:42:22.923792 [ 0.000000] NUMA: No NUMA configuration found
10316 04:42:22.930507 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10317 04:42:22.937121 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10318 04:42:22.937244 [ 0.000000] Zone ranges:
10319 04:42:22.943580 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10320 04:42:22.947030 [ 0.000000] DMA32 empty
10321 04:42:22.953877 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10322 04:42:22.957044 [ 0.000000] Movable zone start for each node
10323 04:42:22.960513 [ 0.000000] Early memory node ranges
10324 04:42:22.967068 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10325 04:42:22.973634 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10326 04:42:22.980640 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10327 04:42:22.987190 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10328 04:42:22.993918 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10329 04:42:22.999909 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10330 04:42:23.056650 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10331 04:42:23.062914 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10332 04:42:23.069266 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10333 04:42:23.072960 [ 0.000000] psci: probing for conduit method from DT.
10334 04:42:23.079231 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10335 04:42:23.082535 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10336 04:42:23.089127 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10337 04:42:23.092446 [ 0.000000] psci: SMC Calling Convention v1.2
10338 04:42:23.098899 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10339 04:42:23.102360 [ 0.000000] Detected VIPT I-cache on CPU0
10340 04:42:23.108883 [ 0.000000] CPU features: detected: GIC system register CPU interface
10341 04:42:23.115382 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10342 04:42:23.122120 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10343 04:42:23.128623 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10344 04:42:23.135179 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10345 04:42:23.145337 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10346 04:42:23.148248 [ 0.000000] alternatives: applying boot alternatives
10347 04:42:23.155035 [ 0.000000] Fallback order for Node 0: 0
10348 04:42:23.161505 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10349 04:42:23.164936 [ 0.000000] Policy zone: Normal
10350 04:42:23.187883 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12699810/extract-nfsrootfs-ogidnyo1,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10351 04:42:23.197917 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10352 04:42:23.208823 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10353 04:42:23.218568 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10354 04:42:23.225020 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10355 04:42:23.228370 <6>[ 0.000000] software IO TLB: area num 8.
10356 04:42:23.285187 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10357 04:42:23.434317 <6>[ 0.000000] Memory: 7949808K/8385536K available (18048K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 616K bss, 402960K reserved, 32768K cma-reserved)
10358 04:42:23.440889 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10359 04:42:23.447669 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10360 04:42:23.451160 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10361 04:42:23.457431 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10362 04:42:23.464177 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10363 04:42:23.467490 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10364 04:42:23.477318 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10365 04:42:23.483978 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10366 04:42:23.490610 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10367 04:42:23.497389 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10368 04:42:23.500459 <6>[ 0.000000] GICv3: 608 SPIs implemented
10369 04:42:23.504039 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10370 04:42:23.510706 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10371 04:42:23.514248 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10372 04:42:23.520719 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10373 04:42:23.533854 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10374 04:42:23.543980 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10375 04:42:23.553798 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10376 04:42:23.561285 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10377 04:42:23.574309 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10378 04:42:23.580825 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10379 04:42:23.587513 <6>[ 0.009231] Console: colour dummy device 80x25
10380 04:42:23.597541 <6>[ 0.013982] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10381 04:42:23.604404 <6>[ 0.024423] pid_max: default: 32768 minimum: 301
10382 04:42:23.607499 <6>[ 0.029294] LSM: Security Framework initializing
10383 04:42:23.614103 <6>[ 0.034232] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10384 04:42:23.624342 <6>[ 0.042095] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10385 04:42:23.634073 <6>[ 0.051504] cblist_init_generic: Setting adjustable number of callback queues.
10386 04:42:23.637227 <6>[ 0.058994] cblist_init_generic: Setting shift to 3 and lim to 1.
10387 04:42:23.647104 <6>[ 0.065372] cblist_init_generic: Setting adjustable number of callback queues.
10388 04:42:23.653934 <6>[ 0.072798] cblist_init_generic: Setting shift to 3 and lim to 1.
10389 04:42:23.657274 <6>[ 0.079236] rcu: Hierarchical SRCU implementation.
10390 04:42:23.663682 <6>[ 0.079238] rcu: Max phase no-delay instances is 1000.
10391 04:42:23.670281 <6>[ 0.079262] printk: bootconsole [mtk8250] printing thread started
10392 04:42:23.676765 <6>[ 0.097559] EFI services will not be available.
10393 04:42:23.680216 <6>[ 0.097756] smp: Bringing up secondary CPUs ...
10394 04:42:23.683169 <6>[ 0.098059] Detected VIPT I-cache on CPU1
10395 04:42:23.693211 <6>[ 0.098126] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10396 04:42:23.699579 <6>[ 0.098156] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10397 04:42:23.709068 <6>[ 0.126041] Detected VIPT I-cache on CPU2
10398 04:42:23.715567 <6>[ 0.126088] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10399 04:42:23.725309 <6>[ 0.126104] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10400 04:42:23.728809 <6>[ 0.126356] Detected VIPT I-cache on CPU3
10401 04:42:23.735398 <6>[ 0.126400] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10402 04:42:23.741943 <6>[ 0.126414] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10403 04:42:23.745405 <6>[ 0.126720] CPU features: detected: Spectre-v4
10404 04:42:23.751835 <6>[ 0.126727] CPU features: detected: Spectre-BHB
10405 04:42:23.755014 <6>[ 0.126732] Detected PIPT I-cache on CPU4
10406 04:42:23.761873 <6>[ 0.126793] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10407 04:42:23.768067 <6>[ 0.126809] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10408 04:42:23.774936 <6>[ 0.127096] Detected PIPT I-cache on CPU5
10409 04:42:23.781649 <6>[ 0.127157] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10410 04:42:23.788368 <6>[ 0.127173] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10411 04:42:23.791523 <6>[ 0.127444] Detected PIPT I-cache on CPU6
10412 04:42:23.801484 <6>[ 0.127508] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10413 04:42:23.807990 <6>[ 0.127524] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10414 04:42:23.811178 <6>[ 0.127812] Detected PIPT I-cache on CPU7
10415 04:42:23.817914 <6>[ 0.127875] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10416 04:42:23.824284 <6>[ 0.127891] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10417 04:42:23.827992 <6>[ 0.127937] smp: Brought up 1 node, 8 CPUs
10418 04:42:23.834221 <6>[ 0.127942] SMP: Total of 8 processors activated.
10419 04:42:23.840855 <6>[ 0.127945] CPU features: detected: 32-bit EL0 Support
10420 04:42:23.847333 <6>[ 0.127947] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10421 04:42:23.853926 <6>[ 0.127949] CPU features: detected: Common not Private translations
10422 04:42:23.860503 <6>[ 0.127951] CPU features: detected: CRC32 instructions
10423 04:42:23.867266 <6>[ 0.127954] CPU features: detected: RCpc load-acquire (LDAPR)
10424 04:42:23.870779 <6>[ 0.127955] CPU features: detected: LSE atomic instructions
10425 04:42:23.877155 <6>[ 0.127957] CPU features: detected: Privileged Access Never
10426 04:42:23.883562 <6>[ 0.127958] CPU features: detected: RAS Extension Support
10427 04:42:23.890342 <6>[ 0.127961] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10428 04:42:23.893677 <6>[ 0.128028] CPU: All CPU(s) started at EL2
10429 04:42:23.900423 <6>[ 0.128030] alternatives: applying system-wide alternatives
10430 04:42:23.903560 <6>[ 0.141134] devtmpfs: initialized
10431 04:42:23.913336 <6>[ 0.147409] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10432 04:42:23.942297 ���rQ��U���ѕɕ���}%9Q��ɽѽ����2�����5R�<6>[ < 0.365132] printk: console [ttyS0] printing thread started
10433 04:42:23.948870 6<6>[ 0.365177] printk: console [ttyS0] enabled
10434 04:42:23.955590 >[ 0.228813] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10435 04:42:23.963471 <6>[ 0.365182] printk: bootconsole [mtk8250] disabled
10436 04:42:23.969889 <6>[ 0.383255] printk: bootconsole [mtk8250] printing thread stopped
10437 04:42:23.973381 <6>[ 0.384664] SuperH (H)SCI(F) driver initialized
10438 04:42:23.979985 <6>[ 0.385165] msm_serial: driver initialized
10439 04:42:23.986631 <6>[ 0.389878] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10440 04:42:23.996593 <6>[ 0.389909] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10441 04:42:24.008822 <6>[ 0.389938] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10442 04:42:24.019332 <6>[ 0.389968] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10443 04:42:24.027677 <6>[ 0.389989] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10444 04:42:24.043661 <6>[ 0.390017] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10445 04:42:24.044033 <6>[ 0.390045] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10446 04:42:24.050041 <6>[ 0.390157] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10447 04:42:24.057755 <6>[ 0.390187] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10448 04:42:24.061652 <6>[ 0.400829] loop: module loaded
10449 04:42:24.066243 <6>[ 0.403497] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10450 04:42:24.072763 <4>[ 0.420447] mtk-pmic-keys: Failed to locate of_node [id: -1]
10451 04:42:24.076357 <6>[ 0.421473] megasas: 07.719.03.00-rc1
10452 04:42:24.082989 <6>[ 0.428929] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10453 04:42:24.086107 <6>[ 0.433030] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10454 04:42:24.092811 <6>[ 0.440892] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10455 04:42:24.105947 <6>[ 0.494680] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10456 04:42:24.583161 <6>[ 1.003312] Freeing initrd memory: 17380K
10457 04:42:24.590132 <6>[ 1.009612] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10458 04:42:24.593217 <6>[ 1.014310] tun: Universal TUN/TAP device driver, 1.6
10459 04:42:24.596629 <6>[ 1.015072] thunder_xcv, ver 1.0
10460 04:42:24.599889 <6>[ 1.015093] thunder_bgx, ver 1.0
10461 04:42:24.603086 <6>[ 1.015106] nicpf, ver 1.0
10462 04:42:24.613234 <6>[ 1.016166] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10463 04:42:24.616530 <6>[ 1.016169] hns3: Copyright (c) 2017 Huawei Corporation.
10464 04:42:24.619714 <6>[ 1.016195] hclge is initializing
10465 04:42:24.626618 <6>[ 1.016209] e1000: Intel(R) PRO/1000 Network Driver
10466 04:42:24.633248 <6>[ 1.016211] e1000: Copyright (c) 1999-2006 Intel Corporation.
10467 04:42:24.637259 <6>[ 1.016231] e1000e: Intel(R) PRO/1000 Network Driver
10468 04:42:24.644468 <6>[ 1.016232] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10469 04:42:24.648154 <6>[ 1.016248] igb: Intel(R) Gigabit Ethernet Network Driver
10470 04:42:24.654660 <6>[ 1.016249] igb: Copyright (c) 2007-2014 Intel Corporation.
10471 04:42:24.661594 <6>[ 1.016268] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10472 04:42:24.668913 <6>[ 1.016270] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10473 04:42:24.672168 <6>[ 1.016565] sky2: driver version 1.30
10474 04:42:24.675150 <6>[ 1.017650] VFIO - User Level meta-driver version: 0.3
10475 04:42:24.681813 <6>[ 1.020475] usbcore: registered new interface driver usb-storage
10476 04:42:24.688440 <6>[ 1.020657] usbcore: registered new device driver onboard-usb-hub
10477 04:42:24.695270 <6>[ 1.023468] mt6397-rtc mt6359-rtc: registered as rtc0
10478 04:42:24.704839 <6>[ 1.023625] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-04T04:42:26 UTC (1707021746)
10479 04:42:24.708604 <6>[ 1.024239] i2c_dev: i2c /dev entries driver
10480 04:42:24.715167 <6>[ 1.031494] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10481 04:42:24.721405 <6>[ 1.047498] cpu cpu0: EM: created perf domain
10482 04:42:24.724992 <6>[ 1.047810] cpu cpu4: EM: created perf domain
10483 04:42:24.731767 <6>[ 1.053108] sdhci: Secure Digital Host Controller Interface driver
10484 04:42:24.735119 <6>[ 1.053109] sdhci: Copyright(c) Pierre Ossman
10485 04:42:24.741197 <6>[ 1.053460] Synopsys Designware Multimedia Card Interface Driver
10486 04:42:24.747800 <6>[ 1.053829] sdhci-pltfm: SDHCI platform and OF driver helper
10487 04:42:24.754888 <6>[ 1.059093] ledtrig-cpu: registered to indicate activity on CPUs
10488 04:42:24.757981 <6>[ 1.059555] mmc0: CQHCI version 5.10
10489 04:42:24.764522 <6>[ 1.059958] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10490 04:42:24.771503 <6>[ 1.060237] usbcore: registered new interface driver usbhid
10491 04:42:24.774557 <6>[ 1.060239] usbhid: USB HID core driver
10492 04:42:24.781335 <6>[ 1.060359] spi_master spi0: will run message pump with realtime priority
10493 04:42:24.794603 <6>[ 1.090247] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10494 04:42:24.807599 <6>[ 1.092978] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10495 04:42:24.814579 <6>[ 1.094105] cros-ec-spi spi0.0: Chrome EC device registered
10496 04:42:24.824219 <6>[ 1.108086] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10497 04:42:24.827533 <6>[ 1.109078] NET: Registered PF_PACKET protocol family
10498 04:42:24.834551 <6>[ 1.109154] 9pnet: Installing 9P2000 support
10499 04:42:24.837544 <5>[ 1.109187] Key type dns_resolver registered
10500 04:42:24.840892 <6>[ 1.109618] registered taskstats version 1
10501 04:42:24.847369 <5>[ 1.109635] Loading compiled-in X.509 certificates
10502 04:42:24.857403 <4>[ 1.126185] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10503 04:42:24.867376 <4>[ 1.126412] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10504 04:42:24.874011 <3>[ 1.126424] debugfs: File 'uA_load' in directory '/' already present!
10505 04:42:24.880633 <3>[ 1.126430] debugfs: File 'min_uV' in directory '/' already present!
10506 04:42:24.887252 <3>[ 1.126434] debugfs: File 'max_uV' in directory '/' already present!
10507 04:42:24.897320 <3>[ 1.126437] debugfs: File 'constraint_flags' in directory '/' already present!
10508 04:42:24.903850 <3>[ 1.128693] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10509 04:42:24.910777 <6>[ 1.137553] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10510 04:42:24.917075 <6>[ 1.138184] xhci-mtk 11200000.usb: xHCI Host Controller
10511 04:42:24.923837 <6>[ 1.138203] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10512 04:42:24.933651 <6>[ 1.138404] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10513 04:42:24.940383 <6>[ 1.138441] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10514 04:42:24.943419 <6>[ 1.138515] xhci-mtk 11200000.usb: xHCI Host Controller
10515 04:42:24.953743 <6>[ 1.138518] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10516 04:42:24.960079 <6>[ 1.138526] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10517 04:42:24.963270 <6>[ 1.138818] hub 1-0:1.0: USB hub found
10518 04:42:24.966656 <6>[ 1.138830] hub 1-0:1.0: 1 port detected
10519 04:42:24.976718 <6>[ 1.138926] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10520 04:42:24.980101 <6>[ 1.139067] hub 2-0:1.0: USB hub found
10521 04:42:24.983189 <6>[ 1.139073] hub 2-0:1.0: 1 port detected
10522 04:42:24.989772 <6>[ 1.141717] mtk-msdc 11f70000.mmc: Got CD GPIO
10523 04:42:24.996759 <6>[ 1.150950] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10524 04:42:25.003310 <6>[ 1.150957] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10525 04:42:25.013188 <4>[ 1.151032] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10526 04:42:25.023433 <6>[ 1.151532] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10527 04:42:25.030035 <6>[ 1.151533] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10528 04:42:25.036430 <6>[ 1.151651] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10529 04:42:25.046752 <6>[ 1.151658] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10530 04:42:25.053273 <6>[ 1.151661] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10531 04:42:25.063113 <6>[ 1.151664] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10532 04:42:25.069576 <6>[ 1.152814] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10533 04:42:25.079673 <6>[ 1.152830] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10534 04:42:25.086292 <6>[ 1.152834] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10535 04:42:25.096328 <6>[ 1.152838] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10536 04:42:25.102890 <6>[ 1.152841] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10537 04:42:25.112606 <6>[ 1.152845] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10538 04:42:25.119410 <6>[ 1.152848] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10539 04:42:25.128991 <6>[ 1.152852] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10540 04:42:25.135487 <6>[ 1.152856] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10541 04:42:25.145364 <6>[ 1.152860] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10542 04:42:25.155643 <6>[ 1.152864] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10543 04:42:25.162340 <6>[ 1.152868] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10544 04:42:25.172159 <6>[ 1.152871] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10545 04:42:25.178565 <6>[ 1.152875] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10546 04:42:25.188554 <6>[ 1.152879] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10547 04:42:25.195246 <6>[ 1.153250] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10548 04:42:25.201541 <6>[ 1.153942] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10549 04:42:25.208444 <6>[ 1.154169] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10550 04:42:25.214968 <6>[ 1.154399] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10551 04:42:25.221544 <6>[ 1.154631] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10552 04:42:25.228004 <6>[ 1.154797] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10553 04:42:25.238069 <6>[ 1.154807] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10554 04:42:25.247937 <6>[ 1.154809] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10555 04:42:25.257646 <6>[ 1.154813] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10556 04:42:25.267672 <6>[ 1.154817] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10557 04:42:25.274168 <6>[ 1.154819] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10558 04:42:25.283994 <6>[ 1.154822] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10559 04:42:25.294148 <6>[ 1.154825] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10560 04:42:25.303918 <6>[ 1.154827] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10561 04:42:25.314018 <6>[ 1.154831] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10562 04:42:25.323828 <6>[ 1.154834] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10563 04:42:25.333771 <6>[ 1.155423] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10564 04:42:25.337100 <6>[ 1.158893] mmc0: Command Queue Engine enabled
10565 04:42:25.343906 <6>[ 1.158904] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10566 04:42:25.346926 <6>[ 1.159405] mmcblk0: mmc0:0001 DA4128 116 GiB
10567 04:42:25.353749 <6>[ 1.162468] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10568 04:42:25.359999 <6>[ 1.163343] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10569 04:42:25.363384 <6>[ 1.164031] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10570 04:42:25.370146 <6>[ 1.164522] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10571 04:42:25.376857 <6>[ 1.174060] Trying to probe devices needed for running init ...
10572 04:42:25.383267 <6>[ 1.517855] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10573 04:42:25.386600 <6>[ 1.544754] hub 2-1:1.0: USB hub found
10574 04:42:25.393037 <6>[ 1.545136] hub 2-1:1.0: 3 ports detected
10575 04:42:25.396555 <6>[ 1.547493] hub 2-1:1.0: USB hub found
10576 04:42:25.399818 <6>[ 1.547842] hub 2-1:1.0: 3 ports detected
10577 04:42:25.406308 <6>[ 1.665606] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10578 04:42:25.409823 <6>[ 1.818084] hub 1-1:1.0: USB hub found
10579 04:42:25.416470 <6>[ 1.818462] hub 1-1:1.0: 4 ports detected
10580 04:42:25.419588 <6>[ 1.822451] hub 1-1:1.0: USB hub found
10581 04:42:25.422797 <6>[ 1.822808] hub 1-1:1.0: 4 ports detected
10582 04:42:25.483005 <6>[ 1.897769] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10583 04:42:25.718406 <6>[ 2.133776] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10584 04:42:25.839251 <6>[ 2.261004] hub 1-1.4:1.0: USB hub found
10585 04:42:25.842704 <6>[ 2.261325] hub 1-1.4:1.0: 2 ports detected
10586 04:42:25.846174 <6>[ 2.264350] hub 1-1.4:1.0: USB hub found
10587 04:42:25.852744 <6>[ 2.264659] hub 1-1.4:1.0: 2 ports detected
10588 04:42:26.138635 <6>[ 2.553738] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10589 04:42:26.322573 <6>[ 2.737734] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10590 04:42:37.019077 <6>[ 13.442781] ALSA device list:
10591 04:42:37.025664 <6>[ 13.442803] No soundcards found.
10592 04:42:37.028745 <6>[ 13.447205] Freeing unused kernel memory: 8448K
10593 04:42:37.032028 <6>[ 13.447361] Run /init as init process
10594 04:42:37.035475 Loading, please wait...
10595 04:42:37.052259 Starting version 247.3-7+deb11u2
10596 04:42:37.285097 <6>[ 13.704351] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10597 04:42:37.292083 <6>[ 13.704416] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10598 04:42:37.301812 <6>[ 13.704429] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10599 04:42:37.308355 <3>[ 13.714702] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10600 04:42:37.318303 <3>[ 13.714737] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10601 04:42:37.325065 <3>[ 13.714747] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10602 04:42:37.334715 <3>[ 13.715358] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10603 04:42:37.341359 <3>[ 13.715373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10604 04:42:37.351531 <3>[ 13.715380] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10605 04:42:37.358116 <3>[ 13.715391] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10606 04:42:37.367927 <3>[ 13.715399] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10607 04:42:37.374633 <3>[ 13.715449] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10608 04:42:37.381612 <3>[ 13.715507] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10609 04:42:37.391875 <3>[ 13.715515] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10610 04:42:37.398633 <3>[ 13.715521] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10611 04:42:37.405638 <3>[ 13.715573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10612 04:42:37.415880 <3>[ 13.715581] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10613 04:42:37.422152 <3>[ 13.715587] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10614 04:42:37.432152 <3>[ 13.715595] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10615 04:42:37.438646 <3>[ 13.715602] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10616 04:42:37.448679 <3>[ 13.715650] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10617 04:42:37.455224 <6>[ 13.738874] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10618 04:42:37.458629 <6>[ 13.744501] mc: Linux media interface: v0.10
10619 04:42:37.464991 <4>[ 13.749102] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10620 04:42:37.474974 <4>[ 13.750258] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10621 04:42:37.478476 <6>[ 13.750714] remoteproc remoteproc0: scp is available
10622 04:42:37.484976 <6>[ 13.750805] remoteproc remoteproc0: powering up scp
10623 04:42:37.491624 <6>[ 13.750812] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10624 04:42:37.498002 <6>[ 13.750831] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10625 04:42:37.504783 <6>[ 13.771850] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10626 04:42:37.511512 <6>[ 13.779378] usbcore: registered new device driver r8152-cfgselector
10627 04:42:37.517800 <6>[ 13.787797] videodev: Linux video capture interface: v2.00
10628 04:42:37.527937 <4>[ 13.795687] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10629 04:42:37.531271 <4>[ 13.795687] Fallback method does not support PEC.
10630 04:42:37.541066 <3>[ 13.812569] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10631 04:42:37.550984 <6>[ 13.817984] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10632 04:42:37.561110 <6>[ 13.818409] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10633 04:42:37.567271 <6>[ 13.822831] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10634 04:42:37.570876 <6>[ 13.822842] pci_bus 0000:00: root bus resource [bus 00-ff]
10635 04:42:37.580462 <6>[ 13.822848] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10636 04:42:37.590781 <6>[ 13.822853] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10637 04:42:37.597276 <6>[ 13.822888] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10638 04:42:37.603897 <6>[ 13.822907] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10639 04:42:37.607153 <6>[ 13.822984] pci 0000:00:00.0: supports D1 D2
10640 04:42:37.613663 <6>[ 13.822987] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10641 04:42:37.623864 <6>[ 13.824538] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10642 04:42:37.630428 <6>[ 13.824641] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10643 04:42:37.636880 <6>[ 13.824671] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10644 04:42:37.643538 <6>[ 13.824690] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10645 04:42:37.650294 <6>[ 13.824708] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10646 04:42:37.656815 <6>[ 13.824819] pci 0000:01:00.0: supports D1 D2
10647 04:42:37.663478 <6>[ 13.824822] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10648 04:42:37.670160 <6>[ 13.833503] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10649 04:42:37.676901 <6>[ 13.833545] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10650 04:42:37.686744 <6>[ 13.833551] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10651 04:42:37.693386 <6>[ 13.833564] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10652 04:42:37.703093 <6>[ 13.833581] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10653 04:42:37.709681 <6>[ 13.833597] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10654 04:42:37.716266 <6>[ 13.833613] pci 0000:00:00.0: PCI bridge to [bus 01]
10655 04:42:37.722872 <6>[ 13.833622] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10656 04:42:37.729369 <6>[ 13.833784] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10657 04:42:37.736121 <6>[ 13.835101] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10658 04:42:37.742564 <3>[ 13.835215] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10659 04:42:37.749385 <6>[ 13.835831] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10660 04:42:37.759295 <6>[ 13.857562] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10661 04:42:37.768811 <6>[ 13.865870] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10662 04:42:37.775818 <6>[ 13.883352] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10663 04:42:37.781972 <6>[ 13.883413] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10664 04:42:37.788568 <6>[ 13.883421] remoteproc remoteproc0: remote processor scp is now up
10665 04:42:37.798648 <5>[ 13.885891] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10666 04:42:37.802285 <6>[ 13.888613] Bluetooth: Core ver 2.22
10667 04:42:37.805389 <6>[ 13.888737] NET: Registered PF_BLUETOOTH protocol family
10668 04:42:37.811856 <6>[ 13.888740] Bluetooth: HCI device and connection manager initialized
10669 04:42:37.818570 <6>[ 13.888766] Bluetooth: HCI socket layer initialized
10670 04:42:37.825259 <6>[ 13.888771] Bluetooth: L2CAP socket layer initialized
10671 04:42:37.828496 <6>[ 13.888781] Bluetooth: SCO socket layer initialized
10672 04:42:37.838267 <4>[ 13.891727] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10673 04:42:37.845372 <4>[ 13.891741] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10674 04:42:37.851763 <5>[ 13.898844] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10675 04:42:37.861630 <5>[ 13.899301] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10676 04:42:37.871549 <4>[ 13.899372] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10677 04:42:37.874778 <6>[ 13.899380] cfg80211: failed to load regulatory.db
10678 04:42:37.884545 <6>[ 13.905300] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10679 04:42:37.891280 <6>[ 13.907373] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10680 04:42:37.898005 <6>[ 13.927939] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10681 04:42:37.911182 <6>[ 13.928971] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10682 04:42:37.917819 <6>[ 13.929061] usbcore: registered new interface driver uvcvideo
10683 04:42:37.921131 <6>[ 13.941648] r8152 2-1.3:1.0 eth0: v1.12.13
10684 04:42:37.927448 <6>[ 13.941743] usbcore: registered new interface driver r8152
10685 04:42:37.934130 <6>[ 13.948383] usbcore: registered new interface driver btusb
10686 04:42:37.940749 <6>[ 13.948746] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10687 04:42:37.950825 <4>[ 13.949244] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10688 04:42:37.957323 <3>[ 13.949251] Bluetooth: hci0: Failed to load firmware file (-2)
10689 04:42:37.960477 <3>[ 13.949256] Bluetooth: hci0: Failed to set up firmware (-2)
10690 04:42:37.970555 <4>[ 13.949259] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10691 04:42:37.977405 <6>[ 13.960841] usbcore: registered new interface driver cdc_ether
10692 04:42:37.983754 <6>[ 13.969571] usbcore: registered new interface driver r8153_ecm
10693 04:42:37.990231 <6>[ 13.984120] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10694 04:42:37.996960 <6>[ 14.015054] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10695 04:42:38.003499 <6>[ 14.015150] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10696 04:42:38.010203 <6>[ 14.033636] mt7921e 0000:01:00.0: ASIC revision: 79610010
10697 04:42:38.016722 <6>[ 14.132581] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10698 04:42:38.020208 <6>[ 14.132581]
10699 04:42:38.030104 <6>[ 14.390488] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10700 04:42:38.033268 Begin: Loading essential drivers ... done.
10701 04:42:38.036628 Begin: Running /scripts/init-premount ... done.
10702 04:42:38.043173 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10703 04:42:38.053295 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10704 04:42:38.056693 Device /sys/class/net/enx0024323078ff found
10705 04:42:38.056798 done.
10706 04:42:38.097152 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10707 04:42:38.813803 <6>[ 15.236513] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10708 04:42:39.089604 <6>[ 15.509992] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10709 04:42:39.099783 IP-Config: no response after 2 secs - giving up
10710 04:42:39.169019 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10711 04:42:39.186130 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:07 mtu 1500 DHCP
10712 04:42:39.899273 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10713 04:42:39.906042 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10714 04:42:39.912754 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10715 04:42:39.919274 host : mt8192-asurada-spherion-r0-cbg-8
10716 04:42:39.925533 domain : lava-rack
10717 04:42:39.932275 rootserver: 192.168.201.1 rootpath:
10718 04:42:39.932385 filename :
10719 04:42:40.051512 done.
10720 04:42:40.059540 Begin: Running /scripts/nfs-bottom ... done.
10721 04:42:40.082020 Begin: Running /scripts/init-bottom ... done.
10722 04:42:41.307117 <6>[ 17.727191] NET: Registered PF_INET6 protocol family
10723 04:42:41.310083 <6>[ 17.729198] Segment Routing with IPv6
10724 04:42:41.316574 <6>[ 17.729223] In-situ OAM (IOAM) with IPv6
10725 04:42:41.450516 <30>[ 17.850250] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10726 04:42:41.452427 <30>[ 17.851249] systemd[1]: Detected architecture arm64.
10727 04:42:41.452561
10728 04:42:41.459094 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10729 04:42:41.459184
10730 04:42:41.481499 <30>[ 17.904765] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10731 04:42:42.364705 <30>[ 18.783334] systemd[1]: Queued start job for default target Graphical Interface.
10732 04:42:42.391977 [[0;32m OK [<30>[ 18.812188] systemd[1]: Created slice system-getty.slice.
10733 04:42:42.395198 0m] Created slice [0;1;39msystem-getty.slice[0m.
10734 04:42:42.414316 [[0;32m OK [0m] Created slic<30>[ 18.835149] systemd[1]: Created slice system-modprobe.slice.
10735 04:42:42.417815 e [0;1;39msystem-modprobe.slice[0m.
10736 04:42:42.438374 [[0;32m OK [0m] Created slic<30>[ 18.859050] systemd[1]: Created slice system-serial\x2dgetty.slice.
10737 04:42:42.444702 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10738 04:42:42.462739 [[0;32m OK [0m] Created slic<30>[ 18.883584] systemd[1]: Created slice User and Session Slice.
10739 04:42:42.466209 e [0;1;39mUser and Session Slice[0m.
10740 04:42:42.489209 [[0;32m OK [0m] Started [0;<30>[ 18.906572] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10741 04:42:42.492725 1;39mDispatch Password …ts to Console Directory Watch[0m.
10742 04:42:42.516944 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 18.934394] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10743 04:42:42.520512 sword R…uests to Wall Directory Watch[0m.
10744 04:42:42.548318 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 18.962074] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10745 04:42:42.557895 l Encrypted Volu<30>[ 18.962268] systemd[1]: Reached target Local Encrypted Volumes.
10746 04:42:42.558001 mes[0m.
10747 04:42:42.577076 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 18.997868] systemd[1]: Reached target Paths.
10748 04:42:42.577180 s[0m.
10749 04:42:42.600216 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.017752] systemd[1]: Reached target Remote File Systems.
10750 04:42:42.600335 te File Systems[0m.
10751 04:42:42.621747 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.042135] systemd[1]: Reached target Slices.
10752 04:42:42.621859 es[0m.
10753 04:42:42.640969 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.061766] systemd[1]: Reached target Swap.
10754 04:42:42.641083 [0m.
10755 04:42:42.664905 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.082262] systemd[1]: Listening on initctl Compatibility Named Pipe.
10756 04:42:42.668100 l Compatibility Named Pipe[0m.
10757 04:42:42.678262 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.098533] systemd[1]: Listening on Journal Audit Socket.
10758 04:42:42.681233 l Audit Socket[0m.
10759 04:42:42.702878 [[0;32m OK [0m] Listening on<30>[ 19.123235] systemd[1]: Listening on Journal Socket (/dev/log).
10760 04:42:42.705737 [0;1;39mJournal Socket (/dev/log)[0m.
10761 04:42:42.726251 [[0;32m OK [0m] Listening on<30>[ 19.147025] systemd[1]: Listening on Journal Socket.
10762 04:42:42.729660 [0;1;39mJournal Socket[0m.
10763 04:42:42.746810 [[0;32m OK [0m] Listening on<30>[ 19.167542] systemd[1]: Listening on Network Service Netlink Socket.
10764 04:42:42.753425 [0;1;39mNetwork Service Netlink Socket[0m.
10765 04:42:42.772974 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 19.193550] systemd[1]: Listening on udev Control Socket.
10766 04:42:42.776393 ontrol Socket[0m.
10767 04:42:42.793641 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 19.214266] systemd[1]: Listening on udev Kernel Socket.
10768 04:42:42.796663 ernel Socket[0m.
10769 04:42:42.860616 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.278075] systemd[1]: Mounting Huge Pages File System...
10770 04:42:42.860751 m[0m...
10771 04:42:42.879411 Mountin<30>[ 19.300182] systemd[1]: Mounting POSIX Message Queue File System...
10772 04:42:42.882623 g [0;1;39mPOSIX Message Queue File System[0m...
10773 04:42:42.908708 Mounting [0;1;39mKernel Debug File Sys<30>[ 19.325736] systemd[1]: Mounting Kernel Debug File System...
10774 04:42:42.908846 tem[0m...
10775 04:42:42.928643 <30>[ 19.346238] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10776 04:42:42.938446 <30>[ 19.353524] systemd[1]: Starting Create list of static device nodes for the current kernel...
10777 04:42:42.945141 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10778 04:42:42.972176 Starting [0;1;39mLoad Kernel Module co<30>[ 19.389687] systemd[1]: Starting Load Kernel Module configfs...
10779 04:42:42.972283 nfigfs[0m...
10780 04:42:42.996389 Startin<30>[ 19.416838] systemd[1]: Starting Load Kernel Module drm...
10781 04:42:42.999507 g [0;1;39mLoad Kernel Module drm[0m...
10782 04:42:43.025928 Starting [0;1;39mLoad <30>[ 19.446667] systemd[1]: Starting Load Kernel Module fuse...
10783 04:42:43.029447 Kernel Module fuse[0m...
10784 04:42:43.065904 <6>[ 19.488613] fuse: init (API version 7.37)
10785 04:42:43.075546 <30>[ 19.489650] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10786 04:42:43.086967 Starting [0;1;39mJourn<30>[ 19.507529] systemd[1]: Starting Journal Service...
10787 04:42:43.087057 al Service[0m...
10788 04:42:43.121487 Starting [0;1;39mLoad Kernel Modules[<30>[ 19.542295] systemd[1]: Starting Load Kernel Modules...
10789 04:42:43.124800 0m...
10790 04:42:43.152359 Startin<30>[ 19.572950] systemd[1]: Starting Remount Root and Kernel File Systems...
10791 04:42:43.159048 g [0;1;39mRemount Root and Kernel File Systems[0m...
10792 04:42:43.186143 Starting [0;1;39mColdp<30>[ 19.606825] systemd[1]: Starting Coldplug All udev Devices...
10793 04:42:43.189367 lug All udev Devices[0m...
10794 04:42:43.214614 [[0;32m OK [0m] Mounted [0;<30>[ 19.634981] systemd[1]: Mounted Huge Pages File System.
10795 04:42:43.224678 1;39mHuge Pages <3>[ 19.637071] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10796 04:42:43.224798 File System[0m.
10797 04:42:43.248508 <3>[ 19.665643] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10798 04:42:43.259714 [[0;32m OK [<30>[ 19.680297] systemd[1]: Mounted POSIX Message Queue File System.
10799 04:42:43.263001 0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10800 04:42:43.280565 <3>[ 19.697532] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10801 04:42:43.291215 [[0;32m OK [0m] Mounted [0;<30>[ 19.710923] systemd[1]: Mounted Kernel Debug File System.
10802 04:42:43.300857 1;39mKernel Debu<3>[ 19.718894] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10803 04:42:43.300967 g File System[0m.
10804 04:42:43.329761 [[0;32m OK [0m] Finished [0<30>[ 19.746717] systemd[1]: Finished Create list of static device nodes for the current kernel.
10805 04:42:43.339870 ;1;39mCreate lis<3>[ 19.754187] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10806 04:42:43.342977 t of st… nodes for the current kernel[0m.
10807 04:42:43.356368 <3>[ 19.774344] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10808 04:42:43.367956 [[0;32m OK [0m] Finished [0<30>[ 19.787382] systemd[1]: modprobe@configfs.service: Succeeded.
10809 04:42:43.374866 ;1;39mLoad Kerne<30>[ 19.788009] systemd[1]: Finished Load Kernel Module configfs.
10810 04:42:43.384970 l Module configf<3>[ 19.795165] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10811 04:42:43.385087 s[0m.
10812 04:42:43.396587 <3>[ 19.815209] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10813 04:42:43.407680 [[0;32m OK [0m] Finished [0<30>[ 19.827412] systemd[1]: modprobe@drm.service: Succeeded.
10814 04:42:43.414405 ;1;39mLoad Kerne<30>[ 19.828056] systemd[1]: Finished Load Kernel Module drm.
10815 04:42:43.424344 l Module drm[0m<3>[ 19.836554] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10816 04:42:43.424456 .
10817 04:42:43.440522 <3>[ 19.859945] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10818 04:42:43.452138 [[0;32m OK [<30>[ 19.871618] systemd[1]: modprobe@fuse.service: Succeeded.
10819 04:42:43.458862 0m] Finished [0<30>[ 19.872272] systemd[1]: Finished Load Kernel Module fuse.
10820 04:42:43.461650 ;1;39mLoad Kernel Module fuse[0m.
10821 04:42:43.478667 [[0;32m OK [0m] Finished [0<30>[ 19.899059] systemd[1]: Finished Load Kernel Modules.
10822 04:42:43.481795 ;1;39mLoad Kernel Modules[0m.
10823 04:42:43.497624 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 19.918221] systemd[1]: Started Journal Service.
10824 04:42:43.500691 vice[0m.
10825 04:42:43.520825 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10826 04:42:43.578708 Mounting [0;1;39mFUSE Control File System[0m...
10827 04:42:43.597882 Mounting [0;1;39mKernel Configuration File System[0m...
10828 04:42:43.638319 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10829 04:42:43.656707 Starting [0;1;39mLoad/Save Random Seed[0m...
10830 04:42:43.677758 Starting [0;1;39mApply Kernel Variables[0m...
10831 04:42:43.700614 <46>[ 20.118769] systemd-journald[307]: Received client request to flush runtime journal.
10832 04:42:43.707092 Starting [0;1;39mCreate System Users[0m...
10833 04:42:43.725991 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10834 04:42:43.742047 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10835 04:42:43.758752 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10836 04:42:43.779048 <4>[ 20.190944] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10837 04:42:43.788965 <3>[ 20.191001] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10838 04:42:43.795762 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10839 04:42:43.809715 See 'systemctl status systemd-udev-trigger.service' for details.
10840 04:42:44.449143 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10841 04:42:45.096702 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10842 04:42:45.148433 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10843 04:42:45.198544 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10844 04:42:45.303129 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10845 04:42:45.318114 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10846 04:42:45.337453 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10847 04:42:45.381640 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10848 04:42:45.405365 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10849 04:42:45.566233 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10850 04:42:45.620018 Starting [0;1;39mNetwork Service[0m...
10851 04:42:45.763182 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10852 04:42:45.961939 Starting [0;1;39mNetwork Time Synchronization[0m...
10853 04:42:45.984364 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10854 04:42:46.097987 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10855 04:42:46.367521 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10856 04:42:46.387572 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10857 04:42:46.410225 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10858 04:42:46.425515 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10859 04:42:46.444665 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10860 04:42:46.489390 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10861 04:42:46.521861 Starting [0;1;39mNetwork Name Resolution[0m...
10862 04:42:46.539211 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10863 04:42:46.558811 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10864 04:42:46.577675 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10865 04:42:46.646325 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10866 04:42:46.668294 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10867 04:42:46.682568 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10868 04:42:47.323333 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10869 04:42:47.661698 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10870 04:42:47.690708 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10871 04:42:47.711204 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10872 04:42:47.728383 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10873 04:42:47.741068 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10874 04:42:47.779326 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10875 04:42:47.793870 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10876 04:42:47.809279 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10877 04:42:47.853920 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10878 04:42:48.032642 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10879 04:42:48.191676 Starting [0;1;39mUser Login Management[0m...
10880 04:42:48.209948 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10881 04:42:48.325818 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10882 04:42:48.346363 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10883 04:42:48.356311 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10884 04:42:48.390800 Starting [0;1;39mPermit User Sessions[0m...
10885 04:42:48.491370 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10886 04:42:48.511250 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10887 04:42:48.553713 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10888 04:42:48.572186 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10889 04:42:48.588952 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10890 04:42:48.609673 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10891 04:42:48.627260 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10892 04:42:48.645812 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10893 04:42:48.698148 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10894 04:42:48.743079 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10895 04:42:48.810454
10896 04:42:48.810607
10897 04:42:48.813776 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10898 04:42:48.813867
10899 04:42:48.817095 debian-bullseye-arm64 login: root (automatic login)
10900 04:42:48.817183
10901 04:42:48.817257
10902 04:42:49.147919 Linux debian-bullseye-arm64 6.1.75-cip14-rt8 #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024 aarch64
10903 04:42:49.148071
10904 04:42:49.154641 The programs included with the Debian GNU/Linux system are free software;
10905 04:42:49.161163 the exact distribution terms for each program are described in the
10906 04:42:49.164711 individual files in /usr/share/doc/*/copyright.
10907 04:42:49.164819
10908 04:42:49.171364 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10909 04:42:49.174424 permitted by applicable law.
10910 04:42:49.276804 Matched prompt #10: / #
10912 04:42:49.277093 Setting prompt string to ['/ #']
10913 04:42:49.277189 end: 2.2.5.1 login-action (duration 00:00:26) [common]
10915 04:42:49.277380 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10916 04:42:49.277468 start: 2.2.6 expect-shell-connection (timeout 00:03:16) [common]
10917 04:42:49.277578 Setting prompt string to ['/ #']
10918 04:42:49.277638 Forcing a shell prompt, looking for ['/ #']
10920 04:42:49.327863 / #
10921 04:42:49.328044 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10922 04:42:49.328159 Waiting using forced prompt support (timeout 00:02:30)
10923 04:42:49.332861
10924 04:42:49.333162 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10925 04:42:49.333259 start: 2.2.7 export-device-env (timeout 00:03:15) [common]
10927 04:42:49.433586 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12699810/extract-nfsrootfs-ogidnyo1'
10928 04:42:49.438661 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12699810/extract-nfsrootfs-ogidnyo1'
10930 04:42:49.539459 / # export NFS_SERVER_IP='192.168.201.1'
10931 04:42:49.545099 export NFS_SERVER_IP='192.168.201.1'
10932 04:42:49.545571 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10933 04:42:49.545764 end: 2.2 depthcharge-retry (duration 00:01:45) [common]
10934 04:42:49.545917 end: 2 depthcharge-action (duration 00:01:45) [common]
10935 04:42:49.546068 start: 3 lava-test-retry (timeout 00:30:00) [common]
10936 04:42:49.546215 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10937 04:42:49.546335 Using namespace: common
10939 04:42:49.647035 / # #
10940 04:42:49.647645 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
10941 04:42:49.653249 #
10942 04:42:49.654096 Using /lava-12699810
10944 04:42:49.755057 / # export SHELL=/bin/sh
10945 04:42:49.760490 export SHELL=/bin/sh
10947 04:42:49.860985 / # . /lava-12699810/environment
10948 04:42:49.865806 . /lava-12699810/environment
10950 04:42:49.972640 / # /lava-12699810/bin/lava-test-runner /lava-12699810/0
10951 04:42:49.973153 Test shell timeout: 10s (minimum of the action and connection timeout)
10952 04:42:49.979004 /lava-12699810/bin/lava-test-runner /lava-12699810/0
10953 04:42:50.272823 + export TESTRUN_ID=0_lc-compliance
10954 04:42:50.279069 + cd /lava-12699810/0/tests/0_lc-compliance
10955 04:42:50.279169 + cat uuid
10956 04:42:50.289393 + UUID=12699810_1.6.2.3.1
10957 04:42:50.289481 + set +x
10958 04:42:50.296125 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 12699810_1.6.2.3.1>
10959 04:42:50.296378 Received signal: <STARTRUN> 0_lc-compliance 12699810_1.6.2.3.1
10960 04:42:50.296456 Starting test lava.0_lc-compliance (12699810_1.6.2.3.1)
10961 04:42:50.296580 Skipping test definition patterns.
10962 04:42:50.299233 + /usr/bin/lc-compliance-parser.sh
10963 04:42:51.555354 [0:00:27.936232078] [412] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:297 [0mlibcamera v0.0.0+1-1f607da9
10964 04:42:51.558637 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
10965 04:42:51.573174 [0:00:27.954322924] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10966 04:42:51.632953 [0:00:28.014030693] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10967 04:42:51.658576 [==========] Running 120 tests from 1 test suite.
10968 04:42:51.688402 [0:00:28.069308770] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10969 04:42:51.742455 [0:00:28.123689001] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10970 04:42:51.760942 [----------] Global test environment set-up.
10971 04:42:51.853671 [----------] 120 tests from CaptureTests/SingleStream
10972 04:42:51.945775 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
10973 04:42:52.015478 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
10974 04:42:52.015782 Received signal: <TESTSET> START CaptureTests/SingleStream
10975 04:42:52.015875 Starting test_set CaptureTests/SingleStream
10976 04:42:52.018623 Camera needs 4 requests, can't test only 1
10977 04:42:52.100557 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10978 04:42:52.171484 [0:00:28.552637155] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10979 04:42:52.194599
10980 04:42:52.286820 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (60 ms)
10981 04:42:52.401967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
10982 04:42:52.402359 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
10984 04:42:52.421659 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
10985 04:42:52.480032 Camera needs 4 requests, can't test only 2
10986 04:42:52.580483 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10987 04:42:52.666873
10988 04:42:52.700157 [0:00:29.081279155] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10989 04:42:52.762559 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (55 ms)
10990 04:42:52.871082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
10991 04:42:52.871411 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
10993 04:42:52.889579 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
10994 04:42:52.955018 Camera needs 4 requests, can't test only 3
10995 04:42:53.052034 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10996 04:42:53.140774
10997 04:42:53.237676 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (54 ms)
10998 04:42:53.333172 [0:00:29.714481539] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10999 04:42:53.344804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11000 04:42:53.345084 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11002 04:42:53.365533 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11003 04:42:53.425629 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (430 ms)
11004 04:42:53.527822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11005 04:42:53.528129 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11007 04:42:53.545761 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11008 04:42:53.603243 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (526 ms)
11009 04:42:53.707794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11010 04:42:53.708110 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11012 04:42:53.727096 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11013 04:42:53.783783 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (633 ms)
11014 04:42:53.882363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11015 04:42:53.882703 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11017 04:42:53.901831 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11018 04:42:54.220837 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (897 ms)
11019 04:42:54.230644 [0:00:30.611343693] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11020 04:42:54.338198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11021 04:42:54.338500 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11023 04:42:54.359220 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11024 04:42:55.615553 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1395 ms)
11025 04:42:55.625403 [0:00:32.006723616] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11026 04:42:55.721956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11027 04:42:55.722249 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11029 04:42:55.742828 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11030 04:42:57.710926 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2095 ms)
11031 04:42:57.720700 [0:00:34.101927463] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11032 04:42:57.824347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11033 04:42:57.824646 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11035 04:42:57.842373 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11036 04:43:00.938776 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3229 ms)
11037 04:43:00.948831 [0:00:37.330931924] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11038 04:43:01.003171 [0:00:37.385575232] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11039 04:43:01.043103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11040 04:43:01.043402 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11042 04:43:01.057763 [0:00:37.439772617] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11043 04:43:01.064122 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11044 04:43:01.111737 [0:00:37.493970771] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11045 04:43:01.124436 Camera needs 4 requests, can't test only 1
11046 04:43:01.209095 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11047 04:43:01.287726
11048 04:43:01.377049 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (56 ms)
11049 04:43:01.476344 [0:00:37.858599540] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11050 04:43:01.479998 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11052 04:43:01.483003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11053 04:43:01.491726 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11054 04:43:01.549180 Camera needs 4 requests, can't test only 2
11055 04:43:01.635811 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11056 04:43:01.711727
11057 04:43:01.797576 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (54 ms)
11058 04:43:01.892039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11059 04:43:01.892360 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11061 04:43:01.909179 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11062 04:43:01.941300 [0:00:38.323738617] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11063 04:43:01.963083 Camera needs 4 requests, can't test only 3
11064 04:43:02.049758 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11065 04:43:02.130087
11066 04:43:02.217874 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (54 ms)
11067 04:43:02.319645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11068 04:43:02.320336 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11070 04:43:02.342475 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11071 04:43:02.411403 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (364 ms)
11072 04:43:02.510589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11073 04:43:02.510900 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11075 04:43:02.528066 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11076 04:43:02.584774 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (465 ms)
11077 04:43:02.637140 [0:00:39.019479617] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11078 04:43:02.683144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11079 04:43:02.683472 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11081 04:43:02.700871 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11082 04:43:02.756775 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (696 ms)
11083 04:43:02.854064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11084 04:43:02.854383 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11086 04:43:02.872208 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11087 04:43:03.528048 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (899 ms)
11088 04:43:03.540879 [0:00:39.919156694] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11089 04:43:03.648385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11090 04:43:03.648725 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11092 04:43:03.666451 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11093 04:43:04.924075 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1396 ms)
11094 04:43:04.937322 [0:00:41.316217463] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11095 04:43:05.052597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11096 04:43:05.053403 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11098 04:43:05.076288 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11099 04:43:07.021611 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2097 ms)
11100 04:43:07.034460 [0:00:43.413978155] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11101 04:43:07.154387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11102 04:43:07.155161 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11104 04:43:07.175449 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11105 04:43:07.607721 <6>[ 44.033695] vpu: disabling
11106 04:43:07.611147 <6>[ 44.033817] vproc2: disabling
11107 04:43:07.614330 <6>[ 44.033873] vproc1: disabling
11108 04:43:07.617519 <6>[ 44.033928] vaud18: disabling
11109 04:43:07.620648 <6>[ 44.034180] vsram_others: disabling
11110 04:43:07.624015 <6>[ 44.034361] va09: disabling
11111 04:43:07.627917 <6>[ 44.034439] vsram_md: disabling
11112 04:43:07.630821 <6>[ 44.034572] Vgpu: disabling
11113 04:43:10.188534 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3168 ms)
11114 04:43:10.201747 [0:00:46.580862617] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11115 04:43:10.252285 [0:00:46.635471310] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11116 04:43:10.306926 [0:00:46.690143079] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11117 04:43:10.314601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11118 04:43:10.314895 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11120 04:43:10.332121 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11121 04:43:10.362169 [0:00:46.745452694] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11122 04:43:10.395690 Camera needs 4 requests, can't test only 1
11123 04:43:10.493414 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11124 04:43:10.577403
11125 04:43:10.678251 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (56 ms)
11126 04:43:10.792259 [0:00:47.174995925] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11127 04:43:10.798800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11128 04:43:10.799574 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11130 04:43:10.819063 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11131 04:43:10.886954 Camera needs 4 requests, can't test only 2
11132 04:43:10.992931 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11133 04:43:11.094365
11134 04:43:11.202049 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (54 ms)
11135 04:43:11.257117 [0:00:47.640038310] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11136 04:43:11.329335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11137 04:43:11.330231 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11139 04:43:11.350571 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11140 04:43:11.420850 Camera needs 4 requests, can't test only 3
11141 04:43:11.528721 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11142 04:43:11.633041
11143 04:43:11.744835 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (55 ms)
11144 04:43:11.870516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11145 04:43:11.871341 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11147 04:43:11.892031 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11148 04:43:11.952863 [0:00:48.335781694] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11149 04:43:11.963346 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (430 ms)
11150 04:43:12.083361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11151 04:43:12.084152 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11153 04:43:12.105657 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11154 04:43:12.176487 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (465 ms)
11155 04:43:12.300720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11156 04:43:12.301569 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11158 04:43:12.323115 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11159 04:43:12.398053 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (696 ms)
11160 04:43:12.522819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11161 04:43:12.523692 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11163 04:43:12.545465 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11164 04:43:12.940162 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (996 ms)
11165 04:43:12.953195 [0:00:49.333336310] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11166 04:43:13.072299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11167 04:43:13.073103 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11169 04:43:13.091843 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11170 04:43:14.370945 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1431 ms)
11171 04:43:14.383912 [0:00:50.763295617] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11172 04:43:14.493907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11173 04:43:14.494220 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11175 04:43:14.512569 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11176 04:43:16.465662 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2095 ms)
11177 04:43:16.478603 [0:00:52.858347618] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11178 04:43:16.586279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11179 04:43:16.587072 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11181 04:43:16.607490 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11182 04:43:19.630096 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3165 ms)
11183 04:43:19.643042 [0:00:56.023197441] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11184 04:43:19.691635 [0:00:56.075751723] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11185 04:43:19.733399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11186 04:43:19.733738 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11188 04:43:19.748372 [0:00:56.132313620] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11189 04:43:19.751448 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11190 04:43:19.802361 [0:00:56.186608083] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11191 04:43:19.810438 Camera needs 4 requests, can't test only 1
11192 04:43:19.887663 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11193 04:43:19.968221
11194 04:43:20.050909 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (54 ms)
11195 04:43:20.141330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11196 04:43:20.141638 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11198 04:43:20.160089 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11199 04:43:20.170063 [0:00:56.551538996] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11200 04:43:20.219539 Camera needs 4 requests, can't test only 2
11201 04:43:20.299875 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11202 04:43:20.378790
11203 04:43:20.462626 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (56 ms)
11204 04:43:20.562773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11205 04:43:20.563098 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11207 04:43:20.579745 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11208 04:43:20.631677 [0:00:57.015656743] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11209 04:43:20.638176 Camera needs 4 requests, can't test only 3
11210 04:43:20.717743 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11211 04:43:20.792653
11212 04:43:20.879150 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (54 ms)
11213 04:43:20.976532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11214 04:43:20.976842 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11216 04:43:20.994682 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11217 04:43:21.049273 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (365 ms)
11218 04:43:21.141371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11219 04:43:21.141732 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11221 04:43:21.158771 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11222 04:43:21.217061 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (464 ms)
11223 04:43:21.302877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11224 04:43:21.303214 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11226 04:43:21.319203 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11227 04:43:21.328761 [0:00:57.711452888] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11228 04:43:21.375686 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (695 ms)
11229 04:43:21.464070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11230 04:43:21.464384 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11232 04:43:21.483272 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11233 04:43:22.216866 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (899 ms)
11234 04:43:22.230231 [0:00:58.609360766] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11235 04:43:22.315704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11236 04:43:22.316024 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11238 04:43:22.333429 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11239 04:43:23.612306 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1395 ms)
11240 04:43:23.625511 [0:01:00.005421900] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11241 04:43:23.701095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11242 04:43:23.701418 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11244 04:43:23.718256 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11245 04:43:25.707881 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2095 ms)
11246 04:43:25.720880 [0:01:02.100792651] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11247 04:43:25.801559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11248 04:43:25.801894 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11250 04:43:25.818696 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11251 04:43:28.935684 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3228 ms)
11252 04:43:28.949017 [0:01:05.328865090] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11253 04:43:28.999281 [0:01:05.382812028] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11254 04:43:29.036092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11255 04:43:29.036385 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11257 04:43:29.054265 [0:01:05.437758692] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11258 04:43:29.057488 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11259 04:43:29.110580 [0:01:05.493958728] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11260 04:43:29.113693 Camera needs 4 requests, can't test only 1
11261 04:43:29.186922 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11262 04:43:29.264967
11263 04:43:29.346760 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (54 ms)
11264 04:43:29.439539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11265 04:43:29.439881 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11267 04:43:29.455749 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11268 04:43:29.517290 Camera needs 4 requests, can't test only 2
11269 04:43:29.595599 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11270 04:43:29.670099
11271 04:43:29.752772 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (55 ms)
11272 04:43:29.842382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11273 04:43:29.842695 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11275 04:43:29.858899 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11276 04:43:29.911053 Camera needs 4 requests, can't test only 3
11277 04:43:29.993201 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11278 04:43:30.065585
11279 04:43:30.143431 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (56 ms)
11280 04:43:30.198706 [0:01:06.582354529] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11281 04:43:30.232202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11282 04:43:30.232546 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11284 04:43:30.247976 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11285 04:43:30.299594 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1088 ms)
11286 04:43:30.384036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11287 04:43:30.384361 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11289 04:43:30.399527 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11290 04:43:31.740047 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1550 ms)
11291 04:43:31.752768 [0:01:08.132741950] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11292 04:43:31.831806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11293 04:43:31.832140 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11295 04:43:31.848042 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11296 04:43:33.821443 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2082 ms)
11297 04:43:33.834620 [0:01:10.214379255] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11298 04:43:33.917000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11299 04:43:33.917341 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11301 04:43:33.932819 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11302 04:43:36.604720 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2783 ms)
11303 04:43:36.617741 [0:01:12.996650336] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11304 04:43:36.705970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11305 04:43:36.706304 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11307 04:43:36.724155 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11308 04:43:40.783234 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4179 ms)
11309 04:43:40.796338 [0:01:17.176358070] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11310 04:43:40.876792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11311 04:43:40.877146 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11313 04:43:40.893925 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11314 04:43:47.095292 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6312 ms)
11315 04:43:47.108373 [0:01:23.488644926] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11316 04:43:47.194472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11317 04:43:47.194862 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11319 04:43:47.212887 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11320 04:43:56.742177 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9648 ms)
11321 04:43:56.755398 [0:01:33.136384689] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11322 04:43:56.805275 [0:01:33.190193612] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11323 04:43:56.847573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11324 04:43:56.847902 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11326 04:43:56.860888 [0:01:33.245845030] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11327 04:43:56.868395 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11328 04:43:56.913575 [0:01:33.298715589] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11329 04:43:56.932589 Camera needs 4 requests, can't test only 1
11330 04:43:57.020567 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11331 04:43:57.105470
11332 04:43:57.203969 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (54 ms)
11333 04:43:57.317002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11334 04:43:57.317338 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11336 04:43:57.331070 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11337 04:43:57.393319 Camera needs 4 requests, can't test only 2
11338 04:43:57.489061 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11339 04:43:57.575784
11340 04:43:57.681131 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (56 ms)
11341 04:43:57.788487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11342 04:43:57.788830 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11344 04:43:57.804914 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11345 04:43:57.864365 Camera needs 4 requests, can't test only 3
11346 04:43:57.954733 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11347 04:43:58.036861
11348 04:43:58.062073 [0:01:34.447372399] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11349 04:43:58.139138 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (53 ms)
11350 04:43:58.245505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11351 04:43:58.245874 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11353 04:43:58.259673 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11354 04:43:58.324141 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1149 ms)
11355 04:43:58.428393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11356 04:43:58.428740 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11358 04:43:58.442595 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11359 04:43:59.442902 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1385 ms)
11360 04:43:59.452723 [0:01:35.833886826] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11361 04:43:59.546801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11362 04:43:59.547165 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11364 04:43:59.561383 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11365 04:44:01.557025 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2115 ms)
11366 04:44:01.566812 [0:01:37.948492616] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11367 04:44:01.665549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11368 04:44:01.665888 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11370 04:44:01.680639 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11371 04:44:04.242215 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2685 ms)
11372 04:44:04.252198 [0:01:40.633510453] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11373 04:44:04.344707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11374 04:44:04.345059 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11376 04:44:04.358601 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11377 04:44:08.421129 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4179 ms)
11378 04:44:08.431042 [0:01:44.813544187] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11379 04:44:08.511637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11380 04:44:08.511939 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11382 04:44:08.523703 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11383 04:44:14.700199 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6279 ms)
11384 04:44:14.709770 [0:01:51.092979783] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11385 04:44:14.793989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11386 04:44:14.794284 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11388 04:44:14.806573 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11389 04:44:24.314664 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9615 ms)
11390 04:44:24.324443 [0:02:00.707902918] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11391 04:44:24.374801 [0:02:00.762386336] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11392 04:44:24.428372 [0:02:00.815903996] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11393 04:44:24.434822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11394 04:44:24.435112 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11396 04:44:24.447293 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11397 04:44:24.482161 [0:02:00.869760418] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11398 04:44:24.506734 Camera needs 4 requests, can't test only 1
11399 04:44:24.592815 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11400 04:44:24.676252
11401 04:44:24.769319 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (55 ms)
11402 04:44:24.880709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11403 04:44:24.881020 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11405 04:44:24.894683 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11406 04:44:24.950734 Camera needs 4 requests, can't test only 2
11407 04:44:25.035354 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11408 04:44:25.122463
11409 04:44:25.215032 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (54 ms)
11410 04:44:25.311275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11411 04:44:25.311588 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11413 04:44:25.324667 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11414 04:44:25.379772 Camera needs 4 requests, can't test only 3
11415 04:44:25.468753 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11416 04:44:25.550169
11417 04:44:25.567370 [0:02:01.954877080] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11418 04:44:25.646573 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (54 ms)
11419 04:44:25.738901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11420 04:44:25.739199 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11422 04:44:25.755555 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11423 04:44:25.818690 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1085 ms)
11424 04:44:25.908810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11425 04:44:25.909106 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11427 04:44:25.922897 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11428 04:44:26.948536 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1386 ms)
11429 04:44:26.958176 [0:02:03.341194255] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11430 04:44:27.044347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11431 04:44:27.044667 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11433 04:44:27.058771 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11434 04:44:29.029461 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2081 ms)
11435 04:44:29.039505 [0:02:05.422349543] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11436 04:44:29.122754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11437 04:44:29.123040 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11439 04:44:29.135708 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11440 04:44:31.813050 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2783 ms)
11441 04:44:31.823040 [0:02:08.204699354] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11442 04:44:31.916360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11443 04:44:31.916656 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11445 04:44:31.930320 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11446 04:44:35.992282 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4179 ms)
11447 04:44:36.002112 [0:02:12.384279511] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11448 04:44:36.091601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11449 04:44:36.091903 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11451 04:44:36.105816 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11452 04:44:42.270419 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6278 ms)
11453 04:44:42.280144 [0:02:18.662304110] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11454 04:44:42.368478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11455 04:44:42.368818 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11457 04:44:42.382012 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11458 04:44:51.917680 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9647 ms)
11459 04:44:51.927233 [0:02:28.308674654] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11460 04:44:51.977415 [0:02:28.363156422] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11461 04:44:52.015174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11462 04:44:52.015452 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11464 04:44:52.030761 [0:02:28.416069122] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11465 04:44:52.033885 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11466 04:44:52.086763 [0:02:28.472294611] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11467 04:44:52.089853 Camera needs 4 requests, can't test only 1
11468 04:44:52.167321 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11469 04:44:52.243132
11470 04:44:52.330459 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (54 ms)
11471 04:44:52.424541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11472 04:44:52.424858 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11474 04:44:52.438260 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11475 04:44:52.497716 Camera needs 4 requests, can't test only 2
11476 04:44:52.579198 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11477 04:44:52.659731
11478 04:44:52.749831 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (53 ms)
11479 04:44:52.847465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11480 04:44:52.847750 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11482 04:44:52.860138 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11483 04:44:52.914007 Camera needs 4 requests, can't test only 3
11484 04:44:52.991547 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11485 04:44:53.067574
11486 04:44:53.158401 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (56 ms)
11487 04:44:53.168144 [0:02:29.556121014] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11488 04:44:53.260834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11489 04:44:53.261163 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11491 04:44:53.275901 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11492 04:44:53.337114 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1084 ms)
11493 04:44:53.434951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11494 04:44:53.435254 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11496 04:44:53.448642 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11497 04:44:54.555018 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1389 ms)
11498 04:44:54.565145 [0:02:30.946726892] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11499 04:44:54.650124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11500 04:44:54.650428 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11502 04:44:54.662843 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11503 04:44:56.669367 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2114 ms)
11504 04:44:56.678955 [0:02:33.061135304] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11505 04:44:56.773707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11506 04:44:56.773995 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11508 04:44:56.788627 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11509 04:44:59.355738 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2686 ms)
11510 04:44:59.365358 [0:02:35.747083149] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11511 04:44:59.488461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11512 04:44:59.489269 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11514 04:44:59.507962 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11515 04:45:03.567804 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4212 ms)
11516 04:45:03.577363 [0:02:39.959189194] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11517 04:45:03.691330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11518 04:45:03.692089 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11520 04:45:03.709402 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11521 04:45:09.879989 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6313 ms)
11522 04:45:09.889622 [0:02:46.271437546] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11523 04:45:10.009597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11524 04:45:10.010380 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11526 04:45:10.027721 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11527 04:45:19.493303 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9614 ms)
11528 04:45:19.503440 [0:02:55.885545013] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11529 04:45:19.617901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11530 04:45:19.618886 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11532 04:45:19.636422 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11533 04:45:19.755534 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (265 ms)
11534 04:45:19.768907 [0:02:56.151635624] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11535 04:45:19.878851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11536 04:45:19.879565 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11538 04:45:19.899601 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11539 04:45:20.021385 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (266 ms)
11540 04:45:20.034198 [0:02:56.417306669] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11541 04:45:20.147128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11542 04:45:20.148027 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11544 04:45:20.167825 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11545 04:45:20.319830 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (299 ms)
11546 04:45:20.332764 [0:02:56.714555387] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11547 04:45:20.441108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11548 04:45:20.441865 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11550 04:45:20.463372 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11551 04:45:20.748824 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (429 ms)
11552 04:45:20.761943 [0:02:57.144473559] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11553 04:45:20.865646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11554 04:45:20.865931 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11556 04:45:20.882594 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11557 04:45:21.278134 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (529 ms)
11558 04:45:21.291143 [0:02:57.673998304] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11559 04:45:21.399489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11560 04:45:21.400445 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11562 04:45:21.420521 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11563 04:45:21.913348 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (635 ms)
11564 04:45:21.926513 [0:02:58.308234701] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11565 04:45:22.030505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11566 04:45:22.030969 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11568 04:45:22.050740 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11569 04:45:22.810609 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (898 ms)
11570 04:45:22.823823 [0:02:59.206054734] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11571 04:45:22.937447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11572 04:45:22.938276 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11574 04:45:22.958891 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11575 04:45:24.207810 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1396 ms)
11576 04:45:24.220740 [0:03:00.604264612] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11577 04:45:24.343150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11578 04:45:24.343920 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11580 04:45:24.378786 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11581 04:45:26.339097 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2132 ms)
11582 04:45:26.351547 [0:03:02.734868739] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11583 04:45:26.473722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11584 04:45:26.474497 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11586 04:45:26.496563 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11587 04:45:29.568645 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3230 ms)
11588 04:45:29.581451 [0:03:05.964907672] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11589 04:45:29.692776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11590 04:45:29.693514 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11592 04:45:29.715946 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11593 04:45:29.807094 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (235 ms)
11594 04:45:29.817116 [0:03:06.199380115] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11595 04:45:29.931790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11596 04:45:29.932505 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11598 04:45:29.950940 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11599 04:45:30.074880 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (268 ms)
11600 04:45:30.084581 [0:03:06.467607544] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11601 04:45:30.205313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11602 04:45:30.206112 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11604 04:45:30.223314 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11605 04:45:30.374673 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (300 ms)
11606 04:45:30.384541 [0:03:06.766967486] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11607 04:45:30.502345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11608 04:45:30.503064 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11610 04:45:30.521043 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11611 04:45:30.804612 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (430 ms)
11612 04:45:30.814351 [0:03:07.197066035] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11613 04:45:30.925949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11614 04:45:30.926728 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11616 04:45:30.945330 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11617 04:45:31.269313 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (464 ms)
11618 04:45:31.279155 [0:03:07.662089391] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11619 04:45:31.398015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11620 04:45:31.398781 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11622 04:45:31.417594 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11623 04:45:31.967028 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (697 ms)
11624 04:45:31.977162 [0:03:08.361576233] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11625 04:45:32.080771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11626 04:45:32.081561 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11628 04:45:32.098925 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11629 04:45:32.867198 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (900 ms)
11630 04:45:32.876993 [0:03:09.261261601] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11631 04:45:32.997433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11632 04:45:32.998236 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11634 04:45:33.014080 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11635 04:45:34.265537 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1398 ms)
11636 04:45:34.275128 [0:03:10.658562662] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11637 04:45:34.390763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11638 04:45:34.391475 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11640 04:45:34.411258 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11641 04:45:36.394760 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2129 ms)
11642 04:45:36.404728 [0:03:12.787618712] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11643 04:45:36.515491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11644 04:45:36.516291 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11646 04:45:36.534186 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11647 04:45:39.622706 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3228 ms)
11648 04:45:39.632213 [0:03:16.016038790] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11649 04:45:39.725337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11650 04:45:39.725642 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11652 04:45:39.739935 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11653 04:45:39.856534 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (233 ms)
11654 04:45:39.866182 [0:03:16.250197892] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11655 04:45:39.961869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11656 04:45:39.962161 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11658 04:45:39.976486 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11659 04:45:40.125010 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (268 ms)
11660 04:45:40.134689 [0:03:16.519115977] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11661 04:45:40.234530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11662 04:45:40.234826 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11664 04:45:40.249364 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11665 04:45:40.424784 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (300 ms)
11666 04:45:40.434718 [0:03:16.819120650] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11667 04:45:40.531788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11668 04:45:40.532081 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11670 04:45:40.546035 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11671 04:45:40.856851 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (432 ms)
11672 04:45:40.866671 [0:03:17.250538330] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11673 04:45:40.956792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11674 04:45:40.957081 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11676 04:45:40.972052 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11677 04:45:41.386307 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (529 ms)
11678 04:45:41.396324 [0:03:17.779697119] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11679 04:45:41.491524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11680 04:45:41.491855 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11682 04:45:41.505375 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11683 04:45:42.082337 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (696 ms)
11684 04:45:42.092124 [0:03:18.475774357] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11685 04:45:42.180789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11686 04:45:42.181077 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11688 04:45:42.195117 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11689 04:45:42.982718 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (900 ms)
11690 04:45:42.992328 [0:03:19.377735846] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11691 04:45:43.110386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11692 04:45:43.111069 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11694 04:45:43.129370 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11695 04:45:44.380911 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1398 ms)
11696 04:45:44.390436 [0:03:20.773583060] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11697 04:45:44.503557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11698 04:45:44.504440 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11700 04:45:44.522814 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11701 04:45:46.477108 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2097 ms)
11702 04:45:46.486845 [0:03:22.870161192] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11703 04:45:46.600343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11704 04:45:46.600884 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11706 04:45:46.619545 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11707 04:45:49.705824 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3228 ms)
11708 04:45:49.715538 [0:03:26.098939597] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11709 04:45:49.833179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11710 04:45:49.834052 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11712 04:45:49.851462 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11713 04:45:49.938397 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (233 ms)
11714 04:45:49.948195 [0:03:26.331584150] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11715 04:45:50.060486 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11717 04:45:50.063628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11718 04:45:50.080610 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11719 04:45:50.206352 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (268 ms)
11720 04:45:50.216075 [0:03:26.599875473] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11721 04:45:50.307951 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11723 04:45:50.310817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11724 04:45:50.324863 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11725 04:45:50.506116 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (299 ms)
11726 04:45:50.515639 [0:03:26.898883580] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11727 04:45:50.625300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11728 04:45:50.626059 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11730 04:45:50.645355 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11731 04:45:50.936539 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (430 ms)
11732 04:45:50.946061 [0:03:27.329723080] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11733 04:45:51.049299 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11735 04:45:51.052364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11736 04:45:51.069438 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11737 04:45:51.466442 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (530 ms)
11738 04:45:51.475857 [0:03:27.859720436] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11739 04:45:51.586581 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11741 04:45:51.589414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11742 04:45:51.608198 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11743 04:45:52.162742 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (697 ms)
11744 04:45:52.172415 [0:03:28.556103945] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11745 04:45:52.280036 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11747 04:45:52.282560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11748 04:45:52.300346 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11749 04:45:53.061130 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (898 ms)
11750 04:45:53.070905 [0:03:29.453606453] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11751 04:45:53.180032 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11753 04:45:53.182769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11754 04:45:53.201583 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11755 04:45:54.457759 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1396 ms)
11756 04:45:54.467557 [0:03:30.851416436] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11757 04:45:54.575263 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11759 04:45:54.578094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11760 04:45:54.595104 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11761 04:45:56.553286 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2097 ms)
11762 04:45:56.563099 [0:03:32.947802261] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11763 04:45:56.655888 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11765 04:45:56.659092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11766 04:45:56.673265 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11767 04:45:59.783198 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3230 ms)
11768 04:45:59.876785 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11770 04:45:59.879878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11771 04:45:59.893878 [----------] 120 tests from CaptureTests/SingleStream (188223 ms total)
11772 04:45:59.974924
11773 04:46:00.063848 [----------] Global test environment tear-down
11774 04:46:00.149174 [==========] 120 tests from 1 test suite ran. (188224 ms total)
11775 04:46:00.236368 <LAVA_SIGNAL_TESTSET STOP>
11776 04:46:00.236717 Received signal: <TESTSET> STOP
11777 04:46:00.236805 Closing test_set CaptureTests/SingleStream
11778 04:46:00.246839 + set +x
11779 04:46:00.250124 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 12699810_1.6.2.3.1>
11780 04:46:00.250377 Received signal: <ENDRUN> 0_lc-compliance 12699810_1.6.2.3.1
11781 04:46:00.250458 Ending use of test pattern.
11782 04:46:00.250519 Ending test lava.0_lc-compliance (12699810_1.6.2.3.1), duration 189.95
11784 04:46:00.253297 <LAVA_TEST_RUNNER EXIT>
11785 04:46:00.253512 ok: lava_test_shell seems to have completed
11786 04:46:00.255409 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11787 04:46:00.255585 end: 3.1 lava-test-shell (duration 00:03:11) [common]
11788 04:46:00.255672 end: 3 lava-test-retry (duration 00:03:11) [common]
11789 04:46:00.255760 start: 4 finalize (timeout 00:10:00) [common]
11790 04:46:00.255846 start: 4.1 power-off (timeout 00:00:30) [common]
11791 04:46:00.255996 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11792 04:46:00.331851 >> Command sent successfully.
11793 04:46:00.334897 Returned 0 in 0 seconds
11794 04:46:00.435285 end: 4.1 power-off (duration 00:00:00) [common]
11796 04:46:00.435619 start: 4.2 read-feedback (timeout 00:10:00) [common]
11797 04:46:00.435889 Listened to connection for namespace 'common' for up to 1s
11798 04:46:01.436846 Finalising connection for namespace 'common'
11799 04:46:01.437017 Disconnecting from shell: Finalise
11800 04:46:01.437098 / #
11801 04:46:01.537444 end: 4.2 read-feedback (duration 00:00:01) [common]
11802 04:46:01.537663 end: 4 finalize (duration 00:00:01) [common]
11803 04:46:01.537820 Cleaning after the job
11804 04:46:01.537980 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/ramdisk
11805 04:46:01.540554 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/kernel
11806 04:46:01.553712 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/dtb
11807 04:46:01.553911 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/nfsrootfs
11808 04:46:01.610645 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699810/tftp-deploy-swjqm2qw/modules
11809 04:46:01.617725 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12699810
11810 04:46:01.939807 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12699810
11811 04:46:01.939992 Job finished correctly