Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 35
- Kernel Errors: 28
1 04:46:35.873393 lava-dispatcher, installed at version: 2023.10
2 04:46:35.873630 start: 0 validate
3 04:46:35.873827 Start time: 2024-02-04 04:46:35.873819+00:00 (UTC)
4 04:46:35.873956 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:46:35.874098 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 04:46:36.148534 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:46:36.148714 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:46:36.415070 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:46:36.415246 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:46:36.681374 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:46:36.681622 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 04:46:36.940765 validate duration: 1.07
14 04:46:36.941046 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:46:36.941140 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:46:36.941227 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:46:36.941378 Not decompressing ramdisk as can be used compressed.
18 04:46:36.941549 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 04:46:36.941667 saving as /var/lib/lava/dispatcher/tmp/12699853/tftp-deploy-46nymtka/ramdisk/rootfs.cpio.gz
20 04:46:36.941769 total size: 84918747 (80 MB)
21 04:46:36.943259 progress 0 % (0 MB)
22 04:46:36.965543 progress 5 % (4 MB)
23 04:46:36.987189 progress 10 % (8 MB)
24 04:46:37.009677 progress 15 % (12 MB)
25 04:46:37.032375 progress 20 % (16 MB)
26 04:46:37.054723 progress 25 % (20 MB)
27 04:46:37.076938 progress 30 % (24 MB)
28 04:46:37.098924 progress 35 % (28 MB)
29 04:46:37.120729 progress 40 % (32 MB)
30 04:46:37.142733 progress 45 % (36 MB)
31 04:46:37.165221 progress 50 % (40 MB)
32 04:46:37.187739 progress 55 % (44 MB)
33 04:46:37.209581 progress 60 % (48 MB)
34 04:46:37.231639 progress 65 % (52 MB)
35 04:46:37.254146 progress 70 % (56 MB)
36 04:46:37.276184 progress 75 % (60 MB)
37 04:46:37.298402 progress 80 % (64 MB)
38 04:46:37.320079 progress 85 % (68 MB)
39 04:46:37.342233 progress 90 % (72 MB)
40 04:46:37.364080 progress 95 % (76 MB)
41 04:46:37.385871 progress 100 % (80 MB)
42 04:46:37.386104 80 MB downloaded in 0.44 s (182.26 MB/s)
43 04:46:37.386268 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:46:37.386511 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:46:37.386596 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:46:37.386680 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:46:37.386820 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 04:46:37.386892 saving as /var/lib/lava/dispatcher/tmp/12699853/tftp-deploy-46nymtka/kernel/Image
50 04:46:37.386953 total size: 51597824 (49 MB)
51 04:46:37.387014 No compression specified
52 04:46:37.388143 progress 0 % (0 MB)
53 04:46:37.401380 progress 5 % (2 MB)
54 04:46:37.414880 progress 10 % (4 MB)
55 04:46:37.428516 progress 15 % (7 MB)
56 04:46:37.441800 progress 20 % (9 MB)
57 04:46:37.455204 progress 25 % (12 MB)
58 04:46:37.468551 progress 30 % (14 MB)
59 04:46:37.481996 progress 35 % (17 MB)
60 04:46:37.495265 progress 40 % (19 MB)
61 04:46:37.509125 progress 45 % (22 MB)
62 04:46:37.523143 progress 50 % (24 MB)
63 04:46:37.537015 progress 55 % (27 MB)
64 04:46:37.551769 progress 60 % (29 MB)
65 04:46:37.566326 progress 65 % (32 MB)
66 04:46:37.580277 progress 70 % (34 MB)
67 04:46:37.594471 progress 75 % (36 MB)
68 04:46:37.607723 progress 80 % (39 MB)
69 04:46:37.620937 progress 85 % (41 MB)
70 04:46:37.634410 progress 90 % (44 MB)
71 04:46:37.647586 progress 95 % (46 MB)
72 04:46:37.660753 progress 100 % (49 MB)
73 04:46:37.660983 49 MB downloaded in 0.27 s (179.57 MB/s)
74 04:46:37.661136 end: 1.2.1 http-download (duration 00:00:00) [common]
76 04:46:37.661370 end: 1.2 download-retry (duration 00:00:00) [common]
77 04:46:37.661455 start: 1.3 download-retry (timeout 00:09:59) [common]
78 04:46:37.661592 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 04:46:37.661733 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 04:46:37.661803 saving as /var/lib/lava/dispatcher/tmp/12699853/tftp-deploy-46nymtka/dtb/mt8192-asurada-spherion-r0.dtb
81 04:46:37.661863 total size: 47278 (0 MB)
82 04:46:37.661924 No compression specified
83 04:46:37.663052 progress 69 % (0 MB)
84 04:46:37.663328 progress 100 % (0 MB)
85 04:46:37.663483 0 MB downloaded in 0.00 s (27.87 MB/s)
86 04:46:37.663604 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:46:37.663824 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:46:37.663911 start: 1.4 download-retry (timeout 00:09:59) [common]
90 04:46:37.663992 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 04:46:37.664107 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 04:46:37.664178 saving as /var/lib/lava/dispatcher/tmp/12699853/tftp-deploy-46nymtka/modules/modules.tar
93 04:46:37.664239 total size: 8633524 (8 MB)
94 04:46:37.664300 Using unxz to decompress xz
95 04:46:37.668328 progress 0 % (0 MB)
96 04:46:37.689282 progress 5 % (0 MB)
97 04:46:37.712725 progress 10 % (0 MB)
98 04:46:37.735990 progress 15 % (1 MB)
99 04:46:37.759233 progress 20 % (1 MB)
100 04:46:37.782880 progress 25 % (2 MB)
101 04:46:37.810055 progress 30 % (2 MB)
102 04:46:37.834195 progress 35 % (2 MB)
103 04:46:37.857327 progress 40 % (3 MB)
104 04:46:37.881271 progress 45 % (3 MB)
105 04:46:37.906246 progress 50 % (4 MB)
106 04:46:37.930495 progress 55 % (4 MB)
107 04:46:37.956688 progress 60 % (4 MB)
108 04:46:37.981861 progress 65 % (5 MB)
109 04:46:38.006335 progress 70 % (5 MB)
110 04:46:38.029562 progress 75 % (6 MB)
111 04:46:38.056087 progress 80 % (6 MB)
112 04:46:38.081051 progress 85 % (7 MB)
113 04:46:38.107213 progress 90 % (7 MB)
114 04:46:38.136502 progress 95 % (7 MB)
115 04:46:38.163914 progress 100 % (8 MB)
116 04:46:38.169242 8 MB downloaded in 0.50 s (16.30 MB/s)
117 04:46:38.169570 end: 1.4.1 http-download (duration 00:00:01) [common]
119 04:46:38.169830 end: 1.4 download-retry (duration 00:00:01) [common]
120 04:46:38.169920 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 04:46:38.170012 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 04:46:38.170094 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:46:38.170179 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 04:46:38.170406 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8
125 04:46:38.170540 makedir: /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin
126 04:46:38.170643 makedir: /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/tests
127 04:46:38.170740 makedir: /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/results
128 04:46:38.170888 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-add-keys
129 04:46:38.171032 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-add-sources
130 04:46:38.171160 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-background-process-start
131 04:46:38.171285 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-background-process-stop
132 04:46:38.171408 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-common-functions
133 04:46:38.171531 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-echo-ipv4
134 04:46:38.171652 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-install-packages
135 04:46:38.171772 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-installed-packages
136 04:46:38.171897 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-os-build
137 04:46:38.172018 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-probe-channel
138 04:46:38.172141 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-probe-ip
139 04:46:38.172261 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-target-ip
140 04:46:38.172390 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-target-mac
141 04:46:38.172513 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-target-storage
142 04:46:38.172640 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-test-case
143 04:46:38.172762 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-test-event
144 04:46:38.172882 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-test-feedback
145 04:46:38.173003 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-test-raise
146 04:46:38.173126 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-test-reference
147 04:46:38.173246 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-test-runner
148 04:46:38.173368 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-test-set
149 04:46:38.173531 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-test-shell
150 04:46:38.173660 Updating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-install-packages (oe)
151 04:46:38.173808 Updating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/bin/lava-installed-packages (oe)
152 04:46:38.173930 Creating /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/environment
153 04:46:38.174029 LAVA metadata
154 04:46:38.174102 - LAVA_JOB_ID=12699853
155 04:46:38.174166 - LAVA_DISPATCHER_IP=192.168.201.1
156 04:46:38.174263 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 04:46:38.174328 skipped lava-vland-overlay
158 04:46:38.174400 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 04:46:38.174476 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 04:46:38.174540 skipped lava-multinode-overlay
161 04:46:38.174613 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 04:46:38.174692 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 04:46:38.174768 Loading test definitions
164 04:46:38.174854 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 04:46:38.174925 Using /lava-12699853 at stage 0
166 04:46:38.175029 Fetching tests from https://github.com/kernelci/kernelci-core
167 04:46:38.175110 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/0/tests/0_sleep'
168 04:46:38.788546 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/0/tests/0_sleep
169 04:46:38.789913 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 04:46:38.790315 uuid=12699853_1.5.2.3.1 testdef=None
171 04:46:38.790460 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 04:46:38.790721 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 04:46:38.791282 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 04:46:38.791507 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 04:46:38.792208 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 04:46:38.792446 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 04:46:38.793106 runner path: /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/0/tests/0_sleep test_uuid 12699853_1.5.2.3.1
181 04:46:38.793192 sleep_params='mem'
182 04:46:38.793334 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 04:46:38.793563 Creating lava-test-runner.conf files
185 04:46:38.793629 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12699853/lava-overlay-krukbm_8/lava-12699853/0 for stage 0
186 04:46:38.793723 - 0_sleep
187 04:46:38.793826 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 04:46:38.793912 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 04:46:38.927849 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 04:46:38.928003 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 04:46:38.928095 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 04:46:38.928190 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 04:46:38.928275 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 04:46:41.360759 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 04:46:41.361168 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
196 04:46:41.361286 extracting modules file /var/lib/lava/dispatcher/tmp/12699853/tftp-deploy-46nymtka/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699853/extract-overlay-ramdisk-dss9jpz0/ramdisk
197 04:46:41.586020 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 04:46:41.586194 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 04:46:41.586290 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699853/compress-overlay-2l5f04kf/overlay-1.5.2.4.tar.gz to ramdisk
200 04:46:41.586362 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699853/compress-overlay-2l5f04kf/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12699853/extract-overlay-ramdisk-dss9jpz0/ramdisk
201 04:46:41.685295 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 04:46:41.685451 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 04:46:41.685593 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 04:46:41.685681 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 04:46:41.685758 Building ramdisk /var/lib/lava/dispatcher/tmp/12699853/extract-overlay-ramdisk-dss9jpz0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12699853/extract-overlay-ramdisk-dss9jpz0/ramdisk
206 04:46:43.198893 >> 563705 blocks
207 04:46:52.945615 rename /var/lib/lava/dispatcher/tmp/12699853/extract-overlay-ramdisk-dss9jpz0/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12699853/tftp-deploy-46nymtka/ramdisk/ramdisk.cpio.gz
208 04:46:52.946084 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 04:46:52.946205 start: 1.5.8 prepare-kernel (timeout 00:09:44) [common]
210 04:46:52.946306 start: 1.5.8.1 prepare-fit (timeout 00:09:44) [common]
211 04:46:52.946416 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12699853/tftp-deploy-46nymtka/kernel/Image'
212 04:47:05.551749 Returned 0 in 12 seconds
213 04:47:05.652390 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12699853/tftp-deploy-46nymtka/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12699853/tftp-deploy-46nymtka/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12699853/tftp-deploy-46nymtka/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12699853/tftp-deploy-46nymtka/kernel/image.itb
214 04:47:07.007147 output: FIT description: Kernel Image image with one or more FDT blobs
215 04:47:07.007540 output: Created: Sun Feb 4 04:47:06 2024
216 04:47:07.007616 output: Image 0 (kernel-1)
217 04:47:07.007677 output: Description:
218 04:47:07.007735 output: Created: Sun Feb 4 04:47:06 2024
219 04:47:07.007793 output: Type: Kernel Image
220 04:47:07.007877 output: Compression: lzma compressed
221 04:47:07.007936 output: Data Size: 12048508 Bytes = 11766.12 KiB = 11.49 MiB
222 04:47:07.007995 output: Architecture: AArch64
223 04:47:07.008065 output: OS: Linux
224 04:47:07.008125 output: Load Address: 0x00000000
225 04:47:07.008182 output: Entry Point: 0x00000000
226 04:47:07.008237 output: Hash algo: crc32
227 04:47:07.008296 output: Hash value: 3b31d50c
228 04:47:07.008368 output: Image 1 (fdt-1)
229 04:47:07.008453 output: Description: mt8192-asurada-spherion-r0
230 04:47:07.008519 output: Created: Sun Feb 4 04:47:06 2024
231 04:47:07.008572 output: Type: Flat Device Tree
232 04:47:07.008625 output: Compression: uncompressed
233 04:47:07.008678 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 04:47:07.008731 output: Architecture: AArch64
235 04:47:07.008783 output: Hash algo: crc32
236 04:47:07.008835 output: Hash value: cc4352de
237 04:47:07.008887 output: Image 2 (ramdisk-1)
238 04:47:07.008938 output: Description: unavailable
239 04:47:07.008990 output: Created: Sun Feb 4 04:47:06 2024
240 04:47:07.009042 output: Type: RAMDisk Image
241 04:47:07.009095 output: Compression: Unknown Compression
242 04:47:07.009147 output: Data Size: 98333092 Bytes = 96028.41 KiB = 93.78 MiB
243 04:47:07.009199 output: Architecture: AArch64
244 04:47:07.009251 output: OS: Linux
245 04:47:07.009309 output: Load Address: unavailable
246 04:47:07.009447 output: Entry Point: unavailable
247 04:47:07.009537 output: Hash algo: crc32
248 04:47:07.009592 output: Hash value: 65ed240e
249 04:47:07.009673 output: Default Configuration: 'conf-1'
250 04:47:07.009727 output: Configuration 0 (conf-1)
251 04:47:07.009809 output: Description: mt8192-asurada-spherion-r0
252 04:47:07.009875 output: Kernel: kernel-1
253 04:47:07.009927 output: Init Ramdisk: ramdisk-1
254 04:47:07.009979 output: FDT: fdt-1
255 04:47:07.010031 output: Loadables: kernel-1
256 04:47:07.010083 output:
257 04:47:07.010280 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 04:47:07.010370 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 04:47:07.010470 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
260 04:47:07.010566 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:30) [common]
261 04:47:07.010644 No LXC device requested
262 04:47:07.010721 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 04:47:07.010804 start: 1.7 deploy-device-env (timeout 00:09:30) [common]
264 04:47:07.010879 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 04:47:07.010947 Checking files for TFTP limit of 4294967296 bytes.
266 04:47:07.011433 end: 1 tftp-deploy (duration 00:00:30) [common]
267 04:47:07.011585 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 04:47:07.011732 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 04:47:07.011870 substitutions:
270 04:47:07.011935 - {DTB}: 12699853/tftp-deploy-46nymtka/dtb/mt8192-asurada-spherion-r0.dtb
271 04:47:07.011998 - {INITRD}: 12699853/tftp-deploy-46nymtka/ramdisk/ramdisk.cpio.gz
272 04:47:07.012056 - {KERNEL}: 12699853/tftp-deploy-46nymtka/kernel/Image
273 04:47:07.012113 - {LAVA_MAC}: None
274 04:47:07.012169 - {PRESEED_CONFIG}: None
275 04:47:07.012224 - {PRESEED_LOCAL}: None
276 04:47:07.012278 - {RAMDISK}: 12699853/tftp-deploy-46nymtka/ramdisk/ramdisk.cpio.gz
277 04:47:07.012332 - {ROOT_PART}: None
278 04:47:07.012385 - {ROOT}: None
279 04:47:07.012437 - {SERVER_IP}: 192.168.201.1
280 04:47:07.012490 - {TEE}: None
281 04:47:07.012542 Parsed boot commands:
282 04:47:07.012608 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 04:47:07.012787 Parsed boot commands: tftpboot 192.168.201.1 12699853/tftp-deploy-46nymtka/kernel/image.itb 12699853/tftp-deploy-46nymtka/kernel/cmdline
284 04:47:07.012876 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 04:47:07.012963 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 04:47:07.013057 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 04:47:07.013141 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 04:47:07.013211 Not connected, no need to disconnect.
289 04:47:07.013284 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 04:47:07.013364 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 04:47:07.013429 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
292 04:47:07.017424 Setting prompt string to ['lava-test: # ']
293 04:47:07.017828 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 04:47:07.017935 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 04:47:07.018030 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 04:47:07.018117 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 04:47:07.018307 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
298 04:47:12.151754 >> Command sent successfully.
299 04:47:12.154618 Returned 0 in 5 seconds
300 04:47:12.255020 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 04:47:12.255346 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 04:47:12.255451 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 04:47:12.255541 Setting prompt string to 'Starting depthcharge on Spherion...'
305 04:47:12.255613 Changing prompt to 'Starting depthcharge on Spherion...'
306 04:47:12.255692 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 04:47:12.255975 [Enter `^Ec?' for help]
308 04:47:12.427122
309 04:47:12.427411
310 04:47:12.427642 F0: 102B 0000
311 04:47:12.427859
312 04:47:12.428065 F3: 1001 0000 [0200]
313 04:47:12.428264
314 04:47:12.430799 F3: 1001 0000
315 04:47:12.431052
316 04:47:12.431310 F7: 102D 0000
317 04:47:12.431555
318 04:47:12.433884 F1: 0000 0000
319 04:47:12.434139
320 04:47:12.434405 V0: 0000 0000 [0001]
321 04:47:12.434657
322 04:47:12.437147 00: 0007 8000
323 04:47:12.437454
324 04:47:12.437719 01: 0000 0000
325 04:47:12.437960
326 04:47:12.440447 BP: 0C00 0209 [0000]
327 04:47:12.440737
328 04:47:12.441036 G0: 1182 0000
329 04:47:12.441272
330 04:47:12.441570 EC: 0000 0021 [4000]
331 04:47:12.444573
332 04:47:12.444814 S7: 0000 0000 [0000]
333 04:47:12.444899
334 04:47:12.444977 CC: 0000 0000 [0001]
335 04:47:12.445036
336 04:47:12.447984 T0: 0000 0040 [010F]
337 04:47:12.448077
338 04:47:12.448166 Jump to BL
339 04:47:12.448249
340 04:47:12.474203
341 04:47:12.474293
342 04:47:12.474379
343 04:47:12.480796 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 04:47:12.484434 ARM64: Exception handlers installed.
345 04:47:12.487845 ARM64: Testing exception
346 04:47:12.491315 ARM64: Done test exception
347 04:47:12.498210 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 04:47:12.508018 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 04:47:12.514820 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 04:47:12.524727 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 04:47:12.531490 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 04:47:12.541611 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 04:47:12.552241 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 04:47:12.558953 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 04:47:12.576611 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 04:47:12.580075 WDT: Last reset was cold boot
357 04:47:12.583494 SPI1(PAD0) initialized at 2873684 Hz
358 04:47:12.586930 SPI5(PAD0) initialized at 992727 Hz
359 04:47:12.590341 VBOOT: Loading verstage.
360 04:47:12.596719 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 04:47:12.599899 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 04:47:12.603310 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 04:47:12.606840 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 04:47:12.614114 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 04:47:12.620951 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 04:47:12.631620 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
367 04:47:12.631700
368 04:47:12.631765
369 04:47:12.641784 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 04:47:12.645048 ARM64: Exception handlers installed.
371 04:47:12.648142 ARM64: Testing exception
372 04:47:12.648215 ARM64: Done test exception
373 04:47:12.655891 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 04:47:12.659057 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 04:47:12.673061 Probing TPM: . done!
376 04:47:12.673140 TPM ready after 0 ms
377 04:47:12.679557 Connected to device vid:did:rid of 1ae0:0028:00
378 04:47:12.686199 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 04:47:12.726302 Initialized TPM device CR50 revision 0
380 04:47:12.738295 tlcl_send_startup: Startup return code is 0
381 04:47:12.738410 TPM: setup succeeded
382 04:47:12.750245 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 04:47:12.758589 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 04:47:12.769985 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 04:47:12.780116 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 04:47:12.783394 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 04:47:12.787307 in-header: 03 07 00 00 08 00 00 00
388 04:47:12.790952 in-data: aa e4 47 04 13 02 00 00
389 04:47:12.794422 Chrome EC: UHEPI supported
390 04:47:12.801316 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 04:47:12.805212 in-header: 03 9d 00 00 08 00 00 00
392 04:47:12.808750 in-data: 10 20 20 08 00 00 00 00
393 04:47:12.808835 Phase 1
394 04:47:12.812607 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 04:47:12.819713 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 04:47:12.827053 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 04:47:12.830489 Recovery requested (1009000e)
398 04:47:12.836365 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 04:47:12.841721 tlcl_extend: response is 0
400 04:47:12.849567 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 04:47:12.854908 tlcl_extend: response is 0
402 04:47:12.861703 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 04:47:12.882995 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
404 04:47:12.890431 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 04:47:12.890541
406 04:47:12.890630
407 04:47:12.897705 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 04:47:12.901217 ARM64: Exception handlers installed.
409 04:47:12.904606 ARM64: Testing exception
410 04:47:12.907874 ARM64: Done test exception
411 04:47:12.928129 pmic_efuse_setting: Set efuses in 11 msecs
412 04:47:12.931596 pmwrap_interface_init: Select PMIF_VLD_RDY
413 04:47:12.939246 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 04:47:12.942782 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 04:47:12.946642 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 04:47:12.950121 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 04:47:12.957594 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 04:47:12.961029 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 04:47:12.964790 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 04:47:12.972070 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 04:47:12.975535 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 04:47:12.978602 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 04:47:12.985220 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 04:47:12.988761 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 04:47:12.991670 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 04:47:12.999159 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 04:47:13.005861 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 04:47:13.012631 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 04:47:13.015854 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 04:47:13.022635 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 04:47:13.029417 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 04:47:13.033185 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 04:47:13.040555 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 04:47:13.044296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 04:47:13.050931 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 04:47:13.058437 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 04:47:13.061547 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 04:47:13.068328 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 04:47:13.071725 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 04:47:13.075708 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 04:47:13.082562 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 04:47:13.085890 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 04:47:13.092674 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 04:47:13.096590 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 04:47:13.100158 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 04:47:13.107251 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 04:47:13.111109 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 04:47:13.118555 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 04:47:13.121989 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 04:47:13.125318 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 04:47:13.131903 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 04:47:13.135309 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 04:47:13.138710 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 04:47:13.145328 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 04:47:13.148343 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 04:47:13.151797 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 04:47:13.158740 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 04:47:13.161882 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 04:47:13.165414 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 04:47:13.168580 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 04:47:13.175307 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 04:47:13.178825 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 04:47:13.182044 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 04:47:13.191807 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 04:47:13.198503 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 04:47:13.202107 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 04:47:13.211974 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 04:47:13.218880 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 04:47:13.225339 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 04:47:13.228993 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 04:47:13.232105 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 04:47:13.240513 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x27
473 04:47:13.246969 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 04:47:13.250590 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
475 04:47:13.257154 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 04:47:13.264712 [RTC]rtc_get_frequency_meter,154: input=15, output=793
477 04:47:13.268138 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 04:47:13.274913 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 04:47:13.278396 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 04:47:13.281601 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 04:47:13.284867 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 04:47:13.288250 ADC[4]: Raw value=895561 ID=7
483 04:47:13.291556 ADC[3]: Raw value=213440 ID=1
484 04:47:13.294740 RAM Code: 0x71
485 04:47:13.298389 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 04:47:13.301587 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 04:47:13.311650 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 04:47:13.318939 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 04:47:13.322026 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 04:47:13.325714 in-header: 03 07 00 00 08 00 00 00
491 04:47:13.329107 in-data: aa e4 47 04 13 02 00 00
492 04:47:13.332081 Chrome EC: UHEPI supported
493 04:47:13.335665 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 04:47:13.340033 in-header: 03 d5 00 00 08 00 00 00
495 04:47:13.343713 in-data: 98 20 60 08 00 00 00 00
496 04:47:13.347451 MRC: failed to locate region type 0.
497 04:47:13.354822 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 04:47:13.358240 DRAM-K: Running full calibration
499 04:47:13.361637 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 04:47:13.365115 header.status = 0x0
501 04:47:13.368590 header.version = 0x6 (expected: 0x6)
502 04:47:13.372514 header.size = 0xd00 (expected: 0xd00)
503 04:47:13.372598 header.flags = 0x0
504 04:47:13.379155 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 04:47:13.397211 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 04:47:13.403610 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 04:47:13.406994 dram_init: ddr_geometry: 2
508 04:47:13.410580 [EMI] MDL number = 2
509 04:47:13.410664 [EMI] Get MDL freq = 0
510 04:47:13.413616 dram_init: ddr_type: 0
511 04:47:13.413700 is_discrete_lpddr4: 1
512 04:47:13.417181 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 04:47:13.417265
514 04:47:13.417332
515 04:47:13.420417 [Bian_co] ETT version 0.0.0.1
516 04:47:13.427048 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 04:47:13.427136
518 04:47:13.430641 dramc_set_vcore_voltage set vcore to 650000
519 04:47:13.430727 Read voltage for 800, 4
520 04:47:13.433847 Vio18 = 0
521 04:47:13.433933 Vcore = 650000
522 04:47:13.434021 Vdram = 0
523 04:47:13.437218 Vddq = 0
524 04:47:13.437304 Vmddr = 0
525 04:47:13.440521 dram_init: config_dvfs: 1
526 04:47:13.443815 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 04:47:13.450849 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 04:47:13.453844 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
529 04:47:13.457303 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
530 04:47:13.460558 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 04:47:13.463802 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 04:47:13.467127 MEM_TYPE=3, freq_sel=18
533 04:47:13.470375 sv_algorithm_assistance_LP4_1600
534 04:47:13.473800 ============ PULL DRAM RESETB DOWN ============
535 04:47:13.477510 ========== PULL DRAM RESETB DOWN end =========
536 04:47:13.484635 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 04:47:13.488519 ===================================
538 04:47:13.488605 LPDDR4 DRAM CONFIGURATION
539 04:47:13.491884 ===================================
540 04:47:13.496256 EX_ROW_EN[0] = 0x0
541 04:47:13.496343 EX_ROW_EN[1] = 0x0
542 04:47:13.500009 LP4Y_EN = 0x0
543 04:47:13.500098 WORK_FSP = 0x0
544 04:47:13.500165 WL = 0x2
545 04:47:13.503667 RL = 0x2
546 04:47:13.503751 BL = 0x2
547 04:47:13.507401 RPST = 0x0
548 04:47:13.507484 RD_PRE = 0x0
549 04:47:13.511389 WR_PRE = 0x1
550 04:47:13.511502 WR_PST = 0x0
551 04:47:13.514877 DBI_WR = 0x0
552 04:47:13.514960 DBI_RD = 0x0
553 04:47:13.518219 OTF = 0x1
554 04:47:13.522092 ===================================
555 04:47:13.522175 ===================================
556 04:47:13.526017 ANA top config
557 04:47:13.529380 ===================================
558 04:47:13.529464 DLL_ASYNC_EN = 0
559 04:47:13.533551 ALL_SLAVE_EN = 1
560 04:47:13.536997 NEW_RANK_MODE = 1
561 04:47:13.537081 DLL_IDLE_MODE = 1
562 04:47:13.540545 LP45_APHY_COMB_EN = 1
563 04:47:13.544446 TX_ODT_DIS = 1
564 04:47:13.544529 NEW_8X_MODE = 1
565 04:47:13.548428 ===================================
566 04:47:13.551858 ===================================
567 04:47:13.555713 data_rate = 1600
568 04:47:13.559871 CKR = 1
569 04:47:13.559954 DQ_P2S_RATIO = 8
570 04:47:13.563177 ===================================
571 04:47:13.566713 CA_P2S_RATIO = 8
572 04:47:13.570246 DQ_CA_OPEN = 0
573 04:47:13.573346 DQ_SEMI_OPEN = 0
574 04:47:13.577016 CA_SEMI_OPEN = 0
575 04:47:13.577129 CA_FULL_RATE = 0
576 04:47:13.580228 DQ_CKDIV4_EN = 1
577 04:47:13.583549 CA_CKDIV4_EN = 1
578 04:47:13.586609 CA_PREDIV_EN = 0
579 04:47:13.590197 PH8_DLY = 0
580 04:47:13.593422 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 04:47:13.593542 DQ_AAMCK_DIV = 4
582 04:47:13.596709 CA_AAMCK_DIV = 4
583 04:47:13.600257 CA_ADMCK_DIV = 4
584 04:47:13.603422 DQ_TRACK_CA_EN = 0
585 04:47:13.606874 CA_PICK = 800
586 04:47:13.610213 CA_MCKIO = 800
587 04:47:13.610316 MCKIO_SEMI = 0
588 04:47:13.613443 PLL_FREQ = 3068
589 04:47:13.616986 DQ_UI_PI_RATIO = 32
590 04:47:13.620483 CA_UI_PI_RATIO = 0
591 04:47:13.623283 ===================================
592 04:47:13.626737 ===================================
593 04:47:13.630196 memory_type:LPDDR4
594 04:47:13.630400 GP_NUM : 10
595 04:47:13.633750 SRAM_EN : 1
596 04:47:13.636890 MD32_EN : 0
597 04:47:13.640190 ===================================
598 04:47:13.640378 [ANA_INIT] >>>>>>>>>>>>>>
599 04:47:13.643696 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 04:47:13.646838 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 04:47:13.650304 ===================================
602 04:47:13.653644 data_rate = 1600,PCW = 0X7600
603 04:47:13.657005 ===================================
604 04:47:13.660187 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 04:47:13.666971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 04:47:13.670662 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 04:47:13.677214 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 04:47:13.680908 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 04:47:13.684158 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 04:47:13.684242 [ANA_INIT] flow start
611 04:47:13.687378 [ANA_INIT] PLL >>>>>>>>
612 04:47:13.687462 [ANA_INIT] PLL <<<<<<<<
613 04:47:13.691722 [ANA_INIT] MIDPI >>>>>>>>
614 04:47:13.695219 [ANA_INIT] MIDPI <<<<<<<<
615 04:47:13.695303 [ANA_INIT] DLL >>>>>>>>
616 04:47:13.698957 [ANA_INIT] flow end
617 04:47:13.702194 ============ LP4 DIFF to SE enter ============
618 04:47:13.706897 ============ LP4 DIFF to SE exit ============
619 04:47:13.710288 [ANA_INIT] <<<<<<<<<<<<<
620 04:47:13.713535 [Flow] Enable top DCM control >>>>>
621 04:47:13.713640 [Flow] Enable top DCM control <<<<<
622 04:47:13.717631 Enable DLL master slave shuffle
623 04:47:13.725122 ==============================================================
624 04:47:13.725218 Gating Mode config
625 04:47:13.731683 ==============================================================
626 04:47:13.731787 Config description:
627 04:47:13.741757 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 04:47:13.748633 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 04:47:13.755238 SELPH_MODE 0: By rank 1: By Phase
630 04:47:13.758246 ==============================================================
631 04:47:13.761649 GAT_TRACK_EN = 1
632 04:47:13.765449 RX_GATING_MODE = 2
633 04:47:13.768434 RX_GATING_TRACK_MODE = 2
634 04:47:13.771655 SELPH_MODE = 1
635 04:47:13.775219 PICG_EARLY_EN = 1
636 04:47:13.778295 VALID_LAT_VALUE = 1
637 04:47:13.781494 ==============================================================
638 04:47:13.785087 Enter into Gating configuration >>>>
639 04:47:13.788365 Exit from Gating configuration <<<<
640 04:47:13.791721 Enter into DVFS_PRE_config >>>>>
641 04:47:13.805200 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 04:47:13.808381 Exit from DVFS_PRE_config <<<<<
643 04:47:13.812152 Enter into PICG configuration >>>>
644 04:47:13.812236 Exit from PICG configuration <<<<
645 04:47:13.815048 [RX_INPUT] configuration >>>>>
646 04:47:13.818363 [RX_INPUT] configuration <<<<<
647 04:47:13.824996 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 04:47:13.828039 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 04:47:13.834939 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 04:47:13.841573 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 04:47:13.848128 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 04:47:13.854758 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 04:47:13.857870 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 04:47:13.861667 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 04:47:13.864790 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 04:47:13.871263 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 04:47:13.874873 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 04:47:13.877894 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 04:47:13.881643 ===================================
660 04:47:13.885163 LPDDR4 DRAM CONFIGURATION
661 04:47:13.888224 ===================================
662 04:47:13.891840 EX_ROW_EN[0] = 0x0
663 04:47:13.892269 EX_ROW_EN[1] = 0x0
664 04:47:13.895013 LP4Y_EN = 0x0
665 04:47:13.895448 WORK_FSP = 0x0
666 04:47:13.898503 WL = 0x2
667 04:47:13.899020 RL = 0x2
668 04:47:13.901843 BL = 0x2
669 04:47:13.902275 RPST = 0x0
670 04:47:13.904996 RD_PRE = 0x0
671 04:47:13.905530 WR_PRE = 0x1
672 04:47:13.908218 WR_PST = 0x0
673 04:47:13.908653 DBI_WR = 0x0
674 04:47:13.911827 DBI_RD = 0x0
675 04:47:13.912543 OTF = 0x1
676 04:47:13.915024 ===================================
677 04:47:13.921583 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 04:47:13.925246 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 04:47:13.928143 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 04:47:13.931789 ===================================
681 04:47:13.934986 LPDDR4 DRAM CONFIGURATION
682 04:47:13.938209 ===================================
683 04:47:13.938721 EX_ROW_EN[0] = 0x10
684 04:47:13.941334 EX_ROW_EN[1] = 0x0
685 04:47:13.944998 LP4Y_EN = 0x0
686 04:47:13.945306 WORK_FSP = 0x0
687 04:47:13.948033 WL = 0x2
688 04:47:13.948294 RL = 0x2
689 04:47:13.951661 BL = 0x2
690 04:47:13.951914 RPST = 0x0
691 04:47:13.955214 RD_PRE = 0x0
692 04:47:13.955466 WR_PRE = 0x1
693 04:47:13.958139 WR_PST = 0x0
694 04:47:13.958342 DBI_WR = 0x0
695 04:47:13.961831 DBI_RD = 0x0
696 04:47:13.962018 OTF = 0x1
697 04:47:13.965025 ===================================
698 04:47:13.971489 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 04:47:13.975426 nWR fixed to 40
700 04:47:13.978821 [ModeRegInit_LP4] CH0 RK0
701 04:47:13.978928 [ModeRegInit_LP4] CH0 RK1
702 04:47:13.982309 [ModeRegInit_LP4] CH1 RK0
703 04:47:13.985426 [ModeRegInit_LP4] CH1 RK1
704 04:47:13.985554 match AC timing 13
705 04:47:13.992169 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 04:47:13.995594 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 04:47:13.998867 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 04:47:14.005469 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 04:47:14.008976 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 04:47:14.009056 [EMI DOE] emi_dcm 0
711 04:47:14.015660 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 04:47:14.015737 ==
713 04:47:14.018756 Dram Type= 6, Freq= 0, CH_0, rank 0
714 04:47:14.022464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 04:47:14.022565 ==
716 04:47:14.029048 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 04:47:14.035407 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 04:47:14.043000 [CA 0] Center 38 (7~69) winsize 63
719 04:47:14.046413 [CA 1] Center 37 (7~68) winsize 62
720 04:47:14.049640 [CA 2] Center 35 (5~66) winsize 62
721 04:47:14.053097 [CA 3] Center 35 (5~66) winsize 62
722 04:47:14.056265 [CA 4] Center 34 (4~65) winsize 62
723 04:47:14.059803 [CA 5] Center 34 (4~64) winsize 61
724 04:47:14.059886
725 04:47:14.063462 [CmdBusTrainingLP45] Vref(ca) range 1: 32
726 04:47:14.063541
727 04:47:14.067310 [CATrainingPosCal] consider 1 rank data
728 04:47:14.071016 u2DelayCellTimex100 = 270/100 ps
729 04:47:14.074606 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
730 04:47:14.078688 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
731 04:47:14.082062 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
732 04:47:14.086295 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
733 04:47:14.089583 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
734 04:47:14.092989 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
735 04:47:14.093081
736 04:47:14.097102 CA PerBit enable=1, Macro0, CA PI delay=34
737 04:47:14.097240
738 04:47:14.100536 [CBTSetCACLKResult] CA Dly = 34
739 04:47:14.100683 CS Dly: 5 (0~36)
740 04:47:14.100777 ==
741 04:47:14.104049 Dram Type= 6, Freq= 0, CH_0, rank 1
742 04:47:14.108108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 04:47:14.108239 ==
744 04:47:14.114964 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 04:47:14.118833 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 04:47:14.129766 [CA 0] Center 38 (7~69) winsize 63
747 04:47:14.133684 [CA 1] Center 37 (7~68) winsize 62
748 04:47:14.136931 [CA 2] Center 35 (5~66) winsize 62
749 04:47:14.140272 [CA 3] Center 35 (5~66) winsize 62
750 04:47:14.144115 [CA 4] Center 34 (4~65) winsize 62
751 04:47:14.147654 [CA 5] Center 34 (4~65) winsize 62
752 04:47:14.147783
753 04:47:14.151808 [CmdBusTrainingLP45] Vref(ca) range 1: 30
754 04:47:14.151938
755 04:47:14.155521 [CATrainingPosCal] consider 2 rank data
756 04:47:14.155629 u2DelayCellTimex100 = 270/100 ps
757 04:47:14.159472 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
758 04:47:14.163129 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
759 04:47:14.166513 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
760 04:47:14.170122 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
761 04:47:14.173865 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
762 04:47:14.177687 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
763 04:47:14.177818
764 04:47:14.181398 CA PerBit enable=1, Macro0, CA PI delay=34
765 04:47:14.181561
766 04:47:14.185043 [CBTSetCACLKResult] CA Dly = 34
767 04:47:14.189032 CS Dly: 6 (0~38)
768 04:47:14.189162
769 04:47:14.192532 ----->DramcWriteLeveling(PI) begin...
770 04:47:14.192639 ==
771 04:47:14.192723 Dram Type= 6, Freq= 0, CH_0, rank 0
772 04:47:14.200134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 04:47:14.200240 ==
774 04:47:14.203624 Write leveling (Byte 0): 33 => 33
775 04:47:14.203745 Write leveling (Byte 1): 31 => 31
776 04:47:14.207498 DramcWriteLeveling(PI) end<-----
777 04:47:14.207649
778 04:47:14.207768 ==
779 04:47:14.210848 Dram Type= 6, Freq= 0, CH_0, rank 0
780 04:47:14.214608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 04:47:14.214716 ==
782 04:47:14.218745 [Gating] SW mode calibration
783 04:47:14.226071 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 04:47:14.229744 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 04:47:14.233706 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 04:47:14.240856 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 04:47:14.244685 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 04:47:14.248393 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 04:47:14.252112 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 04:47:14.256048 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 04:47:14.263283 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 04:47:14.266811 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 04:47:14.270475 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 04:47:14.273829 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 04:47:14.277691 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 04:47:14.285684 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 04:47:14.289000 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 04:47:14.292804 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 04:47:14.296451 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 04:47:14.299994 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 04:47:14.307511 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 04:47:14.311462 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 04:47:14.314749 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 04:47:14.318744 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 04:47:14.322630 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 04:47:14.326094 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 04:47:14.333470 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 04:47:14.337100 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 04:47:14.340882 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 04:47:14.344736 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 04:47:14.348450 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 04:47:14.352384 0 9 12 | B1->B0 | 2626 3232 | 1 1 | (0 0) (1 1)
813 04:47:14.359786 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 04:47:14.363506 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 04:47:14.367167 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 04:47:14.370913 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 04:47:14.374434 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 04:47:14.381671 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 04:47:14.385458 0 10 8 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (1 1)
820 04:47:14.388978 0 10 12 | B1->B0 | 2f2f 2525 | 0 0 | (1 0) (0 0)
821 04:47:14.391975 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 04:47:14.398730 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 04:47:14.402290 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 04:47:14.405402 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 04:47:14.412127 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 04:47:14.415645 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 04:47:14.418753 0 11 8 | B1->B0 | 2424 2a2a | 0 0 | (1 1) (1 1)
828 04:47:14.425356 0 11 12 | B1->B0 | 3434 3c3c | 0 0 | (0 0) (0 0)
829 04:47:14.428905 0 11 16 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
830 04:47:14.431994 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 04:47:14.438797 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 04:47:14.441989 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 04:47:14.445297 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 04:47:14.449063 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 04:47:14.455329 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 04:47:14.458595 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 04:47:14.461980 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 04:47:14.468724 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 04:47:14.472194 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 04:47:14.475661 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 04:47:14.482066 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 04:47:14.485431 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 04:47:14.488906 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 04:47:14.495851 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 04:47:14.498784 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 04:47:14.502075 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 04:47:14.508612 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 04:47:14.512059 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 04:47:14.515435 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 04:47:14.522087 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 04:47:14.525506 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 04:47:14.528812 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 04:47:14.532035 Total UI for P1: 0, mck2ui 16
854 04:47:14.535734 best dqsien dly found for B0: ( 0, 14, 8)
855 04:47:14.538784 Total UI for P1: 0, mck2ui 16
856 04:47:14.542117 best dqsien dly found for B1: ( 0, 14, 10)
857 04:47:14.545298 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
858 04:47:14.548917 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
859 04:47:14.549001
860 04:47:14.551993 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
861 04:47:14.558795 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 04:47:14.558879 [Gating] SW calibration Done
863 04:47:14.558946 ==
864 04:47:14.561947 Dram Type= 6, Freq= 0, CH_0, rank 0
865 04:47:14.568968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 04:47:14.569052 ==
867 04:47:14.569119 RX Vref Scan: 0
868 04:47:14.569182
869 04:47:14.572083 RX Vref 0 -> 0, step: 1
870 04:47:14.572166
871 04:47:14.575545 RX Delay -130 -> 252, step: 16
872 04:47:14.578917 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
873 04:47:14.582508 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 04:47:14.585533 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
875 04:47:14.589065 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
876 04:47:14.595673 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
877 04:47:14.599237 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
878 04:47:14.602250 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
879 04:47:14.605515 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
880 04:47:14.609056 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
881 04:47:14.615787 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
882 04:47:14.618967 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
883 04:47:14.622198 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
884 04:47:14.625733 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
885 04:47:14.629019 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
886 04:47:14.635626 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
887 04:47:14.639013 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
888 04:47:14.639096 ==
889 04:47:14.642079 Dram Type= 6, Freq= 0, CH_0, rank 0
890 04:47:14.645656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 04:47:14.645739 ==
892 04:47:14.649138 DQS Delay:
893 04:47:14.649221 DQS0 = 0, DQS1 = 0
894 04:47:14.649287 DQM Delay:
895 04:47:14.652563 DQM0 = 80, DQM1 = 70
896 04:47:14.652645 DQ Delay:
897 04:47:14.655840 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
898 04:47:14.659275 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
899 04:47:14.662488 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
900 04:47:14.665859 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
901 04:47:14.665944
902 04:47:14.666011
903 04:47:14.666073 ==
904 04:47:14.669009 Dram Type= 6, Freq= 0, CH_0, rank 0
905 04:47:14.676858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 04:47:14.676942 ==
907 04:47:14.677009
908 04:47:14.677072
909 04:47:14.677148 TX Vref Scan disable
910 04:47:14.679853 == TX Byte 0 ==
911 04:47:14.683102 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
912 04:47:14.686556 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
913 04:47:14.689979 == TX Byte 1 ==
914 04:47:14.693277 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
915 04:47:14.696611 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
916 04:47:14.696710 ==
917 04:47:14.699897 Dram Type= 6, Freq= 0, CH_0, rank 0
918 04:47:14.706516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 04:47:14.706638 ==
920 04:47:14.718622 TX Vref=22, minBit 3, minWin=26, winSum=431
921 04:47:14.721910 TX Vref=24, minBit 11, minWin=26, winSum=437
922 04:47:14.725044 TX Vref=26, minBit 2, minWin=27, winSum=439
923 04:47:14.728510 TX Vref=28, minBit 10, minWin=26, winSum=439
924 04:47:14.731934 TX Vref=30, minBit 10, minWin=26, winSum=439
925 04:47:14.738669 TX Vref=32, minBit 9, minWin=26, winSum=438
926 04:47:14.741954 [TxChooseVref] Worse bit 2, Min win 27, Win sum 439, Final Vref 26
927 04:47:14.742169
928 04:47:14.745274 Final TX Range 1 Vref 26
929 04:47:14.745430
930 04:47:14.745615 ==
931 04:47:14.748321 Dram Type= 6, Freq= 0, CH_0, rank 0
932 04:47:14.751479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 04:47:14.755008 ==
934 04:47:14.755221
935 04:47:14.755348
936 04:47:14.755464 TX Vref Scan disable
937 04:47:14.758540 == TX Byte 0 ==
938 04:47:14.761988 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
939 04:47:14.764965 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
940 04:47:14.768566 == TX Byte 1 ==
941 04:47:14.772043 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
942 04:47:14.775278 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
943 04:47:14.778671
944 04:47:14.778834 [DATLAT]
945 04:47:14.778959 Freq=800, CH0 RK0
946 04:47:14.779093
947 04:47:14.782273 DATLAT Default: 0xa
948 04:47:14.782427 0, 0xFFFF, sum = 0
949 04:47:14.785139 1, 0xFFFF, sum = 0
950 04:47:14.785353 2, 0xFFFF, sum = 0
951 04:47:14.788616 3, 0xFFFF, sum = 0
952 04:47:14.788818 4, 0xFFFF, sum = 0
953 04:47:14.792192 5, 0xFFFF, sum = 0
954 04:47:14.792348 6, 0xFFFF, sum = 0
955 04:47:14.795276 7, 0xFFFF, sum = 0
956 04:47:14.795499 8, 0xFFFF, sum = 0
957 04:47:14.798737 9, 0x0, sum = 1
958 04:47:14.798910 10, 0x0, sum = 2
959 04:47:14.802205 11, 0x0, sum = 3
960 04:47:14.802362 12, 0x0, sum = 4
961 04:47:14.805453 best_step = 10
962 04:47:14.805660
963 04:47:14.805787 ==
964 04:47:14.808685 Dram Type= 6, Freq= 0, CH_0, rank 0
965 04:47:14.812177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 04:47:14.812371 ==
967 04:47:14.815269 RX Vref Scan: 1
968 04:47:14.815477
969 04:47:14.815639 Set Vref Range= 32 -> 127
970 04:47:14.815791
971 04:47:14.818979 RX Vref 32 -> 127, step: 1
972 04:47:14.819183
973 04:47:14.822070 RX Delay -111 -> 252, step: 8
974 04:47:14.822274
975 04:47:14.825364 Set Vref, RX VrefLevel [Byte0]: 32
976 04:47:14.828673 [Byte1]: 32
977 04:47:14.828865
978 04:47:14.831980 Set Vref, RX VrefLevel [Byte0]: 33
979 04:47:14.835402 [Byte1]: 33
980 04:47:14.838974
981 04:47:14.839131 Set Vref, RX VrefLevel [Byte0]: 34
982 04:47:14.842279 [Byte1]: 34
983 04:47:14.846645
984 04:47:14.846775 Set Vref, RX VrefLevel [Byte0]: 35
985 04:47:14.849839 [Byte1]: 35
986 04:47:14.854060
987 04:47:14.854163 Set Vref, RX VrefLevel [Byte0]: 36
988 04:47:14.857724 [Byte1]: 36
989 04:47:14.861790
990 04:47:14.861887 Set Vref, RX VrefLevel [Byte0]: 37
991 04:47:14.865093 [Byte1]: 37
992 04:47:14.869470
993 04:47:14.869587 Set Vref, RX VrefLevel [Byte0]: 38
994 04:47:14.872859 [Byte1]: 38
995 04:47:14.877052
996 04:47:14.877134 Set Vref, RX VrefLevel [Byte0]: 39
997 04:47:14.880209 [Byte1]: 39
998 04:47:14.885008
999 04:47:14.885090 Set Vref, RX VrefLevel [Byte0]: 40
1000 04:47:14.888245 [Byte1]: 40
1001 04:47:14.892431
1002 04:47:14.892513 Set Vref, RX VrefLevel [Byte0]: 41
1003 04:47:14.895665 [Byte1]: 41
1004 04:47:14.899977
1005 04:47:14.900077 Set Vref, RX VrefLevel [Byte0]: 42
1006 04:47:14.903377 [Byte1]: 42
1007 04:47:14.907666
1008 04:47:14.907748 Set Vref, RX VrefLevel [Byte0]: 43
1009 04:47:14.911041 [Byte1]: 43
1010 04:47:14.915221
1011 04:47:14.915309 Set Vref, RX VrefLevel [Byte0]: 44
1012 04:47:14.918515 [Byte1]: 44
1013 04:47:14.923245
1014 04:47:14.923341 Set Vref, RX VrefLevel [Byte0]: 45
1015 04:47:14.926476 [Byte1]: 45
1016 04:47:14.931000
1017 04:47:14.931111 Set Vref, RX VrefLevel [Byte0]: 46
1018 04:47:14.933939 [Byte1]: 46
1019 04:47:14.938700
1020 04:47:14.938781 Set Vref, RX VrefLevel [Byte0]: 47
1021 04:47:14.941867 [Byte1]: 47
1022 04:47:14.946601
1023 04:47:14.946708 Set Vref, RX VrefLevel [Byte0]: 48
1024 04:47:14.950244 [Byte1]: 48
1025 04:47:14.953892
1026 04:47:14.954007 Set Vref, RX VrefLevel [Byte0]: 49
1027 04:47:14.957400 [Byte1]: 49
1028 04:47:14.961897
1029 04:47:14.961982 Set Vref, RX VrefLevel [Byte0]: 50
1030 04:47:14.964754 [Byte1]: 50
1031 04:47:14.968971
1032 04:47:14.969100 Set Vref, RX VrefLevel [Byte0]: 51
1033 04:47:14.972191 [Byte1]: 51
1034 04:47:14.976603
1035 04:47:14.976685 Set Vref, RX VrefLevel [Byte0]: 52
1036 04:47:14.979747 [Byte1]: 52
1037 04:47:14.984075
1038 04:47:14.984196 Set Vref, RX VrefLevel [Byte0]: 53
1039 04:47:14.987597 [Byte1]: 53
1040 04:47:14.991698
1041 04:47:14.991786 Set Vref, RX VrefLevel [Byte0]: 54
1042 04:47:14.994993 [Byte1]: 54
1043 04:47:14.999341
1044 04:47:14.999429 Set Vref, RX VrefLevel [Byte0]: 55
1045 04:47:15.002704 [Byte1]: 55
1046 04:47:15.006788
1047 04:47:15.006890 Set Vref, RX VrefLevel [Byte0]: 56
1048 04:47:15.010340 [Byte1]: 56
1049 04:47:15.014774
1050 04:47:15.014858 Set Vref, RX VrefLevel [Byte0]: 57
1051 04:47:15.017889 [Byte1]: 57
1052 04:47:15.022152
1053 04:47:15.022261 Set Vref, RX VrefLevel [Byte0]: 58
1054 04:47:15.025623 [Byte1]: 58
1055 04:47:15.030021
1056 04:47:15.030104 Set Vref, RX VrefLevel [Byte0]: 59
1057 04:47:15.033221 [Byte1]: 59
1058 04:47:15.037770
1059 04:47:15.037853 Set Vref, RX VrefLevel [Byte0]: 60
1060 04:47:15.041142 [Byte1]: 60
1061 04:47:15.045323
1062 04:47:15.045422 Set Vref, RX VrefLevel [Byte0]: 61
1063 04:47:15.048413 [Byte1]: 61
1064 04:47:15.052935
1065 04:47:15.053018 Set Vref, RX VrefLevel [Byte0]: 62
1066 04:47:15.056048 [Byte1]: 62
1067 04:47:15.060665
1068 04:47:15.060814 Set Vref, RX VrefLevel [Byte0]: 63
1069 04:47:15.063801 [Byte1]: 63
1070 04:47:15.068413
1071 04:47:15.068496 Set Vref, RX VrefLevel [Byte0]: 64
1072 04:47:15.071495 [Byte1]: 64
1073 04:47:15.075743
1074 04:47:15.075856 Set Vref, RX VrefLevel [Byte0]: 65
1075 04:47:15.079050 [Byte1]: 65
1076 04:47:15.083720
1077 04:47:15.083831 Set Vref, RX VrefLevel [Byte0]: 66
1078 04:47:15.086712 [Byte1]: 66
1079 04:47:15.091195
1080 04:47:15.091291 Set Vref, RX VrefLevel [Byte0]: 67
1081 04:47:15.094420 [Byte1]: 67
1082 04:47:15.098926
1083 04:47:15.099042 Set Vref, RX VrefLevel [Byte0]: 68
1084 04:47:15.102039 [Byte1]: 68
1085 04:47:15.106609
1086 04:47:15.106728 Set Vref, RX VrefLevel [Byte0]: 69
1087 04:47:15.109721 [Byte1]: 69
1088 04:47:15.113955
1089 04:47:15.114043 Set Vref, RX VrefLevel [Byte0]: 70
1090 04:47:15.117255 [Byte1]: 70
1091 04:47:15.121630
1092 04:47:15.121751 Set Vref, RX VrefLevel [Byte0]: 71
1093 04:47:15.125200 [Byte1]: 71
1094 04:47:15.129302
1095 04:47:15.129414 Set Vref, RX VrefLevel [Byte0]: 72
1096 04:47:15.132850 [Byte1]: 72
1097 04:47:15.137189
1098 04:47:15.137301 Set Vref, RX VrefLevel [Byte0]: 73
1099 04:47:15.140323 [Byte1]: 73
1100 04:47:15.144720
1101 04:47:15.144835 Set Vref, RX VrefLevel [Byte0]: 74
1102 04:47:15.147850 [Byte1]: 74
1103 04:47:15.152253
1104 04:47:15.152371 Set Vref, RX VrefLevel [Byte0]: 75
1105 04:47:15.155481 [Byte1]: 75
1106 04:47:15.159851
1107 04:47:15.159965 Set Vref, RX VrefLevel [Byte0]: 76
1108 04:47:15.163412 [Byte1]: 76
1109 04:47:15.167547
1110 04:47:15.167677 Set Vref, RX VrefLevel [Byte0]: 77
1111 04:47:15.170805 [Byte1]: 77
1112 04:47:15.175229
1113 04:47:15.175364 Set Vref, RX VrefLevel [Byte0]: 78
1114 04:47:15.178263 [Byte1]: 78
1115 04:47:15.182750
1116 04:47:15.182868 Set Vref, RX VrefLevel [Byte0]: 79
1117 04:47:15.186320 [Byte1]: 79
1118 04:47:15.190616
1119 04:47:15.190731 Final RX Vref Byte 0 = 59 to rank0
1120 04:47:15.193791 Final RX Vref Byte 1 = 59 to rank0
1121 04:47:15.197273 Final RX Vref Byte 0 = 59 to rank1
1122 04:47:15.200225 Final RX Vref Byte 1 = 59 to rank1==
1123 04:47:15.203877 Dram Type= 6, Freq= 0, CH_0, rank 0
1124 04:47:15.210370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1125 04:47:15.210453 ==
1126 04:47:15.210578 DQS Delay:
1127 04:47:15.210671 DQS0 = 0, DQS1 = 0
1128 04:47:15.213941 DQM Delay:
1129 04:47:15.214015 DQM0 = 82, DQM1 = 68
1130 04:47:15.217390 DQ Delay:
1131 04:47:15.220685 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1132 04:47:15.220769 DQ4 =84, DQ5 =68, DQ6 =88, DQ7 =92
1133 04:47:15.223933 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1134 04:47:15.227232 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1135 04:47:15.230456
1136 04:47:15.230540
1137 04:47:15.237420 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1138 04:47:15.240501 CH0 RK0: MR19=606, MR18=2424
1139 04:47:15.247334 CH0_RK0: MR19=0x606, MR18=0x2424, DQSOSC=400, MR23=63, INC=92, DEC=61
1140 04:47:15.247420
1141 04:47:15.250517 ----->DramcWriteLeveling(PI) begin...
1142 04:47:15.250606 ==
1143 04:47:15.253989 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 04:47:15.257062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 04:47:15.257147 ==
1146 04:47:15.260487 Write leveling (Byte 0): 31 => 31
1147 04:47:15.263825 Write leveling (Byte 1): 30 => 30
1148 04:47:15.267334 DramcWriteLeveling(PI) end<-----
1149 04:47:15.267418
1150 04:47:15.267484 ==
1151 04:47:15.270486 Dram Type= 6, Freq= 0, CH_0, rank 1
1152 04:47:15.273951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1153 04:47:15.274069 ==
1154 04:47:15.276817 [Gating] SW mode calibration
1155 04:47:15.283777 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1156 04:47:15.290301 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1157 04:47:15.293449 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1158 04:47:15.297183 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 04:47:15.303762 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1160 04:47:15.306974 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 04:47:15.310500 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 04:47:15.317093 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 04:47:15.320509 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 04:47:15.323530 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 04:47:15.330412 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 04:47:15.333554 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 04:47:15.336710 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 04:47:15.343672 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 04:47:15.346816 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 04:47:15.390627 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 04:47:15.391041 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 04:47:15.391311 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 04:47:15.391386 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 04:47:15.391452 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1175 04:47:15.391529 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1176 04:47:15.391895 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1177 04:47:15.392201 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 04:47:15.392304 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 04:47:15.392407 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 04:47:15.427523 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 04:47:15.428100 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 04:47:15.428365 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 04:47:15.428433 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
1184 04:47:15.428495 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
1185 04:47:15.428564 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 04:47:15.428634 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 04:47:15.431814 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 04:47:15.431886 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 04:47:15.435336 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 04:47:15.438376 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
1191 04:47:15.441648 0 10 8 | B1->B0 | 2f2f 2828 | 1 0 | (1 0) (0 0)
1192 04:47:15.448432 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 04:47:15.451792 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 04:47:15.455105 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 04:47:15.461871 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 04:47:15.465385 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 04:47:15.468478 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 04:47:15.475417 0 11 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1199 04:47:15.478447 0 11 8 | B1->B0 | 3131 3c3c | 0 0 | (0 0) (1 1)
1200 04:47:15.481882 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1201 04:47:15.488583 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 04:47:15.491945 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 04:47:15.495080 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 04:47:15.501658 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 04:47:15.505719 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 04:47:15.509370 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 04:47:15.513015 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1208 04:47:15.516906 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1209 04:47:15.523886 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 04:47:15.527150 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 04:47:15.530626 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 04:47:15.534119 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 04:47:15.541213 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 04:47:15.544212 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 04:47:15.547561 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 04:47:15.554381 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 04:47:15.557828 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 04:47:15.561208 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 04:47:15.567625 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 04:47:15.570921 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 04:47:15.574434 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 04:47:15.581036 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1223 04:47:15.584662 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1224 04:47:15.587845 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1225 04:47:15.590759 Total UI for P1: 0, mck2ui 16
1226 04:47:15.594148 best dqsien dly found for B0: ( 0, 14, 6)
1227 04:47:15.597582 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1228 04:47:15.600883 Total UI for P1: 0, mck2ui 16
1229 04:47:15.604445 best dqsien dly found for B1: ( 0, 14, 10)
1230 04:47:15.607709 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1231 04:47:15.614104 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1232 04:47:15.614189
1233 04:47:15.617350 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1234 04:47:15.620888 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1235 04:47:15.624081 [Gating] SW calibration Done
1236 04:47:15.624160 ==
1237 04:47:15.627622 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 04:47:15.630892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1239 04:47:15.630977 ==
1240 04:47:15.631064 RX Vref Scan: 0
1241 04:47:15.634383
1242 04:47:15.634466 RX Vref 0 -> 0, step: 1
1243 04:47:15.634552
1244 04:47:15.637575 RX Delay -130 -> 252, step: 16
1245 04:47:15.640916 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1246 04:47:15.644519 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1247 04:47:15.651092 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1248 04:47:15.654373 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1249 04:47:15.657426 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1250 04:47:15.660989 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1251 04:47:15.664554 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1252 04:47:15.671089 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1253 04:47:15.674115 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1254 04:47:15.677823 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1255 04:47:15.680663 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1256 04:47:15.684356 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1257 04:47:15.690667 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1258 04:47:15.693958 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1259 04:47:15.697697 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1260 04:47:15.701017 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1261 04:47:15.701125 ==
1262 04:47:15.704272 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 04:47:15.710811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 04:47:15.710896 ==
1265 04:47:15.710981 DQS Delay:
1266 04:47:15.714217 DQS0 = 0, DQS1 = 0
1267 04:47:15.714301 DQM Delay:
1268 04:47:15.714386 DQM0 = 75, DQM1 = 69
1269 04:47:15.717645 DQ Delay:
1270 04:47:15.720631 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1271 04:47:15.724023 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1272 04:47:15.727415 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1273 04:47:15.730989 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1274 04:47:15.731072
1275 04:47:15.731157
1276 04:47:15.731237 ==
1277 04:47:15.734165 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 04:47:15.737587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 04:47:15.737672 ==
1280 04:47:15.737758
1281 04:47:15.737838
1282 04:47:15.740837 TX Vref Scan disable
1283 04:47:15.740921 == TX Byte 0 ==
1284 04:47:15.747550 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1285 04:47:15.750670 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1286 04:47:15.750756 == TX Byte 1 ==
1287 04:47:15.757359 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1288 04:47:15.760861 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1289 04:47:15.760945 ==
1290 04:47:15.764222 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 04:47:15.767686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 04:47:15.767781 ==
1293 04:47:15.781315 TX Vref=22, minBit 11, minWin=26, winSum=435
1294 04:47:15.784467 TX Vref=24, minBit 11, minWin=26, winSum=434
1295 04:47:15.787973 TX Vref=26, minBit 1, minWin=27, winSum=441
1296 04:47:15.791350 TX Vref=28, minBit 2, minWin=27, winSum=442
1297 04:47:15.794708 TX Vref=30, minBit 1, minWin=27, winSum=442
1298 04:47:15.801402 TX Vref=32, minBit 8, minWin=27, winSum=443
1299 04:47:15.804915 [TxChooseVref] Worse bit 8, Min win 27, Win sum 443, Final Vref 32
1300 04:47:15.805013
1301 04:47:15.807908 Final TX Range 1 Vref 32
1302 04:47:15.807989
1303 04:47:15.808068 ==
1304 04:47:15.811316 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 04:47:15.814704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 04:47:15.814877 ==
1307 04:47:15.814971
1308 04:47:15.817884
1309 04:47:15.817998 TX Vref Scan disable
1310 04:47:15.821161 == TX Byte 0 ==
1311 04:47:15.824839 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1312 04:47:15.831395 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1313 04:47:15.831500 == TX Byte 1 ==
1314 04:47:15.834706 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1315 04:47:15.838095 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1316 04:47:15.841262
1317 04:47:15.841365 [DATLAT]
1318 04:47:15.841459 Freq=800, CH0 RK1
1319 04:47:15.841606
1320 04:47:15.844775 DATLAT Default: 0xa
1321 04:47:15.844851 0, 0xFFFF, sum = 0
1322 04:47:15.848167 1, 0xFFFF, sum = 0
1323 04:47:15.848270 2, 0xFFFF, sum = 0
1324 04:47:15.851294 3, 0xFFFF, sum = 0
1325 04:47:15.851382 4, 0xFFFF, sum = 0
1326 04:47:15.854835 5, 0xFFFF, sum = 0
1327 04:47:15.854944 6, 0xFFFF, sum = 0
1328 04:47:15.857869 7, 0xFFFF, sum = 0
1329 04:47:15.861218 8, 0xFFFF, sum = 0
1330 04:47:15.861326 9, 0x0, sum = 1
1331 04:47:15.861426 10, 0x0, sum = 2
1332 04:47:15.864802 11, 0x0, sum = 3
1333 04:47:15.864915 12, 0x0, sum = 4
1334 04:47:15.867859 best_step = 10
1335 04:47:15.867961
1336 04:47:15.868057 ==
1337 04:47:15.871170 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 04:47:15.874701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 04:47:15.874807 ==
1340 04:47:15.877973 RX Vref Scan: 0
1341 04:47:15.878076
1342 04:47:15.878166 RX Vref 0 -> 0, step: 1
1343 04:47:15.878272
1344 04:47:15.881395 RX Delay -111 -> 252, step: 8
1345 04:47:15.887926 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1346 04:47:15.891493 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1347 04:47:15.894428 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1348 04:47:15.897900 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1349 04:47:15.901534 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1350 04:47:15.907911 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1351 04:47:15.911305 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1352 04:47:15.914397 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1353 04:47:15.917957 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1354 04:47:15.921178 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1355 04:47:15.927770 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1356 04:47:15.931048 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1357 04:47:15.934608 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1358 04:47:15.937868 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1359 04:47:15.944466 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1360 04:47:15.948106 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1361 04:47:15.948180 ==
1362 04:47:15.951113 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 04:47:15.954638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 04:47:15.954719 ==
1365 04:47:15.954782 DQS Delay:
1366 04:47:15.958038 DQS0 = 0, DQS1 = 0
1367 04:47:15.958118 DQM Delay:
1368 04:47:15.961445 DQM0 = 79, DQM1 = 71
1369 04:47:15.961564 DQ Delay:
1370 04:47:15.964611 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1371 04:47:15.967771 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =88
1372 04:47:15.971385 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1373 04:47:15.974597 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1374 04:47:15.974677
1375 04:47:15.974740
1376 04:47:15.984675 [DQSOSCAuto] RK1, (LSB)MR18= 0x4621, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1377 04:47:15.984757 CH0 RK1: MR19=606, MR18=4621
1378 04:47:15.991371 CH0_RK1: MR19=0x606, MR18=0x4621, DQSOSC=392, MR23=63, INC=96, DEC=64
1379 04:47:15.994654 [RxdqsGatingPostProcess] freq 800
1380 04:47:16.001246 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1381 04:47:16.004569 Pre-setting of DQS Precalculation
1382 04:47:16.007848 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1383 04:47:16.008095 ==
1384 04:47:16.011158 Dram Type= 6, Freq= 0, CH_1, rank 0
1385 04:47:16.014477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 04:47:16.017766 ==
1387 04:47:16.021003 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1388 04:47:16.027486 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1389 04:47:16.036337 [CA 0] Center 36 (7~66) winsize 60
1390 04:47:16.039857 [CA 1] Center 36 (6~67) winsize 62
1391 04:47:16.043015 [CA 2] Center 34 (5~64) winsize 60
1392 04:47:16.046467 [CA 3] Center 34 (4~64) winsize 61
1393 04:47:16.049804 [CA 4] Center 34 (4~65) winsize 62
1394 04:47:16.052844 [CA 5] Center 34 (4~64) winsize 61
1395 04:47:16.052926
1396 04:47:16.056429 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1397 04:47:16.056509
1398 04:47:16.059637 [CATrainingPosCal] consider 1 rank data
1399 04:47:16.062750 u2DelayCellTimex100 = 270/100 ps
1400 04:47:16.066425 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1401 04:47:16.069801 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1402 04:47:16.076297 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1403 04:47:16.079671 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1404 04:47:16.083129 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1405 04:47:16.086285 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1406 04:47:16.086366
1407 04:47:16.089861 CA PerBit enable=1, Macro0, CA PI delay=34
1408 04:47:16.089942
1409 04:47:16.092969 [CBTSetCACLKResult] CA Dly = 34
1410 04:47:16.093049 CS Dly: 5 (0~36)
1411 04:47:16.093114 ==
1412 04:47:16.096503 Dram Type= 6, Freq= 0, CH_1, rank 1
1413 04:47:16.102884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 04:47:16.102970 ==
1415 04:47:16.106404 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1416 04:47:16.112979 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1417 04:47:16.122417 [CA 0] Center 36 (6~67) winsize 62
1418 04:47:16.125894 [CA 1] Center 36 (6~67) winsize 62
1419 04:47:16.129114 [CA 2] Center 35 (5~65) winsize 61
1420 04:47:16.132491 [CA 3] Center 34 (4~64) winsize 61
1421 04:47:16.135894 [CA 4] Center 34 (4~65) winsize 62
1422 04:47:16.139289 [CA 5] Center 33 (3~64) winsize 62
1423 04:47:16.139381
1424 04:47:16.142290 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1425 04:47:16.142399
1426 04:47:16.145694 [CATrainingPosCal] consider 2 rank data
1427 04:47:16.149232 u2DelayCellTimex100 = 270/100 ps
1428 04:47:16.152364 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1429 04:47:16.156448 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1430 04:47:16.162565 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1431 04:47:16.165943 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1432 04:47:16.169318 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1433 04:47:16.173215 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1434 04:47:16.173299
1435 04:47:16.176672 CA PerBit enable=1, Macro0, CA PI delay=34
1436 04:47:16.176756
1437 04:47:16.180143 [CBTSetCACLKResult] CA Dly = 34
1438 04:47:16.180228 CS Dly: 5 (0~37)
1439 04:47:16.180314
1440 04:47:16.183995 ----->DramcWriteLeveling(PI) begin...
1441 04:47:16.184082 ==
1442 04:47:16.187625 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 04:47:16.191225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 04:47:16.191311 ==
1445 04:47:16.194624 Write leveling (Byte 0): 26 => 26
1446 04:47:16.198638 Write leveling (Byte 1): 32 => 32
1447 04:47:16.202254 DramcWriteLeveling(PI) end<-----
1448 04:47:16.202355
1449 04:47:16.202457 ==
1450 04:47:16.205725 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 04:47:16.209165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 04:47:16.209275 ==
1453 04:47:16.212765 [Gating] SW mode calibration
1454 04:47:16.219268 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1455 04:47:16.222749 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1456 04:47:16.229047 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1457 04:47:16.232537 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1458 04:47:16.235940 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1459 04:47:16.242664 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 04:47:16.246086 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 04:47:16.249017 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 04:47:16.255735 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 04:47:16.259270 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 04:47:16.262557 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 04:47:16.269121 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 04:47:16.272639 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 04:47:16.275812 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 04:47:16.282250 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 04:47:16.285707 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 04:47:16.289086 0 7 24 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1471 04:47:16.295890 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 04:47:16.299379 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 04:47:16.302300 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1474 04:47:16.306270 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1475 04:47:16.312546 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 04:47:16.315701 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 04:47:16.319056 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 04:47:16.325762 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 04:47:16.329248 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 04:47:16.332723 0 9 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1481 04:47:16.339302 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 04:47:16.342824 0 9 8 | B1->B0 | 2727 2626 | 0 1 | (0 0) (0 0)
1483 04:47:16.345821 0 9 12 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
1484 04:47:16.352451 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 04:47:16.355960 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 04:47:16.359285 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 04:47:16.365672 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 04:47:16.369139 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 04:47:16.372500 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1490 04:47:16.378898 0 10 8 | B1->B0 | 2e2e 2d2d | 0 0 | (1 0) (0 0)
1491 04:47:16.382318 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 04:47:16.385635 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 04:47:16.392202 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 04:47:16.395912 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 04:47:16.399110 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 04:47:16.402249 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 04:47:16.409203 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1498 04:47:16.412834 0 11 8 | B1->B0 | 3333 3535 | 0 0 | (0 0) (0 0)
1499 04:47:16.415706 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 04:47:16.422744 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 04:47:16.425840 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 04:47:16.429405 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 04:47:16.435991 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 04:47:16.439341 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 04:47:16.442352 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 04:47:16.449246 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1507 04:47:16.452838 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1508 04:47:16.456055 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 04:47:16.462677 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 04:47:16.465735 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 04:47:16.469300 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 04:47:16.475729 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 04:47:16.479289 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 04:47:16.482704 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 04:47:16.489142 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 04:47:16.492588 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 04:47:16.495888 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 04:47:16.499222 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 04:47:16.505808 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 04:47:16.509176 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 04:47:16.512503 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1522 04:47:16.519046 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 04:47:16.522303 Total UI for P1: 0, mck2ui 16
1524 04:47:16.525470 best dqsien dly found for B0: ( 0, 14, 4)
1525 04:47:16.529036 Total UI for P1: 0, mck2ui 16
1526 04:47:16.532312 best dqsien dly found for B1: ( 0, 14, 6)
1527 04:47:16.535734 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1528 04:47:16.538986 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1529 04:47:16.539069
1530 04:47:16.542479 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1531 04:47:16.545699 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1532 04:47:16.549031 [Gating] SW calibration Done
1533 04:47:16.549114 ==
1534 04:47:16.552600 Dram Type= 6, Freq= 0, CH_1, rank 0
1535 04:47:16.555879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1536 04:47:16.555963 ==
1537 04:47:16.558969 RX Vref Scan: 0
1538 04:47:16.559062
1539 04:47:16.559162 RX Vref 0 -> 0, step: 1
1540 04:47:16.559264
1541 04:47:16.562068 RX Delay -130 -> 252, step: 16
1542 04:47:16.565574 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1543 04:47:16.572370 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1544 04:47:16.575559 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1545 04:47:16.579044 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1546 04:47:16.582184 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1547 04:47:16.585591 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1548 04:47:16.592140 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1549 04:47:16.595356 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1550 04:47:16.598888 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1551 04:47:16.601922 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1552 04:47:16.605369 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1553 04:47:16.611928 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1554 04:47:16.615360 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1555 04:47:16.618810 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1556 04:47:16.622128 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1557 04:47:16.628549 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1558 04:47:16.628646 ==
1559 04:47:16.631857 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 04:47:16.635378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 04:47:16.635476 ==
1562 04:47:16.635576 DQS Delay:
1563 04:47:16.638488 DQS0 = 0, DQS1 = 0
1564 04:47:16.638584 DQM Delay:
1565 04:47:16.641933 DQM0 = 81, DQM1 = 70
1566 04:47:16.642029 DQ Delay:
1567 04:47:16.645596 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1568 04:47:16.648646 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1569 04:47:16.651883 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1570 04:47:16.655498 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1571 04:47:16.655595
1572 04:47:16.655693
1573 04:47:16.655785 ==
1574 04:47:16.658708 Dram Type= 6, Freq= 0, CH_1, rank 0
1575 04:47:16.662013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1576 04:47:16.662101 ==
1577 04:47:16.662192
1578 04:47:16.662277
1579 04:47:16.665279 TX Vref Scan disable
1580 04:47:16.668706 == TX Byte 0 ==
1581 04:47:16.671778 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1582 04:47:16.675236 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1583 04:47:16.678462 == TX Byte 1 ==
1584 04:47:16.681909 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1585 04:47:16.685428 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1586 04:47:16.685519 ==
1587 04:47:16.688514 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 04:47:16.695109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 04:47:16.695193 ==
1590 04:47:16.707367 TX Vref=22, minBit 1, minWin=27, winSum=444
1591 04:47:16.710601 TX Vref=24, minBit 1, minWin=27, winSum=447
1592 04:47:16.713939 TX Vref=26, minBit 1, minWin=27, winSum=448
1593 04:47:16.717278 TX Vref=28, minBit 1, minWin=28, winSum=454
1594 04:47:16.720614 TX Vref=30, minBit 6, minWin=27, winSum=454
1595 04:47:16.723859 TX Vref=32, minBit 0, minWin=28, winSum=451
1596 04:47:16.730635 [TxChooseVref] Worse bit 1, Min win 28, Win sum 454, Final Vref 28
1597 04:47:16.730720
1598 04:47:16.734079 Final TX Range 1 Vref 28
1599 04:47:16.734181
1600 04:47:16.734264 ==
1601 04:47:16.737405 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 04:47:16.740589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 04:47:16.740692 ==
1604 04:47:16.740775
1605 04:47:16.744039
1606 04:47:16.744128 TX Vref Scan disable
1607 04:47:16.747475 == TX Byte 0 ==
1608 04:47:16.751384 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1609 04:47:16.754860 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1610 04:47:16.758135 == TX Byte 1 ==
1611 04:47:16.761332 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1612 04:47:16.764723 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1613 04:47:16.764807
1614 04:47:16.768068 [DATLAT]
1615 04:47:16.768152 Freq=800, CH1 RK0
1616 04:47:16.768238
1617 04:47:16.771524 DATLAT Default: 0xa
1618 04:47:16.771608 0, 0xFFFF, sum = 0
1619 04:47:16.774885 1, 0xFFFF, sum = 0
1620 04:47:16.774970 2, 0xFFFF, sum = 0
1621 04:47:16.777941 3, 0xFFFF, sum = 0
1622 04:47:16.778027 4, 0xFFFF, sum = 0
1623 04:47:16.781515 5, 0xFFFF, sum = 0
1624 04:47:16.781614 6, 0xFFFF, sum = 0
1625 04:47:16.785051 7, 0xFFFF, sum = 0
1626 04:47:16.785136 8, 0xFFFF, sum = 0
1627 04:47:16.788146 9, 0x0, sum = 1
1628 04:47:16.788231 10, 0x0, sum = 2
1629 04:47:16.791772 11, 0x0, sum = 3
1630 04:47:16.791857 12, 0x0, sum = 4
1631 04:47:16.791944 best_step = 10
1632 04:47:16.795175
1633 04:47:16.795259 ==
1634 04:47:16.798402 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 04:47:16.801695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 04:47:16.801785 ==
1637 04:47:16.801870 RX Vref Scan: 1
1638 04:47:16.801951
1639 04:47:16.804745 Set Vref Range= 32 -> 127
1640 04:47:16.804829
1641 04:47:16.808493 RX Vref 32 -> 127, step: 1
1642 04:47:16.808577
1643 04:47:16.811469 RX Delay -111 -> 252, step: 8
1644 04:47:16.811552
1645 04:47:16.814573 Set Vref, RX VrefLevel [Byte0]: 32
1646 04:47:16.818000 [Byte1]: 32
1647 04:47:16.818095
1648 04:47:16.821565 Set Vref, RX VrefLevel [Byte0]: 33
1649 04:47:16.824634 [Byte1]: 33
1650 04:47:16.824718
1651 04:47:16.827943 Set Vref, RX VrefLevel [Byte0]: 34
1652 04:47:16.831239 [Byte1]: 34
1653 04:47:16.835447
1654 04:47:16.835532 Set Vref, RX VrefLevel [Byte0]: 35
1655 04:47:16.838695 [Byte1]: 35
1656 04:47:16.843008
1657 04:47:16.843091 Set Vref, RX VrefLevel [Byte0]: 36
1658 04:47:16.846182 [Byte1]: 36
1659 04:47:16.850538
1660 04:47:16.850621 Set Vref, RX VrefLevel [Byte0]: 37
1661 04:47:16.854156 [Byte1]: 37
1662 04:47:16.858356
1663 04:47:16.858440 Set Vref, RX VrefLevel [Byte0]: 38
1664 04:47:16.861658 [Byte1]: 38
1665 04:47:16.866067
1666 04:47:16.866150 Set Vref, RX VrefLevel [Byte0]: 39
1667 04:47:16.869083 [Byte1]: 39
1668 04:47:16.873659
1669 04:47:16.873742 Set Vref, RX VrefLevel [Byte0]: 40
1670 04:47:16.877095 [Byte1]: 40
1671 04:47:16.881368
1672 04:47:16.881451 Set Vref, RX VrefLevel [Byte0]: 41
1673 04:47:16.884504 [Byte1]: 41
1674 04:47:16.888858
1675 04:47:16.888942 Set Vref, RX VrefLevel [Byte0]: 42
1676 04:47:16.892460 [Byte1]: 42
1677 04:47:16.896673
1678 04:47:16.896757 Set Vref, RX VrefLevel [Byte0]: 43
1679 04:47:16.900095 [Byte1]: 43
1680 04:47:16.904376
1681 04:47:16.904460 Set Vref, RX VrefLevel [Byte0]: 44
1682 04:47:16.907537 [Byte1]: 44
1683 04:47:16.911954
1684 04:47:16.912038 Set Vref, RX VrefLevel [Byte0]: 45
1685 04:47:16.915230 [Byte1]: 45
1686 04:47:16.919487
1687 04:47:16.919571 Set Vref, RX VrefLevel [Byte0]: 46
1688 04:47:16.923134 [Byte1]: 46
1689 04:47:16.927096
1690 04:47:16.927180 Set Vref, RX VrefLevel [Byte0]: 47
1691 04:47:16.930602 [Byte1]: 47
1692 04:47:16.934732
1693 04:47:16.934815 Set Vref, RX VrefLevel [Byte0]: 48
1694 04:47:16.937979 [Byte1]: 48
1695 04:47:16.942333
1696 04:47:16.942417 Set Vref, RX VrefLevel [Byte0]: 49
1697 04:47:16.945629 [Byte1]: 49
1698 04:47:16.950225
1699 04:47:16.950309 Set Vref, RX VrefLevel [Byte0]: 50
1700 04:47:16.953600 [Byte1]: 50
1701 04:47:16.957774
1702 04:47:16.957854 Set Vref, RX VrefLevel [Byte0]: 51
1703 04:47:16.960975 [Byte1]: 51
1704 04:47:16.965250
1705 04:47:16.965366 Set Vref, RX VrefLevel [Byte0]: 52
1706 04:47:16.968575 [Byte1]: 52
1707 04:47:16.973061
1708 04:47:16.973166 Set Vref, RX VrefLevel [Byte0]: 53
1709 04:47:16.976199 [Byte1]: 53
1710 04:47:16.980682
1711 04:47:16.980760 Set Vref, RX VrefLevel [Byte0]: 54
1712 04:47:16.983829 [Byte1]: 54
1713 04:47:16.988397
1714 04:47:16.988498 Set Vref, RX VrefLevel [Byte0]: 55
1715 04:47:16.991675 [Byte1]: 55
1716 04:47:16.996122
1717 04:47:16.996228 Set Vref, RX VrefLevel [Byte0]: 56
1718 04:47:16.999161 [Byte1]: 56
1719 04:47:17.003616
1720 04:47:17.003721 Set Vref, RX VrefLevel [Byte0]: 57
1721 04:47:17.006803 [Byte1]: 57
1722 04:47:17.011229
1723 04:47:17.011331 Set Vref, RX VrefLevel [Byte0]: 58
1724 04:47:17.014840 [Byte1]: 58
1725 04:47:17.018802
1726 04:47:17.018903 Set Vref, RX VrefLevel [Byte0]: 59
1727 04:47:17.022237 [Byte1]: 59
1728 04:47:17.026569
1729 04:47:17.026675 Set Vref, RX VrefLevel [Byte0]: 60
1730 04:47:17.029661 [Byte1]: 60
1731 04:47:17.034155
1732 04:47:17.034285 Set Vref, RX VrefLevel [Byte0]: 61
1733 04:47:17.037345 [Byte1]: 61
1734 04:47:17.041670
1735 04:47:17.041749 Set Vref, RX VrefLevel [Byte0]: 62
1736 04:47:17.045316 [Byte1]: 62
1737 04:47:17.049329
1738 04:47:17.049429 Set Vref, RX VrefLevel [Byte0]: 63
1739 04:47:17.052810 [Byte1]: 63
1740 04:47:17.056969
1741 04:47:17.057060 Set Vref, RX VrefLevel [Byte0]: 64
1742 04:47:17.060514 [Byte1]: 64
1743 04:47:17.065048
1744 04:47:17.065166 Set Vref, RX VrefLevel [Byte0]: 65
1745 04:47:17.067974 [Byte1]: 65
1746 04:47:17.072547
1747 04:47:17.072632 Set Vref, RX VrefLevel [Byte0]: 66
1748 04:47:17.075601 [Byte1]: 66
1749 04:47:17.080108
1750 04:47:17.080214 Set Vref, RX VrefLevel [Byte0]: 67
1751 04:47:17.083285 [Byte1]: 67
1752 04:47:17.087491
1753 04:47:17.087614 Set Vref, RX VrefLevel [Byte0]: 68
1754 04:47:17.090998 [Byte1]: 68
1755 04:47:17.095278
1756 04:47:17.095355 Set Vref, RX VrefLevel [Byte0]: 69
1757 04:47:17.098668 [Byte1]: 69
1758 04:47:17.102781
1759 04:47:17.102861 Set Vref, RX VrefLevel [Byte0]: 70
1760 04:47:17.106279 [Byte1]: 70
1761 04:47:17.110750
1762 04:47:17.110871 Set Vref, RX VrefLevel [Byte0]: 71
1763 04:47:17.113787 [Byte1]: 71
1764 04:47:17.118021
1765 04:47:17.118128 Set Vref, RX VrefLevel [Byte0]: 72
1766 04:47:17.121648 [Byte1]: 72
1767 04:47:17.125985
1768 04:47:17.126071 Set Vref, RX VrefLevel [Byte0]: 73
1769 04:47:17.129237 [Byte1]: 73
1770 04:47:17.133455
1771 04:47:17.133554 Set Vref, RX VrefLevel [Byte0]: 74
1772 04:47:17.136845 [Byte1]: 74
1773 04:47:17.141187
1774 04:47:17.141272 Set Vref, RX VrefLevel [Byte0]: 75
1775 04:47:17.144328 [Byte1]: 75
1776 04:47:17.149095
1777 04:47:17.149180 Final RX Vref Byte 0 = 61 to rank0
1778 04:47:17.152244 Final RX Vref Byte 1 = 57 to rank0
1779 04:47:17.155658 Final RX Vref Byte 0 = 61 to rank1
1780 04:47:17.158728 Final RX Vref Byte 1 = 57 to rank1==
1781 04:47:17.162242 Dram Type= 6, Freq= 0, CH_1, rank 0
1782 04:47:17.168869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 04:47:17.168956 ==
1784 04:47:17.169045 DQS Delay:
1785 04:47:17.169146 DQS0 = 0, DQS1 = 0
1786 04:47:17.171948 DQM Delay:
1787 04:47:17.172034 DQM0 = 81, DQM1 = 71
1788 04:47:17.175419 DQ Delay:
1789 04:47:17.178658 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1790 04:47:17.182005 DQ4 =76, DQ5 =92, DQ6 =96, DQ7 =76
1791 04:47:17.182091 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1792 04:47:17.188698 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1793 04:47:17.188784
1794 04:47:17.188871
1795 04:47:17.195452 [DQSOSCAuto] RK0, (LSB)MR18= 0x111c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
1796 04:47:17.199152 CH1 RK0: MR19=606, MR18=111C
1797 04:47:17.205547 CH1_RK0: MR19=0x606, MR18=0x111C, DQSOSC=402, MR23=63, INC=91, DEC=60
1798 04:47:17.205634
1799 04:47:17.208990 ----->DramcWriteLeveling(PI) begin...
1800 04:47:17.209077 ==
1801 04:47:17.212032 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 04:47:17.215835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 04:47:17.215920 ==
1804 04:47:17.218886 Write leveling (Byte 0): 29 => 29
1805 04:47:17.222280 Write leveling (Byte 1): 29 => 29
1806 04:47:17.225610 DramcWriteLeveling(PI) end<-----
1807 04:47:17.225693
1808 04:47:17.225778 ==
1809 04:47:17.228868 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 04:47:17.232540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 04:47:17.232624 ==
1812 04:47:17.235629 [Gating] SW mode calibration
1813 04:47:17.241998 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1814 04:47:17.249165 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1815 04:47:17.252301 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1816 04:47:17.255613 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1817 04:47:17.262604 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 04:47:17.265490 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 04:47:17.269209 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 04:47:17.275707 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 04:47:17.278963 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 04:47:17.282209 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 04:47:17.288878 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 04:47:17.292403 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 04:47:17.295535 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 04:47:17.299088 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 04:47:17.305692 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 04:47:17.308951 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 04:47:17.312450 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 04:47:17.318954 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 04:47:17.322400 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 04:47:17.325917 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1833 04:47:17.332285 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1834 04:47:17.335813 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 04:47:17.339088 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 04:47:17.345513 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 04:47:17.348977 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 04:47:17.352451 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 04:47:17.358636 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 04:47:17.362133 0 9 4 | B1->B0 | 2323 2c2c | 1 0 | (1 1) (1 1)
1841 04:47:17.365612 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
1842 04:47:17.372331 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 04:47:17.375381 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 04:47:17.378428 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 04:47:17.385179 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 04:47:17.388642 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 04:47:17.392002 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1848 04:47:17.398605 0 10 4 | B1->B0 | 3232 2d2d | 0 0 | (0 0) (0 0)
1849 04:47:17.401732 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
1850 04:47:17.405310 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 04:47:17.411870 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 04:47:17.415169 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 04:47:17.418666 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 04:47:17.425011 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 04:47:17.428352 0 11 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
1856 04:47:17.431700 0 11 4 | B1->B0 | 2b2b 3a3a | 0 0 | (0 0) (0 0)
1857 04:47:17.435125 0 11 8 | B1->B0 | 3c3c 4646 | 1 0 | (1 1) (0 0)
1858 04:47:17.441764 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 04:47:17.445221 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 04:47:17.448647 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 04:47:17.455022 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 04:47:17.458556 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 04:47:17.461780 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1864 04:47:17.468432 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1865 04:47:17.471740 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 04:47:17.475102 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 04:47:17.481718 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 04:47:17.485302 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 04:47:17.488192 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 04:47:17.495066 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 04:47:17.498593 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 04:47:17.501578 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 04:47:17.508759 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 04:47:17.511868 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 04:47:17.515241 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 04:47:17.521862 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 04:47:17.525259 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 04:47:17.528513 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 04:47:17.531761 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 04:47:17.538283 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 04:47:17.541707 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 04:47:17.545130 Total UI for P1: 0, mck2ui 16
1883 04:47:17.548748 best dqsien dly found for B0: ( 0, 14, 6)
1884 04:47:17.551864 Total UI for P1: 0, mck2ui 16
1885 04:47:17.557931 best dqsien dly found for B1: ( 0, 14, 6)
1886 04:47:17.558619 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1887 04:47:17.562072 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1888 04:47:17.562155
1889 04:47:17.565464 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1890 04:47:17.568601 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1891 04:47:17.571859 [Gating] SW calibration Done
1892 04:47:17.571943 ==
1893 04:47:17.575236 Dram Type= 6, Freq= 0, CH_1, rank 1
1894 04:47:17.578676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1895 04:47:17.581899 ==
1896 04:47:17.581982 RX Vref Scan: 0
1897 04:47:17.582068
1898 04:47:17.585086 RX Vref 0 -> 0, step: 1
1899 04:47:17.585169
1900 04:47:17.588414 RX Delay -130 -> 252, step: 16
1901 04:47:17.591883 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1902 04:47:17.594946 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1903 04:47:17.598570 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1904 04:47:17.601814 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1905 04:47:17.608486 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1906 04:47:17.611932 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1907 04:47:17.615043 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1908 04:47:17.618548 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1909 04:47:17.622038 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1910 04:47:17.628472 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1911 04:47:17.632027 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1912 04:47:17.635129 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1913 04:47:17.638489 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1914 04:47:17.641896 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1915 04:47:17.648533 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1916 04:47:17.651905 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1917 04:47:17.651990 ==
1918 04:47:17.655424 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 04:47:17.658375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 04:47:17.658459 ==
1921 04:47:17.661958 DQS Delay:
1922 04:47:17.662041 DQS0 = 0, DQS1 = 0
1923 04:47:17.662128 DQM Delay:
1924 04:47:17.665229 DQM0 = 76, DQM1 = 71
1925 04:47:17.665312 DQ Delay:
1926 04:47:17.668301 DQ0 =77, DQ1 =69, DQ2 =61, DQ3 =77
1927 04:47:17.671876 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1928 04:47:17.674911 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1929 04:47:17.678225 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1930 04:47:17.678308
1931 04:47:17.678394
1932 04:47:17.678474 ==
1933 04:47:17.681481 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 04:47:17.688192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 04:47:17.688279 ==
1936 04:47:17.688367
1937 04:47:17.688449
1938 04:47:17.688529 TX Vref Scan disable
1939 04:47:17.691510 == TX Byte 0 ==
1940 04:47:17.695054 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1941 04:47:17.701628 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1942 04:47:17.701712 == TX Byte 1 ==
1943 04:47:17.704983 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1944 04:47:17.708275 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1945 04:47:17.711673 ==
1946 04:47:17.715052 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 04:47:17.718230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 04:47:17.718314 ==
1949 04:47:17.730783 TX Vref=22, minBit 1, minWin=27, winSum=449
1950 04:47:17.733780 TX Vref=24, minBit 1, minWin=27, winSum=448
1951 04:47:17.737230 TX Vref=26, minBit 1, minWin=27, winSum=454
1952 04:47:17.740626 TX Vref=28, minBit 1, minWin=27, winSum=451
1953 04:47:17.743624 TX Vref=30, minBit 1, minWin=27, winSum=457
1954 04:47:17.750357 TX Vref=32, minBit 1, minWin=27, winSum=456
1955 04:47:17.753848 [TxChooseVref] Worse bit 1, Min win 27, Win sum 457, Final Vref 30
1956 04:47:17.753933
1957 04:47:17.757051 Final TX Range 1 Vref 30
1958 04:47:17.757136
1959 04:47:17.757221 ==
1960 04:47:17.760527 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 04:47:17.763819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 04:47:17.763903 ==
1963 04:47:17.763989
1964 04:47:17.766954
1965 04:47:17.767037 TX Vref Scan disable
1966 04:47:17.770251 == TX Byte 0 ==
1967 04:47:17.773725 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1968 04:47:17.780273 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1969 04:47:17.780357 == TX Byte 1 ==
1970 04:47:17.783682 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1971 04:47:17.787066 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1972 04:47:17.790413
1973 04:47:17.790497 [DATLAT]
1974 04:47:17.790583 Freq=800, CH1 RK1
1975 04:47:17.790664
1976 04:47:17.793696 DATLAT Default: 0xa
1977 04:47:17.793779 0, 0xFFFF, sum = 0
1978 04:47:17.796917 1, 0xFFFF, sum = 0
1979 04:47:17.797026 2, 0xFFFF, sum = 0
1980 04:47:17.800324 3, 0xFFFF, sum = 0
1981 04:47:17.800410 4, 0xFFFF, sum = 0
1982 04:47:17.803437 5, 0xFFFF, sum = 0
1983 04:47:17.807213 6, 0xFFFF, sum = 0
1984 04:47:17.807298 7, 0xFFFF, sum = 0
1985 04:47:17.810527 8, 0xFFFF, sum = 0
1986 04:47:17.810613 9, 0x0, sum = 1
1987 04:47:17.810719 10, 0x0, sum = 2
1988 04:47:17.813388 11, 0x0, sum = 3
1989 04:47:17.813515 12, 0x0, sum = 4
1990 04:47:17.817040 best_step = 10
1991 04:47:17.817123
1992 04:47:17.817224 ==
1993 04:47:17.820166 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 04:47:17.823704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 04:47:17.823788 ==
1996 04:47:17.827014 RX Vref Scan: 0
1997 04:47:17.827098
1998 04:47:17.827198 RX Vref 0 -> 0, step: 1
1999 04:47:17.827300
2000 04:47:17.830400 RX Delay -111 -> 252, step: 8
2001 04:47:17.837039 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2002 04:47:17.840360 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2003 04:47:17.843617 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2004 04:47:17.847125 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2005 04:47:17.850465 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2006 04:47:17.857089 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2007 04:47:17.860480 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2008 04:47:17.863549 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2009 04:47:17.867132 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2010 04:47:17.870079 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2011 04:47:17.876966 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2012 04:47:17.880426 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2013 04:47:17.883707 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2014 04:47:17.887175 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2015 04:47:17.893674 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2016 04:47:17.896978 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2017 04:47:17.897083 ==
2018 04:47:17.900273 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 04:47:17.903504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 04:47:17.903609 ==
2021 04:47:17.903716 DQS Delay:
2022 04:47:17.907262 DQS0 = 0, DQS1 = 0
2023 04:47:17.907368 DQM Delay:
2024 04:47:17.910149 DQM0 = 77, DQM1 = 74
2025 04:47:17.910253 DQ Delay:
2026 04:47:17.913667 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2027 04:47:17.917063 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2028 04:47:17.920213 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2029 04:47:17.923397 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2030 04:47:17.923501
2031 04:47:17.923608
2032 04:47:17.933882 [DQSOSCAuto] RK1, (LSB)MR18= 0x253d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2033 04:47:17.933988 CH1 RK1: MR19=606, MR18=253D
2034 04:47:17.940233 CH1_RK1: MR19=0x606, MR18=0x253D, DQSOSC=394, MR23=63, INC=95, DEC=63
2035 04:47:17.943496 [RxdqsGatingPostProcess] freq 800
2036 04:47:17.950256 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2037 04:47:17.953560 Pre-setting of DQS Precalculation
2038 04:47:17.956832 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2039 04:47:17.963603 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2040 04:47:17.969970 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2041 04:47:17.973385
2042 04:47:17.973513
2043 04:47:17.973610 [Calibration Summary] 1600 Mbps
2044 04:47:17.976741 CH 0, Rank 0
2045 04:47:17.976824 SW Impedance : PASS
2046 04:47:17.980122 DUTY Scan : NO K
2047 04:47:17.983343 ZQ Calibration : PASS
2048 04:47:17.983427 Jitter Meter : NO K
2049 04:47:17.986975 CBT Training : PASS
2050 04:47:17.990109 Write leveling : PASS
2051 04:47:17.990193 RX DQS gating : PASS
2052 04:47:17.993694 RX DQ/DQS(RDDQC) : PASS
2053 04:47:17.996786 TX DQ/DQS : PASS
2054 04:47:17.996870 RX DATLAT : PASS
2055 04:47:18.000230 RX DQ/DQS(Engine): PASS
2056 04:47:18.003837 TX OE : NO K
2057 04:47:18.003922 All Pass.
2058 04:47:18.004007
2059 04:47:18.004087 CH 0, Rank 1
2060 04:47:18.007190 SW Impedance : PASS
2061 04:47:18.007274 DUTY Scan : NO K
2062 04:47:18.010482 ZQ Calibration : PASS
2063 04:47:18.013697 Jitter Meter : NO K
2064 04:47:18.013781 CBT Training : PASS
2065 04:47:18.016912 Write leveling : PASS
2066 04:47:18.020234 RX DQS gating : PASS
2067 04:47:18.020318 RX DQ/DQS(RDDQC) : PASS
2068 04:47:18.023758 TX DQ/DQS : PASS
2069 04:47:18.027024 RX DATLAT : PASS
2070 04:47:18.027108 RX DQ/DQS(Engine): PASS
2071 04:47:18.030161 TX OE : NO K
2072 04:47:18.030246 All Pass.
2073 04:47:18.030331
2074 04:47:18.033708 CH 1, Rank 0
2075 04:47:18.033792 SW Impedance : PASS
2076 04:47:18.036767 DUTY Scan : NO K
2077 04:47:18.040349 ZQ Calibration : PASS
2078 04:47:18.040434 Jitter Meter : NO K
2079 04:47:18.043567 CBT Training : PASS
2080 04:47:18.046906 Write leveling : PASS
2081 04:47:18.046990 RX DQS gating : PASS
2082 04:47:18.050346 RX DQ/DQS(RDDQC) : PASS
2083 04:47:18.050428 TX DQ/DQS : PASS
2084 04:47:18.053577 RX DATLAT : PASS
2085 04:47:18.056836 RX DQ/DQS(Engine): PASS
2086 04:47:18.056925 TX OE : NO K
2087 04:47:18.060248 All Pass.
2088 04:47:18.060332
2089 04:47:18.060417 CH 1, Rank 1
2090 04:47:18.063493 SW Impedance : PASS
2091 04:47:18.063570 DUTY Scan : NO K
2092 04:47:18.066822 ZQ Calibration : PASS
2093 04:47:18.070325 Jitter Meter : NO K
2094 04:47:18.070406 CBT Training : PASS
2095 04:47:18.073815 Write leveling : PASS
2096 04:47:18.076962 RX DQS gating : PASS
2097 04:47:18.077046 RX DQ/DQS(RDDQC) : PASS
2098 04:47:18.080376 TX DQ/DQS : PASS
2099 04:47:18.083849 RX DATLAT : PASS
2100 04:47:18.083933 RX DQ/DQS(Engine): PASS
2101 04:47:18.087059 TX OE : NO K
2102 04:47:18.087143 All Pass.
2103 04:47:18.087228
2104 04:47:18.090087 DramC Write-DBI off
2105 04:47:18.093652 PER_BANK_REFRESH: Hybrid Mode
2106 04:47:18.093736 TX_TRACKING: ON
2107 04:47:18.097308 [GetDramInforAfterCalByMRR] Vendor 6.
2108 04:47:18.100197 [GetDramInforAfterCalByMRR] Revision 606.
2109 04:47:18.103535 [GetDramInforAfterCalByMRR] Revision 2 0.
2110 04:47:18.107128 MR0 0x3b3b
2111 04:47:18.107213 MR8 0x5151
2112 04:47:18.110292 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 04:47:18.110376
2114 04:47:18.110462 MR0 0x3b3b
2115 04:47:18.113528 MR8 0x5151
2116 04:47:18.116826 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 04:47:18.116928
2118 04:47:18.123802 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2119 04:47:18.130454 [FAST_K] Save calibration result to emmc
2120 04:47:18.133622 [FAST_K] Save calibration result to emmc
2121 04:47:18.133712 dram_init: config_dvfs: 1
2122 04:47:18.137105 dramc_set_vcore_voltage set vcore to 662500
2123 04:47:18.140392 Read voltage for 1200, 2
2124 04:47:18.140482 Vio18 = 0
2125 04:47:18.143749 Vcore = 662500
2126 04:47:18.143839 Vdram = 0
2127 04:47:18.143930 Vddq = 0
2128 04:47:18.146974 Vmddr = 0
2129 04:47:18.150368 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2130 04:47:18.156852 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2131 04:47:18.156942 MEM_TYPE=3, freq_sel=15
2132 04:47:18.160436 sv_algorithm_assistance_LP4_1600
2133 04:47:18.167100 ============ PULL DRAM RESETB DOWN ============
2134 04:47:18.170192 ========== PULL DRAM RESETB DOWN end =========
2135 04:47:18.173694 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2136 04:47:18.176657 ===================================
2137 04:47:18.180254 LPDDR4 DRAM CONFIGURATION
2138 04:47:18.183351 ===================================
2139 04:47:18.187105 EX_ROW_EN[0] = 0x0
2140 04:47:18.187189 EX_ROW_EN[1] = 0x0
2141 04:47:18.190274 LP4Y_EN = 0x0
2142 04:47:18.190357 WORK_FSP = 0x0
2143 04:47:18.193434 WL = 0x4
2144 04:47:18.193564 RL = 0x4
2145 04:47:18.196634 BL = 0x2
2146 04:47:18.196718 RPST = 0x0
2147 04:47:18.200149 RD_PRE = 0x0
2148 04:47:18.200233 WR_PRE = 0x1
2149 04:47:18.203823 WR_PST = 0x0
2150 04:47:18.203907 DBI_WR = 0x0
2151 04:47:18.206837 DBI_RD = 0x0
2152 04:47:18.206921 OTF = 0x1
2153 04:47:18.210319 ===================================
2154 04:47:18.213418 ===================================
2155 04:47:18.216995 ANA top config
2156 04:47:18.220073 ===================================
2157 04:47:18.223355 DLL_ASYNC_EN = 0
2158 04:47:18.223464 ALL_SLAVE_EN = 0
2159 04:47:18.226973 NEW_RANK_MODE = 1
2160 04:47:18.230122 DLL_IDLE_MODE = 1
2161 04:47:18.233190 LP45_APHY_COMB_EN = 1
2162 04:47:18.233274 TX_ODT_DIS = 1
2163 04:47:18.236713 NEW_8X_MODE = 1
2164 04:47:18.240001 ===================================
2165 04:47:18.243328 ===================================
2166 04:47:18.246648 data_rate = 2400
2167 04:47:18.249861 CKR = 1
2168 04:47:18.253357 DQ_P2S_RATIO = 8
2169 04:47:18.256717 ===================================
2170 04:47:18.259888 CA_P2S_RATIO = 8
2171 04:47:18.259972 DQ_CA_OPEN = 0
2172 04:47:18.263236 DQ_SEMI_OPEN = 0
2173 04:47:18.266361 CA_SEMI_OPEN = 0
2174 04:47:18.269850 CA_FULL_RATE = 0
2175 04:47:18.272957 DQ_CKDIV4_EN = 0
2176 04:47:18.276326 CA_CKDIV4_EN = 0
2177 04:47:18.276410 CA_PREDIV_EN = 0
2178 04:47:18.279857 PH8_DLY = 17
2179 04:47:18.283089 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2180 04:47:18.286246 DQ_AAMCK_DIV = 4
2181 04:47:18.289610 CA_AAMCK_DIV = 4
2182 04:47:18.292951 CA_ADMCK_DIV = 4
2183 04:47:18.293035 DQ_TRACK_CA_EN = 0
2184 04:47:18.296711 CA_PICK = 1200
2185 04:47:18.299569 CA_MCKIO = 1200
2186 04:47:18.302930 MCKIO_SEMI = 0
2187 04:47:18.306658 PLL_FREQ = 2366
2188 04:47:18.309460 DQ_UI_PI_RATIO = 32
2189 04:47:18.313123 CA_UI_PI_RATIO = 0
2190 04:47:18.316538 ===================================
2191 04:47:18.319712 ===================================
2192 04:47:18.319805 memory_type:LPDDR4
2193 04:47:18.322826 GP_NUM : 10
2194 04:47:18.326670 SRAM_EN : 1
2195 04:47:18.326754 MD32_EN : 0
2196 04:47:18.329644 ===================================
2197 04:47:18.333160 [ANA_INIT] >>>>>>>>>>>>>>
2198 04:47:18.336179 <<<<<< [CONFIGURE PHASE]: ANA_TX
2199 04:47:18.339869 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2200 04:47:18.343079 ===================================
2201 04:47:18.346207 data_rate = 2400,PCW = 0X5b00
2202 04:47:18.349734 ===================================
2203 04:47:18.353041 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2204 04:47:18.356062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 04:47:18.363004 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 04:47:18.366293 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2207 04:47:18.369868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2208 04:47:18.372913 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2209 04:47:18.376072 [ANA_INIT] flow start
2210 04:47:18.379516 [ANA_INIT] PLL >>>>>>>>
2211 04:47:18.379600 [ANA_INIT] PLL <<<<<<<<
2212 04:47:18.382896 [ANA_INIT] MIDPI >>>>>>>>
2213 04:47:18.386145 [ANA_INIT] MIDPI <<<<<<<<
2214 04:47:18.386229 [ANA_INIT] DLL >>>>>>>>
2215 04:47:18.389439 [ANA_INIT] DLL <<<<<<<<
2216 04:47:18.392923 [ANA_INIT] flow end
2217 04:47:18.396369 ============ LP4 DIFF to SE enter ============
2218 04:47:18.399627 ============ LP4 DIFF to SE exit ============
2219 04:47:18.403396 [ANA_INIT] <<<<<<<<<<<<<
2220 04:47:18.406196 [Flow] Enable top DCM control >>>>>
2221 04:47:18.409803 [Flow] Enable top DCM control <<<<<
2222 04:47:18.413211 Enable DLL master slave shuffle
2223 04:47:18.416512 ==============================================================
2224 04:47:18.419540 Gating Mode config
2225 04:47:18.426240 ==============================================================
2226 04:47:18.426325 Config description:
2227 04:47:18.436442 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2228 04:47:18.443249 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2229 04:47:18.446186 SELPH_MODE 0: By rank 1: By Phase
2230 04:47:18.453162 ==============================================================
2231 04:47:18.456450 GAT_TRACK_EN = 1
2232 04:47:18.459573 RX_GATING_MODE = 2
2233 04:47:18.462947 RX_GATING_TRACK_MODE = 2
2234 04:47:18.466462 SELPH_MODE = 1
2235 04:47:18.469816 PICG_EARLY_EN = 1
2236 04:47:18.469900 VALID_LAT_VALUE = 1
2237 04:47:18.476323 ==============================================================
2238 04:47:18.480014 Enter into Gating configuration >>>>
2239 04:47:18.483045 Exit from Gating configuration <<<<
2240 04:47:18.486579 Enter into DVFS_PRE_config >>>>>
2241 04:47:18.496191 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2242 04:47:18.499796 Exit from DVFS_PRE_config <<<<<
2243 04:47:18.502920 Enter into PICG configuration >>>>
2244 04:47:18.506242 Exit from PICG configuration <<<<
2245 04:47:18.509460 [RX_INPUT] configuration >>>>>
2246 04:47:18.512962 [RX_INPUT] configuration <<<<<
2247 04:47:18.516212 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2248 04:47:18.522814 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2249 04:47:18.529533 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 04:47:18.536210 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 04:47:18.542871 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 04:47:18.549651 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 04:47:18.552824 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2254 04:47:18.556306 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2255 04:47:18.559788 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2256 04:47:18.562577 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2257 04:47:18.569646 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2258 04:47:18.572644 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2259 04:47:18.575975 ===================================
2260 04:47:18.579582 LPDDR4 DRAM CONFIGURATION
2261 04:47:18.582780 ===================================
2262 04:47:18.582862 EX_ROW_EN[0] = 0x0
2263 04:47:18.586016 EX_ROW_EN[1] = 0x0
2264 04:47:18.586098 LP4Y_EN = 0x0
2265 04:47:18.589430 WORK_FSP = 0x0
2266 04:47:18.589549 WL = 0x4
2267 04:47:18.592716 RL = 0x4
2268 04:47:18.592797 BL = 0x2
2269 04:47:18.596120 RPST = 0x0
2270 04:47:18.599351 RD_PRE = 0x0
2271 04:47:18.599432 WR_PRE = 0x1
2272 04:47:18.602715 WR_PST = 0x0
2273 04:47:18.602796 DBI_WR = 0x0
2274 04:47:18.605986 DBI_RD = 0x0
2275 04:47:18.606068 OTF = 0x1
2276 04:47:18.609360 ===================================
2277 04:47:18.612493 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2278 04:47:18.615928 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2279 04:47:18.622554 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2280 04:47:18.625895 ===================================
2281 04:47:18.629363 LPDDR4 DRAM CONFIGURATION
2282 04:47:18.632529 ===================================
2283 04:47:18.632610 EX_ROW_EN[0] = 0x10
2284 04:47:18.636043 EX_ROW_EN[1] = 0x0
2285 04:47:18.636156 LP4Y_EN = 0x0
2286 04:47:18.639647 WORK_FSP = 0x0
2287 04:47:18.639728 WL = 0x4
2288 04:47:18.642631 RL = 0x4
2289 04:47:18.642712 BL = 0x2
2290 04:47:18.646166 RPST = 0x0
2291 04:47:18.646247 RD_PRE = 0x0
2292 04:47:18.649637 WR_PRE = 0x1
2293 04:47:18.649718 WR_PST = 0x0
2294 04:47:18.652622 DBI_WR = 0x0
2295 04:47:18.652703 DBI_RD = 0x0
2296 04:47:18.656248 OTF = 0x1
2297 04:47:18.659442 ===================================
2298 04:47:18.665723 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2299 04:47:18.665805 ==
2300 04:47:18.669225 Dram Type= 6, Freq= 0, CH_0, rank 0
2301 04:47:18.672537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2302 04:47:18.672618 ==
2303 04:47:18.675883 [Duty_Offset_Calibration]
2304 04:47:18.675964 B0:2 B1:0 CA:3
2305 04:47:18.676029
2306 04:47:18.679072 [DutyScan_Calibration_Flow] k_type=0
2307 04:47:18.689796
2308 04:47:18.689876 ==CLK 0==
2309 04:47:18.693066 Final CLK duty delay cell = 0
2310 04:47:18.696354 [0] MAX Duty = 5031%(X100), DQS PI = 12
2311 04:47:18.699754 [0] MIN Duty = 4875%(X100), DQS PI = 58
2312 04:47:18.699838 [0] AVG Duty = 4953%(X100)
2313 04:47:18.703304
2314 04:47:18.706290 CH0 CLK Duty spec in!! Max-Min= 156%
2315 04:47:18.710017 [DutyScan_Calibration_Flow] ====Done====
2316 04:47:18.710100
2317 04:47:18.712944 [DutyScan_Calibration_Flow] k_type=1
2318 04:47:18.729088
2319 04:47:18.729168 ==DQS 0 ==
2320 04:47:18.732088 Final DQS duty delay cell = 0
2321 04:47:18.735765 [0] MAX Duty = 5062%(X100), DQS PI = 12
2322 04:47:18.738955 [0] MIN Duty = 4907%(X100), DQS PI = 2
2323 04:47:18.742097 [0] AVG Duty = 4984%(X100)
2324 04:47:18.742172
2325 04:47:18.742234 ==DQS 1 ==
2326 04:47:18.745596 Final DQS duty delay cell = 0
2327 04:47:18.748761 [0] MAX Duty = 5125%(X100), DQS PI = 34
2328 04:47:18.752187 [0] MIN Duty = 5031%(X100), DQS PI = 0
2329 04:47:18.755609 [0] AVG Duty = 5078%(X100)
2330 04:47:18.755685
2331 04:47:18.758823 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2332 04:47:18.758905
2333 04:47:18.762466 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2334 04:47:18.765573 [DutyScan_Calibration_Flow] ====Done====
2335 04:47:18.765647
2336 04:47:18.768975 [DutyScan_Calibration_Flow] k_type=3
2337 04:47:18.786347
2338 04:47:18.786448 ==DQM 0 ==
2339 04:47:18.789740 Final DQM duty delay cell = 0
2340 04:47:18.792665 [0] MAX Duty = 5124%(X100), DQS PI = 10
2341 04:47:18.796148 [0] MIN Duty = 4876%(X100), DQS PI = 0
2342 04:47:18.796223 [0] AVG Duty = 5000%(X100)
2343 04:47:18.799580
2344 04:47:18.799652 ==DQM 1 ==
2345 04:47:18.803092 Final DQM duty delay cell = 4
2346 04:47:18.806284 [4] MAX Duty = 5124%(X100), DQS PI = 50
2347 04:47:18.809776 [4] MIN Duty = 5031%(X100), DQS PI = 12
2348 04:47:18.809851 [4] AVG Duty = 5077%(X100)
2349 04:47:18.812775
2350 04:47:18.816081 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2351 04:47:18.816167
2352 04:47:18.819472 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2353 04:47:18.822747 [DutyScan_Calibration_Flow] ====Done====
2354 04:47:18.822818
2355 04:47:18.825872 [DutyScan_Calibration_Flow] k_type=2
2356 04:47:18.840953
2357 04:47:18.841058 ==DQ 0 ==
2358 04:47:18.844331 Final DQ duty delay cell = -4
2359 04:47:18.847585 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2360 04:47:18.851119 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2361 04:47:18.854230 [-4] AVG Duty = 4969%(X100)
2362 04:47:18.854310
2363 04:47:18.854374 ==DQ 1 ==
2364 04:47:18.857660 Final DQ duty delay cell = -4
2365 04:47:18.860619 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2366 04:47:18.864138 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2367 04:47:18.867648 [-4] AVG Duty = 4922%(X100)
2368 04:47:18.867728
2369 04:47:18.870844 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2370 04:47:18.870924
2371 04:47:18.874048 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2372 04:47:18.877658 [DutyScan_Calibration_Flow] ====Done====
2373 04:47:18.877739 ==
2374 04:47:18.881123 Dram Type= 6, Freq= 0, CH_1, rank 0
2375 04:47:18.884091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2376 04:47:18.884175 ==
2377 04:47:18.887480 [Duty_Offset_Calibration]
2378 04:47:18.887560 B0:1 B1:-2 CA:1
2379 04:47:18.887624
2380 04:47:18.890785 [DutyScan_Calibration_Flow] k_type=0
2381 04:47:18.901265
2382 04:47:18.901345 ==CLK 0==
2383 04:47:18.904883 Final CLK duty delay cell = 0
2384 04:47:18.908015 [0] MAX Duty = 5031%(X100), DQS PI = 18
2385 04:47:18.911584 [0] MIN Duty = 4875%(X100), DQS PI = 58
2386 04:47:18.911664 [0] AVG Duty = 4953%(X100)
2387 04:47:18.914915
2388 04:47:18.918198 CH1 CLK Duty spec in!! Max-Min= 156%
2389 04:47:18.921629 [DutyScan_Calibration_Flow] ====Done====
2390 04:47:18.921710
2391 04:47:18.924645 [DutyScan_Calibration_Flow] k_type=1
2392 04:47:18.939981
2393 04:47:18.940074 ==DQS 0 ==
2394 04:47:18.943313 Final DQS duty delay cell = -4
2395 04:47:18.946360 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2396 04:47:18.949682 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2397 04:47:18.953047 [-4] AVG Duty = 4969%(X100)
2398 04:47:18.953148
2399 04:47:18.953238 ==DQS 1 ==
2400 04:47:18.956565 Final DQS duty delay cell = 0
2401 04:47:18.959704 [0] MAX Duty = 5093%(X100), DQS PI = 0
2402 04:47:18.963159 [0] MIN Duty = 4875%(X100), DQS PI = 26
2403 04:47:18.966521 [0] AVG Duty = 4984%(X100)
2404 04:47:18.966597
2405 04:47:18.969677 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2406 04:47:18.969754
2407 04:47:18.973083 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2408 04:47:18.976322 [DutyScan_Calibration_Flow] ====Done====
2409 04:47:18.976413
2410 04:47:18.979713 [DutyScan_Calibration_Flow] k_type=3
2411 04:47:18.997391
2412 04:47:18.997515 ==DQM 0 ==
2413 04:47:19.000876 Final DQM duty delay cell = 4
2414 04:47:19.004002 [4] MAX Duty = 5156%(X100), DQS PI = 20
2415 04:47:19.007366 [4] MIN Duty = 5000%(X100), DQS PI = 52
2416 04:47:19.007448 [4] AVG Duty = 5078%(X100)
2417 04:47:19.010668
2418 04:47:19.010749 ==DQM 1 ==
2419 04:47:19.014116 Final DQM duty delay cell = 0
2420 04:47:19.017179 [0] MAX Duty = 5031%(X100), DQS PI = 34
2421 04:47:19.020611 [0] MIN Duty = 4907%(X100), DQS PI = 2
2422 04:47:19.020692 [0] AVG Duty = 4969%(X100)
2423 04:47:19.024243
2424 04:47:19.027237 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2425 04:47:19.027319
2426 04:47:19.030677 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2427 04:47:19.033972 [DutyScan_Calibration_Flow] ====Done====
2428 04:47:19.034053
2429 04:47:19.037290 [DutyScan_Calibration_Flow] k_type=2
2430 04:47:19.053675
2431 04:47:19.053756 ==DQ 0 ==
2432 04:47:19.057222 Final DQ duty delay cell = 0
2433 04:47:19.060223 [0] MAX Duty = 5062%(X100), DQS PI = 10
2434 04:47:19.063855 [0] MIN Duty = 4938%(X100), DQS PI = 52
2435 04:47:19.063937 [0] AVG Duty = 5000%(X100)
2436 04:47:19.067208
2437 04:47:19.067289 ==DQ 1 ==
2438 04:47:19.070361 Final DQ duty delay cell = 0
2439 04:47:19.073678 [0] MAX Duty = 5093%(X100), DQS PI = 20
2440 04:47:19.076999 [0] MIN Duty = 4969%(X100), DQS PI = 26
2441 04:47:19.077123 [0] AVG Duty = 5031%(X100)
2442 04:47:19.077190
2443 04:47:19.080488 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2444 04:47:19.083718
2445 04:47:19.087200 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2446 04:47:19.090230 [DutyScan_Calibration_Flow] ====Done====
2447 04:47:19.093727 nWR fixed to 30
2448 04:47:19.093809 [ModeRegInit_LP4] CH0 RK0
2449 04:47:19.097217 [ModeRegInit_LP4] CH0 RK1
2450 04:47:19.100238 [ModeRegInit_LP4] CH1 RK0
2451 04:47:19.100319 [ModeRegInit_LP4] CH1 RK1
2452 04:47:19.104029 match AC timing 7
2453 04:47:19.106892 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2454 04:47:19.110462 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2455 04:47:19.117045 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2456 04:47:19.120286 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2457 04:47:19.127151 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2458 04:47:19.127232 ==
2459 04:47:19.130639 Dram Type= 6, Freq= 0, CH_0, rank 0
2460 04:47:19.133956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2461 04:47:19.134038 ==
2462 04:47:19.140476 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2463 04:47:19.144223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2464 04:47:19.153926 [CA 0] Center 40 (10~71) winsize 62
2465 04:47:19.157145 [CA 1] Center 39 (9~70) winsize 62
2466 04:47:19.160783 [CA 2] Center 36 (6~66) winsize 61
2467 04:47:19.163888 [CA 3] Center 35 (5~66) winsize 62
2468 04:47:19.167507 [CA 4] Center 34 (4~65) winsize 62
2469 04:47:19.170544 [CA 5] Center 33 (3~64) winsize 62
2470 04:47:19.170626
2471 04:47:19.173789 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2472 04:47:19.173875
2473 04:47:19.177449 [CATrainingPosCal] consider 1 rank data
2474 04:47:19.180652 u2DelayCellTimex100 = 270/100 ps
2475 04:47:19.183961 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2476 04:47:19.187563 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2477 04:47:19.194059 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2478 04:47:19.197252 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2479 04:47:19.200450 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2480 04:47:19.203916 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2481 04:47:19.204023
2482 04:47:19.207280 CA PerBit enable=1, Macro0, CA PI delay=33
2483 04:47:19.207363
2484 04:47:19.210719 [CBTSetCACLKResult] CA Dly = 33
2485 04:47:19.210800 CS Dly: 7 (0~38)
2486 04:47:19.210866 ==
2487 04:47:19.214058 Dram Type= 6, Freq= 0, CH_0, rank 1
2488 04:47:19.220667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 04:47:19.220781 ==
2490 04:47:19.224175 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 04:47:19.230900 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2492 04:47:19.239939 [CA 0] Center 40 (10~70) winsize 61
2493 04:47:19.243419 [CA 1] Center 39 (9~70) winsize 62
2494 04:47:19.246461 [CA 2] Center 36 (6~66) winsize 61
2495 04:47:19.250103 [CA 3] Center 35 (5~66) winsize 62
2496 04:47:19.253242 [CA 4] Center 34 (3~65) winsize 63
2497 04:47:19.256606 [CA 5] Center 33 (3~64) winsize 62
2498 04:47:19.256687
2499 04:47:19.259823 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2500 04:47:19.259904
2501 04:47:19.263188 [CATrainingPosCal] consider 2 rank data
2502 04:47:19.266671 u2DelayCellTimex100 = 270/100 ps
2503 04:47:19.269915 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2504 04:47:19.276527 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2505 04:47:19.279952 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2506 04:47:19.283050 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2507 04:47:19.286570 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2508 04:47:19.289683 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2509 04:47:19.289764
2510 04:47:19.292974 CA PerBit enable=1, Macro0, CA PI delay=33
2511 04:47:19.293055
2512 04:47:19.296366 [CBTSetCACLKResult] CA Dly = 33
2513 04:47:19.296447 CS Dly: 8 (0~40)
2514 04:47:19.299625
2515 04:47:19.302974 ----->DramcWriteLeveling(PI) begin...
2516 04:47:19.303057 ==
2517 04:47:19.306568 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 04:47:19.309425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 04:47:19.309545 ==
2520 04:47:19.313087 Write leveling (Byte 0): 34 => 34
2521 04:47:19.316301 Write leveling (Byte 1): 30 => 30
2522 04:47:19.319621 DramcWriteLeveling(PI) end<-----
2523 04:47:19.319702
2524 04:47:19.319766 ==
2525 04:47:19.322811 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 04:47:19.326468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 04:47:19.326550 ==
2528 04:47:19.329538 [Gating] SW mode calibration
2529 04:47:19.336072 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2530 04:47:19.342823 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2531 04:47:19.346339 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2532 04:47:19.349449 0 15 4 | B1->B0 | 2626 3333 | 1 0 | (0 0) (0 0)
2533 04:47:19.356211 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 04:47:19.359767 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 04:47:19.362891 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 04:47:19.369512 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 04:47:19.373112 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 04:47:19.376302 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2539 04:47:19.379664 1 0 0 | B1->B0 | 3232 2c2c | 0 1 | (0 1) (1 0)
2540 04:47:19.386177 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 04:47:19.389743 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 04:47:19.392992 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 04:47:19.399451 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 04:47:19.402735 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 04:47:19.406348 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 04:47:19.412915 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 04:47:19.416077 1 1 0 | B1->B0 | 2b2b 3131 | 0 0 | (0 0) (0 0)
2548 04:47:19.419461 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 04:47:19.426120 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 04:47:19.429689 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 04:47:19.432648 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 04:47:19.439561 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 04:47:19.442742 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 04:47:19.445893 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2555 04:47:19.452540 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2556 04:47:19.456086 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 04:47:19.459486 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 04:47:19.465987 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 04:47:19.469347 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 04:47:19.472745 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 04:47:19.479412 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 04:47:19.482714 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 04:47:19.486132 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 04:47:19.489311 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 04:47:19.495909 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 04:47:19.499305 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 04:47:19.502559 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 04:47:19.509232 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 04:47:19.512461 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 04:47:19.515934 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2571 04:47:19.522626 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2572 04:47:19.525945 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 04:47:19.529266 Total UI for P1: 0, mck2ui 16
2574 04:47:19.532327 best dqsien dly found for B0: ( 1, 3, 30)
2575 04:47:19.535970 Total UI for P1: 0, mck2ui 16
2576 04:47:19.539202 best dqsien dly found for B1: ( 1, 4, 2)
2577 04:47:19.542522 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2578 04:47:19.545880 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2579 04:47:19.545996
2580 04:47:19.549461 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2581 04:47:19.552606 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2582 04:47:19.556022 [Gating] SW calibration Done
2583 04:47:19.556104 ==
2584 04:47:19.559171 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 04:47:19.562348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 04:47:19.565513 ==
2587 04:47:19.565608 RX Vref Scan: 0
2588 04:47:19.565673
2589 04:47:19.569164 RX Vref 0 -> 0, step: 1
2590 04:47:19.569245
2591 04:47:19.572297 RX Delay -40 -> 252, step: 8
2592 04:47:19.575738 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2593 04:47:19.579209 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2594 04:47:19.582186 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
2595 04:47:19.585941 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2596 04:47:19.589009 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2597 04:47:19.595881 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2598 04:47:19.599169 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2599 04:47:19.602784 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2600 04:47:19.605771 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2601 04:47:19.609110 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2602 04:47:19.615863 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2603 04:47:19.619116 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2604 04:47:19.622715 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2605 04:47:19.625633 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2606 04:47:19.629199 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2607 04:47:19.635802 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2608 04:47:19.635899 ==
2609 04:47:19.638903 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 04:47:19.642558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 04:47:19.642640 ==
2612 04:47:19.642706 DQS Delay:
2613 04:47:19.645467 DQS0 = 0, DQS1 = 0
2614 04:47:19.645589 DQM Delay:
2615 04:47:19.649125 DQM0 = 111, DQM1 = 102
2616 04:47:19.649207 DQ Delay:
2617 04:47:19.652266 DQ0 =111, DQ1 =111, DQ2 =107, DQ3 =107
2618 04:47:19.655768 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2619 04:47:19.659184 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2620 04:47:19.662525 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2621 04:47:19.662607
2622 04:47:19.662671
2623 04:47:19.662731 ==
2624 04:47:19.665623 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 04:47:19.672283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 04:47:19.672365 ==
2627 04:47:19.672430
2628 04:47:19.672519
2629 04:47:19.672576 TX Vref Scan disable
2630 04:47:19.676038 == TX Byte 0 ==
2631 04:47:19.679514 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2632 04:47:19.686006 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2633 04:47:19.686088 == TX Byte 1 ==
2634 04:47:19.689813 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2635 04:47:19.696224 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2636 04:47:19.696306 ==
2637 04:47:19.699542 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 04:47:19.702597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 04:47:19.702679 ==
2640 04:47:19.714355 TX Vref=22, minBit 4, minWin=25, winSum=416
2641 04:47:19.717636 TX Vref=24, minBit 7, minWin=25, winSum=423
2642 04:47:19.721070 TX Vref=26, minBit 0, minWin=26, winSum=434
2643 04:47:19.724333 TX Vref=28, minBit 2, minWin=26, winSum=437
2644 04:47:19.727743 TX Vref=30, minBit 2, minWin=26, winSum=434
2645 04:47:19.734511 TX Vref=32, minBit 1, minWin=26, winSum=427
2646 04:47:19.737765 [TxChooseVref] Worse bit 2, Min win 26, Win sum 437, Final Vref 28
2647 04:47:19.737848
2648 04:47:19.740663 Final TX Range 1 Vref 28
2649 04:47:19.740745
2650 04:47:19.740810 ==
2651 04:47:19.744318 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 04:47:19.747612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 04:47:19.747694 ==
2654 04:47:19.747758
2655 04:47:19.750981
2656 04:47:19.751062 TX Vref Scan disable
2657 04:47:19.754283 == TX Byte 0 ==
2658 04:47:19.757401 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2659 04:47:19.760840 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2660 04:47:19.764024 == TX Byte 1 ==
2661 04:47:19.767453 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2662 04:47:19.770973 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2663 04:47:19.771055
2664 04:47:19.774212 [DATLAT]
2665 04:47:19.774294 Freq=1200, CH0 RK0
2666 04:47:19.774360
2667 04:47:19.777462 DATLAT Default: 0xd
2668 04:47:19.777568 0, 0xFFFF, sum = 0
2669 04:47:19.780700 1, 0xFFFF, sum = 0
2670 04:47:19.780782 2, 0xFFFF, sum = 0
2671 04:47:19.784071 3, 0xFFFF, sum = 0
2672 04:47:19.784154 4, 0xFFFF, sum = 0
2673 04:47:19.787648 5, 0xFFFF, sum = 0
2674 04:47:19.790781 6, 0xFFFF, sum = 0
2675 04:47:19.790863 7, 0xFFFF, sum = 0
2676 04:47:19.793962 8, 0xFFFF, sum = 0
2677 04:47:19.794044 9, 0xFFFF, sum = 0
2678 04:47:19.797684 10, 0xFFFF, sum = 0
2679 04:47:19.797766 11, 0xFFFF, sum = 0
2680 04:47:19.800623 12, 0x0, sum = 1
2681 04:47:19.800706 13, 0x0, sum = 2
2682 04:47:19.804270 14, 0x0, sum = 3
2683 04:47:19.804352 15, 0x0, sum = 4
2684 04:47:19.804418 best_step = 13
2685 04:47:19.804478
2686 04:47:19.807260 ==
2687 04:47:19.810534 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 04:47:19.813907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 04:47:19.813989 ==
2690 04:47:19.814055 RX Vref Scan: 1
2691 04:47:19.814116
2692 04:47:19.817441 Set Vref Range= 32 -> 127
2693 04:47:19.817564
2694 04:47:19.820665 RX Vref 32 -> 127, step: 1
2695 04:47:19.820773
2696 04:47:19.823840 RX Delay -37 -> 252, step: 4
2697 04:47:19.823921
2698 04:47:19.827247 Set Vref, RX VrefLevel [Byte0]: 32
2699 04:47:19.830603 [Byte1]: 32
2700 04:47:19.830708
2701 04:47:19.833916 Set Vref, RX VrefLevel [Byte0]: 33
2702 04:47:19.836922 [Byte1]: 33
2703 04:47:19.840485
2704 04:47:19.840573 Set Vref, RX VrefLevel [Byte0]: 34
2705 04:47:19.843973 [Byte1]: 34
2706 04:47:19.848503
2707 04:47:19.848600 Set Vref, RX VrefLevel [Byte0]: 35
2708 04:47:19.852125 [Byte1]: 35
2709 04:47:19.856523
2710 04:47:19.856610 Set Vref, RX VrefLevel [Byte0]: 36
2711 04:47:19.860044 [Byte1]: 36
2712 04:47:19.864899
2713 04:47:19.864988 Set Vref, RX VrefLevel [Byte0]: 37
2714 04:47:19.867972 [Byte1]: 37
2715 04:47:19.872673
2716 04:47:19.872754 Set Vref, RX VrefLevel [Byte0]: 38
2717 04:47:19.876026 [Byte1]: 38
2718 04:47:19.880848
2719 04:47:19.880928 Set Vref, RX VrefLevel [Byte0]: 39
2720 04:47:19.883839 [Byte1]: 39
2721 04:47:19.888442
2722 04:47:19.888523 Set Vref, RX VrefLevel [Byte0]: 40
2723 04:47:19.891855 [Byte1]: 40
2724 04:47:19.896572
2725 04:47:19.896653 Set Vref, RX VrefLevel [Byte0]: 41
2726 04:47:19.900095 [Byte1]: 41
2727 04:47:19.904425
2728 04:47:19.904505 Set Vref, RX VrefLevel [Byte0]: 42
2729 04:47:19.907851 [Byte1]: 42
2730 04:47:19.912579
2731 04:47:19.912660 Set Vref, RX VrefLevel [Byte0]: 43
2732 04:47:19.915854 [Byte1]: 43
2733 04:47:19.920505
2734 04:47:19.920594 Set Vref, RX VrefLevel [Byte0]: 44
2735 04:47:19.923777 [Byte1]: 44
2736 04:47:19.928544
2737 04:47:19.928634 Set Vref, RX VrefLevel [Byte0]: 45
2738 04:47:19.931786 [Byte1]: 45
2739 04:47:19.936724
2740 04:47:19.936824 Set Vref, RX VrefLevel [Byte0]: 46
2741 04:47:19.939983 [Byte1]: 46
2742 04:47:19.944507
2743 04:47:19.944603 Set Vref, RX VrefLevel [Byte0]: 47
2744 04:47:19.947743 [Byte1]: 47
2745 04:47:19.952702
2746 04:47:19.952811 Set Vref, RX VrefLevel [Byte0]: 48
2747 04:47:19.955989 [Byte1]: 48
2748 04:47:19.960556
2749 04:47:19.960632 Set Vref, RX VrefLevel [Byte0]: 49
2750 04:47:19.963995 [Byte1]: 49
2751 04:47:19.968743
2752 04:47:19.971680 Set Vref, RX VrefLevel [Byte0]: 50
2753 04:47:19.975146 [Byte1]: 50
2754 04:47:19.975228
2755 04:47:19.978577 Set Vref, RX VrefLevel [Byte0]: 51
2756 04:47:19.982017 [Byte1]: 51
2757 04:47:19.982099
2758 04:47:19.985281 Set Vref, RX VrefLevel [Byte0]: 52
2759 04:47:19.988545 [Byte1]: 52
2760 04:47:19.992795
2761 04:47:19.993032 Set Vref, RX VrefLevel [Byte0]: 53
2762 04:47:19.996195 [Byte1]: 53
2763 04:47:20.000579
2764 04:47:20.000735 Set Vref, RX VrefLevel [Byte0]: 54
2765 04:47:20.004049 [Byte1]: 54
2766 04:47:20.008842
2767 04:47:20.008958 Set Vref, RX VrefLevel [Byte0]: 55
2768 04:47:20.011983 [Byte1]: 55
2769 04:47:20.016796
2770 04:47:20.016900 Set Vref, RX VrefLevel [Byte0]: 56
2771 04:47:20.020108 [Byte1]: 56
2772 04:47:20.024884
2773 04:47:20.024969 Set Vref, RX VrefLevel [Byte0]: 57
2774 04:47:20.027839 [Byte1]: 57
2775 04:47:20.032488
2776 04:47:20.032568 Set Vref, RX VrefLevel [Byte0]: 58
2777 04:47:20.035995 [Byte1]: 58
2778 04:47:20.040650
2779 04:47:20.040731 Set Vref, RX VrefLevel [Byte0]: 59
2780 04:47:20.043992 [Byte1]: 59
2781 04:47:20.048558
2782 04:47:20.048639 Set Vref, RX VrefLevel [Byte0]: 60
2783 04:47:20.051949 [Byte1]: 60
2784 04:47:20.056828
2785 04:47:20.056913 Set Vref, RX VrefLevel [Byte0]: 61
2786 04:47:20.060015 [Byte1]: 61
2787 04:47:20.064611
2788 04:47:20.064693 Set Vref, RX VrefLevel [Byte0]: 62
2789 04:47:20.067849 [Byte1]: 62
2790 04:47:20.073076
2791 04:47:20.073156 Set Vref, RX VrefLevel [Byte0]: 63
2792 04:47:20.076139 [Byte1]: 63
2793 04:47:20.080793
2794 04:47:20.080874 Set Vref, RX VrefLevel [Byte0]: 64
2795 04:47:20.083911 [Byte1]: 64
2796 04:47:20.088683
2797 04:47:20.088764 Set Vref, RX VrefLevel [Byte0]: 65
2798 04:47:20.091905 [Byte1]: 65
2799 04:47:20.096503
2800 04:47:20.096584 Set Vref, RX VrefLevel [Byte0]: 66
2801 04:47:20.099993 [Byte1]: 66
2802 04:47:20.104719
2803 04:47:20.104800 Set Vref, RX VrefLevel [Byte0]: 67
2804 04:47:20.107834 [Byte1]: 67
2805 04:47:20.112524
2806 04:47:20.112605 Set Vref, RX VrefLevel [Byte0]: 68
2807 04:47:20.116094 [Byte1]: 68
2808 04:47:20.120552
2809 04:47:20.120633 Set Vref, RX VrefLevel [Byte0]: 69
2810 04:47:20.124022 [Byte1]: 69
2811 04:47:20.128669
2812 04:47:20.128749 Set Vref, RX VrefLevel [Byte0]: 70
2813 04:47:20.131891 [Byte1]: 70
2814 04:47:20.136502
2815 04:47:20.136582 Set Vref, RX VrefLevel [Byte0]: 71
2816 04:47:20.139961 [Byte1]: 71
2817 04:47:20.144714
2818 04:47:20.144794 Set Vref, RX VrefLevel [Byte0]: 72
2819 04:47:20.148128 [Byte1]: 72
2820 04:47:20.152653
2821 04:47:20.152737 Set Vref, RX VrefLevel [Byte0]: 73
2822 04:47:20.155860 [Byte1]: 73
2823 04:47:20.160989
2824 04:47:20.161070 Set Vref, RX VrefLevel [Byte0]: 74
2825 04:47:20.163998 [Byte1]: 74
2826 04:47:20.168809
2827 04:47:20.168883 Set Vref, RX VrefLevel [Byte0]: 75
2828 04:47:20.171956 [Byte1]: 75
2829 04:47:20.176552
2830 04:47:20.176621 Final RX Vref Byte 0 = 61 to rank0
2831 04:47:20.179954 Final RX Vref Byte 1 = 51 to rank0
2832 04:47:20.183355 Final RX Vref Byte 0 = 61 to rank1
2833 04:47:20.186807 Final RX Vref Byte 1 = 51 to rank1==
2834 04:47:20.190140 Dram Type= 6, Freq= 0, CH_0, rank 0
2835 04:47:20.196670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2836 04:47:20.196752 ==
2837 04:47:20.196817 DQS Delay:
2838 04:47:20.196877 DQS0 = 0, DQS1 = 0
2839 04:47:20.200228 DQM Delay:
2840 04:47:20.200309 DQM0 = 112, DQM1 = 101
2841 04:47:20.203434 DQ Delay:
2842 04:47:20.206649 DQ0 =112, DQ1 =112, DQ2 =112, DQ3 =108
2843 04:47:20.209811 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2844 04:47:20.213203 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2845 04:47:20.216564 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =110
2846 04:47:20.216646
2847 04:47:20.216711
2848 04:47:20.223143 [DQSOSCAuto] RK0, (LSB)MR18= 0xff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2849 04:47:20.226782 CH0 RK0: MR19=403, MR18=FF
2850 04:47:20.233290 CH0_RK0: MR19=0x403, MR18=0xFF, DQSOSC=410, MR23=63, INC=39, DEC=26
2851 04:47:20.233373
2852 04:47:20.236544 ----->DramcWriteLeveling(PI) begin...
2853 04:47:20.236628 ==
2854 04:47:20.240071 Dram Type= 6, Freq= 0, CH_0, rank 1
2855 04:47:20.243027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2856 04:47:20.243111 ==
2857 04:47:20.246761 Write leveling (Byte 0): 33 => 33
2858 04:47:20.249991 Write leveling (Byte 1): 31 => 31
2859 04:47:20.253439 DramcWriteLeveling(PI) end<-----
2860 04:47:20.253539
2861 04:47:20.253605 ==
2862 04:47:20.256561 Dram Type= 6, Freq= 0, CH_0, rank 1
2863 04:47:20.259904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2864 04:47:20.259987 ==
2865 04:47:20.263318 [Gating] SW mode calibration
2866 04:47:20.270003 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2867 04:47:20.276567 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2868 04:47:20.279990 0 15 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2869 04:47:20.286477 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 04:47:20.290083 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2871 04:47:20.293343 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 04:47:20.299821 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2873 04:47:20.303336 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2874 04:47:20.306751 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2875 04:47:20.313130 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
2876 04:47:20.316485 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
2877 04:47:20.320037 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 04:47:20.323286 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 04:47:20.329599 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 04:47:20.333246 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2881 04:47:20.336555 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2882 04:47:20.343896 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2883 04:47:20.346897 1 0 28 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
2884 04:47:20.350423 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2885 04:47:20.356998 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 04:47:20.360654 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 04:47:20.363472 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 04:47:20.370347 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 04:47:20.373677 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 04:47:20.376911 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2891 04:47:20.383562 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2892 04:47:20.387145 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2893 04:47:20.390143 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 04:47:20.397019 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 04:47:20.400179 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 04:47:20.403923 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 04:47:20.410393 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 04:47:20.413637 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 04:47:20.417030 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 04:47:20.423808 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 04:47:20.426879 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 04:47:20.430607 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 04:47:20.433738 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 04:47:20.440045 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 04:47:20.443652 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 04:47:20.446744 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 04:47:20.453955 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2908 04:47:20.457009 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2909 04:47:20.460444 Total UI for P1: 0, mck2ui 16
2910 04:47:20.463632 best dqsien dly found for B0: ( 1, 3, 28)
2911 04:47:20.466696 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 04:47:20.470057 Total UI for P1: 0, mck2ui 16
2913 04:47:20.473449 best dqsien dly found for B1: ( 1, 4, 0)
2914 04:47:20.476791 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2915 04:47:20.479929 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2916 04:47:20.480400
2917 04:47:20.486732 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2918 04:47:20.489836 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2919 04:47:20.493429 [Gating] SW calibration Done
2920 04:47:20.493942 ==
2921 04:47:20.496634 Dram Type= 6, Freq= 0, CH_0, rank 1
2922 04:47:20.499952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2923 04:47:20.500423 ==
2924 04:47:20.500798 RX Vref Scan: 0
2925 04:47:20.501147
2926 04:47:20.503168 RX Vref 0 -> 0, step: 1
2927 04:47:20.503639
2928 04:47:20.506828 RX Delay -40 -> 252, step: 8
2929 04:47:20.510315 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2930 04:47:20.513285 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2931 04:47:20.516850 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2932 04:47:20.523052 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2933 04:47:20.526637 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2934 04:47:20.530014 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2935 04:47:20.533590 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2936 04:47:20.536613 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2937 04:47:20.543247 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2938 04:47:20.546733 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2939 04:47:20.550056 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2940 04:47:20.553571 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2941 04:47:20.556747 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2942 04:47:20.563456 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2943 04:47:20.567250 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2944 04:47:20.570079 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2945 04:47:20.570503 ==
2946 04:47:20.573741 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 04:47:20.577184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 04:47:20.577836 ==
2949 04:47:20.580313 DQS Delay:
2950 04:47:20.580831 DQS0 = 0, DQS1 = 0
2951 04:47:20.583575 DQM Delay:
2952 04:47:20.583995 DQM0 = 112, DQM1 = 101
2953 04:47:20.584335 DQ Delay:
2954 04:47:20.586901 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2955 04:47:20.590145 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2956 04:47:20.593621 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2957 04:47:20.600217 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
2958 04:47:20.600742
2959 04:47:20.601080
2960 04:47:20.601393 ==
2961 04:47:20.603277 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 04:47:20.606653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 04:47:20.607074 ==
2964 04:47:20.607410
2965 04:47:20.607722
2966 04:47:20.610034 TX Vref Scan disable
2967 04:47:20.610668 == TX Byte 0 ==
2968 04:47:20.616977 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2969 04:47:20.619945 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2970 04:47:20.620405 == TX Byte 1 ==
2971 04:47:20.626703 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2972 04:47:20.630026 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2973 04:47:20.630489 ==
2974 04:47:20.633861 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 04:47:20.636696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 04:47:20.637261 ==
2977 04:47:20.649995 TX Vref=22, minBit 1, minWin=26, winSum=426
2978 04:47:20.653468 TX Vref=24, minBit 2, minWin=25, winSum=433
2979 04:47:20.656400 TX Vref=26, minBit 1, minWin=26, winSum=438
2980 04:47:20.660068 TX Vref=28, minBit 0, minWin=27, winSum=443
2981 04:47:20.663070 TX Vref=30, minBit 0, minWin=27, winSum=443
2982 04:47:20.670017 TX Vref=32, minBit 13, minWin=26, winSum=440
2983 04:47:20.673268 [TxChooseVref] Worse bit 0, Min win 27, Win sum 443, Final Vref 28
2984 04:47:20.673875
2985 04:47:20.676591 Final TX Range 1 Vref 28
2986 04:47:20.677054
2987 04:47:20.677418 ==
2988 04:47:20.679679 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 04:47:20.683412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 04:47:20.683980 ==
2991 04:47:20.684354
2992 04:47:20.686285
2993 04:47:20.686739 TX Vref Scan disable
2994 04:47:20.689717 == TX Byte 0 ==
2995 04:47:20.693312 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2996 04:47:20.696504 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2997 04:47:20.699700 == TX Byte 1 ==
2998 04:47:20.703272 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2999 04:47:20.706052 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3000 04:47:20.706516
3001 04:47:20.709714 [DATLAT]
3002 04:47:20.710171 Freq=1200, CH0 RK1
3003 04:47:20.710563
3004 04:47:20.713085 DATLAT Default: 0xd
3005 04:47:20.713591 0, 0xFFFF, sum = 0
3006 04:47:20.716232 1, 0xFFFF, sum = 0
3007 04:47:20.716700 2, 0xFFFF, sum = 0
3008 04:47:20.719408 3, 0xFFFF, sum = 0
3009 04:47:20.719872 4, 0xFFFF, sum = 0
3010 04:47:20.722797 5, 0xFFFF, sum = 0
3011 04:47:20.726082 6, 0xFFFF, sum = 0
3012 04:47:20.726568 7, 0xFFFF, sum = 0
3013 04:47:20.729632 8, 0xFFFF, sum = 0
3014 04:47:20.730121 9, 0xFFFF, sum = 0
3015 04:47:20.732811 10, 0xFFFF, sum = 0
3016 04:47:20.733297 11, 0xFFFF, sum = 0
3017 04:47:20.735993 12, 0x0, sum = 1
3018 04:47:20.736474 13, 0x0, sum = 2
3019 04:47:20.739567 14, 0x0, sum = 3
3020 04:47:20.740052 15, 0x0, sum = 4
3021 04:47:20.740559 best_step = 13
3022 04:47:20.741001
3023 04:47:20.742957 ==
3024 04:47:20.746051 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 04:47:20.749299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 04:47:20.749762 ==
3027 04:47:20.750202 RX Vref Scan: 0
3028 04:47:20.750618
3029 04:47:20.752746 RX Vref 0 -> 0, step: 1
3030 04:47:20.753176
3031 04:47:20.755971 RX Delay -37 -> 252, step: 4
3032 04:47:20.759627 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3033 04:47:20.766078 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3034 04:47:20.769518 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3035 04:47:20.773269 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3036 04:47:20.776053 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3037 04:47:20.779269 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3038 04:47:20.785843 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3039 04:47:20.789696 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3040 04:47:20.793158 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3041 04:47:20.796720 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3042 04:47:20.799781 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3043 04:47:20.802944 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3044 04:47:20.809510 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3045 04:47:20.813153 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3046 04:47:20.816173 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3047 04:47:20.819627 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3048 04:47:20.820218 ==
3049 04:47:20.822960 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 04:47:20.829273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 04:47:20.829873 ==
3052 04:47:20.830363 DQS Delay:
3053 04:47:20.832982 DQS0 = 0, DQS1 = 0
3054 04:47:20.833623 DQM Delay:
3055 04:47:20.834119 DQM0 = 110, DQM1 = 100
3056 04:47:20.836372 DQ Delay:
3057 04:47:20.839628 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3058 04:47:20.842816 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3059 04:47:20.846289 DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =92
3060 04:47:20.849618 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =108
3061 04:47:20.850270
3062 04:47:20.850663
3063 04:47:20.856122 [DQSOSCAuto] RK1, (LSB)MR18= 0x15fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 401 ps
3064 04:47:20.859755 CH0 RK1: MR19=403, MR18=15FE
3065 04:47:20.866416 CH0_RK1: MR19=0x403, MR18=0x15FE, DQSOSC=401, MR23=63, INC=40, DEC=27
3066 04:47:20.869637 [RxdqsGatingPostProcess] freq 1200
3067 04:47:20.876454 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3068 04:47:20.879672 best DQS0 dly(2T, 0.5T) = (0, 11)
3069 04:47:20.883114 best DQS1 dly(2T, 0.5T) = (0, 12)
3070 04:47:20.886242 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3071 04:47:20.886711 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3072 04:47:20.889777 best DQS0 dly(2T, 0.5T) = (0, 11)
3073 04:47:20.893173 best DQS1 dly(2T, 0.5T) = (0, 12)
3074 04:47:20.896307 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3075 04:47:20.900020 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3076 04:47:20.902773 Pre-setting of DQS Precalculation
3077 04:47:20.909939 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3078 04:47:20.910508 ==
3079 04:47:20.913001 Dram Type= 6, Freq= 0, CH_1, rank 0
3080 04:47:20.916399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 04:47:20.916870 ==
3082 04:47:20.920062 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3083 04:47:20.926186 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3084 04:47:20.936018 [CA 0] Center 37 (8~67) winsize 60
3085 04:47:20.939096 [CA 1] Center 37 (7~68) winsize 62
3086 04:47:20.942349 [CA 2] Center 34 (4~64) winsize 61
3087 04:47:20.945472 [CA 3] Center 33 (3~64) winsize 62
3088 04:47:20.949004 [CA 4] Center 34 (4~64) winsize 61
3089 04:47:20.952774 [CA 5] Center 33 (3~63) winsize 61
3090 04:47:20.953349
3091 04:47:20.955599 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3092 04:47:20.956078
3093 04:47:20.958833 [CATrainingPosCal] consider 1 rank data
3094 04:47:20.962333 u2DelayCellTimex100 = 270/100 ps
3095 04:47:20.965856 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3096 04:47:20.972469 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3097 04:47:20.975973 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3098 04:47:20.978845 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3099 04:47:20.982298 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3100 04:47:20.985425 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3101 04:47:20.985959
3102 04:47:20.988891 CA PerBit enable=1, Macro0, CA PI delay=33
3103 04:47:20.989373
3104 04:47:20.992634 [CBTSetCACLKResult] CA Dly = 33
3105 04:47:20.993193 CS Dly: 5 (0~36)
3106 04:47:20.995692 ==
3107 04:47:20.996250 Dram Type= 6, Freq= 0, CH_1, rank 1
3108 04:47:21.002310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 04:47:21.002784 ==
3110 04:47:21.005611 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3111 04:47:21.011902 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3112 04:47:21.021249 [CA 0] Center 37 (7~67) winsize 61
3113 04:47:21.024407 [CA 1] Center 37 (7~68) winsize 62
3114 04:47:21.027793 [CA 2] Center 34 (4~65) winsize 62
3115 04:47:21.031370 [CA 3] Center 33 (3~64) winsize 62
3116 04:47:21.034707 [CA 4] Center 34 (4~64) winsize 61
3117 04:47:21.038138 [CA 5] Center 32 (2~63) winsize 62
3118 04:47:21.038710
3119 04:47:21.041454 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3120 04:47:21.041985
3121 04:47:21.044316 [CATrainingPosCal] consider 2 rank data
3122 04:47:21.048071 u2DelayCellTimex100 = 270/100 ps
3123 04:47:21.051550 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3124 04:47:21.054663 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3125 04:47:21.061282 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3126 04:47:21.064649 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3127 04:47:21.068215 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3128 04:47:21.071078 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3129 04:47:21.071550
3130 04:47:21.074689 CA PerBit enable=1, Macro0, CA PI delay=33
3131 04:47:21.075260
3132 04:47:21.077861 [CBTSetCACLKResult] CA Dly = 33
3133 04:47:21.078413 CS Dly: 7 (0~40)
3134 04:47:21.078789
3135 04:47:21.081380 ----->DramcWriteLeveling(PI) begin...
3136 04:47:21.084877 ==
3137 04:47:21.085448 Dram Type= 6, Freq= 0, CH_1, rank 0
3138 04:47:21.091373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3139 04:47:21.091949 ==
3140 04:47:21.094961 Write leveling (Byte 0): 26 => 26
3141 04:47:21.098161 Write leveling (Byte 1): 27 => 27
3142 04:47:21.101206 DramcWriteLeveling(PI) end<-----
3143 04:47:21.101727
3144 04:47:21.102105 ==
3145 04:47:21.104307 Dram Type= 6, Freq= 0, CH_1, rank 0
3146 04:47:21.107965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3147 04:47:21.108526 ==
3148 04:47:21.111234 [Gating] SW mode calibration
3149 04:47:21.118211 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3150 04:47:21.124451 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3151 04:47:21.127700 0 15 0 | B1->B0 | 3030 2b2b | 0 0 | (0 0) (0 0)
3152 04:47:21.131100 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 04:47:21.134761 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 04:47:21.141344 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3155 04:47:21.144611 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3156 04:47:21.147930 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3157 04:47:21.154591 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3158 04:47:21.157878 0 15 28 | B1->B0 | 2e2e 2e2e | 0 1 | (0 0) (1 0)
3159 04:47:21.161159 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 04:47:21.167919 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 04:47:21.171256 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 04:47:21.174239 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3163 04:47:21.181006 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3164 04:47:21.184794 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3165 04:47:21.188007 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3166 04:47:21.194397 1 0 28 | B1->B0 | 3d3d 403f | 0 1 | (0 0) (0 0)
3167 04:47:21.197912 1 1 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3168 04:47:21.201118 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 04:47:21.207723 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 04:47:21.210769 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 04:47:21.214151 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 04:47:21.220502 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 04:47:21.224075 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 04:47:21.227539 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3175 04:47:21.234371 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3176 04:47:21.237622 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 04:47:21.241147 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 04:47:21.247892 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 04:47:21.251189 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 04:47:21.254147 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 04:47:21.257652 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 04:47:21.264329 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 04:47:21.267903 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 04:47:21.270632 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 04:47:21.277688 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 04:47:21.280559 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 04:47:21.284648 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 04:47:21.290783 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 04:47:21.294155 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 04:47:21.297756 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3191 04:47:21.304532 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 04:47:21.305171 Total UI for P1: 0, mck2ui 16
3193 04:47:21.310577 best dqsien dly found for B0: ( 1, 3, 28)
3194 04:47:21.311132 Total UI for P1: 0, mck2ui 16
3195 04:47:21.317323 best dqsien dly found for B1: ( 1, 3, 28)
3196 04:47:21.320888 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3197 04:47:21.324133 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3198 04:47:21.324715
3199 04:47:21.327520 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3200 04:47:21.330729 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3201 04:47:21.334281 [Gating] SW calibration Done
3202 04:47:21.334842 ==
3203 04:47:21.337761 Dram Type= 6, Freq= 0, CH_1, rank 0
3204 04:47:21.341021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3205 04:47:21.341634 ==
3206 04:47:21.344246 RX Vref Scan: 0
3207 04:47:21.344705
3208 04:47:21.345071 RX Vref 0 -> 0, step: 1
3209 04:47:21.345410
3210 04:47:21.347726 RX Delay -40 -> 252, step: 8
3211 04:47:21.351045 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3212 04:47:21.357872 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3213 04:47:21.361297 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3214 04:47:21.364445 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3215 04:47:21.367850 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3216 04:47:21.371108 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3217 04:47:21.374471 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3218 04:47:21.381066 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3219 04:47:21.384485 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3220 04:47:21.387247 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3221 04:47:21.391055 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3222 04:47:21.394280 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3223 04:47:21.400816 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3224 04:47:21.404534 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3225 04:47:21.407734 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3226 04:47:21.410953 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3227 04:47:21.411520 ==
3228 04:47:21.414199 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 04:47:21.420921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 04:47:21.421402 ==
3231 04:47:21.421840 DQS Delay:
3232 04:47:21.422194 DQS0 = 0, DQS1 = 0
3233 04:47:21.424324 DQM Delay:
3234 04:47:21.424783 DQM0 = 113, DQM1 = 105
3235 04:47:21.427618 DQ Delay:
3236 04:47:21.430752 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =115
3237 04:47:21.434219 DQ4 =107, DQ5 =123, DQ6 =123, DQ7 =115
3238 04:47:21.437640 DQ8 =91, DQ9 =99, DQ10 =107, DQ11 =103
3239 04:47:21.440836 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3240 04:47:21.441361
3241 04:47:21.441745
3242 04:47:21.442060 ==
3243 04:47:21.444080 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 04:47:21.447678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 04:47:21.448202 ==
3246 04:47:21.448542
3247 04:47:21.450682
3248 04:47:21.451097 TX Vref Scan disable
3249 04:47:21.454888 == TX Byte 0 ==
3250 04:47:21.457702 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3251 04:47:21.461145 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3252 04:47:21.464423 == TX Byte 1 ==
3253 04:47:21.468010 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3254 04:47:21.471430 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3255 04:47:21.471959 ==
3256 04:47:21.474079 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 04:47:21.480947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 04:47:21.481514 ==
3259 04:47:21.491139 TX Vref=22, minBit 9, minWin=24, winSum=404
3260 04:47:21.494751 TX Vref=24, minBit 8, minWin=24, winSum=407
3261 04:47:21.498187 TX Vref=26, minBit 9, minWin=24, winSum=415
3262 04:47:21.501576 TX Vref=28, minBit 9, minWin=25, winSum=419
3263 04:47:21.505150 TX Vref=30, minBit 9, minWin=25, winSum=421
3264 04:47:21.507866 TX Vref=32, minBit 9, minWin=24, winSum=420
3265 04:47:21.514857 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 30
3266 04:47:21.515398
3267 04:47:21.517790 Final TX Range 1 Vref 30
3268 04:47:21.518210
3269 04:47:21.518542 ==
3270 04:47:21.521250 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 04:47:21.524575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 04:47:21.524998 ==
3273 04:47:21.525337
3274 04:47:21.527775
3275 04:47:21.528192 TX Vref Scan disable
3276 04:47:21.531159 == TX Byte 0 ==
3277 04:47:21.534515 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3278 04:47:21.538100 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3279 04:47:21.541382 == TX Byte 1 ==
3280 04:47:21.545018 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3281 04:47:21.548026 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3282 04:47:21.548448
3283 04:47:21.551569 [DATLAT]
3284 04:47:21.552140 Freq=1200, CH1 RK0
3285 04:47:21.552520
3286 04:47:21.554733 DATLAT Default: 0xd
3287 04:47:21.555302 0, 0xFFFF, sum = 0
3288 04:47:21.558090 1, 0xFFFF, sum = 0
3289 04:47:21.558688 2, 0xFFFF, sum = 0
3290 04:47:21.561364 3, 0xFFFF, sum = 0
3291 04:47:21.561847 4, 0xFFFF, sum = 0
3292 04:47:21.564496 5, 0xFFFF, sum = 0
3293 04:47:21.564926 6, 0xFFFF, sum = 0
3294 04:47:21.567973 7, 0xFFFF, sum = 0
3295 04:47:21.568403 8, 0xFFFF, sum = 0
3296 04:47:21.570998 9, 0xFFFF, sum = 0
3297 04:47:21.574707 10, 0xFFFF, sum = 0
3298 04:47:21.575249 11, 0xFFFF, sum = 0
3299 04:47:21.577798 12, 0x0, sum = 1
3300 04:47:21.578226 13, 0x0, sum = 2
3301 04:47:21.578569 14, 0x0, sum = 3
3302 04:47:21.581339 15, 0x0, sum = 4
3303 04:47:21.581798 best_step = 13
3304 04:47:21.582135
3305 04:47:21.582444 ==
3306 04:47:21.584608 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 04:47:21.590892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 04:47:21.591332 ==
3309 04:47:21.591669 RX Vref Scan: 1
3310 04:47:21.591979
3311 04:47:21.594269 Set Vref Range= 32 -> 127
3312 04:47:21.594685
3313 04:47:21.598025 RX Vref 32 -> 127, step: 1
3314 04:47:21.598470
3315 04:47:21.601107 RX Delay -21 -> 252, step: 4
3316 04:47:21.601564
3317 04:47:21.604172 Set Vref, RX VrefLevel [Byte0]: 32
3318 04:47:21.607608 [Byte1]: 32
3319 04:47:21.608026
3320 04:47:21.611090 Set Vref, RX VrefLevel [Byte0]: 33
3321 04:47:21.614349 [Byte1]: 33
3322 04:47:21.614785
3323 04:47:21.617346 Set Vref, RX VrefLevel [Byte0]: 34
3324 04:47:21.620980 [Byte1]: 34
3325 04:47:21.625273
3326 04:47:21.625778 Set Vref, RX VrefLevel [Byte0]: 35
3327 04:47:21.628384 [Byte1]: 35
3328 04:47:21.633012
3329 04:47:21.636424 Set Vref, RX VrefLevel [Byte0]: 36
3330 04:47:21.636837 [Byte1]: 36
3331 04:47:21.641129
3332 04:47:21.641630 Set Vref, RX VrefLevel [Byte0]: 37
3333 04:47:21.644164 [Byte1]: 37
3334 04:47:21.648919
3335 04:47:21.649339 Set Vref, RX VrefLevel [Byte0]: 38
3336 04:47:21.652841 [Byte1]: 38
3337 04:47:21.657095
3338 04:47:21.657674 Set Vref, RX VrefLevel [Byte0]: 39
3339 04:47:21.660837 [Byte1]: 39
3340 04:47:21.665125
3341 04:47:21.665734 Set Vref, RX VrefLevel [Byte0]: 40
3342 04:47:21.668150 [Byte1]: 40
3343 04:47:21.672971
3344 04:47:21.673582 Set Vref, RX VrefLevel [Byte0]: 41
3345 04:47:21.676201 [Byte1]: 41
3346 04:47:21.681005
3347 04:47:21.681597 Set Vref, RX VrefLevel [Byte0]: 42
3348 04:47:21.684159 [Byte1]: 42
3349 04:47:21.688553
3350 04:47:21.688968 Set Vref, RX VrefLevel [Byte0]: 43
3351 04:47:21.692273 [Byte1]: 43
3352 04:47:21.696963
3353 04:47:21.697526 Set Vref, RX VrefLevel [Byte0]: 44
3354 04:47:21.699977 [Byte1]: 44
3355 04:47:21.704779
3356 04:47:21.705308 Set Vref, RX VrefLevel [Byte0]: 45
3357 04:47:21.707810 [Byte1]: 45
3358 04:47:21.712784
3359 04:47:21.713318 Set Vref, RX VrefLevel [Byte0]: 46
3360 04:47:21.715902 [Byte1]: 46
3361 04:47:21.720294
3362 04:47:21.720804 Set Vref, RX VrefLevel [Byte0]: 47
3363 04:47:21.723412 [Byte1]: 47
3364 04:47:21.727919
3365 04:47:21.728378 Set Vref, RX VrefLevel [Byte0]: 48
3366 04:47:21.731441 [Byte1]: 48
3367 04:47:21.735959
3368 04:47:21.736378 Set Vref, RX VrefLevel [Byte0]: 49
3369 04:47:21.739449 [Byte1]: 49
3370 04:47:21.744069
3371 04:47:21.744489 Set Vref, RX VrefLevel [Byte0]: 50
3372 04:47:21.747226 [Byte1]: 50
3373 04:47:21.751819
3374 04:47:21.752236 Set Vref, RX VrefLevel [Byte0]: 51
3375 04:47:21.755175 [Byte1]: 51
3376 04:47:21.759848
3377 04:47:21.760266 Set Vref, RX VrefLevel [Byte0]: 52
3378 04:47:21.763232 [Byte1]: 52
3379 04:47:21.767714
3380 04:47:21.768015 Set Vref, RX VrefLevel [Byte0]: 53
3381 04:47:21.771049 [Byte1]: 53
3382 04:47:21.775698
3383 04:47:21.776002 Set Vref, RX VrefLevel [Byte0]: 54
3384 04:47:21.778985 [Byte1]: 54
3385 04:47:21.783452
3386 04:47:21.783754 Set Vref, RX VrefLevel [Byte0]: 55
3387 04:47:21.786819 [Byte1]: 55
3388 04:47:21.791292
3389 04:47:21.791684 Set Vref, RX VrefLevel [Byte0]: 56
3390 04:47:21.794717 [Byte1]: 56
3391 04:47:21.799187
3392 04:47:21.799416 Set Vref, RX VrefLevel [Byte0]: 57
3393 04:47:21.802685 [Byte1]: 57
3394 04:47:21.807096
3395 04:47:21.807250 Set Vref, RX VrefLevel [Byte0]: 58
3396 04:47:21.810260 [Byte1]: 58
3397 04:47:21.814821
3398 04:47:21.814954 Set Vref, RX VrefLevel [Byte0]: 59
3399 04:47:21.818288 [Byte1]: 59
3400 04:47:21.823173
3401 04:47:21.823281 Set Vref, RX VrefLevel [Byte0]: 60
3402 04:47:21.826116 [Byte1]: 60
3403 04:47:21.830802
3404 04:47:21.830899 Set Vref, RX VrefLevel [Byte0]: 61
3405 04:47:21.834102 [Byte1]: 61
3406 04:47:21.838859
3407 04:47:21.838957 Set Vref, RX VrefLevel [Byte0]: 62
3408 04:47:21.842136 [Byte1]: 62
3409 04:47:21.846851
3410 04:47:21.847020 Set Vref, RX VrefLevel [Byte0]: 63
3411 04:47:21.850262 [Byte1]: 63
3412 04:47:21.855063
3413 04:47:21.855240 Set Vref, RX VrefLevel [Byte0]: 64
3414 04:47:21.858001 [Byte1]: 64
3415 04:47:21.862613
3416 04:47:21.862798 Set Vref, RX VrefLevel [Byte0]: 65
3417 04:47:21.865994 [Byte1]: 65
3418 04:47:21.870445
3419 04:47:21.870639 Set Vref, RX VrefLevel [Byte0]: 66
3420 04:47:21.873900 [Byte1]: 66
3421 04:47:21.878544
3422 04:47:21.878770 Set Vref, RX VrefLevel [Byte0]: 67
3423 04:47:21.882079 [Byte1]: 67
3424 04:47:21.886629
3425 04:47:21.886925 Set Vref, RX VrefLevel [Byte0]: 68
3426 04:47:21.889832 [Byte1]: 68
3427 04:47:21.894508
3428 04:47:21.894860 Final RX Vref Byte 0 = 55 to rank0
3429 04:47:21.897647 Final RX Vref Byte 1 = 51 to rank0
3430 04:47:21.901029 Final RX Vref Byte 0 = 55 to rank1
3431 04:47:21.904543 Final RX Vref Byte 1 = 51 to rank1==
3432 04:47:21.908085 Dram Type= 6, Freq= 0, CH_1, rank 0
3433 04:47:21.914306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 04:47:21.914737 ==
3435 04:47:21.915175 DQS Delay:
3436 04:47:21.915592 DQS0 = 0, DQS1 = 0
3437 04:47:21.917813 DQM Delay:
3438 04:47:21.918291 DQM0 = 115, DQM1 = 105
3439 04:47:21.921282 DQ Delay:
3440 04:47:21.924605 DQ0 =116, DQ1 =112, DQ2 =104, DQ3 =112
3441 04:47:21.927612 DQ4 =112, DQ5 =124, DQ6 =128, DQ7 =112
3442 04:47:21.930963 DQ8 =94, DQ9 =96, DQ10 =104, DQ11 =100
3443 04:47:21.934376 DQ12 =114, DQ13 =110, DQ14 =112, DQ15 =110
3444 04:47:21.934806
3445 04:47:21.935240
3446 04:47:21.941438 [DQSOSCAuto] RK0, (LSB)MR18= 0xf2f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
3447 04:47:21.944681 CH1 RK0: MR19=303, MR18=F2F9
3448 04:47:21.951277 CH1_RK0: MR19=0x303, MR18=0xF2F9, DQSOSC=412, MR23=63, INC=38, DEC=25
3449 04:47:21.951881
3450 04:47:21.954382 ----->DramcWriteLeveling(PI) begin...
3451 04:47:21.954806 ==
3452 04:47:21.958147 Dram Type= 6, Freq= 0, CH_1, rank 1
3453 04:47:21.961335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3454 04:47:21.964583 ==
3455 04:47:21.965099 Write leveling (Byte 0): 24 => 24
3456 04:47:21.967809 Write leveling (Byte 1): 29 => 29
3457 04:47:21.970862 DramcWriteLeveling(PI) end<-----
3458 04:47:21.971394
3459 04:47:21.971736 ==
3460 04:47:21.974225 Dram Type= 6, Freq= 0, CH_1, rank 1
3461 04:47:21.980814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 04:47:21.981331 ==
3463 04:47:21.984290 [Gating] SW mode calibration
3464 04:47:21.991166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3465 04:47:21.994228 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3466 04:47:22.001154 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3467 04:47:22.004384 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 04:47:22.007970 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 04:47:22.014309 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 04:47:22.017602 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 04:47:22.021002 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 04:47:22.024261 0 15 24 | B1->B0 | 3131 2323 | 0 0 | (0 1) (1 0)
3473 04:47:22.030931 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3474 04:47:22.034221 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 04:47:22.037942 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 04:47:22.044261 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 04:47:22.047856 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 04:47:22.050775 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 04:47:22.057368 1 0 20 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
3480 04:47:22.060902 1 0 24 | B1->B0 | 2625 4646 | 1 0 | (0 0) (0 0)
3481 04:47:22.064422 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 04:47:22.070808 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 04:47:22.073703 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 04:47:22.077633 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 04:47:22.084361 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 04:47:22.087180 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 04:47:22.090772 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 04:47:22.096996 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3489 04:47:22.100321 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3490 04:47:22.103643 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 04:47:22.110608 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 04:47:22.114081 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 04:47:22.117096 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 04:47:22.123413 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 04:47:22.127130 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 04:47:22.130265 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 04:47:22.136783 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 04:47:22.140147 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 04:47:22.143294 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 04:47:22.150254 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 04:47:22.153769 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 04:47:22.157104 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 04:47:22.163440 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3504 04:47:22.167241 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3505 04:47:22.170263 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 04:47:22.173555 Total UI for P1: 0, mck2ui 16
3507 04:47:22.176964 best dqsien dly found for B0: ( 1, 3, 22)
3508 04:47:22.180176 Total UI for P1: 0, mck2ui 16
3509 04:47:22.183854 best dqsien dly found for B1: ( 1, 3, 24)
3510 04:47:22.187225 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3511 04:47:22.190033 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3512 04:47:22.190564
3513 04:47:22.193680 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3514 04:47:22.200110 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3515 04:47:22.200645 [Gating] SW calibration Done
3516 04:47:22.200994 ==
3517 04:47:22.203185 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 04:47:22.209813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 04:47:22.210241 ==
3520 04:47:22.210577 RX Vref Scan: 0
3521 04:47:22.210908
3522 04:47:22.213161 RX Vref 0 -> 0, step: 1
3523 04:47:22.213620
3524 04:47:22.216446 RX Delay -40 -> 252, step: 8
3525 04:47:22.219725 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3526 04:47:22.223135 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3527 04:47:22.226276 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3528 04:47:22.233047 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3529 04:47:22.236412 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3530 04:47:22.240092 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3531 04:47:22.242934 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3532 04:47:22.246117 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3533 04:47:22.252758 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3534 04:47:22.256351 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3535 04:47:22.259490 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3536 04:47:22.262732 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3537 04:47:22.266272 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3538 04:47:22.272852 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3539 04:47:22.275949 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3540 04:47:22.279311 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3541 04:47:22.279875 ==
3542 04:47:22.282759 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 04:47:22.286451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 04:47:22.286975 ==
3545 04:47:22.289524 DQS Delay:
3546 04:47:22.290048 DQS0 = 0, DQS1 = 0
3547 04:47:22.292562 DQM Delay:
3548 04:47:22.293076 DQM0 = 110, DQM1 = 109
3549 04:47:22.295616 DQ Delay:
3550 04:47:22.299232 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3551 04:47:22.302708 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3552 04:47:22.305771 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3553 04:47:22.309282 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
3554 04:47:22.309896
3555 04:47:22.310236
3556 04:47:22.310546 ==
3557 04:47:22.312427 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 04:47:22.316109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 04:47:22.316663 ==
3560 04:47:22.317030
3561 04:47:22.317341
3562 04:47:22.318713 TX Vref Scan disable
3563 04:47:22.322041 == TX Byte 0 ==
3564 04:47:22.325410 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3565 04:47:22.328797 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3566 04:47:22.332140 == TX Byte 1 ==
3567 04:47:22.335696 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3568 04:47:22.338788 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3569 04:47:22.339304 ==
3570 04:47:22.342116 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 04:47:22.349128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 04:47:22.349693 ==
3573 04:47:22.359730 TX Vref=22, minBit 8, minWin=25, winSum=425
3574 04:47:22.362750 TX Vref=24, minBit 2, minWin=26, winSum=430
3575 04:47:22.366364 TX Vref=26, minBit 1, minWin=26, winSum=432
3576 04:47:22.369552 TX Vref=28, minBit 0, minWin=27, winSum=438
3577 04:47:22.372940 TX Vref=30, minBit 8, minWin=26, winSum=435
3578 04:47:22.376181 TX Vref=32, minBit 8, minWin=26, winSum=432
3579 04:47:22.382622 [TxChooseVref] Worse bit 0, Min win 27, Win sum 438, Final Vref 28
3580 04:47:22.383138
3581 04:47:22.386091 Final TX Range 1 Vref 28
3582 04:47:22.386605
3583 04:47:22.386942 ==
3584 04:47:22.389369 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 04:47:22.392366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 04:47:22.392876 ==
3587 04:47:22.395837
3588 04:47:22.396343
3589 04:47:22.396722 TX Vref Scan disable
3590 04:47:22.399157 == TX Byte 0 ==
3591 04:47:22.402627 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3592 04:47:22.405635 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3593 04:47:22.409579 == TX Byte 1 ==
3594 04:47:22.412706 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3595 04:47:22.418807 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3596 04:47:22.419479
3597 04:47:22.419838 [DATLAT]
3598 04:47:22.420358 Freq=1200, CH1 RK1
3599 04:47:22.420746
3600 04:47:22.422045 DATLAT Default: 0xd
3601 04:47:22.422461 0, 0xFFFF, sum = 0
3602 04:47:22.425530 1, 0xFFFF, sum = 0
3603 04:47:22.428833 2, 0xFFFF, sum = 0
3604 04:47:22.429356 3, 0xFFFF, sum = 0
3605 04:47:22.432198 4, 0xFFFF, sum = 0
3606 04:47:22.432646 5, 0xFFFF, sum = 0
3607 04:47:22.435479 6, 0xFFFF, sum = 0
3608 04:47:22.435902 7, 0xFFFF, sum = 0
3609 04:47:22.439268 8, 0xFFFF, sum = 0
3610 04:47:22.439792 9, 0xFFFF, sum = 0
3611 04:47:22.442398 10, 0xFFFF, sum = 0
3612 04:47:22.442920 11, 0xFFFF, sum = 0
3613 04:47:22.445640 12, 0x0, sum = 1
3614 04:47:22.446159 13, 0x0, sum = 2
3615 04:47:22.448923 14, 0x0, sum = 3
3616 04:47:22.449459 15, 0x0, sum = 4
3617 04:47:22.452051 best_step = 13
3618 04:47:22.452565
3619 04:47:22.452900 ==
3620 04:47:22.455483 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 04:47:22.458921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 04:47:22.459447 ==
3623 04:47:22.459786 RX Vref Scan: 0
3624 04:47:22.462037
3625 04:47:22.462573 RX Vref 0 -> 0, step: 1
3626 04:47:22.462917
3627 04:47:22.465326 RX Delay -21 -> 252, step: 4
3628 04:47:22.472152 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3629 04:47:22.475664 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3630 04:47:22.478614 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3631 04:47:22.481982 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3632 04:47:22.485460 iDelay=195, Bit 4, Center 108 (35 ~ 182) 148
3633 04:47:22.492125 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3634 04:47:22.495019 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3635 04:47:22.498407 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3636 04:47:22.501913 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3637 04:47:22.505384 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3638 04:47:22.508357 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3639 04:47:22.514701 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3640 04:47:22.518236 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3641 04:47:22.521169 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3642 04:47:22.524600 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3643 04:47:22.531395 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3644 04:47:22.531833 ==
3645 04:47:22.534599 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 04:47:22.538237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 04:47:22.538767 ==
3648 04:47:22.539107 DQS Delay:
3649 04:47:22.541213 DQS0 = 0, DQS1 = 0
3650 04:47:22.541666 DQM Delay:
3651 04:47:22.544733 DQM0 = 111, DQM1 = 109
3652 04:47:22.545157 DQ Delay:
3653 04:47:22.548273 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3654 04:47:22.551791 DQ4 =108, DQ5 =120, DQ6 =122, DQ7 =110
3655 04:47:22.554845 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =104
3656 04:47:22.558212 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3657 04:47:22.558744
3658 04:47:22.559080
3659 04:47:22.568391 [DQSOSCAuto] RK1, (LSB)MR18= 0xf606, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
3660 04:47:22.571415 CH1 RK1: MR19=304, MR18=F606
3661 04:47:22.578074 CH1_RK1: MR19=0x304, MR18=0xF606, DQSOSC=407, MR23=63, INC=39, DEC=26
3662 04:47:22.578648 [RxdqsGatingPostProcess] freq 1200
3663 04:47:22.584486 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3664 04:47:22.587783 best DQS0 dly(2T, 0.5T) = (0, 11)
3665 04:47:22.591679 best DQS1 dly(2T, 0.5T) = (0, 11)
3666 04:47:22.594564 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3667 04:47:22.597865 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3668 04:47:22.601302 best DQS0 dly(2T, 0.5T) = (0, 11)
3669 04:47:22.604865 best DQS1 dly(2T, 0.5T) = (0, 11)
3670 04:47:22.607532 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3671 04:47:22.611231 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3672 04:47:22.614643 Pre-setting of DQS Precalculation
3673 04:47:22.617899 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3674 04:47:22.624221 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3675 04:47:22.634068 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3676 04:47:22.634486
3677 04:47:22.634903
3678 04:47:22.635225 [Calibration Summary] 2400 Mbps
3679 04:47:22.637508 CH 0, Rank 0
3680 04:47:22.640980 SW Impedance : PASS
3681 04:47:22.641590 DUTY Scan : NO K
3682 04:47:22.643950 ZQ Calibration : PASS
3683 04:47:22.644368 Jitter Meter : NO K
3684 04:47:22.647235 CBT Training : PASS
3685 04:47:22.651046 Write leveling : PASS
3686 04:47:22.651561 RX DQS gating : PASS
3687 04:47:22.654033 RX DQ/DQS(RDDQC) : PASS
3688 04:47:22.657148 TX DQ/DQS : PASS
3689 04:47:22.657772 RX DATLAT : PASS
3690 04:47:22.660699 RX DQ/DQS(Engine): PASS
3691 04:47:22.664453 TX OE : NO K
3692 04:47:22.664976 All Pass.
3693 04:47:22.665350
3694 04:47:22.665741 CH 0, Rank 1
3695 04:47:22.667670 SW Impedance : PASS
3696 04:47:22.670809 DUTY Scan : NO K
3697 04:47:22.671329 ZQ Calibration : PASS
3698 04:47:22.673846 Jitter Meter : NO K
3699 04:47:22.677021 CBT Training : PASS
3700 04:47:22.677440 Write leveling : PASS
3701 04:47:22.680602 RX DQS gating : PASS
3702 04:47:22.683965 RX DQ/DQS(RDDQC) : PASS
3703 04:47:22.684382 TX DQ/DQS : PASS
3704 04:47:22.686914 RX DATLAT : PASS
3705 04:47:22.690691 RX DQ/DQS(Engine): PASS
3706 04:47:22.691110 TX OE : NO K
3707 04:47:22.691443 All Pass.
3708 04:47:22.693879
3709 04:47:22.694320 CH 1, Rank 0
3710 04:47:22.697242 SW Impedance : PASS
3711 04:47:22.697691 DUTY Scan : NO K
3712 04:47:22.700345 ZQ Calibration : PASS
3713 04:47:22.700761 Jitter Meter : NO K
3714 04:47:22.703633 CBT Training : PASS
3715 04:47:22.707494 Write leveling : PASS
3716 04:47:22.708017 RX DQS gating : PASS
3717 04:47:22.710321 RX DQ/DQS(RDDQC) : PASS
3718 04:47:22.713708 TX DQ/DQS : PASS
3719 04:47:22.714125 RX DATLAT : PASS
3720 04:47:22.716842 RX DQ/DQS(Engine): PASS
3721 04:47:22.720131 TX OE : NO K
3722 04:47:22.720550 All Pass.
3723 04:47:22.720883
3724 04:47:22.721208 CH 1, Rank 1
3725 04:47:22.723743 SW Impedance : PASS
3726 04:47:22.726700 DUTY Scan : NO K
3727 04:47:22.727115 ZQ Calibration : PASS
3728 04:47:22.730086 Jitter Meter : NO K
3729 04:47:22.733456 CBT Training : PASS
3730 04:47:22.733915 Write leveling : PASS
3731 04:47:22.736971 RX DQS gating : PASS
3732 04:47:22.740644 RX DQ/DQS(RDDQC) : PASS
3733 04:47:22.741193 TX DQ/DQS : PASS
3734 04:47:22.743423 RX DATLAT : PASS
3735 04:47:22.746784 RX DQ/DQS(Engine): PASS
3736 04:47:22.747259 TX OE : NO K
3737 04:47:22.750115 All Pass.
3738 04:47:22.750529
3739 04:47:22.750858 DramC Write-DBI off
3740 04:47:22.753191 PER_BANK_REFRESH: Hybrid Mode
3741 04:47:22.753663 TX_TRACKING: ON
3742 04:47:22.763155 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3743 04:47:22.766646 [FAST_K] Save calibration result to emmc
3744 04:47:22.770102 dramc_set_vcore_voltage set vcore to 650000
3745 04:47:22.772963 Read voltage for 600, 5
3746 04:47:22.773668 Vio18 = 0
3747 04:47:22.776654 Vcore = 650000
3748 04:47:22.777203 Vdram = 0
3749 04:47:22.777702 Vddq = 0
3750 04:47:22.778027 Vmddr = 0
3751 04:47:22.783519 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3752 04:47:22.789682 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3753 04:47:22.790109 MEM_TYPE=3, freq_sel=19
3754 04:47:22.793157 sv_algorithm_assistance_LP4_1600
3755 04:47:22.796334 ============ PULL DRAM RESETB DOWN ============
3756 04:47:22.802978 ========== PULL DRAM RESETB DOWN end =========
3757 04:47:22.806183 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3758 04:47:22.810041 ===================================
3759 04:47:22.813106 LPDDR4 DRAM CONFIGURATION
3760 04:47:22.816612 ===================================
3761 04:47:22.817143 EX_ROW_EN[0] = 0x0
3762 04:47:22.819402 EX_ROW_EN[1] = 0x0
3763 04:47:22.822530 LP4Y_EN = 0x0
3764 04:47:22.822983 WORK_FSP = 0x0
3765 04:47:22.826193 WL = 0x2
3766 04:47:22.826617 RL = 0x2
3767 04:47:22.829676 BL = 0x2
3768 04:47:22.830105 RPST = 0x0
3769 04:47:22.833112 RD_PRE = 0x0
3770 04:47:22.833692 WR_PRE = 0x1
3771 04:47:22.836440 WR_PST = 0x0
3772 04:47:22.836968 DBI_WR = 0x0
3773 04:47:22.839762 DBI_RD = 0x0
3774 04:47:22.840292 OTF = 0x1
3775 04:47:22.842735 ===================================
3776 04:47:22.846363 ===================================
3777 04:47:22.850072 ANA top config
3778 04:47:22.853093 ===================================
3779 04:47:22.853663 DLL_ASYNC_EN = 0
3780 04:47:22.856631 ALL_SLAVE_EN = 1
3781 04:47:22.859739 NEW_RANK_MODE = 1
3782 04:47:22.862808 DLL_IDLE_MODE = 1
3783 04:47:22.863336 LP45_APHY_COMB_EN = 1
3784 04:47:22.866315 TX_ODT_DIS = 1
3785 04:47:22.869424 NEW_8X_MODE = 1
3786 04:47:22.872742 ===================================
3787 04:47:22.876186 ===================================
3788 04:47:22.879403 data_rate = 1200
3789 04:47:22.882699 CKR = 1
3790 04:47:22.885813 DQ_P2S_RATIO = 8
3791 04:47:22.889104 ===================================
3792 04:47:22.889575 CA_P2S_RATIO = 8
3793 04:47:22.892863 DQ_CA_OPEN = 0
3794 04:47:22.896010 DQ_SEMI_OPEN = 0
3795 04:47:22.899237 CA_SEMI_OPEN = 0
3796 04:47:22.902783 CA_FULL_RATE = 0
3797 04:47:22.906157 DQ_CKDIV4_EN = 1
3798 04:47:22.906765 CA_CKDIV4_EN = 1
3799 04:47:22.909340 CA_PREDIV_EN = 0
3800 04:47:22.912820 PH8_DLY = 0
3801 04:47:22.916000 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3802 04:47:22.919161 DQ_AAMCK_DIV = 4
3803 04:47:22.922242 CA_AAMCK_DIV = 4
3804 04:47:22.922683 CA_ADMCK_DIV = 4
3805 04:47:22.925654 DQ_TRACK_CA_EN = 0
3806 04:47:22.928914 CA_PICK = 600
3807 04:47:22.932222 CA_MCKIO = 600
3808 04:47:22.935382 MCKIO_SEMI = 0
3809 04:47:22.939276 PLL_FREQ = 2288
3810 04:47:22.942350 DQ_UI_PI_RATIO = 32
3811 04:47:22.942776 CA_UI_PI_RATIO = 0
3812 04:47:22.945404 ===================================
3813 04:47:22.948963 ===================================
3814 04:47:22.952528 memory_type:LPDDR4
3815 04:47:22.955856 GP_NUM : 10
3816 04:47:22.956378 SRAM_EN : 1
3817 04:47:22.958881 MD32_EN : 0
3818 04:47:22.962377 ===================================
3819 04:47:22.965596 [ANA_INIT] >>>>>>>>>>>>>>
3820 04:47:22.969191 <<<<<< [CONFIGURE PHASE]: ANA_TX
3821 04:47:22.972219 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3822 04:47:22.975538 ===================================
3823 04:47:22.975962 data_rate = 1200,PCW = 0X5800
3824 04:47:22.978772 ===================================
3825 04:47:22.982185 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3826 04:47:22.989036 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3827 04:47:22.995609 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3828 04:47:22.998956 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3829 04:47:23.002010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3830 04:47:23.005548 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3831 04:47:23.009069 [ANA_INIT] flow start
3832 04:47:23.009639 [ANA_INIT] PLL >>>>>>>>
3833 04:47:23.012219 [ANA_INIT] PLL <<<<<<<<
3834 04:47:23.015368 [ANA_INIT] MIDPI >>>>>>>>
3835 04:47:23.018450 [ANA_INIT] MIDPI <<<<<<<<
3836 04:47:23.018872 [ANA_INIT] DLL >>>>>>>>
3837 04:47:23.021761 [ANA_INIT] flow end
3838 04:47:23.025174 ============ LP4 DIFF to SE enter ============
3839 04:47:23.028742 ============ LP4 DIFF to SE exit ============
3840 04:47:23.031633 [ANA_INIT] <<<<<<<<<<<<<
3841 04:47:23.034906 [Flow] Enable top DCM control >>>>>
3842 04:47:23.038134 [Flow] Enable top DCM control <<<<<
3843 04:47:23.041535 Enable DLL master slave shuffle
3844 04:47:23.048182 ==============================================================
3845 04:47:23.048647 Gating Mode config
3846 04:47:23.054887 ==============================================================
3847 04:47:23.055330 Config description:
3848 04:47:23.064441 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3849 04:47:23.071125 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3850 04:47:23.077698 SELPH_MODE 0: By rank 1: By Phase
3851 04:47:23.080870 ==============================================================
3852 04:47:23.084204 GAT_TRACK_EN = 1
3853 04:47:23.087596 RX_GATING_MODE = 2
3854 04:47:23.090785 RX_GATING_TRACK_MODE = 2
3855 04:47:23.094014 SELPH_MODE = 1
3856 04:47:23.097448 PICG_EARLY_EN = 1
3857 04:47:23.100526 VALID_LAT_VALUE = 1
3858 04:47:23.107399 ==============================================================
3859 04:47:23.110517 Enter into Gating configuration >>>>
3860 04:47:23.113897 Exit from Gating configuration <<<<
3861 04:47:23.116964 Enter into DVFS_PRE_config >>>>>
3862 04:47:23.127118 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3863 04:47:23.130647 Exit from DVFS_PRE_config <<<<<
3864 04:47:23.133530 Enter into PICG configuration >>>>
3865 04:47:23.136846 Exit from PICG configuration <<<<
3866 04:47:23.140258 [RX_INPUT] configuration >>>>>
3867 04:47:23.140343 [RX_INPUT] configuration <<<<<
3868 04:47:23.147102 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3869 04:47:23.153385 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3870 04:47:23.159925 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3871 04:47:23.163387 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3872 04:47:23.170250 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3873 04:47:23.176554 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3874 04:47:23.179858 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3875 04:47:23.186372 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3876 04:47:23.189741 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3877 04:47:23.193189 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3878 04:47:23.196633 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3879 04:47:23.203329 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3880 04:47:23.206635 ===================================
3881 04:47:23.206719 LPDDR4 DRAM CONFIGURATION
3882 04:47:23.209684 ===================================
3883 04:47:23.213178 EX_ROW_EN[0] = 0x0
3884 04:47:23.216369 EX_ROW_EN[1] = 0x0
3885 04:47:23.216450 LP4Y_EN = 0x0
3886 04:47:23.219793 WORK_FSP = 0x0
3887 04:47:23.219922 WL = 0x2
3888 04:47:23.222961 RL = 0x2
3889 04:47:23.223041 BL = 0x2
3890 04:47:23.226245 RPST = 0x0
3891 04:47:23.226329 RD_PRE = 0x0
3892 04:47:23.229466 WR_PRE = 0x1
3893 04:47:23.229608 WR_PST = 0x0
3894 04:47:23.233090 DBI_WR = 0x0
3895 04:47:23.233213 DBI_RD = 0x0
3896 04:47:23.236416 OTF = 0x1
3897 04:47:23.239483 ===================================
3898 04:47:23.243042 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3899 04:47:23.246038 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3900 04:47:23.252714 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3901 04:47:23.256022 ===================================
3902 04:47:23.256105 LPDDR4 DRAM CONFIGURATION
3903 04:47:23.259169 ===================================
3904 04:47:23.262658 EX_ROW_EN[0] = 0x10
3905 04:47:23.265944 EX_ROW_EN[1] = 0x0
3906 04:47:23.266025 LP4Y_EN = 0x0
3907 04:47:23.269136 WORK_FSP = 0x0
3908 04:47:23.269217 WL = 0x2
3909 04:47:23.272516 RL = 0x2
3910 04:47:23.272597 BL = 0x2
3911 04:47:23.276004 RPST = 0x0
3912 04:47:23.276084 RD_PRE = 0x0
3913 04:47:23.279396 WR_PRE = 0x1
3914 04:47:23.279476 WR_PST = 0x0
3915 04:47:23.282286 DBI_WR = 0x0
3916 04:47:23.282367 DBI_RD = 0x0
3917 04:47:23.285595 OTF = 0x1
3918 04:47:23.289078 ===================================
3919 04:47:23.295893 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3920 04:47:23.299334 nWR fixed to 30
3921 04:47:23.299494 [ModeRegInit_LP4] CH0 RK0
3922 04:47:23.302681 [ModeRegInit_LP4] CH0 RK1
3923 04:47:23.306018 [ModeRegInit_LP4] CH1 RK0
3924 04:47:23.309575 [ModeRegInit_LP4] CH1 RK1
3925 04:47:23.309733 match AC timing 17
3926 04:47:23.315810 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3927 04:47:23.318822 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3928 04:47:23.322480 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3929 04:47:23.328992 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3930 04:47:23.332246 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3931 04:47:23.332398 ==
3932 04:47:23.335903 Dram Type= 6, Freq= 0, CH_0, rank 0
3933 04:47:23.339103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3934 04:47:23.339287 ==
3935 04:47:23.345764 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3936 04:47:23.352406 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3937 04:47:23.355386 [CA 0] Center 37 (7~67) winsize 61
3938 04:47:23.358777 [CA 1] Center 36 (6~66) winsize 61
3939 04:47:23.361907 [CA 2] Center 35 (5~65) winsize 61
3940 04:47:23.365263 [CA 3] Center 35 (5~65) winsize 61
3941 04:47:23.369001 [CA 4] Center 34 (4~65) winsize 62
3942 04:47:23.372243 [CA 5] Center 34 (4~64) winsize 61
3943 04:47:23.372533
3944 04:47:23.375402 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3945 04:47:23.375608
3946 04:47:23.378861 [CATrainingPosCal] consider 1 rank data
3947 04:47:23.382367 u2DelayCellTimex100 = 270/100 ps
3948 04:47:23.385291 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3949 04:47:23.388686 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
3950 04:47:23.392442 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3951 04:47:23.395217 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3952 04:47:23.398734 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3953 04:47:23.401855 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3954 04:47:23.401959
3955 04:47:23.408435 CA PerBit enable=1, Macro0, CA PI delay=34
3956 04:47:23.408592
3957 04:47:23.411704 [CBTSetCACLKResult] CA Dly = 34
3958 04:47:23.411819 CS Dly: 6 (0~37)
3959 04:47:23.411897 ==
3960 04:47:23.415148 Dram Type= 6, Freq= 0, CH_0, rank 1
3961 04:47:23.418450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3962 04:47:23.418563 ==
3963 04:47:23.424748 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3964 04:47:23.431406 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3965 04:47:23.434652 [CA 0] Center 37 (7~67) winsize 61
3966 04:47:23.438041 [CA 1] Center 36 (6~67) winsize 62
3967 04:47:23.441656 [CA 2] Center 35 (5~65) winsize 61
3968 04:47:23.444725 [CA 3] Center 34 (4~65) winsize 62
3969 04:47:23.448024 [CA 4] Center 34 (4~64) winsize 61
3970 04:47:23.451614 [CA 5] Center 33 (3~64) winsize 62
3971 04:47:23.451776
3972 04:47:23.454631 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3973 04:47:23.454796
3974 04:47:23.457970 [CATrainingPosCal] consider 2 rank data
3975 04:47:23.461562 u2DelayCellTimex100 = 270/100 ps
3976 04:47:23.464598 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3977 04:47:23.468139 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
3978 04:47:23.471181 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3979 04:47:23.478072 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3980 04:47:23.481197 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3981 04:47:23.484333 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3982 04:47:23.484505
3983 04:47:23.487740 CA PerBit enable=1, Macro0, CA PI delay=34
3984 04:47:23.487971
3985 04:47:23.490820 [CBTSetCACLKResult] CA Dly = 34
3986 04:47:23.490973 CS Dly: 6 (0~38)
3987 04:47:23.491116
3988 04:47:23.494107 ----->DramcWriteLeveling(PI) begin...
3989 04:47:23.494274 ==
3990 04:47:23.497350 Dram Type= 6, Freq= 0, CH_0, rank 0
3991 04:47:23.504134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3992 04:47:23.504454 ==
3993 04:47:23.507650 Write leveling (Byte 0): 31 => 31
3994 04:47:23.511196 Write leveling (Byte 1): 30 => 30
3995 04:47:23.514103 DramcWriteLeveling(PI) end<-----
3996 04:47:23.514571
3997 04:47:23.514907 ==
3998 04:47:23.517597 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 04:47:23.521092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 04:47:23.521660 ==
4001 04:47:23.524289 [Gating] SW mode calibration
4002 04:47:23.530690 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4003 04:47:23.534179 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4004 04:47:23.540985 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 04:47:23.543911 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4006 04:47:23.547596 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 04:47:23.554268 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
4008 04:47:23.557354 0 9 16 | B1->B0 | 3030 2727 | 0 0 | (1 1) (0 0)
4009 04:47:23.560852 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 04:47:23.567327 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 04:47:23.570907 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 04:47:23.573707 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 04:47:23.580467 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 04:47:23.583480 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 04:47:23.587311 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4016 04:47:23.593953 0 10 16 | B1->B0 | 3232 3939 | 0 0 | (0 0) (0 0)
4017 04:47:23.597193 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 04:47:23.600392 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 04:47:23.606879 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 04:47:23.610243 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 04:47:23.613585 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 04:47:23.619974 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 04:47:23.623270 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4024 04:47:23.626449 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4025 04:47:23.633227 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 04:47:23.636617 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 04:47:23.640082 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 04:47:23.646275 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 04:47:23.649696 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 04:47:23.652838 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 04:47:23.659766 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 04:47:23.662655 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 04:47:23.666104 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 04:47:23.672904 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 04:47:23.676002 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 04:47:23.679391 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 04:47:23.685557 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 04:47:23.689185 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 04:47:23.692523 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4040 04:47:23.698859 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 04:47:23.702258 Total UI for P1: 0, mck2ui 16
4042 04:47:23.705810 best dqsien dly found for B0: ( 0, 13, 12)
4043 04:47:23.708923 Total UI for P1: 0, mck2ui 16
4044 04:47:23.712302 best dqsien dly found for B1: ( 0, 13, 14)
4045 04:47:23.715558 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4046 04:47:23.718852 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4047 04:47:23.719406
4048 04:47:23.722241 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4049 04:47:23.725636 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4050 04:47:23.728738 [Gating] SW calibration Done
4051 04:47:23.729287 ==
4052 04:47:23.731730 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 04:47:23.735367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 04:47:23.735793 ==
4055 04:47:23.738870 RX Vref Scan: 0
4056 04:47:23.739423
4057 04:47:23.742292 RX Vref 0 -> 0, step: 1
4058 04:47:23.742981
4059 04:47:23.743562 RX Delay -230 -> 252, step: 16
4060 04:47:23.748700 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4061 04:47:23.751800 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4062 04:47:23.755236 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4063 04:47:23.758644 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4064 04:47:23.765085 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4065 04:47:23.768387 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4066 04:47:23.771699 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4067 04:47:23.775496 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4068 04:47:23.778378 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4069 04:47:23.785115 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4070 04:47:23.788689 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4071 04:47:23.791737 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4072 04:47:23.795195 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4073 04:47:23.801970 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4074 04:47:23.805595 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4075 04:47:23.808396 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4076 04:47:23.808821 ==
4077 04:47:23.811564 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 04:47:23.814746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 04:47:23.818087 ==
4080 04:47:23.818504 DQS Delay:
4081 04:47:23.818839 DQS0 = 0, DQS1 = 0
4082 04:47:23.821463 DQM Delay:
4083 04:47:23.821912 DQM0 = 36, DQM1 = 30
4084 04:47:23.825144 DQ Delay:
4085 04:47:23.828350 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4086 04:47:23.828771 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4087 04:47:23.831731 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4088 04:47:23.838217 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4089 04:47:23.838635
4090 04:47:23.838972
4091 04:47:23.839283 ==
4092 04:47:23.841357 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 04:47:23.844746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 04:47:23.845185 ==
4095 04:47:23.845602
4096 04:47:23.845928
4097 04:47:23.848052 TX Vref Scan disable
4098 04:47:23.848470 == TX Byte 0 ==
4099 04:47:23.855138 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4100 04:47:23.857978 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4101 04:47:23.858401 == TX Byte 1 ==
4102 04:47:23.864679 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4103 04:47:23.868173 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4104 04:47:23.868698 ==
4105 04:47:23.871477 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 04:47:23.874804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 04:47:23.875336 ==
4108 04:47:23.875678
4109 04:47:23.875990
4110 04:47:23.877785 TX Vref Scan disable
4111 04:47:23.881287 == TX Byte 0 ==
4112 04:47:23.885072 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4113 04:47:23.888260 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4114 04:47:23.891146 == TX Byte 1 ==
4115 04:47:23.894906 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4116 04:47:23.901192 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4117 04:47:23.901743
4118 04:47:23.902082 [DATLAT]
4119 04:47:23.902395 Freq=600, CH0 RK0
4120 04:47:23.902696
4121 04:47:23.904525 DATLAT Default: 0x9
4122 04:47:23.904942 0, 0xFFFF, sum = 0
4123 04:47:23.908018 1, 0xFFFF, sum = 0
4124 04:47:23.908562 2, 0xFFFF, sum = 0
4125 04:47:23.911497 3, 0xFFFF, sum = 0
4126 04:47:23.914518 4, 0xFFFF, sum = 0
4127 04:47:23.914982 5, 0xFFFF, sum = 0
4128 04:47:23.918369 6, 0xFFFF, sum = 0
4129 04:47:23.918906 7, 0xFFFF, sum = 0
4130 04:47:23.921092 8, 0x0, sum = 1
4131 04:47:23.921563 9, 0x0, sum = 2
4132 04:47:23.921906 10, 0x0, sum = 3
4133 04:47:23.924323 11, 0x0, sum = 4
4134 04:47:23.924750 best_step = 9
4135 04:47:23.925083
4136 04:47:23.925396 ==
4137 04:47:23.927518 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 04:47:23.934412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 04:47:23.934868 ==
4140 04:47:23.935205 RX Vref Scan: 1
4141 04:47:23.935518
4142 04:47:23.937544 RX Vref 0 -> 0, step: 1
4143 04:47:23.937980
4144 04:47:23.941083 RX Delay -195 -> 252, step: 8
4145 04:47:23.941685
4146 04:47:23.944319 Set Vref, RX VrefLevel [Byte0]: 61
4147 04:47:23.947731 [Byte1]: 51
4148 04:47:23.948256
4149 04:47:23.950816 Final RX Vref Byte 0 = 61 to rank0
4150 04:47:23.954154 Final RX Vref Byte 1 = 51 to rank0
4151 04:47:23.957794 Final RX Vref Byte 0 = 61 to rank1
4152 04:47:23.961120 Final RX Vref Byte 1 = 51 to rank1==
4153 04:47:23.964049 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 04:47:23.967899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 04:47:23.968518 ==
4156 04:47:23.970889 DQS Delay:
4157 04:47:23.971412 DQS0 = 0, DQS1 = 0
4158 04:47:23.974252 DQM Delay:
4159 04:47:23.974774 DQM0 = 35, DQM1 = 29
4160 04:47:23.975119 DQ Delay:
4161 04:47:23.977347 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4162 04:47:23.980922 DQ4 =36, DQ5 =24, DQ6 =40, DQ7 =44
4163 04:47:23.983975 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =20
4164 04:47:23.987011 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4165 04:47:23.987525
4166 04:47:23.987869
4167 04:47:23.997120 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4168 04:47:24.000377 CH0 RK0: MR19=808, MR18=3B3A
4169 04:47:24.006945 CH0_RK0: MR19=0x808, MR18=0x3B3A, DQSOSC=398, MR23=63, INC=165, DEC=110
4170 04:47:24.007368
4171 04:47:24.010213 ----->DramcWriteLeveling(PI) begin...
4172 04:47:24.010638 ==
4173 04:47:24.013360 Dram Type= 6, Freq= 0, CH_0, rank 1
4174 04:47:24.016903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 04:47:24.017325 ==
4176 04:47:24.020006 Write leveling (Byte 0): 30 => 30
4177 04:47:24.023689 Write leveling (Byte 1): 33 => 33
4178 04:47:24.026883 DramcWriteLeveling(PI) end<-----
4179 04:47:24.027307
4180 04:47:24.027919 ==
4181 04:47:24.029810 Dram Type= 6, Freq= 0, CH_0, rank 1
4182 04:47:24.033243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 04:47:24.033708 ==
4184 04:47:24.036983 [Gating] SW mode calibration
4185 04:47:24.043321 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4186 04:47:24.050183 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4187 04:47:24.053345 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4188 04:47:24.056765 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4189 04:47:24.063385 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4190 04:47:24.066245 0 9 12 | B1->B0 | 3131 2f2f | 1 1 | (1 1) (1 1)
4191 04:47:24.069655 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4192 04:47:24.076835 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 04:47:24.079494 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 04:47:24.083334 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 04:47:24.089661 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 04:47:24.092741 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 04:47:24.096497 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 04:47:24.102737 0 10 12 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (0 0)
4199 04:47:24.106094 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4200 04:47:24.109405 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 04:47:24.116167 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 04:47:24.119365 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 04:47:24.122444 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 04:47:24.129042 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 04:47:24.132462 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 04:47:24.135602 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4207 04:47:24.142737 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4208 04:47:24.145567 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 04:47:24.148826 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 04:47:24.156065 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 04:47:24.159228 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 04:47:24.162497 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 04:47:24.169205 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 04:47:24.172472 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 04:47:24.175903 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 04:47:24.182362 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 04:47:24.185638 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 04:47:24.188890 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 04:47:24.195543 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 04:47:24.198720 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 04:47:24.202182 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 04:47:24.208704 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 04:47:24.212137 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 04:47:24.215176 Total UI for P1: 0, mck2ui 16
4225 04:47:24.218245 best dqsien dly found for B0: ( 0, 13, 14)
4226 04:47:24.221703 Total UI for P1: 0, mck2ui 16
4227 04:47:24.224993 best dqsien dly found for B1: ( 0, 13, 14)
4228 04:47:24.228225 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4229 04:47:24.231477 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4230 04:47:24.232015
4231 04:47:24.234667 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4232 04:47:24.238341 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4233 04:47:24.241549 [Gating] SW calibration Done
4234 04:47:24.241968 ==
4235 04:47:24.244821 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 04:47:24.251499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 04:47:24.252019 ==
4238 04:47:24.252358 RX Vref Scan: 0
4239 04:47:24.252671
4240 04:47:24.254563 RX Vref 0 -> 0, step: 1
4241 04:47:24.255009
4242 04:47:24.257900 RX Delay -230 -> 252, step: 16
4243 04:47:24.261018 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4244 04:47:24.264629 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4245 04:47:24.268198 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4246 04:47:24.274566 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4247 04:47:24.278015 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4248 04:47:24.281261 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4249 04:47:24.284347 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4250 04:47:24.291005 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4251 04:47:24.294152 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4252 04:47:24.297311 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4253 04:47:24.300838 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4254 04:47:24.304198 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4255 04:47:24.310607 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4256 04:47:24.314352 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4257 04:47:24.317306 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4258 04:47:24.320739 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4259 04:47:24.323860 ==
4260 04:47:24.327269 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 04:47:24.330371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 04:47:24.330588 ==
4263 04:47:24.330717 DQS Delay:
4264 04:47:24.333941 DQS0 = 0, DQS1 = 0
4265 04:47:24.334139 DQM Delay:
4266 04:47:24.337137 DQM0 = 36, DQM1 = 31
4267 04:47:24.337334 DQ Delay:
4268 04:47:24.340490 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4269 04:47:24.343766 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4270 04:47:24.346843 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4271 04:47:24.350458 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4272 04:47:24.350635
4273 04:47:24.350766
4274 04:47:24.350880 ==
4275 04:47:24.353704 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 04:47:24.357075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 04:47:24.357164 ==
4278 04:47:24.357230
4279 04:47:24.357290
4280 04:47:24.360281 TX Vref Scan disable
4281 04:47:24.363658 == TX Byte 0 ==
4282 04:47:24.366801 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4283 04:47:24.370243 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4284 04:47:24.373457 == TX Byte 1 ==
4285 04:47:24.376757 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4286 04:47:24.379992 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4287 04:47:24.380075 ==
4288 04:47:24.383355 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 04:47:24.389830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 04:47:24.389912 ==
4291 04:47:24.389976
4292 04:47:24.390035
4293 04:47:24.390091 TX Vref Scan disable
4294 04:47:24.394067 == TX Byte 0 ==
4295 04:47:24.397708 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4296 04:47:24.404627 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4297 04:47:24.404708 == TX Byte 1 ==
4298 04:47:24.407526 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4299 04:47:24.414123 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4300 04:47:24.414205
4301 04:47:24.414269 [DATLAT]
4302 04:47:24.414329 Freq=600, CH0 RK1
4303 04:47:24.414386
4304 04:47:24.417433 DATLAT Default: 0x9
4305 04:47:24.417549 0, 0xFFFF, sum = 0
4306 04:47:24.420971 1, 0xFFFF, sum = 0
4307 04:47:24.421051 2, 0xFFFF, sum = 0
4308 04:47:24.424013 3, 0xFFFF, sum = 0
4309 04:47:24.427562 4, 0xFFFF, sum = 0
4310 04:47:24.427643 5, 0xFFFF, sum = 0
4311 04:47:24.430623 6, 0xFFFF, sum = 0
4312 04:47:24.430709 7, 0xFFFF, sum = 0
4313 04:47:24.434207 8, 0x0, sum = 1
4314 04:47:24.434289 9, 0x0, sum = 2
4315 04:47:24.434354 10, 0x0, sum = 3
4316 04:47:24.437299 11, 0x0, sum = 4
4317 04:47:24.437410 best_step = 9
4318 04:47:24.437538
4319 04:47:24.437632 ==
4320 04:47:24.440924 Dram Type= 6, Freq= 0, CH_0, rank 1
4321 04:47:24.447373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 04:47:24.447510 ==
4323 04:47:24.447590 RX Vref Scan: 0
4324 04:47:24.447652
4325 04:47:24.450630 RX Vref 0 -> 0, step: 1
4326 04:47:24.450712
4327 04:47:24.453857 RX Delay -195 -> 252, step: 8
4328 04:47:24.457498 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4329 04:47:24.463994 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4330 04:47:24.467278 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4331 04:47:24.470551 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4332 04:47:24.473794 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4333 04:47:24.480619 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4334 04:47:24.483971 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4335 04:47:24.487283 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4336 04:47:24.490518 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4337 04:47:24.493708 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4338 04:47:24.500253 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4339 04:47:24.503756 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4340 04:47:24.507032 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4341 04:47:24.510023 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4342 04:47:24.516873 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4343 04:47:24.520050 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4344 04:47:24.520163 ==
4345 04:47:24.523471 Dram Type= 6, Freq= 0, CH_0, rank 1
4346 04:47:24.526621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 04:47:24.526724 ==
4348 04:47:24.530118 DQS Delay:
4349 04:47:24.530221 DQS0 = 0, DQS1 = 0
4350 04:47:24.533450 DQM Delay:
4351 04:47:24.533556 DQM0 = 33, DQM1 = 28
4352 04:47:24.533622 DQ Delay:
4353 04:47:24.536548 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4354 04:47:24.540064 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4355 04:47:24.543158 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4356 04:47:24.546624 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4357 04:47:24.546705
4358 04:47:24.546770
4359 04:47:24.556273 [DQSOSCAuto] RK1, (LSB)MR18= 0x7240, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4360 04:47:24.559965 CH0 RK1: MR19=808, MR18=7240
4361 04:47:24.566704 CH0_RK1: MR19=0x808, MR18=0x7240, DQSOSC=388, MR23=63, INC=174, DEC=116
4362 04:47:24.566784 [RxdqsGatingPostProcess] freq 600
4363 04:47:24.573068 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4364 04:47:24.576804 Pre-setting of DQS Precalculation
4365 04:47:24.580021 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4366 04:47:24.583403 ==
4367 04:47:24.583582 Dram Type= 6, Freq= 0, CH_1, rank 0
4368 04:47:24.589789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 04:47:24.589977 ==
4370 04:47:24.593438 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4371 04:47:24.599985 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4372 04:47:24.603968 [CA 0] Center 35 (5~66) winsize 62
4373 04:47:24.607160 [CA 1] Center 35 (5~66) winsize 62
4374 04:47:24.610408 [CA 2] Center 34 (4~65) winsize 62
4375 04:47:24.613455 [CA 3] Center 34 (4~65) winsize 62
4376 04:47:24.617002 [CA 4] Center 34 (4~65) winsize 62
4377 04:47:24.620410 [CA 5] Center 33 (3~64) winsize 62
4378 04:47:24.620735
4379 04:47:24.623443 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4380 04:47:24.623742
4381 04:47:24.626973 [CATrainingPosCal] consider 1 rank data
4382 04:47:24.630429 u2DelayCellTimex100 = 270/100 ps
4383 04:47:24.633449 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4384 04:47:24.640317 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4385 04:47:24.643387 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4386 04:47:24.646738 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4387 04:47:24.650463 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4388 04:47:24.653905 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4389 04:47:24.654426
4390 04:47:24.656944 CA PerBit enable=1, Macro0, CA PI delay=33
4391 04:47:24.657465
4392 04:47:24.660388 [CBTSetCACLKResult] CA Dly = 33
4393 04:47:24.663628 CS Dly: 4 (0~35)
4394 04:47:24.664149 ==
4395 04:47:24.666702 Dram Type= 6, Freq= 0, CH_1, rank 1
4396 04:47:24.670108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 04:47:24.670635 ==
4398 04:47:24.676519 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4399 04:47:24.679994 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4400 04:47:24.684327 [CA 0] Center 36 (6~66) winsize 61
4401 04:47:24.687355 [CA 1] Center 36 (6~67) winsize 62
4402 04:47:24.690406 [CA 2] Center 34 (4~65) winsize 62
4403 04:47:24.693821 [CA 3] Center 34 (3~65) winsize 63
4404 04:47:24.697287 [CA 4] Center 34 (4~65) winsize 62
4405 04:47:24.700452 [CA 5] Center 33 (3~64) winsize 62
4406 04:47:24.700877
4407 04:47:24.703897 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4408 04:47:24.704444
4409 04:47:24.707217 [CATrainingPosCal] consider 2 rank data
4410 04:47:24.710804 u2DelayCellTimex100 = 270/100 ps
4411 04:47:24.713783 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4412 04:47:24.720654 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4413 04:47:24.723449 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4414 04:47:24.727023 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4415 04:47:24.730004 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4416 04:47:24.733307 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 04:47:24.733820
4418 04:47:24.736559 CA PerBit enable=1, Macro0, CA PI delay=33
4419 04:47:24.736983
4420 04:47:24.739954 [CBTSetCACLKResult] CA Dly = 33
4421 04:47:24.740378 CS Dly: 5 (0~37)
4422 04:47:24.743783
4423 04:47:24.746757 ----->DramcWriteLeveling(PI) begin...
4424 04:47:24.747194 ==
4425 04:47:24.750319 Dram Type= 6, Freq= 0, CH_1, rank 0
4426 04:47:24.753506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4427 04:47:24.753937 ==
4428 04:47:24.756702 Write leveling (Byte 0): 29 => 29
4429 04:47:24.760535 Write leveling (Byte 1): 29 => 29
4430 04:47:24.763261 DramcWriteLeveling(PI) end<-----
4431 04:47:24.763682
4432 04:47:24.764015 ==
4433 04:47:24.766527 Dram Type= 6, Freq= 0, CH_1, rank 0
4434 04:47:24.769907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4435 04:47:24.770330 ==
4436 04:47:24.773519 [Gating] SW mode calibration
4437 04:47:24.780267 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4438 04:47:24.786776 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4439 04:47:24.789730 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4440 04:47:24.793263 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4441 04:47:24.800005 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 04:47:24.802816 0 9 12 | B1->B0 | 3030 3030 | 0 1 | (0 0) (1 0)
4443 04:47:24.806518 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
4444 04:47:24.813366 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 04:47:24.816749 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 04:47:24.819865 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 04:47:24.826462 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 04:47:24.829648 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 04:47:24.832773 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 04:47:24.839800 0 10 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (1 1)
4451 04:47:24.842819 0 10 16 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
4452 04:47:24.846287 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 04:47:24.849387 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 04:47:24.856385 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 04:47:24.859745 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 04:47:24.862628 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 04:47:24.869251 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 04:47:24.872610 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4459 04:47:24.875991 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4460 04:47:24.882616 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 04:47:24.885656 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 04:47:24.889013 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 04:47:24.896032 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 04:47:24.898960 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 04:47:24.902646 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 04:47:24.909155 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 04:47:24.912318 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 04:47:24.915737 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 04:47:24.921952 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 04:47:24.925417 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 04:47:24.928843 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 04:47:24.935388 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 04:47:24.938794 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 04:47:24.942006 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4475 04:47:24.948632 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4476 04:47:24.951913 Total UI for P1: 0, mck2ui 16
4477 04:47:24.955011 best dqsien dly found for B0: ( 0, 13, 14)
4478 04:47:24.958428 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 04:47:24.961849 Total UI for P1: 0, mck2ui 16
4480 04:47:24.964881 best dqsien dly found for B1: ( 0, 13, 14)
4481 04:47:24.968255 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4482 04:47:24.971524 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4483 04:47:24.971707
4484 04:47:24.974780 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4485 04:47:24.981295 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4486 04:47:24.981426 [Gating] SW calibration Done
4487 04:47:24.981542 ==
4488 04:47:24.984563 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 04:47:24.991320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 04:47:24.991403 ==
4491 04:47:24.991476 RX Vref Scan: 0
4492 04:47:24.991546
4493 04:47:24.994547 RX Vref 0 -> 0, step: 1
4494 04:47:24.994654
4495 04:47:24.997916 RX Delay -230 -> 252, step: 16
4496 04:47:25.001271 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4497 04:47:25.004395 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4498 04:47:25.007761 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4499 04:47:25.014267 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4500 04:47:25.017830 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4501 04:47:25.020993 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4502 04:47:25.024537 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4503 04:47:25.031115 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4504 04:47:25.034409 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4505 04:47:25.037540 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4506 04:47:25.040838 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4507 04:47:25.047557 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4508 04:47:25.050726 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4509 04:47:25.054077 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4510 04:47:25.057420 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4511 04:47:25.064112 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4512 04:47:25.064194 ==
4513 04:47:25.067319 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 04:47:25.070442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 04:47:25.070525 ==
4516 04:47:25.070592 DQS Delay:
4517 04:47:25.073911 DQS0 = 0, DQS1 = 0
4518 04:47:25.073995 DQM Delay:
4519 04:47:25.077404 DQM0 = 38, DQM1 = 28
4520 04:47:25.077513 DQ Delay:
4521 04:47:25.080457 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4522 04:47:25.083815 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4523 04:47:25.087193 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4524 04:47:25.090573 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4525 04:47:25.090656
4526 04:47:25.090757
4527 04:47:25.090855 ==
4528 04:47:25.093876 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 04:47:25.097101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 04:47:25.097227 ==
4531 04:47:25.097307
4532 04:47:25.097386
4533 04:47:25.100273 TX Vref Scan disable
4534 04:47:25.103510 == TX Byte 0 ==
4535 04:47:25.107227 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4536 04:47:25.110153 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4537 04:47:25.113580 == TX Byte 1 ==
4538 04:47:25.117033 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4539 04:47:25.120782 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4540 04:47:25.120872 ==
4541 04:47:25.123680 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 04:47:25.130084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 04:47:25.130192 ==
4544 04:47:25.130285
4545 04:47:25.130373
4546 04:47:25.130470 TX Vref Scan disable
4547 04:47:25.134514 == TX Byte 0 ==
4548 04:47:25.137987 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4549 04:47:25.144711 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4550 04:47:25.144795 == TX Byte 1 ==
4551 04:47:25.147727 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4552 04:47:25.154588 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4553 04:47:25.154671
4554 04:47:25.154736 [DATLAT]
4555 04:47:25.154797 Freq=600, CH1 RK0
4556 04:47:25.154856
4557 04:47:25.157912 DATLAT Default: 0x9
4558 04:47:25.157994 0, 0xFFFF, sum = 0
4559 04:47:25.161277 1, 0xFFFF, sum = 0
4560 04:47:25.161387 2, 0xFFFF, sum = 0
4561 04:47:25.164408 3, 0xFFFF, sum = 0
4562 04:47:25.167586 4, 0xFFFF, sum = 0
4563 04:47:25.167685 5, 0xFFFF, sum = 0
4564 04:47:25.171172 6, 0xFFFF, sum = 0
4565 04:47:25.171255 7, 0xFFFF, sum = 0
4566 04:47:25.174622 8, 0x0, sum = 1
4567 04:47:25.174705 9, 0x0, sum = 2
4568 04:47:25.174771 10, 0x0, sum = 3
4569 04:47:25.177890 11, 0x0, sum = 4
4570 04:47:25.177974 best_step = 9
4571 04:47:25.178039
4572 04:47:25.178100 ==
4573 04:47:25.180996 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 04:47:25.187612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 04:47:25.187694 ==
4576 04:47:25.187760 RX Vref Scan: 1
4577 04:47:25.187820
4578 04:47:25.191144 RX Vref 0 -> 0, step: 1
4579 04:47:25.191226
4580 04:47:25.194234 RX Delay -195 -> 252, step: 8
4581 04:47:25.194316
4582 04:47:25.197816 Set Vref, RX VrefLevel [Byte0]: 55
4583 04:47:25.200769 [Byte1]: 51
4584 04:47:25.200852
4585 04:47:25.204539 Final RX Vref Byte 0 = 55 to rank0
4586 04:47:25.207475 Final RX Vref Byte 1 = 51 to rank0
4587 04:47:25.211180 Final RX Vref Byte 0 = 55 to rank1
4588 04:47:25.214269 Final RX Vref Byte 1 = 51 to rank1==
4589 04:47:25.217446 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 04:47:25.221259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 04:47:25.221365 ==
4592 04:47:25.224332 DQS Delay:
4593 04:47:25.224413 DQS0 = 0, DQS1 = 0
4594 04:47:25.227728 DQM Delay:
4595 04:47:25.227811 DQM0 = 39, DQM1 = 29
4596 04:47:25.227877 DQ Delay:
4597 04:47:25.230689 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4598 04:47:25.234381 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4599 04:47:25.237241 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =24
4600 04:47:25.241023 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4601 04:47:25.241106
4602 04:47:25.241170
4603 04:47:25.250971 [DQSOSCAuto] RK0, (LSB)MR18= 0x2331, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4604 04:47:25.254216 CH1 RK0: MR19=808, MR18=2331
4605 04:47:25.260490 CH1_RK0: MR19=0x808, MR18=0x2331, DQSOSC=400, MR23=63, INC=163, DEC=109
4606 04:47:25.260573
4607 04:47:25.263987 ----->DramcWriteLeveling(PI) begin...
4608 04:47:25.264072 ==
4609 04:47:25.267355 Dram Type= 6, Freq= 0, CH_1, rank 1
4610 04:47:25.270571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 04:47:25.270654 ==
4612 04:47:25.273915 Write leveling (Byte 0): 29 => 29
4613 04:47:25.277272 Write leveling (Byte 1): 30 => 30
4614 04:47:25.280671 DramcWriteLeveling(PI) end<-----
4615 04:47:25.280749
4616 04:47:25.280831 ==
4617 04:47:25.283941 Dram Type= 6, Freq= 0, CH_1, rank 1
4618 04:47:25.286978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 04:47:25.287062 ==
4620 04:47:25.290432 [Gating] SW mode calibration
4621 04:47:25.297104 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4622 04:47:25.303937 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4623 04:47:25.306864 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4624 04:47:25.310300 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4625 04:47:25.317061 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4626 04:47:25.320307 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (1 1)
4627 04:47:25.323841 0 9 16 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
4628 04:47:25.330264 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 04:47:25.333601 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 04:47:25.336729 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 04:47:25.343568 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 04:47:25.346835 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 04:47:25.350386 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4634 04:47:25.356853 0 10 12 | B1->B0 | 3131 3939 | 0 0 | (0 0) (0 0)
4635 04:47:25.360485 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4636 04:47:25.363464 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 04:47:25.370091 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 04:47:25.373717 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 04:47:25.376839 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 04:47:25.380175 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 04:47:25.386625 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 04:47:25.389999 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 04:47:25.393274 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 04:47:25.399903 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 04:47:25.403176 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 04:47:25.406725 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 04:47:25.413246 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 04:47:25.416190 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 04:47:25.419848 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 04:47:25.426248 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 04:47:25.429682 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 04:47:25.432747 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 04:47:25.439611 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 04:47:25.443066 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 04:47:25.446200 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 04:47:25.452716 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 04:47:25.456351 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4658 04:47:25.459261 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4659 04:47:25.465787 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 04:47:25.469264 Total UI for P1: 0, mck2ui 16
4661 04:47:25.472762 best dqsien dly found for B0: ( 0, 13, 10)
4662 04:47:25.472845 Total UI for P1: 0, mck2ui 16
4663 04:47:25.479626 best dqsien dly found for B1: ( 0, 13, 14)
4664 04:47:25.482835 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4665 04:47:25.486042 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4666 04:47:25.486125
4667 04:47:25.489127 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4668 04:47:25.492616 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4669 04:47:25.495649 [Gating] SW calibration Done
4670 04:47:25.495732 ==
4671 04:47:25.499166 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 04:47:25.502696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 04:47:25.502779 ==
4674 04:47:25.505860 RX Vref Scan: 0
4675 04:47:25.505941
4676 04:47:25.509414 RX Vref 0 -> 0, step: 1
4677 04:47:25.509522
4678 04:47:25.509589 RX Delay -230 -> 252, step: 16
4679 04:47:25.516263 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4680 04:47:25.519636 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4681 04:47:25.522751 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4682 04:47:25.525855 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4683 04:47:25.532568 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4684 04:47:25.536057 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4685 04:47:25.539257 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4686 04:47:25.542376 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4687 04:47:25.545666 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4688 04:47:25.552600 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4689 04:47:25.555923 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4690 04:47:25.558970 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4691 04:47:25.562415 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4692 04:47:25.568933 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4693 04:47:25.572300 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4694 04:47:25.575482 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4695 04:47:25.575556 ==
4696 04:47:25.578745 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 04:47:25.582082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 04:47:25.585544 ==
4699 04:47:25.585707 DQS Delay:
4700 04:47:25.585785 DQS0 = 0, DQS1 = 0
4701 04:47:25.589029 DQM Delay:
4702 04:47:25.589197 DQM0 = 37, DQM1 = 32
4703 04:47:25.592325 DQ Delay:
4704 04:47:25.595544 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4705 04:47:25.595717 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4706 04:47:25.598966 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4707 04:47:25.601817 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4708 04:47:25.605276
4709 04:47:25.605465
4710 04:47:25.605579 ==
4711 04:47:25.608527 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 04:47:25.612169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 04:47:25.612385 ==
4714 04:47:25.612562
4715 04:47:25.612684
4716 04:47:25.614921 TX Vref Scan disable
4717 04:47:25.615087 == TX Byte 0 ==
4718 04:47:25.621975 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4719 04:47:25.625055 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4720 04:47:25.625229 == TX Byte 1 ==
4721 04:47:25.631996 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4722 04:47:25.635350 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4723 04:47:25.635559 ==
4724 04:47:25.638721 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 04:47:25.641968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 04:47:25.642217 ==
4727 04:47:25.642475
4728 04:47:25.642714
4729 04:47:25.645044 TX Vref Scan disable
4730 04:47:25.648852 == TX Byte 0 ==
4731 04:47:25.652560 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4732 04:47:25.655655 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4733 04:47:25.658825 == TX Byte 1 ==
4734 04:47:25.662188 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4735 04:47:25.668891 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4736 04:47:25.669412
4737 04:47:25.669803 [DATLAT]
4738 04:47:25.670123 Freq=600, CH1 RK1
4739 04:47:25.670430
4740 04:47:25.671701 DATLAT Default: 0x9
4741 04:47:25.672124 0, 0xFFFF, sum = 0
4742 04:47:25.674910 1, 0xFFFF, sum = 0
4743 04:47:25.675344 2, 0xFFFF, sum = 0
4744 04:47:25.678784 3, 0xFFFF, sum = 0
4745 04:47:25.682254 4, 0xFFFF, sum = 0
4746 04:47:25.682773 5, 0xFFFF, sum = 0
4747 04:47:25.685381 6, 0xFFFF, sum = 0
4748 04:47:25.685949 7, 0xFFFF, sum = 0
4749 04:47:25.688846 8, 0x0, sum = 1
4750 04:47:25.689372 9, 0x0, sum = 2
4751 04:47:25.689784 10, 0x0, sum = 3
4752 04:47:25.691927 11, 0x0, sum = 4
4753 04:47:25.692589 best_step = 9
4754 04:47:25.693014
4755 04:47:25.694903 ==
4756 04:47:25.695323 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 04:47:25.701540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 04:47:25.702134 ==
4759 04:47:25.702486 RX Vref Scan: 0
4760 04:47:25.702804
4761 04:47:25.705085 RX Vref 0 -> 0, step: 1
4762 04:47:25.705642
4763 04:47:25.707884 RX Delay -195 -> 252, step: 8
4764 04:47:25.715104 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4765 04:47:25.718110 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4766 04:47:25.721611 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4767 04:47:25.724891 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4768 04:47:25.728247 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4769 04:47:25.734592 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4770 04:47:25.737999 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4771 04:47:25.741461 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4772 04:47:25.744765 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4773 04:47:25.751445 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4774 04:47:25.754398 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4775 04:47:25.757717 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4776 04:47:25.761247 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4777 04:47:25.768011 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4778 04:47:25.771064 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4779 04:47:25.774416 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4780 04:47:25.774953 ==
4781 04:47:25.777831 Dram Type= 6, Freq= 0, CH_1, rank 1
4782 04:47:25.780621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4783 04:47:25.781048 ==
4784 04:47:25.784478 DQS Delay:
4785 04:47:25.785007 DQS0 = 0, DQS1 = 0
4786 04:47:25.787754 DQM Delay:
4787 04:47:25.788287 DQM0 = 36, DQM1 = 29
4788 04:47:25.788635 DQ Delay:
4789 04:47:25.790544 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4790 04:47:25.794192 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4791 04:47:25.797174 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4792 04:47:25.800933 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4793 04:47:25.801454
4794 04:47:25.804048
4795 04:47:25.810878 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a5a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4796 04:47:25.814099 CH1 RK1: MR19=808, MR18=3A5A
4797 04:47:25.820519 CH1_RK1: MR19=0x808, MR18=0x3A5A, DQSOSC=392, MR23=63, INC=170, DEC=113
4798 04:47:25.823702 [RxdqsGatingPostProcess] freq 600
4799 04:47:25.827070 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4800 04:47:25.830438 Pre-setting of DQS Precalculation
4801 04:47:25.837164 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4802 04:47:25.843881 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4803 04:47:25.850067 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4804 04:47:25.850572
4805 04:47:25.850908
4806 04:47:25.853454 [Calibration Summary] 1200 Mbps
4807 04:47:25.853909 CH 0, Rank 0
4808 04:47:25.856962 SW Impedance : PASS
4809 04:47:25.860240 DUTY Scan : NO K
4810 04:47:25.860787 ZQ Calibration : PASS
4811 04:47:25.863459 Jitter Meter : NO K
4812 04:47:25.866629 CBT Training : PASS
4813 04:47:25.867051 Write leveling : PASS
4814 04:47:25.870232 RX DQS gating : PASS
4815 04:47:25.870751 RX DQ/DQS(RDDQC) : PASS
4816 04:47:25.873934 TX DQ/DQS : PASS
4817 04:47:25.876850 RX DATLAT : PASS
4818 04:47:25.877369 RX DQ/DQS(Engine): PASS
4819 04:47:25.880156 TX OE : NO K
4820 04:47:25.880582 All Pass.
4821 04:47:25.880921
4822 04:47:25.883386 CH 0, Rank 1
4823 04:47:25.883906 SW Impedance : PASS
4824 04:47:25.886827 DUTY Scan : NO K
4825 04:47:25.889629 ZQ Calibration : PASS
4826 04:47:25.890054 Jitter Meter : NO K
4827 04:47:25.893435 CBT Training : PASS
4828 04:47:25.896413 Write leveling : PASS
4829 04:47:25.896947 RX DQS gating : PASS
4830 04:47:25.899785 RX DQ/DQS(RDDQC) : PASS
4831 04:47:25.903222 TX DQ/DQS : PASS
4832 04:47:25.903750 RX DATLAT : PASS
4833 04:47:25.906223 RX DQ/DQS(Engine): PASS
4834 04:47:25.909976 TX OE : NO K
4835 04:47:25.910494 All Pass.
4836 04:47:25.910836
4837 04:47:25.911153 CH 1, Rank 0
4838 04:47:25.912875 SW Impedance : PASS
4839 04:47:25.915878 DUTY Scan : NO K
4840 04:47:25.916302 ZQ Calibration : PASS
4841 04:47:25.919453 Jitter Meter : NO K
4842 04:47:25.922811 CBT Training : PASS
4843 04:47:25.923338 Write leveling : PASS
4844 04:47:25.926018 RX DQS gating : PASS
4845 04:47:25.929064 RX DQ/DQS(RDDQC) : PASS
4846 04:47:25.929602 TX DQ/DQS : PASS
4847 04:47:25.932536 RX DATLAT : PASS
4848 04:47:25.932957 RX DQ/DQS(Engine): PASS
4849 04:47:25.935843 TX OE : NO K
4850 04:47:25.936269 All Pass.
4851 04:47:25.936606
4852 04:47:25.939718 CH 1, Rank 1
4853 04:47:25.940237 SW Impedance : PASS
4854 04:47:25.942488 DUTY Scan : NO K
4855 04:47:25.945992 ZQ Calibration : PASS
4856 04:47:25.946433 Jitter Meter : NO K
4857 04:47:25.949265 CBT Training : PASS
4858 04:47:25.952345 Write leveling : PASS
4859 04:47:25.952929 RX DQS gating : PASS
4860 04:47:25.955636 RX DQ/DQS(RDDQC) : PASS
4861 04:47:25.959218 TX DQ/DQS : PASS
4862 04:47:25.959637 RX DATLAT : PASS
4863 04:47:25.962453 RX DQ/DQS(Engine): PASS
4864 04:47:25.965628 TX OE : NO K
4865 04:47:25.966048 All Pass.
4866 04:47:25.966381
4867 04:47:25.969404 DramC Write-DBI off
4868 04:47:25.969878 PER_BANK_REFRESH: Hybrid Mode
4869 04:47:25.972421 TX_TRACKING: ON
4870 04:47:25.978679 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4871 04:47:25.985636 [FAST_K] Save calibration result to emmc
4872 04:47:25.988905 dramc_set_vcore_voltage set vcore to 662500
4873 04:47:25.989430 Read voltage for 933, 3
4874 04:47:25.992238 Vio18 = 0
4875 04:47:25.992661 Vcore = 662500
4876 04:47:25.992997 Vdram = 0
4877 04:47:25.995456 Vddq = 0
4878 04:47:25.995879 Vmddr = 0
4879 04:47:25.998862 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4880 04:47:26.005612 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4881 04:47:26.008620 MEM_TYPE=3, freq_sel=17
4882 04:47:26.011983 sv_algorithm_assistance_LP4_1600
4883 04:47:26.015324 ============ PULL DRAM RESETB DOWN ============
4884 04:47:26.018452 ========== PULL DRAM RESETB DOWN end =========
4885 04:47:26.025366 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4886 04:47:26.028466 ===================================
4887 04:47:26.028887 LPDDR4 DRAM CONFIGURATION
4888 04:47:26.032219 ===================================
4889 04:47:26.035104 EX_ROW_EN[0] = 0x0
4890 04:47:26.035549 EX_ROW_EN[1] = 0x0
4891 04:47:26.038502 LP4Y_EN = 0x0
4892 04:47:26.038918 WORK_FSP = 0x0
4893 04:47:26.041975 WL = 0x3
4894 04:47:26.044902 RL = 0x3
4895 04:47:26.045318 BL = 0x2
4896 04:47:26.048525 RPST = 0x0
4897 04:47:26.049007 RD_PRE = 0x0
4898 04:47:26.051691 WR_PRE = 0x1
4899 04:47:26.052117 WR_PST = 0x0
4900 04:47:26.054884 DBI_WR = 0x0
4901 04:47:26.055307 DBI_RD = 0x0
4902 04:47:26.058778 OTF = 0x1
4903 04:47:26.061869 ===================================
4904 04:47:26.065153 ===================================
4905 04:47:26.065604 ANA top config
4906 04:47:26.068517 ===================================
4907 04:47:26.071516 DLL_ASYNC_EN = 0
4908 04:47:26.075397 ALL_SLAVE_EN = 1
4909 04:47:26.075964 NEW_RANK_MODE = 1
4910 04:47:26.077994 DLL_IDLE_MODE = 1
4911 04:47:26.081835 LP45_APHY_COMB_EN = 1
4912 04:47:26.084874 TX_ODT_DIS = 1
4913 04:47:26.088059 NEW_8X_MODE = 1
4914 04:47:26.091434 ===================================
4915 04:47:26.094611 ===================================
4916 04:47:26.095038 data_rate = 1866
4917 04:47:26.098150 CKR = 1
4918 04:47:26.101623 DQ_P2S_RATIO = 8
4919 04:47:26.105092 ===================================
4920 04:47:26.107950 CA_P2S_RATIO = 8
4921 04:47:26.111309 DQ_CA_OPEN = 0
4922 04:47:26.114971 DQ_SEMI_OPEN = 0
4923 04:47:26.115503 CA_SEMI_OPEN = 0
4924 04:47:26.118035 CA_FULL_RATE = 0
4925 04:47:26.121150 DQ_CKDIV4_EN = 1
4926 04:47:26.124541 CA_CKDIV4_EN = 1
4927 04:47:26.128255 CA_PREDIV_EN = 0
4928 04:47:26.130978 PH8_DLY = 0
4929 04:47:26.131413 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4930 04:47:26.134309 DQ_AAMCK_DIV = 4
4931 04:47:26.137534 CA_AAMCK_DIV = 4
4932 04:47:26.140985 CA_ADMCK_DIV = 4
4933 04:47:26.144551 DQ_TRACK_CA_EN = 0
4934 04:47:26.147511 CA_PICK = 933
4935 04:47:26.150864 CA_MCKIO = 933
4936 04:47:26.151333 MCKIO_SEMI = 0
4937 04:47:26.154404 PLL_FREQ = 3732
4938 04:47:26.157648 DQ_UI_PI_RATIO = 32
4939 04:47:26.161019 CA_UI_PI_RATIO = 0
4940 04:47:26.164424 ===================================
4941 04:47:26.167901 ===================================
4942 04:47:26.171391 memory_type:LPDDR4
4943 04:47:26.171935 GP_NUM : 10
4944 04:47:26.174354 SRAM_EN : 1
4945 04:47:26.177606 MD32_EN : 0
4946 04:47:26.180859 ===================================
4947 04:47:26.181375 [ANA_INIT] >>>>>>>>>>>>>>
4948 04:47:26.184029 <<<<<< [CONFIGURE PHASE]: ANA_TX
4949 04:47:26.187293 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4950 04:47:26.190768 ===================================
4951 04:47:26.194168 data_rate = 1866,PCW = 0X8f00
4952 04:47:26.197543 ===================================
4953 04:47:26.200712 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4954 04:47:26.207555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4955 04:47:26.210997 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4956 04:47:26.217627 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4957 04:47:26.220881 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4958 04:47:26.224029 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4959 04:47:26.224554 [ANA_INIT] flow start
4960 04:47:26.227101 [ANA_INIT] PLL >>>>>>>>
4961 04:47:26.230382 [ANA_INIT] PLL <<<<<<<<
4962 04:47:26.230854 [ANA_INIT] MIDPI >>>>>>>>
4963 04:47:26.233742 [ANA_INIT] MIDPI <<<<<<<<
4964 04:47:26.237212 [ANA_INIT] DLL >>>>>>>>
4965 04:47:26.237689 [ANA_INIT] flow end
4966 04:47:26.244015 ============ LP4 DIFF to SE enter ============
4967 04:47:26.247529 ============ LP4 DIFF to SE exit ============
4968 04:47:26.250322 [ANA_INIT] <<<<<<<<<<<<<
4969 04:47:26.253788 [Flow] Enable top DCM control >>>>>
4970 04:47:26.257248 [Flow] Enable top DCM control <<<<<
4971 04:47:26.257720 Enable DLL master slave shuffle
4972 04:47:26.263689 ==============================================================
4973 04:47:26.266784 Gating Mode config
4974 04:47:26.270153 ==============================================================
4975 04:47:26.273425 Config description:
4976 04:47:26.283779 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4977 04:47:26.290363 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4978 04:47:26.293533 SELPH_MODE 0: By rank 1: By Phase
4979 04:47:26.300470 ==============================================================
4980 04:47:26.303279 GAT_TRACK_EN = 1
4981 04:47:26.306372 RX_GATING_MODE = 2
4982 04:47:26.310040 RX_GATING_TRACK_MODE = 2
4983 04:47:26.313131 SELPH_MODE = 1
4984 04:47:26.316718 PICG_EARLY_EN = 1
4985 04:47:26.320081 VALID_LAT_VALUE = 1
4986 04:47:26.322853 ==============================================================
4987 04:47:26.326424 Enter into Gating configuration >>>>
4988 04:47:26.329963 Exit from Gating configuration <<<<
4989 04:47:26.333318 Enter into DVFS_PRE_config >>>>>
4990 04:47:26.342891 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4991 04:47:26.346192 Exit from DVFS_PRE_config <<<<<
4992 04:47:26.349294 Enter into PICG configuration >>>>
4993 04:47:26.352801 Exit from PICG configuration <<<<
4994 04:47:26.356343 [RX_INPUT] configuration >>>>>
4995 04:47:26.360149 [RX_INPUT] configuration <<<<<
4996 04:47:26.366222 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4997 04:47:26.369362 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4998 04:47:26.376273 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4999 04:47:26.383086 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5000 04:47:26.389377 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5001 04:47:26.395803 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5002 04:47:26.399506 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5003 04:47:26.402802 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5004 04:47:26.405987 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5005 04:47:26.412707 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5006 04:47:26.416267 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5007 04:47:26.419519 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5008 04:47:26.422442 ===================================
5009 04:47:26.425996 LPDDR4 DRAM CONFIGURATION
5010 04:47:26.429469 ===================================
5011 04:47:26.430031 EX_ROW_EN[0] = 0x0
5012 04:47:26.432456 EX_ROW_EN[1] = 0x0
5013 04:47:26.435356 LP4Y_EN = 0x0
5014 04:47:26.435780 WORK_FSP = 0x0
5015 04:47:26.438724 WL = 0x3
5016 04:47:26.439183 RL = 0x3
5017 04:47:26.442059 BL = 0x2
5018 04:47:26.442482 RPST = 0x0
5019 04:47:26.445472 RD_PRE = 0x0
5020 04:47:26.445926 WR_PRE = 0x1
5021 04:47:26.449288 WR_PST = 0x0
5022 04:47:26.449908 DBI_WR = 0x0
5023 04:47:26.452253 DBI_RD = 0x0
5024 04:47:26.452772 OTF = 0x1
5025 04:47:26.455727 ===================================
5026 04:47:26.458985 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5027 04:47:26.465735 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5028 04:47:26.468902 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5029 04:47:26.472341 ===================================
5030 04:47:26.475248 LPDDR4 DRAM CONFIGURATION
5031 04:47:26.478539 ===================================
5032 04:47:26.479006 EX_ROW_EN[0] = 0x10
5033 04:47:26.481589 EX_ROW_EN[1] = 0x0
5034 04:47:26.485336 LP4Y_EN = 0x0
5035 04:47:26.485897 WORK_FSP = 0x0
5036 04:47:26.488754 WL = 0x3
5037 04:47:26.489303 RL = 0x3
5038 04:47:26.491466 BL = 0x2
5039 04:47:26.491882 RPST = 0x0
5040 04:47:26.495123 RD_PRE = 0x0
5041 04:47:26.495539 WR_PRE = 0x1
5042 04:47:26.498147 WR_PST = 0x0
5043 04:47:26.498565 DBI_WR = 0x0
5044 04:47:26.501851 DBI_RD = 0x0
5045 04:47:26.502445 OTF = 0x1
5046 04:47:26.504822 ===================================
5047 04:47:26.511634 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5048 04:47:26.516244 nWR fixed to 30
5049 04:47:26.519621 [ModeRegInit_LP4] CH0 RK0
5050 04:47:26.520140 [ModeRegInit_LP4] CH0 RK1
5051 04:47:26.522860 [ModeRegInit_LP4] CH1 RK0
5052 04:47:26.526012 [ModeRegInit_LP4] CH1 RK1
5053 04:47:26.526427 match AC timing 9
5054 04:47:26.532955 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5055 04:47:26.535760 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5056 04:47:26.539135 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5057 04:47:26.545894 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5058 04:47:26.549228 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5059 04:47:26.549684 ==
5060 04:47:26.552676 Dram Type= 6, Freq= 0, CH_0, rank 0
5061 04:47:26.556144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5062 04:47:26.556667 ==
5063 04:47:26.562489 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5064 04:47:26.569275 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5065 04:47:26.572453 [CA 0] Center 38 (8~69) winsize 62
5066 04:47:26.575740 [CA 1] Center 38 (8~68) winsize 61
5067 04:47:26.579290 [CA 2] Center 35 (5~65) winsize 61
5068 04:47:26.582353 [CA 3] Center 35 (5~65) winsize 61
5069 04:47:26.585392 [CA 4] Center 34 (4~64) winsize 61
5070 04:47:26.589100 [CA 5] Center 33 (3~64) winsize 62
5071 04:47:26.589663
5072 04:47:26.592136 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5073 04:47:26.592550
5074 04:47:26.595792 [CATrainingPosCal] consider 1 rank data
5075 04:47:26.599015 u2DelayCellTimex100 = 270/100 ps
5076 04:47:26.602371 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5077 04:47:26.605583 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5078 04:47:26.608952 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5079 04:47:26.612213 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5080 04:47:26.615335 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5081 04:47:26.622098 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5082 04:47:26.622522
5083 04:47:26.625399 CA PerBit enable=1, Macro0, CA PI delay=33
5084 04:47:26.625884
5085 04:47:26.628786 [CBTSetCACLKResult] CA Dly = 33
5086 04:47:26.629303 CS Dly: 7 (0~38)
5087 04:47:26.629720 ==
5088 04:47:26.632141 Dram Type= 6, Freq= 0, CH_0, rank 1
5089 04:47:26.635108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 04:47:26.638379 ==
5091 04:47:26.641798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5092 04:47:26.648446 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5093 04:47:26.651726 [CA 0] Center 38 (8~69) winsize 62
5094 04:47:26.654992 [CA 1] Center 38 (8~69) winsize 62
5095 04:47:26.658260 [CA 2] Center 35 (5~66) winsize 62
5096 04:47:26.661980 [CA 3] Center 35 (5~66) winsize 62
5097 04:47:26.665204 [CA 4] Center 34 (4~64) winsize 61
5098 04:47:26.668151 [CA 5] Center 34 (4~64) winsize 61
5099 04:47:26.668567
5100 04:47:26.671790 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5101 04:47:26.672311
5102 04:47:26.675031 [CATrainingPosCal] consider 2 rank data
5103 04:47:26.678158 u2DelayCellTimex100 = 270/100 ps
5104 04:47:26.681625 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5105 04:47:26.685193 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5106 04:47:26.688374 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5107 04:47:26.695094 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5108 04:47:26.698191 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5109 04:47:26.701413 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5110 04:47:26.702062
5111 04:47:26.704793 CA PerBit enable=1, Macro0, CA PI delay=34
5112 04:47:26.705269
5113 04:47:26.707870 [CBTSetCACLKResult] CA Dly = 34
5114 04:47:26.708400 CS Dly: 7 (0~39)
5115 04:47:26.708740
5116 04:47:26.711026 ----->DramcWriteLeveling(PI) begin...
5117 04:47:26.714226 ==
5118 04:47:26.717835 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 04:47:26.720885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5120 04:47:26.721304 ==
5121 04:47:26.724478 Write leveling (Byte 0): 30 => 30
5122 04:47:26.727545 Write leveling (Byte 1): 30 => 30
5123 04:47:26.730776 DramcWriteLeveling(PI) end<-----
5124 04:47:26.731204
5125 04:47:26.731532 ==
5126 04:47:26.734146 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 04:47:26.737632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5128 04:47:26.738068 ==
5129 04:47:26.740749 [Gating] SW mode calibration
5130 04:47:26.747517 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5131 04:47:26.753934 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5132 04:47:26.757295 0 14 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5133 04:47:26.760585 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5134 04:47:26.767462 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 04:47:26.770798 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 04:47:26.773837 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 04:47:26.780501 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 04:47:26.783678 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 04:47:26.787433 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5140 04:47:26.793568 0 15 0 | B1->B0 | 3434 2b2b | 1 0 | (0 1) (0 0)
5141 04:47:26.796921 0 15 4 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
5142 04:47:26.800376 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 04:47:26.807442 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 04:47:26.810411 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 04:47:26.813918 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 04:47:26.820837 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 04:47:26.823367 0 15 28 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
5148 04:47:26.826622 1 0 0 | B1->B0 | 2a2a 4141 | 0 0 | (0 0) (0 0)
5149 04:47:26.833200 1 0 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5150 04:47:26.836534 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 04:47:26.840002 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 04:47:26.843232 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 04:47:26.849972 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 04:47:26.853131 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 04:47:26.856694 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5156 04:47:26.863116 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5157 04:47:26.866874 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5158 04:47:26.869673 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 04:47:26.876559 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 04:47:26.879973 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 04:47:26.883040 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 04:47:26.889580 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 04:47:26.893164 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 04:47:26.896008 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 04:47:26.902889 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 04:47:26.905996 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 04:47:26.909337 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 04:47:26.916440 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 04:47:26.919398 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 04:47:26.925981 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 04:47:26.929159 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5172 04:47:26.932525 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5173 04:47:26.938746 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5174 04:47:26.939165 Total UI for P1: 0, mck2ui 16
5175 04:47:26.942017 best dqsien dly found for B0: ( 1, 2, 30)
5176 04:47:26.948709 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 04:47:26.952253 Total UI for P1: 0, mck2ui 16
5178 04:47:26.955297 best dqsien dly found for B1: ( 1, 3, 4)
5179 04:47:26.958712 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5180 04:47:26.961878 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5181 04:47:26.962341
5182 04:47:26.965068 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5183 04:47:26.968749 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5184 04:47:26.972032 [Gating] SW calibration Done
5185 04:47:26.972557 ==
5186 04:47:26.975443 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 04:47:26.978195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 04:47:26.978620 ==
5189 04:47:26.981931 RX Vref Scan: 0
5190 04:47:26.982363
5191 04:47:26.985306 RX Vref 0 -> 0, step: 1
5192 04:47:26.985858
5193 04:47:26.986195 RX Delay -80 -> 252, step: 8
5194 04:47:26.991647 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5195 04:47:26.995236 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5196 04:47:26.998418 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5197 04:47:27.001788 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5198 04:47:27.005122 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5199 04:47:27.011846 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5200 04:47:27.014718 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5201 04:47:27.017946 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5202 04:47:27.021316 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5203 04:47:27.024820 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5204 04:47:27.028214 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5205 04:47:27.034614 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5206 04:47:27.037914 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5207 04:47:27.040910 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5208 04:47:27.044327 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5209 04:47:27.050875 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5210 04:47:27.051394 ==
5211 04:47:27.054037 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 04:47:27.057759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 04:47:27.058179 ==
5214 04:47:27.058510 DQS Delay:
5215 04:47:27.060786 DQS0 = 0, DQS1 = 0
5216 04:47:27.061200 DQM Delay:
5217 04:47:27.064657 DQM0 = 94, DQM1 = 83
5218 04:47:27.065192 DQ Delay:
5219 04:47:27.067404 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5220 04:47:27.070745 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5221 04:47:27.074153 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5222 04:47:27.077788 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5223 04:47:27.078320
5224 04:47:27.078658
5225 04:47:27.078964 ==
5226 04:47:27.081199 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 04:47:27.084176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 04:47:27.084684 ==
5229 04:47:27.087638
5230 04:47:27.088195
5231 04:47:27.088538 TX Vref Scan disable
5232 04:47:27.090563 == TX Byte 0 ==
5233 04:47:27.093992 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5234 04:47:27.097922 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5235 04:47:27.100934 == TX Byte 1 ==
5236 04:47:27.104466 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5237 04:47:27.107617 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5238 04:47:27.108135 ==
5239 04:47:27.110679 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 04:47:27.117715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 04:47:27.118236 ==
5242 04:47:27.118574
5243 04:47:27.118883
5244 04:47:27.119176 TX Vref Scan disable
5245 04:47:27.121714 == TX Byte 0 ==
5246 04:47:27.124753 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5247 04:47:27.131519 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5248 04:47:27.131944 == TX Byte 1 ==
5249 04:47:27.134949 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5250 04:47:27.141597 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5251 04:47:27.142048
5252 04:47:27.142383 [DATLAT]
5253 04:47:27.142702 Freq=933, CH0 RK0
5254 04:47:27.143009
5255 04:47:27.145060 DATLAT Default: 0xd
5256 04:47:27.145516 0, 0xFFFF, sum = 0
5257 04:47:27.148001 1, 0xFFFF, sum = 0
5258 04:47:27.148421 2, 0xFFFF, sum = 0
5259 04:47:27.151463 3, 0xFFFF, sum = 0
5260 04:47:27.151912 4, 0xFFFF, sum = 0
5261 04:47:27.154693 5, 0xFFFF, sum = 0
5262 04:47:27.158241 6, 0xFFFF, sum = 0
5263 04:47:27.158666 7, 0xFFFF, sum = 0
5264 04:47:27.161439 8, 0xFFFF, sum = 0
5265 04:47:27.161902 9, 0xFFFF, sum = 0
5266 04:47:27.164746 10, 0x0, sum = 1
5267 04:47:27.165270 11, 0x0, sum = 2
5268 04:47:27.165657 12, 0x0, sum = 3
5269 04:47:27.167983 13, 0x0, sum = 4
5270 04:47:27.168421 best_step = 11
5271 04:47:27.168759
5272 04:47:27.171641 ==
5273 04:47:27.172171 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 04:47:27.178064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 04:47:27.178614 ==
5276 04:47:27.178962 RX Vref Scan: 1
5277 04:47:27.179275
5278 04:47:27.181212 RX Vref 0 -> 0, step: 1
5279 04:47:27.181732
5280 04:47:27.184770 RX Delay -69 -> 252, step: 4
5281 04:47:27.185183
5282 04:47:27.188037 Set Vref, RX VrefLevel [Byte0]: 61
5283 04:47:27.191327 [Byte1]: 51
5284 04:47:27.191742
5285 04:47:27.194624 Final RX Vref Byte 0 = 61 to rank0
5286 04:47:27.197699 Final RX Vref Byte 1 = 51 to rank0
5287 04:47:27.201286 Final RX Vref Byte 0 = 61 to rank1
5288 04:47:27.204773 Final RX Vref Byte 1 = 51 to rank1==
5289 04:47:27.207966 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 04:47:27.211459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 04:47:27.214564 ==
5292 04:47:27.214981 DQS Delay:
5293 04:47:27.215313 DQS0 = 0, DQS1 = 0
5294 04:47:27.217862 DQM Delay:
5295 04:47:27.218276 DQM0 = 96, DQM1 = 82
5296 04:47:27.220952 DQ Delay:
5297 04:47:27.221364 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =94
5298 04:47:27.224295 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5299 04:47:27.227783 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
5300 04:47:27.231125 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =90
5301 04:47:27.234201
5302 04:47:27.234628
5303 04:47:27.240924 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5304 04:47:27.244368 CH0 RK0: MR19=505, MR18=1212
5305 04:47:27.251049 CH0_RK0: MR19=0x505, MR18=0x1212, DQSOSC=416, MR23=63, INC=62, DEC=41
5306 04:47:27.251561
5307 04:47:27.254447 ----->DramcWriteLeveling(PI) begin...
5308 04:47:27.255093 ==
5309 04:47:27.257456 Dram Type= 6, Freq= 0, CH_0, rank 1
5310 04:47:27.261329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 04:47:27.261922 ==
5312 04:47:27.264101 Write leveling (Byte 0): 31 => 31
5313 04:47:27.267694 Write leveling (Byte 1): 29 => 29
5314 04:47:27.270643 DramcWriteLeveling(PI) end<-----
5315 04:47:27.271055
5316 04:47:27.271379 ==
5317 04:47:27.274194 Dram Type= 6, Freq= 0, CH_0, rank 1
5318 04:47:27.277458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 04:47:27.278000 ==
5320 04:47:27.280875 [Gating] SW mode calibration
5321 04:47:27.287623 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5322 04:47:27.294088 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5323 04:47:27.297594 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
5324 04:47:27.300635 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 04:47:27.307683 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 04:47:27.311013 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 04:47:27.313756 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 04:47:27.320381 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 04:47:27.324030 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 04:47:27.327400 0 14 28 | B1->B0 | 3232 2828 | 0 0 | (0 0) (0 0)
5331 04:47:27.334057 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5332 04:47:27.337056 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 04:47:27.340179 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 04:47:27.347240 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 04:47:27.350382 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 04:47:27.353594 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 04:47:27.360741 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 04:47:27.364080 0 15 28 | B1->B0 | 2424 3737 | 0 0 | (0 0) (1 1)
5339 04:47:27.367367 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5340 04:47:27.373841 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 04:47:27.377188 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 04:47:27.380435 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 04:47:27.387142 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 04:47:27.390210 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 04:47:27.393442 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 04:47:27.400437 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 04:47:27.403454 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5348 04:47:27.406768 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 04:47:27.413709 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 04:47:27.417197 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 04:47:27.420384 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 04:47:27.426898 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 04:47:27.429793 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 04:47:27.433276 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 04:47:27.439872 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 04:47:27.443401 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 04:47:27.446991 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 04:47:27.450344 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 04:47:27.456912 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 04:47:27.460344 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 04:47:27.463538 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 04:47:27.470188 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5363 04:47:27.473134 Total UI for P1: 0, mck2ui 16
5364 04:47:27.476741 best dqsien dly found for B0: ( 1, 2, 26)
5365 04:47:27.480007 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5366 04:47:27.483049 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 04:47:27.486525 Total UI for P1: 0, mck2ui 16
5368 04:47:27.489422 best dqsien dly found for B1: ( 1, 2, 30)
5369 04:47:27.493143 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5370 04:47:27.496364 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5371 04:47:27.499621
5372 04:47:27.502931 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5373 04:47:27.505906 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5374 04:47:27.509799 [Gating] SW calibration Done
5375 04:47:27.510311 ==
5376 04:47:27.513168 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 04:47:27.516162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 04:47:27.516686 ==
5379 04:47:27.517015 RX Vref Scan: 0
5380 04:47:27.519974
5381 04:47:27.520486 RX Vref 0 -> 0, step: 1
5382 04:47:27.520816
5383 04:47:27.522623 RX Delay -80 -> 252, step: 8
5384 04:47:27.526277 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5385 04:47:27.529832 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5386 04:47:27.536391 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5387 04:47:27.539679 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5388 04:47:27.542750 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5389 04:47:27.545943 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5390 04:47:27.549707 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5391 04:47:27.552721 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5392 04:47:27.559194 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5393 04:47:27.565650 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5394 04:47:27.566422 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5395 04:47:27.568995 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5396 04:47:27.572547 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5397 04:47:27.579046 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5398 04:47:27.582377 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5399 04:47:27.586308 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5400 04:47:27.586830 ==
5401 04:47:27.589167 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 04:47:27.592487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 04:47:27.593003 ==
5404 04:47:27.595701 DQS Delay:
5405 04:47:27.596117 DQS0 = 0, DQS1 = 0
5406 04:47:27.599040 DQM Delay:
5407 04:47:27.599457 DQM0 = 90, DQM1 = 83
5408 04:47:27.599792 DQ Delay:
5409 04:47:27.602101 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5410 04:47:27.605628 DQ4 =91, DQ5 =75, DQ6 =99, DQ7 =103
5411 04:47:27.608830 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =75
5412 04:47:27.612081 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5413 04:47:27.615343
5414 04:47:27.615757
5415 04:47:27.616092 ==
5416 04:47:27.618969 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 04:47:27.622163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 04:47:27.622688 ==
5419 04:47:27.623029
5420 04:47:27.623340
5421 04:47:27.625551 TX Vref Scan disable
5422 04:47:27.626070 == TX Byte 0 ==
5423 04:47:27.632394 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5424 04:47:27.635219 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5425 04:47:27.635654 == TX Byte 1 ==
5426 04:47:27.641636 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5427 04:47:27.645292 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5428 04:47:27.645760 ==
5429 04:47:27.648765 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 04:47:27.651904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 04:47:27.652337 ==
5432 04:47:27.652776
5433 04:47:27.653191
5434 04:47:27.655336 TX Vref Scan disable
5435 04:47:27.658523 == TX Byte 0 ==
5436 04:47:27.662018 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5437 04:47:27.665402 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5438 04:47:27.668743 == TX Byte 1 ==
5439 04:47:27.671734 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5440 04:47:27.675491 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5441 04:47:27.676025
5442 04:47:27.678169 [DATLAT]
5443 04:47:27.678598 Freq=933, CH0 RK1
5444 04:47:27.679042
5445 04:47:27.681644 DATLAT Default: 0xb
5446 04:47:27.682176 0, 0xFFFF, sum = 0
5447 04:47:27.685157 1, 0xFFFF, sum = 0
5448 04:47:27.685737 2, 0xFFFF, sum = 0
5449 04:47:27.688790 3, 0xFFFF, sum = 0
5450 04:47:27.689332 4, 0xFFFF, sum = 0
5451 04:47:27.691760 5, 0xFFFF, sum = 0
5452 04:47:27.692297 6, 0xFFFF, sum = 0
5453 04:47:27.694894 7, 0xFFFF, sum = 0
5454 04:47:27.695330 8, 0xFFFF, sum = 0
5455 04:47:27.698457 9, 0xFFFF, sum = 0
5456 04:47:27.699001 10, 0x0, sum = 1
5457 04:47:27.701301 11, 0x0, sum = 2
5458 04:47:27.701792 12, 0x0, sum = 3
5459 04:47:27.704817 13, 0x0, sum = 4
5460 04:47:27.705372 best_step = 11
5461 04:47:27.705864
5462 04:47:27.706277 ==
5463 04:47:27.708071 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 04:47:27.714959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 04:47:27.715514 ==
5466 04:47:27.715981 RX Vref Scan: 0
5467 04:47:27.716396
5468 04:47:27.718000 RX Vref 0 -> 0, step: 1
5469 04:47:27.718431
5470 04:47:27.721555 RX Delay -77 -> 252, step: 4
5471 04:47:27.724657 iDelay=199, Bit 0, Center 90 (-1 ~ 182) 184
5472 04:47:27.731329 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5473 04:47:27.734748 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5474 04:47:27.737850 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5475 04:47:27.740987 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5476 04:47:27.744602 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5477 04:47:27.748222 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5478 04:47:27.754308 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5479 04:47:27.757685 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5480 04:47:27.761319 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5481 04:47:27.764571 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5482 04:47:27.767458 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5483 04:47:27.774429 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5484 04:47:27.777429 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5485 04:47:27.780858 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5486 04:47:27.784252 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5487 04:47:27.784670 ==
5488 04:47:27.787625 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 04:47:27.791296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 04:47:27.794280 ==
5491 04:47:27.794698 DQS Delay:
5492 04:47:27.795034 DQS0 = 0, DQS1 = 0
5493 04:47:27.797662 DQM Delay:
5494 04:47:27.798173 DQM0 = 92, DQM1 = 84
5495 04:47:27.801214 DQ Delay:
5496 04:47:27.804267 DQ0 =90, DQ1 =94, DQ2 =90, DQ3 =88
5497 04:47:27.807344 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
5498 04:47:27.807759 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
5499 04:47:27.814068 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =90
5500 04:47:27.814485
5501 04:47:27.814819
5502 04:47:27.820814 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5503 04:47:27.823881 CH0 RK1: MR19=505, MR18=2F10
5504 04:47:27.830630 CH0_RK1: MR19=0x505, MR18=0x2F10, DQSOSC=407, MR23=63, INC=65, DEC=43
5505 04:47:27.833925 [RxdqsGatingPostProcess] freq 933
5506 04:47:27.837230 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5507 04:47:27.840406 best DQS0 dly(2T, 0.5T) = (0, 10)
5508 04:47:27.843706 best DQS1 dly(2T, 0.5T) = (0, 11)
5509 04:47:27.847164 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5510 04:47:27.850483 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5511 04:47:27.853864 best DQS0 dly(2T, 0.5T) = (0, 10)
5512 04:47:27.857220 best DQS1 dly(2T, 0.5T) = (0, 10)
5513 04:47:27.860729 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5514 04:47:27.863689 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5515 04:47:27.867153 Pre-setting of DQS Precalculation
5516 04:47:27.870129 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5517 04:47:27.870353 ==
5518 04:47:27.873642 Dram Type= 6, Freq= 0, CH_1, rank 0
5519 04:47:27.879991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 04:47:27.880200 ==
5521 04:47:27.883256 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5522 04:47:27.890101 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5523 04:47:27.893433 [CA 0] Center 37 (7~67) winsize 61
5524 04:47:27.896687 [CA 1] Center 37 (7~68) winsize 62
5525 04:47:27.899980 [CA 2] Center 35 (5~65) winsize 61
5526 04:47:27.903163 [CA 3] Center 34 (4~64) winsize 61
5527 04:47:27.906565 [CA 4] Center 35 (5~65) winsize 61
5528 04:47:27.909739 [CA 5] Center 33 (4~63) winsize 60
5529 04:47:27.909820
5530 04:47:27.913305 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5531 04:47:27.913386
5532 04:47:27.916525 [CATrainingPosCal] consider 1 rank data
5533 04:47:27.919606 u2DelayCellTimex100 = 270/100 ps
5534 04:47:27.923024 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5535 04:47:27.926225 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5536 04:47:27.933132 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5537 04:47:27.936179 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5538 04:47:27.939795 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5539 04:47:27.942819 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5540 04:47:27.942900
5541 04:47:27.946227 CA PerBit enable=1, Macro0, CA PI delay=33
5542 04:47:27.946308
5543 04:47:27.949316 [CBTSetCACLKResult] CA Dly = 33
5544 04:47:27.949397 CS Dly: 6 (0~37)
5545 04:47:27.952926 ==
5546 04:47:27.956065 Dram Type= 6, Freq= 0, CH_1, rank 1
5547 04:47:27.959623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 04:47:27.959704 ==
5549 04:47:27.962749 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5550 04:47:27.969529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5551 04:47:27.973396 [CA 0] Center 37 (7~68) winsize 62
5552 04:47:27.976532 [CA 1] Center 38 (7~69) winsize 63
5553 04:47:27.979774 [CA 2] Center 35 (5~65) winsize 61
5554 04:47:27.983046 [CA 3] Center 34 (4~64) winsize 61
5555 04:47:27.986565 [CA 4] Center 34 (4~65) winsize 62
5556 04:47:27.989719 [CA 5] Center 34 (4~64) winsize 61
5557 04:47:27.989793
5558 04:47:27.993186 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5559 04:47:27.993257
5560 04:47:27.996301 [CATrainingPosCal] consider 2 rank data
5561 04:47:27.999903 u2DelayCellTimex100 = 270/100 ps
5562 04:47:28.003701 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5563 04:47:28.009894 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5564 04:47:28.013353 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5565 04:47:28.016789 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5566 04:47:28.020073 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5567 04:47:28.023073 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5568 04:47:28.023499
5569 04:47:28.026487 CA PerBit enable=1, Macro0, CA PI delay=33
5570 04:47:28.026922
5571 04:47:28.029749 [CBTSetCACLKResult] CA Dly = 33
5572 04:47:28.033173 CS Dly: 7 (0~39)
5573 04:47:28.033649
5574 04:47:28.036428 ----->DramcWriteLeveling(PI) begin...
5575 04:47:28.036849 ==
5576 04:47:28.039701 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 04:47:28.042997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 04:47:28.043412 ==
5579 04:47:28.046458 Write leveling (Byte 0): 28 => 28
5580 04:47:28.049853 Write leveling (Byte 1): 30 => 30
5581 04:47:28.052827 DramcWriteLeveling(PI) end<-----
5582 04:47:28.053238
5583 04:47:28.053613 ==
5584 04:47:28.056328 Dram Type= 6, Freq= 0, CH_1, rank 0
5585 04:47:28.059801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 04:47:28.060269 ==
5587 04:47:28.063037 [Gating] SW mode calibration
5588 04:47:28.069671 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5589 04:47:28.076464 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5590 04:47:28.079587 0 14 0 | B1->B0 | 3433 3232 | 1 0 | (1 1) (0 0)
5591 04:47:28.082847 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 04:47:28.089932 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 04:47:28.092984 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 04:47:28.096250 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 04:47:28.103365 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 04:47:28.106143 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 04:47:28.109559 0 14 28 | B1->B0 | 2f2f 3131 | 0 0 | (1 0) (1 1)
5598 04:47:28.115754 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5599 04:47:28.119297 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 04:47:28.122381 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 04:47:28.129145 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 04:47:28.132408 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 04:47:28.135954 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 04:47:28.142464 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 04:47:28.145768 0 15 28 | B1->B0 | 2e2e 2b2b | 0 0 | (0 0) (0 0)
5606 04:47:28.149173 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 04:47:28.155637 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 04:47:28.158730 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 04:47:28.162663 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 04:47:28.168822 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 04:47:28.172051 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 04:47:28.175466 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 04:47:28.181880 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5614 04:47:28.185097 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 04:47:28.188914 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 04:47:28.195380 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 04:47:28.199060 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 04:47:28.202005 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 04:47:28.208736 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 04:47:28.212080 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 04:47:28.215095 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 04:47:28.218460 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 04:47:28.225076 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 04:47:28.228593 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 04:47:28.231844 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 04:47:28.238561 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 04:47:28.241834 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 04:47:28.244831 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 04:47:28.251572 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5630 04:47:28.254765 Total UI for P1: 0, mck2ui 16
5631 04:47:28.258187 best dqsien dly found for B1: ( 1, 2, 26)
5632 04:47:28.261561 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 04:47:28.265076 Total UI for P1: 0, mck2ui 16
5634 04:47:28.268346 best dqsien dly found for B0: ( 1, 2, 28)
5635 04:47:28.271588 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5636 04:47:28.275246 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5637 04:47:28.275669
5638 04:47:28.278151 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5639 04:47:28.281578 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5640 04:47:28.285094 [Gating] SW calibration Done
5641 04:47:28.285558 ==
5642 04:47:28.288283 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 04:47:28.294892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 04:47:28.295335 ==
5645 04:47:28.295783 RX Vref Scan: 0
5646 04:47:28.296207
5647 04:47:28.298054 RX Vref 0 -> 0, step: 1
5648 04:47:28.298488
5649 04:47:28.301559 RX Delay -80 -> 252, step: 8
5650 04:47:28.304521 iDelay=208, Bit 0, Center 103 (0 ~ 207) 208
5651 04:47:28.308274 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5652 04:47:28.311412 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5653 04:47:28.314672 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5654 04:47:28.321655 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5655 04:47:28.324618 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5656 04:47:28.327904 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5657 04:47:28.331285 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5658 04:47:28.334217 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5659 04:47:28.341063 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5660 04:47:28.344468 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5661 04:47:28.347858 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5662 04:47:28.351082 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5663 04:47:28.354409 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5664 04:47:28.361172 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5665 04:47:28.364120 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5666 04:47:28.364539 ==
5667 04:47:28.367501 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 04:47:28.370832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 04:47:28.371252 ==
5670 04:47:28.371588 DQS Delay:
5671 04:47:28.374049 DQS0 = 0, DQS1 = 0
5672 04:47:28.374467 DQM Delay:
5673 04:47:28.377578 DQM0 = 94, DQM1 = 85
5674 04:47:28.377995 DQ Delay:
5675 04:47:28.380541 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =91
5676 04:47:28.384080 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5677 04:47:28.387371 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5678 04:47:28.390708 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5679 04:47:28.391124
5680 04:47:28.391453
5681 04:47:28.391760 ==
5682 04:47:28.394124 Dram Type= 6, Freq= 0, CH_1, rank 0
5683 04:47:28.400595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5684 04:47:28.401011 ==
5685 04:47:28.401342
5686 04:47:28.401711
5687 04:47:28.402014 TX Vref Scan disable
5688 04:47:28.404035 == TX Byte 0 ==
5689 04:47:28.407304 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5690 04:47:28.413943 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5691 04:47:28.414400 == TX Byte 1 ==
5692 04:47:28.417170 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5693 04:47:28.424073 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5694 04:47:28.424599 ==
5695 04:47:28.427390 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 04:47:28.430520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 04:47:28.430990 ==
5698 04:47:28.431320
5699 04:47:28.431640
5700 04:47:28.433829 TX Vref Scan disable
5701 04:47:28.434399 == TX Byte 0 ==
5702 04:47:28.440516 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5703 04:47:28.443942 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5704 04:47:28.444439 == TX Byte 1 ==
5705 04:47:28.450769 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5706 04:47:28.454129 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5707 04:47:28.454548
5708 04:47:28.454881 [DATLAT]
5709 04:47:28.456941 Freq=933, CH1 RK0
5710 04:47:28.457358
5711 04:47:28.457746 DATLAT Default: 0xd
5712 04:47:28.460388 0, 0xFFFF, sum = 0
5713 04:47:28.460814 1, 0xFFFF, sum = 0
5714 04:47:28.463659 2, 0xFFFF, sum = 0
5715 04:47:28.464085 3, 0xFFFF, sum = 0
5716 04:47:28.467219 4, 0xFFFF, sum = 0
5717 04:47:28.470253 5, 0xFFFF, sum = 0
5718 04:47:28.470676 6, 0xFFFF, sum = 0
5719 04:47:28.473663 7, 0xFFFF, sum = 0
5720 04:47:28.474089 8, 0xFFFF, sum = 0
5721 04:47:28.476863 9, 0xFFFF, sum = 0
5722 04:47:28.477287 10, 0x0, sum = 1
5723 04:47:28.480656 11, 0x0, sum = 2
5724 04:47:28.481076 12, 0x0, sum = 3
5725 04:47:28.481411 13, 0x0, sum = 4
5726 04:47:28.483658 best_step = 11
5727 04:47:28.484080
5728 04:47:28.484423 ==
5729 04:47:28.486959 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 04:47:28.490357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 04:47:28.490775 ==
5732 04:47:28.493644 RX Vref Scan: 1
5733 04:47:28.494058
5734 04:47:28.494386 RX Vref 0 -> 0, step: 1
5735 04:47:28.497010
5736 04:47:28.497554 RX Delay -69 -> 252, step: 4
5737 04:47:28.497925
5738 04:47:28.500099 Set Vref, RX VrefLevel [Byte0]: 55
5739 04:47:28.503610 [Byte1]: 51
5740 04:47:28.508074
5741 04:47:28.508498 Final RX Vref Byte 0 = 55 to rank0
5742 04:47:28.511525 Final RX Vref Byte 1 = 51 to rank0
5743 04:47:28.514678 Final RX Vref Byte 0 = 55 to rank1
5744 04:47:28.518061 Final RX Vref Byte 1 = 51 to rank1==
5745 04:47:28.521605 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 04:47:28.528100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 04:47:28.528518 ==
5748 04:47:28.528924 DQS Delay:
5749 04:47:28.529241 DQS0 = 0, DQS1 = 0
5750 04:47:28.531333 DQM Delay:
5751 04:47:28.531747 DQM0 = 95, DQM1 = 88
5752 04:47:28.534434 DQ Delay:
5753 04:47:28.537970 DQ0 =102, DQ1 =92, DQ2 =82, DQ3 =92
5754 04:47:28.541596 DQ4 =94, DQ5 =104, DQ6 =106, DQ7 =94
5755 04:47:28.544738 DQ8 =76, DQ9 =82, DQ10 =86, DQ11 =84
5756 04:47:28.547736 DQ12 =96, DQ13 =94, DQ14 =96, DQ15 =94
5757 04:47:28.548215
5758 04:47:28.548562
5759 04:47:28.554678 [DQSOSCAuto] RK0, (LSB)MR18= 0x30c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5760 04:47:28.558098 CH1 RK0: MR19=505, MR18=30C
5761 04:47:28.564440 CH1_RK0: MR19=0x505, MR18=0x30C, DQSOSC=418, MR23=63, INC=62, DEC=41
5762 04:47:28.564895
5763 04:47:28.567979 ----->DramcWriteLeveling(PI) begin...
5764 04:47:28.568400 ==
5765 04:47:28.571051 Dram Type= 6, Freq= 0, CH_1, rank 1
5766 04:47:28.574577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 04:47:28.574990 ==
5768 04:47:28.577774 Write leveling (Byte 0): 27 => 27
5769 04:47:28.581159 Write leveling (Byte 1): 29 => 29
5770 04:47:28.584296 DramcWriteLeveling(PI) end<-----
5771 04:47:28.584710
5772 04:47:28.585036 ==
5773 04:47:28.588041 Dram Type= 6, Freq= 0, CH_1, rank 1
5774 04:47:28.591151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5775 04:47:28.591572 ==
5776 04:47:28.593994 [Gating] SW mode calibration
5777 04:47:28.600903 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5778 04:47:28.607595 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5779 04:47:28.610777 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5780 04:47:28.617572 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 04:47:28.620659 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 04:47:28.623915 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 04:47:28.627719 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 04:47:28.634100 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5785 04:47:28.637633 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5786 04:47:28.640848 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (1 0)
5787 04:47:28.647511 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5788 04:47:28.650939 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 04:47:28.654289 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 04:47:28.660733 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 04:47:28.663886 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 04:47:28.667480 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 04:47:28.674131 0 15 24 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
5794 04:47:28.677264 0 15 28 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
5795 04:47:28.680739 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 04:47:28.687243 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 04:47:28.690576 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 04:47:28.693966 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 04:47:28.700348 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 04:47:28.703874 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 04:47:28.706983 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 04:47:28.713929 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5803 04:47:28.717049 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 04:47:28.720403 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 04:47:28.727021 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 04:47:28.730566 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 04:47:28.733401 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 04:47:28.740076 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 04:47:28.743559 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 04:47:28.746505 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 04:47:28.753368 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 04:47:28.756573 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 04:47:28.760096 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 04:47:28.766393 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 04:47:28.769788 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 04:47:28.772931 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 04:47:28.779620 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5818 04:47:28.782877 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 04:47:28.786459 Total UI for P1: 0, mck2ui 16
5820 04:47:28.789533 best dqsien dly found for B0: ( 1, 2, 24)
5821 04:47:28.792882 Total UI for P1: 0, mck2ui 16
5822 04:47:28.796223 best dqsien dly found for B1: ( 1, 2, 26)
5823 04:47:28.799719 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5824 04:47:28.802683 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5825 04:47:28.803104
5826 04:47:28.806072 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5827 04:47:28.809423 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5828 04:47:28.812592 [Gating] SW calibration Done
5829 04:47:28.813047 ==
5830 04:47:28.815944 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 04:47:28.818762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 04:47:28.822377 ==
5833 04:47:28.822458 RX Vref Scan: 0
5834 04:47:28.822522
5835 04:47:28.825464 RX Vref 0 -> 0, step: 1
5836 04:47:28.825582
5837 04:47:28.828712 RX Delay -80 -> 252, step: 8
5838 04:47:28.831845 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5839 04:47:28.835247 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5840 04:47:28.838694 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5841 04:47:28.841679 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5842 04:47:28.848682 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5843 04:47:28.852071 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5844 04:47:28.855184 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5845 04:47:28.858496 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5846 04:47:28.861953 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5847 04:47:28.865448 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5848 04:47:28.871796 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5849 04:47:28.875034 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5850 04:47:28.878652 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5851 04:47:28.881763 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5852 04:47:28.885281 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5853 04:47:28.891638 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5854 04:47:28.891720 ==
5855 04:47:28.894993 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 04:47:28.898200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 04:47:28.898281 ==
5858 04:47:28.898346 DQS Delay:
5859 04:47:28.901581 DQS0 = 0, DQS1 = 0
5860 04:47:28.901662 DQM Delay:
5861 04:47:28.904870 DQM0 = 93, DQM1 = 88
5862 04:47:28.904951 DQ Delay:
5863 04:47:28.908107 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5864 04:47:28.911482 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5865 04:47:28.914853 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5866 04:47:28.918198 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5867 04:47:28.918279
5868 04:47:28.918344
5869 04:47:28.918404 ==
5870 04:47:28.921447 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 04:47:28.924556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 04:47:28.928039 ==
5873 04:47:28.928120
5874 04:47:28.928184
5875 04:47:28.928244 TX Vref Scan disable
5876 04:47:28.931322 == TX Byte 0 ==
5877 04:47:28.934360 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5878 04:47:28.937969 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5879 04:47:28.941213 == TX Byte 1 ==
5880 04:47:28.944516 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5881 04:47:28.947767 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5882 04:47:28.950985 ==
5883 04:47:28.951067 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 04:47:28.957844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 04:47:28.957926 ==
5886 04:47:28.957990
5887 04:47:28.958050
5888 04:47:28.960951 TX Vref Scan disable
5889 04:47:28.961032 == TX Byte 0 ==
5890 04:47:28.967794 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5891 04:47:28.970874 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5892 04:47:28.970956 == TX Byte 1 ==
5893 04:47:28.977649 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5894 04:47:28.980765 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5895 04:47:28.980846
5896 04:47:28.980911 [DATLAT]
5897 04:47:28.984366 Freq=933, CH1 RK1
5898 04:47:28.984447
5899 04:47:28.984533 DATLAT Default: 0xb
5900 04:47:28.987423 0, 0xFFFF, sum = 0
5901 04:47:28.987506 1, 0xFFFF, sum = 0
5902 04:47:28.990929 2, 0xFFFF, sum = 0
5903 04:47:28.991012 3, 0xFFFF, sum = 0
5904 04:47:28.994204 4, 0xFFFF, sum = 0
5905 04:47:28.994286 5, 0xFFFF, sum = 0
5906 04:47:28.997507 6, 0xFFFF, sum = 0
5907 04:47:28.997589 7, 0xFFFF, sum = 0
5908 04:47:29.000802 8, 0xFFFF, sum = 0
5909 04:47:29.000884 9, 0xFFFF, sum = 0
5910 04:47:29.004068 10, 0x0, sum = 1
5911 04:47:29.004151 11, 0x0, sum = 2
5912 04:47:29.007520 12, 0x0, sum = 3
5913 04:47:29.007602 13, 0x0, sum = 4
5914 04:47:29.010966 best_step = 11
5915 04:47:29.011047
5916 04:47:29.011112 ==
5917 04:47:29.014240 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 04:47:29.017528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 04:47:29.017610 ==
5920 04:47:29.020662 RX Vref Scan: 0
5921 04:47:29.020743
5922 04:47:29.020807 RX Vref 0 -> 0, step: 1
5923 04:47:29.020867
5924 04:47:29.024086 RX Delay -69 -> 252, step: 4
5925 04:47:29.031116 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5926 04:47:29.034709 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5927 04:47:29.037855 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5928 04:47:29.041280 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5929 04:47:29.044647 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5930 04:47:29.051141 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5931 04:47:29.054490 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5932 04:47:29.058043 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5933 04:47:29.060984 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5934 04:47:29.064502 iDelay=203, Bit 9, Center 86 (-5 ~ 178) 184
5935 04:47:29.067916 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5936 04:47:29.074420 iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184
5937 04:47:29.077866 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5938 04:47:29.080926 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5939 04:47:29.084439 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5940 04:47:29.087476 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5941 04:47:29.090936 ==
5942 04:47:29.091018 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 04:47:29.097614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 04:47:29.097702 ==
5945 04:47:29.097772 DQS Delay:
5946 04:47:29.100862 DQS0 = 0, DQS1 = 0
5947 04:47:29.100948 DQM Delay:
5948 04:47:29.104171 DQM0 = 91, DQM1 = 90
5949 04:47:29.104252 DQ Delay:
5950 04:47:29.107336 DQ0 =94, DQ1 =86, DQ2 =82, DQ3 =90
5951 04:47:29.110628 DQ4 =90, DQ5 =100, DQ6 =102, DQ7 =90
5952 04:47:29.114305 DQ8 =78, DQ9 =86, DQ10 =90, DQ11 =86
5953 04:47:29.117471 DQ12 =100, DQ13 =96, DQ14 =94, DQ15 =96
5954 04:47:29.117584
5955 04:47:29.117648
5956 04:47:29.124098 [DQSOSCAuto] RK1, (LSB)MR18= 0xb1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
5957 04:47:29.127547 CH1 RK1: MR19=505, MR18=B1F
5958 04:47:29.134164 CH1_RK1: MR19=0x505, MR18=0xB1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5959 04:47:29.137615 [RxdqsGatingPostProcess] freq 933
5960 04:47:29.140908 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5961 04:47:29.144002 best DQS0 dly(2T, 0.5T) = (0, 10)
5962 04:47:29.147283 best DQS1 dly(2T, 0.5T) = (0, 10)
5963 04:47:29.151008 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5964 04:47:29.154308 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5965 04:47:29.157430 best DQS0 dly(2T, 0.5T) = (0, 10)
5966 04:47:29.161039 best DQS1 dly(2T, 0.5T) = (0, 10)
5967 04:47:29.164443 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5968 04:47:29.167500 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5969 04:47:29.171004 Pre-setting of DQS Precalculation
5970 04:47:29.174399 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5971 04:47:29.183959 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5972 04:47:29.190884 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5973 04:47:29.191109
5974 04:47:29.191286
5975 04:47:29.193995 [Calibration Summary] 1866 Mbps
5976 04:47:29.194219 CH 0, Rank 0
5977 04:47:29.197145 SW Impedance : PASS
5978 04:47:29.197421 DUTY Scan : NO K
5979 04:47:29.200592 ZQ Calibration : PASS
5980 04:47:29.203938 Jitter Meter : NO K
5981 04:47:29.204292 CBT Training : PASS
5982 04:47:29.207464 Write leveling : PASS
5983 04:47:29.210909 RX DQS gating : PASS
5984 04:47:29.211325 RX DQ/DQS(RDDQC) : PASS
5985 04:47:29.213924 TX DQ/DQS : PASS
5986 04:47:29.217320 RX DATLAT : PASS
5987 04:47:29.217771 RX DQ/DQS(Engine): PASS
5988 04:47:29.220769 TX OE : NO K
5989 04:47:29.221187 All Pass.
5990 04:47:29.221565
5991 04:47:29.224098 CH 0, Rank 1
5992 04:47:29.224512 SW Impedance : PASS
5993 04:47:29.227289 DUTY Scan : NO K
5994 04:47:29.230814 ZQ Calibration : PASS
5995 04:47:29.231229 Jitter Meter : NO K
5996 04:47:29.233972 CBT Training : PASS
5997 04:47:29.237235 Write leveling : PASS
5998 04:47:29.237685 RX DQS gating : PASS
5999 04:47:29.240370 RX DQ/DQS(RDDQC) : PASS
6000 04:47:29.243758 TX DQ/DQS : PASS
6001 04:47:29.244242 RX DATLAT : PASS
6002 04:47:29.247274 RX DQ/DQS(Engine): PASS
6003 04:47:29.250074 TX OE : NO K
6004 04:47:29.250497 All Pass.
6005 04:47:29.250837
6006 04:47:29.251149 CH 1, Rank 0
6007 04:47:29.253613 SW Impedance : PASS
6008 04:47:29.256752 DUTY Scan : NO K
6009 04:47:29.257178 ZQ Calibration : PASS
6010 04:47:29.260163 Jitter Meter : NO K
6011 04:47:29.260621 CBT Training : PASS
6012 04:47:29.263633 Write leveling : PASS
6013 04:47:29.266668 RX DQS gating : PASS
6014 04:47:29.267080 RX DQ/DQS(RDDQC) : PASS
6015 04:47:29.270241 TX DQ/DQS : PASS
6016 04:47:29.273571 RX DATLAT : PASS
6017 04:47:29.274054 RX DQ/DQS(Engine): PASS
6018 04:47:29.276852 TX OE : NO K
6019 04:47:29.277308 All Pass.
6020 04:47:29.277719
6021 04:47:29.279882 CH 1, Rank 1
6022 04:47:29.280322 SW Impedance : PASS
6023 04:47:29.283485 DUTY Scan : NO K
6024 04:47:29.286784 ZQ Calibration : PASS
6025 04:47:29.287233 Jitter Meter : NO K
6026 04:47:29.289819 CBT Training : PASS
6027 04:47:29.293441 Write leveling : PASS
6028 04:47:29.293956 RX DQS gating : PASS
6029 04:47:29.296517 RX DQ/DQS(RDDQC) : PASS
6030 04:47:29.299864 TX DQ/DQS : PASS
6031 04:47:29.300293 RX DATLAT : PASS
6032 04:47:29.303246 RX DQ/DQS(Engine): PASS
6033 04:47:29.306581 TX OE : NO K
6034 04:47:29.307010 All Pass.
6035 04:47:29.307458
6036 04:47:29.307865 DramC Write-DBI off
6037 04:47:29.309972 PER_BANK_REFRESH: Hybrid Mode
6038 04:47:29.313278 TX_TRACKING: ON
6039 04:47:29.320067 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6040 04:47:29.323584 [FAST_K] Save calibration result to emmc
6041 04:47:29.329993 dramc_set_vcore_voltage set vcore to 650000
6042 04:47:29.330627 Read voltage for 400, 6
6043 04:47:29.333192 Vio18 = 0
6044 04:47:29.333745 Vcore = 650000
6045 04:47:29.334089 Vdram = 0
6046 04:47:29.334404 Vddq = 0
6047 04:47:29.336310 Vmddr = 0
6048 04:47:29.339598 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6049 04:47:29.346257 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6050 04:47:29.349109 MEM_TYPE=3, freq_sel=20
6051 04:47:29.349241 sv_algorithm_assistance_LP4_800
6052 04:47:29.355951 ============ PULL DRAM RESETB DOWN ============
6053 04:47:29.359209 ========== PULL DRAM RESETB DOWN end =========
6054 04:47:29.362675 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6055 04:47:29.365984 ===================================
6056 04:47:29.369150 LPDDR4 DRAM CONFIGURATION
6057 04:47:29.372554 ===================================
6058 04:47:29.375727 EX_ROW_EN[0] = 0x0
6059 04:47:29.375814 EX_ROW_EN[1] = 0x0
6060 04:47:29.379281 LP4Y_EN = 0x0
6061 04:47:29.379363 WORK_FSP = 0x0
6062 04:47:29.382485 WL = 0x2
6063 04:47:29.382566 RL = 0x2
6064 04:47:29.385525 BL = 0x2
6065 04:47:29.385606 RPST = 0x0
6066 04:47:29.388926 RD_PRE = 0x0
6067 04:47:29.389007 WR_PRE = 0x1
6068 04:47:29.392161 WR_PST = 0x0
6069 04:47:29.392268 DBI_WR = 0x0
6070 04:47:29.395960 DBI_RD = 0x0
6071 04:47:29.398877 OTF = 0x1
6072 04:47:29.402391 ===================================
6073 04:47:29.405371 ===================================
6074 04:47:29.405460 ANA top config
6075 04:47:29.408735 ===================================
6076 04:47:29.412250 DLL_ASYNC_EN = 0
6077 04:47:29.412363 ALL_SLAVE_EN = 1
6078 04:47:29.415410 NEW_RANK_MODE = 1
6079 04:47:29.418610 DLL_IDLE_MODE = 1
6080 04:47:29.422129 LP45_APHY_COMB_EN = 1
6081 04:47:29.425448 TX_ODT_DIS = 1
6082 04:47:29.425590 NEW_8X_MODE = 1
6083 04:47:29.428887 ===================================
6084 04:47:29.432044 ===================================
6085 04:47:29.435398 data_rate = 800
6086 04:47:29.438732 CKR = 1
6087 04:47:29.442189 DQ_P2S_RATIO = 4
6088 04:47:29.445487 ===================================
6089 04:47:29.448916 CA_P2S_RATIO = 4
6090 04:47:29.452237 DQ_CA_OPEN = 0
6091 04:47:29.452626 DQ_SEMI_OPEN = 1
6092 04:47:29.455754 CA_SEMI_OPEN = 1
6093 04:47:29.458769 CA_FULL_RATE = 0
6094 04:47:29.462145 DQ_CKDIV4_EN = 0
6095 04:47:29.465509 CA_CKDIV4_EN = 1
6096 04:47:29.468397 CA_PREDIV_EN = 0
6097 04:47:29.468532 PH8_DLY = 0
6098 04:47:29.471565 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6099 04:47:29.474954 DQ_AAMCK_DIV = 0
6100 04:47:29.478480 CA_AAMCK_DIV = 0
6101 04:47:29.481902 CA_ADMCK_DIV = 4
6102 04:47:29.485314 DQ_TRACK_CA_EN = 0
6103 04:47:29.485389 CA_PICK = 800
6104 04:47:29.488408 CA_MCKIO = 400
6105 04:47:29.491954 MCKIO_SEMI = 400
6106 04:47:29.495484 PLL_FREQ = 3016
6107 04:47:29.498751 DQ_UI_PI_RATIO = 32
6108 04:47:29.502058 CA_UI_PI_RATIO = 32
6109 04:47:29.505029 ===================================
6110 04:47:29.508357 ===================================
6111 04:47:29.511834 memory_type:LPDDR4
6112 04:47:29.511934 GP_NUM : 10
6113 04:47:29.515112 SRAM_EN : 1
6114 04:47:29.515187 MD32_EN : 0
6115 04:47:29.518183 ===================================
6116 04:47:29.521568 [ANA_INIT] >>>>>>>>>>>>>>
6117 04:47:29.525148 <<<<<< [CONFIGURE PHASE]: ANA_TX
6118 04:47:29.528447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6119 04:47:29.531640 ===================================
6120 04:47:29.535022 data_rate = 800,PCW = 0X7400
6121 04:47:29.538503 ===================================
6122 04:47:29.541630 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6123 04:47:29.545177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6124 04:47:29.558135 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6125 04:47:29.561245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6126 04:47:29.564643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6127 04:47:29.568177 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6128 04:47:29.571621 [ANA_INIT] flow start
6129 04:47:29.575258 [ANA_INIT] PLL >>>>>>>>
6130 04:47:29.575675 [ANA_INIT] PLL <<<<<<<<
6131 04:47:29.578334 [ANA_INIT] MIDPI >>>>>>>>
6132 04:47:29.581699 [ANA_INIT] MIDPI <<<<<<<<
6133 04:47:29.582209 [ANA_INIT] DLL >>>>>>>>
6134 04:47:29.584820 [ANA_INIT] flow end
6135 04:47:29.588232 ============ LP4 DIFF to SE enter ============
6136 04:47:29.595034 ============ LP4 DIFF to SE exit ============
6137 04:47:29.595540 [ANA_INIT] <<<<<<<<<<<<<
6138 04:47:29.598150 [Flow] Enable top DCM control >>>>>
6139 04:47:29.601814 [Flow] Enable top DCM control <<<<<
6140 04:47:29.604737 Enable DLL master slave shuffle
6141 04:47:29.611580 ==============================================================
6142 04:47:29.612132 Gating Mode config
6143 04:47:29.617909 ==============================================================
6144 04:47:29.621262 Config description:
6145 04:47:29.631050 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6146 04:47:29.637901 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6147 04:47:29.640845 SELPH_MODE 0: By rank 1: By Phase
6148 04:47:29.647680 ==============================================================
6149 04:47:29.650658 GAT_TRACK_EN = 0
6150 04:47:29.654060 RX_GATING_MODE = 2
6151 04:47:29.654558 RX_GATING_TRACK_MODE = 2
6152 04:47:29.657336 SELPH_MODE = 1
6153 04:47:29.660490 PICG_EARLY_EN = 1
6154 04:47:29.663876 VALID_LAT_VALUE = 1
6155 04:47:29.670795 ==============================================================
6156 04:47:29.673957 Enter into Gating configuration >>>>
6157 04:47:29.677444 Exit from Gating configuration <<<<
6158 04:47:29.680413 Enter into DVFS_PRE_config >>>>>
6159 04:47:29.690441 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6160 04:47:29.693871 Exit from DVFS_PRE_config <<<<<
6161 04:47:29.696946 Enter into PICG configuration >>>>
6162 04:47:29.700278 Exit from PICG configuration <<<<
6163 04:47:29.703821 [RX_INPUT] configuration >>>>>
6164 04:47:29.707162 [RX_INPUT] configuration <<<<<
6165 04:47:29.710262 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6166 04:47:29.716964 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6167 04:47:29.723573 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6168 04:47:29.730450 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6169 04:47:29.733757 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6170 04:47:29.740439 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6171 04:47:29.743742 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6172 04:47:29.750289 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6173 04:47:29.753560 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6174 04:47:29.756682 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6175 04:47:29.759910 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6176 04:47:29.766787 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6177 04:47:29.770240 ===================================
6178 04:47:29.773525 LPDDR4 DRAM CONFIGURATION
6179 04:47:29.776683 ===================================
6180 04:47:29.777100 EX_ROW_EN[0] = 0x0
6181 04:47:29.780119 EX_ROW_EN[1] = 0x0
6182 04:47:29.780656 LP4Y_EN = 0x0
6183 04:47:29.783274 WORK_FSP = 0x0
6184 04:47:29.783737 WL = 0x2
6185 04:47:29.786211 RL = 0x2
6186 04:47:29.786710 BL = 0x2
6187 04:47:29.789462 RPST = 0x0
6188 04:47:29.789964 RD_PRE = 0x0
6189 04:47:29.793267 WR_PRE = 0x1
6190 04:47:29.793828 WR_PST = 0x0
6191 04:47:29.796287 DBI_WR = 0x0
6192 04:47:29.799482 DBI_RD = 0x0
6193 04:47:29.800050 OTF = 0x1
6194 04:47:29.802882 ===================================
6195 04:47:29.806280 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6196 04:47:29.809271 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6197 04:47:29.815992 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6198 04:47:29.819263 ===================================
6199 04:47:29.822526 LPDDR4 DRAM CONFIGURATION
6200 04:47:29.826127 ===================================
6201 04:47:29.826620 EX_ROW_EN[0] = 0x10
6202 04:47:29.829146 EX_ROW_EN[1] = 0x0
6203 04:47:29.829615 LP4Y_EN = 0x0
6204 04:47:29.832592 WORK_FSP = 0x0
6205 04:47:29.832957 WL = 0x2
6206 04:47:29.835768 RL = 0x2
6207 04:47:29.836182 BL = 0x2
6208 04:47:29.839232 RPST = 0x0
6209 04:47:29.839646 RD_PRE = 0x0
6210 04:47:29.842672 WR_PRE = 0x1
6211 04:47:29.843127 WR_PST = 0x0
6212 04:47:29.845518 DBI_WR = 0x0
6213 04:47:29.849014 DBI_RD = 0x0
6214 04:47:29.849426 OTF = 0x1
6215 04:47:29.852432 ===================================
6216 04:47:29.859048 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6217 04:47:29.862753 nWR fixed to 30
6218 04:47:29.865900 [ModeRegInit_LP4] CH0 RK0
6219 04:47:29.866344 [ModeRegInit_LP4] CH0 RK1
6220 04:47:29.869290 [ModeRegInit_LP4] CH1 RK0
6221 04:47:29.872368 [ModeRegInit_LP4] CH1 RK1
6222 04:47:29.872779 match AC timing 19
6223 04:47:29.879224 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6224 04:47:29.882138 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6225 04:47:29.885594 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6226 04:47:29.892163 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6227 04:47:29.895470 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6228 04:47:29.895886 ==
6229 04:47:29.898813 Dram Type= 6, Freq= 0, CH_0, rank 0
6230 04:47:29.902210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6231 04:47:29.902687 ==
6232 04:47:29.909087 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6233 04:47:29.915712 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6234 04:47:29.918802 [CA 0] Center 36 (8~64) winsize 57
6235 04:47:29.922226 [CA 1] Center 36 (8~64) winsize 57
6236 04:47:29.925701 [CA 2] Center 36 (8~64) winsize 57
6237 04:47:29.928961 [CA 3] Center 36 (8~64) winsize 57
6238 04:47:29.932156 [CA 4] Center 36 (8~64) winsize 57
6239 04:47:29.932588 [CA 5] Center 36 (8~64) winsize 57
6240 04:47:29.932921
6241 04:47:29.938468 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6242 04:47:29.939013
6243 04:47:29.941946 [CATrainingPosCal] consider 1 rank data
6244 04:47:29.945414 u2DelayCellTimex100 = 270/100 ps
6245 04:47:29.948684 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 04:47:29.951820 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 04:47:29.955188 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 04:47:29.958358 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 04:47:29.961736 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 04:47:29.965100 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 04:47:29.965551
6252 04:47:29.968782 CA PerBit enable=1, Macro0, CA PI delay=36
6253 04:47:29.969548
6254 04:47:29.971765 [CBTSetCACLKResult] CA Dly = 36
6255 04:47:29.975216 CS Dly: 1 (0~32)
6256 04:47:29.975736 ==
6257 04:47:29.978417 Dram Type= 6, Freq= 0, CH_0, rank 1
6258 04:47:29.981793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 04:47:29.982211 ==
6260 04:47:29.988167 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6261 04:47:29.995099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6262 04:47:29.998201 [CA 0] Center 36 (8~64) winsize 57
6263 04:47:30.001469 [CA 1] Center 36 (8~64) winsize 57
6264 04:47:30.001936 [CA 2] Center 36 (8~64) winsize 57
6265 04:47:30.004796 [CA 3] Center 36 (8~64) winsize 57
6266 04:47:30.007959 [CA 4] Center 36 (8~64) winsize 57
6267 04:47:30.011510 [CA 5] Center 36 (8~64) winsize 57
6268 04:47:30.011926
6269 04:47:30.014614 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6270 04:47:30.015039
6271 04:47:30.021584 [CATrainingPosCal] consider 2 rank data
6272 04:47:30.022053 u2DelayCellTimex100 = 270/100 ps
6273 04:47:30.024682 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 04:47:30.031330 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 04:47:30.034514 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 04:47:30.037972 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 04:47:30.041299 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 04:47:30.044294 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 04:47:30.044711
6280 04:47:30.047943 CA PerBit enable=1, Macro0, CA PI delay=36
6281 04:47:30.048365
6282 04:47:30.051010 [CBTSetCACLKResult] CA Dly = 36
6283 04:47:30.054582 CS Dly: 1 (0~32)
6284 04:47:30.054999
6285 04:47:30.057919 ----->DramcWriteLeveling(PI) begin...
6286 04:47:30.058342 ==
6287 04:47:30.061410 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 04:47:30.064300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 04:47:30.064720 ==
6290 04:47:30.068197 Write leveling (Byte 0): 40 => 8
6291 04:47:30.071691 Write leveling (Byte 1): 40 => 8
6292 04:47:30.074392 DramcWriteLeveling(PI) end<-----
6293 04:47:30.074809
6294 04:47:30.075206 ==
6295 04:47:30.077592 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 04:47:30.080899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 04:47:30.081317 ==
6298 04:47:30.084254 [Gating] SW mode calibration
6299 04:47:30.090849 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6300 04:47:30.097697 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6301 04:47:30.100748 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6302 04:47:30.104014 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6303 04:47:30.110698 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6304 04:47:30.113916 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6305 04:47:30.117217 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 04:47:30.124154 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 04:47:30.127234 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 04:47:30.130494 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 04:47:30.137179 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6310 04:47:30.137749 Total UI for P1: 0, mck2ui 16
6311 04:47:30.143552 best dqsien dly found for B0: ( 0, 14, 24)
6312 04:47:30.143975 Total UI for P1: 0, mck2ui 16
6313 04:47:30.150359 best dqsien dly found for B1: ( 0, 14, 24)
6314 04:47:30.153560 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6315 04:47:30.157032 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6316 04:47:30.157449
6317 04:47:30.160373 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6318 04:47:30.163539 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6319 04:47:30.166957 [Gating] SW calibration Done
6320 04:47:30.167455 ==
6321 04:47:30.170647 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 04:47:30.173552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 04:47:30.173974 ==
6324 04:47:30.177038 RX Vref Scan: 0
6325 04:47:30.177448
6326 04:47:30.177853 RX Vref 0 -> 0, step: 1
6327 04:47:30.178163
6328 04:47:30.180234 RX Delay -410 -> 252, step: 16
6329 04:47:30.186971 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6330 04:47:30.190273 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6331 04:47:30.193435 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6332 04:47:30.196752 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6333 04:47:30.203662 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6334 04:47:30.206817 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6335 04:47:30.210256 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6336 04:47:30.213367 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6337 04:47:30.220261 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6338 04:47:30.223253 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6339 04:47:30.226702 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6340 04:47:30.230241 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6341 04:47:30.236986 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6342 04:47:30.240019 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6343 04:47:30.243083 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6344 04:47:30.246551 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6345 04:47:30.249683 ==
6346 04:47:30.253169 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 04:47:30.256492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 04:47:30.256949 ==
6349 04:47:30.257532 DQS Delay:
6350 04:47:30.260012 DQS0 = 59, DQS1 = 59
6351 04:47:30.260556 DQM Delay:
6352 04:47:30.263206 DQM0 = 18, DQM1 = 10
6353 04:47:30.263616 DQ Delay:
6354 04:47:30.266244 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6355 04:47:30.269779 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6356 04:47:30.273288 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6357 04:47:30.276556 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6358 04:47:30.277106
6359 04:47:30.277451
6360 04:47:30.277826 ==
6361 04:47:30.279592 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 04:47:30.283451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 04:47:30.283973 ==
6364 04:47:30.284344
6365 04:47:30.284650
6366 04:47:30.286453 TX Vref Scan disable
6367 04:47:30.286878 == TX Byte 0 ==
6368 04:47:30.293115 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6369 04:47:30.296296 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6370 04:47:30.296710 == TX Byte 1 ==
6371 04:47:30.303342 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6372 04:47:30.306208 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6373 04:47:30.306625 ==
6374 04:47:30.309680 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 04:47:30.312872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 04:47:30.313295 ==
6377 04:47:30.313748
6378 04:47:30.314061
6379 04:47:30.316474 TX Vref Scan disable
6380 04:47:30.317037 == TX Byte 0 ==
6381 04:47:30.323059 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6382 04:47:30.326373 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6383 04:47:30.326812 == TX Byte 1 ==
6384 04:47:30.332715 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6385 04:47:30.335948 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6386 04:47:30.336387
6387 04:47:30.336741 [DATLAT]
6388 04:47:30.339360 Freq=400, CH0 RK0
6389 04:47:30.339857
6390 04:47:30.340189 DATLAT Default: 0xf
6391 04:47:30.343045 0, 0xFFFF, sum = 0
6392 04:47:30.343469 1, 0xFFFF, sum = 0
6393 04:47:30.345912 2, 0xFFFF, sum = 0
6394 04:47:30.346350 3, 0xFFFF, sum = 0
6395 04:47:30.349180 4, 0xFFFF, sum = 0
6396 04:47:30.349657 5, 0xFFFF, sum = 0
6397 04:47:30.352624 6, 0xFFFF, sum = 0
6398 04:47:30.353068 7, 0xFFFF, sum = 0
6399 04:47:30.356147 8, 0xFFFF, sum = 0
6400 04:47:30.359574 9, 0xFFFF, sum = 0
6401 04:47:30.360040 10, 0xFFFF, sum = 0
6402 04:47:30.362482 11, 0xFFFF, sum = 0
6403 04:47:30.363013 12, 0xFFFF, sum = 0
6404 04:47:30.366000 13, 0x0, sum = 1
6405 04:47:30.366443 14, 0x0, sum = 2
6406 04:47:30.369247 15, 0x0, sum = 3
6407 04:47:30.369698 16, 0x0, sum = 4
6408 04:47:30.370077 best_step = 14
6409 04:47:30.372890
6410 04:47:30.373296 ==
6411 04:47:30.375711 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 04:47:30.379218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 04:47:30.379690 ==
6414 04:47:30.380023 RX Vref Scan: 1
6415 04:47:30.380333
6416 04:47:30.382571 RX Vref 0 -> 0, step: 1
6417 04:47:30.382983
6418 04:47:30.385813 RX Delay -359 -> 252, step: 8
6419 04:47:30.386224
6420 04:47:30.389320 Set Vref, RX VrefLevel [Byte0]: 61
6421 04:47:30.392711 [Byte1]: 51
6422 04:47:30.396181
6423 04:47:30.396597 Final RX Vref Byte 0 = 61 to rank0
6424 04:47:30.399678 Final RX Vref Byte 1 = 51 to rank0
6425 04:47:30.403432 Final RX Vref Byte 0 = 61 to rank1
6426 04:47:30.406276 Final RX Vref Byte 1 = 51 to rank1==
6427 04:47:30.409805 Dram Type= 6, Freq= 0, CH_0, rank 0
6428 04:47:30.416375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 04:47:30.416794 ==
6430 04:47:30.417126 DQS Delay:
6431 04:47:30.419808 DQS0 = 60, DQS1 = 68
6432 04:47:30.420226 DQM Delay:
6433 04:47:30.420559 DQM0 = 15, DQM1 = 13
6434 04:47:30.422965 DQ Delay:
6435 04:47:30.426533 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6436 04:47:30.429821 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6437 04:47:30.430263 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6438 04:47:30.432782 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6439 04:47:30.436185
6440 04:47:30.436729
6441 04:47:30.442975 [DQSOSCAuto] RK0, (LSB)MR18= 0x7e7d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6442 04:47:30.446189 CH0 RK0: MR19=C0C, MR18=7E7D
6443 04:47:30.452646 CH0_RK0: MR19=0xC0C, MR18=0x7E7D, DQSOSC=393, MR23=63, INC=382, DEC=254
6444 04:47:30.453070 ==
6445 04:47:30.455999 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 04:47:30.459205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 04:47:30.459706 ==
6448 04:47:30.462779 [Gating] SW mode calibration
6449 04:47:30.469215 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6450 04:47:30.475791 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6451 04:47:30.479202 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6452 04:47:30.482404 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6453 04:47:30.488827 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6454 04:47:30.492216 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6455 04:47:30.495862 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 04:47:30.502080 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 04:47:30.505555 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 04:47:30.508571 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 04:47:30.515431 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6460 04:47:30.515921 Total UI for P1: 0, mck2ui 16
6461 04:47:30.521831 best dqsien dly found for B0: ( 0, 14, 24)
6462 04:47:30.522250 Total UI for P1: 0, mck2ui 16
6463 04:47:30.528413 best dqsien dly found for B1: ( 0, 14, 24)
6464 04:47:30.532301 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6465 04:47:30.535413 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6466 04:47:30.535905
6467 04:47:30.538574 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6468 04:47:30.542064 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6469 04:47:30.544979 [Gating] SW calibration Done
6470 04:47:30.545413 ==
6471 04:47:30.548458 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 04:47:30.551582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 04:47:30.551968 ==
6474 04:47:30.555169 RX Vref Scan: 0
6475 04:47:30.555703
6476 04:47:30.556045 RX Vref 0 -> 0, step: 1
6477 04:47:30.556406
6478 04:47:30.558483 RX Delay -410 -> 252, step: 16
6479 04:47:30.565030 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6480 04:47:30.568096 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6481 04:47:30.571934 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6482 04:47:30.575223 iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528
6483 04:47:30.581809 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6484 04:47:30.585213 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6485 04:47:30.588165 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6486 04:47:30.591515 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6487 04:47:30.598146 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6488 04:47:30.601397 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6489 04:47:30.604813 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6490 04:47:30.608379 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6491 04:47:30.614560 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6492 04:47:30.618102 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6493 04:47:30.620957 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6494 04:47:30.627964 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6495 04:47:30.628484 ==
6496 04:47:30.630985 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 04:47:30.634849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 04:47:30.635375 ==
6499 04:47:30.635718 DQS Delay:
6500 04:47:30.637994 DQS0 = 59, DQS1 = 59
6501 04:47:30.638412 DQM Delay:
6502 04:47:30.640978 DQM0 = 15, DQM1 = 10
6503 04:47:30.641397 DQ Delay:
6504 04:47:30.644089 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6505 04:47:30.647527 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6506 04:47:30.650919 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6507 04:47:30.654050 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6508 04:47:30.654465
6509 04:47:30.654794
6510 04:47:30.655103 ==
6511 04:47:30.657420 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 04:47:30.660645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 04:47:30.661063 ==
6514 04:47:30.661392
6515 04:47:30.664100
6516 04:47:30.664541 TX Vref Scan disable
6517 04:47:30.667347 == TX Byte 0 ==
6518 04:47:30.670609 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6519 04:47:30.674049 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6520 04:47:30.677199 == TX Byte 1 ==
6521 04:47:30.680693 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6522 04:47:30.683749 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6523 04:47:30.684168 ==
6524 04:47:30.687148 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 04:47:30.690618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 04:47:30.693762 ==
6527 04:47:30.694305
6528 04:47:30.694651
6529 04:47:30.694960 TX Vref Scan disable
6530 04:47:30.697078 == TX Byte 0 ==
6531 04:47:30.700160 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6532 04:47:30.703751 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6533 04:47:30.706850 == TX Byte 1 ==
6534 04:47:30.710047 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6535 04:47:30.713591 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6536 04:47:30.714075
6537 04:47:30.716787 [DATLAT]
6538 04:47:30.717235 Freq=400, CH0 RK1
6539 04:47:30.717634
6540 04:47:30.720052 DATLAT Default: 0xe
6541 04:47:30.720464 0, 0xFFFF, sum = 0
6542 04:47:30.723290 1, 0xFFFF, sum = 0
6543 04:47:30.723816 2, 0xFFFF, sum = 0
6544 04:47:30.726666 3, 0xFFFF, sum = 0
6545 04:47:30.727088 4, 0xFFFF, sum = 0
6546 04:47:30.729923 5, 0xFFFF, sum = 0
6547 04:47:30.730392 6, 0xFFFF, sum = 0
6548 04:47:30.733186 7, 0xFFFF, sum = 0
6549 04:47:30.733702 8, 0xFFFF, sum = 0
6550 04:47:30.736542 9, 0xFFFF, sum = 0
6551 04:47:30.736964 10, 0xFFFF, sum = 0
6552 04:47:30.739692 11, 0xFFFF, sum = 0
6553 04:47:30.742924 12, 0xFFFF, sum = 0
6554 04:47:30.743349 13, 0x0, sum = 1
6555 04:47:30.743687 14, 0x0, sum = 2
6556 04:47:30.746296 15, 0x0, sum = 3
6557 04:47:30.746751 16, 0x0, sum = 4
6558 04:47:30.749550 best_step = 14
6559 04:47:30.749973
6560 04:47:30.750308 ==
6561 04:47:30.753018 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 04:47:30.756145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 04:47:30.756627 ==
6564 04:47:30.759473 RX Vref Scan: 0
6565 04:47:30.759886
6566 04:47:30.760218 RX Vref 0 -> 0, step: 1
6567 04:47:30.760528
6568 04:47:30.762825 RX Delay -359 -> 252, step: 8
6569 04:47:30.771062 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6570 04:47:30.774328 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6571 04:47:30.777743 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6572 04:47:30.780835 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6573 04:47:30.788049 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6574 04:47:30.791499 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6575 04:47:30.794504 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6576 04:47:30.797729 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6577 04:47:30.804487 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6578 04:47:30.807894 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6579 04:47:30.811205 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6580 04:47:30.814464 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6581 04:47:30.821039 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6582 04:47:30.824415 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6583 04:47:30.827599 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6584 04:47:30.834043 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6585 04:47:30.834486 ==
6586 04:47:30.837172 Dram Type= 6, Freq= 0, CH_0, rank 1
6587 04:47:30.840649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 04:47:30.841068 ==
6589 04:47:30.841403 DQS Delay:
6590 04:47:30.843970 DQS0 = 60, DQS1 = 72
6591 04:47:30.844431 DQM Delay:
6592 04:47:30.847529 DQM0 = 11, DQM1 = 17
6593 04:47:30.847987 DQ Delay:
6594 04:47:30.850805 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6595 04:47:30.853945 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6596 04:47:30.857253 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6597 04:47:30.860680 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6598 04:47:30.861103
6599 04:47:30.861438
6600 04:47:30.867016 [DQSOSCAuto] RK1, (LSB)MR18= 0xc67d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6601 04:47:30.870689 CH0 RK1: MR19=C0C, MR18=C67D
6602 04:47:30.877032 CH0_RK1: MR19=0xC0C, MR18=0xC67D, DQSOSC=385, MR23=63, INC=398, DEC=265
6603 04:47:30.880308 [RxdqsGatingPostProcess] freq 400
6604 04:47:30.886903 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6605 04:47:30.890124 best DQS0 dly(2T, 0.5T) = (0, 10)
6606 04:47:30.890544 best DQS1 dly(2T, 0.5T) = (0, 10)
6607 04:47:30.893714 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6608 04:47:30.897247 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6609 04:47:30.900343 best DQS0 dly(2T, 0.5T) = (0, 10)
6610 04:47:30.903672 best DQS1 dly(2T, 0.5T) = (0, 10)
6611 04:47:30.906816 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6612 04:47:30.910094 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6613 04:47:30.913576 Pre-setting of DQS Precalculation
6614 04:47:30.920212 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6615 04:47:30.920631 ==
6616 04:47:30.923458 Dram Type= 6, Freq= 0, CH_1, rank 0
6617 04:47:30.926845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 04:47:30.927262 ==
6619 04:47:30.933182 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6620 04:47:30.936496 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6621 04:47:30.939815 [CA 0] Center 36 (8~64) winsize 57
6622 04:47:30.943111 [CA 1] Center 36 (8~64) winsize 57
6623 04:47:30.946793 [CA 2] Center 36 (8~64) winsize 57
6624 04:47:30.949843 [CA 3] Center 36 (8~64) winsize 57
6625 04:47:30.953049 [CA 4] Center 36 (8~64) winsize 57
6626 04:47:30.956520 [CA 5] Center 36 (8~64) winsize 57
6627 04:47:30.957102
6628 04:47:30.959712 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6629 04:47:30.960087
6630 04:47:30.963560 [CATrainingPosCal] consider 1 rank data
6631 04:47:30.966496 u2DelayCellTimex100 = 270/100 ps
6632 04:47:30.969925 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 04:47:30.973295 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 04:47:30.979646 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 04:47:30.982940 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 04:47:30.986099 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 04:47:30.989435 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 04:47:30.989899
6639 04:47:30.992809 CA PerBit enable=1, Macro0, CA PI delay=36
6640 04:47:30.993228
6641 04:47:30.996052 [CBTSetCACLKResult] CA Dly = 36
6642 04:47:30.996471 CS Dly: 1 (0~32)
6643 04:47:30.999485 ==
6644 04:47:31.003044 Dram Type= 6, Freq= 0, CH_1, rank 1
6645 04:47:31.006218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 04:47:31.006637 ==
6647 04:47:31.009302 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6648 04:47:31.016260 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6649 04:47:31.019370 [CA 0] Center 36 (8~64) winsize 57
6650 04:47:31.022530 [CA 1] Center 36 (8~64) winsize 57
6651 04:47:31.025996 [CA 2] Center 36 (8~64) winsize 57
6652 04:47:31.029614 [CA 3] Center 36 (8~64) winsize 57
6653 04:47:31.033156 [CA 4] Center 36 (8~64) winsize 57
6654 04:47:31.036605 [CA 5] Center 36 (8~64) winsize 57
6655 04:47:31.037197
6656 04:47:31.039441 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6657 04:47:31.039960
6658 04:47:31.042829 [CATrainingPosCal] consider 2 rank data
6659 04:47:31.045852 u2DelayCellTimex100 = 270/100 ps
6660 04:47:31.049122 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 04:47:31.052559 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 04:47:31.055781 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 04:47:31.059136 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 04:47:31.065810 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 04:47:31.068951 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 04:47:31.069558
6667 04:47:31.072461 CA PerBit enable=1, Macro0, CA PI delay=36
6668 04:47:31.072877
6669 04:47:31.076162 [CBTSetCACLKResult] CA Dly = 36
6670 04:47:31.076687 CS Dly: 1 (0~32)
6671 04:47:31.077025
6672 04:47:31.078913 ----->DramcWriteLeveling(PI) begin...
6673 04:47:31.079424 ==
6674 04:47:31.082234 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 04:47:31.089410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 04:47:31.089995 ==
6677 04:47:31.092522 Write leveling (Byte 0): 40 => 8
6678 04:47:31.092947 Write leveling (Byte 1): 40 => 8
6679 04:47:31.096124 DramcWriteLeveling(PI) end<-----
6680 04:47:31.096654
6681 04:47:31.096993 ==
6682 04:47:31.099049 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 04:47:31.105917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 04:47:31.106442 ==
6685 04:47:31.109379 [Gating] SW mode calibration
6686 04:47:31.115575 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6687 04:47:31.118989 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6688 04:47:31.125785 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6689 04:47:31.128845 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6690 04:47:31.132036 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6691 04:47:31.139079 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6692 04:47:31.142465 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 04:47:31.145650 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 04:47:31.149035 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 04:47:31.156134 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 04:47:31.159085 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6697 04:47:31.162244 Total UI for P1: 0, mck2ui 16
6698 04:47:31.165588 best dqsien dly found for B0: ( 0, 14, 24)
6699 04:47:31.169237 Total UI for P1: 0, mck2ui 16
6700 04:47:31.171926 best dqsien dly found for B1: ( 0, 14, 24)
6701 04:47:31.175216 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6702 04:47:31.178499 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6703 04:47:31.178944
6704 04:47:31.181884 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6705 04:47:31.188843 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6706 04:47:31.189264 [Gating] SW calibration Done
6707 04:47:31.189643 ==
6708 04:47:31.191914 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 04:47:31.198768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 04:47:31.199290 ==
6711 04:47:31.199627 RX Vref Scan: 0
6712 04:47:31.199941
6713 04:47:31.202232 RX Vref 0 -> 0, step: 1
6714 04:47:31.202735
6715 04:47:31.205110 RX Delay -410 -> 252, step: 16
6716 04:47:31.208333 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6717 04:47:31.211633 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6718 04:47:31.218447 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6719 04:47:31.221983 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6720 04:47:31.224960 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6721 04:47:31.228181 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6722 04:47:31.235140 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6723 04:47:31.238011 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6724 04:47:31.241607 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6725 04:47:31.244714 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6726 04:47:31.251199 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6727 04:47:31.254725 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6728 04:47:31.258021 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6729 04:47:31.264466 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6730 04:47:31.268067 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6731 04:47:31.271187 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6732 04:47:31.271604 ==
6733 04:47:31.274579 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 04:47:31.277754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 04:47:31.281092 ==
6736 04:47:31.281697 DQS Delay:
6737 04:47:31.282082 DQS0 = 51, DQS1 = 67
6738 04:47:31.284259 DQM Delay:
6739 04:47:31.284687 DQM0 = 12, DQM1 = 20
6740 04:47:31.287869 DQ Delay:
6741 04:47:31.288459 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6742 04:47:31.290915 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6743 04:47:31.294140 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6744 04:47:31.297528 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =32
6745 04:47:31.298134
6746 04:47:31.298485
6747 04:47:31.300711 ==
6748 04:47:31.304347 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 04:47:31.307267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 04:47:31.307688 ==
6751 04:47:31.308021
6752 04:47:31.308325
6753 04:47:31.310564 TX Vref Scan disable
6754 04:47:31.310978 == TX Byte 0 ==
6755 04:47:31.313938 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 04:47:31.320789 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 04:47:31.321309 == TX Byte 1 ==
6758 04:47:31.324255 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6759 04:47:31.330566 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6760 04:47:31.330985 ==
6761 04:47:31.333893 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 04:47:31.337196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 04:47:31.337684 ==
6764 04:47:31.338125
6765 04:47:31.338541
6766 04:47:31.340379 TX Vref Scan disable
6767 04:47:31.340816 == TX Byte 0 ==
6768 04:47:31.343451 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 04:47:31.350208 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 04:47:31.350645 == TX Byte 1 ==
6771 04:47:31.353764 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 04:47:31.360045 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 04:47:31.360561
6774 04:47:31.360899 [DATLAT]
6775 04:47:31.361210 Freq=400, CH1 RK0
6776 04:47:31.363595
6777 04:47:31.364007 DATLAT Default: 0xf
6778 04:47:31.366502 0, 0xFFFF, sum = 0
6779 04:47:31.366927 1, 0xFFFF, sum = 0
6780 04:47:31.369821 2, 0xFFFF, sum = 0
6781 04:47:31.370261 3, 0xFFFF, sum = 0
6782 04:47:31.373433 4, 0xFFFF, sum = 0
6783 04:47:31.373888 5, 0xFFFF, sum = 0
6784 04:47:31.376871 6, 0xFFFF, sum = 0
6785 04:47:31.377289 7, 0xFFFF, sum = 0
6786 04:47:31.380252 8, 0xFFFF, sum = 0
6787 04:47:31.380779 9, 0xFFFF, sum = 0
6788 04:47:31.383604 10, 0xFFFF, sum = 0
6789 04:47:31.384132 11, 0xFFFF, sum = 0
6790 04:47:31.386950 12, 0xFFFF, sum = 0
6791 04:47:31.387477 13, 0x0, sum = 1
6792 04:47:31.390071 14, 0x0, sum = 2
6793 04:47:31.390507 15, 0x0, sum = 3
6794 04:47:31.393047 16, 0x0, sum = 4
6795 04:47:31.393471 best_step = 14
6796 04:47:31.393951
6797 04:47:31.394279 ==
6798 04:47:31.396103 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 04:47:31.402806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 04:47:31.402902 ==
6801 04:47:31.402968 RX Vref Scan: 1
6802 04:47:31.403028
6803 04:47:31.406010 RX Vref 0 -> 0, step: 1
6804 04:47:31.406090
6805 04:47:31.409655 RX Delay -375 -> 252, step: 8
6806 04:47:31.409736
6807 04:47:31.412722 Set Vref, RX VrefLevel [Byte0]: 55
6808 04:47:31.415978 [Byte1]: 51
6809 04:47:31.419573
6810 04:47:31.419654 Final RX Vref Byte 0 = 55 to rank0
6811 04:47:31.422526 Final RX Vref Byte 1 = 51 to rank0
6812 04:47:31.425866 Final RX Vref Byte 0 = 55 to rank1
6813 04:47:31.429296 Final RX Vref Byte 1 = 51 to rank1==
6814 04:47:31.432418 Dram Type= 6, Freq= 0, CH_1, rank 0
6815 04:47:31.439503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 04:47:31.439685 ==
6817 04:47:31.439776 DQS Delay:
6818 04:47:31.442441 DQS0 = 56, DQS1 = 64
6819 04:47:31.442588 DQM Delay:
6820 04:47:31.442685 DQM0 = 12, DQM1 = 11
6821 04:47:31.445705 DQ Delay:
6822 04:47:31.449331 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6823 04:47:31.449860 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6824 04:47:31.453036 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6825 04:47:31.456029 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6826 04:47:31.456451
6827 04:47:31.459383
6828 04:47:31.465860 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b6e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6829 04:47:31.469153 CH1 RK0: MR19=C0C, MR18=5B6E
6830 04:47:31.475589 CH1_RK0: MR19=0xC0C, MR18=0x5B6E, DQSOSC=395, MR23=63, INC=378, DEC=252
6831 04:47:31.476014 ==
6832 04:47:31.479068 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 04:47:31.482549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 04:47:31.482973 ==
6835 04:47:31.485919 [Gating] SW mode calibration
6836 04:47:31.492442 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6837 04:47:31.498849 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6838 04:47:31.502019 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6839 04:47:31.505418 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6840 04:47:31.512011 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6841 04:47:31.515376 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6842 04:47:31.518926 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 04:47:31.525435 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 04:47:31.528412 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 04:47:31.531986 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 04:47:31.538609 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6847 04:47:31.539227 Total UI for P1: 0, mck2ui 16
6848 04:47:31.545012 best dqsien dly found for B0: ( 0, 14, 24)
6849 04:47:31.545691 Total UI for P1: 0, mck2ui 16
6850 04:47:31.548560 best dqsien dly found for B1: ( 0, 14, 24)
6851 04:47:31.555164 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6852 04:47:31.558358 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6853 04:47:31.558795
6854 04:47:31.561566 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6855 04:47:31.565263 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6856 04:47:31.568407 [Gating] SW calibration Done
6857 04:47:31.568936 ==
6858 04:47:31.571716 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 04:47:31.574888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 04:47:31.575305 ==
6861 04:47:31.578110 RX Vref Scan: 0
6862 04:47:31.578526
6863 04:47:31.578855 RX Vref 0 -> 0, step: 1
6864 04:47:31.579165
6865 04:47:31.581401 RX Delay -410 -> 252, step: 16
6866 04:47:31.587832 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6867 04:47:31.591407 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6868 04:47:31.594916 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6869 04:47:31.598028 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6870 04:47:31.604397 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6871 04:47:31.607729 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6872 04:47:31.611202 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6873 04:47:31.614344 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6874 04:47:31.620717 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6875 04:47:31.624186 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6876 04:47:31.627656 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6877 04:47:31.634157 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6878 04:47:31.637627 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6879 04:47:31.640941 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6880 04:47:31.643901 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6881 04:47:31.650328 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6882 04:47:31.650801 ==
6883 04:47:31.654115 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 04:47:31.657252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 04:47:31.657810 ==
6886 04:47:31.658158 DQS Delay:
6887 04:47:31.660363 DQS0 = 59, DQS1 = 59
6888 04:47:31.660800 DQM Delay:
6889 04:47:31.663809 DQM0 = 19, DQM1 = 13
6890 04:47:31.664307 DQ Delay:
6891 04:47:31.667453 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6892 04:47:31.670463 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6893 04:47:31.673780 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6894 04:47:31.676952 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6895 04:47:31.677559
6896 04:47:31.678128
6897 04:47:31.678673 ==
6898 04:47:31.680341 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 04:47:31.683589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 04:47:31.684008 ==
6901 04:47:31.686956
6902 04:47:31.687384
6903 04:47:31.687771 TX Vref Scan disable
6904 04:47:31.690143 == TX Byte 0 ==
6905 04:47:31.693365 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6906 04:47:31.696738 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6907 04:47:31.699901 == TX Byte 1 ==
6908 04:47:31.703436 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6909 04:47:31.706785 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6910 04:47:31.707206 ==
6911 04:47:31.709976 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 04:47:31.713209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 04:47:31.716822 ==
6914 04:47:31.717246
6915 04:47:31.717626
6916 04:47:31.717948 TX Vref Scan disable
6917 04:47:31.719832 == TX Byte 0 ==
6918 04:47:31.723215 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6919 04:47:31.726720 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6920 04:47:31.729780 == TX Byte 1 ==
6921 04:47:31.733061 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6922 04:47:31.736424 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6923 04:47:31.736970
6924 04:47:31.739722 [DATLAT]
6925 04:47:31.740278 Freq=400, CH1 RK1
6926 04:47:31.740843
6927 04:47:31.742953 DATLAT Default: 0xe
6928 04:47:31.743509 0, 0xFFFF, sum = 0
6929 04:47:31.746304 1, 0xFFFF, sum = 0
6930 04:47:31.746958 2, 0xFFFF, sum = 0
6931 04:47:31.749980 3, 0xFFFF, sum = 0
6932 04:47:31.750458 4, 0xFFFF, sum = 0
6933 04:47:31.753018 5, 0xFFFF, sum = 0
6934 04:47:31.753495 6, 0xFFFF, sum = 0
6935 04:47:31.756087 7, 0xFFFF, sum = 0
6936 04:47:31.756510 8, 0xFFFF, sum = 0
6937 04:47:31.759875 9, 0xFFFF, sum = 0
6938 04:47:31.760300 10, 0xFFFF, sum = 0
6939 04:47:31.762633 11, 0xFFFF, sum = 0
6940 04:47:31.765934 12, 0xFFFF, sum = 0
6941 04:47:31.766420 13, 0x0, sum = 1
6942 04:47:31.766763 14, 0x0, sum = 2
6943 04:47:31.769529 15, 0x0, sum = 3
6944 04:47:31.769960 16, 0x0, sum = 4
6945 04:47:31.772734 best_step = 14
6946 04:47:31.773453
6947 04:47:31.773855 ==
6948 04:47:31.775965 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 04:47:31.779388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 04:47:31.779827 ==
6951 04:47:31.782535 RX Vref Scan: 0
6952 04:47:31.782955
6953 04:47:31.783305 RX Vref 0 -> 0, step: 1
6954 04:47:31.783619
6955 04:47:31.785879 RX Delay -359 -> 252, step: 8
6956 04:47:31.794450 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6957 04:47:31.797813 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6958 04:47:31.801095 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6959 04:47:31.804379 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6960 04:47:31.810805 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6961 04:47:31.814208 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6962 04:47:31.817569 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6963 04:47:31.820488 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6964 04:47:31.827594 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6965 04:47:31.830861 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6966 04:47:31.834265 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6967 04:47:31.840063 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6968 04:47:31.843636 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6969 04:47:31.846817 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6970 04:47:31.850252 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6971 04:47:31.856840 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6972 04:47:31.856922 ==
6973 04:47:31.860131 Dram Type= 6, Freq= 0, CH_1, rank 1
6974 04:47:31.863448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6975 04:47:31.863532 ==
6976 04:47:31.863598 DQS Delay:
6977 04:47:31.866636 DQS0 = 60, DQS1 = 64
6978 04:47:31.866717 DQM Delay:
6979 04:47:31.870094 DQM0 = 12, DQM1 = 10
6980 04:47:31.870175 DQ Delay:
6981 04:47:31.873377 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6982 04:47:31.876438 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6983 04:47:31.879868 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6984 04:47:31.883475 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6985 04:47:31.883560
6986 04:47:31.883647
6987 04:47:31.889888 [DQSOSCAuto] RK1, (LSB)MR18= 0x7cac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6988 04:47:31.893188 CH1 RK1: MR19=C0C, MR18=7CAC
6989 04:47:31.899815 CH1_RK1: MR19=0xC0C, MR18=0x7CAC, DQSOSC=388, MR23=63, INC=392, DEC=261
6990 04:47:31.903134 [RxdqsGatingPostProcess] freq 400
6991 04:47:31.909481 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6992 04:47:31.913082 best DQS0 dly(2T, 0.5T) = (0, 10)
6993 04:47:31.916434 best DQS1 dly(2T, 0.5T) = (0, 10)
6994 04:47:31.916516 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6995 04:47:31.919816 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6996 04:47:31.922943 best DQS0 dly(2T, 0.5T) = (0, 10)
6997 04:47:31.926407 best DQS1 dly(2T, 0.5T) = (0, 10)
6998 04:47:31.929664 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6999 04:47:31.933025 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7000 04:47:31.936435 Pre-setting of DQS Precalculation
7001 04:47:31.942984 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7002 04:47:31.949664 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7003 04:47:31.956506 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7004 04:47:31.956601
7005 04:47:31.956676
7006 04:47:31.959479 [Calibration Summary] 800 Mbps
7007 04:47:31.959573 CH 0, Rank 0
7008 04:47:31.962796 SW Impedance : PASS
7009 04:47:31.966238 DUTY Scan : NO K
7010 04:47:31.966349 ZQ Calibration : PASS
7011 04:47:31.969690 Jitter Meter : NO K
7012 04:47:31.973088 CBT Training : PASS
7013 04:47:31.973199 Write leveling : PASS
7014 04:47:31.976010 RX DQS gating : PASS
7015 04:47:31.979702 RX DQ/DQS(RDDQC) : PASS
7016 04:47:31.979841 TX DQ/DQS : PASS
7017 04:47:31.982545 RX DATLAT : PASS
7018 04:47:31.982680 RX DQ/DQS(Engine): PASS
7019 04:47:31.986181 TX OE : NO K
7020 04:47:31.986333 All Pass.
7021 04:47:31.986455
7022 04:47:31.989355 CH 0, Rank 1
7023 04:47:31.989486 SW Impedance : PASS
7024 04:47:31.992716 DUTY Scan : NO K
7025 04:47:31.995763 ZQ Calibration : PASS
7026 04:47:31.995844 Jitter Meter : NO K
7027 04:47:31.999117 CBT Training : PASS
7028 04:47:32.002435 Write leveling : NO K
7029 04:47:32.002516 RX DQS gating : PASS
7030 04:47:32.005976 RX DQ/DQS(RDDQC) : PASS
7031 04:47:32.009257 TX DQ/DQS : PASS
7032 04:47:32.009344 RX DATLAT : PASS
7033 04:47:32.012499 RX DQ/DQS(Engine): PASS
7034 04:47:32.015814 TX OE : NO K
7035 04:47:32.015915 All Pass.
7036 04:47:32.015996
7037 04:47:32.016071 CH 1, Rank 0
7038 04:47:32.018895 SW Impedance : PASS
7039 04:47:32.022313 DUTY Scan : NO K
7040 04:47:32.022424 ZQ Calibration : PASS
7041 04:47:32.025706 Jitter Meter : NO K
7042 04:47:32.028837 CBT Training : PASS
7043 04:47:32.028919 Write leveling : PASS
7044 04:47:32.032156 RX DQS gating : PASS
7045 04:47:32.035521 RX DQ/DQS(RDDQC) : PASS
7046 04:47:32.035609 TX DQ/DQS : PASS
7047 04:47:32.039258 RX DATLAT : PASS
7048 04:47:32.042311 RX DQ/DQS(Engine): PASS
7049 04:47:32.042406 TX OE : NO K
7050 04:47:32.042481 All Pass.
7051 04:47:32.045721
7052 04:47:32.045822 CH 1, Rank 1
7053 04:47:32.048844 SW Impedance : PASS
7054 04:47:32.048947 DUTY Scan : NO K
7055 04:47:32.052239 ZQ Calibration : PASS
7056 04:47:32.052350 Jitter Meter : NO K
7057 04:47:32.055194 CBT Training : PASS
7058 04:47:32.058835 Write leveling : NO K
7059 04:47:32.058916 RX DQS gating : PASS
7060 04:47:32.062207 RX DQ/DQS(RDDQC) : PASS
7061 04:47:32.065510 TX DQ/DQS : PASS
7062 04:47:32.065687 RX DATLAT : PASS
7063 04:47:32.068703 RX DQ/DQS(Engine): PASS
7064 04:47:32.071949 TX OE : NO K
7065 04:47:32.072132 All Pass.
7066 04:47:32.072220
7067 04:47:32.075306 DramC Write-DBI off
7068 04:47:32.075419 PER_BANK_REFRESH: Hybrid Mode
7069 04:47:32.078642 TX_TRACKING: ON
7070 04:47:32.086040 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7071 04:47:32.092245 [FAST_K] Save calibration result to emmc
7072 04:47:32.095682 dramc_set_vcore_voltage set vcore to 725000
7073 04:47:32.096175 Read voltage for 1600, 0
7074 04:47:32.098968 Vio18 = 0
7075 04:47:32.099386 Vcore = 725000
7076 04:47:32.099719 Vdram = 0
7077 04:47:32.102383 Vddq = 0
7078 04:47:32.102801 Vmddr = 0
7079 04:47:32.105562 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7080 04:47:32.112298 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7081 04:47:32.115752 MEM_TYPE=3, freq_sel=13
7082 04:47:32.119136 sv_algorithm_assistance_LP4_3733
7083 04:47:32.122295 ============ PULL DRAM RESETB DOWN ============
7084 04:47:32.125712 ========== PULL DRAM RESETB DOWN end =========
7085 04:47:32.132004 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7086 04:47:32.135638 ===================================
7087 04:47:32.136056 LPDDR4 DRAM CONFIGURATION
7088 04:47:32.139046 ===================================
7089 04:47:32.142372 EX_ROW_EN[0] = 0x0
7090 04:47:32.142891 EX_ROW_EN[1] = 0x0
7091 04:47:32.145583 LP4Y_EN = 0x0
7092 04:47:32.145996 WORK_FSP = 0x1
7093 04:47:32.148658 WL = 0x5
7094 04:47:32.152193 RL = 0x5
7095 04:47:32.152716 BL = 0x2
7096 04:47:32.155455 RPST = 0x0
7097 04:47:32.155869 RD_PRE = 0x0
7098 04:47:32.158507 WR_PRE = 0x1
7099 04:47:32.158921 WR_PST = 0x1
7100 04:47:32.161897 DBI_WR = 0x0
7101 04:47:32.162343 DBI_RD = 0x0
7102 04:47:32.165413 OTF = 0x1
7103 04:47:32.168614 ===================================
7104 04:47:32.172129 ===================================
7105 04:47:32.172645 ANA top config
7106 04:47:32.175471 ===================================
7107 04:47:32.178886 DLL_ASYNC_EN = 0
7108 04:47:32.182044 ALL_SLAVE_EN = 0
7109 04:47:32.182564 NEW_RANK_MODE = 1
7110 04:47:32.185119 DLL_IDLE_MODE = 1
7111 04:47:32.188113 LP45_APHY_COMB_EN = 1
7112 04:47:32.191601 TX_ODT_DIS = 0
7113 04:47:32.195165 NEW_8X_MODE = 1
7114 04:47:32.198332 ===================================
7115 04:47:32.201738 ===================================
7116 04:47:32.202314 data_rate = 3200
7117 04:47:32.204928 CKR = 1
7118 04:47:32.207962 DQ_P2S_RATIO = 8
7119 04:47:32.211159 ===================================
7120 04:47:32.214518 CA_P2S_RATIO = 8
7121 04:47:32.217889 DQ_CA_OPEN = 0
7122 04:47:32.221235 DQ_SEMI_OPEN = 0
7123 04:47:32.221318 CA_SEMI_OPEN = 0
7124 04:47:32.224456 CA_FULL_RATE = 0
7125 04:47:32.227709 DQ_CKDIV4_EN = 0
7126 04:47:32.231257 CA_CKDIV4_EN = 0
7127 04:47:32.234172 CA_PREDIV_EN = 0
7128 04:47:32.237472 PH8_DLY = 12
7129 04:47:32.237595 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7130 04:47:32.241005 DQ_AAMCK_DIV = 4
7131 04:47:32.244489 CA_AAMCK_DIV = 4
7132 04:47:32.247471 CA_ADMCK_DIV = 4
7133 04:47:32.250941 DQ_TRACK_CA_EN = 0
7134 04:47:32.254329 CA_PICK = 1600
7135 04:47:32.257345 CA_MCKIO = 1600
7136 04:47:32.257490 MCKIO_SEMI = 0
7137 04:47:32.260718 PLL_FREQ = 3068
7138 04:47:32.263908 DQ_UI_PI_RATIO = 32
7139 04:47:32.267220 CA_UI_PI_RATIO = 0
7140 04:47:32.270581 ===================================
7141 04:47:32.273801 ===================================
7142 04:47:32.277228 memory_type:LPDDR4
7143 04:47:32.277310 GP_NUM : 10
7144 04:47:32.280615 SRAM_EN : 1
7145 04:47:32.283750 MD32_EN : 0
7146 04:47:32.286957 ===================================
7147 04:47:32.287044 [ANA_INIT] >>>>>>>>>>>>>>
7148 04:47:32.290247 <<<<<< [CONFIGURE PHASE]: ANA_TX
7149 04:47:32.293925 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7150 04:47:32.296926 ===================================
7151 04:47:32.300248 data_rate = 3200,PCW = 0X7600
7152 04:47:32.303423 ===================================
7153 04:47:32.306873 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7154 04:47:32.313560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7155 04:47:32.316611 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7156 04:47:32.323238 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7157 04:47:32.326418 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7158 04:47:32.329836 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7159 04:47:32.333144 [ANA_INIT] flow start
7160 04:47:32.333218 [ANA_INIT] PLL >>>>>>>>
7161 04:47:32.336641 [ANA_INIT] PLL <<<<<<<<
7162 04:47:32.340005 [ANA_INIT] MIDPI >>>>>>>>
7163 04:47:32.340087 [ANA_INIT] MIDPI <<<<<<<<
7164 04:47:32.343375 [ANA_INIT] DLL >>>>>>>>
7165 04:47:32.346407 [ANA_INIT] DLL <<<<<<<<
7166 04:47:32.346490 [ANA_INIT] flow end
7167 04:47:32.353266 ============ LP4 DIFF to SE enter ============
7168 04:47:32.356475 ============ LP4 DIFF to SE exit ============
7169 04:47:32.359645 [ANA_INIT] <<<<<<<<<<<<<
7170 04:47:32.363059 [Flow] Enable top DCM control >>>>>
7171 04:47:32.366161 [Flow] Enable top DCM control <<<<<
7172 04:47:32.366243 Enable DLL master slave shuffle
7173 04:47:32.372765 ==============================================================
7174 04:47:32.376422 Gating Mode config
7175 04:47:32.379609 ==============================================================
7176 04:47:32.382771 Config description:
7177 04:47:32.392809 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7178 04:47:32.399214 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7179 04:47:32.402845 SELPH_MODE 0: By rank 1: By Phase
7180 04:47:32.409207 ==============================================================
7181 04:47:32.412595 GAT_TRACK_EN = 1
7182 04:47:32.415924 RX_GATING_MODE = 2
7183 04:47:32.419239 RX_GATING_TRACK_MODE = 2
7184 04:47:32.422721 SELPH_MODE = 1
7185 04:47:32.422803 PICG_EARLY_EN = 1
7186 04:47:32.425776 VALID_LAT_VALUE = 1
7187 04:47:32.432257 ==============================================================
7188 04:47:32.435623 Enter into Gating configuration >>>>
7189 04:47:32.439095 Exit from Gating configuration <<<<
7190 04:47:32.442407 Enter into DVFS_PRE_config >>>>>
7191 04:47:32.451907 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7192 04:47:32.455358 Exit from DVFS_PRE_config <<<<<
7193 04:47:32.458663 Enter into PICG configuration >>>>
7194 04:47:32.461852 Exit from PICG configuration <<<<
7195 04:47:32.465289 [RX_INPUT] configuration >>>>>
7196 04:47:32.468738 [RX_INPUT] configuration <<<<<
7197 04:47:32.472145 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7198 04:47:32.478644 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7199 04:47:32.485487 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7200 04:47:32.491712 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7201 04:47:32.498709 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7202 04:47:32.505085 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7203 04:47:32.508500 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7204 04:47:32.512130 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7205 04:47:32.515134 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7206 04:47:32.521600 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7207 04:47:32.525138 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7208 04:47:32.528305 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7209 04:47:32.531623 ===================================
7210 04:47:32.535079 LPDDR4 DRAM CONFIGURATION
7211 04:47:32.538339 ===================================
7212 04:47:32.538420 EX_ROW_EN[0] = 0x0
7213 04:47:32.541535 EX_ROW_EN[1] = 0x0
7214 04:47:32.541616 LP4Y_EN = 0x0
7215 04:47:32.545060 WORK_FSP = 0x1
7216 04:47:32.545158 WL = 0x5
7217 04:47:32.548417 RL = 0x5
7218 04:47:32.551647 BL = 0x2
7219 04:47:32.551729 RPST = 0x0
7220 04:47:32.554959 RD_PRE = 0x0
7221 04:47:32.555040 WR_PRE = 0x1
7222 04:47:32.558077 WR_PST = 0x1
7223 04:47:32.558158 DBI_WR = 0x0
7224 04:47:32.561489 DBI_RD = 0x0
7225 04:47:32.561570 OTF = 0x1
7226 04:47:32.564744 ===================================
7227 04:47:32.568212 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7228 04:47:32.574531 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7229 04:47:32.577985 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7230 04:47:32.581258 ===================================
7231 04:47:32.584771 LPDDR4 DRAM CONFIGURATION
7232 04:47:32.588092 ===================================
7233 04:47:32.588219 EX_ROW_EN[0] = 0x10
7234 04:47:32.591416 EX_ROW_EN[1] = 0x0
7235 04:47:32.591519 LP4Y_EN = 0x0
7236 04:47:32.594531 WORK_FSP = 0x1
7237 04:47:32.594617 WL = 0x5
7238 04:47:32.597684 RL = 0x5
7239 04:47:32.601175 BL = 0x2
7240 04:47:32.601259 RPST = 0x0
7241 04:47:32.604614 RD_PRE = 0x0
7242 04:47:32.604691 WR_PRE = 0x1
7243 04:47:32.607662 WR_PST = 0x1
7244 04:47:32.607764 DBI_WR = 0x0
7245 04:47:32.610937 DBI_RD = 0x0
7246 04:47:32.611021 OTF = 0x1
7247 04:47:32.614490 ===================================
7248 04:47:32.620970 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7249 04:47:32.621058 ==
7250 04:47:32.624392 Dram Type= 6, Freq= 0, CH_0, rank 0
7251 04:47:32.627661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7252 04:47:32.627768 ==
7253 04:47:32.630814 [Duty_Offset_Calibration]
7254 04:47:32.634291 B0:2 B1:0 CA:3
7255 04:47:32.634368
7256 04:47:32.637443 [DutyScan_Calibration_Flow] k_type=0
7257 04:47:32.646014
7258 04:47:32.646100 ==CLK 0==
7259 04:47:32.649325 Final CLK duty delay cell = 0
7260 04:47:32.652622 [0] MAX Duty = 5031%(X100), DQS PI = 12
7261 04:47:32.655818 [0] MIN Duty = 4875%(X100), DQS PI = 54
7262 04:47:32.659209 [0] AVG Duty = 4953%(X100)
7263 04:47:32.659283
7264 04:47:32.662548 CH0 CLK Duty spec in!! Max-Min= 156%
7265 04:47:32.665969 [DutyScan_Calibration_Flow] ====Done====
7266 04:47:32.666046
7267 04:47:32.669142 [DutyScan_Calibration_Flow] k_type=1
7268 04:47:32.685982
7269 04:47:32.686090 ==DQS 0 ==
7270 04:47:32.689369 Final DQS duty delay cell = 0
7271 04:47:32.692387 [0] MAX Duty = 5094%(X100), DQS PI = 14
7272 04:47:32.695779 [0] MIN Duty = 4907%(X100), DQS PI = 0
7273 04:47:32.699069 [0] AVG Duty = 5000%(X100)
7274 04:47:32.699171
7275 04:47:32.699279 ==DQS 1 ==
7276 04:47:32.702572 Final DQS duty delay cell = 0
7277 04:47:32.705831 [0] MAX Duty = 5156%(X100), DQS PI = 32
7278 04:47:32.709380 [0] MIN Duty = 5031%(X100), DQS PI = 14
7279 04:47:32.712370 [0] AVG Duty = 5093%(X100)
7280 04:47:32.712468
7281 04:47:32.715687 CH0 DQS 0 Duty spec in!! Max-Min= 187%
7282 04:47:32.715803
7283 04:47:32.719107 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7284 04:47:32.722455 [DutyScan_Calibration_Flow] ====Done====
7285 04:47:32.722551
7286 04:47:32.725560 [DutyScan_Calibration_Flow] k_type=3
7287 04:47:32.743982
7288 04:47:32.744102 ==DQM 0 ==
7289 04:47:32.747423 Final DQM duty delay cell = 0
7290 04:47:32.750666 [0] MAX Duty = 5156%(X100), DQS PI = 30
7291 04:47:32.753950 [0] MIN Duty = 4844%(X100), DQS PI = 52
7292 04:47:32.757301 [0] AVG Duty = 5000%(X100)
7293 04:47:32.757410
7294 04:47:32.757533 ==DQM 1 ==
7295 04:47:32.760537 Final DQM duty delay cell = 4
7296 04:47:32.763886 [4] MAX Duty = 5187%(X100), DQS PI = 60
7297 04:47:32.767164 [4] MIN Duty = 5031%(X100), DQS PI = 14
7298 04:47:32.770547 [4] AVG Duty = 5109%(X100)
7299 04:47:32.770626
7300 04:47:32.773957 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7301 04:47:32.774031
7302 04:47:32.777059 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7303 04:47:32.780312 [DutyScan_Calibration_Flow] ====Done====
7304 04:47:32.780413
7305 04:47:32.783443 [DutyScan_Calibration_Flow] k_type=2
7306 04:47:32.800503
7307 04:47:32.800624 ==DQ 0 ==
7308 04:47:32.805355 Final DQ duty delay cell = -4
7309 04:47:32.806947 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7310 04:47:32.810342 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7311 04:47:32.813674 [-4] AVG Duty = 4938%(X100)
7312 04:47:32.813747
7313 04:47:32.813825 ==DQ 1 ==
7314 04:47:32.816882 Final DQ duty delay cell = 0
7315 04:47:32.820316 [0] MAX Duty = 5156%(X100), DQS PI = 58
7316 04:47:32.823340 [0] MIN Duty = 5000%(X100), DQS PI = 16
7317 04:47:32.826740 [0] AVG Duty = 5078%(X100)
7318 04:47:32.826815
7319 04:47:32.830098 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7320 04:47:32.830198
7321 04:47:32.833516 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7322 04:47:32.836863 [DutyScan_Calibration_Flow] ====Done====
7323 04:47:32.836945 ==
7324 04:47:32.839888 Dram Type= 6, Freq= 0, CH_1, rank 0
7325 04:47:32.843314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7326 04:47:32.843408 ==
7327 04:47:32.846785 [Duty_Offset_Calibration]
7328 04:47:32.846888 B0:1 B1:-2 CA:0
7329 04:47:32.846975
7330 04:47:32.850076 [DutyScan_Calibration_Flow] k_type=0
7331 04:47:32.861002
7332 04:47:32.861083 ==CLK 0==
7333 04:47:32.864466 Final CLK duty delay cell = 0
7334 04:47:32.867676 [0] MAX Duty = 5062%(X100), DQS PI = 22
7335 04:47:32.870763 [0] MIN Duty = 4844%(X100), DQS PI = 0
7336 04:47:32.874190 [0] AVG Duty = 4953%(X100)
7337 04:47:32.874303
7338 04:47:32.877663 CH1 CLK Duty spec in!! Max-Min= 218%
7339 04:47:32.880800 [DutyScan_Calibration_Flow] ====Done====
7340 04:47:32.880882
7341 04:47:32.883966 [DutyScan_Calibration_Flow] k_type=1
7342 04:47:32.900002
7343 04:47:32.900083 ==DQS 0 ==
7344 04:47:32.903441 Final DQS duty delay cell = -4
7345 04:47:32.906367 [-4] MAX Duty = 4969%(X100), DQS PI = 26
7346 04:47:32.909811 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7347 04:47:32.912970 [-4] AVG Duty = 4906%(X100)
7348 04:47:32.913051
7349 04:47:32.913115 ==DQS 1 ==
7350 04:47:32.916233 Final DQS duty delay cell = 0
7351 04:47:32.919635 [0] MAX Duty = 5124%(X100), DQS PI = 62
7352 04:47:32.922979 [0] MIN Duty = 4844%(X100), DQS PI = 24
7353 04:47:32.926251 [0] AVG Duty = 4984%(X100)
7354 04:47:32.926332
7355 04:47:32.929688 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7356 04:47:32.929769
7357 04:47:32.932748 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7358 04:47:32.936294 [DutyScan_Calibration_Flow] ====Done====
7359 04:47:32.936375
7360 04:47:32.939479 [DutyScan_Calibration_Flow] k_type=3
7361 04:47:32.957363
7362 04:47:32.957448 ==DQM 0 ==
7363 04:47:32.960739 Final DQM duty delay cell = 0
7364 04:47:32.963634 [0] MAX Duty = 5031%(X100), DQS PI = 26
7365 04:47:32.967194 [0] MIN Duty = 4813%(X100), DQS PI = 54
7366 04:47:32.970306 [0] AVG Duty = 4922%(X100)
7367 04:47:32.970428
7368 04:47:32.970526 ==DQM 1 ==
7369 04:47:32.973840 Final DQM duty delay cell = 0
7370 04:47:32.976994 [0] MAX Duty = 5062%(X100), DQS PI = 34
7371 04:47:32.980307 [0] MIN Duty = 4875%(X100), DQS PI = 24
7372 04:47:32.983803 [0] AVG Duty = 4968%(X100)
7373 04:47:32.983885
7374 04:47:32.987106 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7375 04:47:32.987191
7376 04:47:32.990457 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7377 04:47:32.993753 [DutyScan_Calibration_Flow] ====Done====
7378 04:47:32.993838
7379 04:47:32.997051 [DutyScan_Calibration_Flow] k_type=2
7380 04:47:33.014244
7381 04:47:33.014326 ==DQ 0 ==
7382 04:47:33.017638 Final DQ duty delay cell = 0
7383 04:47:33.021031 [0] MAX Duty = 5093%(X100), DQS PI = 22
7384 04:47:33.024034 [0] MIN Duty = 4907%(X100), DQS PI = 60
7385 04:47:33.024117 [0] AVG Duty = 5000%(X100)
7386 04:47:33.027413
7387 04:47:33.027495 ==DQ 1 ==
7388 04:47:33.030964 Final DQ duty delay cell = 0
7389 04:47:33.034015 [0] MAX Duty = 5125%(X100), DQS PI = 34
7390 04:47:33.037325 [0] MIN Duty = 4938%(X100), DQS PI = 24
7391 04:47:33.037441 [0] AVG Duty = 5031%(X100)
7392 04:47:33.037561
7393 04:47:33.043993 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7394 04:47:33.044099
7395 04:47:33.047401 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7396 04:47:33.050422 [DutyScan_Calibration_Flow] ====Done====
7397 04:47:33.053924 nWR fixed to 30
7398 04:47:33.054006 [ModeRegInit_LP4] CH0 RK0
7399 04:47:33.057420 [ModeRegInit_LP4] CH0 RK1
7400 04:47:33.060302 [ModeRegInit_LP4] CH1 RK0
7401 04:47:33.063578 [ModeRegInit_LP4] CH1 RK1
7402 04:47:33.063659 match AC timing 5
7403 04:47:33.070382 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7404 04:47:33.073592 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7405 04:47:33.077129 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7406 04:47:33.083407 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7407 04:47:33.086778 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7408 04:47:33.086860 [MiockJmeterHQA]
7409 04:47:33.086925
7410 04:47:33.090376 [DramcMiockJmeter] u1RxGatingPI = 0
7411 04:47:33.093887 0 : 4255, 4026
7412 04:47:33.093970 4 : 4252, 4027
7413 04:47:33.096681 8 : 4363, 4138
7414 04:47:33.096763 12 : 4257, 4026
7415 04:47:33.096829 16 : 4368, 4140
7416 04:47:33.100014 20 : 4252, 4026
7417 04:47:33.100129 24 : 4252, 4027
7418 04:47:33.103540 28 : 4252, 4027
7419 04:47:33.103649 32 : 4255, 4029
7420 04:47:33.106684 36 : 4249, 4027
7421 04:47:33.106796 40 : 4363, 4137
7422 04:47:33.110143 44 : 4360, 4138
7423 04:47:33.110253 48 : 4254, 4029
7424 04:47:33.110346 52 : 4252, 4027
7425 04:47:33.113446 56 : 4253, 4027
7426 04:47:33.113579 60 : 4250, 4026
7427 04:47:33.116896 64 : 4252, 4030
7428 04:47:33.117005 68 : 4360, 4137
7429 04:47:33.119812 72 : 4250, 4027
7430 04:47:33.119921 76 : 4249, 4027
7431 04:47:33.123192 80 : 4250, 4027
7432 04:47:33.123293 84 : 4252, 4030
7433 04:47:33.123392 88 : 4249, 4027
7434 04:47:33.126480 92 : 4363, 4140
7435 04:47:33.126589 96 : 4360, 4138
7436 04:47:33.130039 100 : 4250, 4026
7437 04:47:33.130145 104 : 4361, 3768
7438 04:47:33.133238 108 : 4250, 0
7439 04:47:33.133348 112 : 4250, 0
7440 04:47:33.133438 116 : 4250, 0
7441 04:47:33.136240 120 : 4250, 0
7442 04:47:33.136340 124 : 4250, 0
7443 04:47:33.139825 128 : 4250, 0
7444 04:47:33.139930 132 : 4253, 0
7445 04:47:33.140037 136 : 4360, 0
7446 04:47:33.143234 140 : 4361, 0
7447 04:47:33.143350 144 : 4363, 0
7448 04:47:33.146162 148 : 4250, 0
7449 04:47:33.146272 152 : 4250, 0
7450 04:47:33.146377 156 : 4250, 0
7451 04:47:33.149805 160 : 4250, 0
7452 04:47:33.149914 164 : 4250, 0
7453 04:47:33.152829 168 : 4250, 0
7454 04:47:33.152943 172 : 4253, 0
7455 04:47:33.153034 176 : 4250, 0
7456 04:47:33.156251 180 : 4250, 0
7457 04:47:33.156374 184 : 4253, 0
7458 04:47:33.156470 188 : 4360, 0
7459 04:47:33.159611 192 : 4361, 0
7460 04:47:33.159728 196 : 4363, 0
7461 04:47:33.163149 200 : 4250, 0
7462 04:47:33.163259 204 : 4250, 0
7463 04:47:33.163354 208 : 4250, 0
7464 04:47:33.166117 212 : 4250, 0
7465 04:47:33.166201 216 : 4250, 0
7466 04:47:33.169575 220 : 4250, 0
7467 04:47:33.169658 224 : 4252, 0
7468 04:47:33.169725 228 : 4250, 0
7469 04:47:33.172767 232 : 4250, 2
7470 04:47:33.172850 236 : 4253, 1126
7471 04:47:33.176303 240 : 4249, 4027
7472 04:47:33.176385 244 : 4253, 4026
7473 04:47:33.179659 248 : 4250, 4027
7474 04:47:33.179741 252 : 4252, 4030
7475 04:47:33.183023 256 : 4249, 4027
7476 04:47:33.183106 260 : 4250, 4026
7477 04:47:33.186177 264 : 4361, 4137
7478 04:47:33.186260 268 : 4250, 4027
7479 04:47:33.186326 272 : 4249, 4027
7480 04:47:33.189659 276 : 4360, 4137
7481 04:47:33.189742 280 : 4250, 4026
7482 04:47:33.192697 284 : 4250, 4027
7483 04:47:33.192779 288 : 4363, 4140
7484 04:47:33.196116 292 : 4250, 4027
7485 04:47:33.196199 296 : 4250, 4026
7486 04:47:33.199559 300 : 4250, 4027
7487 04:47:33.199641 304 : 4252, 4030
7488 04:47:33.202642 308 : 4250, 4027
7489 04:47:33.202724 312 : 4250, 4026
7490 04:47:33.206300 316 : 4361, 4137
7491 04:47:33.206383 320 : 4250, 4027
7492 04:47:33.209394 324 : 4249, 4027
7493 04:47:33.209485 328 : 4360, 4137
7494 04:47:33.209552 332 : 4250, 4027
7495 04:47:33.212560 336 : 4250, 4027
7496 04:47:33.212643 340 : 4363, 4140
7497 04:47:33.216091 344 : 4249, 4027
7498 04:47:33.216173 348 : 4250, 4026
7499 04:47:33.219365 352 : 4250, 3948
7500 04:47:33.219448 356 : 4252, 2764
7501 04:47:33.222488 360 : 4249, 0
7502 04:47:33.222570
7503 04:47:33.222635 MIOCK jitter meter ch=0
7504 04:47:33.222695
7505 04:47:33.225884 1T = (360-108) = 252 dly cells
7506 04:47:33.232610 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7507 04:47:33.232693 ==
7508 04:47:33.235983 Dram Type= 6, Freq= 0, CH_0, rank 0
7509 04:47:33.239450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7510 04:47:33.239533 ==
7511 04:47:33.245963 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7512 04:47:33.249235 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7513 04:47:33.252640 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7514 04:47:33.259127 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7515 04:47:33.269207 [CA 0] Center 43 (13~74) winsize 62
7516 04:47:33.272183 [CA 1] Center 43 (13~74) winsize 62
7517 04:47:33.275872 [CA 2] Center 39 (10~68) winsize 59
7518 04:47:33.278792 [CA 3] Center 38 (9~68) winsize 60
7519 04:47:33.282235 [CA 4] Center 36 (7~66) winsize 60
7520 04:47:33.285500 [CA 5] Center 36 (7~66) winsize 60
7521 04:47:33.285587
7522 04:47:33.288855 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7523 04:47:33.288936
7524 04:47:33.292471 [CATrainingPosCal] consider 1 rank data
7525 04:47:33.295480 u2DelayCellTimex100 = 258/100 ps
7526 04:47:33.302003 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7527 04:47:33.305494 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7528 04:47:33.308763 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7529 04:47:33.312131 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7530 04:47:33.315430 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7531 04:47:33.318768 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7532 04:47:33.318849
7533 04:47:33.321781 CA PerBit enable=1, Macro0, CA PI delay=36
7534 04:47:33.321862
7535 04:47:33.325111 [CBTSetCACLKResult] CA Dly = 36
7536 04:47:33.328432 CS Dly: 11 (0~42)
7537 04:47:33.331885 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7538 04:47:33.335175 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7539 04:47:33.335257 ==
7540 04:47:33.338437 Dram Type= 6, Freq= 0, CH_0, rank 1
7541 04:47:33.345186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7542 04:47:33.345268 ==
7543 04:47:33.348521 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7544 04:47:33.354968 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7545 04:47:33.358265 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7546 04:47:33.364969 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7547 04:47:33.372766 [CA 0] Center 43 (13~74) winsize 62
7548 04:47:33.376312 [CA 1] Center 43 (13~74) winsize 62
7549 04:47:33.379533 [CA 2] Center 38 (9~68) winsize 60
7550 04:47:33.382855 [CA 3] Center 39 (10~68) winsize 59
7551 04:47:33.386083 [CA 4] Center 36 (6~66) winsize 61
7552 04:47:33.389385 [CA 5] Center 36 (6~66) winsize 61
7553 04:47:33.389466
7554 04:47:33.392816 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7555 04:47:33.392897
7556 04:47:33.396190 [CATrainingPosCal] consider 2 rank data
7557 04:47:33.399448 u2DelayCellTimex100 = 258/100 ps
7558 04:47:33.405737 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7559 04:47:33.409016 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7560 04:47:33.412483 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7561 04:47:33.415741 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7562 04:47:33.419356 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7563 04:47:33.422505 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7564 04:47:33.422592
7565 04:47:33.425751 CA PerBit enable=1, Macro0, CA PI delay=36
7566 04:47:33.425832
7567 04:47:33.429263 [CBTSetCACLKResult] CA Dly = 36
7568 04:47:33.432237 CS Dly: 11 (0~43)
7569 04:47:33.435652 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7570 04:47:33.439087 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7571 04:47:33.439168
7572 04:47:33.442452 ----->DramcWriteLeveling(PI) begin...
7573 04:47:33.442534 ==
7574 04:47:33.445610 Dram Type= 6, Freq= 0, CH_0, rank 0
7575 04:47:33.452368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7576 04:47:33.452450 ==
7577 04:47:33.455599 Write leveling (Byte 0): 35 => 35
7578 04:47:33.458965 Write leveling (Byte 1): 29 => 29
7579 04:47:33.459048 DramcWriteLeveling(PI) end<-----
7580 04:47:33.461941
7581 04:47:33.462021 ==
7582 04:47:33.465431 Dram Type= 6, Freq= 0, CH_0, rank 0
7583 04:47:33.468922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7584 04:47:33.469004 ==
7585 04:47:33.472361 [Gating] SW mode calibration
7586 04:47:33.478791 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7587 04:47:33.482335 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7588 04:47:33.488466 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 04:47:33.491896 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 04:47:33.495472 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 04:47:33.501856 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 04:47:33.505261 1 4 16 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7593 04:47:33.508478 1 4 20 | B1->B0 | 2323 3434 | 0 0 | (1 1) (0 0)
7594 04:47:33.515031 1 4 24 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7595 04:47:33.518479 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 04:47:33.521572 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 04:47:33.528283 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 04:47:33.531528 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 04:47:33.535104 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 04:47:33.541389 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
7601 04:47:33.544853 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7602 04:47:33.548184 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
7603 04:47:33.554690 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 04:47:33.558129 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 04:47:33.561443 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 04:47:33.567942 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 04:47:33.571608 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 04:47:33.574549 1 6 16 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7609 04:47:33.581306 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7610 04:47:33.584606 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 04:47:33.588084 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 04:47:33.594634 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 04:47:33.597958 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 04:47:33.601407 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 04:47:33.607960 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7616 04:47:33.611194 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7617 04:47:33.614642 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7618 04:47:33.621267 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7619 04:47:33.624617 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 04:47:33.627854 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 04:47:33.634503 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 04:47:33.637846 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 04:47:33.641078 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 04:47:33.647721 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 04:47:33.650884 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 04:47:33.654359 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 04:47:33.660799 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 04:47:33.664135 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 04:47:33.667250 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 04:47:33.673952 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 04:47:33.677363 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7632 04:47:33.680520 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7633 04:47:33.687327 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7634 04:47:33.687411 Total UI for P1: 0, mck2ui 16
7635 04:47:33.690476 best dqsien dly found for B0: ( 1, 9, 14)
7636 04:47:33.697185 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7637 04:47:33.700506 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 04:47:33.703891 Total UI for P1: 0, mck2ui 16
7639 04:47:33.707115 best dqsien dly found for B1: ( 1, 9, 24)
7640 04:47:33.710662 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7641 04:47:33.713673 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7642 04:47:33.713755
7643 04:47:33.717063 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7644 04:47:33.723802 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7645 04:47:33.723884 [Gating] SW calibration Done
7646 04:47:33.723950 ==
7647 04:47:33.727032 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 04:47:33.733547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 04:47:33.733630 ==
7650 04:47:33.733696 RX Vref Scan: 0
7651 04:47:33.733758
7652 04:47:33.737014 RX Vref 0 -> 0, step: 1
7653 04:47:33.737095
7654 04:47:33.740217 RX Delay 0 -> 252, step: 8
7655 04:47:33.743763 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7656 04:47:33.746768 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7657 04:47:33.750269 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7658 04:47:33.756875 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7659 04:47:33.760358 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7660 04:47:33.763415 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7661 04:47:33.766599 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7662 04:47:33.770329 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7663 04:47:33.776831 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7664 04:47:33.780361 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7665 04:47:33.783273 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7666 04:47:33.786607 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7667 04:47:33.790130 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7668 04:47:33.796934 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7669 04:47:33.800414 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7670 04:47:33.803734 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7671 04:47:33.803967 ==
7672 04:47:33.806532 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 04:47:33.810101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 04:47:33.810372 ==
7675 04:47:33.813602 DQS Delay:
7676 04:47:33.813882 DQS0 = 0, DQS1 = 0
7677 04:47:33.817040 DQM Delay:
7678 04:47:33.817327 DQM0 = 128, DQM1 = 124
7679 04:47:33.820222 DQ Delay:
7680 04:47:33.823654 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7681 04:47:33.826900 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7682 04:47:33.830186 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7683 04:47:33.833628 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7684 04:47:33.834179
7685 04:47:33.834556
7686 04:47:33.834905 ==
7687 04:47:33.836681 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 04:47:33.840166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 04:47:33.840634 ==
7690 04:47:33.841005
7691 04:47:33.841318
7692 04:47:33.843495 TX Vref Scan disable
7693 04:47:33.846757 == TX Byte 0 ==
7694 04:47:33.849818 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7695 04:47:33.853261 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7696 04:47:33.856645 == TX Byte 1 ==
7697 04:47:33.860113 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7698 04:47:33.863349 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7699 04:47:33.863788 ==
7700 04:47:33.866512 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 04:47:33.872877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 04:47:33.873302 ==
7703 04:47:33.886442
7704 04:47:33.889758 TX Vref early break, caculate TX vref
7705 04:47:33.893150 TX Vref=16, minBit 8, minWin=21, winSum=358
7706 04:47:33.896559 TX Vref=18, minBit 7, minWin=22, winSum=367
7707 04:47:33.899616 TX Vref=20, minBit 8, minWin=22, winSum=379
7708 04:47:33.903361 TX Vref=22, minBit 8, minWin=23, winSum=391
7709 04:47:33.906261 TX Vref=24, minBit 4, minWin=24, winSum=396
7710 04:47:33.912627 TX Vref=26, minBit 8, minWin=24, winSum=405
7711 04:47:33.916406 TX Vref=28, minBit 4, minWin=24, winSum=404
7712 04:47:33.919455 TX Vref=30, minBit 8, minWin=24, winSum=402
7713 04:47:33.923090 TX Vref=32, minBit 0, minWin=24, winSum=394
7714 04:47:33.926035 TX Vref=34, minBit 8, minWin=23, winSum=385
7715 04:47:33.929283 TX Vref=36, minBit 8, minWin=22, winSum=375
7716 04:47:33.935964 [TxChooseVref] Worse bit 8, Min win 24, Win sum 405, Final Vref 26
7717 04:47:33.936386
7718 04:47:33.939763 Final TX Range 0 Vref 26
7719 04:47:33.940282
7720 04:47:33.940622 ==
7721 04:47:33.942727 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 04:47:33.945960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 04:47:33.946395 ==
7724 04:47:33.946731
7725 04:47:33.949106
7726 04:47:33.949564 TX Vref Scan disable
7727 04:47:33.956253 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7728 04:47:33.956778 == TX Byte 0 ==
7729 04:47:33.959685 u2DelayCellOfst[0]=11 cells (3 PI)
7730 04:47:33.962687 u2DelayCellOfst[1]=15 cells (4 PI)
7731 04:47:33.966105 u2DelayCellOfst[2]=7 cells (2 PI)
7732 04:47:33.969181 u2DelayCellOfst[3]=11 cells (3 PI)
7733 04:47:33.973036 u2DelayCellOfst[4]=3 cells (1 PI)
7734 04:47:33.976174 u2DelayCellOfst[5]=0 cells (0 PI)
7735 04:47:33.979170 u2DelayCellOfst[6]=18 cells (5 PI)
7736 04:47:33.983091 u2DelayCellOfst[7]=15 cells (4 PI)
7737 04:47:33.986030 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7738 04:47:33.989535 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7739 04:47:33.992810 == TX Byte 1 ==
7740 04:47:33.995852 u2DelayCellOfst[8]=0 cells (0 PI)
7741 04:47:33.996469 u2DelayCellOfst[9]=3 cells (1 PI)
7742 04:47:33.999116 u2DelayCellOfst[10]=7 cells (2 PI)
7743 04:47:34.002696 u2DelayCellOfst[11]=3 cells (1 PI)
7744 04:47:34.005673 u2DelayCellOfst[12]=11 cells (3 PI)
7745 04:47:34.009253 u2DelayCellOfst[13]=11 cells (3 PI)
7746 04:47:34.012628 u2DelayCellOfst[14]=15 cells (4 PI)
7747 04:47:34.016018 u2DelayCellOfst[15]=11 cells (3 PI)
7748 04:47:34.022203 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7749 04:47:34.025266 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7750 04:47:34.025348 DramC Write-DBI on
7751 04:47:34.025413 ==
7752 04:47:34.028737 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 04:47:34.035153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 04:47:34.035235 ==
7755 04:47:34.035309
7756 04:47:34.035370
7757 04:47:34.035428 TX Vref Scan disable
7758 04:47:34.039372 == TX Byte 0 ==
7759 04:47:34.042700 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7760 04:47:34.045884 == TX Byte 1 ==
7761 04:47:34.049211 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7762 04:47:34.052801 DramC Write-DBI off
7763 04:47:34.052882
7764 04:47:34.052947 [DATLAT]
7765 04:47:34.053007 Freq=1600, CH0 RK0
7766 04:47:34.053066
7767 04:47:34.056005 DATLAT Default: 0xf
7768 04:47:34.056086 0, 0xFFFF, sum = 0
7769 04:47:34.059193 1, 0xFFFF, sum = 0
7770 04:47:34.059276 2, 0xFFFF, sum = 0
7771 04:47:34.062532 3, 0xFFFF, sum = 0
7772 04:47:34.066057 4, 0xFFFF, sum = 0
7773 04:47:34.066141 5, 0xFFFF, sum = 0
7774 04:47:34.069356 6, 0xFFFF, sum = 0
7775 04:47:34.069481 7, 0xFFFF, sum = 0
7776 04:47:34.072638 8, 0xFFFF, sum = 0
7777 04:47:34.072727 9, 0xFFFF, sum = 0
7778 04:47:34.076038 10, 0xFFFF, sum = 0
7779 04:47:34.076134 11, 0xFFFF, sum = 0
7780 04:47:34.079275 12, 0xFFFF, sum = 0
7781 04:47:34.079379 13, 0xFFFF, sum = 0
7782 04:47:34.082297 14, 0x0, sum = 1
7783 04:47:34.082411 15, 0x0, sum = 2
7784 04:47:34.085466 16, 0x0, sum = 3
7785 04:47:34.085591 17, 0x0, sum = 4
7786 04:47:34.089156 best_step = 15
7787 04:47:34.089277
7788 04:47:34.089374 ==
7789 04:47:34.092406 Dram Type= 6, Freq= 0, CH_0, rank 0
7790 04:47:34.095725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7791 04:47:34.095864 ==
7792 04:47:34.099123 RX Vref Scan: 1
7793 04:47:34.099275
7794 04:47:34.099397 Set Vref Range= 24 -> 127
7795 04:47:34.099510
7796 04:47:34.102284 RX Vref 24 -> 127, step: 1
7797 04:47:34.102436
7798 04:47:34.106031 RX Delay 11 -> 252, step: 4
7799 04:47:34.106454
7800 04:47:34.109319 Set Vref, RX VrefLevel [Byte0]: 24
7801 04:47:34.112647 [Byte1]: 24
7802 04:47:34.113068
7803 04:47:34.115839 Set Vref, RX VrefLevel [Byte0]: 25
7804 04:47:34.119016 [Byte1]: 25
7805 04:47:34.122260
7806 04:47:34.122341 Set Vref, RX VrefLevel [Byte0]: 26
7807 04:47:34.125282 [Byte1]: 26
7808 04:47:34.129822
7809 04:47:34.129904 Set Vref, RX VrefLevel [Byte0]: 27
7810 04:47:34.133257 [Byte1]: 27
7811 04:47:34.137324
7812 04:47:34.137405 Set Vref, RX VrefLevel [Byte0]: 28
7813 04:47:34.140534 [Byte1]: 28
7814 04:47:34.145022
7815 04:47:34.145104 Set Vref, RX VrefLevel [Byte0]: 29
7816 04:47:34.148444 [Byte1]: 29
7817 04:47:34.152924
7818 04:47:34.153005 Set Vref, RX VrefLevel [Byte0]: 30
7819 04:47:34.155665 [Byte1]: 30
7820 04:47:34.160143
7821 04:47:34.160224 Set Vref, RX VrefLevel [Byte0]: 31
7822 04:47:34.163627 [Byte1]: 31
7823 04:47:34.167712
7824 04:47:34.167817 Set Vref, RX VrefLevel [Byte0]: 32
7825 04:47:34.171198 [Byte1]: 32
7826 04:47:34.175312
7827 04:47:34.175383 Set Vref, RX VrefLevel [Byte0]: 33
7828 04:47:34.178757 [Byte1]: 33
7829 04:47:34.183050
7830 04:47:34.183144 Set Vref, RX VrefLevel [Byte0]: 34
7831 04:47:34.186319 [Byte1]: 34
7832 04:47:34.190474
7833 04:47:34.190545 Set Vref, RX VrefLevel [Byte0]: 35
7834 04:47:34.193707 [Byte1]: 35
7835 04:47:34.198132
7836 04:47:34.198206 Set Vref, RX VrefLevel [Byte0]: 36
7837 04:47:34.201399 [Byte1]: 36
7838 04:47:34.205882
7839 04:47:34.205963 Set Vref, RX VrefLevel [Byte0]: 37
7840 04:47:34.208820 [Byte1]: 37
7841 04:47:34.213464
7842 04:47:34.213578 Set Vref, RX VrefLevel [Byte0]: 38
7843 04:47:34.216475 [Byte1]: 38
7844 04:47:34.221132
7845 04:47:34.221330 Set Vref, RX VrefLevel [Byte0]: 39
7846 04:47:34.224285 [Byte1]: 39
7847 04:47:34.228844
7848 04:47:34.228926 Set Vref, RX VrefLevel [Byte0]: 40
7849 04:47:34.231946 [Byte1]: 40
7850 04:47:34.236531
7851 04:47:34.236613 Set Vref, RX VrefLevel [Byte0]: 41
7852 04:47:34.239701 [Byte1]: 41
7853 04:47:34.243696
7854 04:47:34.243778 Set Vref, RX VrefLevel [Byte0]: 42
7855 04:47:34.247191 [Byte1]: 42
7856 04:47:34.251758
7857 04:47:34.251839 Set Vref, RX VrefLevel [Byte0]: 43
7858 04:47:34.254874 [Byte1]: 43
7859 04:47:34.258843
7860 04:47:34.258931 Set Vref, RX VrefLevel [Byte0]: 44
7861 04:47:34.262290 [Byte1]: 44
7862 04:47:34.266660
7863 04:47:34.266742 Set Vref, RX VrefLevel [Byte0]: 45
7864 04:47:34.270161 [Byte1]: 45
7865 04:47:34.274167
7866 04:47:34.274247 Set Vref, RX VrefLevel [Byte0]: 46
7867 04:47:34.277521 [Byte1]: 46
7868 04:47:34.282032
7869 04:47:34.282112 Set Vref, RX VrefLevel [Byte0]: 47
7870 04:47:34.285215 [Byte1]: 47
7871 04:47:34.289406
7872 04:47:34.289523 Set Vref, RX VrefLevel [Byte0]: 48
7873 04:47:34.292950 [Byte1]: 48
7874 04:47:34.297281
7875 04:47:34.297362 Set Vref, RX VrefLevel [Byte0]: 49
7876 04:47:34.300388 [Byte1]: 49
7877 04:47:34.304760
7878 04:47:34.304840 Set Vref, RX VrefLevel [Byte0]: 50
7879 04:47:34.307882 [Byte1]: 50
7880 04:47:34.312386
7881 04:47:34.312467 Set Vref, RX VrefLevel [Byte0]: 51
7882 04:47:34.315702 [Byte1]: 51
7883 04:47:34.320050
7884 04:47:34.320131 Set Vref, RX VrefLevel [Byte0]: 52
7885 04:47:34.323539 [Byte1]: 52
7886 04:47:34.327533
7887 04:47:34.327614 Set Vref, RX VrefLevel [Byte0]: 53
7888 04:47:34.330871 [Byte1]: 53
7889 04:47:34.335105
7890 04:47:34.335187 Set Vref, RX VrefLevel [Byte0]: 54
7891 04:47:34.338496 [Byte1]: 54
7892 04:47:34.342824
7893 04:47:34.342911 Set Vref, RX VrefLevel [Byte0]: 55
7894 04:47:34.346152 [Byte1]: 55
7895 04:47:34.350414
7896 04:47:34.350516 Set Vref, RX VrefLevel [Byte0]: 56
7897 04:47:34.353835 [Byte1]: 56
7898 04:47:34.358308
7899 04:47:34.358418 Set Vref, RX VrefLevel [Byte0]: 57
7900 04:47:34.361485 [Byte1]: 57
7901 04:47:34.365622
7902 04:47:34.365755 Set Vref, RX VrefLevel [Byte0]: 58
7903 04:47:34.369222 [Byte1]: 58
7904 04:47:34.373611
7905 04:47:34.373761 Set Vref, RX VrefLevel [Byte0]: 59
7906 04:47:34.376605 [Byte1]: 59
7907 04:47:34.380936
7908 04:47:34.381017 Set Vref, RX VrefLevel [Byte0]: 60
7909 04:47:34.384107 [Byte1]: 60
7910 04:47:34.388550
7911 04:47:34.388632 Set Vref, RX VrefLevel [Byte0]: 61
7912 04:47:34.391993 [Byte1]: 61
7913 04:47:34.396207
7914 04:47:34.396293 Set Vref, RX VrefLevel [Byte0]: 62
7915 04:47:34.399413 [Byte1]: 62
7916 04:47:34.403846
7917 04:47:34.403928 Set Vref, RX VrefLevel [Byte0]: 63
7918 04:47:34.406952 [Byte1]: 63
7919 04:47:34.411087
7920 04:47:34.411169 Set Vref, RX VrefLevel [Byte0]: 64
7921 04:47:34.414485 [Byte1]: 64
7922 04:47:34.418736
7923 04:47:34.418817 Set Vref, RX VrefLevel [Byte0]: 65
7924 04:47:34.422234 [Byte1]: 65
7925 04:47:34.426493
7926 04:47:34.426579 Set Vref, RX VrefLevel [Byte0]: 66
7927 04:47:34.429879 [Byte1]: 66
7928 04:47:34.434143
7929 04:47:34.434224 Set Vref, RX VrefLevel [Byte0]: 67
7930 04:47:34.437352 [Byte1]: 67
7931 04:47:34.441940
7932 04:47:34.442021 Set Vref, RX VrefLevel [Byte0]: 68
7933 04:47:34.445096 [Byte1]: 68
7934 04:47:34.449366
7935 04:47:34.449469 Set Vref, RX VrefLevel [Byte0]: 69
7936 04:47:34.452864 [Byte1]: 69
7937 04:47:34.456787
7938 04:47:34.456861 Set Vref, RX VrefLevel [Byte0]: 70
7939 04:47:34.460154 [Byte1]: 70
7940 04:47:34.464765
7941 04:47:34.464844 Set Vref, RX VrefLevel [Byte0]: 71
7942 04:47:34.467927 [Byte1]: 71
7943 04:47:34.472372
7944 04:47:34.472449 Set Vref, RX VrefLevel [Byte0]: 72
7945 04:47:34.475329 [Byte1]: 72
7946 04:47:34.479787
7947 04:47:34.479861 Set Vref, RX VrefLevel [Byte0]: 73
7948 04:47:34.483139 [Byte1]: 73
7949 04:47:34.487263
7950 04:47:34.487335 Set Vref, RX VrefLevel [Byte0]: 74
7951 04:47:34.490684 [Byte1]: 74
7952 04:47:34.494962
7953 04:47:34.495041 Set Vref, RX VrefLevel [Byte0]: 75
7954 04:47:34.498289 [Byte1]: 75
7955 04:47:34.502735
7956 04:47:34.502818 Set Vref, RX VrefLevel [Byte0]: 76
7957 04:47:34.505899 [Byte1]: 76
7958 04:47:34.510181
7959 04:47:34.510263 Set Vref, RX VrefLevel [Byte0]: 77
7960 04:47:34.513439 [Byte1]: 77
7961 04:47:34.518168
7962 04:47:34.518241 Final RX Vref Byte 0 = 64 to rank0
7963 04:47:34.520978 Final RX Vref Byte 1 = 58 to rank0
7964 04:47:34.524339 Final RX Vref Byte 0 = 64 to rank1
7965 04:47:34.527790 Final RX Vref Byte 1 = 58 to rank1==
7966 04:47:34.531222 Dram Type= 6, Freq= 0, CH_0, rank 0
7967 04:47:34.537612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7968 04:47:34.537708 ==
7969 04:47:34.537776 DQS Delay:
7970 04:47:34.537836 DQS0 = 0, DQS1 = 0
7971 04:47:34.540868 DQM Delay:
7972 04:47:34.540939 DQM0 = 126, DQM1 = 120
7973 04:47:34.544400 DQ Delay:
7974 04:47:34.547669 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7975 04:47:34.550893 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7976 04:47:34.554256 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
7977 04:47:34.557464 DQ12 =126, DQ13 =124, DQ14 =130, DQ15 =128
7978 04:47:34.557581
7979 04:47:34.557643
7980 04:47:34.557716
7981 04:47:34.560707 [DramC_TX_OE_Calibration] TA2
7982 04:47:34.564067 Original DQ_B0 (3 6) =30, OEN = 27
7983 04:47:34.567313 Original DQ_B1 (3 6) =30, OEN = 27
7984 04:47:34.570769 24, 0x0, End_B0=24 End_B1=24
7985 04:47:34.570851 25, 0x0, End_B0=25 End_B1=25
7986 04:47:34.574316 26, 0x0, End_B0=26 End_B1=26
7987 04:47:34.577380 27, 0x0, End_B0=27 End_B1=27
7988 04:47:34.580671 28, 0x0, End_B0=28 End_B1=28
7989 04:47:34.584143 29, 0x0, End_B0=29 End_B1=29
7990 04:47:34.584217 30, 0x0, End_B0=30 End_B1=30
7991 04:47:34.587308 31, 0x4545, End_B0=30 End_B1=30
7992 04:47:34.590689 Byte0 end_step=30 best_step=27
7993 04:47:34.593961 Byte1 end_step=30 best_step=27
7994 04:47:34.597428 Byte0 TX OE(2T, 0.5T) = (3, 3)
7995 04:47:34.600443 Byte1 TX OE(2T, 0.5T) = (3, 3)
7996 04:47:34.600525
7997 04:47:34.600590
7998 04:47:34.607424 [DQSOSCAuto] RK0, (LSB)MR18= 0x1312, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
7999 04:47:34.610739 CH0 RK0: MR19=303, MR18=1312
8000 04:47:34.617107 CH0_RK0: MR19=0x303, MR18=0x1312, DQSOSC=400, MR23=63, INC=23, DEC=15
8001 04:47:34.617190
8002 04:47:34.620687 ----->DramcWriteLeveling(PI) begin...
8003 04:47:34.620770 ==
8004 04:47:34.624078 Dram Type= 6, Freq= 0, CH_0, rank 1
8005 04:47:34.627113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8006 04:47:34.627195 ==
8007 04:47:34.630461 Write leveling (Byte 0): 34 => 34
8008 04:47:34.633952 Write leveling (Byte 1): 27 => 27
8009 04:47:34.637151 DramcWriteLeveling(PI) end<-----
8010 04:47:34.637232
8011 04:47:34.637297 ==
8012 04:47:34.640665 Dram Type= 6, Freq= 0, CH_0, rank 1
8013 04:47:34.643894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 04:47:34.643976 ==
8015 04:47:34.647021 [Gating] SW mode calibration
8016 04:47:34.653741 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8017 04:47:34.660467 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8018 04:47:34.663950 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 04:47:34.670283 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 04:47:34.673672 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 04:47:34.676880 1 4 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
8022 04:47:34.683522 1 4 16 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
8023 04:47:34.686898 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8024 04:47:34.690024 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 04:47:34.696956 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 04:47:34.700265 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 04:47:34.703398 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 04:47:34.706935 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8029 04:47:34.713469 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8030 04:47:34.716867 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8031 04:47:34.720039 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8032 04:47:34.726587 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8033 04:47:34.730113 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 04:47:34.733575 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 04:47:34.739895 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 04:47:34.743381 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8037 04:47:34.746365 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8038 04:47:34.753269 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8039 04:47:34.756327 1 6 20 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
8040 04:47:34.759958 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 04:47:34.766427 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 04:47:34.769763 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 04:47:34.772991 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 04:47:34.779556 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8045 04:47:34.783058 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8046 04:47:34.786226 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8047 04:47:34.792682 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8048 04:47:34.796197 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 04:47:34.799504 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 04:47:34.806137 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 04:47:34.809579 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 04:47:34.812523 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 04:47:34.819373 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 04:47:34.822805 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 04:47:34.825938 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 04:47:34.832799 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 04:47:34.835806 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 04:47:34.839196 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 04:47:34.846025 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 04:47:34.849431 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8061 04:47:34.852626 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8062 04:47:34.859647 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8063 04:47:34.859953 Total UI for P1: 0, mck2ui 16
8064 04:47:34.862866 best dqsien dly found for B0: ( 1, 9, 10)
8065 04:47:34.869446 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 04:47:34.872902 Total UI for P1: 0, mck2ui 16
8067 04:47:34.876107 best dqsien dly found for B1: ( 1, 9, 18)
8068 04:47:34.879708 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8069 04:47:34.882915 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8070 04:47:34.883334
8071 04:47:34.886142 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8072 04:47:34.889525 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8073 04:47:34.892825 [Gating] SW calibration Done
8074 04:47:34.893246 ==
8075 04:47:34.896289 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 04:47:34.899506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 04:47:34.899928 ==
8078 04:47:34.902792 RX Vref Scan: 0
8079 04:47:34.903209
8080 04:47:34.906034 RX Vref 0 -> 0, step: 1
8081 04:47:34.906527
8082 04:47:34.906866 RX Delay 0 -> 252, step: 8
8083 04:47:34.912748 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8084 04:47:34.915948 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8085 04:47:34.919047 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8086 04:47:34.922432 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8087 04:47:34.925969 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8088 04:47:34.932427 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8089 04:47:34.935975 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8090 04:47:34.939199 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8091 04:47:34.942605 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8092 04:47:34.945550 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8093 04:47:34.952362 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
8094 04:47:34.955119 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8095 04:47:34.958516 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8096 04:47:34.961655 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8097 04:47:34.968589 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8098 04:47:34.971530 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8099 04:47:34.971612 ==
8100 04:47:34.974908 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 04:47:34.978598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 04:47:34.978704 ==
8103 04:47:34.981461 DQS Delay:
8104 04:47:34.981584 DQS0 = 0, DQS1 = 0
8105 04:47:34.981651 DQM Delay:
8106 04:47:34.984673 DQM0 = 128, DQM1 = 120
8107 04:47:34.984755 DQ Delay:
8108 04:47:34.988252 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8109 04:47:34.991415 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8110 04:47:34.994982 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
8111 04:47:35.001681 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8112 04:47:35.001762
8113 04:47:35.001827
8114 04:47:35.001886 ==
8115 04:47:35.004866 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 04:47:35.008354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 04:47:35.008442 ==
8118 04:47:35.008512
8119 04:47:35.008579
8120 04:47:35.011663 TX Vref Scan disable
8121 04:47:35.011758 == TX Byte 0 ==
8122 04:47:35.018219 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8123 04:47:35.021625 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8124 04:47:35.021741 == TX Byte 1 ==
8125 04:47:35.028200 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8126 04:47:35.031585 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8127 04:47:35.031721 ==
8128 04:47:35.035014 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 04:47:35.038305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 04:47:35.038458 ==
8131 04:47:35.054103
8132 04:47:35.057503 TX Vref early break, caculate TX vref
8133 04:47:35.060575 TX Vref=16, minBit 8, minWin=21, winSum=365
8134 04:47:35.064131 TX Vref=18, minBit 8, minWin=22, winSum=370
8135 04:47:35.067235 TX Vref=20, minBit 8, minWin=22, winSum=381
8136 04:47:35.070667 TX Vref=22, minBit 1, minWin=23, winSum=391
8137 04:47:35.074129 TX Vref=24, minBit 0, minWin=24, winSum=399
8138 04:47:35.080783 TX Vref=26, minBit 8, minWin=24, winSum=404
8139 04:47:35.083880 TX Vref=28, minBit 8, minWin=24, winSum=408
8140 04:47:35.087254 TX Vref=30, minBit 8, minWin=23, winSum=401
8141 04:47:35.090675 TX Vref=32, minBit 8, minWin=23, winSum=397
8142 04:47:35.093980 TX Vref=34, minBit 8, minWin=22, winSum=387
8143 04:47:35.097091 TX Vref=36, minBit 8, minWin=22, winSum=379
8144 04:47:35.104142 [TxChooseVref] Worse bit 8, Min win 24, Win sum 408, Final Vref 28
8145 04:47:35.104570
8146 04:47:35.107276 Final TX Range 0 Vref 28
8147 04:47:35.107699
8148 04:47:35.108063 ==
8149 04:47:35.110744 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 04:47:35.113782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 04:47:35.114361 ==
8152 04:47:35.114960
8153 04:47:35.117223
8154 04:47:35.117794 TX Vref Scan disable
8155 04:47:35.124098 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8156 04:47:35.124522 == TX Byte 0 ==
8157 04:47:35.127046 u2DelayCellOfst[0]=18 cells (5 PI)
8158 04:47:35.130462 u2DelayCellOfst[1]=22 cells (6 PI)
8159 04:47:35.133699 u2DelayCellOfst[2]=15 cells (4 PI)
8160 04:47:35.137107 u2DelayCellOfst[3]=15 cells (4 PI)
8161 04:47:35.140301 u2DelayCellOfst[4]=11 cells (3 PI)
8162 04:47:35.143453 u2DelayCellOfst[5]=0 cells (0 PI)
8163 04:47:35.146976 u2DelayCellOfst[6]=22 cells (6 PI)
8164 04:47:35.150346 u2DelayCellOfst[7]=18 cells (5 PI)
8165 04:47:35.153559 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8166 04:47:35.156985 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8167 04:47:35.160521 == TX Byte 1 ==
8168 04:47:35.163575 u2DelayCellOfst[8]=0 cells (0 PI)
8169 04:47:35.166953 u2DelayCellOfst[9]=0 cells (0 PI)
8170 04:47:35.170198 u2DelayCellOfst[10]=11 cells (3 PI)
8171 04:47:35.170675 u2DelayCellOfst[11]=7 cells (2 PI)
8172 04:47:35.173536 u2DelayCellOfst[12]=11 cells (3 PI)
8173 04:47:35.176995 u2DelayCellOfst[13]=11 cells (3 PI)
8174 04:47:35.180181 u2DelayCellOfst[14]=15 cells (4 PI)
8175 04:47:35.183536 u2DelayCellOfst[15]=15 cells (4 PI)
8176 04:47:35.190231 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8177 04:47:35.193464 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8178 04:47:35.194077 DramC Write-DBI on
8179 04:47:35.196711 ==
8180 04:47:35.197176 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 04:47:35.203374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 04:47:35.203812 ==
8183 04:47:35.204149
8184 04:47:35.204463
8185 04:47:35.206620 TX Vref Scan disable
8186 04:47:35.207132 == TX Byte 0 ==
8187 04:47:35.212996 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8188 04:47:35.213079 == TX Byte 1 ==
8189 04:47:35.216456 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8190 04:47:35.219893 DramC Write-DBI off
8191 04:47:35.220317
8192 04:47:35.220709 [DATLAT]
8193 04:47:35.223263 Freq=1600, CH0 RK1
8194 04:47:35.223687
8195 04:47:35.224022 DATLAT Default: 0xf
8196 04:47:35.226385 0, 0xFFFF, sum = 0
8197 04:47:35.226815 1, 0xFFFF, sum = 0
8198 04:47:35.229533 2, 0xFFFF, sum = 0
8199 04:47:35.229964 3, 0xFFFF, sum = 0
8200 04:47:35.233168 4, 0xFFFF, sum = 0
8201 04:47:35.233682 5, 0xFFFF, sum = 0
8202 04:47:35.236604 6, 0xFFFF, sum = 0
8203 04:47:35.239640 7, 0xFFFF, sum = 0
8204 04:47:35.240296 8, 0xFFFF, sum = 0
8205 04:47:35.242979 9, 0xFFFF, sum = 0
8206 04:47:35.243531 10, 0xFFFF, sum = 0
8207 04:47:35.246016 11, 0xFFFF, sum = 0
8208 04:47:35.246444 12, 0xFFFF, sum = 0
8209 04:47:35.249460 13, 0xCFFF, sum = 0
8210 04:47:35.249931 14, 0x0, sum = 1
8211 04:47:35.252927 15, 0x0, sum = 2
8212 04:47:35.253447 16, 0x0, sum = 3
8213 04:47:35.255948 17, 0x0, sum = 4
8214 04:47:35.256376 best_step = 15
8215 04:47:35.256712
8216 04:47:35.257028 ==
8217 04:47:35.259412 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 04:47:35.262466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 04:47:35.266283 ==
8220 04:47:35.266705 RX Vref Scan: 0
8221 04:47:35.267044
8222 04:47:35.269204 RX Vref 0 -> 0, step: 1
8223 04:47:35.269881
8224 04:47:35.270242 RX Delay 3 -> 252, step: 4
8225 04:47:35.276364 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8226 04:47:35.280209 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8227 04:47:35.283173 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8228 04:47:35.286498 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8229 04:47:35.290058 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8230 04:47:35.296887 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8231 04:47:35.300469 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8232 04:47:35.303198 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8233 04:47:35.306597 iDelay=191, Bit 8, Center 108 (51 ~ 166) 116
8234 04:47:35.309923 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8235 04:47:35.316771 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8236 04:47:35.320111 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8237 04:47:35.323224 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8238 04:47:35.326335 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8239 04:47:35.332822 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8240 04:47:35.336291 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8241 04:47:35.336822 ==
8242 04:47:35.339633 Dram Type= 6, Freq= 0, CH_0, rank 1
8243 04:47:35.342790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 04:47:35.343216 ==
8245 04:47:35.343555 DQS Delay:
8246 04:47:35.346287 DQS0 = 0, DQS1 = 0
8247 04:47:35.346710 DQM Delay:
8248 04:47:35.349563 DQM0 = 124, DQM1 = 117
8249 04:47:35.349992 DQ Delay:
8250 04:47:35.352859 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8251 04:47:35.356078 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8252 04:47:35.359649 DQ8 =108, DQ9 =104, DQ10 =118, DQ11 =112
8253 04:47:35.366021 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8254 04:47:35.366446
8255 04:47:35.366784
8256 04:47:35.367096
8257 04:47:35.369301 [DramC_TX_OE_Calibration] TA2
8258 04:47:35.369886 Original DQ_B0 (3 6) =30, OEN = 27
8259 04:47:35.372776 Original DQ_B1 (3 6) =30, OEN = 27
8260 04:47:35.375966 24, 0x0, End_B0=24 End_B1=24
8261 04:47:35.379442 25, 0x0, End_B0=25 End_B1=25
8262 04:47:35.382519 26, 0x0, End_B0=26 End_B1=26
8263 04:47:35.385967 27, 0x0, End_B0=27 End_B1=27
8264 04:47:35.386395 28, 0x0, End_B0=28 End_B1=28
8265 04:47:35.389516 29, 0x0, End_B0=29 End_B1=29
8266 04:47:35.393061 30, 0x0, End_B0=30 End_B1=30
8267 04:47:35.395932 31, 0x4545, End_B0=30 End_B1=30
8268 04:47:35.399113 Byte0 end_step=30 best_step=27
8269 04:47:35.399599 Byte1 end_step=30 best_step=27
8270 04:47:35.402560 Byte0 TX OE(2T, 0.5T) = (3, 3)
8271 04:47:35.406017 Byte1 TX OE(2T, 0.5T) = (3, 3)
8272 04:47:35.406455
8273 04:47:35.406929
8274 04:47:35.416084 [DQSOSCAuto] RK1, (LSB)MR18= 0x2613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
8275 04:47:35.416571 CH0 RK1: MR19=303, MR18=2613
8276 04:47:35.422600 CH0_RK1: MR19=0x303, MR18=0x2613, DQSOSC=390, MR23=63, INC=24, DEC=16
8277 04:47:35.425890 [RxdqsGatingPostProcess] freq 1600
8278 04:47:35.432343 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8279 04:47:35.435659 best DQS0 dly(2T, 0.5T) = (1, 1)
8280 04:47:35.439020 best DQS1 dly(2T, 0.5T) = (1, 1)
8281 04:47:35.442176 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8282 04:47:35.445787 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8283 04:47:35.446323 best DQS0 dly(2T, 0.5T) = (1, 1)
8284 04:47:35.449006 best DQS1 dly(2T, 0.5T) = (1, 1)
8285 04:47:35.452392 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8286 04:47:35.456191 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8287 04:47:35.459010 Pre-setting of DQS Precalculation
8288 04:47:35.465368 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8289 04:47:35.465839 ==
8290 04:47:35.468826 Dram Type= 6, Freq= 0, CH_1, rank 0
8291 04:47:35.472140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 04:47:35.472566 ==
8293 04:47:35.478999 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8294 04:47:35.481965 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8295 04:47:35.485406 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8296 04:47:35.491932 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8297 04:47:35.501208 [CA 0] Center 42 (13~72) winsize 60
8298 04:47:35.504074 [CA 1] Center 43 (14~73) winsize 60
8299 04:47:35.507521 [CA 2] Center 38 (10~67) winsize 58
8300 04:47:35.511020 [CA 3] Center 37 (8~66) winsize 59
8301 04:47:35.514098 [CA 4] Center 37 (8~67) winsize 60
8302 04:47:35.517220 [CA 5] Center 37 (8~66) winsize 59
8303 04:47:35.517671
8304 04:47:35.520866 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8305 04:47:35.521315
8306 04:47:35.527289 [CATrainingPosCal] consider 1 rank data
8307 04:47:35.527710 u2DelayCellTimex100 = 258/100 ps
8308 04:47:35.533963 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8309 04:47:35.537553 CA1 delay=43 (14~73),Diff = 6 PI (22 cell)
8310 04:47:35.540648 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8311 04:47:35.543771 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8312 04:47:35.547081 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8313 04:47:35.550452 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8314 04:47:35.550868
8315 04:47:35.553817 CA PerBit enable=1, Macro0, CA PI delay=37
8316 04:47:35.554288
8317 04:47:35.556974 [CBTSetCACLKResult] CA Dly = 37
8318 04:47:35.560142 CS Dly: 9 (0~40)
8319 04:47:35.563421 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8320 04:47:35.566666 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8321 04:47:35.567184 ==
8322 04:47:35.570282 Dram Type= 6, Freq= 0, CH_1, rank 1
8323 04:47:35.576763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 04:47:35.577185 ==
8325 04:47:35.580036 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8326 04:47:35.583480 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8327 04:47:35.590333 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8328 04:47:35.596615 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8329 04:47:35.604288 [CA 0] Center 42 (13~71) winsize 59
8330 04:47:35.607395 [CA 1] Center 42 (12~72) winsize 61
8331 04:47:35.610734 [CA 2] Center 37 (8~66) winsize 59
8332 04:47:35.614173 [CA 3] Center 36 (7~66) winsize 60
8333 04:47:35.617212 [CA 4] Center 37 (7~67) winsize 61
8334 04:47:35.620716 [CA 5] Center 36 (6~66) winsize 61
8335 04:47:35.621129
8336 04:47:35.624067 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8337 04:47:35.624482
8338 04:47:35.627463 [CATrainingPosCal] consider 2 rank data
8339 04:47:35.630683 u2DelayCellTimex100 = 258/100 ps
8340 04:47:35.634574 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8341 04:47:35.640533 CA1 delay=43 (14~72),Diff = 6 PI (22 cell)
8342 04:47:35.644010 CA2 delay=38 (10~66),Diff = 1 PI (3 cell)
8343 04:47:35.646996 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8344 04:47:35.650376 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8345 04:47:35.653756 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8346 04:47:35.654171
8347 04:47:35.657154 CA PerBit enable=1, Macro0, CA PI delay=37
8348 04:47:35.657612
8349 04:47:35.660369 [CBTSetCACLKResult] CA Dly = 37
8350 04:47:35.663737 CS Dly: 11 (0~44)
8351 04:47:35.667181 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8352 04:47:35.670098 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8353 04:47:35.670512
8354 04:47:35.673585 ----->DramcWriteLeveling(PI) begin...
8355 04:47:35.674010 ==
8356 04:47:35.676967 Dram Type= 6, Freq= 0, CH_1, rank 0
8357 04:47:35.683898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 04:47:35.684394 ==
8359 04:47:35.687024 Write leveling (Byte 0): 25 => 25
8360 04:47:35.687546 Write leveling (Byte 1): 28 => 28
8361 04:47:35.690496 DramcWriteLeveling(PI) end<-----
8362 04:47:35.690929
8363 04:47:35.693426 ==
8364 04:47:35.693899 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 04:47:35.700267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 04:47:35.700701 ==
8367 04:47:35.703700 [Gating] SW mode calibration
8368 04:47:35.710075 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8369 04:47:35.713544 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8370 04:47:35.719837 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 04:47:35.723414 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 04:47:35.726576 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 04:47:35.733258 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 04:47:35.736291 1 4 16 | B1->B0 | 3434 3232 | 1 1 | (0 0) (0 0)
8375 04:47:35.739822 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 04:47:35.746697 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 04:47:35.749981 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 04:47:35.753409 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 04:47:35.760366 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 04:47:35.762992 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8381 04:47:35.766436 1 5 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
8382 04:47:35.772934 1 5 16 | B1->B0 | 2424 2424 | 0 0 | (1 0) (1 0)
8383 04:47:35.776260 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 04:47:35.779942 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 04:47:35.786642 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 04:47:35.789686 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 04:47:35.793212 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 04:47:35.799950 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 04:47:35.803215 1 6 12 | B1->B0 | 2d2d 2828 | 0 0 | (0 0) (0 0)
8390 04:47:35.806388 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 04:47:35.812769 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 04:47:35.816309 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 04:47:35.819604 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 04:47:35.826006 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 04:47:35.829556 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 04:47:35.832910 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 04:47:35.839205 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 04:47:35.842609 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8399 04:47:35.845834 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8400 04:47:35.849278 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 04:47:35.856115 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 04:47:35.859266 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 04:47:35.862430 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 04:47:35.869149 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 04:47:35.872271 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 04:47:35.875654 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 04:47:35.882387 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 04:47:35.885466 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 04:47:35.889072 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 04:47:35.895613 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 04:47:35.898938 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 04:47:35.902590 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 04:47:35.908990 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8414 04:47:35.911963 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8415 04:47:35.915278 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8416 04:47:35.918827 Total UI for P1: 0, mck2ui 16
8417 04:47:35.921992 best dqsien dly found for B1: ( 1, 9, 14)
8418 04:47:35.928736 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 04:47:35.929169 Total UI for P1: 0, mck2ui 16
8420 04:47:35.935412 best dqsien dly found for B0: ( 1, 9, 16)
8421 04:47:35.938741 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8422 04:47:35.942048 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8423 04:47:35.942468
8424 04:47:35.945255 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8425 04:47:35.948762 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8426 04:47:35.952160 [Gating] SW calibration Done
8427 04:47:35.952577 ==
8428 04:47:35.955103 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 04:47:35.958535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 04:47:35.958960 ==
8431 04:47:35.961669 RX Vref Scan: 0
8432 04:47:35.962088
8433 04:47:35.962420 RX Vref 0 -> 0, step: 1
8434 04:47:35.965196
8435 04:47:35.965655 RX Delay 0 -> 252, step: 8
8436 04:47:35.968731 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8437 04:47:35.975099 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8438 04:47:35.978265 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8439 04:47:35.981827 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8440 04:47:35.985081 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8441 04:47:35.988268 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8442 04:47:35.994720 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8443 04:47:35.998096 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8444 04:47:36.001529 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8445 04:47:36.004882 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8446 04:47:36.008180 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8447 04:47:36.014857 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8448 04:47:36.018155 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8449 04:47:36.021587 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8450 04:47:36.024891 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8451 04:47:36.031909 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8452 04:47:36.032341 ==
8453 04:47:36.035072 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 04:47:36.038315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 04:47:36.038748 ==
8456 04:47:36.039182 DQS Delay:
8457 04:47:36.041899 DQS0 = 0, DQS1 = 0
8458 04:47:36.042358 DQM Delay:
8459 04:47:36.044824 DQM0 = 132, DQM1 = 126
8460 04:47:36.045317 DQ Delay:
8461 04:47:36.048198 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8462 04:47:36.051306 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8463 04:47:36.054665 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8464 04:47:36.058147 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8465 04:47:36.058617
8466 04:47:36.059071
8467 04:47:36.061733 ==
8468 04:47:36.062311 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 04:47:36.068363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 04:47:36.068903 ==
8471 04:47:36.069385
8472 04:47:36.069870
8473 04:47:36.071287 TX Vref Scan disable
8474 04:47:36.071754 == TX Byte 0 ==
8475 04:47:36.074529 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8476 04:47:36.081262 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8477 04:47:36.081831 == TX Byte 1 ==
8478 04:47:36.084492 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8479 04:47:36.091223 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8480 04:47:36.091804 ==
8481 04:47:36.094743 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 04:47:36.097937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 04:47:36.098434 ==
8484 04:47:36.110532
8485 04:47:36.113959 TX Vref early break, caculate TX vref
8486 04:47:36.117304 TX Vref=16, minBit 5, minWin=21, winSum=360
8487 04:47:36.120965 TX Vref=18, minBit 9, minWin=22, winSum=369
8488 04:47:36.124156 TX Vref=20, minBit 5, minWin=23, winSum=380
8489 04:47:36.127445 TX Vref=22, minBit 12, minWin=23, winSum=390
8490 04:47:36.130489 TX Vref=24, minBit 5, minWin=24, winSum=400
8491 04:47:36.137023 TX Vref=26, minBit 13, minWin=24, winSum=413
8492 04:47:36.140567 TX Vref=28, minBit 5, minWin=25, winSum=418
8493 04:47:36.143792 TX Vref=30, minBit 0, minWin=25, winSum=416
8494 04:47:36.147026 TX Vref=32, minBit 0, minWin=24, winSum=405
8495 04:47:36.150555 TX Vref=34, minBit 6, minWin=22, winSum=395
8496 04:47:36.156949 [TxChooseVref] Worse bit 5, Min win 25, Win sum 418, Final Vref 28
8497 04:47:36.157430
8498 04:47:36.160432 Final TX Range 0 Vref 28
8499 04:47:36.160849
8500 04:47:36.161181 ==
8501 04:47:36.163928 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 04:47:36.166810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 04:47:36.167232 ==
8504 04:47:36.167567
8505 04:47:36.167877
8506 04:47:36.170132 TX Vref Scan disable
8507 04:47:36.177011 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8508 04:47:36.177609 == TX Byte 0 ==
8509 04:47:36.180304 u2DelayCellOfst[0]=22 cells (6 PI)
8510 04:47:36.183341 u2DelayCellOfst[1]=15 cells (4 PI)
8511 04:47:36.186803 u2DelayCellOfst[2]=0 cells (0 PI)
8512 04:47:36.190127 u2DelayCellOfst[3]=7 cells (2 PI)
8513 04:47:36.193542 u2DelayCellOfst[4]=11 cells (3 PI)
8514 04:47:36.196573 u2DelayCellOfst[5]=22 cells (6 PI)
8515 04:47:36.200021 u2DelayCellOfst[6]=22 cells (6 PI)
8516 04:47:36.203331 u2DelayCellOfst[7]=7 cells (2 PI)
8517 04:47:36.206745 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8518 04:47:36.210126 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8519 04:47:36.213392 == TX Byte 1 ==
8520 04:47:36.216710 u2DelayCellOfst[8]=0 cells (0 PI)
8521 04:47:36.219955 u2DelayCellOfst[9]=7 cells (2 PI)
8522 04:47:36.220428 u2DelayCellOfst[10]=18 cells (5 PI)
8523 04:47:36.223340 u2DelayCellOfst[11]=7 cells (2 PI)
8524 04:47:36.226649 u2DelayCellOfst[12]=18 cells (5 PI)
8525 04:47:36.229784 u2DelayCellOfst[13]=22 cells (6 PI)
8526 04:47:36.233294 u2DelayCellOfst[14]=22 cells (6 PI)
8527 04:47:36.236365 u2DelayCellOfst[15]=22 cells (6 PI)
8528 04:47:36.242874 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8529 04:47:36.246396 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8530 04:47:36.246806 DramC Write-DBI on
8531 04:47:36.247156 ==
8532 04:47:36.249674 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 04:47:36.255895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 04:47:36.256417 ==
8535 04:47:36.256849
8536 04:47:36.257345
8537 04:47:36.259215 TX Vref Scan disable
8538 04:47:36.259623 == TX Byte 0 ==
8539 04:47:36.265817 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8540 04:47:36.266229 == TX Byte 1 ==
8541 04:47:36.269279 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8542 04:47:36.272559 DramC Write-DBI off
8543 04:47:36.273079
8544 04:47:36.273607 [DATLAT]
8545 04:47:36.275657 Freq=1600, CH1 RK0
8546 04:47:36.276020
8547 04:47:36.276324 DATLAT Default: 0xf
8548 04:47:36.279204 0, 0xFFFF, sum = 0
8549 04:47:36.279754 1, 0xFFFF, sum = 0
8550 04:47:36.282557 2, 0xFFFF, sum = 0
8551 04:47:36.283004 3, 0xFFFF, sum = 0
8552 04:47:36.285821 4, 0xFFFF, sum = 0
8553 04:47:36.286369 5, 0xFFFF, sum = 0
8554 04:47:36.289181 6, 0xFFFF, sum = 0
8555 04:47:36.289672 7, 0xFFFF, sum = 0
8556 04:47:36.292765 8, 0xFFFF, sum = 0
8557 04:47:36.293349 9, 0xFFFF, sum = 0
8558 04:47:36.295936 10, 0xFFFF, sum = 0
8559 04:47:36.299280 11, 0xFFFF, sum = 0
8560 04:47:36.299830 12, 0xFFFF, sum = 0
8561 04:47:36.302818 13, 0x8FFF, sum = 0
8562 04:47:36.303344 14, 0x0, sum = 1
8563 04:47:36.305569 15, 0x0, sum = 2
8564 04:47:36.306026 16, 0x0, sum = 3
8565 04:47:36.309120 17, 0x0, sum = 4
8566 04:47:36.309611 best_step = 15
8567 04:47:36.309995
8568 04:47:36.310312 ==
8569 04:47:36.312429 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 04:47:36.315558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 04:47:36.315990 ==
8572 04:47:36.319085 RX Vref Scan: 1
8573 04:47:36.319511
8574 04:47:36.322149 Set Vref Range= 24 -> 127
8575 04:47:36.322579
8576 04:47:36.323040 RX Vref 24 -> 127, step: 1
8577 04:47:36.323458
8578 04:47:36.325394 RX Delay 11 -> 252, step: 4
8579 04:47:36.325895
8580 04:47:36.328664 Set Vref, RX VrefLevel [Byte0]: 24
8581 04:47:36.332107 [Byte1]: 24
8582 04:47:36.335438
8583 04:47:36.335861 Set Vref, RX VrefLevel [Byte0]: 25
8584 04:47:36.338590 [Byte1]: 25
8585 04:47:36.343434
8586 04:47:36.343856 Set Vref, RX VrefLevel [Byte0]: 26
8587 04:47:36.346651 [Byte1]: 26
8588 04:47:36.350796
8589 04:47:36.351230 Set Vref, RX VrefLevel [Byte0]: 27
8590 04:47:36.354251 [Byte1]: 27
8591 04:47:36.358428
8592 04:47:36.358848 Set Vref, RX VrefLevel [Byte0]: 28
8593 04:47:36.361646 [Byte1]: 28
8594 04:47:36.365873
8595 04:47:36.366306 Set Vref, RX VrefLevel [Byte0]: 29
8596 04:47:36.369374 [Byte1]: 29
8597 04:47:36.373582
8598 04:47:36.374039 Set Vref, RX VrefLevel [Byte0]: 30
8599 04:47:36.376876 [Byte1]: 30
8600 04:47:36.381150
8601 04:47:36.381629 Set Vref, RX VrefLevel [Byte0]: 31
8602 04:47:36.384517 [Byte1]: 31
8603 04:47:36.388933
8604 04:47:36.389352 Set Vref, RX VrefLevel [Byte0]: 32
8605 04:47:36.392358 [Byte1]: 32
8606 04:47:36.396390
8607 04:47:36.396810 Set Vref, RX VrefLevel [Byte0]: 33
8608 04:47:36.400159 [Byte1]: 33
8609 04:47:36.404166
8610 04:47:36.404593 Set Vref, RX VrefLevel [Byte0]: 34
8611 04:47:36.407833 [Byte1]: 34
8612 04:47:36.412123
8613 04:47:36.412687 Set Vref, RX VrefLevel [Byte0]: 35
8614 04:47:36.415601 [Byte1]: 35
8615 04:47:36.419730
8616 04:47:36.420344 Set Vref, RX VrefLevel [Byte0]: 36
8617 04:47:36.422479 [Byte1]: 36
8618 04:47:36.427391
8619 04:47:36.427951 Set Vref, RX VrefLevel [Byte0]: 37
8620 04:47:36.430216 [Byte1]: 37
8621 04:47:36.434442
8622 04:47:36.434919 Set Vref, RX VrefLevel [Byte0]: 38
8623 04:47:36.437910 [Byte1]: 38
8624 04:47:36.442510
8625 04:47:36.443070 Set Vref, RX VrefLevel [Byte0]: 39
8626 04:47:36.445521 [Byte1]: 39
8627 04:47:36.449924
8628 04:47:36.450485 Set Vref, RX VrefLevel [Byte0]: 40
8629 04:47:36.453233 [Byte1]: 40
8630 04:47:36.457333
8631 04:47:36.457863 Set Vref, RX VrefLevel [Byte0]: 41
8632 04:47:36.460855 [Byte1]: 41
8633 04:47:36.465052
8634 04:47:36.465555 Set Vref, RX VrefLevel [Byte0]: 42
8635 04:47:36.468340 [Byte1]: 42
8636 04:47:36.473027
8637 04:47:36.473596 Set Vref, RX VrefLevel [Byte0]: 43
8638 04:47:36.475847 [Byte1]: 43
8639 04:47:36.480718
8640 04:47:36.481285 Set Vref, RX VrefLevel [Byte0]: 44
8641 04:47:36.483768 [Byte1]: 44
8642 04:47:36.487929
8643 04:47:36.488493 Set Vref, RX VrefLevel [Byte0]: 45
8644 04:47:36.491103 [Byte1]: 45
8645 04:47:36.495384
8646 04:47:36.495992 Set Vref, RX VrefLevel [Byte0]: 46
8647 04:47:36.498709 [Byte1]: 46
8648 04:47:36.503103
8649 04:47:36.503566 Set Vref, RX VrefLevel [Byte0]: 47
8650 04:47:36.506452 [Byte1]: 47
8651 04:47:36.510707
8652 04:47:36.511235 Set Vref, RX VrefLevel [Byte0]: 48
8653 04:47:36.514111 [Byte1]: 48
8654 04:47:36.518194
8655 04:47:36.518621 Set Vref, RX VrefLevel [Byte0]: 49
8656 04:47:36.521755 [Byte1]: 49
8657 04:47:36.525931
8658 04:47:36.526367 Set Vref, RX VrefLevel [Byte0]: 50
8659 04:47:36.529338 [Byte1]: 50
8660 04:47:36.533558
8661 04:47:36.533986 Set Vref, RX VrefLevel [Byte0]: 51
8662 04:47:36.536605 [Byte1]: 51
8663 04:47:36.540796
8664 04:47:36.541222 Set Vref, RX VrefLevel [Byte0]: 52
8665 04:47:36.544172 [Byte1]: 52
8666 04:47:36.548918
8667 04:47:36.549337 Set Vref, RX VrefLevel [Byte0]: 53
8668 04:47:36.551919 [Byte1]: 53
8669 04:47:36.556671
8670 04:47:36.557092 Set Vref, RX VrefLevel [Byte0]: 54
8671 04:47:36.559781 [Byte1]: 54
8672 04:47:36.564151
8673 04:47:36.564699 Set Vref, RX VrefLevel [Byte0]: 55
8674 04:47:36.567260 [Byte1]: 55
8675 04:47:36.571363
8676 04:47:36.571782 Set Vref, RX VrefLevel [Byte0]: 56
8677 04:47:36.575034 [Byte1]: 56
8678 04:47:36.579101
8679 04:47:36.579530 Set Vref, RX VrefLevel [Byte0]: 57
8680 04:47:36.582456 [Byte1]: 57
8681 04:47:36.586625
8682 04:47:36.587041 Set Vref, RX VrefLevel [Byte0]: 58
8683 04:47:36.590131 [Byte1]: 58
8684 04:47:36.594611
8685 04:47:36.595051 Set Vref, RX VrefLevel [Byte0]: 59
8686 04:47:36.597518 [Byte1]: 59
8687 04:47:36.601913
8688 04:47:36.602335 Set Vref, RX VrefLevel [Byte0]: 60
8689 04:47:36.605306 [Byte1]: 60
8690 04:47:36.609451
8691 04:47:36.610001 Set Vref, RX VrefLevel [Byte0]: 61
8692 04:47:36.615910 [Byte1]: 61
8693 04:47:36.616327
8694 04:47:36.619491 Set Vref, RX VrefLevel [Byte0]: 62
8695 04:47:36.623013 [Byte1]: 62
8696 04:47:36.623454
8697 04:47:36.625949 Set Vref, RX VrefLevel [Byte0]: 63
8698 04:47:36.629374 [Byte1]: 63
8699 04:47:36.629890
8700 04:47:36.632855 Set Vref, RX VrefLevel [Byte0]: 64
8701 04:47:36.636098 [Byte1]: 64
8702 04:47:36.640251
8703 04:47:36.640666 Set Vref, RX VrefLevel [Byte0]: 65
8704 04:47:36.643367 [Byte1]: 65
8705 04:47:36.647602
8706 04:47:36.648016 Set Vref, RX VrefLevel [Byte0]: 66
8707 04:47:36.651032 [Byte1]: 66
8708 04:47:36.655230
8709 04:47:36.655668 Set Vref, RX VrefLevel [Byte0]: 67
8710 04:47:36.658598 [Byte1]: 67
8711 04:47:36.662624
8712 04:47:36.663040 Set Vref, RX VrefLevel [Byte0]: 68
8713 04:47:36.665970 [Byte1]: 68
8714 04:47:36.670475
8715 04:47:36.670890 Set Vref, RX VrefLevel [Byte0]: 69
8716 04:47:36.673746 [Byte1]: 69
8717 04:47:36.678046
8718 04:47:36.678464 Set Vref, RX VrefLevel [Byte0]: 70
8719 04:47:36.681424 [Byte1]: 70
8720 04:47:36.685583
8721 04:47:36.686002 Set Vref, RX VrefLevel [Byte0]: 71
8722 04:47:36.689169 [Byte1]: 71
8723 04:47:36.693334
8724 04:47:36.693805 Final RX Vref Byte 0 = 57 to rank0
8725 04:47:36.696731 Final RX Vref Byte 1 = 55 to rank0
8726 04:47:36.700372 Final RX Vref Byte 0 = 57 to rank1
8727 04:47:36.703688 Final RX Vref Byte 1 = 55 to rank1==
8728 04:47:36.706787 Dram Type= 6, Freq= 0, CH_1, rank 0
8729 04:47:36.713648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8730 04:47:36.714255 ==
8731 04:47:36.714606 DQS Delay:
8732 04:47:36.714922 DQS0 = 0, DQS1 = 0
8733 04:47:36.716372 DQM Delay:
8734 04:47:36.716902 DQM0 = 131, DQM1 = 123
8735 04:47:36.719591 DQ Delay:
8736 04:47:36.723041 DQ0 =134, DQ1 =126, DQ2 =122, DQ3 =128
8737 04:47:36.726446 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8738 04:47:36.729714 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8739 04:47:36.733291 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =132
8740 04:47:36.733764
8741 04:47:36.734102
8742 04:47:36.734413
8743 04:47:36.736607 [DramC_TX_OE_Calibration] TA2
8744 04:47:36.739758 Original DQ_B0 (3 6) =30, OEN = 27
8745 04:47:36.743234 Original DQ_B1 (3 6) =30, OEN = 27
8746 04:47:36.746418 24, 0x0, End_B0=24 End_B1=24
8747 04:47:36.746845 25, 0x0, End_B0=25 End_B1=25
8748 04:47:36.749681 26, 0x0, End_B0=26 End_B1=26
8749 04:47:36.753087 27, 0x0, End_B0=27 End_B1=27
8750 04:47:36.756528 28, 0x0, End_B0=28 End_B1=28
8751 04:47:36.759782 29, 0x0, End_B0=29 End_B1=29
8752 04:47:36.760209 30, 0x0, End_B0=30 End_B1=30
8753 04:47:36.763302 31, 0x4545, End_B0=30 End_B1=30
8754 04:47:36.766378 Byte0 end_step=30 best_step=27
8755 04:47:36.769871 Byte1 end_step=30 best_step=27
8756 04:47:36.772818 Byte0 TX OE(2T, 0.5T) = (3, 3)
8757 04:47:36.776239 Byte1 TX OE(2T, 0.5T) = (3, 3)
8758 04:47:36.776729
8759 04:47:36.777250
8760 04:47:36.782831 [DQSOSCAuto] RK0, (LSB)MR18= 0x70c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
8761 04:47:36.786254 CH1 RK0: MR19=303, MR18=70C
8762 04:47:36.792733 CH1_RK0: MR19=0x303, MR18=0x70C, DQSOSC=403, MR23=63, INC=22, DEC=15
8763 04:47:36.793285
8764 04:47:36.796247 ----->DramcWriteLeveling(PI) begin...
8765 04:47:36.796762 ==
8766 04:47:36.799399 Dram Type= 6, Freq= 0, CH_1, rank 1
8767 04:47:36.803144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 04:47:36.803665 ==
8769 04:47:36.805996 Write leveling (Byte 0): 24 => 24
8770 04:47:36.809159 Write leveling (Byte 1): 26 => 26
8771 04:47:36.812544 DramcWriteLeveling(PI) end<-----
8772 04:47:36.813117
8773 04:47:36.813657 ==
8774 04:47:36.815903 Dram Type= 6, Freq= 0, CH_1, rank 1
8775 04:47:36.819298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 04:47:36.819723 ==
8777 04:47:36.822633 [Gating] SW mode calibration
8778 04:47:36.829450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8779 04:47:36.836006 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8780 04:47:36.839210 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 04:47:36.842575 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 04:47:36.849144 1 4 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8783 04:47:36.852244 1 4 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
8784 04:47:36.855527 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 04:47:36.862376 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 04:47:36.865571 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 04:47:36.868789 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 04:47:36.875567 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 04:47:36.878924 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8790 04:47:36.882228 1 5 8 | B1->B0 | 3434 2626 | 1 1 | (1 0) (1 0)
8791 04:47:36.889332 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8792 04:47:36.892134 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 04:47:36.895511 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 04:47:36.902049 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 04:47:36.905459 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 04:47:36.909108 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 04:47:36.915478 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 04:47:36.918490 1 6 8 | B1->B0 | 2e2d 4646 | 1 0 | (0 0) (0 0)
8799 04:47:36.921773 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8800 04:47:36.928352 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 04:47:36.931865 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 04:47:36.934875 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 04:47:36.941181 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 04:47:36.944979 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 04:47:36.948093 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 04:47:36.954626 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8807 04:47:36.957910 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8808 04:47:36.961307 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 04:47:36.968026 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 04:47:36.971600 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 04:47:36.974858 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 04:47:36.981536 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 04:47:36.984448 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 04:47:36.987805 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 04:47:36.994475 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 04:47:36.998100 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 04:47:37.001055 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 04:47:37.007868 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 04:47:37.011062 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 04:47:37.014288 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 04:47:37.020915 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8822 04:47:37.024585 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8823 04:47:37.027971 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8824 04:47:37.030911 Total UI for P1: 0, mck2ui 16
8825 04:47:37.034380 best dqsien dly found for B0: ( 1, 9, 6)
8826 04:47:37.037723 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 04:47:37.041135 Total UI for P1: 0, mck2ui 16
8828 04:47:37.044401 best dqsien dly found for B1: ( 1, 9, 10)
8829 04:47:37.047547 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8830 04:47:37.054073 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8831 04:47:37.054488
8832 04:47:37.057843 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8833 04:47:37.060999 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8834 04:47:37.064293 [Gating] SW calibration Done
8835 04:47:37.064710 ==
8836 04:47:37.067258 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 04:47:37.070910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 04:47:37.071333 ==
8839 04:47:37.074301 RX Vref Scan: 0
8840 04:47:37.074955
8841 04:47:37.075310 RX Vref 0 -> 0, step: 1
8842 04:47:37.075631
8843 04:47:37.077211 RX Delay 0 -> 252, step: 8
8844 04:47:37.080724 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8845 04:47:37.084070 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8846 04:47:37.090762 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8847 04:47:37.093779 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8848 04:47:37.097362 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8849 04:47:37.100448 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8850 04:47:37.103880 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8851 04:47:37.110823 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8852 04:47:37.114144 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8853 04:47:37.117036 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8854 04:47:37.120359 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8855 04:47:37.123847 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8856 04:47:37.130548 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8857 04:47:37.133981 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8858 04:47:37.136835 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8859 04:47:37.140542 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8860 04:47:37.141059 ==
8861 04:47:37.143842 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 04:47:37.150457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 04:47:37.150875 ==
8864 04:47:37.151210 DQS Delay:
8865 04:47:37.153751 DQS0 = 0, DQS1 = 0
8866 04:47:37.154210 DQM Delay:
8867 04:47:37.156834 DQM0 = 130, DQM1 = 129
8868 04:47:37.157193 DQ Delay:
8869 04:47:37.160143 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8870 04:47:37.163704 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8871 04:47:37.166923 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8872 04:47:37.170253 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8873 04:47:37.170670
8874 04:47:37.170999
8875 04:47:37.171303 ==
8876 04:47:37.173459 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 04:47:37.179952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 04:47:37.180431 ==
8879 04:47:37.180809
8880 04:47:37.181126
8881 04:47:37.181452 TX Vref Scan disable
8882 04:47:37.183418 == TX Byte 0 ==
8883 04:47:37.186992 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8884 04:47:37.193564 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8885 04:47:37.193981 == TX Byte 1 ==
8886 04:47:37.196870 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8887 04:47:37.203432 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8888 04:47:37.203852 ==
8889 04:47:37.206674 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 04:47:37.209910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 04:47:37.210326 ==
8892 04:47:37.222282
8893 04:47:37.225920 TX Vref early break, caculate TX vref
8894 04:47:37.228998 TX Vref=16, minBit 0, minWin=22, winSum=386
8895 04:47:37.232346 TX Vref=18, minBit 0, minWin=23, winSum=397
8896 04:47:37.235706 TX Vref=20, minBit 0, minWin=24, winSum=407
8897 04:47:37.238865 TX Vref=22, minBit 0, minWin=25, winSum=412
8898 04:47:37.242331 TX Vref=24, minBit 0, minWin=25, winSum=420
8899 04:47:37.248706 TX Vref=26, minBit 0, minWin=26, winSum=431
8900 04:47:37.252301 TX Vref=28, minBit 5, minWin=25, winSum=429
8901 04:47:37.255634 TX Vref=30, minBit 1, minWin=24, winSum=421
8902 04:47:37.258910 TX Vref=32, minBit 1, minWin=24, winSum=418
8903 04:47:37.262005 TX Vref=34, minBit 0, minWin=23, winSum=404
8904 04:47:37.268633 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 26
8905 04:47:37.269111
8906 04:47:37.272041 Final TX Range 0 Vref 26
8907 04:47:37.272464
8908 04:47:37.272799 ==
8909 04:47:37.275390 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 04:47:37.278706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 04:47:37.279131 ==
8912 04:47:37.279551
8913 04:47:37.280045
8914 04:47:37.282094 TX Vref Scan disable
8915 04:47:37.288565 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8916 04:47:37.288989 == TX Byte 0 ==
8917 04:47:37.292153 u2DelayCellOfst[0]=18 cells (5 PI)
8918 04:47:37.295399 u2DelayCellOfst[1]=15 cells (4 PI)
8919 04:47:37.298432 u2DelayCellOfst[2]=0 cells (0 PI)
8920 04:47:37.301953 u2DelayCellOfst[3]=7 cells (2 PI)
8921 04:47:37.305200 u2DelayCellOfst[4]=7 cells (2 PI)
8922 04:47:37.308289 u2DelayCellOfst[5]=22 cells (6 PI)
8923 04:47:37.311590 u2DelayCellOfst[6]=22 cells (6 PI)
8924 04:47:37.315009 u2DelayCellOfst[7]=7 cells (2 PI)
8925 04:47:37.318215 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8926 04:47:37.321779 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8927 04:47:37.325018 == TX Byte 1 ==
8928 04:47:37.325663 u2DelayCellOfst[8]=0 cells (0 PI)
8929 04:47:37.328231 u2DelayCellOfst[9]=7 cells (2 PI)
8930 04:47:37.331647 u2DelayCellOfst[10]=15 cells (4 PI)
8931 04:47:37.335065 u2DelayCellOfst[11]=7 cells (2 PI)
8932 04:47:37.337982 u2DelayCellOfst[12]=15 cells (4 PI)
8933 04:47:37.341503 u2DelayCellOfst[13]=18 cells (5 PI)
8934 04:47:37.344901 u2DelayCellOfst[14]=22 cells (6 PI)
8935 04:47:37.348099 u2DelayCellOfst[15]=18 cells (5 PI)
8936 04:47:37.351530 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8937 04:47:37.357918 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8938 04:47:37.358365 DramC Write-DBI on
8939 04:47:37.358720 ==
8940 04:47:37.361399 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 04:47:37.367793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 04:47:37.368215 ==
8943 04:47:37.368567
8944 04:47:37.368881
8945 04:47:37.369252 TX Vref Scan disable
8946 04:47:37.371656 == TX Byte 0 ==
8947 04:47:37.374980 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8948 04:47:37.378273 == TX Byte 1 ==
8949 04:47:37.381584 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8950 04:47:37.385130 DramC Write-DBI off
8951 04:47:37.385624
8952 04:47:37.386074 [DATLAT]
8953 04:47:37.386399 Freq=1600, CH1 RK1
8954 04:47:37.386707
8955 04:47:37.388053 DATLAT Default: 0xf
8956 04:47:37.388504 0, 0xFFFF, sum = 0
8957 04:47:37.391633 1, 0xFFFF, sum = 0
8958 04:47:37.392085 2, 0xFFFF, sum = 0
8959 04:47:37.394870 3, 0xFFFF, sum = 0
8960 04:47:37.398043 4, 0xFFFF, sum = 0
8961 04:47:37.398473 5, 0xFFFF, sum = 0
8962 04:47:37.401321 6, 0xFFFF, sum = 0
8963 04:47:37.401797 7, 0xFFFF, sum = 0
8964 04:47:37.404699 8, 0xFFFF, sum = 0
8965 04:47:37.405123 9, 0xFFFF, sum = 0
8966 04:47:37.408156 10, 0xFFFF, sum = 0
8967 04:47:37.408586 11, 0xFFFF, sum = 0
8968 04:47:37.411748 12, 0xFFFF, sum = 0
8969 04:47:37.412179 13, 0x8FFF, sum = 0
8970 04:47:37.414911 14, 0x0, sum = 1
8971 04:47:37.415337 15, 0x0, sum = 2
8972 04:47:37.418045 16, 0x0, sum = 3
8973 04:47:37.418540 17, 0x0, sum = 4
8974 04:47:37.421149 best_step = 15
8975 04:47:37.421231
8976 04:47:37.421295 ==
8977 04:47:37.424273 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 04:47:37.427574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 04:47:37.427657 ==
8980 04:47:37.430919 RX Vref Scan: 0
8981 04:47:37.431001
8982 04:47:37.431066 RX Vref 0 -> 0, step: 1
8983 04:47:37.431127
8984 04:47:37.434091 RX Delay 11 -> 252, step: 4
8985 04:47:37.437508 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8986 04:47:37.444092 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8987 04:47:37.447657 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8988 04:47:37.450590 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8989 04:47:37.453995 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8990 04:47:37.457579 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8991 04:47:37.464013 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8992 04:47:37.467392 iDelay=195, Bit 7, Center 122 (67 ~ 178) 112
8993 04:47:37.470574 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
8994 04:47:37.473882 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8995 04:47:37.477144 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8996 04:47:37.483633 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
8997 04:47:37.487002 iDelay=195, Bit 12, Center 134 (79 ~ 190) 112
8998 04:47:37.490438 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8999 04:47:37.493726 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9000 04:47:37.500161 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9001 04:47:37.500267 ==
9002 04:47:37.503682 Dram Type= 6, Freq= 0, CH_1, rank 1
9003 04:47:37.506877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9004 04:47:37.506946 ==
9005 04:47:37.507007 DQS Delay:
9006 04:47:37.510447 DQS0 = 0, DQS1 = 0
9007 04:47:37.510535 DQM Delay:
9008 04:47:37.513815 DQM0 = 127, DQM1 = 124
9009 04:47:37.513905 DQ Delay:
9010 04:47:37.516999 DQ0 =132, DQ1 =126, DQ2 =116, DQ3 =124
9011 04:47:37.520370 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =122
9012 04:47:37.523925 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =118
9013 04:47:37.526912 DQ12 =134, DQ13 =132, DQ14 =130, DQ15 =134
9014 04:47:37.527097
9015 04:47:37.527193
9016 04:47:37.530750
9017 04:47:37.530943 [DramC_TX_OE_Calibration] TA2
9018 04:47:37.533869 Original DQ_B0 (3 6) =30, OEN = 27
9019 04:47:37.537332 Original DQ_B1 (3 6) =30, OEN = 27
9020 04:47:37.540404 24, 0x0, End_B0=24 End_B1=24
9021 04:47:37.543621 25, 0x0, End_B0=25 End_B1=25
9022 04:47:37.547350 26, 0x0, End_B0=26 End_B1=26
9023 04:47:37.547604 27, 0x0, End_B0=27 End_B1=27
9024 04:47:37.550359 28, 0x0, End_B0=28 End_B1=28
9025 04:47:37.553674 29, 0x0, End_B0=29 End_B1=29
9026 04:47:37.557076 30, 0x0, End_B0=30 End_B1=30
9027 04:47:37.560102 31, 0x4141, End_B0=30 End_B1=30
9028 04:47:37.560344 Byte0 end_step=30 best_step=27
9029 04:47:37.563657 Byte1 end_step=30 best_step=27
9030 04:47:37.566858 Byte0 TX OE(2T, 0.5T) = (3, 3)
9031 04:47:37.570453 Byte1 TX OE(2T, 0.5T) = (3, 3)
9032 04:47:37.570858
9033 04:47:37.571191
9034 04:47:37.577017 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9035 04:47:37.580128 CH1 RK1: MR19=303, MR18=E1A
9036 04:47:37.587427 CH1_RK1: MR19=0x303, MR18=0xE1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9037 04:47:37.590176 [RxdqsGatingPostProcess] freq 1600
9038 04:47:37.596661 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9039 04:47:37.600124 best DQS0 dly(2T, 0.5T) = (1, 1)
9040 04:47:37.600553 best DQS1 dly(2T, 0.5T) = (1, 1)
9041 04:47:37.603580 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9042 04:47:37.606971 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9043 04:47:37.610070 best DQS0 dly(2T, 0.5T) = (1, 1)
9044 04:47:37.613459 best DQS1 dly(2T, 0.5T) = (1, 1)
9045 04:47:37.616791 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9046 04:47:37.620156 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9047 04:47:37.623358 Pre-setting of DQS Precalculation
9048 04:47:37.626690 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9049 04:47:37.636922 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9050 04:47:37.643488 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9051 04:47:37.644022
9052 04:47:37.644467
9053 04:47:37.647057 [Calibration Summary] 3200 Mbps
9054 04:47:37.647600 CH 0, Rank 0
9055 04:47:37.649830 SW Impedance : PASS
9056 04:47:37.650258 DUTY Scan : NO K
9057 04:47:37.653016 ZQ Calibration : PASS
9058 04:47:37.656322 Jitter Meter : NO K
9059 04:47:37.656787 CBT Training : PASS
9060 04:47:37.659996 Write leveling : PASS
9061 04:47:37.663546 RX DQS gating : PASS
9062 04:47:37.664078 RX DQ/DQS(RDDQC) : PASS
9063 04:47:37.666417 TX DQ/DQS : PASS
9064 04:47:37.669907 RX DATLAT : PASS
9065 04:47:37.670339 RX DQ/DQS(Engine): PASS
9066 04:47:37.673392 TX OE : PASS
9067 04:47:37.673966 All Pass.
9068 04:47:37.674414
9069 04:47:37.676808 CH 0, Rank 1
9070 04:47:37.677361 SW Impedance : PASS
9071 04:47:37.679758 DUTY Scan : NO K
9072 04:47:37.683060 ZQ Calibration : PASS
9073 04:47:37.683553 Jitter Meter : NO K
9074 04:47:37.686748 CBT Training : PASS
9075 04:47:37.689793 Write leveling : PASS
9076 04:47:37.690215 RX DQS gating : PASS
9077 04:47:37.693655 RX DQ/DQS(RDDQC) : PASS
9078 04:47:37.696056 TX DQ/DQS : PASS
9079 04:47:37.696483 RX DATLAT : PASS
9080 04:47:37.699893 RX DQ/DQS(Engine): PASS
9081 04:47:37.700430 TX OE : PASS
9082 04:47:37.703152 All Pass.
9083 04:47:37.703660
9084 04:47:37.704001 CH 1, Rank 0
9085 04:47:37.706416 SW Impedance : PASS
9086 04:47:37.706855 DUTY Scan : NO K
9087 04:47:37.709402 ZQ Calibration : PASS
9088 04:47:37.713237 Jitter Meter : NO K
9089 04:47:37.713946 CBT Training : PASS
9090 04:47:37.716101 Write leveling : PASS
9091 04:47:37.719497 RX DQS gating : PASS
9092 04:47:37.719921 RX DQ/DQS(RDDQC) : PASS
9093 04:47:37.722708 TX DQ/DQS : PASS
9094 04:47:37.725850 RX DATLAT : PASS
9095 04:47:37.726276 RX DQ/DQS(Engine): PASS
9096 04:47:37.729302 TX OE : PASS
9097 04:47:37.729765 All Pass.
9098 04:47:37.730105
9099 04:47:37.733216 CH 1, Rank 1
9100 04:47:37.733803 SW Impedance : PASS
9101 04:47:37.736026 DUTY Scan : NO K
9102 04:47:37.739650 ZQ Calibration : PASS
9103 04:47:37.740165 Jitter Meter : NO K
9104 04:47:37.743294 CBT Training : PASS
9105 04:47:37.746056 Write leveling : PASS
9106 04:47:37.746483 RX DQS gating : PASS
9107 04:47:37.749443 RX DQ/DQS(RDDQC) : PASS
9108 04:47:37.753032 TX DQ/DQS : PASS
9109 04:47:37.753622 RX DATLAT : PASS
9110 04:47:37.756119 RX DQ/DQS(Engine): PASS
9111 04:47:37.756556 TX OE : PASS
9112 04:47:37.759812 All Pass.
9113 04:47:37.760336
9114 04:47:37.760678 DramC Write-DBI on
9115 04:47:37.762572 PER_BANK_REFRESH: Hybrid Mode
9116 04:47:37.766070 TX_TRACKING: ON
9117 04:47:37.772581 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9118 04:47:37.782654 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9119 04:47:37.789202 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9120 04:47:37.792259 [FAST_K] Save calibration result to emmc
9121 04:47:37.795796 sync common calibartion params.
9122 04:47:37.796363 sync cbt_mode0:1, 1:1
9123 04:47:37.798931 dram_init: ddr_geometry: 2
9124 04:47:37.802279 dram_init: ddr_geometry: 2
9125 04:47:37.805904 dram_init: ddr_geometry: 2
9126 04:47:37.806341 0:dram_rank_size:100000000
9127 04:47:37.808838 1:dram_rank_size:100000000
9128 04:47:37.815542 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9129 04:47:37.815966 DFS_SHUFFLE_HW_MODE: ON
9130 04:47:37.822491 dramc_set_vcore_voltage set vcore to 725000
9131 04:47:37.822914 Read voltage for 1600, 0
9132 04:47:37.825927 Vio18 = 0
9133 04:47:37.826344 Vcore = 725000
9134 04:47:37.826678 Vdram = 0
9135 04:47:37.826991 Vddq = 0
9136 04:47:37.829075 Vmddr = 0
9137 04:47:37.829515 switch to 3200 Mbps bootup
9138 04:47:37.832116 [DramcRunTimeConfig]
9139 04:47:37.832532 PHYPLL
9140 04:47:37.835573 DPM_CONTROL_AFTERK: ON
9141 04:47:37.836098 PER_BANK_REFRESH: ON
9142 04:47:37.838887 REFRESH_OVERHEAD_REDUCTION: ON
9143 04:47:37.842423 CMD_PICG_NEW_MODE: OFF
9144 04:47:37.842841 XRTWTW_NEW_MODE: ON
9145 04:47:37.845341 XRTRTR_NEW_MODE: ON
9146 04:47:37.845740 TX_TRACKING: ON
9147 04:47:37.849044 RDSEL_TRACKING: OFF
9148 04:47:37.852301 DQS Precalculation for DVFS: ON
9149 04:47:37.852721 RX_TRACKING: OFF
9150 04:47:37.855333 HW_GATING DBG: ON
9151 04:47:37.855751 ZQCS_ENABLE_LP4: ON
9152 04:47:37.858827 RX_PICG_NEW_MODE: ON
9153 04:47:37.859244 TX_PICG_NEW_MODE: ON
9154 04:47:37.861945 ENABLE_RX_DCM_DPHY: ON
9155 04:47:37.865319 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9156 04:47:37.868637 DUMMY_READ_FOR_TRACKING: OFF
9157 04:47:37.872158 !!! SPM_CONTROL_AFTERK: OFF
9158 04:47:37.872632 !!! SPM could not control APHY
9159 04:47:37.875803 IMPEDANCE_TRACKING: ON
9160 04:47:37.876396 TEMP_SENSOR: ON
9161 04:47:37.878778 HW_SAVE_FOR_SR: OFF
9162 04:47:37.882003 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9163 04:47:37.885471 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9164 04:47:37.888737 Read ODT Tracking: ON
9165 04:47:37.889266 Refresh Rate DeBounce: ON
9166 04:47:37.891996 DFS_NO_QUEUE_FLUSH: ON
9167 04:47:37.895693 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9168 04:47:37.899021 ENABLE_DFS_RUNTIME_MRW: OFF
9169 04:47:37.899546 DDR_RESERVE_NEW_MODE: ON
9170 04:47:37.902383 MR_CBT_SWITCH_FREQ: ON
9171 04:47:37.905432 =========================
9172 04:47:37.922855 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9173 04:47:37.926258 dram_init: ddr_geometry: 2
9174 04:47:37.944512 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9175 04:47:37.948243 dram_init: dram init end (result: 0)
9176 04:47:37.954339 DRAM-K: Full calibration passed in 24585 msecs
9177 04:47:37.957564 MRC: failed to locate region type 0.
9178 04:47:37.958035 DRAM rank0 size:0x100000000,
9179 04:47:37.960928 DRAM rank1 size=0x100000000
9180 04:47:37.970923 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9181 04:47:37.977694 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9182 04:47:37.984335 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9183 04:47:37.991100 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9184 04:47:37.994392 DRAM rank0 size:0x100000000,
9185 04:47:37.997555 DRAM rank1 size=0x100000000
9186 04:47:37.997982 CBMEM:
9187 04:47:38.001078 IMD: root @ 0xfffff000 254 entries.
9188 04:47:38.004438 IMD: root @ 0xffffec00 62 entries.
9189 04:47:38.007717 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9190 04:47:38.011253 WARNING: RO_VPD is uninitialized or empty.
9191 04:47:38.017325 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9192 04:47:38.024780 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9193 04:47:38.037175 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9194 04:47:38.048790 BS: romstage times (exec / console): total (unknown) / 24042 ms
9195 04:47:38.049218
9196 04:47:38.049600
9197 04:47:38.058434 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9198 04:47:38.062041 ARM64: Exception handlers installed.
9199 04:47:38.065242 ARM64: Testing exception
9200 04:47:38.068737 ARM64: Done test exception
9201 04:47:38.069167 Enumerating buses...
9202 04:47:38.071657 Show all devs... Before device enumeration.
9203 04:47:38.075279 Root Device: enabled 1
9204 04:47:38.078742 CPU_CLUSTER: 0: enabled 1
9205 04:47:38.079165 CPU: 00: enabled 1
9206 04:47:38.081988 Compare with tree...
9207 04:47:38.082545 Root Device: enabled 1
9208 04:47:38.085177 CPU_CLUSTER: 0: enabled 1
9209 04:47:38.088597 CPU: 00: enabled 1
9210 04:47:38.089016 Root Device scanning...
9211 04:47:38.091791 scan_static_bus for Root Device
9212 04:47:38.095270 CPU_CLUSTER: 0 enabled
9213 04:47:38.098515 scan_static_bus for Root Device done
9214 04:47:38.101761 scan_bus: bus Root Device finished in 8 msecs
9215 04:47:38.102182 done
9216 04:47:38.108557 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9217 04:47:38.111818 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9218 04:47:38.117998 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9219 04:47:38.121403 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9220 04:47:38.124755 Allocating resources...
9221 04:47:38.128187 Reading resources...
9222 04:47:38.131431 Root Device read_resources bus 0 link: 0
9223 04:47:38.134538 DRAM rank0 size:0x100000000,
9224 04:47:38.134976 DRAM rank1 size=0x100000000
9225 04:47:38.138009 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9226 04:47:38.141059 CPU: 00 missing read_resources
9227 04:47:38.147692 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9228 04:47:38.151012 Root Device read_resources bus 0 link: 0 done
9229 04:47:38.151434 Done reading resources.
9230 04:47:38.157922 Show resources in subtree (Root Device)...After reading.
9231 04:47:38.161250 Root Device child on link 0 CPU_CLUSTER: 0
9232 04:47:38.164473 CPU_CLUSTER: 0 child on link 0 CPU: 00
9233 04:47:38.174525 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9234 04:47:38.174949 CPU: 00
9235 04:47:38.177920 Root Device assign_resources, bus 0 link: 0
9236 04:47:38.181321 CPU_CLUSTER: 0 missing set_resources
9237 04:47:38.187896 Root Device assign_resources, bus 0 link: 0 done
9238 04:47:38.188321 Done setting resources.
9239 04:47:38.194467 Show resources in subtree (Root Device)...After assigning values.
9240 04:47:38.197652 Root Device child on link 0 CPU_CLUSTER: 0
9241 04:47:38.201320 CPU_CLUSTER: 0 child on link 0 CPU: 00
9242 04:47:38.211440 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9243 04:47:38.211972 CPU: 00
9244 04:47:38.214726 Done allocating resources.
9245 04:47:38.218153 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9246 04:47:38.221589 Enabling resources...
9247 04:47:38.222112 done.
9248 04:47:38.227613 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9249 04:47:38.228036 Initializing devices...
9250 04:47:38.230950 Root Device init
9251 04:47:38.231367 init hardware done!
9252 04:47:38.234196 0x00000018: ctrlr->caps
9253 04:47:38.237696 52.000 MHz: ctrlr->f_max
9254 04:47:38.238140 0.400 MHz: ctrlr->f_min
9255 04:47:38.241128 0x40ff8080: ctrlr->voltages
9256 04:47:38.241707 sclk: 390625
9257 04:47:38.244329 Bus Width = 1
9258 04:47:38.244851 sclk: 390625
9259 04:47:38.247639 Bus Width = 1
9260 04:47:38.248058 Early init status = 3
9261 04:47:38.254264 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9262 04:47:38.257562 in-header: 03 fc 00 00 01 00 00 00
9263 04:47:38.260501 in-data: 00
9264 04:47:38.264040 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9265 04:47:38.269048 in-header: 03 fd 00 00 00 00 00 00
9266 04:47:38.272483 in-data:
9267 04:47:38.276010 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9268 04:47:38.280327 in-header: 03 fc 00 00 01 00 00 00
9269 04:47:38.283724 in-data: 00
9270 04:47:38.286528 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9271 04:47:38.292324 in-header: 03 fd 00 00 00 00 00 00
9272 04:47:38.295596 in-data:
9273 04:47:38.298837 [SSUSB] Setting up USB HOST controller...
9274 04:47:38.302189 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9275 04:47:38.305207 [SSUSB] phy power-on done.
9276 04:47:38.308690 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9277 04:47:38.315549 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9278 04:47:38.319181 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9279 04:47:38.324987 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9280 04:47:38.331814 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9281 04:47:38.338648 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9282 04:47:38.345068 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9283 04:47:38.351701 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9284 04:47:38.355055 SPM: binary array size = 0x9dc
9285 04:47:38.358433 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9286 04:47:38.364979 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9287 04:47:38.371667 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9288 04:47:38.375144 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9289 04:47:38.381265 configure_display: Starting display init
9290 04:47:38.415531 anx7625_power_on_init: Init interface.
9291 04:47:38.419205 anx7625_disable_pd_protocol: Disabled PD feature.
9292 04:47:38.422449 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9293 04:47:38.450274 anx7625_start_dp_work: Secure OCM version=00
9294 04:47:38.453640 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9295 04:47:38.468048 sp_tx_get_edid_block: EDID Block = 1
9296 04:47:38.570601 Extracted contents:
9297 04:47:38.573636 header: 00 ff ff ff ff ff ff 00
9298 04:47:38.577002 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9299 04:47:38.580227 version: 01 04
9300 04:47:38.583516 basic params: 95 1f 11 78 0a
9301 04:47:38.586998 chroma info: 76 90 94 55 54 90 27 21 50 54
9302 04:47:38.590323 established: 00 00 00
9303 04:47:38.597009 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9304 04:47:38.603566 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9305 04:47:38.607141 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9306 04:47:38.613358 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9307 04:47:38.620119 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9308 04:47:38.623279 extensions: 00
9309 04:47:38.623699 checksum: fb
9310 04:47:38.624036
9311 04:47:38.629692 Manufacturer: IVO Model 57d Serial Number 0
9312 04:47:38.630115 Made week 0 of 2020
9313 04:47:38.633288 EDID version: 1.4
9314 04:47:38.633858 Digital display
9315 04:47:38.636191 6 bits per primary color channel
9316 04:47:38.639351 DisplayPort interface
9317 04:47:38.639771 Maximum image size: 31 cm x 17 cm
9318 04:47:38.643358 Gamma: 220%
9319 04:47:38.643890 Check DPMS levels
9320 04:47:38.649690 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9321 04:47:38.653125 First detailed timing is preferred timing
9322 04:47:38.653589 Established timings supported:
9323 04:47:38.656418 Standard timings supported:
9324 04:47:38.659517 Detailed timings
9325 04:47:38.662991 Hex of detail: 383680a07038204018303c0035ae10000019
9326 04:47:38.669509 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9327 04:47:38.672957 0780 0798 07c8 0820 hborder 0
9328 04:47:38.676072 0438 043b 0447 0458 vborder 0
9329 04:47:38.679500 -hsync -vsync
9330 04:47:38.679920 Did detailed timing
9331 04:47:38.685954 Hex of detail: 000000000000000000000000000000000000
9332 04:47:38.689540 Manufacturer-specified data, tag 0
9333 04:47:38.692971 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9334 04:47:38.695917 ASCII string: InfoVision
9335 04:47:38.699625 Hex of detail: 000000fe00523134304e574635205248200a
9336 04:47:38.702580 ASCII string: R140NWF5 RH
9337 04:47:38.702998 Checksum
9338 04:47:38.706013 Checksum: 0xfb (valid)
9339 04:47:38.709176 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9340 04:47:38.712508 DSI data_rate: 832800000 bps
9341 04:47:38.718842 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9342 04:47:38.722378 anx7625_parse_edid: pixelclock(138800).
9343 04:47:38.725545 hactive(1920), hsync(48), hfp(24), hbp(88)
9344 04:47:38.728788 vactive(1080), vsync(12), vfp(3), vbp(17)
9345 04:47:38.732265 anx7625_dsi_config: config dsi.
9346 04:47:38.738855 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9347 04:47:38.752053 anx7625_dsi_config: success to config DSI
9348 04:47:38.755446 anx7625_dp_start: MIPI phy setup OK.
9349 04:47:38.758875 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9350 04:47:38.762062 mtk_ddp_mode_set invalid vrefresh 60
9351 04:47:38.765467 main_disp_path_setup
9352 04:47:38.765684 ovl_layer_smi_id_en
9353 04:47:38.768995 ovl_layer_smi_id_en
9354 04:47:38.769237 ccorr_config
9355 04:47:38.769428 aal_config
9356 04:47:38.772066 gamma_config
9357 04:47:38.772306 postmask_config
9358 04:47:38.775658 dither_config
9359 04:47:38.779321 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9360 04:47:38.785762 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9361 04:47:38.788946 Root Device init finished in 555 msecs
9362 04:47:38.792410 CPU_CLUSTER: 0 init
9363 04:47:38.798857 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9364 04:47:38.802279 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9365 04:47:38.805576 APU_MBOX 0x190000b0 = 0x10001
9366 04:47:38.809165 APU_MBOX 0x190001b0 = 0x10001
9367 04:47:38.812597 APU_MBOX 0x190005b0 = 0x10001
9368 04:47:38.815730 APU_MBOX 0x190006b0 = 0x10001
9369 04:47:38.819204 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9370 04:47:38.831892 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9371 04:47:38.844040 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9372 04:47:38.850566 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9373 04:47:38.862329 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9374 04:47:38.871249 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9375 04:47:38.874887 CPU_CLUSTER: 0 init finished in 81 msecs
9376 04:47:38.877993 Devices initialized
9377 04:47:38.881548 Show all devs... After init.
9378 04:47:38.882076 Root Device: enabled 1
9379 04:47:38.884991 CPU_CLUSTER: 0: enabled 1
9380 04:47:38.887849 CPU: 00: enabled 1
9381 04:47:38.891395 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9382 04:47:38.894827 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9383 04:47:38.898016 ELOG: NV offset 0x57f000 size 0x1000
9384 04:47:38.904593 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9385 04:47:38.910927 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9386 04:47:38.914373 ELOG: Event(17) added with size 13 at 2024-02-04 04:47:38 UTC
9387 04:47:38.920656 out: cmd=0x121: 03 db 21 01 00 00 00 00
9388 04:47:38.924572 in-header: 03 4f 00 00 2c 00 00 00
9389 04:47:38.934434 in-data: 0f 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9390 04:47:38.940937 ELOG: Event(A1) added with size 10 at 2024-02-04 04:47:38 UTC
9391 04:47:38.947389 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9392 04:47:38.954117 ELOG: Event(A0) added with size 9 at 2024-02-04 04:47:38 UTC
9393 04:47:38.957105 elog_add_boot_reason: Logged dev mode boot
9394 04:47:38.963779 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9395 04:47:38.964247 Finalize devices...
9396 04:47:38.967561 Devices finalized
9397 04:47:38.970458 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9398 04:47:38.973649 Writing coreboot table at 0xffe64000
9399 04:47:38.977257 0. 000000000010a000-0000000000113fff: RAMSTAGE
9400 04:47:38.980890 1. 0000000040000000-00000000400fffff: RAM
9401 04:47:38.987240 2. 0000000040100000-000000004032afff: RAMSTAGE
9402 04:47:38.990432 3. 000000004032b000-00000000545fffff: RAM
9403 04:47:38.993836 4. 0000000054600000-000000005465ffff: BL31
9404 04:47:38.997149 5. 0000000054660000-00000000ffe63fff: RAM
9405 04:47:39.003425 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9406 04:47:39.006959 7. 0000000100000000-000000023fffffff: RAM
9407 04:47:39.010437 Passing 5 GPIOs to payload:
9408 04:47:39.014097 NAME | PORT | POLARITY | VALUE
9409 04:47:39.020491 EC in RW | 0x000000aa | low | undefined
9410 04:47:39.023878 EC interrupt | 0x00000005 | low | undefined
9411 04:47:39.027269 TPM interrupt | 0x000000ab | high | undefined
9412 04:47:39.033749 SD card detect | 0x00000011 | high | undefined
9413 04:47:39.037262 speaker enable | 0x00000093 | high | undefined
9414 04:47:39.040600 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9415 04:47:39.043813 in-header: 03 f9 00 00 02 00 00 00
9416 04:47:39.046890 in-data: 02 00
9417 04:47:39.050153 ADC[4]: Raw value=895191 ID=7
9418 04:47:39.050617 ADC[3]: Raw value=212700 ID=1
9419 04:47:39.053666 RAM Code: 0x71
9420 04:47:39.056765 ADC[6]: Raw value=74722 ID=0
9421 04:47:39.057188 ADC[5]: Raw value=211960 ID=1
9422 04:47:39.059811 SKU Code: 0x1
9423 04:47:39.066678 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 81d2
9424 04:47:39.067106 coreboot table: 964 bytes.
9425 04:47:39.069778 IMD ROOT 0. 0xfffff000 0x00001000
9426 04:47:39.073044 IMD SMALL 1. 0xffffe000 0x00001000
9427 04:47:39.076834 RO MCACHE 2. 0xffffc000 0x00001104
9428 04:47:39.079985 CONSOLE 3. 0xfff7c000 0x00080000
9429 04:47:39.083534 FMAP 4. 0xfff7b000 0x00000452
9430 04:47:39.086389 TIME STAMP 5. 0xfff7a000 0x00000910
9431 04:47:39.089846 VBOOT WORK 6. 0xfff66000 0x00014000
9432 04:47:39.093185 RAMOOPS 7. 0xffe66000 0x00100000
9433 04:47:39.096648 COREBOOT 8. 0xffe64000 0x00002000
9434 04:47:39.099905 IMD small region:
9435 04:47:39.102877 IMD ROOT 0. 0xffffec00 0x00000400
9436 04:47:39.106357 VPD 1. 0xffffeb80 0x0000006c
9437 04:47:39.109617 MMC STATUS 2. 0xffffeb60 0x00000004
9438 04:47:39.113098 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9439 04:47:39.116340 Probing TPM: done!
9440 04:47:39.119790 Connected to device vid:did:rid of 1ae0:0028:00
9441 04:47:39.130698 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9442 04:47:39.134098 Initialized TPM device CR50 revision 0
9443 04:47:39.137358 Checking cr50 for pending updates
9444 04:47:39.141915 Reading cr50 TPM mode
9445 04:47:39.150078 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9446 04:47:39.156597 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9447 04:47:39.196614 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9448 04:47:39.200155 Checking segment from ROM address 0x40100000
9449 04:47:39.203145 Checking segment from ROM address 0x4010001c
9450 04:47:39.210119 Loading segment from ROM address 0x40100000
9451 04:47:39.210547 code (compression=0)
9452 04:47:39.220213 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9453 04:47:39.226667 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9454 04:47:39.227102 it's not compressed!
9455 04:47:39.232998 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9456 04:47:39.236465 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9457 04:47:39.256950 Loading segment from ROM address 0x4010001c
9458 04:47:39.257459 Entry Point 0x80000000
9459 04:47:39.260351 Loaded segments
9460 04:47:39.263391 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9461 04:47:39.270439 Jumping to boot code at 0x80000000(0xffe64000)
9462 04:47:39.277015 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9463 04:47:39.283914 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9464 04:47:39.291804 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9465 04:47:39.294896 Checking segment from ROM address 0x40100000
9466 04:47:39.298180 Checking segment from ROM address 0x4010001c
9467 04:47:39.304833 Loading segment from ROM address 0x40100000
9468 04:47:39.305260 code (compression=1)
9469 04:47:39.311666 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9470 04:47:39.321315 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9471 04:47:39.321915 using LZMA
9472 04:47:39.329971 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9473 04:47:39.336926 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9474 04:47:39.340294 Loading segment from ROM address 0x4010001c
9475 04:47:39.340819 Entry Point 0x54601000
9476 04:47:39.343155 Loaded segments
9477 04:47:39.346772 NOTICE: MT8192 bl31_setup
9478 04:47:39.353865 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9479 04:47:39.357005 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9480 04:47:39.360271 WARNING: region 0:
9481 04:47:39.363793 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 04:47:39.364326 WARNING: region 1:
9483 04:47:39.370258 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9484 04:47:39.373524 WARNING: region 2:
9485 04:47:39.377145 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9486 04:47:39.380228 WARNING: region 3:
9487 04:47:39.383589 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9488 04:47:39.386666 WARNING: region 4:
9489 04:47:39.393610 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9490 04:47:39.394037 WARNING: region 5:
9491 04:47:39.397026 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 04:47:39.400187 WARNING: region 6:
9493 04:47:39.403584 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 04:47:39.406835 WARNING: region 7:
9495 04:47:39.410211 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 04:47:39.417414 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9497 04:47:39.420366 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9498 04:47:39.423829 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9499 04:47:39.430016 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9500 04:47:39.433610 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9501 04:47:39.437044 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9502 04:47:39.443531 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9503 04:47:39.447209 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9504 04:47:39.454240 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9505 04:47:39.457099 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9506 04:47:39.460454 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9507 04:47:39.466864 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9508 04:47:39.470180 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9509 04:47:39.473835 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9510 04:47:39.480516 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9511 04:47:39.483898 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9512 04:47:39.487024 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9513 04:47:39.493535 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9514 04:47:39.497062 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9515 04:47:39.503634 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9516 04:47:39.506997 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9517 04:47:39.510435 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9518 04:47:39.517338 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9519 04:47:39.520284 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9520 04:47:39.527520 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9521 04:47:39.530603 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9522 04:47:39.534021 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9523 04:47:39.540510 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9524 04:47:39.543654 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9525 04:47:39.546855 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9526 04:47:39.553655 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9527 04:47:39.557081 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9528 04:47:39.560292 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9529 04:47:39.567034 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9530 04:47:39.570522 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9531 04:47:39.573918 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9532 04:47:39.576983 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9533 04:47:39.583532 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9534 04:47:39.587157 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9535 04:47:39.590413 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9536 04:47:39.593837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9537 04:47:39.600307 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9538 04:47:39.603606 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9539 04:47:39.606960 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9540 04:47:39.610169 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9541 04:47:39.617017 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9542 04:47:39.620505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9543 04:47:39.623439 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9544 04:47:39.630603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9545 04:47:39.633751 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9546 04:47:39.640316 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9547 04:47:39.643529 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9548 04:47:39.647005 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9549 04:47:39.653606 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9550 04:47:39.656939 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9551 04:47:39.663563 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9552 04:47:39.666919 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9553 04:47:39.670451 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9554 04:47:39.677216 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9555 04:47:39.680623 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9556 04:47:39.687195 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9557 04:47:39.690711 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9558 04:47:39.697043 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9559 04:47:39.700400 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9560 04:47:39.707144 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9561 04:47:39.710144 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9562 04:47:39.713634 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9563 04:47:39.720316 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9564 04:47:39.723614 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9565 04:47:39.730531 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9566 04:47:39.733435 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9567 04:47:39.740299 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9568 04:47:39.743590 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9569 04:47:39.747102 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9570 04:47:39.753652 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9571 04:47:39.757003 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9572 04:47:39.763960 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9573 04:47:39.766913 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9574 04:47:39.773563 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9575 04:47:39.777037 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9576 04:47:39.780235 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9577 04:47:39.786896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9578 04:47:39.790182 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9579 04:47:39.797238 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9580 04:47:39.800492 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9581 04:47:39.807034 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9582 04:47:39.810560 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9583 04:47:39.813797 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9584 04:47:39.820458 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9585 04:47:39.823791 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9586 04:47:39.830285 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9587 04:47:39.833559 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9588 04:47:39.840308 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9589 04:47:39.843711 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9590 04:47:39.846883 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9591 04:47:39.853593 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9592 04:47:39.857242 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9593 04:47:39.860192 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9594 04:47:39.866990 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9595 04:47:39.870175 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9596 04:47:39.873827 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9597 04:47:39.880239 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9598 04:47:39.883483 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9599 04:47:39.886541 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9600 04:47:39.893359 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9601 04:47:39.896822 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9602 04:47:39.903096 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9603 04:47:39.906537 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9604 04:47:39.909841 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9605 04:47:39.916805 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9606 04:47:39.920176 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9607 04:47:39.926928 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9608 04:47:39.929887 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9609 04:47:39.933282 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9610 04:47:39.939859 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9611 04:47:39.942942 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9612 04:47:39.946585 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9613 04:47:39.953348 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9614 04:47:39.956469 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9615 04:47:39.959858 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9616 04:47:39.966543 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9617 04:47:39.969797 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9618 04:47:39.973206 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9619 04:47:39.976611 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9620 04:47:39.983387 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9621 04:47:39.986704 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9622 04:47:39.990088 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9623 04:47:39.996635 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9624 04:47:40.000105 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9625 04:47:40.006864 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9626 04:47:40.010122 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9627 04:47:40.013587 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9628 04:47:40.020153 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9629 04:47:40.023573 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9630 04:47:40.029994 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9631 04:47:40.033204 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9632 04:47:40.036698 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9633 04:47:40.043519 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9634 04:47:40.046918 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9635 04:47:40.049983 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9636 04:47:40.056677 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9637 04:47:40.060164 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9638 04:47:40.066992 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9639 04:47:40.069855 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9640 04:47:40.073310 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9641 04:47:40.079969 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9642 04:47:40.083035 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9643 04:47:40.089743 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9644 04:47:40.093194 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9645 04:47:40.096581 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9646 04:47:40.103160 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9647 04:47:40.106492 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9648 04:47:40.109723 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9649 04:47:40.116384 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9650 04:47:40.119795 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9651 04:47:40.126047 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9652 04:47:40.129436 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9653 04:47:40.132905 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9654 04:47:40.140009 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9655 04:47:40.143223 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9656 04:47:40.150004 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9657 04:47:40.153114 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9658 04:47:40.156538 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9659 04:47:40.162874 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9660 04:47:40.166482 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9661 04:47:40.173335 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9662 04:47:40.176452 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9663 04:47:40.179691 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9664 04:47:40.186390 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9665 04:47:40.189573 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9666 04:47:40.196023 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9667 04:47:40.199251 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9668 04:47:40.202881 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9669 04:47:40.209535 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9670 04:47:40.212854 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9671 04:47:40.219174 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9672 04:47:40.222615 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9673 04:47:40.225931 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9674 04:47:40.232480 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9675 04:47:40.235983 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9676 04:47:40.239047 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9677 04:47:40.245784 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9678 04:47:40.249329 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9679 04:47:40.255911 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9680 04:47:40.259166 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9681 04:47:40.262397 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9682 04:47:40.269251 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9683 04:47:40.272458 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9684 04:47:40.279423 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9685 04:47:40.282533 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9686 04:47:40.285885 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9687 04:47:40.292452 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9688 04:47:40.295698 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9689 04:47:40.302458 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9690 04:47:40.305595 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9691 04:47:40.312293 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9692 04:47:40.315554 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9693 04:47:40.318761 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9694 04:47:40.325413 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9695 04:47:40.328887 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9696 04:47:40.335568 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9697 04:47:40.338772 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9698 04:47:40.342323 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9699 04:47:40.348806 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9700 04:47:40.352376 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9701 04:47:40.358815 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9702 04:47:40.362003 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9703 04:47:40.368984 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9704 04:47:40.372197 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9705 04:47:40.375386 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9706 04:47:40.382127 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9707 04:47:40.385597 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9708 04:47:40.392132 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9709 04:47:40.395287 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9710 04:47:40.398555 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9711 04:47:40.405180 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9712 04:47:40.409013 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9713 04:47:40.415245 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9714 04:47:40.418794 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9715 04:47:40.425405 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9716 04:47:40.429061 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9717 04:47:40.432071 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9718 04:47:40.438458 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9719 04:47:40.441502 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9720 04:47:40.447987 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9721 04:47:40.451113 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9722 04:47:40.458123 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9723 04:47:40.461597 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9724 04:47:40.464790 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9725 04:47:40.471252 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9726 04:47:40.474717 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9727 04:47:40.478337 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9728 04:47:40.481653 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9729 04:47:40.484856 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9730 04:47:40.491420 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9731 04:47:40.494880 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9732 04:47:40.501277 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9733 04:47:40.504826 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9734 04:47:40.508140 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9735 04:47:40.515140 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9736 04:47:40.518196 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9737 04:47:40.522030 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9738 04:47:40.528651 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9739 04:47:40.531562 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9740 04:47:40.535029 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9741 04:47:40.541713 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9742 04:47:40.544806 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9743 04:47:40.551752 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9744 04:47:40.554707 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9745 04:47:40.558435 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9746 04:47:40.564873 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9747 04:47:40.567609 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9748 04:47:40.574453 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9749 04:47:40.577758 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9750 04:47:40.581332 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9751 04:47:40.587776 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9752 04:47:40.591224 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9753 04:47:40.594348 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9754 04:47:40.600717 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9755 04:47:40.603954 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9756 04:47:40.607265 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9757 04:47:40.614069 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9758 04:47:40.617340 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9759 04:47:40.620833 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9760 04:47:40.627527 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9761 04:47:40.630618 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9762 04:47:40.637686 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9763 04:47:40.640852 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9764 04:47:40.644241 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9765 04:47:40.647736 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9766 04:47:40.654125 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9767 04:47:40.656913 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9768 04:47:40.660407 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9769 04:47:40.663636 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9770 04:47:40.670804 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9771 04:47:40.673832 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9772 04:47:40.677293 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9773 04:47:40.680659 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9774 04:47:40.687209 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9775 04:47:40.690258 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9776 04:47:40.693585 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9777 04:47:40.700760 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9778 04:47:40.703728 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9779 04:47:40.707114 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9780 04:47:40.713702 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9781 04:47:40.717110 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9782 04:47:40.723798 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9783 04:47:40.726397 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9784 04:47:40.733192 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9785 04:47:40.736625 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9786 04:47:40.740154 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9787 04:47:40.746298 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9788 04:47:40.749991 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9789 04:47:40.756534 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9790 04:47:40.759942 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9791 04:47:40.763349 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9792 04:47:40.770086 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9793 04:47:40.773105 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9794 04:47:40.779641 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9795 04:47:40.783107 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9796 04:47:40.789325 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9797 04:47:40.792414 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9798 04:47:40.796076 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9799 04:47:40.802542 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9800 04:47:40.805827 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9801 04:47:40.812898 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9802 04:47:40.815899 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9803 04:47:40.818818 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9804 04:47:40.826064 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9805 04:47:40.829116 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9806 04:47:40.835545 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9807 04:47:40.839005 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9808 04:47:40.845679 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9809 04:47:40.849046 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9810 04:47:40.852382 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9811 04:47:40.858933 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9812 04:47:40.861875 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9813 04:47:40.868598 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9814 04:47:40.871769 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9815 04:47:40.875223 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9816 04:47:40.881468 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9817 04:47:40.885021 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9818 04:47:40.891572 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9819 04:47:40.894885 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9820 04:47:40.898165 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9821 04:47:40.905083 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9822 04:47:40.908556 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9823 04:47:40.914875 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9824 04:47:40.918224 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9825 04:47:40.921848 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9826 04:47:40.928920 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9827 04:47:40.931795 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9828 04:47:40.938717 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9829 04:47:40.941716 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9830 04:47:40.948583 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9831 04:47:40.951862 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9832 04:47:40.955278 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9833 04:47:40.961444 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9834 04:47:40.964852 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9835 04:47:40.971501 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9836 04:47:40.975032 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9837 04:47:40.978058 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9838 04:47:40.984626 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9839 04:47:40.987964 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9840 04:47:40.994598 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9841 04:47:40.997967 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9842 04:47:41.001134 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9843 04:47:41.007973 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9844 04:47:41.011218 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9845 04:47:41.018040 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9846 04:47:41.020942 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9847 04:47:41.027832 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9848 04:47:41.031361 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9849 04:47:41.034298 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9850 04:47:41.040672 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9851 04:47:41.044456 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9852 04:47:41.051168 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9853 04:47:41.054419 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9854 04:47:41.060717 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9855 04:47:41.064319 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9856 04:47:41.067479 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9857 04:47:41.074381 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9858 04:47:41.077400 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9859 04:47:41.084526 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9860 04:47:41.087661 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9861 04:47:41.094359 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9862 04:47:41.097294 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9863 04:47:41.100727 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9864 04:47:41.107568 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9865 04:47:41.110649 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9866 04:47:41.117323 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9867 04:47:41.120269 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9868 04:47:41.127244 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9869 04:47:41.130250 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9870 04:47:41.137173 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9871 04:47:41.140786 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9872 04:47:41.143908 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9873 04:47:41.150646 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9874 04:47:41.153823 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9875 04:47:41.160470 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9876 04:47:41.163655 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9877 04:47:41.170292 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9878 04:47:41.173892 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9879 04:47:41.177542 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9880 04:47:41.183406 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9881 04:47:41.186913 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9882 04:47:41.193656 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9883 04:47:41.197032 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9884 04:47:41.203465 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9885 04:47:41.206857 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9886 04:47:41.210042 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9887 04:47:41.217061 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9888 04:47:41.219948 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9889 04:47:41.226479 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9890 04:47:41.230232 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9891 04:47:41.236645 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9892 04:47:41.240157 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9893 04:47:41.246717 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9894 04:47:41.249492 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9895 04:47:41.252781 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9896 04:47:41.259279 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9897 04:47:41.262699 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9898 04:47:41.266001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9899 04:47:41.272647 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9900 04:47:41.276032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9901 04:47:41.282635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9902 04:47:41.286094 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9903 04:47:41.292544 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9904 04:47:41.296083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9905 04:47:41.302901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9906 04:47:41.305871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9907 04:47:41.313180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9908 04:47:41.315947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9909 04:47:41.322748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9910 04:47:41.326453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9911 04:47:41.333026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9912 04:47:41.336536 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9913 04:47:41.343135 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9914 04:47:41.346069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9915 04:47:41.352915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9916 04:47:41.356149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9917 04:47:41.362688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9918 04:47:41.365997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9919 04:47:41.372768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9920 04:47:41.375842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9921 04:47:41.382467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9922 04:47:41.385764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9923 04:47:41.392347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9924 04:47:41.395688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9925 04:47:41.402257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9926 04:47:41.405580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9927 04:47:41.412115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9928 04:47:41.415391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9929 04:47:41.422358 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9930 04:47:41.425176 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9931 04:47:41.428669 INFO: [APUAPC] vio 0
9932 04:47:41.431927 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9933 04:47:41.439075 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9934 04:47:41.442096 INFO: [APUAPC] D0_APC_0: 0x400510
9935 04:47:41.442523 INFO: [APUAPC] D0_APC_1: 0x0
9936 04:47:41.445462 INFO: [APUAPC] D0_APC_2: 0x1540
9937 04:47:41.448900 INFO: [APUAPC] D0_APC_3: 0x0
9938 04:47:41.452265 INFO: [APUAPC] D1_APC_0: 0xffffffff
9939 04:47:41.455109 INFO: [APUAPC] D1_APC_1: 0xffffffff
9940 04:47:41.458619 INFO: [APUAPC] D1_APC_2: 0x3fffff
9941 04:47:41.462050 INFO: [APUAPC] D1_APC_3: 0x0
9942 04:47:41.465727 INFO: [APUAPC] D2_APC_0: 0xffffffff
9943 04:47:41.468767 INFO: [APUAPC] D2_APC_1: 0xffffffff
9944 04:47:41.472315 INFO: [APUAPC] D2_APC_2: 0x3fffff
9945 04:47:41.475061 INFO: [APUAPC] D2_APC_3: 0x0
9946 04:47:41.478296 INFO: [APUAPC] D3_APC_0: 0xffffffff
9947 04:47:41.481923 INFO: [APUAPC] D3_APC_1: 0xffffffff
9948 04:47:41.484911 INFO: [APUAPC] D3_APC_2: 0x3fffff
9949 04:47:41.488273 INFO: [APUAPC] D3_APC_3: 0x0
9950 04:47:41.491546 INFO: [APUAPC] D4_APC_0: 0xffffffff
9951 04:47:41.494954 INFO: [APUAPC] D4_APC_1: 0xffffffff
9952 04:47:41.497925 INFO: [APUAPC] D4_APC_2: 0x3fffff
9953 04:47:41.501252 INFO: [APUAPC] D4_APC_3: 0x0
9954 04:47:41.504802 INFO: [APUAPC] D5_APC_0: 0xffffffff
9955 04:47:41.507960 INFO: [APUAPC] D5_APC_1: 0xffffffff
9956 04:47:41.511195 INFO: [APUAPC] D5_APC_2: 0x3fffff
9957 04:47:41.514874 INFO: [APUAPC] D5_APC_3: 0x0
9958 04:47:41.517947 INFO: [APUAPC] D6_APC_0: 0xffffffff
9959 04:47:41.521057 INFO: [APUAPC] D6_APC_1: 0xffffffff
9960 04:47:41.524387 INFO: [APUAPC] D6_APC_2: 0x3fffff
9961 04:47:41.527828 INFO: [APUAPC] D6_APC_3: 0x0
9962 04:47:41.531185 INFO: [APUAPC] D7_APC_0: 0xffffffff
9963 04:47:41.534214 INFO: [APUAPC] D7_APC_1: 0xffffffff
9964 04:47:41.537585 INFO: [APUAPC] D7_APC_2: 0x3fffff
9965 04:47:41.541040 INFO: [APUAPC] D7_APC_3: 0x0
9966 04:47:41.544432 INFO: [APUAPC] D8_APC_0: 0xffffffff
9967 04:47:41.547487 INFO: [APUAPC] D8_APC_1: 0xffffffff
9968 04:47:41.550929 INFO: [APUAPC] D8_APC_2: 0x3fffff
9969 04:47:41.554332 INFO: [APUAPC] D8_APC_3: 0x0
9970 04:47:41.557466 INFO: [APUAPC] D9_APC_0: 0xffffffff
9971 04:47:41.560832 INFO: [APUAPC] D9_APC_1: 0xffffffff
9972 04:47:41.563931 INFO: [APUAPC] D9_APC_2: 0x3fffff
9973 04:47:41.567450 INFO: [APUAPC] D9_APC_3: 0x0
9974 04:47:41.571047 INFO: [APUAPC] D10_APC_0: 0xffffffff
9975 04:47:41.574081 INFO: [APUAPC] D10_APC_1: 0xffffffff
9976 04:47:41.577641 INFO: [APUAPC] D10_APC_2: 0x3fffff
9977 04:47:41.580822 INFO: [APUAPC] D10_APC_3: 0x0
9978 04:47:41.583960 INFO: [APUAPC] D11_APC_0: 0xffffffff
9979 04:47:41.587224 INFO: [APUAPC] D11_APC_1: 0xffffffff
9980 04:47:41.591097 INFO: [APUAPC] D11_APC_2: 0x3fffff
9981 04:47:41.594097 INFO: [APUAPC] D11_APC_3: 0x0
9982 04:47:41.597128 INFO: [APUAPC] D12_APC_0: 0xffffffff
9983 04:47:41.600402 INFO: [APUAPC] D12_APC_1: 0xffffffff
9984 04:47:41.603845 INFO: [APUAPC] D12_APC_2: 0x3fffff
9985 04:47:41.606966 INFO: [APUAPC] D12_APC_3: 0x0
9986 04:47:41.610160 INFO: [APUAPC] D13_APC_0: 0xffffffff
9987 04:47:41.613365 INFO: [APUAPC] D13_APC_1: 0xffffffff
9988 04:47:41.616755 INFO: [APUAPC] D13_APC_2: 0x3fffff
9989 04:47:41.620110 INFO: [APUAPC] D13_APC_3: 0x0
9990 04:47:41.623305 INFO: [APUAPC] D14_APC_0: 0xffffffff
9991 04:47:41.626765 INFO: [APUAPC] D14_APC_1: 0xffffffff
9992 04:47:41.629894 INFO: [APUAPC] D14_APC_2: 0x3fffff
9993 04:47:41.633627 INFO: [APUAPC] D14_APC_3: 0x0
9994 04:47:41.636862 INFO: [APUAPC] D15_APC_0: 0xffffffff
9995 04:47:41.639995 INFO: [APUAPC] D15_APC_1: 0xffffffff
9996 04:47:41.643262 INFO: [APUAPC] D15_APC_2: 0x3fffff
9997 04:47:41.646645 INFO: [APUAPC] D15_APC_3: 0x0
9998 04:47:41.649832 INFO: [APUAPC] APC_CON: 0x4
9999 04:47:41.652972 INFO: [NOCDAPC] D0_APC_0: 0x0
10000 04:47:41.656124 INFO: [NOCDAPC] D0_APC_1: 0x0
10001 04:47:41.656194 INFO: [NOCDAPC] D1_APC_0: 0x0
10002 04:47:41.659826 INFO: [NOCDAPC] D1_APC_1: 0xfff
10003 04:47:41.662694 INFO: [NOCDAPC] D2_APC_0: 0x0
10004 04:47:41.666006 INFO: [NOCDAPC] D2_APC_1: 0xfff
10005 04:47:41.669446 INFO: [NOCDAPC] D3_APC_0: 0x0
10006 04:47:41.672820 INFO: [NOCDAPC] D3_APC_1: 0xfff
10007 04:47:41.676082 INFO: [NOCDAPC] D4_APC_0: 0x0
10008 04:47:41.679466 INFO: [NOCDAPC] D4_APC_1: 0xfff
10009 04:47:41.682798 INFO: [NOCDAPC] D5_APC_0: 0x0
10010 04:47:41.686130 INFO: [NOCDAPC] D5_APC_1: 0xfff
10011 04:47:41.689502 INFO: [NOCDAPC] D6_APC_0: 0x0
10012 04:47:41.692664 INFO: [NOCDAPC] D6_APC_1: 0xfff
10013 04:47:41.692789 INFO: [NOCDAPC] D7_APC_0: 0x0
10014 04:47:41.696273 INFO: [NOCDAPC] D7_APC_1: 0xfff
10015 04:47:41.699437 INFO: [NOCDAPC] D8_APC_0: 0x0
10016 04:47:41.702619 INFO: [NOCDAPC] D8_APC_1: 0xfff
10017 04:47:41.705806 INFO: [NOCDAPC] D9_APC_0: 0x0
10018 04:47:41.709424 INFO: [NOCDAPC] D9_APC_1: 0xfff
10019 04:47:41.712918 INFO: [NOCDAPC] D10_APC_0: 0x0
10020 04:47:41.716044 INFO: [NOCDAPC] D10_APC_1: 0xfff
10021 04:47:41.719468 INFO: [NOCDAPC] D11_APC_0: 0x0
10022 04:47:41.722831 INFO: [NOCDAPC] D11_APC_1: 0xfff
10023 04:47:41.725960 INFO: [NOCDAPC] D12_APC_0: 0x0
10024 04:47:41.729533 INFO: [NOCDAPC] D12_APC_1: 0xfff
10025 04:47:41.732859 INFO: [NOCDAPC] D13_APC_0: 0x0
10026 04:47:41.733458 INFO: [NOCDAPC] D13_APC_1: 0xfff
10027 04:47:41.735734 INFO: [NOCDAPC] D14_APC_0: 0x0
10028 04:47:41.738863 INFO: [NOCDAPC] D14_APC_1: 0xfff
10029 04:47:41.742256 INFO: [NOCDAPC] D15_APC_0: 0x0
10030 04:47:41.745536 INFO: [NOCDAPC] D15_APC_1: 0xfff
10031 04:47:41.749522 INFO: [NOCDAPC] APC_CON: 0x4
10032 04:47:41.752618 INFO: [APUAPC] set_apusys_apc done
10033 04:47:41.755821 INFO: [DEVAPC] devapc_init done
10034 04:47:41.759052 INFO: GICv3 without legacy support detected.
10035 04:47:41.765638 INFO: ARM GICv3 driver initialized in EL3
10036 04:47:41.768926 INFO: Maximum SPI INTID supported: 639
10037 04:47:41.771914 INFO: BL31: Initializing runtime services
10038 04:47:41.778700 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10039 04:47:41.779161 INFO: SPM: enable CPC mode
10040 04:47:41.785944 INFO: mcdi ready for mcusys-off-idle and system suspend
10041 04:47:41.788991 INFO: BL31: Preparing for EL3 exit to normal world
10042 04:47:41.795565 INFO: Entry point address = 0x80000000
10043 04:47:41.796098 INFO: SPSR = 0x8
10044 04:47:41.801544
10045 04:47:41.801989
10046 04:47:41.802323
10047 04:47:41.804735 Starting depthcharge on Spherion...
10048 04:47:41.805150
10049 04:47:41.805550 Wipe memory regions:
10050 04:47:41.805883
10051 04:47:41.808454 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10052 04:47:41.808946 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10053 04:47:41.809359 Setting prompt string to ['asurada:']
10054 04:47:41.809865 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10055 04:47:41.810528 [0x00000040000000, 0x00000054600000)
10056 04:47:41.930411
10057 04:47:41.931001 [0x00000054660000, 0x00000080000000)
10058 04:47:42.190586
10059 04:47:42.190767 [0x000000821a7280, 0x000000ffe64000)
10060 04:47:42.935652
10061 04:47:42.935833 [0x00000100000000, 0x00000240000000)
10062 04:47:44.826566
10063 04:47:44.829634 Initializing XHCI USB controller at 0x11200000.
10064 04:47:45.867544
10065 04:47:45.870760 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10066 04:47:45.871192
10067 04:47:45.871533
10068 04:47:45.871850
10069 04:47:45.872690 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10071 04:47:45.973671 asurada: tftpboot 192.168.201.1 12699853/tftp-deploy-46nymtka/kernel/image.itb 12699853/tftp-deploy-46nymtka/kernel/cmdline
10072 04:47:45.973858 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10073 04:47:45.973949 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10074 04:47:45.977717 tftpboot 192.168.201.1 12699853/tftp-deploy-46nymtka/kernel/image.ittp-deploy-46nymtka/kernel/cmdline
10075 04:47:45.977801
10076 04:47:45.977873 Waiting for link
10077 04:47:46.138450
10078 04:47:46.138626 R8152: Initializing
10079 04:47:46.138723
10080 04:47:46.141702 Version 6 (ocp_data = 5c30)
10081 04:47:46.141775
10082 04:47:46.144733 R8152: Done initializing
10083 04:47:46.144802
10084 04:47:46.144861 Adding net device
10085 04:47:48.172490
10086 04:47:48.172668 done.
10087 04:47:48.172763
10088 04:47:48.172853 MAC: 00:24:32:30:78:ff
10089 04:47:48.172941
10090 04:47:48.175694 Sending DHCP discover... done.
10091 04:47:48.175764
10092 04:47:58.542308 Waiting for reply... R8152: Bulk read error 0xffffffbf
10093 04:47:58.542447
10094 04:47:58.545428 Receive failed.
10095 04:47:58.545540
10096 04:47:58.545604 done.
10097 04:47:58.545664
10098 04:47:58.548795 Sending DHCP request... done.
10099 04:47:58.548877
10100 04:47:58.551879 Waiting for reply... done.
10101 04:47:58.551960
10102 04:47:58.555141 My ip is 192.168.201.21
10103 04:47:58.555222
10104 04:47:58.558736 The DHCP server ip is 192.168.201.1
10105 04:47:58.558818
10106 04:47:58.562047 TFTP server IP predefined by user: 192.168.201.1
10107 04:47:58.562143
10108 04:47:58.568495 Bootfile predefined by user: 12699853/tftp-deploy-46nymtka/kernel/image.itb
10109 04:47:58.568575
10110 04:47:58.571793 Sending tftp read request... done.
10111 04:47:58.571873
10112 04:47:58.574940 Waiting for the transfer...
10113 04:47:58.575020
10114 04:47:59.143888 00000000 ################################################################
10115 04:47:59.144036
10116 04:47:59.725012 00080000 ################################################################
10117 04:47:59.725163
10118 04:48:00.312432 00100000 ################################################################
10119 04:48:00.312584
10120 04:48:00.876853 00180000 ################################################################
10121 04:48:00.877004
10122 04:48:01.424659 00200000 ################################################################
10123 04:48:01.424810
10124 04:48:01.976072 00280000 ################################################################
10125 04:48:01.976218
10126 04:48:02.536930 00300000 ################################################################
10127 04:48:02.537077
10128 04:48:03.081004 00380000 ################################################################
10129 04:48:03.081152
10130 04:48:03.624522 00400000 ################################################################
10131 04:48:03.624674
10132 04:48:04.192182 00480000 ################################################################
10133 04:48:04.192320
10134 04:48:04.752606 00500000 ################################################################
10135 04:48:04.752755
10136 04:48:05.294359 00580000 ################################################################
10137 04:48:05.294511
10138 04:48:05.836998 00600000 ################################################################
10139 04:48:05.837137
10140 04:48:06.405221 00680000 ################################################################
10141 04:48:06.405371
10142 04:48:06.972231 00700000 ################################################################
10143 04:48:06.972382
10144 04:48:07.546196 00780000 ################################################################
10145 04:48:07.546349
10146 04:48:08.109427 00800000 ################################################################
10147 04:48:08.109622
10148 04:48:08.665229 00880000 ################################################################
10149 04:48:08.665381
10150 04:48:09.251896 00900000 ################################################################
10151 04:48:09.252372
10152 04:48:09.937900 00980000 ################################################################
10153 04:48:09.938387
10154 04:48:10.551073 00a00000 ################################################################
10155 04:48:10.551210
10156 04:48:11.106115 00a80000 ################################################################
10157 04:48:11.106264
10158 04:48:11.676944 00b00000 ################################################################
10159 04:48:11.677523
10160 04:48:12.247222 00b80000 ################################################################
10161 04:48:12.247410
10162 04:48:12.826425 00c00000 ################################################################
10163 04:48:12.826577
10164 04:48:13.398861 00c80000 ################################################################
10165 04:48:13.399013
10166 04:48:13.971622 00d00000 ################################################################
10167 04:48:13.971771
10168 04:48:14.534004 00d80000 ################################################################
10169 04:48:14.534152
10170 04:48:15.101489 00e00000 ################################################################
10171 04:48:15.101633
10172 04:48:15.677470 00e80000 ################################################################
10173 04:48:15.677617
10174 04:48:16.246257 00f00000 ################################################################
10175 04:48:16.246404
10176 04:48:16.809143 00f80000 ################################################################
10177 04:48:16.809289
10178 04:48:17.376490 01000000 ################################################################
10179 04:48:17.376633
10180 04:48:17.935684 01080000 ################################################################
10181 04:48:17.935832
10182 04:48:18.519858 01100000 ################################################################
10183 04:48:18.520003
10184 04:48:19.088360 01180000 ################################################################
10185 04:48:19.088515
10186 04:48:19.672717 01200000 ################################################################
10187 04:48:19.672865
10188 04:48:20.241780 01280000 ################################################################
10189 04:48:20.241920
10190 04:48:20.809499 01300000 ################################################################
10191 04:48:20.809665
10192 04:48:21.396477 01380000 ################################################################
10193 04:48:21.396628
10194 04:48:21.990783 01400000 ################################################################
10195 04:48:21.990924
10196 04:48:22.568405 01480000 ################################################################
10197 04:48:22.568553
10198 04:48:23.143185 01500000 ################################################################
10199 04:48:23.143336
10200 04:48:23.704273 01580000 ################################################################
10201 04:48:23.704416
10202 04:48:24.267793 01600000 ################################################################
10203 04:48:24.267956
10204 04:48:24.826003 01680000 ################################################################
10205 04:48:24.826179
10206 04:48:25.389733 01700000 ################################################################
10207 04:48:25.389891
10208 04:48:25.947754 01780000 ################################################################
10209 04:48:25.947909
10210 04:48:26.508124 01800000 ################################################################
10211 04:48:26.508280
10212 04:48:27.064137 01880000 ################################################################
10213 04:48:27.064297
10214 04:48:27.632283 01900000 ################################################################
10215 04:48:27.632440
10216 04:48:28.185799 01980000 ################################################################
10217 04:48:28.185954
10218 04:48:28.752238 01a00000 ################################################################
10219 04:48:28.752399
10220 04:48:29.306913 01a80000 ################################################################
10221 04:48:29.307071
10222 04:48:29.867234 01b00000 ################################################################
10223 04:48:29.867390
10224 04:48:30.431408 01b80000 ################################################################
10225 04:48:30.431589
10226 04:48:31.008616 01c00000 ################################################################
10227 04:48:31.008767
10228 04:48:31.567207 01c80000 ################################################################
10229 04:48:31.567361
10230 04:48:32.119175 01d00000 ################################################################
10231 04:48:32.119329
10232 04:48:32.663770 01d80000 ################################################################
10233 04:48:32.663922
10234 04:48:33.220320 01e00000 ################################################################
10235 04:48:33.220472
10236 04:48:33.773657 01e80000 ################################################################
10237 04:48:33.773812
10238 04:48:34.324466 01f00000 ################################################################
10239 04:48:34.324618
10240 04:48:34.878519 01f80000 ################################################################
10241 04:48:34.878668
10242 04:48:35.453187 02000000 ################################################################
10243 04:48:35.453369
10244 04:48:36.010635 02080000 ################################################################
10245 04:48:36.010790
10246 04:48:36.576935 02100000 ################################################################
10247 04:48:36.577365
10248 04:48:37.191983 02180000 ################################################################
10249 04:48:37.192522
10250 04:48:37.865311 02200000 ################################################################
10251 04:48:37.865549
10252 04:48:38.557964 02280000 ################################################################
10253 04:48:38.558490
10254 04:48:39.281032 02300000 ################################################################
10255 04:48:39.281600
10256 04:48:39.948707 02380000 ################################################################
10257 04:48:39.949226
10258 04:48:40.682895 02400000 ################################################################
10259 04:48:40.683421
10260 04:48:41.400728 02480000 ################################################################
10261 04:48:41.401244
10262 04:48:42.100381 02500000 ################################################################
10263 04:48:42.100592
10264 04:48:42.725704 02580000 ################################################################
10265 04:48:42.725863
10266 04:48:43.341720 02600000 ################################################################
10267 04:48:43.341856
10268 04:48:43.983454 02680000 ################################################################
10269 04:48:43.983586
10270 04:48:44.601885 02700000 ################################################################
10271 04:48:44.602420
10272 04:48:45.328533 02780000 ################################################################
10273 04:48:45.329050
10274 04:48:46.041043 02800000 ################################################################
10275 04:48:46.041585
10276 04:48:46.714702 02880000 ################################################################
10277 04:48:46.715261
10278 04:48:47.315292 02900000 ################################################################
10279 04:48:47.315462
10280 04:48:47.871634 02980000 ################################################################
10281 04:48:47.871805
10282 04:48:48.443417 02a00000 ################################################################
10283 04:48:48.443565
10284 04:48:49.012850 02a80000 ################################################################
10285 04:48:49.012983
10286 04:48:49.556764 02b00000 ################################################################
10287 04:48:49.556931
10288 04:48:50.074454 02b80000 ################################################################
10289 04:48:50.074592
10290 04:48:50.633070 02c00000 ################################################################
10291 04:48:50.633229
10292 04:48:51.192848 02c80000 ################################################################
10293 04:48:51.192983
10294 04:48:51.735629 02d00000 ################################################################
10295 04:48:51.735764
10296 04:48:52.314422 02d80000 ################################################################
10297 04:48:52.314570
10298 04:48:52.894133 02e00000 ################################################################
10299 04:48:52.894276
10300 04:48:53.464401 02e80000 ################################################################
10301 04:48:53.464569
10302 04:48:53.997033 02f00000 ################################################################
10303 04:48:53.997206
10304 04:48:54.548056 02f80000 ################################################################
10305 04:48:54.548223
10306 04:48:55.110091 03000000 ################################################################
10307 04:48:55.110244
10308 04:48:55.666032 03080000 ################################################################
10309 04:48:55.666186
10310 04:48:56.239282 03100000 ################################################################
10311 04:48:56.239460
10312 04:48:56.778802 03180000 ################################################################
10313 04:48:56.778940
10314 04:48:57.321387 03200000 ################################################################
10315 04:48:57.321561
10316 04:48:57.854045 03280000 ################################################################
10317 04:48:57.854184
10318 04:48:58.395938 03300000 ################################################################
10319 04:48:58.396082
10320 04:48:58.939387 03380000 ################################################################
10321 04:48:58.939565
10322 04:48:59.487342 03400000 ################################################################
10323 04:48:59.487482
10324 04:49:00.047147 03480000 ################################################################
10325 04:49:00.047293
10326 04:49:00.606400 03500000 ################################################################
10327 04:49:00.606541
10328 04:49:01.228368 03580000 ################################################################
10329 04:49:01.228539
10330 04:49:01.770150 03600000 ################################################################
10331 04:49:01.770308
10332 04:49:02.355596 03680000 ################################################################
10333 04:49:02.356168
10334 04:49:03.108716 03700000 ################################################################
10335 04:49:03.109259
10336 04:49:03.848136 03780000 ################################################################
10337 04:49:03.848720
10338 04:49:04.543818 03800000 ################################################################
10339 04:49:04.543977
10340 04:49:05.118274 03880000 ################################################################
10341 04:49:05.118440
10342 04:49:05.717316 03900000 ################################################################
10343 04:49:05.717882
10344 04:49:06.346081 03980000 ################################################################
10345 04:49:06.346593
10346 04:49:06.937701 03a00000 ################################################################
10347 04:49:06.937838
10348 04:49:07.583923 03a80000 ################################################################
10349 04:49:07.584430
10350 04:49:08.293648 03b00000 ################################################################
10351 04:49:08.294157
10352 04:49:08.941393 03b80000 ################################################################
10353 04:49:08.941563
10354 04:49:09.671353 03c00000 ################################################################
10355 04:49:09.671905
10356 04:49:10.393730 03c80000 ################################################################
10357 04:49:10.394242
10358 04:49:11.123126 03d00000 ################################################################
10359 04:49:11.123697
10360 04:49:11.851921 03d80000 ################################################################
10361 04:49:11.852439
10362 04:49:12.597162 03e00000 ################################################################
10363 04:49:12.597708
10364 04:49:13.323203 03e80000 ################################################################
10365 04:49:13.323719
10366 04:49:14.021884 03f00000 ################################################################
10367 04:49:14.022504
10368 04:49:14.762252 03f80000 ################################################################
10369 04:49:14.762776
10370 04:49:15.489809 04000000 ################################################################
10371 04:49:15.490357
10372 04:49:16.239739 04080000 ################################################################
10373 04:49:16.240271
10374 04:49:16.959221 04100000 ################################################################
10375 04:49:16.959759
10376 04:49:17.668382 04180000 ################################################################
10377 04:49:17.668896
10378 04:49:18.402638 04200000 ################################################################
10379 04:49:18.403165
10380 04:49:19.114969 04280000 ################################################################
10381 04:49:19.115513
10382 04:49:19.831996 04300000 ################################################################
10383 04:49:19.832512
10384 04:49:20.530524 04380000 ################################################################
10385 04:49:20.530658
10386 04:49:21.139129 04400000 ################################################################
10387 04:49:21.139626
10388 04:49:21.864647 04480000 ################################################################
10389 04:49:21.864797
10390 04:49:22.537929 04500000 ################################################################
10391 04:49:22.538429
10392 04:49:23.267870 04580000 ################################################################
10393 04:49:23.268435
10394 04:49:23.970025 04600000 ################################################################
10395 04:49:23.970579
10396 04:49:24.607012 04680000 ################################################################
10397 04:49:24.607144
10398 04:49:25.246071 04700000 ################################################################
10399 04:49:25.246781
10400 04:49:25.952530 04780000 ################################################################
10401 04:49:25.953212
10402 04:49:26.602720 04800000 ################################################################
10403 04:49:26.602929
10404 04:49:27.249111 04880000 ################################################################
10405 04:49:27.249795
10406 04:49:27.838964 04900000 ################################################################
10407 04:49:27.839108
10408 04:49:28.478359 04980000 ################################################################
10409 04:49:28.478843
10410 04:49:29.112110 04a00000 ################################################################
10411 04:49:29.112254
10412 04:49:29.707813 04a80000 ################################################################
10413 04:49:29.708524
10414 04:49:30.392305 04b00000 ################################################################
10415 04:49:30.392925
10416 04:49:31.079303 04b80000 ################################################################
10417 04:49:31.079812
10418 04:49:31.759186 04c00000 ################################################################
10419 04:49:31.759333
10420 04:49:32.447333 04c80000 ################################################################
10421 04:49:32.447884
10422 04:49:33.079033 04d00000 ################################################################
10423 04:49:33.079196
10424 04:49:33.739496 04d80000 ################################################################
10425 04:49:33.740038
10426 04:49:34.468591 04e00000 ################################################################
10427 04:49:34.469115
10428 04:49:35.196809 04e80000 ################################################################
10429 04:49:35.197359
10430 04:49:35.834129 04f00000 ################################################################
10431 04:49:35.834268
10432 04:49:36.548237 04f80000 ################################################################
10433 04:49:36.548834
10434 04:49:37.278020 05000000 ################################################################
10435 04:49:37.278548
10436 04:49:38.006436 05080000 ################################################################
10437 04:49:38.007044
10438 04:49:38.706631 05100000 ################################################################
10439 04:49:38.706779
10440 04:49:39.403691 05180000 ################################################################
10441 04:49:39.404215
10442 04:49:40.117283 05200000 ################################################################
10443 04:49:40.117842
10444 04:49:40.854949 05280000 ################################################################
10445 04:49:40.855593
10446 04:49:41.552804 05300000 ################################################################
10447 04:49:41.553344
10448 04:49:42.264251 05380000 ################################################################
10449 04:49:42.264406
10450 04:49:42.929349 05400000 ################################################################
10451 04:49:42.929896
10452 04:49:43.627706 05480000 ################################################################
10453 04:49:43.628218
10454 04:49:44.333298 05500000 ################################################################
10455 04:49:44.333844
10456 04:49:45.057415 05580000 ################################################################
10457 04:49:45.057966
10458 04:49:45.767088 05600000 ################################################################
10459 04:49:45.767600
10460 04:49:46.489320 05680000 ################################################################
10461 04:49:46.489952
10462 04:49:47.215538 05700000 ################################################################
10463 04:49:47.216054
10464 04:49:47.931737 05780000 ################################################################
10465 04:49:47.932264
10466 04:49:48.659082 05800000 ################################################################
10467 04:49:48.659617
10468 04:49:49.390286 05880000 ################################################################
10469 04:49:49.390802
10470 04:49:50.131536 05900000 ################################################################
10471 04:49:50.132079
10472 04:49:50.856244 05980000 ################################################################
10473 04:49:50.856745
10474 04:49:51.592887 05a00000 ################################################################
10475 04:49:51.593421
10476 04:49:52.307626 05a80000 ################################################################
10477 04:49:52.308152
10478 04:49:52.961751 05b00000 ################################################################
10479 04:49:52.962260
10480 04:49:53.680665 05b80000 ################################################################
10481 04:49:53.681171
10482 04:49:54.364693 05c00000 ################################################################
10483 04:49:54.365203
10484 04:49:55.079798 05c80000 ################################################################
10485 04:49:55.080359
10486 04:49:55.797966 05d00000 ################################################################
10487 04:49:55.798545
10488 04:49:56.500752 05d80000 ################################################################
10489 04:49:56.501262
10490 04:49:57.218974 05e00000 ################################################################
10491 04:49:57.219495
10492 04:49:57.941218 05e80000 ################################################################
10493 04:49:57.941818
10494 04:49:58.626724 05f00000 ################################################################
10495 04:49:58.627239
10496 04:49:59.336130 05f80000 ################################################################
10497 04:49:59.336649
10498 04:50:00.049953 06000000 ################################################################
10499 04:50:00.050095
10500 04:50:00.687656 06080000 ################################################################
10501 04:50:00.688336
10502 04:50:01.279612 06100000 ################################################################
10503 04:50:01.279748
10504 04:50:01.960207 06180000 ################################################################
10505 04:50:01.960711
10506 04:50:02.673649 06200000 ################################################################
10507 04:50:02.674146
10508 04:50:03.253168 06280000 ################################################################
10509 04:50:03.253322
10510 04:50:03.908266 06300000 ################################################################
10511 04:50:03.908839
10512 04:50:04.647381 06380000 ################################################################
10513 04:50:04.647912
10514 04:50:05.387040 06400000 ################################################################
10515 04:50:05.387562
10516 04:50:06.099172 06480000 ################################################################
10517 04:50:06.099694
10518 04:50:06.818215 06500000 ################################################################
10519 04:50:06.818730
10520 04:50:07.552842 06580000 ################################################################
10521 04:50:07.553361
10522 04:50:08.274752 06600000 ################################################################
10523 04:50:08.275275
10524 04:50:08.993421 06680000 ################################################################
10525 04:50:08.993973
10526 04:50:09.700383 06700000 ################################################################
10527 04:50:09.700902
10528 04:50:10.375761 06780000 ################################################################
10529 04:50:10.376275
10530 04:50:11.093129 06800000 ################################################################
10531 04:50:11.093680
10532 04:50:11.810266 06880000 ################################################################
10533 04:50:11.810805
10534 04:50:12.251647 06900000 ######################################### done.
10535 04:50:12.252177
10536 04:50:12.255194 The bootfile was 110430910 bytes long.
10537 04:50:12.255823
10538 04:50:12.258115 Sending tftp read request... done.
10539 04:50:12.258533
10540 04:50:12.262199 Waiting for the transfer...
10541 04:50:12.262618
10542 04:50:12.262951 00000000 # done.
10543 04:50:12.263272
10544 04:50:12.268847 Command line loaded dynamically from TFTP file: 12699853/tftp-deploy-46nymtka/kernel/cmdline
10545 04:50:12.269366
10546 04:50:12.282008 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10547 04:50:12.285419
10548 04:50:12.285877 Loading FIT.
10549 04:50:12.286215
10550 04:50:12.288780 Image ramdisk-1 has 98333092 bytes.
10551 04:50:12.289200
10552 04:50:12.292237 Image fdt-1 has 47278 bytes.
10553 04:50:12.292718
10554 04:50:12.295733 Image kernel-1 has 12048508 bytes.
10555 04:50:12.296260
10556 04:50:12.301942 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10557 04:50:12.302399
10558 04:50:12.321964 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10559 04:50:12.322493
10560 04:50:12.325439 Choosing best match conf-1 for compat google,spherion-rev2.
10561 04:50:12.329911
10562 04:50:12.334356 Connected to device vid:did:rid of 1ae0:0028:00
10563 04:50:12.342619
10564 04:50:12.345725 tpm_get_response: command 0x17b, return code 0x0
10565 04:50:12.346167
10566 04:50:12.349217 ec_init: CrosEC protocol v3 supported (256, 248)
10567 04:50:12.352908
10568 04:50:12.356208 tpm_cleanup: add release locality here.
10569 04:50:12.356627
10570 04:50:12.357000 Shutting down all USB controllers.
10571 04:50:12.359736
10572 04:50:12.360150 Removing current net device
10573 04:50:12.360484
10574 04:50:12.366235 Exiting depthcharge with code 4 at timestamp: 179888225
10575 04:50:12.366736
10576 04:50:12.369830 LZMA decompressing kernel-1 to 0x821a6718
10577 04:50:12.370248
10578 04:50:12.373062 LZMA decompressing kernel-1 to 0x40000000
10579 04:50:13.872456
10580 04:50:13.872969 jumping to kernel
10581 04:50:13.875105 end: 2.2.4 bootloader-commands (duration 00:02:32) [common]
10582 04:50:13.875800 start: 2.2.5 auto-login-action (timeout 00:01:53) [common]
10583 04:50:13.876321 Setting prompt string to ['Linux version [0-9]']
10584 04:50:13.876692 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10585 04:50:13.877051 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10586 04:50:13.954485
10587 04:50:13.957927 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10588 04:50:13.961439 start: 2.2.5.1 login-action (timeout 00:01:53) [common]
10589 04:50:13.961977 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10590 04:50:13.962352 Setting prompt string to []
10591 04:50:13.962749 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10592 04:50:13.963173 Using line separator: #'\n'#
10593 04:50:13.963485 No login prompt set.
10594 04:50:13.963798 Parsing kernel messages
10595 04:50:13.964087 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10596 04:50:13.964641 [login-action] Waiting for messages, (timeout 00:01:53)
10597 04:50:13.981105 [ 0.000000] Linux version 6.1.75-cip14-rt8 (KernelCI@build-j97480-arm64-gcc-10-defconfig-arm64-chromebook-6n26j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024
10598 04:50:13.984830 [ 0.000000] random: crng init done
10599 04:50:13.991129 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10600 04:50:13.994305 [ 0.000000] efi: UEFI not found.
10601 04:50:14.000759 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10602 04:50:14.007587 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10603 04:50:14.017765 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10604 04:50:14.027748 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10605 04:50:14.034393 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10606 04:50:14.040807 [ 0.000000] printk: bootconsole [mtk8250] enabled
10607 04:50:14.047441 [ 0.000000] NUMA: No NUMA configuration found
10608 04:50:14.054231 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10609 04:50:14.057290 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10610 04:50:14.060408 [ 0.000000] Zone ranges:
10611 04:50:14.067488 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10612 04:50:14.070302 [ 0.000000] DMA32 empty
10613 04:50:14.077561 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10614 04:50:14.080561 [ 0.000000] Movable zone start for each node
10615 04:50:14.083690 [ 0.000000] Early memory node ranges
10616 04:50:14.090161 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10617 04:50:14.097457 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10618 04:50:14.103518 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10619 04:50:14.110194 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10620 04:50:14.113830 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10621 04:50:14.123743 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10622 04:50:14.179481 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10623 04:50:14.186182 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10624 04:50:14.192880 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10625 04:50:14.195923 [ 0.000000] psci: probing for conduit method from DT.
10626 04:50:14.202360 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10627 04:50:14.205599 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10628 04:50:14.212351 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10629 04:50:14.215734 [ 0.000000] psci: SMC Calling Convention v1.2
10630 04:50:14.222192 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10631 04:50:14.225583 [ 0.000000] Detected VIPT I-cache on CPU0
10632 04:50:14.231800 [ 0.000000] CPU features: detected: GIC system register CPU interface
10633 04:50:14.238628 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10634 04:50:14.245039 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10635 04:50:14.251956 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10636 04:50:14.261737 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10637 04:50:14.268574 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10638 04:50:14.271946 [ 0.000000] alternatives: applying boot alternatives
10639 04:50:14.278224 [ 0.000000] Fallback order for Node 0: 0
10640 04:50:14.284984 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10641 04:50:14.287907 [ 0.000000] Policy zone: Normal
10642 04:50:14.301387 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10643 04:50:14.311239 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10644 04:50:14.323739 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10645 04:50:14.333731 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10646 04:50:14.340221 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10647 04:50:14.343376 <6>[ 0.000000] software IO TLB: area num 8.
10648 04:50:14.400747 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10649 04:50:14.548920 <6>[ 0.000000] Memory: 7871164K/8385536K available (18048K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 616K bss, 481604K reserved, 32768K cma-reserved)
10650 04:50:14.555444 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10651 04:50:14.561986 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10652 04:50:14.565652 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10653 04:50:14.572047 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10654 04:50:14.578783 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10655 04:50:14.581690 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10656 04:50:14.591899 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10657 04:50:14.598338 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10658 04:50:14.604920 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10659 04:50:14.611712 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10660 04:50:14.614834 <6>[ 0.000000] GICv3: 608 SPIs implemented
10661 04:50:14.618413 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10662 04:50:14.624810 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10663 04:50:14.628009 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10664 04:50:14.634630 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10665 04:50:14.648671 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10666 04:50:14.661812 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10667 04:50:14.668459 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10668 04:50:14.676132 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10669 04:50:14.689552 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10670 04:50:14.696048 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10671 04:50:14.702505 <6>[ 0.009182] Console: colour dummy device 80x25
10672 04:50:14.712259 <6>[ 0.013899] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10673 04:50:14.719014 <6>[ 0.024405] pid_max: default: 32768 minimum: 301
10674 04:50:14.722614 <6>[ 0.029306] LSM: Security Framework initializing
10675 04:50:14.729329 <6>[ 0.034244] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10676 04:50:14.739159 <6>[ 0.042105] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10677 04:50:14.745769 <6>[ 0.051509] cblist_init_generic: Setting adjustable number of callback queues.
10678 04:50:14.751939 <6>[ 0.058951] cblist_init_generic: Setting shift to 3 and lim to 1.
10679 04:50:14.762213 <6>[ 0.065290] cblist_init_generic: Setting adjustable number of callback queues.
10680 04:50:14.768701 <6>[ 0.072763] cblist_init_generic: Setting shift to 3 and lim to 1.
10681 04:50:14.771944 <6>[ 0.079202] rcu: Hierarchical SRCU implementation.
10682 04:50:14.778958 <6>[ 0.079204] rcu: Max phase no-delay instances is 1000.
10683 04:50:14.785052 <6>[ 0.079228] printk: bootconsole [mtk8250] printing thread started
10684 04:50:14.791524 <6>[ 0.097542] EFI services will not be available.
10685 04:50:14.795075 <6>[ 0.097731] smp: Bringing up secondary CPUs ...
10686 04:50:14.798250 <6>[ 0.098007] Detected VIPT I-cache on CPU1
10687 04:50:14.808136 <6>[ 0.098063] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10688 04:50:14.814670 <6>[ 0.098087] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10689 04:50:14.824102 <6>[ 0.126025] Detected VIPT I-cache on CPU2
10690 04:50:14.830844 <6>[ 0.126069] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10691 04:50:14.840679 <6>[ 0.126084] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10692 04:50:14.844132 <6>[ 0.126336] Detected VIPT I-cache on CPU3
10693 04:50:14.850580 <6>[ 0.126382] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10694 04:50:14.857033 <6>[ 0.126395] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10695 04:50:14.860225 <6>[ 0.126703] CPU features: detected: Spectre-v4
10696 04:50:14.866851 <6>[ 0.126710] CPU features: detected: Spectre-BHB
10697 04:50:14.870244 <6>[ 0.126715] Detected PIPT I-cache on CPU4
10698 04:50:14.876750 <6>[ 0.126773] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10699 04:50:14.883570 <6>[ 0.126789] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10700 04:50:14.890180 <6>[ 0.127082] Detected PIPT I-cache on CPU5
10701 04:50:14.896737 <6>[ 0.127142] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10702 04:50:14.903395 <6>[ 0.127159] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10703 04:50:14.906826 <6>[ 0.127430] Detected PIPT I-cache on CPU6
10704 04:50:14.913370 <6>[ 0.127495] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10705 04:50:14.920386 <6>[ 0.127511] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10706 04:50:14.928679 <6>[ 0.127799] Detected PIPT I-cache on CPU7
10707 04:50:14.935475 <6>[ 0.127863] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10708 04:50:14.942313 <6>[ 0.127879] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10709 04:50:14.945353 <6>[ 0.127925] smp: Brought up 1 node, 8 CPUs
10710 04:50:14.952238 <6>[ 0.127930] SMP: Total of 8 processors activated.
10711 04:50:14.954932 <6>[ 0.127932] CPU features: detected: 32-bit EL0 Support
10712 04:50:14.965131 <6>[ 0.127935] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10713 04:50:14.971630 <6>[ 0.127937] CPU features: detected: Common not Private translations
10714 04:50:14.978104 <6>[ 0.127939] CPU features: detected: CRC32 instructions
10715 04:50:14.985066 <6>[ 0.127941] CPU features: detected: RCpc load-acquire (LDAPR)
10716 04:50:14.988225 <6>[ 0.127943] CPU features: detected: LSE atomic instructions
10717 04:50:14.994730 <6>[ 0.127944] CPU features: detected: Privileged Access Never
10718 04:50:15.001403 <6>[ 0.127946] CPU features: detected: RAS Extension Support
10719 04:50:15.007699 <6>[ 0.127949] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10720 04:50:15.011362 <6>[ 0.128015] CPU: All CPU(s) started at EL2
10721 04:50:15.017596 <6>[ 0.128017] alternatives: applying system-wide alternatives
10722 04:50:15.021094 <6>[ 0.141097] devtmpfs: initialized
10723 04:50:15.030874 <6>[ 0.147394] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10724 04:50:15.037955 <6>[ 0.147411] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10725 04:50:15.066948 �ѕ��������Bzɑ����b���ª���ѕͱb����ɥjR�<6>[ 0.374<576] printk: console [ttyS0] enabled
10726 04:50:15.076767 6>[ 0.247496] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10727 04:50:15.084506 <6>[ 0.374575] printk: console [ttyS0] printing thread started
10728 04:50:15.091551 <6>[ 0.374579] printk: bootconsole [mtk8250] disabled
10729 04:50:15.098234 <6>[ 0.387838] printk: bootconsole [mtk8250] printing thread stopped
10730 04:50:15.101560 <6>[ 0.389180] SuperH (H)SCI(F) driver initialized
10731 04:50:15.104922 <6>[ 0.389660] msm_serial: driver initialized
10732 04:50:15.114561 <6>[ 0.394259] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10733 04:50:15.124161 <6>[ 0.394288] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10734 04:50:15.138845 <6>[ 0.394318] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10735 04:50:15.144433 <6>[ 0.394347] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10736 04:50:15.152553 <6>[ 0.394369] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10737 04:50:15.168956 <6>[ 0.394397] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10738 04:50:15.170240 <6>[ 0.394424] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10739 04:50:15.178448 <6>[ 0.394547] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10740 04:50:15.183306 <6>[ 0.394578] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10741 04:50:15.187017 <6>[ 0.406206] loop: module loaded
10742 04:50:15.194990 <6>[ 0.408805] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10743 04:50:15.197829 <4>[ 0.426016] mtk-pmic-keys: Failed to locate of_node [id: -1]
10744 04:50:15.204909 <6>[ 0.427086] megasas: 07.719.03.00-rc1
10745 04:50:15.207960 <6>[ 0.436457] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10746 04:50:15.214735 <6>[ 0.439005] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10747 04:50:15.221381 <6>[ 0.450917] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10748 04:50:15.231590 <6>[ 0.504664] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10749 04:50:18.976699 <6>[ 4.280081] Freeing initrd memory: 96024K
10750 04:50:18.982573 <6>[ 4.286369] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10751 04:50:18.986183 <6>[ 4.290976] tun: Universal TUN/TAP device driver, 1.6
10752 04:50:18.989435 <6>[ 4.291731] thunder_xcv, ver 1.0
10753 04:50:18.992702 <6>[ 4.291748] thunder_bgx, ver 1.0
10754 04:50:18.996518 <6>[ 4.291761] nicpf, ver 1.0
10755 04:50:19.006012 <6>[ 4.292822] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10756 04:50:19.009107 <6>[ 4.292826] hns3: Copyright (c) 2017 Huawei Corporation.
10757 04:50:19.013088 <6>[ 4.292850] hclge is initializing
10758 04:50:19.019340 <6>[ 4.292867] e1000: Intel(R) PRO/1000 Network Driver
10759 04:50:19.026530 <6>[ 4.292869] e1000: Copyright (c) 1999-2006 Intel Corporation.
10760 04:50:19.030206 <6>[ 4.292885] e1000e: Intel(R) PRO/1000 Network Driver
10761 04:50:19.037094 <6>[ 4.292887] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10762 04:50:19.040708 <6>[ 4.292905] igb: Intel(R) Gigabit Ethernet Network Driver
10763 04:50:19.047339 <6>[ 4.292906] igb: Copyright (c) 2007-2014 Intel Corporation.
10764 04:50:19.054150 <6>[ 4.292920] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10765 04:50:19.060719 <6>[ 4.292922] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10766 04:50:19.064510 <6>[ 4.293211] sky2: driver version 1.30
10767 04:50:19.071309 <6>[ 4.294272] VFIO - User Level meta-driver version: 0.3
10768 04:50:19.077537 <6>[ 4.297097] usbcore: registered new interface driver usb-storage
10769 04:50:19.081137 <6>[ 4.297277] usbcore: registered new device driver onboard-usb-hub
10770 04:50:19.087748 <6>[ 4.300055] mt6397-rtc mt6359-rtc: registered as rtc0
10771 04:50:19.097304 <6>[ 4.300207] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-04T04:50:19 UTC (1707022219)
10772 04:50:19.100636 <6>[ 4.300820] i2c_dev: i2c /dev entries driver
10773 04:50:19.110553 <6>[ 4.307862] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10774 04:50:19.113944 <6>[ 4.322862] cpu cpu0: EM: created perf domain
10775 04:50:19.117215 <6>[ 4.323165] cpu cpu4: EM: created perf domain
10776 04:50:19.123709 <6>[ 4.326086] sdhci: Secure Digital Host Controller Interface driver
10777 04:50:19.130476 <6>[ 4.326087] sdhci: Copyright(c) Pierre Ossman
10778 04:50:19.137274 <6>[ 4.326437] Synopsys Designware Multimedia Card Interface Driver
10779 04:50:19.140293 <6>[ 4.326826] sdhci-pltfm: SDHCI platform and OF driver helper
10780 04:50:19.146842 <6>[ 4.331050] ledtrig-cpu: registered to indicate activity on CPUs
10781 04:50:19.150514 <6>[ 4.331728] mmc0: CQHCI version 5.10
10782 04:50:19.156595 <6>[ 4.331828] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10783 04:50:19.163463 <6>[ 4.332115] usbcore: registered new interface driver usbhid
10784 04:50:19.167231 <6>[ 4.332116] usbhid: USB HID core driver
10785 04:50:19.176561 <6>[ 4.332240] spi_master spi0: will run message pump with realtime priority
10786 04:50:19.186543 <6>[ 4.362984] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10787 04:50:19.199934 <6>[ 4.365281] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10788 04:50:19.206276 <6>[ 4.367538] cros-ec-spi spi0.0: Chrome EC device registered
10789 04:50:19.216113 <6>[ 4.381414] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10790 04:50:19.222475 <6>[ 4.382407] NET: Registered PF_PACKET protocol family
10791 04:50:19.225916 <6>[ 4.382475] 9pnet: Installing 9P2000 support
10792 04:50:19.229509 <5>[ 4.382514] Key type dns_resolver registered
10793 04:50:19.235576 <6>[ 4.382912] registered taskstats version 1
10794 04:50:19.239043 <5>[ 4.382926] Loading compiled-in X.509 certificates
10795 04:50:19.249268 <4>[ 4.399085] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10796 04:50:19.262541 <4>[ 4.399264] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10797 04:50:19.268997 <3>[ 4.399278] debugfs: File 'uA_load' in directory '/' already present!
10798 04:50:19.275521 <3>[ 4.399285] debugfs: File 'min_uV' in directory '/' already present!
10799 04:50:19.282304 <3>[ 4.399289] debugfs: File 'max_uV' in directory '/' already present!
10800 04:50:19.289216 <3>[ 4.399292] debugfs: File 'constraint_flags' in directory '/' already present!
10801 04:50:19.295790 <3>[ 4.401403] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10802 04:50:19.302264 <6>[ 4.414512] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10803 04:50:19.308889 <6>[ 4.415314] xhci-mtk 11200000.usb: xHCI Host Controller
10804 04:50:19.315753 <6>[ 4.415350] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10805 04:50:19.325153 <6>[ 4.415590] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10806 04:50:19.331581 <6>[ 4.415658] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10807 04:50:19.338408 <6>[ 4.415755] xhci-mtk 11200000.usb: xHCI Host Controller
10808 04:50:19.344987 <6>[ 4.415763] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10809 04:50:19.351663 <6>[ 4.415771] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10810 04:50:19.354992 <6>[ 4.416534] hub 1-0:1.0: USB hub found
10811 04:50:19.361204 <6>[ 4.416618] hub 1-0:1.0: 1 port detected
10812 04:50:19.368348 <6>[ 4.416926] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10813 04:50:19.371021 <6>[ 4.417346] hub 2-0:1.0: USB hub found
10814 04:50:19.377850 <6>[ 4.417367] hub 2-0:1.0: 1 port detected
10815 04:50:19.381416 <6>[ 4.420470] mtk-msdc 11f70000.mmc: Got CD GPIO
10816 04:50:19.384340 <6>[ 4.430506] mmc0: Command Queue Engine enabled
10817 04:50:19.391179 <6>[ 4.430519] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10818 04:50:19.397400 <6>[ 4.430936] mmcblk0: mmc0:0001 DA4128 116 GiB
10819 04:50:19.404069 <6>[ 4.434164] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10820 04:50:19.407727 <6>[ 4.435317] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10821 04:50:19.414151 <6>[ 4.436578] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10822 04:50:19.420845 <6>[ 4.438153] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10823 04:50:19.427079 <6>[ 4.439037] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10824 04:50:19.437615 <6>[ 4.439041] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10825 04:50:19.444141 <4>[ 4.439117] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10826 04:50:19.453655 <6>[ 4.439621] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10827 04:50:19.460267 <6>[ 4.439622] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10828 04:50:19.470180 <6>[ 4.439901] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10829 04:50:19.477046 <6>[ 4.439914] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10830 04:50:19.483565 <6>[ 4.439916] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10831 04:50:19.493244 <6>[ 4.439920] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10832 04:50:19.502957 <6>[ 4.441186] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10833 04:50:19.509907 <6>[ 4.441203] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10834 04:50:19.519553 <6>[ 4.441206] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10835 04:50:19.526402 <6>[ 4.441210] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10836 04:50:19.536271 <6>[ 4.441214] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10837 04:50:19.542934 <6>[ 4.441217] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10838 04:50:19.552900 <6>[ 4.441221] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10839 04:50:19.559547 <6>[ 4.441225] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10840 04:50:19.569412 <6>[ 4.441228] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10841 04:50:19.575706 <6>[ 4.441232] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10842 04:50:19.585452 <6>[ 4.441236] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10843 04:50:19.592206 <6>[ 4.441240] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10844 04:50:19.602216 <6>[ 4.441244] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10845 04:50:19.608918 <6>[ 4.441247] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10846 04:50:19.618831 <6>[ 4.441251] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10847 04:50:19.625430 <6>[ 4.441587] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10848 04:50:19.631578 <6>[ 4.442198] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10849 04:50:19.638360 <6>[ 4.442422] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10850 04:50:19.645440 <6>[ 4.442660] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10851 04:50:19.651881 <6>[ 4.442900] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10852 04:50:19.661394 <6>[ 4.443053] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10853 04:50:19.671253 <6>[ 4.443062] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10854 04:50:19.678233 <6>[ 4.443064] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10855 04:50:19.687940 <6>[ 4.443067] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10856 04:50:19.697881 <6>[ 4.443071] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10857 04:50:19.707842 <6>[ 4.443074] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10858 04:50:19.717614 <6>[ 4.443079] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10859 04:50:19.724122 <6>[ 4.443082] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10860 04:50:19.734181 <6>[ 4.443084] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10861 04:50:19.744193 <6>[ 4.443088] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10862 04:50:19.753993 <6>[ 4.443091] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10863 04:50:19.763922 <6>[ 4.443464] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10864 04:50:19.770469 <6>[ 4.804014] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10865 04:50:19.773249 <6>[ 4.834531] hub 2-1:1.0: USB hub found
10866 04:50:19.780580 <6>[ 4.834822] hub 2-1:1.0: 3 ports detected
10867 04:50:19.783889 <6>[ 4.836409] hub 2-1:1.0: USB hub found
10868 04:50:19.786790 <6>[ 4.836692] hub 2-1:1.0: 3 ports detected
10869 04:50:19.793366 <6>[ 4.955686] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10870 04:50:19.804181 <6>[ 5.108448] hub 1-1:1.0: USB hub found
10871 04:50:19.807909 <6>[ 5.108846] hub 1-1:1.0: 4 ports detected
10872 04:50:19.811080 <6>[ 5.112748] hub 1-1:1.0: USB hub found
10873 04:50:19.814046 <6>[ 5.113150] hub 1-1:1.0: 4 ports detected
10874 04:50:19.887455 <6>[ 5.188095] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10875 04:50:20.123875 <6>[ 5.423874] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10876 04:50:20.248738 <6>[ 5.551919] hub 1-1.4:1.0: USB hub found
10877 04:50:20.251914 <6>[ 5.552381] hub 1-1.4:1.0: 2 ports detected
10878 04:50:20.255162 <6>[ 5.556630] hub 1-1.4:1.0: USB hub found
10879 04:50:20.261414 <6>[ 5.557017] hub 1-1.4:1.0: 2 ports detected
10880 04:50:20.543909 <6>[ 5.843849] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10881 04:50:20.727762 <6>[ 6.027856] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10882 04:50:31.428075 <6>[ 16.736882] ALSA device list:
10883 04:50:31.434777 <6>[ 16.736902] No soundcards found.
10884 04:50:31.437546 <6>[ 16.741370] Freeing unused kernel memory: 8448K
10885 04:50:31.441118 <6>[ 16.741537] Run /init as init process
10886 04:50:31.479356 <6>[ 16.786725] NET: Registered PF_INET6 protocol family
10887 04:50:31.482292 <6>[ 16.787622] Segment Routing with IPv6
10888 04:50:31.488820 <6>[ 16.787638] In-situ OAM (IOAM) with IPv6
10889 04:50:31.493353
10890 04:50:31.516416 Welcome to [1mDebian GNU/Linu<30>[ 16.804374] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10891 04:50:31.523407 <30>[ 16.804951] systemd[1]: Detected architecture arm64.
10892 04:50:31.526084 x 11 (bullseye)[0m!
10893 04:50:31.526501
10894 04:50:31.542724 <30>[ 16.848008] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10895 04:50:31.678453 <30>[ 16.980743] systemd[1]: Queued start job for default target Graphical Interface.
10896 04:50:31.723561 [[0;32m OK [0m] Created slic<30>[ 17.028705] systemd[1]: Created slice system-getty.slice.
10897 04:50:31.726955 e [0;1;39msystem-getty.slice[0m.
10898 04:50:31.752212 [[0;32m OK [0m] Created slic<30>[ 17.057280] systemd[1]: Created slice system-modprobe.slice.
10899 04:50:31.755737 e [0;1;39msystem-modprobe.slice[0m.
10900 04:50:31.778310 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 17.080217] systemd[1]: Created slice system-serial\x2dgetty.slice.
10901 04:50:31.781602 m-serial\x2dgetty.slice[0m.
10902 04:50:31.799733 [[0;32m OK [0m] Created slic<30>[ 17.104833] systemd[1]: Created slice User and Session Slice.
10903 04:50:31.802996 e [0;1;39mUser and Session Slice[0m.
10904 04:50:31.826424 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 17.128040] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10905 04:50:31.829276 ssword …ts to Console Directory Watch[0m.
10906 04:50:31.850376 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 17.151874] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10907 04:50:31.853558 sword R…uests to Wall Directory Watch[0m.
10908 04:50:31.877576 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 17.175844] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10909 04:50:31.883993 <30>[ 17.176027] systemd[1]: Reached target Local Encrypted Volumes.
10910 04:50:31.887471 l Encrypted Volumes[0m.
10911 04:50:31.906985 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 17.212271] systemd[1]: Reached target Paths.
10912 04:50:31.907508 s[0m.
10913 04:50:31.929616 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 17.231814] systemd[1]: Reached target Remote File Systems.
10914 04:50:31.930123 te File Systems[0m.
10915 04:50:31.946294 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 17.251759] systemd[1]: Reached target Slices.
10916 04:50:31.946799 es[0m.
10917 04:50:31.966196 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 17.271825] systemd[1]: Reached target Swap.
10918 04:50:31.966707 [0m.
10919 04:50:31.990251 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 17.292309] systemd[1]: Listening on initctl Compatibility Named Pipe.
10920 04:50:31.993415 l Compatibility Named Pipe[0m.
10921 04:50:32.014647 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 17.316740] systemd[1]: Listening on Journal Audit Socket.
10922 04:50:32.015169 l Audit Socket[0m.
10923 04:50:32.036069 [[0;32m OK [0m] Listening on<30>[ 17.341017] systemd[1]: Listening on Journal Socket (/dev/log).
10924 04:50:32.038924 [0;1;39mJournal Socket (/dev/log)[0m.
10925 04:50:32.060173 [[0;32m OK [0m] Listening on<30>[ 17.365041] systemd[1]: Listening on Journal Socket.
10926 04:50:32.063172 [0;1;39mJournal Socket[0m.
10927 04:50:32.079222 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 17.384408] systemd[1]: Listening on udev Control Socket.
10928 04:50:32.082010 ontrol Socket[0m.
10929 04:50:32.103439 [[0;32m OK [0m] Listening on<30>[ 17.408889] systemd[1]: Listening on udev Kernel Socket.
10930 04:50:32.106666 [0;1;39mudev Kernel Socket[0m.
10931 04:50:32.162798 Mounting [0;1;39mHuge Pages File Syste<30>[ 17.468005] systemd[1]: Mounting Huge Pages File System...
10932 04:50:32.166010 m[0m...
10933 04:50:32.189808 Mounting [0;1;39mPOSIX Message Queue F<30>[ 17.492099] systemd[1]: Mounting POSIX Message Queue File System...
10934 04:50:32.190231 ile System[0m...
10935 04:50:32.212461 Mounting [0;1;39mKerne<30>[ 17.517980] systemd[1]: Mounting Kernel Debug File System...
10936 04:50:32.215548 l Debug File System[0m...
10937 04:50:32.237894 <30>[ 17.540345] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10938 04:50:32.247929 <30>[ 17.544954] systemd[1]: Starting Create list of static device nodes for the current kernel...
10939 04:50:32.254483 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10940 04:50:32.317518 Starting [0;1;39mLoad Kernel Module co<30>[ 17.620191] systemd[1]: Starting Load Kernel Module configfs...
10941 04:50:32.317643 nfigfs[0m...
10942 04:50:32.334437 <30>[ 17.643458] systemd[1]: Starting Load Kernel Module drm...
10943 04:50:32.341032 Starting [0;1;39mLoad Kernel Module drm[0m...
10944 04:50:32.361686 <30>[ 17.664146] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10945 04:50:32.374848 Starting [0;1;39mJourn<30>[ 17.680711] systemd[1]: Starting Journal Service...
10946 04:50:32.374999 al Service[0m...
10947 04:50:32.396988 Startin<30>[ 17.702540] systemd[1]: Starting Load Kernel Modules...
10948 04:50:32.400391 g [0;1;39mLoad Kernel Modules[0m...
10949 04:50:32.423944 Starting [0;1;39mRemou<30>[ 17.729357] systemd[1]: Starting Remount Root and Kernel File Systems...
10950 04:50:32.430624 nt Root and Kernel File Systems[0m...
10951 04:50:32.479900 Starting [0;1;39mColdp<30>[ 17.785078] systemd[1]: Starting Coldplug All udev Devices...
10952 04:50:32.483348 lug All udev Devices[0m...
10953 04:50:32.502153 [[0;32m OK [<30>[ 17.810745] systemd[1]: Started Journal Service.
10954 04:50:32.508783 0m] Started [0;1;39mJournal Service[0m.
10955 04:50:32.525400 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10956 04:50:32.544052 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10957 04:50:32.559764 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10958 04:50:32.579945 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10959 04:50:32.598803 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10960 04:50:32.616519 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10961 04:50:32.636500 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10962 04:50:32.657888 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10963 04:50:32.675153 See 'systemctl status systemd-remount-fs.service' for details.
10964 04:50:32.728441 Mounting [0;1;39mKernel Configuration File System[0m...
10965 04:50:32.748033 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10966 04:50:32.761997 <46>[ 18.067285] systemd-journald[193]: Received client request to flush runtime journal.
10967 04:50:32.773076 Starting [0;1;39mLoad/Save Random Seed[0m...
10968 04:50:32.793461 Starting [0;1;39mApply Kernel Variables[0m...
10969 04:50:32.813416 Starting [0;1;39mCreate System Users[0m...
10970 04:50:32.833284 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10971 04:50:32.855896 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10972 04:50:32.876429 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10973 04:50:32.889248 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10974 04:50:32.905016 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10975 04:50:32.920987 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10976 04:50:32.959957 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10977 04:50:32.983163 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10978 04:50:32.995420 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10979 04:50:33.015174 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10980 04:50:33.063520 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10981 04:50:33.092290 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10982 04:50:33.112931 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10983 04:50:33.134908 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10984 04:50:33.196586 Starting [0;1;39mNetwork Time Synchronization[0m...
10985 04:50:33.218363 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10986 04:50:33.254167 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10987 04:50:33.273726 <6>[ 18.576199] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10988 04:50:33.284413 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10989 04:50:33.302682 <6>[ 18.608630] remoteproc remoteproc0: scp is available
10990 04:50:33.309253 <6>[ 18.608959] remoteproc remoteproc0: powering up scp
10991 04:50:33.315819 <6>[ 18.608980] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10992 04:50:33.322306 <6>[ 18.609023] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10993 04:50:33.328861 <6>[ 18.620064] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10994 04:50:33.339223 <6>[ 18.620106] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10995 04:50:33.348858 <6>[ 18.620117] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10996 04:50:33.355728 <3>[ 18.657641] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10997 04:50:33.362278 <3>[ 18.657662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10998 04:50:33.371900 <3>[ 18.657670] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10999 04:50:33.378840 <3>[ 18.670403] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11000 04:50:33.388448 <3>[ 18.670447] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11001 04:50:33.395206 <3>[ 18.670453] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11002 04:50:33.405080 <3>[ 18.670464] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11003 04:50:33.411860 <3>[ 18.670472] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11004 04:50:33.421593 <3>[ 18.670535] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11005 04:50:33.428275 <3>[ 18.670586] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11006 04:50:33.435291 <3>[ 18.670612] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11007 04:50:33.445551 <3>[ 18.670615] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11008 04:50:33.452147 <3>[ 18.670647] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11009 04:50:33.462275 Startin<3>[ 18.670649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11010 04:50:33.472884 g [0;1;39mLoad/<3>[ 18.670652] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11011 04:50:33.483026 Save Screen …o<3>[ 18.670654] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11012 04:50:33.490129 f leds:white:kbd<3>[ 18.670657] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11013 04:50:33.500661 _backlight[0m..<3>[ 18.670677] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11014 04:50:33.501197 .
11015 04:50:33.506850 <4>[ 18.671956] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11016 04:50:33.513730 <4>[ 18.679187] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11017 04:50:33.520425 <6>[ 18.693145] usbcore: registered new device driver r8152-cfgselector
11018 04:50:33.534201 [[0;32m OK [0m] Started [0;1;39mNetwork Tim<6>[ 18.701030] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11019 04:50:33.543995 e Synchronizatio<6>[ 18.734618] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11020 04:50:33.544508 n[0m.
11021 04:50:33.550704 <6>[ 18.734625] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11022 04:50:33.557236 <6>[ 18.734649] remoteproc remoteproc0: remote processor scp is now up
11023 04:50:33.568183 <4>[ 18.736422] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11024 04:50:33.571563 <4>[ 18.736422] Fallback method does not support PEC.
11025 04:50:33.574536 <6>[ 18.742966] mc: Linux media interface: v0.10
11026 04:50:33.581444 <6>[ 18.746808] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11027 04:50:33.588141 <6>[ 18.746823] pci_bus 0000:00: root bus resource [bus 00-ff]
11028 04:50:33.595133 <6>[ 18.746828] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11029 04:50:33.605957 [[0;32m OK [<6>[ 18.746833] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11030 04:50:33.616405 0m] Finished [0<6>[ 18.746867] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11031 04:50:33.623618 ;1;39mLoad/Save <6>[ 18.746886] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11032 04:50:33.630148 Screen …s of l<6>[ 18.746969] pci 0000:00:00.0: supports D1 D2
11033 04:50:33.637077 <6>[ 18.746972] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11034 04:50:33.646791 eds:white:kbd_ba<3>[ 18.755768] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11035 04:50:33.653263 <6>[ 18.762564] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11036 04:50:33.656769 cklight[0m.
11037 04:50:33.664003 <6>[ 18.770061] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11038 04:50:33.670572 <6>[ 18.770111] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11039 04:50:33.677104 <6>[ 18.770132] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11040 04:50:33.688106 [[0;32m OK [<6>[ 18.770147] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11041 04:50:33.691282 0m] Found device<6>[ 18.770271] pci 0000:01:00.0: supports D1 D2
11042 04:50:33.698146 <6>[ 18.770275] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11043 04:50:33.708357 <6>[ 18.783653] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11044 04:50:33.715052 [0;1;39m/dev/t<6>[ 18.783697] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11045 04:50:33.718203 tyS0[0m.
11046 04:50:33.724806 <6>[ 18.783701] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11047 04:50:33.731983 <6>[ 18.783709] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11048 04:50:33.742090 <6>[ 18.783721] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11049 04:50:33.748892 <6>[ 18.783734] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11050 04:50:33.752817 <6>[ 18.783746] pci 0000:00:00.0: PCI bridge to [bus 01]
11051 04:50:33.763041 <6>[ 18.783751] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11052 04:50:33.769346 <6>[ 18.783964] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11053 04:50:33.773203 <6>[ 18.784557] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11054 04:50:33.780162 <6>[ 18.784857] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11055 04:50:33.789725 <6>[ 18.787799] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11056 04:50:33.799634 <3>[ 18.791632] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11057 04:50:33.813249 [[0;32m OK [0m] Reached target [0;1;39mBlue<3>[ 18.811466] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11058 04:50:33.819642 <3>[ 18.839096] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11059 04:50:33.829854 <6>[ 18.840286] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11060 04:50:33.839660 <6>[ 18.844377] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11061 04:50:33.849624 <6>[ 18.845155] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11062 04:50:33.852709 <6>[ 18.865974] videodev: Linux video capture interface: v2.00
11063 04:50:33.862531 <6>[ 18.868126] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11064 04:50:33.872718 <4>[ 18.868362] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11065 04:50:33.879277 <4>[ 18.868374] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11066 04:50:33.889079 <6>[ 18.869811] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11067 04:50:33.895683 <5>[ 18.874699] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11068 04:50:33.905640 <3>[ 18.881527] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11069 04:50:33.912445 <5>[ 18.881815] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11070 04:50:33.918794 <5>[ 18.882065] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11071 04:50:33.928748 <4>[ 18.882142] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11072 04:50:33.932371 <6>[ 18.882147] cfg80211: failed to load regulatory.db
11073 04:50:33.938775 <6>[ 18.903156] Bluetooth: Core ver 2.22
11074 04:50:33.941849 <6>[ 18.903288] NET: Registered PF_BLUETOOTH protocol family
11075 04:50:33.948879 <6>[ 18.903292] Bluetooth: HCI device and connection manager initialized
11076 04:50:33.954940 <6>[ 18.903311] Bluetooth: HCI socket layer initialized
11077 04:50:33.958763 <6>[ 18.903319] Bluetooth: L2CAP socket layer initialized
11078 04:50:33.964960 <6>[ 18.903329] Bluetooth: SCO socket layer initialized
11079 04:50:33.968456 <6>[ 18.921211] r8152 2-1.3:1.0 eth0: v1.12.13
11080 04:50:33.974996 <6>[ 18.921296] usbcore: registered new interface driver r8152
11081 04:50:33.984800 <3>[ 18.929006] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11082 04:50:33.991461 <3>[ 18.929692] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11083 04:50:33.998028 <6>[ 18.938719] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11084 04:50:34.011301 <6>[ 18.940378] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11085 04:50:34.017927 <6>[ 18.940656] usbcore: registered new interface driver uvcvideo
11086 04:50:34.027488 <3>[ 18.941997] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11087 04:50:34.030947 <6>[ 18.950913] usbcore: registered new interface driver cdc_ether
11088 04:50:34.037638 <6>[ 18.969207] usbcore: registered new interface driver r8153_ecm
11089 04:50:34.047608 <3>[ 18.978266] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11090 04:50:34.054078 <6>[ 18.986559] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11091 04:50:34.063896 <4>[ 18.988105] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11092 04:50:34.070422 <3>[ 18.988125] Bluetooth: hci0: Failed to load firmware file (-2)
11093 04:50:34.077714 <3>[ 18.988129] Bluetooth: hci0: Failed to set up firmware (-2)
11094 04:50:34.087237 <4>[ 18.988132] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11095 04:50:34.093763 <6>[ 18.988854] usbcore: registered new interface driver btusb
11096 04:50:34.100344 <6>[ 19.000112] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11097 04:50:34.107199 <6>[ 19.000254] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11098 04:50:34.114007 <3>[ 19.002143] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11099 04:50:34.120143 <6>[ 19.007285] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
11100 04:50:34.126777 <6>[ 19.019716] mt7921e 0000:01:00.0: ASIC revision: 79610010
11101 04:50:34.133545 <6>[ 19.118825] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11102 04:50:34.136526 <6>[ 19.118825]
11103 04:50:34.146279 <6>[ 19.376746] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11104 04:50:34.146787 tooth[0m.
11105 04:50:34.163120 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11106 04:50:34.182491 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11107 04:50:34.194884 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11108 04:50:34.211562 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11109 04:50:34.230892 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11110 04:50:34.242925 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11111 04:50:34.262671 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11112 04:50:34.275067 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11113 04:50:34.290932 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11114 04:50:34.310201 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11115 04:50:34.351186 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11116 04:50:34.382083 Starting [0;1;39mUser Login Management[0m...
11117 04:50:34.399857 Starting [0;1;39mPermit User Sessions[0m...
11118 04:50:34.419770 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11119 04:50:34.472301 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11120 04:50:34.492465 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11121 04:50:34.507513 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11122 04:50:34.527801 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11123 04:50:34.544514 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11124 04:50:34.560117 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11125 04:50:34.568125 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11126 04:50:34.583608 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11127 04:50:34.639265 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11128 04:50:34.670021 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11129 04:50:34.702274
11130 04:50:34.702782
11131 04:50:34.705777 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11132 04:50:34.706298
11133 04:50:34.708760 debian-bullseye-arm64 login: root (automatic login)
11134 04:50:34.709180
11135 04:50:34.709568
11136 04:50:34.724527 Linux debian-bullseye-arm64 6.1.75-cip14-rt8 #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024 aarch64
11137 04:50:34.725088
11138 04:50:34.731337 The programs included with the Debian GNU/Linux system are free software;
11139 04:50:34.737876 the exact distribution terms for each program are described in the
11140 04:50:34.741286 individual files in /usr/share/doc/*/copyright.
11141 04:50:34.741851
11142 04:50:34.747877 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11143 04:50:34.750919 permitted by applicable law.
11144 04:50:34.752219 Matched prompt #10: / #
11146 04:50:34.753249 Setting prompt string to ['/ #']
11147 04:50:34.753835 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11149 04:50:34.754838 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11150 04:50:34.755310 start: 2.2.6 expect-shell-connection (timeout 00:01:32) [common]
11151 04:50:34.755657 Setting prompt string to ['/ #']
11152 04:50:34.755964 Forcing a shell prompt, looking for ['/ #']
11154 04:50:34.806825 / #
11155 04:50:34.807444 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11156 04:50:34.807883 Waiting using forced prompt support (timeout 00:02:30)
11157 04:50:34.812835
11158 04:50:34.813725 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11159 04:50:34.814216 start: 2.2.7 export-device-env (timeout 00:01:32) [common]
11160 04:50:34.814664 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11161 04:50:34.815114 end: 2.2 depthcharge-retry (duration 00:03:28) [common]
11162 04:50:34.815560 end: 2 depthcharge-action (duration 00:03:28) [common]
11163 04:50:34.815993 start: 3 lava-test-retry (timeout 00:05:00) [common]
11164 04:50:34.816423 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11165 04:50:34.816785 Using namespace: common
11167 04:50:34.917957 / # #
11168 04:50:34.918568 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11169 04:50:34.919094 #<6>[ 20.225967] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11170 04:50:34.923808
11171 04:50:34.924513 Using /lava-12699853
11173 04:50:35.025877 / # export SHELL=/bin/sh
11174 04:50:35.032403 export SHELL=/bin/sh
11176 04:50:35.133998 / # . /lava-12699853/environment
11177 04:50:35.140689 . /lava-12699853/environment
11179 04:50:35.242541 / # /lava-12699853/bin/lava-test-runner /lava-12699853/0
11180 04:50:35.243172 Test shell timeout: 10s (minimum of the action and connection timeout)
11181 04:50:35.249165 /lava-12699853/bin/lava-test-runner /lava-12699853/0
11182 04:50:35.271039 + export TESTRUN_ID=0_sleep
11183 04:50:35.274233 + cd /lava-12699853/0/tests/0_sleep
11184 04:50:35.277635 + cat uuid
11185 04:50:35.278199 + UUID=12699853_1.5.2.3.1
11186 04:50:35.281116 + set +x
11187 04:50:35.284236 <LAVA_SIGNAL_STARTRUN 0_sleep 12699853_1.5.2.3.1>
11188 04:50:35.285022 Received signal: <STARTRUN> 0_sleep 12699853_1.5.2.3.1
11189 04:50:35.285453 Starting test lava.0_sleep (12699853_1.5.2.3.1)
11190 04:50:35.285943 Skipping test definition patterns.
11191 04:50:35.287845 + ./config/lava/sleep/sleep.sh mem
11192 04:50:35.291028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11193 04:50:35.291819 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11195 04:50:35.297407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11196 04:50:35.298141 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11198 04:50:35.300616 rtcwake: assuming RTC uses UTC ...
11199 04:50:35.306964 rtcwake: wakeup from "mem" using rtc0 at Sun Feb 4 04:50:41 2024
11200 04:50:35.314730 <6>[ 20.621097] PM: suspend entry (deep)
11201 04:50:35.317693 <6>[ 20.621138] Filesystems sync: 0.000 seconds
11202 04:50:35.321267 <6>[ 20.623487] Freezing user space processes
11203 04:50:35.337954 <6>[ 20.639784] Freezing user space processes completed (elapsed 0.016 seconds)
11204 04:50:35.341016 <6>[ 20.639799] OOM killer disabled.
11205 04:50:35.344711 <6>[ 20.639802] Freezing remaining freezable tasks
11206 04:50:35.351226 <6>[ 20.641194] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11207 04:50:35.360800 <6>[ 20.641205] printk: Suspending console(s) (use no_console_suspend to debug)
11208 04:50:41.322249 <6>[ 20.867357] Disabling non-boot CPUs ...
11209 04:50:41.325433 <4>[ 20.868491] IRQ282: set affinity failed(-22).
11210 04:50:41.328913 <4>[ 20.868507] IRQ284: set affinity failed(-22).
11211 04:50:41.335407 <6>[ 20.869597] psci: CPU1 killed (polled 0 ms)
11212 04:50:41.338867 <4>[ 20.871050] IRQ282: set affinity failed(-22).
11213 04:50:41.345205 <4>[ 20.871062] IRQ284: set affinity failed(-22).
11214 04:50:41.348615 <6>[ 20.871144] psci: CPU2 killed (polled 0 ms)
11215 04:50:41.351862 <4>[ 20.872468] IRQ282: set affinity failed(-22).
11216 04:50:41.358828 <4>[ 20.872479] IRQ284: set affinity failed(-22).
11217 04:50:41.362087 <6>[ 20.872538] psci: CPU3 killed (polled 0 ms)
11218 04:50:41.365417 <4>[ 20.873595] IRQ282: set affinity failed(-22).
11219 04:50:41.372035 <4>[ 20.873600] IRQ284: set affinity failed(-22).
11220 04:50:41.375243 <6>[ 20.873651] psci: CPU4 killed (polled 0 ms)
11221 04:50:41.381869 <4>[ 20.874534] IRQ282: set affinity failed(-22).
11222 04:50:41.385176 <4>[ 20.874541] IRQ284: set affinity failed(-22).
11223 04:50:41.388529 <6>[ 20.874594] psci: CPU5 killed (polled 0 ms)
11224 04:50:41.395159 <6>[ 20.876710] psci: CPU6 killed (polled 0 ms)
11225 04:50:41.398529 <6>[ 20.877681] psci: CPU7 killed (polled 0 ms)
11226 04:50:41.401666 <6>[ 20.878301] Enabling non-boot CPUs ...
11227 04:50:41.405093 <6>[ 20.878549] Detected VIPT I-cache on CPU1
11228 04:50:41.415246 <6>[ 20.878642] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11229 04:50:41.421721 <6>[ 20.878710] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11230 04:50:41.425112 <6>[ 20.879353] CPU1 is up
11231 04:50:41.428355 <6>[ 20.879510] Detected VIPT I-cache on CPU2
11232 04:50:41.434880 <6>[ 20.879570] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11233 04:50:41.441785 <6>[ 20.879613] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11234 04:50:41.444812 <6>[ 20.880117] CPU2 is up
11235 04:50:41.448085 <6>[ 20.880273] Detected VIPT I-cache on CPU3
11236 04:50:41.454807 <6>[ 20.880335] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11237 04:50:41.461316 <6>[ 20.880377] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11238 04:50:41.465050 <6>[ 20.880906] CPU3 is up
11239 04:50:41.471330 <6>[ 20.881034] CPU features: detected: Hardware dirty bit management
11240 04:50:41.474687 <6>[ 20.881056] Detected PIPT I-cache on CPU4
11241 04:50:41.484611 <6>[ 20.881086] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11242 04:50:41.491328 <6>[ 20.881110] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11243 04:50:41.491413 <6>[ 20.881476] CPU4 is up
11244 04:50:41.498327 <6>[ 20.881622] Detected PIPT I-cache on CPU5
11245 04:50:41.504678 <6>[ 20.881657] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11246 04:50:41.511209 <6>[ 20.881680] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11247 04:50:41.514653 <6>[ 20.882012] CPU5 is up
11248 04:50:41.517765 <6>[ 20.882156] Detected PIPT I-cache on CPU6
11249 04:50:41.524766 <6>[ 20.882190] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11250 04:50:41.531238 <6>[ 20.882213] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11251 04:50:41.534605 <6>[ 20.882556] CPU6 is up
11252 04:50:41.537976 <6>[ 20.882700] Detected PIPT I-cache on CPU7
11253 04:50:41.544747 <6>[ 20.882735] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11254 04:50:41.554355 <6>[ 20.882757] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11255 04:50:41.554453 <6>[ 20.883118] CPU7 is up
11256 04:50:41.561037 <4>[ 21.021597] typec port0-partner: PM: parent port0 should not be sleeping
11257 04:50:41.570239 <6>[ 21.492952] OOM killer enabled.
11258 04:50:41.573361 <6>[ 21.492960] Restarting tasks ... done.
11259 04:50:41.576780 <5>[ 21.494693] random: crng reseeded on system resumption
11260 04:50:41.585514 <LAVA_SIGNAL_TES<6>[ 21.508407] PM: suspend exit
11261 04:50:41.588514 TCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=pass>
11262 04:50:41.588778 Received signal: <TES<6>[> 21.508407] PM: suspend exit
TCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=pass
11263 04:50:41.592342 rtcwake: assuming RTC uses UTC ...
11264 04:50:41.598649 rtcwake: wakeup from "mem" using rtc0 at Sun Feb 4 04:50:47 2024
11265 04:50:41.614115 <6>[ 21.537005] PM: suspend entry (deep)
11266 04:50:41.617673 <6>[ 21.537048] Filesystems sync: 0.000 seconds
11267 04:50:41.620623 <6>[ 21.537641] Freezing user space processes
11268 04:50:41.633543 <6>[ 21.539317] Freezing user space processes completed (elapsed 0.001 seconds)
11269 04:50:41.636759 <6>[ 21.539325] OOM killer disabled.
11270 04:50:41.640184 <6>[ 21.539327] Freezing remaining freezable tasks
11271 04:50:41.646822 <6>[ 21.540543] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11272 04:50:41.656497 <6>[ 21.540550] printk: Suspending console(s) (use no_console_suspend to debug)
11273 04:50:47.312133 <6>[ 21.727437] Disabling non-boot CPUs ...
11274 04:50:47.315331 <6>[ 21.729273] psci: CPU1 killed (polled 0 ms)
11275 04:50:47.318552 <6>[ 21.731218] psci: CPU2 killed (polled 0 ms)
11276 04:50:47.325311 <6>[ 21.733062] psci: CPU3 killed (polled 0 ms)
11277 04:50:47.328401 <6>[ 21.733513] psci: CPU4 killed (polled 0 ms)
11278 04:50:47.331665 <6>[ 21.733963] psci: CPU5 killed (polled 0 ms)
11279 04:50:47.338307 <6>[ 21.734548] psci: CPU6 killed (polled 0 ms)
11280 04:50:47.341720 <6>[ 21.735150] psci: CPU7 killed (polled 0 ms)
11281 04:50:47.345231 <6>[ 21.735532] Enabling non-boot CPUs ...
11282 04:50:47.351525 <6>[ 21.735731] Detected VIPT I-cache on CPU1
11283 04:50:47.358273 <6>[ 21.735804] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11284 04:50:47.364862 <6>[ 21.735853] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11285 04:50:47.368325 <6>[ 21.736406] CPU1 is up
11286 04:50:47.371728 <6>[ 21.736518] Detected VIPT I-cache on CPU2
11287 04:50:47.378421 <6>[ 21.736560] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11288 04:50:47.384983 <6>[ 21.736588] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11289 04:50:47.388320 <6>[ 21.736989] CPU2 is up
11290 04:50:47.391908 <6>[ 21.737099] Detected VIPT I-cache on CPU3
11291 04:50:47.398094 <6>[ 21.737142] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11292 04:50:47.404942 <6>[ 21.737170] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11293 04:50:47.408266 <6>[ 21.737569] CPU3 is up
11294 04:50:47.411621 <6>[ 21.737681] Detected PIPT I-cache on CPU4
11295 04:50:47.421840 <6>[ 21.737703] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11296 04:50:47.427891 <6>[ 21.737719] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11297 04:50:47.431375 <6>[ 21.737992] CPU4 is up
11298 04:50:47.438129 <6>[ 21.738102] Detected PIPT I-cache on CPU5
11299 04:50:47.444707 <6>[ 21.738126] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11300 04:50:47.451367 <6>[ 21.738141] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11301 04:50:47.454861 <6>[ 21.738383] CPU5 is up
11302 04:50:47.458062 <6>[ 21.738490] Detected PIPT I-cache on CPU6
11303 04:50:47.464513 <6>[ 21.738514] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11304 04:50:47.471503 <6>[ 21.738529] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11305 04:50:47.474759 <6>[ 21.738778] CPU6 is up
11306 04:50:47.477978 <6>[ 21.738885] Detected PIPT I-cache on CPU7
11307 04:50:47.484279 <6>[ 21.738908] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11308 04:50:47.491254 <6>[ 21.738923] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11309 04:50:47.494383 <6>[ 21.739185] CPU7 is up
11310 04:50:47.536143 <6>[ 22.315780] OOM killer enabled.
11311 04:50:47.539153 <6>[ 22.315790] Restarting tasks ... done.
11312 04:50:47.545811 <LAVA_SIGNAL_TES<5>[ 22.317637] random: crng reseeded on system resumption
11313 04:50:47.546153 Received signal: <TES<5>[> 22.317637] random: crng reseeded on system resumption
<6
11314 04:50:47.549237 <6>[ 22.319001] PM: suspend exit
11315 04:50:47.552581 TCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=pass>
11316 04:50:47.555938 rtcwake: assuming RTC uses UTC ...
11317 04:50:47.562282 rtcwake: wakeup from "mem" using rtc0 at Sun Feb 4 04:50:53 2024
11318 04:50:47.575979 <6>[ 22.357946] PM: suspend entry (deep)
11319 04:50:47.579287 <6>[ 22.357974] Filesystems sync: 0.000 seconds
11320 04:50:47.582421 <6>[ 22.358264] Freezing user space processes
11321 04:50:47.589090 <6>[ 22.359539] Freezing user space processes completed (elapsed 0.001 seconds)
11322 04:50:47.592673 <6>[ 22.359545] OOM killer disabled.
11323 04:50:47.599062 <6>[ 22.359546] Freezing remaining freezable tasks
11324 04:50:47.605763 <6>[ 22.360774] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11325 04:50:47.612300 <6>[ 22.360780] printk: Suspending console(s) (use no_console_suspend to debug)
11326 04:50:53.314663 <6>[ 22.551726] Disabling non-boot CPUs ...
11327 04:50:53.317798 <6>[ 22.552845] psci: CPU1 killed (polled 0 ms)
11328 04:50:53.321423 <6>[ 22.555042] psci: CPU2 killed (polled 0 ms)
11329 04:50:53.327931 <6>[ 22.557100] psci: CPU3 killed (polled 0 ms)
11330 04:50:53.330947 <6>[ 22.557811] psci: CPU4 killed (polled 0 ms)
11331 04:50:53.334334 <6>[ 22.558425] psci: CPU5 killed (polled 0 ms)
11332 04:50:53.341055 <6>[ 22.559054] psci: CPU6 killed (polled 0 ms)
11333 04:50:53.344323 <6>[ 22.559658] psci: CPU7 killed (polled 0 ms)
11334 04:50:53.347744 <6>[ 22.560111] Enabling non-boot CPUs ...
11335 04:50:53.354147 <6>[ 22.560357] Detected VIPT I-cache on CPU1
11336 04:50:53.361059 <6>[ 22.560449] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11337 04:50:53.367553 <6>[ 22.560512] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11338 04:50:53.370954 <6>[ 22.561254] CPU1 is up
11339 04:50:53.374174 <6>[ 22.561412] Detected VIPT I-cache on CPU2
11340 04:50:53.380557 <6>[ 22.561476] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11341 04:50:53.387379 <6>[ 22.561518] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11342 04:50:53.390880 <6>[ 22.562102] CPU2 is up
11343 04:50:53.394093 <6>[ 22.562253] Detected VIPT I-cache on CPU3
11344 04:50:53.403714 <6>[ 22.562315] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11345 04:50:53.410487 <6>[ 22.562356] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11346 04:50:53.410573 <6>[ 22.562959] CPU3 is up
11347 04:50:53.416975 <6>[ 22.563089] Detected PIPT I-cache on CPU4
11348 04:50:53.423925 <6>[ 22.563111] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11349 04:50:53.430459 <6>[ 22.563125] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11350 04:50:53.433602 <6>[ 22.563475] CPU4 is up
11351 04:50:53.437030 <6>[ 22.563605] Detected PIPT I-cache on CPU5
11352 04:50:53.444094 <6>[ 22.563628] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11353 04:50:53.450555 <6>[ 22.563643] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11354 04:50:53.454043 <6>[ 22.563890] CPU5 is up
11355 04:50:53.457112 <6>[ 22.564020] Detected PIPT I-cache on CPU6
11356 04:50:53.467094 <6>[ 22.564043] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11357 04:50:53.473611 <6>[ 22.564057] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11358 04:50:53.473694 <6>[ 22.564307] CPU6 is up
11359 04:50:53.480109 <6>[ 22.564434] Detected PIPT I-cache on CPU7
11360 04:50:53.486831 <6>[ 22.564456] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11361 04:50:53.493397 <6>[ 22.564471] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11362 04:50:53.496662 <6>[ 22.564736] CPU7 is up
11363 04:50:53.546455 <6>[ 23.151750] OOM killer enabled.
11364 04:50:53.549732 <6>[ 23.151760] Restarting tasks ... done.
11365 04:50:53.556748 <LAVA_SIGNAL_TES<5>[ 23.153626] random: crng reseeded on system resumption
11366 04:50:53.557012 Received signal: <TES<5>[> 23.153626] random: crng reseeded on system resumption
<6
11367 04:50:53.559729 <6>[ 23.155438] PM: suspend exit
11368 04:50:53.563078 TCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=pass>
11369 04:50:53.566333 rtcwake: assuming RTC uses UTC ...
11370 04:50:53.572879 rtcwake: wakeup from "mem" using rtc0 at Sun Feb 4 04:50:59 2024
11371 04:50:53.586444 <6>[ 23.193109] PM: suspend entry (deep)
11372 04:50:53.589831 <6>[ 23.193139] Filesystems sync: 0.000 seconds
11373 04:50:53.592977 <6>[ 23.193438] Freezing user space processes
11374 04:50:53.599420 <6>[ 23.194860] Freezing user space processes completed (elapsed 0.001 seconds)
11375 04:50:53.606206 <6>[ 23.194867] OOM killer disabled.
11376 04:50:53.609805 <6>[ 23.194869] Freezing remaining freezable tasks
11377 04:50:53.616506 <6>[ 23.195986] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11378 04:50:53.622860 <6>[ 23.195990] printk: Suspending console(s) (use no_console_suspend to debug)
11379 04:50:59.327422 <6>[ 23.405725] Disabling non-boot CPUs ...
11380 04:50:59.330739 <6>[ 23.407823] psci: CPU1 killed (polled 4 ms)
11381 04:50:59.333889 <6>[ 23.410048] psci: CPU2 killed (polled 0 ms)
11382 04:50:59.340718 <6>[ 23.411444] psci: CPU3 killed (polled 4 ms)
11383 04:50:59.343748 <6>[ 23.412026] psci: CPU4 killed (polled 0 ms)
11384 04:50:59.347255 <6>[ 23.412558] psci: CPU5 killed (polled 0 ms)
11385 04:50:59.353952 <6>[ 23.413155] psci: CPU6 killed (polled 0 ms)
11386 04:50:59.356973 <6>[ 23.413790] psci: CPU7 killed (polled 0 ms)
11387 04:50:59.360415 <6>[ 23.414158] Enabling non-boot CPUs ...
11388 04:50:59.367071 <6>[ 23.414406] Detected VIPT I-cache on CPU1
11389 04:50:59.373801 <6>[ 23.414497] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11390 04:50:59.380360 <6>[ 23.414559] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11391 04:50:59.383643 <6>[ 23.415283] CPU1 is up
11392 04:50:59.387178 <6>[ 23.415507] Detected VIPT I-cache on CPU2
11393 04:50:59.393629 <6>[ 23.415569] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11394 04:50:59.400044 <6>[ 23.415608] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11395 04:50:59.403352 <6>[ 23.416168] CPU2 is up
11396 04:50:59.406725 <6>[ 23.416330] Detected VIPT I-cache on CPU3
11397 04:50:59.413268 <6>[ 23.416393] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11398 04:50:59.423238 <6>[ 23.416433] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11399 04:50:59.423324 <6>[ 23.417010] CPU3 is up
11400 04:50:59.430237 <6>[ 23.417135] Detected PIPT I-cache on CPU4
11401 04:50:59.436349 <6>[ 23.417153] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11402 04:50:59.443015 <6>[ 23.417165] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11403 04:50:59.446529 <6>[ 23.417406] CPU4 is up
11404 04:50:59.449859 <6>[ 23.417529] Detected PIPT I-cache on CPU5
11405 04:50:59.456533 <6>[ 23.417547] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11406 04:50:59.463155 <6>[ 23.417558] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11407 04:50:59.466674 <6>[ 23.417774] CPU5 is up
11408 04:50:59.469761 <6>[ 23.417895] Detected PIPT I-cache on CPU6
11409 04:50:59.476505 <6>[ 23.417913] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11410 04:50:59.486573 <6>[ 23.417925] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11411 04:50:59.486660 <6>[ 23.418134] CPU6 is up
11412 04:50:59.493107 <6>[ 23.418255] Detected PIPT I-cache on CPU7
11413 04:50:59.499637 <6>[ 23.418273] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11414 04:50:59.506282 <6>[ 23.418285] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11415 04:50:59.509311 <6>[ 23.418521] CPU7 is up
11416 04:50:59.579534 <6>[ 24.039740] OOM killer enabled.
11417 04:50:59.582839 <6>[ 24.039751] Restarting tasks ... done.
11418 04:50:59.586171 <5>[ 24.041754] random: crng reseeded on system resumption
11419 04:50:59.589300 <6>[ 24.042768] PM: suspend exit
11420 04:50:59.595705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=pass>
11421 04:50:59.595971 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=pass
11423 04:50:59.599116 rtcwake: assuming RTC uses UTC ...
11424 04:50:59.605927 rtcwake: wakeup from "mem" using rtc0 at Sun Feb 4 04:51:05 2024
11425 04:50:59.619518 <6>[ 24.080982] PM: suspend entry (deep)
11426 04:50:59.622592 <6>[ 24.081022] Filesystems sync: 0.000 seconds
11427 04:50:59.626055 <6>[ 24.081622] Freezing user space processes
11428 04:50:59.632800 <6>[ 24.083291] Freezing user space processes completed (elapsed 0.001 seconds)
11429 04:50:59.636089 <6>[ 24.083299] OOM killer disabled.
11430 04:50:59.642833 <6>[ 24.083302] Freezing remaining freezable tasks
11431 04:50:59.649426 <6>[ 24.084567] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11432 04:50:59.656175 <6>[ 24.084574] printk: Suspending console(s) (use no_console_suspend to debug)
11433 04:51:05.307132 <6>[ 24.194871] Disabling non-boot CPUs ...
11434 04:51:05.310672 <6>[ 24.195485] psci: CPU1 killed (polled 0 ms)
11435 04:51:05.314112 <6>[ 24.196089] psci: CPU2 killed (polled 0 ms)
11436 04:51:05.320449 <6>[ 24.197594] psci: CPU3 killed (polled 0 ms)
11437 04:51:05.323627 <6>[ 24.197988] psci: CPU4 killed (polled 0 ms)
11438 04:51:05.327185 <6>[ 24.199333] psci: CPU5 killed (polled 0 ms)
11439 04:51:05.333779 <6>[ 24.200789] psci: CPU6 killed (polled 0 ms)
11440 04:51:05.337106 <6>[ 24.201147] psci: CPU7 killed (polled 0 ms)
11441 04:51:05.340718 <6>[ 24.201437] Enabling non-boot CPUs ...
11442 04:51:05.347248 <6>[ 24.201599] Detected VIPT I-cache on CPU1
11443 04:51:05.354059 <6>[ 24.201652] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11444 04:51:05.360288 <6>[ 24.201691] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11445 04:51:05.363688 <6>[ 24.202092] CPU1 is up
11446 04:51:05.367194 <6>[ 24.202172] Detected VIPT I-cache on CPU2
11447 04:51:05.373725 <6>[ 24.202197] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11448 04:51:05.380315 <6>[ 24.202214] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11449 04:51:05.383583 <6>[ 24.202454] CPU2 is up
11450 04:51:05.387113 <6>[ 24.202532] Detected VIPT I-cache on CPU3
11451 04:51:05.393791 <6>[ 24.202557] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11452 04:51:05.400452 <6>[ 24.202574] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11453 04:51:05.403565 <6>[ 24.202811] CPU3 is up
11454 04:51:05.406947 <6>[ 24.202897] Detected PIPT I-cache on CPU4
11455 04:51:05.416943 <6>[ 24.202913] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11456 04:51:05.423765 <6>[ 24.202923] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11457 04:51:05.423894 <6>[ 24.203125] CPU4 is up
11458 04:51:05.430152 <6>[ 24.203208] Detected PIPT I-cache on CPU5
11459 04:51:05.436674 <6>[ 24.203224] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11460 04:51:05.445434 <6>[ 24.203235] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11461 04:51:05.446825 <6>[ 24.203429] CPU5 is up
11462 04:51:05.450181 <6>[ 24.203519] Detected PIPT I-cache on CPU6
11463 04:51:05.462667 <6>[ 24.203535] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11464 04:51:05.468843 <6>[ 24.203545] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11465 04:51:05.472316 <6>[ 24.203727] CPU6 is up
11466 04:51:05.475937 <6>[ 24.203809] Detected PIPT I-cache on CPU7
11467 04:51:05.482415 <6>[ 24.203826] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11468 04:51:05.488924 <6>[ 24.203836] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11469 04:51:05.492288 <6>[ 24.204030] CPU7 is up
11470 04:51:05.567306 <6>[ 24.815639] OOM killer enabled.
11471 04:51:05.570526 <6>[ 24.815650] Restarting tasks ... done.
11472 04:51:05.573647 <5>[ 24.817494] random: crng reseeded on system resumption
11473 04:51:05.576870 <6>[ 24.819210] PM: suspend exit
11474 04:51:05.584068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=pass>
11475 04:51:05.584367 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=pass
11477 04:51:05.587112 rtcwake: assuming RTC uses UTC ...
11478 04:51:05.593527 rtcwake: wakeup from "mem" using rtc0 at Sun Feb 4 04:51:11 2024
11479 04:51:05.607387 <6>[ 24.856410] PM: suspend entry (deep)
11480 04:51:05.610368 <6>[ 24.856441] Filesystems sync: 0.000 seconds
11481 04:51:05.613965 <6>[ 24.856757] Freezing user space processes
11482 04:51:05.620549 <6>[ 24.858191] Freezing user space processes completed (elapsed 0.001 seconds)
11483 04:51:05.623926 <6>[ 24.858199] OOM killer disabled.
11484 04:51:05.630568 <6>[ 24.858200] Freezing remaining freezable tasks
11485 04:51:05.637068 <6>[ 24.859453] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11486 04:51:05.643533 <6>[ 24.859461] printk: Suspending console(s) (use no_console_suspend to debug)
11487 04:51:11.309391 <6>[ 25.058039] Disabling non-boot CPUs ...
11488 04:51:11.312408 <6>[ 25.059128] psci: CPU1 killed (polled 0 ms)
11489 04:51:11.315999 <6>[ 25.061386] psci: CPU2 killed (polled 0 ms)
11490 04:51:11.322593 <6>[ 25.063778] psci: CPU3 killed (polled 4 ms)
11491 04:51:11.325926 <6>[ 25.064363] psci: CPU4 killed (polled 0 ms)
11492 04:51:11.329383 <6>[ 25.064881] psci: CPU5 killed (polled 0 ms)
11493 04:51:11.336069 <6>[ 25.065563] psci: CPU6 killed (polled 0 ms)
11494 04:51:11.339357 <6>[ 25.066201] psci: CPU7 killed (polled 0 ms)
11495 04:51:11.342768 <6>[ 25.066607] Enabling non-boot CPUs ...
11496 04:51:11.346273 <6>[ 25.066860] Detected VIPT I-cache on CPU1
11497 04:51:11.356049 <6>[ 25.066950] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11498 04:51:11.362898 <6>[ 25.067012] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11499 04:51:11.362994 <6>[ 25.067772] CPU1 is up
11500 04:51:11.369382 <6>[ 25.067938] Detected VIPT I-cache on CPU2
11501 04:51:11.376233 <6>[ 25.068000] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11502 04:51:11.382683 <6>[ 25.068040] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11503 04:51:11.386033 <6>[ 25.068600] CPU2 is up
11504 04:51:11.389393 <6>[ 25.068762] Detected VIPT I-cache on CPU3
11505 04:51:11.396089 <6>[ 25.068825] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11506 04:51:11.402644 <6>[ 25.068865] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11507 04:51:11.405720 <6>[ 25.069453] CPU3 is up
11508 04:51:11.409284 <6>[ 25.069581] Detected PIPT I-cache on CPU4
11509 04:51:11.418967 <6>[ 25.069600] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11510 04:51:11.425738 <6>[ 25.069613] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11511 04:51:11.425839 <6>[ 25.069877] CPU4 is up
11512 04:51:11.432212 <6>[ 25.069999] Detected PIPT I-cache on CPU5
11513 04:51:11.439147 <6>[ 25.070019] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11514 04:51:11.445526 <6>[ 25.070032] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11515 04:51:11.448754 <6>[ 25.070252] CPU5 is up
11516 04:51:11.452309 <6>[ 25.070376] Detected PIPT I-cache on CPU6
11517 04:51:11.458673 <6>[ 25.070396] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11518 04:51:11.465355 <6>[ 25.070408] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11519 04:51:11.468705 <6>[ 25.070640] CPU6 is up
11520 04:51:11.472064 <6>[ 25.070762] Detected PIPT I-cache on CPU7
11521 04:51:11.481927 <6>[ 25.070782] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11522 04:51:11.488310 <6>[ 25.070794] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11523 04:51:11.488404 <6>[ 25.071037] CPU7 is up
11524 04:51:11.558005 <6>[ 25.675600] OOM killer enabled.
11525 04:51:11.564508 <6>[ 25.675610] Restarting tasks ... done.
11526 04:51:11.567898 <5>[ 25.677488] random: crng reseeded on system resumption
11527 04:51:11.571331 <6>[ 25.678467] PM: suspend exit
11528 04:51:11.577870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=pass>
11529 04:51:11.578149 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=pass
11531 04:51:11.581248 rtcwake: assuming RTC uses UTC ...
11532 04:51:11.587871 rtcwake: wakeup from "mem" using rtc0 at Sun Feb 4 04:51:17 2024
11533 04:51:11.601287 <6>[ 25.716471] PM: suspend entry (deep)
11534 04:51:11.604493 <6>[ 25.716502] Filesystems sync: 0.000 seconds
11535 04:51:11.607981 <6>[ 25.716807] Freezing user space processes
11536 04:51:11.614641 <6>[ 25.718264] Freezing user space processes completed (elapsed 0.001 seconds)
11537 04:51:11.617740 <6>[ 25.718271] OOM killer disabled.
11538 04:51:11.624371 <6>[ 25.718273] Freezing remaining freezable tasks
11539 04:51:11.631128 <6>[ 25.719481] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11540 04:51:11.637761 <6>[ 25.719488] printk: Suspending console(s) (use no_console_suspend to debug)
11541 04:51:17.321768 <6>[ 25.910653] Disabling non-boot CPUs ...
11542 04:51:17.325634 <4>[ 25.911698] migrate_one_irq: 74 callbacks suppressed
11543 04:51:17.331540 <4>[ 25.911712] IRQ282: set affinity failed(-22).
11544 04:51:17.335098 <4>[ 25.911722] IRQ284: set affinity failed(-22).
11545 04:51:17.338198 <6>[ 25.911803] psci: CPU1 killed (polled 0 ms)
11546 04:51:17.344928 <4>[ 25.912892] IRQ282: set affinity failed(-22).
11547 04:51:17.348422 <4>[ 25.912903] IRQ284: set affinity failed(-22).
11548 04:51:17.354575 <6>[ 25.913979] psci: CPU2 killed (polled 0 ms)
11549 04:51:17.358372 <4>[ 25.914975] IRQ282: set affinity failed(-22).
11550 04:51:17.361758 <4>[ 25.914986] IRQ284: set affinity failed(-22).
11551 04:51:17.368519 <6>[ 25.915306] psci: CPU3 killed (polled 4 ms)
11552 04:51:17.371565 <4>[ 25.915638] IRQ282: set affinity failed(-22).
11553 04:51:17.375123 <4>[ 25.915641] IRQ284: set affinity failed(-22).
11554 04:51:17.381554 <6>[ 25.915674] psci: CPU4 killed (polled 0 ms)
11555 04:51:17.384623 <4>[ 25.915973] IRQ282: set affinity failed(-22).
11556 04:51:17.391343 <4>[ 25.915977] IRQ284: set affinity failed(-22).
11557 04:51:17.394734 <6>[ 25.916017] psci: CPU5 killed (polled 0 ms)
11558 04:51:17.398029 <6>[ 25.916587] psci: CPU6 killed (polled 0 ms)
11559 04:51:17.404861 <6>[ 25.917191] psci: CPU7 killed (polled 0 ms)
11560 04:51:17.407963 <6>[ 25.917662] Enabling non-boot CPUs ...
11561 04:51:17.411186 <6>[ 25.917909] Detected VIPT I-cache on CPU1
11562 04:51:17.417482 <6>[ 25.917998] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11563 04:51:17.424210 <6>[ 25.918060] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11564 04:51:17.427255 <6>[ 25.918765] CPU1 is up
11565 04:51:17.430925 <6>[ 25.918928] Detected VIPT I-cache on CPU2
11566 04:51:17.440455 <6>[ 25.918990] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11567 04:51:17.447540 <6>[ 25.919028] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11568 04:51:17.450488 <6>[ 25.919630] CPU2 is up
11569 04:51:17.454065 <6>[ 25.919788] Detected VIPT I-cache on CPU3
11570 04:51:17.460513 <6>[ 25.919851] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11571 04:51:17.467037 <6>[ 25.919890] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11572 04:51:17.470575 <6>[ 25.920466] CPU3 is up
11573 04:51:17.474108 <6>[ 25.920594] Detected PIPT I-cache on CPU4
11574 04:51:17.480708 <6>[ 25.920611] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11575 04:51:17.487127 <6>[ 25.920623] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11576 04:51:17.490437 <6>[ 25.920869] CPU4 is up
11577 04:51:17.497272 <6>[ 25.920989] Detected PIPT I-cache on CPU5
11578 04:51:17.503840 <6>[ 25.921006] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11579 04:51:17.510606 <6>[ 25.921018] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11580 04:51:17.513619 <6>[ 25.921219] CPU5 is up
11581 04:51:17.517159 <6>[ 25.921340] Detected PIPT I-cache on CPU6
11582 04:51:17.523851 <6>[ 25.921357] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11583 04:51:17.530322 <6>[ 25.921368] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11584 04:51:17.533393 <6>[ 25.921575] CPU6 is up
11585 04:51:17.536898 <6>[ 25.921695] Detected PIPT I-cache on CPU7
11586 04:51:17.543590 <6>[ 25.921712] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11587 04:51:17.550183 <6>[ 25.921723] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11588 04:51:17.553739 <6>[ 25.921939] CPU7 is up
11589 04:51:17.561195 <6>[ 26.529412] OOM killer enabled.
11590 04:51:17.564713 <6>[ 26.529422] Restarting tasks ... done.
11591 04:51:17.571337 <5>[ 26.531347] random: crng reseeded on system resumption
11592 04:51:17.571747 <6>[ 26.538693] PM: suspend exit
11593 04:51:17.577645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=pass>
11594 04:51:17.578375 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=pass
11596 04:51:17.581213 rtcwake: assuming RTC uses UTC ...
11597 04:51:17.587551 rtcwake: wakeup from "mem" using rtc0 at Sun Feb 4 04:51:23 2024
11598 04:51:17.601148 <6>[ 26.569893] PM: suspend entry (deep)
11599 04:51:17.604508 <6>[ 26.569918] Filesystems sync: 0.000 seconds
11600 04:51:17.607662 <6>[ 26.570188] Freezing user space processes
11601 04:51:17.614352 <6>[ 26.571296] Freezing user space processes completed (elapsed 0.001 seconds)
11602 04:51:17.617940 <6>[ 26.571301] OOM killer disabled.
11603 04:51:17.624331 <6>[ 26.571302] Freezing remaining freezable tasks
11604 04:51:17.631478 <6>[ 26.572513] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11605 04:51:17.637672 <6>[ 26.572519] printk: Suspending console(s) (use no_console_suspend to debug)
11606 04:51:23.313244 <6>[ 26.773473] Disabling non-boot CPUs ...
11607 04:51:23.316678 <6>[ 26.774454] psci: CPU1 killed (polled 0 ms)
11608 04:51:23.319587 <6>[ 26.776618] psci: CPU2 killed (polled 0 ms)
11609 04:51:23.326403 <6>[ 26.778647] psci: CPU3 killed (polled 0 ms)
11610 04:51:23.329682 <6>[ 26.779352] psci: CPU4 killed (polled 0 ms)
11611 04:51:23.333133 <6>[ 26.779943] psci: CPU5 killed (polled 0 ms)
11612 04:51:23.339631 <6>[ 26.780500] psci: CPU6 killed (polled 0 ms)
11613 04:51:23.343066 <6>[ 26.781138] psci: CPU7 killed (polled 0 ms)
11614 04:51:23.346420 <6>[ 26.781534] Enabling non-boot CPUs ...
11615 04:51:23.352751 <6>[ 26.781778] Detected VIPT I-cache on CPU1
11616 04:51:23.359611 <6>[ 26.781868] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11617 04:51:23.366406 <6>[ 26.781929] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11618 04:51:23.369595 <6>[ 26.782645] CPU1 is up
11619 04:51:23.372855 <6>[ 26.782804] Detected VIPT I-cache on CPU2
11620 04:51:23.379468 <6>[ 26.782865] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11621 04:51:23.386027 <6>[ 26.782905] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11622 04:51:23.389319 <6>[ 26.783502] CPU2 is up
11623 04:51:23.392882 <6>[ 26.783662] Detected VIPT I-cache on CPU3
11624 04:51:23.399657 <6>[ 26.783724] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11625 04:51:23.405913 <6>[ 26.783763] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11626 04:51:23.409439 <6>[ 26.784347] CPU3 is up
11627 04:51:23.412713 <6>[ 26.784469] Detected PIPT I-cache on CPU4
11628 04:51:23.424292 <6>[ 26.784486] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11629 04:51:23.431071 <6>[ 26.784497] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11630 04:51:23.433955 <6>[ 26.784720] CPU4 is up
11631 04:51:23.437908 <6>[ 26.784856] Detected PIPT I-cache on CPU5
11632 04:51:23.444598 <6>[ 26.784874] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11633 04:51:23.450728 <6>[ 26.784884] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11634 04:51:23.454248 <6>[ 26.785081] CPU5 is up
11635 04:51:23.457362 <6>[ 26.785200] Detected PIPT I-cache on CPU6
11636 04:51:23.464214 <6>[ 26.785216] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11637 04:51:23.470688 <6>[ 26.785227] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11638 04:51:23.473881 <6>[ 26.785432] CPU6 is up
11639 04:51:23.480282 <6>[ 26.785556] Detected PIPT I-cache on CPU7
11640 04:51:23.487556 <6>[ 26.785573] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11641 04:51:23.493547 <6>[ 26.785584] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11642 04:51:23.496855 <6>[ 26.785809] CPU7 is up
11643 04:51:23.528828 <6>[ 27.359508] OOM killer enabled.
11644 04:51:23.532007 <6>[ 27.359518] Restarting tasks ... done.
11645 04:51:23.535933 <5>[ 27.361452] random: crng reseeded on system resumption
11646 04:51:23.538780 <6>[ 27.362223] PM: suspend exit
11647 04:51:23.545219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=pass>
11648 04:51:23.545973 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=pass
11650 04:51:23.548714 rtcwake: assuming RTC uses UTC ...
11651 04:51:23.555668 rtcwake: wakeup from "mem" using rtc0 at Sun Feb 4 04:51:29 2024
11652 04:51:23.569339 <6>[ 27.401219] PM: suspend entry (deep)
11653 04:51:23.572371 <6>[ 27.401253] Filesystems sync: 0.000 seconds
11654 04:51:23.575812 <6>[ 27.401579] Freezing user space processes
11655 04:51:23.582045 <6>[ 27.403098] Freezing user space processes completed (elapsed 0.001 seconds)
11656 04:51:23.585677 <6>[ 27.403106] OOM killer disabled.
11657 04:51:23.592463 <6>[ 27.403108] Freezing remaining freezable tasks
11658 04:51:23.598999 <6>[ 27.404339] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11659 04:51:23.605394 <6>[ 27.404347] printk: Suspending console(s) (use no_console_suspend to debug)
11660 04:51:29.307146 <6>[ 27.581349] Disabling non-boot CPUs ...
11661 04:51:29.310618 <6>[ 27.583215] psci: CPU1 killed (polled 4 ms)
11662 04:51:29.313925 <6>[ 27.585373] psci: CPU2 killed (polled 0 ms)
11663 04:51:29.320486 <6>[ 27.587218] psci: CPU3 killed (polled 4 ms)
11664 04:51:29.323634 <6>[ 27.587849] psci: CPU4 killed (polled 0 ms)
11665 04:51:29.326840 <6>[ 27.588382] psci: CPU5 killed (polled 0 ms)
11666 04:51:29.334107 <6>[ 27.589083] psci: CPU6 killed (polled 0 ms)
11667 04:51:29.336872 <6>[ 27.589752] psci: CPU7 killed (polled 0 ms)
11668 04:51:29.340589 <6>[ 27.590100] Enabling non-boot CPUs ...
11669 04:51:29.346941 <6>[ 27.590344] Detected VIPT I-cache on CPU1
11670 04:51:29.353823 <6>[ 27.590435] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11671 04:51:29.360384 <6>[ 27.590498] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11672 04:51:29.363388 <6>[ 27.591274] CPU1 is up
11673 04:51:29.366879 <6>[ 27.591434] Detected VIPT I-cache on CPU2
11674 04:51:29.373369 <6>[ 27.591498] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11675 04:51:29.379900 <6>[ 27.591539] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11676 04:51:29.383412 <6>[ 27.592113] CPU2 is up
11677 04:51:29.386714 <6>[ 27.592265] Detected VIPT I-cache on CPU3
11678 04:51:29.393486 <6>[ 27.592328] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11679 04:51:29.403093 <6>[ 27.592368] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11680 04:51:29.403177 <6>[ 27.592969] CPU3 is up
11681 04:51:29.409859 <6>[ 27.593098] Detected PIPT I-cache on CPU4
11682 04:51:29.416402 <6>[ 27.593120] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11683 04:51:29.426353 <6>[ 27.593135] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11684 04:51:29.426435 <6>[ 27.593410] CPU4 is up
11685 04:51:29.432910 <6>[ 27.593540] Detected PIPT I-cache on CPU5
11686 04:51:29.439466 <6>[ 27.593562] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11687 04:51:29.445845 <6>[ 27.593577] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11688 04:51:29.449405 <6>[ 27.593821] CPU5 is up
11689 04:51:29.452497 <6>[ 27.593950] Detected PIPT I-cache on CPU6
11690 04:51:29.459251 <6>[ 27.593972] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11691 04:51:29.465756 <6>[ 27.593987] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11692 04:51:29.469067 <6>[ 27.594236] CPU6 is up
11693 04:51:29.472524 <6>[ 27.594364] Detected PIPT I-cache on CPU7
11694 04:51:29.479079 <6>[ 27.594386] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11695 04:51:29.488807 <6>[ 27.594400] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11696 04:51:29.488915 <6>[ 27.594673] CPU7 is up
11697 04:51:29.530981 <6>[ 28.171390] OOM killer enabled.
11698 04:51:29.534182 <6>[ 28.171400] Restarting tasks ... done.
11699 04:51:29.540840 <5>[ 28.172838] random: crng reseeded on system resumption
11700 04:51:29.540949 <6>[ 28.182672] PM: suspend exit
11701 04:51:29.547387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=pass>
11702 04:51:29.547650 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=pass
11704 04:51:29.550711 rtcwake: assuming RTC uses UTC ...
11705 04:51:29.557350 rtcwake: wakeup from "mem" using rtc0 at Sun Feb 4 04:51:35 2024
11706 04:51:29.570999 <6>[ 28.213874] PM: suspend entry (deep)
11707 04:51:29.574051 <6>[ 28.213902] Filesystems sync: 0.000 seconds
11708 04:51:29.577629 <6>[ 28.214193] Freezing user space processes
11709 04:51:29.590184 <6>[ 28.215208] Freezing user space processes completed (elapsed 0.001 seconds)
11710 04:51:29.593454 <6>[ 28.215213] OOM killer disabled.
11711 04:51:29.596913 <6>[ 28.215215] Freezing remaining freezable tasks
11712 04:51:29.603812 <6>[ 28.216448] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11713 04:51:29.613532 <6>[ 28.216454] printk: Suspending console(s) (use no_console_suspend to debug)
11714 04:51:35.312035 <6>[ 28.407515] Disabling non-boot CPUs ...
11715 04:51:35.315488 <6>[ 28.409644] psci: CPU1 killed (polled 0 ms)
11716 04:51:35.318391 <6>[ 28.411174] psci: CPU2 killed (polled 4 ms)
11717 04:51:35.325017 <6>[ 28.413248] psci: CPU3 killed (polled 0 ms)
11718 04:51:35.328497 <6>[ 28.413955] psci: CPU4 killed (polled 0 ms)
11719 04:51:35.331415 <6>[ 28.414540] psci: CPU5 killed (polled 0 ms)
11720 04:51:35.338312 <6>[ 28.415304] psci: CPU6 killed (polled 0 ms)
11721 04:51:35.341592 <6>[ 28.416013] psci: CPU7 killed (polled 0 ms)
11722 04:51:35.345102 <6>[ 28.416368] Enabling non-boot CPUs ...
11723 04:51:35.351588 <6>[ 28.416619] Detected VIPT I-cache on CPU1
11724 04:51:35.358224 <6>[ 28.416713] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11725 04:51:35.364985 <6>[ 28.416780] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11726 04:51:35.368298 <6>[ 28.417532] CPU1 is up
11727 04:51:35.371344 <6>[ 28.417690] Detected VIPT I-cache on CPU2
11728 04:51:35.378167 <6>[ 28.417754] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11729 04:51:35.384766 <6>[ 28.417798] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11730 04:51:35.387993 <6>[ 28.418396] CPU2 is up
11731 04:51:35.391351 <6>[ 28.418550] Detected VIPT I-cache on CPU3
11732 04:51:35.397916 <6>[ 28.418614] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11733 04:51:35.404559 <6>[ 28.418658] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11734 04:51:35.408179 <6>[ 28.419309] CPU3 is up
11735 04:51:35.414809 <6>[ 28.419450] Detected PIPT I-cache on CPU4
11736 04:51:35.421409 <6>[ 28.419477] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11737 04:51:35.427879 <6>[ 28.419495] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11738 04:51:35.431319 <6>[ 28.419809] CPU4 is up
11739 04:51:35.434631 <6>[ 28.419950] Detected PIPT I-cache on CPU5
11740 04:51:35.441392 <6>[ 28.419977] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11741 04:51:35.448093 <6>[ 28.419995] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11742 04:51:35.451201 <6>[ 28.420283] CPU5 is up
11743 04:51:35.454306 <6>[ 28.420418] Detected PIPT I-cache on CPU6
11744 04:51:35.464569 <6>[ 28.420446] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11745 04:51:35.471073 <6>[ 28.420463] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11746 04:51:35.471155 <6>[ 28.420755] CPU6 is up
11747 04:51:35.477928 <6>[ 28.420893] Detected PIPT I-cache on CPU7
11748 04:51:35.484325 <6>[ 28.420920] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11749 04:51:35.491176 <6>[ 28.420938] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11750 04:51:35.494461 <6>[ 28.421244] CPU7 is up
11751 04:51:35.543669 <6>[ 29.011426] OOM killer enabled.
11752 04:51:35.547051 <6>[ 29.011436] Restarting tasks ... done.
11753 04:51:35.550359 <5>[ 29.013253] random: crng reseeded on system resumption
11754 04:51:35.553672 <6>[ 29.014010] PM: suspend exit
11755 04:51:35.560309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=pass>
11756 04:51:35.560392 + set +x
11757 04:51:35.560640 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=pass
11759 04:51:35.563942 Received signal: <ENDRUN> 0_sleep 12699853_1.5.2.3.1
11760 04:51:35.564036 Ending use of test pattern.
11761 04:51:35.564101 Ending test lava.0_sleep (12699853_1.5.2.3.1), duration 60.28
11763 04:51:35.566833 <LAVA_SIGNAL_ENDRUN 0_sleep 12699853_1.5.2.3.1>
11764 04:51:35.566914 <LAVA_TEST_RUNNER EXIT>
11765 04:51:35.567149 ok: lava_test_shell seems to have completed
11766 04:51:35.567273 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-mem-10: pass
rtcwake-mem-4: pass
rtcwake-mem-5: pass
rtcwake-mem-6: pass
rtcwake-mem-7: pass
rtcwake-mem-8: pass
rtcwake-mem-9: pass
11767 04:51:35.567362 end: 3.1 lava-test-shell (duration 00:01:01) [common]
11768 04:51:35.567442 end: 3 lava-test-retry (duration 00:01:01) [common]
11769 04:51:35.567523 start: 4 finalize (timeout 00:05:01) [common]
11770 04:51:35.567612 start: 4.1 power-off (timeout 00:00:30) [common]
11771 04:51:35.567759 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11772 04:51:35.643467 >> Command sent successfully.
11773 04:51:35.645888 Returned 0 in 0 seconds
11774 04:51:35.746733 end: 4.1 power-off (duration 00:00:00) [common]
11776 04:51:35.748335 start: 4.2 read-feedback (timeout 00:05:01) [common]
11777 04:51:35.749839 Listened to connection for namespace 'common' for up to 1s
11778 04:51:36.749591 Finalising connection for namespace 'common'
11779 04:51:36.749774 Disconnecting from shell: Finalise
11780 04:51:36.749852 / #
11781 04:51:36.850135 end: 4.2 read-feedback (duration 00:00:01) [common]
11782 04:51:36.850287 end: 4 finalize (duration 00:00:01) [common]
11783 04:51:36.850402 Cleaning after the job
11784 04:51:36.850504 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699853/tftp-deploy-46nymtka/ramdisk
11785 04:51:36.864006 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699853/tftp-deploy-46nymtka/kernel
11786 04:51:36.887909 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699853/tftp-deploy-46nymtka/dtb
11787 04:51:36.888110 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699853/tftp-deploy-46nymtka/modules
11788 04:51:36.895313 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12699853
11789 04:51:37.068954 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12699853
11790 04:51:37.069132 Job finished correctly