Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 13
- Kernel Errors: 29
1 04:49:55.248417 lava-dispatcher, installed at version: 2023.10
2 04:49:55.248613 start: 0 validate
3 04:49:55.248744 Start time: 2024-02-04 04:49:55.248736+00:00 (UTC)
4 04:49:55.248864 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:49:55.248997 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 04:49:55.530543 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:49:55.531300 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:49:55.792853 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:49:55.793643 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:49:56.063614 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:49:56.064348 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 04:49:56.339879 validate duration: 1.09
14 04:49:56.341388 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:49:56.341973 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:49:56.342504 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:49:56.343128 Not decompressing ramdisk as can be used compressed.
18 04:49:56.343629 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 04:49:56.344006 saving as /var/lib/lava/dispatcher/tmp/12699866/tftp-deploy-ha4svlpj/ramdisk/rootfs.cpio.gz
20 04:49:56.344363 total size: 26246609 (25 MB)
21 04:49:56.349681 progress 0 % (0 MB)
22 04:49:56.378327 progress 5 % (1 MB)
23 04:49:56.390727 progress 10 % (2 MB)
24 04:49:56.399827 progress 15 % (3 MB)
25 04:49:56.407457 progress 20 % (5 MB)
26 04:49:56.414203 progress 25 % (6 MB)
27 04:49:56.420707 progress 30 % (7 MB)
28 04:49:56.427363 progress 35 % (8 MB)
29 04:49:56.433933 progress 40 % (10 MB)
30 04:49:56.440545 progress 45 % (11 MB)
31 04:49:56.447113 progress 50 % (12 MB)
32 04:49:56.453675 progress 55 % (13 MB)
33 04:49:56.460313 progress 60 % (15 MB)
34 04:49:56.466976 progress 65 % (16 MB)
35 04:49:56.473555 progress 70 % (17 MB)
36 04:49:56.480200 progress 75 % (18 MB)
37 04:49:56.486805 progress 80 % (20 MB)
38 04:49:56.493359 progress 85 % (21 MB)
39 04:49:56.499872 progress 90 % (22 MB)
40 04:49:56.506377 progress 95 % (23 MB)
41 04:49:56.512885 progress 100 % (25 MB)
42 04:49:56.513124 25 MB downloaded in 0.17 s (148.30 MB/s)
43 04:49:56.513282 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:49:56.513525 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:49:56.513611 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:49:56.513695 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:49:56.513828 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 04:49:56.513902 saving as /var/lib/lava/dispatcher/tmp/12699866/tftp-deploy-ha4svlpj/kernel/Image
50 04:49:56.513994 total size: 51597824 (49 MB)
51 04:49:56.514069 No compression specified
52 04:49:56.515176 progress 0 % (0 MB)
53 04:49:56.528019 progress 5 % (2 MB)
54 04:49:56.541050 progress 10 % (4 MB)
55 04:49:56.553928 progress 15 % (7 MB)
56 04:49:56.566727 progress 20 % (9 MB)
57 04:49:56.579578 progress 25 % (12 MB)
58 04:49:56.592522 progress 30 % (14 MB)
59 04:49:56.605429 progress 35 % (17 MB)
60 04:49:56.618211 progress 40 % (19 MB)
61 04:49:56.631084 progress 45 % (22 MB)
62 04:49:56.644063 progress 50 % (24 MB)
63 04:49:56.656906 progress 55 % (27 MB)
64 04:49:56.669690 progress 60 % (29 MB)
65 04:49:56.682648 progress 65 % (32 MB)
66 04:49:56.695563 progress 70 % (34 MB)
67 04:49:56.708323 progress 75 % (36 MB)
68 04:49:56.721265 progress 80 % (39 MB)
69 04:49:56.734115 progress 85 % (41 MB)
70 04:49:56.746850 progress 90 % (44 MB)
71 04:49:56.759549 progress 95 % (46 MB)
72 04:49:56.772255 progress 100 % (49 MB)
73 04:49:56.772458 49 MB downloaded in 0.26 s (190.39 MB/s)
74 04:49:56.772611 end: 1.2.1 http-download (duration 00:00:00) [common]
76 04:49:56.772934 end: 1.2 download-retry (duration 00:00:00) [common]
77 04:49:56.773023 start: 1.3 download-retry (timeout 00:10:00) [common]
78 04:49:56.773110 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 04:49:56.773245 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 04:49:56.773313 saving as /var/lib/lava/dispatcher/tmp/12699866/tftp-deploy-ha4svlpj/dtb/mt8192-asurada-spherion-r0.dtb
81 04:49:56.773374 total size: 47278 (0 MB)
82 04:49:56.773434 No compression specified
83 04:49:56.774616 progress 69 % (0 MB)
84 04:49:56.774917 progress 100 % (0 MB)
85 04:49:56.775068 0 MB downloaded in 0.00 s (26.65 MB/s)
86 04:49:56.775188 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:49:56.775405 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:49:56.775488 start: 1.4 download-retry (timeout 00:10:00) [common]
90 04:49:56.775570 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 04:49:56.775676 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 04:49:56.775745 saving as /var/lib/lava/dispatcher/tmp/12699866/tftp-deploy-ha4svlpj/modules/modules.tar
93 04:49:56.775806 total size: 8633524 (8 MB)
94 04:49:56.775867 Using unxz to decompress xz
95 04:49:56.779562 progress 0 % (0 MB)
96 04:49:56.800193 progress 5 % (0 MB)
97 04:49:56.823156 progress 10 % (0 MB)
98 04:49:56.846029 progress 15 % (1 MB)
99 04:49:56.869526 progress 20 % (1 MB)
100 04:49:56.893570 progress 25 % (2 MB)
101 04:49:56.920579 progress 30 % (2 MB)
102 04:49:56.944099 progress 35 % (2 MB)
103 04:49:56.967292 progress 40 % (3 MB)
104 04:49:56.991300 progress 45 % (3 MB)
105 04:49:57.015926 progress 50 % (4 MB)
106 04:49:57.039502 progress 55 % (4 MB)
107 04:49:57.065503 progress 60 % (4 MB)
108 04:49:57.090838 progress 65 % (5 MB)
109 04:49:57.115530 progress 70 % (5 MB)
110 04:49:57.138558 progress 75 % (6 MB)
111 04:49:57.164926 progress 80 % (6 MB)
112 04:49:57.190227 progress 85 % (7 MB)
113 04:49:57.216772 progress 90 % (7 MB)
114 04:49:57.245625 progress 95 % (7 MB)
115 04:49:57.272545 progress 100 % (8 MB)
116 04:49:57.278079 8 MB downloaded in 0.50 s (16.39 MB/s)
117 04:49:57.278318 end: 1.4.1 http-download (duration 00:00:01) [common]
119 04:49:57.278568 end: 1.4 download-retry (duration 00:00:01) [common]
120 04:49:57.278657 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 04:49:57.278754 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 04:49:57.278832 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:49:57.278912 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 04:49:57.279123 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8
125 04:49:57.279246 makedir: /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin
126 04:49:57.279347 makedir: /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/tests
127 04:49:57.279500 makedir: /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/results
128 04:49:57.279612 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-add-keys
129 04:49:57.279754 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-add-sources
130 04:49:57.279877 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-background-process-start
131 04:49:57.280001 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-background-process-stop
132 04:49:57.280147 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-common-functions
133 04:49:57.280277 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-echo-ipv4
134 04:49:57.280396 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-install-packages
135 04:49:57.280512 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-installed-packages
136 04:49:57.280627 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-os-build
137 04:49:57.280741 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-probe-channel
138 04:49:57.280855 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-probe-ip
139 04:49:57.280969 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-target-ip
140 04:49:57.281082 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-target-mac
141 04:49:57.281196 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-target-storage
142 04:49:57.281314 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-test-case
143 04:49:57.281477 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-test-event
144 04:49:57.281636 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-test-feedback
145 04:49:57.281751 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-test-raise
146 04:49:57.281867 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-test-reference
147 04:49:57.282023 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-test-runner
148 04:49:57.282152 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-test-set
149 04:49:57.282269 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-test-shell
150 04:49:57.282387 Updating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-install-packages (oe)
151 04:49:57.282529 Updating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/bin/lava-installed-packages (oe)
152 04:49:57.282643 Creating /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/environment
153 04:49:57.282737 LAVA metadata
154 04:49:57.282807 - LAVA_JOB_ID=12699866
155 04:49:57.282870 - LAVA_DISPATCHER_IP=192.168.201.1
156 04:49:57.282966 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 04:49:57.283033 skipped lava-vland-overlay
158 04:49:57.283104 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 04:49:57.283183 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 04:49:57.283248 skipped lava-multinode-overlay
161 04:49:57.283322 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 04:49:57.283451 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 04:49:57.283619 Loading test definitions
164 04:49:57.283720 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 04:49:57.283792 Using /lava-12699866 at stage 0
166 04:49:57.284072 uuid=12699866_1.5.2.3.1 testdef=None
167 04:49:57.284157 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 04:49:57.284242 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 04:49:57.284726 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 04:49:57.284942 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 04:49:57.285562 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 04:49:57.285786 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 04:49:57.286440 runner path: /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/0/tests/0_v4l2-compliance-uvc test_uuid 12699866_1.5.2.3.1
176 04:49:57.286622 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 04:49:57.286822 Creating lava-test-runner.conf files
179 04:49:57.286884 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12699866/lava-overlay-g22db6f8/lava-12699866/0 for stage 0
180 04:49:57.286970 - 0_v4l2-compliance-uvc
181 04:49:57.287061 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 04:49:57.287143 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 04:49:57.293581 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 04:49:57.293687 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 04:49:57.293771 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 04:49:57.293855 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 04:49:57.293949 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 04:49:57.961068 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 04:49:57.961398 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 04:49:57.961511 extracting modules file /var/lib/lava/dispatcher/tmp/12699866/tftp-deploy-ha4svlpj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699866/extract-overlay-ramdisk-z224qioo/ramdisk
191 04:49:58.164991 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 04:49:58.165150 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 04:49:58.165243 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699866/compress-overlay-vgk2clnn/overlay-1.5.2.4.tar.gz to ramdisk
194 04:49:58.165311 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699866/compress-overlay-vgk2clnn/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12699866/extract-overlay-ramdisk-z224qioo/ramdisk
195 04:49:58.171586 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 04:49:58.171697 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 04:49:58.171816 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 04:49:58.171961 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 04:49:58.172058 Building ramdisk /var/lib/lava/dispatcher/tmp/12699866/extract-overlay-ramdisk-z224qioo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12699866/extract-overlay-ramdisk-z224qioo/ramdisk
200 04:49:58.743035 >> 228465 blocks
201 04:50:02.546643 rename /var/lib/lava/dispatcher/tmp/12699866/extract-overlay-ramdisk-z224qioo/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12699866/tftp-deploy-ha4svlpj/ramdisk/ramdisk.cpio.gz
202 04:50:02.547034 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 04:50:02.547156 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 04:50:02.547256 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 04:50:02.547357 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12699866/tftp-deploy-ha4svlpj/kernel/Image'
206 04:50:14.870510 Returned 0 in 12 seconds
207 04:50:14.971533 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12699866/tftp-deploy-ha4svlpj/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12699866/tftp-deploy-ha4svlpj/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12699866/tftp-deploy-ha4svlpj/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12699866/tftp-deploy-ha4svlpj/kernel/image.itb
208 04:50:15.596548 output: FIT description: Kernel Image image with one or more FDT blobs
209 04:50:15.596869 output: Created: Sun Feb 4 04:50:15 2024
210 04:50:15.597003 output: Image 0 (kernel-1)
211 04:50:15.597071 output: Description:
212 04:50:15.597133 output: Created: Sun Feb 4 04:50:15 2024
213 04:50:15.597198 output: Type: Kernel Image
214 04:50:15.597258 output: Compression: lzma compressed
215 04:50:15.597315 output: Data Size: 12048508 Bytes = 11766.12 KiB = 11.49 MiB
216 04:50:15.597376 output: Architecture: AArch64
217 04:50:15.597433 output: OS: Linux
218 04:50:15.597487 output: Load Address: 0x00000000
219 04:50:15.597539 output: Entry Point: 0x00000000
220 04:50:15.597593 output: Hash algo: crc32
221 04:50:15.597645 output: Hash value: 3b31d50c
222 04:50:15.597697 output: Image 1 (fdt-1)
223 04:50:15.597750 output: Description: mt8192-asurada-spherion-r0
224 04:50:15.597801 output: Created: Sun Feb 4 04:50:15 2024
225 04:50:15.597853 output: Type: Flat Device Tree
226 04:50:15.597904 output: Compression: uncompressed
227 04:50:15.597987 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 04:50:15.598067 output: Architecture: AArch64
229 04:50:15.598119 output: Hash algo: crc32
230 04:50:15.598171 output: Hash value: cc4352de
231 04:50:15.598222 output: Image 2 (ramdisk-1)
232 04:50:15.598274 output: Description: unavailable
233 04:50:15.598325 output: Created: Sun Feb 4 04:50:15 2024
234 04:50:15.598377 output: Type: RAMDisk Image
235 04:50:15.598429 output: Compression: Unknown Compression
236 04:50:15.598480 output: Data Size: 39376483 Bytes = 38453.60 KiB = 37.55 MiB
237 04:50:15.598532 output: Architecture: AArch64
238 04:50:15.598582 output: OS: Linux
239 04:50:15.598634 output: Load Address: unavailable
240 04:50:15.598685 output: Entry Point: unavailable
241 04:50:15.598736 output: Hash algo: crc32
242 04:50:15.598787 output: Hash value: fba1b888
243 04:50:15.598838 output: Default Configuration: 'conf-1'
244 04:50:15.598889 output: Configuration 0 (conf-1)
245 04:50:15.598940 output: Description: mt8192-asurada-spherion-r0
246 04:50:15.598991 output: Kernel: kernel-1
247 04:50:15.599042 output: Init Ramdisk: ramdisk-1
248 04:50:15.599093 output: FDT: fdt-1
249 04:50:15.599144 output: Loadables: kernel-1
250 04:50:15.599194 output:
251 04:50:15.599377 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 04:50:15.599505 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 04:50:15.599626 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 04:50:15.599716 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 04:50:15.599793 No LXC device requested
256 04:50:15.599871 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 04:50:15.599954 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 04:50:15.600029 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 04:50:15.600095 Checking files for TFTP limit of 4294967296 bytes.
260 04:50:15.600565 end: 1 tftp-deploy (duration 00:00:19) [common]
261 04:50:15.600664 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 04:50:15.600756 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 04:50:15.600875 substitutions:
264 04:50:15.600941 - {DTB}: 12699866/tftp-deploy-ha4svlpj/dtb/mt8192-asurada-spherion-r0.dtb
265 04:50:15.601004 - {INITRD}: 12699866/tftp-deploy-ha4svlpj/ramdisk/ramdisk.cpio.gz
266 04:50:15.601063 - {KERNEL}: 12699866/tftp-deploy-ha4svlpj/kernel/Image
267 04:50:15.601119 - {LAVA_MAC}: None
268 04:50:15.601172 - {PRESEED_CONFIG}: None
269 04:50:15.601226 - {PRESEED_LOCAL}: None
270 04:50:15.601279 - {RAMDISK}: 12699866/tftp-deploy-ha4svlpj/ramdisk/ramdisk.cpio.gz
271 04:50:15.601332 - {ROOT_PART}: None
272 04:50:15.601384 - {ROOT}: None
273 04:50:15.601436 - {SERVER_IP}: 192.168.201.1
274 04:50:15.601488 - {TEE}: None
275 04:50:15.601540 Parsed boot commands:
276 04:50:15.601595 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 04:50:15.601757 Parsed boot commands: tftpboot 192.168.201.1 12699866/tftp-deploy-ha4svlpj/kernel/image.itb 12699866/tftp-deploy-ha4svlpj/kernel/cmdline
278 04:50:15.601843 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 04:50:15.601927 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 04:50:15.602085 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 04:50:15.602167 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 04:50:15.602234 Not connected, no need to disconnect.
283 04:50:15.602306 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 04:50:15.602384 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 04:50:15.602447 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 04:50:15.605677 Setting prompt string to ['lava-test: # ']
287 04:50:15.606063 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 04:50:15.606165 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 04:50:15.606277 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 04:50:15.606396 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 04:50:15.606626 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 04:50:20.758448 >> Command sent successfully.
293 04:50:20.769803 Returned 0 in 5 seconds
294 04:50:20.871052 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 04:50:20.872550 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 04:50:20.873136 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 04:50:20.873604 Setting prompt string to 'Starting depthcharge on Spherion...'
299 04:50:20.874035 Changing prompt to 'Starting depthcharge on Spherion...'
300 04:50:20.874418 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 04:50:20.875710 [Enter `^Ec?' for help]
302 04:50:21.034489
303 04:50:21.035062
304 04:50:21.035455 F0: 102B 0000
305 04:50:21.035823
306 04:50:21.036163 F3: 1001 0000 [0200]
307 04:50:21.036501
308 04:50:21.037314 F3: 1001 0000
309 04:50:21.037725
310 04:50:21.038077 F7: 102D 0000
311 04:50:21.038406
312 04:50:21.040976 F1: 0000 0000
313 04:50:21.041444
314 04:50:21.041829 V0: 0000 0000 [0001]
315 04:50:21.042235
316 04:50:21.044145 00: 0007 8000
317 04:50:21.044648
318 04:50:21.045027 01: 0000 0000
319 04:50:21.045400
320 04:50:21.047424 BP: 0C00 0209 [0000]
321 04:50:21.047902
322 04:50:21.048278 G0: 1182 0000
323 04:50:21.048633
324 04:50:21.048970 EC: 0000 0021 [4000]
325 04:50:21.051243
326 04:50:21.051739 S7: 0000 0000 [0000]
327 04:50:21.052368
328 04:50:21.054785 CC: 0000 0000 [0001]
329 04:50:21.055221
330 04:50:21.055566 T0: 0000 0040 [010F]
331 04:50:21.055905
332 04:50:21.056218 Jump to BL
333 04:50:21.056529
334 04:50:21.081025
335 04:50:21.081597
336 04:50:21.082027
337 04:50:21.088691 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 04:50:21.092253 ARM64: Exception handlers installed.
339 04:50:21.095979 ARM64: Testing exception
340 04:50:21.099144 ARM64: Done test exception
341 04:50:21.106091 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 04:50:21.116035 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 04:50:21.122382 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 04:50:21.132879 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 04:50:21.139525 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 04:50:21.146300 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 04:50:21.157677 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 04:50:21.164623 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 04:50:21.183989 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 04:50:21.187105 WDT: Last reset was cold boot
351 04:50:21.190300 SPI1(PAD0) initialized at 2873684 Hz
352 04:50:21.193624 SPI5(PAD0) initialized at 992727 Hz
353 04:50:21.197269 VBOOT: Loading verstage.
354 04:50:21.203666 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 04:50:21.207148 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 04:50:21.210547 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 04:50:21.213373 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 04:50:21.221628 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 04:50:21.228233 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 04:50:21.238813 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 04:50:21.239425
362 04:50:21.239804
363 04:50:21.248673 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 04:50:21.252000 ARM64: Exception handlers installed.
365 04:50:21.255428 ARM64: Testing exception
366 04:50:21.256149 ARM64: Done test exception
367 04:50:21.262018 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 04:50:21.265496 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 04:50:21.279748 Probing TPM: . done!
370 04:50:21.280333 TPM ready after 0 ms
371 04:50:21.286422 Connected to device vid:did:rid of 1ae0:0028:00
372 04:50:21.293515 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 04:50:21.350222 Initialized TPM device CR50 revision 0
374 04:50:21.361529 tlcl_send_startup: Startup return code is 0
375 04:50:21.362011 TPM: setup succeeded
376 04:50:21.373072 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 04:50:21.381716 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 04:50:21.392289 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 04:50:21.401396 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 04:50:21.404384 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 04:50:21.413894 in-header: 03 07 00 00 08 00 00 00
382 04:50:21.417872 in-data: aa e4 47 04 13 02 00 00
383 04:50:21.421729 Chrome EC: UHEPI supported
384 04:50:21.428611 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 04:50:21.431985 in-header: 03 ad 00 00 08 00 00 00
386 04:50:21.435960 in-data: 00 20 20 08 00 00 00 00
387 04:50:21.436544 Phase 1
388 04:50:21.439419 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 04:50:21.447119 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 04:50:21.450255 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 04:50:21.454570 Recovery requested (1009000e)
392 04:50:21.463221 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 04:50:21.468552 tlcl_extend: response is 0
394 04:50:21.478297 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 04:50:21.483873 tlcl_extend: response is 0
396 04:50:21.490460 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 04:50:21.511256 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 04:50:21.518203 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 04:50:21.518789
400 04:50:21.519281
401 04:50:21.528218 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 04:50:21.531240 ARM64: Exception handlers installed.
403 04:50:21.531737 ARM64: Testing exception
404 04:50:21.535030 ARM64: Done test exception
405 04:50:21.556753 pmic_efuse_setting: Set efuses in 11 msecs
406 04:50:21.559878 pmwrap_interface_init: Select PMIF_VLD_RDY
407 04:50:21.567255 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 04:50:21.570481 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 04:50:21.573705 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 04:50:21.580282 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 04:50:21.583772 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 04:50:21.591163 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 04:50:21.594824 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 04:50:21.598328 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 04:50:21.602453 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 04:50:21.609719 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 04:50:21.613629 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 04:50:21.616588 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 04:50:21.623679 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 04:50:21.630016 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 04:50:21.633605 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 04:50:21.640658 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 04:50:21.643952 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 04:50:21.651139 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 04:50:21.658773 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 04:50:21.661785 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 04:50:21.668928 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 04:50:21.672510 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 04:50:21.679312 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 04:50:21.685781 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 04:50:21.689336 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 04:50:21.695838 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 04:50:21.699110 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 04:50:21.706113 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 04:50:21.709673 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 04:50:21.715801 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 04:50:21.719402 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 04:50:21.725843 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 04:50:21.729300 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 04:50:21.736159 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 04:50:21.739493 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 04:50:21.746032 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 04:50:21.749273 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 04:50:21.755887 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 04:50:21.759815 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 04:50:21.763067 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 04:50:21.770125 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 04:50:21.773554 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 04:50:21.776828 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 04:50:21.780339 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 04:50:21.787224 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 04:50:21.790407 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 04:50:21.793753 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 04:50:21.800231 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 04:50:21.803671 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 04:50:21.807003 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 04:50:21.810266 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 04:50:21.820334 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 04:50:21.827073 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 04:50:21.833703 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 04:50:21.840399 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 04:50:21.850238 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 04:50:21.853744 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 04:50:21.856761 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 04:50:21.863641 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 04:50:21.870145 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x18
467 04:50:21.873858 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 04:50:21.880975 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 04:50:21.884261 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 04:50:21.893554 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 04:50:21.903113 [RTC]rtc_get_frequency_meter,154: input=23, output=957
472 04:50:21.912566 [RTC]rtc_get_frequency_meter,154: input=19, output=863
473 04:50:21.922063 [RTC]rtc_get_frequency_meter,154: input=17, output=818
474 04:50:21.932014 [RTC]rtc_get_frequency_meter,154: input=16, output=796
475 04:50:21.935007 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 04:50:21.942062 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 04:50:21.945015 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 04:50:21.948186 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 04:50:21.951728 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 04:50:21.954773 ADC[4]: Raw value=903245 ID=7
481 04:50:21.958086 ADC[3]: Raw value=213179 ID=1
482 04:50:21.958570 RAM Code: 0x71
483 04:50:21.965219 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 04:50:21.968825 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 04:50:21.978522 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 04:50:21.984957 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 04:50:21.988297 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 04:50:21.991713 in-header: 03 07 00 00 08 00 00 00
489 04:50:21.994605 in-data: aa e4 47 04 13 02 00 00
490 04:50:21.998173 Chrome EC: UHEPI supported
491 04:50:22.005142 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 04:50:22.008290 in-header: 03 ed 00 00 08 00 00 00
493 04:50:22.011429 in-data: 80 20 60 08 00 00 00 00
494 04:50:22.014514 MRC: failed to locate region type 0.
495 04:50:22.021690 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 04:50:22.022226 DRAM-K: Running full calibration
497 04:50:22.029163 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 04:50:22.032851 header.status = 0x0
499 04:50:22.036167 header.version = 0x6 (expected: 0x6)
500 04:50:22.036644 header.size = 0xd00 (expected: 0xd00)
501 04:50:22.040694 header.flags = 0x0
502 04:50:22.047558 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 04:50:22.063762 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
504 04:50:22.071434 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 04:50:22.075508 dram_init: ddr_geometry: 2
506 04:50:22.076120 [EMI] MDL number = 2
507 04:50:22.079113 [EMI] Get MDL freq = 0
508 04:50:22.079720 dram_init: ddr_type: 0
509 04:50:22.082215 is_discrete_lpddr4: 1
510 04:50:22.085678 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 04:50:22.086201
512 04:50:22.086584
513 04:50:22.089204 [Bian_co] ETT version 0.0.0.1
514 04:50:22.092174 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 04:50:22.092659
516 04:50:22.095649 dramc_set_vcore_voltage set vcore to 650000
517 04:50:22.099622 Read voltage for 800, 4
518 04:50:22.100214 Vio18 = 0
519 04:50:22.102203 Vcore = 650000
520 04:50:22.102675 Vdram = 0
521 04:50:22.103050 Vddq = 0
522 04:50:22.103397 Vmddr = 0
523 04:50:22.105748 dram_init: config_dvfs: 1
524 04:50:22.112227 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 04:50:22.115650 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 04:50:22.118930 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 04:50:22.122224 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 04:50:22.129288 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 04:50:22.132584 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 04:50:22.133184 MEM_TYPE=3, freq_sel=18
531 04:50:22.135878 sv_algorithm_assistance_LP4_1600
532 04:50:22.139098 ============ PULL DRAM RESETB DOWN ============
533 04:50:22.146349 ========== PULL DRAM RESETB DOWN end =========
534 04:50:22.150017 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 04:50:22.153879 ===================================
536 04:50:22.154403 LPDDR4 DRAM CONFIGURATION
537 04:50:22.157640 ===================================
538 04:50:22.161053 EX_ROW_EN[0] = 0x0
539 04:50:22.161540 EX_ROW_EN[1] = 0x0
540 04:50:22.164388 LP4Y_EN = 0x0
541 04:50:22.164988 WORK_FSP = 0x0
542 04:50:22.167895 WL = 0x2
543 04:50:22.171459 RL = 0x2
544 04:50:22.172045 BL = 0x2
545 04:50:22.174392 RPST = 0x0
546 04:50:22.174869 RD_PRE = 0x0
547 04:50:22.177602 WR_PRE = 0x1
548 04:50:22.178101 WR_PST = 0x0
549 04:50:22.180643 DBI_WR = 0x0
550 04:50:22.181119 DBI_RD = 0x0
551 04:50:22.184678 OTF = 0x1
552 04:50:22.187884 ===================================
553 04:50:22.190661 ===================================
554 04:50:22.191145 ANA top config
555 04:50:22.194589 ===================================
556 04:50:22.197674 DLL_ASYNC_EN = 0
557 04:50:22.201172 ALL_SLAVE_EN = 1
558 04:50:22.201757 NEW_RANK_MODE = 1
559 04:50:22.204748 DLL_IDLE_MODE = 1
560 04:50:22.208227 LP45_APHY_COMB_EN = 1
561 04:50:22.211006 TX_ODT_DIS = 1
562 04:50:22.211494 NEW_8X_MODE = 1
563 04:50:22.214637 ===================================
564 04:50:22.217539 ===================================
565 04:50:22.220903 data_rate = 1600
566 04:50:22.224267 CKR = 1
567 04:50:22.227832 DQ_P2S_RATIO = 8
568 04:50:22.231145 ===================================
569 04:50:22.234574 CA_P2S_RATIO = 8
570 04:50:22.238120 DQ_CA_OPEN = 0
571 04:50:22.238704 DQ_SEMI_OPEN = 0
572 04:50:22.241124 CA_SEMI_OPEN = 0
573 04:50:22.244555 CA_FULL_RATE = 0
574 04:50:22.247719 DQ_CKDIV4_EN = 1
575 04:50:22.250744 CA_CKDIV4_EN = 1
576 04:50:22.254459 CA_PREDIV_EN = 0
577 04:50:22.254946 PH8_DLY = 0
578 04:50:22.257608 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 04:50:22.260972 DQ_AAMCK_DIV = 4
580 04:50:22.264633 CA_AAMCK_DIV = 4
581 04:50:22.268279 CA_ADMCK_DIV = 4
582 04:50:22.271217 DQ_TRACK_CA_EN = 0
583 04:50:22.271807 CA_PICK = 800
584 04:50:22.274281 CA_MCKIO = 800
585 04:50:22.277716 MCKIO_SEMI = 0
586 04:50:22.280791 PLL_FREQ = 3068
587 04:50:22.284488 DQ_UI_PI_RATIO = 32
588 04:50:22.287678 CA_UI_PI_RATIO = 0
589 04:50:22.291083 ===================================
590 04:50:22.294024 ===================================
591 04:50:22.294797 memory_type:LPDDR4
592 04:50:22.297426 GP_NUM : 10
593 04:50:22.300715 SRAM_EN : 1
594 04:50:22.301210 MD32_EN : 0
595 04:50:22.304321 ===================================
596 04:50:22.307892 [ANA_INIT] >>>>>>>>>>>>>>
597 04:50:22.311710 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 04:50:22.315580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 04:50:22.318677 ===================================
600 04:50:22.319183 data_rate = 1600,PCW = 0X7600
601 04:50:22.322593 ===================================
602 04:50:22.326640 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 04:50:22.333431 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 04:50:22.337307 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 04:50:22.341375 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 04:50:22.344584 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 04:50:22.347864 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 04:50:22.351100 [ANA_INIT] flow start
609 04:50:22.354201 [ANA_INIT] PLL >>>>>>>>
610 04:50:22.354699 [ANA_INIT] PLL <<<<<<<<
611 04:50:22.357882 [ANA_INIT] MIDPI >>>>>>>>
612 04:50:22.361131 [ANA_INIT] MIDPI <<<<<<<<
613 04:50:22.361610 [ANA_INIT] DLL >>>>>>>>
614 04:50:22.364437 [ANA_INIT] flow end
615 04:50:22.367700 ============ LP4 DIFF to SE enter ============
616 04:50:22.370908 ============ LP4 DIFF to SE exit ============
617 04:50:22.374485 [ANA_INIT] <<<<<<<<<<<<<
618 04:50:22.377801 [Flow] Enable top DCM control >>>>>
619 04:50:22.381268 [Flow] Enable top DCM control <<<<<
620 04:50:22.384357 Enable DLL master slave shuffle
621 04:50:22.391540 ==============================================================
622 04:50:22.392040 Gating Mode config
623 04:50:22.397801 ==============================================================
624 04:50:22.398284 Config description:
625 04:50:22.408193 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 04:50:22.414615 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 04:50:22.421132 SELPH_MODE 0: By rank 1: By Phase
628 04:50:22.424963 ==============================================================
629 04:50:22.427853 GAT_TRACK_EN = 1
630 04:50:22.431298 RX_GATING_MODE = 2
631 04:50:22.434649 RX_GATING_TRACK_MODE = 2
632 04:50:22.437885 SELPH_MODE = 1
633 04:50:22.441377 PICG_EARLY_EN = 1
634 04:50:22.444689 VALID_LAT_VALUE = 1
635 04:50:22.448366 ==============================================================
636 04:50:22.451707 Enter into Gating configuration >>>>
637 04:50:22.454881 Exit from Gating configuration <<<<
638 04:50:22.457924 Enter into DVFS_PRE_config >>>>>
639 04:50:22.471901 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 04:50:22.475241 Exit from DVFS_PRE_config <<<<<
641 04:50:22.477879 Enter into PICG configuration >>>>
642 04:50:22.478417 Exit from PICG configuration <<<<
643 04:50:22.481808 [RX_INPUT] configuration >>>>>
644 04:50:22.485077 [RX_INPUT] configuration <<<<<
645 04:50:22.492094 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 04:50:22.494853 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 04:50:22.501549 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 04:50:22.508440 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 04:50:22.514686 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 04:50:22.521596 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 04:50:22.525367 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 04:50:22.528718 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 04:50:22.532314 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 04:50:22.536645 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 04:50:22.539345 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 04:50:22.546544 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 04:50:22.550397 ===================================
658 04:50:22.550881 LPDDR4 DRAM CONFIGURATION
659 04:50:22.553861 ===================================
660 04:50:22.557930 EX_ROW_EN[0] = 0x0
661 04:50:22.558555 EX_ROW_EN[1] = 0x0
662 04:50:22.561560 LP4Y_EN = 0x0
663 04:50:22.562305 WORK_FSP = 0x0
664 04:50:22.565520 WL = 0x2
665 04:50:22.566057 RL = 0x2
666 04:50:22.568888 BL = 0x2
667 04:50:22.569383 RPST = 0x0
668 04:50:22.569866 RD_PRE = 0x0
669 04:50:22.572186 WR_PRE = 0x1
670 04:50:22.572674 WR_PST = 0x0
671 04:50:22.576133 DBI_WR = 0x0
672 04:50:22.576624 DBI_RD = 0x0
673 04:50:22.579928 OTF = 0x1
674 04:50:22.583456 ===================================
675 04:50:22.586917 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 04:50:22.591149 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 04:50:22.594802 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 04:50:22.598317 ===================================
679 04:50:22.602631 LPDDR4 DRAM CONFIGURATION
680 04:50:22.603228 ===================================
681 04:50:22.606117 EX_ROW_EN[0] = 0x10
682 04:50:22.609505 EX_ROW_EN[1] = 0x0
683 04:50:22.610036 LP4Y_EN = 0x0
684 04:50:22.613365 WORK_FSP = 0x0
685 04:50:22.613936 WL = 0x2
686 04:50:22.614456 RL = 0x2
687 04:50:22.617124 BL = 0x2
688 04:50:22.617613 RPST = 0x0
689 04:50:22.621013 RD_PRE = 0x0
690 04:50:22.621571 WR_PRE = 0x1
691 04:50:22.624723 WR_PST = 0x0
692 04:50:22.625313 DBI_WR = 0x0
693 04:50:22.628871 DBI_RD = 0x0
694 04:50:22.629456 OTF = 0x1
695 04:50:22.632035 ===================================
696 04:50:22.639733 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 04:50:22.643076 nWR fixed to 40
698 04:50:22.643632 [ModeRegInit_LP4] CH0 RK0
699 04:50:22.646879 [ModeRegInit_LP4] CH0 RK1
700 04:50:22.650031 [ModeRegInit_LP4] CH1 RK0
701 04:50:22.650532 [ModeRegInit_LP4] CH1 RK1
702 04:50:22.653777 match AC timing 13
703 04:50:22.658024 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 04:50:22.660960 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 04:50:22.664868 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 04:50:22.672546 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 04:50:22.675865 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 04:50:22.676346 [EMI DOE] emi_dcm 0
709 04:50:22.679957 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 04:50:22.683705 ==
711 04:50:22.684190 Dram Type= 6, Freq= 0, CH_0, rank 0
712 04:50:22.687433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 04:50:22.691178 ==
714 04:50:22.694653 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 04:50:22.701599 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 04:50:22.709977 [CA 0] Center 38 (7~69) winsize 63
717 04:50:22.713384 [CA 1] Center 38 (7~69) winsize 63
718 04:50:22.716743 [CA 2] Center 35 (5~66) winsize 62
719 04:50:22.719958 [CA 3] Center 35 (5~66) winsize 62
720 04:50:22.724182 [CA 4] Center 34 (4~65) winsize 62
721 04:50:22.727769 [CA 5] Center 33 (3~64) winsize 62
722 04:50:22.728260
723 04:50:22.731012 [CmdBusTrainingLP45] Vref(ca) range 1: 32
724 04:50:22.731505
725 04:50:22.734757 [CATrainingPosCal] consider 1 rank data
726 04:50:22.738562 u2DelayCellTimex100 = 270/100 ps
727 04:50:22.742085 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
728 04:50:22.746300 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 04:50:22.749679 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 04:50:22.753415 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
731 04:50:22.757387 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
732 04:50:22.758017 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 04:50:22.760672
734 04:50:22.764408 CA PerBit enable=1, Macro0, CA PI delay=33
735 04:50:22.764902
736 04:50:22.765388 [CBTSetCACLKResult] CA Dly = 33
737 04:50:22.768229 CS Dly: 6 (0~37)
738 04:50:22.768719 ==
739 04:50:22.771675 Dram Type= 6, Freq= 0, CH_0, rank 1
740 04:50:22.775333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 04:50:22.775929 ==
742 04:50:22.779212 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 04:50:22.785662 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 04:50:22.796272 [CA 0] Center 38 (7~69) winsize 63
745 04:50:22.799628 [CA 1] Center 38 (8~69) winsize 62
746 04:50:22.802849 [CA 2] Center 36 (6~67) winsize 62
747 04:50:22.806007 [CA 3] Center 35 (5~66) winsize 62
748 04:50:22.809686 [CA 4] Center 35 (4~66) winsize 63
749 04:50:22.812660 [CA 5] Center 34 (4~65) winsize 62
750 04:50:22.813146
751 04:50:22.816257 [CmdBusTrainingLP45] Vref(ca) range 1: 34
752 04:50:22.816848
753 04:50:22.819337 [CATrainingPosCal] consider 2 rank data
754 04:50:22.822566 u2DelayCellTimex100 = 270/100 ps
755 04:50:22.826432 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 04:50:22.829482 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
757 04:50:22.836350 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 04:50:22.839300 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 04:50:22.842531 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 04:50:22.846167 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 04:50:22.846704
762 04:50:22.849266 CA PerBit enable=1, Macro0, CA PI delay=34
763 04:50:22.849750
764 04:50:22.852935 [CBTSetCACLKResult] CA Dly = 34
765 04:50:22.853526 CS Dly: 6 (0~38)
766 04:50:22.853913
767 04:50:22.856368 ----->DramcWriteLeveling(PI) begin...
768 04:50:22.859603 ==
769 04:50:22.860087 Dram Type= 6, Freq= 0, CH_0, rank 0
770 04:50:22.866482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 04:50:22.866971 ==
772 04:50:22.869424 Write leveling (Byte 0): 32 => 32
773 04:50:22.872797 Write leveling (Byte 1): 31 => 31
774 04:50:22.873421 DramcWriteLeveling(PI) end<-----
775 04:50:22.876228
776 04:50:22.876704 ==
777 04:50:22.879311 Dram Type= 6, Freq= 0, CH_0, rank 0
778 04:50:22.883002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 04:50:22.883502 ==
780 04:50:22.886637 [Gating] SW mode calibration
781 04:50:22.893777 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 04:50:22.897693 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 04:50:22.901527 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 04:50:22.904549 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
785 04:50:22.911514 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 04:50:22.914441 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 04:50:22.918944 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 04:50:22.926067 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 04:50:22.928930 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 04:50:22.932644 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 04:50:22.935338 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 04:50:22.942245 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 04:50:22.945568 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 04:50:22.948596 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 04:50:22.955728 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 04:50:22.959103 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 04:50:22.962419 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 04:50:22.969252 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 04:50:22.972145 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 04:50:22.975244 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
801 04:50:22.982052 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
802 04:50:22.985382 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 04:50:22.988782 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 04:50:22.995174 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 04:50:22.999078 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 04:50:23.001810 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 04:50:23.008685 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 04:50:23.012262 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
809 04:50:23.015916 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
810 04:50:23.022599 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
811 04:50:23.025835 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 04:50:23.029170 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 04:50:23.032716 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 04:50:23.038521 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 04:50:23.042120 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 04:50:23.045875 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
817 04:50:23.052507 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
818 04:50:23.055396 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
819 04:50:23.058767 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 04:50:23.065471 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 04:50:23.069005 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 04:50:23.072358 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 04:50:23.078832 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 04:50:23.082060 0 11 4 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
825 04:50:23.085233 0 11 8 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
826 04:50:23.092417 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
827 04:50:23.095683 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 04:50:23.098695 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 04:50:23.105423 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 04:50:23.108618 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 04:50:23.112006 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 04:50:23.118642 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
833 04:50:23.121996 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
834 04:50:23.125515 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 04:50:23.129179 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 04:50:23.135157 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 04:50:23.138629 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 04:50:23.142004 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 04:50:23.148944 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 04:50:23.152105 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 04:50:23.155360 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 04:50:23.162304 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 04:50:23.165617 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 04:50:23.169311 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 04:50:23.175538 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 04:50:23.179058 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 04:50:23.182368 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
848 04:50:23.189249 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
849 04:50:23.192496 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 04:50:23.195643 Total UI for P1: 0, mck2ui 16
851 04:50:23.198880 best dqsien dly found for B0: ( 0, 14, 2)
852 04:50:23.202264 Total UI for P1: 0, mck2ui 16
853 04:50:23.205465 best dqsien dly found for B1: ( 0, 14, 6)
854 04:50:23.208908 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
855 04:50:23.212188 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
856 04:50:23.212675
857 04:50:23.215478 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
858 04:50:23.218932 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
859 04:50:23.222026 [Gating] SW calibration Done
860 04:50:23.222507 ==
861 04:50:23.225411 Dram Type= 6, Freq= 0, CH_0, rank 0
862 04:50:23.228861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
863 04:50:23.229468 ==
864 04:50:23.232110 RX Vref Scan: 0
865 04:50:23.232699
866 04:50:23.233083 RX Vref 0 -> 0, step: 1
867 04:50:23.235534
868 04:50:23.236014 RX Delay -130 -> 252, step: 16
869 04:50:23.242841 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
870 04:50:23.245815 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
871 04:50:23.249288 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
872 04:50:23.252772 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
873 04:50:23.255754 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
874 04:50:23.259652 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
875 04:50:23.266028 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
876 04:50:23.269250 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
877 04:50:23.272619 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
878 04:50:23.275926 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
879 04:50:23.279026 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
880 04:50:23.286176 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
881 04:50:23.288893 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
882 04:50:23.292467 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
883 04:50:23.295885 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
884 04:50:23.302677 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
885 04:50:23.303283 ==
886 04:50:23.305999 Dram Type= 6, Freq= 0, CH_0, rank 0
887 04:50:23.308986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
888 04:50:23.309794 ==
889 04:50:23.310562 DQS Delay:
890 04:50:23.312350 DQS0 = 0, DQS1 = 0
891 04:50:23.313071 DQM Delay:
892 04:50:23.315718 DQM0 = 91, DQM1 = 79
893 04:50:23.316253 DQ Delay:
894 04:50:23.319360 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
895 04:50:23.322217 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
896 04:50:23.325495 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
897 04:50:23.328794 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
898 04:50:23.329309
899 04:50:23.329692
900 04:50:23.330088 ==
901 04:50:23.332555 Dram Type= 6, Freq= 0, CH_0, rank 0
902 04:50:23.335494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 04:50:23.336004 ==
904 04:50:23.336638
905 04:50:23.339074
906 04:50:23.339569 TX Vref Scan disable
907 04:50:23.342202 == TX Byte 0 ==
908 04:50:23.345842 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
909 04:50:23.349397 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
910 04:50:23.352391 == TX Byte 1 ==
911 04:50:23.355643 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
912 04:50:23.359282 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
913 04:50:23.359759 ==
914 04:50:23.362510 Dram Type= 6, Freq= 0, CH_0, rank 0
915 04:50:23.369142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
916 04:50:23.369718 ==
917 04:50:23.380792 TX Vref=22, minBit 6, minWin=27, winSum=443
918 04:50:23.384206 TX Vref=24, minBit 6, minWin=27, winSum=444
919 04:50:23.387625 TX Vref=26, minBit 8, minWin=27, winSum=444
920 04:50:23.391251 TX Vref=28, minBit 8, minWin=27, winSum=453
921 04:50:23.393993 TX Vref=30, minBit 6, minWin=28, winSum=457
922 04:50:23.397104 TX Vref=32, minBit 10, minWin=27, winSum=457
923 04:50:23.404495 [TxChooseVref] Worse bit 6, Min win 28, Win sum 457, Final Vref 30
924 04:50:23.405080
925 04:50:23.407937 Final TX Range 1 Vref 30
926 04:50:23.408526
927 04:50:23.408912 ==
928 04:50:23.410592 Dram Type= 6, Freq= 0, CH_0, rank 0
929 04:50:23.414427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 04:50:23.415181 ==
931 04:50:23.415796
932 04:50:23.416306
933 04:50:23.417584 TX Vref Scan disable
934 04:50:23.420933 == TX Byte 0 ==
935 04:50:23.423944 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
936 04:50:23.427580 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
937 04:50:23.430991 == TX Byte 1 ==
938 04:50:23.434226 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
939 04:50:23.437248 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
940 04:50:23.437732
941 04:50:23.441102 [DATLAT]
942 04:50:23.441599 Freq=800, CH0 RK0
943 04:50:23.442063
944 04:50:23.444293 DATLAT Default: 0xa
945 04:50:23.444879 0, 0xFFFF, sum = 0
946 04:50:23.447135 1, 0xFFFF, sum = 0
947 04:50:23.447668 2, 0xFFFF, sum = 0
948 04:50:23.450697 3, 0xFFFF, sum = 0
949 04:50:23.451192 4, 0xFFFF, sum = 0
950 04:50:23.453788 5, 0xFFFF, sum = 0
951 04:50:23.454316 6, 0xFFFF, sum = 0
952 04:50:23.457490 7, 0xFFFF, sum = 0
953 04:50:23.458129 8, 0xFFFF, sum = 0
954 04:50:23.461044 9, 0x0, sum = 1
955 04:50:23.461637 10, 0x0, sum = 2
956 04:50:23.463959 11, 0x0, sum = 3
957 04:50:23.464465 12, 0x0, sum = 4
958 04:50:23.467417 best_step = 10
959 04:50:23.467906
960 04:50:23.468434 ==
961 04:50:23.470542 Dram Type= 6, Freq= 0, CH_0, rank 0
962 04:50:23.474169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
963 04:50:23.474664 ==
964 04:50:23.477283 RX Vref Scan: 1
965 04:50:23.477866
966 04:50:23.478388 Set Vref Range= 32 -> 127
967 04:50:23.478846
968 04:50:23.480828 RX Vref 32 -> 127, step: 1
969 04:50:23.481318
970 04:50:23.484204 RX Delay -95 -> 252, step: 8
971 04:50:23.484788
972 04:50:23.487798 Set Vref, RX VrefLevel [Byte0]: 32
973 04:50:23.490971 [Byte1]: 32
974 04:50:23.491559
975 04:50:23.494187 Set Vref, RX VrefLevel [Byte0]: 33
976 04:50:23.497675 [Byte1]: 33
977 04:50:23.501111
978 04:50:23.501702 Set Vref, RX VrefLevel [Byte0]: 34
979 04:50:23.504351 [Byte1]: 34
980 04:50:23.508886
981 04:50:23.509472 Set Vref, RX VrefLevel [Byte0]: 35
982 04:50:23.511622 [Byte1]: 35
983 04:50:23.515831
984 04:50:23.516324 Set Vref, RX VrefLevel [Byte0]: 36
985 04:50:23.519376 [Byte1]: 36
986 04:50:23.523372
987 04:50:23.523862 Set Vref, RX VrefLevel [Byte0]: 37
988 04:50:23.527059 [Byte1]: 37
989 04:50:23.531373
990 04:50:23.531916 Set Vref, RX VrefLevel [Byte0]: 38
991 04:50:23.534492 [Byte1]: 38
992 04:50:23.538887
993 04:50:23.539375 Set Vref, RX VrefLevel [Byte0]: 39
994 04:50:23.542284 [Byte1]: 39
995 04:50:23.546786
996 04:50:23.547332 Set Vref, RX VrefLevel [Byte0]: 40
997 04:50:23.550104 [Byte1]: 40
998 04:50:23.554313
999 04:50:23.554882 Set Vref, RX VrefLevel [Byte0]: 41
1000 04:50:23.557876 [Byte1]: 41
1001 04:50:23.562492
1002 04:50:23.563089 Set Vref, RX VrefLevel [Byte0]: 42
1003 04:50:23.565753 [Byte1]: 42
1004 04:50:23.569638
1005 04:50:23.570338 Set Vref, RX VrefLevel [Byte0]: 43
1006 04:50:23.573317 [Byte1]: 43
1007 04:50:23.577328
1008 04:50:23.577982 Set Vref, RX VrefLevel [Byte0]: 44
1009 04:50:23.580999 [Byte1]: 44
1010 04:50:23.584545
1011 04:50:23.585154 Set Vref, RX VrefLevel [Byte0]: 45
1012 04:50:23.588333 [Byte1]: 45
1013 04:50:23.592585
1014 04:50:23.593111 Set Vref, RX VrefLevel [Byte0]: 46
1015 04:50:23.595631 [Byte1]: 46
1016 04:50:23.599532
1017 04:50:23.599970 Set Vref, RX VrefLevel [Byte0]: 47
1018 04:50:23.603069 [Byte1]: 47
1019 04:50:23.607155
1020 04:50:23.607709 Set Vref, RX VrefLevel [Byte0]: 48
1021 04:50:23.610719 [Byte1]: 48
1022 04:50:23.614915
1023 04:50:23.615466 Set Vref, RX VrefLevel [Byte0]: 49
1024 04:50:23.618159 [Byte1]: 49
1025 04:50:23.622754
1026 04:50:23.623276 Set Vref, RX VrefLevel [Byte0]: 50
1027 04:50:23.626219 [Byte1]: 50
1028 04:50:23.630165
1029 04:50:23.630680 Set Vref, RX VrefLevel [Byte0]: 51
1030 04:50:23.633671 [Byte1]: 51
1031 04:50:23.637680
1032 04:50:23.638172 Set Vref, RX VrefLevel [Byte0]: 52
1033 04:50:23.641333 [Byte1]: 52
1034 04:50:23.645248
1035 04:50:23.645665 Set Vref, RX VrefLevel [Byte0]: 53
1036 04:50:23.648574 [Byte1]: 53
1037 04:50:23.653022
1038 04:50:23.653544 Set Vref, RX VrefLevel [Byte0]: 54
1039 04:50:23.656028 [Byte1]: 54
1040 04:50:23.660369
1041 04:50:23.660906 Set Vref, RX VrefLevel [Byte0]: 55
1042 04:50:23.663958 [Byte1]: 55
1043 04:50:23.668005
1044 04:50:23.668610 Set Vref, RX VrefLevel [Byte0]: 56
1045 04:50:23.671526 [Byte1]: 56
1046 04:50:23.675339
1047 04:50:23.675758 Set Vref, RX VrefLevel [Byte0]: 57
1048 04:50:23.678547 [Byte1]: 57
1049 04:50:23.683205
1050 04:50:23.683716 Set Vref, RX VrefLevel [Byte0]: 58
1051 04:50:23.686460 [Byte1]: 58
1052 04:50:23.690812
1053 04:50:23.691325 Set Vref, RX VrefLevel [Byte0]: 59
1054 04:50:23.694392 [Byte1]: 59
1055 04:50:23.698523
1056 04:50:23.699081 Set Vref, RX VrefLevel [Byte0]: 60
1057 04:50:23.702012 [Byte1]: 60
1058 04:50:23.706505
1059 04:50:23.707022 Set Vref, RX VrefLevel [Byte0]: 61
1060 04:50:23.709199 [Byte1]: 61
1061 04:50:23.714060
1062 04:50:23.714575 Set Vref, RX VrefLevel [Byte0]: 62
1063 04:50:23.716674 [Byte1]: 62
1064 04:50:23.721313
1065 04:50:23.721834 Set Vref, RX VrefLevel [Byte0]: 63
1066 04:50:23.724250 [Byte1]: 63
1067 04:50:23.729281
1068 04:50:23.729799 Set Vref, RX VrefLevel [Byte0]: 64
1069 04:50:23.731975 [Byte1]: 64
1070 04:50:23.736292
1071 04:50:23.736811 Set Vref, RX VrefLevel [Byte0]: 65
1072 04:50:23.739682 [Byte1]: 65
1073 04:50:23.744099
1074 04:50:23.744626 Set Vref, RX VrefLevel [Byte0]: 66
1075 04:50:23.747057 [Byte1]: 66
1076 04:50:23.751388
1077 04:50:23.751804 Set Vref, RX VrefLevel [Byte0]: 67
1078 04:50:23.755104 [Byte1]: 67
1079 04:50:23.759156
1080 04:50:23.759581 Set Vref, RX VrefLevel [Byte0]: 68
1081 04:50:23.762653 [Byte1]: 68
1082 04:50:23.766591
1083 04:50:23.767234 Set Vref, RX VrefLevel [Byte0]: 69
1084 04:50:23.770213 [Byte1]: 69
1085 04:50:23.774115
1086 04:50:23.774583 Set Vref, RX VrefLevel [Byte0]: 70
1087 04:50:23.777618 [Byte1]: 70
1088 04:50:23.782030
1089 04:50:23.782446 Set Vref, RX VrefLevel [Byte0]: 71
1090 04:50:23.785622 [Byte1]: 71
1091 04:50:23.789817
1092 04:50:23.790381 Set Vref, RX VrefLevel [Byte0]: 72
1093 04:50:23.793176 [Byte1]: 72
1094 04:50:23.796904
1095 04:50:23.797421 Set Vref, RX VrefLevel [Byte0]: 73
1096 04:50:23.800589 [Byte1]: 73
1097 04:50:23.805010
1098 04:50:23.805521 Set Vref, RX VrefLevel [Byte0]: 74
1099 04:50:23.808148 [Byte1]: 74
1100 04:50:23.812330
1101 04:50:23.812752 Set Vref, RX VrefLevel [Byte0]: 75
1102 04:50:23.815437 [Byte1]: 75
1103 04:50:23.820180
1104 04:50:23.820692 Set Vref, RX VrefLevel [Byte0]: 76
1105 04:50:23.823086 [Byte1]: 76
1106 04:50:23.827602
1107 04:50:23.828117 Set Vref, RX VrefLevel [Byte0]: 77
1108 04:50:23.830719 [Byte1]: 77
1109 04:50:23.835171
1110 04:50:23.835688 Set Vref, RX VrefLevel [Byte0]: 78
1111 04:50:23.838529 [Byte1]: 78
1112 04:50:23.843127
1113 04:50:23.843652 Final RX Vref Byte 0 = 62 to rank0
1114 04:50:23.846178 Final RX Vref Byte 1 = 52 to rank0
1115 04:50:23.849425 Final RX Vref Byte 0 = 62 to rank1
1116 04:50:23.853386 Final RX Vref Byte 1 = 52 to rank1==
1117 04:50:23.856545 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 04:50:23.859475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 04:50:23.862857 ==
1120 04:50:23.863459 DQS Delay:
1121 04:50:23.863798 DQS0 = 0, DQS1 = 0
1122 04:50:23.866324 DQM Delay:
1123 04:50:23.866745 DQM0 = 93, DQM1 = 81
1124 04:50:23.869634 DQ Delay:
1125 04:50:23.872731 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1126 04:50:23.873217 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1127 04:50:23.876184 DQ8 =76, DQ9 =72, DQ10 =80, DQ11 =76
1128 04:50:23.883175 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1129 04:50:23.883716
1130 04:50:23.884051
1131 04:50:23.889553 [DQSOSCAuto] RK0, (LSB)MR18= 0x3632, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
1132 04:50:23.893114 CH0 RK0: MR19=606, MR18=3632
1133 04:50:23.899526 CH0_RK0: MR19=0x606, MR18=0x3632, DQSOSC=396, MR23=63, INC=94, DEC=62
1134 04:50:23.899953
1135 04:50:23.902786 ----->DramcWriteLeveling(PI) begin...
1136 04:50:23.903296 ==
1137 04:50:23.906311 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 04:50:23.909730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 04:50:23.910248 ==
1140 04:50:23.913416 Write leveling (Byte 0): 31 => 31
1141 04:50:23.915971 Write leveling (Byte 1): 28 => 28
1142 04:50:23.919444 DramcWriteLeveling(PI) end<-----
1143 04:50:23.919987
1144 04:50:23.920354 ==
1145 04:50:23.923237 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 04:50:23.926526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 04:50:23.927097 ==
1148 04:50:23.929703 [Gating] SW mode calibration
1149 04:50:23.936301 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 04:50:23.942863 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 04:50:23.946121 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 04:50:23.949337 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 04:50:23.956132 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 04:50:23.959972 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 04:50:24.003430 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 04:50:24.004442 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 04:50:24.004875 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 04:50:24.005231 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 04:50:24.005573 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 04:50:24.006026 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 04:50:24.006402 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 04:50:24.006797 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 04:50:24.007135 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 04:50:24.007450 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 04:50:24.047774 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 04:50:24.048399 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 04:50:24.049223 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 04:50:24.049690 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1169 04:50:24.050094 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1170 04:50:24.050443 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 04:50:24.050776 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 04:50:24.051103 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 04:50:24.051425 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 04:50:24.051804 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 04:50:24.080442 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 04:50:24.081124 0 9 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
1177 04:50:24.081529 0 9 8 | B1->B0 | 2828 3433 | 1 1 | (0 0) (1 1)
1178 04:50:24.081882 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 04:50:24.082634 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 04:50:24.083019 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 04:50:24.083353 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 04:50:24.084398 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 04:50:24.088511 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1184 04:50:24.091175 0 10 4 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (1 0)
1185 04:50:24.094595 0 10 8 | B1->B0 | 2727 2323 | 1 0 | (1 0) (1 0)
1186 04:50:24.100999 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 04:50:24.104680 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 04:50:24.107769 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 04:50:24.114812 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 04:50:24.117996 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 04:50:24.121337 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 04:50:24.128097 0 11 4 | B1->B0 | 2525 3030 | 0 0 | (0 0) (1 1)
1193 04:50:24.131053 0 11 8 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
1194 04:50:24.134721 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 04:50:24.138377 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 04:50:24.146398 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 04:50:24.149967 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 04:50:24.153752 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 04:50:24.156874 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 04:50:24.160070 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1201 04:50:24.167714 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 04:50:24.170709 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 04:50:24.174439 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 04:50:24.177713 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 04:50:24.184298 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 04:50:24.187922 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 04:50:24.190732 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 04:50:24.197603 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 04:50:24.200789 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 04:50:24.204241 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 04:50:24.210911 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 04:50:24.214273 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 04:50:24.217892 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 04:50:24.224585 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 04:50:24.227587 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 04:50:24.230910 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1217 04:50:24.237848 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 04:50:24.238444 Total UI for P1: 0, mck2ui 16
1219 04:50:24.241354 best dqsien dly found for B0: ( 0, 14, 4)
1220 04:50:24.244815 Total UI for P1: 0, mck2ui 16
1221 04:50:24.248302 best dqsien dly found for B1: ( 0, 14, 6)
1222 04:50:24.251176 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1223 04:50:24.258096 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1224 04:50:24.258656
1225 04:50:24.261063 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1226 04:50:24.264681 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1227 04:50:24.267906 [Gating] SW calibration Done
1228 04:50:24.268371 ==
1229 04:50:24.271327 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 04:50:24.274351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1231 04:50:24.274827 ==
1232 04:50:24.275195 RX Vref Scan: 0
1233 04:50:24.275539
1234 04:50:24.278182 RX Vref 0 -> 0, step: 1
1235 04:50:24.278649
1236 04:50:24.281572 RX Delay -130 -> 252, step: 16
1237 04:50:24.284900 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1238 04:50:24.288087 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1239 04:50:24.294573 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1240 04:50:24.297914 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1241 04:50:24.301192 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1242 04:50:24.304740 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1243 04:50:24.307925 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1244 04:50:24.314607 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1245 04:50:24.318026 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1246 04:50:24.321323 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1247 04:50:24.324323 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1248 04:50:24.327559 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1249 04:50:24.334617 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
1250 04:50:24.337721 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1251 04:50:24.341202 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1252 04:50:24.344499 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1253 04:50:24.345109 ==
1254 04:50:24.347739 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 04:50:24.354538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1256 04:50:24.354978 ==
1257 04:50:24.355344 DQS Delay:
1258 04:50:24.356000 DQS0 = 0, DQS1 = 0
1259 04:50:24.357721 DQM Delay:
1260 04:50:24.358186 DQM0 = 92, DQM1 = 81
1261 04:50:24.360898 DQ Delay:
1262 04:50:24.364640 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1263 04:50:24.367667 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1264 04:50:24.371197 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1265 04:50:24.374691 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1266 04:50:24.375117
1267 04:50:24.375456
1268 04:50:24.375767 ==
1269 04:50:24.377839 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 04:50:24.381448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 04:50:24.381969 ==
1272 04:50:24.382331
1273 04:50:24.382645
1274 04:50:24.384914 TX Vref Scan disable
1275 04:50:24.385456 == TX Byte 0 ==
1276 04:50:24.391701 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1277 04:50:24.394337 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1278 04:50:24.394763 == TX Byte 1 ==
1279 04:50:24.401545 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1280 04:50:24.404840 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1281 04:50:24.405417 ==
1282 04:50:24.408096 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 04:50:24.411420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 04:50:24.411892 ==
1285 04:50:24.425361 TX Vref=22, minBit 8, minWin=27, winSum=448
1286 04:50:24.428784 TX Vref=24, minBit 8, minWin=27, winSum=449
1287 04:50:24.431847 TX Vref=26, minBit 8, minWin=27, winSum=449
1288 04:50:24.435462 TX Vref=28, minBit 4, minWin=28, winSum=455
1289 04:50:24.439073 TX Vref=30, minBit 1, minWin=28, winSum=454
1290 04:50:24.442108 TX Vref=32, minBit 4, minWin=28, winSum=457
1291 04:50:24.449172 [TxChooseVref] Worse bit 4, Min win 28, Win sum 457, Final Vref 32
1292 04:50:24.449785
1293 04:50:24.452303 Final TX Range 1 Vref 32
1294 04:50:24.452756
1295 04:50:24.453108 ==
1296 04:50:24.455598 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 04:50:24.458950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 04:50:24.459403 ==
1299 04:50:24.459757
1300 04:50:24.461920
1301 04:50:24.462345 TX Vref Scan disable
1302 04:50:24.465384 == TX Byte 0 ==
1303 04:50:24.468637 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1304 04:50:24.472227 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1305 04:50:24.475569 == TX Byte 1 ==
1306 04:50:24.478866 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1307 04:50:24.481992 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1308 04:50:24.485643
1309 04:50:24.486209 [DATLAT]
1310 04:50:24.486547 Freq=800, CH0 RK1
1311 04:50:24.486858
1312 04:50:24.488460 DATLAT Default: 0xa
1313 04:50:24.488950 0, 0xFFFF, sum = 0
1314 04:50:24.492419 1, 0xFFFF, sum = 0
1315 04:50:24.492946 2, 0xFFFF, sum = 0
1316 04:50:24.495747 3, 0xFFFF, sum = 0
1317 04:50:24.496283 4, 0xFFFF, sum = 0
1318 04:50:24.498888 5, 0xFFFF, sum = 0
1319 04:50:24.499313 6, 0xFFFF, sum = 0
1320 04:50:24.502067 7, 0xFFFF, sum = 0
1321 04:50:24.502518 8, 0xFFFF, sum = 0
1322 04:50:24.505830 9, 0x0, sum = 1
1323 04:50:24.506397 10, 0x0, sum = 2
1324 04:50:24.509247 11, 0x0, sum = 3
1325 04:50:24.509809 12, 0x0, sum = 4
1326 04:50:24.512346 best_step = 10
1327 04:50:24.512803
1328 04:50:24.513162 ==
1329 04:50:24.515413 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 04:50:24.518668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 04:50:24.519093 ==
1332 04:50:24.522283 RX Vref Scan: 0
1333 04:50:24.522698
1334 04:50:24.523024 RX Vref 0 -> 0, step: 1
1335 04:50:24.523333
1336 04:50:24.525673 RX Delay -95 -> 252, step: 8
1337 04:50:24.532272 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1338 04:50:24.535920 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1339 04:50:24.538974 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1340 04:50:24.542444 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1341 04:50:24.545637 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1342 04:50:24.552434 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1343 04:50:24.556004 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1344 04:50:24.559224 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1345 04:50:24.562367 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1346 04:50:24.565440 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1347 04:50:24.572395 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1348 04:50:24.575464 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1349 04:50:24.578593 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1350 04:50:24.582271 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1351 04:50:24.585705 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1352 04:50:24.592283 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1353 04:50:24.592858 ==
1354 04:50:24.595429 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 04:50:24.598684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 04:50:24.599140 ==
1357 04:50:24.599493 DQS Delay:
1358 04:50:24.602073 DQS0 = 0, DQS1 = 0
1359 04:50:24.602613 DQM Delay:
1360 04:50:24.605480 DQM0 = 90, DQM1 = 82
1361 04:50:24.606041 DQ Delay:
1362 04:50:24.609191 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1363 04:50:24.612666 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1364 04:50:24.615511 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =80
1365 04:50:24.618934 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1366 04:50:24.619497
1367 04:50:24.619854
1368 04:50:24.625429 [DQSOSCAuto] RK1, (LSB)MR18= 0x411a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1369 04:50:24.629193 CH0 RK1: MR19=606, MR18=411A
1370 04:50:24.635573 CH0_RK1: MR19=0x606, MR18=0x411A, DQSOSC=393, MR23=63, INC=95, DEC=63
1371 04:50:24.638835 [RxdqsGatingPostProcess] freq 800
1372 04:50:24.645562 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 04:50:24.648959 Pre-setting of DQS Precalculation
1374 04:50:24.652223 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1375 04:50:24.652706 ==
1376 04:50:24.655853 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 04:50:24.658973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 04:50:24.659429 ==
1379 04:50:24.665997 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 04:50:24.672381 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 04:50:24.680540 [CA 0] Center 36 (6~67) winsize 62
1382 04:50:24.683726 [CA 1] Center 36 (6~67) winsize 62
1383 04:50:24.687167 [CA 2] Center 34 (4~65) winsize 62
1384 04:50:24.690699 [CA 3] Center 34 (4~65) winsize 62
1385 04:50:24.693893 [CA 4] Center 34 (4~65) winsize 62
1386 04:50:24.697383 [CA 5] Center 33 (3~64) winsize 62
1387 04:50:24.697842
1388 04:50:24.700335 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1389 04:50:24.700900
1390 04:50:24.703605 [CATrainingPosCal] consider 1 rank data
1391 04:50:24.707222 u2DelayCellTimex100 = 270/100 ps
1392 04:50:24.710719 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1393 04:50:24.713861 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1394 04:50:24.720992 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1395 04:50:24.724200 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 04:50:24.727321 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1397 04:50:24.730481 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1398 04:50:24.730937
1399 04:50:24.733787 CA PerBit enable=1, Macro0, CA PI delay=33
1400 04:50:24.734393
1401 04:50:24.737516 [CBTSetCACLKResult] CA Dly = 33
1402 04:50:24.738103 CS Dly: 5 (0~36)
1403 04:50:24.738474 ==
1404 04:50:24.740378 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 04:50:24.747691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 04:50:24.748253 ==
1407 04:50:24.750568 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 04:50:24.757045 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 04:50:24.767041 [CA 0] Center 36 (6~67) winsize 62
1410 04:50:24.770082 [CA 1] Center 37 (6~68) winsize 63
1411 04:50:24.773126 [CA 2] Center 35 (5~66) winsize 62
1412 04:50:24.776398 [CA 3] Center 34 (4~65) winsize 62
1413 04:50:24.779927 [CA 4] Center 34 (4~65) winsize 62
1414 04:50:24.783213 [CA 5] Center 34 (4~65) winsize 62
1415 04:50:24.783667
1416 04:50:24.787007 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1417 04:50:24.787563
1418 04:50:24.790472 [CATrainingPosCal] consider 2 rank data
1419 04:50:24.793445 u2DelayCellTimex100 = 270/100 ps
1420 04:50:24.796520 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1421 04:50:24.799867 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1422 04:50:24.803894 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1423 04:50:24.807388 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 04:50:24.811397 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1425 04:50:24.815123 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1426 04:50:24.815684
1427 04:50:24.818845 CA PerBit enable=1, Macro0, CA PI delay=34
1428 04:50:24.819552
1429 04:50:24.822445 [CBTSetCACLKResult] CA Dly = 34
1430 04:50:24.826460 CS Dly: 6 (0~38)
1431 04:50:24.827146
1432 04:50:24.830052 ----->DramcWriteLeveling(PI) begin...
1433 04:50:24.830665 ==
1434 04:50:24.833680 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 04:50:24.836941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 04:50:24.837403 ==
1437 04:50:24.840523 Write leveling (Byte 0): 26 => 26
1438 04:50:24.840975 Write leveling (Byte 1): 28 => 28
1439 04:50:24.844143 DramcWriteLeveling(PI) end<-----
1440 04:50:24.844696
1441 04:50:24.845051 ==
1442 04:50:24.847627 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 04:50:24.853718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 04:50:24.854290 ==
1445 04:50:24.857151 [Gating] SW mode calibration
1446 04:50:24.864040 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 04:50:24.867436 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 04:50:24.873816 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1449 04:50:24.877474 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1450 04:50:24.881117 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 04:50:24.887318 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 04:50:24.890838 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 04:50:24.893992 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 04:50:24.897392 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 04:50:24.904278 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 04:50:24.907256 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 04:50:24.910489 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 04:50:24.917239 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 04:50:24.920577 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 04:50:24.924109 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 04:50:24.930734 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 04:50:24.934062 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 04:50:24.937194 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 04:50:24.944632 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1465 04:50:24.947338 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1466 04:50:24.950515 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 04:50:24.957421 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 04:50:24.960979 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 04:50:24.963991 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 04:50:24.967823 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 04:50:24.974019 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 04:50:24.977531 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 04:50:24.980964 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1474 04:50:24.987746 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 04:50:24.990885 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 04:50:24.994672 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 04:50:25.001185 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 04:50:25.004279 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 04:50:25.007828 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 04:50:25.014578 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1481 04:50:25.018068 0 10 4 | B1->B0 | 3232 2626 | 0 0 | (0 1) (0 0)
1482 04:50:25.020985 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 04:50:25.027665 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 04:50:25.031158 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 04:50:25.034291 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 04:50:25.040606 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 04:50:25.044143 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 04:50:25.047585 0 11 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
1489 04:50:25.054827 0 11 4 | B1->B0 | 2e2e 3535 | 0 0 | (0 0) (0 0)
1490 04:50:25.057636 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 04:50:25.061141 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 04:50:25.064197 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 04:50:25.070738 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 04:50:25.074111 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 04:50:25.077511 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 04:50:25.085100 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 04:50:25.087530 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1498 04:50:25.090523 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 04:50:25.097436 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 04:50:25.100745 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 04:50:25.103890 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 04:50:25.110759 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 04:50:25.114579 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 04:50:25.117568 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 04:50:25.124105 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 04:50:25.127651 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 04:50:25.131020 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 04:50:25.137694 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 04:50:25.141103 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 04:50:25.144097 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 04:50:25.150553 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 04:50:25.154154 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 04:50:25.157936 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1514 04:50:25.160933 Total UI for P1: 0, mck2ui 16
1515 04:50:25.164264 best dqsien dly found for B0: ( 0, 14, 2)
1516 04:50:25.167569 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 04:50:25.171235 Total UI for P1: 0, mck2ui 16
1518 04:50:25.174179 best dqsien dly found for B1: ( 0, 14, 4)
1519 04:50:25.177560 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1520 04:50:25.180756 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1521 04:50:25.184447
1522 04:50:25.187642 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1523 04:50:25.190856 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1524 04:50:25.194181 [Gating] SW calibration Done
1525 04:50:25.194639 ==
1526 04:50:25.197476 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 04:50:25.200867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 04:50:25.201430 ==
1529 04:50:25.201795 RX Vref Scan: 0
1530 04:50:25.202279
1531 04:50:25.204416 RX Vref 0 -> 0, step: 1
1532 04:50:25.204972
1533 04:50:25.207514 RX Delay -130 -> 252, step: 16
1534 04:50:25.210920 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1535 04:50:25.214138 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1536 04:50:25.220676 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1537 04:50:25.224739 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1538 04:50:25.227521 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1539 04:50:25.230943 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1540 04:50:25.234173 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1541 04:50:25.237703 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1542 04:50:25.244594 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1543 04:50:25.247772 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1544 04:50:25.251166 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1545 04:50:25.254173 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1546 04:50:25.261278 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1547 04:50:25.264601 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1548 04:50:25.267696 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1549 04:50:25.270829 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1550 04:50:25.271368 ==
1551 04:50:25.274855 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 04:50:25.277659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 04:50:25.281440 ==
1554 04:50:25.282050 DQS Delay:
1555 04:50:25.282426 DQS0 = 0, DQS1 = 0
1556 04:50:25.284467 DQM Delay:
1557 04:50:25.285027 DQM0 = 91, DQM1 = 85
1558 04:50:25.285396 DQ Delay:
1559 04:50:25.287990 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1560 04:50:25.291292 DQ4 =93, DQ5 =93, DQ6 =101, DQ7 =93
1561 04:50:25.294332 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =77
1562 04:50:25.297709 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1563 04:50:25.298214
1564 04:50:25.298579
1565 04:50:25.301243 ==
1566 04:50:25.305164 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 04:50:25.307756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 04:50:25.308332 ==
1569 04:50:25.308700
1570 04:50:25.309037
1571 04:50:25.311385 TX Vref Scan disable
1572 04:50:25.311845 == TX Byte 0 ==
1573 04:50:25.314671 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1574 04:50:25.320977 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1575 04:50:25.321441 == TX Byte 1 ==
1576 04:50:25.324303 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1577 04:50:25.331446 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1578 04:50:25.332035 ==
1579 04:50:25.334553 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 04:50:25.337786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 04:50:25.338287 ==
1582 04:50:25.351493 TX Vref=22, minBit 10, minWin=27, winSum=449
1583 04:50:25.354781 TX Vref=24, minBit 10, minWin=27, winSum=453
1584 04:50:25.357864 TX Vref=26, minBit 15, minWin=27, winSum=457
1585 04:50:25.361008 TX Vref=28, minBit 15, minWin=27, winSum=459
1586 04:50:25.364111 TX Vref=30, minBit 8, minWin=28, winSum=458
1587 04:50:25.370809 TX Vref=32, minBit 8, minWin=28, winSum=461
1588 04:50:25.374559 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 32
1589 04:50:25.375389
1590 04:50:25.377915 Final TX Range 1 Vref 32
1591 04:50:25.378441
1592 04:50:25.378818 ==
1593 04:50:25.380964 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 04:50:25.384922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 04:50:25.385433 ==
1596 04:50:25.385825
1597 04:50:25.386242
1598 04:50:25.388481 TX Vref Scan disable
1599 04:50:25.391656 == TX Byte 0 ==
1600 04:50:25.395105 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1601 04:50:25.398664 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1602 04:50:25.401578 == TX Byte 1 ==
1603 04:50:25.405105 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1604 04:50:25.408458 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1605 04:50:25.408975
1606 04:50:25.412121 [DATLAT]
1607 04:50:25.412743 Freq=800, CH1 RK0
1608 04:50:25.413226
1609 04:50:25.414853 DATLAT Default: 0xa
1610 04:50:25.415398 0, 0xFFFF, sum = 0
1611 04:50:25.418437 1, 0xFFFF, sum = 0
1612 04:50:25.418880 2, 0xFFFF, sum = 0
1613 04:50:25.421424 3, 0xFFFF, sum = 0
1614 04:50:25.421846 4, 0xFFFF, sum = 0
1615 04:50:25.425216 5, 0xFFFF, sum = 0
1616 04:50:25.425685 6, 0xFFFF, sum = 0
1617 04:50:25.428244 7, 0xFFFF, sum = 0
1618 04:50:25.428680 8, 0xFFFF, sum = 0
1619 04:50:25.431937 9, 0x0, sum = 1
1620 04:50:25.432392 10, 0x0, sum = 2
1621 04:50:25.435139 11, 0x0, sum = 3
1622 04:50:25.435562 12, 0x0, sum = 4
1623 04:50:25.438626 best_step = 10
1624 04:50:25.439093
1625 04:50:25.439447 ==
1626 04:50:25.441738 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 04:50:25.445052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 04:50:25.445536 ==
1629 04:50:25.448462 RX Vref Scan: 1
1630 04:50:25.448910
1631 04:50:25.449251 Set Vref Range= 32 -> 127
1632 04:50:25.449561
1633 04:50:25.451946 RX Vref 32 -> 127, step: 1
1634 04:50:25.452401
1635 04:50:25.455390 RX Delay -95 -> 252, step: 8
1636 04:50:25.455807
1637 04:50:25.458696 Set Vref, RX VrefLevel [Byte0]: 32
1638 04:50:25.461818 [Byte1]: 32
1639 04:50:25.462268
1640 04:50:25.465366 Set Vref, RX VrefLevel [Byte0]: 33
1641 04:50:25.468912 [Byte1]: 33
1642 04:50:25.469332
1643 04:50:25.472005 Set Vref, RX VrefLevel [Byte0]: 34
1644 04:50:25.475160 [Byte1]: 34
1645 04:50:25.479324
1646 04:50:25.479766 Set Vref, RX VrefLevel [Byte0]: 35
1647 04:50:25.482379 [Byte1]: 35
1648 04:50:25.486700
1649 04:50:25.487135 Set Vref, RX VrefLevel [Byte0]: 36
1650 04:50:25.489728 [Byte1]: 36
1651 04:50:25.494420
1652 04:50:25.494919 Set Vref, RX VrefLevel [Byte0]: 37
1653 04:50:25.497595 [Byte1]: 37
1654 04:50:25.501898
1655 04:50:25.502356 Set Vref, RX VrefLevel [Byte0]: 38
1656 04:50:25.505257 [Byte1]: 38
1657 04:50:25.509426
1658 04:50:25.510073 Set Vref, RX VrefLevel [Byte0]: 39
1659 04:50:25.512642 [Byte1]: 39
1660 04:50:25.517077
1661 04:50:25.517497 Set Vref, RX VrefLevel [Byte0]: 40
1662 04:50:25.520582 [Byte1]: 40
1663 04:50:25.524648
1664 04:50:25.525091 Set Vref, RX VrefLevel [Byte0]: 41
1665 04:50:25.527864 [Byte1]: 41
1666 04:50:25.532623
1667 04:50:25.533041 Set Vref, RX VrefLevel [Byte0]: 42
1668 04:50:25.535782 [Byte1]: 42
1669 04:50:25.540034
1670 04:50:25.540449 Set Vref, RX VrefLevel [Byte0]: 43
1671 04:50:25.543230 [Byte1]: 43
1672 04:50:25.547359
1673 04:50:25.547922 Set Vref, RX VrefLevel [Byte0]: 44
1674 04:50:25.551065 [Byte1]: 44
1675 04:50:25.555148
1676 04:50:25.555569 Set Vref, RX VrefLevel [Byte0]: 45
1677 04:50:25.558425 [Byte1]: 45
1678 04:50:25.562990
1679 04:50:25.563410 Set Vref, RX VrefLevel [Byte0]: 46
1680 04:50:25.569054 [Byte1]: 46
1681 04:50:25.569473
1682 04:50:25.572570 Set Vref, RX VrefLevel [Byte0]: 47
1683 04:50:25.575803 [Byte1]: 47
1684 04:50:25.576291
1685 04:50:25.578967 Set Vref, RX VrefLevel [Byte0]: 48
1686 04:50:25.582458 [Byte1]: 48
1687 04:50:25.582895
1688 04:50:25.585550 Set Vref, RX VrefLevel [Byte0]: 49
1689 04:50:25.589157 [Byte1]: 49
1690 04:50:25.593172
1691 04:50:25.593590 Set Vref, RX VrefLevel [Byte0]: 50
1692 04:50:25.596173 [Byte1]: 50
1693 04:50:25.600953
1694 04:50:25.601367 Set Vref, RX VrefLevel [Byte0]: 51
1695 04:50:25.604042 [Byte1]: 51
1696 04:50:25.608590
1697 04:50:25.609107 Set Vref, RX VrefLevel [Byte0]: 52
1698 04:50:25.611808 [Byte1]: 52
1699 04:50:25.615851
1700 04:50:25.616305 Set Vref, RX VrefLevel [Byte0]: 53
1701 04:50:25.619085 [Byte1]: 53
1702 04:50:25.623568
1703 04:50:25.623987 Set Vref, RX VrefLevel [Byte0]: 54
1704 04:50:25.626694 [Byte1]: 54
1705 04:50:25.631205
1706 04:50:25.631619 Set Vref, RX VrefLevel [Byte0]: 55
1707 04:50:25.634175 [Byte1]: 55
1708 04:50:25.638482
1709 04:50:25.639033 Set Vref, RX VrefLevel [Byte0]: 56
1710 04:50:25.642127 [Byte1]: 56
1711 04:50:25.646091
1712 04:50:25.646684 Set Vref, RX VrefLevel [Byte0]: 57
1713 04:50:25.649759 [Byte1]: 57
1714 04:50:25.653618
1715 04:50:25.654021 Set Vref, RX VrefLevel [Byte0]: 58
1716 04:50:25.656978 [Byte1]: 58
1717 04:50:25.661689
1718 04:50:25.662261 Set Vref, RX VrefLevel [Byte0]: 59
1719 04:50:25.667645 [Byte1]: 59
1720 04:50:25.668142
1721 04:50:25.671167 Set Vref, RX VrefLevel [Byte0]: 60
1722 04:50:25.674438 [Byte1]: 60
1723 04:50:25.674968
1724 04:50:25.677819 Set Vref, RX VrefLevel [Byte0]: 61
1725 04:50:25.681294 [Byte1]: 61
1726 04:50:25.681819
1727 04:50:25.684590 Set Vref, RX VrefLevel [Byte0]: 62
1728 04:50:25.687583 [Byte1]: 62
1729 04:50:25.691618
1730 04:50:25.692119 Set Vref, RX VrefLevel [Byte0]: 63
1731 04:50:25.695027 [Byte1]: 63
1732 04:50:25.699206
1733 04:50:25.699728 Set Vref, RX VrefLevel [Byte0]: 64
1734 04:50:25.702474 [Byte1]: 64
1735 04:50:25.706908
1736 04:50:25.707303 Set Vref, RX VrefLevel [Byte0]: 65
1737 04:50:25.709754 [Byte1]: 65
1738 04:50:25.714467
1739 04:50:25.714538 Set Vref, RX VrefLevel [Byte0]: 66
1740 04:50:25.717925 [Byte1]: 66
1741 04:50:25.721957
1742 04:50:25.722052 Set Vref, RX VrefLevel [Byte0]: 67
1743 04:50:25.725223 [Byte1]: 67
1744 04:50:25.729186
1745 04:50:25.729287 Set Vref, RX VrefLevel [Byte0]: 68
1746 04:50:25.732633 [Byte1]: 68
1747 04:50:25.736816
1748 04:50:25.736920 Set Vref, RX VrefLevel [Byte0]: 69
1749 04:50:25.740404 [Byte1]: 69
1750 04:50:25.744827
1751 04:50:25.744949 Set Vref, RX VrefLevel [Byte0]: 70
1752 04:50:25.748027 [Byte1]: 70
1753 04:50:25.752278
1754 04:50:25.752414 Set Vref, RX VrefLevel [Byte0]: 71
1755 04:50:25.755800 [Byte1]: 71
1756 04:50:25.760039
1757 04:50:25.760212 Set Vref, RX VrefLevel [Byte0]: 72
1758 04:50:25.763318 [Byte1]: 72
1759 04:50:25.767599
1760 04:50:25.767797 Set Vref, RX VrefLevel [Byte0]: 73
1761 04:50:25.771299 [Byte1]: 73
1762 04:50:25.775217
1763 04:50:25.775514 Set Vref, RX VrefLevel [Byte0]: 74
1764 04:50:25.778582 [Byte1]: 74
1765 04:50:25.782929
1766 04:50:25.783310 Set Vref, RX VrefLevel [Byte0]: 75
1767 04:50:25.786384 [Byte1]: 75
1768 04:50:25.790482
1769 04:50:25.790900 Set Vref, RX VrefLevel [Byte0]: 76
1770 04:50:25.793859 [Byte1]: 76
1771 04:50:25.798121
1772 04:50:25.798561 Final RX Vref Byte 0 = 52 to rank0
1773 04:50:25.801653 Final RX Vref Byte 1 = 63 to rank0
1774 04:50:25.804901 Final RX Vref Byte 0 = 52 to rank1
1775 04:50:25.808302 Final RX Vref Byte 1 = 63 to rank1==
1776 04:50:25.811560 Dram Type= 6, Freq= 0, CH_1, rank 0
1777 04:50:25.815152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1778 04:50:25.818377 ==
1779 04:50:25.818796 DQS Delay:
1780 04:50:25.819124 DQS0 = 0, DQS1 = 0
1781 04:50:25.821688 DQM Delay:
1782 04:50:25.822236 DQM0 = 92, DQM1 = 83
1783 04:50:25.825149 DQ Delay:
1784 04:50:25.828370 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1785 04:50:25.831606 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1786 04:50:25.832024 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1787 04:50:25.838252 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1788 04:50:25.838672
1789 04:50:25.839180
1790 04:50:25.844929 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a47, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1791 04:50:25.848020 CH1 RK0: MR19=606, MR18=2A47
1792 04:50:25.854992 CH1_RK0: MR19=0x606, MR18=0x2A47, DQSOSC=392, MR23=63, INC=96, DEC=64
1793 04:50:25.855444
1794 04:50:25.858281 ----->DramcWriteLeveling(PI) begin...
1795 04:50:25.858745 ==
1796 04:50:25.861785 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 04:50:25.864928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 04:50:25.865497 ==
1799 04:50:25.868245 Write leveling (Byte 0): 27 => 27
1800 04:50:25.871595 Write leveling (Byte 1): 30 => 30
1801 04:50:25.875310 DramcWriteLeveling(PI) end<-----
1802 04:50:25.875826
1803 04:50:25.876307 ==
1804 04:50:25.878498 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 04:50:25.881644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 04:50:25.882206 ==
1807 04:50:25.884829 [Gating] SW mode calibration
1808 04:50:25.891555 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1809 04:50:25.898006 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1810 04:50:25.901350 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1811 04:50:25.905166 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1812 04:50:25.911571 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 04:50:25.915146 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 04:50:25.918323 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 04:50:25.925283 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 04:50:25.928217 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 04:50:25.931893 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 04:50:25.935486 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 04:50:25.941257 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 04:50:25.944941 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 04:50:25.948414 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 04:50:25.954794 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 04:50:25.958139 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 04:50:25.961627 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 04:50:25.968134 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 04:50:25.971619 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1827 04:50:25.975035 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1828 04:50:25.982009 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 04:50:25.985267 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 04:50:25.988476 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 04:50:25.995319 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 04:50:25.998652 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 04:50:26.001850 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 04:50:26.008150 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 04:50:26.011519 0 9 4 | B1->B0 | 2323 2323 | 1 1 | (1 1) (0 0)
1836 04:50:26.014936 0 9 8 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1837 04:50:26.021556 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 04:50:26.025030 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 04:50:26.028422 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 04:50:26.035125 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 04:50:26.038465 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 04:50:26.041482 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
1843 04:50:26.045116 0 10 4 | B1->B0 | 2f2f 3131 | 0 0 | (1 0) (0 0)
1844 04:50:26.051758 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 04:50:26.055117 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 04:50:26.058307 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 04:50:26.065435 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 04:50:26.068366 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 04:50:26.071833 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 04:50:26.078333 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 04:50:26.081724 0 11 4 | B1->B0 | 3232 3131 | 1 0 | (0 0) (0 0)
1852 04:50:26.085164 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1853 04:50:26.091815 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 04:50:26.095094 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 04:50:26.098672 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 04:50:26.105196 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 04:50:26.108365 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 04:50:26.112269 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 04:50:26.118567 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1860 04:50:26.122111 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 04:50:26.125382 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 04:50:26.128856 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 04:50:26.135439 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 04:50:26.138414 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 04:50:26.141933 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 04:50:26.148598 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 04:50:26.151818 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 04:50:26.155342 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 04:50:26.162057 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 04:50:26.165275 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 04:50:26.168972 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 04:50:26.175361 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 04:50:26.178978 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 04:50:26.182364 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 04:50:26.185564 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1876 04:50:26.192586 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1877 04:50:26.195594 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 04:50:26.198981 Total UI for P1: 0, mck2ui 16
1879 04:50:26.202319 best dqsien dly found for B0: ( 0, 14, 8)
1880 04:50:26.205511 Total UI for P1: 0, mck2ui 16
1881 04:50:26.208913 best dqsien dly found for B1: ( 0, 14, 6)
1882 04:50:26.212571 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1883 04:50:26.215816 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1884 04:50:26.216233
1885 04:50:26.219248 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1886 04:50:26.222461 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1887 04:50:26.225737 [Gating] SW calibration Done
1888 04:50:26.226194 ==
1889 04:50:26.229058 Dram Type= 6, Freq= 0, CH_1, rank 1
1890 04:50:26.232219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1891 04:50:26.236001 ==
1892 04:50:26.236419 RX Vref Scan: 0
1893 04:50:26.236750
1894 04:50:26.239181 RX Vref 0 -> 0, step: 1
1895 04:50:26.239599
1896 04:50:26.241972 RX Delay -130 -> 252, step: 16
1897 04:50:26.245797 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1898 04:50:26.248802 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1899 04:50:26.252412 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1900 04:50:26.255488 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1901 04:50:26.261977 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1902 04:50:26.265676 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1903 04:50:26.268681 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1904 04:50:26.272092 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1905 04:50:26.275440 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1906 04:50:26.282365 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1907 04:50:26.285389 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1908 04:50:26.288747 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1909 04:50:26.292455 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1910 04:50:26.295417 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1911 04:50:26.302441 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1912 04:50:26.305753 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1913 04:50:26.306215 ==
1914 04:50:26.308784 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 04:50:26.312189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 04:50:26.312733 ==
1917 04:50:26.313073 DQS Delay:
1918 04:50:26.315684 DQS0 = 0, DQS1 = 0
1919 04:50:26.316106 DQM Delay:
1920 04:50:26.318995 DQM0 = 89, DQM1 = 81
1921 04:50:26.319411 DQ Delay:
1922 04:50:26.322697 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1923 04:50:26.325875 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1924 04:50:26.328903 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =69
1925 04:50:26.332194 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1926 04:50:26.332611
1927 04:50:26.332938
1928 04:50:26.333242 ==
1929 04:50:26.335710 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 04:50:26.339062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 04:50:26.342366 ==
1932 04:50:26.342783
1933 04:50:26.343108
1934 04:50:26.343407 TX Vref Scan disable
1935 04:50:26.345875 == TX Byte 0 ==
1936 04:50:26.349058 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1937 04:50:26.352552 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1938 04:50:26.355802 == TX Byte 1 ==
1939 04:50:26.359133 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1940 04:50:26.362629 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1941 04:50:26.365894 ==
1942 04:50:26.366336 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 04:50:26.372169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 04:50:26.372588 ==
1945 04:50:26.384826 TX Vref=22, minBit 13, minWin=27, winSum=450
1946 04:50:26.388074 TX Vref=24, minBit 13, minWin=27, winSum=455
1947 04:50:26.391406 TX Vref=26, minBit 15, minWin=27, winSum=456
1948 04:50:26.394466 TX Vref=28, minBit 8, minWin=28, winSum=458
1949 04:50:26.397814 TX Vref=30, minBit 8, minWin=28, winSum=459
1950 04:50:26.404529 TX Vref=32, minBit 9, minWin=27, winSum=457
1951 04:50:26.408114 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
1952 04:50:26.408535
1953 04:50:26.411269 Final TX Range 1 Vref 30
1954 04:50:26.411687
1955 04:50:26.412015 ==
1956 04:50:26.414844 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 04:50:26.418005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 04:50:26.418448 ==
1959 04:50:26.421319
1960 04:50:26.421733
1961 04:50:26.422101 TX Vref Scan disable
1962 04:50:26.424880 == TX Byte 0 ==
1963 04:50:26.428189 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1964 04:50:26.434643 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1965 04:50:26.435063 == TX Byte 1 ==
1966 04:50:26.438040 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1967 04:50:26.441338 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1968 04:50:26.444861
1969 04:50:26.445276 [DATLAT]
1970 04:50:26.445604 Freq=800, CH1 RK1
1971 04:50:26.445912
1972 04:50:26.448089 DATLAT Default: 0xa
1973 04:50:26.448506 0, 0xFFFF, sum = 0
1974 04:50:26.451595 1, 0xFFFF, sum = 0
1975 04:50:26.452022 2, 0xFFFF, sum = 0
1976 04:50:26.455170 3, 0xFFFF, sum = 0
1977 04:50:26.455598 4, 0xFFFF, sum = 0
1978 04:50:26.458284 5, 0xFFFF, sum = 0
1979 04:50:26.461285 6, 0xFFFF, sum = 0
1980 04:50:26.461706 7, 0xFFFF, sum = 0
1981 04:50:26.464801 8, 0xFFFF, sum = 0
1982 04:50:26.465283 9, 0x0, sum = 1
1983 04:50:26.465626 10, 0x0, sum = 2
1984 04:50:26.467898 11, 0x0, sum = 3
1985 04:50:26.468325 12, 0x0, sum = 4
1986 04:50:26.471456 best_step = 10
1987 04:50:26.471875
1988 04:50:26.472204 ==
1989 04:50:26.474630 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 04:50:26.478123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 04:50:26.478678 ==
1992 04:50:26.481287 RX Vref Scan: 0
1993 04:50:26.481802
1994 04:50:26.482283 RX Vref 0 -> 0, step: 1
1995 04:50:26.482737
1996 04:50:26.484920 RX Delay -95 -> 252, step: 8
1997 04:50:26.491378 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
1998 04:50:26.494635 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
1999 04:50:26.497859 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2000 04:50:26.501425 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2001 04:50:26.504554 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2002 04:50:26.511185 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2003 04:50:26.514543 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2004 04:50:26.518276 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2005 04:50:26.521128 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2006 04:50:26.524849 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2007 04:50:26.531528 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2008 04:50:26.534639 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2009 04:50:26.538200 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2010 04:50:26.541377 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2011 04:50:26.544651 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2012 04:50:26.551812 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2013 04:50:26.552251 ==
2014 04:50:26.554717 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 04:50:26.558191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 04:50:26.558631 ==
2017 04:50:26.559067 DQS Delay:
2018 04:50:26.561256 DQS0 = 0, DQS1 = 0
2019 04:50:26.561693 DQM Delay:
2020 04:50:26.564627 DQM0 = 91, DQM1 = 84
2021 04:50:26.565065 DQ Delay:
2022 04:50:26.568101 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2023 04:50:26.571374 DQ4 =92, DQ5 =108, DQ6 =96, DQ7 =88
2024 04:50:26.574667 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2025 04:50:26.578180 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2026 04:50:26.578617
2027 04:50:26.579054
2028 04:50:26.584824 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a0f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2029 04:50:26.588020 CH1 RK1: MR19=606, MR18=3A0F
2030 04:50:26.594744 CH1_RK1: MR19=0x606, MR18=0x3A0F, DQSOSC=395, MR23=63, INC=94, DEC=63
2031 04:50:26.598328 [RxdqsGatingPostProcess] freq 800
2032 04:50:26.604827 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2033 04:50:26.605270 Pre-setting of DQS Precalculation
2034 04:50:26.611483 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2035 04:50:26.618078 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2036 04:50:26.625102 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2037 04:50:26.625545
2038 04:50:26.626004
2039 04:50:26.628227 [Calibration Summary] 1600 Mbps
2040 04:50:26.631567 CH 0, Rank 0
2041 04:50:26.632008 SW Impedance : PASS
2042 04:50:26.635036 DUTY Scan : NO K
2043 04:50:26.635478 ZQ Calibration : PASS
2044 04:50:26.638524 Jitter Meter : NO K
2045 04:50:26.641636 CBT Training : PASS
2046 04:50:26.642109 Write leveling : PASS
2047 04:50:26.645450 RX DQS gating : PASS
2048 04:50:26.648285 RX DQ/DQS(RDDQC) : PASS
2049 04:50:26.648724 TX DQ/DQS : PASS
2050 04:50:26.651944 RX DATLAT : PASS
2051 04:50:26.654799 RX DQ/DQS(Engine): PASS
2052 04:50:26.655242 TX OE : NO K
2053 04:50:26.658541 All Pass.
2054 04:50:26.658977
2055 04:50:26.659411 CH 0, Rank 1
2056 04:50:26.661862 SW Impedance : PASS
2057 04:50:26.662342 DUTY Scan : NO K
2058 04:50:26.665202 ZQ Calibration : PASS
2059 04:50:26.668333 Jitter Meter : NO K
2060 04:50:26.668774 CBT Training : PASS
2061 04:50:26.671518 Write leveling : PASS
2062 04:50:26.675402 RX DQS gating : PASS
2063 04:50:26.675843 RX DQ/DQS(RDDQC) : PASS
2064 04:50:26.678258 TX DQ/DQS : PASS
2065 04:50:26.678699 RX DATLAT : PASS
2066 04:50:26.681599 RX DQ/DQS(Engine): PASS
2067 04:50:26.684944 TX OE : NO K
2068 04:50:26.685384 All Pass.
2069 04:50:26.685819
2070 04:50:26.686256 CH 1, Rank 0
2071 04:50:26.688700 SW Impedance : PASS
2072 04:50:26.691819 DUTY Scan : NO K
2073 04:50:26.692259 ZQ Calibration : PASS
2074 04:50:26.695148 Jitter Meter : NO K
2075 04:50:26.698678 CBT Training : PASS
2076 04:50:26.699117 Write leveling : PASS
2077 04:50:26.702042 RX DQS gating : PASS
2078 04:50:26.705339 RX DQ/DQS(RDDQC) : PASS
2079 04:50:26.705781 TX DQ/DQS : PASS
2080 04:50:26.708701 RX DATLAT : PASS
2081 04:50:26.709141 RX DQ/DQS(Engine): PASS
2082 04:50:26.712484 TX OE : NO K
2083 04:50:26.712927 All Pass.
2084 04:50:26.713363
2085 04:50:26.715365 CH 1, Rank 1
2086 04:50:26.715802 SW Impedance : PASS
2087 04:50:26.719002 DUTY Scan : NO K
2088 04:50:26.721932 ZQ Calibration : PASS
2089 04:50:26.722410 Jitter Meter : NO K
2090 04:50:26.725341 CBT Training : PASS
2091 04:50:26.728748 Write leveling : PASS
2092 04:50:26.729187 RX DQS gating : PASS
2093 04:50:26.732066 RX DQ/DQS(RDDQC) : PASS
2094 04:50:26.735444 TX DQ/DQS : PASS
2095 04:50:26.735886 RX DATLAT : PASS
2096 04:50:26.738466 RX DQ/DQS(Engine): PASS
2097 04:50:26.742245 TX OE : NO K
2098 04:50:26.742686 All Pass.
2099 04:50:26.743123
2100 04:50:26.743532 DramC Write-DBI off
2101 04:50:26.745109 PER_BANK_REFRESH: Hybrid Mode
2102 04:50:26.748859 TX_TRACKING: ON
2103 04:50:26.752120 [GetDramInforAfterCalByMRR] Vendor 6.
2104 04:50:26.755253 [GetDramInforAfterCalByMRR] Revision 606.
2105 04:50:26.758711 [GetDramInforAfterCalByMRR] Revision 2 0.
2106 04:50:26.759149 MR0 0x3b3b
2107 04:50:26.762160 MR8 0x5151
2108 04:50:26.765639 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 04:50:26.766116
2110 04:50:26.766553 MR0 0x3b3b
2111 04:50:26.766966 MR8 0x5151
2112 04:50:26.768605 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 04:50:26.769044
2114 04:50:26.778751 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2115 04:50:26.782315 [FAST_K] Save calibration result to emmc
2116 04:50:26.785232 [FAST_K] Save calibration result to emmc
2117 04:50:26.788915 dram_init: config_dvfs: 1
2118 04:50:26.792155 dramc_set_vcore_voltage set vcore to 662500
2119 04:50:26.795439 Read voltage for 1200, 2
2120 04:50:26.795877 Vio18 = 0
2121 04:50:26.798781 Vcore = 662500
2122 04:50:26.799218 Vdram = 0
2123 04:50:26.799653 Vddq = 0
2124 04:50:26.800065 Vmddr = 0
2125 04:50:26.805446 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2126 04:50:26.809229 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2127 04:50:26.812176 MEM_TYPE=3, freq_sel=15
2128 04:50:26.815749 sv_algorithm_assistance_LP4_1600
2129 04:50:26.819350 ============ PULL DRAM RESETB DOWN ============
2130 04:50:26.825458 ========== PULL DRAM RESETB DOWN end =========
2131 04:50:26.829141 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2132 04:50:26.832481 ===================================
2133 04:50:26.835586 LPDDR4 DRAM CONFIGURATION
2134 04:50:26.838819 ===================================
2135 04:50:26.839263 EX_ROW_EN[0] = 0x0
2136 04:50:26.842371 EX_ROW_EN[1] = 0x0
2137 04:50:26.842811 LP4Y_EN = 0x0
2138 04:50:26.845693 WORK_FSP = 0x0
2139 04:50:26.846167 WL = 0x4
2140 04:50:26.848789 RL = 0x4
2141 04:50:26.849227 BL = 0x2
2142 04:50:26.852146 RPST = 0x0
2143 04:50:26.852586 RD_PRE = 0x0
2144 04:50:26.855880 WR_PRE = 0x1
2145 04:50:26.856319 WR_PST = 0x0
2146 04:50:26.858861 DBI_WR = 0x0
2147 04:50:26.859300 DBI_RD = 0x0
2148 04:50:26.862034 OTF = 0x1
2149 04:50:26.865694 ===================================
2150 04:50:26.868689 ===================================
2151 04:50:26.869129 ANA top config
2152 04:50:26.872384 ===================================
2153 04:50:26.875444 DLL_ASYNC_EN = 0
2154 04:50:26.878991 ALL_SLAVE_EN = 0
2155 04:50:26.882029 NEW_RANK_MODE = 1
2156 04:50:26.882535 DLL_IDLE_MODE = 1
2157 04:50:26.885665 LP45_APHY_COMB_EN = 1
2158 04:50:26.889261 TX_ODT_DIS = 1
2159 04:50:26.892716 NEW_8X_MODE = 1
2160 04:50:26.896125 ===================================
2161 04:50:26.899142 ===================================
2162 04:50:26.902439 data_rate = 2400
2163 04:50:26.902881 CKR = 1
2164 04:50:26.905686 DQ_P2S_RATIO = 8
2165 04:50:26.909129 ===================================
2166 04:50:26.912568 CA_P2S_RATIO = 8
2167 04:50:26.915659 DQ_CA_OPEN = 0
2168 04:50:26.919015 DQ_SEMI_OPEN = 0
2169 04:50:26.922730 CA_SEMI_OPEN = 0
2170 04:50:26.923172 CA_FULL_RATE = 0
2171 04:50:26.925757 DQ_CKDIV4_EN = 0
2172 04:50:26.929846 CA_CKDIV4_EN = 0
2173 04:50:26.932193 CA_PREDIV_EN = 0
2174 04:50:26.935832 PH8_DLY = 17
2175 04:50:26.936272 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2176 04:50:26.939263 DQ_AAMCK_DIV = 4
2177 04:50:26.942598 CA_AAMCK_DIV = 4
2178 04:50:26.945997 CA_ADMCK_DIV = 4
2179 04:50:26.949306 DQ_TRACK_CA_EN = 0
2180 04:50:26.952678 CA_PICK = 1200
2181 04:50:26.955942 CA_MCKIO = 1200
2182 04:50:26.956385 MCKIO_SEMI = 0
2183 04:50:26.959167 PLL_FREQ = 2366
2184 04:50:26.962443 DQ_UI_PI_RATIO = 32
2185 04:50:26.965866 CA_UI_PI_RATIO = 0
2186 04:50:26.969612 ===================================
2187 04:50:26.972522 ===================================
2188 04:50:26.975874 memory_type:LPDDR4
2189 04:50:26.976310 GP_NUM : 10
2190 04:50:26.979236 SRAM_EN : 1
2191 04:50:26.979674 MD32_EN : 0
2192 04:50:26.982544 ===================================
2193 04:50:26.985875 [ANA_INIT] >>>>>>>>>>>>>>
2194 04:50:26.989439 <<<<<< [CONFIGURE PHASE]: ANA_TX
2195 04:50:26.992473 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2196 04:50:26.995727 ===================================
2197 04:50:26.999200 data_rate = 2400,PCW = 0X5b00
2198 04:50:27.002729 ===================================
2199 04:50:27.005819 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2200 04:50:27.012558 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 04:50:27.016194 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 04:50:27.022543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2203 04:50:27.026324 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2204 04:50:27.029482 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2205 04:50:27.029927 [ANA_INIT] flow start
2206 04:50:27.032719 [ANA_INIT] PLL >>>>>>>>
2207 04:50:27.035956 [ANA_INIT] PLL <<<<<<<<
2208 04:50:27.036394 [ANA_INIT] MIDPI >>>>>>>>
2209 04:50:27.039382 [ANA_INIT] MIDPI <<<<<<<<
2210 04:50:27.042742 [ANA_INIT] DLL >>>>>>>>
2211 04:50:27.043180 [ANA_INIT] DLL <<<<<<<<
2212 04:50:27.046226 [ANA_INIT] flow end
2213 04:50:27.049335 ============ LP4 DIFF to SE enter ============
2214 04:50:27.052672 ============ LP4 DIFF to SE exit ============
2215 04:50:27.056219 [ANA_INIT] <<<<<<<<<<<<<
2216 04:50:27.059685 [Flow] Enable top DCM control >>>>>
2217 04:50:27.062565 [Flow] Enable top DCM control <<<<<
2218 04:50:27.066002 Enable DLL master slave shuffle
2219 04:50:27.072844 ==============================================================
2220 04:50:27.073282 Gating Mode config
2221 04:50:27.079506 ==============================================================
2222 04:50:27.079946 Config description:
2223 04:50:27.089826 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2224 04:50:27.096487 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2225 04:50:27.103267 SELPH_MODE 0: By rank 1: By Phase
2226 04:50:27.106098 ==============================================================
2227 04:50:27.109566 GAT_TRACK_EN = 1
2228 04:50:27.113208 RX_GATING_MODE = 2
2229 04:50:27.116424 RX_GATING_TRACK_MODE = 2
2230 04:50:27.119796 SELPH_MODE = 1
2231 04:50:27.122863 PICG_EARLY_EN = 1
2232 04:50:27.126537 VALID_LAT_VALUE = 1
2233 04:50:27.129561 ==============================================================
2234 04:50:27.132882 Enter into Gating configuration >>>>
2235 04:50:27.136530 Exit from Gating configuration <<<<
2236 04:50:27.139771 Enter into DVFS_PRE_config >>>>>
2237 04:50:27.152842 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2238 04:50:27.156483 Exit from DVFS_PRE_config <<<<<
2239 04:50:27.156925 Enter into PICG configuration >>>>
2240 04:50:27.159800 Exit from PICG configuration <<<<
2241 04:50:27.162918 [RX_INPUT] configuration >>>>>
2242 04:50:27.166304 [RX_INPUT] configuration <<<<<
2243 04:50:27.173191 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2244 04:50:27.176416 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2245 04:50:27.183004 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 04:50:27.189598 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 04:50:27.196361 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 04:50:27.203238 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 04:50:27.206314 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2250 04:50:27.209755 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2251 04:50:27.213218 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2252 04:50:27.219384 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2253 04:50:27.223097 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2254 04:50:27.226357 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2255 04:50:27.229466 ===================================
2256 04:50:27.233115 LPDDR4 DRAM CONFIGURATION
2257 04:50:27.236288 ===================================
2258 04:50:27.239735 EX_ROW_EN[0] = 0x0
2259 04:50:27.240176 EX_ROW_EN[1] = 0x0
2260 04:50:27.242524 LP4Y_EN = 0x0
2261 04:50:27.242965 WORK_FSP = 0x0
2262 04:50:27.246401 WL = 0x4
2263 04:50:27.246839 RL = 0x4
2264 04:50:27.249394 BL = 0x2
2265 04:50:27.249831 RPST = 0x0
2266 04:50:27.252557 RD_PRE = 0x0
2267 04:50:27.252996 WR_PRE = 0x1
2268 04:50:27.255955 WR_PST = 0x0
2269 04:50:27.256394 DBI_WR = 0x0
2270 04:50:27.259233 DBI_RD = 0x0
2271 04:50:27.259676 OTF = 0x1
2272 04:50:27.262593 ===================================
2273 04:50:27.265993 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2274 04:50:27.272535 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2275 04:50:27.276137 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2276 04:50:27.279343 ===================================
2277 04:50:27.282791 LPDDR4 DRAM CONFIGURATION
2278 04:50:27.286049 ===================================
2279 04:50:27.286478 EX_ROW_EN[0] = 0x10
2280 04:50:27.289347 EX_ROW_EN[1] = 0x0
2281 04:50:27.292629 LP4Y_EN = 0x0
2282 04:50:27.293054 WORK_FSP = 0x0
2283 04:50:27.296021 WL = 0x4
2284 04:50:27.296446 RL = 0x4
2285 04:50:27.299316 BL = 0x2
2286 04:50:27.299740 RPST = 0x0
2287 04:50:27.302479 RD_PRE = 0x0
2288 04:50:27.302903 WR_PRE = 0x1
2289 04:50:27.306209 WR_PST = 0x0
2290 04:50:27.306632 DBI_WR = 0x0
2291 04:50:27.309325 DBI_RD = 0x0
2292 04:50:27.309751 OTF = 0x1
2293 04:50:27.312694 ===================================
2294 04:50:27.318725 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2295 04:50:27.318809 ==
2296 04:50:27.322177 Dram Type= 6, Freq= 0, CH_0, rank 0
2297 04:50:27.325571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2298 04:50:27.325659 ==
2299 04:50:27.328888 [Duty_Offset_Calibration]
2300 04:50:27.332286 B0:2 B1:0 CA:1
2301 04:50:27.332379
2302 04:50:27.335666 [DutyScan_Calibration_Flow] k_type=0
2303 04:50:27.343198
2304 04:50:27.343311 ==CLK 0==
2305 04:50:27.346111 Final CLK duty delay cell = -4
2306 04:50:27.349517 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2307 04:50:27.353126 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2308 04:50:27.356347 [-4] AVG Duty = 4953%(X100)
2309 04:50:27.356499
2310 04:50:27.359398 CH0 CLK Duty spec in!! Max-Min= 156%
2311 04:50:27.362976 [DutyScan_Calibration_Flow] ====Done====
2312 04:50:27.363148
2313 04:50:27.366084 [DutyScan_Calibration_Flow] k_type=1
2314 04:50:27.382256
2315 04:50:27.382637 ==DQS 0 ==
2316 04:50:27.385706 Final DQS duty delay cell = 0
2317 04:50:27.389082 [0] MAX Duty = 5187%(X100), DQS PI = 30
2318 04:50:27.392114 [0] MIN Duty = 4938%(X100), DQS PI = 0
2319 04:50:27.392530 [0] AVG Duty = 5062%(X100)
2320 04:50:27.395388
2321 04:50:27.395799 ==DQS 1 ==
2322 04:50:27.399103 Final DQS duty delay cell = -4
2323 04:50:27.402225 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2324 04:50:27.405187 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2325 04:50:27.408558 [-4] AVG Duty = 5031%(X100)
2326 04:50:27.408974
2327 04:50:27.412223 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2328 04:50:27.412639
2329 04:50:27.415352 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2330 04:50:27.418948 [DutyScan_Calibration_Flow] ====Done====
2331 04:50:27.419361
2332 04:50:27.421967 [DutyScan_Calibration_Flow] k_type=3
2333 04:50:27.438854
2334 04:50:27.439268 ==DQM 0 ==
2335 04:50:27.441925 Final DQM duty delay cell = 0
2336 04:50:27.445600 [0] MAX Duty = 5062%(X100), DQS PI = 24
2337 04:50:27.448770 [0] MIN Duty = 4813%(X100), DQS PI = 0
2338 04:50:27.449186 [0] AVG Duty = 4937%(X100)
2339 04:50:27.452103
2340 04:50:27.452516 ==DQM 1 ==
2341 04:50:27.455465 Final DQM duty delay cell = 0
2342 04:50:27.458867 [0] MAX Duty = 5187%(X100), DQS PI = 48
2343 04:50:27.462007 [0] MIN Duty = 5000%(X100), DQS PI = 12
2344 04:50:27.462429 [0] AVG Duty = 5093%(X100)
2345 04:50:27.465526
2346 04:50:27.468985 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2347 04:50:27.469402
2348 04:50:27.472145 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2349 04:50:27.475711 [DutyScan_Calibration_Flow] ====Done====
2350 04:50:27.476127
2351 04:50:27.478863 [DutyScan_Calibration_Flow] k_type=2
2352 04:50:27.495387
2353 04:50:27.495802 ==DQ 0 ==
2354 04:50:27.498870 Final DQ duty delay cell = -4
2355 04:50:27.502011 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2356 04:50:27.505386 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2357 04:50:27.508463 [-4] AVG Duty = 4968%(X100)
2358 04:50:27.508877
2359 04:50:27.509203 ==DQ 1 ==
2360 04:50:27.512121 Final DQ duty delay cell = 4
2361 04:50:27.515546 [4] MAX Duty = 5093%(X100), DQS PI = 4
2362 04:50:27.518745 [4] MIN Duty = 5031%(X100), DQS PI = 2
2363 04:50:27.519161 [4] AVG Duty = 5062%(X100)
2364 04:50:27.519487
2365 04:50:27.521772 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2366 04:50:27.525465
2367 04:50:27.528955 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2368 04:50:27.531916 [DutyScan_Calibration_Flow] ====Done====
2369 04:50:27.532331 ==
2370 04:50:27.535229 Dram Type= 6, Freq= 0, CH_1, rank 0
2371 04:50:27.538838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2372 04:50:27.539260 ==
2373 04:50:27.541996 [Duty_Offset_Calibration]
2374 04:50:27.542411 B0:0 B1:-1 CA:2
2375 04:50:27.542738
2376 04:50:27.545591 [DutyScan_Calibration_Flow] k_type=0
2377 04:50:27.555356
2378 04:50:27.555780 ==CLK 0==
2379 04:50:27.558884 Final CLK duty delay cell = 0
2380 04:50:27.562106 [0] MAX Duty = 5156%(X100), DQS PI = 16
2381 04:50:27.565533 [0] MIN Duty = 4938%(X100), DQS PI = 44
2382 04:50:27.565982 [0] AVG Duty = 5047%(X100)
2383 04:50:27.568953
2384 04:50:27.572420 CH1 CLK Duty spec in!! Max-Min= 218%
2385 04:50:27.575438 [DutyScan_Calibration_Flow] ====Done====
2386 04:50:27.575854
2387 04:50:27.578804 [DutyScan_Calibration_Flow] k_type=1
2388 04:50:27.594934
2389 04:50:27.595361 ==DQS 0 ==
2390 04:50:27.597991 Final DQS duty delay cell = 0
2391 04:50:27.601497 [0] MAX Duty = 5093%(X100), DQS PI = 24
2392 04:50:27.604876 [0] MIN Duty = 4969%(X100), DQS PI = 0
2393 04:50:27.605297 [0] AVG Duty = 5031%(X100)
2394 04:50:27.608150
2395 04:50:27.608562 ==DQS 1 ==
2396 04:50:27.611715 Final DQS duty delay cell = 0
2397 04:50:27.614672 [0] MAX Duty = 5156%(X100), DQS PI = 0
2398 04:50:27.618471 [0] MIN Duty = 4813%(X100), DQS PI = 36
2399 04:50:27.618888 [0] AVG Duty = 4984%(X100)
2400 04:50:27.619216
2401 04:50:27.624784 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2402 04:50:27.625201
2403 04:50:27.628070 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2404 04:50:27.631515 [DutyScan_Calibration_Flow] ====Done====
2405 04:50:27.631931
2406 04:50:27.634828 [DutyScan_Calibration_Flow] k_type=3
2407 04:50:27.652336
2408 04:50:27.652750 ==DQM 0 ==
2409 04:50:27.655524 Final DQM duty delay cell = 4
2410 04:50:27.658481 [4] MAX Duty = 5093%(X100), DQS PI = 6
2411 04:50:27.662058 [4] MIN Duty = 4969%(X100), DQS PI = 28
2412 04:50:27.662476 [4] AVG Duty = 5031%(X100)
2413 04:50:27.665568
2414 04:50:27.666013 ==DQM 1 ==
2415 04:50:27.668955 Final DQM duty delay cell = 0
2416 04:50:27.672069 [0] MAX Duty = 5249%(X100), DQS PI = 60
2417 04:50:27.675485 [0] MIN Duty = 4875%(X100), DQS PI = 36
2418 04:50:27.675901 [0] AVG Duty = 5062%(X100)
2419 04:50:27.678626
2420 04:50:27.682169 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2421 04:50:27.682588
2422 04:50:27.685288 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2423 04:50:27.688465 [DutyScan_Calibration_Flow] ====Done====
2424 04:50:27.688883
2425 04:50:27.691844 [DutyScan_Calibration_Flow] k_type=2
2426 04:50:27.708904
2427 04:50:27.709320 ==DQ 0 ==
2428 04:50:27.712063 Final DQ duty delay cell = 0
2429 04:50:27.715506 [0] MAX Duty = 5062%(X100), DQS PI = 20
2430 04:50:27.718982 [0] MIN Duty = 4938%(X100), DQS PI = 0
2431 04:50:27.719399 [0] AVG Duty = 5000%(X100)
2432 04:50:27.719727
2433 04:50:27.722296 ==DQ 1 ==
2434 04:50:27.722710 Final DQ duty delay cell = 0
2435 04:50:27.728776 [0] MAX Duty = 5062%(X100), DQS PI = 4
2436 04:50:27.731978 [0] MIN Duty = 4813%(X100), DQS PI = 36
2437 04:50:27.732396 [0] AVG Duty = 4937%(X100)
2438 04:50:27.732722
2439 04:50:27.735688 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2440 04:50:27.736105
2441 04:50:27.738826 CH1 DQ 1 Duty spec in!! Max-Min= 249%
2442 04:50:27.745291 [DutyScan_Calibration_Flow] ====Done====
2443 04:50:27.748817 nWR fixed to 30
2444 04:50:27.749231 [ModeRegInit_LP4] CH0 RK0
2445 04:50:27.752281 [ModeRegInit_LP4] CH0 RK1
2446 04:50:27.755482 [ModeRegInit_LP4] CH1 RK0
2447 04:50:27.755956 [ModeRegInit_LP4] CH1 RK1
2448 04:50:27.758922 match AC timing 7
2449 04:50:27.762219 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2450 04:50:27.765438 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2451 04:50:27.772384 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2452 04:50:27.775321 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2453 04:50:27.782008 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2454 04:50:27.782449 ==
2455 04:50:27.785407 Dram Type= 6, Freq= 0, CH_0, rank 0
2456 04:50:27.788827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2457 04:50:27.789222 ==
2458 04:50:27.795542 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2459 04:50:27.798646 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2460 04:50:27.808357 [CA 0] Center 38 (8~69) winsize 62
2461 04:50:27.811689 [CA 1] Center 38 (8~69) winsize 62
2462 04:50:27.814973 [CA 2] Center 35 (4~66) winsize 63
2463 04:50:27.818308 [CA 3] Center 35 (4~66) winsize 63
2464 04:50:27.821731 [CA 4] Center 34 (4~65) winsize 62
2465 04:50:27.824872 [CA 5] Center 33 (3~63) winsize 61
2466 04:50:27.825244
2467 04:50:27.828291 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2468 04:50:27.828660
2469 04:50:27.832007 [CATrainingPosCal] consider 1 rank data
2470 04:50:27.834951 u2DelayCellTimex100 = 270/100 ps
2471 04:50:27.838273 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2472 04:50:27.841452 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2473 04:50:27.848201 CA2 delay=35 (4~66),Diff = 2 PI (9 cell)
2474 04:50:27.851460 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2475 04:50:27.855041 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2476 04:50:27.858602 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2477 04:50:27.859053
2478 04:50:27.861612 CA PerBit enable=1, Macro0, CA PI delay=33
2479 04:50:27.862061
2480 04:50:27.865105 [CBTSetCACLKResult] CA Dly = 33
2481 04:50:27.865515 CS Dly: 6 (0~37)
2482 04:50:27.865833 ==
2483 04:50:27.868306 Dram Type= 6, Freq= 0, CH_0, rank 1
2484 04:50:27.875341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2485 04:50:27.875789 ==
2486 04:50:27.878432 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2487 04:50:27.884930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2488 04:50:27.893926 [CA 0] Center 39 (8~70) winsize 63
2489 04:50:27.897451 [CA 1] Center 38 (8~69) winsize 62
2490 04:50:27.900838 [CA 2] Center 35 (5~66) winsize 62
2491 04:50:27.903981 [CA 3] Center 35 (5~66) winsize 62
2492 04:50:27.907539 [CA 4] Center 34 (4~65) winsize 62
2493 04:50:27.910913 [CA 5] Center 34 (4~64) winsize 61
2494 04:50:27.911366
2495 04:50:27.914058 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2496 04:50:27.914514
2497 04:50:27.917589 [CATrainingPosCal] consider 2 rank data
2498 04:50:27.921063 u2DelayCellTimex100 = 270/100 ps
2499 04:50:27.924314 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2500 04:50:27.927379 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2501 04:50:27.930841 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2502 04:50:27.937580 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2503 04:50:27.941487 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2504 04:50:27.944848 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2505 04:50:27.945406
2506 04:50:27.947876 CA PerBit enable=1, Macro0, CA PI delay=33
2507 04:50:27.948334
2508 04:50:27.951108 [CBTSetCACLKResult] CA Dly = 33
2509 04:50:27.951673 CS Dly: 7 (0~39)
2510 04:50:27.952033
2511 04:50:27.954298 ----->DramcWriteLeveling(PI) begin...
2512 04:50:27.954759 ==
2513 04:50:27.958045 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 04:50:27.964574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 04:50:27.965095 ==
2516 04:50:27.967665 Write leveling (Byte 0): 34 => 34
2517 04:50:27.970934 Write leveling (Byte 1): 31 => 31
2518 04:50:27.971390 DramcWriteLeveling(PI) end<-----
2519 04:50:27.971747
2520 04:50:27.974342 ==
2521 04:50:27.977830 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 04:50:27.981633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 04:50:27.982240 ==
2524 04:50:27.984554 [Gating] SW mode calibration
2525 04:50:27.991074 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2526 04:50:27.994626 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2527 04:50:28.000943 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2528 04:50:28.004925 0 15 4 | B1->B0 | 302f 3434 | 1 1 | (0 0) (1 1)
2529 04:50:28.008120 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 04:50:28.014340 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 04:50:28.017547 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 04:50:28.021120 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 04:50:28.027531 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2534 04:50:28.031188 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2535 04:50:28.034551 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2536 04:50:28.037933 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 04:50:28.045143 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 04:50:28.047923 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 04:50:28.051301 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 04:50:28.057867 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 04:50:28.061135 1 0 24 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
2542 04:50:28.065058 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2543 04:50:28.071444 1 1 0 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
2544 04:50:28.074498 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 04:50:28.078429 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 04:50:28.084392 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 04:50:28.087911 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 04:50:28.090909 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 04:50:28.097882 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2550 04:50:28.100765 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2551 04:50:28.104129 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2552 04:50:28.111396 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 04:50:28.114303 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 04:50:28.117734 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 04:50:28.124467 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 04:50:28.127621 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 04:50:28.131182 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 04:50:28.137814 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 04:50:28.140722 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 04:50:28.144283 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 04:50:28.150736 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 04:50:28.154301 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 04:50:28.157736 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 04:50:28.164268 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 04:50:28.167619 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 04:50:28.170797 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2567 04:50:28.174410 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 04:50:28.177106 Total UI for P1: 0, mck2ui 16
2569 04:50:28.181119 best dqsien dly found for B0: ( 1, 3, 28)
2570 04:50:28.184169 Total UI for P1: 0, mck2ui 16
2571 04:50:28.187386 best dqsien dly found for B1: ( 1, 3, 30)
2572 04:50:28.190297 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2573 04:50:28.193811 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2574 04:50:28.196839
2575 04:50:28.200615 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2576 04:50:28.204004 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2577 04:50:28.207714 [Gating] SW calibration Done
2578 04:50:28.208126 ==
2579 04:50:28.211118 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 04:50:28.214098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 04:50:28.214566 ==
2582 04:50:28.214926 RX Vref Scan: 0
2583 04:50:28.215261
2584 04:50:28.217291 RX Vref 0 -> 0, step: 1
2585 04:50:28.217748
2586 04:50:28.221281 RX Delay -40 -> 252, step: 8
2587 04:50:28.224367 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2588 04:50:28.227376 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2589 04:50:28.234270 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2590 04:50:28.237624 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2591 04:50:28.240800 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2592 04:50:28.244259 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2593 04:50:28.247439 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2594 04:50:28.254453 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2595 04:50:28.257344 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2596 04:50:28.260625 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2597 04:50:28.263942 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2598 04:50:28.267586 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2599 04:50:28.274139 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2600 04:50:28.277432 iDelay=208, Bit 13, Center 111 (48 ~ 175) 128
2601 04:50:28.280630 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2602 04:50:28.284457 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2603 04:50:28.285001 ==
2604 04:50:28.287140 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 04:50:28.290644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 04:50:28.294272 ==
2607 04:50:28.294730 DQS Delay:
2608 04:50:28.295088 DQS0 = 0, DQS1 = 0
2609 04:50:28.297420 DQM Delay:
2610 04:50:28.297870 DQM0 = 123, DQM1 = 109
2611 04:50:28.300611 DQ Delay:
2612 04:50:28.304228 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2613 04:50:28.307286 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2614 04:50:28.310515 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2615 04:50:28.313917 DQ12 =115, DQ13 =111, DQ14 =123, DQ15 =115
2616 04:50:28.314419
2617 04:50:28.314778
2618 04:50:28.315109 ==
2619 04:50:28.317701 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 04:50:28.320968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 04:50:28.321532 ==
2622 04:50:28.321898
2623 04:50:28.322273
2624 04:50:28.324417 TX Vref Scan disable
2625 04:50:28.327132 == TX Byte 0 ==
2626 04:50:28.330987 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2627 04:50:28.333859 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2628 04:50:28.337374 == TX Byte 1 ==
2629 04:50:28.340739 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2630 04:50:28.344253 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2631 04:50:28.344716 ==
2632 04:50:28.347672 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 04:50:28.351046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 04:50:28.353757 ==
2635 04:50:28.364176 TX Vref=22, minBit 1, minWin=24, winSum=405
2636 04:50:28.367669 TX Vref=24, minBit 5, minWin=24, winSum=413
2637 04:50:28.370848 TX Vref=26, minBit 0, minWin=25, winSum=416
2638 04:50:28.374452 TX Vref=28, minBit 3, minWin=24, winSum=414
2639 04:50:28.377790 TX Vref=30, minBit 3, minWin=25, winSum=420
2640 04:50:28.381266 TX Vref=32, minBit 1, minWin=25, winSum=417
2641 04:50:28.387863 [TxChooseVref] Worse bit 3, Min win 25, Win sum 420, Final Vref 30
2642 04:50:28.388436
2643 04:50:28.390774 Final TX Range 1 Vref 30
2644 04:50:28.391380
2645 04:50:28.391895 ==
2646 04:50:28.394550 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 04:50:28.397831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 04:50:28.398326 ==
2649 04:50:28.398683
2650 04:50:28.401150
2651 04:50:28.401644 TX Vref Scan disable
2652 04:50:28.404245 == TX Byte 0 ==
2653 04:50:28.407794 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2654 04:50:28.410924 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2655 04:50:28.414272 == TX Byte 1 ==
2656 04:50:28.417797 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2657 04:50:28.421030 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2658 04:50:28.421498
2659 04:50:28.424756 [DATLAT]
2660 04:50:28.425324 Freq=1200, CH0 RK0
2661 04:50:28.425697
2662 04:50:28.427875 DATLAT Default: 0xd
2663 04:50:28.428326 0, 0xFFFF, sum = 0
2664 04:50:28.431390 1, 0xFFFF, sum = 0
2665 04:50:28.431850 2, 0xFFFF, sum = 0
2666 04:50:28.434564 3, 0xFFFF, sum = 0
2667 04:50:28.435209 4, 0xFFFF, sum = 0
2668 04:50:28.438027 5, 0xFFFF, sum = 0
2669 04:50:28.438595 6, 0xFFFF, sum = 0
2670 04:50:28.441602 7, 0xFFFF, sum = 0
2671 04:50:28.442213 8, 0xFFFF, sum = 0
2672 04:50:28.444762 9, 0xFFFF, sum = 0
2673 04:50:28.447708 10, 0xFFFF, sum = 0
2674 04:50:28.448190 11, 0xFFFF, sum = 0
2675 04:50:28.451093 12, 0x0, sum = 1
2676 04:50:28.451636 13, 0x0, sum = 2
2677 04:50:28.452121 14, 0x0, sum = 3
2678 04:50:28.454255 15, 0x0, sum = 4
2679 04:50:28.454719 best_step = 13
2680 04:50:28.455192
2681 04:50:28.455627 ==
2682 04:50:28.457825 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 04:50:28.464339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 04:50:28.464820 ==
2685 04:50:28.465201 RX Vref Scan: 1
2686 04:50:28.465639
2687 04:50:28.468121 Set Vref Range= 32 -> 127
2688 04:50:28.468717
2689 04:50:28.471386 RX Vref 32 -> 127, step: 1
2690 04:50:28.471871
2691 04:50:28.474368 RX Delay -13 -> 252, step: 4
2692 04:50:28.474818
2693 04:50:28.477701 Set Vref, RX VrefLevel [Byte0]: 32
2694 04:50:28.480953 [Byte1]: 32
2695 04:50:28.481405
2696 04:50:28.484651 Set Vref, RX VrefLevel [Byte0]: 33
2697 04:50:28.487729 [Byte1]: 33
2698 04:50:28.488187
2699 04:50:28.491268 Set Vref, RX VrefLevel [Byte0]: 34
2700 04:50:28.494613 [Byte1]: 34
2701 04:50:28.498337
2702 04:50:28.498788 Set Vref, RX VrefLevel [Byte0]: 35
2703 04:50:28.501537 [Byte1]: 35
2704 04:50:28.506346
2705 04:50:28.506890 Set Vref, RX VrefLevel [Byte0]: 36
2706 04:50:28.509917 [Byte1]: 36
2707 04:50:28.514181
2708 04:50:28.514704 Set Vref, RX VrefLevel [Byte0]: 37
2709 04:50:28.517668 [Byte1]: 37
2710 04:50:28.522369
2711 04:50:28.522922 Set Vref, RX VrefLevel [Byte0]: 38
2712 04:50:28.525606 [Byte1]: 38
2713 04:50:28.529707
2714 04:50:28.530363 Set Vref, RX VrefLevel [Byte0]: 39
2715 04:50:28.533344 [Byte1]: 39
2716 04:50:28.538087
2717 04:50:28.538636 Set Vref, RX VrefLevel [Byte0]: 40
2718 04:50:28.541121 [Byte1]: 40
2719 04:50:28.545599
2720 04:50:28.546156 Set Vref, RX VrefLevel [Byte0]: 41
2721 04:50:28.548906 [Byte1]: 41
2722 04:50:28.553854
2723 04:50:28.554436 Set Vref, RX VrefLevel [Byte0]: 42
2724 04:50:28.557056 [Byte1]: 42
2725 04:50:28.561536
2726 04:50:28.562228 Set Vref, RX VrefLevel [Byte0]: 43
2727 04:50:28.565076 [Byte1]: 43
2728 04:50:28.569499
2729 04:50:28.570003 Set Vref, RX VrefLevel [Byte0]: 44
2730 04:50:28.572798 [Byte1]: 44
2731 04:50:28.577271
2732 04:50:28.577736 Set Vref, RX VrefLevel [Byte0]: 45
2733 04:50:28.583632 [Byte1]: 45
2734 04:50:28.584154
2735 04:50:28.586985 Set Vref, RX VrefLevel [Byte0]: 46
2736 04:50:28.590237 [Byte1]: 46
2737 04:50:28.590728
2738 04:50:28.593918 Set Vref, RX VrefLevel [Byte0]: 47
2739 04:50:28.597334 [Byte1]: 47
2740 04:50:28.601243
2741 04:50:28.601766 Set Vref, RX VrefLevel [Byte0]: 48
2742 04:50:28.604207 [Byte1]: 48
2743 04:50:28.608904
2744 04:50:28.609365 Set Vref, RX VrefLevel [Byte0]: 49
2745 04:50:28.612306 [Byte1]: 49
2746 04:50:28.616715
2747 04:50:28.617354 Set Vref, RX VrefLevel [Byte0]: 50
2748 04:50:28.620155 [Byte1]: 50
2749 04:50:28.624650
2750 04:50:28.625199 Set Vref, RX VrefLevel [Byte0]: 51
2751 04:50:28.628032 [Byte1]: 51
2752 04:50:28.632331
2753 04:50:28.632792 Set Vref, RX VrefLevel [Byte0]: 52
2754 04:50:28.636067 [Byte1]: 52
2755 04:50:28.640069
2756 04:50:28.640655 Set Vref, RX VrefLevel [Byte0]: 53
2757 04:50:28.643662 [Byte1]: 53
2758 04:50:28.647992
2759 04:50:28.648450 Set Vref, RX VrefLevel [Byte0]: 54
2760 04:50:28.651489 [Byte1]: 54
2761 04:50:28.656066
2762 04:50:28.656609 Set Vref, RX VrefLevel [Byte0]: 55
2763 04:50:28.659473 [Byte1]: 55
2764 04:50:28.664100
2765 04:50:28.664561 Set Vref, RX VrefLevel [Byte0]: 56
2766 04:50:28.667483 [Byte1]: 56
2767 04:50:28.671948
2768 04:50:28.672500 Set Vref, RX VrefLevel [Byte0]: 57
2769 04:50:28.675042 [Byte1]: 57
2770 04:50:28.679581
2771 04:50:28.680124 Set Vref, RX VrefLevel [Byte0]: 58
2772 04:50:28.682910 [Byte1]: 58
2773 04:50:28.688027
2774 04:50:28.688483 Set Vref, RX VrefLevel [Byte0]: 59
2775 04:50:28.690717 [Byte1]: 59
2776 04:50:28.695568
2777 04:50:28.696027 Set Vref, RX VrefLevel [Byte0]: 60
2778 04:50:28.699116 [Byte1]: 60
2779 04:50:28.703598
2780 04:50:28.704236 Set Vref, RX VrefLevel [Byte0]: 61
2781 04:50:28.706751 [Byte1]: 61
2782 04:50:28.711680
2783 04:50:28.712233 Set Vref, RX VrefLevel [Byte0]: 62
2784 04:50:28.714663 [Byte1]: 62
2785 04:50:28.719423
2786 04:50:28.719989 Set Vref, RX VrefLevel [Byte0]: 63
2787 04:50:28.722565 [Byte1]: 63
2788 04:50:28.726853
2789 04:50:28.727309 Set Vref, RX VrefLevel [Byte0]: 64
2790 04:50:28.730578 [Byte1]: 64
2791 04:50:28.735079
2792 04:50:28.735628 Set Vref, RX VrefLevel [Byte0]: 65
2793 04:50:28.738509 [Byte1]: 65
2794 04:50:28.743309
2795 04:50:28.743864 Set Vref, RX VrefLevel [Byte0]: 66
2796 04:50:28.746569 [Byte1]: 66
2797 04:50:28.750812
2798 04:50:28.751363 Set Vref, RX VrefLevel [Byte0]: 67
2799 04:50:28.754342 [Byte1]: 67
2800 04:50:28.758664
2801 04:50:28.759123 Set Vref, RX VrefLevel [Byte0]: 68
2802 04:50:28.762196 [Byte1]: 68
2803 04:50:28.766648
2804 04:50:28.767197 Set Vref, RX VrefLevel [Byte0]: 69
2805 04:50:28.770007 [Byte1]: 69
2806 04:50:28.774776
2807 04:50:28.775332 Final RX Vref Byte 0 = 59 to rank0
2808 04:50:28.777856 Final RX Vref Byte 1 = 50 to rank0
2809 04:50:28.781271 Final RX Vref Byte 0 = 59 to rank1
2810 04:50:28.784381 Final RX Vref Byte 1 = 50 to rank1==
2811 04:50:28.787843 Dram Type= 6, Freq= 0, CH_0, rank 0
2812 04:50:28.794467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2813 04:50:28.794966 ==
2814 04:50:28.795367 DQS Delay:
2815 04:50:28.795709 DQS0 = 0, DQS1 = 0
2816 04:50:28.798055 DQM Delay:
2817 04:50:28.798518 DQM0 = 122, DQM1 = 109
2818 04:50:28.801296 DQ Delay:
2819 04:50:28.804197 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2820 04:50:28.807603 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2821 04:50:28.811338 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2822 04:50:28.814467 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2823 04:50:28.814934
2824 04:50:28.815314
2825 04:50:28.821037 [DQSOSCAuto] RK0, (LSB)MR18= 0x703, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 407 ps
2826 04:50:28.824411 CH0 RK0: MR19=404, MR18=703
2827 04:50:28.831229 CH0_RK0: MR19=0x404, MR18=0x703, DQSOSC=407, MR23=63, INC=39, DEC=26
2828 04:50:28.831770
2829 04:50:28.834031 ----->DramcWriteLeveling(PI) begin...
2830 04:50:28.834495 ==
2831 04:50:28.837767 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 04:50:28.841010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 04:50:28.844472 ==
2834 04:50:28.845021 Write leveling (Byte 0): 34 => 34
2835 04:50:28.847868 Write leveling (Byte 1): 30 => 30
2836 04:50:28.851192 DramcWriteLeveling(PI) end<-----
2837 04:50:28.851744
2838 04:50:28.852102 ==
2839 04:50:28.854278 Dram Type= 6, Freq= 0, CH_0, rank 1
2840 04:50:28.860807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2841 04:50:28.861266 ==
2842 04:50:28.861651 [Gating] SW mode calibration
2843 04:50:28.870907 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2844 04:50:28.874652 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2845 04:50:28.877708 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2846 04:50:28.884337 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 04:50:28.887973 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 04:50:28.891124 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 04:50:28.897592 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 04:50:28.900825 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 04:50:28.904689 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 04:50:28.910794 0 15 28 | B1->B0 | 2c2c 2c2c | 1 0 | (1 1) (0 1)
2853 04:50:28.914426 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2854 04:50:28.917928 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 04:50:28.924317 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 04:50:28.927586 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 04:50:28.931289 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 04:50:28.938269 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 04:50:28.941091 1 0 24 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
2860 04:50:28.944521 1 0 28 | B1->B0 | 3c3c 3b3b | 0 0 | (0 0) (0 0)
2861 04:50:28.947740 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 04:50:28.954424 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 04:50:28.958028 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 04:50:28.961016 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 04:50:28.968008 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 04:50:28.971208 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 04:50:28.974230 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 04:50:28.981378 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2869 04:50:28.984964 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2870 04:50:28.987930 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 04:50:28.994475 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 04:50:28.998052 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 04:50:29.001263 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 04:50:29.007869 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 04:50:29.011124 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 04:50:29.014766 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 04:50:29.021243 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 04:50:29.024367 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 04:50:29.027988 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 04:50:29.031475 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 04:50:29.038098 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 04:50:29.041661 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 04:50:29.045013 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 04:50:29.051609 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2885 04:50:29.055292 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2886 04:50:29.058041 Total UI for P1: 0, mck2ui 16
2887 04:50:29.061239 best dqsien dly found for B1: ( 1, 3, 28)
2888 04:50:29.065130 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 04:50:29.068302 Total UI for P1: 0, mck2ui 16
2890 04:50:29.071528 best dqsien dly found for B0: ( 1, 3, 30)
2891 04:50:29.074750 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2892 04:50:29.078308 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2893 04:50:29.078862
2894 04:50:29.082075 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2895 04:50:29.088671 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2896 04:50:29.089226 [Gating] SW calibration Done
2897 04:50:29.091565 ==
2898 04:50:29.092027 Dram Type= 6, Freq= 0, CH_0, rank 1
2899 04:50:29.098395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 04:50:29.098951 ==
2901 04:50:29.099327 RX Vref Scan: 0
2902 04:50:29.099801
2903 04:50:29.101644 RX Vref 0 -> 0, step: 1
2904 04:50:29.102248
2905 04:50:29.104954 RX Delay -40 -> 252, step: 8
2906 04:50:29.108609 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2907 04:50:29.111774 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2908 04:50:29.115412 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2909 04:50:29.121694 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2910 04:50:29.125640 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2911 04:50:29.128282 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2912 04:50:29.131640 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2913 04:50:29.134989 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2914 04:50:29.138519 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2915 04:50:29.145148 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2916 04:50:29.148537 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2917 04:50:29.152179 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2918 04:50:29.155689 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2919 04:50:29.158374 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2920 04:50:29.165246 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2921 04:50:29.168799 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2922 04:50:29.169353 ==
2923 04:50:29.171815 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 04:50:29.175606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 04:50:29.176168 ==
2926 04:50:29.178709 DQS Delay:
2927 04:50:29.179262 DQS0 = 0, DQS1 = 0
2928 04:50:29.179625 DQM Delay:
2929 04:50:29.182545 DQM0 = 120, DQM1 = 108
2930 04:50:29.183097 DQ Delay:
2931 04:50:29.185266 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2932 04:50:29.188712 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2933 04:50:29.192009 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2934 04:50:47.770004 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2935 04:50:47.770231
2936 04:50:47.770336
2937 04:50:47.770435 ==
2938 04:50:47.770534 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 04:50:47.770631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 04:50:47.770727 ==
2941 04:50:47.770823
2942 04:50:47.770917
2943 04:50:47.771010 TX Vref Scan disable
2944 04:50:47.771105 == TX Byte 0 ==
2945 04:50:47.771200 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2946 04:50:47.771294 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2947 04:50:47.771389 == TX Byte 1 ==
2948 04:50:47.771482 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2949 04:50:47.771576 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2950 04:50:47.771670 ==
2951 04:50:47.771778 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 04:50:47.771889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 04:50:47.771984 ==
2954 04:50:47.772078 TX Vref=22, minBit 3, minWin=24, winSum=409
2955 04:50:47.772171 TX Vref=24, minBit 1, minWin=24, winSum=413
2956 04:50:47.772264 TX Vref=26, minBit 1, minWin=24, winSum=418
2957 04:50:47.772357 TX Vref=28, minBit 1, minWin=24, winSum=420
2958 04:50:47.772451 TX Vref=30, minBit 1, minWin=25, winSum=421
2959 04:50:47.772543 TX Vref=32, minBit 1, minWin=25, winSum=422
2960 04:50:47.772635 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 32
2961 04:50:47.772727
2962 04:50:47.772818 Final TX Range 1 Vref 32
2963 04:50:47.772912
2964 04:50:47.773003 ==
2965 04:50:47.773095 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 04:50:47.773187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 04:50:47.773280 ==
2968 04:50:47.773372
2969 04:50:47.773464
2970 04:50:47.773555 TX Vref Scan disable
2971 04:50:47.773646 == TX Byte 0 ==
2972 04:50:47.773738 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2973 04:50:47.773831 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2974 04:50:47.773923 == TX Byte 1 ==
2975 04:50:47.774073 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2976 04:50:47.774166 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2977 04:50:47.774259
2978 04:50:47.774349 [DATLAT]
2979 04:50:47.774441 Freq=1200, CH0 RK1
2980 04:50:47.774532
2981 04:50:47.774623 DATLAT Default: 0xd
2982 04:50:47.774715 0, 0xFFFF, sum = 0
2983 04:50:47.774809 1, 0xFFFF, sum = 0
2984 04:50:47.774903 2, 0xFFFF, sum = 0
2985 04:50:47.774997 3, 0xFFFF, sum = 0
2986 04:50:47.775090 4, 0xFFFF, sum = 0
2987 04:50:47.775184 5, 0xFFFF, sum = 0
2988 04:50:47.775278 6, 0xFFFF, sum = 0
2989 04:50:47.775372 7, 0xFFFF, sum = 0
2990 04:50:47.775480 8, 0xFFFF, sum = 0
2991 04:50:47.775630 9, 0xFFFF, sum = 0
2992 04:50:47.775724 10, 0xFFFF, sum = 0
2993 04:50:47.775818 11, 0xFFFF, sum = 0
2994 04:50:47.775911 12, 0x0, sum = 1
2995 04:50:47.776005 13, 0x0, sum = 2
2996 04:50:47.776097 14, 0x0, sum = 3
2997 04:50:47.776190 15, 0x0, sum = 4
2998 04:50:47.776284 best_step = 13
2999 04:50:47.776375
3000 04:50:47.776466 ==
3001 04:50:47.776557 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 04:50:47.776649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 04:50:47.776742 ==
3004 04:50:47.776835 RX Vref Scan: 0
3005 04:50:47.776926
3006 04:50:47.777017 RX Vref 0 -> 0, step: 1
3007 04:50:47.777108
3008 04:50:47.777199 RX Delay -21 -> 252, step: 4
3009 04:50:47.777290 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3010 04:50:47.777382 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3011 04:50:47.777473 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3012 04:50:47.777563 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3013 04:50:47.777655 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3014 04:50:47.777746 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3015 04:50:47.777838 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3016 04:50:47.777928 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3017 04:50:47.778060 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3018 04:50:47.778152 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3019 04:50:47.778243 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3020 04:50:47.778335 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3021 04:50:47.778426 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3022 04:50:47.778517 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3023 04:50:47.778607 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3024 04:50:47.778700 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3025 04:50:47.778790 ==
3026 04:50:47.778882 Dram Type= 6, Freq= 0, CH_0, rank 1
3027 04:50:47.778973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3028 04:50:47.779065 ==
3029 04:50:47.779157 DQS Delay:
3030 04:50:47.779248 DQS0 = 0, DQS1 = 0
3031 04:50:47.779339 DQM Delay:
3032 04:50:47.779429 DQM0 = 119, DQM1 = 107
3033 04:50:47.779520 DQ Delay:
3034 04:50:47.779610 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =116
3035 04:50:47.779702 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3036 04:50:47.779793 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =104
3037 04:50:47.779884 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3038 04:50:47.779974
3039 04:50:47.780064
3040 04:50:47.780154 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3041 04:50:47.780247 CH0 RK1: MR19=403, MR18=BF2
3042 04:50:47.780340 CH0_RK1: MR19=0x403, MR18=0xBF2, DQSOSC=405, MR23=63, INC=39, DEC=26
3043 04:50:47.780432 [RxdqsGatingPostProcess] freq 1200
3044 04:50:47.780524 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3045 04:50:47.780615 best DQS0 dly(2T, 0.5T) = (0, 11)
3046 04:50:47.780706 best DQS1 dly(2T, 0.5T) = (0, 11)
3047 04:50:47.780798 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3048 04:50:47.780889 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3049 04:50:47.780980 best DQS0 dly(2T, 0.5T) = (0, 11)
3050 04:50:47.781072 best DQS1 dly(2T, 0.5T) = (0, 11)
3051 04:50:47.781163 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3052 04:50:47.781255 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3053 04:50:47.781347 Pre-setting of DQS Precalculation
3054 04:50:47.781438 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3055 04:50:47.781531 ==
3056 04:50:47.781623 Dram Type= 6, Freq= 0, CH_1, rank 0
3057 04:50:47.781715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3058 04:50:47.781811 ==
3059 04:50:47.781885 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3060 04:50:47.781963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3061 04:50:47.782038 [CA 0] Center 37 (7~68) winsize 62
3062 04:50:47.782130 [CA 1] Center 37 (7~68) winsize 62
3063 04:50:47.782222 [CA 2] Center 35 (5~65) winsize 61
3064 04:50:47.782313 [CA 3] Center 34 (4~65) winsize 62
3065 04:50:47.782404 [CA 4] Center 34 (3~65) winsize 63
3066 04:50:47.782494 [CA 5] Center 33 (3~64) winsize 62
3067 04:50:47.782583
3068 04:50:47.782673 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3069 04:50:47.782763
3070 04:50:47.782853 [CATrainingPosCal] consider 1 rank data
3071 04:50:47.782943 u2DelayCellTimex100 = 270/100 ps
3072 04:50:47.783231 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3073 04:50:47.783324 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3074 04:50:47.783418 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3075 04:50:47.783510 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3076 04:50:47.783602 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
3077 04:50:47.783693 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3078 04:50:47.783784
3079 04:50:47.783875 CA PerBit enable=1, Macro0, CA PI delay=33
3080 04:50:47.783965
3081 04:50:47.784056 [CBTSetCACLKResult] CA Dly = 33
3082 04:50:47.784147 CS Dly: 5 (0~36)
3083 04:50:47.784238 ==
3084 04:50:47.784329 Dram Type= 6, Freq= 0, CH_1, rank 1
3085 04:50:47.784419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 04:50:47.784510 ==
3087 04:50:47.784600 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3088 04:50:47.784691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3089 04:50:47.784781 [CA 0] Center 38 (8~68) winsize 61
3090 04:50:47.784871 [CA 1] Center 38 (7~69) winsize 63
3091 04:50:47.784961 [CA 2] Center 35 (5~66) winsize 62
3092 04:50:47.785051 [CA 3] Center 35 (5~65) winsize 61
3093 04:50:47.785141 [CA 4] Center 34 (4~64) winsize 61
3094 04:50:47.785231 [CA 5] Center 34 (4~64) winsize 61
3095 04:50:47.785320
3096 04:50:47.785410 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3097 04:50:47.785500
3098 04:50:47.785590 [CATrainingPosCal] consider 2 rank data
3099 04:50:47.785680 u2DelayCellTimex100 = 270/100 ps
3100 04:50:47.785770 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3101 04:50:47.785860 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3102 04:50:47.785957 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3103 04:50:47.786049 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3104 04:50:47.786139 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3105 04:50:47.786229 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3106 04:50:47.786319
3107 04:50:47.786409 CA PerBit enable=1, Macro0, CA PI delay=34
3108 04:50:47.786498
3109 04:50:47.786588 [CBTSetCACLKResult] CA Dly = 34
3110 04:50:47.786677 CS Dly: 6 (0~39)
3111 04:50:47.786766
3112 04:50:47.786856 ----->DramcWriteLeveling(PI) begin...
3113 04:50:47.786948 ==
3114 04:50:47.787038 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 04:50:47.787128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 04:50:47.787218 ==
3117 04:50:47.787308 Write leveling (Byte 0): 25 => 25
3118 04:50:47.787398 Write leveling (Byte 1): 29 => 29
3119 04:50:47.787488 DramcWriteLeveling(PI) end<-----
3120 04:50:47.787577
3121 04:50:47.787667 ==
3122 04:50:47.787757 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 04:50:47.787847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 04:50:47.787937 ==
3125 04:50:47.788027 [Gating] SW mode calibration
3126 04:50:47.788117 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3127 04:50:47.788208 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3128 04:50:47.788298 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 04:50:47.788388 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 04:50:47.788478 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 04:50:47.788568 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 04:50:47.788658 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 04:50:47.788747 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3134 04:50:47.788837 0 15 24 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (1 0)
3135 04:50:47.788926 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3136 04:50:47.789015 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 04:50:47.789105 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 04:50:47.789195 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 04:50:47.789284 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 04:50:47.789373 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 04:50:47.789463 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3142 04:50:47.789553 1 0 24 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
3143 04:50:47.789642 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 04:50:47.789732 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 04:50:47.789821 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 04:50:47.789910 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 04:50:47.790006 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 04:50:47.790096 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 04:50:47.790186 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 04:50:47.790276 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3151 04:50:47.790365 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3152 04:50:47.790455 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 04:50:47.790545 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 04:50:47.790635 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 04:50:47.790725 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 04:50:47.790814 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 04:50:47.790904 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 04:50:47.790994 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 04:50:47.791083 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 04:50:47.791173 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 04:50:47.791262 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 04:50:47.791352 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 04:50:47.791441 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 04:50:47.791531 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 04:50:47.791621 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3166 04:50:47.791710 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3167 04:50:47.791799 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3168 04:50:47.791889 Total UI for P1: 0, mck2ui 16
3169 04:50:47.791980 best dqsien dly found for B0: ( 1, 3, 22)
3170 04:50:47.792070 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 04:50:47.792160 Total UI for P1: 0, mck2ui 16
3172 04:50:47.792251 best dqsien dly found for B1: ( 1, 3, 26)
3173 04:50:47.792341 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3174 04:50:47.792431 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3175 04:50:47.792521
3176 04:50:47.792809 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3177 04:50:47.792904 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3178 04:50:47.793014 [Gating] SW calibration Done
3179 04:50:47.793109 ==
3180 04:50:47.793202 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 04:50:47.793309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 04:50:47.793401 ==
3183 04:50:47.793492 RX Vref Scan: 0
3184 04:50:47.793583
3185 04:50:47.793674 RX Vref 0 -> 0, step: 1
3186 04:50:47.793765
3187 04:50:47.793856 RX Delay -40 -> 252, step: 8
3188 04:50:47.793953 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3189 04:50:47.794079 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3190 04:50:47.794170 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3191 04:50:47.794260 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3192 04:50:47.794350 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3193 04:50:47.794440 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3194 04:50:47.794530 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3195 04:50:47.794620 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3196 04:50:47.794710 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3197 04:50:47.794800 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3198 04:50:47.794889 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3199 04:50:47.794979 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3200 04:50:47.795069 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3201 04:50:47.795158 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3202 04:50:47.795247 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3203 04:50:47.795337 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3204 04:50:47.795426 ==
3205 04:50:47.795516 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 04:50:47.795606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 04:50:47.795697 ==
3208 04:50:47.795786 DQS Delay:
3209 04:50:47.795876 DQS0 = 0, DQS1 = 0
3210 04:50:47.795969 DQM Delay:
3211 04:50:47.796069 DQM0 = 121, DQM1 = 112
3212 04:50:47.796157 DQ Delay:
3213 04:50:47.796242 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3214 04:50:47.796325 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3215 04:50:47.796407 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3216 04:50:47.796505 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3217 04:50:47.796587
3218 04:50:47.796674
3219 04:50:47.796757 ==
3220 04:50:47.796840 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 04:50:47.796924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 04:50:47.797008 ==
3223 04:50:47.797090
3224 04:50:47.797172
3225 04:50:47.797255 TX Vref Scan disable
3226 04:50:47.797338 == TX Byte 0 ==
3227 04:50:47.797421 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3228 04:50:47.797506 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3229 04:50:47.797588 == TX Byte 1 ==
3230 04:50:47.797672 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3231 04:50:47.797759 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3232 04:50:47.797848 ==
3233 04:50:47.797932 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 04:50:47.798044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 04:50:47.798099 ==
3236 04:50:47.798153 TX Vref=22, minBit 1, minWin=24, winSum=403
3237 04:50:47.798206 TX Vref=24, minBit 3, minWin=25, winSum=409
3238 04:50:47.798284 TX Vref=26, minBit 8, minWin=25, winSum=417
3239 04:50:47.798351 TX Vref=28, minBit 9, minWin=25, winSum=425
3240 04:50:47.798404 TX Vref=30, minBit 9, minWin=25, winSum=421
3241 04:50:47.798458 TX Vref=32, minBit 14, minWin=25, winSum=422
3242 04:50:47.798512 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 28
3243 04:50:47.798565
3244 04:50:47.798618 Final TX Range 1 Vref 28
3245 04:50:47.798671
3246 04:50:47.798723 ==
3247 04:50:47.798777 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 04:50:47.798830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 04:50:47.798884 ==
3250 04:50:47.798936
3251 04:50:47.798989
3252 04:50:47.799041 TX Vref Scan disable
3253 04:50:47.799094 == TX Byte 0 ==
3254 04:50:47.799147 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3255 04:50:47.799200 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3256 04:50:47.799253 == TX Byte 1 ==
3257 04:50:47.799306 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3258 04:50:47.799359 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3259 04:50:47.799411
3260 04:50:47.799463 [DATLAT]
3261 04:50:47.799517 Freq=1200, CH1 RK0
3262 04:50:47.799570
3263 04:50:47.799622 DATLAT Default: 0xd
3264 04:50:47.799675 0, 0xFFFF, sum = 0
3265 04:50:47.799730 1, 0xFFFF, sum = 0
3266 04:50:47.799784 2, 0xFFFF, sum = 0
3267 04:50:47.799838 3, 0xFFFF, sum = 0
3268 04:50:47.799892 4, 0xFFFF, sum = 0
3269 04:50:47.799945 5, 0xFFFF, sum = 0
3270 04:50:47.799999 6, 0xFFFF, sum = 0
3271 04:50:47.800081 7, 0xFFFF, sum = 0
3272 04:50:47.800135 8, 0xFFFF, sum = 0
3273 04:50:47.800188 9, 0xFFFF, sum = 0
3274 04:50:47.800242 10, 0xFFFF, sum = 0
3275 04:50:47.800295 11, 0xFFFF, sum = 0
3276 04:50:47.800377 12, 0x0, sum = 1
3277 04:50:47.800430 13, 0x0, sum = 2
3278 04:50:47.800483 14, 0x0, sum = 3
3279 04:50:47.800537 15, 0x0, sum = 4
3280 04:50:47.800590 best_step = 13
3281 04:50:47.800643
3282 04:50:47.800696 ==
3283 04:50:47.800748 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 04:50:47.800801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 04:50:47.800854 ==
3286 04:50:47.800907 RX Vref Scan: 1
3287 04:50:47.800960
3288 04:50:47.801012 Set Vref Range= 32 -> 127
3289 04:50:47.801064
3290 04:50:47.801116 RX Vref 32 -> 127, step: 1
3291 04:50:47.801169
3292 04:50:47.801221 RX Delay -13 -> 252, step: 4
3293 04:50:47.801273
3294 04:50:47.801325 Set Vref, RX VrefLevel [Byte0]: 32
3295 04:50:47.801377 [Byte1]: 32
3296 04:50:47.801427
3297 04:50:47.801478 Set Vref, RX VrefLevel [Byte0]: 33
3298 04:50:47.801529 [Byte1]: 33
3299 04:50:47.801580
3300 04:50:47.801631 Set Vref, RX VrefLevel [Byte0]: 34
3301 04:50:47.801682 [Byte1]: 34
3302 04:50:47.801733
3303 04:50:47.801784 Set Vref, RX VrefLevel [Byte0]: 35
3304 04:50:47.801836 [Byte1]: 35
3305 04:50:47.801887
3306 04:50:47.801945 Set Vref, RX VrefLevel [Byte0]: 36
3307 04:50:47.802048 [Byte1]: 36
3308 04:50:47.802100
3309 04:50:47.802151 Set Vref, RX VrefLevel [Byte0]: 37
3310 04:50:47.802202 [Byte1]: 37
3311 04:50:47.802253
3312 04:50:47.802304 Set Vref, RX VrefLevel [Byte0]: 38
3313 04:50:47.802399 [Byte1]: 38
3314 04:50:47.802492
3315 04:50:47.802543 Set Vref, RX VrefLevel [Byte0]: 39
3316 04:50:47.802594 [Byte1]: 39
3317 04:50:47.802645
3318 04:50:47.802696 Set Vref, RX VrefLevel [Byte0]: 40
3319 04:50:47.802747 [Byte1]: 40
3320 04:50:47.802799
3321 04:50:47.802849 Set Vref, RX VrefLevel [Byte0]: 41
3322 04:50:47.802901 [Byte1]: 41
3323 04:50:47.802952
3324 04:50:47.803002 Set Vref, RX VrefLevel [Byte0]: 42
3325 04:50:47.803083 [Byte1]: 42
3326 04:50:47.803134
3327 04:50:47.803185 Set Vref, RX VrefLevel [Byte0]: 43
3328 04:50:47.803235 [Byte1]: 43
3329 04:50:47.803286
3330 04:50:47.803336 Set Vref, RX VrefLevel [Byte0]: 44
3331 04:50:47.803583 [Byte1]: 44
3332 04:50:47.803697
3333 04:50:47.803751 Set Vref, RX VrefLevel [Byte0]: 45
3334 04:50:47.803804 [Byte1]: 45
3335 04:50:47.803857
3336 04:50:47.803909 Set Vref, RX VrefLevel [Byte0]: 46
3337 04:50:47.803964 [Byte1]: 46
3338 04:50:47.804017
3339 04:50:47.804070 Set Vref, RX VrefLevel [Byte0]: 47
3340 04:50:47.804134 [Byte1]: 47
3341 04:50:47.804185
3342 04:50:47.804237 Set Vref, RX VrefLevel [Byte0]: 48
3343 04:50:47.804288 [Byte1]: 48
3344 04:50:47.804339
3345 04:50:47.804389 Set Vref, RX VrefLevel [Byte0]: 49
3346 04:50:47.804441 [Byte1]: 49
3347 04:50:47.804492
3348 04:50:47.804543 Set Vref, RX VrefLevel [Byte0]: 50
3349 04:50:47.804594 [Byte1]: 50
3350 04:50:47.804645
3351 04:50:47.804696 Set Vref, RX VrefLevel [Byte0]: 51
3352 04:50:47.804747 [Byte1]: 51
3353 04:50:47.804798
3354 04:50:47.804849 Set Vref, RX VrefLevel [Byte0]: 52
3355 04:50:47.804901 [Byte1]: 52
3356 04:50:47.804951
3357 04:50:47.805002 Set Vref, RX VrefLevel [Byte0]: 53
3358 04:50:47.805053 [Byte1]: 53
3359 04:50:47.805104
3360 04:50:47.805155 Set Vref, RX VrefLevel [Byte0]: 54
3361 04:50:47.805207 [Byte1]: 54
3362 04:50:47.805258
3363 04:50:47.805309 Set Vref, RX VrefLevel [Byte0]: 55
3364 04:50:47.805360 [Byte1]: 55
3365 04:50:47.805411
3366 04:50:47.805462 Set Vref, RX VrefLevel [Byte0]: 56
3367 04:50:47.805513 [Byte1]: 56
3368 04:50:47.805564
3369 04:50:47.805619 Set Vref, RX VrefLevel [Byte0]: 57
3370 04:50:47.805708 [Byte1]: 57
3371 04:50:47.805793
3372 04:50:47.805875 Set Vref, RX VrefLevel [Byte0]: 58
3373 04:50:47.805986 [Byte1]: 58
3374 04:50:47.806057
3375 04:50:47.806110 Set Vref, RX VrefLevel [Byte0]: 59
3376 04:50:47.806178 [Byte1]: 59
3377 04:50:47.806231
3378 04:50:47.806313 Set Vref, RX VrefLevel [Byte0]: 60
3379 04:50:47.806369 [Byte1]: 60
3380 04:50:47.806421
3381 04:50:47.806472 Set Vref, RX VrefLevel [Byte0]: 61
3382 04:50:47.806524 [Byte1]: 61
3383 04:50:47.806575
3384 04:50:47.806627 Set Vref, RX VrefLevel [Byte0]: 62
3385 04:50:47.806678 [Byte1]: 62
3386 04:50:47.806729
3387 04:50:47.806780 Set Vref, RX VrefLevel [Byte0]: 63
3388 04:50:47.806831 [Byte1]: 63
3389 04:50:47.806882
3390 04:50:47.806933 Set Vref, RX VrefLevel [Byte0]: 64
3391 04:50:47.806984 [Byte1]: 64
3392 04:50:47.807035
3393 04:50:47.807085 Set Vref, RX VrefLevel [Byte0]: 65
3394 04:50:47.807136 [Byte1]: 65
3395 04:50:47.807187
3396 04:50:47.807238 Set Vref, RX VrefLevel [Byte0]: 66
3397 04:50:47.807288 [Byte1]: 66
3398 04:50:47.807340
3399 04:50:47.807391 Final RX Vref Byte 0 = 52 to rank0
3400 04:50:47.807442 Final RX Vref Byte 1 = 53 to rank0
3401 04:50:47.807494 Final RX Vref Byte 0 = 52 to rank1
3402 04:50:47.807546 Final RX Vref Byte 1 = 53 to rank1==
3403 04:50:47.807598 Dram Type= 6, Freq= 0, CH_1, rank 0
3404 04:50:47.807649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3405 04:50:47.807702 ==
3406 04:50:47.807753 DQS Delay:
3407 04:50:47.807804 DQS0 = 0, DQS1 = 0
3408 04:50:47.807856 DQM Delay:
3409 04:50:47.807907 DQM0 = 119, DQM1 = 112
3410 04:50:47.807958 DQ Delay:
3411 04:50:47.808009 DQ0 =122, DQ1 =112, DQ2 =112, DQ3 =118
3412 04:50:47.808061 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3413 04:50:47.808112 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3414 04:50:47.808164 DQ12 =122, DQ13 =116, DQ14 =120, DQ15 =118
3415 04:50:47.808215
3416 04:50:47.808266
3417 04:50:47.808316 [DQSOSCAuto] RK0, (LSB)MR18= 0x316, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3418 04:50:47.808368 CH1 RK0: MR19=404, MR18=316
3419 04:50:47.808420 CH1_RK0: MR19=0x404, MR18=0x316, DQSOSC=401, MR23=63, INC=40, DEC=27
3420 04:50:47.808472
3421 04:50:47.808524 ----->DramcWriteLeveling(PI) begin...
3422 04:50:47.808576 ==
3423 04:50:47.808627 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 04:50:47.808679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 04:50:47.808731 ==
3426 04:50:47.808783 Write leveling (Byte 0): 26 => 26
3427 04:50:47.808834 Write leveling (Byte 1): 30 => 30
3428 04:50:47.808885 DramcWriteLeveling(PI) end<-----
3429 04:50:47.808937
3430 04:50:47.808988 ==
3431 04:50:47.809039 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 04:50:47.809089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 04:50:47.809141 ==
3434 04:50:47.809192 [Gating] SW mode calibration
3435 04:50:47.809244 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3436 04:50:47.809295 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3437 04:50:47.809347 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 04:50:47.809399 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 04:50:47.809450 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 04:50:47.809502 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 04:50:47.809553 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 04:50:47.809605 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 04:50:47.809656 0 15 24 | B1->B0 | 2929 3333 | 0 0 | (1 0) (0 1)
3444 04:50:47.809707 0 15 28 | B1->B0 | 2323 2b2b | 0 0 | (1 0) (0 0)
3445 04:50:47.809759 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 04:50:47.809810 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 04:50:47.809861 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 04:50:47.809912 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 04:50:47.809990 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 04:50:47.810056 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 04:50:47.810107 1 0 24 | B1->B0 | 3d3d 3030 | 0 0 | (0 0) (0 0)
3452 04:50:47.810159 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3453 04:50:47.810210 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 04:50:47.810261 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 04:50:47.810313 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 04:50:47.810365 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 04:50:47.810417 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 04:50:47.810468 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 04:50:47.810519 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3460 04:50:47.810763 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3461 04:50:47.810821 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 04:50:47.810874 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 04:50:47.810927 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 04:50:47.810978 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 04:50:47.811030 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 04:50:47.811082 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 04:50:47.811133 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 04:50:47.811185 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 04:50:47.811236 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 04:50:47.811288 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 04:50:47.811339 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 04:50:47.811391 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 04:50:47.811442 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 04:50:47.811493 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 04:50:47.811545 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3476 04:50:47.811596 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3477 04:50:47.811647 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 04:50:47.811698 Total UI for P1: 0, mck2ui 16
3479 04:50:47.811750 best dqsien dly found for B0: ( 1, 3, 26)
3480 04:50:47.811802 Total UI for P1: 0, mck2ui 16
3481 04:50:47.811854 best dqsien dly found for B1: ( 1, 3, 26)
3482 04:50:47.811905 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3483 04:50:47.811956 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3484 04:50:47.812007
3485 04:50:47.812058 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3486 04:50:47.812109 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3487 04:50:47.812166 [Gating] SW calibration Done
3488 04:50:47.812243 ==
3489 04:50:47.812309 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 04:50:47.812360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 04:50:47.812413 ==
3492 04:50:47.812465 RX Vref Scan: 0
3493 04:50:47.812517
3494 04:50:47.812568 RX Vref 0 -> 0, step: 1
3495 04:50:47.812619
3496 04:50:47.812670 RX Delay -40 -> 252, step: 8
3497 04:50:47.812721 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3498 04:50:47.812773 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3499 04:50:47.812824 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3500 04:50:47.812875 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3501 04:50:47.812926 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3502 04:50:47.812977 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3503 04:50:47.813029 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3504 04:50:47.813079 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3505 04:50:47.813131 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3506 04:50:47.813182 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3507 04:50:47.813233 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3508 04:50:47.813284 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3509 04:50:47.813335 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3510 04:50:47.813387 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3511 04:50:47.813438 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3512 04:50:47.813489 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3513 04:50:47.813540 ==
3514 04:50:47.813592 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 04:50:47.813643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 04:50:47.813694 ==
3517 04:50:47.813746 DQS Delay:
3518 04:50:47.813797 DQS0 = 0, DQS1 = 0
3519 04:50:47.813848 DQM Delay:
3520 04:50:47.813899 DQM0 = 120, DQM1 = 112
3521 04:50:47.813986 DQ Delay:
3522 04:50:47.814067 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3523 04:50:47.814119 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3524 04:50:47.814170 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3525 04:50:47.814239 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3526 04:50:47.814323
3527 04:50:47.814379
3528 04:50:47.814431 ==
3529 04:50:47.814483 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 04:50:47.814535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 04:50:47.814589 ==
3532 04:50:47.814640
3533 04:50:47.814691
3534 04:50:47.814743 TX Vref Scan disable
3535 04:50:47.814795 == TX Byte 0 ==
3536 04:50:47.814846 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3537 04:50:47.814898 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3538 04:50:47.814950 == TX Byte 1 ==
3539 04:50:47.815001 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3540 04:50:47.815052 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3541 04:50:47.815103 ==
3542 04:50:47.815155 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 04:50:47.815206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 04:50:47.815258 ==
3545 04:50:47.815309 TX Vref=22, minBit 0, minWin=25, winSum=416
3546 04:50:47.815361 TX Vref=24, minBit 1, minWin=25, winSum=425
3547 04:50:47.815413 TX Vref=26, minBit 1, minWin=26, winSum=428
3548 04:50:47.815465 TX Vref=28, minBit 9, minWin=25, winSum=427
3549 04:50:47.815516 TX Vref=30, minBit 1, minWin=27, winSum=435
3550 04:50:47.815567 TX Vref=32, minBit 7, minWin=26, winSum=433
3551 04:50:47.815618 [TxChooseVref] Worse bit 1, Min win 27, Win sum 435, Final Vref 30
3552 04:50:47.815669
3553 04:50:47.815721 Final TX Range 1 Vref 30
3554 04:50:47.815771
3555 04:50:47.815822 ==
3556 04:50:47.815873 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 04:50:47.815925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 04:50:47.815977 ==
3559 04:50:47.816030
3560 04:50:47.816081
3561 04:50:47.816132 TX Vref Scan disable
3562 04:50:47.816183 == TX Byte 0 ==
3563 04:50:47.816237 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3564 04:50:47.816289 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3565 04:50:47.816340 == TX Byte 1 ==
3566 04:50:47.816391 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3567 04:50:47.816445 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3568 04:50:47.816497
3569 04:50:47.816548 [DATLAT]
3570 04:50:47.816598 Freq=1200, CH1 RK1
3571 04:50:47.816650
3572 04:50:47.816702 DATLAT Default: 0xd
3573 04:50:47.816753 0, 0xFFFF, sum = 0
3574 04:50:47.816805 1, 0xFFFF, sum = 0
3575 04:50:47.816858 2, 0xFFFF, sum = 0
3576 04:50:47.816910 3, 0xFFFF, sum = 0
3577 04:50:47.816962 4, 0xFFFF, sum = 0
3578 04:50:47.817013 5, 0xFFFF, sum = 0
3579 04:50:47.817065 6, 0xFFFF, sum = 0
3580 04:50:47.817116 7, 0xFFFF, sum = 0
3581 04:50:47.817168 8, 0xFFFF, sum = 0
3582 04:50:47.817220 9, 0xFFFF, sum = 0
3583 04:50:47.817272 10, 0xFFFF, sum = 0
3584 04:50:47.817324 11, 0xFFFF, sum = 0
3585 04:50:47.817375 12, 0x0, sum = 1
3586 04:50:47.817427 13, 0x0, sum = 2
3587 04:50:47.817479 14, 0x0, sum = 3
3588 04:50:47.817530 15, 0x0, sum = 4
3589 04:50:47.817613 best_step = 13
3590 04:50:47.817692
3591 04:50:47.817777 ==
3592 04:50:47.817859 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 04:50:47.818144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 04:50:47.818235 ==
3595 04:50:47.818293 RX Vref Scan: 0
3596 04:50:47.818346
3597 04:50:47.818399 RX Vref 0 -> 0, step: 1
3598 04:50:47.818451
3599 04:50:47.818511 RX Delay -13 -> 252, step: 4
3600 04:50:47.818564 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3601 04:50:47.818617 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3602 04:50:47.818671 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3603 04:50:47.818724 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3604 04:50:47.818775 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3605 04:50:47.818827 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3606 04:50:47.818883 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3607 04:50:47.818935 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3608 04:50:47.818987 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3609 04:50:47.819040 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3610 04:50:47.819093 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3611 04:50:47.819145 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3612 04:50:47.819196 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3613 04:50:47.819248 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3614 04:50:47.819300 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3615 04:50:47.819352 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3616 04:50:47.819403 ==
3617 04:50:47.819455 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 04:50:47.819506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 04:50:47.819558 ==
3620 04:50:47.819609 DQS Delay:
3621 04:50:47.819661 DQS0 = 0, DQS1 = 0
3622 04:50:47.819713 DQM Delay:
3623 04:50:47.819764 DQM0 = 119, DQM1 = 113
3624 04:50:47.819816 DQ Delay:
3625 04:50:47.819867 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3626 04:50:47.819919 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3627 04:50:47.819971 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =108
3628 04:50:47.820023 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3629 04:50:47.820074
3630 04:50:47.820125
3631 04:50:47.820205 [DQSOSCAuto] RK1, (LSB)MR18= 0x5ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 408 ps
3632 04:50:47.820257 CH1 RK1: MR19=403, MR18=5EA
3633 04:50:47.820309 CH1_RK1: MR19=0x403, MR18=0x5EA, DQSOSC=408, MR23=63, INC=39, DEC=26
3634 04:50:47.820361 [RxdqsGatingPostProcess] freq 1200
3635 04:50:47.820412 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3636 04:50:47.820464 best DQS0 dly(2T, 0.5T) = (0, 11)
3637 04:50:47.820515 best DQS1 dly(2T, 0.5T) = (0, 11)
3638 04:50:47.820566 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3639 04:50:47.820618 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3640 04:50:47.820669 best DQS0 dly(2T, 0.5T) = (0, 11)
3641 04:50:47.820720 best DQS1 dly(2T, 0.5T) = (0, 11)
3642 04:50:47.820771 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3643 04:50:47.820823 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3644 04:50:47.820874 Pre-setting of DQS Precalculation
3645 04:50:47.820925 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3646 04:50:47.820977 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3647 04:50:47.821029 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3648 04:50:47.821081
3649 04:50:47.821132
3650 04:50:47.821183 [Calibration Summary] 2400 Mbps
3651 04:50:47.821235 CH 0, Rank 0
3652 04:50:47.821287 SW Impedance : PASS
3653 04:50:47.821339 DUTY Scan : NO K
3654 04:50:47.821390 ZQ Calibration : PASS
3655 04:50:47.821442 Jitter Meter : NO K
3656 04:50:47.821493 CBT Training : PASS
3657 04:50:47.821544 Write leveling : PASS
3658 04:50:47.821595 RX DQS gating : PASS
3659 04:50:47.821646 RX DQ/DQS(RDDQC) : PASS
3660 04:50:47.821698 TX DQ/DQS : PASS
3661 04:50:47.821750 RX DATLAT : PASS
3662 04:50:47.821801 RX DQ/DQS(Engine): PASS
3663 04:50:47.821852 TX OE : NO K
3664 04:50:47.821904 All Pass.
3665 04:50:47.822000
3666 04:50:47.822067 CH 0, Rank 1
3667 04:50:47.822118 SW Impedance : PASS
3668 04:50:47.822170 DUTY Scan : NO K
3669 04:50:47.822222 ZQ Calibration : PASS
3670 04:50:47.822273 Jitter Meter : NO K
3671 04:50:47.822325 CBT Training : PASS
3672 04:50:47.822376 Write leveling : PASS
3673 04:50:47.822428 RX DQS gating : PASS
3674 04:50:47.822479 RX DQ/DQS(RDDQC) : PASS
3675 04:50:47.822530 TX DQ/DQS : PASS
3676 04:50:47.822582 RX DATLAT : PASS
3677 04:50:47.822633 RX DQ/DQS(Engine): PASS
3678 04:50:47.822690 TX OE : NO K
3679 04:50:47.822772 All Pass.
3680 04:50:47.822852
3681 04:50:47.822932 CH 1, Rank 0
3682 04:50:47.823011 SW Impedance : PASS
3683 04:50:47.823092 DUTY Scan : NO K
3684 04:50:47.823171 ZQ Calibration : PASS
3685 04:50:47.823251 Jitter Meter : NO K
3686 04:50:47.823331 CBT Training : PASS
3687 04:50:47.823412 Write leveling : PASS
3688 04:50:47.823491 RX DQS gating : PASS
3689 04:50:47.823571 RX DQ/DQS(RDDQC) : PASS
3690 04:50:47.823651 TX DQ/DQS : PASS
3691 04:50:47.823732 RX DATLAT : PASS
3692 04:50:47.823812 RX DQ/DQS(Engine): PASS
3693 04:50:47.823892 TX OE : NO K
3694 04:50:47.823972 All Pass.
3695 04:50:47.824051
3696 04:50:47.824132 CH 1, Rank 1
3697 04:50:47.824212 SW Impedance : PASS
3698 04:50:47.824292 DUTY Scan : NO K
3699 04:50:47.824372 ZQ Calibration : PASS
3700 04:50:47.824451 Jitter Meter : NO K
3701 04:50:47.824532 CBT Training : PASS
3702 04:50:47.824611 Write leveling : PASS
3703 04:50:47.824692 RX DQS gating : PASS
3704 04:50:47.824772 RX DQ/DQS(RDDQC) : PASS
3705 04:50:47.824852 TX DQ/DQS : PASS
3706 04:50:47.824932 RX DATLAT : PASS
3707 04:50:47.825012 RX DQ/DQS(Engine): PASS
3708 04:50:47.825092 TX OE : NO K
3709 04:50:47.825172 All Pass.
3710 04:50:47.825251
3711 04:50:47.825331 DramC Write-DBI off
3712 04:50:47.825411 PER_BANK_REFRESH: Hybrid Mode
3713 04:50:47.825491 TX_TRACKING: ON
3714 04:50:47.825573 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3715 04:50:47.825655 [FAST_K] Save calibration result to emmc
3716 04:50:47.825736 dramc_set_vcore_voltage set vcore to 650000
3717 04:50:47.825816 Read voltage for 600, 5
3718 04:50:47.825895 Vio18 = 0
3719 04:50:47.825996 Vcore = 650000
3720 04:50:47.826062 Vdram = 0
3721 04:50:47.826114 Vddq = 0
3722 04:50:47.826166 Vmddr = 0
3723 04:50:47.826217 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3724 04:50:47.826269 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3725 04:50:47.826322 MEM_TYPE=3, freq_sel=19
3726 04:50:47.826377 sv_algorithm_assistance_LP4_1600
3727 04:50:47.826430 ============ PULL DRAM RESETB DOWN ============
3728 04:50:47.826481 ========== PULL DRAM RESETB DOWN end =========
3729 04:50:47.826536 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3730 04:50:47.826588 ===================================
3731 04:50:47.826832 LPDDR4 DRAM CONFIGURATION
3732 04:50:47.826929 ===================================
3733 04:50:47.826982 EX_ROW_EN[0] = 0x0
3734 04:50:47.827033 EX_ROW_EN[1] = 0x0
3735 04:50:47.827085 LP4Y_EN = 0x0
3736 04:50:47.827136 WORK_FSP = 0x0
3737 04:50:47.827188 WL = 0x2
3738 04:50:47.827240 RL = 0x2
3739 04:50:47.827291 BL = 0x2
3740 04:50:47.827341 RPST = 0x0
3741 04:50:47.827392 RD_PRE = 0x0
3742 04:50:47.827443 WR_PRE = 0x1
3743 04:50:47.827494 WR_PST = 0x0
3744 04:50:47.827545 DBI_WR = 0x0
3745 04:50:47.827595 DBI_RD = 0x0
3746 04:50:47.827645 OTF = 0x1
3747 04:50:47.827697 ===================================
3748 04:50:47.827749 ===================================
3749 04:50:47.827800 ANA top config
3750 04:50:47.827851 ===================================
3751 04:50:47.827903 DLL_ASYNC_EN = 0
3752 04:50:47.827954 ALL_SLAVE_EN = 1
3753 04:50:47.828005 NEW_RANK_MODE = 1
3754 04:50:47.828058 DLL_IDLE_MODE = 1
3755 04:50:47.828109 LP45_APHY_COMB_EN = 1
3756 04:50:47.828159 TX_ODT_DIS = 1
3757 04:50:47.828213 NEW_8X_MODE = 1
3758 04:50:47.828265 ===================================
3759 04:50:47.828351 ===================================
3760 04:50:47.828409 data_rate = 1200
3761 04:50:47.828463 CKR = 1
3762 04:50:47.828514 DQ_P2S_RATIO = 8
3763 04:50:47.828565 ===================================
3764 04:50:47.828626 CA_P2S_RATIO = 8
3765 04:50:47.828703 DQ_CA_OPEN = 0
3766 04:50:47.828767 DQ_SEMI_OPEN = 0
3767 04:50:47.828822 CA_SEMI_OPEN = 0
3768 04:50:47.828873 CA_FULL_RATE = 0
3769 04:50:47.828925 DQ_CKDIV4_EN = 1
3770 04:50:47.828990 CA_CKDIV4_EN = 1
3771 04:50:47.829070 CA_PREDIV_EN = 0
3772 04:50:47.829151 PH8_DLY = 0
3773 04:50:47.829231 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3774 04:50:47.829311 DQ_AAMCK_DIV = 4
3775 04:50:47.829391 CA_AAMCK_DIV = 4
3776 04:50:47.829470 CA_ADMCK_DIV = 4
3777 04:50:47.829550 DQ_TRACK_CA_EN = 0
3778 04:50:47.829630 CA_PICK = 600
3779 04:50:47.829710 CA_MCKIO = 600
3780 04:50:47.829790 MCKIO_SEMI = 0
3781 04:50:47.829870 PLL_FREQ = 2288
3782 04:50:47.829984 DQ_UI_PI_RATIO = 32
3783 04:50:47.830053 CA_UI_PI_RATIO = 0
3784 04:50:47.830134 ===================================
3785 04:50:47.830186 ===================================
3786 04:50:47.830238 memory_type:LPDDR4
3787 04:50:47.830289 GP_NUM : 10
3788 04:50:47.830341 SRAM_EN : 1
3789 04:50:47.830392 MD32_EN : 0
3790 04:50:47.830443 ===================================
3791 04:50:47.830494 [ANA_INIT] >>>>>>>>>>>>>>
3792 04:50:47.830545 <<<<<< [CONFIGURE PHASE]: ANA_TX
3793 04:50:47.830597 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3794 04:50:47.830648 ===================================
3795 04:50:47.830748 data_rate = 1200,PCW = 0X5800
3796 04:50:47.830814 ===================================
3797 04:50:47.830891 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3798 04:50:47.830955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 04:50:47.831009 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 04:50:47.831061 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3801 04:50:47.831113 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3802 04:50:47.831165 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3803 04:50:47.831216 [ANA_INIT] flow start
3804 04:50:47.831267 [ANA_INIT] PLL >>>>>>>>
3805 04:50:47.831317 [ANA_INIT] PLL <<<<<<<<
3806 04:50:47.831368 [ANA_INIT] MIDPI >>>>>>>>
3807 04:50:47.831419 [ANA_INIT] MIDPI <<<<<<<<
3808 04:50:47.831470 [ANA_INIT] DLL >>>>>>>>
3809 04:50:47.831521 [ANA_INIT] flow end
3810 04:50:47.831572 ============ LP4 DIFF to SE enter ============
3811 04:50:47.831623 ============ LP4 DIFF to SE exit ============
3812 04:50:47.831675 [ANA_INIT] <<<<<<<<<<<<<
3813 04:50:47.831726 [Flow] Enable top DCM control >>>>>
3814 04:50:47.831777 [Flow] Enable top DCM control <<<<<
3815 04:50:47.831828 Enable DLL master slave shuffle
3816 04:50:47.831880 ==============================================================
3817 04:50:47.831932 Gating Mode config
3818 04:50:47.831983 ==============================================================
3819 04:50:47.832034 Config description:
3820 04:50:47.832085 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3821 04:50:47.832137 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3822 04:50:47.832189 SELPH_MODE 0: By rank 1: By Phase
3823 04:50:47.832240 ==============================================================
3824 04:50:47.832292 GAT_TRACK_EN = 1
3825 04:50:47.832343 RX_GATING_MODE = 2
3826 04:50:47.832393 RX_GATING_TRACK_MODE = 2
3827 04:50:47.832444 SELPH_MODE = 1
3828 04:50:47.832495 PICG_EARLY_EN = 1
3829 04:50:47.832546 VALID_LAT_VALUE = 1
3830 04:50:47.832597 ==============================================================
3831 04:50:47.832649 Enter into Gating configuration >>>>
3832 04:50:47.832716 Exit from Gating configuration <<<<
3833 04:50:47.832780 Enter into DVFS_PRE_config >>>>>
3834 04:50:47.832831 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3835 04:50:47.832884 Exit from DVFS_PRE_config <<<<<
3836 04:50:47.832935 Enter into PICG configuration >>>>
3837 04:50:47.832986 Exit from PICG configuration <<<<
3838 04:50:47.833037 [RX_INPUT] configuration >>>>>
3839 04:50:47.833088 [RX_INPUT] configuration <<<<<
3840 04:50:47.833139 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3841 04:50:47.833190 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3842 04:50:47.833242 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3843 04:50:47.833489 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3844 04:50:47.833603 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3845 04:50:47.833658 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3846 04:50:47.833711 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3847 04:50:47.833764 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3848 04:50:47.833817 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3849 04:50:47.833870 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3850 04:50:47.833922 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3851 04:50:47.834020 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3852 04:50:47.834073 ===================================
3853 04:50:47.834126 LPDDR4 DRAM CONFIGURATION
3854 04:50:47.834178 ===================================
3855 04:50:47.834230 EX_ROW_EN[0] = 0x0
3856 04:50:47.834282 EX_ROW_EN[1] = 0x0
3857 04:50:47.834334 LP4Y_EN = 0x0
3858 04:50:47.834386 WORK_FSP = 0x0
3859 04:50:47.834438 WL = 0x2
3860 04:50:47.834501 RL = 0x2
3861 04:50:47.834552 BL = 0x2
3862 04:50:47.834603 RPST = 0x0
3863 04:50:47.834657 RD_PRE = 0x0
3864 04:50:47.834713 WR_PRE = 0x1
3865 04:50:47.834764 WR_PST = 0x0
3866 04:50:47.834815 DBI_WR = 0x0
3867 04:50:47.834866 DBI_RD = 0x0
3868 04:50:47.834917 OTF = 0x1
3869 04:50:47.834968 ===================================
3870 04:50:47.835020 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3871 04:50:47.835071 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3872 04:50:47.835122 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 04:50:47.835173 ===================================
3874 04:50:47.835224 LPDDR4 DRAM CONFIGURATION
3875 04:50:47.835275 ===================================
3876 04:50:47.835326 EX_ROW_EN[0] = 0x10
3877 04:50:47.835377 EX_ROW_EN[1] = 0x0
3878 04:50:47.835427 LP4Y_EN = 0x0
3879 04:50:47.835478 WORK_FSP = 0x0
3880 04:50:47.835529 WL = 0x2
3881 04:50:47.835580 RL = 0x2
3882 04:50:47.835630 BL = 0x2
3883 04:50:47.835681 RPST = 0x0
3884 04:50:47.835731 RD_PRE = 0x0
3885 04:50:47.835782 WR_PRE = 0x1
3886 04:50:47.835832 WR_PST = 0x0
3887 04:50:47.835882 DBI_WR = 0x0
3888 04:50:47.835932 DBI_RD = 0x0
3889 04:50:47.835983 OTF = 0x1
3890 04:50:47.836034 ===================================
3891 04:50:47.836086 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3892 04:50:47.836137 nWR fixed to 30
3893 04:50:47.836189 [ModeRegInit_LP4] CH0 RK0
3894 04:50:47.836240 [ModeRegInit_LP4] CH0 RK1
3895 04:50:47.836291 [ModeRegInit_LP4] CH1 RK0
3896 04:50:47.836342 [ModeRegInit_LP4] CH1 RK1
3897 04:50:47.836392 match AC timing 17
3898 04:50:47.836443 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3899 04:50:47.836495 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3900 04:50:47.836546 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3901 04:50:47.836597 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3902 04:50:47.836649 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3903 04:50:47.836700 ==
3904 04:50:47.836751 Dram Type= 6, Freq= 0, CH_0, rank 0
3905 04:50:47.836803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3906 04:50:47.836854 ==
3907 04:50:47.836910 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3908 04:50:47.836962 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3909 04:50:47.837014 [CA 0] Center 36 (5~67) winsize 63
3910 04:50:47.837065 [CA 1] Center 36 (6~67) winsize 62
3911 04:50:47.837120 [CA 2] Center 34 (4~65) winsize 62
3912 04:50:47.837171 [CA 3] Center 34 (4~65) winsize 62
3913 04:50:47.837222 [CA 4] Center 34 (3~65) winsize 63
3914 04:50:47.837278 [CA 5] Center 33 (2~64) winsize 63
3915 04:50:47.837330
3916 04:50:47.837381 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3917 04:50:47.837432
3918 04:50:47.837485 [CATrainingPosCal] consider 1 rank data
3919 04:50:47.837537 u2DelayCellTimex100 = 270/100 ps
3920 04:50:47.837588 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3921 04:50:47.837639 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3922 04:50:47.837690 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3923 04:50:47.837741 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3924 04:50:47.837792 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3925 04:50:47.837843 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3926 04:50:47.837893
3927 04:50:47.837948 CA PerBit enable=1, Macro0, CA PI delay=33
3928 04:50:48.318118
3929 04:50:48.318633 [CBTSetCACLKResult] CA Dly = 33
3930 04:50:48.318994 CS Dly: 4 (0~35)
3931 04:50:48.319328 ==
3932 04:50:48.319651 Dram Type= 6, Freq= 0, CH_0, rank 1
3933 04:50:48.319968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3934 04:50:48.320278 ==
3935 04:50:48.320587 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3936 04:50:48.320893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3937 04:50:48.321197 [CA 0] Center 36 (6~67) winsize 62
3938 04:50:48.321500 [CA 1] Center 36 (6~67) winsize 62
3939 04:50:48.321801 [CA 2] Center 34 (4~65) winsize 62
3940 04:50:48.322151 [CA 3] Center 34 (4~65) winsize 62
3941 04:50:48.322457 [CA 4] Center 34 (3~65) winsize 63
3942 04:50:48.322754 [CA 5] Center 33 (3~64) winsize 62
3943 04:50:48.323052
3944 04:50:48.323347 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3945 04:50:48.323645
3946 04:50:48.323938 [CATrainingPosCal] consider 2 rank data
3947 04:50:48.324235 u2DelayCellTimex100 = 270/100 ps
3948 04:50:48.324530 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3949 04:50:48.324826 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3950 04:50:48.325124 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3951 04:50:48.325457 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3952 04:50:48.325767 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3953 04:50:48.326094 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3954 04:50:48.326396
3955 04:50:48.326691 CA PerBit enable=1, Macro0, CA PI delay=33
3956 04:50:48.326987
3957 04:50:48.327328 [CBTSetCACLKResult] CA Dly = 33
3958 04:50:48.327635 CS Dly: 4 (0~36)
3959 04:50:48.327930
3960 04:50:48.328222 ----->DramcWriteLeveling(PI) begin...
3961 04:50:48.328525 ==
3962 04:50:48.328821 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 04:50:48.329118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 04:50:48.329628 ==
3965 04:50:48.329994 Write leveling (Byte 0): 33 => 33
3966 04:50:48.330313 Write leveling (Byte 1): 32 => 32
3967 04:50:48.330612 DramcWriteLeveling(PI) end<-----
3968 04:50:48.330909
3969 04:50:48.331202 ==
3970 04:50:48.331497 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 04:50:48.332264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 04:50:48.332611 ==
3973 04:50:48.332921 [Gating] SW mode calibration
3974 04:50:48.333225 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3975 04:50:48.333527 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3976 04:50:48.333823 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 04:50:48.334169 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 04:50:48.334474 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 04:50:48.334773 0 9 12 | B1->B0 | 3434 3131 | 0 1 | (1 0) (1 1)
3980 04:50:48.335069 0 9 16 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
3981 04:50:48.335367 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 04:50:48.335664 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 04:50:48.336025 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 04:50:48.336333 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 04:50:48.336629 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 04:50:48.336926 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 04:50:48.337220 0 10 12 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
3988 04:50:48.337516 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
3989 04:50:48.337808 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 04:50:48.338214 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 04:50:48.338523 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 04:50:48.338822 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 04:50:48.339115 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 04:50:48.339411 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 04:50:48.339706 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3996 04:50:48.340007 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3997 04:50:48.340514 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 04:50:48.340842 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 04:50:48.341142 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 04:50:48.341438 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 04:50:48.341737 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 04:50:48.342027 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 04:50:48.342301 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 04:50:48.342569 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 04:50:48.342836 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 04:50:48.343103 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 04:50:48.343372 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 04:50:48.343665 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 04:50:48.343958 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 04:50:48.344251 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 04:50:48.344544 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4012 04:50:48.344779 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4013 04:50:48.344988 Total UI for P1: 0, mck2ui 16
4014 04:50:48.345199 best dqsien dly found for B0: ( 0, 13, 12)
4015 04:50:48.345409 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 04:50:48.345619 Total UI for P1: 0, mck2ui 16
4017 04:50:48.345829 best dqsien dly found for B1: ( 0, 13, 14)
4018 04:50:48.346065 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4019 04:50:48.346276 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4020 04:50:48.346484
4021 04:50:48.346691 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4022 04:50:48.346903 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4023 04:50:48.347113 [Gating] SW calibration Done
4024 04:50:48.347324 ==
4025 04:50:48.347532 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 04:50:48.347742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 04:50:48.347953 ==
4028 04:50:48.348162 RX Vref Scan: 0
4029 04:50:48.348372
4030 04:50:48.348579 RX Vref 0 -> 0, step: 1
4031 04:50:48.348788
4032 04:50:48.348995 RX Delay -230 -> 252, step: 16
4033 04:50:48.349216 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4034 04:50:48.349434 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4035 04:50:48.349641 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4036 04:50:48.349799 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4037 04:50:48.349969 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4038 04:50:48.350129 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4039 04:50:48.350288 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4040 04:50:48.350445 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4041 04:50:48.350605 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4042 04:50:48.350764 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4043 04:50:48.350923 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4044 04:50:48.351082 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4045 04:50:48.351240 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4046 04:50:48.351398 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4047 04:50:48.351558 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4048 04:50:48.351717 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4049 04:50:48.351872 ==
4050 04:50:48.352029 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 04:50:48.352198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 04:50:48.352360 ==
4053 04:50:48.352518 DQS Delay:
4054 04:50:48.352676 DQS0 = 0, DQS1 = 0
4055 04:50:48.352834 DQM Delay:
4056 04:50:48.352992 DQM0 = 50, DQM1 = 39
4057 04:50:48.353150 DQ Delay:
4058 04:50:48.353309 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4059 04:50:48.353468 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4060 04:50:48.353626 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4061 04:50:48.353786 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =41
4062 04:50:48.353957
4063 04:50:48.354119
4064 04:50:48.354276 ==
4065 04:50:48.354435 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 04:50:48.354608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 04:50:48.354735 ==
4068 04:50:48.354859
4069 04:50:48.354983
4070 04:50:48.355107 TX Vref Scan disable
4071 04:50:48.355232 == TX Byte 0 ==
4072 04:50:48.355358 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4073 04:50:48.355485 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4074 04:50:48.355611 == TX Byte 1 ==
4075 04:50:48.355736 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4076 04:50:48.355862 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4077 04:50:48.355987 ==
4078 04:50:48.356361 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 04:50:48.356504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 04:50:48.356635 ==
4081 04:50:48.356764
4082 04:50:48.356891
4083 04:50:48.357016 TX Vref Scan disable
4084 04:50:48.357144 == TX Byte 0 ==
4085 04:50:48.357271 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4086 04:50:48.357397 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4087 04:50:48.357523 == TX Byte 1 ==
4088 04:50:48.357650 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4089 04:50:48.357778 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4090 04:50:48.357904
4091 04:50:48.358054 [DATLAT]
4092 04:50:48.358183 Freq=600, CH0 RK0
4093 04:50:48.358310
4094 04:50:48.358434 DATLAT Default: 0x9
4095 04:50:48.358560 0, 0xFFFF, sum = 0
4096 04:50:48.358688 1, 0xFFFF, sum = 0
4097 04:50:48.358817 2, 0xFFFF, sum = 0
4098 04:50:48.358944 3, 0xFFFF, sum = 0
4099 04:50:48.359072 4, 0xFFFF, sum = 0
4100 04:50:48.359198 5, 0xFFFF, sum = 0
4101 04:50:48.359326 6, 0xFFFF, sum = 0
4102 04:50:48.359453 7, 0xFFFF, sum = 0
4103 04:50:48.359595 8, 0x0, sum = 1
4104 04:50:48.359701 9, 0x0, sum = 2
4105 04:50:48.359806 10, 0x0, sum = 3
4106 04:50:48.359913 11, 0x0, sum = 4
4107 04:50:48.360020 best_step = 9
4108 04:50:48.360124
4109 04:50:48.360226 ==
4110 04:50:48.360329 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 04:50:48.360434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 04:50:48.360540 ==
4113 04:50:48.360643 RX Vref Scan: 1
4114 04:50:48.360747
4115 04:50:48.360851 RX Vref 0 -> 0, step: 1
4116 04:50:48.360955
4117 04:50:48.361059 RX Delay -179 -> 252, step: 8
4118 04:50:48.361162
4119 04:50:48.361266 Set Vref, RX VrefLevel [Byte0]: 59
4120 04:50:48.361371 [Byte1]: 50
4121 04:50:48.361475
4122 04:50:48.361578 Final RX Vref Byte 0 = 59 to rank0
4123 04:50:48.361683 Final RX Vref Byte 1 = 50 to rank0
4124 04:50:48.361788 Final RX Vref Byte 0 = 59 to rank1
4125 04:50:48.361893 Final RX Vref Byte 1 = 50 to rank1==
4126 04:50:48.362007 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 04:50:48.362113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 04:50:48.362219 ==
4129 04:50:48.362323 DQS Delay:
4130 04:50:48.362427 DQS0 = 0, DQS1 = 0
4131 04:50:48.362530 DQM Delay:
4132 04:50:48.362634 DQM0 = 50, DQM1 = 36
4133 04:50:48.362738 DQ Delay:
4134 04:50:48.362843 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =48
4135 04:50:48.362947 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4136 04:50:48.363051 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4137 04:50:48.363155 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4138 04:50:48.363260
4139 04:50:48.363364
4140 04:50:48.363468 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d57, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4141 04:50:48.363574 CH0 RK0: MR19=808, MR18=5D57
4142 04:50:48.363679 CH0_RK0: MR19=0x808, MR18=0x5D57, DQSOSC=392, MR23=63, INC=170, DEC=113
4143 04:50:48.363784
4144 04:50:48.363887 ----->DramcWriteLeveling(PI) begin...
4145 04:50:48.363994 ==
4146 04:50:48.364100 Dram Type= 6, Freq= 0, CH_0, rank 1
4147 04:50:48.364205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 04:50:48.364310 ==
4149 04:50:48.364416 Write leveling (Byte 0): 33 => 33
4150 04:50:48.364520 Write leveling (Byte 1): 33 => 33
4151 04:50:48.364633 DramcWriteLeveling(PI) end<-----
4152 04:50:48.364721
4153 04:50:48.364810 ==
4154 04:50:48.364898 Dram Type= 6, Freq= 0, CH_0, rank 1
4155 04:50:48.364987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 04:50:48.365076 ==
4157 04:50:48.365166 [Gating] SW mode calibration
4158 04:50:48.365255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4159 04:50:48.365345 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4160 04:50:48.365434 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 04:50:48.365524 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 04:50:48.365613 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4163 04:50:48.365701 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
4164 04:50:48.365790 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 04:50:48.365879 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 04:50:48.365974 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 04:50:48.366065 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 04:50:48.366154 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 04:50:48.366243 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 04:50:48.366332 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 04:50:48.366419 0 10 12 | B1->B0 | 3131 3838 | 0 0 | (1 1) (0 0)
4172 04:50:48.366508 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4173 04:50:48.366596 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 04:50:48.366685 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 04:50:48.366774 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 04:50:48.366863 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 04:50:48.366952 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 04:50:48.367041 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 04:50:48.367130 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4180 04:50:48.367219 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 04:50:48.367307 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 04:50:48.367395 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 04:50:48.367483 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 04:50:48.367584 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 04:50:48.367683 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 04:50:48.367772 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 04:50:48.367862 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 04:50:48.367951 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 04:50:48.368041 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 04:50:48.368130 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 04:50:48.368219 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 04:50:48.368309 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 04:50:48.368399 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 04:50:48.368488 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 04:50:48.368578 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4196 04:50:48.368667 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4197 04:50:48.368756 Total UI for P1: 0, mck2ui 16
4198 04:50:48.368846 best dqsien dly found for B0: ( 0, 13, 12)
4199 04:50:48.368936 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 04:50:48.369240 Total UI for P1: 0, mck2ui 16
4201 04:50:48.369341 best dqsien dly found for B1: ( 0, 13, 16)
4202 04:50:48.369434 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4203 04:50:48.369524 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4204 04:50:48.369620
4205 04:50:48.369723 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4206 04:50:48.369805 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4207 04:50:48.369883 [Gating] SW calibration Done
4208 04:50:48.369973 ==
4209 04:50:48.370054 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 04:50:48.370134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 04:50:48.370213 ==
4212 04:50:48.370292 RX Vref Scan: 0
4213 04:50:48.370370
4214 04:50:48.370446 RX Vref 0 -> 0, step: 1
4215 04:50:48.370523
4216 04:50:48.370601 RX Delay -230 -> 252, step: 16
4217 04:50:48.370679 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4218 04:50:48.370756 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4219 04:50:48.370834 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4220 04:50:48.370912 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4221 04:50:48.370990 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4222 04:50:48.371068 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4223 04:50:48.371145 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4224 04:50:48.371223 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4225 04:50:48.371301 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4226 04:50:48.371378 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4227 04:50:48.371456 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4228 04:50:48.371534 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4229 04:50:48.371612 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4230 04:50:48.371709 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4231 04:50:48.371788 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4232 04:50:48.371866 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4233 04:50:48.371944 ==
4234 04:50:48.372023 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 04:50:48.372101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 04:50:48.372179 ==
4237 04:50:48.372257 DQS Delay:
4238 04:50:48.372335 DQS0 = 0, DQS1 = 0
4239 04:50:48.372412 DQM Delay:
4240 04:50:48.372490 DQM0 = 51, DQM1 = 44
4241 04:50:48.372568 DQ Delay:
4242 04:50:48.372645 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4243 04:50:48.372724 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4244 04:50:48.372800 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =41
4245 04:50:48.372878 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4246 04:50:48.372956
4247 04:50:48.373033
4248 04:50:48.373111 ==
4249 04:50:48.373188 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 04:50:48.373271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 04:50:48.373349 ==
4252 04:50:48.373443
4253 04:50:48.373524
4254 04:50:48.373601 TX Vref Scan disable
4255 04:50:48.373688 == TX Byte 0 ==
4256 04:50:48.373768 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4257 04:50:48.373847 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4258 04:50:48.373924 == TX Byte 1 ==
4259 04:50:48.374014 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4260 04:50:48.374093 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4261 04:50:48.374171 ==
4262 04:50:48.374248 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 04:50:48.374326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 04:50:48.374405 ==
4265 04:50:48.374482
4266 04:50:48.374572
4267 04:50:48.374640 TX Vref Scan disable
4268 04:50:48.374709 == TX Byte 0 ==
4269 04:50:48.374778 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4270 04:50:48.374847 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4271 04:50:48.374916 == TX Byte 1 ==
4272 04:50:48.374985 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4273 04:50:48.375054 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4274 04:50:48.375123
4275 04:50:48.375191 [DATLAT]
4276 04:50:48.375259 Freq=600, CH0 RK1
4277 04:50:48.375328
4278 04:50:48.375396 DATLAT Default: 0x9
4279 04:50:48.375465 0, 0xFFFF, sum = 0
4280 04:50:48.375535 1, 0xFFFF, sum = 0
4281 04:50:48.375605 2, 0xFFFF, sum = 0
4282 04:50:48.375682 3, 0xFFFF, sum = 0
4283 04:50:48.375753 4, 0xFFFF, sum = 0
4284 04:50:48.375823 5, 0xFFFF, sum = 0
4285 04:50:48.375893 6, 0xFFFF, sum = 0
4286 04:50:48.375963 7, 0xFFFF, sum = 0
4287 04:50:48.376032 8, 0x0, sum = 1
4288 04:50:48.376102 9, 0x0, sum = 2
4289 04:50:48.376172 10, 0x0, sum = 3
4290 04:50:48.376242 11, 0x0, sum = 4
4291 04:50:48.376313 best_step = 9
4292 04:50:48.376381
4293 04:50:48.376450 ==
4294 04:50:48.376517 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 04:50:48.376585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 04:50:48.376653 ==
4297 04:50:48.376720 RX Vref Scan: 0
4298 04:50:48.376786
4299 04:50:48.376852 RX Vref 0 -> 0, step: 1
4300 04:50:48.376918
4301 04:50:48.377006 RX Delay -179 -> 252, step: 8
4302 04:50:48.377076 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4303 04:50:48.377144 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4304 04:50:48.377211 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4305 04:50:48.377278 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4306 04:50:48.377344 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4307 04:50:48.377411 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4308 04:50:48.377479 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4309 04:50:48.377546 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4310 04:50:48.377612 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4311 04:50:48.377699 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4312 04:50:48.377768 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4313 04:50:48.377836 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4314 04:50:48.377904 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4315 04:50:48.377983 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4316 04:50:48.378051 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4317 04:50:48.378119 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4318 04:50:48.378186 ==
4319 04:50:48.378254 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 04:50:48.378322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 04:50:48.378389 ==
4322 04:50:48.378456 DQS Delay:
4323 04:50:48.378524 DQS0 = 0, DQS1 = 0
4324 04:50:48.378590 DQM Delay:
4325 04:50:48.378657 DQM0 = 48, DQM1 = 41
4326 04:50:48.378724 DQ Delay:
4327 04:50:48.378790 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4328 04:50:48.378857 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =52
4329 04:50:48.378924 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4330 04:50:48.378990 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4331 04:50:48.379056
4332 04:50:48.379123
4333 04:50:48.379189 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d2b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
4334 04:50:48.379258 CH0 RK1: MR19=808, MR18=5D2B
4335 04:50:48.379325 CH0_RK1: MR19=0x808, MR18=0x5D2B, DQSOSC=392, MR23=63, INC=170, DEC=113
4336 04:50:48.379393 [RxdqsGatingPostProcess] freq 600
4337 04:50:48.379460 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4338 04:50:48.379527 Pre-setting of DQS Precalculation
4339 04:50:48.379807 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4340 04:50:48.379880 ==
4341 04:50:48.379943 Dram Type= 6, Freq= 0, CH_1, rank 0
4342 04:50:48.380004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 04:50:48.380065 ==
4344 04:50:48.380125 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4345 04:50:48.380187 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4346 04:50:48.380247 [CA 0] Center 35 (5~66) winsize 62
4347 04:50:48.380308 [CA 1] Center 35 (5~66) winsize 62
4348 04:50:48.380368 [CA 2] Center 34 (4~65) winsize 62
4349 04:50:48.380428 [CA 3] Center 33 (3~64) winsize 62
4350 04:50:48.380488 [CA 4] Center 34 (3~65) winsize 63
4351 04:50:48.380548 [CA 5] Center 33 (3~64) winsize 62
4352 04:50:48.380608
4353 04:50:48.380668 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4354 04:50:48.380728
4355 04:50:48.380788 [CATrainingPosCal] consider 1 rank data
4356 04:50:48.380848 u2DelayCellTimex100 = 270/100 ps
4357 04:50:48.380907 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4358 04:50:48.380968 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4359 04:50:48.381027 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4360 04:50:48.381087 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4361 04:50:48.381148 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4362 04:50:48.381208 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4363 04:50:48.381268
4364 04:50:48.381328 CA PerBit enable=1, Macro0, CA PI delay=33
4365 04:50:48.381387
4366 04:50:48.381451 [CBTSetCACLKResult] CA Dly = 33
4367 04:50:48.381513 CS Dly: 5 (0~36)
4368 04:50:48.381573 ==
4369 04:50:48.381633 Dram Type= 6, Freq= 0, CH_1, rank 1
4370 04:50:48.381734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 04:50:48.381828 ==
4372 04:50:48.381900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4373 04:50:48.381969 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4374 04:50:48.382031 [CA 0] Center 35 (5~66) winsize 62
4375 04:50:48.382095 [CA 1] Center 35 (5~66) winsize 62
4376 04:50:48.382156 [CA 2] Center 34 (4~65) winsize 62
4377 04:50:48.382217 [CA 3] Center 34 (4~64) winsize 61
4378 04:50:48.382282 [CA 4] Center 34 (4~64) winsize 61
4379 04:50:48.382342 [CA 5] Center 33 (3~64) winsize 62
4380 04:50:48.382402
4381 04:50:48.382466 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4382 04:50:48.382528
4383 04:50:48.382588 [CATrainingPosCal] consider 2 rank data
4384 04:50:48.382648 u2DelayCellTimex100 = 270/100 ps
4385 04:50:48.382709 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4386 04:50:48.382769 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4387 04:50:48.382829 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4388 04:50:48.382888 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4389 04:50:48.382948 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4390 04:50:48.383008 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4391 04:50:48.383068
4392 04:50:48.383127 CA PerBit enable=1, Macro0, CA PI delay=33
4393 04:50:48.383187
4394 04:50:48.383246 [CBTSetCACLKResult] CA Dly = 33
4395 04:50:48.383306 CS Dly: 5 (0~36)
4396 04:50:48.383366
4397 04:50:48.383425 ----->DramcWriteLeveling(PI) begin...
4398 04:50:48.383486 ==
4399 04:50:48.383546 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 04:50:48.383607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 04:50:48.383667 ==
4402 04:50:48.383728 Write leveling (Byte 0): 28 => 28
4403 04:50:48.383788 Write leveling (Byte 1): 29 => 29
4404 04:50:48.383848 DramcWriteLeveling(PI) end<-----
4405 04:50:48.383907
4406 04:50:48.383965 ==
4407 04:50:48.384026 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 04:50:48.384086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 04:50:48.384147 ==
4410 04:50:48.384206 [Gating] SW mode calibration
4411 04:50:48.384266 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4412 04:50:48.384328 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4413 04:50:48.384389 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 04:50:48.384449 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 04:50:48.384509 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
4416 04:50:48.384569 0 9 12 | B1->B0 | 2d2d 3030 | 0 0 | (0 1) (1 1)
4417 04:50:48.384641 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 04:50:48.384695 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 04:50:48.384749 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 04:50:48.384803 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 04:50:48.384858 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 04:50:48.384913 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 04:50:48.384967 0 10 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
4424 04:50:48.385022 0 10 12 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (1 1)
4425 04:50:48.385076 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 04:50:48.385130 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 04:50:48.385184 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 04:50:48.385239 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 04:50:48.385293 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 04:50:48.385347 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 04:50:48.385401 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 04:50:48.385455 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4433 04:50:48.385510 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 04:50:48.385564 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 04:50:48.385618 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 04:50:48.385673 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 04:50:48.385736 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 04:50:48.385792 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 04:50:48.385846 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 04:50:48.385901 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 04:50:48.385963 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 04:50:48.386020 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 04:50:48.386075 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 04:50:48.386129 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 04:50:48.386184 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 04:50:48.386433 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 04:50:48.386496 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 04:50:48.386553 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4449 04:50:48.386609 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 04:50:48.386664 Total UI for P1: 0, mck2ui 16
4451 04:50:48.386719 best dqsien dly found for B0: ( 0, 13, 12)
4452 04:50:48.386774 Total UI for P1: 0, mck2ui 16
4453 04:50:48.386830 best dqsien dly found for B1: ( 0, 13, 12)
4454 04:50:48.386885 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4455 04:50:48.386939 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4456 04:50:48.386994
4457 04:50:48.387048 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4458 04:50:48.387103 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4459 04:50:48.387159 [Gating] SW calibration Done
4460 04:50:48.387213 ==
4461 04:50:48.387268 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 04:50:48.387323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 04:50:48.387378 ==
4464 04:50:48.387432 RX Vref Scan: 0
4465 04:50:48.387487
4466 04:50:48.387541 RX Vref 0 -> 0, step: 1
4467 04:50:48.387595
4468 04:50:48.387649 RX Delay -230 -> 252, step: 16
4469 04:50:48.387714 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4470 04:50:48.387770 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4471 04:50:48.387824 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4472 04:50:48.387879 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4473 04:50:48.387933 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4474 04:50:48.387988 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4475 04:50:48.388042 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4476 04:50:48.388097 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4477 04:50:48.388151 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4478 04:50:48.388206 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4479 04:50:48.388261 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4480 04:50:48.388315 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4481 04:50:48.388369 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4482 04:50:48.388424 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4483 04:50:48.388479 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4484 04:50:48.388534 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4485 04:50:48.388588 ==
4486 04:50:48.388642 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 04:50:48.388696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 04:50:48.388751 ==
4489 04:50:48.388806 DQS Delay:
4490 04:50:48.388860 DQS0 = 0, DQS1 = 0
4491 04:50:48.388914 DQM Delay:
4492 04:50:48.388969 DQM0 = 51, DQM1 = 45
4493 04:50:48.389023 DQ Delay:
4494 04:50:48.389077 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4495 04:50:48.389132 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4496 04:50:48.389186 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4497 04:50:48.389240 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =49
4498 04:50:48.389295
4499 04:50:48.389349
4500 04:50:48.389403 ==
4501 04:50:48.389457 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 04:50:48.389512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 04:50:48.389579 ==
4504 04:50:48.389631
4505 04:50:48.389683
4506 04:50:48.389734 TX Vref Scan disable
4507 04:50:48.389787 == TX Byte 0 ==
4508 04:50:48.389839 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4509 04:50:48.389891 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4510 04:50:48.389953 == TX Byte 1 ==
4511 04:50:48.390072 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4512 04:50:48.390125 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4513 04:50:48.390178 ==
4514 04:50:48.390231 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 04:50:48.390283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 04:50:48.390336 ==
4517 04:50:48.390388
4518 04:50:48.390440
4519 04:50:48.390491 TX Vref Scan disable
4520 04:50:48.390543 == TX Byte 0 ==
4521 04:50:48.390595 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4522 04:50:48.390647 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4523 04:50:48.390699 == TX Byte 1 ==
4524 04:50:48.390752 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4525 04:50:48.390805 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4526 04:50:48.390857
4527 04:50:48.390909 [DATLAT]
4528 04:50:48.390961 Freq=600, CH1 RK0
4529 04:50:48.391013
4530 04:50:48.391064 DATLAT Default: 0x9
4531 04:50:48.391116 0, 0xFFFF, sum = 0
4532 04:50:48.391170 1, 0xFFFF, sum = 0
4533 04:50:48.391223 2, 0xFFFF, sum = 0
4534 04:50:48.391276 3, 0xFFFF, sum = 0
4535 04:50:48.391329 4, 0xFFFF, sum = 0
4536 04:50:48.391381 5, 0xFFFF, sum = 0
4537 04:50:48.391434 6, 0xFFFF, sum = 0
4538 04:50:48.391487 7, 0xFFFF, sum = 0
4539 04:50:48.391539 8, 0x0, sum = 1
4540 04:50:48.391592 9, 0x0, sum = 2
4541 04:50:48.391644 10, 0x0, sum = 3
4542 04:50:48.391718 11, 0x0, sum = 4
4543 04:50:48.391802 best_step = 9
4544 04:50:48.391858
4545 04:50:48.391914 ==
4546 04:50:48.391967 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 04:50:48.392020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 04:50:48.392074 ==
4549 04:50:48.392129 RX Vref Scan: 1
4550 04:50:48.392182
4551 04:50:48.392235 RX Vref 0 -> 0, step: 1
4552 04:50:48.392290
4553 04:50:48.392342 RX Delay -179 -> 252, step: 8
4554 04:50:48.392394
4555 04:50:48.392446 Set Vref, RX VrefLevel [Byte0]: 52
4556 04:50:48.392504 [Byte1]: 53
4557 04:50:48.392557
4558 04:50:48.392608 Final RX Vref Byte 0 = 52 to rank0
4559 04:50:48.392664 Final RX Vref Byte 1 = 53 to rank0
4560 04:50:48.392717 Final RX Vref Byte 0 = 52 to rank1
4561 04:50:48.392770 Final RX Vref Byte 1 = 53 to rank1==
4562 04:50:48.392822 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 04:50:48.392878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 04:50:48.392932 ==
4565 04:50:48.392984 DQS Delay:
4566 04:50:48.393038 DQS0 = 0, DQS1 = 0
4567 04:50:48.393091 DQM Delay:
4568 04:50:48.393144 DQM0 = 49, DQM1 = 41
4569 04:50:48.393196 DQ Delay:
4570 04:50:48.393259 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =48
4571 04:50:48.393341 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4572 04:50:48.393424 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4573 04:50:48.393506 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4574 04:50:48.393587
4575 04:50:48.393673
4576 04:50:48.393756 [DQSOSCAuto] RK0, (LSB)MR18= 0x466e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4577 04:50:48.393841 CH1 RK0: MR19=808, MR18=466E
4578 04:50:48.393924 CH1_RK0: MR19=0x808, MR18=0x466E, DQSOSC=389, MR23=63, INC=173, DEC=115
4579 04:50:48.394029
4580 04:50:48.394083 ----->DramcWriteLeveling(PI) begin...
4581 04:50:48.394136 ==
4582 04:50:48.394189 Dram Type= 6, Freq= 0, CH_1, rank 1
4583 04:50:48.394241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 04:50:48.394294 ==
4585 04:50:48.394346 Write leveling (Byte 0): 30 => 30
4586 04:50:48.394398 Write leveling (Byte 1): 32 => 32
4587 04:50:48.394451 DramcWriteLeveling(PI) end<-----
4588 04:50:48.394503
4589 04:50:48.394555 ==
4590 04:50:48.394607 Dram Type= 6, Freq= 0, CH_1, rank 1
4591 04:50:48.394658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 04:50:48.394711 ==
4593 04:50:48.394763 [Gating] SW mode calibration
4594 04:50:48.395007 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4595 04:50:48.395069 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4596 04:50:48.395124 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 04:50:48.395178 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4598 04:50:48.395230 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4599 04:50:48.395283 0 9 12 | B1->B0 | 2e2e 3232 | 0 1 | (0 0) (1 1)
4600 04:50:48.395336 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 04:50:48.395389 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 04:50:48.395441 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 04:50:48.395494 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 04:50:48.395546 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 04:50:48.395599 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 04:50:48.395652 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4607 04:50:48.395705 0 10 12 | B1->B0 | 3e3e 3131 | 0 0 | (0 0) (0 0)
4608 04:50:48.395758 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4609 04:50:48.395811 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 04:50:48.395864 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 04:50:48.395916 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 04:50:48.395968 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 04:50:48.396020 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 04:50:48.396072 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 04:50:48.396124 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4616 04:50:48.396177 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 04:50:48.396229 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 04:50:48.396282 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 04:50:48.396334 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 04:50:48.396386 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 04:50:48.396439 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 04:50:48.396491 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 04:50:48.396544 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 04:50:48.396596 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 04:50:48.396648 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 04:50:48.396700 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 04:50:48.396752 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 04:50:48.396804 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 04:50:48.396856 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 04:50:48.396908 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4631 04:50:48.396961 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4632 04:50:48.397012 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4633 04:50:48.397064 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 04:50:48.397116 Total UI for P1: 0, mck2ui 16
4635 04:50:48.397168 best dqsien dly found for B0: ( 0, 13, 12)
4636 04:50:48.397220 Total UI for P1: 0, mck2ui 16
4637 04:50:48.397273 best dqsien dly found for B1: ( 0, 13, 14)
4638 04:50:48.397325 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4639 04:50:48.397377 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4640 04:50:48.397428
4641 04:50:48.397481 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4642 04:50:48.397534 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4643 04:50:48.397586 [Gating] SW calibration Done
4644 04:50:48.397638 ==
4645 04:50:48.397689 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 04:50:48.397779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 04:50:48.397867 ==
4648 04:50:48.397972 RX Vref Scan: 0
4649 04:50:48.398042
4650 04:50:48.398094 RX Vref 0 -> 0, step: 1
4651 04:50:48.398147
4652 04:50:48.398198 RX Delay -230 -> 252, step: 16
4653 04:50:48.398251 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4654 04:50:48.398303 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4655 04:50:48.398356 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4656 04:50:48.398408 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4657 04:50:48.398460 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4658 04:50:48.398512 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4659 04:50:48.398564 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4660 04:50:48.398616 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4661 04:50:48.398668 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4662 04:50:48.398719 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4663 04:50:48.398772 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4664 04:50:48.398824 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4665 04:50:48.398876 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4666 04:50:48.398940 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4667 04:50:48.399033 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4668 04:50:48.399090 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4669 04:50:48.399143 ==
4670 04:50:48.399196 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 04:50:48.399249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 04:50:48.399302 ==
4673 04:50:48.399354 DQS Delay:
4674 04:50:48.399406 DQS0 = 0, DQS1 = 0
4675 04:50:48.399458 DQM Delay:
4676 04:50:48.399510 DQM0 = 51, DQM1 = 44
4677 04:50:48.399563 DQ Delay:
4678 04:50:48.399614 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4679 04:50:48.399667 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4680 04:50:48.399719 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4681 04:50:48.399772 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =57
4682 04:50:48.399824
4683 04:50:48.399875
4684 04:50:48.399927 ==
4685 04:50:48.399979 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 04:50:48.400031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 04:50:48.400084 ==
4688 04:50:48.400136
4689 04:50:48.400188
4690 04:50:48.400240 TX Vref Scan disable
4691 04:50:48.400292 == TX Byte 0 ==
4692 04:50:48.400344 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4693 04:50:48.400398 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4694 04:50:48.400450 == TX Byte 1 ==
4695 04:50:48.400502 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4696 04:50:48.400554 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4697 04:50:48.400605 ==
4698 04:50:48.400658 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 04:50:48.400904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 04:50:48.400969 ==
4701 04:50:48.401023
4702 04:50:48.401076
4703 04:50:48.401129 TX Vref Scan disable
4704 04:50:48.401181 == TX Byte 0 ==
4705 04:50:48.401234 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4706 04:50:48.401287 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4707 04:50:48.401340 == TX Byte 1 ==
4708 04:50:48.401392 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4709 04:50:48.401444 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4710 04:50:48.401497
4711 04:50:48.401548 [DATLAT]
4712 04:50:48.401600 Freq=600, CH1 RK1
4713 04:50:48.401652
4714 04:50:48.401703 DATLAT Default: 0x9
4715 04:50:48.401755 0, 0xFFFF, sum = 0
4716 04:50:48.401808 1, 0xFFFF, sum = 0
4717 04:50:48.401861 2, 0xFFFF, sum = 0
4718 04:50:48.401914 3, 0xFFFF, sum = 0
4719 04:50:48.401998 4, 0xFFFF, sum = 0
4720 04:50:48.402066 5, 0xFFFF, sum = 0
4721 04:50:48.402119 6, 0xFFFF, sum = 0
4722 04:50:48.402172 7, 0xFFFF, sum = 0
4723 04:50:48.402225 8, 0x0, sum = 1
4724 04:50:48.402278 9, 0x0, sum = 2
4725 04:50:48.402335 10, 0x0, sum = 3
4726 04:50:48.402388 11, 0x0, sum = 4
4727 04:50:48.402441 best_step = 9
4728 04:50:48.402494
4729 04:50:48.402549 ==
4730 04:50:48.402601 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 04:50:48.402653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 04:50:48.402706 ==
4733 04:50:48.402758 RX Vref Scan: 0
4734 04:50:48.402810
4735 04:50:48.402862 RX Vref 0 -> 0, step: 1
4736 04:50:48.402914
4737 04:50:48.402965 RX Delay -163 -> 252, step: 8
4738 04:50:48.403017 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4739 04:50:48.403070 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4740 04:50:48.403122 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4741 04:50:48.403176 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4742 04:50:48.403228 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4743 04:50:48.403281 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4744 04:50:48.403332 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4745 04:50:48.403388 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4746 04:50:48.403441 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4747 04:50:48.403493 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4748 04:50:48.403548 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4749 04:50:48.403601 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4750 04:50:48.403653 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4751 04:50:48.403705 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4752 04:50:48.403760 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4753 04:50:48.403813 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4754 04:50:48.403865 ==
4755 04:50:48.403917 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 04:50:48.403969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 04:50:48.404022 ==
4758 04:50:48.404074 DQS Delay:
4759 04:50:48.404126 DQS0 = 0, DQS1 = 0
4760 04:50:48.404178 DQM Delay:
4761 04:50:48.404230 DQM0 = 49, DQM1 = 44
4762 04:50:48.404282 DQ Delay:
4763 04:50:48.404334 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =48
4764 04:50:48.404386 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4765 04:50:48.404440 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4766 04:50:48.404492 DQ12 =48, DQ13 =52, DQ14 =48, DQ15 =56
4767 04:50:48.404543
4768 04:50:48.404595
4769 04:50:48.404647 [DQSOSCAuto] RK1, (LSB)MR18= 0x581e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4770 04:50:48.404700 CH1 RK1: MR19=808, MR18=581E
4771 04:50:48.404752 CH1_RK1: MR19=0x808, MR18=0x581E, DQSOSC=393, MR23=63, INC=169, DEC=113
4772 04:50:48.404805 [RxdqsGatingPostProcess] freq 600
4773 04:50:48.404858 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4774 04:50:48.404910 Pre-setting of DQS Precalculation
4775 04:50:48.404962 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4776 04:50:48.405015 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4777 04:50:48.405068 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4778 04:50:48.405120
4779 04:50:48.405172
4780 04:50:48.405223 [Calibration Summary] 1200 Mbps
4781 04:50:48.405275 CH 0, Rank 0
4782 04:50:48.405327 SW Impedance : PASS
4783 04:50:48.405379 DUTY Scan : NO K
4784 04:50:48.405430 ZQ Calibration : PASS
4785 04:50:48.405483 Jitter Meter : NO K
4786 04:50:48.405534 CBT Training : PASS
4787 04:50:48.405587 Write leveling : PASS
4788 04:50:48.405639 RX DQS gating : PASS
4789 04:50:48.405691 RX DQ/DQS(RDDQC) : PASS
4790 04:50:48.405742 TX DQ/DQS : PASS
4791 04:50:48.405794 RX DATLAT : PASS
4792 04:50:48.405847 RX DQ/DQS(Engine): PASS
4793 04:50:48.405898 TX OE : NO K
4794 04:50:48.405981 All Pass.
4795 04:50:48.406048
4796 04:50:48.406100 CH 0, Rank 1
4797 04:50:48.406151 SW Impedance : PASS
4798 04:50:48.406204 DUTY Scan : NO K
4799 04:50:48.406256 ZQ Calibration : PASS
4800 04:50:48.406308 Jitter Meter : NO K
4801 04:50:48.406359 CBT Training : PASS
4802 04:50:48.406411 Write leveling : PASS
4803 04:50:48.406463 RX DQS gating : PASS
4804 04:50:48.406514 RX DQ/DQS(RDDQC) : PASS
4805 04:50:48.406567 TX DQ/DQS : PASS
4806 04:50:48.406619 RX DATLAT : PASS
4807 04:50:48.406671 RX DQ/DQS(Engine): PASS
4808 04:50:48.406723 TX OE : NO K
4809 04:50:48.406775 All Pass.
4810 04:50:48.406827
4811 04:50:48.406879 CH 1, Rank 0
4812 04:50:48.406931 SW Impedance : PASS
4813 04:50:48.406983 DUTY Scan : NO K
4814 04:50:48.407035 ZQ Calibration : PASS
4815 04:50:48.407086 Jitter Meter : NO K
4816 04:50:48.407138 CBT Training : PASS
4817 04:50:48.407190 Write leveling : PASS
4818 04:50:48.407242 RX DQS gating : PASS
4819 04:50:48.407294 RX DQ/DQS(RDDQC) : PASS
4820 04:50:48.407353 TX DQ/DQS : PASS
4821 04:50:48.407408 RX DATLAT : PASS
4822 04:50:48.407461 RX DQ/DQS(Engine): PASS
4823 04:50:48.407513 TX OE : NO K
4824 04:50:48.407564 All Pass.
4825 04:50:48.407617
4826 04:50:48.407668 CH 1, Rank 1
4827 04:50:48.407720 SW Impedance : PASS
4828 04:50:48.407773 DUTY Scan : NO K
4829 04:50:48.407825 ZQ Calibration : PASS
4830 04:50:48.407877 Jitter Meter : NO K
4831 04:50:48.407929 CBT Training : PASS
4832 04:50:48.407981 Write leveling : PASS
4833 04:50:48.408033 RX DQS gating : PASS
4834 04:50:48.408084 RX DQ/DQS(RDDQC) : PASS
4835 04:50:48.408136 TX DQ/DQS : PASS
4836 04:50:48.408188 RX DATLAT : PASS
4837 04:50:48.408239 RX DQ/DQS(Engine): PASS
4838 04:50:48.408291 TX OE : NO K
4839 04:50:48.408343 All Pass.
4840 04:50:48.408395
4841 04:50:48.408446 DramC Write-DBI off
4842 04:50:48.408498 PER_BANK_REFRESH: Hybrid Mode
4843 04:50:48.408550 TX_TRACKING: ON
4844 04:50:48.408602 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4845 04:50:48.408655 [FAST_K] Save calibration result to emmc
4846 04:50:48.408706 dramc_set_vcore_voltage set vcore to 662500
4847 04:50:48.408759 Read voltage for 933, 3
4848 04:50:48.408811 Vio18 = 0
4849 04:50:48.408863 Vcore = 662500
4850 04:50:48.408914 Vdram = 0
4851 04:50:48.408966 Vddq = 0
4852 04:50:48.409018 Vmddr = 0
4853 04:50:48.409261 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4854 04:50:48.409321 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4855 04:50:48.409375 MEM_TYPE=3, freq_sel=17
4856 04:50:48.409428 sv_algorithm_assistance_LP4_1600
4857 04:50:48.409482 ============ PULL DRAM RESETB DOWN ============
4858 04:50:48.409535 ========== PULL DRAM RESETB DOWN end =========
4859 04:50:48.409588 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4860 04:50:48.409640 ===================================
4861 04:50:48.409693 LPDDR4 DRAM CONFIGURATION
4862 04:50:48.409745 ===================================
4863 04:50:48.409797 EX_ROW_EN[0] = 0x0
4864 04:50:48.409849 EX_ROW_EN[1] = 0x0
4865 04:50:48.409901 LP4Y_EN = 0x0
4866 04:50:48.410003 WORK_FSP = 0x0
4867 04:50:48.410058 WL = 0x3
4868 04:50:48.410111 RL = 0x3
4869 04:50:48.410163 BL = 0x2
4870 04:50:48.410214 RPST = 0x0
4871 04:50:48.410266 RD_PRE = 0x0
4872 04:50:48.410318 WR_PRE = 0x1
4873 04:50:48.410370 WR_PST = 0x0
4874 04:50:48.410422 DBI_WR = 0x0
4875 04:50:48.410473 DBI_RD = 0x0
4876 04:50:48.410525 OTF = 0x1
4877 04:50:48.410577 ===================================
4878 04:50:48.410630 ===================================
4879 04:50:48.410682 ANA top config
4880 04:50:48.410733 ===================================
4881 04:50:48.410785 DLL_ASYNC_EN = 0
4882 04:50:48.410838 ALL_SLAVE_EN = 1
4883 04:50:48.410890 NEW_RANK_MODE = 1
4884 04:50:48.410942 DLL_IDLE_MODE = 1
4885 04:50:48.410995 LP45_APHY_COMB_EN = 1
4886 04:50:48.411047 TX_ODT_DIS = 1
4887 04:50:48.411099 NEW_8X_MODE = 1
4888 04:50:48.411152 ===================================
4889 04:50:48.411205 ===================================
4890 04:50:48.411258 data_rate = 1866
4891 04:50:48.411310 CKR = 1
4892 04:50:48.411362 DQ_P2S_RATIO = 8
4893 04:50:48.411413 ===================================
4894 04:50:48.411465 CA_P2S_RATIO = 8
4895 04:50:48.411517 DQ_CA_OPEN = 0
4896 04:50:48.411569 DQ_SEMI_OPEN = 0
4897 04:50:48.411621 CA_SEMI_OPEN = 0
4898 04:50:48.411672 CA_FULL_RATE = 0
4899 04:50:48.411724 DQ_CKDIV4_EN = 1
4900 04:50:48.411776 CA_CKDIV4_EN = 1
4901 04:50:48.411828 CA_PREDIV_EN = 0
4902 04:50:48.411880 PH8_DLY = 0
4903 04:50:48.411932 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4904 04:50:48.411984 DQ_AAMCK_DIV = 4
4905 04:50:48.412036 CA_AAMCK_DIV = 4
4906 04:50:48.412087 CA_ADMCK_DIV = 4
4907 04:50:48.412139 DQ_TRACK_CA_EN = 0
4908 04:50:48.412191 CA_PICK = 933
4909 04:50:48.412243 CA_MCKIO = 933
4910 04:50:48.412294 MCKIO_SEMI = 0
4911 04:50:48.412346 PLL_FREQ = 3732
4912 04:50:48.412398 DQ_UI_PI_RATIO = 32
4913 04:50:48.412450 CA_UI_PI_RATIO = 0
4914 04:50:48.412502 ===================================
4915 04:50:48.412554 ===================================
4916 04:50:48.412606 memory_type:LPDDR4
4917 04:50:48.412658 GP_NUM : 10
4918 04:50:48.412710 SRAM_EN : 1
4919 04:50:48.412762 MD32_EN : 0
4920 04:50:48.412813 ===================================
4921 04:50:48.412865 [ANA_INIT] >>>>>>>>>>>>>>
4922 04:50:48.412918 <<<<<< [CONFIGURE PHASE]: ANA_TX
4923 04:50:48.412970 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4924 04:50:48.413022 ===================================
4925 04:50:48.413074 data_rate = 1866,PCW = 0X8f00
4926 04:50:48.413127 ===================================
4927 04:50:48.413179 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4928 04:50:48.947098 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4929 04:50:48.947622 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4930 04:50:48.947988 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4931 04:50:48.948323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4932 04:50:48.948648 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4933 04:50:48.948965 [ANA_INIT] flow start
4934 04:50:48.949271 [ANA_INIT] PLL >>>>>>>>
4935 04:50:48.949573 [ANA_INIT] PLL <<<<<<<<
4936 04:50:48.949871 [ANA_INIT] MIDPI >>>>>>>>
4937 04:50:48.950210 [ANA_INIT] MIDPI <<<<<<<<
4938 04:50:48.950512 [ANA_INIT] DLL >>>>>>>>
4939 04:50:48.950811 [ANA_INIT] flow end
4940 04:50:48.951106 ============ LP4 DIFF to SE enter ============
4941 04:50:48.951408 ============ LP4 DIFF to SE exit ============
4942 04:50:48.951707 [ANA_INIT] <<<<<<<<<<<<<
4943 04:50:48.952002 [Flow] Enable top DCM control >>>>>
4944 04:50:48.952294 [Flow] Enable top DCM control <<<<<
4945 04:50:48.952590 Enable DLL master slave shuffle
4946 04:50:48.952885 ==============================================================
4947 04:50:48.953184 Gating Mode config
4948 04:50:48.953478 ==============================================================
4949 04:50:48.953774 Config description:
4950 04:50:48.954091 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4951 04:50:48.954398 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4952 04:50:48.954695 SELPH_MODE 0: By rank 1: By Phase
4953 04:50:48.954993 ==============================================================
4954 04:50:48.955290 GAT_TRACK_EN = 1
4955 04:50:48.955584 RX_GATING_MODE = 2
4956 04:50:48.955877 RX_GATING_TRACK_MODE = 2
4957 04:50:48.956172 SELPH_MODE = 1
4958 04:50:48.956467 PICG_EARLY_EN = 1
4959 04:50:48.956761 VALID_LAT_VALUE = 1
4960 04:50:48.957053 ==============================================================
4961 04:50:48.957348 Enter into Gating configuration >>>>
4962 04:50:48.957641 Exit from Gating configuration <<<<
4963 04:50:48.957934 Enter into DVFS_PRE_config >>>>>
4964 04:50:48.958255 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4965 04:50:48.958554 Exit from DVFS_PRE_config <<<<<
4966 04:50:48.958847 Enter into PICG configuration >>>>
4967 04:50:48.959556 Exit from PICG configuration <<<<
4968 04:50:48.959894 [RX_INPUT] configuration >>>>>
4969 04:50:48.960203 [RX_INPUT] configuration <<<<<
4970 04:50:48.960504 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4971 04:50:48.960806 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4972 04:50:48.961102 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4973 04:50:48.961398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4974 04:50:48.961694 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4975 04:50:48.962014 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4976 04:50:48.962314 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4977 04:50:48.962607 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4978 04:50:48.962902 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4979 04:50:48.963196 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4980 04:50:48.963492 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4981 04:50:48.963782 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4982 04:50:48.964076 ===================================
4983 04:50:48.964370 LPDDR4 DRAM CONFIGURATION
4984 04:50:48.964646 ===================================
4985 04:50:48.964854 EX_ROW_EN[0] = 0x0
4986 04:50:48.965065 EX_ROW_EN[1] = 0x0
4987 04:50:48.965300 LP4Y_EN = 0x0
4988 04:50:48.965516 WORK_FSP = 0x0
4989 04:50:48.965727 WL = 0x3
4990 04:50:48.965935 RL = 0x3
4991 04:50:48.966179 BL = 0x2
4992 04:50:48.966390 RPST = 0x0
4993 04:50:48.966600 RD_PRE = 0x0
4994 04:50:48.966807 WR_PRE = 0x1
4995 04:50:48.967017 WR_PST = 0x0
4996 04:50:48.967258 DBI_WR = 0x0
4997 04:50:48.967576 DBI_RD = 0x0
4998 04:50:48.967839 OTF = 0x1
4999 04:50:48.968057 ===================================
5000 04:50:48.968272 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5001 04:50:48.968485 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5002 04:50:48.968698 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5003 04:50:48.968910 ===================================
5004 04:50:48.969121 LPDDR4 DRAM CONFIGURATION
5005 04:50:48.969330 ===================================
5006 04:50:48.969540 EX_ROW_EN[0] = 0x10
5007 04:50:48.969717 EX_ROW_EN[1] = 0x0
5008 04:50:48.969871 LP4Y_EN = 0x0
5009 04:50:48.970052 WORK_FSP = 0x0
5010 04:50:48.970208 WL = 0x3
5011 04:50:48.970362 RL = 0x3
5012 04:50:48.970516 BL = 0x2
5013 04:50:48.970670 RPST = 0x0
5014 04:50:48.970822 RD_PRE = 0x0
5015 04:50:48.970974 WR_PRE = 0x1
5016 04:50:48.971127 WR_PST = 0x0
5017 04:50:48.971281 DBI_WR = 0x0
5018 04:50:48.971434 DBI_RD = 0x0
5019 04:50:48.971586 OTF = 0x1
5020 04:50:48.971741 ===================================
5021 04:50:48.971897 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5022 04:50:48.972055 nWR fixed to 30
5023 04:50:48.972210 [ModeRegInit_LP4] CH0 RK0
5024 04:50:48.972365 [ModeRegInit_LP4] CH0 RK1
5025 04:50:48.972518 [ModeRegInit_LP4] CH1 RK0
5026 04:50:48.972671 [ModeRegInit_LP4] CH1 RK1
5027 04:50:48.972825 match AC timing 9
5028 04:50:48.972980 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5029 04:50:48.973135 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5030 04:50:48.973291 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5031 04:50:48.973446 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5032 04:50:48.973601 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5033 04:50:48.973757 ==
5034 04:50:48.973913 Dram Type= 6, Freq= 0, CH_0, rank 0
5035 04:50:48.974092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5036 04:50:48.974260 ==
5037 04:50:48.974419 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5038 04:50:48.974586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5039 04:50:48.974711 [CA 0] Center 38 (7~69) winsize 63
5040 04:50:48.974834 [CA 1] Center 38 (8~69) winsize 62
5041 04:50:48.974961 [CA 2] Center 35 (5~66) winsize 62
5042 04:50:48.975088 [CA 3] Center 34 (4~65) winsize 62
5043 04:50:48.975215 [CA 4] Center 34 (4~65) winsize 62
5044 04:50:48.975340 [CA 5] Center 33 (3~64) winsize 62
5045 04:50:48.975467
5046 04:50:48.975593 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5047 04:50:48.975720
5048 04:50:48.975846 [CATrainingPosCal] consider 1 rank data
5049 04:50:48.975972 u2DelayCellTimex100 = 270/100 ps
5050 04:50:48.976097 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5051 04:50:48.976223 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5052 04:50:48.976349 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5053 04:50:48.976475 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5054 04:50:48.976601 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5055 04:50:48.976727 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5056 04:50:48.976852
5057 04:50:48.976977 CA PerBit enable=1, Macro0, CA PI delay=33
5058 04:50:48.977103
5059 04:50:48.977229 [CBTSetCACLKResult] CA Dly = 33
5060 04:50:48.977355 CS Dly: 7 (0~38)
5061 04:50:48.977481 ==
5062 04:50:48.977607 Dram Type= 6, Freq= 0, CH_0, rank 1
5063 04:50:48.977734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5064 04:50:48.977861 ==
5065 04:50:48.978020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5066 04:50:48.978230 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5067 04:50:48.978368 [CA 0] Center 38 (7~69) winsize 63
5068 04:50:48.978497 [CA 1] Center 38 (8~69) winsize 62
5069 04:50:48.978625 [CA 2] Center 36 (6~66) winsize 61
5070 04:50:48.978752 [CA 3] Center 35 (5~66) winsize 62
5071 04:50:48.978878 [CA 4] Center 34 (4~65) winsize 62
5072 04:50:48.979007 [CA 5] Center 34 (4~65) winsize 62
5073 04:50:48.979132
5074 04:50:48.979258 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5075 04:50:48.979385
5076 04:50:48.979511 [CATrainingPosCal] consider 2 rank data
5077 04:50:48.979637 u2DelayCellTimex100 = 270/100 ps
5078 04:50:48.979741 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5079 04:50:48.979847 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5080 04:50:48.979950 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5081 04:50:48.980055 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5082 04:50:48.980159 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5083 04:50:48.980263 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5084 04:50:48.980368
5085 04:50:48.980472 CA PerBit enable=1, Macro0, CA PI delay=34
5086 04:50:48.980575
5087 04:50:48.980679 [CBTSetCACLKResult] CA Dly = 34
5088 04:50:48.981016 CS Dly: 7 (0~39)
5089 04:50:48.981133
5090 04:50:48.981241 ----->DramcWriteLeveling(PI) begin...
5091 04:50:48.981350 ==
5092 04:50:48.981456 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 04:50:48.981561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 04:50:48.981667 ==
5095 04:50:48.981773 Write leveling (Byte 0): 32 => 32
5096 04:50:48.981878 Write leveling (Byte 1): 30 => 30
5097 04:50:48.981993 DramcWriteLeveling(PI) end<-----
5098 04:50:48.982099
5099 04:50:48.982203 ==
5100 04:50:48.982307 Dram Type= 6, Freq= 0, CH_0, rank 0
5101 04:50:48.982412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 04:50:48.982517 ==
5103 04:50:48.982623 [Gating] SW mode calibration
5104 04:50:48.982728 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5105 04:50:48.982834 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5106 04:50:48.982939 0 14 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5107 04:50:48.983044 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 04:50:48.983150 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 04:50:48.983255 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 04:50:48.983359 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 04:50:48.983464 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 04:50:48.983568 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
5113 04:50:48.983673 0 14 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
5114 04:50:48.983778 0 15 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
5115 04:50:48.983881 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 04:50:48.983985 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 04:50:48.984090 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 04:50:48.984195 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 04:50:48.984298 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 04:50:48.984402 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5121 04:50:48.984507 0 15 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
5122 04:50:48.984614 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5123 04:50:48.984702 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 04:50:48.984792 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 04:50:48.984880 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 04:50:48.984969 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 04:50:48.985058 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 04:50:48.985147 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 04:50:48.985237 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5130 04:50:48.985326 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 04:50:48.985415 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 04:50:48.985504 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 04:50:48.985594 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 04:50:48.985682 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 04:50:48.985771 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 04:50:48.985860 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 04:50:48.985955 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 04:50:48.986046 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 04:50:48.986135 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 04:50:48.986223 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 04:50:48.986312 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 04:50:48.986401 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 04:50:48.986490 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 04:50:48.986578 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5145 04:50:48.986668 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5146 04:50:48.986757 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5147 04:50:48.986846 Total UI for P1: 0, mck2ui 16
5148 04:50:48.986936 best dqsien dly found for B0: ( 1, 2, 26)
5149 04:50:48.987025 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 04:50:48.987114 Total UI for P1: 0, mck2ui 16
5151 04:50:48.987203 best dqsien dly found for B1: ( 1, 2, 30)
5152 04:50:48.987294 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5153 04:50:48.987383 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5154 04:50:48.987473
5155 04:50:48.987562 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5156 04:50:48.987652 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5157 04:50:48.987739 [Gating] SW calibration Done
5158 04:50:48.987829 ==
5159 04:50:48.987918 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 04:50:48.988007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 04:50:48.988096 ==
5162 04:50:48.988186 RX Vref Scan: 0
5163 04:50:48.988274
5164 04:50:48.988363 RX Vref 0 -> 0, step: 1
5165 04:50:48.988452
5166 04:50:48.988540 RX Delay -80 -> 252, step: 8
5167 04:50:48.988629 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5168 04:50:48.988718 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5169 04:50:48.988807 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5170 04:50:48.988895 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5171 04:50:48.988983 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5172 04:50:48.989072 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5173 04:50:48.989160 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5174 04:50:48.989249 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5175 04:50:48.989337 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5176 04:50:48.989426 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5177 04:50:48.989516 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5178 04:50:48.989613 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5179 04:50:48.989690 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5180 04:50:48.989767 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5181 04:50:48.989845 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5182 04:50:48.989923 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5183 04:50:48.990006 ==
5184 04:50:48.990084 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 04:50:48.990162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 04:50:48.990240 ==
5187 04:50:48.990317 DQS Delay:
5188 04:50:48.990395 DQS0 = 0, DQS1 = 0
5189 04:50:48.990472 DQM Delay:
5190 04:50:48.990551 DQM0 = 106, DQM1 = 90
5191 04:50:48.990628 DQ Delay:
5192 04:50:48.990914 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5193 04:50:48.991003 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5194 04:50:48.991084 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5195 04:50:48.991163 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5196 04:50:48.991242
5197 04:50:48.991320
5198 04:50:48.991397 ==
5199 04:50:48.991475 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 04:50:48.991554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 04:50:48.991633 ==
5202 04:50:48.991711
5203 04:50:48.991788
5204 04:50:48.991864 TX Vref Scan disable
5205 04:50:48.991942 == TX Byte 0 ==
5206 04:50:48.992019 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5207 04:50:48.992098 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5208 04:50:48.992175 == TX Byte 1 ==
5209 04:50:48.992253 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5210 04:50:48.992331 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5211 04:50:48.992409 ==
5212 04:50:48.992487 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 04:50:48.992565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 04:50:48.992644 ==
5215 04:50:48.992721
5216 04:50:48.992797
5217 04:50:48.992873 TX Vref Scan disable
5218 04:50:48.992951 == TX Byte 0 ==
5219 04:50:48.993028 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5220 04:50:48.993106 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5221 04:50:48.993182 == TX Byte 1 ==
5222 04:50:48.993260 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5223 04:50:48.993337 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5224 04:50:48.993414
5225 04:50:48.993490 [DATLAT]
5226 04:50:48.993567 Freq=933, CH0 RK0
5227 04:50:48.993645
5228 04:50:48.993722 DATLAT Default: 0xd
5229 04:50:48.993799 0, 0xFFFF, sum = 0
5230 04:50:48.993878 1, 0xFFFF, sum = 0
5231 04:50:48.993968 2, 0xFFFF, sum = 0
5232 04:50:48.994049 3, 0xFFFF, sum = 0
5233 04:50:48.994128 4, 0xFFFF, sum = 0
5234 04:50:48.994206 5, 0xFFFF, sum = 0
5235 04:50:48.994285 6, 0xFFFF, sum = 0
5236 04:50:48.994363 7, 0xFFFF, sum = 0
5237 04:50:48.994441 8, 0xFFFF, sum = 0
5238 04:50:48.994519 9, 0xFFFF, sum = 0
5239 04:50:48.994606 10, 0x0, sum = 1
5240 04:50:48.994676 11, 0x0, sum = 2
5241 04:50:48.994746 12, 0x0, sum = 3
5242 04:50:48.994815 13, 0x0, sum = 4
5243 04:50:48.994885 best_step = 11
5244 04:50:48.994953
5245 04:50:48.995022 ==
5246 04:50:48.995091 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 04:50:48.995159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 04:50:48.995229 ==
5249 04:50:48.995297 RX Vref Scan: 1
5250 04:50:48.995366
5251 04:50:48.995434 RX Vref 0 -> 0, step: 1
5252 04:50:48.995503
5253 04:50:48.995571 RX Delay -53 -> 252, step: 4
5254 04:50:48.995639
5255 04:50:48.995708 Set Vref, RX VrefLevel [Byte0]: 59
5256 04:50:48.995777 [Byte1]: 50
5257 04:50:48.995845
5258 04:50:48.995913 Final RX Vref Byte 0 = 59 to rank0
5259 04:50:48.995982 Final RX Vref Byte 1 = 50 to rank0
5260 04:50:48.996051 Final RX Vref Byte 0 = 59 to rank1
5261 04:50:48.996120 Final RX Vref Byte 1 = 50 to rank1==
5262 04:50:48.996188 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 04:50:48.996257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 04:50:48.996327 ==
5265 04:50:48.996396 DQS Delay:
5266 04:50:48.996464 DQS0 = 0, DQS1 = 0
5267 04:50:48.996532 DQM Delay:
5268 04:50:48.996601 DQM0 = 107, DQM1 = 91
5269 04:50:48.996669 DQ Delay:
5270 04:50:48.996736 DQ0 =108, DQ1 =108, DQ2 =104, DQ3 =106
5271 04:50:48.996804 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =114
5272 04:50:48.996873 DQ8 =86, DQ9 =76, DQ10 =92, DQ11 =90
5273 04:50:48.996942 DQ12 =96, DQ13 =92, DQ14 =102, DQ15 =100
5274 04:50:48.997011
5275 04:50:48.997079
5276 04:50:48.997148 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5277 04:50:48.997217 CH0 RK0: MR19=505, MR18=1F1C
5278 04:50:48.997287 CH0_RK0: MR19=0x505, MR18=0x1F1C, DQSOSC=412, MR23=63, INC=63, DEC=42
5279 04:50:48.997356
5280 04:50:48.997424 ----->DramcWriteLeveling(PI) begin...
5281 04:50:48.997494 ==
5282 04:50:48.997563 Dram Type= 6, Freq= 0, CH_0, rank 1
5283 04:50:48.997632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 04:50:48.997700 ==
5285 04:50:48.997769 Write leveling (Byte 0): 35 => 35
5286 04:50:48.997839 Write leveling (Byte 1): 30 => 30
5287 04:50:48.997908 DramcWriteLeveling(PI) end<-----
5288 04:50:48.997982
5289 04:50:48.998051 ==
5290 04:50:48.998119 Dram Type= 6, Freq= 0, CH_0, rank 1
5291 04:50:48.998189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 04:50:48.998258 ==
5293 04:50:48.998327 [Gating] SW mode calibration
5294 04:50:48.998394 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5295 04:50:48.998462 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5296 04:50:48.998542 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 04:50:48.998651 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 04:50:48.998760 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 04:50:48.998832 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 04:50:48.998900 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 04:50:48.998967 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 04:50:48.999043 0 14 24 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 1)
5303 04:50:48.999115 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5304 04:50:48.999182 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5305 04:50:48.999250 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 04:50:48.999317 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 04:50:48.999385 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 04:50:48.999453 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 04:50:48.999520 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 04:50:48.999599 0 15 24 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 0)
5311 04:50:48.999659 0 15 28 | B1->B0 | 3737 4040 | 0 0 | (0 0) (0 0)
5312 04:50:48.999720 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 04:50:48.999779 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 04:50:48.999840 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 04:50:48.999900 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 04:50:48.999961 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 04:50:49.000021 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 04:50:49.000081 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5319 04:50:49.000141 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5320 04:50:49.000201 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 04:50:49.000261 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 04:50:49.000321 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 04:50:49.000381 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 04:50:49.000441 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 04:50:49.000707 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 04:50:49.000779 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 04:50:49.000844 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 04:50:49.000905 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 04:50:49.000966 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 04:50:49.001026 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 04:50:49.001086 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 04:50:49.001147 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 04:50:49.001207 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 04:50:49.001268 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 04:50:49.001329 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5336 04:50:49.001435 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 04:50:49.001511 Total UI for P1: 0, mck2ui 16
5338 04:50:49.001574 best dqsien dly found for B0: ( 1, 2, 28)
5339 04:50:49.001636 Total UI for P1: 0, mck2ui 16
5340 04:50:49.001697 best dqsien dly found for B1: ( 1, 2, 28)
5341 04:50:49.001758 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5342 04:50:49.001819 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5343 04:50:49.001879
5344 04:50:49.001950 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5345 04:50:49.002013 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5346 04:50:49.002074 [Gating] SW calibration Done
5347 04:50:49.002135 ==
5348 04:50:49.002195 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 04:50:49.002255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 04:50:49.002316 ==
5351 04:50:49.002376 RX Vref Scan: 0
5352 04:50:49.002436
5353 04:50:49.002496 RX Vref 0 -> 0, step: 1
5354 04:50:49.002556
5355 04:50:49.002616 RX Delay -80 -> 252, step: 8
5356 04:50:49.002676 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5357 04:50:49.002736 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5358 04:50:49.002796 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5359 04:50:49.002856 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5360 04:50:49.002915 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5361 04:50:49.002975 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5362 04:50:49.003035 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5363 04:50:49.003095 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5364 04:50:49.003155 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5365 04:50:49.003216 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5366 04:50:49.003275 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5367 04:50:49.003336 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5368 04:50:49.003396 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5369 04:50:49.003456 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5370 04:50:49.003515 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5371 04:50:49.003575 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5372 04:50:49.003635 ==
5373 04:50:49.003696 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 04:50:49.003756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 04:50:49.003817 ==
5376 04:50:49.003877 DQS Delay:
5377 04:50:49.003937 DQS0 = 0, DQS1 = 0
5378 04:50:49.003997 DQM Delay:
5379 04:50:49.004056 DQM0 = 105, DQM1 = 91
5380 04:50:49.004116 DQ Delay:
5381 04:50:49.004176 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5382 04:50:49.004236 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5383 04:50:49.004295 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5384 04:50:49.004355 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =95
5385 04:50:49.004415
5386 04:50:49.004474
5387 04:50:49.004533 ==
5388 04:50:49.004601 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 04:50:49.004655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 04:50:49.004710 ==
5391 04:50:49.004765
5392 04:50:49.004819
5393 04:50:49.004872 TX Vref Scan disable
5394 04:50:49.004927 == TX Byte 0 ==
5395 04:50:49.004981 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5396 04:50:49.005036 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5397 04:50:49.005090 == TX Byte 1 ==
5398 04:50:49.005144 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5399 04:50:49.005199 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5400 04:50:49.005254 ==
5401 04:50:49.005308 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 04:50:49.005363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 04:50:49.005418 ==
5404 04:50:49.005472
5405 04:50:49.005527
5406 04:50:49.005581 TX Vref Scan disable
5407 04:50:49.005635 == TX Byte 0 ==
5408 04:50:49.005689 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5409 04:50:49.005744 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5410 04:50:49.005798 == TX Byte 1 ==
5411 04:50:49.005852 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5412 04:50:49.005907 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5413 04:50:49.005970
5414 04:50:49.006025 [DATLAT]
5415 04:50:49.006079 Freq=933, CH0 RK1
5416 04:50:49.006134
5417 04:50:49.006188 DATLAT Default: 0xb
5418 04:50:49.006242 0, 0xFFFF, sum = 0
5419 04:50:49.006298 1, 0xFFFF, sum = 0
5420 04:50:49.006353 2, 0xFFFF, sum = 0
5421 04:50:49.006409 3, 0xFFFF, sum = 0
5422 04:50:49.006464 4, 0xFFFF, sum = 0
5423 04:50:49.006519 5, 0xFFFF, sum = 0
5424 04:50:49.006574 6, 0xFFFF, sum = 0
5425 04:50:49.006629 7, 0xFFFF, sum = 0
5426 04:50:49.006684 8, 0xFFFF, sum = 0
5427 04:50:49.006738 9, 0xFFFF, sum = 0
5428 04:50:49.006793 10, 0x0, sum = 1
5429 04:50:49.006849 11, 0x0, sum = 2
5430 04:50:49.006903 12, 0x0, sum = 3
5431 04:50:49.006958 13, 0x0, sum = 4
5432 04:50:49.007013 best_step = 11
5433 04:50:49.007067
5434 04:50:49.007127 ==
5435 04:50:49.007215 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 04:50:49.007319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 04:50:49.007389 ==
5438 04:50:49.007447 RX Vref Scan: 0
5439 04:50:49.007502
5440 04:50:49.007557 RX Vref 0 -> 0, step: 1
5441 04:50:49.007617
5442 04:50:49.007672 RX Delay -53 -> 252, step: 4
5443 04:50:49.007728 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5444 04:50:49.007787 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5445 04:50:49.007843 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5446 04:50:49.007898 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5447 04:50:49.007955 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5448 04:50:49.008011 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5449 04:50:49.008068 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5450 04:50:49.008122 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5451 04:50:49.008177 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5452 04:50:49.008232 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5453 04:50:49.008287 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5454 04:50:49.008342 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5455 04:50:49.008409 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5456 04:50:49.008465 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5457 04:50:49.008520 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5458 04:50:49.008768 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5459 04:50:49.008830 ==
5460 04:50:49.008886 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 04:50:49.008942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 04:50:49.008998 ==
5463 04:50:49.009053 DQS Delay:
5464 04:50:49.009107 DQS0 = 0, DQS1 = 0
5465 04:50:49.009162 DQM Delay:
5466 04:50:49.009217 DQM0 = 103, DQM1 = 92
5467 04:50:49.009271 DQ Delay:
5468 04:50:49.009326 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =98
5469 04:50:49.009381 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5470 04:50:49.009436 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5471 04:50:49.009491 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =98
5472 04:50:49.009545
5473 04:50:49.009611
5474 04:50:49.009663 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5475 04:50:49.009716 CH0 RK1: MR19=505, MR18=2A0B
5476 04:50:49.009769 CH0_RK1: MR19=0x505, MR18=0x2A0B, DQSOSC=408, MR23=63, INC=65, DEC=43
5477 04:50:49.009822 [RxdqsGatingPostProcess] freq 933
5478 04:50:49.009875 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5479 04:50:49.009928 best DQS0 dly(2T, 0.5T) = (0, 10)
5480 04:50:49.010025 best DQS1 dly(2T, 0.5T) = (0, 10)
5481 04:50:49.010078 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5482 04:50:49.010130 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5483 04:50:49.010183 best DQS0 dly(2T, 0.5T) = (0, 10)
5484 04:50:49.010235 best DQS1 dly(2T, 0.5T) = (0, 10)
5485 04:50:49.010287 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5486 04:50:49.010339 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5487 04:50:49.010392 Pre-setting of DQS Precalculation
5488 04:50:49.010444 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5489 04:50:49.010497 ==
5490 04:50:49.010549 Dram Type= 6, Freq= 0, CH_1, rank 0
5491 04:50:49.010601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 04:50:49.010654 ==
5493 04:50:49.010705 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5494 04:50:49.010758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5495 04:50:49.010811 [CA 0] Center 38 (8~68) winsize 61
5496 04:50:49.010863 [CA 1] Center 38 (8~68) winsize 61
5497 04:50:49.010915 [CA 2] Center 36 (6~66) winsize 61
5498 04:50:49.010967 [CA 3] Center 34 (4~65) winsize 62
5499 04:50:49.011019 [CA 4] Center 34 (4~65) winsize 62
5500 04:50:49.011071 [CA 5] Center 34 (4~65) winsize 62
5501 04:50:49.011123
5502 04:50:49.011175 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5503 04:50:49.011227
5504 04:50:49.011279 [CATrainingPosCal] consider 1 rank data
5505 04:50:49.011331 u2DelayCellTimex100 = 270/100 ps
5506 04:50:49.011383 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5507 04:50:49.011436 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5508 04:50:49.011488 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5509 04:50:49.011539 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5510 04:50:49.011591 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5511 04:50:49.011643 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5512 04:50:49.011695
5513 04:50:49.011747 CA PerBit enable=1, Macro0, CA PI delay=34
5514 04:50:49.011798
5515 04:50:49.011850 [CBTSetCACLKResult] CA Dly = 34
5516 04:50:49.011902 CS Dly: 6 (0~37)
5517 04:50:49.011954 ==
5518 04:50:49.012007 Dram Type= 6, Freq= 0, CH_1, rank 1
5519 04:50:49.012060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 04:50:49.012113 ==
5521 04:50:49.012165 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5522 04:50:49.012218 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5523 04:50:49.012270 [CA 0] Center 38 (8~68) winsize 61
5524 04:50:49.012322 [CA 1] Center 38 (8~68) winsize 61
5525 04:50:49.012375 [CA 2] Center 35 (5~66) winsize 62
5526 04:50:49.012428 [CA 3] Center 35 (5~65) winsize 61
5527 04:50:49.012480 [CA 4] Center 35 (5~65) winsize 61
5528 04:50:49.012531 [CA 5] Center 35 (5~65) winsize 61
5529 04:50:49.012583
5530 04:50:49.012634 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5531 04:50:49.012687
5532 04:50:49.012738 [CATrainingPosCal] consider 2 rank data
5533 04:50:49.012790 u2DelayCellTimex100 = 270/100 ps
5534 04:50:49.012843 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5535 04:50:49.012895 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5536 04:50:49.012947 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5537 04:50:49.012998 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5538 04:50:49.013050 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
5539 04:50:49.013102 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5540 04:50:49.013154
5541 04:50:49.013206 CA PerBit enable=1, Macro0, CA PI delay=35
5542 04:50:49.013258
5543 04:50:49.013310 [CBTSetCACLKResult] CA Dly = 35
5544 04:50:49.013361 CS Dly: 7 (0~40)
5545 04:50:49.013413
5546 04:50:49.013464 ----->DramcWriteLeveling(PI) begin...
5547 04:50:49.013518 ==
5548 04:50:49.013570 Dram Type= 6, Freq= 0, CH_1, rank 0
5549 04:50:49.013622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 04:50:49.013674 ==
5551 04:50:49.013726 Write leveling (Byte 0): 28 => 28
5552 04:50:49.013778 Write leveling (Byte 1): 28 => 28
5553 04:50:49.013830 DramcWriteLeveling(PI) end<-----
5554 04:50:49.013881
5555 04:50:49.013933 ==
5556 04:50:49.014030 Dram Type= 6, Freq= 0, CH_1, rank 0
5557 04:50:49.014083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 04:50:49.014136 ==
5559 04:50:49.014188 [Gating] SW mode calibration
5560 04:50:49.014239 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5561 04:50:49.014292 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5562 04:50:49.014344 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 04:50:49.014396 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 04:50:49.014449 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 04:50:49.014501 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 04:50:49.014554 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 04:50:49.014606 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5568 04:50:49.014658 0 14 24 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
5569 04:50:49.014710 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5570 04:50:49.014762 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 04:50:49.014814 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 04:50:49.014866 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 04:50:49.014919 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 04:50:49.014970 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 04:50:49.015212 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 04:50:49.015271 0 15 24 | B1->B0 | 2626 2828 | 1 1 | (0 0) (0 0)
5577 04:50:49.015325 0 15 28 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (0 0)
5578 04:50:49.015377 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 04:50:49.015430 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 04:50:49.015483 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 04:50:49.015535 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 04:50:49.015588 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 04:50:49.015640 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5584 04:50:49.015693 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5585 04:50:49.015745 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 04:50:49.015797 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 04:50:49.015849 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 04:50:49.015901 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 04:50:49.015953 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 04:50:49.016005 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 04:50:49.016056 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 04:50:49.016108 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 04:50:49.016161 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 04:50:49.016213 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 04:50:49.016265 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 04:50:49.016317 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 04:50:49.016369 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 04:50:49.016422 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 04:50:49.016475 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 04:50:49.016527 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5601 04:50:49.016579 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 04:50:49.016630 Total UI for P1: 0, mck2ui 16
5603 04:50:49.016683 best dqsien dly found for B0: ( 1, 2, 24)
5604 04:50:49.016735 Total UI for P1: 0, mck2ui 16
5605 04:50:49.016787 best dqsien dly found for B1: ( 1, 2, 26)
5606 04:50:49.016839 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5607 04:50:49.016891 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5608 04:50:49.016943
5609 04:50:49.016995 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5610 04:50:49.017047 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5611 04:50:49.017099 [Gating] SW calibration Done
5612 04:50:49.017150 ==
5613 04:50:49.017202 Dram Type= 6, Freq= 0, CH_1, rank 0
5614 04:50:49.017254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 04:50:49.017307 ==
5616 04:50:49.017359 RX Vref Scan: 0
5617 04:50:49.017414
5618 04:50:49.017466 RX Vref 0 -> 0, step: 1
5619 04:50:49.017518
5620 04:50:49.017576 RX Delay -80 -> 252, step: 8
5621 04:50:49.017659 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5622 04:50:49.017742 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5623 04:50:49.017825 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5624 04:50:49.017907 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5625 04:50:49.018025 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5626 04:50:49.018079 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5627 04:50:49.018135 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5628 04:50:49.018188 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5629 04:50:49.018240 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5630 04:50:49.018294 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5631 04:50:49.018347 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5632 04:50:49.018400 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5633 04:50:49.018452 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5634 04:50:49.018509 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5635 04:50:49.018563 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5636 04:50:49.018615 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5637 04:50:49.018670 ==
5638 04:50:49.018723 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 04:50:49.018776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 04:50:49.018829 ==
5641 04:50:49.018886 DQS Delay:
5642 04:50:49.018938 DQS0 = 0, DQS1 = 0
5643 04:50:49.018991 DQM Delay:
5644 04:50:49.019048 DQM0 = 101, DQM1 = 95
5645 04:50:49.019103 DQ Delay:
5646 04:50:49.019155 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5647 04:50:49.019207 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5648 04:50:49.019262 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5649 04:50:49.019314 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5650 04:50:49.019367
5651 04:50:49.019423
5652 04:50:49.019505 ==
5653 04:50:49.019587 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 04:50:49.019670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 04:50:49.019752 ==
5656 04:50:49.019832
5657 04:50:49.019912
5658 04:50:49.019993 TX Vref Scan disable
5659 04:50:49.020074 == TX Byte 0 ==
5660 04:50:49.020155 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5661 04:50:49.020238 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5662 04:50:49.020318 == TX Byte 1 ==
5663 04:50:49.020400 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5664 04:50:49.020482 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5665 04:50:49.020562 ==
5666 04:50:49.020644 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 04:50:49.020725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 04:50:49.020806 ==
5669 04:50:49.020887
5670 04:50:49.020967
5671 04:50:49.021048 TX Vref Scan disable
5672 04:50:49.021128 == TX Byte 0 ==
5673 04:50:49.021209 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5674 04:50:49.021291 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5675 04:50:49.021372 == TX Byte 1 ==
5676 04:50:49.021453 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5677 04:50:49.021535 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5678 04:50:49.021615
5679 04:50:49.021696 [DATLAT]
5680 04:50:49.021778 Freq=933, CH1 RK0
5681 04:50:49.021859
5682 04:50:49.021944 DATLAT Default: 0xd
5683 04:50:49.022062 0, 0xFFFF, sum = 0
5684 04:50:49.022146 1, 0xFFFF, sum = 0
5685 04:50:49.022229 2, 0xFFFF, sum = 0
5686 04:50:49.022312 3, 0xFFFF, sum = 0
5687 04:50:49.022395 4, 0xFFFF, sum = 0
5688 04:50:49.022478 5, 0xFFFF, sum = 0
5689 04:50:49.022561 6, 0xFFFF, sum = 0
5690 04:50:49.022644 7, 0xFFFF, sum = 0
5691 04:50:49.022727 8, 0xFFFF, sum = 0
5692 04:50:49.022810 9, 0xFFFF, sum = 0
5693 04:50:49.022893 10, 0x0, sum = 1
5694 04:50:49.022976 11, 0x0, sum = 2
5695 04:50:49.023059 12, 0x0, sum = 3
5696 04:50:49.023141 13, 0x0, sum = 4
5697 04:50:49.023224 best_step = 11
5698 04:50:49.023305
5699 04:50:49.023385 ==
5700 04:50:49.023467 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 04:50:49.023549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 04:50:49.023630 ==
5703 04:50:49.023712 RX Vref Scan: 1
5704 04:50:49.023793
5705 04:50:49.024073 RX Vref 0 -> 0, step: 1
5706 04:50:49.024162
5707 04:50:49.024244 RX Delay -53 -> 252, step: 4
5708 04:50:49.024325
5709 04:50:49.024407 Set Vref, RX VrefLevel [Byte0]: 52
5710 04:50:49.024473 [Byte1]: 53
5711 04:50:49.024527
5712 04:50:49.024580 Final RX Vref Byte 0 = 52 to rank0
5713 04:50:49.024633 Final RX Vref Byte 1 = 53 to rank0
5714 04:50:49.024685 Final RX Vref Byte 0 = 52 to rank1
5715 04:50:49.024738 Final RX Vref Byte 1 = 53 to rank1==
5716 04:50:49.024791 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 04:50:49.024844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 04:50:49.024897 ==
5719 04:50:49.024949 DQS Delay:
5720 04:50:49.025001 DQS0 = 0, DQS1 = 0
5721 04:50:49.025053 DQM Delay:
5722 04:50:49.025105 DQM0 = 103, DQM1 = 96
5723 04:50:49.025157 DQ Delay:
5724 04:50:49.025209 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5725 04:50:49.025262 DQ4 =102, DQ5 =110, DQ6 =112, DQ7 =102
5726 04:50:49.025313 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =92
5727 04:50:49.025366 DQ12 =106, DQ13 =100, DQ14 =102, DQ15 =102
5728 04:50:49.025418
5729 04:50:49.025469
5730 04:50:49.025520 [DQSOSCAuto] RK0, (LSB)MR18= 0x1730, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5731 04:50:49.025572 CH1 RK0: MR19=505, MR18=1730
5732 04:50:49.025625 CH1_RK0: MR19=0x505, MR18=0x1730, DQSOSC=406, MR23=63, INC=65, DEC=43
5733 04:50:49.025677
5734 04:50:49.025728 ----->DramcWriteLeveling(PI) begin...
5735 04:50:49.025782 ==
5736 04:50:49.025834 Dram Type= 6, Freq= 0, CH_1, rank 1
5737 04:50:49.025887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 04:50:49.025960 ==
5739 04:50:49.026017 Write leveling (Byte 0): 27 => 27
5740 04:50:49.026070 Write leveling (Byte 1): 29 => 29
5741 04:50:49.026122 DramcWriteLeveling(PI) end<-----
5742 04:50:49.026175
5743 04:50:49.026227 ==
5744 04:50:49.026279 Dram Type= 6, Freq= 0, CH_1, rank 1
5745 04:50:49.026332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 04:50:49.026385 ==
5747 04:50:49.026448 [Gating] SW mode calibration
5748 04:50:49.026541 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5749 04:50:49.026606 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5750 04:50:49.026660 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 04:50:49.026714 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 04:50:49.026768 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 04:50:49.026821 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 04:50:49.026874 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 04:50:49.026926 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 04:50:49.026979 0 14 24 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 1)
5757 04:50:49.027032 0 14 28 | B1->B0 | 2525 2e2e | 0 1 | (0 0) (1 1)
5758 04:50:49.027085 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5759 04:50:49.027137 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 04:50:49.027190 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 04:50:49.027242 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 04:50:49.027295 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 04:50:49.027348 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 04:50:49.027400 0 15 24 | B1->B0 | 2b2b 2424 | 0 0 | (1 1) (1 1)
5765 04:50:49.027453 0 15 28 | B1->B0 | 4141 3939 | 0 0 | (0 0) (0 0)
5766 04:50:49.027505 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 04:50:49.027556 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 04:50:49.027609 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 04:50:49.027661 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 04:50:49.027714 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 04:50:49.027765 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 04:50:49.027820 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5773 04:50:49.027873 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5774 04:50:49.027925 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 04:50:49.027978 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 04:50:49.028033 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 04:50:49.028085 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 04:50:49.028137 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 04:50:49.028189 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 04:50:49.028241 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 04:50:49.028293 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 04:50:49.028345 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 04:50:49.028401 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 04:50:49.028454 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 04:50:49.028506 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 04:50:49.028560 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 04:50:49.028614 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 04:50:49.028667 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5789 04:50:49.028719 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 04:50:49.028771 Total UI for P1: 0, mck2ui 16
5791 04:50:49.028824 best dqsien dly found for B0: ( 1, 2, 26)
5792 04:50:49.028877 Total UI for P1: 0, mck2ui 16
5793 04:50:49.028929 best dqsien dly found for B1: ( 1, 2, 24)
5794 04:50:49.028981 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5795 04:50:49.029033 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5796 04:50:49.029085
5797 04:50:49.029137 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5798 04:50:49.029190 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5799 04:50:49.029242 [Gating] SW calibration Done
5800 04:50:49.029293 ==
5801 04:50:49.029345 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 04:50:49.029398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 04:50:49.029451 ==
5804 04:50:49.029503 RX Vref Scan: 0
5805 04:50:49.029556
5806 04:50:49.029607 RX Vref 0 -> 0, step: 1
5807 04:50:49.029659
5808 04:50:49.029711 RX Delay -80 -> 252, step: 8
5809 04:50:49.029763 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5810 04:50:49.029815 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5811 04:50:49.029867 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5812 04:50:49.029918 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5813 04:50:49.029975 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5814 04:50:49.030219 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5815 04:50:49.030278 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5816 04:50:49.030332 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5817 04:50:49.030385 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5818 04:50:49.030482 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5819 04:50:49.030580 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5820 04:50:49.030633 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5821 04:50:49.030685 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5822 04:50:49.030737 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5823 04:50:49.030789 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5824 04:50:49.030841 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5825 04:50:49.030893 ==
5826 04:50:49.030945 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 04:50:49.030998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 04:50:49.031051 ==
5829 04:50:49.031103 DQS Delay:
5830 04:50:49.031155 DQS0 = 0, DQS1 = 0
5831 04:50:49.031206 DQM Delay:
5832 04:50:49.031259 DQM0 = 103, DQM1 = 96
5833 04:50:49.031311 DQ Delay:
5834 04:50:49.031363 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =103
5835 04:50:49.031415 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =103
5836 04:50:49.031468 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5837 04:50:49.031521 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5838 04:50:49.031573
5839 04:50:49.031625
5840 04:50:49.031676 ==
5841 04:50:49.031728 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 04:50:49.031780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 04:50:49.031833 ==
5844 04:50:49.031884
5845 04:50:49.031936
5846 04:50:49.031987 TX Vref Scan disable
5847 04:50:49.032040 == TX Byte 0 ==
5848 04:50:49.032092 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5849 04:50:49.032145 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5850 04:50:49.032197 == TX Byte 1 ==
5851 04:50:49.032249 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5852 04:50:49.032302 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5853 04:50:49.032354 ==
5854 04:50:49.032412 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 04:50:49.032467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 04:50:49.032519 ==
5857 04:50:49.032571
5858 04:50:49.032622
5859 04:50:49.032674 TX Vref Scan disable
5860 04:50:49.032726 == TX Byte 0 ==
5861 04:50:49.032778 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5862 04:50:49.032830 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5863 04:50:49.032882 == TX Byte 1 ==
5864 04:50:49.032934 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5865 04:50:49.032987 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5866 04:50:49.033039
5867 04:50:49.033091 [DATLAT]
5868 04:50:49.033143 Freq=933, CH1 RK1
5869 04:50:49.033195
5870 04:50:49.033247 DATLAT Default: 0xb
5871 04:50:49.033298 0, 0xFFFF, sum = 0
5872 04:50:49.033352 1, 0xFFFF, sum = 0
5873 04:50:49.033405 2, 0xFFFF, sum = 0
5874 04:50:49.033458 3, 0xFFFF, sum = 0
5875 04:50:49.033510 4, 0xFFFF, sum = 0
5876 04:50:49.033563 5, 0xFFFF, sum = 0
5877 04:50:49.033615 6, 0xFFFF, sum = 0
5878 04:50:49.033669 7, 0xFFFF, sum = 0
5879 04:50:49.033722 8, 0xFFFF, sum = 0
5880 04:50:49.033775 9, 0xFFFF, sum = 0
5881 04:50:49.033828 10, 0x0, sum = 1
5882 04:50:49.033882 11, 0x0, sum = 2
5883 04:50:49.033935 12, 0x0, sum = 3
5884 04:50:49.033997 13, 0x0, sum = 4
5885 04:50:49.034051 best_step = 11
5886 04:50:49.034102
5887 04:50:49.034154 ==
5888 04:50:49.034206 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 04:50:49.034259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 04:50:49.034311 ==
5891 04:50:49.034363 RX Vref Scan: 0
5892 04:50:49.034426
5893 04:50:49.034498 RX Vref 0 -> 0, step: 1
5894 04:50:49.034571
5895 04:50:49.034626 RX Delay -53 -> 252, step: 4
5896 04:50:49.034678 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5897 04:50:49.034731 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5898 04:50:49.034784 iDelay=199, Bit 2, Center 92 (11 ~ 174) 164
5899 04:50:49.034837 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5900 04:50:49.034889 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5901 04:50:49.034941 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5902 04:50:49.034993 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5903 04:50:49.035046 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5904 04:50:49.035097 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5905 04:50:49.035149 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5906 04:50:49.035201 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5907 04:50:49.035253 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5908 04:50:49.035305 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5909 04:50:49.035357 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5910 04:50:49.035408 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5911 04:50:49.035460 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5912 04:50:49.035512 ==
5913 04:50:49.035565 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 04:50:49.035618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 04:50:49.035670 ==
5916 04:50:49.035723 DQS Delay:
5917 04:50:49.035775 DQS0 = 0, DQS1 = 0
5918 04:50:49.035827 DQM Delay:
5919 04:50:49.035879 DQM0 = 104, DQM1 = 97
5920 04:50:49.488635 DQ Delay:
5921 04:50:49.489217 DQ0 =108, DQ1 =98, DQ2 =92, DQ3 =102
5922 04:50:49.489582 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5923 04:50:49.490189 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =90
5924 04:50:49.490636 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =106
5925 04:50:49.490973
5926 04:50:49.491388
5927 04:50:49.491748 [DQSOSCAuto] RK1, (LSB)MR18= 0x2402, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
5928 04:50:49.492087 CH1 RK1: MR19=505, MR18=2402
5929 04:50:49.492391 CH1_RK1: MR19=0x505, MR18=0x2402, DQSOSC=410, MR23=63, INC=64, DEC=42
5930 04:50:49.492776 [RxdqsGatingPostProcess] freq 933
5931 04:50:49.493081 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5932 04:50:49.493445 best DQS0 dly(2T, 0.5T) = (0, 10)
5933 04:50:49.493794 best DQS1 dly(2T, 0.5T) = (0, 10)
5934 04:50:49.494219 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5935 04:50:49.494526 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5936 04:50:49.494823 best DQS0 dly(2T, 0.5T) = (0, 10)
5937 04:50:49.495208 best DQS1 dly(2T, 0.5T) = (0, 10)
5938 04:50:49.495563 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5939 04:50:49.495874 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5940 04:50:49.496250 Pre-setting of DQS Precalculation
5941 04:50:49.496553 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5942 04:50:49.496932 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5943 04:50:49.497280 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5944 04:50:49.497579
5945 04:50:49.497872
5946 04:50:49.498231 [Calibration Summary] 1866 Mbps
5947 04:50:49.498525 CH 0, Rank 0
5948 04:50:49.498823 SW Impedance : PASS
5949 04:50:49.499205 DUTY Scan : NO K
5950 04:50:49.499529 ZQ Calibration : PASS
5951 04:50:49.500298 Jitter Meter : NO K
5952 04:50:49.500750 CBT Training : PASS
5953 04:50:49.501116 Write leveling : PASS
5954 04:50:49.501430 RX DQS gating : PASS
5955 04:50:49.501844 RX DQ/DQS(RDDQC) : PASS
5956 04:50:49.502195 TX DQ/DQS : PASS
5957 04:50:49.502495 RX DATLAT : PASS
5958 04:50:49.502786 RX DQ/DQS(Engine): PASS
5959 04:50:49.503075 TX OE : NO K
5960 04:50:49.503654 All Pass.
5961 04:50:49.504047
5962 04:50:49.504353 CH 0, Rank 1
5963 04:50:49.504649 SW Impedance : PASS
5964 04:50:49.504942 DUTY Scan : NO K
5965 04:50:49.505231 ZQ Calibration : PASS
5966 04:50:49.505519 Jitter Meter : NO K
5967 04:50:49.505809 CBT Training : PASS
5968 04:50:49.506166 Write leveling : PASS
5969 04:50:49.506462 RX DQS gating : PASS
5970 04:50:49.506748 RX DQ/DQS(RDDQC) : PASS
5971 04:50:49.507036 TX DQ/DQS : PASS
5972 04:50:49.507369 RX DATLAT : PASS
5973 04:50:49.507662 RX DQ/DQS(Engine): PASS
5974 04:50:49.507952 TX OE : NO K
5975 04:50:49.508342 All Pass.
5976 04:50:49.508793
5977 04:50:49.509120 CH 1, Rank 0
5978 04:50:49.509415 SW Impedance : PASS
5979 04:50:49.509710 DUTY Scan : NO K
5980 04:50:49.510034 ZQ Calibration : PASS
5981 04:50:49.510334 Jitter Meter : NO K
5982 04:50:49.510660 CBT Training : PASS
5983 04:50:49.510955 Write leveling : PASS
5984 04:50:49.511244 RX DQS gating : PASS
5985 04:50:49.511533 RX DQ/DQS(RDDQC) : PASS
5986 04:50:49.511820 TX DQ/DQS : PASS
5987 04:50:49.512110 RX DATLAT : PASS
5988 04:50:49.512397 RX DQ/DQS(Engine): PASS
5989 04:50:49.512684 TX OE : NO K
5990 04:50:49.512973 All Pass.
5991 04:50:49.513261
5992 04:50:49.513583 CH 1, Rank 1
5993 04:50:49.513873 SW Impedance : PASS
5994 04:50:49.514202 DUTY Scan : NO K
5995 04:50:49.514496 ZQ Calibration : PASS
5996 04:50:49.514740 Jitter Meter : NO K
5997 04:50:49.514944 CBT Training : PASS
5998 04:50:49.515146 Write leveling : PASS
5999 04:50:49.515348 RX DQS gating : PASS
6000 04:50:49.515548 RX DQ/DQS(RDDQC) : PASS
6001 04:50:49.515750 TX DQ/DQS : PASS
6002 04:50:49.515952 RX DATLAT : PASS
6003 04:50:49.516155 RX DQ/DQS(Engine): PASS
6004 04:50:49.516355 TX OE : NO K
6005 04:50:49.516556 All Pass.
6006 04:50:49.516785
6007 04:50:49.516991 DramC Write-DBI off
6008 04:50:49.517195 PER_BANK_REFRESH: Hybrid Mode
6009 04:50:49.517397 TX_TRACKING: ON
6010 04:50:49.517603 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6011 04:50:49.517812 [FAST_K] Save calibration result to emmc
6012 04:50:49.518050 dramc_set_vcore_voltage set vcore to 650000
6013 04:50:49.518262 Read voltage for 400, 6
6014 04:50:49.518473 Vio18 = 0
6015 04:50:49.518683 Vcore = 650000
6016 04:50:49.518892 Vdram = 0
6017 04:50:49.519100 Vddq = 0
6018 04:50:49.519309 Vmddr = 0
6019 04:50:49.519521 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6020 04:50:49.519713 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6021 04:50:49.519870 MEM_TYPE=3, freq_sel=20
6022 04:50:49.520025 sv_algorithm_assistance_LP4_800
6023 04:50:49.520202 ============ PULL DRAM RESETB DOWN ============
6024 04:50:49.520359 ========== PULL DRAM RESETB DOWN end =========
6025 04:50:49.520515 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6026 04:50:49.520704 ===================================
6027 04:50:49.520862 LPDDR4 DRAM CONFIGURATION
6028 04:50:49.521016 ===================================
6029 04:50:49.521171 EX_ROW_EN[0] = 0x0
6030 04:50:49.521324 EX_ROW_EN[1] = 0x0
6031 04:50:49.521478 LP4Y_EN = 0x0
6032 04:50:49.521630 WORK_FSP = 0x0
6033 04:50:49.521783 WL = 0x2
6034 04:50:49.521936 RL = 0x2
6035 04:50:49.522117 BL = 0x2
6036 04:50:49.522271 RPST = 0x0
6037 04:50:49.522424 RD_PRE = 0x0
6038 04:50:49.522577 WR_PRE = 0x1
6039 04:50:49.522729 WR_PST = 0x0
6040 04:50:49.522882 DBI_WR = 0x0
6041 04:50:49.523035 DBI_RD = 0x0
6042 04:50:49.523188 OTF = 0x1
6043 04:50:49.523342 ===================================
6044 04:50:49.523496 ===================================
6045 04:50:49.523672 ANA top config
6046 04:50:49.523827 ===================================
6047 04:50:49.523983 DLL_ASYNC_EN = 0
6048 04:50:49.524136 ALL_SLAVE_EN = 1
6049 04:50:49.524291 NEW_RANK_MODE = 1
6050 04:50:49.524448 DLL_IDLE_MODE = 1
6051 04:50:49.524611 LP45_APHY_COMB_EN = 1
6052 04:50:49.524732 TX_ODT_DIS = 1
6053 04:50:49.524855 NEW_8X_MODE = 1
6054 04:50:49.524979 ===================================
6055 04:50:49.525101 ===================================
6056 04:50:49.525223 data_rate = 800
6057 04:50:49.525346 CKR = 1
6058 04:50:49.525468 DQ_P2S_RATIO = 4
6059 04:50:49.525590 ===================================
6060 04:50:49.525712 CA_P2S_RATIO = 4
6061 04:50:49.525835 DQ_CA_OPEN = 0
6062 04:50:49.525970 DQ_SEMI_OPEN = 1
6063 04:50:49.526097 CA_SEMI_OPEN = 1
6064 04:50:49.526219 CA_FULL_RATE = 0
6065 04:50:49.526341 DQ_CKDIV4_EN = 0
6066 04:50:49.526463 CA_CKDIV4_EN = 1
6067 04:50:49.526586 CA_PREDIV_EN = 0
6068 04:50:49.526722 PH8_DLY = 0
6069 04:50:49.526845 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6070 04:50:49.526967 DQ_AAMCK_DIV = 0
6071 04:50:49.527087 CA_AAMCK_DIV = 0
6072 04:50:49.527209 CA_ADMCK_DIV = 4
6073 04:50:49.527330 DQ_TRACK_CA_EN = 0
6074 04:50:49.527453 CA_PICK = 800
6075 04:50:49.527575 CA_MCKIO = 400
6076 04:50:49.527697 MCKIO_SEMI = 400
6077 04:50:49.527820 PLL_FREQ = 3016
6078 04:50:49.527942 DQ_UI_PI_RATIO = 32
6079 04:50:49.528064 CA_UI_PI_RATIO = 32
6080 04:50:49.528186 ===================================
6081 04:50:49.528309 ===================================
6082 04:50:49.528432 memory_type:LPDDR4
6083 04:50:49.528555 GP_NUM : 10
6084 04:50:49.528677 SRAM_EN : 1
6085 04:50:49.528799 MD32_EN : 0
6086 04:50:49.528919 ===================================
6087 04:50:49.529041 [ANA_INIT] >>>>>>>>>>>>>>
6088 04:50:49.529163 <<<<<< [CONFIGURE PHASE]: ANA_TX
6089 04:50:49.529288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6090 04:50:49.529410 ===================================
6091 04:50:49.529546 data_rate = 800,PCW = 0X7400
6092 04:50:49.529648 ===================================
6093 04:50:49.529750 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6094 04:50:49.529852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6095 04:50:49.530199 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6096 04:50:49.530340 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6097 04:50:49.530447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6098 04:50:49.530551 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6099 04:50:49.530656 [ANA_INIT] flow start
6100 04:50:49.530757 [ANA_INIT] PLL >>>>>>>>
6101 04:50:49.530857 [ANA_INIT] PLL <<<<<<<<
6102 04:50:49.530958 [ANA_INIT] MIDPI >>>>>>>>
6103 04:50:49.531059 [ANA_INIT] MIDPI <<<<<<<<
6104 04:50:49.531159 [ANA_INIT] DLL >>>>>>>>
6105 04:50:49.531259 [ANA_INIT] flow end
6106 04:50:49.531360 ============ LP4 DIFF to SE enter ============
6107 04:50:49.531462 ============ LP4 DIFF to SE exit ============
6108 04:50:49.531565 [ANA_INIT] <<<<<<<<<<<<<
6109 04:50:49.531666 [Flow] Enable top DCM control >>>>>
6110 04:50:49.531767 [Flow] Enable top DCM control <<<<<
6111 04:50:49.531868 Enable DLL master slave shuffle
6112 04:50:49.531970 ==============================================================
6113 04:50:49.532073 Gating Mode config
6114 04:50:49.532176 ==============================================================
6115 04:50:49.532278 Config description:
6116 04:50:49.532380 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6117 04:50:49.532484 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6118 04:50:49.532588 SELPH_MODE 0: By rank 1: By Phase
6119 04:50:49.532690 ==============================================================
6120 04:50:49.532792 GAT_TRACK_EN = 0
6121 04:50:49.532894 RX_GATING_MODE = 2
6122 04:50:49.532995 RX_GATING_TRACK_MODE = 2
6123 04:50:49.533097 SELPH_MODE = 1
6124 04:50:49.533198 PICG_EARLY_EN = 1
6125 04:50:49.533300 VALID_LAT_VALUE = 1
6126 04:50:49.533414 ==============================================================
6127 04:50:49.533519 Enter into Gating configuration >>>>
6128 04:50:49.533621 Exit from Gating configuration <<<<
6129 04:50:49.533724 Enter into DVFS_PRE_config >>>>>
6130 04:50:49.533826 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6131 04:50:49.533931 Exit from DVFS_PRE_config <<<<<
6132 04:50:49.534053 Enter into PICG configuration >>>>
6133 04:50:49.534157 Exit from PICG configuration <<<<
6134 04:50:49.534258 [RX_INPUT] configuration >>>>>
6135 04:50:49.534360 [RX_INPUT] configuration <<<<<
6136 04:50:49.534462 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6137 04:50:49.534577 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6138 04:50:49.534665 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6139 04:50:49.534753 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6140 04:50:49.534840 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6141 04:50:49.534928 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6142 04:50:49.535016 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6143 04:50:49.535103 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6144 04:50:49.535190 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6145 04:50:49.535277 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6146 04:50:49.535364 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6147 04:50:49.535451 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6148 04:50:49.535539 ===================================
6149 04:50:49.535626 LPDDR4 DRAM CONFIGURATION
6150 04:50:49.535713 ===================================
6151 04:50:49.535800 EX_ROW_EN[0] = 0x0
6152 04:50:49.535887 EX_ROW_EN[1] = 0x0
6153 04:50:49.535973 LP4Y_EN = 0x0
6154 04:50:49.536059 WORK_FSP = 0x0
6155 04:50:49.536146 WL = 0x2
6156 04:50:49.536231 RL = 0x2
6157 04:50:49.536316 BL = 0x2
6158 04:50:49.536403 RPST = 0x0
6159 04:50:49.536489 RD_PRE = 0x0
6160 04:50:49.536586 WR_PRE = 0x1
6161 04:50:49.536673 WR_PST = 0x0
6162 04:50:49.536759 DBI_WR = 0x0
6163 04:50:49.536845 DBI_RD = 0x0
6164 04:50:49.536932 OTF = 0x1
6165 04:50:49.537018 ===================================
6166 04:50:49.537105 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6167 04:50:49.537191 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6168 04:50:49.537279 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6169 04:50:49.537366 ===================================
6170 04:50:49.537453 LPDDR4 DRAM CONFIGURATION
6171 04:50:49.537539 ===================================
6172 04:50:49.537625 EX_ROW_EN[0] = 0x10
6173 04:50:49.537712 EX_ROW_EN[1] = 0x0
6174 04:50:49.537797 LP4Y_EN = 0x0
6175 04:50:49.537882 WORK_FSP = 0x0
6176 04:50:49.537979 WL = 0x2
6177 04:50:49.538067 RL = 0x2
6178 04:50:49.538154 BL = 0x2
6179 04:50:49.538240 RPST = 0x0
6180 04:50:49.538327 RD_PRE = 0x0
6181 04:50:49.538414 WR_PRE = 0x1
6182 04:50:49.538500 WR_PST = 0x0
6183 04:50:49.538586 DBI_WR = 0x0
6184 04:50:49.538672 DBI_RD = 0x0
6185 04:50:49.538759 OTF = 0x1
6186 04:50:49.538845 ===================================
6187 04:50:49.538933 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6188 04:50:49.539020 nWR fixed to 30
6189 04:50:49.539108 [ModeRegInit_LP4] CH0 RK0
6190 04:50:49.539195 [ModeRegInit_LP4] CH0 RK1
6191 04:50:49.539281 [ModeRegInit_LP4] CH1 RK0
6192 04:50:49.539366 [ModeRegInit_LP4] CH1 RK1
6193 04:50:49.539452 match AC timing 19
6194 04:50:49.539538 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6195 04:50:49.539633 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6196 04:50:49.539709 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6197 04:50:49.539786 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6198 04:50:49.539862 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6199 04:50:49.539948 ==
6200 04:50:49.540025 Dram Type= 6, Freq= 0, CH_0, rank 0
6201 04:50:49.540101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6202 04:50:49.540178 ==
6203 04:50:49.540254 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6204 04:50:49.540541 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6205 04:50:49.540627 [CA 0] Center 36 (8~64) winsize 57
6206 04:50:49.540706 [CA 1] Center 36 (8~64) winsize 57
6207 04:50:49.540782 [CA 2] Center 36 (8~64) winsize 57
6208 04:50:49.540858 [CA 3] Center 36 (8~64) winsize 57
6209 04:50:49.540934 [CA 4] Center 36 (8~64) winsize 57
6210 04:50:49.541010 [CA 5] Center 36 (8~64) winsize 57
6211 04:50:49.541086
6212 04:50:49.541161 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6213 04:50:49.541237
6214 04:50:49.541312 [CATrainingPosCal] consider 1 rank data
6215 04:50:49.541389 u2DelayCellTimex100 = 270/100 ps
6216 04:50:49.541464 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 04:50:49.541540 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 04:50:49.541617 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 04:50:49.541693 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 04:50:49.541769 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 04:50:49.541844 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 04:50:49.541920
6223 04:50:49.542010 CA PerBit enable=1, Macro0, CA PI delay=36
6224 04:50:49.542088
6225 04:50:49.542164 [CBTSetCACLKResult] CA Dly = 36
6226 04:50:49.542240 CS Dly: 1 (0~32)
6227 04:50:49.542315 ==
6228 04:50:49.542391 Dram Type= 6, Freq= 0, CH_0, rank 1
6229 04:50:49.542468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6230 04:50:49.542544 ==
6231 04:50:49.542621 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6232 04:50:49.542698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6233 04:50:49.542774 [CA 0] Center 36 (8~64) winsize 57
6234 04:50:49.542851 [CA 1] Center 36 (8~64) winsize 57
6235 04:50:49.542926 [CA 2] Center 36 (8~64) winsize 57
6236 04:50:49.543001 [CA 3] Center 36 (8~64) winsize 57
6237 04:50:49.543077 [CA 4] Center 36 (8~64) winsize 57
6238 04:50:49.543153 [CA 5] Center 36 (8~64) winsize 57
6239 04:50:49.543238
6240 04:50:49.543316 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6241 04:50:49.543391
6242 04:50:49.543467 [CATrainingPosCal] consider 2 rank data
6243 04:50:49.543543 u2DelayCellTimex100 = 270/100 ps
6244 04:50:49.543619 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 04:50:49.543695 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 04:50:49.543770 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 04:50:49.543846 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 04:50:49.543922 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 04:50:49.543998 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 04:50:49.544073
6251 04:50:49.544149 CA PerBit enable=1, Macro0, CA PI delay=36
6252 04:50:49.544224
6253 04:50:49.544301 [CBTSetCACLKResult] CA Dly = 36
6254 04:50:49.544377 CS Dly: 1 (0~32)
6255 04:50:49.544452
6256 04:50:49.544526 ----->DramcWriteLeveling(PI) begin...
6257 04:50:49.544610 ==
6258 04:50:49.544678 Dram Type= 6, Freq= 0, CH_0, rank 0
6259 04:50:49.544745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 04:50:49.544814 ==
6261 04:50:49.544881 Write leveling (Byte 0): 40 => 8
6262 04:50:49.544949 Write leveling (Byte 1): 32 => 0
6263 04:50:49.545016 DramcWriteLeveling(PI) end<-----
6264 04:50:49.545083
6265 04:50:49.545150 ==
6266 04:50:49.545217 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 04:50:49.545283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 04:50:49.545351 ==
6269 04:50:49.545418 [Gating] SW mode calibration
6270 04:50:49.545485 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6271 04:50:49.545552 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6272 04:50:49.545620 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 04:50:49.545688 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 04:50:49.545755 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 04:50:49.545823 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 04:50:49.545891 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 04:50:49.545972 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 04:50:49.546042 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 04:50:49.546110 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 04:50:49.546177 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 04:50:49.546244 Total UI for P1: 0, mck2ui 16
6282 04:50:49.546312 best dqsien dly found for B0: ( 0, 14, 24)
6283 04:50:49.546379 Total UI for P1: 0, mck2ui 16
6284 04:50:49.546447 best dqsien dly found for B1: ( 0, 14, 24)
6285 04:50:49.546524 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6286 04:50:49.546592 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6287 04:50:49.546659
6288 04:50:49.546727 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6289 04:50:49.546800 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6290 04:50:49.546868 [Gating] SW calibration Done
6291 04:50:49.546935 ==
6292 04:50:49.547002 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 04:50:49.547070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 04:50:49.547136 ==
6295 04:50:49.547202 RX Vref Scan: 0
6296 04:50:49.547267
6297 04:50:49.547332 RX Vref 0 -> 0, step: 1
6298 04:50:49.547397
6299 04:50:49.547461 RX Delay -410 -> 252, step: 16
6300 04:50:49.547527 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6301 04:50:49.547593 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6302 04:50:49.547658 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6303 04:50:49.547723 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6304 04:50:49.547788 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6305 04:50:49.547853 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6306 04:50:49.547917 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6307 04:50:49.547983 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6308 04:50:49.548048 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6309 04:50:49.548113 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6310 04:50:49.548178 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6311 04:50:49.548243 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6312 04:50:49.548309 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6313 04:50:49.548374 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6314 04:50:49.548439 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6315 04:50:49.548504 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6316 04:50:49.548569 ==
6317 04:50:49.548634 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 04:50:49.548699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 04:50:49.548779 ==
6320 04:50:49.548851 DQS Delay:
6321 04:50:49.548916 DQS0 = 27, DQS1 = 43
6322 04:50:49.548981 DQM Delay:
6323 04:50:49.549046 DQM0 = 13, DQM1 = 14
6324 04:50:49.549317 DQ Delay:
6325 04:50:49.549394 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8
6326 04:50:49.549463 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6327 04:50:49.549530 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6328 04:50:49.549608 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6329 04:50:49.549668
6330 04:50:49.549726
6331 04:50:49.549784 ==
6332 04:50:49.549843 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 04:50:49.549903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 04:50:49.549969 ==
6335 04:50:49.550029
6336 04:50:49.550097
6337 04:50:49.550157 TX Vref Scan disable
6338 04:50:49.550216 == TX Byte 0 ==
6339 04:50:49.550274 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6340 04:50:49.550334 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6341 04:50:49.550393 == TX Byte 1 ==
6342 04:50:49.550453 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6343 04:50:49.550512 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6344 04:50:49.550571 ==
6345 04:50:49.550629 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 04:50:49.550688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 04:50:49.550759 ==
6348 04:50:49.550825
6349 04:50:49.550883
6350 04:50:49.550942 TX Vref Scan disable
6351 04:50:49.551000 == TX Byte 0 ==
6352 04:50:49.551059 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 04:50:49.551119 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 04:50:49.551177 == TX Byte 1 ==
6355 04:50:49.551236 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6356 04:50:49.551295 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6357 04:50:49.551354
6358 04:50:49.551412 [DATLAT]
6359 04:50:49.551470 Freq=400, CH0 RK0
6360 04:50:49.551528
6361 04:50:49.551587 DATLAT Default: 0xf
6362 04:50:49.551646 0, 0xFFFF, sum = 0
6363 04:50:49.551706 1, 0xFFFF, sum = 0
6364 04:50:49.551767 2, 0xFFFF, sum = 0
6365 04:50:49.551826 3, 0xFFFF, sum = 0
6366 04:50:49.551886 4, 0xFFFF, sum = 0
6367 04:50:49.551946 5, 0xFFFF, sum = 0
6368 04:50:49.552006 6, 0xFFFF, sum = 0
6369 04:50:49.552065 7, 0xFFFF, sum = 0
6370 04:50:49.552125 8, 0xFFFF, sum = 0
6371 04:50:49.552185 9, 0xFFFF, sum = 0
6372 04:50:49.552245 10, 0xFFFF, sum = 0
6373 04:50:49.552304 11, 0xFFFF, sum = 0
6374 04:50:49.552364 12, 0xFFFF, sum = 0
6375 04:50:49.552424 13, 0x0, sum = 1
6376 04:50:49.552484 14, 0x0, sum = 2
6377 04:50:49.552544 15, 0x0, sum = 3
6378 04:50:49.552605 16, 0x0, sum = 4
6379 04:50:49.552664 best_step = 14
6380 04:50:49.552722
6381 04:50:49.552780 ==
6382 04:50:49.552839 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 04:50:49.552899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 04:50:49.552958 ==
6385 04:50:49.553016 RX Vref Scan: 1
6386 04:50:49.553075
6387 04:50:49.553132 RX Vref 0 -> 0, step: 1
6388 04:50:49.553191
6389 04:50:49.553249 RX Delay -327 -> 252, step: 8
6390 04:50:49.553307
6391 04:50:49.553376 Set Vref, RX VrefLevel [Byte0]: 59
6392 04:50:49.553435 [Byte1]: 50
6393 04:50:49.553493
6394 04:50:49.553551 Final RX Vref Byte 0 = 59 to rank0
6395 04:50:49.553610 Final RX Vref Byte 1 = 50 to rank0
6396 04:50:49.553669 Final RX Vref Byte 0 = 59 to rank1
6397 04:50:49.553727 Final RX Vref Byte 1 = 50 to rank1==
6398 04:50:49.553786 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 04:50:49.553845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 04:50:49.553904 ==
6401 04:50:49.553975 DQS Delay:
6402 04:50:49.554035 DQS0 = 28, DQS1 = 48
6403 04:50:49.554094 DQM Delay:
6404 04:50:49.554153 DQM0 = 11, DQM1 = 15
6405 04:50:49.554211 DQ Delay:
6406 04:50:49.554270 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6407 04:50:49.554342 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =20
6408 04:50:49.554403 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =12
6409 04:50:49.554462 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6410 04:50:49.554520
6411 04:50:49.554589
6412 04:50:49.554642 [DQSOSCAuto] RK0, (LSB)MR18= 0xa8a0, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6413 04:50:49.554697 CH0 RK0: MR19=C0C, MR18=A8A0
6414 04:50:49.554751 CH0_RK0: MR19=0xC0C, MR18=0xA8A0, DQSOSC=388, MR23=63, INC=392, DEC=261
6415 04:50:49.554805 ==
6416 04:50:49.554858 Dram Type= 6, Freq= 0, CH_0, rank 1
6417 04:50:49.554912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 04:50:49.554966 ==
6419 04:50:49.555020 [Gating] SW mode calibration
6420 04:50:49.555074 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6421 04:50:49.555129 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6422 04:50:49.555183 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6423 04:50:49.555237 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 04:50:49.555290 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 04:50:49.555343 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 04:50:49.555397 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 04:50:49.555450 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 04:50:49.555503 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 04:50:49.555557 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 04:50:49.555611 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 04:50:49.555664 Total UI for P1: 0, mck2ui 16
6432 04:50:49.555718 best dqsien dly found for B0: ( 0, 14, 24)
6433 04:50:49.555772 Total UI for P1: 0, mck2ui 16
6434 04:50:49.555826 best dqsien dly found for B1: ( 0, 14, 24)
6435 04:50:49.555879 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6436 04:50:49.555933 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6437 04:50:49.555985
6438 04:50:49.556039 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6439 04:50:49.556092 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6440 04:50:49.556145 [Gating] SW calibration Done
6441 04:50:49.556198 ==
6442 04:50:49.556252 Dram Type= 6, Freq= 0, CH_0, rank 1
6443 04:50:49.556305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 04:50:49.556359 ==
6445 04:50:49.556412 RX Vref Scan: 0
6446 04:50:49.556465
6447 04:50:49.556518 RX Vref 0 -> 0, step: 1
6448 04:50:49.556571
6449 04:50:49.556624 RX Delay -410 -> 252, step: 16
6450 04:50:49.556677 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6451 04:50:49.556730 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6452 04:50:49.556784 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6453 04:50:49.556837 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6454 04:50:49.556890 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6455 04:50:49.556952 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6456 04:50:49.557006 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6457 04:50:49.557060 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6458 04:50:49.557115 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6459 04:50:49.557169 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6460 04:50:49.557222 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6461 04:50:49.557276 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6462 04:50:49.557330 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6463 04:50:49.557579 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6464 04:50:49.557641 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6465 04:50:49.557697 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6466 04:50:49.557751 ==
6467 04:50:49.557805 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 04:50:49.557860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 04:50:49.557914 ==
6470 04:50:49.557979 DQS Delay:
6471 04:50:49.558034 DQS0 = 27, DQS1 = 43
6472 04:50:49.558088 DQM Delay:
6473 04:50:49.558141 DQM0 = 9, DQM1 = 15
6474 04:50:49.558195 DQ Delay:
6475 04:50:49.558248 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6476 04:50:49.558302 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6477 04:50:49.558355 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6478 04:50:49.558409 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6479 04:50:49.558462
6480 04:50:49.558514
6481 04:50:49.558567 ==
6482 04:50:49.558620 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 04:50:49.558673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 04:50:49.558726 ==
6485 04:50:49.558780
6486 04:50:49.558833
6487 04:50:49.558885 TX Vref Scan disable
6488 04:50:49.558938 == TX Byte 0 ==
6489 04:50:49.558992 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6490 04:50:49.559045 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6491 04:50:49.559102 == TX Byte 1 ==
6492 04:50:49.559168 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6493 04:50:49.559222 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6494 04:50:49.559275 ==
6495 04:50:49.559328 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 04:50:49.559381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 04:50:49.559435 ==
6498 04:50:49.559488
6499 04:50:49.559541
6500 04:50:49.559606 TX Vref Scan disable
6501 04:50:49.559656 == TX Byte 0 ==
6502 04:50:49.559707 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6503 04:50:49.559758 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6504 04:50:49.559818 == TX Byte 1 ==
6505 04:50:49.559870 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6506 04:50:49.559921 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6507 04:50:49.559971
6508 04:50:49.560022 [DATLAT]
6509 04:50:49.560073 Freq=400, CH0 RK1
6510 04:50:49.560123
6511 04:50:49.560174 DATLAT Default: 0xe
6512 04:50:49.560225 0, 0xFFFF, sum = 0
6513 04:50:49.560277 1, 0xFFFF, sum = 0
6514 04:50:49.560328 2, 0xFFFF, sum = 0
6515 04:50:49.560379 3, 0xFFFF, sum = 0
6516 04:50:49.560430 4, 0xFFFF, sum = 0
6517 04:50:49.560481 5, 0xFFFF, sum = 0
6518 04:50:49.560533 6, 0xFFFF, sum = 0
6519 04:50:49.560584 7, 0xFFFF, sum = 0
6520 04:50:49.560635 8, 0xFFFF, sum = 0
6521 04:50:49.560686 9, 0xFFFF, sum = 0
6522 04:50:49.560738 10, 0xFFFF, sum = 0
6523 04:50:49.560789 11, 0xFFFF, sum = 0
6524 04:50:49.560841 12, 0xFFFF, sum = 0
6525 04:50:49.560892 13, 0x0, sum = 1
6526 04:50:49.560943 14, 0x0, sum = 2
6527 04:50:49.560995 15, 0x0, sum = 3
6528 04:50:49.561046 16, 0x0, sum = 4
6529 04:50:49.561102 best_step = 14
6530 04:50:49.561164
6531 04:50:49.561215 ==
6532 04:50:49.561266 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 04:50:49.561317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 04:50:49.561368 ==
6535 04:50:49.561419 RX Vref Scan: 0
6536 04:50:49.561469
6537 04:50:49.561520 RX Vref 0 -> 0, step: 1
6538 04:50:49.561571
6539 04:50:49.561620 RX Delay -327 -> 252, step: 8
6540 04:50:49.561671 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6541 04:50:49.561722 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6542 04:50:49.561773 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6543 04:50:49.561825 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6544 04:50:49.561875 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6545 04:50:49.561927 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6546 04:50:49.561984 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6547 04:50:49.562035 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6548 04:50:49.562086 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6549 04:50:49.562137 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6550 04:50:49.562188 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6551 04:50:49.562239 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6552 04:50:49.562289 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6553 04:50:49.562339 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6554 04:50:49.562390 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6555 04:50:49.562441 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6556 04:50:49.562491 ==
6557 04:50:49.562542 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 04:50:49.562593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 04:50:49.562644 ==
6560 04:50:49.562695 DQS Delay:
6561 04:50:49.562745 DQS0 = 24, DQS1 = 40
6562 04:50:49.562795 DQM Delay:
6563 04:50:49.562846 DQM0 = 6, DQM1 = 12
6564 04:50:49.562897 DQ Delay:
6565 04:50:49.562948 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =4
6566 04:50:49.562999 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =12
6567 04:50:49.563050 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6568 04:50:49.563103 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6569 04:50:49.563166
6570 04:50:49.563216
6571 04:50:49.563276 [DQSOSCAuto] RK1, (LSB)MR18= 0xb468, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6572 04:50:49.563329 CH0 RK1: MR19=C0C, MR18=B468
6573 04:50:49.563380 CH0_RK1: MR19=0xC0C, MR18=0xB468, DQSOSC=387, MR23=63, INC=394, DEC=262
6574 04:50:49.563432 [RxdqsGatingPostProcess] freq 400
6575 04:50:49.563483 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6576 04:50:49.563534 best DQS0 dly(2T, 0.5T) = (0, 10)
6577 04:50:49.563586 best DQS1 dly(2T, 0.5T) = (0, 10)
6578 04:50:49.563637 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6579 04:50:49.563687 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6580 04:50:49.563739 best DQS0 dly(2T, 0.5T) = (0, 10)
6581 04:50:49.563790 best DQS1 dly(2T, 0.5T) = (0, 10)
6582 04:50:49.563841 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6583 04:50:49.563892 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6584 04:50:49.563942 Pre-setting of DQS Precalculation
6585 04:50:49.563993 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6586 04:50:49.564044 ==
6587 04:50:49.564095 Dram Type= 6, Freq= 0, CH_1, rank 0
6588 04:50:49.564146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 04:50:49.564198 ==
6590 04:50:49.564248 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6591 04:50:49.564299 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6592 04:50:49.564350 [CA 0] Center 36 (8~64) winsize 57
6593 04:50:49.564401 [CA 1] Center 36 (8~64) winsize 57
6594 04:50:49.564451 [CA 2] Center 36 (8~64) winsize 57
6595 04:50:49.564502 [CA 3] Center 36 (8~64) winsize 57
6596 04:50:49.564552 [CA 4] Center 36 (8~64) winsize 57
6597 04:50:49.564603 [CA 5] Center 36 (8~64) winsize 57
6598 04:50:49.564653
6599 04:50:49.564704 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6600 04:50:49.564754
6601 04:50:49.564805 [CATrainingPosCal] consider 1 rank data
6602 04:50:49.564855 u2DelayCellTimex100 = 270/100 ps
6603 04:50:49.564906 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 04:50:49.565164 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 04:50:49.565225 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 04:50:49.565278 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 04:50:49.565330 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 04:50:49.565381 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 04:50:49.565432
6610 04:50:49.565483 CA PerBit enable=1, Macro0, CA PI delay=36
6611 04:50:49.565536
6612 04:50:49.565586 [CBTSetCACLKResult] CA Dly = 36
6613 04:50:49.565638 CS Dly: 1 (0~32)
6614 04:50:49.565688 ==
6615 04:50:49.565740 Dram Type= 6, Freq= 0, CH_1, rank 1
6616 04:50:49.565791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 04:50:49.565843 ==
6618 04:50:49.565894 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6619 04:50:49.565952 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6620 04:50:49.566042 [CA 0] Center 36 (8~64) winsize 57
6621 04:50:49.566093 [CA 1] Center 36 (8~64) winsize 57
6622 04:50:49.566144 [CA 2] Center 36 (8~64) winsize 57
6623 04:50:49.566194 [CA 3] Center 36 (8~64) winsize 57
6624 04:50:49.566245 [CA 4] Center 36 (8~64) winsize 57
6625 04:50:49.566296 [CA 5] Center 36 (8~64) winsize 57
6626 04:50:49.566346
6627 04:50:49.566397 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6628 04:50:49.566457
6629 04:50:49.566508 [CATrainingPosCal] consider 2 rank data
6630 04:50:49.566560 u2DelayCellTimex100 = 270/100 ps
6631 04:50:49.566611 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 04:50:49.566662 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 04:50:49.566713 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 04:50:49.566764 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 04:50:49.566814 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 04:50:49.566865 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 04:50:49.566915
6638 04:50:49.566971 CA PerBit enable=1, Macro0, CA PI delay=36
6639 04:50:49.567022
6640 04:50:49.567073 [CBTSetCACLKResult] CA Dly = 36
6641 04:50:49.567140 CS Dly: 1 (0~32)
6642 04:50:49.567193
6643 04:50:49.567243 ----->DramcWriteLeveling(PI) begin...
6644 04:50:49.567295 ==
6645 04:50:49.567346 Dram Type= 6, Freq= 0, CH_1, rank 0
6646 04:50:49.567397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 04:50:49.567449 ==
6648 04:50:49.567500 Write leveling (Byte 0): 40 => 8
6649 04:50:49.567551 Write leveling (Byte 1): 32 => 0
6650 04:50:49.567601 DramcWriteLeveling(PI) end<-----
6651 04:50:49.567652
6652 04:50:49.567702 ==
6653 04:50:49.567753 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 04:50:49.567803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 04:50:49.567854 ==
6656 04:50:49.567906 [Gating] SW mode calibration
6657 04:50:49.567956 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6658 04:50:49.568008 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6659 04:50:49.568060 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6660 04:50:49.568112 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6661 04:50:49.568163 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 04:50:49.568214 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 04:50:49.568265 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 04:50:49.568316 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 04:50:49.568367 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 04:50:49.568418 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 04:50:49.568469 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 04:50:49.568520 Total UI for P1: 0, mck2ui 16
6669 04:50:49.568571 best dqsien dly found for B0: ( 0, 14, 24)
6670 04:50:49.568622 Total UI for P1: 0, mck2ui 16
6671 04:50:49.568673 best dqsien dly found for B1: ( 0, 14, 24)
6672 04:50:49.568724 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6673 04:50:49.568776 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6674 04:50:49.568826
6675 04:50:49.568876 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6676 04:50:49.568927 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6677 04:50:49.568978 [Gating] SW calibration Done
6678 04:50:49.569028 ==
6679 04:50:49.569079 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 04:50:49.569148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 04:50:49.569200 ==
6682 04:50:49.569251 RX Vref Scan: 0
6683 04:50:49.569302
6684 04:50:49.569352 RX Vref 0 -> 0, step: 1
6685 04:50:49.569403
6686 04:50:49.569454 RX Delay -410 -> 252, step: 16
6687 04:50:49.569504 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6688 04:50:49.569556 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6689 04:50:49.569608 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6690 04:50:49.569665 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6691 04:50:49.569718 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6692 04:50:49.569769 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6693 04:50:49.569820 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6694 04:50:49.569871 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6695 04:50:49.569922 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6696 04:50:49.570004 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6697 04:50:49.570070 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6698 04:50:49.570120 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6699 04:50:49.570171 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6700 04:50:49.570222 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6701 04:50:49.570273 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6702 04:50:49.570324 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6703 04:50:49.570375 ==
6704 04:50:49.570425 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 04:50:49.570476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 04:50:49.570527 ==
6707 04:50:49.570577 DQS Delay:
6708 04:50:49.570628 DQS0 = 27, DQS1 = 43
6709 04:50:49.570678 DQM Delay:
6710 04:50:49.570729 DQM0 = 9, DQM1 = 19
6711 04:50:49.570779 DQ Delay:
6712 04:50:49.570830 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6713 04:50:49.570880 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6714 04:50:49.570931 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6715 04:50:49.570982 DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =32
6716 04:50:49.571033
6717 04:50:49.571088
6718 04:50:49.571150 ==
6719 04:50:49.571202 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 04:50:49.571253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 04:50:49.571305 ==
6722 04:50:49.571356
6723 04:50:49.571406
6724 04:50:49.571456 TX Vref Scan disable
6725 04:50:49.571506 == TX Byte 0 ==
6726 04:50:49.571557 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6727 04:50:49.571608 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6728 04:50:49.571659 == TX Byte 1 ==
6729 04:50:49.571709 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6730 04:50:49.571951 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6731 04:50:49.572008 ==
6732 04:50:49.572061 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 04:50:49.572113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 04:50:49.572165 ==
6735 04:50:49.572216
6736 04:50:49.572266
6737 04:50:49.572317 TX Vref Scan disable
6738 04:50:49.572369 == TX Byte 0 ==
6739 04:50:49.572419 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 04:50:49.572471 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 04:50:49.572521 == TX Byte 1 ==
6742 04:50:49.572572 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6743 04:50:49.572624 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6744 04:50:49.572675
6745 04:50:49.572725 [DATLAT]
6746 04:50:49.572776 Freq=400, CH1 RK0
6747 04:50:49.572827
6748 04:50:49.572877 DATLAT Default: 0xf
6749 04:50:49.572936 0, 0xFFFF, sum = 0
6750 04:50:49.572990 1, 0xFFFF, sum = 0
6751 04:50:49.573042 2, 0xFFFF, sum = 0
6752 04:50:49.573099 3, 0xFFFF, sum = 0
6753 04:50:49.573162 4, 0xFFFF, sum = 0
6754 04:50:49.573214 5, 0xFFFF, sum = 0
6755 04:50:49.573266 6, 0xFFFF, sum = 0
6756 04:50:49.573317 7, 0xFFFF, sum = 0
6757 04:50:49.573368 8, 0xFFFF, sum = 0
6758 04:50:49.573420 9, 0xFFFF, sum = 0
6759 04:50:49.573471 10, 0xFFFF, sum = 0
6760 04:50:49.573523 11, 0xFFFF, sum = 0
6761 04:50:49.573575 12, 0xFFFF, sum = 0
6762 04:50:49.573626 13, 0x0, sum = 1
6763 04:50:49.573678 14, 0x0, sum = 2
6764 04:50:49.573730 15, 0x0, sum = 3
6765 04:50:49.573781 16, 0x0, sum = 4
6766 04:50:49.573833 best_step = 14
6767 04:50:49.573884
6768 04:50:49.573934 ==
6769 04:50:49.574018 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 04:50:49.574083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 04:50:49.574135 ==
6772 04:50:49.574185 RX Vref Scan: 1
6773 04:50:49.574236
6774 04:50:49.574287 RX Vref 0 -> 0, step: 1
6775 04:50:49.574338
6776 04:50:49.574388 RX Delay -327 -> 252, step: 8
6777 04:50:49.574439
6778 04:50:49.574489 Set Vref, RX VrefLevel [Byte0]: 52
6779 04:50:49.574540 [Byte1]: 53
6780 04:50:49.574591
6781 04:50:49.574642 Final RX Vref Byte 0 = 52 to rank0
6782 04:50:49.574693 Final RX Vref Byte 1 = 53 to rank0
6783 04:50:49.574745 Final RX Vref Byte 0 = 52 to rank1
6784 04:50:49.574796 Final RX Vref Byte 1 = 53 to rank1==
6785 04:50:49.574848 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 04:50:49.574898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 04:50:49.574950 ==
6788 04:50:49.575001 DQS Delay:
6789 04:50:49.575052 DQS0 = 32, DQS1 = 40
6790 04:50:49.575107 DQM Delay:
6791 04:50:49.575171 DQM0 = 11, DQM1 = 13
6792 04:50:49.575222 DQ Delay:
6793 04:50:49.575273 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6794 04:50:49.575324 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6795 04:50:49.575374 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6796 04:50:49.575425 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =16
6797 04:50:49.575476
6798 04:50:49.575526
6799 04:50:49.575581 [DQSOSCAuto] RK0, (LSB)MR18= 0x90cb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6800 04:50:49.575633 CH1 RK0: MR19=C0C, MR18=90CB
6801 04:50:49.575684 CH1_RK0: MR19=0xC0C, MR18=0x90CB, DQSOSC=384, MR23=63, INC=400, DEC=267
6802 04:50:49.575745 ==
6803 04:50:49.575800 Dram Type= 6, Freq= 0, CH_1, rank 1
6804 04:50:49.575872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 04:50:49.575935 ==
6806 04:50:49.575997 [Gating] SW mode calibration
6807 04:50:49.576061 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6808 04:50:49.576123 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6809 04:50:49.576182 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6810 04:50:49.576246 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6811 04:50:49.576309 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 04:50:49.576371 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 04:50:49.576431 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 04:50:49.576487 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 04:50:49.576539 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 04:50:49.576591 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 04:50:49.576642 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 04:50:49.576693 Total UI for P1: 0, mck2ui 16
6819 04:50:49.576744 best dqsien dly found for B0: ( 0, 14, 24)
6820 04:50:49.576796 Total UI for P1: 0, mck2ui 16
6821 04:50:49.576849 best dqsien dly found for B1: ( 0, 14, 24)
6822 04:50:49.576900 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6823 04:50:49.576952 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6824 04:50:49.577003
6825 04:50:49.577061 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6826 04:50:49.577125 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6827 04:50:49.577177 [Gating] SW calibration Done
6828 04:50:49.577227 ==
6829 04:50:49.577278 Dram Type= 6, Freq= 0, CH_1, rank 1
6830 04:50:49.577329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 04:50:49.577380 ==
6832 04:50:49.577431 RX Vref Scan: 0
6833 04:50:49.577482
6834 04:50:49.577533 RX Vref 0 -> 0, step: 1
6835 04:50:49.577584
6836 04:50:49.577635 RX Delay -410 -> 252, step: 16
6837 04:50:49.577685 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6838 04:50:49.577737 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6839 04:50:49.577788 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6840 04:50:49.577839 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6841 04:50:49.577890 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6842 04:50:49.577944 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6843 04:50:49.578032 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6844 04:50:49.578083 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6845 04:50:49.578134 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6846 04:50:49.578184 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6847 04:50:49.578235 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6848 04:50:49.578286 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6849 04:50:49.578337 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6850 04:50:49.578387 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6851 04:50:49.578438 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6852 04:50:49.578489 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6853 04:50:49.578540 ==
6854 04:50:49.578591 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 04:50:49.578642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 04:50:49.578693 ==
6857 04:50:49.578744 DQS Delay:
6858 04:50:49.578795 DQS0 = 35, DQS1 = 43
6859 04:50:49.578846 DQM Delay:
6860 04:50:49.578898 DQM0 = 18, DQM1 = 18
6861 04:50:49.578949 DQ Delay:
6862 04:50:49.579003 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6863 04:50:49.579063 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6864 04:50:49.579164 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6865 04:50:49.579246 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6866 04:50:49.579335
6867 04:50:49.579416
6868 04:50:49.579496 ==
6869 04:50:49.579585 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 04:50:49.579860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 04:50:49.579946 ==
6872 04:50:49.580028
6873 04:50:49.580108
6874 04:50:49.580188 TX Vref Scan disable
6875 04:50:49.580268 == TX Byte 0 ==
6876 04:50:49.580349 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6877 04:50:49.580430 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6878 04:50:49.580511 == TX Byte 1 ==
6879 04:50:49.580592 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6880 04:50:49.580673 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6881 04:50:49.580756 ==
6882 04:50:49.580837 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 04:50:49.580918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 04:50:49.580999 ==
6885 04:50:49.581078
6886 04:50:49.581174
6887 04:50:49.581255 TX Vref Scan disable
6888 04:50:49.581335 == TX Byte 0 ==
6889 04:50:49.581415 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6890 04:50:49.581495 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6891 04:50:49.581575 == TX Byte 1 ==
6892 04:50:49.581656 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6893 04:50:49.581737 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6894 04:50:49.581816
6895 04:50:49.581896 [DATLAT]
6896 04:50:49.582002 Freq=400, CH1 RK1
6897 04:50:49.582069
6898 04:50:49.582120 DATLAT Default: 0xe
6899 04:50:49.582172 0, 0xFFFF, sum = 0
6900 04:50:49.582225 1, 0xFFFF, sum = 0
6901 04:50:49.582277 2, 0xFFFF, sum = 0
6902 04:50:49.582329 3, 0xFFFF, sum = 0
6903 04:50:49.582381 4, 0xFFFF, sum = 0
6904 04:50:49.582434 5, 0xFFFF, sum = 0
6905 04:50:49.582486 6, 0xFFFF, sum = 0
6906 04:50:49.582537 7, 0xFFFF, sum = 0
6907 04:50:49.582589 8, 0xFFFF, sum = 0
6908 04:50:49.582641 9, 0xFFFF, sum = 0
6909 04:50:49.582693 10, 0xFFFF, sum = 0
6910 04:50:49.582745 11, 0xFFFF, sum = 0
6911 04:50:49.582797 12, 0xFFFF, sum = 0
6912 04:50:49.582849 13, 0x0, sum = 1
6913 04:50:49.582901 14, 0x0, sum = 2
6914 04:50:49.582952 15, 0x0, sum = 3
6915 04:50:49.583003 16, 0x0, sum = 4
6916 04:50:49.583054 best_step = 14
6917 04:50:49.583108
6918 04:50:49.583174 ==
6919 04:50:49.583226 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 04:50:49.583277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 04:50:49.583328 ==
6922 04:50:49.583379 RX Vref Scan: 0
6923 04:50:49.583430
6924 04:50:49.583482 RX Vref 0 -> 0, step: 1
6925 04:50:49.583532
6926 04:50:49.583583 RX Delay -327 -> 252, step: 8
6927 04:50:49.583634 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6928 04:50:49.583685 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6929 04:50:49.583737 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6930 04:50:49.583787 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6931 04:50:49.583838 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6932 04:50:49.583889 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6933 04:50:49.583940 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6934 04:50:49.583992 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6935 04:50:49.584042 iDelay=217, Bit 8, Center -40 (-271 ~ 192) 464
6936 04:50:49.584093 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6937 04:50:49.584144 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6938 04:50:49.584195 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6939 04:50:49.584246 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6940 04:50:49.584297 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6941 04:50:49.584348 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6942 04:50:49.584399 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6943 04:50:50.008517 ==
6944 04:50:50.009042 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 04:50:50.009402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 04:50:50.009722 ==
6947 04:50:50.009793 DQS Delay:
6948 04:50:50.009847 DQS0 = 32, DQS1 = 40
6949 04:50:50.009900 DQM Delay:
6950 04:50:50.009992 DQM0 = 12, DQM1 = 14
6951 04:50:50.010058 DQ Delay:
6952 04:50:50.010110 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6953 04:50:50.010162 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =8
6954 04:50:50.010213 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6955 04:50:50.010264 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
6956 04:50:50.010315
6957 04:50:50.010366
6958 04:50:50.010416 [DQSOSCAuto] RK1, (LSB)MR18= 0xa953, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6959 04:50:50.010468 CH1 RK1: MR19=C0C, MR18=A953
6960 04:50:50.010572 CH1_RK1: MR19=0xC0C, MR18=0xA953, DQSOSC=388, MR23=63, INC=392, DEC=261
6961 04:50:50.010669 [RxdqsGatingPostProcess] freq 400
6962 04:50:50.010723 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6963 04:50:50.010775 best DQS0 dly(2T, 0.5T) = (0, 10)
6964 04:50:50.010826 best DQS1 dly(2T, 0.5T) = (0, 10)
6965 04:50:50.010877 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6966 04:50:50.010927 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6967 04:50:50.010978 best DQS0 dly(2T, 0.5T) = (0, 10)
6968 04:50:50.011028 best DQS1 dly(2T, 0.5T) = (0, 10)
6969 04:50:50.011078 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6970 04:50:50.011128 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6971 04:50:50.011178 Pre-setting of DQS Precalculation
6972 04:50:50.011229 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6973 04:50:50.011279 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6974 04:50:50.011331 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6975 04:50:50.011406
6976 04:50:50.011469
6977 04:50:50.011518 [Calibration Summary] 800 Mbps
6978 04:50:50.011568 CH 0, Rank 0
6979 04:50:50.011634 SW Impedance : PASS
6980 04:50:50.011710 DUTY Scan : NO K
6981 04:50:50.011802 ZQ Calibration : PASS
6982 04:50:50.011882 Jitter Meter : NO K
6983 04:50:50.011933 CBT Training : PASS
6984 04:50:50.011982 Write leveling : PASS
6985 04:50:50.012033 RX DQS gating : PASS
6986 04:50:50.012082 RX DQ/DQS(RDDQC) : PASS
6987 04:50:50.012132 TX DQ/DQS : PASS
6988 04:50:50.012183 RX DATLAT : PASS
6989 04:50:50.012232 RX DQ/DQS(Engine): PASS
6990 04:50:50.012282 TX OE : NO K
6991 04:50:50.012332 All Pass.
6992 04:50:50.012382
6993 04:50:50.012431 CH 0, Rank 1
6994 04:50:50.012481 SW Impedance : PASS
6995 04:50:50.012531 DUTY Scan : NO K
6996 04:50:50.012580 ZQ Calibration : PASS
6997 04:50:50.012630 Jitter Meter : NO K
6998 04:50:50.012680 CBT Training : PASS
6999 04:50:50.012729 Write leveling : NO K
7000 04:50:50.012779 RX DQS gating : PASS
7001 04:50:50.012829 RX DQ/DQS(RDDQC) : PASS
7002 04:50:50.012879 TX DQ/DQS : PASS
7003 04:50:50.012929 RX DATLAT : PASS
7004 04:50:50.012979 RX DQ/DQS(Engine): PASS
7005 04:50:50.013029 TX OE : NO K
7006 04:50:50.013079 All Pass.
7007 04:50:50.013129
7008 04:50:50.013178 CH 1, Rank 0
7009 04:50:50.013228 SW Impedance : PASS
7010 04:50:50.013278 DUTY Scan : NO K
7011 04:50:50.013328 ZQ Calibration : PASS
7012 04:50:50.013377 Jitter Meter : NO K
7013 04:50:50.013427 CBT Training : PASS
7014 04:50:50.013477 Write leveling : PASS
7015 04:50:50.013527 RX DQS gating : PASS
7016 04:50:50.013576 RX DQ/DQS(RDDQC) : PASS
7017 04:50:50.013872 TX DQ/DQS : PASS
7018 04:50:50.013932 RX DATLAT : PASS
7019 04:50:50.014025 RX DQ/DQS(Engine): PASS
7020 04:50:50.014077 TX OE : NO K
7021 04:50:50.014129 All Pass.
7022 04:50:50.014181
7023 04:50:50.014232 CH 1, Rank 1
7024 04:50:50.014283 SW Impedance : PASS
7025 04:50:50.014334 DUTY Scan : NO K
7026 04:50:50.014399 ZQ Calibration : PASS
7027 04:50:50.014449 Jitter Meter : NO K
7028 04:50:50.014498 CBT Training : PASS
7029 04:50:50.014548 Write leveling : NO K
7030 04:50:50.014598 RX DQS gating : PASS
7031 04:50:50.014648 RX DQ/DQS(RDDQC) : PASS
7032 04:50:50.014697 TX DQ/DQS : PASS
7033 04:50:50.014747 RX DATLAT : PASS
7034 04:50:50.014797 RX DQ/DQS(Engine): PASS
7035 04:50:50.014847 TX OE : NO K
7036 04:50:50.014897 All Pass.
7037 04:50:50.014947
7038 04:50:50.014997 DramC Write-DBI off
7039 04:50:50.015047 PER_BANK_REFRESH: Hybrid Mode
7040 04:50:50.015097 TX_TRACKING: ON
7041 04:50:50.015147 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7042 04:50:50.015198 [FAST_K] Save calibration result to emmc
7043 04:50:50.015248 dramc_set_vcore_voltage set vcore to 725000
7044 04:50:50.015298 Read voltage for 1600, 0
7045 04:50:50.015368 Vio18 = 0
7046 04:50:50.015432 Vcore = 725000
7047 04:50:50.015481 Vdram = 0
7048 04:50:50.015531 Vddq = 0
7049 04:50:50.015585 Vmddr = 0
7050 04:50:50.015662 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7051 04:50:50.015728 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7052 04:50:50.015780 MEM_TYPE=3, freq_sel=13
7053 04:50:50.015830 sv_algorithm_assistance_LP4_3733
7054 04:50:50.015881 ============ PULL DRAM RESETB DOWN ============
7055 04:50:50.015932 ========== PULL DRAM RESETB DOWN end =========
7056 04:50:50.015983 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7057 04:50:50.016034 ===================================
7058 04:50:50.016086 LPDDR4 DRAM CONFIGURATION
7059 04:50:50.016136 ===================================
7060 04:50:50.016187 EX_ROW_EN[0] = 0x0
7061 04:50:50.016237 EX_ROW_EN[1] = 0x0
7062 04:50:50.016288 LP4Y_EN = 0x0
7063 04:50:50.016339 WORK_FSP = 0x1
7064 04:50:50.016390 WL = 0x5
7065 04:50:50.016441 RL = 0x5
7066 04:50:50.016492 BL = 0x2
7067 04:50:50.016543 RPST = 0x0
7068 04:50:50.016595 RD_PRE = 0x0
7069 04:50:50.016646 WR_PRE = 0x1
7070 04:50:50.016697 WR_PST = 0x1
7071 04:50:50.016748 DBI_WR = 0x0
7072 04:50:50.016799 DBI_RD = 0x0
7073 04:50:50.016851 OTF = 0x1
7074 04:50:50.016903 ===================================
7075 04:50:50.016955 ===================================
7076 04:50:50.017006 ANA top config
7077 04:50:50.017057 ===================================
7078 04:50:50.017109 DLL_ASYNC_EN = 0
7079 04:50:50.017160 ALL_SLAVE_EN = 0
7080 04:50:50.017250 NEW_RANK_MODE = 1
7081 04:50:50.017303 DLL_IDLE_MODE = 1
7082 04:50:50.017356 LP45_APHY_COMB_EN = 1
7083 04:50:50.017426 TX_ODT_DIS = 0
7084 04:50:50.017490 NEW_8X_MODE = 1
7085 04:50:50.017541 ===================================
7086 04:50:50.017596 ===================================
7087 04:50:50.017682 data_rate = 3200
7088 04:50:50.017765 CKR = 1
7089 04:50:50.017818 DQ_P2S_RATIO = 8
7090 04:50:50.017871 ===================================
7091 04:50:50.017923 CA_P2S_RATIO = 8
7092 04:50:50.018031 DQ_CA_OPEN = 0
7093 04:50:50.018084 DQ_SEMI_OPEN = 0
7094 04:50:50.018135 CA_SEMI_OPEN = 0
7095 04:50:50.018186 CA_FULL_RATE = 0
7096 04:50:50.018237 DQ_CKDIV4_EN = 0
7097 04:50:50.018289 CA_CKDIV4_EN = 0
7098 04:50:50.018341 CA_PREDIV_EN = 0
7099 04:50:50.018393 PH8_DLY = 12
7100 04:50:50.018444 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7101 04:50:50.018496 DQ_AAMCK_DIV = 4
7102 04:50:50.018548 CA_AAMCK_DIV = 4
7103 04:50:50.018599 CA_ADMCK_DIV = 4
7104 04:50:50.018650 DQ_TRACK_CA_EN = 0
7105 04:50:50.018701 CA_PICK = 1600
7106 04:50:50.018753 CA_MCKIO = 1600
7107 04:50:50.018804 MCKIO_SEMI = 0
7108 04:50:50.018856 PLL_FREQ = 3068
7109 04:50:50.018907 DQ_UI_PI_RATIO = 32
7110 04:50:50.018958 CA_UI_PI_RATIO = 0
7111 04:50:50.019009 ===================================
7112 04:50:50.019061 ===================================
7113 04:50:50.019112 memory_type:LPDDR4
7114 04:50:50.019164 GP_NUM : 10
7115 04:50:50.019216 SRAM_EN : 1
7116 04:50:50.019268 MD32_EN : 0
7117 04:50:50.019319 ===================================
7118 04:50:50.019371 [ANA_INIT] >>>>>>>>>>>>>>
7119 04:50:50.019423 <<<<<< [CONFIGURE PHASE]: ANA_TX
7120 04:50:50.019475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7121 04:50:50.019526 ===================================
7122 04:50:50.019578 data_rate = 3200,PCW = 0X7600
7123 04:50:50.019645 ===================================
7124 04:50:50.019736 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7125 04:50:50.019787 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7126 04:50:50.019840 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7127 04:50:50.019892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7128 04:50:50.019944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7129 04:50:50.019996 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7130 04:50:50.020048 [ANA_INIT] flow start
7131 04:50:50.020099 [ANA_INIT] PLL >>>>>>>>
7132 04:50:50.020151 [ANA_INIT] PLL <<<<<<<<
7133 04:50:50.020202 [ANA_INIT] MIDPI >>>>>>>>
7134 04:50:50.020253 [ANA_INIT] MIDPI <<<<<<<<
7135 04:50:50.020305 [ANA_INIT] DLL >>>>>>>>
7136 04:50:50.020357 [ANA_INIT] DLL <<<<<<<<
7137 04:50:50.020408 [ANA_INIT] flow end
7138 04:50:50.020460 ============ LP4 DIFF to SE enter ============
7139 04:50:50.020512 ============ LP4 DIFF to SE exit ============
7140 04:50:50.020573 [ANA_INIT] <<<<<<<<<<<<<
7141 04:50:50.020654 [Flow] Enable top DCM control >>>>>
7142 04:50:50.020706 [Flow] Enable top DCM control <<<<<
7143 04:50:50.020758 Enable DLL master slave shuffle
7144 04:50:50.020809 ==============================================================
7145 04:50:50.020861 Gating Mode config
7146 04:50:50.020912 ==============================================================
7147 04:50:50.020964 Config description:
7148 04:50:50.021211 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7149 04:50:50.021303 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7150 04:50:50.021358 SELPH_MODE 0: By rank 1: By Phase
7151 04:50:50.021411 ==============================================================
7152 04:50:50.021464 GAT_TRACK_EN = 1
7153 04:50:50.021516 RX_GATING_MODE = 2
7154 04:50:50.021567 RX_GATING_TRACK_MODE = 2
7155 04:50:50.021631 SELPH_MODE = 1
7156 04:50:50.021739 PICG_EARLY_EN = 1
7157 04:50:50.021791 VALID_LAT_VALUE = 1
7158 04:50:50.021857 ==============================================================
7159 04:50:50.021910 Enter into Gating configuration >>>>
7160 04:50:50.021986 Exit from Gating configuration <<<<
7161 04:50:50.022053 Enter into DVFS_PRE_config >>>>>
7162 04:50:50.022106 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7163 04:50:50.022159 Exit from DVFS_PRE_config <<<<<
7164 04:50:50.022211 Enter into PICG configuration >>>>
7165 04:50:50.022263 Exit from PICG configuration <<<<
7166 04:50:50.022315 [RX_INPUT] configuration >>>>>
7167 04:50:50.022367 [RX_INPUT] configuration <<<<<
7168 04:50:50.022418 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7169 04:50:50.022471 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7170 04:50:50.022523 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7171 04:50:50.022575 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7172 04:50:50.022627 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7173 04:50:50.022679 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7174 04:50:50.022731 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7175 04:50:50.022783 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7176 04:50:50.022834 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7177 04:50:50.022886 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7178 04:50:50.022938 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7179 04:50:50.022989 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7180 04:50:50.023041 ===================================
7181 04:50:50.023093 LPDDR4 DRAM CONFIGURATION
7182 04:50:50.023145 ===================================
7183 04:50:50.023197 EX_ROW_EN[0] = 0x0
7184 04:50:50.023249 EX_ROW_EN[1] = 0x0
7185 04:50:50.023300 LP4Y_EN = 0x0
7186 04:50:50.023352 WORK_FSP = 0x1
7187 04:50:50.023403 WL = 0x5
7188 04:50:50.023454 RL = 0x5
7189 04:50:50.023505 BL = 0x2
7190 04:50:50.023556 RPST = 0x0
7191 04:50:50.023612 RD_PRE = 0x0
7192 04:50:50.023691 WR_PRE = 0x1
7193 04:50:50.023785 WR_PST = 0x1
7194 04:50:50.023882 DBI_WR = 0x0
7195 04:50:50.023947 DBI_RD = 0x0
7196 04:50:50.023997 OTF = 0x1
7197 04:50:50.024048 ===================================
7198 04:50:50.024099 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7199 04:50:50.024157 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7200 04:50:50.024226 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7201 04:50:50.024293 ===================================
7202 04:50:50.024343 LPDDR4 DRAM CONFIGURATION
7203 04:50:50.024395 ===================================
7204 04:50:50.024446 EX_ROW_EN[0] = 0x10
7205 04:50:50.024498 EX_ROW_EN[1] = 0x0
7206 04:50:50.024549 LP4Y_EN = 0x0
7207 04:50:50.024600 WORK_FSP = 0x1
7208 04:50:50.024651 WL = 0x5
7209 04:50:50.024702 RL = 0x5
7210 04:50:50.024753 BL = 0x2
7211 04:50:50.024804 RPST = 0x0
7212 04:50:50.024855 RD_PRE = 0x0
7213 04:50:50.024906 WR_PRE = 0x1
7214 04:50:50.024957 WR_PST = 0x1
7215 04:50:50.025008 DBI_WR = 0x0
7216 04:50:50.025059 DBI_RD = 0x0
7217 04:50:50.025110 OTF = 0x1
7218 04:50:50.025161 ===================================
7219 04:50:50.025213 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7220 04:50:50.025264 ==
7221 04:50:50.025316 Dram Type= 6, Freq= 0, CH_0, rank 0
7222 04:50:50.025368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7223 04:50:50.025420 ==
7224 04:50:50.025471 [Duty_Offset_Calibration]
7225 04:50:50.025539 B0:2 B1:0 CA:1
7226 04:50:50.025607
7227 04:50:50.025685 [DutyScan_Calibration_Flow] k_type=0
7228 04:50:50.025750
7229 04:50:50.025801 ==CLK 0==
7230 04:50:50.025852 Final CLK duty delay cell = -4
7231 04:50:50.025904 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7232 04:50:50.025980 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7233 04:50:50.026061 [-4] AVG Duty = 4906%(X100)
7234 04:50:50.026112
7235 04:50:50.026163 CH0 CLK Duty spec in!! Max-Min= 187%
7236 04:50:50.026215 [DutyScan_Calibration_Flow] ====Done====
7237 04:50:50.026267
7238 04:50:50.026318 [DutyScan_Calibration_Flow] k_type=1
7239 04:50:50.026369
7240 04:50:50.026420 ==DQS 0 ==
7241 04:50:50.026472 Final DQS duty delay cell = 0
7242 04:50:50.026524 [0] MAX Duty = 5249%(X100), DQS PI = 32
7243 04:50:50.026576 [0] MIN Duty = 4969%(X100), DQS PI = 0
7244 04:50:50.026627 [0] AVG Duty = 5109%(X100)
7245 04:50:50.026678
7246 04:50:50.026729 ==DQS 1 ==
7247 04:50:50.026781 Final DQS duty delay cell = -4
7248 04:50:50.026832 [-4] MAX Duty = 5125%(X100), DQS PI = 44
7249 04:50:50.026884 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7250 04:50:50.026935 [-4] AVG Duty = 5000%(X100)
7251 04:50:50.026986
7252 04:50:50.027037 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7253 04:50:50.027088
7254 04:50:50.027161 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7255 04:50:50.027228 [DutyScan_Calibration_Flow] ====Done====
7256 04:50:50.027280
7257 04:50:50.027331 [DutyScan_Calibration_Flow] k_type=3
7258 04:50:50.027382
7259 04:50:50.027434 ==DQM 0 ==
7260 04:50:50.027514 Final DQM duty delay cell = 0
7261 04:50:50.027566 [0] MAX Duty = 5093%(X100), DQS PI = 26
7262 04:50:50.027647 [0] MIN Duty = 4813%(X100), DQS PI = 52
7263 04:50:50.027716 [0] AVG Duty = 4953%(X100)
7264 04:50:50.027768
7265 04:50:50.027819 ==DQM 1 ==
7266 04:50:50.027870 Final DQM duty delay cell = 0
7267 04:50:50.027922 [0] MAX Duty = 5249%(X100), DQS PI = 30
7268 04:50:50.027975 [0] MIN Duty = 5031%(X100), DQS PI = 10
7269 04:50:50.028026 [0] AVG Duty = 5140%(X100)
7270 04:50:50.028077
7271 04:50:50.028128 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7272 04:50:50.028179
7273 04:50:50.028231 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7274 04:50:50.028282 [DutyScan_Calibration_Flow] ====Done====
7275 04:50:50.028333
7276 04:50:50.028575 [DutyScan_Calibration_Flow] k_type=2
7277 04:50:50.028633
7278 04:50:50.028685 ==DQ 0 ==
7279 04:50:50.028737 Final DQ duty delay cell = 0
7280 04:50:50.028789 [0] MAX Duty = 5124%(X100), DQS PI = 32
7281 04:50:50.028841 [0] MIN Duty = 5000%(X100), DQS PI = 0
7282 04:50:50.028892 [0] AVG Duty = 5062%(X100)
7283 04:50:50.028944
7284 04:50:50.028995 ==DQ 1 ==
7285 04:50:50.029047 Final DQ duty delay cell = 0
7286 04:50:50.029098 [0] MAX Duty = 4969%(X100), DQS PI = 42
7287 04:50:50.029150 [0] MIN Duty = 4875%(X100), DQS PI = 0
7288 04:50:50.029201 [0] AVG Duty = 4922%(X100)
7289 04:50:50.029253
7290 04:50:50.029303 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7291 04:50:50.029355
7292 04:50:50.029406 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7293 04:50:50.029457 [DutyScan_Calibration_Flow] ====Done====
7294 04:50:50.029508 ==
7295 04:50:50.029557 Dram Type= 6, Freq= 0, CH_1, rank 0
7296 04:50:50.029611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7297 04:50:50.029711 ==
7298 04:50:50.029803 [Duty_Offset_Calibration]
7299 04:50:50.029854 B0:0 B1:-1 CA:2
7300 04:50:50.029904
7301 04:50:50.029992 [DutyScan_Calibration_Flow] k_type=0
7302 04:50:50.030057
7303 04:50:50.030107 ==CLK 0==
7304 04:50:50.030157 Final CLK duty delay cell = 0
7305 04:50:50.030207 [0] MAX Duty = 5156%(X100), DQS PI = 10
7306 04:50:50.030257 [0] MIN Duty = 4906%(X100), DQS PI = 46
7307 04:50:50.030307 [0] AVG Duty = 5031%(X100)
7308 04:50:50.030356
7309 04:50:50.030415 CH1 CLK Duty spec in!! Max-Min= 250%
7310 04:50:50.030465 [DutyScan_Calibration_Flow] ====Done====
7311 04:50:50.030515
7312 04:50:50.030564 [DutyScan_Calibration_Flow] k_type=1
7313 04:50:50.030614
7314 04:50:50.030663 ==DQS 0 ==
7315 04:50:50.030713 Final DQS duty delay cell = 0
7316 04:50:50.030764 [0] MAX Duty = 5093%(X100), DQS PI = 24
7317 04:50:50.030813 [0] MIN Duty = 4969%(X100), DQS PI = 0
7318 04:50:50.030863 [0] AVG Duty = 5031%(X100)
7319 04:50:50.030913
7320 04:50:50.030963 ==DQS 1 ==
7321 04:50:50.031013 Final DQS duty delay cell = 0
7322 04:50:50.031064 [0] MAX Duty = 5187%(X100), DQS PI = 2
7323 04:50:50.031114 [0] MIN Duty = 4844%(X100), DQS PI = 34
7324 04:50:50.031163 [0] AVG Duty = 5015%(X100)
7325 04:50:50.031213
7326 04:50:50.031263 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7327 04:50:50.031313
7328 04:50:50.031362 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7329 04:50:50.031412 [DutyScan_Calibration_Flow] ====Done====
7330 04:50:50.031465
7331 04:50:50.031516 [DutyScan_Calibration_Flow] k_type=3
7332 04:50:50.031566
7333 04:50:50.031620 ==DQM 0 ==
7334 04:50:50.031742 Final DQM duty delay cell = 4
7335 04:50:50.031805 [4] MAX Duty = 5125%(X100), DQS PI = 10
7336 04:50:50.031855 [4] MIN Duty = 5000%(X100), DQS PI = 32
7337 04:50:50.031906 [4] AVG Duty = 5062%(X100)
7338 04:50:50.031956
7339 04:50:50.032005 ==DQM 1 ==
7340 04:50:50.032055 Final DQM duty delay cell = 0
7341 04:50:50.032105 [0] MAX Duty = 5281%(X100), DQS PI = 60
7342 04:50:50.032155 [0] MIN Duty = 4844%(X100), DQS PI = 34
7343 04:50:50.032204 [0] AVG Duty = 5062%(X100)
7344 04:50:50.032253
7345 04:50:50.032303 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7346 04:50:50.032353
7347 04:50:50.032402 CH1 DQM 1 Duty spec in!! Max-Min= 437%
7348 04:50:50.032452 [DutyScan_Calibration_Flow] ====Done====
7349 04:50:50.032502
7350 04:50:50.032551 [DutyScan_Calibration_Flow] k_type=2
7351 04:50:50.032601
7352 04:50:50.032651 ==DQ 0 ==
7353 04:50:50.032700 Final DQ duty delay cell = 0
7354 04:50:50.032751 [0] MAX Duty = 5093%(X100), DQS PI = 20
7355 04:50:50.032801 [0] MIN Duty = 4969%(X100), DQS PI = 46
7356 04:50:50.032851 [0] AVG Duty = 5031%(X100)
7357 04:50:50.032900
7358 04:50:50.032950 ==DQ 1 ==
7359 04:50:50.032999 Final DQ duty delay cell = 0
7360 04:50:50.033049 [0] MAX Duty = 5062%(X100), DQS PI = 2
7361 04:50:50.033099 [0] MIN Duty = 4813%(X100), DQS PI = 34
7362 04:50:50.033149 [0] AVG Duty = 4937%(X100)
7363 04:50:50.033198
7364 04:50:50.033247 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7365 04:50:50.033297
7366 04:50:50.033346 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7367 04:50:50.033396 [DutyScan_Calibration_Flow] ====Done====
7368 04:50:50.033447 nWR fixed to 30
7369 04:50:50.033497 [ModeRegInit_LP4] CH0 RK0
7370 04:50:50.033547 [ModeRegInit_LP4] CH0 RK1
7371 04:50:50.033600 [ModeRegInit_LP4] CH1 RK0
7372 04:50:50.033680 [ModeRegInit_LP4] CH1 RK1
7373 04:50:50.033743 match AC timing 5
7374 04:50:50.033793 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7375 04:50:50.033844 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7376 04:50:50.033894 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7377 04:50:50.033974 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7378 04:50:50.034055 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7379 04:50:50.034106 [MiockJmeterHQA]
7380 04:50:50.034164
7381 04:50:50.034215 [DramcMiockJmeter] u1RxGatingPI = 0
7382 04:50:50.034265 0 : 4252, 4026
7383 04:50:50.034316 4 : 4368, 4140
7384 04:50:50.034367 8 : 4257, 4030
7385 04:50:50.034419 12 : 4252, 4027
7386 04:50:50.034470 16 : 4253, 4027
7387 04:50:50.034521 20 : 4252, 4027
7388 04:50:50.034571 24 : 4255, 4029
7389 04:50:50.034622 28 : 4253, 4027
7390 04:50:50.034673 32 : 4252, 4027
7391 04:50:50.034723 36 : 4365, 4140
7392 04:50:50.034773 40 : 4252, 4026
7393 04:50:50.034824 44 : 4255, 4029
7394 04:50:50.034875 48 : 4253, 4027
7395 04:50:50.034925 52 : 4361, 4138
7396 04:50:50.034975 56 : 4250, 4027
7397 04:50:50.035025 60 : 4360, 4137
7398 04:50:50.035076 64 : 4250, 4027
7399 04:50:50.035126 68 : 4250, 4027
7400 04:50:50.035177 72 : 4252, 4027
7401 04:50:50.035227 76 : 4252, 4029
7402 04:50:50.035278 80 : 4360, 4138
7403 04:50:50.035328 84 : 4249, 4027
7404 04:50:50.035379 88 : 4360, 3978
7405 04:50:50.035430 92 : 4250, 0
7406 04:50:50.035481 96 : 4250, 0
7407 04:50:50.035531 100 : 4250, 0
7408 04:50:50.035586 104 : 4250, 0
7409 04:50:50.035663 108 : 4252, 0
7410 04:50:50.035728 112 : 4250, 0
7411 04:50:50.035778 116 : 4252, 0
7412 04:50:50.035829 120 : 4361, 0
7413 04:50:50.035879 124 : 4250, 0
7414 04:50:50.035929 128 : 4250, 0
7415 04:50:50.035979 132 : 4360, 0
7416 04:50:50.036029 136 : 4361, 0
7417 04:50:50.036079 140 : 4363, 0
7418 04:50:50.036129 144 : 4250, 0
7419 04:50:50.036180 148 : 4361, 0
7420 04:50:50.036230 152 : 4250, 0
7421 04:50:50.036280 156 : 4250, 0
7422 04:50:50.036331 160 : 4249, 0
7423 04:50:50.036381 164 : 4250, 0
7424 04:50:50.036433 168 : 4252, 0
7425 04:50:50.036484 172 : 4361, 0
7426 04:50:50.036534 176 : 4250, 0
7427 04:50:50.036584 180 : 4250, 0
7428 04:50:50.036634 184 : 4360, 0
7429 04:50:50.036684 188 : 4360, 0
7430 04:50:50.036735 192 : 4250, 0
7431 04:50:50.036785 196 : 4250, 0
7432 04:50:50.036836 200 : 4250, 0
7433 04:50:50.036886 204 : 4250, 2089
7434 04:50:50.036936 208 : 4361, 4137
7435 04:50:50.036987 212 : 4362, 4140
7436 04:50:50.037037 216 : 4250, 4027
7437 04:50:50.037088 220 : 4363, 4140
7438 04:50:50.037138 224 : 4250, 4027
7439 04:50:50.037197 228 : 4250, 4027
7440 04:50:50.037248 232 : 4249, 4027
7441 04:50:50.037298 236 : 4252, 4030
7442 04:50:50.037348 240 : 4249, 4027
7443 04:50:50.037399 244 : 4250, 4026
7444 04:50:50.037449 248 : 4250, 4027
7445 04:50:50.037500 252 : 4252, 4030
7446 04:50:50.037550 256 : 4250, 4027
7447 04:50:50.037606 260 : 4361, 4137
7448 04:50:50.037670 264 : 4361, 4137
7449 04:50:50.037764 268 : 4250, 4027
7450 04:50:50.037829 272 : 4363, 4140
7451 04:50:50.037880 276 : 4250, 4027
7452 04:50:50.037930 280 : 4250, 4027
7453 04:50:50.038017 284 : 4252, 4027
7454 04:50:50.038069 288 : 4252, 4029
7455 04:50:50.038119 292 : 4250, 4027
7456 04:50:50.038169 296 : 4250, 4027
7457 04:50:50.038220 300 : 4252, 4027
7458 04:50:50.038271 304 : 4252, 4029
7459 04:50:50.038321 308 : 4250, 4027
7460 04:50:50.038372 312 : 4361, 4077
7461 04:50:50.038423 316 : 4361, 2311
7462 04:50:50.038473 320 : 4250, 24
7463 04:50:50.038523
7464 04:50:50.038765 MIOCK jitter meter ch=0
7465 04:50:50.038821
7466 04:50:50.038873 1T = (320-92) = 228 dly cells
7467 04:50:50.038924 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7468 04:50:50.038975 ==
7469 04:50:50.039042 Dram Type= 6, Freq= 0, CH_0, rank 0
7470 04:50:50.039105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7471 04:50:50.039156 ==
7472 04:50:50.039207 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7473 04:50:50.039257 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7474 04:50:50.039308 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7475 04:50:50.039358 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7476 04:50:50.039408 [CA 0] Center 43 (13~73) winsize 61
7477 04:50:50.039458 [CA 1] Center 43 (13~73) winsize 61
7478 04:50:50.039508 [CA 2] Center 38 (8~68) winsize 61
7479 04:50:50.039558 [CA 3] Center 37 (8~67) winsize 60
7480 04:50:50.039608 [CA 4] Center 36 (6~66) winsize 61
7481 04:50:50.039658 [CA 5] Center 35 (5~66) winsize 62
7482 04:50:50.039708
7483 04:50:50.039757 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7484 04:50:50.039807
7485 04:50:50.039856 [CATrainingPosCal] consider 1 rank data
7486 04:50:50.039906 u2DelayCellTimex100 = 285/100 ps
7487 04:50:50.039955 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7488 04:50:50.040005 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7489 04:50:50.040055 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7490 04:50:50.040105 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7491 04:50:50.040155 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7492 04:50:50.040204 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7493 04:50:50.040254
7494 04:50:50.040303 CA PerBit enable=1, Macro0, CA PI delay=35
7495 04:50:50.040353
7496 04:50:50.040402 [CBTSetCACLKResult] CA Dly = 35
7497 04:50:50.040461 CS Dly: 9 (0~40)
7498 04:50:50.040512 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7499 04:50:50.040563 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7500 04:50:50.040613 ==
7501 04:50:50.040664 Dram Type= 6, Freq= 0, CH_0, rank 1
7502 04:50:50.040714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7503 04:50:50.040765 ==
7504 04:50:50.040815 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7505 04:50:50.040865 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7506 04:50:50.040915 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7507 04:50:50.040965 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7508 04:50:50.041017 [CA 0] Center 43 (13~74) winsize 62
7509 04:50:50.041066 [CA 1] Center 43 (13~73) winsize 61
7510 04:50:50.041116 [CA 2] Center 38 (9~68) winsize 60
7511 04:50:50.041165 [CA 3] Center 38 (9~68) winsize 60
7512 04:50:50.041215 [CA 4] Center 36 (7~66) winsize 60
7513 04:50:50.041264 [CA 5] Center 36 (6~66) winsize 61
7514 04:50:50.041313
7515 04:50:50.041363 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7516 04:50:50.041412
7517 04:50:50.041462 [CATrainingPosCal] consider 2 rank data
7518 04:50:50.041512 u2DelayCellTimex100 = 285/100 ps
7519 04:50:50.041561 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7520 04:50:50.041611 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7521 04:50:50.041661 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7522 04:50:50.041711 CA3 delay=38 (9~67),Diff = 2 PI (6 cell)
7523 04:50:50.041761 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7524 04:50:50.041811 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7525 04:50:50.041861
7526 04:50:50.041911 CA PerBit enable=1, Macro0, CA PI delay=36
7527 04:50:50.041987
7528 04:50:50.042051 [CBTSetCACLKResult] CA Dly = 36
7529 04:50:50.042101 CS Dly: 10 (0~43)
7530 04:50:50.042150 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7531 04:50:50.042200 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7532 04:50:50.042250
7533 04:50:50.042299 ----->DramcWriteLeveling(PI) begin...
7534 04:50:50.042350 ==
7535 04:50:50.042400 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 04:50:50.042450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 04:50:50.042501 ==
7538 04:50:50.042551 Write leveling (Byte 0): 38 => 38
7539 04:50:50.042601 Write leveling (Byte 1): 30 => 30
7540 04:50:50.042651 DramcWriteLeveling(PI) end<-----
7541 04:50:50.042701
7542 04:50:50.042751 ==
7543 04:50:50.042800 Dram Type= 6, Freq= 0, CH_0, rank 0
7544 04:50:50.042850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7545 04:50:50.042900 ==
7546 04:50:50.042950 [Gating] SW mode calibration
7547 04:50:50.043000 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7548 04:50:50.043051 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7549 04:50:50.043101 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 04:50:50.043152 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 04:50:50.043202 1 4 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7552 04:50:50.043252 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7553 04:50:50.043302 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7554 04:50:50.043352 1 4 20 | B1->B0 | 3332 3434 | 1 1 | (0 0) (1 1)
7555 04:50:50.043401 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7556 04:50:50.043451 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7557 04:50:50.043501 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 04:50:50.043551 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 04:50:50.043609 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
7560 04:50:50.043660 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7561 04:50:50.043710 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7562 04:50:50.043760 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
7563 04:50:50.043810 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7564 04:50:50.043860 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 04:50:50.043910 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 04:50:50.043960 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7567 04:50:50.044010 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7568 04:50:50.044061 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7569 04:50:50.044111 1 6 16 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7570 04:50:50.044161 1 6 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7571 04:50:50.044211 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 04:50:50.044260 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 04:50:50.044501 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 04:50:50.044567 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 04:50:50.044623 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 04:50:50.044674 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7577 04:50:50.044725 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7578 04:50:50.044775 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7579 04:50:50.044826 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 04:50:50.044876 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 04:50:50.044927 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 04:50:50.044978 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 04:50:50.045047 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 04:50:50.045110 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 04:50:50.045168 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 04:50:50.045223 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 04:50:50.045283 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 04:50:50.045340 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 04:50:50.045394 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 04:50:50.045445 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 04:50:50.045495 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7592 04:50:50.045546 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7593 04:50:50.045596 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7594 04:50:50.045646 Total UI for P1: 0, mck2ui 16
7595 04:50:50.045696 best dqsien dly found for B0: ( 1, 9, 10)
7596 04:50:50.045746 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7597 04:50:50.045797 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7598 04:50:50.045847 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 04:50:50.045897 Total UI for P1: 0, mck2ui 16
7600 04:50:50.045983 best dqsien dly found for B1: ( 1, 9, 20)
7601 04:50:50.046049 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7602 04:50:50.046100 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7603 04:50:50.046150
7604 04:50:50.046200 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7605 04:50:50.046250 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7606 04:50:50.046300 [Gating] SW calibration Done
7607 04:50:50.046350 ==
7608 04:50:50.046400 Dram Type= 6, Freq= 0, CH_0, rank 0
7609 04:50:50.046450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7610 04:50:50.046500 ==
7611 04:50:50.046550 RX Vref Scan: 0
7612 04:50:50.046600
7613 04:50:50.046650 RX Vref 0 -> 0, step: 1
7614 04:50:50.046699
7615 04:50:50.046748 RX Delay 0 -> 252, step: 8
7616 04:50:50.046798 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7617 04:50:50.046848 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7618 04:50:50.046899 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7619 04:50:50.046949 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7620 04:50:50.046998 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7621 04:50:50.047047 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7622 04:50:50.047097 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7623 04:50:50.047147 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7624 04:50:50.047196 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7625 04:50:50.047245 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7626 04:50:50.047295 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7627 04:50:50.047345 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7628 04:50:50.047394 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7629 04:50:50.047454 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7630 04:50:50.047504 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7631 04:50:50.047554 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7632 04:50:50.047603 ==
7633 04:50:50.047654 Dram Type= 6, Freq= 0, CH_0, rank 0
7634 04:50:50.047704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7635 04:50:50.047755 ==
7636 04:50:50.047805 DQS Delay:
7637 04:50:50.047856 DQS0 = 0, DQS1 = 0
7638 04:50:50.047906 DQM Delay:
7639 04:50:50.047955 DQM0 = 137, DQM1 = 126
7640 04:50:50.048005 DQ Delay:
7641 04:50:50.048055 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7642 04:50:50.048105 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7643 04:50:50.048155 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7644 04:50:50.048204 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7645 04:50:50.048255
7646 04:50:50.048304
7647 04:50:50.048354 ==
7648 04:50:50.048404 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 04:50:50.048454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 04:50:50.048505 ==
7651 04:50:50.048554
7652 04:50:50.048604
7653 04:50:50.048654 TX Vref Scan disable
7654 04:50:50.048703 == TX Byte 0 ==
7655 04:50:50.048753 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7656 04:50:50.048804 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7657 04:50:50.048854 == TX Byte 1 ==
7658 04:50:50.048905 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7659 04:50:50.048956 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7660 04:50:50.049006 ==
7661 04:50:50.049056 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 04:50:50.049106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 04:50:50.049157 ==
7664 04:50:50.049207
7665 04:50:50.049257 TX Vref early break, caculate TX vref
7666 04:50:50.049307 TX Vref=16, minBit 7, minWin=23, winSum=383
7667 04:50:50.049357 TX Vref=18, minBit 7, minWin=23, winSum=389
7668 04:50:50.049408 TX Vref=20, minBit 12, minWin=23, winSum=395
7669 04:50:50.049458 TX Vref=22, minBit 0, minWin=25, winSum=406
7670 04:50:50.049508 TX Vref=24, minBit 3, minWin=25, winSum=417
7671 04:50:50.049559 TX Vref=26, minBit 12, minWin=25, winSum=427
7672 04:50:50.049608 TX Vref=28, minBit 0, minWin=26, winSum=429
7673 04:50:50.049659 TX Vref=30, minBit 0, minWin=26, winSum=423
7674 04:50:50.049708 TX Vref=32, minBit 0, minWin=25, winSum=413
7675 04:50:50.049758 TX Vref=34, minBit 2, minWin=24, winSum=404
7676 04:50:50.049808 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
7677 04:50:50.049858
7678 04:50:50.049908 Final TX Range 0 Vref 28
7679 04:50:50.049991
7680 04:50:50.050054 ==
7681 04:50:50.050104 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 04:50:50.050154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 04:50:50.050205 ==
7684 04:50:50.050262
7685 04:50:50.050313
7686 04:50:50.050362 TX Vref Scan disable
7687 04:50:50.050412 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7688 04:50:50.050463 == TX Byte 0 ==
7689 04:50:50.050513 u2DelayCellOfst[0]=13 cells (4 PI)
7690 04:50:50.050755 u2DelayCellOfst[1]=20 cells (6 PI)
7691 04:50:50.050815 u2DelayCellOfst[2]=13 cells (4 PI)
7692 04:50:50.050867 u2DelayCellOfst[3]=13 cells (4 PI)
7693 04:50:50.050918 u2DelayCellOfst[4]=10 cells (3 PI)
7694 04:50:50.050968 u2DelayCellOfst[5]=0 cells (0 PI)
7695 04:50:50.051018 u2DelayCellOfst[6]=20 cells (6 PI)
7696 04:50:50.051068 u2DelayCellOfst[7]=17 cells (5 PI)
7697 04:50:50.051118 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7698 04:50:50.051170 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7699 04:50:50.051221 == TX Byte 1 ==
7700 04:50:50.051271 u2DelayCellOfst[8]=3 cells (1 PI)
7701 04:50:50.051320 u2DelayCellOfst[9]=0 cells (0 PI)
7702 04:50:50.051370 u2DelayCellOfst[10]=6 cells (2 PI)
7703 04:50:50.051420 u2DelayCellOfst[11]=3 cells (1 PI)
7704 04:50:50.051470 u2DelayCellOfst[12]=13 cells (4 PI)
7705 04:50:50.051520 u2DelayCellOfst[13]=10 cells (3 PI)
7706 04:50:50.051570 u2DelayCellOfst[14]=13 cells (4 PI)
7707 04:50:50.051620 u2DelayCellOfst[15]=10 cells (3 PI)
7708 04:50:50.051669 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7709 04:50:50.051719 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7710 04:50:50.051769 DramC Write-DBI on
7711 04:50:50.051819 ==
7712 04:50:50.051869 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 04:50:50.051919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 04:50:50.051969 ==
7715 04:50:50.052019
7716 04:50:50.052068
7717 04:50:50.052117 TX Vref Scan disable
7718 04:50:50.052167 == TX Byte 0 ==
7719 04:50:50.052217 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7720 04:50:50.052267 == TX Byte 1 ==
7721 04:50:50.052316 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7722 04:50:50.052366 DramC Write-DBI off
7723 04:50:50.052415
7724 04:50:50.052465 [DATLAT]
7725 04:50:50.052515 Freq=1600, CH0 RK0
7726 04:50:50.052564
7727 04:50:50.052614 DATLAT Default: 0xf
7728 04:50:50.052664 0, 0xFFFF, sum = 0
7729 04:50:50.052714 1, 0xFFFF, sum = 0
7730 04:50:50.052765 2, 0xFFFF, sum = 0
7731 04:50:50.052815 3, 0xFFFF, sum = 0
7732 04:50:50.052865 4, 0xFFFF, sum = 0
7733 04:50:50.052916 5, 0xFFFF, sum = 0
7734 04:50:50.052966 6, 0xFFFF, sum = 0
7735 04:50:50.053016 7, 0xFFFF, sum = 0
7736 04:50:50.053066 8, 0xFFFF, sum = 0
7737 04:50:50.053116 9, 0xFFFF, sum = 0
7738 04:50:50.053166 10, 0xFFFF, sum = 0
7739 04:50:50.053217 11, 0xFFFF, sum = 0
7740 04:50:50.053268 12, 0xFFFF, sum = 0
7741 04:50:50.053319 13, 0xFFFF, sum = 0
7742 04:50:50.053370 14, 0x0, sum = 1
7743 04:50:50.053420 15, 0x0, sum = 2
7744 04:50:50.053471 16, 0x0, sum = 3
7745 04:50:50.053521 17, 0x0, sum = 4
7746 04:50:50.053572 best_step = 15
7747 04:50:50.053621
7748 04:50:50.053671 ==
7749 04:50:50.053721 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 04:50:50.053771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 04:50:50.053831 ==
7752 04:50:50.053882 RX Vref Scan: 1
7753 04:50:50.053931
7754 04:50:50.054023 Set Vref Range= 24 -> 127
7755 04:50:50.054073
7756 04:50:50.054122 RX Vref 24 -> 127, step: 1
7757 04:50:50.054172
7758 04:50:50.054222 RX Delay 19 -> 252, step: 4
7759 04:50:50.054271
7760 04:50:50.054320 Set Vref, RX VrefLevel [Byte0]: 24
7761 04:50:50.054370 [Byte1]: 24
7762 04:50:50.054420
7763 04:50:50.054469 Set Vref, RX VrefLevel [Byte0]: 25
7764 04:50:50.054519 [Byte1]: 25
7765 04:50:50.054569
7766 04:50:50.054619 Set Vref, RX VrefLevel [Byte0]: 26
7767 04:50:50.054669 [Byte1]: 26
7768 04:50:50.054719
7769 04:50:50.054768 Set Vref, RX VrefLevel [Byte0]: 27
7770 04:50:50.054818 [Byte1]: 27
7771 04:50:50.054867
7772 04:50:50.054916 Set Vref, RX VrefLevel [Byte0]: 28
7773 04:50:50.054966 [Byte1]: 28
7774 04:50:50.055015
7775 04:50:50.055064 Set Vref, RX VrefLevel [Byte0]: 29
7776 04:50:50.055114 [Byte1]: 29
7777 04:50:50.055205
7778 04:50:50.055292 Set Vref, RX VrefLevel [Byte0]: 30
7779 04:50:50.055373 [Byte1]: 30
7780 04:50:50.055443
7781 04:50:50.055503 Set Vref, RX VrefLevel [Byte0]: 31
7782 04:50:50.055554 [Byte1]: 31
7783 04:50:50.055605
7784 04:50:50.055664 Set Vref, RX VrefLevel [Byte0]: 32
7785 04:50:50.055737 [Byte1]: 32
7786 04:50:50.055819
7787 04:50:50.055905 Set Vref, RX VrefLevel [Byte0]: 33
7788 04:50:50.055984 [Byte1]: 33
7789 04:50:50.056062
7790 04:50:50.056142 Set Vref, RX VrefLevel [Byte0]: 34
7791 04:50:50.056200 [Byte1]: 34
7792 04:50:50.056283
7793 04:50:50.056369 Set Vref, RX VrefLevel [Byte0]: 35
7794 04:50:50.056450 [Byte1]: 35
7795 04:50:50.056528
7796 04:50:50.056607 Set Vref, RX VrefLevel [Byte0]: 36
7797 04:50:50.056686 [Byte1]: 36
7798 04:50:50.056763
7799 04:50:50.056842 Set Vref, RX VrefLevel [Byte0]: 37
7800 04:50:50.056920 [Byte1]: 37
7801 04:50:50.056998
7802 04:50:50.057077 Set Vref, RX VrefLevel [Byte0]: 38
7803 04:50:50.057155 [Byte1]: 38
7804 04:50:50.057278
7805 04:50:50.057356 Set Vref, RX VrefLevel [Byte0]: 39
7806 04:50:50.057435 [Byte1]: 39
7807 04:50:50.057513
7808 04:50:50.057591 Set Vref, RX VrefLevel [Byte0]: 40
7809 04:50:50.057670 [Byte1]: 40
7810 04:50:50.057747
7811 04:50:50.057826 Set Vref, RX VrefLevel [Byte0]: 41
7812 04:50:50.057905 [Byte1]: 41
7813 04:50:50.058024
7814 04:50:50.058103 Set Vref, RX VrefLevel [Byte0]: 42
7815 04:50:50.058181 [Byte1]: 42
7816 04:50:50.058259
7817 04:50:50.058337 Set Vref, RX VrefLevel [Byte0]: 43
7818 04:50:50.058416 [Byte1]: 43
7819 04:50:50.058493
7820 04:50:50.058572 Set Vref, RX VrefLevel [Byte0]: 44
7821 04:50:50.058652 [Byte1]: 44
7822 04:50:50.058706
7823 04:50:50.058757 Set Vref, RX VrefLevel [Byte0]: 45
7824 04:50:50.058807 [Byte1]: 45
7825 04:50:50.058857
7826 04:50:50.058907 Set Vref, RX VrefLevel [Byte0]: 46
7827 04:50:50.058958 [Byte1]: 46
7828 04:50:50.059008
7829 04:50:50.059058 Set Vref, RX VrefLevel [Byte0]: 47
7830 04:50:50.059108 [Byte1]: 47
7831 04:50:50.059157
7832 04:50:50.059207 Set Vref, RX VrefLevel [Byte0]: 48
7833 04:50:50.059257 [Byte1]: 48
7834 04:50:50.059307
7835 04:50:50.059356 Set Vref, RX VrefLevel [Byte0]: 49
7836 04:50:50.059406 [Byte1]: 49
7837 04:50:50.059456
7838 04:50:50.059506 Set Vref, RX VrefLevel [Byte0]: 50
7839 04:50:50.059556 [Byte1]: 50
7840 04:50:50.059606
7841 04:50:50.059656 Set Vref, RX VrefLevel [Byte0]: 51
7842 04:50:50.059706 [Byte1]: 51
7843 04:50:50.059755
7844 04:50:50.059805 Set Vref, RX VrefLevel [Byte0]: 52
7845 04:50:50.059855 [Byte1]: 52
7846 04:50:50.059905
7847 04:50:50.059954 Set Vref, RX VrefLevel [Byte0]: 53
7848 04:50:50.060004 [Byte1]: 53
7849 04:50:50.060053
7850 04:50:50.060103 Set Vref, RX VrefLevel [Byte0]: 54
7851 04:50:50.060153 [Byte1]: 54
7852 04:50:50.060203
7853 04:50:50.060253 Set Vref, RX VrefLevel [Byte0]: 55
7854 04:50:50.060493 [Byte1]: 55
7855 04:50:50.060589
7856 04:50:50.060641 Set Vref, RX VrefLevel [Byte0]: 56
7857 04:50:50.060692 [Byte1]: 56
7858 04:50:50.060742
7859 04:50:50.060792 Set Vref, RX VrefLevel [Byte0]: 57
7860 04:50:50.060842 [Byte1]: 57
7861 04:50:50.060892
7862 04:50:50.060942 Set Vref, RX VrefLevel [Byte0]: 58
7863 04:50:50.060992 [Byte1]: 58
7864 04:50:50.061042
7865 04:50:50.061092 Set Vref, RX VrefLevel [Byte0]: 59
7866 04:50:50.061142 [Byte1]: 59
7867 04:50:50.061191
7868 04:50:50.061241 Set Vref, RX VrefLevel [Byte0]: 60
7869 04:50:50.061292 [Byte1]: 60
7870 04:50:50.061341
7871 04:50:50.061390 Set Vref, RX VrefLevel [Byte0]: 61
7872 04:50:50.061440 [Byte1]: 61
7873 04:50:50.061490
7874 04:50:50.061539 Set Vref, RX VrefLevel [Byte0]: 62
7875 04:50:50.061588 [Byte1]: 62
7876 04:50:50.061638
7877 04:50:50.061687 Set Vref, RX VrefLevel [Byte0]: 63
7878 04:50:50.061737 [Byte1]: 63
7879 04:50:50.061786
7880 04:50:50.061835 Set Vref, RX VrefLevel [Byte0]: 64
7881 04:50:50.061885 [Byte1]: 64
7882 04:50:50.061934
7883 04:50:50.062027 Set Vref, RX VrefLevel [Byte0]: 65
7884 04:50:50.062078 [Byte1]: 65
7885 04:50:50.062128
7886 04:50:50.062177 Set Vref, RX VrefLevel [Byte0]: 66
7887 04:50:50.062227 [Byte1]: 66
7888 04:50:50.062276
7889 04:50:50.062326 Set Vref, RX VrefLevel [Byte0]: 67
7890 04:50:50.062376 [Byte1]: 67
7891 04:50:50.062425
7892 04:50:50.062475 Set Vref, RX VrefLevel [Byte0]: 68
7893 04:50:50.062525 [Byte1]: 68
7894 04:50:50.062575
7895 04:50:50.062624 Set Vref, RX VrefLevel [Byte0]: 69
7896 04:50:50.062674 [Byte1]: 69
7897 04:50:50.062723
7898 04:50:50.062773 Set Vref, RX VrefLevel [Byte0]: 70
7899 04:50:50.062823 [Byte1]: 70
7900 04:50:50.062873
7901 04:50:50.062922 Set Vref, RX VrefLevel [Byte0]: 71
7902 04:50:50.062972 [Byte1]: 71
7903 04:50:50.063021
7904 04:50:50.063071 Set Vref, RX VrefLevel [Byte0]: 72
7905 04:50:50.063120 [Byte1]: 72
7906 04:50:50.063169
7907 04:50:50.063219 Set Vref, RX VrefLevel [Byte0]: 73
7908 04:50:50.063269 [Byte1]: 73
7909 04:50:50.063318
7910 04:50:50.063368 Set Vref, RX VrefLevel [Byte0]: 74
7911 04:50:50.063418 [Byte1]: 74
7912 04:50:50.063467
7913 04:50:50.063517 Set Vref, RX VrefLevel [Byte0]: 75
7914 04:50:50.063567 [Byte1]: 75
7915 04:50:50.063616
7916 04:50:50.063664 Set Vref, RX VrefLevel [Byte0]: 76
7917 04:50:50.063714 [Byte1]: 76
7918 04:50:50.063764
7919 04:50:50.063822 Set Vref, RX VrefLevel [Byte0]: 77
7920 04:50:50.063873 [Byte1]: 77
7921 04:50:50.063922
7922 04:50:50.063972 Set Vref, RX VrefLevel [Byte0]: 78
7923 04:50:50.064021 [Byte1]: 78
7924 04:50:50.064071
7925 04:50:50.064120 Set Vref, RX VrefLevel [Byte0]: 79
7926 04:50:50.064170 [Byte1]: 79
7927 04:50:50.064220
7928 04:50:50.064269 Set Vref, RX VrefLevel [Byte0]: 80
7929 04:50:50.064319 [Byte1]: 80
7930 04:50:50.064367
7931 04:50:50.064417 Final RX Vref Byte 0 = 62 to rank0
7932 04:50:50.064466 Final RX Vref Byte 1 = 61 to rank0
7933 04:50:50.064516 Final RX Vref Byte 0 = 62 to rank1
7934 04:50:50.064566 Final RX Vref Byte 1 = 61 to rank1==
7935 04:50:50.064616 Dram Type= 6, Freq= 0, CH_0, rank 0
7936 04:50:50.064666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7937 04:50:50.064716 ==
7938 04:50:50.064766 DQS Delay:
7939 04:50:50.064815 DQS0 = 0, DQS1 = 0
7940 04:50:50.064865 DQM Delay:
7941 04:50:50.064915 DQM0 = 135, DQM1 = 124
7942 04:50:50.064965 DQ Delay:
7943 04:50:50.065014 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7944 04:50:50.065064 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =142
7945 04:50:50.065114 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7946 04:50:50.065163 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
7947 04:50:50.065213
7948 04:50:50.065263
7949 04:50:50.065312
7950 04:50:50.065361 [DramC_TX_OE_Calibration] TA2
7951 04:50:50.065411 Original DQ_B0 (3 6) =30, OEN = 27
7952 04:50:50.065461 Original DQ_B1 (3 6) =30, OEN = 27
7953 04:50:50.464465 24, 0x0, End_B0=24 End_B1=24
7954 04:50:50.465130 25, 0x0, End_B0=25 End_B1=25
7955 04:50:50.465515 26, 0x0, End_B0=26 End_B1=26
7956 04:50:50.465700 27, 0x0, End_B0=27 End_B1=27
7957 04:50:50.465758 28, 0x0, End_B0=28 End_B1=28
7958 04:50:50.465813 29, 0x0, End_B0=29 End_B1=29
7959 04:50:50.465867 30, 0x0, End_B0=30 End_B1=30
7960 04:50:50.465921 31, 0x4141, End_B0=30 End_B1=30
7961 04:50:50.465998 Byte0 end_step=30 best_step=27
7962 04:50:50.466063 Byte1 end_step=30 best_step=27
7963 04:50:50.466115 Byte0 TX OE(2T, 0.5T) = (3, 3)
7964 04:50:50.466167 Byte1 TX OE(2T, 0.5T) = (3, 3)
7965 04:50:50.466222
7966 04:50:50.466285
7967 04:50:50.466365 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
7968 04:50:50.466418 CH0 RK0: MR19=303, MR18=1A19
7969 04:50:50.466469 CH0_RK0: MR19=0x303, MR18=0x1A19, DQSOSC=396, MR23=63, INC=23, DEC=15
7970 04:50:50.466519
7971 04:50:50.466569 ----->DramcWriteLeveling(PI) begin...
7972 04:50:50.466621 ==
7973 04:50:50.466673 Dram Type= 6, Freq= 0, CH_0, rank 1
7974 04:50:50.466724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7975 04:50:50.466775 ==
7976 04:50:50.466825 Write leveling (Byte 0): 38 => 38
7977 04:50:50.466876 Write leveling (Byte 1): 28 => 28
7978 04:50:50.466926 DramcWriteLeveling(PI) end<-----
7979 04:50:50.466976
7980 04:50:50.467026 ==
7981 04:50:50.467076 Dram Type= 6, Freq= 0, CH_0, rank 1
7982 04:50:50.467127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7983 04:50:50.467178 ==
7984 04:50:50.467228 [Gating] SW mode calibration
7985 04:50:50.467279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7986 04:50:50.467330 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7987 04:50:50.467381 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7988 04:50:50.467431 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7989 04:50:50.467481 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 04:50:50.467531 1 4 12 | B1->B0 | 2423 2f2f | 1 0 | (0 0) (0 0)
7991 04:50:50.467582 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7992 04:50:50.467633 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7993 04:50:50.467683 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7994 04:50:50.467733 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 04:50:50.467783 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 04:50:50.467834 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 04:50:50.468096 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7998 04:50:50.468211 1 5 12 | B1->B0 | 3333 2525 | 1 0 | (1 0) (0 1)
7999 04:50:50.468276 1 5 16 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8000 04:50:50.468329 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 04:50:50.468381 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 04:50:50.468433 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 04:50:50.468485 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 04:50:50.468536 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 04:50:50.468587 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8006 04:50:50.468638 1 6 12 | B1->B0 | 2a2a 4242 | 0 0 | (0 0) (0 0)
8007 04:50:50.468690 1 6 16 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
8008 04:50:50.468740 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 04:50:50.468791 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 04:50:50.468842 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 04:50:50.468894 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 04:50:50.468945 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 04:50:50.468996 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8014 04:50:50.469047 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8015 04:50:50.469110 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8016 04:50:50.469160 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 04:50:50.469210 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 04:50:50.469260 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 04:50:50.469310 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 04:50:50.469360 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 04:50:50.469410 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 04:50:50.469460 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 04:50:50.469510 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 04:50:50.469560 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 04:50:50.469611 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 04:50:50.469661 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 04:50:50.469711 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 04:50:50.469761 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 04:50:50.469811 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 04:50:50.469861 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8031 04:50:50.469912 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8032 04:50:50.470005 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 04:50:50.470084 Total UI for P1: 0, mck2ui 16
8034 04:50:50.470135 best dqsien dly found for B0: ( 1, 9, 14)
8035 04:50:50.470185 Total UI for P1: 0, mck2ui 16
8036 04:50:50.470239 best dqsien dly found for B1: ( 1, 9, 14)
8037 04:50:50.470320 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8038 04:50:50.470412 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8039 04:50:50.470479
8040 04:50:50.470543 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8041 04:50:50.470593 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8042 04:50:50.470643 [Gating] SW calibration Done
8043 04:50:50.470693 ==
8044 04:50:50.470743 Dram Type= 6, Freq= 0, CH_0, rank 1
8045 04:50:50.470794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 04:50:50.470845 ==
8047 04:50:50.470894 RX Vref Scan: 0
8048 04:50:50.470944
8049 04:50:50.470994 RX Vref 0 -> 0, step: 1
8050 04:50:50.471044
8051 04:50:50.471093 RX Delay 0 -> 252, step: 8
8052 04:50:50.471143 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8053 04:50:50.471194 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8054 04:50:50.471244 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8055 04:50:50.471294 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8056 04:50:50.471344 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8057 04:50:50.471393 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8058 04:50:50.471443 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8059 04:50:50.471495 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8060 04:50:50.471546 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8061 04:50:50.471597 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8062 04:50:50.471648 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8063 04:50:50.471699 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8064 04:50:50.471750 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8065 04:50:50.471800 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8066 04:50:50.471852 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8067 04:50:50.471903 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8068 04:50:50.471955 ==
8069 04:50:50.472006 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 04:50:50.472058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 04:50:50.472109 ==
8072 04:50:50.472161 DQS Delay:
8073 04:50:50.472212 DQS0 = 0, DQS1 = 0
8074 04:50:50.472263 DQM Delay:
8075 04:50:50.472315 DQM0 = 136, DQM1 = 124
8076 04:50:50.472367 DQ Delay:
8077 04:50:50.472418 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8078 04:50:50.472469 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8079 04:50:50.472521 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8080 04:50:50.472572 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8081 04:50:50.472623
8082 04:50:50.472674
8083 04:50:50.472725 ==
8084 04:50:50.472776 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 04:50:50.472828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 04:50:50.472879 ==
8087 04:50:50.472931
8088 04:50:50.472982
8089 04:50:50.473033 TX Vref Scan disable
8090 04:50:50.473085 == TX Byte 0 ==
8091 04:50:50.473135 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8092 04:50:50.473188 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8093 04:50:50.473239 == TX Byte 1 ==
8094 04:50:50.473291 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8095 04:50:50.473342 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8096 04:50:50.473393 ==
8097 04:50:50.473444 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 04:50:50.473496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 04:50:50.473548 ==
8100 04:50:50.473599
8101 04:50:50.473649 TX Vref early break, caculate TX vref
8102 04:50:50.473701 TX Vref=16, minBit 0, minWin=23, winSum=388
8103 04:50:50.473753 TX Vref=18, minBit 8, minWin=24, winSum=403
8104 04:50:50.473804 TX Vref=20, minBit 0, minWin=24, winSum=402
8105 04:50:50.474063 TX Vref=22, minBit 2, minWin=25, winSum=414
8106 04:50:50.474152 TX Vref=24, minBit 0, minWin=25, winSum=419
8107 04:50:50.474207 TX Vref=26, minBit 2, minWin=25, winSum=426
8108 04:50:50.474260 TX Vref=28, minBit 0, minWin=26, winSum=430
8109 04:50:50.474314 TX Vref=30, minBit 0, minWin=26, winSum=424
8110 04:50:50.474367 TX Vref=32, minBit 0, minWin=26, winSum=422
8111 04:50:50.474420 TX Vref=34, minBit 0, minWin=25, winSum=411
8112 04:50:50.474473 TX Vref=36, minBit 2, minWin=24, winSum=399
8113 04:50:50.474539 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8114 04:50:50.474592
8115 04:50:50.474643 Final TX Range 0 Vref 28
8116 04:50:50.474695
8117 04:50:50.474747 ==
8118 04:50:50.474798 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 04:50:50.474850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 04:50:50.474902 ==
8121 04:50:50.474953
8122 04:50:50.475004
8123 04:50:50.475056 TX Vref Scan disable
8124 04:50:50.475108 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8125 04:50:50.475159 == TX Byte 0 ==
8126 04:50:50.475211 u2DelayCellOfst[0]=17 cells (5 PI)
8127 04:50:50.475263 u2DelayCellOfst[1]=20 cells (6 PI)
8128 04:50:50.475314 u2DelayCellOfst[2]=13 cells (4 PI)
8129 04:50:50.475366 u2DelayCellOfst[3]=13 cells (4 PI)
8130 04:50:50.475417 u2DelayCellOfst[4]=10 cells (3 PI)
8131 04:50:50.475469 u2DelayCellOfst[5]=0 cells (0 PI)
8132 04:50:50.475520 u2DelayCellOfst[6]=20 cells (6 PI)
8133 04:50:50.475571 u2DelayCellOfst[7]=20 cells (6 PI)
8134 04:50:50.475622 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8135 04:50:50.475675 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8136 04:50:50.475727 == TX Byte 1 ==
8137 04:50:50.475778 u2DelayCellOfst[8]=3 cells (1 PI)
8138 04:50:50.475830 u2DelayCellOfst[9]=0 cells (0 PI)
8139 04:50:50.475881 u2DelayCellOfst[10]=6 cells (2 PI)
8140 04:50:50.475933 u2DelayCellOfst[11]=3 cells (1 PI)
8141 04:50:50.475985 u2DelayCellOfst[12]=13 cells (4 PI)
8142 04:50:50.476036 u2DelayCellOfst[13]=10 cells (3 PI)
8143 04:50:50.476087 u2DelayCellOfst[14]=13 cells (4 PI)
8144 04:50:50.476138 u2DelayCellOfst[15]=13 cells (4 PI)
8145 04:50:50.476189 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8146 04:50:50.476241 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8147 04:50:50.476292 DramC Write-DBI on
8148 04:50:50.476343 ==
8149 04:50:50.476395 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 04:50:50.476446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 04:50:50.476498 ==
8152 04:50:50.476550
8153 04:50:50.476601
8154 04:50:50.476652 TX Vref Scan disable
8155 04:50:50.476703 == TX Byte 0 ==
8156 04:50:50.476755 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8157 04:50:50.476807 == TX Byte 1 ==
8158 04:50:50.476859 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8159 04:50:50.476910 DramC Write-DBI off
8160 04:50:50.476961
8161 04:50:50.477028 [DATLAT]
8162 04:50:50.477093 Freq=1600, CH0 RK1
8163 04:50:50.477174
8164 04:50:50.477224 DATLAT Default: 0xf
8165 04:50:50.477276 0, 0xFFFF, sum = 0
8166 04:50:50.477329 1, 0xFFFF, sum = 0
8167 04:50:50.477382 2, 0xFFFF, sum = 0
8168 04:50:50.477450 3, 0xFFFF, sum = 0
8169 04:50:50.477516 4, 0xFFFF, sum = 0
8170 04:50:50.477568 5, 0xFFFF, sum = 0
8171 04:50:50.477621 6, 0xFFFF, sum = 0
8172 04:50:50.477674 7, 0xFFFF, sum = 0
8173 04:50:50.477727 8, 0xFFFF, sum = 0
8174 04:50:50.477779 9, 0xFFFF, sum = 0
8175 04:50:50.477831 10, 0xFFFF, sum = 0
8176 04:50:50.477884 11, 0xFFFF, sum = 0
8177 04:50:50.477936 12, 0xFFFF, sum = 0
8178 04:50:50.478050 13, 0xFFFF, sum = 0
8179 04:50:50.478102 14, 0x0, sum = 1
8180 04:50:50.478154 15, 0x0, sum = 2
8181 04:50:50.478207 16, 0x0, sum = 3
8182 04:50:50.478259 17, 0x0, sum = 4
8183 04:50:50.478311 best_step = 15
8184 04:50:50.478362
8185 04:50:50.478413 ==
8186 04:50:50.478464 Dram Type= 6, Freq= 0, CH_0, rank 1
8187 04:50:50.478515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8188 04:50:50.478567 ==
8189 04:50:50.478619 RX Vref Scan: 0
8190 04:50:50.478671
8191 04:50:50.478722 RX Vref 0 -> 0, step: 1
8192 04:50:50.478773
8193 04:50:50.478824 RX Delay 11 -> 252, step: 4
8194 04:50:50.478876 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8195 04:50:50.478928 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8196 04:50:50.478979 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8197 04:50:50.479031 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8198 04:50:50.479082 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8199 04:50:50.479133 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8200 04:50:50.479185 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8201 04:50:50.479236 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8202 04:50:50.479287 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8203 04:50:50.479339 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8204 04:50:50.479390 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8205 04:50:50.479441 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8206 04:50:50.479492 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8207 04:50:50.479543 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8208 04:50:50.479595 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8209 04:50:50.479646 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8210 04:50:50.479697 ==
8211 04:50:50.479749 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 04:50:50.479801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 04:50:50.479854 ==
8214 04:50:50.479905 DQS Delay:
8215 04:50:50.479957 DQS0 = 0, DQS1 = 0
8216 04:50:50.480008 DQM Delay:
8217 04:50:50.480059 DQM0 = 133, DQM1 = 123
8218 04:50:50.480110 DQ Delay:
8219 04:50:50.480162 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8220 04:50:50.480214 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8221 04:50:50.480265 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8222 04:50:50.480317 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8223 04:50:50.480368
8224 04:50:50.480419
8225 04:50:50.480470
8226 04:50:50.480521 [DramC_TX_OE_Calibration] TA2
8227 04:50:50.480572 Original DQ_B0 (3 6) =30, OEN = 27
8228 04:50:50.480624 Original DQ_B1 (3 6) =30, OEN = 27
8229 04:50:50.480676 24, 0x0, End_B0=24 End_B1=24
8230 04:50:50.480728 25, 0x0, End_B0=25 End_B1=25
8231 04:50:50.480780 26, 0x0, End_B0=26 End_B1=26
8232 04:50:50.480833 27, 0x0, End_B0=27 End_B1=27
8233 04:50:50.480903 28, 0x0, End_B0=28 End_B1=28
8234 04:50:50.480969 29, 0x0, End_B0=29 End_B1=29
8235 04:50:50.481021 30, 0x0, End_B0=30 End_B1=30
8236 04:50:50.481073 31, 0x4141, End_B0=30 End_B1=30
8237 04:50:50.481126 Byte0 end_step=30 best_step=27
8238 04:50:50.481177 Byte1 end_step=30 best_step=27
8239 04:50:50.481244 Byte0 TX OE(2T, 0.5T) = (3, 3)
8240 04:50:50.481321 Byte1 TX OE(2T, 0.5T) = (3, 3)
8241 04:50:50.481375
8242 04:50:50.481439
8243 04:50:50.481490 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
8244 04:50:50.481543 CH0 RK1: MR19=303, MR18=1E0B
8245 04:50:50.481595 CH0_RK1: MR19=0x303, MR18=0x1E0B, DQSOSC=394, MR23=63, INC=23, DEC=15
8246 04:50:50.481647 [RxdqsGatingPostProcess] freq 1600
8247 04:50:50.481888 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8248 04:50:50.481998 best DQS0 dly(2T, 0.5T) = (1, 1)
8249 04:50:50.482067 best DQS1 dly(2T, 0.5T) = (1, 1)
8250 04:50:50.482119 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8251 04:50:50.482171 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8252 04:50:50.482224 best DQS0 dly(2T, 0.5T) = (1, 1)
8253 04:50:50.482276 best DQS1 dly(2T, 0.5T) = (1, 1)
8254 04:50:50.482328 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8255 04:50:50.482380 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8256 04:50:50.482444 Pre-setting of DQS Precalculation
8257 04:50:50.482496 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8258 04:50:50.482548 ==
8259 04:50:50.482599 Dram Type= 6, Freq= 0, CH_1, rank 0
8260 04:50:50.482651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 04:50:50.482702 ==
8262 04:50:50.482754 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8263 04:50:50.482806 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8264 04:50:50.482858 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8265 04:50:50.482910 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8266 04:50:50.482978 [CA 0] Center 40 (11~70) winsize 60
8267 04:50:50.483043 [CA 1] Center 41 (11~71) winsize 61
8268 04:50:50.483094 [CA 2] Center 37 (8~67) winsize 60
8269 04:50:50.483145 [CA 3] Center 36 (7~66) winsize 60
8270 04:50:50.483197 [CA 4] Center 36 (6~66) winsize 61
8271 04:50:50.483248 [CA 5] Center 36 (6~66) winsize 61
8272 04:50:50.483299
8273 04:50:50.483350 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8274 04:50:50.483402
8275 04:50:50.483453 [CATrainingPosCal] consider 1 rank data
8276 04:50:50.483504 u2DelayCellTimex100 = 285/100 ps
8277 04:50:50.483555 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8278 04:50:50.483607 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8279 04:50:50.483658 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8280 04:50:50.483709 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8281 04:50:50.483761 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
8282 04:50:50.483812 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8283 04:50:50.483863
8284 04:50:50.483914 CA PerBit enable=1, Macro0, CA PI delay=36
8285 04:50:50.483965
8286 04:50:50.484016 [CBTSetCACLKResult] CA Dly = 36
8287 04:50:50.484067 CS Dly: 8 (0~39)
8288 04:50:50.484119 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8289 04:50:50.484170 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8290 04:50:50.484222 ==
8291 04:50:50.484273 Dram Type= 6, Freq= 0, CH_1, rank 1
8292 04:50:50.484325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 04:50:50.484377 ==
8294 04:50:50.484427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8295 04:50:50.484477 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8296 04:50:50.484527 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8297 04:50:50.484577 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8298 04:50:50.484628 [CA 0] Center 42 (13~72) winsize 60
8299 04:50:50.484677 [CA 1] Center 42 (12~72) winsize 61
8300 04:50:50.484727 [CA 2] Center 38 (9~68) winsize 60
8301 04:50:50.484776 [CA 3] Center 37 (8~67) winsize 60
8302 04:50:50.484826 [CA 4] Center 38 (9~68) winsize 60
8303 04:50:50.484876 [CA 5] Center 37 (8~67) winsize 60
8304 04:50:50.484926
8305 04:50:50.484975 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8306 04:50:50.485024
8307 04:50:50.485074 [CATrainingPosCal] consider 2 rank data
8308 04:50:50.485124 u2DelayCellTimex100 = 285/100 ps
8309 04:50:50.485174 CA0 delay=41 (13~70),Diff = 4 PI (13 cell)
8310 04:50:50.485224 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8311 04:50:50.485273 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8312 04:50:50.485323 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8313 04:50:50.485373 CA4 delay=37 (9~66),Diff = 0 PI (0 cell)
8314 04:50:50.485422 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8315 04:50:50.485471
8316 04:50:50.485521 CA PerBit enable=1, Macro0, CA PI delay=37
8317 04:50:50.485570
8318 04:50:50.485620 [CBTSetCACLKResult] CA Dly = 37
8319 04:50:50.485669 CS Dly: 9 (0~41)
8320 04:50:50.485719 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8321 04:50:50.485769 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8322 04:50:50.485818
8323 04:50:50.485868 ----->DramcWriteLeveling(PI) begin...
8324 04:50:50.485918 ==
8325 04:50:50.485991 Dram Type= 6, Freq= 0, CH_1, rank 0
8326 04:50:50.486054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 04:50:50.486105 ==
8328 04:50:50.486168 Write leveling (Byte 0): 24 => 24
8329 04:50:50.486233 Write leveling (Byte 1): 29 => 29
8330 04:50:50.486282 DramcWriteLeveling(PI) end<-----
8331 04:50:50.486332
8332 04:50:50.486381 ==
8333 04:50:50.486431 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 04:50:50.486482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 04:50:50.486532 ==
8336 04:50:50.486582 [Gating] SW mode calibration
8337 04:50:50.486632 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8338 04:50:50.486682 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8339 04:50:50.486732 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 04:50:50.486782 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 04:50:50.486832 1 4 8 | B1->B0 | 2424 3030 | 1 1 | (1 1) (1 1)
8342 04:50:50.486882 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8343 04:50:50.486932 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 04:50:50.486981 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 04:50:50.487031 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 04:50:50.487080 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 04:50:50.487131 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 04:50:50.487181 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8349 04:50:50.487230 1 5 8 | B1->B0 | 3434 2323 | 0 0 | (0 1) (1 0)
8350 04:50:50.487280 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8351 04:50:50.487330 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 04:50:50.487379 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 04:50:50.487429 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 04:50:50.487478 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 04:50:50.487528 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 04:50:50.487578 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8357 04:50:50.487836 1 6 8 | B1->B0 | 2c2c 4444 | 1 0 | (0 0) (0 0)
8358 04:50:50.487925 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8359 04:50:50.487978 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 04:50:50.488030 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 04:50:50.488081 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 04:50:50.488132 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 04:50:50.488183 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 04:50:50.488234 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 04:50:50.488285 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8366 04:50:50.488349 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8367 04:50:50.488399 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8368 04:50:50.488450 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 04:50:50.488517 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 04:50:50.488609 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 04:50:50.488688 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 04:50:50.488766 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 04:50:50.488816 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 04:50:50.488865 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 04:50:50.488931 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 04:50:50.488994 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 04:50:50.489044 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 04:50:50.489110 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 04:50:50.489173 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 04:50:50.489223 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8381 04:50:50.489289 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8382 04:50:50.489352 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8383 04:50:50.489402 Total UI for P1: 0, mck2ui 16
8384 04:50:50.489452 best dqsien dly found for B0: ( 1, 9, 6)
8385 04:50:50.489503 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 04:50:50.489553 Total UI for P1: 0, mck2ui 16
8387 04:50:50.489602 best dqsien dly found for B1: ( 1, 9, 10)
8388 04:50:50.489652 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8389 04:50:50.489703 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8390 04:50:50.489753
8391 04:50:50.489802 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8392 04:50:50.489852 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8393 04:50:50.489903 [Gating] SW calibration Done
8394 04:50:50.489974 ==
8395 04:50:50.490043 Dram Type= 6, Freq= 0, CH_1, rank 0
8396 04:50:50.490123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8397 04:50:50.490174 ==
8398 04:50:50.490224 RX Vref Scan: 0
8399 04:50:50.490274
8400 04:50:50.490323 RX Vref 0 -> 0, step: 1
8401 04:50:50.490373
8402 04:50:50.490423 RX Delay 0 -> 252, step: 8
8403 04:50:50.490473 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8404 04:50:50.490524 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8405 04:50:50.490575 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8406 04:50:50.490625 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8407 04:50:50.490675 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8408 04:50:50.490726 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8409 04:50:50.490775 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8410 04:50:50.490825 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8411 04:50:50.490875 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8412 04:50:50.490925 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8413 04:50:50.490974 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8414 04:50:50.491024 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8415 04:50:50.491074 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8416 04:50:50.491124 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8417 04:50:50.491173 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8418 04:50:50.491223 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8419 04:50:50.491273 ==
8420 04:50:50.491323 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 04:50:50.491373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 04:50:50.491423 ==
8423 04:50:50.491473 DQS Delay:
8424 04:50:50.491523 DQS0 = 0, DQS1 = 0
8425 04:50:50.491573 DQM Delay:
8426 04:50:50.491623 DQM0 = 139, DQM1 = 130
8427 04:50:50.491672 DQ Delay:
8428 04:50:50.491722 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8429 04:50:50.491773 DQ4 =139, DQ5 =147, DQ6 =147, DQ7 =135
8430 04:50:50.491823 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8431 04:50:50.491873 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8432 04:50:50.491923
8433 04:50:50.491973
8434 04:50:50.492022 ==
8435 04:50:50.492072 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 04:50:50.492149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 04:50:50.492223 ==
8438 04:50:50.492273
8439 04:50:50.492322
8440 04:50:50.492372 TX Vref Scan disable
8441 04:50:50.492422 == TX Byte 0 ==
8442 04:50:50.492472 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8443 04:50:50.492523 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8444 04:50:50.492573 == TX Byte 1 ==
8445 04:50:50.492623 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8446 04:50:50.492673 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8447 04:50:50.492724 ==
8448 04:50:50.492773 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 04:50:50.492823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 04:50:50.492873 ==
8451 04:50:50.492923
8452 04:50:50.492973 TX Vref early break, caculate TX vref
8453 04:50:50.493023 TX Vref=16, minBit 15, minWin=21, winSum=370
8454 04:50:50.493074 TX Vref=18, minBit 11, minWin=21, winSum=378
8455 04:50:50.493124 TX Vref=20, minBit 15, minWin=22, winSum=388
8456 04:50:50.493174 TX Vref=22, minBit 9, minWin=23, winSum=399
8457 04:50:50.493224 TX Vref=24, minBit 15, minWin=24, winSum=409
8458 04:50:50.493289 TX Vref=26, minBit 15, minWin=25, winSum=420
8459 04:50:50.493369 TX Vref=28, minBit 5, minWin=26, winSum=426
8460 04:50:50.493432 TX Vref=30, minBit 10, minWin=24, winSum=415
8461 04:50:50.493482 TX Vref=32, minBit 10, minWin=23, winSum=408
8462 04:50:50.493532 TX Vref=34, minBit 10, minWin=23, winSum=397
8463 04:50:50.493582 [TxChooseVref] Worse bit 5, Min win 26, Win sum 426, Final Vref 28
8464 04:50:50.493633
8465 04:50:50.493683 Final TX Range 0 Vref 28
8466 04:50:50.493733
8467 04:50:50.493782 ==
8468 04:50:50.493831 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 04:50:50.494072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 04:50:50.494166 ==
8471 04:50:50.494252
8472 04:50:50.494305
8473 04:50:50.494369 TX Vref Scan disable
8474 04:50:50.494419 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8475 04:50:50.494470 == TX Byte 0 ==
8476 04:50:50.494521 u2DelayCellOfst[0]=17 cells (5 PI)
8477 04:50:50.494571 u2DelayCellOfst[1]=6 cells (2 PI)
8478 04:50:50.494622 u2DelayCellOfst[2]=0 cells (0 PI)
8479 04:50:50.494672 u2DelayCellOfst[3]=6 cells (2 PI)
8480 04:50:50.494722 u2DelayCellOfst[4]=6 cells (2 PI)
8481 04:50:50.494773 u2DelayCellOfst[5]=17 cells (5 PI)
8482 04:50:50.494822 u2DelayCellOfst[6]=17 cells (5 PI)
8483 04:50:50.494872 u2DelayCellOfst[7]=6 cells (2 PI)
8484 04:50:50.494921 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8485 04:50:50.494973 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8486 04:50:50.495024 == TX Byte 1 ==
8487 04:50:50.495074 u2DelayCellOfst[8]=0 cells (0 PI)
8488 04:50:50.495123 u2DelayCellOfst[9]=0 cells (0 PI)
8489 04:50:50.495174 u2DelayCellOfst[10]=10 cells (3 PI)
8490 04:50:50.495223 u2DelayCellOfst[11]=0 cells (0 PI)
8491 04:50:50.495273 u2DelayCellOfst[12]=13 cells (4 PI)
8492 04:50:50.495322 u2DelayCellOfst[13]=13 cells (4 PI)
8493 04:50:50.495372 u2DelayCellOfst[14]=13 cells (4 PI)
8494 04:50:50.495422 u2DelayCellOfst[15]=13 cells (4 PI)
8495 04:50:50.495472 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8496 04:50:50.495522 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8497 04:50:50.495573 DramC Write-DBI on
8498 04:50:50.495622 ==
8499 04:50:50.495673 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 04:50:50.495722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 04:50:50.495772 ==
8502 04:50:50.495822
8503 04:50:50.495872
8504 04:50:50.495921 TX Vref Scan disable
8505 04:50:50.495971 == TX Byte 0 ==
8506 04:50:50.496021 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8507 04:50:50.496071 == TX Byte 1 ==
8508 04:50:50.496120 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8509 04:50:50.496170 DramC Write-DBI off
8510 04:50:50.496219
8511 04:50:50.496269 [DATLAT]
8512 04:50:50.496319 Freq=1600, CH1 RK0
8513 04:50:50.496369
8514 04:50:50.496418 DATLAT Default: 0xf
8515 04:50:50.496468 0, 0xFFFF, sum = 0
8516 04:50:50.496519 1, 0xFFFF, sum = 0
8517 04:50:50.496570 2, 0xFFFF, sum = 0
8518 04:50:50.496621 3, 0xFFFF, sum = 0
8519 04:50:50.496672 4, 0xFFFF, sum = 0
8520 04:50:50.496722 5, 0xFFFF, sum = 0
8521 04:50:50.496772 6, 0xFFFF, sum = 0
8522 04:50:50.496822 7, 0xFFFF, sum = 0
8523 04:50:50.496873 8, 0xFFFF, sum = 0
8524 04:50:50.496923 9, 0xFFFF, sum = 0
8525 04:50:50.496974 10, 0xFFFF, sum = 0
8526 04:50:50.497025 11, 0xFFFF, sum = 0
8527 04:50:50.497077 12, 0xFFFF, sum = 0
8528 04:50:50.497128 13, 0xFFFF, sum = 0
8529 04:50:50.497179 14, 0x0, sum = 1
8530 04:50:50.497229 15, 0x0, sum = 2
8531 04:50:50.497280 16, 0x0, sum = 3
8532 04:50:50.497331 17, 0x0, sum = 4
8533 04:50:50.497382 best_step = 15
8534 04:50:50.497431
8535 04:50:50.497481 ==
8536 04:50:50.497530 Dram Type= 6, Freq= 0, CH_1, rank 0
8537 04:50:50.497581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8538 04:50:50.497631 ==
8539 04:50:50.497682 RX Vref Scan: 1
8540 04:50:50.497731
8541 04:50:50.497781 Set Vref Range= 24 -> 127
8542 04:50:50.497830
8543 04:50:50.497880 RX Vref 24 -> 127, step: 1
8544 04:50:50.497929
8545 04:50:50.498024 RX Delay 19 -> 252, step: 4
8546 04:50:50.498087
8547 04:50:50.498137 Set Vref, RX VrefLevel [Byte0]: 24
8548 04:50:50.498187 [Byte1]: 24
8549 04:50:50.498237
8550 04:50:50.498286 Set Vref, RX VrefLevel [Byte0]: 25
8551 04:50:50.498336 [Byte1]: 25
8552 04:50:50.498386
8553 04:50:50.498435 Set Vref, RX VrefLevel [Byte0]: 26
8554 04:50:50.498486 [Byte1]: 26
8555 04:50:50.498536
8556 04:50:50.498585 Set Vref, RX VrefLevel [Byte0]: 27
8557 04:50:50.498635 [Byte1]: 27
8558 04:50:50.498685
8559 04:50:50.498747 Set Vref, RX VrefLevel [Byte0]: 28
8560 04:50:50.498800 [Byte1]: 28
8561 04:50:50.498850
8562 04:50:50.498911 Set Vref, RX VrefLevel [Byte0]: 29
8563 04:50:50.498962 [Byte1]: 29
8564 04:50:50.499012
8565 04:50:50.499062 Set Vref, RX VrefLevel [Byte0]: 30
8566 04:50:50.499112 [Byte1]: 30
8567 04:50:50.499179
8568 04:50:50.499236 Set Vref, RX VrefLevel [Byte0]: 31
8569 04:50:50.499300 [Byte1]: 31
8570 04:50:50.499361
8571 04:50:50.499421 Set Vref, RX VrefLevel [Byte0]: 32
8572 04:50:50.499486 [Byte1]: 32
8573 04:50:50.499543
8574 04:50:50.499601 Set Vref, RX VrefLevel [Byte0]: 33
8575 04:50:50.499661 [Byte1]: 33
8576 04:50:50.499714
8577 04:50:50.499764 Set Vref, RX VrefLevel [Byte0]: 34
8578 04:50:50.499815 [Byte1]: 34
8579 04:50:50.499865
8580 04:50:50.499915 Set Vref, RX VrefLevel [Byte0]: 35
8581 04:50:50.499994 [Byte1]: 35
8582 04:50:50.500044
8583 04:50:50.500094 Set Vref, RX VrefLevel [Byte0]: 36
8584 04:50:50.500144 [Byte1]: 36
8585 04:50:50.500194
8586 04:50:50.500244 Set Vref, RX VrefLevel [Byte0]: 37
8587 04:50:50.500294 [Byte1]: 37
8588 04:50:50.500344
8589 04:50:50.500394 Set Vref, RX VrefLevel [Byte0]: 38
8590 04:50:50.500444 [Byte1]: 38
8591 04:50:50.500494
8592 04:50:50.500543 Set Vref, RX VrefLevel [Byte0]: 39
8593 04:50:50.500594 [Byte1]: 39
8594 04:50:50.500643
8595 04:50:50.500692 Set Vref, RX VrefLevel [Byte0]: 40
8596 04:50:50.500742 [Byte1]: 40
8597 04:50:50.500792
8598 04:50:50.500842 Set Vref, RX VrefLevel [Byte0]: 41
8599 04:50:50.500891 [Byte1]: 41
8600 04:50:50.500941
8601 04:50:50.500990 Set Vref, RX VrefLevel [Byte0]: 42
8602 04:50:50.501040 [Byte1]: 42
8603 04:50:50.501090
8604 04:50:50.501140 Set Vref, RX VrefLevel [Byte0]: 43
8605 04:50:50.501189 [Byte1]: 43
8606 04:50:50.501239
8607 04:50:50.501289 Set Vref, RX VrefLevel [Byte0]: 44
8608 04:50:50.501339 [Byte1]: 44
8609 04:50:50.501389
8610 04:50:50.501439 Set Vref, RX VrefLevel [Byte0]: 45
8611 04:50:50.501489 [Byte1]: 45
8612 04:50:50.501568
8613 04:50:50.501618 Set Vref, RX VrefLevel [Byte0]: 46
8614 04:50:50.501668 [Byte1]: 46
8615 04:50:50.501718
8616 04:50:50.501767 Set Vref, RX VrefLevel [Byte0]: 47
8617 04:50:50.501817 [Byte1]: 47
8618 04:50:50.501867
8619 04:50:50.501917 Set Vref, RX VrefLevel [Byte0]: 48
8620 04:50:50.502063 [Byte1]: 48
8621 04:50:50.502144
8622 04:50:50.502194 Set Vref, RX VrefLevel [Byte0]: 49
8623 04:50:50.502244 [Byte1]: 49
8624 04:50:50.502294
8625 04:50:50.502343 Set Vref, RX VrefLevel [Byte0]: 50
8626 04:50:50.502393 [Byte1]: 50
8627 04:50:50.502442
8628 04:50:50.502492 Set Vref, RX VrefLevel [Byte0]: 51
8629 04:50:50.502542 [Byte1]: 51
8630 04:50:50.502591
8631 04:50:50.502640 Set Vref, RX VrefLevel [Byte0]: 52
8632 04:50:50.502690 [Byte1]: 52
8633 04:50:50.502740
8634 04:50:50.502789 Set Vref, RX VrefLevel [Byte0]: 53
8635 04:50:50.503029 [Byte1]: 53
8636 04:50:50.503104
8637 04:50:50.503201 Set Vref, RX VrefLevel [Byte0]: 54
8638 04:50:50.503253 [Byte1]: 54
8639 04:50:50.503303
8640 04:50:50.503353 Set Vref, RX VrefLevel [Byte0]: 55
8641 04:50:50.503404 [Byte1]: 55
8642 04:50:50.503454
8643 04:50:50.503504 Set Vref, RX VrefLevel [Byte0]: 56
8644 04:50:50.503554 [Byte1]: 56
8645 04:50:50.503605
8646 04:50:50.503654 Set Vref, RX VrefLevel [Byte0]: 57
8647 04:50:50.503704 [Byte1]: 57
8648 04:50:50.503755
8649 04:50:50.503804 Set Vref, RX VrefLevel [Byte0]: 58
8650 04:50:50.503854 [Byte1]: 58
8651 04:50:50.503904
8652 04:50:50.503954 Set Vref, RX VrefLevel [Byte0]: 59
8653 04:50:50.504028 [Byte1]: 59
8654 04:50:50.504091
8655 04:50:50.504141 Set Vref, RX VrefLevel [Byte0]: 60
8656 04:50:50.504192 [Byte1]: 60
8657 04:50:50.504242
8658 04:50:50.504293 Set Vref, RX VrefLevel [Byte0]: 61
8659 04:50:50.504343 [Byte1]: 61
8660 04:50:50.504392
8661 04:50:50.504442 Set Vref, RX VrefLevel [Byte0]: 62
8662 04:50:50.504491 [Byte1]: 62
8663 04:50:50.504541
8664 04:50:50.504590 Set Vref, RX VrefLevel [Byte0]: 63
8665 04:50:50.504640 [Byte1]: 63
8666 04:50:50.504690
8667 04:50:50.504740 Set Vref, RX VrefLevel [Byte0]: 64
8668 04:50:50.504789 [Byte1]: 64
8669 04:50:50.504839
8670 04:50:50.504888 Set Vref, RX VrefLevel [Byte0]: 65
8671 04:50:50.504938 [Byte1]: 65
8672 04:50:50.504988
8673 04:50:50.505037 Set Vref, RX VrefLevel [Byte0]: 66
8674 04:50:50.505086 [Byte1]: 66
8675 04:50:50.505136
8676 04:50:50.505186 Set Vref, RX VrefLevel [Byte0]: 67
8677 04:50:50.505236 [Byte1]: 67
8678 04:50:50.505286
8679 04:50:50.505335 Set Vref, RX VrefLevel [Byte0]: 68
8680 04:50:50.505385 [Byte1]: 68
8681 04:50:50.505435
8682 04:50:50.505484 Set Vref, RX VrefLevel [Byte0]: 69
8683 04:50:50.505534 [Byte1]: 69
8684 04:50:50.505583
8685 04:50:50.505633 Set Vref, RX VrefLevel [Byte0]: 70
8686 04:50:50.505683 [Byte1]: 70
8687 04:50:50.505733
8688 04:50:50.505783 Set Vref, RX VrefLevel [Byte0]: 71
8689 04:50:50.505833 [Byte1]: 71
8690 04:50:50.505883
8691 04:50:50.505932 Set Vref, RX VrefLevel [Byte0]: 72
8692 04:50:50.506041 [Byte1]: 72
8693 04:50:50.506096
8694 04:50:50.506156 Set Vref, RX VrefLevel [Byte0]: 73
8695 04:50:50.506211 [Byte1]: 73
8696 04:50:50.506261
8697 04:50:50.506311 Set Vref, RX VrefLevel [Byte0]: 74
8698 04:50:50.506362 [Byte1]: 74
8699 04:50:50.506412
8700 04:50:50.506462 Final RX Vref Byte 0 = 61 to rank0
8701 04:50:50.506512 Final RX Vref Byte 1 = 62 to rank0
8702 04:50:50.506563 Final RX Vref Byte 0 = 61 to rank1
8703 04:50:50.506613 Final RX Vref Byte 1 = 62 to rank1==
8704 04:50:50.506664 Dram Type= 6, Freq= 0, CH_1, rank 0
8705 04:50:50.506714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8706 04:50:50.506765 ==
8707 04:50:50.506815 DQS Delay:
8708 04:50:50.506865 DQS0 = 0, DQS1 = 0
8709 04:50:50.506914 DQM Delay:
8710 04:50:50.506964 DQM0 = 135, DQM1 = 128
8711 04:50:50.507014 DQ Delay:
8712 04:50:50.507064 DQ0 =138, DQ1 =130, DQ2 =124, DQ3 =134
8713 04:50:50.507114 DQ4 =132, DQ5 =146, DQ6 =148, DQ7 =132
8714 04:50:50.507164 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8715 04:50:50.507214 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =134
8716 04:50:50.507264
8717 04:50:50.507313
8718 04:50:50.507362
8719 04:50:50.507411 [DramC_TX_OE_Calibration] TA2
8720 04:50:50.507461 Original DQ_B0 (3 6) =30, OEN = 27
8721 04:50:50.507512 Original DQ_B1 (3 6) =30, OEN = 27
8722 04:50:50.507562 24, 0x0, End_B0=24 End_B1=24
8723 04:50:50.507613 25, 0x0, End_B0=25 End_B1=25
8724 04:50:50.507664 26, 0x0, End_B0=26 End_B1=26
8725 04:50:50.507715 27, 0x0, End_B0=27 End_B1=27
8726 04:50:50.507765 28, 0x0, End_B0=28 End_B1=28
8727 04:50:50.507816 29, 0x0, End_B0=29 End_B1=29
8728 04:50:50.507866 30, 0x0, End_B0=30 End_B1=30
8729 04:50:50.507917 31, 0x4141, End_B0=30 End_B1=30
8730 04:50:50.507988 Byte0 end_step=30 best_step=27
8731 04:50:50.508083 Byte1 end_step=30 best_step=27
8732 04:50:50.508214 Byte0 TX OE(2T, 0.5T) = (3, 3)
8733 04:50:50.508295 Byte1 TX OE(2T, 0.5T) = (3, 3)
8734 04:50:50.508373
8735 04:50:50.508451
8736 04:50:50.508532 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8737 04:50:50.508611 CH1 RK0: MR19=303, MR18=1523
8738 04:50:50.508691 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8739 04:50:50.508771
8740 04:50:50.508850 ----->DramcWriteLeveling(PI) begin...
8741 04:50:50.508930 ==
8742 04:50:50.509016 Dram Type= 6, Freq= 0, CH_1, rank 1
8743 04:50:50.509097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8744 04:50:50.509157 ==
8745 04:50:50.509209 Write leveling (Byte 0): 24 => 24
8746 04:50:50.509260 Write leveling (Byte 1): 29 => 29
8747 04:50:50.509310 DramcWriteLeveling(PI) end<-----
8748 04:50:50.509360
8749 04:50:50.509410 ==
8750 04:50:50.509460 Dram Type= 6, Freq= 0, CH_1, rank 1
8751 04:50:50.509510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8752 04:50:50.509561 ==
8753 04:50:50.509612 [Gating] SW mode calibration
8754 04:50:50.509662 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8755 04:50:50.509713 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8756 04:50:50.509763 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 04:50:50.509813 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 04:50:50.509864 1 4 8 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
8759 04:50:50.509914 1 4 12 | B1->B0 | 3434 2525 | 0 1 | (0 0) (0 0)
8760 04:50:50.509995 1 4 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8761 04:50:50.510074 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 04:50:50.510124 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 04:50:50.510174 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 04:50:50.510229 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 04:50:50.510290 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 04:50:50.510350 1 5 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 0)
8767 04:50:50.510411 1 5 12 | B1->B0 | 2323 3131 | 0 0 | (1 0) (1 1)
8768 04:50:50.510470 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 04:50:50.510542 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 04:50:50.510628 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 04:50:50.510911 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 04:50:50.510998 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 04:50:50.511129 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 04:50:50.511215 1 6 8 | B1->B0 | 3939 2424 | 0 0 | (0 0) (0 0)
8775 04:50:50.511306 1 6 12 | B1->B0 | 4646 3a3a | 0 0 | (0 0) (0 0)
8776 04:50:50.511393 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8777 04:50:50.511479 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 04:50:50.511561 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 04:50:50.511642 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 04:50:50.511723 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 04:50:50.511816 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 04:50:50.511895 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8783 04:50:50.511974 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8784 04:50:50.512053 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8785 04:50:50.512132 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 04:50:50.512211 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 04:50:50.512290 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 04:50:50.512369 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 04:50:50.512449 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 04:50:50.512527 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 04:50:50.512628 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 04:50:50.512731 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 04:50:50.512812 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 04:50:50.512892 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 04:50:50.512971 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 04:50:50.513051 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 04:50:50.513130 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8798 04:50:50.513209 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 04:50:50.513288 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8800 04:50:50.513383 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 04:50:50.513463 Total UI for P1: 0, mck2ui 16
8802 04:50:50.513556 best dqsien dly found for B0: ( 1, 9, 12)
8803 04:50:50.513636 Total UI for P1: 0, mck2ui 16
8804 04:50:50.513715 best dqsien dly found for B1: ( 1, 9, 12)
8805 04:50:50.513794 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8806 04:50:50.513874 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8807 04:50:50.513978
8808 04:50:50.514060 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8809 04:50:50.514112 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8810 04:50:50.514163 [Gating] SW calibration Done
8811 04:50:50.514213 ==
8812 04:50:50.514263 Dram Type= 6, Freq= 0, CH_1, rank 1
8813 04:50:50.514314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 04:50:50.514364 ==
8815 04:50:50.514414 RX Vref Scan: 0
8816 04:50:50.514464
8817 04:50:50.514514 RX Vref 0 -> 0, step: 1
8818 04:50:50.514564
8819 04:50:50.514614 RX Delay 0 -> 252, step: 8
8820 04:50:50.514664 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8821 04:50:50.514714 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8822 04:50:50.514764 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8823 04:50:50.514814 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8824 04:50:50.514863 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8825 04:50:50.514913 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8826 04:50:50.514963 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8827 04:50:50.515013 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8828 04:50:50.515062 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8829 04:50:50.515112 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8830 04:50:50.515161 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8831 04:50:50.515211 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8832 04:50:50.515261 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8833 04:50:50.515311 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8834 04:50:50.515360 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8835 04:50:50.515410 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8836 04:50:50.515460 ==
8837 04:50:50.515509 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 04:50:50.515559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 04:50:50.515610 ==
8840 04:50:50.515660 DQS Delay:
8841 04:50:50.515710 DQS0 = 0, DQS1 = 0
8842 04:50:50.515759 DQM Delay:
8843 04:50:50.515809 DQM0 = 139, DQM1 = 132
8844 04:50:50.515859 DQ Delay:
8845 04:50:50.515909 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8846 04:50:50.515959 DQ4 =139, DQ5 =151, DQ6 =147, DQ7 =139
8847 04:50:50.516009 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8848 04:50:50.516060 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8849 04:50:50.516110
8850 04:50:50.516159
8851 04:50:50.516209 ==
8852 04:50:50.516259 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 04:50:50.516309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 04:50:50.516359 ==
8855 04:50:50.516409
8856 04:50:50.516459
8857 04:50:50.516509 TX Vref Scan disable
8858 04:50:50.516559 == TX Byte 0 ==
8859 04:50:50.516608 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8860 04:50:50.516659 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8861 04:50:50.516709 == TX Byte 1 ==
8862 04:50:50.516760 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8863 04:50:50.516810 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8864 04:50:50.516860 ==
8865 04:50:50.516910 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 04:50:50.516960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 04:50:50.517011 ==
8868 04:50:50.517060
8869 04:50:50.517110 TX Vref early break, caculate TX vref
8870 04:50:50.517161 TX Vref=16, minBit 9, minWin=23, winSum=381
8871 04:50:50.517211 TX Vref=18, minBit 9, minWin=23, winSum=390
8872 04:50:50.517261 TX Vref=20, minBit 10, minWin=24, winSum=405
8873 04:50:50.517311 TX Vref=22, minBit 13, minWin=23, winSum=408
8874 04:50:50.517362 TX Vref=24, minBit 13, minWin=24, winSum=419
8875 04:50:50.517412 TX Vref=26, minBit 13, minWin=25, winSum=427
8876 04:50:50.517461 TX Vref=28, minBit 10, minWin=25, winSum=423
8877 04:50:50.517511 TX Vref=30, minBit 10, minWin=25, winSum=422
8878 04:50:50.517562 TX Vref=32, minBit 9, minWin=24, winSum=409
8879 04:50:50.517611 TX Vref=34, minBit 10, minWin=23, winSum=403
8880 04:50:50.517853 [TxChooseVref] Worse bit 13, Min win 25, Win sum 427, Final Vref 26
8881 04:50:50.517934
8882 04:50:50.518041 Final TX Range 0 Vref 26
8883 04:50:50.518092
8884 04:50:50.518142 ==
8885 04:50:50.518193 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 04:50:50.518244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 04:50:50.518295 ==
8888 04:50:50.518345
8889 04:50:50.518395
8890 04:50:50.518445 TX Vref Scan disable
8891 04:50:50.518495 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8892 04:50:50.518545 == TX Byte 0 ==
8893 04:50:50.518595 u2DelayCellOfst[0]=13 cells (4 PI)
8894 04:50:50.518645 u2DelayCellOfst[1]=10 cells (3 PI)
8895 04:50:50.518694 u2DelayCellOfst[2]=0 cells (0 PI)
8896 04:50:50.518744 u2DelayCellOfst[3]=3 cells (1 PI)
8897 04:50:50.518794 u2DelayCellOfst[4]=6 cells (2 PI)
8898 04:50:50.518843 u2DelayCellOfst[5]=17 cells (5 PI)
8899 04:50:50.518892 u2DelayCellOfst[6]=17 cells (5 PI)
8900 04:50:50.518942 u2DelayCellOfst[7]=3 cells (1 PI)
8901 04:50:50.518991 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8902 04:50:50.519041 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8903 04:50:50.519091 == TX Byte 1 ==
8904 04:50:50.519141 u2DelayCellOfst[8]=0 cells (0 PI)
8905 04:50:50.519190 u2DelayCellOfst[9]=6 cells (2 PI)
8906 04:50:50.519239 u2DelayCellOfst[10]=10 cells (3 PI)
8907 04:50:50.519289 u2DelayCellOfst[11]=3 cells (1 PI)
8908 04:50:50.519347 u2DelayCellOfst[12]=13 cells (4 PI)
8909 04:50:50.519399 u2DelayCellOfst[13]=13 cells (4 PI)
8910 04:50:50.519448 u2DelayCellOfst[14]=17 cells (5 PI)
8911 04:50:50.519498 u2DelayCellOfst[15]=13 cells (4 PI)
8912 04:50:50.519548 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8913 04:50:50.519598 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8914 04:50:50.519648 DramC Write-DBI on
8915 04:50:50.519698 ==
8916 04:50:50.519748 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 04:50:50.519799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 04:50:50.519849 ==
8919 04:50:50.519899
8920 04:50:50.519949
8921 04:50:50.519998 TX Vref Scan disable
8922 04:50:50.520048 == TX Byte 0 ==
8923 04:50:50.520098 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8924 04:50:50.520148 == TX Byte 1 ==
8925 04:50:50.520198 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8926 04:50:50.520248 DramC Write-DBI off
8927 04:50:50.520297
8928 04:50:50.520346 [DATLAT]
8929 04:50:50.520395 Freq=1600, CH1 RK1
8930 04:50:50.768024
8931 04:50:50.768541 DATLAT Default: 0xf
8932 04:50:50.768894 0, 0xFFFF, sum = 0
8933 04:50:50.769300 1, 0xFFFF, sum = 0
8934 04:50:50.769621 2, 0xFFFF, sum = 0
8935 04:50:50.769962 3, 0xFFFF, sum = 0
8936 04:50:50.770278 4, 0xFFFF, sum = 0
8937 04:50:50.770581 5, 0xFFFF, sum = 0
8938 04:50:50.770883 6, 0xFFFF, sum = 0
8939 04:50:50.771232 7, 0xFFFF, sum = 0
8940 04:50:50.771535 8, 0xFFFF, sum = 0
8941 04:50:50.771830 9, 0xFFFF, sum = 0
8942 04:50:50.772127 10, 0xFFFF, sum = 0
8943 04:50:50.772422 11, 0xFFFF, sum = 0
8944 04:50:50.772716 12, 0xFFFF, sum = 0
8945 04:50:50.773006 13, 0xFFFF, sum = 0
8946 04:50:50.773354 14, 0x0, sum = 1
8947 04:50:50.773649 15, 0x0, sum = 2
8948 04:50:50.773961 16, 0x0, sum = 3
8949 04:50:50.774261 17, 0x0, sum = 4
8950 04:50:50.774556 best_step = 15
8951 04:50:50.774842
8952 04:50:50.775175 ==
8953 04:50:50.775474 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 04:50:50.775766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 04:50:50.776061 ==
8956 04:50:50.776351 RX Vref Scan: 0
8957 04:50:50.776635
8958 04:50:50.776921 RX Vref 0 -> 0, step: 1
8959 04:50:50.777251
8960 04:50:50.777540 RX Delay 19 -> 252, step: 4
8961 04:50:50.777831 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8962 04:50:50.778145 iDelay=195, Bit 1, Center 132 (87 ~ 178) 92
8963 04:50:50.778434 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8964 04:50:50.778724 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8965 04:50:50.779013 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8966 04:50:50.779346 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8967 04:50:50.779639 iDelay=195, Bit 6, Center 146 (99 ~ 194) 96
8968 04:50:50.779926 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8969 04:50:50.780214 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8970 04:50:50.780501 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8971 04:50:50.780790 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8972 04:50:50.781115 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8973 04:50:50.781414 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8974 04:50:50.781704 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8975 04:50:50.782049 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8976 04:50:50.782410 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8977 04:50:50.782706 ==
8978 04:50:50.782997 Dram Type= 6, Freq= 0, CH_1, rank 1
8979 04:50:50.783368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8980 04:50:50.783670 ==
8981 04:50:50.784013 DQS Delay:
8982 04:50:50.784308 DQS0 = 0, DQS1 = 0
8983 04:50:50.784596 DQM Delay:
8984 04:50:50.784883 DQM0 = 134, DQM1 = 130
8985 04:50:50.785172 DQ Delay:
8986 04:50:50.785603 DQ0 =138, DQ1 =132, DQ2 =120, DQ3 =132
8987 04:50:50.786100 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =132
8988 04:50:50.786422 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
8989 04:50:50.786718 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8990 04:50:50.787047
8991 04:50:50.787380
8992 04:50:50.787676
8993 04:50:50.787962 [DramC_TX_OE_Calibration] TA2
8994 04:50:50.788248 Original DQ_B0 (3 6) =30, OEN = 27
8995 04:50:50.788539 Original DQ_B1 (3 6) =30, OEN = 27
8996 04:50:50.788832 24, 0x0, End_B0=24 End_B1=24
8997 04:50:50.789129 25, 0x0, End_B0=25 End_B1=25
8998 04:50:50.789464 26, 0x0, End_B0=26 End_B1=26
8999 04:50:50.789763 27, 0x0, End_B0=27 End_B1=27
9000 04:50:50.790089 28, 0x0, End_B0=28 End_B1=28
9001 04:50:50.790385 29, 0x0, End_B0=29 End_B1=29
9002 04:50:50.790678 30, 0x0, End_B0=30 End_B1=30
9003 04:50:50.790970 31, 0x4545, End_B0=30 End_B1=30
9004 04:50:50.791260 Byte0 end_step=30 best_step=27
9005 04:50:50.791594 Byte1 end_step=30 best_step=27
9006 04:50:50.791882 Byte0 TX OE(2T, 0.5T) = (3, 3)
9007 04:50:50.792169 Byte1 TX OE(2T, 0.5T) = (3, 3)
9008 04:50:50.792458
9009 04:50:50.792745
9010 04:50:50.793030 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a05, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
9011 04:50:50.793324 CH1 RK1: MR19=303, MR18=1A05
9012 04:50:50.793658 CH1_RK1: MR19=0x303, MR18=0x1A05, DQSOSC=396, MR23=63, INC=23, DEC=15
9013 04:50:50.793970 [RxdqsGatingPostProcess] freq 1600
9014 04:50:50.794263 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9015 04:50:50.794553 best DQS0 dly(2T, 0.5T) = (1, 1)
9016 04:50:50.794841 best DQS1 dly(2T, 0.5T) = (1, 1)
9017 04:50:50.795130 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9018 04:50:50.795421 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9019 04:50:50.795710 best DQS0 dly(2T, 0.5T) = (1, 1)
9020 04:50:50.795997 best DQS1 dly(2T, 0.5T) = (1, 1)
9021 04:50:50.796282 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9022 04:50:50.796568 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9023 04:50:50.796855 Pre-setting of DQS Precalculation
9024 04:50:50.797572 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9025 04:50:50.797908 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9026 04:50:50.798243 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9027 04:50:50.798541
9028 04:50:50.798832
9029 04:50:50.799120 [Calibration Summary] 3200 Mbps
9030 04:50:50.799412 CH 0, Rank 0
9031 04:50:50.799667 SW Impedance : PASS
9032 04:50:50.799871 DUTY Scan : NO K
9033 04:50:50.800075 ZQ Calibration : PASS
9034 04:50:50.800278 Jitter Meter : NO K
9035 04:50:50.800485 CBT Training : PASS
9036 04:50:50.800693 Write leveling : PASS
9037 04:50:50.800903 RX DQS gating : PASS
9038 04:50:50.801112 RX DQ/DQS(RDDQC) : PASS
9039 04:50:50.801321 TX DQ/DQS : PASS
9040 04:50:50.801530 RX DATLAT : PASS
9041 04:50:50.801739 RX DQ/DQS(Engine): PASS
9042 04:50:50.801959 TX OE : PASS
9043 04:50:50.802173 All Pass.
9044 04:50:50.802383
9045 04:50:50.802589 CH 0, Rank 1
9046 04:50:50.802796 SW Impedance : PASS
9047 04:50:50.803004 DUTY Scan : NO K
9048 04:50:50.803210 ZQ Calibration : PASS
9049 04:50:50.803418 Jitter Meter : NO K
9050 04:50:50.803626 CBT Training : PASS
9051 04:50:50.803835 Write leveling : PASS
9052 04:50:50.804043 RX DQS gating : PASS
9053 04:50:50.804249 RX DQ/DQS(RDDQC) : PASS
9054 04:50:50.804459 TX DQ/DQS : PASS
9055 04:50:50.804650 RX DATLAT : PASS
9056 04:50:50.804805 RX DQ/DQS(Engine): PASS
9057 04:50:50.804958 TX OE : PASS
9058 04:50:50.805114 All Pass.
9059 04:50:50.805268
9060 04:50:50.805421 CH 1, Rank 0
9061 04:50:50.805576 SW Impedance : PASS
9062 04:50:50.805730 DUTY Scan : NO K
9063 04:50:50.805884 ZQ Calibration : PASS
9064 04:50:50.806048 Jitter Meter : NO K
9065 04:50:50.806232 CBT Training : PASS
9066 04:50:50.806385 Write leveling : PASS
9067 04:50:50.806539 RX DQS gating : PASS
9068 04:50:50.806695 RX DQ/DQS(RDDQC) : PASS
9069 04:50:50.806849 TX DQ/DQS : PASS
9070 04:50:50.807003 RX DATLAT : PASS
9071 04:50:50.807157 RX DQ/DQS(Engine): PASS
9072 04:50:50.807311 TX OE : PASS
9073 04:50:50.807466 All Pass.
9074 04:50:50.807619
9075 04:50:50.807773 CH 1, Rank 1
9076 04:50:50.807926 SW Impedance : PASS
9077 04:50:50.808101 DUTY Scan : NO K
9078 04:50:50.808260 ZQ Calibration : PASS
9079 04:50:50.808414 Jitter Meter : NO K
9080 04:50:50.808569 CBT Training : PASS
9081 04:50:50.808723 Write leveling : PASS
9082 04:50:50.808878 RX DQS gating : PASS
9083 04:50:50.809032 RX DQ/DQS(RDDQC) : PASS
9084 04:50:50.809187 TX DQ/DQS : PASS
9085 04:50:50.809342 RX DATLAT : PASS
9086 04:50:50.809566 RX DQ/DQS(Engine): PASS
9087 04:50:50.809762 TX OE : PASS
9088 04:50:50.809895 All Pass.
9089 04:50:50.810046
9090 04:50:50.810197 DramC Write-DBI on
9091 04:50:50.810323 PER_BANK_REFRESH: Hybrid Mode
9092 04:50:50.810448 TX_TRACKING: ON
9093 04:50:50.810572 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9094 04:50:50.810697 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9095 04:50:50.810822 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9096 04:50:50.810946 [FAST_K] Save calibration result to emmc
9097 04:50:50.811069 sync common calibartion params.
9098 04:50:50.811191 sync cbt_mode0:1, 1:1
9099 04:50:50.811312 dram_init: ddr_geometry: 2
9100 04:50:50.811433 dram_init: ddr_geometry: 2
9101 04:50:50.811554 dram_init: ddr_geometry: 2
9102 04:50:50.811676 0:dram_rank_size:100000000
9103 04:50:50.811803 1:dram_rank_size:100000000
9104 04:50:50.811928 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9105 04:50:50.812052 DFS_SHUFFLE_HW_MODE: ON
9106 04:50:50.812174 dramc_set_vcore_voltage set vcore to 725000
9107 04:50:50.812295 Read voltage for 1600, 0
9108 04:50:50.812416 Vio18 = 0
9109 04:50:50.812540 Vcore = 725000
9110 04:50:50.812661 Vdram = 0
9111 04:50:50.812784 Vddq = 0
9112 04:50:50.812905 Vmddr = 0
9113 04:50:50.813026 switch to 3200 Mbps bootup
9114 04:50:50.813149 [DramcRunTimeConfig]
9115 04:50:50.813271 PHYPLL
9116 04:50:50.813392 DPM_CONTROL_AFTERK: ON
9117 04:50:50.813515 PER_BANK_REFRESH: ON
9118 04:50:50.813637 REFRESH_OVERHEAD_REDUCTION: ON
9119 04:50:50.813760 CMD_PICG_NEW_MODE: OFF
9120 04:50:50.813882 XRTWTW_NEW_MODE: ON
9121 04:50:50.814120 XRTRTR_NEW_MODE: ON
9122 04:50:50.814260 TX_TRACKING: ON
9123 04:50:50.814384 RDSEL_TRACKING: OFF
9124 04:50:50.814505 DQS Precalculation for DVFS: ON
9125 04:50:50.814632 RX_TRACKING: OFF
9126 04:50:50.814733 HW_GATING DBG: ON
9127 04:50:50.814835 ZQCS_ENABLE_LP4: ON
9128 04:50:50.814935 RX_PICG_NEW_MODE: ON
9129 04:50:50.815037 TX_PICG_NEW_MODE: ON
9130 04:50:50.815137 ENABLE_RX_DCM_DPHY: ON
9131 04:50:50.815239 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9132 04:50:50.815340 DUMMY_READ_FOR_TRACKING: OFF
9133 04:50:50.815441 !!! SPM_CONTROL_AFTERK: OFF
9134 04:50:50.815551 !!! SPM could not control APHY
9135 04:50:50.815654 IMPEDANCE_TRACKING: ON
9136 04:50:50.815754 TEMP_SENSOR: ON
9137 04:50:50.815854 HW_SAVE_FOR_SR: OFF
9138 04:50:50.815956 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9139 04:50:50.816057 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9140 04:50:50.816158 Read ODT Tracking: ON
9141 04:50:50.816258 Refresh Rate DeBounce: ON
9142 04:50:50.816358 DFS_NO_QUEUE_FLUSH: ON
9143 04:50:50.816459 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9144 04:50:50.816560 ENABLE_DFS_RUNTIME_MRW: OFF
9145 04:50:50.816660 DDR_RESERVE_NEW_MODE: ON
9146 04:50:50.816761 MR_CBT_SWITCH_FREQ: ON
9147 04:50:50.816862 =========================
9148 04:50:50.816963 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9149 04:50:50.817066 dram_init: ddr_geometry: 2
9150 04:50:50.817166 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9151 04:50:50.817269 dram_init: dram init end (result: 0)
9152 04:50:50.817371 DRAM-K: Full calibration passed in 24512 msecs
9153 04:50:50.817473 MRC: failed to locate region type 0.
9154 04:50:50.817574 DRAM rank0 size:0x100000000,
9155 04:50:50.817675 DRAM rank1 size=0x100000000
9156 04:50:50.817776 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9157 04:50:50.817880 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9158 04:50:50.817996 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9159 04:50:50.818101 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9160 04:50:50.818203 DRAM rank0 size:0x100000000,
9161 04:50:50.818304 DRAM rank1 size=0x100000000
9162 04:50:50.818404 CBMEM:
9163 04:50:50.818505 IMD: root @ 0xfffff000 254 entries.
9164 04:50:50.818842 IMD: root @ 0xffffec00 62 entries.
9165 04:50:50.818957 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9166 04:50:50.819062 WARNING: RO_VPD is uninitialized or empty.
9167 04:50:50.819166 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9168 04:50:50.819269 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9169 04:50:50.819373 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9170 04:50:50.819475 BS: romstage times (exec / console): total (unknown) / 24011 ms
9171 04:50:50.819587
9172 04:50:50.819674
9173 04:50:50.819759 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9174 04:50:50.819847 ARM64: Exception handlers installed.
9175 04:50:50.819933 ARM64: Testing exception
9176 04:50:50.820019 ARM64: Done test exception
9177 04:50:50.820106 Enumerating buses...
9178 04:50:50.820191 Show all devs... Before device enumeration.
9179 04:50:50.820278 Root Device: enabled 1
9180 04:50:50.820385 CPU_CLUSTER: 0: enabled 1
9181 04:50:50.820474 CPU: 00: enabled 1
9182 04:50:50.820561 Compare with tree...
9183 04:50:50.820647 Root Device: enabled 1
9184 04:50:50.820733 CPU_CLUSTER: 0: enabled 1
9185 04:50:50.820819 CPU: 00: enabled 1
9186 04:50:50.820905 Root Device scanning...
9187 04:50:50.820991 scan_static_bus for Root Device
9188 04:50:50.821077 CPU_CLUSTER: 0 enabled
9189 04:50:50.821164 scan_static_bus for Root Device done
9190 04:50:50.821251 scan_bus: bus Root Device finished in 8 msecs
9191 04:50:50.821337 done
9192 04:50:50.821424 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9193 04:50:50.821512 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9194 04:50:50.821600 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9195 04:50:50.821687 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9196 04:50:50.821774 Allocating resources...
9197 04:50:50.821861 Reading resources...
9198 04:50:50.821958 Root Device read_resources bus 0 link: 0
9199 04:50:50.822049 DRAM rank0 size:0x100000000,
9200 04:50:50.822135 DRAM rank1 size=0x100000000
9201 04:50:50.822223 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9202 04:50:50.822310 CPU: 00 missing read_resources
9203 04:50:50.822420 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9204 04:50:50.822509 Root Device read_resources bus 0 link: 0 done
9205 04:50:50.822595 Done reading resources.
9206 04:50:50.822681 Show resources in subtree (Root Device)...After reading.
9207 04:50:50.822769 Root Device child on link 0 CPU_CLUSTER: 0
9208 04:50:50.822855 CPU_CLUSTER: 0 child on link 0 CPU: 00
9209 04:50:50.822943 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9210 04:50:50.823030 CPU: 00
9211 04:50:50.823116 Root Device assign_resources, bus 0 link: 0
9212 04:50:50.823203 CPU_CLUSTER: 0 missing set_resources
9213 04:50:50.823289 Root Device assign_resources, bus 0 link: 0 done
9214 04:50:50.823376 Done setting resources.
9215 04:50:50.823463 Show resources in subtree (Root Device)...After assigning values.
9216 04:50:50.823549 Root Device child on link 0 CPU_CLUSTER: 0
9217 04:50:50.823636 CPU_CLUSTER: 0 child on link 0 CPU: 00
9218 04:50:50.823723 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9219 04:50:50.823811 CPU: 00
9220 04:50:50.823897 Done allocating resources.
9221 04:50:50.823984 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9222 04:50:50.824071 Enabling resources...
9223 04:50:50.824157 done.
9224 04:50:50.824244 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9225 04:50:50.824331 Initializing devices...
9226 04:50:50.824416 Root Device init
9227 04:50:50.824503 init hardware done!
9228 04:50:50.824595 0x00000018: ctrlr->caps
9229 04:50:50.824673 52.000 MHz: ctrlr->f_max
9230 04:50:50.824752 0.400 MHz: ctrlr->f_min
9231 04:50:50.824830 0x40ff8080: ctrlr->voltages
9232 04:50:50.824908 sclk: 390625
9233 04:50:50.824983 Bus Width = 1
9234 04:50:50.825059 sclk: 390625
9235 04:50:50.825134 Bus Width = 1
9236 04:50:50.825209 Early init status = 3
9237 04:50:50.825284 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9238 04:50:50.825361 in-header: 03 fc 00 00 01 00 00 00
9239 04:50:50.825436 in-data: 00
9240 04:50:50.825512 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9241 04:50:50.825589 in-header: 03 fd 00 00 00 00 00 00
9242 04:50:50.825664 in-data:
9243 04:50:50.825740 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9244 04:50:50.825817 in-header: 03 fc 00 00 01 00 00 00
9245 04:50:50.825892 in-data: 00
9246 04:50:50.825979 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9247 04:50:50.826058 in-header: 03 fd 00 00 00 00 00 00
9248 04:50:50.826135 in-data:
9249 04:50:50.826211 [SSUSB] Setting up USB HOST controller...
9250 04:50:50.826287 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9251 04:50:50.826364 [SSUSB] phy power-on done.
9252 04:50:50.826440 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9253 04:50:50.826517 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9254 04:50:50.826593 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9255 04:50:50.826670 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9256 04:50:50.826746 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9257 04:50:50.826822 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9258 04:50:50.826898 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9259 04:50:50.826975 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9260 04:50:50.827050 SPM: binary array size = 0x9dc
9261 04:50:50.827126 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9262 04:50:50.827202 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9263 04:50:50.827279 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9264 04:50:50.827355 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9265 04:50:50.827432 configure_display: Starting display init
9266 04:50:50.827508 anx7625_power_on_init: Init interface.
9267 04:50:50.827798 anx7625_disable_pd_protocol: Disabled PD feature.
9268 04:50:50.827884 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9269 04:50:50.827962 anx7625_start_dp_work: Secure OCM version=00
9270 04:50:50.828039 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9271 04:50:50.828117 sp_tx_get_edid_block: EDID Block = 1
9272 04:50:50.828194 Extracted contents:
9273 04:50:50.828270 header: 00 ff ff ff ff ff ff 00
9274 04:50:50.828347 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9275 04:50:50.828424 version: 01 04
9276 04:50:50.828504 basic params: 95 1f 11 78 0a
9277 04:50:50.828581 chroma info: 76 90 94 55 54 90 27 21 50 54
9278 04:50:50.828657 established: 00 00 00
9279 04:50:50.828733 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9280 04:50:50.828810 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9281 04:50:50.828887 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9282 04:50:50.828963 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9283 04:50:50.829040 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9284 04:50:50.829116 extensions: 00
9285 04:50:50.829191 checksum: fb
9286 04:50:50.829266
9287 04:50:50.829342 Manufacturer: IVO Model 57d Serial Number 0
9288 04:50:50.829418 Made week 0 of 2020
9289 04:50:50.829493 EDID version: 1.4
9290 04:50:50.829576 Digital display
9291 04:50:50.829643 6 bits per primary color channel
9292 04:50:50.829712 DisplayPort interface
9293 04:50:50.829780 Maximum image size: 31 cm x 17 cm
9294 04:50:50.829845 Gamma: 220%
9295 04:50:50.829911 Check DPMS levels
9296 04:50:50.829989 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9297 04:50:50.830056 First detailed timing is preferred timing
9298 04:50:50.830124 Established timings supported:
9299 04:50:50.830189 Standard timings supported:
9300 04:50:50.830254 Detailed timings
9301 04:50:50.830319 Hex of detail: 383680a07038204018303c0035ae10000019
9302 04:50:50.830384 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9303 04:50:50.830450 0780 0798 07c8 0820 hborder 0
9304 04:50:50.830515 0438 043b 0447 0458 vborder 0
9305 04:50:50.830581 -hsync -vsync
9306 04:50:50.830646 Did detailed timing
9307 04:50:50.830711 Hex of detail: 000000000000000000000000000000000000
9308 04:50:50.830777 Manufacturer-specified data, tag 0
9309 04:50:50.830842 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9310 04:50:50.830908 ASCII string: InfoVision
9311 04:50:50.830973 Hex of detail: 000000fe00523134304e574635205248200a
9312 04:50:50.831037 ASCII string: R140NWF5 RH
9313 04:50:50.831102 Checksum
9314 04:50:50.831167 Checksum: 0xfb (valid)
9315 04:50:50.831233 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9316 04:50:50.831297 DSI data_rate: 832800000 bps
9317 04:50:50.831362 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9318 04:50:50.831428 anx7625_parse_edid: pixelclock(138800).
9319 04:50:50.831494 hactive(1920), hsync(48), hfp(24), hbp(88)
9320 04:50:50.831559 vactive(1080), vsync(12), vfp(3), vbp(17)
9321 04:50:50.831624 anx7625_dsi_config: config dsi.
9322 04:50:50.831689 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9323 04:50:50.831754 anx7625_dsi_config: success to config DSI
9324 04:50:50.831820 anx7625_dp_start: MIPI phy setup OK.
9325 04:50:50.831884 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9326 04:50:50.831950 mtk_ddp_mode_set invalid vrefresh 60
9327 04:50:50.832015 main_disp_path_setup
9328 04:50:50.832080 ovl_layer_smi_id_en
9329 04:50:50.832145 ovl_layer_smi_id_en
9330 04:50:50.832210 ccorr_config
9331 04:50:50.832275 aal_config
9332 04:50:50.832341 gamma_config
9333 04:50:50.832406 postmask_config
9334 04:50:50.832470 dither_config
9335 04:50:50.832535 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9336 04:50:50.832601 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9337 04:50:50.832667 Root Device init finished in 555 msecs
9338 04:50:50.832733 CPU_CLUSTER: 0 init
9339 04:50:50.832797 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9340 04:50:50.832864 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9341 04:50:50.832929 APU_MBOX 0x190000b0 = 0x10001
9342 04:50:50.832994 APU_MBOX 0x190001b0 = 0x10001
9343 04:50:50.833059 APU_MBOX 0x190005b0 = 0x10001
9344 04:50:50.833123 APU_MBOX 0x190006b0 = 0x10001
9345 04:50:50.833188 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9346 04:50:50.833253 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9347 04:50:50.833319 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9348 04:50:50.833385 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9349 04:50:50.833451 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9350 04:50:50.833516 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9351 04:50:50.833582 CPU_CLUSTER: 0 init finished in 81 msecs
9352 04:50:50.833648 Devices initialized
9353 04:50:50.833713 Show all devs... After init.
9354 04:50:50.833777 Root Device: enabled 1
9355 04:50:50.833841 CPU_CLUSTER: 0: enabled 1
9356 04:50:50.833906 CPU: 00: enabled 1
9357 04:50:50.833977 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9358 04:50:50.834043 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9359 04:50:50.834109 ELOG: NV offset 0x57f000 size 0x1000
9360 04:50:50.834173 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9361 04:50:50.834239 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9362 04:50:50.834305 ELOG: Event(17) added with size 13 at 2024-02-04 04:50:07 UTC
9363 04:50:50.834371 out: cmd=0x121: 03 db 21 01 00 00 00 00
9364 04:50:50.834436 in-header: 03 26 00 00 2c 00 00 00
9365 04:50:50.834503 in-data: 39 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9366 04:50:50.834783 ELOG: Event(A1) added with size 10 at 2024-02-04 04:50:07 UTC
9367 04:50:50.834854 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9368 04:50:50.834918 ELOG: Event(A0) added with size 9 at 2024-02-04 04:50:07 UTC
9369 04:50:50.834978 elog_add_boot_reason: Logged dev mode boot
9370 04:50:50.835038 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9371 04:50:50.835098 Finalize devices...
9372 04:50:50.835157 Devices finalized
9373 04:50:50.835217 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9374 04:50:50.835276 Writing coreboot table at 0xffe64000
9375 04:50:50.835335 0. 000000000010a000-0000000000113fff: RAMSTAGE
9376 04:50:50.835394 1. 0000000040000000-00000000400fffff: RAM
9377 04:50:50.835454 2. 0000000040100000-000000004032afff: RAMSTAGE
9378 04:50:50.835513 3. 000000004032b000-00000000545fffff: RAM
9379 04:50:50.835572 4. 0000000054600000-000000005465ffff: BL31
9380 04:50:50.835631 5. 0000000054660000-00000000ffe63fff: RAM
9381 04:50:50.835690 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9382 04:50:50.835749 7. 0000000100000000-000000023fffffff: RAM
9383 04:50:50.835807 Passing 5 GPIOs to payload:
9384 04:50:50.835866 NAME | PORT | POLARITY | VALUE
9385 04:50:50.835925 EC in RW | 0x000000aa | low | undefined
9386 04:50:50.835984 EC interrupt | 0x00000005 | low | undefined
9387 04:50:50.836044 TPM interrupt | 0x000000ab | high | undefined
9388 04:50:50.836103 SD card detect | 0x00000011 | high | undefined
9389 04:50:50.836163 speaker enable | 0x00000093 | high | undefined
9390 04:50:50.836221 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9391 04:50:50.836281 in-header: 03 f9 00 00 02 00 00 00
9392 04:50:50.836339 in-data: 02 00
9393 04:50:50.836398 ADC[4]: Raw value=901401 ID=7
9394 04:50:50.836457 ADC[3]: Raw value=213179 ID=1
9395 04:50:50.836515 RAM Code: 0x71
9396 04:50:50.836573 ADC[6]: Raw value=74502 ID=0
9397 04:50:50.836632 ADC[5]: Raw value=212810 ID=1
9398 04:50:50.836692 SKU Code: 0x1
9399 04:50:50.836751 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3234
9400 04:50:50.836810 coreboot table: 964 bytes.
9401 04:50:50.836868 IMD ROOT 0. 0xfffff000 0x00001000
9402 04:50:50.836928 IMD SMALL 1. 0xffffe000 0x00001000
9403 04:50:50.836988 RO MCACHE 2. 0xffffc000 0x00001104
9404 04:50:50.837047 CONSOLE 3. 0xfff7c000 0x00080000
9405 04:50:50.837106 FMAP 4. 0xfff7b000 0x00000452
9406 04:50:50.837165 TIME STAMP 5. 0xfff7a000 0x00000910
9407 04:50:50.837225 VBOOT WORK 6. 0xfff66000 0x00014000
9408 04:50:50.837284 RAMOOPS 7. 0xffe66000 0x00100000
9409 04:50:50.837342 COREBOOT 8. 0xffe64000 0x00002000
9410 04:50:50.837400 IMD small region:
9411 04:50:50.837459 IMD ROOT 0. 0xffffec00 0x00000400
9412 04:50:50.837518 VPD 1. 0xffffeb80 0x0000006c
9413 04:50:50.837577 MMC STATUS 2. 0xffffeb60 0x00000004
9414 04:50:50.837636 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9415 04:50:50.837695 Probing TPM: done!
9416 04:50:50.837754 Connected to device vid:did:rid of 1ae0:0028:00
9417 04:50:50.837813 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9418 04:50:50.837873 Initialized TPM device CR50 revision 0
9419 04:50:50.837932 Checking cr50 for pending updates
9420 04:50:50.837998 Reading cr50 TPM mode
9421 04:50:50.838057 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9422 04:50:50.838117 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9423 04:50:50.838176 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9424 04:50:50.838236 Checking segment from ROM address 0x40100000
9425 04:50:50.838294 Checking segment from ROM address 0x4010001c
9426 04:50:50.838353 Loading segment from ROM address 0x40100000
9427 04:50:50.838412 code (compression=0)
9428 04:50:50.838471 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9429 04:50:50.838530 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9430 04:50:50.838589 it's not compressed!
9431 04:50:50.838648 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9432 04:50:50.838707 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9433 04:50:50.838766 Loading segment from ROM address 0x4010001c
9434 04:50:50.838826 Entry Point 0x80000000
9435 04:50:50.838884 Loaded segments
9436 04:50:50.838943 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9437 04:50:50.839001 Jumping to boot code at 0x80000000(0xffe64000)
9438 04:50:50.839061 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9439 04:50:50.839121 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9440 04:50:50.839180 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9441 04:50:50.839239 Checking segment from ROM address 0x40100000
9442 04:50:50.839297 Checking segment from ROM address 0x4010001c
9443 04:50:50.839356 Loading segment from ROM address 0x40100000
9444 04:50:50.839414 code (compression=1)
9445 04:50:50.839473 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9446 04:50:50.839544 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9447 04:50:50.839598 using LZMA
9448 04:50:50.839651 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9449 04:50:50.839709 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9450 04:50:50.839775 Loading segment from ROM address 0x4010001c
9451 04:50:50.839834 Entry Point 0x54601000
9452 04:50:50.839887 Loaded segments
9453 04:50:50.839941 NOTICE: MT8192 bl31_setup
9454 04:50:50.839994 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9455 04:50:50.840049 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9456 04:50:50.840103 WARNING: region 0:
9457 04:50:50.840350 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 04:50:50.840411 WARNING: region 1:
9459 04:50:50.840466 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9460 04:50:50.840521 WARNING: region 2:
9461 04:50:50.840575 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9462 04:50:50.840630 WARNING: region 3:
9463 04:50:50.840683 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9464 04:50:50.840738 WARNING: region 4:
9465 04:50:50.840792 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9466 04:50:50.840846 WARNING: region 5:
9467 04:50:50.840899 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 04:50:50.840952 WARNING: region 6:
9469 04:50:50.841005 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 04:50:50.841058 WARNING: region 7:
9471 04:50:50.841111 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 04:50:50.841165 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9473 04:50:50.841219 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9474 04:50:50.841273 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9475 04:50:50.841327 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9476 04:50:50.841380 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9477 04:50:50.841433 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9478 04:50:50.841486 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9479 04:50:50.841540 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9480 04:50:50.841593 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9481 04:50:50.841646 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9482 04:50:50.841704 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9483 04:50:50.841767 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9484 04:50:50.841827 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9485 04:50:50.841881 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9486 04:50:50.841934 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9487 04:50:50.841994 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9488 04:50:50.842048 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9489 04:50:50.842101 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9490 04:50:50.842155 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9491 04:50:50.842209 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9492 04:50:50.842262 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9493 04:50:50.842315 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9494 04:50:50.842369 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9495 04:50:50.842422 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9496 04:50:50.842476 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9497 04:50:50.842529 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9498 04:50:50.842582 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9499 04:50:50.842635 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9500 04:50:50.842688 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9501 04:50:50.842742 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9502 04:50:50.842795 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9503 04:50:50.842848 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9504 04:50:50.842901 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9505 04:50:50.842955 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9506 04:50:50.843014 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9507 04:50:50.843068 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9508 04:50:50.843121 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9509 04:50:50.843174 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9510 04:50:50.843227 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9511 04:50:50.843280 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9512 04:50:50.843333 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9513 04:50:50.843386 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9514 04:50:50.843440 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9515 04:50:50.843493 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9516 04:50:50.843546 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9517 04:50:50.843599 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9518 04:50:50.843653 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9519 04:50:50.843706 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9520 04:50:50.843759 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9521 04:50:50.843813 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9522 04:50:50.843866 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9523 04:50:50.843919 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9524 04:50:50.843973 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9525 04:50:50.844026 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9526 04:50:50.844079 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9527 04:50:50.844131 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9528 04:50:50.844185 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9529 04:50:50.844238 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9530 04:50:50.844291 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9531 04:50:50.844345 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9532 04:50:50.844398 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9533 04:50:50.844452 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9534 04:50:50.844505 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9535 04:50:50.844557 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9536 04:50:50.844621 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9537 04:50:50.844672 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9538 04:50:50.844724 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9539 04:50:50.844966 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9540 04:50:50.845023 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9541 04:50:50.845076 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9542 04:50:50.845128 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9543 04:50:50.845180 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9544 04:50:50.845232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9545 04:50:50.845297 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9546 04:50:50.845350 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9547 04:50:50.845402 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9548 04:50:50.845453 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9549 04:50:50.845505 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9550 04:50:50.845556 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9551 04:50:50.845607 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9552 04:50:50.845658 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9553 04:50:50.845709 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9554 04:50:50.845759 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9555 04:50:50.845810 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9556 04:50:50.845861 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9557 04:50:50.845912 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9558 04:50:50.845969 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9559 04:50:50.846021 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9560 04:50:50.846072 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9561 04:50:50.846123 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9562 04:50:50.846174 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9563 04:50:50.846226 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9564 04:50:50.846277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9565 04:50:50.846328 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9566 04:50:50.846379 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9567 04:50:50.846453 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9568 04:50:50.846510 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9569 04:50:50.846563 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9570 04:50:50.846626 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9571 04:50:50.846697 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9572 04:50:50.846755 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9573 04:50:50.846819 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9574 04:50:50.846889 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9575 04:50:50.846948 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9576 04:50:50.847006 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9577 04:50:50.847067 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9578 04:50:50.847124 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9579 04:50:50.847176 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9580 04:50:50.847228 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9581 04:50:50.847279 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9582 04:50:50.847331 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9583 04:50:50.847382 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9584 04:50:50.847433 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9585 04:50:50.847484 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9586 04:50:50.847536 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9587 04:50:50.847587 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9588 04:50:50.847638 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9589 04:50:50.847690 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9590 04:50:50.847741 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9591 04:50:50.847793 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9592 04:50:50.847844 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9593 04:50:50.847895 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9594 04:50:50.847946 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9595 04:50:50.847997 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9596 04:50:50.848048 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9597 04:50:50.848099 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9598 04:50:50.848150 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9599 04:50:50.848201 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9600 04:50:50.848251 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9601 04:50:50.848303 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9602 04:50:50.848354 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9603 04:50:50.848405 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9604 04:50:50.848456 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9605 04:50:50.848507 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9606 04:50:50.848558 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9607 04:50:50.848609 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9608 04:50:50.848661 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9609 04:50:50.848712 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9610 04:50:50.848763 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9611 04:50:50.848814 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9612 04:50:50.848907 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9613 04:50:50.848989 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9614 04:50:50.849070 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9615 04:50:50.849344 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9616 04:50:50.849430 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9617 04:50:50.849513 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9618 04:50:50.849598 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9619 04:50:50.849679 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9620 04:50:50.849761 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9621 04:50:50.849842 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9622 04:50:50.849923 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9623 04:50:50.850011 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9624 04:50:50.850093 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9625 04:50:50.850174 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9626 04:50:50.850254 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9627 04:50:50.850335 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9628 04:50:50.850416 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9629 04:50:50.850496 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9630 04:50:50.850577 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9631 04:50:50.850658 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9632 04:50:50.850739 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9633 04:50:50.850820 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9634 04:50:50.850926 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9635 04:50:50.850981 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9636 04:50:50.851033 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9637 04:50:50.851085 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9638 04:50:50.851136 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9639 04:50:50.851188 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9640 04:50:50.851239 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9641 04:50:50.851290 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9642 04:50:50.851341 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9643 04:50:50.851393 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9644 04:50:50.851444 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9645 04:50:50.851495 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9646 04:50:50.851547 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9647 04:50:50.851598 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9648 04:50:50.851649 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9649 04:50:50.851700 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9650 04:50:50.851751 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9651 04:50:50.851803 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9652 04:50:50.851854 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9653 04:50:50.851905 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9654 04:50:50.851956 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9655 04:50:50.852007 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9656 04:50:50.852057 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9657 04:50:50.852108 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9658 04:50:50.852158 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9659 04:50:50.852209 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9660 04:50:50.852260 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9661 04:50:50.852311 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9662 04:50:50.852362 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9663 04:50:50.852413 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9664 04:50:50.852463 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9665 04:50:50.852514 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9666 04:50:50.852565 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9667 04:50:50.852616 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9668 04:50:50.852667 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9669 04:50:50.852718 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9670 04:50:50.852769 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9671 04:50:50.852820 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9672 04:50:50.852891 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9673 04:50:50.852974 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9674 04:50:50.853050 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9675 04:50:50.853105 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9676 04:50:50.853158 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9677 04:50:50.853209 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9678 04:50:50.853261 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9679 04:50:50.853313 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9680 04:50:50.853364 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9681 04:50:50.853415 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9682 04:50:50.853467 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9683 04:50:50.853518 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9684 04:50:50.853569 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9685 04:50:50.853620 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9686 04:50:50.853671 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9687 04:50:50.853722 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9688 04:50:50.853773 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9689 04:50:50.853823 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9690 04:50:50.853874 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9691 04:50:50.854154 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9692 04:50:50.854216 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9693 04:50:50.854270 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9694 04:50:50.854322 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9695 04:50:50.854374 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9696 04:50:50.854424 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9697 04:50:50.854476 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9698 04:50:50.854528 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9699 04:50:50.854579 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9700 04:50:50.854630 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9701 04:50:50.854682 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9702 04:50:50.854734 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9703 04:50:50.854786 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9704 04:50:50.854837 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9705 04:50:50.854888 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9706 04:50:50.854939 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9707 04:50:50.854990 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9708 04:50:50.855041 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9709 04:50:50.855091 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9710 04:50:50.855142 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9711 04:50:50.855193 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9712 04:50:50.855245 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9713 04:50:50.855295 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9714 04:50:50.855346 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9715 04:50:50.855397 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9716 04:50:50.855448 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9717 04:50:50.855499 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9718 04:50:50.855550 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9719 04:50:50.855601 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9720 04:50:50.855651 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9721 04:50:50.855703 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9722 04:50:50.855753 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9723 04:50:50.855804 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9724 04:50:50.855855 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9725 04:50:50.855906 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9726 04:50:50.855956 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9727 04:50:50.856007 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9728 04:50:50.856058 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9729 04:50:50.856109 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9730 04:50:50.856160 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9731 04:50:50.856210 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9732 04:50:50.856261 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9733 04:50:50.856312 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9734 04:50:50.856362 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9735 04:50:50.856413 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9736 04:50:50.856464 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9737 04:50:50.856515 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9738 04:50:50.856566 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9739 04:50:50.856616 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9740 04:50:50.856667 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9741 04:50:50.856718 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9742 04:50:50.856768 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9743 04:50:50.856819 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9744 04:50:50.856869 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9745 04:50:50.856919 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9746 04:50:50.856970 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9747 04:50:50.857021 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9748 04:50:50.857072 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9749 04:50:50.857122 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9750 04:50:50.857173 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9751 04:50:50.857223 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9752 04:50:50.857278 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9753 04:50:50.857336 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9754 04:50:50.857387 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9755 04:50:50.857439 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9756 04:50:50.857489 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9757 04:50:50.857540 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9758 04:50:50.857591 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9759 04:50:50.857642 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9760 04:50:50.857693 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9761 04:50:50.857743 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9762 04:50:50.857795 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9763 04:50:50.857846 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9764 04:50:50.857896 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9765 04:50:50.857954 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9766 04:50:50.858006 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9767 04:50:50.858057 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9768 04:50:50.858108 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9769 04:50:50.858160 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9770 04:50:50.858400 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9771 04:50:50.858458 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9772 04:50:50.858510 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9773 04:50:50.858562 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9774 04:50:50.858613 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9775 04:50:50.858664 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9776 04:50:50.858715 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9777 04:50:50.858766 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9778 04:50:50.858817 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9779 04:50:50.858868 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9780 04:50:50.858918 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9781 04:50:50.858969 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9782 04:50:50.859020 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9783 04:50:50.859071 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9784 04:50:50.859121 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9785 04:50:50.859172 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9786 04:50:50.859223 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9787 04:50:50.859274 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9788 04:50:50.859325 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9789 04:50:50.859376 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9790 04:50:50.859426 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9791 04:50:50.859477 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9792 04:50:50.859528 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9793 04:50:50.859578 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9794 04:50:50.859629 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9795 04:50:50.859680 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9796 04:50:50.859731 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9797 04:50:50.859782 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9798 04:50:50.859833 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9799 04:50:50.859884 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9800 04:50:50.859935 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9801 04:50:50.859986 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9802 04:50:50.860038 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9803 04:50:50.860089 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9804 04:50:50.860159 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9805 04:50:50.860215 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9806 04:50:50.860269 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9807 04:50:50.860321 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9808 04:50:50.860372 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9809 04:50:50.860423 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9810 04:50:50.860513 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9811 04:50:50.860601 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9812 04:50:50.860690 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9813 04:50:50.860783 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9814 04:50:50.860872 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9815 04:50:50.860959 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9816 04:50:50.861048 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9817 04:50:50.861138 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9818 04:50:50.861226 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9819 04:50:50.861313 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9820 04:50:50.861401 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9821 04:50:50.861489 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9822 04:50:50.861576 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9823 04:50:50.861662 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9824 04:50:50.861750 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9825 04:50:50.861835 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9826 04:50:50.861917 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9827 04:50:50.862005 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9828 04:50:50.862087 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9829 04:50:50.862168 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9830 04:50:50.862249 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9831 04:50:50.862331 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9832 04:50:51.228129 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9833 04:50:51.228648 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9834 04:50:51.229049 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9835 04:50:51.229387 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9836 04:50:51.229705 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9837 04:50:51.230069 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9838 04:50:51.230386 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9839 04:50:51.230686 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9840 04:50:51.230982 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9841 04:50:51.231278 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9842 04:50:51.231576 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9843 04:50:51.231873 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9844 04:50:51.232162 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9845 04:50:51.232870 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9846 04:50:51.233204 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9847 04:50:51.233505 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9848 04:50:51.233802 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9849 04:50:51.234145 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9850 04:50:51.234443 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9851 04:50:51.234730 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9852 04:50:51.235024 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9853 04:50:51.235316 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9854 04:50:51.235607 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9855 04:50:51.235893 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9856 04:50:51.236182 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9857 04:50:51.236471 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9858 04:50:51.236764 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9859 04:50:51.237052 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9860 04:50:51.237340 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9861 04:50:51.237631 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9862 04:50:51.237923 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9863 04:50:51.238255 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9864 04:50:51.238545 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9865 04:50:51.238835 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9866 04:50:51.239125 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9867 04:50:51.239471 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9868 04:50:51.239762 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9869 04:50:51.240051 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9870 04:50:51.240340 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9871 04:50:51.240629 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9872 04:50:51.240913 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9873 04:50:51.241201 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9874 04:50:51.241543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9875 04:50:51.241839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9876 04:50:51.242177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9877 04:50:51.242474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9878 04:50:51.242767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9879 04:50:51.243057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9880 04:50:51.243346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9881 04:50:51.243637 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9882 04:50:51.243930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9883 04:50:51.244221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9884 04:50:51.244512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9885 04:50:51.244800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9886 04:50:51.245090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9887 04:50:51.245381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9888 04:50:51.245671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9889 04:50:51.245989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9890 04:50:51.246291 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9891 04:50:51.246583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9892 04:50:51.246877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9893 04:50:51.247166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9894 04:50:51.247455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9895 04:50:51.247744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9896 04:50:51.248035 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9897 04:50:51.248322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9898 04:50:51.248613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9899 04:50:51.248905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9900 04:50:51.249194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9901 04:50:51.249482 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9902 04:50:51.249769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9903 04:50:51.250080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9904 04:50:51.250370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9905 04:50:51.250657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9906 04:50:51.250942 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9907 04:50:51.251231 INFO: [APUAPC] vio 0
9908 04:50:51.251519 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9909 04:50:51.251809 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9910 04:50:51.252097 INFO: [APUAPC] D0_APC_0: 0x400510
9911 04:50:51.252385 INFO: [APUAPC] D0_APC_1: 0x0
9912 04:50:51.252672 INFO: [APUAPC] D0_APC_2: 0x1540
9913 04:50:51.252960 INFO: [APUAPC] D0_APC_3: 0x0
9914 04:50:51.253245 INFO: [APUAPC] D1_APC_0: 0xffffffff
9915 04:50:51.253535 INFO: [APUAPC] D1_APC_1: 0xffffffff
9916 04:50:51.253822 INFO: [APUAPC] D1_APC_2: 0x3fffff
9917 04:50:51.254140 INFO: [APUAPC] D1_APC_3: 0x0
9918 04:50:51.254429 INFO: [APUAPC] D2_APC_0: 0xffffffff
9919 04:50:51.254687 INFO: [APUAPC] D2_APC_1: 0xffffffff
9920 04:50:51.254944 INFO: [APUAPC] D2_APC_2: 0x3fffff
9921 04:50:51.255162 INFO: [APUAPC] D2_APC_3: 0x0
9922 04:50:51.255374 INFO: [APUAPC] D3_APC_0: 0xffffffff
9923 04:50:51.255889 INFO: [APUAPC] D3_APC_1: 0xffffffff
9924 04:50:51.256126 INFO: [APUAPC] D3_APC_2: 0x3fffff
9925 04:50:51.256344 INFO: [APUAPC] D3_APC_3: 0x0
9926 04:50:51.256555 INFO: [APUAPC] D4_APC_0: 0xffffffff
9927 04:50:51.256768 INFO: [APUAPC] D4_APC_1: 0xffffffff
9928 04:50:51.256979 INFO: [APUAPC] D4_APC_2: 0x3fffff
9929 04:50:51.257191 INFO: [APUAPC] D4_APC_3: 0x0
9930 04:50:51.257400 INFO: [APUAPC] D5_APC_0: 0xffffffff
9931 04:50:51.257610 INFO: [APUAPC] D5_APC_1: 0xffffffff
9932 04:50:51.257820 INFO: [APUAPC] D5_APC_2: 0x3fffff
9933 04:50:51.258085 INFO: [APUAPC] D5_APC_3: 0x0
9934 04:50:51.258389 INFO: [APUAPC] D6_APC_0: 0xffffffff
9935 04:50:51.258608 INFO: [APUAPC] D6_APC_1: 0xffffffff
9936 04:50:51.258818 INFO: [APUAPC] D6_APC_2: 0x3fffff
9937 04:50:51.259073 INFO: [APUAPC] D6_APC_3: 0x0
9938 04:50:51.259286 INFO: [APUAPC] D7_APC_0: 0xffffffff
9939 04:50:51.259497 INFO: [APUAPC] D7_APC_1: 0xffffffff
9940 04:50:51.259674 INFO: [APUAPC] D7_APC_2: 0x3fffff
9941 04:50:51.259829 INFO: [APUAPC] D7_APC_3: 0x0
9942 04:50:51.259985 INFO: [APUAPC] D8_APC_0: 0xffffffff
9943 04:50:51.260140 INFO: [APUAPC] D8_APC_1: 0xffffffff
9944 04:50:51.260295 INFO: [APUAPC] D8_APC_2: 0x3fffff
9945 04:50:51.260451 INFO: [APUAPC] D8_APC_3: 0x0
9946 04:50:51.260606 INFO: [APUAPC] D9_APC_0: 0xffffffff
9947 04:50:51.260759 INFO: [APUAPC] D9_APC_1: 0xffffffff
9948 04:50:51.260941 INFO: [APUAPC] D9_APC_2: 0x3fffff
9949 04:50:51.261098 INFO: [APUAPC] D9_APC_3: 0x0
9950 04:50:51.261253 INFO: [APUAPC] D10_APC_0: 0xffffffff
9951 04:50:51.261407 INFO: [APUAPC] D10_APC_1: 0xffffffff
9952 04:50:51.261562 INFO: [APUAPC] D10_APC_2: 0x3fffff
9953 04:50:51.261717 INFO: [APUAPC] D10_APC_3: 0x0
9954 04:50:51.261884 INFO: [APUAPC] D11_APC_0: 0xffffffff
9955 04:50:51.262082 INFO: [APUAPC] D11_APC_1: 0xffffffff
9956 04:50:51.262239 INFO: [APUAPC] D11_APC_2: 0x3fffff
9957 04:50:51.262396 INFO: [APUAPC] D11_APC_3: 0x0
9958 04:50:51.262553 INFO: [APUAPC] D12_APC_0: 0xffffffff
9959 04:50:51.262709 INFO: [APUAPC] D12_APC_1: 0xffffffff
9960 04:50:51.262863 INFO: [APUAPC] D12_APC_2: 0x3fffff
9961 04:50:51.263018 INFO: [APUAPC] D12_APC_3: 0x0
9962 04:50:51.263171 INFO: [APUAPC] D13_APC_0: 0xffffffff
9963 04:50:51.263325 INFO: [APUAPC] D13_APC_1: 0xffffffff
9964 04:50:51.263478 INFO: [APUAPC] D13_APC_2: 0x3fffff
9965 04:50:51.263635 INFO: [APUAPC] D13_APC_3: 0x0
9966 04:50:51.263789 INFO: [APUAPC] D14_APC_0: 0xffffffff
9967 04:50:51.263944 INFO: [APUAPC] D14_APC_1: 0xffffffff
9968 04:50:51.264098 INFO: [APUAPC] D14_APC_2: 0x3fffff
9969 04:50:51.264252 INFO: [APUAPC] D14_APC_3: 0x0
9970 04:50:51.264406 INFO: [APUAPC] D15_APC_0: 0xffffffff
9971 04:50:51.264565 INFO: [APUAPC] D15_APC_1: 0xffffffff
9972 04:50:51.264688 INFO: [APUAPC] D15_APC_2: 0x3fffff
9973 04:50:51.264811 INFO: [APUAPC] D15_APC_3: 0x0
9974 04:50:51.264933 INFO: [APUAPC] APC_CON: 0x4
9975 04:50:51.265055 INFO: [NOCDAPC] D0_APC_0: 0x0
9976 04:50:51.265178 INFO: [NOCDAPC] D0_APC_1: 0x0
9977 04:50:51.265300 INFO: [NOCDAPC] D1_APC_0: 0x0
9978 04:50:51.265423 INFO: [NOCDAPC] D1_APC_1: 0xfff
9979 04:50:51.265546 INFO: [NOCDAPC] D2_APC_0: 0x0
9980 04:50:51.265668 INFO: [NOCDAPC] D2_APC_1: 0xfff
9981 04:50:51.265791 INFO: [NOCDAPC] D3_APC_0: 0x0
9982 04:50:51.265912 INFO: [NOCDAPC] D3_APC_1: 0xfff
9983 04:50:51.266043 INFO: [NOCDAPC] D4_APC_0: 0x0
9984 04:50:51.266165 INFO: [NOCDAPC] D4_APC_1: 0xfff
9985 04:50:51.266288 INFO: [NOCDAPC] D5_APC_0: 0x0
9986 04:50:51.266408 INFO: [NOCDAPC] D5_APC_1: 0xfff
9987 04:50:51.266531 INFO: [NOCDAPC] D6_APC_0: 0x0
9988 04:50:51.266654 INFO: [NOCDAPC] D6_APC_1: 0xfff
9989 04:50:51.266776 INFO: [NOCDAPC] D7_APC_0: 0x0
9990 04:50:51.266897 INFO: [NOCDAPC] D7_APC_1: 0xfff
9991 04:50:51.267018 INFO: [NOCDAPC] D8_APC_0: 0x0
9992 04:50:51.267141 INFO: [NOCDAPC] D8_APC_1: 0xfff
9993 04:50:51.267262 INFO: [NOCDAPC] D9_APC_0: 0x0
9994 04:50:51.267384 INFO: [NOCDAPC] D9_APC_1: 0xfff
9995 04:50:51.267505 INFO: [NOCDAPC] D10_APC_0: 0x0
9996 04:50:51.267627 INFO: [NOCDAPC] D10_APC_1: 0xfff
9997 04:50:51.267750 INFO: [NOCDAPC] D11_APC_0: 0x0
9998 04:50:51.267874 INFO: [NOCDAPC] D11_APC_1: 0xfff
9999 04:50:51.267996 INFO: [NOCDAPC] D12_APC_0: 0x0
10000 04:50:51.268118 INFO: [NOCDAPC] D12_APC_1: 0xfff
10001 04:50:51.268239 INFO: [NOCDAPC] D13_APC_0: 0x0
10002 04:50:51.268360 INFO: [NOCDAPC] D13_APC_1: 0xfff
10003 04:50:51.268482 INFO: [NOCDAPC] D14_APC_0: 0x0
10004 04:50:51.268604 INFO: [NOCDAPC] D14_APC_1: 0xfff
10005 04:50:51.268726 INFO: [NOCDAPC] D15_APC_0: 0x0
10006 04:50:51.268847 INFO: [NOCDAPC] D15_APC_1: 0xfff
10007 04:50:51.268969 INFO: [NOCDAPC] APC_CON: 0x4
10008 04:50:51.269090 INFO: [APUAPC] set_apusys_apc done
10009 04:50:51.269213 INFO: [DEVAPC] devapc_init done
10010 04:50:51.269335 INFO: GICv3 without legacy support detected.
10011 04:50:51.269457 INFO: ARM GICv3 driver initialized in EL3
10012 04:50:51.269589 INFO: Maximum SPI INTID supported: 639
10013 04:50:51.269691 INFO: BL31: Initializing runtime services
10014 04:50:51.269792 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10015 04:50:51.269934 INFO: SPM: enable CPC mode
10016 04:50:51.270057 INFO: mcdi ready for mcusys-off-idle and system suspend
10017 04:50:51.270161 INFO: BL31: Preparing for EL3 exit to normal world
10018 04:50:51.270265 INFO: Entry point address = 0x80000000
10019 04:50:51.270368 INFO: SPSR = 0x8
10020 04:50:51.270471
10021 04:50:51.270572
10022 04:50:51.270673
10023 04:50:51.270774 Starting depthcharge on Spherion...
10024 04:50:51.270877
10025 04:50:51.270978 Wipe memory regions:
10026 04:50:51.271078
10027 04:50:51.271179 [0x00000040000000, 0x00000054600000)
10028 04:50:51.271281
10029 04:50:51.271382 [0x00000054660000, 0x00000080000000)
10030 04:50:51.271482
10031 04:50:51.271583 [0x000000821a7280, 0x000000ffe64000)
10032 04:50:51.272481 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10033 04:50:51.272666 start: 2.2.4 bootloader-commands (timeout 00:04:24) [common]
10034 04:50:51.272813 Setting prompt string to ['asurada:']
10035 04:50:51.272954 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:24)
10036 04:50:51.529292
10037 04:50:51.529852 [0x00000100000000, 0x00000240000000)
10038 04:50:53.419714
10039 04:50:53.422787 Initializing XHCI USB controller at 0x11200000.
10040 04:50:54.460747
10041 04:50:54.464181 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10042 04:50:54.464655
10043 04:50:54.465023
10044 04:50:54.465432
10045 04:50:54.466256 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10047 04:50:54.567522 asurada: tftpboot 192.168.201.1 12699866/tftp-deploy-ha4svlpj/kernel/image.itb 12699866/tftp-deploy-ha4svlpj/kernel/cmdline
10048 04:50:54.568105 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10049 04:50:54.568552 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10050 04:50:54.573013 tftpboot 192.168.201.1 12699866/tftp-deploy-ha4svlpj/kernel/image.itp-deploy-ha4svlpj/kernel/cmdline
10051 04:50:54.573497
10052 04:50:54.573864 Waiting for link
10053 04:50:54.733843
10054 04:50:54.734480 R8152: Initializing
10055 04:50:54.734861
10056 04:50:54.736921 Version 9 (ocp_data = 6010)
10057 04:50:54.737490
10058 04:50:54.740350 R8152: Done initializing
10059 04:50:54.740928
10060 04:50:54.741302 Adding net device
10061 04:50:56.608861
10062 04:50:56.609442 done.
10063 04:50:56.609812
10064 04:50:56.610180 MAC: 00:e0:4c:72:2d:d6
10065 04:50:56.610528
10066 04:50:56.611684 Sending DHCP discover... done.
10067 04:50:56.612140
10068 04:50:56.614857 Waiting for reply... done.
10069 04:50:56.614936
10070 04:50:56.618252 Sending DHCP request... done.
10071 04:50:56.618333
10072 04:50:56.618394 Waiting for reply... done.
10073 04:50:56.622208
10074 04:50:56.622288 My ip is 192.168.201.21
10075 04:50:56.622350
10076 04:50:56.624913 The DHCP server ip is 192.168.201.1
10077 04:50:56.624997
10078 04:50:56.628427 TFTP server IP predefined by user: 192.168.201.1
10079 04:50:56.628600
10080 04:50:56.635021 Bootfile predefined by user: 12699866/tftp-deploy-ha4svlpj/kernel/image.itb
10081 04:50:56.635584
10082 04:50:56.638491 Sending tftp read request... done.
10083 04:50:56.639056
10084 04:50:56.645238 Waiting for the transfer...
10085 04:50:56.645693
10086 04:50:56.920255 00000000 ################################################################
10087 04:50:56.920398
10088 04:50:57.198663 00080000 ################################################################
10089 04:50:57.198795
10090 04:50:57.482723 00100000 ################################################################
10091 04:50:57.482860
10092 04:50:57.774710 00180000 ################################################################
10093 04:50:57.774842
10094 04:50:58.066919 00200000 ################################################################
10095 04:50:58.067058
10096 04:50:58.318879 00280000 ################################################################
10097 04:50:58.319027
10098 04:50:58.571326 00300000 ################################################################
10099 04:50:58.571500
10100 04:50:58.819081 00380000 ################################################################
10101 04:50:58.819243
10102 04:50:59.109977 00400000 ################################################################
10103 04:50:59.110140
10104 04:50:59.405933 00480000 ################################################################
10105 04:50:59.406233
10106 04:50:59.701453 00500000 ################################################################
10107 04:50:59.701617
10108 04:50:59.996881 00580000 ################################################################
10109 04:50:59.997031
10110 04:51:00.284739 00600000 ################################################################
10111 04:51:00.284893
10112 04:51:00.556008 00680000 ################################################################
10113 04:51:00.556157
10114 04:51:00.831970 00700000 ################################################################
10115 04:51:00.832092
10116 04:51:01.083168 00780000 ################################################################
10117 04:51:01.083319
10118 04:51:01.335518 00800000 ################################################################
10119 04:51:01.335682
10120 04:51:01.590424 00880000 ################################################################
10121 04:51:01.590564
10122 04:51:01.840198 00900000 ################################################################
10123 04:51:01.840331
10124 04:51:02.088718 00980000 ################################################################
10125 04:51:02.088868
10126 04:51:02.351937 00a00000 ################################################################
10127 04:51:02.352069
10128 04:51:02.609113 00a80000 ################################################################
10129 04:51:02.609261
10130 04:51:02.877975 00b00000 ################################################################
10131 04:51:02.878127
10132 04:51:03.173711 00b80000 ################################################################
10133 04:51:03.173855
10134 04:51:03.468301 00c00000 ################################################################
10135 04:51:03.468429
10136 04:51:03.724913 00c80000 ################################################################
10137 04:51:03.725044
10138 04:51:03.986932 00d00000 ################################################################
10139 04:51:03.987090
10140 04:51:04.249280 00d80000 ################################################################
10141 04:51:04.249424
10142 04:51:04.513765 00e00000 ################################################################
10143 04:51:04.513895
10144 04:51:04.765015 00e80000 ################################################################
10145 04:51:04.765156
10146 04:51:05.017339 00f00000 ################################################################
10147 04:51:05.017477
10148 04:51:05.267137 00f80000 ################################################################
10149 04:51:05.267266
10150 04:51:05.518813 01000000 ################################################################
10151 04:51:05.518950
10152 04:51:05.761596 01080000 ################################################################
10153 04:51:05.761756
10154 04:51:06.006253 01100000 ################################################################
10155 04:51:06.006384
10156 04:51:06.252560 01180000 ################################################################
10157 04:51:06.252727
10158 04:51:06.499755 01200000 ################################################################
10159 04:51:06.499890
10160 04:51:06.742905 01280000 ################################################################
10161 04:51:06.743069
10162 04:51:06.996724 01300000 ################################################################
10163 04:51:06.996882
10164 04:51:07.254760 01380000 ################################################################
10165 04:51:07.254913
10166 04:51:07.559475 01400000 ################################################################
10167 04:51:07.559618
10168 04:51:07.816148 01480000 ################################################################
10169 04:51:07.816285
10170 04:51:08.077391 01500000 ################################################################
10171 04:51:08.077519
10172 04:51:08.370855 01580000 ################################################################
10173 04:51:08.370987
10174 04:51:08.649204 01600000 ################################################################
10175 04:51:08.649360
10176 04:51:08.907170 01680000 ################################################################
10177 04:51:08.907389
10178 04:51:09.168469 01700000 ################################################################
10179 04:51:09.168616
10180 04:51:09.423021 01780000 ################################################################
10181 04:51:09.423187
10182 04:51:09.723352 01800000 ################################################################
10183 04:51:09.723550
10184 04:51:09.978633 01880000 ################################################################
10185 04:51:09.978773
10186 04:51:10.263418 01900000 ################################################################
10187 04:51:10.263539
10188 04:51:10.516399 01980000 ################################################################
10189 04:51:10.516523
10190 04:51:10.800547 01a00000 ################################################################
10191 04:51:10.800670
10192 04:51:11.050457 01a80000 ################################################################
10193 04:51:11.050581
10194 04:51:11.299912 01b00000 ################################################################
10195 04:51:11.300031
10196 04:51:11.570317 01b80000 ################################################################
10197 04:51:11.570439
10198 04:51:11.835117 01c00000 ################################################################
10199 04:51:11.835256
10200 04:51:12.126472 01c80000 ################################################################
10201 04:51:12.126605
10202 04:51:12.414429 01d00000 ################################################################
10203 04:51:12.414561
10204 04:51:12.699043 01d80000 ################################################################
10205 04:51:12.699171
10206 04:51:12.975589 01e00000 ################################################################
10207 04:51:12.975724
10208 04:51:13.254894 01e80000 ################################################################
10209 04:51:13.255019
10210 04:51:13.535902 01f00000 ################################################################
10211 04:51:13.536065
10212 04:51:13.831983 01f80000 ################################################################
10213 04:51:13.832140
10214 04:51:14.124928 02000000 ################################################################
10215 04:51:14.125086
10216 04:51:14.422281 02080000 ################################################################
10217 04:51:14.422415
10218 04:51:14.718116 02100000 ################################################################
10219 04:51:14.718265
10220 04:51:14.998363 02180000 ################################################################
10221 04:51:14.998502
10222 04:51:15.287218 02200000 ################################################################
10223 04:51:15.287371
10224 04:51:15.553236 02280000 ################################################################
10225 04:51:15.553373
10226 04:51:15.802905 02300000 ################################################################
10227 04:51:15.803024
10228 04:51:16.052672 02380000 ################################################################
10229 04:51:16.052798
10230 04:51:16.301950 02400000 ################################################################
10231 04:51:16.302089
10232 04:51:16.581570 02480000 ################################################################
10233 04:51:16.581694
10234 04:51:16.876117 02500000 ################################################################
10235 04:51:16.876250
10236 04:51:17.150337 02580000 ################################################################
10237 04:51:17.150487
10238 04:51:17.440935 02600000 ################################################################
10239 04:51:17.441090
10240 04:51:17.728297 02680000 ################################################################
10241 04:51:17.728443
10242 04:51:18.005591 02700000 ################################################################
10243 04:51:18.005715
10244 04:51:18.262890 02780000 ################################################################
10245 04:51:18.263017
10246 04:51:18.547846 02800000 ################################################################
10247 04:51:18.548004
10248 04:51:18.839668 02880000 ################################################################
10249 04:51:18.839800
10250 04:51:19.097252 02900000 ################################################################
10251 04:51:19.097407
10252 04:51:19.388719 02980000 ################################################################
10253 04:51:19.388873
10254 04:51:19.658808 02a00000 ################################################################
10255 04:51:19.658929
10256 04:51:19.922839 02a80000 ################################################################
10257 04:51:19.922983
10258 04:51:20.200592 02b00000 ################################################################
10259 04:51:20.200724
10260 04:51:20.493151 02b80000 ################################################################
10261 04:51:20.493307
10262 04:51:20.783464 02c00000 ################################################################
10263 04:51:20.783601
10264 04:51:21.075380 02c80000 ################################################################
10265 04:51:21.075536
10266 04:51:21.330566 02d00000 ################################################################
10267 04:51:21.330700
10268 04:51:21.586683 02d80000 ################################################################
10269 04:51:21.586804
10270 04:51:21.878200 02e00000 ################################################################
10271 04:51:21.878323
10272 04:51:22.166533 02e80000 ################################################################
10273 04:51:22.166665
10274 04:51:22.453385 02f00000 ################################################################
10275 04:51:22.453519
10276 04:51:22.738725 02f80000 ################################################################
10277 04:51:22.738849
10278 04:51:23.035671 03000000 ################################################################
10279 04:51:23.035798
10280 04:51:23.289116 03080000 ################################################################
10281 04:51:23.289256
10282 04:51:23.332626 03100000 ############ done.
10283 04:51:23.332712
10284 04:51:23.336099 The bootfile was 51474302 bytes long.
10285 04:51:23.336182
10286 04:51:23.339567 Sending tftp read request... done.
10287 04:51:23.339730
10288 04:51:23.343258 Waiting for the transfer...
10289 04:51:23.343428
10290 04:51:23.343510 00000000 # done.
10291 04:51:23.343588
10292 04:51:23.352791 Command line loaded dynamically from TFTP file: 12699866/tftp-deploy-ha4svlpj/kernel/cmdline
10293 04:51:23.353036
10294 04:51:23.365978 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10295 04:51:23.366196
10296 04:51:23.366314 Loading FIT.
10297 04:51:23.366419
10298 04:51:23.369576 Image ramdisk-1 has 39376483 bytes.
10299 04:51:23.369811
10300 04:51:23.372620 Image fdt-1 has 47278 bytes.
10301 04:51:23.372796
10302 04:51:23.376019 Image kernel-1 has 12048508 bytes.
10303 04:51:23.376281
10304 04:51:23.385803 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10305 04:51:23.386076
10306 04:51:23.402485 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10307 04:51:23.403070
10308 04:51:23.409436 Choosing best match conf-1 for compat google,spherion-rev2.
10309 04:51:23.409907
10310 04:51:23.412744 Connected to device vid:did:rid of 1ae0:0028:00
10311 04:51:23.425419
10312 04:51:23.428566 tpm_get_response: command 0x17b, return code 0x0
10313 04:51:23.429139
10314 04:51:23.431177 ec_init: CrosEC protocol v3 supported (256, 248)
10315 04:51:23.435298
10316 04:51:23.438518 tpm_cleanup: add release locality here.
10317 04:51:23.438990
10318 04:51:23.439355 Shutting down all USB controllers.
10319 04:51:23.442277
10320 04:51:23.442837 Removing current net device
10321 04:51:23.443213
10322 04:51:23.449608 Exiting depthcharge with code 4 at timestamp: 62364214
10323 04:51:23.450220
10324 04:51:23.452358 LZMA decompressing kernel-1 to 0x821a6718
10325 04:51:23.452826
10326 04:51:23.455375 LZMA decompressing kernel-1 to 0x40000000
10327 04:51:24.954357
10328 04:51:24.954919 jumping to kernel
10329 04:51:24.956970 end: 2.2.4 bootloader-commands (duration 00:00:34) [common]
10330 04:51:24.957501 start: 2.2.5 auto-login-action (timeout 00:03:51) [common]
10331 04:51:24.957918 Setting prompt string to ['Linux version [0-9]']
10332 04:51:24.958362 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10333 04:51:24.958748 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10334 04:51:25.036250
10335 04:51:25.039529 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10336 04:51:25.043257 start: 2.2.5.1 login-action (timeout 00:03:51) [common]
10337 04:51:25.043772 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10338 04:51:25.044173 Setting prompt string to []
10339 04:51:25.044589 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10340 04:51:25.044999 Using line separator: #'\n'#
10341 04:51:25.045338 No login prompt set.
10342 04:51:25.045674 Parsing kernel messages
10343 04:51:25.046012 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10344 04:51:25.046577 [login-action] Waiting for messages, (timeout 00:03:51)
10345 04:51:25.062660 [ 0.000000] Linux version 6.1.75-cip14-rt8 (KernelCI@build-j97480-arm64-gcc-10-defconfig-arm64-chromebook-6n26j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024
10346 04:51:25.066095 [ 0.000000] random: crng init done
10347 04:51:25.073023 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10348 04:51:25.075723 [ 0.000000] efi: UEFI not found.
10349 04:51:25.082625 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10350 04:51:25.089303 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10351 04:51:25.099607 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10352 04:51:25.108857 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10353 04:51:25.115575 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10354 04:51:25.122146 [ 0.000000] printk: bootconsole [mtk8250] enabled
10355 04:51:25.129272 [ 0.000000] NUMA: No NUMA configuration found
10356 04:51:25.135796 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10357 04:51:25.138663 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10358 04:51:25.142083 [ 0.000000] Zone ranges:
10359 04:51:25.148699 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10360 04:51:25.151991 [ 0.000000] DMA32 empty
10361 04:51:25.158862 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10362 04:51:25.162403 [ 0.000000] Movable zone start for each node
10363 04:51:25.165861 [ 0.000000] Early memory node ranges
10364 04:51:25.172215 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10365 04:51:25.178693 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10366 04:51:25.185857 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10367 04:51:25.192220 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10368 04:51:25.195147 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10369 04:51:25.205423 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10370 04:51:25.260959 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10371 04:51:25.267589 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10372 04:51:25.274116 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10373 04:51:25.278091 [ 0.000000] psci: probing for conduit method from DT.
10374 04:51:25.284314 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10375 04:51:25.287475 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10376 04:51:25.294183 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10377 04:51:25.297512 [ 0.000000] psci: SMC Calling Convention v1.2
10378 04:51:25.304397 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10379 04:51:25.307785 [ 0.000000] Detected VIPT I-cache on CPU0
10380 04:51:25.314295 [ 0.000000] CPU features: detected: GIC system register CPU interface
10381 04:51:25.321025 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10382 04:51:25.327369 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10383 04:51:25.334100 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10384 04:51:25.340646 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10385 04:51:25.347379 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10386 04:51:25.353774 [ 0.000000] alternatives: applying boot alternatives
10387 04:51:25.357281 [ 0.000000] Fallback order for Node 0: 0
10388 04:51:25.367223 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10389 04:51:25.370563 [ 0.000000] Policy zone: Normal
10390 04:51:25.383331 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10391 04:51:25.393407 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10392 04:51:25.404498 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10393 04:51:25.414333 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10394 04:51:25.421060 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10395 04:51:25.424319 <6>[ 0.000000] software IO TLB: area num 8.
10396 04:51:25.480614 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10397 04:51:25.630482 <6>[ 0.000000] Memory: 7928740K/8385536K available (18048K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 616K bss, 424028K reserved, 32768K cma-reserved)
10398 04:51:25.636731 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10399 04:51:25.643475 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10400 04:51:25.646857 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10401 04:51:25.653389 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10402 04:51:25.660479 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10403 04:51:25.662982 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10404 04:51:25.674644 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10405 04:51:25.680086 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10406 04:51:25.683113 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10407 04:51:25.691175 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10408 04:51:25.694282 <6>[ 0.000000] GICv3: 608 SPIs implemented
10409 04:51:25.700914 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10410 04:51:25.704287 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10411 04:51:25.707618 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10412 04:51:25.717789 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10413 04:51:25.727662 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10414 04:51:25.740684 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10415 04:51:25.747812 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10416 04:51:25.756427 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10417 04:51:25.769739 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10418 04:51:25.776627 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10419 04:51:25.783637 <6>[ 0.009186] Console: colour dummy device 80x25
10420 04:51:25.792937 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10421 04:51:25.799546 <6>[ 0.024415] pid_max: default: 32768 minimum: 301
10422 04:51:25.803093 <6>[ 0.029286] LSM: Security Framework initializing
10423 04:51:25.810028 <6>[ 0.034224] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10424 04:51:25.819670 <6>[ 0.042040] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10425 04:51:25.826868 <6>[ 0.051445] cblist_init_generic: Setting adjustable number of callback queues.
10426 04:51:25.833167 <6>[ 0.058934] cblist_init_generic: Setting shift to 3 and lim to 1.
10427 04:51:25.842856 <6>[ 0.065273] cblist_init_generic: Setting adjustable number of callback queues.
10428 04:51:25.849210 <6>[ 0.072747] cblist_init_generic: Setting shift to 3 and lim to 1.
10429 04:51:25.852586 <6>[ 0.079174] rcu: Hierarchical SRCU implementation.
10430 04:51:25.859375 <6>[ 0.079176] rcu: Max phase no-delay instances is 1000.
10431 04:51:25.865820 <6>[ 0.079199] printk: bootconsole [mtk8250] printing thread started
10432 04:51:25.872396 <6>[ 0.097510] EFI services will not be available.
10433 04:51:25.875721 <6>[ 0.097709] smp: Bringing up secondary CPUs ...
10434 04:51:25.879383 <6>[ 0.098021] Detected VIPT I-cache on CPU1
10435 04:51:25.889226 <6>[ 0.098089] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10436 04:51:25.895506 <6>[ 0.098122] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10437 04:51:25.904792 <6>[ 0.125988] Detected VIPT I-cache on CPU2
10438 04:51:25.911234 <6>[ 0.126034] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10439 04:51:25.921341 <6>[ 0.126049] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10440 04:51:25.924836 <6>[ 0.126304] Detected VIPT I-cache on CPU3
10441 04:51:25.930928 <6>[ 0.126351] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10442 04:51:25.937711 <6>[ 0.126364] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10443 04:51:25.941414 <6>[ 0.126675] CPU features: detected: Spectre-v4
10444 04:51:25.947595 <6>[ 0.126682] CPU features: detected: Spectre-BHB
10445 04:51:25.951147 <6>[ 0.126687] Detected PIPT I-cache on CPU4
10446 04:51:25.957355 <6>[ 0.126747] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10447 04:51:25.963634 <6>[ 0.126763] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10448 04:51:25.970955 <6>[ 0.127054] Detected PIPT I-cache on CPU5
10449 04:51:25.977280 <6>[ 0.127116] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10450 04:51:25.984361 <6>[ 0.127132] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10451 04:51:25.987314 <6>[ 0.127406] Detected PIPT I-cache on CPU6
10452 04:51:25.996728 <6>[ 0.127469] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10453 04:51:26.003751 <6>[ 0.127486] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10454 04:51:26.006986 <6>[ 0.127778] Detected PIPT I-cache on CPU7
10455 04:51:26.013959 <6>[ 0.127842] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10456 04:51:26.020304 <6>[ 0.127858] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10457 04:51:26.026835 <6>[ 0.127905] smp: Brought up 1 node, 8 CPUs
10458 04:51:26.030228 <6>[ 0.127910] SMP: Total of 8 processors activated.
10459 04:51:26.036437 <6>[ 0.127912] CPU features: detected: 32-bit EL0 Support
10460 04:51:26.043286 <6>[ 0.127914] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10461 04:51:26.049614 <6>[ 0.127917] CPU features: detected: Common not Private translations
10462 04:51:26.055987 <6>[ 0.127918] CPU features: detected: CRC32 instructions
10463 04:51:26.063008 <6>[ 0.127921] CPU features: detected: RCpc load-acquire (LDAPR)
10464 04:51:26.066314 <6>[ 0.127922] CPU features: detected: LSE atomic instructions
10465 04:51:26.072921 <6>[ 0.127924] CPU features: detected: Privileged Access Never
10466 04:51:26.079461 <6>[ 0.127925] CPU features: detected: RAS Extension Support
10467 04:51:26.085935 <6>[ 0.127928] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10468 04:51:26.089368 <6>[ 0.127993] CPU: All CPU(s) started at EL2
10469 04:51:26.095890 <6>[ 0.127995] alternatives: applying system-wide alternatives
10470 04:51:26.099117 <6>[ 0.141089] devtmpfs: initialized
10471 04:51:26.109019 <6>[ 0.147301] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10472 04:51:26.138327 ��郒����ѕɕ��C}%9Q��ɽѽ����������5)�<6>[ 0<.364692] printk: console [ttyS0] printing thread started
10473 04:51:26.145101 6<6>[ 0.364720] printk: console [ttyS0] enabled
10474 04:51:26.151572 >[ 0.228694] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10475 04:51:26.159169 <6>[ 0.364723] printk: bootconsole [mtk8250] disabled
10476 04:51:26.165717 <6>[ 0.382805] printk: bootconsole [mtk8250] printing thread stopped
10477 04:51:26.169258 <6>[ 0.383804] SuperH (H)SCI(F) driver initialized
10478 04:51:26.175930 <6>[ 0.384275] msm_serial: driver initialized
10479 04:51:26.182373 <6>[ 0.388849] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10480 04:51:26.192558 <6>[ 0.388879] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10481 04:51:26.198902 <6>[ 0.388909] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10482 04:51:26.208568 <6>[ 0.388938] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10483 04:51:26.227164 <6>[ 0.388960] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10484 04:51:26.227739 <6>[ 0.388986] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10485 04:51:26.244139 <6>[ 0.389014] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10486 04:51:26.244693 <6>[ 0.389117] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10487 04:51:26.253168 <6>[ 0.389147] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10488 04:51:26.257864 <6>[ 0.400258] loop: module loaded
10489 04:51:26.262368 <6>[ 0.402885] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10490 04:51:26.269059 <4>[ 0.419503] mtk-pmic-keys: Failed to locate of_node [id: -1]
10491 04:51:26.272405 <6>[ 0.420423] megasas: 07.719.03.00-rc1
10492 04:51:26.279008 <6>[ 0.432768] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10493 04:51:26.282202 <6>[ 0.432951] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10494 04:51:26.288865 <6>[ 0.444783] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10495 04:51:26.299425 <6>[ 0.498423] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10496 04:51:27.598826 <6>[ 1.823209] Freeing initrd memory: 38448K
10497 04:51:27.605335 <6>[ 1.829529] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10498 04:51:27.608655 <6>[ 1.834161] tun: Universal TUN/TAP device driver, 1.6
10499 04:51:27.612163 <6>[ 1.834910] thunder_xcv, ver 1.0
10500 04:51:27.615331 <6>[ 1.834927] thunder_bgx, ver 1.0
10501 04:51:27.618390 <6>[ 1.834940] nicpf, ver 1.0
10502 04:51:27.628369 <6>[ 1.835979] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10503 04:51:27.631508 <6>[ 1.835982] hns3: Copyright (c) 2017 Huawei Corporation.
10504 04:51:27.635073 <6>[ 1.836004] hclge is initializing
10505 04:51:27.641405 <6>[ 1.836021] e1000: Intel(R) PRO/1000 Network Driver
10506 04:51:27.648766 <6>[ 1.836023] e1000: Copyright (c) 1999-2006 Intel Corporation.
10507 04:51:27.652412 <6>[ 1.836042] e1000e: Intel(R) PRO/1000 Network Driver
10508 04:51:27.659706 <6>[ 1.836044] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10509 04:51:27.663707 <6>[ 1.836059] igb: Intel(R) Gigabit Ethernet Network Driver
10510 04:51:27.670123 <6>[ 1.836061] igb: Copyright (c) 2007-2014 Intel Corporation.
10511 04:51:27.677460 <6>[ 1.836077] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10512 04:51:27.684312 <6>[ 1.836080] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10513 04:51:27.687799 <6>[ 1.836372] sky2: driver version 1.30
10514 04:51:27.691195 <6>[ 1.837434] VFIO - User Level meta-driver version: 0.3
10515 04:51:27.698078 <6>[ 1.840234] usbcore: registered new interface driver usb-storage
10516 04:51:27.704487 <6>[ 1.840413] usbcore: registered new device driver onboard-usb-hub
10517 04:51:27.710615 <6>[ 1.843185] mt6397-rtc mt6359-rtc: registered as rtc0
10518 04:51:27.720937 <6>[ 1.843338] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-04T04:50:48 UTC (1707022248)
10519 04:51:27.724645 <6>[ 1.843950] i2c_dev: i2c /dev entries driver
10520 04:51:27.730609 <6>[ 1.851114] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10521 04:51:27.737011 <6>[ 1.866093] cpu cpu0: EM: created perf domain
10522 04:51:27.740860 <6>[ 1.866431] cpu cpu4: EM: created perf domain
10523 04:51:27.747105 <6>[ 1.867902] sdhci: Secure Digital Host Controller Interface driver
10524 04:51:27.750335 <6>[ 1.867904] sdhci: Copyright(c) Pierre Ossman
10525 04:51:27.756955 <6>[ 1.868263] Synopsys Designware Multimedia Card Interface Driver
10526 04:51:27.763734 <6>[ 1.868655] sdhci-pltfm: SDHCI platform and OF driver helper
10527 04:51:27.770727 <6>[ 1.872917] ledtrig-cpu: registered to indicate activity on CPUs
10528 04:51:27.773851 <6>[ 1.873467] mmc0: CQHCI version 5.10
10529 04:51:27.780763 <6>[ 1.873743] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10530 04:51:27.786558 <6>[ 1.874058] usbcore: registered new interface driver usbhid
10531 04:51:27.790116 <6>[ 1.874060] usbhid: USB HID core driver
10532 04:51:27.796881 <6>[ 1.874193] spi_master spi0: will run message pump with realtime priority
10533 04:51:27.809992 <6>[ 1.905352] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10534 04:51:27.823463 <6>[ 1.908480] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10535 04:51:27.829799 <6>[ 1.909611] cros-ec-spi spi0.0: Chrome EC device registered
10536 04:51:27.839789 <6>[ 1.921918] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10537 04:51:27.843288 <6>[ 1.922895] NET: Registered PF_PACKET protocol family
10538 04:51:27.849601 <6>[ 1.922972] 9pnet: Installing 9P2000 support
10539 04:51:27.853109 <5>[ 1.923004] Key type dns_resolver registered
10540 04:51:27.856731 <6>[ 1.923535] registered taskstats version 1
10541 04:51:27.862876 <5>[ 1.923550] Loading compiled-in X.509 certificates
10542 04:51:27.872671 <4>[ 1.937597] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10543 04:51:27.882835 <4>[ 1.937924] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10544 04:51:27.889292 <3>[ 1.937945] debugfs: File 'uA_load' in directory '/' already present!
10545 04:51:27.896155 <3>[ 1.937957] debugfs: File 'min_uV' in directory '/' already present!
10546 04:51:27.902752 <3>[ 1.937965] debugfs: File 'max_uV' in directory '/' already present!
10547 04:51:27.912672 <3>[ 1.937972] debugfs: File 'constraint_flags' in directory '/' already present!
10548 04:51:27.919189 <3>[ 1.940724] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10549 04:51:27.926285 <6>[ 1.948067] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10550 04:51:27.932080 <6>[ 1.948744] xhci-mtk 11200000.usb: xHCI Host Controller
10551 04:51:27.938804 <6>[ 1.948757] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10552 04:51:27.948930 <6>[ 1.948967] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10553 04:51:27.955815 <6>[ 1.949008] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10554 04:51:27.958481 <6>[ 1.949082] xhci-mtk 11200000.usb: xHCI Host Controller
10555 04:51:27.968702 <6>[ 1.949085] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10556 04:51:27.975572 <6>[ 1.949090] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10557 04:51:27.978861 <6>[ 1.949652] hub 1-0:1.0: USB hub found
10558 04:51:27.982435 <6>[ 1.949670] hub 1-0:1.0: 1 port detected
10559 04:51:27.991810 <6>[ 1.949847] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10560 04:51:27.994945 <6>[ 1.950266] hub 2-0:1.0: USB hub found
10561 04:51:27.998627 <6>[ 1.950282] hub 2-0:1.0: 1 port detected
10562 04:51:28.005067 <6>[ 1.953522] mtk-msdc 11f70000.mmc: Got CD GPIO
10563 04:51:28.008243 <6>[ 1.967843] mmc0: Command Queue Engine enabled
10564 04:51:28.014920 <6>[ 1.967858] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10565 04:51:28.021798 <6>[ 1.968500] mmcblk0: mmc0:0001 DA4128 116 GiB
10566 04:51:28.028086 <6>[ 1.968929] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10567 04:51:28.035131 <6>[ 1.968935] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10568 04:51:28.044888 <4>[ 1.969147] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10569 04:51:28.051331 <6>[ 1.969825] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10570 04:51:28.061550 <6>[ 1.969829] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10571 04:51:28.067964 <6>[ 1.969950] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10572 04:51:28.078083 <6>[ 1.969961] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10573 04:51:28.084453 <6>[ 1.969965] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10574 04:51:28.094507 <6>[ 1.969976] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10575 04:51:28.097513 <6>[ 1.972031] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10576 04:51:28.107526 <6>[ 1.972127] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10577 04:51:28.117635 <6>[ 1.972152] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10578 04:51:28.124776 <6>[ 1.972161] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10579 04:51:28.134712 <6>[ 1.972168] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10580 04:51:28.140680 <6>[ 1.972176] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10581 04:51:28.150603 <6>[ 1.972183] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10582 04:51:28.157604 <6>[ 1.972190] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10583 04:51:28.167048 <6>[ 1.972198] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10584 04:51:28.173382 <6>[ 1.972205] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10585 04:51:28.183552 <6>[ 1.972212] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10586 04:51:28.190001 <6>[ 1.972220] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10587 04:51:28.201331 <6>[ 1.972227] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10588 04:51:28.206643 <6>[ 1.972234] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10589 04:51:28.216771 <6>[ 1.972240] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10590 04:51:28.223456 <6>[ 1.972247] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10591 04:51:28.230474 <6>[ 1.972570] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10592 04:51:28.233450 <6>[ 1.972873] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10593 04:51:28.240224 <6>[ 1.972987] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10594 04:51:28.246441 <6>[ 1.973241] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10595 04:51:28.253311 <6>[ 1.974563] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10596 04:51:28.259767 <6>[ 1.975160] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10597 04:51:28.266510 <6>[ 1.975793] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10598 04:51:28.273186 <6>[ 1.976426] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10599 04:51:28.282803 <6>[ 1.976623] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10600 04:51:28.293161 <6>[ 1.976639] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10601 04:51:28.303093 <6>[ 1.976644] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10602 04:51:28.312693 <6>[ 1.976650] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10603 04:51:28.319529 <6>[ 1.976656] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10604 04:51:28.329221 <6>[ 1.976662] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10605 04:51:28.339103 <6>[ 1.976668] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10606 04:51:28.349438 <6>[ 1.976673] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10607 04:51:28.358969 <6>[ 1.976681] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10608 04:51:28.368904 <6>[ 1.976687] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10609 04:51:28.379018 <6>[ 1.976692] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10610 04:51:28.385550 <6>[ 1.977175] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10611 04:51:28.391749 <6>[ 2.361586] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10612 04:51:28.395344 <6>[ 2.514400] hub 1-1:1.0: USB hub found
10613 04:51:28.402129 <6>[ 2.514788] hub 1-1:1.0: 4 ports detected
10614 04:51:28.405298 <6>[ 2.518047] hub 1-1:1.0: USB hub found
10615 04:51:28.408350 <6>[ 2.518402] hub 1-1:1.0: 4 ports detected
10616 04:51:28.422484 <6>[ 2.641865] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10617 04:51:28.443133 <6>[ 2.667005] hub 2-1:1.0: USB hub found
10618 04:51:28.446593 <6>[ 2.667372] hub 2-1:1.0: 3 ports detected
10619 04:51:28.449889 <6>[ 2.670205] hub 2-1:1.0: USB hub found
10620 04:51:28.453077 <6>[ 2.670572] hub 2-1:1.0: 3 ports detected
10621 04:51:28.610115 <6>[ 2.829697] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10622 04:51:28.730788 <6>[ 2.956989] hub 1-1.4:1.0: USB hub found
10623 04:51:28.734112 <6>[ 2.957337] hub 1-1.4:1.0: 2 ports detected
10624 04:51:28.737450 <6>[ 2.960317] hub 1-1.4:1.0: USB hub found
10625 04:51:28.744066 <6>[ 2.960652] hub 1-1.4:1.0: 2 ports detected
10626 04:51:28.814281 <6>[ 3.033883] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10627 04:51:29.030193 <6>[ 3.249665] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10628 04:51:29.214100 <6>[ 3.433667] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10629 04:51:40.046605 <6>[ 14.274639] ALSA device list:
10630 04:51:40.053342 <6>[ 14.274660] No soundcards found.
10631 04:51:40.056623 <6>[ 14.279125] Freeing unused kernel memory: 8448K
10632 04:51:40.059723 <6>[ 14.279295] Run /init as init process
10633 04:51:40.097865 <6>[ 14.322028] NET: Registered PF_INET6 protocol family
10634 04:51:40.101027 <6>[ 14.323226] Segment Routing with IPv6
10635 04:51:40.107928 <6>[ 14.323240] In-situ OAM (IOAM) with IPv6
10636 04:51:40.111867
10637 04:51:40.134929 Welcome to [1mDebian GNU/Linu<30>[ 14.342044] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10638 04:51:40.141870 x 11 (bullseye)<30>[ 14.342658] systemd[1]: Detected architecture arm64.
10639 04:51:40.144827 [0m!
10640 04:51:40.145315
10641 04:51:40.165742 <30>[ 14.389571] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10642 04:51:40.284783 <30>[ 14.506605] systemd[1]: Queued start job for default target Graphical Interface.
10643 04:51:40.314437 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.538388] systemd[1]: Created slice system-getty.slice.
10644 04:51:40.317243 m-getty.slice[0m.
10645 04:51:40.341047 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.562256] systemd[1]: Created slice system-modprobe.slice.
10646 04:51:40.341631 m-modprobe.slice[0m.
10647 04:51:40.362355 [[0;32m OK [0m] Created slic<30>[ 14.586659] systemd[1]: Created slice system-serial\x2dgetty.slice.
10648 04:51:40.368471 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10649 04:51:40.386760 [[0;32m OK [0m] Created slic<30>[ 14.611285] systemd[1]: Created slice User and Session Slice.
10650 04:51:40.390078 e [0;1;39mUser and Session Slice[0m.
10651 04:51:40.413749 [[0;32m OK [0m] Started [0;<30>[ 14.634530] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10652 04:51:40.416832 1;39mDispatch Password …ts to Console Directory Watch[0m.
10653 04:51:40.441597 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 14.662413] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10654 04:51:40.444671 sword R…uests to Wall Directory Watch[0m.
10655 04:51:40.472703 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 14.690179] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10656 04:51:40.479168 <30>[ 14.690433] systemd[1]: Reached target Local Encrypted Volumes.
10657 04:51:40.482248 l Encrypted Volumes[0m.
10658 04:51:40.501759 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 14.726221] systemd[1]: Reached target Paths.
10659 04:51:40.502390 s[0m.
10660 04:51:40.524486 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 14.745649] systemd[1]: Reached target Remote File Systems.
10661 04:51:40.525065 te File Systems[0m.
10662 04:51:40.545847 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 14.770054] systemd[1]: Reached target Slices.
10663 04:51:40.546466 es[0m.
10664 04:51:40.565017 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 14.789666] systemd[1]: Reached target Swap.
10665 04:51:40.565592 [0m.
10666 04:51:40.589050 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 14.810168] systemd[1]: Listening on initctl Compatibility Named Pipe.
10667 04:51:40.592158 l Compatibility Named Pipe[0m.
10668 04:51:40.598640 <30>[ 14.825318] systemd[1]: Listening on Journal Audit Socket.
10669 04:51:40.605592 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10670 04:51:40.622617 [[0;32m OK [0m] Listening on<30>[ 14.846830] systemd[1]: Listening on Journal Socket (/dev/log).
10671 04:51:40.625811 [0;1;39mJournal Socket (/dev/log)[0m.
10672 04:51:40.646906 [[0;32m OK [0m] Listening on<30>[ 14.870902] systemd[1]: Listening on Journal Socket.
10673 04:51:40.649902 [0;1;39mJournal Socket[0m.
10674 04:51:40.669204 [[0;32m OK [0m] Listening on [0;1;39mNetwor<30>[ 14.890343] systemd[1]: Listening on Network Service Netlink Socket.
10675 04:51:40.672136 k Service Netlink Socket[0m.
10676 04:51:40.689733 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 14.914195] systemd[1]: Listening on udev Control Socket.
10677 04:51:40.693301 ontrol Socket[0m.
10678 04:51:40.714633 [[0;32m OK [0m] Listening on<30>[ 14.938755] systemd[1]: Listening on udev Kernel Socket.
10679 04:51:40.717318 [0;1;39mudev Kernel Socket[0m.
10680 04:51:40.777176 Mounting [0;1;39mHuge Pages File Syste<30>[ 14.997890] systemd[1]: Mounting Huge Pages File System...
10681 04:51:40.777760 m[0m...
10682 04:51:40.800814 Mounting [0;1;39mPOSIX Message Queue F<30>[ 15.021739] systemd[1]: Mounting POSIX Message Queue File System...
10683 04:51:40.801401 ile System[0m...
10684 04:51:40.828781 Mounting [0;1;39mKernel Debug File Sys<30>[ 15.049627] systemd[1]: Mounting Kernel Debug File System...
10685 04:51:40.829366 tem[0m...
10686 04:51:40.849389 <30>[ 15.070160] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10687 04:51:40.862464 Starting [0;1;39mCreate list of st…o<30>[ 15.074547] systemd[1]: Starting Create list of static device nodes for the current kernel...
10688 04:51:40.865518 des for the current kernel[0m...
10689 04:51:40.892339 Starting [0;1;39mLoad Kernel Module co<30>[ 15.113630] systemd[1]: Starting Load Kernel Module configfs...
10690 04:51:40.892905 nfigfs[0m...
10691 04:51:40.911537 Startin<30>[ 15.136085] systemd[1]: Starting Load Kernel Module drm...
10692 04:51:40.914770 g [0;1;39mLoad Kernel Module drm[0m...
10693 04:51:40.936698 <30>[ 15.158013] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10694 04:51:40.949610 Starting [0;1;39mJournal Service[0m..<30>[ 15.174039] systemd[1]: Starting Journal Service...
10695 04:51:40.950228 .
10696 04:51:40.971884 Startin<30>[ 15.196570] systemd[1]: Starting Load Kernel Modules...
10697 04:51:40.975218 g [0;1;39mLoad Kernel Modules[0m...
10698 04:51:40.998623 Starting [0;1;39mRemou<30>[ 15.222919] systemd[1]: Starting Remount Root and Kernel File Systems...
10699 04:51:41.005550 nt Root and Kernel File Systems[0m...
10700 04:51:41.026720 Starting [0;1;39mColdp<30>[ 15.250319] systemd[1]: Starting Coldplug All udev Devices...
10701 04:51:41.029716 lug All udev Devices[0m...
10702 04:51:41.050863 [[0;32m OK [0m] Started [0;<30>[ 15.274848] systemd[1]: Started Journal Service.
10703 04:51:41.053733 1;39mJournal Service[0m.
10704 04:51:41.067816 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10705 04:51:41.082674 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10706 04:51:41.098680 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10707 04:51:41.118685 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10708 04:51:41.139236 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10709 04:51:41.159227 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10710 04:51:41.179799 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10711 04:51:41.202354 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10712 04:51:41.221989 See 'systemctl status systemd-remount-fs.service' for details.
10713 04:51:41.274509 Mounting [0;1;39mKernel Configuration File System[0m...
10714 04:51:41.296827 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10715 04:51:41.313021 <46>[ 15.534936] systemd-journald[192]: Received client request to flush runtime journal.
10716 04:51:41.321861 Starting [0;1;39mLoad/Save Random Seed[0m...
10717 04:51:41.341247 Starting [0;1;39mApply Kernel Variables[0m...
10718 04:51:41.363456 Starting [0;1;39mCreate System Users[0m...
10719 04:51:41.386445 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10720 04:51:41.406949 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10721 04:51:41.430738 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10722 04:51:41.447662 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10723 04:51:41.464013 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10724 04:51:41.479305 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10725 04:51:41.543310 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10726 04:51:41.563615 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10727 04:51:41.579578 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10728 04:51:41.593825 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10729 04:51:41.650615 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10730 04:51:41.674380 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10731 04:51:41.696432 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10732 04:51:41.717203 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10733 04:51:41.773092 Starting [0;1;39mNetwork Service[0m...
10734 04:51:41.804551 Starting [0;1;39mNetwork Time Synchronization[0m...
10735 04:51:41.828639 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10736 04:51:41.852896 <6>[ 16.076823] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10737 04:51:41.856485 <6>[ 16.081274] remoteproc remoteproc0: scp is available
10738 04:51:41.863151 <6>[ 16.081579] remoteproc remoteproc0: powering up scp
10739 04:51:41.874505 <6>[ 16.081587] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10740 04:51:41.881251 [[0;32m OK [<6>[ 16.081607] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10741 04:51:41.887509 0m] Started [0;1;39mNetwork Service[0m.
10742 04:51:41.904615 <6>[ 16.128641] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10743 04:51:41.911317 <6>[ 16.128707] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10744 04:51:41.921643 <6>[ 16.128718] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10745 04:51:41.928174 [[0;32m OK [<6>[ 16.156424] mc: Linux media interface: v0.10
10746 04:51:41.941565 0m] Started [0;1;39mNetwork Time Synchronizatio<6>[ 16.164914] usbcore: registered new device driver r8152-cfgselector
10747 04:51:41.942195 n[0m.
10748 04:51:41.944933 <6>[ 16.165130] videodev: Linux video capture interface: v2.00
10749 04:51:41.955413 <3>[ 16.167715] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 04:51:41.962084 <3>[ 16.167735] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 04:51:41.972735 <3>[ 16.167743] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 04:51:41.979241 <3>[ 16.167861] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 04:51:41.989000 <3>[ 16.167869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10754 04:51:41.995828 <3>[ 16.167875] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10755 04:51:42.005931 <3>[ 16.167885] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10756 04:51:42.012772 [[0;32m OK [<3>[ 16.167893] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 04:51:42.022896 0m] Finished [0<3>[ 16.167959] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 04:51:42.032792 ;1;39mUpdate UTM<3>[ 16.168010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 04:51:42.040029 <3>[ 16.168017] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10760 04:51:42.050193 <3>[ 16.168024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 04:51:42.056876 <3>[ 16.169760] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 04:51:42.066732 <3>[ 16.169779] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10763 04:51:42.073195 <3>[ 16.169788] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 04:51:42.083559 P about System B<3>[ 16.169802] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 04:51:42.090203 <3>[ 16.169814] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 04:51:42.097232 <3>[ 16.169869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 04:51:42.107240 oot/Shutdown[0m<6>[ 16.175551] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10768 04:51:42.113815 <4>[ 16.194069] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10769 04:51:42.116860 .
10770 04:51:42.123694 <4>[ 16.194225] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10771 04:51:42.130553 <4>[ 16.202816] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10772 04:51:42.136981 <4>[ 16.202816] Fallback method does not support PEC.
10773 04:51:42.144238 <6>[ 16.211011] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10774 04:51:42.151187 <6>[ 16.213318] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10775 04:51:42.161497 [[0;32m OK [<6>[ 16.213362] remoteproc remoteproc0: remote processor scp is now up
10776 04:51:42.171219 0m] Found device<3>[ 16.220078] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10777 04:51:42.181594 [0;1;39m/dev/t<6>[ 16.255185] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10778 04:51:42.187973 <6>[ 16.258414] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10779 04:51:42.188555 tyS0[0m.
10780 04:51:42.195012 <6>[ 16.258686] pci_bus 0000:00: root bus resource [bus 00-ff]
10781 04:51:42.201242 <6>[ 16.258697] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10782 04:51:42.211983 <6>[ 16.258704] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10783 04:51:42.215592 <6>[ 16.258788] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10784 04:51:42.225236 <6>[ 16.258815] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10785 04:51:42.229285 <6>[ 16.258987] pci 0000:00:00.0: supports D1 D2
10786 04:51:42.235837 <6>[ 16.258991] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10787 04:51:42.245500 <6>[ 16.262072] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10788 04:51:42.252898 <3>[ 16.267364] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10789 04:51:42.263232 <3>[ 16.268212] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10790 04:51:42.273780 <6>[ 16.270400] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10791 04:51:42.280348 <4>[ 16.281639] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10792 04:51:42.290519 <4>[ 16.281659] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10793 04:51:42.297821 <6>[ 16.281820] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10794 04:51:42.304773 <6>[ 16.288570] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10795 04:51:42.315081 [[0;32m OK [<6>[ 16.288621] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10796 04:51:42.321571 0m] Created slic<6>[ 16.288644] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10797 04:51:42.331675 e [0;1;39msyste<6>[ 16.288661] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10798 04:51:42.335327 <6>[ 16.288788] pci 0000:01:00.0: supports D1 D2
10799 04:51:42.341570 <6>[ 16.288790] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10800 04:51:42.348588 <6>[ 16.306562] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10801 04:51:42.358758 <6>[ 16.306603] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10802 04:51:42.365115 <6>[ 16.306606] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10803 04:51:42.371522 <6>[ 16.306616] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10804 04:51:42.381480 <6>[ 16.306629] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10805 04:51:42.388177 <6>[ 16.306642] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10806 04:51:42.394562 <6>[ 16.306656] pci 0000:00:00.0: PCI bridge to [bus 01]
10807 04:51:42.401498 <6>[ 16.306661] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10808 04:51:42.408276 <6>[ 16.306834] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10809 04:51:42.414137 <6>[ 16.307388] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10810 04:51:42.420991 <6>[ 16.307739] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10811 04:51:42.427470 <6>[ 16.308219] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10812 04:51:42.437725 <6>[ 16.309548] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10813 04:51:42.447574 <6>[ 16.310306] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10814 04:51:42.454036 <3>[ 16.324755] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10815 04:51:42.464192 <3>[ 16.330003] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10816 04:51:42.470757 <5>[ 16.335025] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10817 04:51:42.477211 <5>[ 16.353763] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10818 04:51:42.486755 <5>[ 16.354218] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10819 04:51:42.493502 <4>[ 16.354298] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10820 04:51:42.500107 <6>[ 16.354307] cfg80211: failed to load regulatory.db
10821 04:51:42.503707 <6>[ 16.355995] r8152 2-1.3:1.0 eth0: v1.12.13
10822 04:51:42.510522 <6>[ 16.356058] usbcore: registered new interface driver r8152
10823 04:51:42.513590 <6>[ 16.381218] Bluetooth: Core ver 2.22
10824 04:51:42.520347 <6>[ 16.381456] NET: Registered PF_BLUETOOTH protocol family
10825 04:51:42.526576 <6>[ 16.381470] Bluetooth: HCI device and connection manager initialized
10826 04:51:42.530358 <6>[ 16.381510] Bluetooth: HCI socket layer initialized
10827 04:51:42.536493 <6>[ 16.381517] Bluetooth: L2CAP socket layer initialized
10828 04:51:42.543181 <6>[ 16.381544] Bluetooth: SCO socket layer initialized
10829 04:51:42.553175 m-systemd\x2dbac<3>[ 16.388307] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10830 04:51:42.560273 <3>[ 16.388910] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10831 04:51:42.566769 <6>[ 16.393750] usbcore: registered new interface driver cdc_ether
10832 04:51:42.573070 <6>[ 16.413409] usbcore: registered new interface driver r8153_ecm
10833 04:51:42.580527 <6>[ 16.422414] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10834 04:51:42.593169 <6>[ 16.423637] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10835 04:51:42.599259 <6>[ 16.423805] usbcore: registered new interface driver uvcvideo
10836 04:51:42.606333 <3>[ 16.424545] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10837 04:51:42.612715 <6>[ 16.429507] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10838 04:51:42.622897 <3>[ 16.444638] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10839 04:51:42.629287 <6>[ 16.445723] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10840 04:51:42.636223 <6>[ 16.458622] usbcore: registered new interface driver btusb
10841 04:51:42.647974 <4>[ 16.459520] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10842 04:51:42.652511 <3>[ 16.459543] Bluetooth: hci0: Failed to load firmware file (-2)
10843 04:51:42.655404 <3>[ 16.459547] Bluetooth: hci0: Failed to set up firmware (-2)
10844 04:51:42.665456 <4>[ 16.459551] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10845 04:51:42.675874 <3>[ 16.467054] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10846 04:51:42.682309 <6>[ 16.477844] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10847 04:51:42.689010 <6>[ 16.477948] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10848 04:51:42.695548 <6>[ 16.497587] mt7921e 0000:01:00.0: ASIC revision: 79610010
10849 04:51:42.702354 <6>[ 16.592325] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10850 04:51:42.705557 <6>[ 16.592325]
10851 04:51:42.715314 <6>[ 16.850458] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10852 04:51:42.715897 klight.slice[0m.
10853 04:51:42.733829 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10854 04:51:42.749639 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10855 04:51:42.765797 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10856 04:51:42.784839 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10857 04:51:42.824906 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10858 04:51:42.842982 Starting [0;1;39mNetwork Name Resolution[0m...
10859 04:51:42.862777 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10860 04:51:42.884165 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10861 04:51:42.905802 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10862 04:51:42.920983 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10863 04:51:42.934223 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10864 04:51:42.953268 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10865 04:51:42.965443 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10866 04:51:42.981913 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10867 04:51:43.022915 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10868 04:51:43.054168 Starting [0;1;39mUser Login Management[0m...
10869 04:51:43.075010 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10870 04:51:43.091685 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10871 04:51:43.107406 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10872 04:51:43.126286 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10873 04:51:43.149276 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10874 04:51:43.210510 Starting [0;1;39mPermit User Sessions[0m...
10875 04:51:43.226514 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10876 04:51:43.247751 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10877 04:51:43.302960 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10878 04:51:43.326761 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10879 04:51:43.346164 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10880 04:51:43.366190 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10881 04:51:43.382422 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10882 04:51:43.426807 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10883 04:51:43.453102 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10884 04:51:43.465474 <6>[ 17.690232] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10885 04:51:43.503592
10886 04:51:43.504160
10887 04:51:43.507233 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10888 04:51:43.507834
10889 04:51:43.510254 debian-bullseye-arm64 login: root (automatic login)
10890 04:51:43.510725
10891 04:51:43.511096
10892 04:51:43.539827 Linux debian-bullseye-arm64 6.1.75-cip14-rt8 #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024 aarch64
10893 04:51:43.540414
10894 04:51:43.546291 The programs included with the Debian GNU/Linux system are free software;
10895 04:51:43.553059 the exact distribution terms for each program are described in the
10896 04:51:43.556385 individual files in /usr/share/doc/*/copyright.
10897 04:51:43.556961
10898 04:51:43.562678 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10899 04:51:43.565961 permitted by applicable law.
10900 04:51:43.567434 Matched prompt #10: / #
10902 04:51:43.568563 Setting prompt string to ['/ #']
10903 04:51:43.569038 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10905 04:51:43.570124 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10906 04:51:43.570603 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
10907 04:51:43.570986 Setting prompt string to ['/ #']
10908 04:51:43.571333 Forcing a shell prompt, looking for ['/ #']
10910 04:51:43.622141 / #
10911 04:51:43.622801 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10912 04:51:43.623269 Waiting using forced prompt support (timeout 00:02:30)
10913 04:51:43.628605
10914 04:51:43.629584 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10915 04:51:43.630185 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
10916 04:51:43.630713 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10917 04:51:43.631196 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
10918 04:51:43.631665 end: 2 depthcharge-action (duration 00:01:28) [common]
10919 04:51:43.632172 start: 3 lava-test-retry (timeout 00:08:13) [common]
10920 04:51:43.632650 start: 3.1 lava-test-shell (timeout 00:08:13) [common]
10921 04:51:43.633064 Using namespace: common
10923 04:51:43.734524 / # #
10924 04:51:43.735182 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10925 04:51:43.735810 #<6>[ 17.955428] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
10926 04:51:43.736557 <6>[ 17.955946] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10927 04:51:43.778602
10928 04:51:43.779494 Using /lava-12699866
10930 04:51:43.880845 / # export SHELL=/bin/sh
10931 04:51:43.887698 export SHELL=/bin/sh
10933 04:51:43.989646 / # . /lava-12699866/environment
10934 04:51:43.996697 . /lava-12699866/environment
10936 04:51:44.098555 / # /lava-12699866/bin/lava-test-runner /lava-12699866/0
10937 04:51:44.099218 Test shell timeout: 10s (minimum of the action and connection timeout)
10938 04:51:44.105149 /lava-12699866/bin/lava-test-runner /lava-12699866/0
10939 04:51:44.128088 + export TESTRUN_ID=0_v4l2-compliance-uvc
10940 04:51:44.131784 + cd /lava-12699866/0/tests/0_v4l2-compliance-uvc
10941 04:51:44.132369 + cat uuid
10942 04:51:44.134764 + UUID=12699866_1.5.2.3.1
10943 04:51:44.135240 + set +x
10944 04:51:44.141548 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 12699866_1.5.2.3.1>
10945 04:51:44.142456 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 12699866_1.5.2.3.1
10946 04:51:44.142887 Starting test lava.0_v4l2-compliance-uvc (12699866_1.5.2.3.1)
10947 04:51:44.143343 Skipping test definition patterns.
10948 04:51:44.144489 + /usr/bin/v4l2-parser.sh -d uvcvideo
10949 04:51:44.151365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10950 04:51:44.151923 device: /dev/video0
10951 04:51:44.152558 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10953 04:51:50.635233 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
10954 04:51:50.649048 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
10955 04:51:50.658479
10956 04:51:50.673921 Compliance test for uvcvideo device /dev/video0:
10957 04:51:50.681826
10958 04:51:50.693475 Driver Info:
10959 04:51:50.704522 Driver name : uvcvideo
10960 04:51:50.718118 Card type : HD User Facing: HD User Facing
10961 04:51:50.733720 Bus info : usb-11200000.usb-1.4.1
10962 04:51:50.742559 Driver version : 6.1.75
10963 04:51:50.755953 Capabilities : 0x84a00001
10964 04:51:50.770503 Metadata Capture
10965 04:51:50.780224 Streaming
10966 04:51:50.791215 Extended Pix Format
10967 04:51:50.802991 Device Capabilities
10968 04:51:50.814751 Device Caps : 0x04200001
10969 04:51:50.827482 Streaming
10970 04:51:50.842135 Extended Pix Format
10971 04:51:50.851067 Media Driver Info:
10972 04:51:50.863343 Driver name : uvcvideo
10973 04:51:50.880598 Model : HD User Facing: HD User Facing
10974 04:51:50.887986 Serial : 200901010001
10975 04:51:50.905028 Bus info : usb-11200000.usb-1.4.1
10976 04:51:50.911662 Media version : 6.1.75
10977 04:51:50.926695 Hardware revision: 0x00009758 (38744)
10978 04:51:50.934889 Driver version : 6.1.75
10979 04:51:50.946421 Interface Info:
10980 04:51:50.961567 <LAVA_SIGNAL_TESTSET START Interface-Info>
10981 04:51:50.962170 ID : 0x03000002
10982 04:51:50.962828 Received signal: <TESTSET> START Interface-Info
10983 04:51:50.963227 Starting test_set Interface-Info
10984 04:51:50.971392 Type : V4L Video
10985 04:51:50.983122 Entity Info:
10986 04:51:50.989862 <LAVA_SIGNAL_TESTSET STOP>
10987 04:51:50.990725 Received signal: <TESTSET> STOP
10988 04:51:50.991145 Closing test_set Interface-Info
10989 04:51:51.000316 <LAVA_SIGNAL_TESTSET START Entity-Info>
10990 04:51:51.001155 Received signal: <TESTSET> START Entity-Info
10991 04:51:51.001552 Starting test_set Entity-Info
10992 04:51:51.003527 ID : 0x00000001 (1)
10993 04:51:51.013387 Name : HD User Facing: HD User Facing
10994 04:51:51.021576 Function : V4L2 I/O
10995 04:51:51.036810 Flags : default
10996 04:51:51.046993 Pad 0x01000007 : 0: Sink
10997 04:51:51.068882 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
10998 04:51:51.069532
10999 04:51:51.079167 Required ioctls:
11000 04:51:51.086654 <LAVA_SIGNAL_TESTSET STOP>
11001 04:51:51.087324 Received signal: <TESTSET> STOP
11002 04:51:51.087671 Closing test_set Entity-Info
11003 04:51:51.096108 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11004 04:51:51.097024 Received signal: <TESTSET> START Required-ioctls
11005 04:51:51.097423 Starting test_set Required-ioctls
11006 04:51:51.099471 test MC information (see 'Media Driver Info' above): OK
11007 04:51:51.128861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11008 04:51:51.129679 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11010 04:51:51.131575 test VIDIOC_QUERYCAP: OK
11011 04:51:51.150523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11012 04:51:51.151369 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11014 04:51:51.153218 test invalid ioctls: OK
11015 04:51:51.179505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11016 04:51:51.180080
11017 04:51:51.180724 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11019 04:51:51.190887 Allow for multiple opens:
11020 04:51:51.199090 <LAVA_SIGNAL_TESTSET STOP>
11021 04:51:51.199930 Received signal: <TESTSET> STOP
11022 04:51:51.200320 Closing test_set Required-ioctls
11023 04:51:51.211014 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11024 04:51:51.211897 Received signal: <TESTSET> START Allow-for-multiple-opens
11025 04:51:51.212339 Starting test_set Allow-for-multiple-opens
11026 04:51:51.214226 test second /dev/video0 open: OK
11027 04:51:51.237693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11028 04:51:51.238583 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11030 04:51:51.241112 test VIDIOC_QUERYCAP: OK
11031 04:51:51.263905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11032 04:51:51.264776 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11034 04:51:51.266574 test VIDIOC_G/S_PRIORITY: OK
11035 04:51:51.289862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11036 04:51:51.290763 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11038 04:51:51.292659 test for unlimited opens: OK
11039 04:51:51.316959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11040 04:51:51.317536
11041 04:51:51.318333 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11043 04:51:51.330533 Debug ioctls:
11044 04:51:51.338645 <LAVA_SIGNAL_TESTSET STOP>
11045 04:51:51.339510 Received signal: <TESTSET> STOP
11046 04:51:51.339939 Closing test_set Allow-for-multiple-opens
11047 04:51:51.348486 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11048 04:51:51.349335 Received signal: <TESTSET> START Debug-ioctls
11049 04:51:51.349768 Starting test_set Debug-ioctls
11050 04:51:51.352228 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11051 04:51:51.375311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11052 04:51:51.376187 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11054 04:51:51.381641 test VIDIOC_LOG_STATUS: OK (Not Supported)
11055 04:51:51.400524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11056 04:51:51.401107
11057 04:51:51.401871 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11059 04:51:51.410725 Input ioctls:
11060 04:51:51.417219 <LAVA_SIGNAL_TESTSET STOP>
11061 04:51:51.418107 Received signal: <TESTSET> STOP
11062 04:51:51.418545 Closing test_set Debug-ioctls
11063 04:51:51.427428 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11064 04:51:51.428301 Received signal: <TESTSET> START Input-ioctls
11065 04:51:51.428737 Starting test_set Input-ioctls
11066 04:51:51.430453 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11067 04:51:51.459108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11068 04:51:51.459963 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11070 04:51:51.462075 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11071 04:51:51.482339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11072 04:51:51.483188 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11074 04:51:51.488865 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11075 04:51:51.511050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11076 04:51:51.511900 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11078 04:51:51.516950 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11079 04:51:51.538629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11080 04:51:51.539482 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11082 04:51:51.541786 test VIDIOC_G/S/ENUMINPUT: OK
11083 04:51:51.567120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11084 04:51:51.567966 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11086 04:51:51.570416 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11087 04:51:51.596508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11088 04:51:51.597370 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11090 04:51:51.599830 Inputs: 1 Audio Inputs: 0 Tuners: 0
11091 04:51:51.606933
11092 04:51:51.624743 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11093 04:51:51.647014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11094 04:51:51.648074 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11096 04:51:51.653689 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11097 04:51:51.674110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11098 04:51:51.674947 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11100 04:51:51.680459 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11101 04:51:51.699737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11102 04:51:51.700588 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11104 04:51:51.706182 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11105 04:51:51.730508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11106 04:51:51.731358 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11108 04:51:51.733790 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11109 04:51:51.757545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11110 04:51:51.758473 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11112 04:51:51.763612
11113 04:51:51.781644 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11114 04:51:51.803844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11115 04:51:51.804697 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11117 04:51:51.810144 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11118 04:51:51.836437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11119 04:51:51.837290 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11121 04:51:51.839691 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11122 04:51:51.858426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11123 04:51:51.859296 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11125 04:51:51.861384 test VIDIOC_G/S_EDID: OK (Not Supported)
11126 04:51:51.886391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11127 04:51:51.886978
11128 04:51:51.887630 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11130 04:51:51.898629 Control ioctls (Input 0):
11131 04:51:51.907341 <LAVA_SIGNAL_TESTSET STOP>
11132 04:51:51.908189 Received signal: <TESTSET> STOP
11133 04:51:51.908586 Closing test_set Input-ioctls
11134 04:51:51.919391 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11135 04:51:51.920242 Received signal: <TESTSET> START Control-ioctls-Input-0
11136 04:51:51.920646 Starting test_set Control-ioctls-Input-0
11137 04:51:51.922688 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11138 04:51:51.947137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11139 04:51:51.947780 test VIDIOC_QUERYCTRL: OK
11140 04:51:51.948509 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11142 04:51:51.969224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11143 04:51:51.970050 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11145 04:51:51.972514 test VIDIOC_G/S_CTRL: OK
11146 04:51:51.994241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11147 04:51:51.995080 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11149 04:51:51.997224 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11150 04:51:52.018111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11151 04:51:52.018940 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11153 04:51:52.024554 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11154 04:51:52.050165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11155 04:51:52.051004 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11157 04:51:52.052914 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11158 04:51:52.073670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11159 04:51:52.074579 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11161 04:51:52.077295 Standard Controls: 16 Private Controls: 0
11162 04:51:52.083161
11163 04:51:52.093533 Format ioctls (Input 0):
11164 04:51:52.100480 <LAVA_SIGNAL_TESTSET STOP>
11165 04:51:52.101166 Received signal: <TESTSET> STOP
11166 04:51:52.101579 Closing test_set Control-ioctls-Input-0
11167 04:51:52.110694 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11168 04:51:52.111513 Received signal: <TESTSET> START Format-ioctls-Input-0
11169 04:51:52.111917 Starting test_set Format-ioctls-Input-0
11170 04:51:52.113727 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11171 04:51:52.142771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11172 04:51:52.143614 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11174 04:51:52.145430 test VIDIOC_G/S_PARM: OK
11175 04:51:52.165321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11176 04:51:52.166181 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11178 04:51:52.168292 test VIDIOC_G_FBUF: OK (Not Supported)
11179 04:51:52.189090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11180 04:51:52.189993 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11182 04:51:52.192253 test VIDIOC_G_FMT: OK
11183 04:51:52.218771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11184 04:51:52.219582 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11186 04:51:52.222274 test VIDIOC_TRY_FMT: OK
11187 04:51:52.243028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11188 04:51:52.243867 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11190 04:51:52.249476 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11191 04:51:52.258871 test VIDIOC_S_FMT: OK
11192 04:51:52.286992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11193 04:51:52.287832 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11195 04:51:52.290088 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11196 04:51:52.311178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11197 04:51:52.312015 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11199 04:51:52.314534 test Cropping: OK (Not Supported)
11200 04:51:52.336627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11201 04:51:52.337468 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11203 04:51:52.340071 test Composing: OK (Not Supported)
11204 04:51:52.365011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11205 04:51:52.365848 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11207 04:51:52.368657 test Scaling: OK (Not Supported)
11208 04:51:52.394242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11209 04:51:52.394813
11210 04:51:52.395456 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11212 04:51:52.406189 Codec ioctls (Input 0):
11213 04:51:52.413618 <LAVA_SIGNAL_TESTSET STOP>
11214 04:51:52.414473 Received signal: <TESTSET> STOP
11215 04:51:52.414866 Closing test_set Format-ioctls-Input-0
11216 04:51:52.423617 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11217 04:51:52.424474 Received signal: <TESTSET> START Codec-ioctls-Input-0
11218 04:51:52.424877 Starting test_set Codec-ioctls-Input-0
11219 04:51:52.427208 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11220 04:51:52.448656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11221 04:51:52.449499 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11223 04:51:52.455087 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11224 04:51:52.476083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11225 04:51:52.476920 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11227 04:51:52.482587 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11228 04:51:52.503319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11229 04:51:52.503891
11230 04:51:52.504528 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11232 04:51:52.519206 Buffer ioctls (Input 0):
11233 04:51:52.528432 <LAVA_SIGNAL_TESTSET STOP>
11234 04:51:52.529302 Received signal: <TESTSET> STOP
11235 04:51:52.529713 Closing test_set Codec-ioctls-Input-0
11236 04:51:52.539478 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11237 04:51:52.540322 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11238 04:51:52.540721 Starting test_set Buffer-ioctls-Input-0
11239 04:51:52.542468 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11240 04:51:52.567525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11241 04:51:52.568097 test VIDIOC_EXPBUF: OK
11242 04:51:52.568740 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11244 04:51:52.590069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11245 04:51:52.590917 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11247 04:51:52.593621 test Requests: OK (Not Supported)
11248 04:51:52.624764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11249 04:51:52.625319
11250 04:51:52.625978 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11252 04:51:52.636216 Test input 0:
11253 04:51:52.646376
11254 04:51:52.658606 Streaming ioctls:
11255 04:51:52.667370 <LAVA_SIGNAL_TESTSET STOP>
11256 04:51:52.668208 Received signal: <TESTSET> STOP
11257 04:51:52.668600 Closing test_set Buffer-ioctls-Input-0
11258 04:51:52.678807 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11259 04:51:52.679650 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11260 04:51:52.680059 Starting test_set Streaming-ioctls_Test-input-0
11261 04:51:52.682185 test read/write: OK (Not Supported)
11262 04:51:52.704885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11263 04:51:52.705720 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11265 04:51:52.707869 test blocking wait: OK
11266 04:51:52.730652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11267 04:51:52.731511 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11269 04:51:52.739810 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11270 04:51:52.743019 test MMAP (no poll): FAIL
11271 04:51:52.768288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11272 04:51:52.769128 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11274 04:51:52.777842 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11275 04:51:52.781231 test MMAP (select): FAIL
11276 04:51:52.803459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11277 04:51:52.804310 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11279 04:51:52.813357 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11280 04:51:52.816236 test MMAP (epoll): FAIL
11281 04:51:52.845581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11282 04:51:52.846184
11283 04:51:52.846841 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11285 04:51:52.858575
11286 04:51:53.058183
11287 04:51:53.068820 test USERPTR (no poll): OK
11288 04:51:53.094611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11289 04:51:53.095178
11290 04:51:53.095815 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11292 04:51:53.109983
11293 04:51:53.293520
11294 04:51:53.299940 test USERPTR (select): OK
11295 04:51:53.328847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11296 04:51:53.329693 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11298 04:51:53.335594 test DMABUF: Cannot test, specify --expbuf-device
11299 04:51:53.338776
11300 04:51:53.357118 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11301 04:51:53.360309 <LAVA_TEST_RUNNER EXIT>
11302 04:51:53.361147 ok: lava_test_shell seems to have completed
11303 04:51:53.361563 Marking unfinished test run as failed
11305 04:51:53.366864 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11306 04:51:53.367615 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11307 04:51:53.368097 end: 3 lava-test-retry (duration 00:00:10) [common]
11308 04:51:53.368593 start: 4 finalize (timeout 00:08:03) [common]
11309 04:51:53.369095 start: 4.1 power-off (timeout 00:00:30) [common]
11310 04:51:53.370169 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11311 04:51:53.454241 >> Command sent successfully.
11312 04:51:53.458833 Returned 0 in 0 seconds
11313 04:51:53.559825 end: 4.1 power-off (duration 00:00:00) [common]
11315 04:51:53.561327 start: 4.2 read-feedback (timeout 00:08:03) [common]
11316 04:51:53.562604 Listened to connection for namespace 'common' for up to 1s
11317 04:51:54.563217 Finalising connection for namespace 'common'
11318 04:51:54.563920 Disconnecting from shell: Finalise
11319 04:51:54.564335 / #
11320 04:51:54.665457 end: 4.2 read-feedback (duration 00:00:01) [common]
11321 04:51:54.666269 end: 4 finalize (duration 00:00:01) [common]
11322 04:51:54.666863 Cleaning after the job
11323 04:51:54.667465 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699866/tftp-deploy-ha4svlpj/ramdisk
11324 04:51:54.688158 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699866/tftp-deploy-ha4svlpj/kernel
11325 04:51:54.708842 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699866/tftp-deploy-ha4svlpj/dtb
11326 04:51:54.709180 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699866/tftp-deploy-ha4svlpj/modules
11327 04:51:54.718311 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12699866
11328 04:51:54.777615 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12699866
11329 04:51:54.777793 Job finished correctly