Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: FAIL
- Errors: 2
- Kernel Warnings: 14
- Kernel Errors: 34
1 04:40:13.480248 lava-dispatcher, installed at version: 2023.10
2 04:40:13.480469 start: 0 validate
3 04:40:13.480603 Start time: 2024-02-04 04:40:13.480594+00:00 (UTC)
4 04:40:13.480718 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:40:13.480842 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 04:40:13.483600 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:40:13.483718 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:40:32.499262 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:40:32.500044 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:40:32.774666 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:40:32.775448 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 04:40:33.040095 Using caching service: 'http://localhost/cache/?uri=%s'
13 04:40:33.040826 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 04:40:36.047083 validate duration: 22.57
16 04:40:36.047346 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:40:36.047491 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:40:36.047582 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:40:36.047728 Not decompressing ramdisk as can be used compressed.
20 04:40:36.047826 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 04:40:36.047889 saving as /var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/ramdisk/initrd.cpio.gz
22 04:40:36.047956 total size: 4665412 (4 MB)
23 04:40:36.312550 progress 0 % (0 MB)
24 04:40:36.314304 progress 5 % (0 MB)
25 04:40:36.315714 progress 10 % (0 MB)
26 04:40:36.316989 progress 15 % (0 MB)
27 04:40:36.318304 progress 20 % (0 MB)
28 04:40:36.319736 progress 25 % (1 MB)
29 04:40:36.321195 progress 30 % (1 MB)
30 04:40:36.322511 progress 35 % (1 MB)
31 04:40:36.323870 progress 40 % (1 MB)
32 04:40:36.325390 progress 45 % (2 MB)
33 04:40:36.326722 progress 50 % (2 MB)
34 04:40:36.328154 progress 55 % (2 MB)
35 04:40:36.329487 progress 60 % (2 MB)
36 04:40:36.330785 progress 65 % (2 MB)
37 04:40:36.332229 progress 70 % (3 MB)
38 04:40:36.333556 progress 75 % (3 MB)
39 04:40:36.334856 progress 80 % (3 MB)
40 04:40:36.336502 progress 85 % (3 MB)
41 04:40:36.337740 progress 90 % (4 MB)
42 04:40:36.339004 progress 95 % (4 MB)
43 04:40:36.340554 progress 100 % (4 MB)
44 04:40:36.340715 4 MB downloaded in 0.29 s (15.20 MB/s)
45 04:40:36.340871 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:40:36.341115 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:40:36.341232 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:40:36.341318 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:40:36.341460 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 04:40:36.341534 saving as /var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/kernel/Image
52 04:40:36.341609 total size: 51597824 (49 MB)
53 04:40:36.341685 No compression specified
54 04:40:36.342881 progress 0 % (0 MB)
55 04:40:36.356566 progress 5 % (2 MB)
56 04:40:36.370334 progress 10 % (4 MB)
57 04:40:36.384443 progress 15 % (7 MB)
58 04:40:36.398114 progress 20 % (9 MB)
59 04:40:36.412087 progress 25 % (12 MB)
60 04:40:36.425763 progress 30 % (14 MB)
61 04:40:36.439201 progress 35 % (17 MB)
62 04:40:36.452777 progress 40 % (19 MB)
63 04:40:36.467027 progress 45 % (22 MB)
64 04:40:36.481239 progress 50 % (24 MB)
65 04:40:36.495131 progress 55 % (27 MB)
66 04:40:36.508875 progress 60 % (29 MB)
67 04:40:36.522638 progress 65 % (32 MB)
68 04:40:36.536308 progress 70 % (34 MB)
69 04:40:36.549827 progress 75 % (36 MB)
70 04:40:36.563454 progress 80 % (39 MB)
71 04:40:36.577096 progress 85 % (41 MB)
72 04:40:36.590829 progress 90 % (44 MB)
73 04:40:36.604389 progress 95 % (46 MB)
74 04:40:36.617848 progress 100 % (49 MB)
75 04:40:36.618118 49 MB downloaded in 0.28 s (177.96 MB/s)
76 04:40:36.618282 end: 1.2.1 http-download (duration 00:00:00) [common]
78 04:40:36.618516 end: 1.2 download-retry (duration 00:00:00) [common]
79 04:40:36.618609 start: 1.3 download-retry (timeout 00:09:59) [common]
80 04:40:36.618696 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 04:40:36.618833 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 04:40:36.618904 saving as /var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/dtb/mt8192-asurada-spherion-r0.dtb
83 04:40:36.618966 total size: 47278 (0 MB)
84 04:40:36.619029 No compression specified
85 04:40:36.620212 progress 69 % (0 MB)
86 04:40:36.620501 progress 100 % (0 MB)
87 04:40:36.620664 0 MB downloaded in 0.00 s (26.61 MB/s)
88 04:40:36.620793 end: 1.3.1 http-download (duration 00:00:00) [common]
90 04:40:36.621025 end: 1.3 download-retry (duration 00:00:00) [common]
91 04:40:36.621112 start: 1.4 download-retry (timeout 00:09:59) [common]
92 04:40:36.621195 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 04:40:36.621318 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 04:40:36.621387 saving as /var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/nfsrootfs/full.rootfs.tar
95 04:40:36.621449 total size: 125290964 (119 MB)
96 04:40:36.621511 Using unxz to decompress xz
97 04:40:36.625726 progress 0 % (0 MB)
98 04:40:36.957730 progress 5 % (6 MB)
99 04:40:37.298979 progress 10 % (11 MB)
100 04:40:37.637003 progress 15 % (17 MB)
101 04:40:37.830781 progress 20 % (23 MB)
102 04:40:38.010206 progress 25 % (29 MB)
103 04:40:38.371734 progress 30 % (35 MB)
104 04:40:38.732809 progress 35 % (41 MB)
105 04:40:39.135211 progress 40 % (47 MB)
106 04:40:39.536505 progress 45 % (53 MB)
107 04:40:39.942544 progress 50 % (59 MB)
108 04:40:40.308178 progress 55 % (65 MB)
109 04:40:40.678357 progress 60 % (71 MB)
110 04:40:41.033055 progress 65 % (77 MB)
111 04:40:41.407222 progress 70 % (83 MB)
112 04:40:41.806780 progress 75 % (89 MB)
113 04:40:42.247558 progress 80 % (95 MB)
114 04:40:42.703585 progress 85 % (101 MB)
115 04:40:42.963910 progress 90 % (107 MB)
116 04:40:43.318858 progress 95 % (113 MB)
117 04:40:43.702891 progress 100 % (119 MB)
118 04:40:43.709200 119 MB downloaded in 7.09 s (16.86 MB/s)
119 04:40:43.709541 end: 1.4.1 http-download (duration 00:00:07) [common]
121 04:40:43.709830 end: 1.4 download-retry (duration 00:00:07) [common]
122 04:40:43.709923 start: 1.5 download-retry (timeout 00:09:52) [common]
123 04:40:43.710016 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 04:40:43.710171 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 04:40:43.710245 saving as /var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/modules/modules.tar
126 04:40:43.710309 total size: 8633524 (8 MB)
127 04:40:43.710375 Using unxz to decompress xz
128 04:40:43.715756 progress 0 % (0 MB)
129 04:40:43.739319 progress 5 % (0 MB)
130 04:40:43.765280 progress 10 % (0 MB)
131 04:40:43.789927 progress 15 % (1 MB)
132 04:40:43.815144 progress 20 % (1 MB)
133 04:40:43.839987 progress 25 % (2 MB)
134 04:40:43.870395 progress 30 % (2 MB)
135 04:40:43.900055 progress 35 % (2 MB)
136 04:40:43.931933 progress 40 % (3 MB)
137 04:40:43.964783 progress 45 % (3 MB)
138 04:40:43.993832 progress 50 % (4 MB)
139 04:40:44.019430 progress 55 % (4 MB)
140 04:40:44.046769 progress 60 % (4 MB)
141 04:40:44.073080 progress 65 % (5 MB)
142 04:40:44.105972 progress 70 % (5 MB)
143 04:40:44.130385 progress 75 % (6 MB)
144 04:40:44.158054 progress 80 % (6 MB)
145 04:40:44.184473 progress 85 % (7 MB)
146 04:40:44.212260 progress 90 % (7 MB)
147 04:40:44.242917 progress 95 % (7 MB)
148 04:40:44.271320 progress 100 % (8 MB)
149 04:40:44.276897 8 MB downloaded in 0.57 s (14.53 MB/s)
150 04:40:44.277302 end: 1.5.1 http-download (duration 00:00:01) [common]
152 04:40:44.277779 end: 1.5 download-retry (duration 00:00:01) [common]
153 04:40:44.277878 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 04:40:44.277979 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 04:40:46.527149 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12699805/extract-nfsrootfs-yh0oczb8
156 04:40:46.527345 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 04:40:46.527493 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 04:40:46.527653 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy
159 04:40:46.527785 makedir: /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin
160 04:40:46.527889 makedir: /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/tests
161 04:40:46.527990 makedir: /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/results
162 04:40:46.528089 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-add-keys
163 04:40:46.528237 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-add-sources
164 04:40:46.528368 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-background-process-start
165 04:40:46.528499 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-background-process-stop
166 04:40:46.528629 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-common-functions
167 04:40:46.528756 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-echo-ipv4
168 04:40:46.528883 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-install-packages
169 04:40:46.529010 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-installed-packages
170 04:40:46.529135 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-os-build
171 04:40:46.529263 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-probe-channel
172 04:40:46.529389 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-probe-ip
173 04:40:46.529514 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-target-ip
174 04:40:46.529639 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-target-mac
175 04:40:46.529765 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-target-storage
176 04:40:46.529894 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-test-case
177 04:40:46.530023 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-test-event
178 04:40:46.530148 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-test-feedback
179 04:40:46.530274 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-test-raise
180 04:40:46.530398 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-test-reference
181 04:40:46.530524 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-test-runner
182 04:40:46.530650 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-test-set
183 04:40:46.530775 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-test-shell
184 04:40:46.530904 Updating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-install-packages (oe)
185 04:40:46.531058 Updating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/bin/lava-installed-packages (oe)
186 04:40:46.531191 Creating /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/environment
187 04:40:46.531293 LAVA metadata
188 04:40:46.531387 - LAVA_JOB_ID=12699805
189 04:40:46.531469 - LAVA_DISPATCHER_IP=192.168.201.1
190 04:40:46.531572 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 04:40:46.531641 skipped lava-vland-overlay
192 04:40:46.531716 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 04:40:46.531796 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 04:40:46.531858 skipped lava-multinode-overlay
195 04:40:46.531932 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 04:40:46.532011 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 04:40:46.532085 Loading test definitions
198 04:40:46.532174 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 04:40:46.532245 Using /lava-12699805 at stage 0
200 04:40:46.532560 uuid=12699805_1.6.2.3.1 testdef=None
201 04:40:46.532651 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 04:40:46.532737 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 04:40:46.533251 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 04:40:46.533473 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 04:40:46.534114 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 04:40:46.534344 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 04:40:46.534994 runner path: /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/0/tests/0_dmesg test_uuid 12699805_1.6.2.3.1
210 04:40:46.535153 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 04:40:46.535406 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 04:40:46.535494 Using /lava-12699805 at stage 1
214 04:40:46.535796 uuid=12699805_1.6.2.3.5 testdef=None
215 04:40:46.535886 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 04:40:46.535972 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 04:40:46.536444 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 04:40:46.536662 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 04:40:46.537400 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 04:40:46.537628 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 04:40:46.538328 runner path: /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/1/tests/1_bootrr test_uuid 12699805_1.6.2.3.5
224 04:40:46.538498 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 04:40:46.538706 Creating lava-test-runner.conf files
227 04:40:46.538769 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/0 for stage 0
228 04:40:46.538861 - 0_dmesg
229 04:40:46.538941 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12699805/lava-overlay-6dl3axpy/lava-12699805/1 for stage 1
230 04:40:46.539033 - 1_bootrr
231 04:40:46.539128 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 04:40:46.539214 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 04:40:46.546881 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 04:40:46.547009 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 04:40:46.547110 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 04:40:46.547226 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 04:40:46.547325 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:49) [common]
238 04:40:46.669642 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 04:40:46.670039 start: 1.6.4 extract-modules (timeout 00:09:49) [common]
240 04:40:46.670161 extracting modules file /var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699805/extract-nfsrootfs-yh0oczb8
241 04:40:46.895863 extracting modules file /var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699805/extract-overlay-ramdisk-fi2rn7pg/ramdisk
242 04:40:47.138953 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 04:40:47.139132 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 04:40:47.139231 [common] Applying overlay to NFS
245 04:40:47.139305 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699805/compress-overlay-66rm1cqd/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12699805/extract-nfsrootfs-yh0oczb8
246 04:40:47.148143 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 04:40:47.148305 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 04:40:47.148417 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 04:40:47.148505 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 04:40:47.148588 Building ramdisk /var/lib/lava/dispatcher/tmp/12699805/extract-overlay-ramdisk-fi2rn7pg/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12699805/extract-overlay-ramdisk-fi2rn7pg/ramdisk
251 04:40:47.456873 >> 119436 blocks
252 04:40:49.433134 rename /var/lib/lava/dispatcher/tmp/12699805/extract-overlay-ramdisk-fi2rn7pg/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/ramdisk/ramdisk.cpio.gz
253 04:40:49.433578 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 04:40:49.433706 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 04:40:49.433813 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 04:40:49.433918 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/kernel/Image'
257 04:41:02.908081 Returned 0 in 13 seconds
258 04:41:03.008855 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/kernel/image.itb
259 04:41:03.367280 output: FIT description: Kernel Image image with one or more FDT blobs
260 04:41:03.367808 output: Created: Sun Feb 4 04:41:03 2024
261 04:41:03.367926 output: Image 0 (kernel-1)
262 04:41:03.368024 output: Description:
263 04:41:03.368117 output: Created: Sun Feb 4 04:41:03 2024
264 04:41:03.368208 output: Type: Kernel Image
265 04:41:03.368298 output: Compression: lzma compressed
266 04:41:03.368389 output: Data Size: 12048508 Bytes = 11766.12 KiB = 11.49 MiB
267 04:41:03.368479 output: Architecture: AArch64
268 04:41:03.368565 output: OS: Linux
269 04:41:03.368652 output: Load Address: 0x00000000
270 04:41:03.368740 output: Entry Point: 0x00000000
271 04:41:03.368830 output: Hash algo: crc32
272 04:41:03.368921 output: Hash value: 3b31d50c
273 04:41:03.369010 output: Image 1 (fdt-1)
274 04:41:03.369094 output: Description: mt8192-asurada-spherion-r0
275 04:41:03.369178 output: Created: Sun Feb 4 04:41:03 2024
276 04:41:03.369263 output: Type: Flat Device Tree
277 04:41:03.369348 output: Compression: uncompressed
278 04:41:03.369432 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 04:41:03.369516 output: Architecture: AArch64
280 04:41:03.369598 output: Hash algo: crc32
281 04:41:03.369683 output: Hash value: cc4352de
282 04:41:03.369774 output: Image 2 (ramdisk-1)
283 04:41:03.369864 output: Description: unavailable
284 04:41:03.369950 output: Created: Sun Feb 4 04:41:03 2024
285 04:41:03.370035 output: Type: RAMDisk Image
286 04:41:03.370118 output: Compression: Unknown Compression
287 04:41:03.370198 output: Data Size: 17797402 Bytes = 17380.28 KiB = 16.97 MiB
288 04:41:03.370284 output: Architecture: AArch64
289 04:41:03.370370 output: OS: Linux
290 04:41:03.370456 output: Load Address: unavailable
291 04:41:03.370542 output: Entry Point: unavailable
292 04:41:03.370626 output: Hash algo: crc32
293 04:41:03.370711 output: Hash value: d0bf2e08
294 04:41:03.370794 output: Default Configuration: 'conf-1'
295 04:41:03.370879 output: Configuration 0 (conf-1)
296 04:41:03.370962 output: Description: mt8192-asurada-spherion-r0
297 04:41:03.371046 output: Kernel: kernel-1
298 04:41:03.371130 output: Init Ramdisk: ramdisk-1
299 04:41:03.371213 output: FDT: fdt-1
300 04:41:03.371297 output: Loadables: kernel-1
301 04:41:03.371426 output:
302 04:41:03.371755 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
303 04:41:03.371932 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
304 04:41:03.372086 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
305 04:41:03.372230 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:33) [common]
306 04:41:03.372349 No LXC device requested
307 04:41:03.372466 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 04:41:03.372594 start: 1.8 deploy-device-env (timeout 00:09:33) [common]
309 04:41:03.372712 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 04:41:03.372818 Checking files for TFTP limit of 4294967296 bytes.
311 04:41:03.373551 end: 1 tftp-deploy (duration 00:00:27) [common]
312 04:41:03.373694 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 04:41:03.373838 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 04:41:03.374026 substitutions:
315 04:41:03.374127 - {DTB}: 12699805/tftp-deploy-ft8eg3xo/dtb/mt8192-asurada-spherion-r0.dtb
316 04:41:03.374222 - {INITRD}: 12699805/tftp-deploy-ft8eg3xo/ramdisk/ramdisk.cpio.gz
317 04:41:03.374311 - {KERNEL}: 12699805/tftp-deploy-ft8eg3xo/kernel/Image
318 04:41:03.374398 - {LAVA_MAC}: None
319 04:41:03.374485 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12699805/extract-nfsrootfs-yh0oczb8
320 04:41:03.374600 - {NFS_SERVER_IP}: 192.168.201.1
321 04:41:03.374728 - {PRESEED_CONFIG}: None
322 04:41:03.374813 - {PRESEED_LOCAL}: None
323 04:41:03.374898 - {RAMDISK}: 12699805/tftp-deploy-ft8eg3xo/ramdisk/ramdisk.cpio.gz
324 04:41:03.374984 - {ROOT_PART}: None
325 04:41:03.375069 - {ROOT}: None
326 04:41:03.375152 - {SERVER_IP}: 192.168.201.1
327 04:41:03.375237 - {TEE}: None
328 04:41:03.375320 Parsed boot commands:
329 04:41:03.375443 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 04:41:03.375705 Parsed boot commands: tftpboot 192.168.201.1 12699805/tftp-deploy-ft8eg3xo/kernel/image.itb 12699805/tftp-deploy-ft8eg3xo/kernel/cmdline
331 04:41:03.375834 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 04:41:03.375960 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 04:41:03.376098 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 04:41:03.376225 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 04:41:03.376330 Not connected, no need to disconnect.
336 04:41:03.376443 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 04:41:03.376565 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 04:41:03.376668 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
339 04:41:03.381196 Setting prompt string to ['lava-test: # ']
340 04:41:03.381759 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 04:41:03.382000 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 04:41:03.382171 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 04:41:03.382315 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 04:41:03.382649 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
345 04:41:08.519325 >> Command sent successfully.
346 04:41:08.521933 Returned 0 in 5 seconds
347 04:41:08.622369 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 04:41:08.622720 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 04:41:08.622821 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 04:41:08.622913 Setting prompt string to 'Starting depthcharge on Spherion...'
352 04:41:08.622982 Changing prompt to 'Starting depthcharge on Spherion...'
353 04:41:08.623049 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 04:41:08.623321 [Enter `^Ec?' for help]
355 04:41:08.797750
356 04:41:08.797913
357 04:41:08.797987 F0: 102B 0000
358 04:41:08.798051
359 04:41:08.798109 F3: 1001 0000 [0200]
360 04:41:08.800956
361 04:41:08.801056 F3: 1001 0000
362 04:41:08.801121
363 04:41:08.801182 F7: 102D 0000
364 04:41:08.801243
365 04:41:08.804761 F1: 0000 0000
366 04:41:08.804868
367 04:41:08.804938 V0: 0000 0000 [0001]
368 04:41:08.805003
369 04:41:08.807533 00: 0007 8000
370 04:41:08.807630
371 04:41:08.807697 01: 0000 0000
372 04:41:08.807760
373 04:41:08.811132 BP: 0C00 0209 [0000]
374 04:41:08.811236
375 04:41:08.811304 G0: 1182 0000
376 04:41:08.811393
377 04:41:08.814672 EC: 0000 0021 [4000]
378 04:41:08.814772
379 04:41:08.814838 S7: 0000 0000 [0000]
380 04:41:08.814899
381 04:41:08.818340 CC: 0000 0000 [0001]
382 04:41:08.818445
383 04:41:08.818511 T0: 0000 0040 [010F]
384 04:41:08.818573
385 04:41:08.821244 Jump to BL
386 04:41:08.821355
387 04:41:08.844823
388 04:41:08.844981
389 04:41:08.845055
390 04:41:08.851817 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 04:41:08.855312 ARM64: Exception handlers installed.
392 04:41:08.858838 ARM64: Testing exception
393 04:41:08.861890 ARM64: Done test exception
394 04:41:08.868397 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 04:41:08.878695 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 04:41:08.885443 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 04:41:08.895332 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 04:41:08.902071 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 04:41:08.912680 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 04:41:08.923131 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 04:41:08.929642 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 04:41:08.947876 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 04:41:08.951271 WDT: Last reset was cold boot
404 04:41:08.954656 SPI1(PAD0) initialized at 2873684 Hz
405 04:41:08.957399 SPI5(PAD0) initialized at 992727 Hz
406 04:41:08.960943 VBOOT: Loading verstage.
407 04:41:08.967295 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 04:41:08.971061 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 04:41:08.974278 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 04:41:08.977747 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 04:41:08.985411 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 04:41:08.992185 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 04:41:09.002714 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 04:41:09.002870
415 04:41:09.002944
416 04:41:09.012649 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 04:41:09.015692 ARM64: Exception handlers installed.
418 04:41:09.019302 ARM64: Testing exception
419 04:41:09.019441 ARM64: Done test exception
420 04:41:09.026819 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 04:41:09.029668 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 04:41:09.043583 Probing TPM: . done!
423 04:41:09.043727 TPM ready after 0 ms
424 04:41:09.051140 Connected to device vid:did:rid of 1ae0:0028:00
425 04:41:09.058368 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
426 04:41:09.114700 Initialized TPM device CR50 revision 0
427 04:41:09.126189 tlcl_send_startup: Startup return code is 0
428 04:41:09.126332 TPM: setup succeeded
429 04:41:09.137711 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 04:41:09.146572 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 04:41:09.158581 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 04:41:09.169043 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 04:41:09.172095 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 04:41:09.177904 in-header: 03 07 00 00 08 00 00 00
435 04:41:09.181033 in-data: aa e4 47 04 13 02 00 00
436 04:41:09.184516 Chrome EC: UHEPI supported
437 04:41:09.192033 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 04:41:09.195658 in-header: 03 95 00 00 08 00 00 00
439 04:41:09.199441 in-data: 18 20 20 08 00 00 00 00
440 04:41:09.199562 Phase 1
441 04:41:09.203831 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 04:41:09.207315 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 04:41:09.214360 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 04:41:09.218616 Recovery requested (1009000e)
445 04:41:09.226586 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 04:41:09.231778 tlcl_extend: response is 0
447 04:41:09.241384 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 04:41:09.246434 tlcl_extend: response is 0
449 04:41:09.253609 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 04:41:09.273310 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
451 04:41:09.280619 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 04:41:09.280770
453 04:41:09.280845
454 04:41:09.290304 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 04:41:09.293158 ARM64: Exception handlers installed.
456 04:41:09.296744 ARM64: Testing exception
457 04:41:09.296877 ARM64: Done test exception
458 04:41:09.319065 pmic_efuse_setting: Set efuses in 11 msecs
459 04:41:09.321873 pmwrap_interface_init: Select PMIF_VLD_RDY
460 04:41:09.329049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 04:41:09.332358 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 04:41:09.339283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 04:41:09.343173 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 04:41:09.346399 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 04:41:09.353861 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 04:41:09.357899 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 04:41:09.361509 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 04:41:09.365872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 04:41:09.373132 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 04:41:09.376447 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 04:41:09.380294 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 04:41:09.383317 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 04:41:09.390725 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 04:41:09.398688 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 04:41:09.401895 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 04:41:09.409086 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 04:41:09.413275 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 04:41:09.420326 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 04:41:09.423687 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 04:41:09.431327 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 04:41:09.434649 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 04:41:09.441752 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 04:41:09.445753 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 04:41:09.453063 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 04:41:09.457104 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 04:41:09.464607 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 04:41:09.467850 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 04:41:09.471675 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 04:41:09.478977 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 04:41:09.482564 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 04:41:09.486319 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 04:41:09.493574 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 04:41:09.496808 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 04:41:09.504498 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 04:41:09.508234 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 04:41:09.512178 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 04:41:09.519414 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 04:41:09.523019 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 04:41:09.526312 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 04:41:09.530134 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 04:41:09.534636 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 04:41:09.541039 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 04:41:09.545309 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 04:41:09.549106 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 04:41:09.552710 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 04:41:09.556608 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 04:41:09.559932 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 04:41:09.567214 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 04:41:09.570809 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 04:41:09.574370 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 04:41:09.581885 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 04:41:09.589177 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 04:41:09.596204 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 04:41:09.603323 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 04:41:09.611630 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 04:41:09.615289 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 04:41:09.619245 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 04:41:09.626730 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 04:41:09.633554 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x3b
520 04:41:09.637243 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 04:41:09.640809 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
522 04:41:09.647306 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 04:41:09.657075 [RTC]rtc_get_frequency_meter,154: input=15, output=853
524 04:41:09.665394 [RTC]rtc_get_frequency_meter,154: input=7, output=725
525 04:41:09.675352 [RTC]rtc_get_frequency_meter,154: input=11, output=790
526 04:41:09.685005 [RTC]rtc_get_frequency_meter,154: input=13, output=820
527 04:41:09.694318 [RTC]rtc_get_frequency_meter,154: input=12, output=805
528 04:41:09.704190 [RTC]rtc_get_frequency_meter,154: input=11, output=790
529 04:41:09.714118 [RTC]rtc_get_frequency_meter,154: input=12, output=805
530 04:41:09.717316 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
531 04:41:09.721708 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
532 04:41:09.725530 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 04:41:09.732130 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 04:41:09.736131 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 04:41:09.740015 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 04:41:09.743308 ADC[4]: Raw value=903694 ID=7
537 04:41:09.743469 ADC[3]: Raw value=213916 ID=1
538 04:41:09.747148 RAM Code: 0x71
539 04:41:09.750449 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 04:41:09.758239 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 04:41:09.765195 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 04:41:09.772878 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 04:41:09.776246 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 04:41:09.779687 in-header: 03 07 00 00 08 00 00 00
545 04:41:09.779808 in-data: aa e4 47 04 13 02 00 00
546 04:41:09.783279 Chrome EC: UHEPI supported
547 04:41:09.790908 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 04:41:09.794561 in-header: 03 95 00 00 08 00 00 00
549 04:41:09.798487 in-data: 18 20 20 08 00 00 00 00
550 04:41:09.801910 MRC: failed to locate region type 0.
551 04:41:09.809224 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 04:41:09.809365 DRAM-K: Running full calibration
553 04:41:09.816926 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 04:41:09.820335 header.status = 0x0
555 04:41:09.823672 header.version = 0x6 (expected: 0x6)
556 04:41:09.827344 header.size = 0xd00 (expected: 0xd00)
557 04:41:09.827515 header.flags = 0x0
558 04:41:09.834269 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 04:41:09.851573 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
560 04:41:09.859129 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 04:41:09.862783 dram_init: ddr_geometry: 2
562 04:41:09.862952 [EMI] MDL number = 2
563 04:41:09.866376 [EMI] Get MDL freq = 0
564 04:41:09.866476 dram_init: ddr_type: 0
565 04:41:09.870407 is_discrete_lpddr4: 1
566 04:41:09.873836 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 04:41:09.873992
568 04:41:09.874064
569 04:41:09.877598 [Bian_co] ETT version 0.0.0.1
570 04:41:09.880693 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 04:41:09.880794
572 04:41:09.884823 dramc_set_vcore_voltage set vcore to 650000
573 04:41:09.884925 Read voltage for 800, 4
574 04:41:09.888032 Vio18 = 0
575 04:41:09.888147 Vcore = 650000
576 04:41:09.888215 Vdram = 0
577 04:41:09.892047 Vddq = 0
578 04:41:09.892142 Vmddr = 0
579 04:41:09.892209 dram_init: config_dvfs: 1
580 04:41:09.898864 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 04:41:09.905658 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 04:41:09.908619 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
583 04:41:09.911657 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
584 04:41:09.916005 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
585 04:41:09.919853 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
586 04:41:09.919964 MEM_TYPE=3, freq_sel=18
587 04:41:09.923120 sv_algorithm_assistance_LP4_1600
588 04:41:09.930568 ============ PULL DRAM RESETB DOWN ============
589 04:41:09.934438 ========== PULL DRAM RESETB DOWN end =========
590 04:41:09.937745 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 04:41:09.941089 ===================================
592 04:41:09.944469 LPDDR4 DRAM CONFIGURATION
593 04:41:09.947601 ===================================
594 04:41:09.947698 EX_ROW_EN[0] = 0x0
595 04:41:09.951830 EX_ROW_EN[1] = 0x0
596 04:41:09.951926 LP4Y_EN = 0x0
597 04:41:09.954242 WORK_FSP = 0x0
598 04:41:09.954332 WL = 0x2
599 04:41:09.957456 RL = 0x2
600 04:41:09.957545 BL = 0x2
601 04:41:09.960842 RPST = 0x0
602 04:41:09.960935 RD_PRE = 0x0
603 04:41:09.963950 WR_PRE = 0x1
604 04:41:09.964055 WR_PST = 0x0
605 04:41:09.967568 DBI_WR = 0x0
606 04:41:09.967664 DBI_RD = 0x0
607 04:41:09.971269 OTF = 0x1
608 04:41:09.974169 ===================================
609 04:41:09.977354 ===================================
610 04:41:09.977452 ANA top config
611 04:41:09.980771 ===================================
612 04:41:09.984097 DLL_ASYNC_EN = 0
613 04:41:09.987315 ALL_SLAVE_EN = 1
614 04:41:09.990739 NEW_RANK_MODE = 1
615 04:41:09.994343 DLL_IDLE_MODE = 1
616 04:41:09.994440 LP45_APHY_COMB_EN = 1
617 04:41:09.997519 TX_ODT_DIS = 1
618 04:41:10.001464 NEW_8X_MODE = 1
619 04:41:10.004022 ===================================
620 04:41:10.007508 ===================================
621 04:41:10.010645 data_rate = 1600
622 04:41:10.014498 CKR = 1
623 04:41:10.014596 DQ_P2S_RATIO = 8
624 04:41:10.017595 ===================================
625 04:41:10.020715 CA_P2S_RATIO = 8
626 04:41:10.024659 DQ_CA_OPEN = 0
627 04:41:10.027870 DQ_SEMI_OPEN = 0
628 04:41:10.031263 CA_SEMI_OPEN = 0
629 04:41:10.031392 CA_FULL_RATE = 0
630 04:41:10.034279 DQ_CKDIV4_EN = 1
631 04:41:10.037712 CA_CKDIV4_EN = 1
632 04:41:10.041166 CA_PREDIV_EN = 0
633 04:41:10.044640 PH8_DLY = 0
634 04:41:10.044740 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 04:41:10.048182 DQ_AAMCK_DIV = 4
636 04:41:10.051442 CA_AAMCK_DIV = 4
637 04:41:10.055061 CA_ADMCK_DIV = 4
638 04:41:10.057836 DQ_TRACK_CA_EN = 0
639 04:41:10.061069 CA_PICK = 800
640 04:41:10.061180 CA_MCKIO = 800
641 04:41:10.064683 MCKIO_SEMI = 0
642 04:41:10.068115 PLL_FREQ = 3068
643 04:41:10.071901 DQ_UI_PI_RATIO = 32
644 04:41:10.075605 CA_UI_PI_RATIO = 0
645 04:41:10.079596 ===================================
646 04:41:10.079713 ===================================
647 04:41:10.083453 memory_type:LPDDR4
648 04:41:10.087649 GP_NUM : 10
649 04:41:10.087765 SRAM_EN : 1
650 04:41:10.091548 MD32_EN : 0
651 04:41:10.094264 ===================================
652 04:41:10.094363 [ANA_INIT] >>>>>>>>>>>>>>
653 04:41:10.098536 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 04:41:10.102034 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 04:41:10.105035 ===================================
656 04:41:10.108595 data_rate = 1600,PCW = 0X7600
657 04:41:10.111797 ===================================
658 04:41:10.115260 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 04:41:10.118344 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 04:41:10.124911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 04:41:10.128352 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 04:41:10.131498 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 04:41:10.135113 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 04:41:10.138601 [ANA_INIT] flow start
665 04:41:10.141908 [ANA_INIT] PLL >>>>>>>>
666 04:41:10.142003 [ANA_INIT] PLL <<<<<<<<
667 04:41:10.145005 [ANA_INIT] MIDPI >>>>>>>>
668 04:41:10.148640 [ANA_INIT] MIDPI <<<<<<<<
669 04:41:10.151538 [ANA_INIT] DLL >>>>>>>>
670 04:41:10.151639 [ANA_INIT] flow end
671 04:41:10.154743 ============ LP4 DIFF to SE enter ============
672 04:41:10.162008 ============ LP4 DIFF to SE exit ============
673 04:41:10.162139 [ANA_INIT] <<<<<<<<<<<<<
674 04:41:10.165664 [Flow] Enable top DCM control >>>>>
675 04:41:10.168422 [Flow] Enable top DCM control <<<<<
676 04:41:10.171572 Enable DLL master slave shuffle
677 04:41:10.178226 ==============================================================
678 04:41:10.178343 Gating Mode config
679 04:41:10.185486 ==============================================================
680 04:41:10.188405 Config description:
681 04:41:10.198247 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 04:41:10.205063 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 04:41:10.208047 SELPH_MODE 0: By rank 1: By Phase
684 04:41:10.215021 ==============================================================
685 04:41:10.218509 GAT_TRACK_EN = 1
686 04:41:10.218616 RX_GATING_MODE = 2
687 04:41:10.221277 RX_GATING_TRACK_MODE = 2
688 04:41:10.224759 SELPH_MODE = 1
689 04:41:10.228655 PICG_EARLY_EN = 1
690 04:41:10.231280 VALID_LAT_VALUE = 1
691 04:41:10.237785 ==============================================================
692 04:41:10.241281 Enter into Gating configuration >>>>
693 04:41:10.244542 Exit from Gating configuration <<<<
694 04:41:10.247777 Enter into DVFS_PRE_config >>>>>
695 04:41:10.257988 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 04:41:10.261139 Exit from DVFS_PRE_config <<<<<
697 04:41:10.264483 Enter into PICG configuration >>>>
698 04:41:10.268264 Exit from PICG configuration <<<<
699 04:41:10.271183 [RX_INPUT] configuration >>>>>
700 04:41:10.274593 [RX_INPUT] configuration <<<<<
701 04:41:10.277822 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 04:41:10.284361 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 04:41:10.291091 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 04:41:10.294314 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 04:41:10.301075 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 04:41:10.307412 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 04:41:10.310704 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 04:41:10.314300 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 04:41:10.321319 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 04:41:10.324164 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 04:41:10.327836 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 04:41:10.334399 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 04:41:10.337757 ===================================
714 04:41:10.337866 LPDDR4 DRAM CONFIGURATION
715 04:41:10.341584 ===================================
716 04:41:10.344163 EX_ROW_EN[0] = 0x0
717 04:41:10.348118 EX_ROW_EN[1] = 0x0
718 04:41:10.348216 LP4Y_EN = 0x0
719 04:41:10.350986 WORK_FSP = 0x0
720 04:41:10.351072 WL = 0x2
721 04:41:10.354332 RL = 0x2
722 04:41:10.354419 BL = 0x2
723 04:41:10.358008 RPST = 0x0
724 04:41:10.358101 RD_PRE = 0x0
725 04:41:10.361238 WR_PRE = 0x1
726 04:41:10.361328 WR_PST = 0x0
727 04:41:10.364552 DBI_WR = 0x0
728 04:41:10.364646 DBI_RD = 0x0
729 04:41:10.367687 OTF = 0x1
730 04:41:10.370601 ===================================
731 04:41:10.373899 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 04:41:10.378458 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 04:41:10.384063 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 04:41:10.387395 ===================================
735 04:41:10.387508 LPDDR4 DRAM CONFIGURATION
736 04:41:10.390777 ===================================
737 04:41:10.393812 EX_ROW_EN[0] = 0x10
738 04:41:10.393937 EX_ROW_EN[1] = 0x0
739 04:41:10.397401 LP4Y_EN = 0x0
740 04:41:10.400383 WORK_FSP = 0x0
741 04:41:10.400484 WL = 0x2
742 04:41:10.404072 RL = 0x2
743 04:41:10.404170 BL = 0x2
744 04:41:10.406993 RPST = 0x0
745 04:41:10.407108 RD_PRE = 0x0
746 04:41:10.410217 WR_PRE = 0x1
747 04:41:10.410305 WR_PST = 0x0
748 04:41:10.413857 DBI_WR = 0x0
749 04:41:10.413950 DBI_RD = 0x0
750 04:41:10.417355 OTF = 0x1
751 04:41:10.420313 ===================================
752 04:41:10.426984 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 04:41:10.430791 nWR fixed to 40
754 04:41:10.431016 [ModeRegInit_LP4] CH0 RK0
755 04:41:10.433612 [ModeRegInit_LP4] CH0 RK1
756 04:41:10.437382 [ModeRegInit_LP4] CH1 RK0
757 04:41:10.440521 [ModeRegInit_LP4] CH1 RK1
758 04:41:10.440633 match AC timing 13
759 04:41:10.443371 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 04:41:10.450916 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 04:41:10.453699 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 04:41:10.456691 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 04:41:10.463280 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 04:41:10.463435 [EMI DOE] emi_dcm 0
765 04:41:10.469895 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 04:41:10.470015 ==
767 04:41:10.473251 Dram Type= 6, Freq= 0, CH_0, rank 0
768 04:41:10.477136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 04:41:10.477249 ==
770 04:41:10.484155 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 04:41:10.486840 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 04:41:10.497217 [CA 0] Center 37 (7~68) winsize 62
773 04:41:10.500421 [CA 1] Center 37 (6~68) winsize 63
774 04:41:10.503957 [CA 2] Center 34 (4~65) winsize 62
775 04:41:10.507026 [CA 3] Center 35 (4~66) winsize 63
776 04:41:10.510295 [CA 4] Center 33 (3~64) winsize 62
777 04:41:10.513761 [CA 5] Center 33 (3~64) winsize 62
778 04:41:10.513865
779 04:41:10.516800 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 04:41:10.516892
781 04:41:10.520590 [CATrainingPosCal] consider 1 rank data
782 04:41:10.523698 u2DelayCellTimex100 = 270/100 ps
783 04:41:10.526906 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
784 04:41:10.530365 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
785 04:41:10.537493 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
786 04:41:10.540701 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
787 04:41:10.543665 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
788 04:41:10.546959 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 04:41:10.547095
790 04:41:10.550297 CA PerBit enable=1, Macro0, CA PI delay=33
791 04:41:10.550420
792 04:41:10.553925 [CBTSetCACLKResult] CA Dly = 33
793 04:41:10.554029 CS Dly: 5 (0~36)
794 04:41:10.557056 ==
795 04:41:10.557154 Dram Type= 6, Freq= 0, CH_0, rank 1
796 04:41:10.563456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 04:41:10.563598 ==
798 04:41:10.566682 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 04:41:10.573398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 04:41:10.583789 [CA 0] Center 38 (7~69) winsize 63
801 04:41:10.586884 [CA 1] Center 37 (7~68) winsize 62
802 04:41:10.590645 [CA 2] Center 35 (4~66) winsize 63
803 04:41:10.593446 [CA 3] Center 35 (4~66) winsize 63
804 04:41:10.597288 [CA 4] Center 34 (3~65) winsize 63
805 04:41:10.599990 [CA 5] Center 33 (3~64) winsize 62
806 04:41:10.600098
807 04:41:10.603104 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 04:41:10.603198
809 04:41:10.607279 [CATrainingPosCal] consider 2 rank data
810 04:41:10.609737 u2DelayCellTimex100 = 270/100 ps
811 04:41:10.613681 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
812 04:41:10.619957 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
813 04:41:10.623357 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
814 04:41:10.626718 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
815 04:41:10.629681 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
816 04:41:10.633950 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 04:41:10.634129
818 04:41:10.636213 CA PerBit enable=1, Macro0, CA PI delay=33
819 04:41:10.636301
820 04:41:10.639601 [CBTSetCACLKResult] CA Dly = 33
821 04:41:10.639699 CS Dly: 6 (0~38)
822 04:41:10.642936
823 04:41:10.646284 ----->DramcWriteLeveling(PI) begin...
824 04:41:10.646412 ==
825 04:41:10.649917 Dram Type= 6, Freq= 0, CH_0, rank 0
826 04:41:10.653567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 04:41:10.653678 ==
828 04:41:10.657609 Write leveling (Byte 0): 30 => 30
829 04:41:10.657720 Write leveling (Byte 1): 29 => 29
830 04:41:10.661662 DramcWriteLeveling(PI) end<-----
831 04:41:10.661841
832 04:41:10.661927 ==
833 04:41:10.665255 Dram Type= 6, Freq= 0, CH_0, rank 0
834 04:41:10.668355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 04:41:10.668469 ==
836 04:41:10.671753 [Gating] SW mode calibration
837 04:41:10.678712 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 04:41:10.686128 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 04:41:10.689565 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 04:41:10.692654 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
841 04:41:10.699248 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
842 04:41:10.703103 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 04:41:10.705855 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 04:41:10.712684 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 04:41:10.716324 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 04:41:10.718993 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 04:41:10.726103 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 04:41:10.729096 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 04:41:10.733082 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 04:41:10.735821 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 04:41:10.742932 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 04:41:10.746140 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 04:41:10.749338 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 04:41:10.755804 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 04:41:10.759152 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 04:41:10.763348 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
857 04:41:10.769157 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
858 04:41:10.772934 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
859 04:41:10.775802 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 04:41:10.782325 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 04:41:10.786028 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 04:41:10.789268 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 04:41:10.795939 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 04:41:10.799085 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 04:41:10.802990 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
866 04:41:10.809234 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
867 04:41:10.813011 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 04:41:10.815856 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 04:41:10.822363 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 04:41:10.825920 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 04:41:10.829419 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 04:41:10.835912 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
873 04:41:10.839466 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
874 04:41:10.842898 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
875 04:41:10.849107 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 04:41:10.852325 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 04:41:10.855549 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 04:41:10.862213 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 04:41:10.866237 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 04:41:10.868584 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
881 04:41:10.875377 0 11 8 | B1->B0 | 2727 3d3d | 0 0 | (0 0) (0 0)
882 04:41:10.878349 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
883 04:41:10.882275 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 04:41:10.888680 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 04:41:10.892115 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 04:41:10.895506 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 04:41:10.898976 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 04:41:10.905617 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 04:41:10.908636 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
890 04:41:10.912056 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 04:41:10.918918 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 04:41:10.922038 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 04:41:10.925315 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 04:41:10.931768 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 04:41:10.935757 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 04:41:10.938617 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 04:41:10.945237 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 04:41:10.948763 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 04:41:10.951632 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 04:41:10.958426 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 04:41:10.962029 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 04:41:10.965137 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 04:41:10.971883 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 04:41:10.974903 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 04:41:10.978218 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
906 04:41:10.981516 Total UI for P1: 0, mck2ui 16
907 04:41:10.985168 best dqsien dly found for B0: ( 0, 14, 6)
908 04:41:10.991229 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
909 04:41:10.994660 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
910 04:41:10.997927 Total UI for P1: 0, mck2ui 16
911 04:41:11.001448 best dqsien dly found for B1: ( 0, 14, 10)
912 04:41:11.005095 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
913 04:41:11.008022 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
914 04:41:11.008157
915 04:41:11.011514 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
916 04:41:11.014705 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
917 04:41:11.017832 [Gating] SW calibration Done
918 04:41:11.017967 ==
919 04:41:11.021966 Dram Type= 6, Freq= 0, CH_0, rank 0
920 04:41:11.025500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 04:41:11.025642 ==
922 04:41:11.029497 RX Vref Scan: 0
923 04:41:11.029631
924 04:41:11.029731 RX Vref 0 -> 0, step: 1
925 04:41:11.029825
926 04:41:11.032698 RX Delay -130 -> 252, step: 16
927 04:41:11.038968 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
928 04:41:11.041935 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
929 04:41:11.045519 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
930 04:41:11.048571 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
931 04:41:11.051902 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
932 04:41:11.058428 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
933 04:41:11.061752 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
934 04:41:11.065324 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
935 04:41:11.069083 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
936 04:41:11.072320 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
937 04:41:11.078191 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
938 04:41:11.081943 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
939 04:41:11.085330 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
940 04:41:11.088313 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
941 04:41:11.091567 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
942 04:41:11.098049 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
943 04:41:11.098180 ==
944 04:41:11.101535 Dram Type= 6, Freq= 0, CH_0, rank 0
945 04:41:11.105107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
946 04:41:11.105211 ==
947 04:41:11.105282 DQS Delay:
948 04:41:11.108331 DQS0 = 0, DQS1 = 0
949 04:41:11.108422 DQM Delay:
950 04:41:11.111312 DQM0 = 88, DQM1 = 75
951 04:41:11.111439 DQ Delay:
952 04:41:11.115088 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
953 04:41:11.118181 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
954 04:41:11.121428 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
955 04:41:11.124763 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
956 04:41:11.124872
957 04:41:11.124966
958 04:41:11.125049 ==
959 04:41:11.128204 Dram Type= 6, Freq= 0, CH_0, rank 0
960 04:41:11.131359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 04:41:11.134657 ==
962 04:41:11.134763
963 04:41:11.134853
964 04:41:11.134937 TX Vref Scan disable
965 04:41:11.138236 == TX Byte 0 ==
966 04:41:11.141683 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
967 04:41:11.144581 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
968 04:41:11.147816 == TX Byte 1 ==
969 04:41:11.151651 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
970 04:41:11.154762 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
971 04:41:11.157681 ==
972 04:41:11.161338 Dram Type= 6, Freq= 0, CH_0, rank 0
973 04:41:11.164119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 04:41:11.164224 ==
975 04:41:11.177113 TX Vref=22, minBit 4, minWin=26, winSum=437
976 04:41:11.180191 TX Vref=24, minBit 1, minWin=27, winSum=444
977 04:41:11.183603 TX Vref=26, minBit 1, minWin=27, winSum=445
978 04:41:11.186956 TX Vref=28, minBit 1, minWin=27, winSum=449
979 04:41:11.190615 TX Vref=30, minBit 1, minWin=27, winSum=451
980 04:41:11.193370 TX Vref=32, minBit 2, minWin=27, winSum=450
981 04:41:11.200128 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 30
982 04:41:11.200253
983 04:41:11.203649 Final TX Range 1 Vref 30
984 04:41:11.203742
985 04:41:11.203810 ==
986 04:41:11.206715 Dram Type= 6, Freq= 0, CH_0, rank 0
987 04:41:11.209964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 04:41:11.210061 ==
989 04:41:11.210130
990 04:41:11.213408
991 04:41:11.213502 TX Vref Scan disable
992 04:41:11.216528 == TX Byte 0 ==
993 04:41:11.219755 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
994 04:41:11.226376 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
995 04:41:11.226507 == TX Byte 1 ==
996 04:41:11.230539 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
997 04:41:11.236550 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
998 04:41:11.236682
999 04:41:11.236757 [DATLAT]
1000 04:41:11.236819 Freq=800, CH0 RK0
1001 04:41:11.236879
1002 04:41:11.240409 DATLAT Default: 0xa
1003 04:41:11.240505 0, 0xFFFF, sum = 0
1004 04:41:11.243014 1, 0xFFFF, sum = 0
1005 04:41:11.243110 2, 0xFFFF, sum = 0
1006 04:41:11.246598 3, 0xFFFF, sum = 0
1007 04:41:11.249858 4, 0xFFFF, sum = 0
1008 04:41:11.249961 5, 0xFFFF, sum = 0
1009 04:41:11.253219 6, 0xFFFF, sum = 0
1010 04:41:11.253312 7, 0xFFFF, sum = 0
1011 04:41:11.256553 8, 0xFFFF, sum = 0
1012 04:41:11.256650 9, 0x0, sum = 1
1013 04:41:11.256718 10, 0x0, sum = 2
1014 04:41:11.259957 11, 0x0, sum = 3
1015 04:41:11.260047 12, 0x0, sum = 4
1016 04:41:11.263011 best_step = 10
1017 04:41:11.263117
1018 04:41:11.263185 ==
1019 04:41:11.266141 Dram Type= 6, Freq= 0, CH_0, rank 0
1020 04:41:11.270076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1021 04:41:11.270189 ==
1022 04:41:11.272908 RX Vref Scan: 1
1023 04:41:11.272998
1024 04:41:11.276137 Set Vref Range= 32 -> 127
1025 04:41:11.276236
1026 04:41:11.276302 RX Vref 32 -> 127, step: 1
1027 04:41:11.276362
1028 04:41:11.279528 RX Delay -111 -> 252, step: 8
1029 04:41:11.279615
1030 04:41:11.283253 Set Vref, RX VrefLevel [Byte0]: 32
1031 04:41:11.286153 [Byte1]: 32
1032 04:41:11.289531
1033 04:41:11.289638 Set Vref, RX VrefLevel [Byte0]: 33
1034 04:41:11.292973 [Byte1]: 33
1035 04:41:11.297339
1036 04:41:11.297450 Set Vref, RX VrefLevel [Byte0]: 34
1037 04:41:11.300359 [Byte1]: 34
1038 04:41:11.304834
1039 04:41:11.304943 Set Vref, RX VrefLevel [Byte0]: 35
1040 04:41:11.308104 [Byte1]: 35
1041 04:41:11.312582
1042 04:41:11.312687 Set Vref, RX VrefLevel [Byte0]: 36
1043 04:41:11.316233 [Byte1]: 36
1044 04:41:11.320464
1045 04:41:11.320574 Set Vref, RX VrefLevel [Byte0]: 37
1046 04:41:11.323708 [Byte1]: 37
1047 04:41:11.328742
1048 04:41:11.328859 Set Vref, RX VrefLevel [Byte0]: 38
1049 04:41:11.331811 [Byte1]: 38
1050 04:41:11.335945
1051 04:41:11.336057 Set Vref, RX VrefLevel [Byte0]: 39
1052 04:41:11.338766 [Byte1]: 39
1053 04:41:11.343650
1054 04:41:11.343783 Set Vref, RX VrefLevel [Byte0]: 40
1055 04:41:11.346519 [Byte1]: 40
1056 04:41:11.350491
1057 04:41:11.354097 Set Vref, RX VrefLevel [Byte0]: 41
1058 04:41:11.357256 [Byte1]: 41
1059 04:41:11.357356
1060 04:41:11.361073 Set Vref, RX VrefLevel [Byte0]: 42
1061 04:41:11.364209 [Byte1]: 42
1062 04:41:11.364305
1063 04:41:11.367520 Set Vref, RX VrefLevel [Byte0]: 43
1064 04:41:11.370497 [Byte1]: 43
1065 04:41:11.370589
1066 04:41:11.373675 Set Vref, RX VrefLevel [Byte0]: 44
1067 04:41:11.377216 [Byte1]: 44
1068 04:41:11.381196
1069 04:41:11.381295 Set Vref, RX VrefLevel [Byte0]: 45
1070 04:41:11.384750 [Byte1]: 45
1071 04:41:11.388633
1072 04:41:11.388760 Set Vref, RX VrefLevel [Byte0]: 46
1073 04:41:11.392554 [Byte1]: 46
1074 04:41:11.396515
1075 04:41:11.396615 Set Vref, RX VrefLevel [Byte0]: 47
1076 04:41:11.399908 [Byte1]: 47
1077 04:41:11.404453
1078 04:41:11.404554 Set Vref, RX VrefLevel [Byte0]: 48
1079 04:41:11.407502 [Byte1]: 48
1080 04:41:11.412290
1081 04:41:11.412392 Set Vref, RX VrefLevel [Byte0]: 49
1082 04:41:11.415320 [Byte1]: 49
1083 04:41:11.419262
1084 04:41:11.419403 Set Vref, RX VrefLevel [Byte0]: 50
1085 04:41:11.422684 [Byte1]: 50
1086 04:41:11.427092
1087 04:41:11.427187 Set Vref, RX VrefLevel [Byte0]: 51
1088 04:41:11.430645 [Byte1]: 51
1089 04:41:11.434724
1090 04:41:11.434828 Set Vref, RX VrefLevel [Byte0]: 52
1091 04:41:11.437796 [Byte1]: 52
1092 04:41:11.442472
1093 04:41:11.442589 Set Vref, RX VrefLevel [Byte0]: 53
1094 04:41:11.445507 [Byte1]: 53
1095 04:41:11.450036
1096 04:41:11.450166 Set Vref, RX VrefLevel [Byte0]: 54
1097 04:41:11.453864 [Byte1]: 54
1098 04:41:11.457721
1099 04:41:11.457819 Set Vref, RX VrefLevel [Byte0]: 55
1100 04:41:11.461066 [Byte1]: 55
1101 04:41:11.465408
1102 04:41:11.465510 Set Vref, RX VrefLevel [Byte0]: 56
1103 04:41:11.468600 [Byte1]: 56
1104 04:41:11.472915
1105 04:41:11.473017 Set Vref, RX VrefLevel [Byte0]: 57
1106 04:41:11.476074 [Byte1]: 57
1107 04:41:11.480420
1108 04:41:11.480520 Set Vref, RX VrefLevel [Byte0]: 58
1109 04:41:11.484133 [Byte1]: 58
1110 04:41:11.488665
1111 04:41:11.488784 Set Vref, RX VrefLevel [Byte0]: 59
1112 04:41:11.491264 [Byte1]: 59
1113 04:41:11.495788
1114 04:41:11.495888 Set Vref, RX VrefLevel [Byte0]: 60
1115 04:41:11.499534 [Byte1]: 60
1116 04:41:11.503328
1117 04:41:11.503477 Set Vref, RX VrefLevel [Byte0]: 61
1118 04:41:11.506884 [Byte1]: 61
1119 04:41:11.511318
1120 04:41:11.511464 Set Vref, RX VrefLevel [Byte0]: 62
1121 04:41:11.514627 [Byte1]: 62
1122 04:41:11.518771
1123 04:41:11.518889 Set Vref, RX VrefLevel [Byte0]: 63
1124 04:41:11.522315 [Byte1]: 63
1125 04:41:11.526617
1126 04:41:11.526735 Set Vref, RX VrefLevel [Byte0]: 64
1127 04:41:11.529934 [Byte1]: 64
1128 04:41:11.534479
1129 04:41:11.534586 Set Vref, RX VrefLevel [Byte0]: 65
1130 04:41:11.537571 [Byte1]: 65
1131 04:41:11.541439
1132 04:41:11.541556 Set Vref, RX VrefLevel [Byte0]: 66
1133 04:41:11.545262 [Byte1]: 66
1134 04:41:11.549387
1135 04:41:11.549507 Set Vref, RX VrefLevel [Byte0]: 67
1136 04:41:11.552859 [Byte1]: 67
1137 04:41:11.557121
1138 04:41:11.557216 Set Vref, RX VrefLevel [Byte0]: 68
1139 04:41:11.560506 [Byte1]: 68
1140 04:41:11.565178
1141 04:41:11.565282 Set Vref, RX VrefLevel [Byte0]: 69
1142 04:41:11.567855 [Byte1]: 69
1143 04:41:11.572551
1144 04:41:11.572654 Set Vref, RX VrefLevel [Byte0]: 70
1145 04:41:11.576709 [Byte1]: 70
1146 04:41:11.580603
1147 04:41:11.580720 Set Vref, RX VrefLevel [Byte0]: 71
1148 04:41:11.583320 [Byte1]: 71
1149 04:41:11.587739
1150 04:41:11.587831 Set Vref, RX VrefLevel [Byte0]: 72
1151 04:41:11.591053 [Byte1]: 72
1152 04:41:11.594994
1153 04:41:11.595113 Set Vref, RX VrefLevel [Byte0]: 73
1154 04:41:11.598647 [Byte1]: 73
1155 04:41:11.602615
1156 04:41:11.602741 Set Vref, RX VrefLevel [Byte0]: 74
1157 04:41:11.606398 [Byte1]: 74
1158 04:41:11.610508
1159 04:41:11.610606 Final RX Vref Byte 0 = 56 to rank0
1160 04:41:11.613837 Final RX Vref Byte 1 = 58 to rank0
1161 04:41:11.617226 Final RX Vref Byte 0 = 56 to rank1
1162 04:41:11.620873 Final RX Vref Byte 1 = 58 to rank1==
1163 04:41:11.624142 Dram Type= 6, Freq= 0, CH_0, rank 0
1164 04:41:11.630961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1165 04:41:11.631092 ==
1166 04:41:11.631162 DQS Delay:
1167 04:41:11.631221 DQS0 = 0, DQS1 = 0
1168 04:41:11.633677 DQM Delay:
1169 04:41:11.633752 DQM0 = 88, DQM1 = 76
1170 04:41:11.637095 DQ Delay:
1171 04:41:11.640845 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1172 04:41:11.640946 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1173 04:41:11.644277 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1174 04:41:11.650398 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1175 04:41:11.650515
1176 04:41:11.650585
1177 04:41:11.656904 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1178 04:41:11.660532 CH0 RK0: MR19=606, MR18=2E28
1179 04:41:11.667705 CH0_RK0: MR19=0x606, MR18=0x2E28, DQSOSC=398, MR23=63, INC=93, DEC=62
1180 04:41:11.667846
1181 04:41:11.671052 ----->DramcWriteLeveling(PI) begin...
1182 04:41:11.671148 ==
1183 04:41:11.674254 Dram Type= 6, Freq= 0, CH_0, rank 1
1184 04:41:11.676956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1185 04:41:11.677052 ==
1186 04:41:11.680667 Write leveling (Byte 0): 34 => 34
1187 04:41:11.683677 Write leveling (Byte 1): 24 => 24
1188 04:41:11.687109 DramcWriteLeveling(PI) end<-----
1189 04:41:11.687208
1190 04:41:11.687274 ==
1191 04:41:11.690171 Dram Type= 6, Freq= 0, CH_0, rank 1
1192 04:41:11.693546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1193 04:41:11.693643 ==
1194 04:41:11.697122 [Gating] SW mode calibration
1195 04:41:11.703385 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1196 04:41:11.710400 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1197 04:41:11.754381 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1198 04:41:11.754951 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1199 04:41:11.755056 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1200 04:41:11.755309 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 04:41:11.755885 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 04:41:11.756292 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 04:41:11.757011 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 04:41:11.757093 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 04:41:11.757362 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 04:41:11.757856 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 04:41:11.798229 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 04:41:11.798592 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 04:41:11.798688 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 04:41:11.798820 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 04:41:11.798964 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 04:41:11.799062 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 04:41:11.799740 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 04:41:11.799869 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1215 04:41:11.800160 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1216 04:41:11.800229 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 04:41:11.828517 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 04:41:11.828899 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 04:41:11.829008 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 04:41:11.829286 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 04:41:11.830114 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 04:41:11.830395 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1223 04:41:11.833581 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1224 04:41:11.833699 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1225 04:41:11.836526 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1226 04:41:11.842710 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1227 04:41:11.846230 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1228 04:41:11.849635 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1229 04:41:11.856011 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1230 04:41:11.859613 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
1231 04:41:11.862469 0 10 8 | B1->B0 | 3232 2424 | 1 0 | (1 0) (0 0)
1232 04:41:11.869019 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1233 04:41:11.872921 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 04:41:11.876411 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 04:41:11.882610 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 04:41:11.885818 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 04:41:11.889195 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 04:41:11.892573 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1239 04:41:11.899722 0 11 8 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
1240 04:41:11.903289 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 04:41:11.907289 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1242 04:41:11.910827 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1243 04:41:11.917477 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1244 04:41:11.920970 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 04:41:11.924897 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1246 04:41:11.928308 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1247 04:41:11.935244 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1248 04:41:11.938931 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 04:41:11.941873 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 04:41:11.948172 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 04:41:11.951501 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 04:41:11.955221 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 04:41:11.961826 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 04:41:11.965199 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 04:41:11.968343 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 04:41:11.971546 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 04:41:11.978388 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 04:41:11.981259 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 04:41:11.984649 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 04:41:11.991676 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 04:41:11.994849 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1262 04:41:11.998335 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1263 04:41:12.004813 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 04:41:12.008240 Total UI for P1: 0, mck2ui 16
1265 04:41:12.011586 best dqsien dly found for B0: ( 0, 14, 2)
1266 04:41:12.011689 Total UI for P1: 0, mck2ui 16
1267 04:41:12.017768 best dqsien dly found for B1: ( 0, 14, 4)
1268 04:41:12.021238 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1269 04:41:12.025040 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1270 04:41:12.025146
1271 04:41:12.027875 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1272 04:41:12.031194 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1273 04:41:12.034433 [Gating] SW calibration Done
1274 04:41:12.034535 ==
1275 04:41:12.037950 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 04:41:12.041348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 04:41:12.041453 ==
1278 04:41:12.044943 RX Vref Scan: 0
1279 04:41:12.045051
1280 04:41:12.045117 RX Vref 0 -> 0, step: 1
1281 04:41:12.045176
1282 04:41:12.047861 RX Delay -130 -> 252, step: 16
1283 04:41:12.051579 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1284 04:41:12.057990 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1285 04:41:12.061137 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1286 04:41:12.064558 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1287 04:41:12.068240 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1288 04:41:12.071186 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1289 04:41:12.077831 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1290 04:41:12.081317 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1291 04:41:12.084356 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1292 04:41:12.087935 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1293 04:41:12.090953 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1294 04:41:12.097525 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1295 04:41:12.101045 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1296 04:41:12.105062 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1297 04:41:12.108650 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1298 04:41:12.114515 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1299 04:41:12.114640 ==
1300 04:41:12.118662 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 04:41:12.120869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 04:41:12.120966 ==
1303 04:41:12.121031 DQS Delay:
1304 04:41:12.124113 DQS0 = 0, DQS1 = 0
1305 04:41:12.124203 DQM Delay:
1306 04:41:12.127856 DQM0 = 85, DQM1 = 76
1307 04:41:12.127949 DQ Delay:
1308 04:41:12.131014 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1309 04:41:12.134570 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1310 04:41:12.137924 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
1311 04:41:12.141326 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1312 04:41:12.141454
1313 04:41:12.141549
1314 04:41:12.141638 ==
1315 04:41:12.144161 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 04:41:12.147637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 04:41:12.147754 ==
1318 04:41:12.147848
1319 04:41:12.147936
1320 04:41:12.150918 TX Vref Scan disable
1321 04:41:12.154052 == TX Byte 0 ==
1322 04:41:12.157847 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1323 04:41:12.160992 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1324 04:41:12.164284 == TX Byte 1 ==
1325 04:41:12.167308 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1326 04:41:12.170865 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1327 04:41:12.170989 ==
1328 04:41:12.174143 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 04:41:12.181146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 04:41:12.181275 ==
1331 04:41:12.194546 TX Vref=22, minBit 1, minWin=27, winSum=445
1332 04:41:12.197171 TX Vref=24, minBit 1, minWin=27, winSum=448
1333 04:41:12.200309 TX Vref=26, minBit 0, minWin=28, winSum=451
1334 04:41:12.204293 TX Vref=28, minBit 1, minWin=27, winSum=450
1335 04:41:12.206782 TX Vref=30, minBit 4, minWin=27, winSum=451
1336 04:41:12.210282 TX Vref=32, minBit 1, minWin=27, winSum=450
1337 04:41:12.216893 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 26
1338 04:41:12.217038
1339 04:41:12.220933 Final TX Range 1 Vref 26
1340 04:41:12.221031
1341 04:41:12.221119 ==
1342 04:41:12.223789 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 04:41:12.226843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 04:41:12.226935 ==
1345 04:41:12.229840
1346 04:41:12.229964
1347 04:41:12.230058 TX Vref Scan disable
1348 04:41:12.233432 == TX Byte 0 ==
1349 04:41:12.237123 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1350 04:41:12.243733 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1351 04:41:12.243867 == TX Byte 1 ==
1352 04:41:12.247153 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1353 04:41:12.250331 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1354 04:41:12.253421
1355 04:41:12.253519 [DATLAT]
1356 04:41:12.253583 Freq=800, CH0 RK1
1357 04:41:12.253643
1358 04:41:12.257034 DATLAT Default: 0xa
1359 04:41:12.257122 0, 0xFFFF, sum = 0
1360 04:41:12.259960 1, 0xFFFF, sum = 0
1361 04:41:12.260078 2, 0xFFFF, sum = 0
1362 04:41:12.263646 3, 0xFFFF, sum = 0
1363 04:41:12.267044 4, 0xFFFF, sum = 0
1364 04:41:12.267140 5, 0xFFFF, sum = 0
1365 04:41:12.270797 6, 0xFFFF, sum = 0
1366 04:41:12.270929 7, 0xFFFF, sum = 0
1367 04:41:12.273342 8, 0xFFFF, sum = 0
1368 04:41:12.273430 9, 0x0, sum = 1
1369 04:41:12.273495 10, 0x0, sum = 2
1370 04:41:12.277104 11, 0x0, sum = 3
1371 04:41:12.277195 12, 0x0, sum = 4
1372 04:41:12.280201 best_step = 10
1373 04:41:12.280290
1374 04:41:12.280355 ==
1375 04:41:12.283699 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 04:41:12.286665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 04:41:12.286755 ==
1378 04:41:12.290243 RX Vref Scan: 0
1379 04:41:12.290337
1380 04:41:12.290401 RX Vref 0 -> 0, step: 1
1381 04:41:12.290460
1382 04:41:12.293751 RX Delay -111 -> 252, step: 8
1383 04:41:12.300610 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1384 04:41:12.303797 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1385 04:41:12.307567 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1386 04:41:12.310282 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1387 04:41:12.313951 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1388 04:41:12.320432 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1389 04:41:12.324735 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1390 04:41:12.327347 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1391 04:41:12.330297 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1392 04:41:12.333509 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1393 04:41:12.340224 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1394 04:41:12.343496 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1395 04:41:12.346602 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1396 04:41:12.350051 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1397 04:41:12.356512 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1398 04:41:12.359818 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1399 04:41:12.359947 ==
1400 04:41:12.363472 Dram Type= 6, Freq= 0, CH_0, rank 1
1401 04:41:12.366382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 04:41:12.366498 ==
1403 04:41:12.369862 DQS Delay:
1404 04:41:12.369983 DQS0 = 0, DQS1 = 0
1405 04:41:12.370076 DQM Delay:
1406 04:41:12.373212 DQM0 = 86, DQM1 = 77
1407 04:41:12.373323 DQ Delay:
1408 04:41:12.376836 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1409 04:41:12.380002 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1410 04:41:12.383487 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1411 04:41:12.386864 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1412 04:41:12.386992
1413 04:41:12.387085
1414 04:41:12.396442 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1415 04:41:12.396611 CH0 RK1: MR19=606, MR18=2F2A
1416 04:41:12.402862 CH0_RK1: MR19=0x606, MR18=0x2F2A, DQSOSC=397, MR23=63, INC=93, DEC=62
1417 04:41:12.406284 [RxdqsGatingPostProcess] freq 800
1418 04:41:12.412992 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1419 04:41:12.416366 Pre-setting of DQS Precalculation
1420 04:41:12.420028 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1421 04:41:12.420160 ==
1422 04:41:12.423265 Dram Type= 6, Freq= 0, CH_1, rank 0
1423 04:41:12.429734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 04:41:12.429893 ==
1425 04:41:12.432761 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1426 04:41:12.439499 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1427 04:41:12.449116 [CA 0] Center 37 (7~67) winsize 61
1428 04:41:12.452085 [CA 1] Center 37 (6~68) winsize 63
1429 04:41:12.455490 [CA 2] Center 35 (5~66) winsize 62
1430 04:41:12.458851 [CA 3] Center 35 (5~65) winsize 61
1431 04:41:12.462190 [CA 4] Center 35 (4~66) winsize 63
1432 04:41:12.465673 [CA 5] Center 34 (4~65) winsize 62
1433 04:41:12.465825
1434 04:41:12.468563 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1435 04:41:12.468685
1436 04:41:12.471948 [CATrainingPosCal] consider 1 rank data
1437 04:41:12.475494 u2DelayCellTimex100 = 270/100 ps
1438 04:41:12.479028 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1439 04:41:12.481995 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1440 04:41:12.488573 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1441 04:41:12.492217 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1442 04:41:12.495501 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1443 04:41:12.498488 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1444 04:41:12.498608
1445 04:41:12.502461 CA PerBit enable=1, Macro0, CA PI delay=34
1446 04:41:12.502584
1447 04:41:12.505042 [CBTSetCACLKResult] CA Dly = 34
1448 04:41:12.505150 CS Dly: 4 (0~35)
1449 04:41:12.509146 ==
1450 04:41:12.511719 Dram Type= 6, Freq= 0, CH_1, rank 1
1451 04:41:12.514778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 04:41:12.514896 ==
1453 04:41:12.521613 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1454 04:41:12.524839 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1455 04:41:12.535046 [CA 0] Center 36 (6~67) winsize 62
1456 04:41:12.538402 [CA 1] Center 36 (6~67) winsize 62
1457 04:41:12.541451 [CA 2] Center 34 (4~65) winsize 62
1458 04:41:12.545469 [CA 3] Center 34 (4~65) winsize 62
1459 04:41:12.548793 [CA 4] Center 34 (4~65) winsize 62
1460 04:41:12.551858 [CA 5] Center 34 (4~65) winsize 62
1461 04:41:12.551983
1462 04:41:12.555164 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1463 04:41:12.555281
1464 04:41:12.558645 [CATrainingPosCal] consider 2 rank data
1465 04:41:12.561939 u2DelayCellTimex100 = 270/100 ps
1466 04:41:12.565385 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1467 04:41:12.569375 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1468 04:41:12.573714 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1469 04:41:12.576710 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1470 04:41:12.580183 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1471 04:41:12.584075 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1472 04:41:12.584231
1473 04:41:12.588044 CA PerBit enable=1, Macro0, CA PI delay=34
1474 04:41:12.588176
1475 04:41:12.591628 [CBTSetCACLKResult] CA Dly = 34
1476 04:41:12.591754 CS Dly: 5 (0~37)
1477 04:41:12.591850
1478 04:41:12.594888 ----->DramcWriteLeveling(PI) begin...
1479 04:41:12.598658 ==
1480 04:41:12.598793 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 04:41:12.605282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1482 04:41:12.605450 ==
1483 04:41:12.608691 Write leveling (Byte 0): 26 => 26
1484 04:41:12.611572 Write leveling (Byte 1): 26 => 26
1485 04:41:12.611696 DramcWriteLeveling(PI) end<-----
1486 04:41:12.615857
1487 04:41:12.615988 ==
1488 04:41:12.618393 Dram Type= 6, Freq= 0, CH_1, rank 0
1489 04:41:12.621836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1490 04:41:12.621973 ==
1491 04:41:12.624963 [Gating] SW mode calibration
1492 04:41:12.631891 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1493 04:41:12.635200 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1494 04:41:12.642202 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1495 04:41:12.645260 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1496 04:41:12.648465 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 04:41:12.655268 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 04:41:12.658341 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 04:41:12.661362 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 04:41:12.668074 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 04:41:12.671495 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 04:41:12.674749 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 04:41:12.681493 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 04:41:12.684745 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 04:41:12.688611 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 04:41:12.695259 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 04:41:12.697919 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 04:41:12.701315 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 04:41:12.707785 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 04:41:12.710878 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 04:41:12.714752 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1512 04:41:12.720754 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1513 04:41:12.724402 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 04:41:12.727865 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 04:41:12.733983 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 04:41:12.737731 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 04:41:12.740757 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 04:41:12.747186 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 04:41:12.750641 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1520 04:41:12.754146 0 9 8 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (0 0)
1521 04:41:12.760850 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1522 04:41:12.763856 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1523 04:41:12.767471 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1524 04:41:12.774228 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1525 04:41:12.777418 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1526 04:41:12.780768 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1527 04:41:12.787515 0 10 4 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
1528 04:41:12.790996 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
1529 04:41:12.794027 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 04:41:12.797401 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 04:41:12.804498 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 04:41:12.807074 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 04:41:12.810958 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 04:41:12.817197 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 04:41:12.820597 0 11 4 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (1 1)
1536 04:41:12.824306 0 11 8 | B1->B0 | 3939 4242 | 1 0 | (0 0) (0 0)
1537 04:41:12.830562 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 04:41:12.833927 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 04:41:12.837370 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1540 04:41:12.843629 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1541 04:41:12.847316 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1542 04:41:12.850912 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 04:41:12.857348 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1544 04:41:12.860689 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 04:41:12.863754 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 04:41:12.870602 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 04:41:12.873716 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 04:41:12.876965 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 04:41:12.884052 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 04:41:12.887212 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 04:41:12.890417 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 04:41:12.896864 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 04:41:12.900515 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 04:41:12.903304 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 04:41:12.910588 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 04:41:12.913583 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 04:41:12.916773 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 04:41:12.923668 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1559 04:41:12.927396 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1560 04:41:12.930080 Total UI for P1: 0, mck2ui 16
1561 04:41:12.933554 best dqsien dly found for B1: ( 0, 14, 0)
1562 04:41:12.936572 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1563 04:41:12.940408 Total UI for P1: 0, mck2ui 16
1564 04:41:12.942990 best dqsien dly found for B0: ( 0, 14, 4)
1565 04:41:12.946818 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1566 04:41:12.950286 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1567 04:41:12.950390
1568 04:41:12.953180 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1569 04:41:12.959865 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1570 04:41:12.960005 [Gating] SW calibration Done
1571 04:41:12.960106 ==
1572 04:41:12.963279 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 04:41:12.970073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 04:41:12.970209 ==
1575 04:41:12.970313 RX Vref Scan: 0
1576 04:41:12.970432
1577 04:41:12.973139 RX Vref 0 -> 0, step: 1
1578 04:41:12.973247
1579 04:41:12.976221 RX Delay -130 -> 252, step: 16
1580 04:41:12.980211 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1581 04:41:12.983025 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1582 04:41:12.986476 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1583 04:41:12.993085 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1584 04:41:12.996323 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1585 04:41:12.999547 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1586 04:41:13.002467 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1587 04:41:13.006027 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1588 04:41:13.012646 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1589 04:41:13.015915 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1590 04:41:13.019580 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1591 04:41:13.022756 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1592 04:41:13.026354 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1593 04:41:13.032465 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1594 04:41:13.035715 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1595 04:41:13.039132 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1596 04:41:13.039264 ==
1597 04:41:13.042281 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 04:41:13.045831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 04:41:13.049219 ==
1600 04:41:13.049350 DQS Delay:
1601 04:41:13.049446 DQS0 = 0, DQS1 = 0
1602 04:41:13.052543 DQM Delay:
1603 04:41:13.052663 DQM0 = 87, DQM1 = 84
1604 04:41:13.055595 DQ Delay:
1605 04:41:13.055730 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1606 04:41:13.058870 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1607 04:41:13.062798 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1608 04:41:13.065904 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1609 04:41:13.069176
1610 04:41:13.069312
1611 04:41:13.069410 ==
1612 04:41:13.072603 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 04:41:13.075591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 04:41:13.075722 ==
1615 04:41:13.075843
1616 04:41:13.075946
1617 04:41:13.079240 TX Vref Scan disable
1618 04:41:13.079380 == TX Byte 0 ==
1619 04:41:13.086015 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1620 04:41:13.089329 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1621 04:41:13.089466 == TX Byte 1 ==
1622 04:41:13.096310 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1623 04:41:13.099348 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1624 04:41:13.099513 ==
1625 04:41:13.102844 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 04:41:13.105870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 04:41:13.106000 ==
1628 04:41:13.119030 TX Vref=22, minBit 4, minWin=26, winSum=438
1629 04:41:13.122709 TX Vref=24, minBit 1, minWin=27, winSum=450
1630 04:41:13.125564 TX Vref=26, minBit 1, minWin=27, winSum=449
1631 04:41:13.128724 TX Vref=28, minBit 2, minWin=27, winSum=453
1632 04:41:13.132395 TX Vref=30, minBit 2, minWin=27, winSum=456
1633 04:41:13.138822 TX Vref=32, minBit 1, minWin=27, winSum=450
1634 04:41:13.142644 [TxChooseVref] Worse bit 2, Min win 27, Win sum 456, Final Vref 30
1635 04:41:13.142790
1636 04:41:13.145994 Final TX Range 1 Vref 30
1637 04:41:13.146123
1638 04:41:13.146221 ==
1639 04:41:13.149033 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 04:41:13.152268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 04:41:13.152389 ==
1642 04:41:13.152486
1643 04:41:13.152577
1644 04:41:13.155828 TX Vref Scan disable
1645 04:41:13.159122 == TX Byte 0 ==
1646 04:41:13.162409 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1647 04:41:13.165649 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1648 04:41:13.169270 == TX Byte 1 ==
1649 04:41:13.172329 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1650 04:41:13.175628 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1651 04:41:13.178967
1652 04:41:13.179073 [DATLAT]
1653 04:41:13.179163 Freq=800, CH1 RK0
1654 04:41:13.179264
1655 04:41:13.182174 DATLAT Default: 0xa
1656 04:41:13.182261 0, 0xFFFF, sum = 0
1657 04:41:13.185985 1, 0xFFFF, sum = 0
1658 04:41:13.186079 2, 0xFFFF, sum = 0
1659 04:41:13.188659 3, 0xFFFF, sum = 0
1660 04:41:13.188751 4, 0xFFFF, sum = 0
1661 04:41:13.192498 5, 0xFFFF, sum = 0
1662 04:41:13.195926 6, 0xFFFF, sum = 0
1663 04:41:13.196032 7, 0xFFFF, sum = 0
1664 04:41:13.198883 8, 0xFFFF, sum = 0
1665 04:41:13.198974 9, 0x0, sum = 1
1666 04:41:13.199043 10, 0x0, sum = 2
1667 04:41:13.202904 11, 0x0, sum = 3
1668 04:41:13.202999 12, 0x0, sum = 4
1669 04:41:13.205553 best_step = 10
1670 04:41:13.205643
1671 04:41:13.205710 ==
1672 04:41:13.209105 Dram Type= 6, Freq= 0, CH_1, rank 0
1673 04:41:13.212747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1674 04:41:13.212851 ==
1675 04:41:13.215521 RX Vref Scan: 1
1676 04:41:13.215621
1677 04:41:13.215689 Set Vref Range= 32 -> 127
1678 04:41:13.219264
1679 04:41:13.219391 RX Vref 32 -> 127, step: 1
1680 04:41:13.219463
1681 04:41:13.221980 RX Delay -95 -> 252, step: 8
1682 04:41:13.222069
1683 04:41:13.225547 Set Vref, RX VrefLevel [Byte0]: 32
1684 04:41:13.228994 [Byte1]: 32
1685 04:41:13.229092
1686 04:41:13.232618 Set Vref, RX VrefLevel [Byte0]: 33
1687 04:41:13.235164 [Byte1]: 33
1688 04:41:13.239161
1689 04:41:13.239285 Set Vref, RX VrefLevel [Byte0]: 34
1690 04:41:13.242773 [Byte1]: 34
1691 04:41:13.246653
1692 04:41:13.246748 Set Vref, RX VrefLevel [Byte0]: 35
1693 04:41:13.250203 [Byte1]: 35
1694 04:41:13.254877
1695 04:41:13.254981 Set Vref, RX VrefLevel [Byte0]: 36
1696 04:41:13.257792 [Byte1]: 36
1697 04:41:13.262434
1698 04:41:13.262536 Set Vref, RX VrefLevel [Byte0]: 37
1699 04:41:13.265318 [Byte1]: 37
1700 04:41:13.270030
1701 04:41:13.270177 Set Vref, RX VrefLevel [Byte0]: 38
1702 04:41:13.272831 [Byte1]: 38
1703 04:41:13.277484
1704 04:41:13.277600 Set Vref, RX VrefLevel [Byte0]: 39
1705 04:41:13.280538 [Byte1]: 39
1706 04:41:13.284973
1707 04:41:13.285079 Set Vref, RX VrefLevel [Byte0]: 40
1708 04:41:13.288502 [Byte1]: 40
1709 04:41:13.292616
1710 04:41:13.292720 Set Vref, RX VrefLevel [Byte0]: 41
1711 04:41:13.296163 [Byte1]: 41
1712 04:41:13.299901
1713 04:41:13.300045 Set Vref, RX VrefLevel [Byte0]: 42
1714 04:41:13.303857 [Byte1]: 42
1715 04:41:13.307444
1716 04:41:13.307542 Set Vref, RX VrefLevel [Byte0]: 43
1717 04:41:13.310831 [Byte1]: 43
1718 04:41:13.314951
1719 04:41:13.315053 Set Vref, RX VrefLevel [Byte0]: 44
1720 04:41:13.318965 [Byte1]: 44
1721 04:41:13.322900
1722 04:41:13.323009 Set Vref, RX VrefLevel [Byte0]: 45
1723 04:41:13.326599 [Byte1]: 45
1724 04:41:13.330502
1725 04:41:13.330612 Set Vref, RX VrefLevel [Byte0]: 46
1726 04:41:13.333598 [Byte1]: 46
1727 04:41:13.338081
1728 04:41:13.338174 Set Vref, RX VrefLevel [Byte0]: 47
1729 04:41:13.341759 [Byte1]: 47
1730 04:41:13.345736
1731 04:41:13.345835 Set Vref, RX VrefLevel [Byte0]: 48
1732 04:41:13.349027 [Byte1]: 48
1733 04:41:13.353142
1734 04:41:13.353254 Set Vref, RX VrefLevel [Byte0]: 49
1735 04:41:13.357672 [Byte1]: 49
1736 04:41:13.360740
1737 04:41:13.360834 Set Vref, RX VrefLevel [Byte0]: 50
1738 04:41:13.364178 [Byte1]: 50
1739 04:41:13.368450
1740 04:41:13.368542 Set Vref, RX VrefLevel [Byte0]: 51
1741 04:41:13.372031 [Byte1]: 51
1742 04:41:13.375826
1743 04:41:13.375945 Set Vref, RX VrefLevel [Byte0]: 52
1744 04:41:13.379593 [Byte1]: 52
1745 04:41:13.383857
1746 04:41:13.383962 Set Vref, RX VrefLevel [Byte0]: 53
1747 04:41:13.386740 [Byte1]: 53
1748 04:41:13.391072
1749 04:41:13.391196 Set Vref, RX VrefLevel [Byte0]: 54
1750 04:41:13.394690 [Byte1]: 54
1751 04:41:13.398748
1752 04:41:13.398851 Set Vref, RX VrefLevel [Byte0]: 55
1753 04:41:13.401825 [Byte1]: 55
1754 04:41:13.406645
1755 04:41:13.406751 Set Vref, RX VrefLevel [Byte0]: 56
1756 04:41:13.409775 [Byte1]: 56
1757 04:41:13.414035
1758 04:41:13.414139 Set Vref, RX VrefLevel [Byte0]: 57
1759 04:41:13.417958 [Byte1]: 57
1760 04:41:13.421388
1761 04:41:13.421504 Set Vref, RX VrefLevel [Byte0]: 58
1762 04:41:13.424715 [Byte1]: 58
1763 04:41:13.429643
1764 04:41:13.429750 Set Vref, RX VrefLevel [Byte0]: 59
1765 04:41:13.433039 [Byte1]: 59
1766 04:41:13.436959
1767 04:41:13.437092 Set Vref, RX VrefLevel [Byte0]: 60
1768 04:41:13.440417 [Byte1]: 60
1769 04:41:13.444461
1770 04:41:13.444578 Set Vref, RX VrefLevel [Byte0]: 61
1771 04:41:13.447503 [Byte1]: 61
1772 04:41:13.451883
1773 04:41:13.451994 Set Vref, RX VrefLevel [Byte0]: 62
1774 04:41:13.455301 [Byte1]: 62
1775 04:41:13.459749
1776 04:41:13.459857 Set Vref, RX VrefLevel [Byte0]: 63
1777 04:41:13.462779 [Byte1]: 63
1778 04:41:13.467302
1779 04:41:13.467452 Set Vref, RX VrefLevel [Byte0]: 64
1780 04:41:13.470429 [Byte1]: 64
1781 04:41:13.474770
1782 04:41:13.478069 Set Vref, RX VrefLevel [Byte0]: 65
1783 04:41:13.478189 [Byte1]: 65
1784 04:41:13.482218
1785 04:41:13.482301 Set Vref, RX VrefLevel [Byte0]: 66
1786 04:41:13.485582 [Byte1]: 66
1787 04:41:13.489958
1788 04:41:13.490073 Set Vref, RX VrefLevel [Byte0]: 67
1789 04:41:13.493321 [Byte1]: 67
1790 04:41:13.497531
1791 04:41:13.497647 Set Vref, RX VrefLevel [Byte0]: 68
1792 04:41:13.500935 [Byte1]: 68
1793 04:41:13.505198
1794 04:41:13.505287 Set Vref, RX VrefLevel [Byte0]: 69
1795 04:41:13.508429 [Byte1]: 69
1796 04:41:13.512576
1797 04:41:13.512689 Set Vref, RX VrefLevel [Byte0]: 70
1798 04:41:13.516303 [Byte1]: 70
1799 04:41:13.520226
1800 04:41:13.520308 Set Vref, RX VrefLevel [Byte0]: 71
1801 04:41:13.523594 [Byte1]: 71
1802 04:41:13.528370
1803 04:41:13.528487 Set Vref, RX VrefLevel [Byte0]: 72
1804 04:41:13.531585 [Byte1]: 72
1805 04:41:13.535288
1806 04:41:13.535448 Set Vref, RX VrefLevel [Byte0]: 73
1807 04:41:13.538886 [Byte1]: 73
1808 04:41:13.543311
1809 04:41:13.543490 Set Vref, RX VrefLevel [Byte0]: 74
1810 04:41:13.546428 [Byte1]: 74
1811 04:41:13.550484
1812 04:41:13.550581 Final RX Vref Byte 0 = 59 to rank0
1813 04:41:13.554452 Final RX Vref Byte 1 = 58 to rank0
1814 04:41:13.557155 Final RX Vref Byte 0 = 59 to rank1
1815 04:41:13.560904 Final RX Vref Byte 1 = 58 to rank1==
1816 04:41:13.563853 Dram Type= 6, Freq= 0, CH_1, rank 0
1817 04:41:13.570792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 04:41:13.570944 ==
1819 04:41:13.571040 DQS Delay:
1820 04:41:13.571128 DQS0 = 0, DQS1 = 0
1821 04:41:13.573742 DQM Delay:
1822 04:41:13.573855 DQM0 = 87, DQM1 = 82
1823 04:41:13.577336 DQ Delay:
1824 04:41:13.580602 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1825 04:41:13.584064 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
1826 04:41:13.586960 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1827 04:41:13.590630 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
1828 04:41:13.590720
1829 04:41:13.590785
1830 04:41:13.597019 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f32, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1831 04:41:13.600564 CH1 RK0: MR19=606, MR18=1F32
1832 04:41:13.607002 CH1_RK0: MR19=0x606, MR18=0x1F32, DQSOSC=397, MR23=63, INC=93, DEC=62
1833 04:41:13.607147
1834 04:41:13.610459 ----->DramcWriteLeveling(PI) begin...
1835 04:41:13.610586 ==
1836 04:41:13.613930 Dram Type= 6, Freq= 0, CH_1, rank 1
1837 04:41:13.617803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1838 04:41:13.617922 ==
1839 04:41:13.620028 Write leveling (Byte 0): 27 => 27
1840 04:41:13.623908 Write leveling (Byte 1): 27 => 27
1841 04:41:13.626917 DramcWriteLeveling(PI) end<-----
1842 04:41:13.627028
1843 04:41:13.627120 ==
1844 04:41:13.630027 Dram Type= 6, Freq= 0, CH_1, rank 1
1845 04:41:13.633290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1846 04:41:13.633405 ==
1847 04:41:13.637239 [Gating] SW mode calibration
1848 04:41:13.643550 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1849 04:41:13.650111 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1850 04:41:13.653628 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1851 04:41:13.660259 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1852 04:41:13.663783 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 04:41:13.667252 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 04:41:13.670074 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 04:41:13.677473 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 04:41:13.679786 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 04:41:13.683835 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 04:41:13.689814 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 04:41:13.693143 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 04:41:13.696571 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 04:41:13.703353 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 04:41:13.706410 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 04:41:13.709980 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 04:41:13.716483 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 04:41:13.719885 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 04:41:13.723223 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1867 04:41:13.729798 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1868 04:41:13.733130 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 04:41:13.736528 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 04:41:13.743049 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 04:41:13.746815 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 04:41:13.749644 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 04:41:13.756446 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 04:41:13.759971 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 04:41:13.763572 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 04:41:13.769346 0 9 8 | B1->B0 | 2b2b 3434 | 0 1 | (1 1) (1 1)
1877 04:41:13.773378 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 04:41:13.776177 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1879 04:41:13.783385 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1880 04:41:13.786513 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 04:41:13.789571 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1882 04:41:13.796078 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1883 04:41:13.799639 0 10 4 | B1->B0 | 3333 2c2c | 1 1 | (0 0) (1 0)
1884 04:41:13.803138 0 10 8 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
1885 04:41:13.809424 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 04:41:13.812604 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 04:41:13.815909 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 04:41:13.822328 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 04:41:13.826010 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 04:41:13.829401 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1891 04:41:13.835934 0 11 4 | B1->B0 | 2929 3535 | 0 0 | (0 0) (0 0)
1892 04:41:13.839251 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
1893 04:41:13.842665 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 04:41:13.845939 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 04:41:13.853369 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 04:41:13.856150 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 04:41:13.859285 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 04:41:13.865639 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 04:41:13.869592 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1900 04:41:13.872635 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 04:41:13.879355 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 04:41:13.882644 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 04:41:13.886150 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 04:41:13.892944 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 04:41:13.896066 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 04:41:13.899307 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 04:41:13.905824 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 04:41:13.909289 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 04:41:13.912701 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 04:41:13.919019 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 04:41:13.922290 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 04:41:13.926035 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 04:41:13.932234 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 04:41:13.935702 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 04:41:13.939229 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1916 04:41:13.945653 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 04:41:13.945784 Total UI for P1: 0, mck2ui 16
1918 04:41:13.952408 best dqsien dly found for B0: ( 0, 14, 4)
1919 04:41:13.952524 Total UI for P1: 0, mck2ui 16
1920 04:41:13.955827 best dqsien dly found for B1: ( 0, 14, 6)
1921 04:41:13.962048 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1922 04:41:13.965717 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1923 04:41:13.965865
1924 04:41:13.968825 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1925 04:41:13.972382 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1926 04:41:13.975226 [Gating] SW calibration Done
1927 04:41:13.975339 ==
1928 04:41:13.978920 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 04:41:13.982407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 04:41:13.982498 ==
1931 04:41:13.982564 RX Vref Scan: 0
1932 04:41:13.986036
1933 04:41:13.986139 RX Vref 0 -> 0, step: 1
1934 04:41:13.986229
1935 04:41:13.989068 RX Delay -130 -> 252, step: 16
1936 04:41:13.992084 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1937 04:41:13.995469 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1938 04:41:14.002317 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1939 04:41:14.005358 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1940 04:41:14.009381 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1941 04:41:14.011859 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1942 04:41:14.015155 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1943 04:41:14.022050 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1944 04:41:14.025291 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1945 04:41:14.028492 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1946 04:41:14.032207 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1947 04:41:14.035266 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1948 04:41:14.041641 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1949 04:41:14.044931 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1950 04:41:14.048548 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1951 04:41:14.051789 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1952 04:41:14.054930 ==
1953 04:41:14.055045 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 04:41:14.061243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 04:41:14.061359 ==
1956 04:41:14.061428 DQS Delay:
1957 04:41:14.064732 DQS0 = 0, DQS1 = 0
1958 04:41:14.064814 DQM Delay:
1959 04:41:14.067886 DQM0 = 84, DQM1 = 83
1960 04:41:14.067971 DQ Delay:
1961 04:41:14.071456 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1962 04:41:14.074710 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1963 04:41:14.077991 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1964 04:41:14.081511 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1965 04:41:14.081627
1966 04:41:14.081721
1967 04:41:14.081809 ==
1968 04:41:14.085170 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 04:41:14.087925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 04:41:14.088026 ==
1971 04:41:14.088118
1972 04:41:14.088197
1973 04:41:14.091160 TX Vref Scan disable
1974 04:41:14.095144 == TX Byte 0 ==
1975 04:41:14.098243 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1976 04:41:14.101054 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1977 04:41:14.104786 == TX Byte 1 ==
1978 04:41:14.107845 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1979 04:41:14.110936 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1980 04:41:14.111049 ==
1981 04:41:14.114761 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 04:41:14.117975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 04:41:14.121164 ==
1984 04:41:14.132948 TX Vref=22, minBit 1, minWin=26, winSum=439
1985 04:41:14.135586 TX Vref=24, minBit 3, minWin=27, winSum=449
1986 04:41:14.139063 TX Vref=26, minBit 1, minWin=27, winSum=446
1987 04:41:14.142477 TX Vref=28, minBit 5, minWin=27, winSum=452
1988 04:41:14.145783 TX Vref=30, minBit 5, minWin=27, winSum=455
1989 04:41:14.152640 TX Vref=32, minBit 0, minWin=27, winSum=450
1990 04:41:14.155798 [TxChooseVref] Worse bit 5, Min win 27, Win sum 455, Final Vref 30
1991 04:41:14.155896
1992 04:41:14.159468 Final TX Range 1 Vref 30
1993 04:41:14.159575
1994 04:41:14.159641 ==
1995 04:41:14.161994 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 04:41:14.165674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 04:41:14.165808 ==
1998 04:41:14.168520
1999 04:41:14.168627
2000 04:41:14.168751 TX Vref Scan disable
2001 04:41:14.172445 == TX Byte 0 ==
2002 04:41:14.175669 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2003 04:41:14.182682 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2004 04:41:14.182811 == TX Byte 1 ==
2005 04:41:14.185434 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2006 04:41:14.192121 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2007 04:41:14.192237
2008 04:41:14.192312 [DATLAT]
2009 04:41:14.192372 Freq=800, CH1 RK1
2010 04:41:14.192430
2011 04:41:14.196320 DATLAT Default: 0xa
2012 04:41:14.196404 0, 0xFFFF, sum = 0
2013 04:41:14.198710 1, 0xFFFF, sum = 0
2014 04:41:14.198810 2, 0xFFFF, sum = 0
2015 04:41:14.201954 3, 0xFFFF, sum = 0
2016 04:41:14.205224 4, 0xFFFF, sum = 0
2017 04:41:14.205370 5, 0xFFFF, sum = 0
2018 04:41:14.208827 6, 0xFFFF, sum = 0
2019 04:41:14.208961 7, 0xFFFF, sum = 0
2020 04:41:14.212266 8, 0xFFFF, sum = 0
2021 04:41:14.212381 9, 0x0, sum = 1
2022 04:41:14.215029 10, 0x0, sum = 2
2023 04:41:14.215142 11, 0x0, sum = 3
2024 04:41:14.215236 12, 0x0, sum = 4
2025 04:41:14.218767 best_step = 10
2026 04:41:14.218876
2027 04:41:14.218956 ==
2028 04:41:14.222476 Dram Type= 6, Freq= 0, CH_1, rank 1
2029 04:41:14.225326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2030 04:41:14.225435 ==
2031 04:41:14.228389 RX Vref Scan: 0
2032 04:41:14.228501
2033 04:41:14.228583 RX Vref 0 -> 0, step: 1
2034 04:41:14.231528
2035 04:41:14.231630 RX Delay -95 -> 252, step: 8
2036 04:41:14.238983 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2037 04:41:14.242435 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2038 04:41:14.245349 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2039 04:41:14.249230 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2040 04:41:14.251870 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2041 04:41:14.258709 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2042 04:41:14.262125 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2043 04:41:14.265107 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2044 04:41:14.269230 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
2045 04:41:14.272101 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2046 04:41:14.278789 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2047 04:41:14.281969 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2048 04:41:14.285460 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2049 04:41:14.288357 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2050 04:41:14.295390 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2051 04:41:14.298153 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2052 04:41:14.298278 ==
2053 04:41:14.301727 Dram Type= 6, Freq= 0, CH_1, rank 1
2054 04:41:14.304949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2055 04:41:14.305038 ==
2056 04:41:14.308273 DQS Delay:
2057 04:41:14.308367 DQS0 = 0, DQS1 = 0
2058 04:41:14.308434 DQM Delay:
2059 04:41:14.312008 DQM0 = 86, DQM1 = 84
2060 04:41:14.312100 DQ Delay:
2061 04:41:14.315535 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2062 04:41:14.318448 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2063 04:41:14.321676 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =80
2064 04:41:14.324802 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =88
2065 04:41:14.324899
2066 04:41:14.324967
2067 04:41:14.334869 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f3b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 402 ps
2068 04:41:14.335036 CH1 RK1: MR19=606, MR18=1F3B
2069 04:41:14.341283 CH1_RK1: MR19=0x606, MR18=0x1F3B, DQSOSC=394, MR23=63, INC=95, DEC=63
2070 04:41:14.344800 [RxdqsGatingPostProcess] freq 800
2071 04:41:14.351669 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2072 04:41:14.354796 Pre-setting of DQS Precalculation
2073 04:41:14.357993 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2074 04:41:14.364823 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2075 04:41:14.374972 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2076 04:41:14.375123
2077 04:41:14.375196
2078 04:41:14.378370 [Calibration Summary] 1600 Mbps
2079 04:41:14.378451 CH 0, Rank 0
2080 04:41:14.381078 SW Impedance : PASS
2081 04:41:14.381160 DUTY Scan : NO K
2082 04:41:14.384695 ZQ Calibration : PASS
2083 04:41:14.387962 Jitter Meter : NO K
2084 04:41:14.388059 CBT Training : PASS
2085 04:41:14.391149 Write leveling : PASS
2086 04:41:14.394219 RX DQS gating : PASS
2087 04:41:14.394314 RX DQ/DQS(RDDQC) : PASS
2088 04:41:14.397905 TX DQ/DQS : PASS
2089 04:41:14.397999 RX DATLAT : PASS
2090 04:41:14.401301 RX DQ/DQS(Engine): PASS
2091 04:41:14.404775 TX OE : NO K
2092 04:41:14.404867 All Pass.
2093 04:41:14.404944
2094 04:41:14.407610 CH 0, Rank 1
2095 04:41:14.407688 SW Impedance : PASS
2096 04:41:14.410905 DUTY Scan : NO K
2097 04:41:14.410993 ZQ Calibration : PASS
2098 04:41:14.414428 Jitter Meter : NO K
2099 04:41:14.417475 CBT Training : PASS
2100 04:41:14.417570 Write leveling : PASS
2101 04:41:14.420788 RX DQS gating : PASS
2102 04:41:14.424126 RX DQ/DQS(RDDQC) : PASS
2103 04:41:14.424248 TX DQ/DQS : PASS
2104 04:41:14.427240 RX DATLAT : PASS
2105 04:41:14.430960 RX DQ/DQS(Engine): PASS
2106 04:41:14.431068 TX OE : NO K
2107 04:41:14.434288 All Pass.
2108 04:41:14.434376
2109 04:41:14.434484 CH 1, Rank 0
2110 04:41:14.437438 SW Impedance : PASS
2111 04:41:14.437521 DUTY Scan : NO K
2112 04:41:14.441231 ZQ Calibration : PASS
2113 04:41:14.444500 Jitter Meter : NO K
2114 04:41:14.444609 CBT Training : PASS
2115 04:41:14.447926 Write leveling : PASS
2116 04:41:14.451190 RX DQS gating : PASS
2117 04:41:14.451285 RX DQ/DQS(RDDQC) : PASS
2118 04:41:14.454046 TX DQ/DQS : PASS
2119 04:41:14.457837 RX DATLAT : PASS
2120 04:41:14.457935 RX DQ/DQS(Engine): PASS
2121 04:41:14.460981 TX OE : NO K
2122 04:41:14.461073 All Pass.
2123 04:41:14.461156
2124 04:41:14.463940 CH 1, Rank 1
2125 04:41:14.464020 SW Impedance : PASS
2126 04:41:14.467385 DUTY Scan : NO K
2127 04:41:14.467481 ZQ Calibration : PASS
2128 04:41:14.470422 Jitter Meter : NO K
2129 04:41:14.474565 CBT Training : PASS
2130 04:41:14.474674 Write leveling : PASS
2131 04:41:14.477778 RX DQS gating : PASS
2132 04:41:14.480438 RX DQ/DQS(RDDQC) : PASS
2133 04:41:14.480529 TX DQ/DQS : PASS
2134 04:41:14.483981 RX DATLAT : PASS
2135 04:41:14.487269 RX DQ/DQS(Engine): PASS
2136 04:41:14.487356 TX OE : NO K
2137 04:41:14.490598 All Pass.
2138 04:41:14.490676
2139 04:41:14.490758 DramC Write-DBI off
2140 04:41:14.494022 PER_BANK_REFRESH: Hybrid Mode
2141 04:41:14.494105 TX_TRACKING: ON
2142 04:41:14.497317 [GetDramInforAfterCalByMRR] Vendor 6.
2143 04:41:14.504232 [GetDramInforAfterCalByMRR] Revision 606.
2144 04:41:14.507618 [GetDramInforAfterCalByMRR] Revision 2 0.
2145 04:41:14.507714 MR0 0x3b3b
2146 04:41:14.507799 MR8 0x5151
2147 04:41:14.510585 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2148 04:41:14.510669
2149 04:41:14.513935 MR0 0x3b3b
2150 04:41:14.514016 MR8 0x5151
2151 04:41:14.517537 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2152 04:41:14.517621
2153 04:41:14.526910 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2154 04:41:14.530294 [FAST_K] Save calibration result to emmc
2155 04:41:14.533795 [FAST_K] Save calibration result to emmc
2156 04:41:14.536933 dram_init: config_dvfs: 1
2157 04:41:14.540865 dramc_set_vcore_voltage set vcore to 662500
2158 04:41:14.544076 Read voltage for 1200, 2
2159 04:41:14.544159 Vio18 = 0
2160 04:41:14.544244 Vcore = 662500
2161 04:41:14.546722 Vdram = 0
2162 04:41:14.546821 Vddq = 0
2163 04:41:14.546920 Vmddr = 0
2164 04:41:14.553771 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2165 04:41:14.557044 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2166 04:41:14.560285 MEM_TYPE=3, freq_sel=15
2167 04:41:14.564073 sv_algorithm_assistance_LP4_1600
2168 04:41:14.566904 ============ PULL DRAM RESETB DOWN ============
2169 04:41:14.570499 ========== PULL DRAM RESETB DOWN end =========
2170 04:41:14.576983 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2171 04:41:14.580171 ===================================
2172 04:41:14.580260 LPDDR4 DRAM CONFIGURATION
2173 04:41:14.583431 ===================================
2174 04:41:14.587097 EX_ROW_EN[0] = 0x0
2175 04:41:14.590641 EX_ROW_EN[1] = 0x0
2176 04:41:14.590728 LP4Y_EN = 0x0
2177 04:41:14.593369 WORK_FSP = 0x0
2178 04:41:14.593448 WL = 0x4
2179 04:41:14.596694 RL = 0x4
2180 04:41:14.596773 BL = 0x2
2181 04:41:14.600277 RPST = 0x0
2182 04:41:14.600363 RD_PRE = 0x0
2183 04:41:14.603863 WR_PRE = 0x1
2184 04:41:14.603941 WR_PST = 0x0
2185 04:41:14.606773 DBI_WR = 0x0
2186 04:41:14.606851 DBI_RD = 0x0
2187 04:41:14.610068 OTF = 0x1
2188 04:41:14.613191 ===================================
2189 04:41:14.616691 ===================================
2190 04:41:14.616780 ANA top config
2191 04:41:14.620160 ===================================
2192 04:41:14.623236 DLL_ASYNC_EN = 0
2193 04:41:14.626473 ALL_SLAVE_EN = 0
2194 04:41:14.629531 NEW_RANK_MODE = 1
2195 04:41:14.629610 DLL_IDLE_MODE = 1
2196 04:41:14.633581 LP45_APHY_COMB_EN = 1
2197 04:41:14.636155 TX_ODT_DIS = 1
2198 04:41:14.640281 NEW_8X_MODE = 1
2199 04:41:14.643137 ===================================
2200 04:41:14.646327 ===================================
2201 04:41:14.650143 data_rate = 2400
2202 04:41:14.650224 CKR = 1
2203 04:41:14.653184 DQ_P2S_RATIO = 8
2204 04:41:14.656184 ===================================
2205 04:41:14.659480 CA_P2S_RATIO = 8
2206 04:41:14.663015 DQ_CA_OPEN = 0
2207 04:41:14.666300 DQ_SEMI_OPEN = 0
2208 04:41:14.669568 CA_SEMI_OPEN = 0
2209 04:41:14.669656 CA_FULL_RATE = 0
2210 04:41:14.673102 DQ_CKDIV4_EN = 0
2211 04:41:14.676373 CA_CKDIV4_EN = 0
2212 04:41:14.679650 CA_PREDIV_EN = 0
2213 04:41:14.682799 PH8_DLY = 17
2214 04:41:14.686409 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2215 04:41:14.686488 DQ_AAMCK_DIV = 4
2216 04:41:14.689825 CA_AAMCK_DIV = 4
2217 04:41:14.692845 CA_ADMCK_DIV = 4
2218 04:41:14.696334 DQ_TRACK_CA_EN = 0
2219 04:41:14.699893 CA_PICK = 1200
2220 04:41:14.702866 CA_MCKIO = 1200
2221 04:41:14.706279 MCKIO_SEMI = 0
2222 04:41:14.709610 PLL_FREQ = 2366
2223 04:41:14.709691 DQ_UI_PI_RATIO = 32
2224 04:41:14.713289 CA_UI_PI_RATIO = 0
2225 04:41:14.716392 ===================================
2226 04:41:14.719243 ===================================
2227 04:41:14.722967 memory_type:LPDDR4
2228 04:41:14.726043 GP_NUM : 10
2229 04:41:14.726125 SRAM_EN : 1
2230 04:41:14.729250 MD32_EN : 0
2231 04:41:14.732690 ===================================
2232 04:41:14.732771 [ANA_INIT] >>>>>>>>>>>>>>
2233 04:41:14.736466 <<<<<< [CONFIGURE PHASE]: ANA_TX
2234 04:41:14.739112 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2235 04:41:14.743079 ===================================
2236 04:41:14.745718 data_rate = 2400,PCW = 0X5b00
2237 04:41:14.749571 ===================================
2238 04:41:14.752320 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2239 04:41:14.759450 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2240 04:41:14.765972 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2241 04:41:14.768771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2242 04:41:14.772448 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2243 04:41:14.776116 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2244 04:41:14.778829 [ANA_INIT] flow start
2245 04:41:14.778924 [ANA_INIT] PLL >>>>>>>>
2246 04:41:14.782472 [ANA_INIT] PLL <<<<<<<<
2247 04:41:14.785552 [ANA_INIT] MIDPI >>>>>>>>
2248 04:41:14.785635 [ANA_INIT] MIDPI <<<<<<<<
2249 04:41:14.788885 [ANA_INIT] DLL >>>>>>>>
2250 04:41:14.792028 [ANA_INIT] DLL <<<<<<<<
2251 04:41:14.792111 [ANA_INIT] flow end
2252 04:41:14.798991 ============ LP4 DIFF to SE enter ============
2253 04:41:14.802146 ============ LP4 DIFF to SE exit ============
2254 04:41:14.805309 [ANA_INIT] <<<<<<<<<<<<<
2255 04:41:14.808995 [Flow] Enable top DCM control >>>>>
2256 04:41:14.812060 [Flow] Enable top DCM control <<<<<
2257 04:41:14.812142 Enable DLL master slave shuffle
2258 04:41:14.818933 ==============================================================
2259 04:41:14.821831 Gating Mode config
2260 04:41:14.825431 ==============================================================
2261 04:41:14.829020 Config description:
2262 04:41:14.839117 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2263 04:41:14.845392 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2264 04:41:14.848688 SELPH_MODE 0: By rank 1: By Phase
2265 04:41:14.855448 ==============================================================
2266 04:41:14.858976 GAT_TRACK_EN = 1
2267 04:41:14.861941 RX_GATING_MODE = 2
2268 04:41:14.865067 RX_GATING_TRACK_MODE = 2
2269 04:41:14.868519 SELPH_MODE = 1
2270 04:41:14.868606 PICG_EARLY_EN = 1
2271 04:41:14.871771 VALID_LAT_VALUE = 1
2272 04:41:14.878351 ==============================================================
2273 04:41:14.881756 Enter into Gating configuration >>>>
2274 04:41:14.884824 Exit from Gating configuration <<<<
2275 04:41:14.888474 Enter into DVFS_PRE_config >>>>>
2276 04:41:14.899063 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2277 04:41:14.901563 Exit from DVFS_PRE_config <<<<<
2278 04:41:14.905562 Enter into PICG configuration >>>>
2279 04:41:14.908113 Exit from PICG configuration <<<<
2280 04:41:14.911597 [RX_INPUT] configuration >>>>>
2281 04:41:14.914760 [RX_INPUT] configuration <<<<<
2282 04:41:14.918050 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2283 04:41:14.925053 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2284 04:41:14.931890 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2285 04:41:14.938303 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2286 04:41:14.945048 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2287 04:41:14.948236 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2288 04:41:14.954512 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2289 04:41:14.958407 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2290 04:41:14.961464 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2291 04:41:14.964353 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2292 04:41:14.971053 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2293 04:41:14.974496 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2294 04:41:14.977905 ===================================
2295 04:41:14.981022 LPDDR4 DRAM CONFIGURATION
2296 04:41:14.984233 ===================================
2297 04:41:14.984315 EX_ROW_EN[0] = 0x0
2298 04:41:14.988072 EX_ROW_EN[1] = 0x0
2299 04:41:14.988159 LP4Y_EN = 0x0
2300 04:41:14.992013 WORK_FSP = 0x0
2301 04:41:14.992100 WL = 0x4
2302 04:41:14.995009 RL = 0x4
2303 04:41:14.995087 BL = 0x2
2304 04:41:14.997683 RPST = 0x0
2305 04:41:14.997769 RD_PRE = 0x0
2306 04:41:15.001032 WR_PRE = 0x1
2307 04:41:15.004762 WR_PST = 0x0
2308 04:41:15.004849 DBI_WR = 0x0
2309 04:41:15.007660 DBI_RD = 0x0
2310 04:41:15.007740 OTF = 0x1
2311 04:41:15.011079 ===================================
2312 04:41:15.014694 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2313 04:41:15.017981 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2314 04:41:15.024569 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2315 04:41:15.028117 ===================================
2316 04:41:15.031244 LPDDR4 DRAM CONFIGURATION
2317 04:41:15.034209 ===================================
2318 04:41:15.034305 EX_ROW_EN[0] = 0x10
2319 04:41:15.037899 EX_ROW_EN[1] = 0x0
2320 04:41:15.037995 LP4Y_EN = 0x0
2321 04:41:15.041027 WORK_FSP = 0x0
2322 04:41:15.041108 WL = 0x4
2323 04:41:15.044420 RL = 0x4
2324 04:41:15.044537 BL = 0x2
2325 04:41:15.047707 RPST = 0x0
2326 04:41:15.047829 RD_PRE = 0x0
2327 04:41:15.050650 WR_PRE = 0x1
2328 04:41:15.050755 WR_PST = 0x0
2329 04:41:15.054387 DBI_WR = 0x0
2330 04:41:15.057732 DBI_RD = 0x0
2331 04:41:15.057826 OTF = 0x1
2332 04:41:15.060709 ===================================
2333 04:41:15.067558 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2334 04:41:15.067661 ==
2335 04:41:15.070476 Dram Type= 6, Freq= 0, CH_0, rank 0
2336 04:41:15.074411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2337 04:41:15.074534 ==
2338 04:41:15.077270 [Duty_Offset_Calibration]
2339 04:41:15.077357 B0:2 B1:0 CA:4
2340 04:41:15.080614
2341 04:41:15.083466 [DutyScan_Calibration_Flow] k_type=0
2342 04:41:15.090565
2343 04:41:15.090659 ==CLK 0==
2344 04:41:15.094398 Final CLK duty delay cell = -4
2345 04:41:15.097640 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2346 04:41:15.101336 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2347 04:41:15.103861 [-4] AVG Duty = 4937%(X100)
2348 04:41:15.103938
2349 04:41:15.107561 CH0 CLK Duty spec in!! Max-Min= 187%
2350 04:41:15.110405 [DutyScan_Calibration_Flow] ====Done====
2351 04:41:15.110479
2352 04:41:15.114089 [DutyScan_Calibration_Flow] k_type=1
2353 04:41:15.130633
2354 04:41:15.130770 ==DQS 0 ==
2355 04:41:15.133697 Final DQS duty delay cell = 0
2356 04:41:15.137015 [0] MAX Duty = 5156%(X100), DQS PI = 18
2357 04:41:15.140425 [0] MIN Duty = 5093%(X100), DQS PI = 2
2358 04:41:15.143680 [0] AVG Duty = 5124%(X100)
2359 04:41:15.143772
2360 04:41:15.143838 ==DQS 1 ==
2361 04:41:15.146646 Final DQS duty delay cell = 0
2362 04:41:15.150437 [0] MAX Duty = 5125%(X100), DQS PI = 6
2363 04:41:15.154423 [0] MIN Duty = 5000%(X100), DQS PI = 0
2364 04:41:15.156728 [0] AVG Duty = 5062%(X100)
2365 04:41:15.156841
2366 04:41:15.159960 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2367 04:41:15.160045
2368 04:41:15.163733 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2369 04:41:15.167230 [DutyScan_Calibration_Flow] ====Done====
2370 04:41:15.167312
2371 04:41:15.170128 [DutyScan_Calibration_Flow] k_type=3
2372 04:41:15.186771
2373 04:41:15.186919 ==DQM 0 ==
2374 04:41:15.190073 Final DQM duty delay cell = 0
2375 04:41:15.193671 [0] MAX Duty = 5125%(X100), DQS PI = 20
2376 04:41:15.196481 [0] MIN Duty = 4844%(X100), DQS PI = 54
2377 04:41:15.199889 [0] AVG Duty = 4984%(X100)
2378 04:41:15.199981
2379 04:41:15.200048 ==DQM 1 ==
2380 04:41:15.203177 Final DQM duty delay cell = 0
2381 04:41:15.206598 [0] MAX Duty = 5000%(X100), DQS PI = 6
2382 04:41:15.210344 [0] MIN Duty = 4875%(X100), DQS PI = 18
2383 04:41:15.212930 [0] AVG Duty = 4937%(X100)
2384 04:41:15.213019
2385 04:41:15.216432 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2386 04:41:15.216535
2387 04:41:15.219616 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2388 04:41:15.223335 [DutyScan_Calibration_Flow] ====Done====
2389 04:41:15.223439
2390 04:41:15.226330 [DutyScan_Calibration_Flow] k_type=2
2391 04:41:15.243169
2392 04:41:15.243322 ==DQ 0 ==
2393 04:41:15.246296 Final DQ duty delay cell = 0
2394 04:41:15.249625 [0] MAX Duty = 5125%(X100), DQS PI = 18
2395 04:41:15.252962 [0] MIN Duty = 4969%(X100), DQS PI = 50
2396 04:41:15.253054 [0] AVG Duty = 5047%(X100)
2397 04:41:15.256393
2398 04:41:15.256483 ==DQ 1 ==
2399 04:41:15.260164 Final DQ duty delay cell = 0
2400 04:41:15.263061 [0] MAX Duty = 5125%(X100), DQS PI = 6
2401 04:41:15.266596 [0] MIN Duty = 4938%(X100), DQS PI = 16
2402 04:41:15.266691 [0] AVG Duty = 5031%(X100)
2403 04:41:15.266756
2404 04:41:15.273225 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2405 04:41:15.273323
2406 04:41:15.276974 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2407 04:41:15.279375 [DutyScan_Calibration_Flow] ====Done====
2408 04:41:15.279477 ==
2409 04:41:15.282727 Dram Type= 6, Freq= 0, CH_1, rank 0
2410 04:41:15.286258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2411 04:41:15.286349 ==
2412 04:41:15.289742 [Duty_Offset_Calibration]
2413 04:41:15.289828 B0:0 B1:-1 CA:3
2414 04:41:15.289925
2415 04:41:15.293092 [DutyScan_Calibration_Flow] k_type=0
2416 04:41:15.302692
2417 04:41:15.302816 ==CLK 0==
2418 04:41:15.305996 Final CLK duty delay cell = -4
2419 04:41:15.309272 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2420 04:41:15.312398 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2421 04:41:15.316197 [-4] AVG Duty = 4938%(X100)
2422 04:41:15.316293
2423 04:41:15.318704 CH1 CLK Duty spec in!! Max-Min= 124%
2424 04:41:15.322034 [DutyScan_Calibration_Flow] ====Done====
2425 04:41:15.322128
2426 04:41:15.325584 [DutyScan_Calibration_Flow] k_type=1
2427 04:41:15.341118
2428 04:41:15.341287 ==DQS 0 ==
2429 04:41:15.344533 Final DQS duty delay cell = 0
2430 04:41:15.347832 [0] MAX Duty = 5187%(X100), DQS PI = 28
2431 04:41:15.350915 [0] MIN Duty = 4938%(X100), DQS PI = 38
2432 04:41:15.354718 [0] AVG Duty = 5062%(X100)
2433 04:41:15.354819
2434 04:41:15.354885 ==DQS 1 ==
2435 04:41:15.357624 Final DQS duty delay cell = -4
2436 04:41:15.361280 [-4] MAX Duty = 5000%(X100), DQS PI = 10
2437 04:41:15.364813 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2438 04:41:15.368219 [-4] AVG Duty = 4937%(X100)
2439 04:41:15.368314
2440 04:41:15.370988 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2441 04:41:15.371073
2442 04:41:15.374237 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2443 04:41:15.377497 [DutyScan_Calibration_Flow] ====Done====
2444 04:41:15.377606
2445 04:41:15.381041 [DutyScan_Calibration_Flow] k_type=3
2446 04:41:15.397928
2447 04:41:15.398111 ==DQM 0 ==
2448 04:41:15.401403 Final DQM duty delay cell = 0
2449 04:41:15.405037 [0] MAX Duty = 5031%(X100), DQS PI = 26
2450 04:41:15.408285 [0] MIN Duty = 4813%(X100), DQS PI = 38
2451 04:41:15.410876 [0] AVG Duty = 4922%(X100)
2452 04:41:15.410979
2453 04:41:15.411045 ==DQM 1 ==
2454 04:41:15.414979 Final DQM duty delay cell = 0
2455 04:41:15.417881 [0] MAX Duty = 5000%(X100), DQS PI = 34
2456 04:41:15.421331 [0] MIN Duty = 4844%(X100), DQS PI = 0
2457 04:41:15.424286 [0] AVG Duty = 4922%(X100)
2458 04:41:15.424402
2459 04:41:15.427463 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2460 04:41:15.427565
2461 04:41:15.430845 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2462 04:41:15.434062 [DutyScan_Calibration_Flow] ====Done====
2463 04:41:15.434172
2464 04:41:15.437240 [DutyScan_Calibration_Flow] k_type=2
2465 04:41:15.453977
2466 04:41:15.454171 ==DQ 0 ==
2467 04:41:15.457473 Final DQ duty delay cell = -4
2468 04:41:15.460259 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2469 04:41:15.463990 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2470 04:41:15.467479 [-4] AVG Duty = 4953%(X100)
2471 04:41:15.467602
2472 04:41:15.467669 ==DQ 1 ==
2473 04:41:15.470415 Final DQ duty delay cell = 0
2474 04:41:15.473822 [0] MAX Duty = 5062%(X100), DQS PI = 34
2475 04:41:15.476810 [0] MIN Duty = 4844%(X100), DQS PI = 62
2476 04:41:15.480324 [0] AVG Duty = 4953%(X100)
2477 04:41:15.480419
2478 04:41:15.483166 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2479 04:41:15.483250
2480 04:41:15.486675 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2481 04:41:15.490222 [DutyScan_Calibration_Flow] ====Done====
2482 04:41:15.493214 nWR fixed to 30
2483 04:41:15.496977 [ModeRegInit_LP4] CH0 RK0
2484 04:41:15.497102 [ModeRegInit_LP4] CH0 RK1
2485 04:41:15.499931 [ModeRegInit_LP4] CH1 RK0
2486 04:41:15.503544 [ModeRegInit_LP4] CH1 RK1
2487 04:41:15.503634 match AC timing 7
2488 04:41:15.510294 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2489 04:41:15.513011 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2490 04:41:15.516223 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2491 04:41:15.523691 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2492 04:41:15.526512 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2493 04:41:15.526608 ==
2494 04:41:15.529921 Dram Type= 6, Freq= 0, CH_0, rank 0
2495 04:41:15.533291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2496 04:41:15.533381 ==
2497 04:41:15.539955 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2498 04:41:15.546178 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2499 04:41:15.554269 [CA 0] Center 39 (9~70) winsize 62
2500 04:41:15.557637 [CA 1] Center 39 (9~70) winsize 62
2501 04:41:15.561140 [CA 2] Center 35 (5~66) winsize 62
2502 04:41:15.564222 [CA 3] Center 35 (5~66) winsize 62
2503 04:41:15.567332 [CA 4] Center 33 (3~64) winsize 62
2504 04:41:15.570757 [CA 5] Center 33 (3~63) winsize 61
2505 04:41:15.570843
2506 04:41:15.573741 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2507 04:41:15.573818
2508 04:41:15.577403 [CATrainingPosCal] consider 1 rank data
2509 04:41:15.580594 u2DelayCellTimex100 = 270/100 ps
2510 04:41:15.583741 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2511 04:41:15.590529 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2512 04:41:15.594345 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2513 04:41:15.597181 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2514 04:41:15.600209 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2515 04:41:15.604396 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2516 04:41:15.604481
2517 04:41:15.606978 CA PerBit enable=1, Macro0, CA PI delay=33
2518 04:41:15.607063
2519 04:41:15.610146 [CBTSetCACLKResult] CA Dly = 33
2520 04:41:15.610223 CS Dly: 7 (0~38)
2521 04:41:15.613329 ==
2522 04:41:15.617098 Dram Type= 6, Freq= 0, CH_0, rank 1
2523 04:41:15.620132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 04:41:15.620209 ==
2525 04:41:15.623457 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2526 04:41:15.630443 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2527 04:41:15.640284 [CA 0] Center 39 (9~70) winsize 62
2528 04:41:15.643220 [CA 1] Center 39 (9~70) winsize 62
2529 04:41:15.646262 [CA 2] Center 35 (5~66) winsize 62
2530 04:41:15.649758 [CA 3] Center 35 (5~66) winsize 62
2531 04:41:15.653077 [CA 4] Center 34 (4~65) winsize 62
2532 04:41:15.656742 [CA 5] Center 33 (3~64) winsize 62
2533 04:41:15.656820
2534 04:41:15.659786 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2535 04:41:15.659861
2536 04:41:15.663268 [CATrainingPosCal] consider 2 rank data
2537 04:41:15.666403 u2DelayCellTimex100 = 270/100 ps
2538 04:41:15.669811 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2539 04:41:15.673408 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2540 04:41:15.680107 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2541 04:41:15.683216 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2542 04:41:15.686362 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2543 04:41:15.689523 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2544 04:41:15.689600
2545 04:41:15.692733 CA PerBit enable=1, Macro0, CA PI delay=33
2546 04:41:15.692803
2547 04:41:15.695960 [CBTSetCACLKResult] CA Dly = 33
2548 04:41:15.696032 CS Dly: 8 (0~41)
2549 04:41:15.696094
2550 04:41:15.699537 ----->DramcWriteLeveling(PI) begin...
2551 04:41:15.702930 ==
2552 04:41:15.706440 Dram Type= 6, Freq= 0, CH_0, rank 0
2553 04:41:15.709542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2554 04:41:15.709619 ==
2555 04:41:15.712904 Write leveling (Byte 0): 32 => 32
2556 04:41:15.716570 Write leveling (Byte 1): 28 => 28
2557 04:41:15.719274 DramcWriteLeveling(PI) end<-----
2558 04:41:15.719383
2559 04:41:15.719465 ==
2560 04:41:15.722659 Dram Type= 6, Freq= 0, CH_0, rank 0
2561 04:41:15.726231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2562 04:41:15.726314 ==
2563 04:41:15.729815 [Gating] SW mode calibration
2564 04:41:15.735966 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2565 04:41:15.743098 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2566 04:41:15.746057 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2567 04:41:15.749573 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2568 04:41:15.755994 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2569 04:41:15.759772 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2570 04:41:15.762882 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2571 04:41:15.765821 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2572 04:41:15.772490 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2573 04:41:15.776300 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2574 04:41:15.779235 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
2575 04:41:15.786001 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2576 04:41:15.789223 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2577 04:41:15.792751 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2578 04:41:15.799234 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 04:41:15.802436 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 04:41:15.806155 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2581 04:41:15.812950 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2582 04:41:15.815718 1 1 0 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
2583 04:41:15.818689 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2584 04:41:15.825573 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 04:41:15.829107 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 04:41:15.832028 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 04:41:15.838745 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 04:41:15.841810 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2589 04:41:15.845106 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2590 04:41:15.852270 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2591 04:41:15.855049 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 04:41:15.858735 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 04:41:15.865074 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 04:41:15.868297 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 04:41:15.872301 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 04:41:15.878569 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 04:41:15.881872 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 04:41:15.885338 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 04:41:15.891710 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 04:41:15.895067 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 04:41:15.898423 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 04:41:15.905131 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 04:41:15.908313 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 04:41:15.911497 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 04:41:15.918045 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2606 04:41:15.921747 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2607 04:41:15.924858 Total UI for P1: 0, mck2ui 16
2608 04:41:15.928725 best dqsien dly found for B0: ( 1, 3, 28)
2609 04:41:15.931744 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 04:41:15.934759 Total UI for P1: 0, mck2ui 16
2611 04:41:15.938188 best dqsien dly found for B1: ( 1, 4, 0)
2612 04:41:15.941550 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2613 04:41:15.944820 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2614 04:41:15.944901
2615 04:41:15.948094 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2616 04:41:15.954734 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2617 04:41:15.954824 [Gating] SW calibration Done
2618 04:41:15.954892 ==
2619 04:41:15.958233 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 04:41:15.965064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 04:41:15.965179 ==
2622 04:41:15.965251 RX Vref Scan: 0
2623 04:41:15.965313
2624 04:41:15.968137 RX Vref 0 -> 0, step: 1
2625 04:41:15.968224
2626 04:41:15.971554 RX Delay -40 -> 252, step: 8
2627 04:41:15.974800 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2628 04:41:15.978056 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2629 04:41:15.981487 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2630 04:41:15.988073 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2631 04:41:15.991313 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2632 04:41:15.994945 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2633 04:41:15.998267 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2634 04:41:16.001672 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2635 04:41:16.005012 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2636 04:41:16.010984 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2637 04:41:16.014482 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2638 04:41:16.017984 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2639 04:41:16.021197 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2640 04:41:16.027709 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2641 04:41:16.031297 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2642 04:41:16.034620 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2643 04:41:16.034707 ==
2644 04:41:16.037649 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 04:41:16.041323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 04:41:16.041409 ==
2647 04:41:16.044013 DQS Delay:
2648 04:41:16.044096 DQS0 = 0, DQS1 = 0
2649 04:41:16.047327 DQM Delay:
2650 04:41:16.047429 DQM0 = 118, DQM1 = 108
2651 04:41:16.051196 DQ Delay:
2652 04:41:16.054307 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2653 04:41:16.058308 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2654 04:41:16.061350 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2655 04:41:16.064188 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2656 04:41:16.064271
2657 04:41:16.064335
2658 04:41:16.064395 ==
2659 04:41:16.067357 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 04:41:16.071054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 04:41:16.071137 ==
2662 04:41:16.071202
2663 04:41:16.071262
2664 04:41:16.074227 TX Vref Scan disable
2665 04:41:16.078069 == TX Byte 0 ==
2666 04:41:16.081122 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2667 04:41:16.084041 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2668 04:41:16.087375 == TX Byte 1 ==
2669 04:41:16.090777 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2670 04:41:16.094037 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2671 04:41:16.094120 ==
2672 04:41:16.097401 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 04:41:16.100752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 04:41:16.104061 ==
2675 04:41:16.115001 TX Vref=22, minBit 1, minWin=25, winSum=415
2676 04:41:16.117673 TX Vref=24, minBit 10, minWin=25, winSum=420
2677 04:41:16.121186 TX Vref=26, minBit 1, minWin=26, winSum=431
2678 04:41:16.124825 TX Vref=28, minBit 4, minWin=26, winSum=431
2679 04:41:16.127460 TX Vref=30, minBit 12, minWin=26, winSum=435
2680 04:41:16.133809 TX Vref=32, minBit 5, minWin=26, winSum=431
2681 04:41:16.137582 [TxChooseVref] Worse bit 12, Min win 26, Win sum 435, Final Vref 30
2682 04:41:16.137687
2683 04:41:16.140728 Final TX Range 1 Vref 30
2684 04:41:16.140826
2685 04:41:16.140917 ==
2686 04:41:16.144005 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 04:41:16.147207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 04:41:16.150801 ==
2689 04:41:16.151001
2690 04:41:16.151082
2691 04:41:16.151170 TX Vref Scan disable
2692 04:41:16.154382 == TX Byte 0 ==
2693 04:41:16.157951 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2694 04:41:16.164316 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2695 04:41:16.164488 == TX Byte 1 ==
2696 04:41:16.167209 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2697 04:41:16.174226 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2698 04:41:16.174415
2699 04:41:16.174524 [DATLAT]
2700 04:41:16.174612 Freq=1200, CH0 RK0
2701 04:41:16.174733
2702 04:41:16.177419 DATLAT Default: 0xd
2703 04:41:16.177542 0, 0xFFFF, sum = 0
2704 04:41:16.180992 1, 0xFFFF, sum = 0
2705 04:41:16.183821 2, 0xFFFF, sum = 0
2706 04:41:16.183982 3, 0xFFFF, sum = 0
2707 04:41:16.187210 4, 0xFFFF, sum = 0
2708 04:41:16.187327 5, 0xFFFF, sum = 0
2709 04:41:16.190914 6, 0xFFFF, sum = 0
2710 04:41:16.191102 7, 0xFFFF, sum = 0
2711 04:41:16.194080 8, 0xFFFF, sum = 0
2712 04:41:16.194255 9, 0xFFFF, sum = 0
2713 04:41:16.197416 10, 0xFFFF, sum = 0
2714 04:41:16.197560 11, 0xFFFF, sum = 0
2715 04:41:16.200610 12, 0x0, sum = 1
2716 04:41:16.200767 13, 0x0, sum = 2
2717 04:41:16.203868 14, 0x0, sum = 3
2718 04:41:16.203998 15, 0x0, sum = 4
2719 04:41:16.207390 best_step = 13
2720 04:41:16.207483
2721 04:41:16.207544 ==
2722 04:41:16.210336 Dram Type= 6, Freq= 0, CH_0, rank 0
2723 04:41:16.214138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2724 04:41:16.214254 ==
2725 04:41:16.214349 RX Vref Scan: 1
2726 04:41:16.216976
2727 04:41:16.217074 Set Vref Range= 32 -> 127
2728 04:41:16.217160
2729 04:41:16.220273 RX Vref 32 -> 127, step: 1
2730 04:41:16.220346
2731 04:41:16.223807 RX Delay -21 -> 252, step: 4
2732 04:41:16.223908
2733 04:41:16.227126 Set Vref, RX VrefLevel [Byte0]: 32
2734 04:41:16.230318 [Byte1]: 32
2735 04:41:16.230457
2736 04:41:16.233970 Set Vref, RX VrefLevel [Byte0]: 33
2737 04:41:16.237211 [Byte1]: 33
2738 04:41:16.240880
2739 04:41:16.241050 Set Vref, RX VrefLevel [Byte0]: 34
2740 04:41:16.244171 [Byte1]: 34
2741 04:41:16.248755
2742 04:41:16.248925 Set Vref, RX VrefLevel [Byte0]: 35
2743 04:41:16.251826 [Byte1]: 35
2744 04:41:16.256728
2745 04:41:16.256855 Set Vref, RX VrefLevel [Byte0]: 36
2746 04:41:16.260142 [Byte1]: 36
2747 04:41:16.264853
2748 04:41:16.265011 Set Vref, RX VrefLevel [Byte0]: 37
2749 04:41:16.267853 [Byte1]: 37
2750 04:41:16.272092
2751 04:41:16.272220 Set Vref, RX VrefLevel [Byte0]: 38
2752 04:41:16.276230 [Byte1]: 38
2753 04:41:16.280140
2754 04:41:16.280290 Set Vref, RX VrefLevel [Byte0]: 39
2755 04:41:16.283769 [Byte1]: 39
2756 04:41:16.288367
2757 04:41:16.288493 Set Vref, RX VrefLevel [Byte0]: 40
2758 04:41:16.291721 [Byte1]: 40
2759 04:41:16.296200
2760 04:41:16.296350 Set Vref, RX VrefLevel [Byte0]: 41
2761 04:41:16.299410 [Byte1]: 41
2762 04:41:16.303884
2763 04:41:16.304017 Set Vref, RX VrefLevel [Byte0]: 42
2764 04:41:16.307682 [Byte1]: 42
2765 04:41:16.312087
2766 04:41:16.312203 Set Vref, RX VrefLevel [Byte0]: 43
2767 04:41:16.315339 [Byte1]: 43
2768 04:41:16.319712
2769 04:41:16.319841 Set Vref, RX VrefLevel [Byte0]: 44
2770 04:41:16.323151 [Byte1]: 44
2771 04:41:16.327826
2772 04:41:16.327955 Set Vref, RX VrefLevel [Byte0]: 45
2773 04:41:16.331425 [Byte1]: 45
2774 04:41:16.335602
2775 04:41:16.335722 Set Vref, RX VrefLevel [Byte0]: 46
2776 04:41:16.338787 [Byte1]: 46
2777 04:41:16.343904
2778 04:41:16.344034 Set Vref, RX VrefLevel [Byte0]: 47
2779 04:41:16.346815 [Byte1]: 47
2780 04:41:16.351946
2781 04:41:16.352059 Set Vref, RX VrefLevel [Byte0]: 48
2782 04:41:16.354863 [Byte1]: 48
2783 04:41:16.359296
2784 04:41:16.359415 Set Vref, RX VrefLevel [Byte0]: 49
2785 04:41:16.362693 [Byte1]: 49
2786 04:41:16.367534
2787 04:41:16.367620 Set Vref, RX VrefLevel [Byte0]: 50
2788 04:41:16.370981 [Byte1]: 50
2789 04:41:16.375422
2790 04:41:16.375521 Set Vref, RX VrefLevel [Byte0]: 51
2791 04:41:16.378514 [Byte1]: 51
2792 04:41:16.383835
2793 04:41:16.383949 Set Vref, RX VrefLevel [Byte0]: 52
2794 04:41:16.386480 [Byte1]: 52
2795 04:41:16.390983
2796 04:41:16.391087 Set Vref, RX VrefLevel [Byte0]: 53
2797 04:41:16.394918 [Byte1]: 53
2798 04:41:16.399140
2799 04:41:16.399271 Set Vref, RX VrefLevel [Byte0]: 54
2800 04:41:16.402412 [Byte1]: 54
2801 04:41:16.407194
2802 04:41:16.407330 Set Vref, RX VrefLevel [Byte0]: 55
2803 04:41:16.410497 [Byte1]: 55
2804 04:41:16.414806
2805 04:41:16.414892 Set Vref, RX VrefLevel [Byte0]: 56
2806 04:41:16.418300 [Byte1]: 56
2807 04:41:16.422857
2808 04:41:16.422938 Set Vref, RX VrefLevel [Byte0]: 57
2809 04:41:16.426199 [Byte1]: 57
2810 04:41:16.430866
2811 04:41:16.430950 Set Vref, RX VrefLevel [Byte0]: 58
2812 04:41:16.433908 [Byte1]: 58
2813 04:41:16.438617
2814 04:41:16.438701 Set Vref, RX VrefLevel [Byte0]: 59
2815 04:41:16.442089 [Byte1]: 59
2816 04:41:16.447333
2817 04:41:16.447474 Set Vref, RX VrefLevel [Byte0]: 60
2818 04:41:16.449890 [Byte1]: 60
2819 04:41:16.454722
2820 04:41:16.454843 Set Vref, RX VrefLevel [Byte0]: 61
2821 04:41:16.457861 [Byte1]: 61
2822 04:41:16.462734
2823 04:41:16.462847 Set Vref, RX VrefLevel [Byte0]: 62
2824 04:41:16.465830 [Byte1]: 62
2825 04:41:16.470443
2826 04:41:16.470536 Set Vref, RX VrefLevel [Byte0]: 63
2827 04:41:16.474033 [Byte1]: 63
2828 04:41:16.478673
2829 04:41:16.478769 Set Vref, RX VrefLevel [Byte0]: 64
2830 04:41:16.481941 [Byte1]: 64
2831 04:41:16.486588
2832 04:41:16.486672 Set Vref, RX VrefLevel [Byte0]: 65
2833 04:41:16.489740 [Byte1]: 65
2834 04:41:16.494318
2835 04:41:16.494395 Set Vref, RX VrefLevel [Byte0]: 66
2836 04:41:16.497377 [Byte1]: 66
2837 04:41:16.502182
2838 04:41:16.502300 Set Vref, RX VrefLevel [Byte0]: 67
2839 04:41:16.505755 [Byte1]: 67
2840 04:41:16.510620
2841 04:41:16.510720 Final RX Vref Byte 0 = 51 to rank0
2842 04:41:16.514116 Final RX Vref Byte 1 = 47 to rank0
2843 04:41:16.517052 Final RX Vref Byte 0 = 51 to rank1
2844 04:41:16.520554 Final RX Vref Byte 1 = 47 to rank1==
2845 04:41:16.523277 Dram Type= 6, Freq= 0, CH_0, rank 0
2846 04:41:16.530289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 04:41:16.530409 ==
2848 04:41:16.530484 DQS Delay:
2849 04:41:16.530587 DQS0 = 0, DQS1 = 0
2850 04:41:16.533093 DQM Delay:
2851 04:41:16.533174 DQM0 = 117, DQM1 = 103
2852 04:41:16.537331 DQ Delay:
2853 04:41:16.539788 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2854 04:41:16.543386 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
2855 04:41:16.547504 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =98
2856 04:41:16.549798 DQ12 =110, DQ13 =108, DQ14 =112, DQ15 =110
2857 04:41:16.549919
2858 04:41:16.550022
2859 04:41:16.556676 [DQSOSCAuto] RK0, (LSB)MR18= 0x4ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2860 04:41:16.560116 CH0 RK0: MR19=403, MR18=4FF
2861 04:41:16.566786 CH0_RK0: MR19=0x403, MR18=0x4FF, DQSOSC=408, MR23=63, INC=39, DEC=26
2862 04:41:16.566926
2863 04:41:16.569715 ----->DramcWriteLeveling(PI) begin...
2864 04:41:16.569845 ==
2865 04:41:16.573391 Dram Type= 6, Freq= 0, CH_0, rank 1
2866 04:41:16.576806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2867 04:41:16.576965 ==
2868 04:41:16.580147 Write leveling (Byte 0): 31 => 31
2869 04:41:16.582942 Write leveling (Byte 1): 25 => 25
2870 04:41:16.586810 DramcWriteLeveling(PI) end<-----
2871 04:41:16.586928
2872 04:41:16.587023 ==
2873 04:41:16.589802 Dram Type= 6, Freq= 0, CH_0, rank 1
2874 04:41:16.596785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2875 04:41:16.596896 ==
2876 04:41:16.596991 [Gating] SW mode calibration
2877 04:41:16.606481 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2878 04:41:16.609830 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2879 04:41:16.613580 0 15 0 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
2880 04:41:16.620124 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2881 04:41:16.622888 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2882 04:41:16.627067 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 04:41:16.632760 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 04:41:16.636670 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2885 04:41:16.639886 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2886 04:41:16.646633 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
2887 04:41:16.649739 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
2888 04:41:16.652541 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2889 04:41:16.659224 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 04:41:16.662836 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 04:41:16.665785 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 04:41:16.672654 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 04:41:16.675783 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2894 04:41:16.679124 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2895 04:41:16.686466 1 1 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2896 04:41:16.689108 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 04:41:16.692575 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 04:41:16.698842 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 04:41:16.702069 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 04:41:16.705617 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 04:41:16.711949 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2902 04:41:16.715227 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2903 04:41:16.718994 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2904 04:41:16.725677 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 04:41:16.729065 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 04:41:16.731919 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 04:41:16.739169 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 04:41:16.742327 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 04:41:16.745281 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 04:41:16.752278 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 04:41:16.755144 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 04:41:16.759086 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 04:41:16.765068 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 04:41:16.768561 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 04:41:16.771722 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 04:41:16.778633 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 04:41:16.781825 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2918 04:41:16.785173 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2919 04:41:16.788222 Total UI for P1: 0, mck2ui 16
2920 04:41:16.792053 best dqsien dly found for B0: ( 1, 3, 24)
2921 04:41:16.795354 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2922 04:41:16.801587 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 04:41:16.805168 Total UI for P1: 0, mck2ui 16
2924 04:41:16.808350 best dqsien dly found for B1: ( 1, 3, 30)
2925 04:41:16.811787 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2926 04:41:16.814807 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2927 04:41:16.814910
2928 04:41:16.817999 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2929 04:41:16.821832 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2930 04:41:16.825015 [Gating] SW calibration Done
2931 04:41:16.825120 ==
2932 04:41:16.828244 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 04:41:16.831733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 04:41:16.831820 ==
2935 04:41:16.834756 RX Vref Scan: 0
2936 04:41:16.834866
2937 04:41:16.838211 RX Vref 0 -> 0, step: 1
2938 04:41:16.838316
2939 04:41:16.838413 RX Delay -40 -> 252, step: 8
2940 04:41:16.845110 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2941 04:41:16.848586 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2942 04:41:16.851754 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2943 04:41:16.855099 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2944 04:41:16.858326 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2945 04:41:16.864960 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2946 04:41:16.868224 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2947 04:41:16.871509 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2948 04:41:16.875251 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2949 04:41:16.877848 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2950 04:41:16.884848 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2951 04:41:16.888258 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2952 04:41:16.891955 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2953 04:41:16.895162 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2954 04:41:16.898275 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2955 04:41:16.904994 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2956 04:41:16.905090 ==
2957 04:41:16.907949 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 04:41:16.911351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 04:41:16.911472 ==
2960 04:41:16.911572 DQS Delay:
2961 04:41:16.914731 DQS0 = 0, DQS1 = 0
2962 04:41:16.914814 DQM Delay:
2963 04:41:16.918327 DQM0 = 116, DQM1 = 106
2964 04:41:16.918411 DQ Delay:
2965 04:41:16.921427 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2966 04:41:16.924977 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2967 04:41:16.928211 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2968 04:41:16.931248 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2969 04:41:16.931332
2970 04:41:16.931410
2971 04:41:16.934546 ==
2972 04:41:16.937759 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 04:41:16.941650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 04:41:16.941732 ==
2975 04:41:16.941802
2976 04:41:16.941864
2977 04:41:16.944416 TX Vref Scan disable
2978 04:41:16.944512 == TX Byte 0 ==
2979 04:41:16.951268 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2980 04:41:16.954605 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2981 04:41:16.954690 == TX Byte 1 ==
2982 04:41:16.961237 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2983 04:41:16.964879 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2984 04:41:16.965012 ==
2985 04:41:16.968009 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 04:41:16.971152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 04:41:16.971257 ==
2988 04:41:16.983819 TX Vref=22, minBit 3, minWin=25, winSum=413
2989 04:41:16.986939 TX Vref=24, minBit 3, minWin=25, winSum=419
2990 04:41:16.990243 TX Vref=26, minBit 2, minWin=26, winSum=426
2991 04:41:16.993719 TX Vref=28, minBit 4, minWin=25, winSum=424
2992 04:41:16.996932 TX Vref=30, minBit 1, minWin=26, winSum=426
2993 04:41:17.003825 TX Vref=32, minBit 4, minWin=25, winSum=423
2994 04:41:17.006955 [TxChooseVref] Worse bit 2, Min win 26, Win sum 426, Final Vref 26
2995 04:41:17.007089
2996 04:41:17.009876 Final TX Range 1 Vref 26
2997 04:41:17.009990
2998 04:41:17.010084 ==
2999 04:41:17.013425 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 04:41:17.016653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 04:41:17.016763 ==
3002 04:41:17.019744
3003 04:41:17.019825
3004 04:41:17.019889 TX Vref Scan disable
3005 04:41:17.023533 == TX Byte 0 ==
3006 04:41:17.026457 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3007 04:41:17.029870 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3008 04:41:17.033407 == TX Byte 1 ==
3009 04:41:17.036658 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3010 04:41:17.040076 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3011 04:41:17.043305
3012 04:41:17.043415 [DATLAT]
3013 04:41:17.043510 Freq=1200, CH0 RK1
3014 04:41:17.043603
3015 04:41:17.046738 DATLAT Default: 0xd
3016 04:41:17.046844 0, 0xFFFF, sum = 0
3017 04:41:17.050049 1, 0xFFFF, sum = 0
3018 04:41:17.050151 2, 0xFFFF, sum = 0
3019 04:41:17.053315 3, 0xFFFF, sum = 0
3020 04:41:17.053408 4, 0xFFFF, sum = 0
3021 04:41:17.056755 5, 0xFFFF, sum = 0
3022 04:41:17.060017 6, 0xFFFF, sum = 0
3023 04:41:17.060095 7, 0xFFFF, sum = 0
3024 04:41:17.063269 8, 0xFFFF, sum = 0
3025 04:41:17.063385 9, 0xFFFF, sum = 0
3026 04:41:17.066709 10, 0xFFFF, sum = 0
3027 04:41:17.066793 11, 0xFFFF, sum = 0
3028 04:41:17.070124 12, 0x0, sum = 1
3029 04:41:17.070232 13, 0x0, sum = 2
3030 04:41:17.073229 14, 0x0, sum = 3
3031 04:41:17.073336 15, 0x0, sum = 4
3032 04:41:17.073433 best_step = 13
3033 04:41:17.076554
3034 04:41:17.076656 ==
3035 04:41:17.079822 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 04:41:17.083244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 04:41:17.083357 ==
3038 04:41:17.083437 RX Vref Scan: 0
3039 04:41:17.083500
3040 04:41:17.086591 RX Vref 0 -> 0, step: 1
3041 04:41:17.086675
3042 04:41:17.089872 RX Delay -21 -> 252, step: 4
3043 04:41:17.093031 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3044 04:41:17.099734 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3045 04:41:17.103352 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3046 04:41:17.106351 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3047 04:41:17.109912 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3048 04:41:17.113572 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3049 04:41:17.119816 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3050 04:41:17.122953 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3051 04:41:17.126491 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3052 04:41:17.129392 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3053 04:41:17.132677 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3054 04:41:17.139342 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3055 04:41:17.142954 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3056 04:41:17.146219 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3057 04:41:17.149678 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3058 04:41:17.152600 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3059 04:41:17.155879 ==
3060 04:41:17.159506 Dram Type= 6, Freq= 0, CH_0, rank 1
3061 04:41:17.162852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 04:41:17.162952 ==
3063 04:41:17.163060 DQS Delay:
3064 04:41:17.166516 DQS0 = 0, DQS1 = 0
3065 04:41:17.166620 DQM Delay:
3066 04:41:17.169228 DQM0 = 115, DQM1 = 104
3067 04:41:17.169302 DQ Delay:
3068 04:41:17.172931 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3069 04:41:17.176571 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3070 04:41:17.179763 DQ8 =96, DQ9 =92, DQ10 =106, DQ11 =98
3071 04:41:17.182867 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =110
3072 04:41:17.183002
3073 04:41:17.183097
3074 04:41:17.192700 [DQSOSCAuto] RK1, (LSB)MR18= 0xfd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3075 04:41:17.192894 CH0 RK1: MR19=403, MR18=FD
3076 04:41:17.198984 CH0_RK1: MR19=0x403, MR18=0xFD, DQSOSC=410, MR23=63, INC=39, DEC=26
3077 04:41:17.202237 [RxdqsGatingPostProcess] freq 1200
3078 04:41:17.208880 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3079 04:41:17.212302 best DQS0 dly(2T, 0.5T) = (0, 11)
3080 04:41:17.215996 best DQS1 dly(2T, 0.5T) = (0, 12)
3081 04:41:17.218984 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3082 04:41:17.222532 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3083 04:41:17.225349 best DQS0 dly(2T, 0.5T) = (0, 11)
3084 04:41:17.225434 best DQS1 dly(2T, 0.5T) = (0, 11)
3085 04:41:17.228924 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3086 04:41:17.232059 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3087 04:41:17.235384 Pre-setting of DQS Precalculation
3088 04:41:17.242492 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3089 04:41:17.242597 ==
3090 04:41:17.245765 Dram Type= 6, Freq= 0, CH_1, rank 0
3091 04:41:17.248550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3092 04:41:17.248660 ==
3093 04:41:17.255559 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3094 04:41:17.261993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3095 04:41:17.269180 [CA 0] Center 38 (8~68) winsize 61
3096 04:41:17.272909 [CA 1] Center 37 (7~68) winsize 62
3097 04:41:17.275984 [CA 2] Center 35 (5~65) winsize 61
3098 04:41:17.279141 [CA 3] Center 34 (4~64) winsize 61
3099 04:41:17.282176 [CA 4] Center 34 (4~65) winsize 62
3100 04:41:17.286368 [CA 5] Center 34 (4~64) winsize 61
3101 04:41:17.286508
3102 04:41:17.288885 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3103 04:41:17.289003
3104 04:41:17.292484 [CATrainingPosCal] consider 1 rank data
3105 04:41:17.295477 u2DelayCellTimex100 = 270/100 ps
3106 04:41:17.299284 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3107 04:41:17.305614 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3108 04:41:17.309222 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3109 04:41:17.312168 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3110 04:41:17.315625 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3111 04:41:17.319033 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3112 04:41:17.319149
3113 04:41:17.321986 CA PerBit enable=1, Macro0, CA PI delay=34
3114 04:41:17.322095
3115 04:41:17.325269 [CBTSetCACLKResult] CA Dly = 34
3116 04:41:17.325355 CS Dly: 5 (0~36)
3117 04:41:17.329098 ==
3118 04:41:17.332003 Dram Type= 6, Freq= 0, CH_1, rank 1
3119 04:41:17.335655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 04:41:17.335766 ==
3121 04:41:17.338937 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3122 04:41:17.345580 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3123 04:41:17.354388 [CA 0] Center 37 (7~68) winsize 62
3124 04:41:17.357912 [CA 1] Center 38 (8~68) winsize 61
3125 04:41:17.361342 [CA 2] Center 35 (5~65) winsize 61
3126 04:41:17.365002 [CA 3] Center 33 (3~64) winsize 62
3127 04:41:17.368256 [CA 4] Center 34 (4~64) winsize 61
3128 04:41:17.371236 [CA 5] Center 33 (3~64) winsize 62
3129 04:41:17.371340
3130 04:41:17.374845 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3131 04:41:17.374969
3132 04:41:17.377744 [CATrainingPosCal] consider 2 rank data
3133 04:41:17.381193 u2DelayCellTimex100 = 270/100 ps
3134 04:41:17.384843 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3135 04:41:17.388276 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3136 04:41:17.394533 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3137 04:41:17.397739 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3138 04:41:17.401067 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3139 04:41:17.404821 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3140 04:41:17.404937
3141 04:41:17.408085 CA PerBit enable=1, Macro0, CA PI delay=34
3142 04:41:17.408192
3143 04:41:17.411147 [CBTSetCACLKResult] CA Dly = 34
3144 04:41:17.411253 CS Dly: 6 (0~38)
3145 04:41:17.411346
3146 04:41:17.414677 ----->DramcWriteLeveling(PI) begin...
3147 04:41:17.417834 ==
3148 04:41:17.421275 Dram Type= 6, Freq= 0, CH_1, rank 0
3149 04:41:17.424543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3150 04:41:17.424631 ==
3151 04:41:17.428025 Write leveling (Byte 0): 25 => 25
3152 04:41:17.430852 Write leveling (Byte 1): 27 => 27
3153 04:41:17.434483 DramcWriteLeveling(PI) end<-----
3154 04:41:17.434593
3155 04:41:17.434686 ==
3156 04:41:17.437988 Dram Type= 6, Freq= 0, CH_1, rank 0
3157 04:41:17.441177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3158 04:41:17.441283 ==
3159 04:41:17.444505 [Gating] SW mode calibration
3160 04:41:17.451253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3161 04:41:17.457656 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3162 04:41:17.460940 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3163 04:41:17.464641 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 04:41:17.471664 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 04:41:17.474344 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 04:41:17.477390 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 04:41:17.481204 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 04:41:17.487623 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3169 04:41:17.490885 0 15 28 | B1->B0 | 2a2a 2626 | 0 0 | (1 0) (0 0)
3170 04:41:17.494300 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3171 04:41:17.501056 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 04:41:17.504255 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 04:41:17.507659 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 04:41:17.513986 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 04:41:17.517592 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 04:41:17.521141 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
3177 04:41:17.527259 1 0 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
3178 04:41:17.531028 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 04:41:17.534148 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 04:41:17.540639 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 04:41:17.544204 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 04:41:17.547313 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 04:41:17.554417 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 04:41:17.557524 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 04:41:17.560760 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3186 04:41:17.567306 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 04:41:17.571099 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 04:41:17.574256 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 04:41:17.580711 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 04:41:17.583583 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 04:41:17.587587 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 04:41:17.594162 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 04:41:17.597462 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 04:41:17.600495 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 04:41:17.608161 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 04:41:17.610346 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 04:41:17.613883 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 04:41:17.617348 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 04:41:17.623783 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 04:41:17.627001 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3201 04:41:17.630137 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3202 04:41:17.633751 Total UI for P1: 0, mck2ui 16
3203 04:41:17.637571 best dqsien dly found for B1: ( 1, 3, 24)
3204 04:41:17.643939 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 04:41:17.646977 Total UI for P1: 0, mck2ui 16
3206 04:41:17.650515 best dqsien dly found for B0: ( 1, 3, 26)
3207 04:41:17.653470 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3208 04:41:17.657154 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3209 04:41:17.657231
3210 04:41:17.660570 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3211 04:41:17.663271 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3212 04:41:17.667178 [Gating] SW calibration Done
3213 04:41:17.667249 ==
3214 04:41:17.670355 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 04:41:17.674004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 04:41:17.674075 ==
3217 04:41:17.677199 RX Vref Scan: 0
3218 04:41:17.677264
3219 04:41:17.677323 RX Vref 0 -> 0, step: 1
3220 04:41:17.680332
3221 04:41:17.680421 RX Delay -40 -> 252, step: 8
3222 04:41:17.687359 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3223 04:41:17.690361 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3224 04:41:17.693781 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3225 04:41:17.696687 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3226 04:41:17.700231 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3227 04:41:17.706915 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3228 04:41:17.710035 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3229 04:41:17.713437 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3230 04:41:17.716718 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3231 04:41:17.720070 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3232 04:41:17.726722 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3233 04:41:17.729601 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3234 04:41:17.733776 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3235 04:41:17.736973 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3236 04:41:17.739599 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3237 04:41:17.746958 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3238 04:41:17.747044 ==
3239 04:41:17.749937 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 04:41:17.753296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 04:41:17.753370 ==
3242 04:41:17.753433 DQS Delay:
3243 04:41:17.756174 DQS0 = 0, DQS1 = 0
3244 04:41:17.756247 DQM Delay:
3245 04:41:17.759708 DQM0 = 116, DQM1 = 112
3246 04:41:17.759777 DQ Delay:
3247 04:41:17.762628 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =119
3248 04:41:17.766279 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3249 04:41:17.769739 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3250 04:41:17.773292 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3251 04:41:17.773369
3252 04:41:17.776453
3253 04:41:17.776525 ==
3254 04:41:17.779289 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 04:41:17.782930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 04:41:17.783007 ==
3257 04:41:17.783070
3258 04:41:17.783129
3259 04:41:17.786039 TX Vref Scan disable
3260 04:41:17.786111 == TX Byte 0 ==
3261 04:41:17.793020 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3262 04:41:17.795879 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3263 04:41:17.795952 == TX Byte 1 ==
3264 04:41:17.802851 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3265 04:41:17.806315 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3266 04:41:17.806389 ==
3267 04:41:17.809484 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 04:41:17.812795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 04:41:17.812862 ==
3270 04:41:17.824742 TX Vref=22, minBit 3, minWin=24, winSum=406
3271 04:41:17.828518 TX Vref=24, minBit 8, minWin=24, winSum=413
3272 04:41:17.831565 TX Vref=26, minBit 1, minWin=25, winSum=420
3273 04:41:17.834557 TX Vref=28, minBit 9, minWin=25, winSum=425
3274 04:41:17.837954 TX Vref=30, minBit 9, minWin=25, winSum=424
3275 04:41:17.844753 TX Vref=32, minBit 11, minWin=25, winSum=423
3276 04:41:17.848444 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 28
3277 04:41:17.848525
3278 04:41:17.851318 Final TX Range 1 Vref 28
3279 04:41:17.851422
3280 04:41:17.851485 ==
3281 04:41:17.854806 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 04:41:17.858255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 04:41:17.861138 ==
3284 04:41:17.861214
3285 04:41:17.861276
3286 04:41:17.861334 TX Vref Scan disable
3287 04:41:17.864839 == TX Byte 0 ==
3288 04:41:17.868437 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3289 04:41:17.874610 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3290 04:41:17.874687 == TX Byte 1 ==
3291 04:41:17.877880 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3292 04:41:17.884409 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3293 04:41:17.884495
3294 04:41:17.884560 [DATLAT]
3295 04:41:17.884620 Freq=1200, CH1 RK0
3296 04:41:17.884684
3297 04:41:17.888053 DATLAT Default: 0xd
3298 04:41:17.890912 0, 0xFFFF, sum = 0
3299 04:41:17.890989 1, 0xFFFF, sum = 0
3300 04:41:17.894286 2, 0xFFFF, sum = 0
3301 04:41:17.894364 3, 0xFFFF, sum = 0
3302 04:41:17.897793 4, 0xFFFF, sum = 0
3303 04:41:17.897872 5, 0xFFFF, sum = 0
3304 04:41:17.900881 6, 0xFFFF, sum = 0
3305 04:41:17.900959 7, 0xFFFF, sum = 0
3306 04:41:17.904221 8, 0xFFFF, sum = 0
3307 04:41:17.904296 9, 0xFFFF, sum = 0
3308 04:41:17.907524 10, 0xFFFF, sum = 0
3309 04:41:17.907600 11, 0xFFFF, sum = 0
3310 04:41:17.911165 12, 0x0, sum = 1
3311 04:41:17.911265 13, 0x0, sum = 2
3312 04:41:17.914387 14, 0x0, sum = 3
3313 04:41:17.914461 15, 0x0, sum = 4
3314 04:41:17.918032 best_step = 13
3315 04:41:17.918106
3316 04:41:17.918168 ==
3317 04:41:17.920921 Dram Type= 6, Freq= 0, CH_1, rank 0
3318 04:41:17.924322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3319 04:41:17.924400 ==
3320 04:41:17.924468 RX Vref Scan: 1
3321 04:41:17.927978
3322 04:41:17.928050 Set Vref Range= 32 -> 127
3323 04:41:17.928111
3324 04:41:17.930876 RX Vref 32 -> 127, step: 1
3325 04:41:17.930947
3326 04:41:17.934037 RX Delay -13 -> 252, step: 4
3327 04:41:17.934110
3328 04:41:17.937828 Set Vref, RX VrefLevel [Byte0]: 32
3329 04:41:17.940847 [Byte1]: 32
3330 04:41:17.940922
3331 04:41:17.944283 Set Vref, RX VrefLevel [Byte0]: 33
3332 04:41:17.947348 [Byte1]: 33
3333 04:41:17.951139
3334 04:41:17.951260 Set Vref, RX VrefLevel [Byte0]: 34
3335 04:41:17.954067 [Byte1]: 34
3336 04:41:17.959011
3337 04:41:17.959087 Set Vref, RX VrefLevel [Byte0]: 35
3338 04:41:17.962012 [Byte1]: 35
3339 04:41:17.967165
3340 04:41:17.967246 Set Vref, RX VrefLevel [Byte0]: 36
3341 04:41:17.970000 [Byte1]: 36
3342 04:41:17.974581
3343 04:41:17.974655 Set Vref, RX VrefLevel [Byte0]: 37
3344 04:41:17.978266 [Byte1]: 37
3345 04:41:17.982670
3346 04:41:17.985798 Set Vref, RX VrefLevel [Byte0]: 38
3347 04:41:17.985876 [Byte1]: 38
3348 04:41:17.992771
3349 04:41:17.992881 Set Vref, RX VrefLevel [Byte0]: 39
3350 04:41:17.993983 [Byte1]: 39
3351 04:41:17.998482
3352 04:41:17.998557 Set Vref, RX VrefLevel [Byte0]: 40
3353 04:41:18.001513 [Byte1]: 40
3354 04:41:18.006199
3355 04:41:18.006285 Set Vref, RX VrefLevel [Byte0]: 41
3356 04:41:18.009290 [Byte1]: 41
3357 04:41:18.014030
3358 04:41:18.014110 Set Vref, RX VrefLevel [Byte0]: 42
3359 04:41:18.017505 [Byte1]: 42
3360 04:41:18.022334
3361 04:41:18.022409 Set Vref, RX VrefLevel [Byte0]: 43
3362 04:41:18.025271 [Byte1]: 43
3363 04:41:18.029636
3364 04:41:18.029715 Set Vref, RX VrefLevel [Byte0]: 44
3365 04:41:18.032974 [Byte1]: 44
3366 04:41:18.037525
3367 04:41:18.037615 Set Vref, RX VrefLevel [Byte0]: 45
3368 04:41:18.040869 [Byte1]: 45
3369 04:41:18.046097
3370 04:41:18.046170 Set Vref, RX VrefLevel [Byte0]: 46
3371 04:41:18.049000 [Byte1]: 46
3372 04:41:18.053638
3373 04:41:18.053713 Set Vref, RX VrefLevel [Byte0]: 47
3374 04:41:18.056697 [Byte1]: 47
3375 04:41:18.061350
3376 04:41:18.061444 Set Vref, RX VrefLevel [Byte0]: 48
3377 04:41:18.064563 [Byte1]: 48
3378 04:41:18.069742
3379 04:41:18.069845 Set Vref, RX VrefLevel [Byte0]: 49
3380 04:41:18.072701 [Byte1]: 49
3381 04:41:18.076825
3382 04:41:18.076899 Set Vref, RX VrefLevel [Byte0]: 50
3383 04:41:18.080140 [Byte1]: 50
3384 04:41:18.085690
3385 04:41:18.085765 Set Vref, RX VrefLevel [Byte0]: 51
3386 04:41:18.088174 [Byte1]: 51
3387 04:41:18.093323
3388 04:41:18.093395 Set Vref, RX VrefLevel [Byte0]: 52
3389 04:41:18.096084 [Byte1]: 52
3390 04:41:18.100583
3391 04:41:18.100655 Set Vref, RX VrefLevel [Byte0]: 53
3392 04:41:18.104051 [Byte1]: 53
3393 04:41:18.108583
3394 04:41:18.108660 Set Vref, RX VrefLevel [Byte0]: 54
3395 04:41:18.112009 [Byte1]: 54
3396 04:41:18.116705
3397 04:41:18.116781 Set Vref, RX VrefLevel [Byte0]: 55
3398 04:41:18.119821 [Byte1]: 55
3399 04:41:18.124267
3400 04:41:18.124348 Set Vref, RX VrefLevel [Byte0]: 56
3401 04:41:18.127729 [Byte1]: 56
3402 04:41:18.132303
3403 04:41:18.132400 Set Vref, RX VrefLevel [Byte0]: 57
3404 04:41:18.135763 [Byte1]: 57
3405 04:41:18.140052
3406 04:41:18.140155 Set Vref, RX VrefLevel [Byte0]: 58
3407 04:41:18.143323 [Byte1]: 58
3408 04:41:18.147852
3409 04:41:18.147958 Set Vref, RX VrefLevel [Byte0]: 59
3410 04:41:18.151160 [Byte1]: 59
3411 04:41:18.156279
3412 04:41:18.156354 Set Vref, RX VrefLevel [Byte0]: 60
3413 04:41:18.159096 [Byte1]: 60
3414 04:41:18.163665
3415 04:41:18.163746 Set Vref, RX VrefLevel [Byte0]: 61
3416 04:41:18.167240 [Byte1]: 61
3417 04:41:18.171531
3418 04:41:18.171644 Set Vref, RX VrefLevel [Byte0]: 62
3419 04:41:18.175417 [Byte1]: 62
3420 04:41:18.179725
3421 04:41:18.179830 Set Vref, RX VrefLevel [Byte0]: 63
3422 04:41:18.182924 [Byte1]: 63
3423 04:41:18.187667
3424 04:41:18.187760 Set Vref, RX VrefLevel [Byte0]: 64
3425 04:41:18.190622 [Byte1]: 64
3426 04:41:18.195076
3427 04:41:18.195177 Set Vref, RX VrefLevel [Byte0]: 65
3428 04:41:18.198419 [Byte1]: 65
3429 04:41:18.203191
3430 04:41:18.203290 Final RX Vref Byte 0 = 54 to rank0
3431 04:41:18.206285 Final RX Vref Byte 1 = 53 to rank0
3432 04:41:18.210130 Final RX Vref Byte 0 = 54 to rank1
3433 04:41:18.213484 Final RX Vref Byte 1 = 53 to rank1==
3434 04:41:18.216434 Dram Type= 6, Freq= 0, CH_1, rank 0
3435 04:41:18.223263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3436 04:41:18.223382 ==
3437 04:41:18.223460 DQS Delay:
3438 04:41:18.223519 DQS0 = 0, DQS1 = 0
3439 04:41:18.226293 DQM Delay:
3440 04:41:18.226358 DQM0 = 114, DQM1 = 113
3441 04:41:18.230299 DQ Delay:
3442 04:41:18.233458 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3443 04:41:18.236476 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3444 04:41:18.239586 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3445 04:41:18.243178 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =122
3446 04:41:18.243299
3447 04:41:18.243410
3448 04:41:18.252965 [DQSOSCAuto] RK0, (LSB)MR18= 0xf703, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3449 04:41:18.253047 CH1 RK0: MR19=304, MR18=F703
3450 04:41:18.259486 CH1_RK0: MR19=0x304, MR18=0xF703, DQSOSC=408, MR23=63, INC=39, DEC=26
3451 04:41:18.259568
3452 04:41:18.262614 ----->DramcWriteLeveling(PI) begin...
3453 04:41:18.262684 ==
3454 04:41:18.266596 Dram Type= 6, Freq= 0, CH_1, rank 1
3455 04:41:18.272503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3456 04:41:18.272579 ==
3457 04:41:18.276139 Write leveling (Byte 0): 23 => 23
3458 04:41:18.279713 Write leveling (Byte 1): 27 => 27
3459 04:41:18.279787 DramcWriteLeveling(PI) end<-----
3460 04:41:18.279854
3461 04:41:18.282552 ==
3462 04:41:18.285907 Dram Type= 6, Freq= 0, CH_1, rank 1
3463 04:41:18.289558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3464 04:41:18.289634 ==
3465 04:41:18.292855 [Gating] SW mode calibration
3466 04:41:18.299614 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3467 04:41:18.302283 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3468 04:41:18.309113 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 04:41:18.312590 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 04:41:18.316017 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 04:41:18.322628 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 04:41:18.326297 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3473 04:41:18.328968 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3474 04:41:18.336204 0 15 24 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
3475 04:41:18.339504 0 15 28 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
3476 04:41:18.342423 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 04:41:18.349057 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 04:41:18.352134 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 04:41:18.355407 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 04:41:18.362124 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3481 04:41:18.365455 1 0 20 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
3482 04:41:18.368904 1 0 24 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
3483 04:41:18.375545 1 0 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
3484 04:41:18.378667 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 04:41:18.381949 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 04:41:18.389349 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 04:41:18.392347 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 04:41:18.395498 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 04:41:18.402310 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 04:41:18.405389 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3491 04:41:18.408515 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3492 04:41:18.415484 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 04:41:18.418224 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 04:41:18.421486 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 04:41:18.428147 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 04:41:18.431870 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 04:41:18.435345 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 04:41:18.441671 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 04:41:18.444718 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 04:41:18.447969 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 04:41:18.454413 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 04:41:18.457905 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 04:41:18.461341 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 04:41:18.467690 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 04:41:18.471142 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3506 04:41:18.474422 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3507 04:41:18.480882 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3508 04:41:18.480987 Total UI for P1: 0, mck2ui 16
3509 04:41:18.487260 best dqsien dly found for B0: ( 1, 3, 22)
3510 04:41:18.490505 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 04:41:18.494404 Total UI for P1: 0, mck2ui 16
3512 04:41:18.497115 best dqsien dly found for B1: ( 1, 3, 26)
3513 04:41:18.500513 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3514 04:41:18.503740 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3515 04:41:18.503822
3516 04:41:18.506900 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3517 04:41:18.511067 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3518 04:41:18.513749 [Gating] SW calibration Done
3519 04:41:18.513829 ==
3520 04:41:18.516926 Dram Type= 6, Freq= 0, CH_1, rank 1
3521 04:41:18.523639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3522 04:41:18.523716 ==
3523 04:41:18.523778 RX Vref Scan: 0
3524 04:41:18.523844
3525 04:41:18.526868 RX Vref 0 -> 0, step: 1
3526 04:41:18.526936
3527 04:41:18.530350 RX Delay -40 -> 252, step: 8
3528 04:41:18.533080 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3529 04:41:18.537061 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3530 04:41:18.539837 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3531 04:41:18.546557 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3532 04:41:18.549826 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3533 04:41:18.552868 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3534 04:41:18.559978 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3535 04:41:18.560090 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3536 04:41:18.566388 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3537 04:41:18.569239 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3538 04:41:18.573112 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3539 04:41:18.576217 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3540 04:41:18.579281 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3541 04:41:18.585935 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3542 04:41:18.588901 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3543 04:41:18.593239 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3544 04:41:18.593312 ==
3545 04:41:18.595779 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 04:41:18.599221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 04:41:18.602078 ==
3548 04:41:18.602165 DQS Delay:
3549 04:41:18.602232 DQS0 = 0, DQS1 = 0
3550 04:41:18.605952 DQM Delay:
3551 04:41:18.606023 DQM0 = 115, DQM1 = 112
3552 04:41:18.608730 DQ Delay:
3553 04:41:18.611852 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3554 04:41:18.615318 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =119
3555 04:41:18.619084 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3556 04:41:18.622194 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3557 04:41:18.622269
3558 04:41:18.622334
3559 04:41:18.622392 ==
3560 04:41:18.625424 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 04:41:18.628791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 04:41:18.631824 ==
3563 04:41:18.631890
3564 04:41:18.631955
3565 04:41:18.632012 TX Vref Scan disable
3566 04:41:18.635033 == TX Byte 0 ==
3567 04:41:18.638714 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3568 04:41:18.641749 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3569 04:41:18.646007 == TX Byte 1 ==
3570 04:41:18.648655 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3571 04:41:18.651797 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3572 04:41:18.655256 ==
3573 04:41:18.655326 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 04:41:18.661314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 04:41:18.661391 ==
3576 04:41:18.672737 TX Vref=22, minBit 8, minWin=25, winSum=420
3577 04:41:18.676160 TX Vref=24, minBit 2, minWin=25, winSum=421
3578 04:41:18.679523 TX Vref=26, minBit 9, minWin=25, winSum=423
3579 04:41:18.682611 TX Vref=28, minBit 3, minWin=26, winSum=430
3580 04:41:18.685679 TX Vref=30, minBit 7, minWin=26, winSum=434
3581 04:41:18.692858 TX Vref=32, minBit 8, minWin=26, winSum=431
3582 04:41:18.695875 [TxChooseVref] Worse bit 7, Min win 26, Win sum 434, Final Vref 30
3583 04:41:18.695951
3584 04:41:18.698839 Final TX Range 1 Vref 30
3585 04:41:18.698914
3586 04:41:18.698976 ==
3587 04:41:18.702253 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 04:41:18.705647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 04:41:18.708702 ==
3590 04:41:18.708774
3591 04:41:18.708835
3592 04:41:18.708892 TX Vref Scan disable
3593 04:41:18.712681 == TX Byte 0 ==
3594 04:41:18.715603 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3595 04:41:18.722400 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3596 04:41:18.722479 == TX Byte 1 ==
3597 04:41:18.725922 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3598 04:41:18.732403 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3599 04:41:18.732484
3600 04:41:18.732545 [DATLAT]
3601 04:41:18.732603 Freq=1200, CH1 RK1
3602 04:41:18.732660
3603 04:41:18.735931 DATLAT Default: 0xd
3604 04:41:18.739109 0, 0xFFFF, sum = 0
3605 04:41:18.739176 1, 0xFFFF, sum = 0
3606 04:41:18.739235 2, 0xFFFF, sum = 0
3607 04:41:18.742730 3, 0xFFFF, sum = 0
3608 04:41:18.745438 4, 0xFFFF, sum = 0
3609 04:41:18.745507 5, 0xFFFF, sum = 0
3610 04:41:18.749628 6, 0xFFFF, sum = 0
3611 04:41:18.749701 7, 0xFFFF, sum = 0
3612 04:41:18.752169 8, 0xFFFF, sum = 0
3613 04:41:18.752236 9, 0xFFFF, sum = 0
3614 04:41:18.755496 10, 0xFFFF, sum = 0
3615 04:41:18.755566 11, 0xFFFF, sum = 0
3616 04:41:18.758742 12, 0x0, sum = 1
3617 04:41:18.758808 13, 0x0, sum = 2
3618 04:41:18.762102 14, 0x0, sum = 3
3619 04:41:18.762174 15, 0x0, sum = 4
3620 04:41:18.765271 best_step = 13
3621 04:41:18.765341
3622 04:41:18.765400 ==
3623 04:41:18.768647 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 04:41:18.772230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 04:41:18.772297 ==
3626 04:41:18.772355 RX Vref Scan: 0
3627 04:41:18.775523
3628 04:41:18.775586 RX Vref 0 -> 0, step: 1
3629 04:41:18.775642
3630 04:41:18.779238 RX Delay -13 -> 252, step: 4
3631 04:41:18.784965 iDelay=191, Bit 0, Center 116 (47 ~ 186) 140
3632 04:41:18.788265 iDelay=191, Bit 1, Center 112 (43 ~ 182) 140
3633 04:41:18.791491 iDelay=191, Bit 2, Center 106 (39 ~ 174) 136
3634 04:41:18.794875 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3635 04:41:18.798350 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3636 04:41:18.805036 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3637 04:41:18.808331 iDelay=191, Bit 6, Center 120 (51 ~ 190) 140
3638 04:41:18.811379 iDelay=191, Bit 7, Center 114 (47 ~ 182) 136
3639 04:41:18.814593 iDelay=191, Bit 8, Center 100 (39 ~ 162) 124
3640 04:41:18.818108 iDelay=191, Bit 9, Center 102 (39 ~ 166) 128
3641 04:41:18.824381 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3642 04:41:18.827912 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3643 04:41:18.830925 iDelay=191, Bit 12, Center 120 (59 ~ 182) 124
3644 04:41:18.834473 iDelay=191, Bit 13, Center 120 (59 ~ 182) 124
3645 04:41:18.840800 iDelay=191, Bit 14, Center 120 (59 ~ 182) 124
3646 04:41:18.844182 iDelay=191, Bit 15, Center 122 (59 ~ 186) 128
3647 04:41:18.844257 ==
3648 04:41:18.847379 Dram Type= 6, Freq= 0, CH_1, rank 1
3649 04:41:18.850832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3650 04:41:18.850905 ==
3651 04:41:18.853916 DQS Delay:
3652 04:41:18.853984 DQS0 = 0, DQS1 = 0
3653 04:41:18.854043 DQM Delay:
3654 04:41:18.857695 DQM0 = 114, DQM1 = 113
3655 04:41:18.857762 DQ Delay:
3656 04:41:18.860728 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =112
3657 04:41:18.864353 DQ4 =114, DQ5 =122, DQ6 =120, DQ7 =114
3658 04:41:18.867334 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3659 04:41:18.873779 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =122
3660 04:41:18.873856
3661 04:41:18.873918
3662 04:41:18.880295 [DQSOSCAuto] RK1, (LSB)MR18= 0xf709, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3663 04:41:18.883496 CH1 RK1: MR19=304, MR18=F709
3664 04:41:18.890348 CH1_RK1: MR19=0x304, MR18=0xF709, DQSOSC=406, MR23=63, INC=39, DEC=26
3665 04:41:18.893641 [RxdqsGatingPostProcess] freq 1200
3666 04:41:18.900158 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3667 04:41:18.900247 best DQS0 dly(2T, 0.5T) = (0, 11)
3668 04:41:18.903985 best DQS1 dly(2T, 0.5T) = (0, 11)
3669 04:41:18.907036 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3670 04:41:18.909953 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3671 04:41:18.914086 best DQS0 dly(2T, 0.5T) = (0, 11)
3672 04:41:18.917061 best DQS1 dly(2T, 0.5T) = (0, 11)
3673 04:41:18.919849 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3674 04:41:18.923224 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3675 04:41:18.926434 Pre-setting of DQS Precalculation
3676 04:41:18.933257 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3677 04:41:18.940141 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3678 04:41:18.946109 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3679 04:41:18.946197
3680 04:41:18.946261
3681 04:41:18.949946 [Calibration Summary] 2400 Mbps
3682 04:41:18.950028 CH 0, Rank 0
3683 04:41:18.952688 SW Impedance : PASS
3684 04:41:18.956664 DUTY Scan : NO K
3685 04:41:18.956746 ZQ Calibration : PASS
3686 04:41:18.959569 Jitter Meter : NO K
3687 04:41:18.962952 CBT Training : PASS
3688 04:41:18.963034 Write leveling : PASS
3689 04:41:18.966046 RX DQS gating : PASS
3690 04:41:18.969229 RX DQ/DQS(RDDQC) : PASS
3691 04:41:18.969310 TX DQ/DQS : PASS
3692 04:41:18.972927 RX DATLAT : PASS
3693 04:41:18.973008 RX DQ/DQS(Engine): PASS
3694 04:41:18.975907 TX OE : NO K
3695 04:41:18.976034 All Pass.
3696 04:41:18.976097
3697 04:41:18.979346 CH 0, Rank 1
3698 04:41:18.979469 SW Impedance : PASS
3699 04:41:18.982707 DUTY Scan : NO K
3700 04:41:18.985920 ZQ Calibration : PASS
3701 04:41:18.986002 Jitter Meter : NO K
3702 04:41:18.989102 CBT Training : PASS
3703 04:41:18.992854 Write leveling : PASS
3704 04:41:18.992935 RX DQS gating : PASS
3705 04:41:18.995684 RX DQ/DQS(RDDQC) : PASS
3706 04:41:18.999458 TX DQ/DQS : PASS
3707 04:41:18.999571 RX DATLAT : PASS
3708 04:41:19.002087 RX DQ/DQS(Engine): PASS
3709 04:41:19.005392 TX OE : NO K
3710 04:41:19.005473 All Pass.
3711 04:41:19.005537
3712 04:41:19.005597 CH 1, Rank 0
3713 04:41:19.009103 SW Impedance : PASS
3714 04:41:19.012084 DUTY Scan : NO K
3715 04:41:19.012166 ZQ Calibration : PASS
3716 04:41:19.015444 Jitter Meter : NO K
3717 04:41:19.018596 CBT Training : PASS
3718 04:41:19.018677 Write leveling : PASS
3719 04:41:19.021973 RX DQS gating : PASS
3720 04:41:19.025047 RX DQ/DQS(RDDQC) : PASS
3721 04:41:19.025129 TX DQ/DQS : PASS
3722 04:41:19.029198 RX DATLAT : PASS
3723 04:41:19.032156 RX DQ/DQS(Engine): PASS
3724 04:41:19.032254 TX OE : NO K
3725 04:41:19.035461 All Pass.
3726 04:41:19.035606
3727 04:41:19.035670 CH 1, Rank 1
3728 04:41:19.038411 SW Impedance : PASS
3729 04:41:19.038492 DUTY Scan : NO K
3730 04:41:19.042040 ZQ Calibration : PASS
3731 04:41:19.044799 Jitter Meter : NO K
3732 04:41:19.044881 CBT Training : PASS
3733 04:41:19.048259 Write leveling : PASS
3734 04:41:19.052022 RX DQS gating : PASS
3735 04:41:19.052105 RX DQ/DQS(RDDQC) : PASS
3736 04:41:19.054893 TX DQ/DQS : PASS
3737 04:41:19.058117 RX DATLAT : PASS
3738 04:41:19.058198 RX DQ/DQS(Engine): PASS
3739 04:41:19.061174 TX OE : NO K
3740 04:41:19.061256 All Pass.
3741 04:41:19.061320
3742 04:41:19.064390 DramC Write-DBI off
3743 04:41:19.067821 PER_BANK_REFRESH: Hybrid Mode
3744 04:41:19.067904 TX_TRACKING: ON
3745 04:41:19.078241 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3746 04:41:19.080935 [FAST_K] Save calibration result to emmc
3747 04:41:19.084902 dramc_set_vcore_voltage set vcore to 650000
3748 04:41:19.087700 Read voltage for 600, 5
3749 04:41:19.087784 Vio18 = 0
3750 04:41:19.087848 Vcore = 650000
3751 04:41:19.091240 Vdram = 0
3752 04:41:19.091366 Vddq = 0
3753 04:41:19.091450 Vmddr = 0
3754 04:41:19.097527 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3755 04:41:19.100732 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3756 04:41:19.104062 MEM_TYPE=3, freq_sel=19
3757 04:41:19.107429 sv_algorithm_assistance_LP4_1600
3758 04:41:19.110866 ============ PULL DRAM RESETB DOWN ============
3759 04:41:19.114432 ========== PULL DRAM RESETB DOWN end =========
3760 04:41:19.120801 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3761 04:41:19.123880 ===================================
3762 04:41:19.127233 LPDDR4 DRAM CONFIGURATION
3763 04:41:19.130364 ===================================
3764 04:41:19.130446 EX_ROW_EN[0] = 0x0
3765 04:41:19.133666 EX_ROW_EN[1] = 0x0
3766 04:41:19.133748 LP4Y_EN = 0x0
3767 04:41:19.137616 WORK_FSP = 0x0
3768 04:41:19.137697 WL = 0x2
3769 04:41:19.140742 RL = 0x2
3770 04:41:19.140829 BL = 0x2
3771 04:41:19.143953 RPST = 0x0
3772 04:41:19.144029 RD_PRE = 0x0
3773 04:41:19.147655 WR_PRE = 0x1
3774 04:41:19.147723 WR_PST = 0x0
3775 04:41:19.150179 DBI_WR = 0x0
3776 04:41:19.150249 DBI_RD = 0x0
3777 04:41:19.153537 OTF = 0x1
3778 04:41:19.156967 ===================================
3779 04:41:19.160545 ===================================
3780 04:41:19.160614 ANA top config
3781 04:41:19.163636 ===================================
3782 04:41:19.166772 DLL_ASYNC_EN = 0
3783 04:41:19.170623 ALL_SLAVE_EN = 1
3784 04:41:19.173491 NEW_RANK_MODE = 1
3785 04:41:19.177302 DLL_IDLE_MODE = 1
3786 04:41:19.177373 LP45_APHY_COMB_EN = 1
3787 04:41:19.180072 TX_ODT_DIS = 1
3788 04:41:19.183299 NEW_8X_MODE = 1
3789 04:41:19.186363 ===================================
3790 04:41:19.189548 ===================================
3791 04:41:19.192845 data_rate = 1200
3792 04:41:19.196227 CKR = 1
3793 04:41:19.199617 DQ_P2S_RATIO = 8
3794 04:41:19.199692 ===================================
3795 04:41:19.203084 CA_P2S_RATIO = 8
3796 04:41:19.206478 DQ_CA_OPEN = 0
3797 04:41:19.209496 DQ_SEMI_OPEN = 0
3798 04:41:19.213184 CA_SEMI_OPEN = 0
3799 04:41:19.216042 CA_FULL_RATE = 0
3800 04:41:19.216110 DQ_CKDIV4_EN = 1
3801 04:41:19.219617 CA_CKDIV4_EN = 1
3802 04:41:19.223127 CA_PREDIV_EN = 0
3803 04:41:19.225836 PH8_DLY = 0
3804 04:41:19.229718 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3805 04:41:19.232658 DQ_AAMCK_DIV = 4
3806 04:41:19.235769 CA_AAMCK_DIV = 4
3807 04:41:19.235843 CA_ADMCK_DIV = 4
3808 04:41:19.239050 DQ_TRACK_CA_EN = 0
3809 04:41:19.242961 CA_PICK = 600
3810 04:41:19.245773 CA_MCKIO = 600
3811 04:41:19.249230 MCKIO_SEMI = 0
3812 04:41:19.252327 PLL_FREQ = 2288
3813 04:41:19.255869 DQ_UI_PI_RATIO = 32
3814 04:41:19.255951 CA_UI_PI_RATIO = 0
3815 04:41:19.258957 ===================================
3816 04:41:19.261986 ===================================
3817 04:41:19.265594 memory_type:LPDDR4
3818 04:41:19.268605 GP_NUM : 10
3819 04:41:19.268687 SRAM_EN : 1
3820 04:41:19.272051 MD32_EN : 0
3821 04:41:19.275357 ===================================
3822 04:41:19.279296 [ANA_INIT] >>>>>>>>>>>>>>
3823 04:41:19.282559 <<<<<< [CONFIGURE PHASE]: ANA_TX
3824 04:41:19.286287 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3825 04:41:19.288294 ===================================
3826 04:41:19.291795 data_rate = 1200,PCW = 0X5800
3827 04:41:19.295191 ===================================
3828 04:41:19.298191 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3829 04:41:19.301924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3830 04:41:19.308248 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3831 04:41:19.311579 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3832 04:41:19.314950 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3833 04:41:19.318228 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3834 04:41:19.321202 [ANA_INIT] flow start
3835 04:41:19.324603 [ANA_INIT] PLL >>>>>>>>
3836 04:41:19.324678 [ANA_INIT] PLL <<<<<<<<
3837 04:41:19.327772 [ANA_INIT] MIDPI >>>>>>>>
3838 04:41:19.331428 [ANA_INIT] MIDPI <<<<<<<<
3839 04:41:19.334810 [ANA_INIT] DLL >>>>>>>>
3840 04:41:19.334907 [ANA_INIT] flow end
3841 04:41:19.337995 ============ LP4 DIFF to SE enter ============
3842 04:41:19.344664 ============ LP4 DIFF to SE exit ============
3843 04:41:19.344775 [ANA_INIT] <<<<<<<<<<<<<
3844 04:41:19.347895 [Flow] Enable top DCM control >>>>>
3845 04:41:19.351250 [Flow] Enable top DCM control <<<<<
3846 04:41:19.354720 Enable DLL master slave shuffle
3847 04:41:19.360581 ==============================================================
3848 04:41:19.360688 Gating Mode config
3849 04:41:19.367607 ==============================================================
3850 04:41:19.371549 Config description:
3851 04:41:19.380886 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3852 04:41:19.387475 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3853 04:41:19.390787 SELPH_MODE 0: By rank 1: By Phase
3854 04:41:19.397467 ==============================================================
3855 04:41:19.400677 GAT_TRACK_EN = 1
3856 04:41:19.404061 RX_GATING_MODE = 2
3857 04:41:19.404147 RX_GATING_TRACK_MODE = 2
3858 04:41:19.407269 SELPH_MODE = 1
3859 04:41:19.410484 PICG_EARLY_EN = 1
3860 04:41:19.413833 VALID_LAT_VALUE = 1
3861 04:41:19.420563 ==============================================================
3862 04:41:19.423770 Enter into Gating configuration >>>>
3863 04:41:19.427003 Exit from Gating configuration <<<<
3864 04:41:19.429997 Enter into DVFS_PRE_config >>>>>
3865 04:41:19.440165 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3866 04:41:19.443771 Exit from DVFS_PRE_config <<<<<
3867 04:41:19.446485 Enter into PICG configuration >>>>
3868 04:41:19.449633 Exit from PICG configuration <<<<
3869 04:41:19.453270 [RX_INPUT] configuration >>>>>
3870 04:41:19.456591 [RX_INPUT] configuration <<<<<
3871 04:41:19.459999 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3872 04:41:19.466798 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3873 04:41:19.473073 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3874 04:41:19.479404 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3875 04:41:19.486059 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3876 04:41:19.492981 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3877 04:41:19.496272 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3878 04:41:19.498915 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3879 04:41:19.502403 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3880 04:41:19.509551 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3881 04:41:19.512793 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3882 04:41:19.515551 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3883 04:41:19.518939 ===================================
3884 04:41:19.522123 LPDDR4 DRAM CONFIGURATION
3885 04:41:19.525359 ===================================
3886 04:41:19.525444 EX_ROW_EN[0] = 0x0
3887 04:41:19.528849 EX_ROW_EN[1] = 0x0
3888 04:41:19.532367 LP4Y_EN = 0x0
3889 04:41:19.532466 WORK_FSP = 0x0
3890 04:41:19.535565 WL = 0x2
3891 04:41:19.535646 RL = 0x2
3892 04:41:19.538904 BL = 0x2
3893 04:41:19.538985 RPST = 0x0
3894 04:41:19.541902 RD_PRE = 0x0
3895 04:41:19.542001 WR_PRE = 0x1
3896 04:41:19.545569 WR_PST = 0x0
3897 04:41:19.545672 DBI_WR = 0x0
3898 04:41:19.548534 DBI_RD = 0x0
3899 04:41:19.548615 OTF = 0x1
3900 04:41:19.551697 ===================================
3901 04:41:19.554909 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3902 04:41:19.561725 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3903 04:41:19.564812 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3904 04:41:19.568172 ===================================
3905 04:41:19.571272 LPDDR4 DRAM CONFIGURATION
3906 04:41:19.574762 ===================================
3907 04:41:19.577879 EX_ROW_EN[0] = 0x10
3908 04:41:19.577977 EX_ROW_EN[1] = 0x0
3909 04:41:19.581325 LP4Y_EN = 0x0
3910 04:41:19.581406 WORK_FSP = 0x0
3911 04:41:19.584749 WL = 0x2
3912 04:41:19.584832 RL = 0x2
3913 04:41:19.587712 BL = 0x2
3914 04:41:19.587794 RPST = 0x0
3915 04:41:19.591601 RD_PRE = 0x0
3916 04:41:19.591683 WR_PRE = 0x1
3917 04:41:19.594375 WR_PST = 0x0
3918 04:41:19.594473 DBI_WR = 0x0
3919 04:41:19.597702 DBI_RD = 0x0
3920 04:41:19.597784 OTF = 0x1
3921 04:41:19.600779 ===================================
3922 04:41:19.607864 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3923 04:41:19.612454 nWR fixed to 30
3924 04:41:19.615947 [ModeRegInit_LP4] CH0 RK0
3925 04:41:19.616028 [ModeRegInit_LP4] CH0 RK1
3926 04:41:19.619169 [ModeRegInit_LP4] CH1 RK0
3927 04:41:19.622278 [ModeRegInit_LP4] CH1 RK1
3928 04:41:19.622359 match AC timing 17
3929 04:41:19.628874 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3930 04:41:19.632644 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3931 04:41:19.635681 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3932 04:41:19.641966 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3933 04:41:19.645751 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3934 04:41:19.645836 ==
3935 04:41:19.648974 Dram Type= 6, Freq= 0, CH_0, rank 0
3936 04:41:19.651860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3937 04:41:19.651942 ==
3938 04:41:19.658949 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3939 04:41:19.665013 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3940 04:41:19.668385 [CA 0] Center 36 (6~67) winsize 62
3941 04:41:19.671684 [CA 1] Center 36 (5~67) winsize 63
3942 04:41:19.674800 [CA 2] Center 34 (4~65) winsize 62
3943 04:41:19.678283 [CA 3] Center 34 (4~65) winsize 62
3944 04:41:19.681573 [CA 4] Center 33 (3~64) winsize 62
3945 04:41:19.684810 [CA 5] Center 33 (3~64) winsize 62
3946 04:41:19.684898
3947 04:41:19.688274 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3948 04:41:19.688371
3949 04:41:19.691406 [CATrainingPosCal] consider 1 rank data
3950 04:41:19.694398 u2DelayCellTimex100 = 270/100 ps
3951 04:41:19.697934 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3952 04:41:19.701360 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3953 04:41:19.708019 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3954 04:41:19.711105 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3955 04:41:19.714432 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3956 04:41:19.717781 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3957 04:41:19.717862
3958 04:41:19.721030 CA PerBit enable=1, Macro0, CA PI delay=33
3959 04:41:19.721111
3960 04:41:19.724455 [CBTSetCACLKResult] CA Dly = 33
3961 04:41:19.724539 CS Dly: 4 (0~35)
3962 04:41:19.727350 ==
3963 04:41:19.727469 Dram Type= 6, Freq= 0, CH_0, rank 1
3964 04:41:19.733960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 04:41:19.734047 ==
3966 04:41:19.737482 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3967 04:41:19.744066 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3968 04:41:19.747671 [CA 0] Center 36 (6~67) winsize 62
3969 04:41:19.751168 [CA 1] Center 36 (6~67) winsize 62
3970 04:41:19.754387 [CA 2] Center 34 (4~65) winsize 62
3971 04:41:19.757883 [CA 3] Center 34 (4~65) winsize 62
3972 04:41:19.760962 [CA 4] Center 34 (3~65) winsize 63
3973 04:41:19.764151 [CA 5] Center 33 (3~64) winsize 62
3974 04:41:19.764232
3975 04:41:19.767504 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3976 04:41:19.767584
3977 04:41:19.770599 [CATrainingPosCal] consider 2 rank data
3978 04:41:19.774291 u2DelayCellTimex100 = 270/100 ps
3979 04:41:19.777635 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3980 04:41:19.784134 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3981 04:41:19.786939 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3982 04:41:19.790525 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3983 04:41:19.793627 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3984 04:41:19.796988 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3985 04:41:19.797069
3986 04:41:19.800049 CA PerBit enable=1, Macro0, CA PI delay=33
3987 04:41:19.800146
3988 04:41:19.804022 [CBTSetCACLKResult] CA Dly = 33
3989 04:41:19.806881 CS Dly: 5 (0~38)
3990 04:41:19.806961
3991 04:41:19.810478 ----->DramcWriteLeveling(PI) begin...
3992 04:41:19.810560 ==
3993 04:41:19.813463 Dram Type= 6, Freq= 0, CH_0, rank 0
3994 04:41:19.816838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 04:41:19.816919 ==
3996 04:41:19.820120 Write leveling (Byte 0): 32 => 32
3997 04:41:19.823901 Write leveling (Byte 1): 31 => 31
3998 04:41:19.826595 DramcWriteLeveling(PI) end<-----
3999 04:41:19.826675
4000 04:41:19.826739 ==
4001 04:41:19.829802 Dram Type= 6, Freq= 0, CH_0, rank 0
4002 04:41:19.833015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4003 04:41:19.833097 ==
4004 04:41:19.836898 [Gating] SW mode calibration
4005 04:41:19.842768 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4006 04:41:19.849601 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4007 04:41:19.852756 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4008 04:41:19.859551 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4009 04:41:19.862692 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4010 04:41:19.866358 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4011 04:41:19.873003 0 9 16 | B1->B0 | 2f2f 2929 | 1 1 | (1 1) (1 0)
4012 04:41:19.875972 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 04:41:19.879529 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 04:41:19.885937 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 04:41:19.889202 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 04:41:19.892624 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 04:41:19.899007 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 04:41:19.902170 0 10 12 | B1->B0 | 2525 3030 | 0 0 | (0 0) (0 0)
4019 04:41:19.905570 0 10 16 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
4020 04:41:19.911988 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 04:41:19.915838 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 04:41:19.919181 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 04:41:19.925362 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 04:41:19.928665 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 04:41:19.931880 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 04:41:19.938648 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 04:41:19.941773 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 04:41:19.944934 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 04:41:19.951406 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 04:41:19.954989 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 04:41:19.958845 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 04:41:19.964820 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 04:41:19.968168 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 04:41:19.970961 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 04:41:19.977752 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 04:41:19.980985 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 04:41:19.984282 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 04:41:19.990857 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 04:41:19.994539 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 04:41:19.998099 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 04:41:20.004259 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 04:41:20.007367 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4043 04:41:20.010621 Total UI for P1: 0, mck2ui 16
4044 04:41:20.013711 best dqsien dly found for B0: ( 0, 13, 10)
4045 04:41:20.017335 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 04:41:20.020318 Total UI for P1: 0, mck2ui 16
4047 04:41:20.023758 best dqsien dly found for B1: ( 0, 13, 14)
4048 04:41:20.027282 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4049 04:41:20.033464 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4050 04:41:20.033551
4051 04:41:20.036937 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4052 04:41:20.040073 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4053 04:41:20.043282 [Gating] SW calibration Done
4054 04:41:20.043443 ==
4055 04:41:20.047060 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 04:41:20.049766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 04:41:20.049850 ==
4058 04:41:20.053203 RX Vref Scan: 0
4059 04:41:20.053288
4060 04:41:20.053354 RX Vref 0 -> 0, step: 1
4061 04:41:20.053420
4062 04:41:20.056723 RX Delay -230 -> 252, step: 16
4063 04:41:20.059617 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4064 04:41:20.066599 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4065 04:41:20.069465 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4066 04:41:20.072894 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4067 04:41:20.076049 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4068 04:41:20.082756 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4069 04:41:20.086027 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4070 04:41:20.089105 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4071 04:41:20.092680 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4072 04:41:20.099184 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4073 04:41:20.102619 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4074 04:41:20.106438 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4075 04:41:20.109087 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4076 04:41:20.115632 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4077 04:41:20.119054 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4078 04:41:20.122226 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4079 04:41:20.122303 ==
4080 04:41:20.125639 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 04:41:20.129025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 04:41:20.129098 ==
4083 04:41:20.132279 DQS Delay:
4084 04:41:20.132353 DQS0 = 0, DQS1 = 0
4085 04:41:20.135400 DQM Delay:
4086 04:41:20.135472 DQM0 = 44, DQM1 = 36
4087 04:41:20.138810 DQ Delay:
4088 04:41:20.138882 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4089 04:41:20.141890 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4090 04:41:20.145582 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4091 04:41:20.148373 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4092 04:41:20.152173
4093 04:41:20.152251
4094 04:41:20.152314 ==
4095 04:41:20.155384 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 04:41:20.158467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 04:41:20.158541 ==
4098 04:41:20.158607
4099 04:41:20.158666
4100 04:41:20.161770 TX Vref Scan disable
4101 04:41:20.161839 == TX Byte 0 ==
4102 04:41:20.168214 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4103 04:41:20.171987 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4104 04:41:20.172066 == TX Byte 1 ==
4105 04:41:20.178170 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4106 04:41:20.181409 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4107 04:41:20.181494 ==
4108 04:41:20.185300 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 04:41:20.187996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 04:41:20.188070 ==
4111 04:41:20.188132
4112 04:41:20.188195
4113 04:41:20.191166 TX Vref Scan disable
4114 04:41:20.194919 == TX Byte 0 ==
4115 04:41:20.198107 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4116 04:41:20.204380 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4117 04:41:20.204456 == TX Byte 1 ==
4118 04:41:20.208127 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4119 04:41:20.214743 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4120 04:41:20.214822
4121 04:41:20.214886 [DATLAT]
4122 04:41:20.214946 Freq=600, CH0 RK0
4123 04:41:20.215009
4124 04:41:20.217868 DATLAT Default: 0x9
4125 04:41:20.220748 0, 0xFFFF, sum = 0
4126 04:41:20.220821 1, 0xFFFF, sum = 0
4127 04:41:20.224630 2, 0xFFFF, sum = 0
4128 04:41:20.224703 3, 0xFFFF, sum = 0
4129 04:41:20.227834 4, 0xFFFF, sum = 0
4130 04:41:20.227913 5, 0xFFFF, sum = 0
4131 04:41:20.230867 6, 0xFFFF, sum = 0
4132 04:41:20.230937 7, 0xFFFF, sum = 0
4133 04:41:20.234560 8, 0x0, sum = 1
4134 04:41:20.234632 9, 0x0, sum = 2
4135 04:41:20.237470 10, 0x0, sum = 3
4136 04:41:20.237545 11, 0x0, sum = 4
4137 04:41:20.237607 best_step = 9
4138 04:41:20.237665
4139 04:41:20.240939 ==
4140 04:41:20.241009 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 04:41:20.247675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 04:41:20.247751 ==
4143 04:41:20.247814 RX Vref Scan: 1
4144 04:41:20.247904
4145 04:41:20.250619 RX Vref 0 -> 0, step: 1
4146 04:41:20.250693
4147 04:41:20.254236 RX Delay -179 -> 252, step: 8
4148 04:41:20.254312
4149 04:41:20.257304 Set Vref, RX VrefLevel [Byte0]: 51
4150 04:41:20.260399 [Byte1]: 47
4151 04:41:20.260474
4152 04:41:20.264229 Final RX Vref Byte 0 = 51 to rank0
4153 04:41:20.267322 Final RX Vref Byte 1 = 47 to rank0
4154 04:41:20.270531 Final RX Vref Byte 0 = 51 to rank1
4155 04:41:20.273850 Final RX Vref Byte 1 = 47 to rank1==
4156 04:41:20.277149 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 04:41:20.280592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 04:41:20.283489 ==
4159 04:41:20.283571 DQS Delay:
4160 04:41:20.283635 DQS0 = 0, DQS1 = 0
4161 04:41:20.287170 DQM Delay:
4162 04:41:20.287294 DQM0 = 41, DQM1 = 34
4163 04:41:20.290079 DQ Delay:
4164 04:41:20.293448 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4165 04:41:20.293529 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4166 04:41:20.296907 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =32
4167 04:41:20.300047 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4168 04:41:20.303876
4169 04:41:20.303957
4170 04:41:20.309813 [DQSOSCAuto] RK0, (LSB)MR18= 0x473f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4171 04:41:20.313157 CH0 RK0: MR19=808, MR18=473F
4172 04:41:20.319960 CH0_RK0: MR19=0x808, MR18=0x473F, DQSOSC=396, MR23=63, INC=167, DEC=111
4173 04:41:20.320042
4174 04:41:20.323375 ----->DramcWriteLeveling(PI) begin...
4175 04:41:20.323480 ==
4176 04:41:20.327053 Dram Type= 6, Freq= 0, CH_0, rank 1
4177 04:41:20.329938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 04:41:20.330020 ==
4179 04:41:20.333147 Write leveling (Byte 0): 34 => 34
4180 04:41:20.336420 Write leveling (Byte 1): 29 => 29
4181 04:41:20.339514 DramcWriteLeveling(PI) end<-----
4182 04:41:20.339595
4183 04:41:20.339661 ==
4184 04:41:20.342999 Dram Type= 6, Freq= 0, CH_0, rank 1
4185 04:41:20.346536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 04:41:20.346616 ==
4187 04:41:20.349493 [Gating] SW mode calibration
4188 04:41:20.356825 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4189 04:41:20.362782 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4190 04:41:20.366110 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4191 04:41:20.372850 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4192 04:41:20.375990 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4193 04:41:20.379100 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4194 04:41:20.386554 0 9 16 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (1 1)
4195 04:41:20.388926 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 04:41:20.392209 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 04:41:20.398873 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 04:41:20.402317 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 04:41:20.405836 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 04:41:20.412065 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 04:41:20.415334 0 10 12 | B1->B0 | 2929 3434 | 0 0 | (0 0) (0 0)
4202 04:41:20.418758 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4203 04:41:20.425253 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 04:41:20.428600 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 04:41:20.432132 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 04:41:20.438251 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 04:41:20.441468 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 04:41:20.445101 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 04:41:20.452263 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4210 04:41:20.454612 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4211 04:41:20.458453 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 04:41:20.465002 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 04:41:20.468123 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 04:41:20.471581 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 04:41:20.478952 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 04:41:20.481549 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 04:41:20.484671 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 04:41:20.491067 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 04:41:20.494166 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 04:41:20.497677 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 04:41:20.504181 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 04:41:20.507762 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 04:41:20.510975 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 04:41:20.517242 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 04:41:20.520686 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4226 04:41:20.524051 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 04:41:20.527283 Total UI for P1: 0, mck2ui 16
4228 04:41:20.530687 best dqsien dly found for B0: ( 0, 13, 12)
4229 04:41:20.533713 Total UI for P1: 0, mck2ui 16
4230 04:41:20.537063 best dqsien dly found for B1: ( 0, 13, 12)
4231 04:41:20.540718 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4232 04:41:20.547150 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4233 04:41:20.547267
4234 04:41:20.550199 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4235 04:41:20.553403 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4236 04:41:20.556679 [Gating] SW calibration Done
4237 04:41:20.556761 ==
4238 04:41:20.559908 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 04:41:20.563581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 04:41:20.563664 ==
4241 04:41:20.566489 RX Vref Scan: 0
4242 04:41:20.566565
4243 04:41:20.566632 RX Vref 0 -> 0, step: 1
4244 04:41:20.566691
4245 04:41:20.570024 RX Delay -230 -> 252, step: 16
4246 04:41:20.573429 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4247 04:41:20.580303 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4248 04:41:20.583424 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4249 04:41:20.586712 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4250 04:41:20.589735 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4251 04:41:20.596541 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4252 04:41:20.599578 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4253 04:41:20.603104 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4254 04:41:20.606557 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4255 04:41:20.609895 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4256 04:41:20.616551 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4257 04:41:20.619484 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4258 04:41:20.622932 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4259 04:41:20.626182 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4260 04:41:20.632507 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4261 04:41:20.636030 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4262 04:41:20.636100 ==
4263 04:41:20.639282 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 04:41:20.643005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 04:41:20.643081 ==
4266 04:41:20.646115 DQS Delay:
4267 04:41:20.646188 DQS0 = 0, DQS1 = 0
4268 04:41:20.648986 DQM Delay:
4269 04:41:20.649060 DQM0 = 42, DQM1 = 34
4270 04:41:20.649122 DQ Delay:
4271 04:41:20.652490 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4272 04:41:20.656096 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4273 04:41:20.659518 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
4274 04:41:20.662528 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4275 04:41:20.662594
4276 04:41:20.662654
4277 04:41:20.665582 ==
4278 04:41:20.669250 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 04:41:20.672464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 04:41:20.672634 ==
4281 04:41:20.672710
4282 04:41:20.672769
4283 04:41:20.675645 TX Vref Scan disable
4284 04:41:20.675771 == TX Byte 0 ==
4285 04:41:20.682316 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4286 04:41:20.685652 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4287 04:41:20.685774 == TX Byte 1 ==
4288 04:41:20.692941 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4289 04:41:20.695824 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4290 04:41:20.695928 ==
4291 04:41:20.698882 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 04:41:20.702247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 04:41:20.702332 ==
4294 04:41:20.702396
4295 04:41:20.702456
4296 04:41:20.705134 TX Vref Scan disable
4297 04:41:20.708736 == TX Byte 0 ==
4298 04:41:20.711677 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4299 04:41:20.718261 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4300 04:41:20.718393 == TX Byte 1 ==
4301 04:41:20.721233 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4302 04:41:20.727866 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4303 04:41:20.727944
4304 04:41:20.728006 [DATLAT]
4305 04:41:20.728065 Freq=600, CH0 RK1
4306 04:41:20.728129
4307 04:41:20.731234 DATLAT Default: 0x9
4308 04:41:20.734705 0, 0xFFFF, sum = 0
4309 04:41:20.734785 1, 0xFFFF, sum = 0
4310 04:41:20.737912 2, 0xFFFF, sum = 0
4311 04:41:20.737985 3, 0xFFFF, sum = 0
4312 04:41:20.741079 4, 0xFFFF, sum = 0
4313 04:41:20.741162 5, 0xFFFF, sum = 0
4314 04:41:20.744478 6, 0xFFFF, sum = 0
4315 04:41:20.744587 7, 0xFFFF, sum = 0
4316 04:41:20.748069 8, 0x0, sum = 1
4317 04:41:20.748146 9, 0x0, sum = 2
4318 04:41:20.751051 10, 0x0, sum = 3
4319 04:41:20.751131 11, 0x0, sum = 4
4320 04:41:20.751195 best_step = 9
4321 04:41:20.751256
4322 04:41:20.754110 ==
4323 04:41:20.757379 Dram Type= 6, Freq= 0, CH_0, rank 1
4324 04:41:20.760696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4325 04:41:20.760769 ==
4326 04:41:20.760830 RX Vref Scan: 0
4327 04:41:20.760894
4328 04:41:20.764065 RX Vref 0 -> 0, step: 1
4329 04:41:20.764137
4330 04:41:20.767601 RX Delay -195 -> 252, step: 8
4331 04:41:20.774099 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4332 04:41:20.777293 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4333 04:41:20.780800 iDelay=197, Bit 2, Center 40 (-107 ~ 188) 296
4334 04:41:20.783945 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4335 04:41:20.790995 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4336 04:41:20.794152 iDelay=197, Bit 5, Center 32 (-115 ~ 180) 296
4337 04:41:20.797825 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4338 04:41:20.800220 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4339 04:41:20.804054 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4340 04:41:20.810471 iDelay=197, Bit 9, Center 20 (-131 ~ 172) 304
4341 04:41:20.813509 iDelay=197, Bit 10, Center 36 (-115 ~ 188) 304
4342 04:41:20.816663 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4343 04:41:20.820144 iDelay=197, Bit 12, Center 36 (-115 ~ 188) 304
4344 04:41:20.827212 iDelay=197, Bit 13, Center 40 (-107 ~ 188) 296
4345 04:41:20.829862 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4346 04:41:20.833616 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4347 04:41:20.833687 ==
4348 04:41:20.836404 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 04:41:20.840558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 04:41:20.843264 ==
4351 04:41:20.843393 DQS Delay:
4352 04:41:20.843472 DQS0 = 0, DQS1 = 0
4353 04:41:20.846976 DQM Delay:
4354 04:41:20.847046 DQM0 = 42, DQM1 = 33
4355 04:41:20.850081 DQ Delay:
4356 04:41:20.853492 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4357 04:41:20.853571 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4358 04:41:20.856309 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4359 04:41:20.862773 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4360 04:41:20.862851
4361 04:41:20.862929
4362 04:41:20.869882 [DQSOSCAuto] RK1, (LSB)MR18= 0x443e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4363 04:41:20.872717 CH0 RK1: MR19=808, MR18=443E
4364 04:41:20.879856 CH0_RK1: MR19=0x808, MR18=0x443E, DQSOSC=396, MR23=63, INC=167, DEC=111
4365 04:41:20.882821 [RxdqsGatingPostProcess] freq 600
4366 04:41:20.886273 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4367 04:41:20.889981 Pre-setting of DQS Precalculation
4368 04:41:20.895645 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4369 04:41:20.895724 ==
4370 04:41:20.899424 Dram Type= 6, Freq= 0, CH_1, rank 0
4371 04:41:20.902453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 04:41:20.902534 ==
4373 04:41:20.909123 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4374 04:41:20.916154 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4375 04:41:20.918906 [CA 0] Center 36 (6~66) winsize 61
4376 04:41:20.922128 [CA 1] Center 35 (5~66) winsize 62
4377 04:41:20.925842 [CA 2] Center 34 (4~65) winsize 62
4378 04:41:20.929485 [CA 3] Center 34 (3~65) winsize 63
4379 04:41:20.932485 [CA 4] Center 34 (4~65) winsize 62
4380 04:41:20.935594 [CA 5] Center 34 (3~65) winsize 63
4381 04:41:20.935675
4382 04:41:20.938943 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4383 04:41:20.939024
4384 04:41:20.942062 [CATrainingPosCal] consider 1 rank data
4385 04:41:20.946072 u2DelayCellTimex100 = 270/100 ps
4386 04:41:20.948976 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4387 04:41:20.952190 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4388 04:41:20.955368 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4389 04:41:20.958565 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4390 04:41:20.962499 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4391 04:41:20.965316 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4392 04:41:20.965421
4393 04:41:20.971997 CA PerBit enable=1, Macro0, CA PI delay=34
4394 04:41:20.972078
4395 04:41:20.972142 [CBTSetCACLKResult] CA Dly = 34
4396 04:41:20.975299 CS Dly: 4 (0~35)
4397 04:41:20.975437 ==
4398 04:41:20.978273 Dram Type= 6, Freq= 0, CH_1, rank 1
4399 04:41:20.981616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 04:41:20.981698 ==
4401 04:41:20.988581 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4402 04:41:20.995100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4403 04:41:20.998285 [CA 0] Center 35 (5~66) winsize 62
4404 04:41:21.001169 [CA 1] Center 36 (6~66) winsize 61
4405 04:41:21.004523 [CA 2] Center 34 (4~65) winsize 62
4406 04:41:21.008138 [CA 3] Center 33 (3~64) winsize 62
4407 04:41:21.010891 [CA 4] Center 34 (3~65) winsize 63
4408 04:41:21.014658 [CA 5] Center 33 (3~64) winsize 62
4409 04:41:21.014738
4410 04:41:21.017901 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4411 04:41:21.017981
4412 04:41:21.021382 [CATrainingPosCal] consider 2 rank data
4413 04:41:21.024476 u2DelayCellTimex100 = 270/100 ps
4414 04:41:21.027783 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4415 04:41:21.030726 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4416 04:41:21.034427 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4417 04:41:21.040802 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4418 04:41:21.044358 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4419 04:41:21.047620 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4420 04:41:21.047706
4421 04:41:21.050562 CA PerBit enable=1, Macro0, CA PI delay=33
4422 04:41:21.050643
4423 04:41:21.054045 [CBTSetCACLKResult] CA Dly = 33
4424 04:41:21.054138 CS Dly: 5 (0~37)
4425 04:41:21.054204
4426 04:41:21.057016 ----->DramcWriteLeveling(PI) begin...
4427 04:41:21.060315 ==
4428 04:41:21.060397 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 04:41:21.067344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 04:41:21.067468 ==
4431 04:41:21.070658 Write leveling (Byte 0): 29 => 29
4432 04:41:21.073756 Write leveling (Byte 1): 29 => 29
4433 04:41:21.076798 DramcWriteLeveling(PI) end<-----
4434 04:41:21.076878
4435 04:41:21.076941 ==
4436 04:41:21.080295 Dram Type= 6, Freq= 0, CH_1, rank 0
4437 04:41:21.083753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4438 04:41:21.083834 ==
4439 04:41:21.086719 [Gating] SW mode calibration
4440 04:41:21.093449 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4441 04:41:21.099934 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4442 04:41:21.103136 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4443 04:41:21.106721 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4444 04:41:21.113451 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4445 04:41:21.116361 0 9 12 | B1->B0 | 2e2e 2f2f | 1 1 | (1 1) (1 0)
4446 04:41:21.119918 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 04:41:21.126314 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 04:41:21.129345 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 04:41:21.132892 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 04:41:21.139381 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 04:41:21.142433 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 04:41:21.145738 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 04:41:21.152427 0 10 12 | B1->B0 | 2b2b 3535 | 0 0 | (0 0) (1 1)
4454 04:41:21.155679 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 04:41:21.159063 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 04:41:21.165767 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 04:41:21.168655 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 04:41:21.172200 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 04:41:21.178846 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 04:41:21.182075 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 04:41:21.185102 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4462 04:41:21.191822 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 04:41:21.194993 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 04:41:21.198618 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 04:41:21.205031 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 04:41:21.208472 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 04:41:21.211971 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 04:41:21.218774 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 04:41:21.221453 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 04:41:21.225162 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 04:41:21.231550 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 04:41:21.234898 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 04:41:21.238415 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 04:41:21.244781 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 04:41:21.248275 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 04:41:21.251148 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 04:41:21.258083 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4478 04:41:21.258165 Total UI for P1: 0, mck2ui 16
4479 04:41:21.264816 best dqsien dly found for B0: ( 0, 13, 10)
4480 04:41:21.267692 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 04:41:21.270940 Total UI for P1: 0, mck2ui 16
4482 04:41:21.274222 best dqsien dly found for B1: ( 0, 13, 12)
4483 04:41:21.277314 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4484 04:41:21.280548 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4485 04:41:21.280629
4486 04:41:21.283809 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4487 04:41:21.290647 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4488 04:41:21.290729 [Gating] SW calibration Done
4489 04:41:21.290794 ==
4490 04:41:21.294089 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 04:41:21.300282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 04:41:21.300363 ==
4493 04:41:21.300427 RX Vref Scan: 0
4494 04:41:21.300487
4495 04:41:21.304073 RX Vref 0 -> 0, step: 1
4496 04:41:21.304153
4497 04:41:21.306834 RX Delay -230 -> 252, step: 16
4498 04:41:21.310071 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4499 04:41:21.313615 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4500 04:41:21.319910 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4501 04:41:21.323635 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4502 04:41:21.326922 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4503 04:41:21.330481 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4504 04:41:21.333125 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4505 04:41:21.339635 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4506 04:41:21.343329 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4507 04:41:21.346545 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4508 04:41:21.349796 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4509 04:41:21.356469 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4510 04:41:21.359660 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4511 04:41:21.362991 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4512 04:41:21.366007 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4513 04:41:21.372654 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4514 04:41:21.372731 ==
4515 04:41:21.376344 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 04:41:21.379198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 04:41:21.379268 ==
4518 04:41:21.379329 DQS Delay:
4519 04:41:21.382659 DQS0 = 0, DQS1 = 0
4520 04:41:21.382725 DQM Delay:
4521 04:41:21.386150 DQM0 = 43, DQM1 = 38
4522 04:41:21.386250 DQ Delay:
4523 04:41:21.389550 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4524 04:41:21.392510 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4525 04:41:21.395742 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4526 04:41:21.399083 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4527 04:41:21.399165
4528 04:41:21.399229
4529 04:41:21.399287 ==
4530 04:41:21.402551 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 04:41:21.408952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 04:41:21.409034 ==
4533 04:41:21.409097
4534 04:41:21.409156
4535 04:41:21.409213 TX Vref Scan disable
4536 04:41:21.412116 == TX Byte 0 ==
4537 04:41:21.415601 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4538 04:41:21.422421 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4539 04:41:21.422502 == TX Byte 1 ==
4540 04:41:21.425334 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4541 04:41:21.432225 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4542 04:41:21.432344 ==
4543 04:41:21.435141 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 04:41:21.438988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 04:41:21.439069 ==
4546 04:41:21.439133
4547 04:41:21.439193
4548 04:41:21.442169 TX Vref Scan disable
4549 04:41:21.445289 == TX Byte 0 ==
4550 04:41:21.448389 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4551 04:41:21.451908 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4552 04:41:21.454876 == TX Byte 1 ==
4553 04:41:21.458274 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4554 04:41:21.461572 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4555 04:41:21.461653
4556 04:41:21.465070 [DATLAT]
4557 04:41:21.465151 Freq=600, CH1 RK0
4558 04:41:21.465215
4559 04:41:21.468071 DATLAT Default: 0x9
4560 04:41:21.468152 0, 0xFFFF, sum = 0
4561 04:41:21.471614 1, 0xFFFF, sum = 0
4562 04:41:21.471696 2, 0xFFFF, sum = 0
4563 04:41:21.474803 3, 0xFFFF, sum = 0
4564 04:41:21.474885 4, 0xFFFF, sum = 0
4565 04:41:21.478088 5, 0xFFFF, sum = 0
4566 04:41:21.478171 6, 0xFFFF, sum = 0
4567 04:41:21.481064 7, 0xFFFF, sum = 0
4568 04:41:21.481145 8, 0x0, sum = 1
4569 04:41:21.484580 9, 0x0, sum = 2
4570 04:41:21.484663 10, 0x0, sum = 3
4571 04:41:21.487686 11, 0x0, sum = 4
4572 04:41:21.487768 best_step = 9
4573 04:41:21.487832
4574 04:41:21.487891 ==
4575 04:41:21.491421 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 04:41:21.494493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 04:41:21.497535 ==
4578 04:41:21.497616 RX Vref Scan: 1
4579 04:41:21.497681
4580 04:41:21.501017 RX Vref 0 -> 0, step: 1
4581 04:41:21.501097
4582 04:41:21.504194 RX Delay -179 -> 252, step: 8
4583 04:41:21.504274
4584 04:41:21.507671 Set Vref, RX VrefLevel [Byte0]: 54
4585 04:41:21.510697 [Byte1]: 53
4586 04:41:21.510778
4587 04:41:21.514156 Final RX Vref Byte 0 = 54 to rank0
4588 04:41:21.517131 Final RX Vref Byte 1 = 53 to rank0
4589 04:41:21.520570 Final RX Vref Byte 0 = 54 to rank1
4590 04:41:21.523841 Final RX Vref Byte 1 = 53 to rank1==
4591 04:41:21.527574 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 04:41:21.530259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 04:41:21.530341 ==
4594 04:41:21.533647 DQS Delay:
4595 04:41:21.533728 DQS0 = 0, DQS1 = 0
4596 04:41:21.533791 DQM Delay:
4597 04:41:21.537410 DQM0 = 40, DQM1 = 34
4598 04:41:21.537491 DQ Delay:
4599 04:41:21.540147 DQ0 =48, DQ1 =36, DQ2 =28, DQ3 =40
4600 04:41:21.543776 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4601 04:41:21.547056 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4602 04:41:21.550374 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4603 04:41:21.550454
4604 04:41:21.550518
4605 04:41:21.560492 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a44, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4606 04:41:21.563403 CH1 RK0: MR19=808, MR18=2A44
4607 04:41:21.567016 CH1_RK0: MR19=0x808, MR18=0x2A44, DQSOSC=396, MR23=63, INC=167, DEC=111
4608 04:41:21.569918
4609 04:41:21.573557 ----->DramcWriteLeveling(PI) begin...
4610 04:41:21.573639 ==
4611 04:41:21.577025 Dram Type= 6, Freq= 0, CH_1, rank 1
4612 04:41:21.580158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 04:41:21.580240 ==
4614 04:41:21.583266 Write leveling (Byte 0): 29 => 29
4615 04:41:21.586815 Write leveling (Byte 1): 31 => 31
4616 04:41:21.589699 DramcWriteLeveling(PI) end<-----
4617 04:41:21.589810
4618 04:41:21.589878 ==
4619 04:41:21.593225 Dram Type= 6, Freq= 0, CH_1, rank 1
4620 04:41:21.596622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 04:41:21.596705 ==
4622 04:41:21.599921 [Gating] SW mode calibration
4623 04:41:21.606548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4624 04:41:21.613368 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4625 04:41:21.616258 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4626 04:41:21.619813 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4627 04:41:21.626778 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4628 04:41:21.629656 0 9 12 | B1->B0 | 3333 2d2d | 0 0 | (0 1) (1 1)
4629 04:41:21.633140 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 04:41:21.639592 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 04:41:21.642662 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 04:41:21.646434 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 04:41:21.652554 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 04:41:21.656231 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 04:41:21.659326 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4636 04:41:21.665736 0 10 12 | B1->B0 | 2f2f 3c3c | 0 0 | (0 0) (0 0)
4637 04:41:21.669438 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
4638 04:41:21.672634 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 04:41:21.679309 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 04:41:21.682101 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 04:41:21.685756 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 04:41:21.692111 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 04:41:21.695798 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 04:41:21.698817 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 04:41:21.705353 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 04:41:21.708782 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 04:41:21.712281 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 04:41:21.718992 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 04:41:21.722226 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 04:41:21.725631 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 04:41:21.731648 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 04:41:21.735111 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 04:41:21.738703 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 04:41:21.744988 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 04:41:21.748045 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 04:41:21.751370 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 04:41:21.757934 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 04:41:21.761543 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 04:41:21.765042 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 04:41:21.771244 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4661 04:41:21.774464 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 04:41:21.777862 Total UI for P1: 0, mck2ui 16
4663 04:41:21.781266 best dqsien dly found for B0: ( 0, 13, 12)
4664 04:41:21.784928 Total UI for P1: 0, mck2ui 16
4665 04:41:21.788116 best dqsien dly found for B1: ( 0, 13, 14)
4666 04:41:21.790991 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4667 04:41:21.794363 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4668 04:41:21.794447
4669 04:41:21.797852 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4670 04:41:21.801169 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4671 04:41:21.804492 [Gating] SW calibration Done
4672 04:41:21.804575 ==
4673 04:41:21.807937 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 04:41:21.814174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 04:41:21.814257 ==
4676 04:41:21.814323 RX Vref Scan: 0
4677 04:41:21.814384
4678 04:41:21.818099 RX Vref 0 -> 0, step: 1
4679 04:41:21.818181
4680 04:41:21.820604 RX Delay -230 -> 252, step: 16
4681 04:41:21.824064 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4682 04:41:21.827615 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4683 04:41:21.830777 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4684 04:41:21.836983 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4685 04:41:21.840421 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4686 04:41:21.844048 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4687 04:41:21.847325 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4688 04:41:21.853524 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4689 04:41:21.856886 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4690 04:41:21.860070 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4691 04:41:21.863506 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4692 04:41:21.870089 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4693 04:41:21.873416 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4694 04:41:21.876842 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4695 04:41:21.879842 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4696 04:41:21.886615 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4697 04:41:21.886702 ==
4698 04:41:21.889755 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 04:41:21.893128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 04:41:21.893212 ==
4701 04:41:21.893277 DQS Delay:
4702 04:41:21.896441 DQS0 = 0, DQS1 = 0
4703 04:41:21.896524 DQM Delay:
4704 04:41:21.899691 DQM0 = 43, DQM1 = 39
4705 04:41:21.899774 DQ Delay:
4706 04:41:21.902987 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4707 04:41:21.906264 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4708 04:41:21.909672 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4709 04:41:21.912923 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4710 04:41:21.913006
4711 04:41:21.913081
4712 04:41:21.913146 ==
4713 04:41:21.915879 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 04:41:21.919140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 04:41:21.922958 ==
4716 04:41:21.923038
4717 04:41:21.923128
4718 04:41:21.923231 TX Vref Scan disable
4719 04:41:21.925787 == TX Byte 0 ==
4720 04:41:21.929454 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4721 04:41:21.932971 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4722 04:41:21.935759 == TX Byte 1 ==
4723 04:41:21.939356 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4724 04:41:21.942310 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4725 04:41:21.945508 ==
4726 04:41:21.949037 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 04:41:21.952248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 04:41:21.952376 ==
4729 04:41:21.952443
4730 04:41:21.952503
4731 04:41:21.955778 TX Vref Scan disable
4732 04:41:21.958629 == TX Byte 0 ==
4733 04:41:21.961943 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4734 04:41:21.965320 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4735 04:41:21.968941 == TX Byte 1 ==
4736 04:41:21.972415 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4737 04:41:21.975697 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4738 04:41:21.975777
4739 04:41:21.975841 [DATLAT]
4740 04:41:21.978529 Freq=600, CH1 RK1
4741 04:41:21.978609
4742 04:41:21.981691 DATLAT Default: 0x9
4743 04:41:21.981772 0, 0xFFFF, sum = 0
4744 04:41:21.985135 1, 0xFFFF, sum = 0
4745 04:41:21.985217 2, 0xFFFF, sum = 0
4746 04:41:21.988481 3, 0xFFFF, sum = 0
4747 04:41:21.988563 4, 0xFFFF, sum = 0
4748 04:41:21.991888 5, 0xFFFF, sum = 0
4749 04:41:21.991970 6, 0xFFFF, sum = 0
4750 04:41:21.994775 7, 0xFFFF, sum = 0
4751 04:41:21.994857 8, 0x0, sum = 1
4752 04:41:21.998187 9, 0x0, sum = 2
4753 04:41:21.998269 10, 0x0, sum = 3
4754 04:41:22.001637 11, 0x0, sum = 4
4755 04:41:22.001719 best_step = 9
4756 04:41:22.001783
4757 04:41:22.001842 ==
4758 04:41:22.005156 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 04:41:22.008063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 04:41:22.008145 ==
4761 04:41:22.011671 RX Vref Scan: 0
4762 04:41:22.011762
4763 04:41:22.015098 RX Vref 0 -> 0, step: 1
4764 04:41:22.015204
4765 04:41:22.015305 RX Delay -179 -> 252, step: 8
4766 04:41:22.022988 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4767 04:41:22.025993 iDelay=205, Bit 1, Center 32 (-131 ~ 196) 328
4768 04:41:22.029211 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4769 04:41:22.032667 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4770 04:41:22.039073 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4771 04:41:22.042508 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4772 04:41:22.045780 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4773 04:41:22.049892 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4774 04:41:22.056001 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4775 04:41:22.058902 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4776 04:41:22.062405 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4777 04:41:22.065459 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4778 04:41:22.071995 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4779 04:41:22.075715 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4780 04:41:22.078913 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4781 04:41:22.082061 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4782 04:41:22.082142 ==
4783 04:41:22.085777 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 04:41:22.092319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 04:41:22.092403 ==
4786 04:41:22.092467 DQS Delay:
4787 04:41:22.095640 DQS0 = 0, DQS1 = 0
4788 04:41:22.095721 DQM Delay:
4789 04:41:22.095785 DQM0 = 37, DQM1 = 36
4790 04:41:22.098702 DQ Delay:
4791 04:41:22.102265 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4792 04:41:22.105136 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4793 04:41:22.108573 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4794 04:41:22.111552 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4795 04:41:22.111632
4796 04:41:22.111696
4797 04:41:22.118453 [DQSOSCAuto] RK1, (LSB)MR18= 0x3257, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4798 04:41:22.121679 CH1 RK1: MR19=808, MR18=3257
4799 04:41:22.128740 CH1_RK1: MR19=0x808, MR18=0x3257, DQSOSC=393, MR23=63, INC=169, DEC=113
4800 04:41:22.131890 [RxdqsGatingPostProcess] freq 600
4801 04:41:22.135050 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4802 04:41:22.138225 Pre-setting of DQS Precalculation
4803 04:41:22.144672 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4804 04:41:22.151544 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4805 04:41:22.158026 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4806 04:41:22.158108
4807 04:41:22.158172
4808 04:41:22.161259 [Calibration Summary] 1200 Mbps
4809 04:41:22.165066 CH 0, Rank 0
4810 04:41:22.165147 SW Impedance : PASS
4811 04:41:22.168016 DUTY Scan : NO K
4812 04:41:22.168097 ZQ Calibration : PASS
4813 04:41:22.171292 Jitter Meter : NO K
4814 04:41:22.175022 CBT Training : PASS
4815 04:41:22.175135 Write leveling : PASS
4816 04:41:22.177723 RX DQS gating : PASS
4817 04:41:22.181137 RX DQ/DQS(RDDQC) : PASS
4818 04:41:22.181217 TX DQ/DQS : PASS
4819 04:41:22.184436 RX DATLAT : PASS
4820 04:41:22.187926 RX DQ/DQS(Engine): PASS
4821 04:41:22.188007 TX OE : NO K
4822 04:41:22.191297 All Pass.
4823 04:41:22.191428
4824 04:41:22.191493 CH 0, Rank 1
4825 04:41:22.194655 SW Impedance : PASS
4826 04:41:22.194736 DUTY Scan : NO K
4827 04:41:22.197714 ZQ Calibration : PASS
4828 04:41:22.201256 Jitter Meter : NO K
4829 04:41:22.201350 CBT Training : PASS
4830 04:41:22.204107 Write leveling : PASS
4831 04:41:22.207311 RX DQS gating : PASS
4832 04:41:22.207440 RX DQ/DQS(RDDQC) : PASS
4833 04:41:22.210774 TX DQ/DQS : PASS
4834 04:41:22.214022 RX DATLAT : PASS
4835 04:41:22.214103 RX DQ/DQS(Engine): PASS
4836 04:41:22.217994 TX OE : NO K
4837 04:41:22.218075 All Pass.
4838 04:41:22.218140
4839 04:41:22.220860 CH 1, Rank 0
4840 04:41:22.220969 SW Impedance : PASS
4841 04:41:22.223820 DUTY Scan : NO K
4842 04:41:22.227121 ZQ Calibration : PASS
4843 04:41:22.227217 Jitter Meter : NO K
4844 04:41:22.230612 CBT Training : PASS
4845 04:41:22.233891 Write leveling : PASS
4846 04:41:22.233973 RX DQS gating : PASS
4847 04:41:22.237409 RX DQ/DQS(RDDQC) : PASS
4848 04:41:22.237491 TX DQ/DQS : PASS
4849 04:41:22.240981 RX DATLAT : PASS
4850 04:41:22.243714 RX DQ/DQS(Engine): PASS
4851 04:41:22.243794 TX OE : NO K
4852 04:41:22.247200 All Pass.
4853 04:41:22.247281
4854 04:41:22.247344 CH 1, Rank 1
4855 04:41:22.250313 SW Impedance : PASS
4856 04:41:22.250394 DUTY Scan : NO K
4857 04:41:22.254277 ZQ Calibration : PASS
4858 04:41:22.256811 Jitter Meter : NO K
4859 04:41:22.256893 CBT Training : PASS
4860 04:41:22.260432 Write leveling : PASS
4861 04:41:22.263309 RX DQS gating : PASS
4862 04:41:22.263442 RX DQ/DQS(RDDQC) : PASS
4863 04:41:22.267001 TX DQ/DQS : PASS
4864 04:41:22.270379 RX DATLAT : PASS
4865 04:41:22.270460 RX DQ/DQS(Engine): PASS
4866 04:41:22.273467 TX OE : NO K
4867 04:41:22.273578 All Pass.
4868 04:41:22.273647
4869 04:41:22.277093 DramC Write-DBI off
4870 04:41:22.280301 PER_BANK_REFRESH: Hybrid Mode
4871 04:41:22.280382 TX_TRACKING: ON
4872 04:41:22.289902 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4873 04:41:22.293209 [FAST_K] Save calibration result to emmc
4874 04:41:22.296755 dramc_set_vcore_voltage set vcore to 662500
4875 04:41:22.299795 Read voltage for 933, 3
4876 04:41:22.299907 Vio18 = 0
4877 04:41:22.300035 Vcore = 662500
4878 04:41:22.303006 Vdram = 0
4879 04:41:22.303139 Vddq = 0
4880 04:41:22.303232 Vmddr = 0
4881 04:41:22.309737 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4882 04:41:22.312881 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4883 04:41:22.316628 MEM_TYPE=3, freq_sel=17
4884 04:41:22.319868 sv_algorithm_assistance_LP4_1600
4885 04:41:22.323133 ============ PULL DRAM RESETB DOWN ============
4886 04:41:22.329124 ========== PULL DRAM RESETB DOWN end =========
4887 04:41:22.333007 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4888 04:41:22.336099 ===================================
4889 04:41:22.339212 LPDDR4 DRAM CONFIGURATION
4890 04:41:22.342304 ===================================
4891 04:41:22.342400 EX_ROW_EN[0] = 0x0
4892 04:41:22.345837 EX_ROW_EN[1] = 0x0
4893 04:41:22.345918 LP4Y_EN = 0x0
4894 04:41:22.349321 WORK_FSP = 0x0
4895 04:41:22.349402 WL = 0x3
4896 04:41:22.352708 RL = 0x3
4897 04:41:22.352834 BL = 0x2
4898 04:41:22.356021 RPST = 0x0
4899 04:41:22.359221 RD_PRE = 0x0
4900 04:41:22.359303 WR_PRE = 0x1
4901 04:41:22.362383 WR_PST = 0x0
4902 04:41:22.362464 DBI_WR = 0x0
4903 04:41:22.365949 DBI_RD = 0x0
4904 04:41:22.366030 OTF = 0x1
4905 04:41:22.368805 ===================================
4906 04:41:22.372348 ===================================
4907 04:41:22.375494 ANA top config
4908 04:41:22.378950 ===================================
4909 04:41:22.379047 DLL_ASYNC_EN = 0
4910 04:41:22.382091 ALL_SLAVE_EN = 1
4911 04:41:22.385534 NEW_RANK_MODE = 1
4912 04:41:22.389107 DLL_IDLE_MODE = 1
4913 04:41:22.389188 LP45_APHY_COMB_EN = 1
4914 04:41:22.391974 TX_ODT_DIS = 1
4915 04:41:22.395079 NEW_8X_MODE = 1
4916 04:41:22.398458 ===================================
4917 04:41:22.402341 ===================================
4918 04:41:22.405060 data_rate = 1866
4919 04:41:22.408480 CKR = 1
4920 04:41:22.411649 DQ_P2S_RATIO = 8
4921 04:41:22.415064 ===================================
4922 04:41:22.415145 CA_P2S_RATIO = 8
4923 04:41:22.418560 DQ_CA_OPEN = 0
4924 04:41:22.421764 DQ_SEMI_OPEN = 0
4925 04:41:22.425518 CA_SEMI_OPEN = 0
4926 04:41:22.428175 CA_FULL_RATE = 0
4927 04:41:22.431713 DQ_CKDIV4_EN = 1
4928 04:41:22.431794 CA_CKDIV4_EN = 1
4929 04:41:22.434513 CA_PREDIV_EN = 0
4930 04:41:22.437927 PH8_DLY = 0
4931 04:41:22.441444 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4932 04:41:22.444727 DQ_AAMCK_DIV = 4
4933 04:41:22.447801 CA_AAMCK_DIV = 4
4934 04:41:22.451775 CA_ADMCK_DIV = 4
4935 04:41:22.451857 DQ_TRACK_CA_EN = 0
4936 04:41:22.454863 CA_PICK = 933
4937 04:41:22.457634 CA_MCKIO = 933
4938 04:41:22.461323 MCKIO_SEMI = 0
4939 04:41:22.464460 PLL_FREQ = 3732
4940 04:41:22.467706 DQ_UI_PI_RATIO = 32
4941 04:41:22.470735 CA_UI_PI_RATIO = 0
4942 04:41:22.474262 ===================================
4943 04:41:22.477764 ===================================
4944 04:41:22.477845 memory_type:LPDDR4
4945 04:41:22.481161 GP_NUM : 10
4946 04:41:22.484010 SRAM_EN : 1
4947 04:41:22.484092 MD32_EN : 0
4948 04:41:22.487550 ===================================
4949 04:41:22.490809 [ANA_INIT] >>>>>>>>>>>>>>
4950 04:41:22.494100 <<<<<< [CONFIGURE PHASE]: ANA_TX
4951 04:41:22.497583 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4952 04:41:22.500379 ===================================
4953 04:41:22.504110 data_rate = 1866,PCW = 0X8f00
4954 04:41:22.506988 ===================================
4955 04:41:22.510442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4956 04:41:22.513643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4957 04:41:22.520264 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4958 04:41:22.523851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4959 04:41:22.527004 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4960 04:41:22.533674 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4961 04:41:22.533755 [ANA_INIT] flow start
4962 04:41:22.536586 [ANA_INIT] PLL >>>>>>>>
4963 04:41:22.540020 [ANA_INIT] PLL <<<<<<<<
4964 04:41:22.540101 [ANA_INIT] MIDPI >>>>>>>>
4965 04:41:22.543701 [ANA_INIT] MIDPI <<<<<<<<
4966 04:41:22.546585 [ANA_INIT] DLL >>>>>>>>
4967 04:41:22.546665 [ANA_INIT] flow end
4968 04:41:22.549864 ============ LP4 DIFF to SE enter ============
4969 04:41:22.556812 ============ LP4 DIFF to SE exit ============
4970 04:41:22.556899 [ANA_INIT] <<<<<<<<<<<<<
4971 04:41:22.560398 [Flow] Enable top DCM control >>>>>
4972 04:41:22.562912 [Flow] Enable top DCM control <<<<<
4973 04:41:22.566405 Enable DLL master slave shuffle
4974 04:41:22.573092 ==============================================================
4975 04:41:22.576545 Gating Mode config
4976 04:41:22.579546 ==============================================================
4977 04:41:22.582905 Config description:
4978 04:41:22.592801 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4979 04:41:22.599131 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4980 04:41:22.602426 SELPH_MODE 0: By rank 1: By Phase
4981 04:41:22.609077 ==============================================================
4982 04:41:22.612435 GAT_TRACK_EN = 1
4983 04:41:22.615888 RX_GATING_MODE = 2
4984 04:41:22.619578 RX_GATING_TRACK_MODE = 2
4985 04:41:22.623092 SELPH_MODE = 1
4986 04:41:22.623173 PICG_EARLY_EN = 1
4987 04:41:22.625842 VALID_LAT_VALUE = 1
4988 04:41:22.632545 ==============================================================
4989 04:41:22.635786 Enter into Gating configuration >>>>
4990 04:41:22.638839 Exit from Gating configuration <<<<
4991 04:41:22.642536 Enter into DVFS_PRE_config >>>>>
4992 04:41:22.652253 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4993 04:41:22.655192 Exit from DVFS_PRE_config <<<<<
4994 04:41:22.658530 Enter into PICG configuration >>>>
4995 04:41:22.662054 Exit from PICG configuration <<<<
4996 04:41:22.664951 [RX_INPUT] configuration >>>>>
4997 04:41:22.668611 [RX_INPUT] configuration <<<<<
4998 04:41:22.674995 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4999 04:41:22.678045 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5000 04:41:22.684464 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5001 04:41:22.691224 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5002 04:41:22.698190 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5003 04:41:22.704368 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5004 04:41:22.707552 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5005 04:41:22.711414 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5006 04:41:22.714628 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5007 04:41:22.720849 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5008 04:41:22.724316 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5009 04:41:22.727239 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5010 04:41:22.731109 ===================================
5011 04:41:22.734267 LPDDR4 DRAM CONFIGURATION
5012 04:41:22.737189 ===================================
5013 04:41:22.741056 EX_ROW_EN[0] = 0x0
5014 04:41:22.741153 EX_ROW_EN[1] = 0x0
5015 04:41:22.743623 LP4Y_EN = 0x0
5016 04:41:22.743722 WORK_FSP = 0x0
5017 04:41:22.747037 WL = 0x3
5018 04:41:22.747140 RL = 0x3
5019 04:41:22.750092 BL = 0x2
5020 04:41:22.750189 RPST = 0x0
5021 04:41:22.753815 RD_PRE = 0x0
5022 04:41:22.753912 WR_PRE = 0x1
5023 04:41:22.757226 WR_PST = 0x0
5024 04:41:22.757343 DBI_WR = 0x0
5025 04:41:22.760754 DBI_RD = 0x0
5026 04:41:22.763302 OTF = 0x1
5027 04:41:22.766894 ===================================
5028 04:41:22.770786 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5029 04:41:22.773767 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5030 04:41:22.776956 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5031 04:41:22.779840 ===================================
5032 04:41:22.783169 LPDDR4 DRAM CONFIGURATION
5033 04:41:22.786778 ===================================
5034 04:41:22.790247 EX_ROW_EN[0] = 0x10
5035 04:41:22.790370 EX_ROW_EN[1] = 0x0
5036 04:41:22.793337 LP4Y_EN = 0x0
5037 04:41:22.793468 WORK_FSP = 0x0
5038 04:41:22.796697 WL = 0x3
5039 04:41:22.796802 RL = 0x3
5040 04:41:22.800482 BL = 0x2
5041 04:41:22.800594 RPST = 0x0
5042 04:41:22.803215 RD_PRE = 0x0
5043 04:41:22.803300 WR_PRE = 0x1
5044 04:41:22.806443 WR_PST = 0x0
5045 04:41:22.806524 DBI_WR = 0x0
5046 04:41:22.809824 DBI_RD = 0x0
5047 04:41:22.813365 OTF = 0x1
5048 04:41:22.816361 ===================================
5049 04:41:22.819833 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5050 04:41:22.825054 nWR fixed to 30
5051 04:41:22.827930 [ModeRegInit_LP4] CH0 RK0
5052 04:41:22.828043 [ModeRegInit_LP4] CH0 RK1
5053 04:41:22.831566 [ModeRegInit_LP4] CH1 RK0
5054 04:41:22.834579 [ModeRegInit_LP4] CH1 RK1
5055 04:41:22.834653 match AC timing 9
5056 04:41:22.841037 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5057 04:41:22.844542 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5058 04:41:22.847958 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5059 04:41:22.854547 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5060 04:41:22.857248 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5061 04:41:22.857355 ==
5062 04:41:22.860707 Dram Type= 6, Freq= 0, CH_0, rank 0
5063 04:41:22.864163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5064 04:41:22.867696 ==
5065 04:41:22.871084 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5066 04:41:22.877089 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5067 04:41:22.880512 [CA 0] Center 37 (7~68) winsize 62
5068 04:41:22.884051 [CA 1] Center 37 (7~68) winsize 62
5069 04:41:22.886864 [CA 2] Center 34 (4~64) winsize 61
5070 04:41:22.890358 [CA 3] Center 34 (4~65) winsize 62
5071 04:41:22.893855 [CA 4] Center 33 (2~64) winsize 63
5072 04:41:22.897088 [CA 5] Center 32 (2~63) winsize 62
5073 04:41:22.897196
5074 04:41:22.900094 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5075 04:41:22.900177
5076 04:41:22.903969 [CATrainingPosCal] consider 1 rank data
5077 04:41:22.907366 u2DelayCellTimex100 = 270/100 ps
5078 04:41:22.910117 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5079 04:41:22.913773 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5080 04:41:22.919758 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5081 04:41:22.923438 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5082 04:41:22.926433 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5083 04:41:22.929997 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5084 04:41:22.930116
5085 04:41:22.933172 CA PerBit enable=1, Macro0, CA PI delay=32
5086 04:41:22.933257
5087 04:41:22.936459 [CBTSetCACLKResult] CA Dly = 32
5088 04:41:22.936543 CS Dly: 5 (0~36)
5089 04:41:22.939743 ==
5090 04:41:22.942755 Dram Type= 6, Freq= 0, CH_0, rank 1
5091 04:41:22.946110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 04:41:22.946221 ==
5093 04:41:22.949620 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5094 04:41:22.955990 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5095 04:41:22.959795 [CA 0] Center 38 (8~68) winsize 61
5096 04:41:22.963434 [CA 1] Center 37 (7~68) winsize 62
5097 04:41:22.966393 [CA 2] Center 34 (4~65) winsize 62
5098 04:41:22.969874 [CA 3] Center 34 (4~65) winsize 62
5099 04:41:22.973363 [CA 4] Center 33 (3~64) winsize 62
5100 04:41:22.976287 [CA 5] Center 32 (2~63) winsize 62
5101 04:41:22.976372
5102 04:41:22.979632 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5103 04:41:22.979716
5104 04:41:22.982966 [CATrainingPosCal] consider 2 rank data
5105 04:41:22.986473 u2DelayCellTimex100 = 270/100 ps
5106 04:41:22.989791 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5107 04:41:22.996211 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5108 04:41:22.999952 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5109 04:41:23.002619 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5110 04:41:23.005662 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5111 04:41:23.009371 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5112 04:41:23.009470
5113 04:41:23.012809 CA PerBit enable=1, Macro0, CA PI delay=32
5114 04:41:23.012897
5115 04:41:23.015952 [CBTSetCACLKResult] CA Dly = 32
5116 04:41:23.019335 CS Dly: 6 (0~39)
5117 04:41:23.019442
5118 04:41:23.022433 ----->DramcWriteLeveling(PI) begin...
5119 04:41:23.022540 ==
5120 04:41:23.025608 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 04:41:23.028731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 04:41:23.028816 ==
5123 04:41:23.031998 Write leveling (Byte 0): 29 => 29
5124 04:41:23.035418 Write leveling (Byte 1): 26 => 26
5125 04:41:23.039916 DramcWriteLeveling(PI) end<-----
5126 04:41:23.040038
5127 04:41:23.040141 ==
5128 04:41:23.042753 Dram Type= 6, Freq= 0, CH_0, rank 0
5129 04:41:23.045377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 04:41:23.045489 ==
5131 04:41:23.048636 [Gating] SW mode calibration
5132 04:41:23.055511 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5133 04:41:23.061868 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5134 04:41:23.065403 0 14 0 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
5135 04:41:23.071986 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5136 04:41:23.075186 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 04:41:23.078707 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 04:41:23.085122 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 04:41:23.088018 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 04:41:23.091556 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5141 04:41:23.098356 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
5142 04:41:23.101465 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (1 0)
5143 04:41:23.104879 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5144 04:41:23.111174 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 04:41:23.114225 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 04:41:23.117944 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 04:41:23.124291 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 04:41:23.127619 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5149 04:41:23.131077 0 15 28 | B1->B0 | 2424 3938 | 0 1 | (0 0) (0 0)
5150 04:41:23.137605 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
5151 04:41:23.141148 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 04:41:23.144687 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 04:41:23.150730 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 04:41:23.154138 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 04:41:23.157731 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 04:41:23.164180 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 04:41:23.167657 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5158 04:41:23.170635 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5159 04:41:23.177145 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 04:41:23.180587 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 04:41:23.184289 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 04:41:23.190412 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 04:41:23.193736 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 04:41:23.197269 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 04:41:23.203594 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 04:41:23.207290 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 04:41:23.210110 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 04:41:23.217137 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 04:41:23.220545 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 04:41:23.223318 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 04:41:23.230366 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 04:41:23.233597 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5173 04:41:23.237006 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5174 04:41:23.243039 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5175 04:41:23.243123 Total UI for P1: 0, mck2ui 16
5176 04:41:23.249732 best dqsien dly found for B0: ( 1, 2, 26)
5177 04:41:23.252979 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5178 04:41:23.256840 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 04:41:23.259755 Total UI for P1: 0, mck2ui 16
5180 04:41:23.263018 best dqsien dly found for B1: ( 1, 3, 2)
5181 04:41:23.266081 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5182 04:41:23.269508 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5183 04:41:23.269589
5184 04:41:23.272920 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5185 04:41:23.279296 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5186 04:41:23.279402 [Gating] SW calibration Done
5187 04:41:23.283069 ==
5188 04:41:23.283150 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 04:41:23.289245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 04:41:23.289328 ==
5191 04:41:23.289393 RX Vref Scan: 0
5192 04:41:23.289454
5193 04:41:23.292365 RX Vref 0 -> 0, step: 1
5194 04:41:23.292446
5195 04:41:23.295951 RX Delay -80 -> 252, step: 8
5196 04:41:23.299089 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5197 04:41:23.302496 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5198 04:41:23.306019 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5199 04:41:23.312534 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5200 04:41:23.315502 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5201 04:41:23.319106 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5202 04:41:23.322574 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5203 04:41:23.325382 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5204 04:41:23.328740 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5205 04:41:23.335235 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5206 04:41:23.338564 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5207 04:41:23.342133 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5208 04:41:23.345278 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5209 04:41:23.349167 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5210 04:41:23.355261 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5211 04:41:23.358318 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5212 04:41:23.358400 ==
5213 04:41:23.361788 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 04:41:23.365232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 04:41:23.365314 ==
5216 04:41:23.368321 DQS Delay:
5217 04:41:23.368402 DQS0 = 0, DQS1 = 0
5218 04:41:23.368467 DQM Delay:
5219 04:41:23.371472 DQM0 = 100, DQM1 = 88
5220 04:41:23.371554 DQ Delay:
5221 04:41:23.375054 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5222 04:41:23.378053 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =111
5223 04:41:23.381873 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5224 04:41:23.384810 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5225 04:41:23.384891
5226 04:41:23.384955
5227 04:41:23.385014 ==
5228 04:41:23.388391 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 04:41:23.395318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 04:41:23.395427 ==
5231 04:41:23.395492
5232 04:41:23.395552
5233 04:41:23.398158 TX Vref Scan disable
5234 04:41:23.398239 == TX Byte 0 ==
5235 04:41:23.401423 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5236 04:41:23.407568 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5237 04:41:23.407649 == TX Byte 1 ==
5238 04:41:23.414063 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5239 04:41:23.417341 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5240 04:41:23.417449 ==
5241 04:41:23.420627 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 04:41:23.424336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 04:41:23.424411 ==
5244 04:41:23.424483
5245 04:41:23.424580
5246 04:41:23.427182 TX Vref Scan disable
5247 04:41:23.430783 == TX Byte 0 ==
5248 04:41:23.434150 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5249 04:41:23.437137 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5250 04:41:23.440461 == TX Byte 1 ==
5251 04:41:23.443732 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5252 04:41:23.447310 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5253 04:41:23.447442
5254 04:41:23.450641 [DATLAT]
5255 04:41:23.450722 Freq=933, CH0 RK0
5256 04:41:23.450786
5257 04:41:23.453690 DATLAT Default: 0xd
5258 04:41:23.453797 0, 0xFFFF, sum = 0
5259 04:41:23.457019 1, 0xFFFF, sum = 0
5260 04:41:23.457101 2, 0xFFFF, sum = 0
5261 04:41:23.460549 3, 0xFFFF, sum = 0
5262 04:41:23.460631 4, 0xFFFF, sum = 0
5263 04:41:23.463446 5, 0xFFFF, sum = 0
5264 04:41:23.463528 6, 0xFFFF, sum = 0
5265 04:41:23.467068 7, 0xFFFF, sum = 0
5266 04:41:23.467176 8, 0xFFFF, sum = 0
5267 04:41:23.469997 9, 0xFFFF, sum = 0
5268 04:41:23.470116 10, 0x0, sum = 1
5269 04:41:23.473435 11, 0x0, sum = 2
5270 04:41:23.473536 12, 0x0, sum = 3
5271 04:41:23.476591 13, 0x0, sum = 4
5272 04:41:23.476667 best_step = 11
5273 04:41:23.476743
5274 04:41:23.476801 ==
5275 04:41:23.479829 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 04:41:23.486464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 04:41:23.486564 ==
5278 04:41:23.486654 RX Vref Scan: 1
5279 04:41:23.486740
5280 04:41:23.489452 RX Vref 0 -> 0, step: 1
5281 04:41:23.489567
5282 04:41:23.493283 RX Delay -61 -> 252, step: 4
5283 04:41:23.493390
5284 04:41:23.496631 Set Vref, RX VrefLevel [Byte0]: 51
5285 04:41:23.499507 [Byte1]: 47
5286 04:41:23.499604
5287 04:41:23.502882 Final RX Vref Byte 0 = 51 to rank0
5288 04:41:23.506071 Final RX Vref Byte 1 = 47 to rank0
5289 04:41:23.509596 Final RX Vref Byte 0 = 51 to rank1
5290 04:41:23.512876 Final RX Vref Byte 1 = 47 to rank1==
5291 04:41:23.515849 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 04:41:23.519515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 04:41:23.522462 ==
5294 04:41:23.522570 DQS Delay:
5295 04:41:23.522660 DQS0 = 0, DQS1 = 0
5296 04:41:23.526162 DQM Delay:
5297 04:41:23.526296 DQM0 = 99, DQM1 = 87
5298 04:41:23.529465 DQ Delay:
5299 04:41:23.532787 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5300 04:41:23.536054 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =104
5301 04:41:23.539106 DQ8 =80, DQ9 =74, DQ10 =86, DQ11 =82
5302 04:41:23.542330 DQ12 =94, DQ13 =92, DQ14 =96, DQ15 =96
5303 04:41:23.542427
5304 04:41:23.542514
5305 04:41:23.549585 [DQSOSCAuto] RK0, (LSB)MR18= 0x1913, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5306 04:41:23.552383 CH0 RK0: MR19=505, MR18=1913
5307 04:41:23.559104 CH0_RK0: MR19=0x505, MR18=0x1913, DQSOSC=413, MR23=63, INC=63, DEC=42
5308 04:41:23.559205
5309 04:41:23.562345 ----->DramcWriteLeveling(PI) begin...
5310 04:41:23.562446 ==
5311 04:41:23.565827 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 04:41:23.569062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 04:41:23.569133 ==
5314 04:41:23.572403 Write leveling (Byte 0): 34 => 34
5315 04:41:23.575758 Write leveling (Byte 1): 27 => 27
5316 04:41:23.578508 DramcWriteLeveling(PI) end<-----
5317 04:41:23.578592
5318 04:41:23.578653 ==
5319 04:41:23.582053 Dram Type= 6, Freq= 0, CH_0, rank 1
5320 04:41:23.585104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 04:41:23.588257 ==
5322 04:41:23.588356 [Gating] SW mode calibration
5323 04:41:23.598264 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5324 04:41:23.601851 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5325 04:41:23.605653 0 14 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5326 04:41:23.611842 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 04:41:23.615031 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 04:41:23.618441 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 04:41:23.624909 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 04:41:23.628115 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 04:41:23.631014 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5332 04:41:23.637926 0 14 28 | B1->B0 | 3333 2a2a | 1 0 | (1 0) (1 0)
5333 04:41:23.641273 0 15 0 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
5334 04:41:23.644163 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 04:41:23.651479 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 04:41:23.654117 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 04:41:23.657807 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 04:41:23.664107 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 04:41:23.667150 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5340 04:41:23.670902 0 15 28 | B1->B0 | 2c2c 3939 | 0 1 | (0 0) (0 0)
5341 04:41:23.677123 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5342 04:41:23.681324 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 04:41:23.683774 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 04:41:23.690326 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 04:41:23.693528 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 04:41:23.697228 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 04:41:23.703870 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5348 04:41:23.706673 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5349 04:41:23.709968 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5350 04:41:23.716817 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 04:41:23.720123 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 04:41:23.724058 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 04:41:23.730519 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 04:41:23.733194 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 04:41:23.736743 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 04:41:23.743201 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 04:41:23.746509 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 04:41:23.750031 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 04:41:23.756746 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 04:41:23.759977 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 04:41:23.762871 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 04:41:23.769640 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 04:41:23.772739 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5364 04:41:23.776014 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5365 04:41:23.782807 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5366 04:41:23.785895 Total UI for P1: 0, mck2ui 16
5367 04:41:23.789161 best dqsien dly found for B0: ( 1, 2, 26)
5368 04:41:23.792505 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 04:41:23.795798 Total UI for P1: 0, mck2ui 16
5370 04:41:23.799203 best dqsien dly found for B1: ( 1, 3, 0)
5371 04:41:23.802647 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5372 04:41:23.805578 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5373 04:41:23.805678
5374 04:41:23.808899 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5375 04:41:23.815788 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5376 04:41:23.815864 [Gating] SW calibration Done
5377 04:41:23.815927 ==
5378 04:41:23.818738 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 04:41:23.825717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 04:41:23.825798 ==
5381 04:41:23.825861 RX Vref Scan: 0
5382 04:41:23.825922
5383 04:41:23.828758 RX Vref 0 -> 0, step: 1
5384 04:41:23.828838
5385 04:41:23.832085 RX Delay -80 -> 252, step: 8
5386 04:41:23.835757 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5387 04:41:23.838964 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5388 04:41:23.841991 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5389 04:41:23.845212 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5390 04:41:23.852131 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5391 04:41:23.855094 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5392 04:41:23.858659 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5393 04:41:23.862179 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5394 04:41:23.865277 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5395 04:41:23.868502 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5396 04:41:23.874905 iDelay=200, Bit 10, Center 83 (-8 ~ 175) 184
5397 04:41:23.878330 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5398 04:41:23.881606 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5399 04:41:23.884753 iDelay=200, Bit 13, Center 91 (0 ~ 183) 184
5400 04:41:23.888237 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5401 04:41:23.895047 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5402 04:41:23.895121 ==
5403 04:41:23.897932 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 04:41:23.901267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 04:41:23.901365 ==
5406 04:41:23.901463 DQS Delay:
5407 04:41:23.904500 DQS0 = 0, DQS1 = 0
5408 04:41:23.904600 DQM Delay:
5409 04:41:23.907945 DQM0 = 97, DQM1 = 88
5410 04:41:23.908043 DQ Delay:
5411 04:41:23.911478 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5412 04:41:23.914767 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5413 04:41:23.917592 DQ8 =83, DQ9 =79, DQ10 =83, DQ11 =83
5414 04:41:23.921243 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =91
5415 04:41:23.921342
5416 04:41:23.921441
5417 04:41:23.921529 ==
5418 04:41:23.924074 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 04:41:23.927931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 04:41:23.930803 ==
5421 04:41:23.930876
5422 04:41:23.930935
5423 04:41:23.930993 TX Vref Scan disable
5424 04:41:23.934195 == TX Byte 0 ==
5425 04:41:23.937992 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5426 04:41:23.940583 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5427 04:41:23.944346 == TX Byte 1 ==
5428 04:41:23.947500 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5429 04:41:23.950624 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5430 04:41:23.954100 ==
5431 04:41:23.957147 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 04:41:23.960301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 04:41:23.960374 ==
5434 04:41:23.960434
5435 04:41:23.960491
5436 04:41:23.963713 TX Vref Scan disable
5437 04:41:23.963788 == TX Byte 0 ==
5438 04:41:23.970567 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5439 04:41:23.973657 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5440 04:41:23.973760 == TX Byte 1 ==
5441 04:41:23.980017 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5442 04:41:23.983257 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5443 04:41:23.983375
5444 04:41:23.983501 [DATLAT]
5445 04:41:23.986563 Freq=933, CH0 RK1
5446 04:41:23.986665
5447 04:41:23.986752 DATLAT Default: 0xb
5448 04:41:23.989942 0, 0xFFFF, sum = 0
5449 04:41:23.993544 1, 0xFFFF, sum = 0
5450 04:41:23.993632 2, 0xFFFF, sum = 0
5451 04:41:23.996616 3, 0xFFFF, sum = 0
5452 04:41:23.996691 4, 0xFFFF, sum = 0
5453 04:41:24.000110 5, 0xFFFF, sum = 0
5454 04:41:24.000196 6, 0xFFFF, sum = 0
5455 04:41:24.003285 7, 0xFFFF, sum = 0
5456 04:41:24.003420 8, 0xFFFF, sum = 0
5457 04:41:24.006895 9, 0xFFFF, sum = 0
5458 04:41:24.006981 10, 0x0, sum = 1
5459 04:41:24.009821 11, 0x0, sum = 2
5460 04:41:24.009956 12, 0x0, sum = 3
5461 04:41:24.013051 13, 0x0, sum = 4
5462 04:41:24.013123 best_step = 11
5463 04:41:24.013183
5464 04:41:24.013240 ==
5465 04:41:24.017017 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 04:41:24.019435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 04:41:24.023072 ==
5468 04:41:24.023154 RX Vref Scan: 0
5469 04:41:24.023218
5470 04:41:24.026512 RX Vref 0 -> 0, step: 1
5471 04:41:24.026593
5472 04:41:24.029374 RX Delay -53 -> 252, step: 4
5473 04:41:24.032912 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5474 04:41:24.035901 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5475 04:41:24.039434 iDelay=195, Bit 2, Center 94 (7 ~ 182) 176
5476 04:41:24.045822 iDelay=195, Bit 3, Center 94 (7 ~ 182) 176
5477 04:41:24.049290 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5478 04:41:24.052850 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5479 04:41:24.055982 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5480 04:41:24.059216 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5481 04:41:24.066215 iDelay=195, Bit 8, Center 80 (-9 ~ 170) 180
5482 04:41:24.069102 iDelay=195, Bit 9, Center 76 (-13 ~ 166) 180
5483 04:41:24.072480 iDelay=195, Bit 10, Center 88 (-1 ~ 178) 180
5484 04:41:24.075730 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5485 04:41:24.078806 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5486 04:41:24.085709 iDelay=195, Bit 13, Center 94 (7 ~ 182) 176
5487 04:41:24.088657 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5488 04:41:24.092058 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5489 04:41:24.092136 ==
5490 04:41:24.095358 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 04:41:24.098490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 04:41:24.098595 ==
5493 04:41:24.102003 DQS Delay:
5494 04:41:24.102100 DQS0 = 0, DQS1 = 0
5495 04:41:24.102188 DQM Delay:
5496 04:41:24.105876 DQM0 = 98, DQM1 = 88
5497 04:41:24.105974 DQ Delay:
5498 04:41:24.108536 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5499 04:41:24.111858 DQ4 =102, DQ5 =88, DQ6 =106, DQ7 =106
5500 04:41:24.115229 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =82
5501 04:41:24.118676 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =94
5502 04:41:24.118755
5503 04:41:24.118818
5504 04:41:24.128351 [DQSOSCAuto] RK1, (LSB)MR18= 0x110e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5505 04:41:24.131605 CH0 RK1: MR19=505, MR18=110E
5506 04:41:24.138145 CH0_RK1: MR19=0x505, MR18=0x110E, DQSOSC=416, MR23=63, INC=62, DEC=41
5507 04:41:24.138226 [RxdqsGatingPostProcess] freq 933
5508 04:41:24.145043 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5509 04:41:24.148141 best DQS0 dly(2T, 0.5T) = (0, 10)
5510 04:41:24.151639 best DQS1 dly(2T, 0.5T) = (0, 11)
5511 04:41:24.154945 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5512 04:41:24.158042 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5513 04:41:24.161652 best DQS0 dly(2T, 0.5T) = (0, 10)
5514 04:41:24.164573 best DQS1 dly(2T, 0.5T) = (0, 11)
5515 04:41:24.167917 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5516 04:41:24.171266 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5517 04:41:24.174516 Pre-setting of DQS Precalculation
5518 04:41:24.177958 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5519 04:41:24.178039 ==
5520 04:41:24.181630 Dram Type= 6, Freq= 0, CH_1, rank 0
5521 04:41:24.187568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 04:41:24.187649 ==
5523 04:41:24.191021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5524 04:41:24.197356 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5525 04:41:24.200652 [CA 0] Center 36 (6~67) winsize 62
5526 04:41:24.204183 [CA 1] Center 36 (6~67) winsize 62
5527 04:41:24.208299 [CA 2] Center 34 (4~65) winsize 62
5528 04:41:24.210933 [CA 3] Center 34 (4~64) winsize 61
5529 04:41:24.213813 [CA 4] Center 34 (4~65) winsize 62
5530 04:41:24.217171 [CA 5] Center 33 (3~64) winsize 62
5531 04:41:24.217252
5532 04:41:24.220484 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5533 04:41:24.220565
5534 04:41:24.223799 [CATrainingPosCal] consider 1 rank data
5535 04:41:24.226795 u2DelayCellTimex100 = 270/100 ps
5536 04:41:24.230523 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5537 04:41:24.236794 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5538 04:41:24.240282 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5539 04:41:24.243635 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5540 04:41:24.246898 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5541 04:41:24.249897 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5542 04:41:24.249977
5543 04:41:24.253411 CA PerBit enable=1, Macro0, CA PI delay=33
5544 04:41:24.253492
5545 04:41:24.256551 [CBTSetCACLKResult] CA Dly = 33
5546 04:41:24.259834 CS Dly: 5 (0~36)
5547 04:41:24.259914 ==
5548 04:41:24.263071 Dram Type= 6, Freq= 0, CH_1, rank 1
5549 04:41:24.267068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 04:41:24.267149 ==
5551 04:41:24.272746 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5552 04:41:24.275871 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5553 04:41:24.280161 [CA 0] Center 36 (6~67) winsize 62
5554 04:41:24.283372 [CA 1] Center 36 (6~67) winsize 62
5555 04:41:24.287497 [CA 2] Center 34 (4~65) winsize 62
5556 04:41:24.290516 [CA 3] Center 33 (3~64) winsize 62
5557 04:41:24.293428 [CA 4] Center 34 (3~65) winsize 63
5558 04:41:24.297070 [CA 5] Center 33 (3~64) winsize 62
5559 04:41:24.297151
5560 04:41:24.300195 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5561 04:41:24.300276
5562 04:41:24.303710 [CATrainingPosCal] consider 2 rank data
5563 04:41:24.307159 u2DelayCellTimex100 = 270/100 ps
5564 04:41:24.310498 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5565 04:41:24.316594 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5566 04:41:24.320002 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5567 04:41:24.322971 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5568 04:41:24.326256 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5569 04:41:24.329784 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5570 04:41:24.329865
5571 04:41:24.332949 CA PerBit enable=1, Macro0, CA PI delay=33
5572 04:41:24.333030
5573 04:41:24.336138 [CBTSetCACLKResult] CA Dly = 33
5574 04:41:24.339684 CS Dly: 6 (0~38)
5575 04:41:24.339764
5576 04:41:24.342771 ----->DramcWriteLeveling(PI) begin...
5577 04:41:24.342853 ==
5578 04:41:24.346054 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 04:41:24.349346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 04:41:24.349427 ==
5581 04:41:24.353043 Write leveling (Byte 0): 27 => 27
5582 04:41:24.355892 Write leveling (Byte 1): 28 => 28
5583 04:41:24.359604 DramcWriteLeveling(PI) end<-----
5584 04:41:24.359685
5585 04:41:24.359749 ==
5586 04:41:24.362336 Dram Type= 6, Freq= 0, CH_1, rank 0
5587 04:41:24.365911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5588 04:41:24.365991 ==
5589 04:41:24.369440 [Gating] SW mode calibration
5590 04:41:24.376073 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5591 04:41:24.382357 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5592 04:41:24.385582 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 04:41:24.388994 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 04:41:24.395687 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 04:41:24.398721 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 04:41:24.402456 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 04:41:24.408483 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 04:41:24.412034 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5599 04:41:24.415471 0 14 28 | B1->B0 | 2b2b 2828 | 0 0 | (1 0) (1 0)
5600 04:41:24.421970 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 04:41:24.425369 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 04:41:24.428461 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 04:41:24.435325 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 04:41:24.438353 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 04:41:24.441686 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 04:41:24.448330 0 15 24 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
5607 04:41:24.451526 0 15 28 | B1->B0 | 3535 3e3e | 1 0 | (0 0) (0 0)
5608 04:41:24.455031 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 04:41:24.461560 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 04:41:24.464788 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 04:41:24.471006 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 04:41:24.474470 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 04:41:24.478131 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 04:41:24.484358 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 04:41:24.487843 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5616 04:41:24.490812 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 04:41:24.497639 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 04:41:24.501120 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 04:41:24.504415 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 04:41:24.510702 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 04:41:24.514420 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 04:41:24.517490 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 04:41:24.524042 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 04:41:24.527828 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 04:41:24.530498 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 04:41:24.537121 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 04:41:24.540462 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 04:41:24.543799 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 04:41:24.550002 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 04:41:24.553437 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 04:41:24.556891 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5632 04:41:24.563460 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5633 04:41:24.563547 Total UI for P1: 0, mck2ui 16
5634 04:41:24.570128 best dqsien dly found for B0: ( 1, 2, 28)
5635 04:41:24.573036 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 04:41:24.576635 Total UI for P1: 0, mck2ui 16
5637 04:41:24.579730 best dqsien dly found for B1: ( 1, 2, 30)
5638 04:41:24.583089 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5639 04:41:24.586195 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5640 04:41:24.586290
5641 04:41:24.589938 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5642 04:41:24.592711 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5643 04:41:24.596256 [Gating] SW calibration Done
5644 04:41:24.596336 ==
5645 04:41:24.599764 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 04:41:24.603157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 04:41:24.606260 ==
5648 04:41:24.606373 RX Vref Scan: 0
5649 04:41:24.606467
5650 04:41:24.609710 RX Vref 0 -> 0, step: 1
5651 04:41:24.609816
5652 04:41:24.612933 RX Delay -80 -> 252, step: 8
5653 04:41:24.616207 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5654 04:41:24.619163 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5655 04:41:24.622702 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5656 04:41:24.625706 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5657 04:41:24.629066 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5658 04:41:24.636046 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5659 04:41:24.638884 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5660 04:41:24.642333 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5661 04:41:24.645233 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5662 04:41:24.648864 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5663 04:41:24.655332 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5664 04:41:24.658358 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5665 04:41:24.661911 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5666 04:41:24.665062 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5667 04:41:24.668658 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5668 04:41:24.675015 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5669 04:41:24.675113 ==
5670 04:41:24.678495 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 04:41:24.681427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 04:41:24.681498 ==
5673 04:41:24.681575 DQS Delay:
5674 04:41:24.685021 DQS0 = 0, DQS1 = 0
5675 04:41:24.685089 DQM Delay:
5676 04:41:24.688053 DQM0 = 99, DQM1 = 96
5677 04:41:24.688147 DQ Delay:
5678 04:41:24.691702 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5679 04:41:24.694334 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5680 04:41:24.698139 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5681 04:41:24.701057 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5682 04:41:24.701135
5683 04:41:24.701195
5684 04:41:24.701252 ==
5685 04:41:24.704839 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 04:41:24.711015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 04:41:24.711090 ==
5688 04:41:24.711185
5689 04:41:24.711279
5690 04:41:24.711389 TX Vref Scan disable
5691 04:41:24.714935 == TX Byte 0 ==
5692 04:41:24.717621 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5693 04:41:24.724271 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5694 04:41:24.724347 == TX Byte 1 ==
5695 04:41:24.728044 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5696 04:41:24.734096 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5697 04:41:24.734194 ==
5698 04:41:24.737351 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 04:41:24.741530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 04:41:24.741625 ==
5701 04:41:24.741689
5702 04:41:24.741746
5703 04:41:24.744412 TX Vref Scan disable
5704 04:41:24.747550 == TX Byte 0 ==
5705 04:41:24.750719 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5706 04:41:24.753852 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5707 04:41:24.757244 == TX Byte 1 ==
5708 04:41:24.760235 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5709 04:41:24.763535 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5710 04:41:24.763607
5711 04:41:24.763667 [DATLAT]
5712 04:41:24.766903 Freq=933, CH1 RK0
5713 04:41:24.766972
5714 04:41:24.770452 DATLAT Default: 0xd
5715 04:41:24.770521 0, 0xFFFF, sum = 0
5716 04:41:24.773455 1, 0xFFFF, sum = 0
5717 04:41:24.773552 2, 0xFFFF, sum = 0
5718 04:41:24.777263 3, 0xFFFF, sum = 0
5719 04:41:24.777351 4, 0xFFFF, sum = 0
5720 04:41:24.779866 5, 0xFFFF, sum = 0
5721 04:41:24.779937 6, 0xFFFF, sum = 0
5722 04:41:24.783499 7, 0xFFFF, sum = 0
5723 04:41:24.783569 8, 0xFFFF, sum = 0
5724 04:41:24.786958 9, 0xFFFF, sum = 0
5725 04:41:24.787061 10, 0x0, sum = 1
5726 04:41:24.790201 11, 0x0, sum = 2
5727 04:41:24.790275 12, 0x0, sum = 3
5728 04:41:24.793438 13, 0x0, sum = 4
5729 04:41:24.793548 best_step = 11
5730 04:41:24.793638
5731 04:41:24.793731 ==
5732 04:41:24.796368 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 04:41:24.803177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 04:41:24.803282 ==
5735 04:41:24.803400 RX Vref Scan: 1
5736 04:41:24.803503
5737 04:41:24.806607 RX Vref 0 -> 0, step: 1
5738 04:41:24.806705
5739 04:41:24.810198 RX Delay -53 -> 252, step: 4
5740 04:41:24.810295
5741 04:41:24.813141 Set Vref, RX VrefLevel [Byte0]: 54
5742 04:41:24.816566 [Byte1]: 53
5743 04:41:24.816636
5744 04:41:24.820105 Final RX Vref Byte 0 = 54 to rank0
5745 04:41:24.823094 Final RX Vref Byte 1 = 53 to rank0
5746 04:41:24.825967 Final RX Vref Byte 0 = 54 to rank1
5747 04:41:24.829674 Final RX Vref Byte 1 = 53 to rank1==
5748 04:41:24.832681 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 04:41:24.836652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 04:41:24.836756 ==
5751 04:41:24.839547 DQS Delay:
5752 04:41:24.839616 DQS0 = 0, DQS1 = 0
5753 04:41:24.839676 DQM Delay:
5754 04:41:24.843276 DQM0 = 98, DQM1 = 94
5755 04:41:24.843396 DQ Delay:
5756 04:41:24.846140 DQ0 =104, DQ1 =94, DQ2 =86, DQ3 =98
5757 04:41:24.849226 DQ4 =94, DQ5 =108, DQ6 =108, DQ7 =94
5758 04:41:24.852758 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =88
5759 04:41:24.855949 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5760 04:41:24.859360
5761 04:41:24.859445
5762 04:41:24.866221 [DQSOSCAuto] RK0, (LSB)MR18= 0xd1c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 417 ps
5763 04:41:24.868857 CH1 RK0: MR19=505, MR18=D1C
5764 04:41:24.875977 CH1_RK0: MR19=0x505, MR18=0xD1C, DQSOSC=412, MR23=63, INC=63, DEC=42
5765 04:41:24.876058
5766 04:41:24.879252 ----->DramcWriteLeveling(PI) begin...
5767 04:41:24.879336 ==
5768 04:41:24.882184 Dram Type= 6, Freq= 0, CH_1, rank 1
5769 04:41:24.885695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 04:41:24.885777 ==
5771 04:41:24.889115 Write leveling (Byte 0): 25 => 25
5772 04:41:24.892076 Write leveling (Byte 1): 31 => 31
5773 04:41:24.895334 DramcWriteLeveling(PI) end<-----
5774 04:41:24.895455
5775 04:41:24.895519 ==
5776 04:41:24.898967 Dram Type= 6, Freq= 0, CH_1, rank 1
5777 04:41:24.901996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 04:41:24.902077 ==
5779 04:41:24.905404 [Gating] SW mode calibration
5780 04:41:24.912123 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5781 04:41:24.918493 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5782 04:41:24.921663 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
5783 04:41:24.928410 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 04:41:24.931628 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 04:41:24.935031 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 04:41:24.941154 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 04:41:24.944540 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 04:41:24.947940 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
5789 04:41:24.954853 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
5790 04:41:24.957915 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 04:41:24.961359 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 04:41:24.967509 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 04:41:24.970839 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 04:41:24.974126 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 04:41:24.981642 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 04:41:24.984620 0 15 24 | B1->B0 | 2b2b 3636 | 0 1 | (1 1) (0 0)
5797 04:41:24.987607 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5798 04:41:24.993961 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 04:41:24.997059 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 04:41:25.000818 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 04:41:25.007226 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 04:41:25.010892 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 04:41:25.014041 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 04:41:25.020302 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5805 04:41:25.023262 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5806 04:41:25.026676 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 04:41:25.033339 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 04:41:25.036653 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 04:41:25.039995 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 04:41:25.046918 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 04:41:25.049997 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 04:41:25.053374 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 04:41:25.059887 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 04:41:25.062782 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 04:41:25.066225 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 04:41:25.072887 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 04:41:25.076459 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 04:41:25.079277 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 04:41:25.085981 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 04:41:25.089510 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 04:41:25.092743 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5822 04:41:25.095875 Total UI for P1: 0, mck2ui 16
5823 04:41:25.099237 best dqsien dly found for B0: ( 1, 2, 26)
5824 04:41:25.105644 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 04:41:25.105725 Total UI for P1: 0, mck2ui 16
5826 04:41:25.112774 best dqsien dly found for B1: ( 1, 2, 28)
5827 04:41:25.115698 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5828 04:41:25.119025 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5829 04:41:25.119134
5830 04:41:25.122129 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5831 04:41:25.125842 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5832 04:41:25.128867 [Gating] SW calibration Done
5833 04:41:25.128943 ==
5834 04:41:25.131969 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 04:41:25.135328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 04:41:25.135456 ==
5837 04:41:25.138673 RX Vref Scan: 0
5838 04:41:25.138767
5839 04:41:25.138863 RX Vref 0 -> 0, step: 1
5840 04:41:25.138949
5841 04:41:25.142215 RX Delay -80 -> 252, step: 8
5842 04:41:25.148407 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5843 04:41:25.151674 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5844 04:41:25.155610 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5845 04:41:25.158362 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5846 04:41:25.161963 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5847 04:41:25.165227 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5848 04:41:25.172060 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5849 04:41:25.175099 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5850 04:41:25.178462 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5851 04:41:25.181681 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5852 04:41:25.184837 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5853 04:41:25.188370 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5854 04:41:25.194662 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5855 04:41:25.198242 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5856 04:41:25.201324 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5857 04:41:25.204555 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5858 04:41:25.204632 ==
5859 04:41:25.207864 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 04:41:25.214338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 04:41:25.214420 ==
5862 04:41:25.214484 DQS Delay:
5863 04:41:25.214543 DQS0 = 0, DQS1 = 0
5864 04:41:25.217809 DQM Delay:
5865 04:41:25.217889 DQM0 = 97, DQM1 = 94
5866 04:41:25.221433 DQ Delay:
5867 04:41:25.224236 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5868 04:41:25.227936 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5869 04:41:25.231333 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5870 04:41:25.234265 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5871 04:41:25.234345
5872 04:41:25.234409
5873 04:41:25.234468 ==
5874 04:41:25.237768 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 04:41:25.240760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 04:41:25.240841 ==
5877 04:41:25.240905
5878 04:41:25.240964
5879 04:41:25.244119 TX Vref Scan disable
5880 04:41:25.247192 == TX Byte 0 ==
5881 04:41:25.251040 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5882 04:41:25.253822 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5883 04:41:25.257316 == TX Byte 1 ==
5884 04:41:25.260977 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5885 04:41:25.263698 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5886 04:41:25.263779 ==
5887 04:41:25.266973 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 04:41:25.273534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 04:41:25.273616 ==
5890 04:41:25.273679
5891 04:41:25.273739
5892 04:41:25.273795 TX Vref Scan disable
5893 04:41:25.277743 == TX Byte 0 ==
5894 04:41:25.281049 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5895 04:41:25.287501 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5896 04:41:25.287582 == TX Byte 1 ==
5897 04:41:25.290747 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5898 04:41:25.297762 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5899 04:41:25.297844
5900 04:41:25.297907 [DATLAT]
5901 04:41:25.297967 Freq=933, CH1 RK1
5902 04:41:25.298023
5903 04:41:25.300853 DATLAT Default: 0xb
5904 04:41:25.303761 0, 0xFFFF, sum = 0
5905 04:41:25.303844 1, 0xFFFF, sum = 0
5906 04:41:25.307035 2, 0xFFFF, sum = 0
5907 04:41:25.307116 3, 0xFFFF, sum = 0
5908 04:41:25.310435 4, 0xFFFF, sum = 0
5909 04:41:25.310516 5, 0xFFFF, sum = 0
5910 04:41:25.313656 6, 0xFFFF, sum = 0
5911 04:41:25.313738 7, 0xFFFF, sum = 0
5912 04:41:25.317012 8, 0xFFFF, sum = 0
5913 04:41:25.317085 9, 0xFFFF, sum = 0
5914 04:41:25.320786 10, 0x0, sum = 1
5915 04:41:25.320856 11, 0x0, sum = 2
5916 04:41:25.323543 12, 0x0, sum = 3
5917 04:41:25.323612 13, 0x0, sum = 4
5918 04:41:25.327216 best_step = 11
5919 04:41:25.327283
5920 04:41:25.327340 ==
5921 04:41:25.330091 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 04:41:25.333662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 04:41:25.333737 ==
5924 04:41:25.333797 RX Vref Scan: 0
5925 04:41:25.336990
5926 04:41:25.337058 RX Vref 0 -> 0, step: 1
5927 04:41:25.337115
5928 04:41:25.340369 RX Delay -53 -> 252, step: 4
5929 04:41:25.346722 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5930 04:41:25.350157 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5931 04:41:25.353657 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5932 04:41:25.356875 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5933 04:41:25.359832 iDelay=199, Bit 4, Center 98 (3 ~ 194) 192
5934 04:41:25.366397 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5935 04:41:25.369976 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5936 04:41:25.372836 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5937 04:41:25.376206 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5938 04:41:25.379403 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5939 04:41:25.383049 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5940 04:41:25.389818 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5941 04:41:25.393243 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5942 04:41:25.396162 iDelay=199, Bit 13, Center 100 (7 ~ 194) 188
5943 04:41:25.399655 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5944 04:41:25.405829 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5945 04:41:25.405900 ==
5946 04:41:25.409336 Dram Type= 6, Freq= 0, CH_1, rank 1
5947 04:41:25.412254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5948 04:41:25.412326 ==
5949 04:41:25.412388 DQS Delay:
5950 04:41:25.415657 DQS0 = 0, DQS1 = 0
5951 04:41:25.415731 DQM Delay:
5952 04:41:25.419032 DQM0 = 97, DQM1 = 93
5953 04:41:25.419098 DQ Delay:
5954 04:41:25.422229 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =94
5955 04:41:25.425676 DQ4 =98, DQ5 =106, DQ6 =106, DQ7 =94
5956 04:41:25.429155 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =86
5957 04:41:25.432056 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =102
5958 04:41:25.432124
5959 04:41:25.432183
5960 04:41:25.442274 [DQSOSCAuto] RK1, (LSB)MR18= 0xc23, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 418 ps
5961 04:41:25.442349 CH1 RK1: MR19=505, MR18=C23
5962 04:41:25.448993 CH1_RK1: MR19=0x505, MR18=0xC23, DQSOSC=410, MR23=63, INC=64, DEC=42
5963 04:41:25.451949 [RxdqsGatingPostProcess] freq 933
5964 04:41:25.458736 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5965 04:41:25.462143 best DQS0 dly(2T, 0.5T) = (0, 10)
5966 04:41:25.465613 best DQS1 dly(2T, 0.5T) = (0, 10)
5967 04:41:25.468612 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5968 04:41:25.471938 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5969 04:41:25.474987 best DQS0 dly(2T, 0.5T) = (0, 10)
5970 04:41:25.478715 best DQS1 dly(2T, 0.5T) = (0, 10)
5971 04:41:25.481418 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5972 04:41:25.485040 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5973 04:41:25.485114 Pre-setting of DQS Precalculation
5974 04:41:25.491886 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5975 04:41:25.498026 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5976 04:41:25.504609 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5977 04:41:25.504682
5978 04:41:25.504745
5979 04:41:25.507950 [Calibration Summary] 1866 Mbps
5980 04:41:25.511529 CH 0, Rank 0
5981 04:41:25.511598 SW Impedance : PASS
5982 04:41:25.514726 DUTY Scan : NO K
5983 04:41:25.518134 ZQ Calibration : PASS
5984 04:41:25.518204 Jitter Meter : NO K
5985 04:41:25.521423 CBT Training : PASS
5986 04:41:25.524726 Write leveling : PASS
5987 04:41:25.524796 RX DQS gating : PASS
5988 04:41:25.527849 RX DQ/DQS(RDDQC) : PASS
5989 04:41:25.527917 TX DQ/DQS : PASS
5990 04:41:25.531517 RX DATLAT : PASS
5991 04:41:25.534838 RX DQ/DQS(Engine): PASS
5992 04:41:25.534905 TX OE : NO K
5993 04:41:25.538075 All Pass.
5994 04:41:25.538148
5995 04:41:25.538205 CH 0, Rank 1
5996 04:41:25.540966 SW Impedance : PASS
5997 04:41:25.541031 DUTY Scan : NO K
5998 04:41:25.544370 ZQ Calibration : PASS
5999 04:41:25.547866 Jitter Meter : NO K
6000 04:41:25.547940 CBT Training : PASS
6001 04:41:25.550883 Write leveling : PASS
6002 04:41:25.554233 RX DQS gating : PASS
6003 04:41:25.554303 RX DQ/DQS(RDDQC) : PASS
6004 04:41:25.557926 TX DQ/DQS : PASS
6005 04:41:25.560694 RX DATLAT : PASS
6006 04:41:25.560769 RX DQ/DQS(Engine): PASS
6007 04:41:25.564682 TX OE : NO K
6008 04:41:25.564752 All Pass.
6009 04:41:25.564811
6010 04:41:25.567291 CH 1, Rank 0
6011 04:41:25.567358 SW Impedance : PASS
6012 04:41:25.570894 DUTY Scan : NO K
6013 04:41:25.573803 ZQ Calibration : PASS
6014 04:41:25.573875 Jitter Meter : NO K
6015 04:41:25.577743 CBT Training : PASS
6016 04:41:25.580404 Write leveling : PASS
6017 04:41:25.580478 RX DQS gating : PASS
6018 04:41:25.583743 RX DQ/DQS(RDDQC) : PASS
6019 04:41:25.587098 TX DQ/DQS : PASS
6020 04:41:25.587176 RX DATLAT : PASS
6021 04:41:25.590968 RX DQ/DQS(Engine): PASS
6022 04:41:25.593559 TX OE : NO K
6023 04:41:25.593635 All Pass.
6024 04:41:25.593703
6025 04:41:25.593761 CH 1, Rank 1
6026 04:41:25.596956 SW Impedance : PASS
6027 04:41:25.600448 DUTY Scan : NO K
6028 04:41:25.600522 ZQ Calibration : PASS
6029 04:41:25.603544 Jitter Meter : NO K
6030 04:41:25.607240 CBT Training : PASS
6031 04:41:25.607312 Write leveling : PASS
6032 04:41:25.609881 RX DQS gating : PASS
6033 04:41:25.613773 RX DQ/DQS(RDDQC) : PASS
6034 04:41:25.613843 TX DQ/DQS : PASS
6035 04:41:25.616835 RX DATLAT : PASS
6036 04:41:25.616905 RX DQ/DQS(Engine): PASS
6037 04:41:25.619904 TX OE : NO K
6038 04:41:25.619976 All Pass.
6039 04:41:25.620035
6040 04:41:25.623654 DramC Write-DBI off
6041 04:41:25.626273 PER_BANK_REFRESH: Hybrid Mode
6042 04:41:25.626349 TX_TRACKING: ON
6043 04:41:25.636199 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6044 04:41:25.639731 [FAST_K] Save calibration result to emmc
6045 04:41:25.643531 dramc_set_vcore_voltage set vcore to 650000
6046 04:41:25.646127 Read voltage for 400, 6
6047 04:41:25.646198 Vio18 = 0
6048 04:41:25.649681 Vcore = 650000
6049 04:41:25.649756 Vdram = 0
6050 04:41:25.649816 Vddq = 0
6051 04:41:25.652695 Vmddr = 0
6052 04:41:25.656125 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6053 04:41:25.662933 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6054 04:41:25.663015 MEM_TYPE=3, freq_sel=20
6055 04:41:25.666280 sv_algorithm_assistance_LP4_800
6056 04:41:25.669389 ============ PULL DRAM RESETB DOWN ============
6057 04:41:25.676082 ========== PULL DRAM RESETB DOWN end =========
6058 04:41:25.679414 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6059 04:41:25.682680 ===================================
6060 04:41:25.685816 LPDDR4 DRAM CONFIGURATION
6061 04:41:25.688934 ===================================
6062 04:41:25.689004 EX_ROW_EN[0] = 0x0
6063 04:41:25.692291 EX_ROW_EN[1] = 0x0
6064 04:41:25.695851 LP4Y_EN = 0x0
6065 04:41:25.695927 WORK_FSP = 0x0
6066 04:41:25.698715 WL = 0x2
6067 04:41:25.698783 RL = 0x2
6068 04:41:25.702323 BL = 0x2
6069 04:41:25.702395 RPST = 0x0
6070 04:41:25.705306 RD_PRE = 0x0
6071 04:41:25.705374 WR_PRE = 0x1
6072 04:41:25.708674 WR_PST = 0x0
6073 04:41:25.708747 DBI_WR = 0x0
6074 04:41:25.711873 DBI_RD = 0x0
6075 04:41:25.711940 OTF = 0x1
6076 04:41:25.715953 ===================================
6077 04:41:25.718870 ===================================
6078 04:41:25.722113 ANA top config
6079 04:41:25.725193 ===================================
6080 04:41:25.728370 DLL_ASYNC_EN = 0
6081 04:41:25.728469 ALL_SLAVE_EN = 1
6082 04:41:25.731832 NEW_RANK_MODE = 1
6083 04:41:25.735827 DLL_IDLE_MODE = 1
6084 04:41:25.738396 LP45_APHY_COMB_EN = 1
6085 04:41:25.738471 TX_ODT_DIS = 1
6086 04:41:25.741451 NEW_8X_MODE = 1
6087 04:41:25.744897 ===================================
6088 04:41:25.748488 ===================================
6089 04:41:25.751852 data_rate = 800
6090 04:41:25.754894 CKR = 1
6091 04:41:25.758326 DQ_P2S_RATIO = 4
6092 04:41:25.761320 ===================================
6093 04:41:25.764633 CA_P2S_RATIO = 4
6094 04:41:25.764714 DQ_CA_OPEN = 0
6095 04:41:25.768320 DQ_SEMI_OPEN = 1
6096 04:41:25.771997 CA_SEMI_OPEN = 1
6097 04:41:25.774690 CA_FULL_RATE = 0
6098 04:41:25.778154 DQ_CKDIV4_EN = 0
6099 04:41:25.781028 CA_CKDIV4_EN = 1
6100 04:41:25.784588 CA_PREDIV_EN = 0
6101 04:41:25.784669 PH8_DLY = 0
6102 04:41:25.787555 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6103 04:41:25.790794 DQ_AAMCK_DIV = 0
6104 04:41:25.794364 CA_AAMCK_DIV = 0
6105 04:41:25.797761 CA_ADMCK_DIV = 4
6106 04:41:25.800727 DQ_TRACK_CA_EN = 0
6107 04:41:25.800808 CA_PICK = 800
6108 04:41:25.804271 CA_MCKIO = 400
6109 04:41:25.807506 MCKIO_SEMI = 400
6110 04:41:25.811059 PLL_FREQ = 3016
6111 04:41:25.813850 DQ_UI_PI_RATIO = 32
6112 04:41:25.817400 CA_UI_PI_RATIO = 32
6113 04:41:25.820488 ===================================
6114 04:41:25.823715 ===================================
6115 04:41:25.827237 memory_type:LPDDR4
6116 04:41:25.827317 GP_NUM : 10
6117 04:41:25.830634 SRAM_EN : 1
6118 04:41:25.830715 MD32_EN : 0
6119 04:41:25.833844 ===================================
6120 04:41:25.837065 [ANA_INIT] >>>>>>>>>>>>>>
6121 04:41:25.840501 <<<<<< [CONFIGURE PHASE]: ANA_TX
6122 04:41:25.843628 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6123 04:41:25.846804 ===================================
6124 04:41:25.849936 data_rate = 800,PCW = 0X7400
6125 04:41:25.853914 ===================================
6126 04:41:25.856763 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6127 04:41:25.863507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6128 04:41:25.873144 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6129 04:41:25.879867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6130 04:41:25.883266 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6131 04:41:25.886226 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6132 04:41:25.886307 [ANA_INIT] flow start
6133 04:41:25.889873 [ANA_INIT] PLL >>>>>>>>
6134 04:41:25.892620 [ANA_INIT] PLL <<<<<<<<
6135 04:41:25.892781 [ANA_INIT] MIDPI >>>>>>>>
6136 04:41:25.896090 [ANA_INIT] MIDPI <<<<<<<<
6137 04:41:25.899147 [ANA_INIT] DLL >>>>>>>>
6138 04:41:25.899254 [ANA_INIT] flow end
6139 04:41:25.905783 ============ LP4 DIFF to SE enter ============
6140 04:41:25.909766 ============ LP4 DIFF to SE exit ============
6141 04:41:25.912459 [ANA_INIT] <<<<<<<<<<<<<
6142 04:41:25.915775 [Flow] Enable top DCM control >>>>>
6143 04:41:25.919319 [Flow] Enable top DCM control <<<<<
6144 04:41:25.919458 Enable DLL master slave shuffle
6145 04:41:25.925675 ==============================================================
6146 04:41:25.928708 Gating Mode config
6147 04:41:25.932507 ==============================================================
6148 04:41:25.935506 Config description:
6149 04:41:25.945406 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6150 04:41:25.952227 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6151 04:41:25.955343 SELPH_MODE 0: By rank 1: By Phase
6152 04:41:25.961974 ==============================================================
6153 04:41:25.965343 GAT_TRACK_EN = 0
6154 04:41:25.968398 RX_GATING_MODE = 2
6155 04:41:25.971834 RX_GATING_TRACK_MODE = 2
6156 04:41:25.974936 SELPH_MODE = 1
6157 04:41:25.978466 PICG_EARLY_EN = 1
6158 04:41:25.978546 VALID_LAT_VALUE = 1
6159 04:41:25.985025 ==============================================================
6160 04:41:25.988534 Enter into Gating configuration >>>>
6161 04:41:25.991819 Exit from Gating configuration <<<<
6162 04:41:25.994665 Enter into DVFS_PRE_config >>>>>
6163 04:41:26.008117 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6164 04:41:26.008206 Exit from DVFS_PRE_config <<<<<
6165 04:41:26.011182 Enter into PICG configuration >>>>
6166 04:41:26.014651 Exit from PICG configuration <<<<
6167 04:41:26.017887 [RX_INPUT] configuration >>>>>
6168 04:41:26.020975 [RX_INPUT] configuration <<<<<
6169 04:41:26.027894 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6170 04:41:26.030937 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6171 04:41:26.037886 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6172 04:41:26.044426 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6173 04:41:26.050872 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6174 04:41:26.057734 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6175 04:41:26.061202 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6176 04:41:26.064166 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6177 04:41:26.067448 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6178 04:41:26.074297 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6179 04:41:26.077945 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6180 04:41:26.080730 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6181 04:41:26.083939 ===================================
6182 04:41:26.087623 LPDDR4 DRAM CONFIGURATION
6183 04:41:26.090652 ===================================
6184 04:41:26.093876 EX_ROW_EN[0] = 0x0
6185 04:41:26.093958 EX_ROW_EN[1] = 0x0
6186 04:41:26.097372 LP4Y_EN = 0x0
6187 04:41:26.097483 WORK_FSP = 0x0
6188 04:41:26.100952 WL = 0x2
6189 04:41:26.101033 RL = 0x2
6190 04:41:26.103858 BL = 0x2
6191 04:41:26.103970 RPST = 0x0
6192 04:41:26.107468 RD_PRE = 0x0
6193 04:41:26.107549 WR_PRE = 0x1
6194 04:41:26.110372 WR_PST = 0x0
6195 04:41:26.110452 DBI_WR = 0x0
6196 04:41:26.113894 DBI_RD = 0x0
6197 04:41:26.113978 OTF = 0x1
6198 04:41:26.117226 ===================================
6199 04:41:26.123578 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6200 04:41:26.127293 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6201 04:41:26.130184 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6202 04:41:26.133570 ===================================
6203 04:41:26.136905 LPDDR4 DRAM CONFIGURATION
6204 04:41:26.140556 ===================================
6205 04:41:26.143401 EX_ROW_EN[0] = 0x10
6206 04:41:26.143482 EX_ROW_EN[1] = 0x0
6207 04:41:26.146636 LP4Y_EN = 0x0
6208 04:41:26.146717 WORK_FSP = 0x0
6209 04:41:26.149981 WL = 0x2
6210 04:41:26.150103 RL = 0x2
6211 04:41:26.153331 BL = 0x2
6212 04:41:26.153411 RPST = 0x0
6213 04:41:26.156770 RD_PRE = 0x0
6214 04:41:26.156919 WR_PRE = 0x1
6215 04:41:26.159879 WR_PST = 0x0
6216 04:41:26.159960 DBI_WR = 0x0
6217 04:41:26.163074 DBI_RD = 0x0
6218 04:41:26.163155 OTF = 0x1
6219 04:41:26.166916 ===================================
6220 04:41:26.173011 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6221 04:41:26.177747 nWR fixed to 30
6222 04:41:26.181319 [ModeRegInit_LP4] CH0 RK0
6223 04:41:26.181419 [ModeRegInit_LP4] CH0 RK1
6224 04:41:26.184732 [ModeRegInit_LP4] CH1 RK0
6225 04:41:26.187655 [ModeRegInit_LP4] CH1 RK1
6226 04:41:26.187736 match AC timing 19
6227 04:41:26.194608 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6228 04:41:26.197685 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6229 04:41:26.200751 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6230 04:41:26.207306 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6231 04:41:26.210944 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6232 04:41:26.211020 ==
6233 04:41:26.214520 Dram Type= 6, Freq= 0, CH_0, rank 0
6234 04:41:26.217381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6235 04:41:26.217453 ==
6236 04:41:26.224464 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6237 04:41:26.230981 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6238 04:41:26.234077 [CA 0] Center 36 (8~64) winsize 57
6239 04:41:26.237252 [CA 1] Center 36 (8~64) winsize 57
6240 04:41:26.241118 [CA 2] Center 36 (8~64) winsize 57
6241 04:41:26.243895 [CA 3] Center 36 (8~64) winsize 57
6242 04:41:26.247499 [CA 4] Center 36 (8~64) winsize 57
6243 04:41:26.250818 [CA 5] Center 36 (8~64) winsize 57
6244 04:41:26.250929
6245 04:41:26.253697 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6246 04:41:26.253794
6247 04:41:26.257404 [CATrainingPosCal] consider 1 rank data
6248 04:41:26.260240 u2DelayCellTimex100 = 270/100 ps
6249 04:41:26.263812 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 04:41:26.267200 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 04:41:26.270049 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 04:41:26.273329 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 04:41:26.276770 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 04:41:26.279967 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 04:41:26.280069
6256 04:41:26.286668 CA PerBit enable=1, Macro0, CA PI delay=36
6257 04:41:26.286768
6258 04:41:26.286865 [CBTSetCACLKResult] CA Dly = 36
6259 04:41:26.289897 CS Dly: 1 (0~32)
6260 04:41:26.289978 ==
6261 04:41:26.293461 Dram Type= 6, Freq= 0, CH_0, rank 1
6262 04:41:26.296528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 04:41:26.296610 ==
6264 04:41:26.303106 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6265 04:41:26.310243 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6266 04:41:26.312850 [CA 0] Center 36 (8~64) winsize 57
6267 04:41:26.316496 [CA 1] Center 36 (8~64) winsize 57
6268 04:41:26.319585 [CA 2] Center 36 (8~64) winsize 57
6269 04:41:26.322654 [CA 3] Center 36 (8~64) winsize 57
6270 04:41:26.326318 [CA 4] Center 36 (8~64) winsize 57
6271 04:41:26.326410 [CA 5] Center 36 (8~64) winsize 57
6272 04:41:26.329657
6273 04:41:26.332769 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6274 04:41:26.332841
6275 04:41:26.335928 [CATrainingPosCal] consider 2 rank data
6276 04:41:26.339589 u2DelayCellTimex100 = 270/100 ps
6277 04:41:26.342437 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 04:41:26.345905 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 04:41:26.349168 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 04:41:26.352516 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 04:41:26.355638 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 04:41:26.359036 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 04:41:26.359117
6284 04:41:26.362191 CA PerBit enable=1, Macro0, CA PI delay=36
6285 04:41:26.365479
6286 04:41:26.365560 [CBTSetCACLKResult] CA Dly = 36
6287 04:41:26.368703 CS Dly: 1 (0~32)
6288 04:41:26.368784
6289 04:41:26.372233 ----->DramcWriteLeveling(PI) begin...
6290 04:41:26.372314 ==
6291 04:41:26.375190 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 04:41:26.379035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 04:41:26.379116 ==
6294 04:41:26.381817 Write leveling (Byte 0): 40 => 8
6295 04:41:26.385132 Write leveling (Byte 1): 40 => 8
6296 04:41:26.388621 DramcWriteLeveling(PI) end<-----
6297 04:41:26.388702
6298 04:41:26.388794 ==
6299 04:41:26.391998 Dram Type= 6, Freq= 0, CH_0, rank 0
6300 04:41:26.394803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 04:41:26.398649 ==
6302 04:41:26.398730 [Gating] SW mode calibration
6303 04:41:26.408532 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6304 04:41:26.411302 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6305 04:41:26.414707 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6306 04:41:26.421387 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6307 04:41:26.425056 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 04:41:26.427915 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6309 04:41:26.434853 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 04:41:26.437801 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 04:41:26.441305 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 04:41:26.448123 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 04:41:26.450960 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6314 04:41:26.454374 Total UI for P1: 0, mck2ui 16
6315 04:41:26.457868 best dqsien dly found for B0: ( 0, 14, 24)
6316 04:41:26.461167 Total UI for P1: 0, mck2ui 16
6317 04:41:26.464358 best dqsien dly found for B1: ( 0, 14, 24)
6318 04:41:26.467538 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6319 04:41:26.471116 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6320 04:41:26.471215
6321 04:41:26.474152 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6322 04:41:26.480952 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6323 04:41:26.481060 [Gating] SW calibration Done
6324 04:41:26.481152 ==
6325 04:41:26.483741 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 04:41:26.490756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 04:41:26.490841 ==
6328 04:41:26.490905 RX Vref Scan: 0
6329 04:41:26.490964
6330 04:41:26.493716 RX Vref 0 -> 0, step: 1
6331 04:41:26.493801
6332 04:41:26.497589 RX Delay -410 -> 252, step: 16
6333 04:41:26.500665 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6334 04:41:26.503899 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6335 04:41:26.510843 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6336 04:41:26.513724 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6337 04:41:26.516908 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6338 04:41:26.520233 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6339 04:41:26.527083 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6340 04:41:26.530004 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6341 04:41:26.533533 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6342 04:41:26.536631 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6343 04:41:26.543320 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6344 04:41:26.546920 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6345 04:41:26.549847 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6346 04:41:26.556865 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6347 04:41:26.559560 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6348 04:41:26.563107 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6349 04:41:26.563187 ==
6350 04:41:26.566305 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 04:41:26.569992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 04:41:26.573085 ==
6353 04:41:26.573183 DQS Delay:
6354 04:41:26.573248 DQS0 = 43, DQS1 = 51
6355 04:41:26.576011 DQM Delay:
6356 04:41:26.576111 DQM0 = 12, DQM1 = 9
6357 04:41:26.579574 DQ Delay:
6358 04:41:26.579649 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6359 04:41:26.582730 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6360 04:41:26.586056 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6361 04:41:26.589556 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6362 04:41:26.589656
6363 04:41:26.589747
6364 04:41:26.592473 ==
6365 04:41:26.595981 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 04:41:26.599050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 04:41:26.599149 ==
6368 04:41:26.599239
6369 04:41:26.599327
6370 04:41:26.602999 TX Vref Scan disable
6371 04:41:26.603097 == TX Byte 0 ==
6372 04:41:26.605797 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6373 04:41:26.612203 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6374 04:41:26.612284 == TX Byte 1 ==
6375 04:41:26.615996 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 04:41:26.622220 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 04:41:26.622324 ==
6378 04:41:26.625739 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 04:41:26.628841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 04:41:26.628941 ==
6381 04:41:26.629033
6382 04:41:26.629119
6383 04:41:26.632646 TX Vref Scan disable
6384 04:41:26.632723 == TX Byte 0 ==
6385 04:41:26.635842 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 04:41:26.642350 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 04:41:26.642449 == TX Byte 1 ==
6388 04:41:26.645313 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 04:41:26.651821 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 04:41:26.651927
6391 04:41:26.652021 [DATLAT]
6392 04:41:26.652115 Freq=400, CH0 RK0
6393 04:41:26.655270
6394 04:41:26.655393 DATLAT Default: 0xf
6395 04:41:26.658522 0, 0xFFFF, sum = 0
6396 04:41:26.658596 1, 0xFFFF, sum = 0
6397 04:41:26.661591 2, 0xFFFF, sum = 0
6398 04:41:26.661663 3, 0xFFFF, sum = 0
6399 04:41:26.665024 4, 0xFFFF, sum = 0
6400 04:41:26.665123 5, 0xFFFF, sum = 0
6401 04:41:26.668768 6, 0xFFFF, sum = 0
6402 04:41:26.668842 7, 0xFFFF, sum = 0
6403 04:41:26.671675 8, 0xFFFF, sum = 0
6404 04:41:26.671750 9, 0xFFFF, sum = 0
6405 04:41:26.675030 10, 0xFFFF, sum = 0
6406 04:41:26.675129 11, 0xFFFF, sum = 0
6407 04:41:26.678279 12, 0xFFFF, sum = 0
6408 04:41:26.678351 13, 0x0, sum = 1
6409 04:41:26.681794 14, 0x0, sum = 2
6410 04:41:26.681867 15, 0x0, sum = 3
6411 04:41:26.685339 16, 0x0, sum = 4
6412 04:41:26.685413 best_step = 14
6413 04:41:26.685473
6414 04:41:26.685530 ==
6415 04:41:26.688171 Dram Type= 6, Freq= 0, CH_0, rank 0
6416 04:41:26.694904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 04:41:26.695008 ==
6418 04:41:26.695100 RX Vref Scan: 1
6419 04:41:26.695189
6420 04:41:26.697907 RX Vref 0 -> 0, step: 1
6421 04:41:26.698002
6422 04:41:26.701583 RX Delay -343 -> 252, step: 8
6423 04:41:26.701658
6424 04:41:26.704485 Set Vref, RX VrefLevel [Byte0]: 51
6425 04:41:26.707722 [Byte1]: 47
6426 04:41:26.711480
6427 04:41:26.711573 Final RX Vref Byte 0 = 51 to rank0
6428 04:41:26.714899 Final RX Vref Byte 1 = 47 to rank0
6429 04:41:26.717948 Final RX Vref Byte 0 = 51 to rank1
6430 04:41:26.721215 Final RX Vref Byte 1 = 47 to rank1==
6431 04:41:26.724490 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 04:41:26.730878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 04:41:26.730960 ==
6434 04:41:26.731027 DQS Delay:
6435 04:41:26.734262 DQS0 = 44, DQS1 = 60
6436 04:41:26.734341 DQM Delay:
6437 04:41:26.737575 DQM0 = 10, DQM1 = 18
6438 04:41:26.737654 DQ Delay:
6439 04:41:26.740563 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6440 04:41:26.743929 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6441 04:41:26.747312 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6442 04:41:26.750732 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6443 04:41:26.750820
6444 04:41:26.750883
6445 04:41:26.757322 [DQSOSCAuto] RK0, (LSB)MR18= 0x9689, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6446 04:41:26.760891 CH0 RK0: MR19=C0C, MR18=9689
6447 04:41:26.767622 CH0_RK0: MR19=0xC0C, MR18=0x9689, DQSOSC=391, MR23=63, INC=386, DEC=257
6448 04:41:26.767704 ==
6449 04:41:26.770529 Dram Type= 6, Freq= 0, CH_0, rank 1
6450 04:41:26.774145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 04:41:26.774226 ==
6452 04:41:26.777236 [Gating] SW mode calibration
6453 04:41:26.783649 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6454 04:41:26.790346 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6455 04:41:26.793525 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6456 04:41:26.797263 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6457 04:41:26.803696 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 04:41:26.806624 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6459 04:41:26.810229 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 04:41:26.816705 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 04:41:26.820031 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 04:41:26.823299 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 04:41:26.830359 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6464 04:41:26.833243 Total UI for P1: 0, mck2ui 16
6465 04:41:26.836610 best dqsien dly found for B0: ( 0, 14, 24)
6466 04:41:26.840205 Total UI for P1: 0, mck2ui 16
6467 04:41:26.843434 best dqsien dly found for B1: ( 0, 14, 24)
6468 04:41:26.846668 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6469 04:41:26.849915 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6470 04:41:26.849997
6471 04:41:26.852871 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6472 04:41:26.856555 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6473 04:41:26.859987 [Gating] SW calibration Done
6474 04:41:26.860069 ==
6475 04:41:26.862665 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 04:41:26.866374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 04:41:26.866462 ==
6478 04:41:26.869227 RX Vref Scan: 0
6479 04:41:26.869310
6480 04:41:26.872646 RX Vref 0 -> 0, step: 1
6481 04:41:26.872725
6482 04:41:26.872789 RX Delay -410 -> 252, step: 16
6483 04:41:26.879916 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6484 04:41:26.882621 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6485 04:41:26.886179 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6486 04:41:26.892798 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6487 04:41:26.896047 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6488 04:41:26.899458 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6489 04:41:26.902527 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6490 04:41:26.908949 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6491 04:41:26.912648 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6492 04:41:26.915761 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6493 04:41:26.919242 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6494 04:41:26.925812 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6495 04:41:26.928729 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6496 04:41:26.931969 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6497 04:41:26.935923 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6498 04:41:26.942037 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6499 04:41:26.942121 ==
6500 04:41:26.945766 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 04:41:26.948484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 04:41:26.948573 ==
6503 04:41:26.948640 DQS Delay:
6504 04:41:26.951838 DQS0 = 35, DQS1 = 59
6505 04:41:26.951937 DQM Delay:
6506 04:41:26.955716 DQM0 = 10, DQM1 = 17
6507 04:41:26.955816 DQ Delay:
6508 04:41:26.958434 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6509 04:41:26.962003 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6510 04:41:26.964928 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6511 04:41:26.968742 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6512 04:41:26.968824
6513 04:41:26.968888
6514 04:41:26.968948 ==
6515 04:41:26.971660 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 04:41:26.974898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 04:41:26.974981 ==
6518 04:41:26.978704
6519 04:41:26.978811
6520 04:41:26.978903 TX Vref Scan disable
6521 04:41:26.981973 == TX Byte 0 ==
6522 04:41:26.984900 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6523 04:41:26.988287 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6524 04:41:26.991820 == TX Byte 1 ==
6525 04:41:26.995158 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6526 04:41:26.998625 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6527 04:41:26.998707 ==
6528 04:41:27.001931 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 04:41:27.005325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 04:41:27.005410 ==
6531 04:41:27.008595
6532 04:41:27.008690
6533 04:41:27.008768 TX Vref Scan disable
6534 04:41:27.011694 == TX Byte 0 ==
6535 04:41:27.014772 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6536 04:41:27.018186 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6537 04:41:27.021679 == TX Byte 1 ==
6538 04:41:27.025083 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6539 04:41:27.028872 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6540 04:41:27.028986
6541 04:41:27.029050 [DATLAT]
6542 04:41:27.031611 Freq=400, CH0 RK1
6543 04:41:27.031693
6544 04:41:27.034864 DATLAT Default: 0xe
6545 04:41:27.034945 0, 0xFFFF, sum = 0
6546 04:41:27.038124 1, 0xFFFF, sum = 0
6547 04:41:27.038207 2, 0xFFFF, sum = 0
6548 04:41:27.041428 3, 0xFFFF, sum = 0
6549 04:41:27.041548 4, 0xFFFF, sum = 0
6550 04:41:27.044497 5, 0xFFFF, sum = 0
6551 04:41:27.044580 6, 0xFFFF, sum = 0
6552 04:41:27.047845 7, 0xFFFF, sum = 0
6553 04:41:27.047928 8, 0xFFFF, sum = 0
6554 04:41:27.051152 9, 0xFFFF, sum = 0
6555 04:41:27.051234 10, 0xFFFF, sum = 0
6556 04:41:27.055156 11, 0xFFFF, sum = 0
6557 04:41:27.055238 12, 0xFFFF, sum = 0
6558 04:41:27.057921 13, 0x0, sum = 1
6559 04:41:27.058036 14, 0x0, sum = 2
6560 04:41:27.061136 15, 0x0, sum = 3
6561 04:41:27.061238 16, 0x0, sum = 4
6562 04:41:27.064151 best_step = 14
6563 04:41:27.064251
6564 04:41:27.064341 ==
6565 04:41:27.068072 Dram Type= 6, Freq= 0, CH_0, rank 1
6566 04:41:27.071156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 04:41:27.071224 ==
6568 04:41:27.073953 RX Vref Scan: 0
6569 04:41:27.074023
6570 04:41:27.074083 RX Vref 0 -> 0, step: 1
6571 04:41:27.074140
6572 04:41:27.077732 RX Delay -359 -> 252, step: 8
6573 04:41:27.085856 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6574 04:41:27.088751 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6575 04:41:27.092202 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6576 04:41:27.098807 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6577 04:41:27.102229 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6578 04:41:27.105790 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6579 04:41:27.108759 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6580 04:41:27.115434 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6581 04:41:27.119076 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6582 04:41:27.121862 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6583 04:41:27.125026 iDelay=209, Bit 10, Center -40 (-279 ~ 200) 480
6584 04:41:27.131591 iDelay=209, Bit 11, Center -48 (-287 ~ 192) 480
6585 04:41:27.135021 iDelay=209, Bit 12, Center -40 (-279 ~ 200) 480
6586 04:41:27.138359 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6587 04:41:27.141818 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6588 04:41:27.147948 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6589 04:41:27.148049 ==
6590 04:41:27.151771 Dram Type= 6, Freq= 0, CH_0, rank 1
6591 04:41:27.154974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 04:41:27.155080 ==
6593 04:41:27.155173 DQS Delay:
6594 04:41:27.158320 DQS0 = 44, DQS1 = 60
6595 04:41:27.158419 DQM Delay:
6596 04:41:27.161629 DQM0 = 9, DQM1 = 16
6597 04:41:27.161734 DQ Delay:
6598 04:41:27.164827 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6599 04:41:27.168179 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6600 04:41:27.171559 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6601 04:41:27.174531 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6602 04:41:27.174634
6603 04:41:27.174754
6604 04:41:27.184584 [DQSOSCAuto] RK1, (LSB)MR18= 0x8c85, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6605 04:41:27.184692 CH0 RK1: MR19=C0C, MR18=8C85
6606 04:41:27.190985 CH0_RK1: MR19=0xC0C, MR18=0x8C85, DQSOSC=392, MR23=63, INC=384, DEC=256
6607 04:41:27.194630 [RxdqsGatingPostProcess] freq 400
6608 04:41:27.200798 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6609 04:41:27.204465 best DQS0 dly(2T, 0.5T) = (0, 10)
6610 04:41:27.207234 best DQS1 dly(2T, 0.5T) = (0, 10)
6611 04:41:27.211011 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6612 04:41:27.214231 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6613 04:41:27.217446 best DQS0 dly(2T, 0.5T) = (0, 10)
6614 04:41:27.220741 best DQS1 dly(2T, 0.5T) = (0, 10)
6615 04:41:27.224035 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6616 04:41:27.224132 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6617 04:41:27.227466 Pre-setting of DQS Precalculation
6618 04:41:27.233710 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6619 04:41:27.233793 ==
6620 04:41:27.237228 Dram Type= 6, Freq= 0, CH_1, rank 0
6621 04:41:27.240375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 04:41:27.240471 ==
6623 04:41:27.246912 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6624 04:41:27.254218 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6625 04:41:27.257037 [CA 0] Center 36 (8~64) winsize 57
6626 04:41:27.260397 [CA 1] Center 36 (8~64) winsize 57
6627 04:41:27.263955 [CA 2] Center 36 (8~64) winsize 57
6628 04:41:27.266748 [CA 3] Center 36 (8~64) winsize 57
6629 04:41:27.266829 [CA 4] Center 36 (8~64) winsize 57
6630 04:41:27.270332 [CA 5] Center 36 (8~64) winsize 57
6631 04:41:27.270440
6632 04:41:27.276828 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6633 04:41:27.276924
6634 04:41:27.280049 [CATrainingPosCal] consider 1 rank data
6635 04:41:27.283220 u2DelayCellTimex100 = 270/100 ps
6636 04:41:27.286770 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 04:41:27.289762 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 04:41:27.293626 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 04:41:27.296993 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 04:41:27.299891 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 04:41:27.303371 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 04:41:27.303469
6643 04:41:27.306341 CA PerBit enable=1, Macro0, CA PI delay=36
6644 04:41:27.306438
6645 04:41:27.309840 [CBTSetCACLKResult] CA Dly = 36
6646 04:41:27.313146 CS Dly: 1 (0~32)
6647 04:41:27.313229 ==
6648 04:41:27.316360 Dram Type= 6, Freq= 0, CH_1, rank 1
6649 04:41:27.319472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 04:41:27.319554 ==
6651 04:41:27.326349 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6652 04:41:27.332854 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6653 04:41:27.336121 [CA 0] Center 36 (8~64) winsize 57
6654 04:41:27.339183 [CA 1] Center 36 (8~64) winsize 57
6655 04:41:27.339304 [CA 2] Center 36 (8~64) winsize 57
6656 04:41:27.342939 [CA 3] Center 36 (8~64) winsize 57
6657 04:41:27.346599 [CA 4] Center 36 (8~64) winsize 57
6658 04:41:27.349333 [CA 5] Center 36 (8~64) winsize 57
6659 04:41:27.349415
6660 04:41:27.352696 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6661 04:41:27.352811
6662 04:41:27.359510 [CATrainingPosCal] consider 2 rank data
6663 04:41:27.359592 u2DelayCellTimex100 = 270/100 ps
6664 04:41:27.366162 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 04:41:27.369000 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 04:41:27.373146 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 04:41:27.375988 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 04:41:27.379513 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 04:41:27.382585 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 04:41:27.382693
6671 04:41:27.385410 CA PerBit enable=1, Macro0, CA PI delay=36
6672 04:41:27.385492
6673 04:41:27.388893 [CBTSetCACLKResult] CA Dly = 36
6674 04:41:27.392320 CS Dly: 1 (0~32)
6675 04:41:27.392444
6676 04:41:27.395873 ----->DramcWriteLeveling(PI) begin...
6677 04:41:27.395956 ==
6678 04:41:27.399049 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 04:41:27.401941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 04:41:27.402024 ==
6681 04:41:27.405653 Write leveling (Byte 0): 40 => 8
6682 04:41:27.408881 Write leveling (Byte 1): 40 => 8
6683 04:41:27.411862 DramcWriteLeveling(PI) end<-----
6684 04:41:27.411943
6685 04:41:27.412007 ==
6686 04:41:27.415546 Dram Type= 6, Freq= 0, CH_1, rank 0
6687 04:41:27.418935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 04:41:27.419017 ==
6689 04:41:27.421947 [Gating] SW mode calibration
6690 04:41:27.428499 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6691 04:41:27.435425 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6692 04:41:27.438431 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6693 04:41:27.444901 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6694 04:41:27.448610 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 04:41:27.451190 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6696 04:41:27.458304 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 04:41:27.461386 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 04:41:27.464387 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 04:41:27.471182 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 04:41:27.474357 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6701 04:41:27.477688 Total UI for P1: 0, mck2ui 16
6702 04:41:27.481156 best dqsien dly found for B0: ( 0, 14, 24)
6703 04:41:27.484303 Total UI for P1: 0, mck2ui 16
6704 04:41:27.487729 best dqsien dly found for B1: ( 0, 14, 24)
6705 04:41:27.490697 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6706 04:41:27.494328 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6707 04:41:27.494432
6708 04:41:27.497277 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6709 04:41:27.500726 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6710 04:41:27.504295 [Gating] SW calibration Done
6711 04:41:27.504402 ==
6712 04:41:27.507158 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 04:41:27.510596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 04:41:27.514165 ==
6715 04:41:27.514247 RX Vref Scan: 0
6716 04:41:27.514311
6717 04:41:27.517112 RX Vref 0 -> 0, step: 1
6718 04:41:27.517193
6719 04:41:27.520510 RX Delay -410 -> 252, step: 16
6720 04:41:27.523775 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6721 04:41:27.527196 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6722 04:41:27.530071 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6723 04:41:27.537098 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6724 04:41:27.540171 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6725 04:41:27.543317 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6726 04:41:27.549895 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6727 04:41:27.553488 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6728 04:41:27.556896 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6729 04:41:27.559752 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6730 04:41:27.566581 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6731 04:41:27.569636 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6732 04:41:27.573026 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6733 04:41:27.576461 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6734 04:41:27.582821 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6735 04:41:27.586269 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6736 04:41:27.586346 ==
6737 04:41:27.589771 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 04:41:27.592890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 04:41:27.592964 ==
6740 04:41:27.596258 DQS Delay:
6741 04:41:27.596335 DQS0 = 43, DQS1 = 51
6742 04:41:27.599553 DQM Delay:
6743 04:41:27.599630 DQM0 = 13, DQM1 = 13
6744 04:41:27.599692 DQ Delay:
6745 04:41:27.602770 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6746 04:41:27.606118 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6747 04:41:27.609622 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6748 04:41:27.612466 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6749 04:41:27.612538
6750 04:41:27.612599
6751 04:41:27.612657 ==
6752 04:41:27.615961 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 04:41:27.622513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 04:41:27.622595 ==
6755 04:41:27.622660
6756 04:41:27.622750
6757 04:41:27.622846 TX Vref Scan disable
6758 04:41:27.625933 == TX Byte 0 ==
6759 04:41:27.629182 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 04:41:27.632098 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 04:41:27.635785 == TX Byte 1 ==
6762 04:41:27.639199 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 04:41:27.642218 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 04:41:27.645855 ==
6765 04:41:27.648890 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 04:41:27.652039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 04:41:27.652115 ==
6768 04:41:27.652198
6769 04:41:27.652275
6770 04:41:27.655277 TX Vref Scan disable
6771 04:41:27.655401 == TX Byte 0 ==
6772 04:41:27.658603 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 04:41:27.665030 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 04:41:27.665125 == TX Byte 1 ==
6775 04:41:27.668762 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 04:41:27.675137 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 04:41:27.675271
6778 04:41:27.675408 [DATLAT]
6779 04:41:27.675491 Freq=400, CH1 RK0
6780 04:41:27.675569
6781 04:41:27.678185 DATLAT Default: 0xf
6782 04:41:27.681698 0, 0xFFFF, sum = 0
6783 04:41:27.681778 1, 0xFFFF, sum = 0
6784 04:41:27.684764 2, 0xFFFF, sum = 0
6785 04:41:27.684842 3, 0xFFFF, sum = 0
6786 04:41:27.688084 4, 0xFFFF, sum = 0
6787 04:41:27.688168 5, 0xFFFF, sum = 0
6788 04:41:27.691529 6, 0xFFFF, sum = 0
6789 04:41:27.691606 7, 0xFFFF, sum = 0
6790 04:41:27.694836 8, 0xFFFF, sum = 0
6791 04:41:27.694959 9, 0xFFFF, sum = 0
6792 04:41:27.698177 10, 0xFFFF, sum = 0
6793 04:41:27.698260 11, 0xFFFF, sum = 0
6794 04:41:27.701705 12, 0xFFFF, sum = 0
6795 04:41:27.701813 13, 0x0, sum = 1
6796 04:41:27.704853 14, 0x0, sum = 2
6797 04:41:27.704928 15, 0x0, sum = 3
6798 04:41:27.708162 16, 0x0, sum = 4
6799 04:41:27.708238 best_step = 14
6800 04:41:27.708316
6801 04:41:27.708390 ==
6802 04:41:27.711422 Dram Type= 6, Freq= 0, CH_1, rank 0
6803 04:41:27.718075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 04:41:27.718155 ==
6805 04:41:27.718241 RX Vref Scan: 1
6806 04:41:27.718319
6807 04:41:27.721633 RX Vref 0 -> 0, step: 1
6808 04:41:27.721710
6809 04:41:27.724544 RX Delay -343 -> 252, step: 8
6810 04:41:27.724620
6811 04:41:27.727900 Set Vref, RX VrefLevel [Byte0]: 54
6812 04:41:27.731470 [Byte1]: 53
6813 04:41:27.731553
6814 04:41:27.734424 Final RX Vref Byte 0 = 54 to rank0
6815 04:41:27.738023 Final RX Vref Byte 1 = 53 to rank0
6816 04:41:27.741139 Final RX Vref Byte 0 = 54 to rank1
6817 04:41:27.744195 Final RX Vref Byte 1 = 53 to rank1==
6818 04:41:27.747669 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 04:41:27.750682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 04:41:27.754638 ==
6821 04:41:27.754717 DQS Delay:
6822 04:41:27.754803 DQS0 = 44, DQS1 = 52
6823 04:41:27.757476 DQM Delay:
6824 04:41:27.757589 DQM0 = 10, DQM1 = 9
6825 04:41:27.760871 DQ Delay:
6826 04:41:27.760947 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6827 04:41:27.763874 DQ4 =4, DQ5 =20, DQ6 =20, DQ7 =4
6828 04:41:27.767377 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6829 04:41:27.770708 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6830 04:41:27.770785
6831 04:41:27.770866
6832 04:41:27.780756 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a91, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6833 04:41:27.784093 CH1 RK0: MR19=C0C, MR18=6A91
6834 04:41:27.790388 CH1_RK0: MR19=0xC0C, MR18=0x6A91, DQSOSC=391, MR23=63, INC=386, DEC=257
6835 04:41:27.790469 ==
6836 04:41:27.793798 Dram Type= 6, Freq= 0, CH_1, rank 1
6837 04:41:27.797127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 04:41:27.797215 ==
6839 04:41:27.800820 [Gating] SW mode calibration
6840 04:41:27.806765 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6841 04:41:27.813708 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6842 04:41:27.816808 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6843 04:41:27.820150 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6844 04:41:27.826827 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 04:41:27.830126 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6846 04:41:27.833004 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 04:41:27.840069 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 04:41:27.843756 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 04:41:27.846474 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 04:41:27.852806 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6851 04:41:27.852890 Total UI for P1: 0, mck2ui 16
6852 04:41:27.856325 best dqsien dly found for B0: ( 0, 14, 24)
6853 04:41:27.859839 Total UI for P1: 0, mck2ui 16
6854 04:41:27.863070 best dqsien dly found for B1: ( 0, 14, 24)
6855 04:41:27.869505 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6856 04:41:27.872903 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6857 04:41:27.872983
6858 04:41:27.876240 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6859 04:41:27.879219 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6860 04:41:27.882602 [Gating] SW calibration Done
6861 04:41:27.882677 ==
6862 04:41:27.885520 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 04:41:27.889043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 04:41:27.889117 ==
6865 04:41:27.892997 RX Vref Scan: 0
6866 04:41:27.893096
6867 04:41:27.893177 RX Vref 0 -> 0, step: 1
6868 04:41:27.893256
6869 04:41:27.895593 RX Delay -410 -> 252, step: 16
6870 04:41:27.901952 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6871 04:41:27.905220 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6872 04:41:27.908482 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6873 04:41:27.912263 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6874 04:41:27.918767 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6875 04:41:27.921760 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6876 04:41:27.925189 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6877 04:41:27.928620 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6878 04:41:27.935015 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6879 04:41:27.938556 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6880 04:41:27.941719 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6881 04:41:27.948812 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6882 04:41:27.951558 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6883 04:41:27.955052 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6884 04:41:27.958002 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6885 04:41:27.964566 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6886 04:41:27.964649 ==
6887 04:41:27.967996 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 04:41:27.971754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 04:41:27.971836 ==
6890 04:41:27.971918 DQS Delay:
6891 04:41:27.974996 DQS0 = 43, DQS1 = 51
6892 04:41:27.975100 DQM Delay:
6893 04:41:27.978265 DQM0 = 11, DQM1 = 14
6894 04:41:27.978377 DQ Delay:
6895 04:41:27.981434 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6896 04:41:27.984912 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6897 04:41:27.987716 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6898 04:41:27.991336 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6899 04:41:27.991438
6900 04:41:27.991501
6901 04:41:27.991560 ==
6902 04:41:27.994502 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 04:41:27.997740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 04:41:27.997825 ==
6905 04:41:27.997918
6906 04:41:27.998008
6907 04:41:28.001456 TX Vref Scan disable
6908 04:41:28.004331 == TX Byte 0 ==
6909 04:41:28.007984 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6910 04:41:28.011330 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6911 04:41:28.014044 == TX Byte 1 ==
6912 04:41:28.017349 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6913 04:41:28.020829 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6914 04:41:28.020911 ==
6915 04:41:28.024258 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 04:41:28.027876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 04:41:28.027958 ==
6918 04:41:28.030868
6919 04:41:28.030980
6920 04:41:28.031077 TX Vref Scan disable
6921 04:41:28.034302 == TX Byte 0 ==
6922 04:41:28.037026 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6923 04:41:28.040328 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6924 04:41:28.043909 == TX Byte 1 ==
6925 04:41:28.047139 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6926 04:41:28.050609 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6927 04:41:28.050690
6928 04:41:28.050754 [DATLAT]
6929 04:41:28.053740 Freq=400, CH1 RK1
6930 04:41:28.053847
6931 04:41:28.057259 DATLAT Default: 0xe
6932 04:41:28.057447 0, 0xFFFF, sum = 0
6933 04:41:28.060212 1, 0xFFFF, sum = 0
6934 04:41:28.060298 2, 0xFFFF, sum = 0
6935 04:41:28.063784 3, 0xFFFF, sum = 0
6936 04:41:28.063897 4, 0xFFFF, sum = 0
6937 04:41:28.067063 5, 0xFFFF, sum = 0
6938 04:41:28.067188 6, 0xFFFF, sum = 0
6939 04:41:28.070448 7, 0xFFFF, sum = 0
6940 04:41:28.070534 8, 0xFFFF, sum = 0
6941 04:41:28.073699 9, 0xFFFF, sum = 0
6942 04:41:28.073808 10, 0xFFFF, sum = 0
6943 04:41:28.076943 11, 0xFFFF, sum = 0
6944 04:41:28.077039 12, 0xFFFF, sum = 0
6945 04:41:28.079882 13, 0x0, sum = 1
6946 04:41:28.079991 14, 0x0, sum = 2
6947 04:41:28.083891 15, 0x0, sum = 3
6948 04:41:28.083973 16, 0x0, sum = 4
6949 04:41:28.087092 best_step = 14
6950 04:41:28.087199
6951 04:41:28.087291 ==
6952 04:41:28.089742 Dram Type= 6, Freq= 0, CH_1, rank 1
6953 04:41:28.093109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6954 04:41:28.093192 ==
6955 04:41:28.096838 RX Vref Scan: 0
6956 04:41:28.096920
6957 04:41:28.096983 RX Vref 0 -> 0, step: 1
6958 04:41:28.097043
6959 04:41:28.099587 RX Delay -343 -> 252, step: 8
6960 04:41:28.108619 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6961 04:41:28.111887 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6962 04:41:28.115049 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6963 04:41:28.117903 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6964 04:41:28.124655 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6965 04:41:28.128047 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6966 04:41:28.131533 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6967 04:41:28.137645 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6968 04:41:28.141560 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6969 04:41:28.144097 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6970 04:41:28.147587 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6971 04:41:28.154017 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6972 04:41:28.157614 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6973 04:41:28.160624 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6974 04:41:28.164144 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6975 04:41:28.171054 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6976 04:41:28.171142 ==
6977 04:41:28.173815 Dram Type= 6, Freq= 0, CH_1, rank 1
6978 04:41:28.177579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6979 04:41:28.177657 ==
6980 04:41:28.177741 DQS Delay:
6981 04:41:28.180911 DQS0 = 48, DQS1 = 52
6982 04:41:28.180986 DQM Delay:
6983 04:41:28.183924 DQM0 = 12, DQM1 = 11
6984 04:41:28.183996 DQ Delay:
6985 04:41:28.187512 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6986 04:41:28.190366 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6987 04:41:28.193765 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6988 04:41:28.197028 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6989 04:41:28.197111
6990 04:41:28.197194
6991 04:41:28.206806 [DQSOSCAuto] RK1, (LSB)MR18= 0x71a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
6992 04:41:28.206889 CH1 RK1: MR19=C0C, MR18=71A8
6993 04:41:28.213764 CH1_RK1: MR19=0xC0C, MR18=0x71A8, DQSOSC=388, MR23=63, INC=392, DEC=261
6994 04:41:28.216811 [RxdqsGatingPostProcess] freq 400
6995 04:41:28.223414 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6996 04:41:28.226680 best DQS0 dly(2T, 0.5T) = (0, 10)
6997 04:41:28.230093 best DQS1 dly(2T, 0.5T) = (0, 10)
6998 04:41:28.233331 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6999 04:41:28.236891 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7000 04:41:28.239876 best DQS0 dly(2T, 0.5T) = (0, 10)
7001 04:41:28.239956 best DQS1 dly(2T, 0.5T) = (0, 10)
7002 04:41:28.243664 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7003 04:41:28.246599 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7004 04:41:28.250047 Pre-setting of DQS Precalculation
7005 04:41:28.256929 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7006 04:41:28.262881 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7007 04:41:28.269869 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7008 04:41:28.269975
7009 04:41:28.270074
7010 04:41:28.272810 [Calibration Summary] 800 Mbps
7011 04:41:28.276375 CH 0, Rank 0
7012 04:41:28.276481 SW Impedance : PASS
7013 04:41:28.279974 DUTY Scan : NO K
7014 04:41:28.283189 ZQ Calibration : PASS
7015 04:41:28.283269 Jitter Meter : NO K
7016 04:41:28.286201 CBT Training : PASS
7017 04:41:28.286277 Write leveling : PASS
7018 04:41:28.289445 RX DQS gating : PASS
7019 04:41:28.293110 RX DQ/DQS(RDDQC) : PASS
7020 04:41:28.293191 TX DQ/DQS : PASS
7021 04:41:28.295875 RX DATLAT : PASS
7022 04:41:28.299560 RX DQ/DQS(Engine): PASS
7023 04:41:28.299643 TX OE : NO K
7024 04:41:28.302348 All Pass.
7025 04:41:28.302449
7026 04:41:28.302546 CH 0, Rank 1
7027 04:41:28.305632 SW Impedance : PASS
7028 04:41:28.305708 DUTY Scan : NO K
7029 04:41:28.309642 ZQ Calibration : PASS
7030 04:41:28.312814 Jitter Meter : NO K
7031 04:41:28.312901 CBT Training : PASS
7032 04:41:28.316084 Write leveling : NO K
7033 04:41:28.319104 RX DQS gating : PASS
7034 04:41:28.319208 RX DQ/DQS(RDDQC) : PASS
7035 04:41:28.322526 TX DQ/DQS : PASS
7036 04:41:28.325530 RX DATLAT : PASS
7037 04:41:28.325638 RX DQ/DQS(Engine): PASS
7038 04:41:28.328963 TX OE : NO K
7039 04:41:28.329067 All Pass.
7040 04:41:28.329158
7041 04:41:28.332399 CH 1, Rank 0
7042 04:41:28.332478 SW Impedance : PASS
7043 04:41:28.335192 DUTY Scan : NO K
7044 04:41:28.338645 ZQ Calibration : PASS
7045 04:41:28.338749 Jitter Meter : NO K
7046 04:41:28.342323 CBT Training : PASS
7047 04:41:28.345087 Write leveling : PASS
7048 04:41:28.345157 RX DQS gating : PASS
7049 04:41:28.348414 RX DQ/DQS(RDDQC) : PASS
7050 04:41:28.352003 TX DQ/DQS : PASS
7051 04:41:28.352109 RX DATLAT : PASS
7052 04:41:28.355165 RX DQ/DQS(Engine): PASS
7053 04:41:28.358743 TX OE : NO K
7054 04:41:28.358814 All Pass.
7055 04:41:28.358875
7056 04:41:28.358939 CH 1, Rank 1
7057 04:41:28.361800 SW Impedance : PASS
7058 04:41:28.364894 DUTY Scan : NO K
7059 04:41:28.364964 ZQ Calibration : PASS
7060 04:41:28.369036 Jitter Meter : NO K
7061 04:41:28.371652 CBT Training : PASS
7062 04:41:28.371717 Write leveling : NO K
7063 04:41:28.374688 RX DQS gating : PASS
7064 04:41:28.378018 RX DQ/DQS(RDDQC) : PASS
7065 04:41:28.378098 TX DQ/DQS : PASS
7066 04:41:28.381470 RX DATLAT : PASS
7067 04:41:28.381545 RX DQ/DQS(Engine): PASS
7068 04:41:28.384888 TX OE : NO K
7069 04:41:28.384961 All Pass.
7070 04:41:28.385040
7071 04:41:28.387795 DramC Write-DBI off
7072 04:41:28.391408 PER_BANK_REFRESH: Hybrid Mode
7073 04:41:28.391490 TX_TRACKING: ON
7074 04:41:28.401304 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7075 04:41:28.404713 [FAST_K] Save calibration result to emmc
7076 04:41:28.407956 dramc_set_vcore_voltage set vcore to 725000
7077 04:41:28.411012 Read voltage for 1600, 0
7078 04:41:28.411103 Vio18 = 0
7079 04:41:28.414291 Vcore = 725000
7080 04:41:28.414399 Vdram = 0
7081 04:41:28.414494 Vddq = 0
7082 04:41:28.414575 Vmddr = 0
7083 04:41:28.420877 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7084 04:41:28.427457 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7085 04:41:28.427577 MEM_TYPE=3, freq_sel=13
7086 04:41:28.431555 sv_algorithm_assistance_LP4_3733
7087 04:41:28.434148 ============ PULL DRAM RESETB DOWN ============
7088 04:41:28.440731 ========== PULL DRAM RESETB DOWN end =========
7089 04:41:28.444284 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7090 04:41:28.447437 ===================================
7091 04:41:28.450671 LPDDR4 DRAM CONFIGURATION
7092 04:41:28.454018 ===================================
7093 04:41:28.454140 EX_ROW_EN[0] = 0x0
7094 04:41:28.457450 EX_ROW_EN[1] = 0x0
7095 04:41:28.460773 LP4Y_EN = 0x0
7096 04:41:28.460880 WORK_FSP = 0x1
7097 04:41:28.463926 WL = 0x5
7098 04:41:28.464003 RL = 0x5
7099 04:41:28.467577 BL = 0x2
7100 04:41:28.467658 RPST = 0x0
7101 04:41:28.470282 RD_PRE = 0x0
7102 04:41:28.470391 WR_PRE = 0x1
7103 04:41:28.473674 WR_PST = 0x1
7104 04:41:28.473760 DBI_WR = 0x0
7105 04:41:28.477121 DBI_RD = 0x0
7106 04:41:28.477192 OTF = 0x1
7107 04:41:28.480041 ===================================
7108 04:41:28.483580 ===================================
7109 04:41:28.487282 ANA top config
7110 04:41:28.490326 ===================================
7111 04:41:28.493728 DLL_ASYNC_EN = 0
7112 04:41:28.493804 ALL_SLAVE_EN = 0
7113 04:41:28.496538 NEW_RANK_MODE = 1
7114 04:41:28.499645 DLL_IDLE_MODE = 1
7115 04:41:28.503380 LP45_APHY_COMB_EN = 1
7116 04:41:28.503457 TX_ODT_DIS = 0
7117 04:41:28.506237 NEW_8X_MODE = 1
7118 04:41:28.509583 ===================================
7119 04:41:28.513490 ===================================
7120 04:41:28.516536 data_rate = 3200
7121 04:41:28.519658 CKR = 1
7122 04:41:28.522967 DQ_P2S_RATIO = 8
7123 04:41:28.525958 ===================================
7124 04:41:28.529533 CA_P2S_RATIO = 8
7125 04:41:28.529606 DQ_CA_OPEN = 0
7126 04:41:28.532851 DQ_SEMI_OPEN = 0
7127 04:41:28.536089 CA_SEMI_OPEN = 0
7128 04:41:28.539442 CA_FULL_RATE = 0
7129 04:41:28.542676 DQ_CKDIV4_EN = 0
7130 04:41:28.546072 CA_CKDIV4_EN = 0
7131 04:41:28.549277 CA_PREDIV_EN = 0
7132 04:41:28.549358 PH8_DLY = 12
7133 04:41:28.552855 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7134 04:41:28.556031 DQ_AAMCK_DIV = 4
7135 04:41:28.559487 CA_AAMCK_DIV = 4
7136 04:41:28.562348 CA_ADMCK_DIV = 4
7137 04:41:28.565706 DQ_TRACK_CA_EN = 0
7138 04:41:28.565804 CA_PICK = 1600
7139 04:41:28.569237 CA_MCKIO = 1600
7140 04:41:28.572357 MCKIO_SEMI = 0
7141 04:41:28.575620 PLL_FREQ = 3068
7142 04:41:28.579128 DQ_UI_PI_RATIO = 32
7143 04:41:28.582142 CA_UI_PI_RATIO = 0
7144 04:41:28.585594 ===================================
7145 04:41:28.588629 ===================================
7146 04:41:28.592135 memory_type:LPDDR4
7147 04:41:28.592259 GP_NUM : 10
7148 04:41:28.595623 SRAM_EN : 1
7149 04:41:28.595731 MD32_EN : 0
7150 04:41:28.598750 ===================================
7151 04:41:28.602441 [ANA_INIT] >>>>>>>>>>>>>>
7152 04:41:28.605337 <<<<<< [CONFIGURE PHASE]: ANA_TX
7153 04:41:28.608594 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7154 04:41:28.612159 ===================================
7155 04:41:28.615269 data_rate = 3200,PCW = 0X7600
7156 04:41:28.618822 ===================================
7157 04:41:28.622052 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7158 04:41:28.628635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7159 04:41:28.631819 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7160 04:41:28.638368 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7161 04:41:28.641946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7162 04:41:28.644786 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7163 04:41:28.644868 [ANA_INIT] flow start
7164 04:41:28.648066 [ANA_INIT] PLL >>>>>>>>
7165 04:41:28.651359 [ANA_INIT] PLL <<<<<<<<
7166 04:41:28.651478 [ANA_INIT] MIDPI >>>>>>>>
7167 04:41:28.655069 [ANA_INIT] MIDPI <<<<<<<<
7168 04:41:28.657880 [ANA_INIT] DLL >>>>>>>>
7169 04:41:28.661671 [ANA_INIT] DLL <<<<<<<<
7170 04:41:28.661752 [ANA_INIT] flow end
7171 04:41:28.664877 ============ LP4 DIFF to SE enter ============
7172 04:41:28.671524 ============ LP4 DIFF to SE exit ============
7173 04:41:28.671614 [ANA_INIT] <<<<<<<<<<<<<
7174 04:41:28.674822 [Flow] Enable top DCM control >>>>>
7175 04:41:28.677799 [Flow] Enable top DCM control <<<<<
7176 04:41:28.681013 Enable DLL master slave shuffle
7177 04:41:28.687554 ==============================================================
7178 04:41:28.687630 Gating Mode config
7179 04:41:28.694568 ==============================================================
7180 04:41:28.697618 Config description:
7181 04:41:28.707424 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7182 04:41:28.714239 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7183 04:41:28.717326 SELPH_MODE 0: By rank 1: By Phase
7184 04:41:28.724422 ==============================================================
7185 04:41:28.727194 GAT_TRACK_EN = 1
7186 04:41:28.730698 RX_GATING_MODE = 2
7187 04:41:28.730808 RX_GATING_TRACK_MODE = 2
7188 04:41:28.734247 SELPH_MODE = 1
7189 04:41:28.737366 PICG_EARLY_EN = 1
7190 04:41:28.740580 VALID_LAT_VALUE = 1
7191 04:41:28.747210 ==============================================================
7192 04:41:28.750597 Enter into Gating configuration >>>>
7193 04:41:28.753695 Exit from Gating configuration <<<<
7194 04:41:28.756904 Enter into DVFS_PRE_config >>>>>
7195 04:41:28.766880 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7196 04:41:28.770290 Exit from DVFS_PRE_config <<<<<
7197 04:41:28.773697 Enter into PICG configuration >>>>
7198 04:41:28.776811 Exit from PICG configuration <<<<
7199 04:41:28.779967 [RX_INPUT] configuration >>>>>
7200 04:41:28.783842 [RX_INPUT] configuration <<<<<
7201 04:41:28.787015 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7202 04:41:28.793627 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7203 04:41:28.800044 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7204 04:41:28.806562 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7205 04:41:28.812969 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7206 04:41:28.816456 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7207 04:41:28.823505 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7208 04:41:28.826604 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7209 04:41:28.830247 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7210 04:41:28.833248 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7211 04:41:28.839493 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7212 04:41:28.842945 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7213 04:41:28.846216 ===================================
7214 04:41:28.849560 LPDDR4 DRAM CONFIGURATION
7215 04:41:28.852616 ===================================
7216 04:41:28.852717 EX_ROW_EN[0] = 0x0
7217 04:41:28.855740 EX_ROW_EN[1] = 0x0
7218 04:41:28.855840 LP4Y_EN = 0x0
7219 04:41:28.859031 WORK_FSP = 0x1
7220 04:41:28.859134 WL = 0x5
7221 04:41:28.862480 RL = 0x5
7222 04:41:28.866163 BL = 0x2
7223 04:41:28.866232 RPST = 0x0
7224 04:41:28.869369 RD_PRE = 0x0
7225 04:41:28.869440 WR_PRE = 0x1
7226 04:41:28.872436 WR_PST = 0x1
7227 04:41:28.872541 DBI_WR = 0x0
7228 04:41:28.875966 DBI_RD = 0x0
7229 04:41:28.876048 OTF = 0x1
7230 04:41:28.879551 ===================================
7231 04:41:28.882634 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7232 04:41:28.889304 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7233 04:41:28.892339 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7234 04:41:28.895783 ===================================
7235 04:41:28.899249 LPDDR4 DRAM CONFIGURATION
7236 04:41:28.902541 ===================================
7237 04:41:28.902622 EX_ROW_EN[0] = 0x10
7238 04:41:28.905919 EX_ROW_EN[1] = 0x0
7239 04:41:28.906000 LP4Y_EN = 0x0
7240 04:41:28.908713 WORK_FSP = 0x1
7241 04:41:28.908793 WL = 0x5
7242 04:41:28.912361 RL = 0x5
7243 04:41:28.915260 BL = 0x2
7244 04:41:28.915340 RPST = 0x0
7245 04:41:28.919056 RD_PRE = 0x0
7246 04:41:28.919136 WR_PRE = 0x1
7247 04:41:28.922071 WR_PST = 0x1
7248 04:41:28.922152 DBI_WR = 0x0
7249 04:41:28.925492 DBI_RD = 0x0
7250 04:41:28.925573 OTF = 0x1
7251 04:41:28.929080 ===================================
7252 04:41:28.935060 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7253 04:41:28.935141 ==
7254 04:41:28.938932 Dram Type= 6, Freq= 0, CH_0, rank 0
7255 04:41:28.941963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7256 04:41:28.942045 ==
7257 04:41:28.945502 [Duty_Offset_Calibration]
7258 04:41:28.948767 B0:2 B1:0 CA:4
7259 04:41:28.948848
7260 04:41:28.951667 [DutyScan_Calibration_Flow] k_type=0
7261 04:41:28.959634
7262 04:41:28.959714 ==CLK 0==
7263 04:41:28.963155 Final CLK duty delay cell = -4
7264 04:41:28.965901 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7265 04:41:28.969647 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7266 04:41:28.972562 [-4] AVG Duty = 4937%(X100)
7267 04:41:28.972643
7268 04:41:28.976083 CH0 CLK Duty spec in!! Max-Min= 187%
7269 04:41:28.979354 [DutyScan_Calibration_Flow] ====Done====
7270 04:41:28.979471
7271 04:41:28.982287 [DutyScan_Calibration_Flow] k_type=1
7272 04:41:29.000103
7273 04:41:29.000184 ==DQS 0 ==
7274 04:41:29.003011 Final DQS duty delay cell = 0
7275 04:41:29.006442 [0] MAX Duty = 5218%(X100), DQS PI = 22
7276 04:41:29.009931 [0] MIN Duty = 5093%(X100), DQS PI = 8
7277 04:41:29.013103 [0] AVG Duty = 5155%(X100)
7278 04:41:29.013184
7279 04:41:29.013276 ==DQS 1 ==
7280 04:41:29.016331 Final DQS duty delay cell = 0
7281 04:41:29.019310 [0] MAX Duty = 5156%(X100), DQS PI = 0
7282 04:41:29.023531 [0] MIN Duty = 4969%(X100), DQS PI = 12
7283 04:41:29.026152 [0] AVG Duty = 5062%(X100)
7284 04:41:29.026233
7285 04:41:29.029471 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7286 04:41:29.029552
7287 04:41:29.033281 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7288 04:41:29.036537 [DutyScan_Calibration_Flow] ====Done====
7289 04:41:29.036618
7290 04:41:29.039111 [DutyScan_Calibration_Flow] k_type=3
7291 04:41:29.056734
7292 04:41:29.056814 ==DQM 0 ==
7293 04:41:29.060516 Final DQM duty delay cell = 0
7294 04:41:29.063683 [0] MAX Duty = 5124%(X100), DQS PI = 20
7295 04:41:29.066829 [0] MIN Duty = 4875%(X100), DQS PI = 56
7296 04:41:29.070111 [0] AVG Duty = 4999%(X100)
7297 04:41:29.070191
7298 04:41:29.070255 ==DQM 1 ==
7299 04:41:29.073472 Final DQM duty delay cell = 0
7300 04:41:29.076975 [0] MAX Duty = 5000%(X100), DQS PI = 2
7301 04:41:29.079884 [0] MIN Duty = 4844%(X100), DQS PI = 14
7302 04:41:29.083366 [0] AVG Duty = 4922%(X100)
7303 04:41:29.083462
7304 04:41:29.086760 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7305 04:41:29.086841
7306 04:41:29.089829 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7307 04:41:29.093345 [DutyScan_Calibration_Flow] ====Done====
7308 04:41:29.093426
7309 04:41:29.096535 [DutyScan_Calibration_Flow] k_type=2
7310 04:41:29.113876
7311 04:41:29.113973 ==DQ 0 ==
7312 04:41:29.117263 Final DQ duty delay cell = 0
7313 04:41:29.120725 [0] MAX Duty = 5156%(X100), DQS PI = 20
7314 04:41:29.124150 [0] MIN Duty = 4938%(X100), DQS PI = 12
7315 04:41:29.124232 [0] AVG Duty = 5047%(X100)
7316 04:41:29.127141
7317 04:41:29.127222 ==DQ 1 ==
7318 04:41:29.130633 Final DQ duty delay cell = 0
7319 04:41:29.134026 [0] MAX Duty = 5187%(X100), DQS PI = 2
7320 04:41:29.137487 [0] MIN Duty = 4938%(X100), DQS PI = 12
7321 04:41:29.137584 [0] AVG Duty = 5062%(X100)
7322 04:41:29.137693
7323 04:41:29.143691 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7324 04:41:29.143808
7325 04:41:29.147313 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7326 04:41:29.150481 [DutyScan_Calibration_Flow] ====Done====
7327 04:41:29.150675 ==
7328 04:41:29.153400 Dram Type= 6, Freq= 0, CH_1, rank 0
7329 04:41:29.156993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7330 04:41:29.157074 ==
7331 04:41:29.159898 [Duty_Offset_Calibration]
7332 04:41:29.159978 B0:0 B1:-1 CA:3
7333 04:41:29.160042
7334 04:41:29.163551 [DutyScan_Calibration_Flow] k_type=0
7335 04:41:29.173451
7336 04:41:29.173535 ==CLK 0==
7337 04:41:29.176728 Final CLK duty delay cell = -4
7338 04:41:29.179730 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7339 04:41:29.183615 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7340 04:41:29.186937 [-4] AVG Duty = 4937%(X100)
7341 04:41:29.187018
7342 04:41:29.189830 CH1 CLK Duty spec in!! Max-Min= 125%
7343 04:41:29.193067 [DutyScan_Calibration_Flow] ====Done====
7344 04:41:29.193149
7345 04:41:29.196254 [DutyScan_Calibration_Flow] k_type=1
7346 04:41:29.212378
7347 04:41:29.212466 ==DQS 0 ==
7348 04:41:29.215820 Final DQS duty delay cell = 0
7349 04:41:29.219244 [0] MAX Duty = 5250%(X100), DQS PI = 30
7350 04:41:29.222625 [0] MIN Duty = 4938%(X100), DQS PI = 40
7351 04:41:29.225488 [0] AVG Duty = 5094%(X100)
7352 04:41:29.225569
7353 04:41:29.225632 ==DQS 1 ==
7354 04:41:29.229104 Final DQS duty delay cell = -4
7355 04:41:29.232093 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7356 04:41:29.235614 [-4] MIN Duty = 4844%(X100), DQS PI = 62
7357 04:41:29.239273 [-4] AVG Duty = 4922%(X100)
7358 04:41:29.239353
7359 04:41:29.242477 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7360 04:41:29.242557
7361 04:41:29.245321 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7362 04:41:29.248693 [DutyScan_Calibration_Flow] ====Done====
7363 04:41:29.248773
7364 04:41:29.251879 [DutyScan_Calibration_Flow] k_type=3
7365 04:41:29.270084
7366 04:41:29.270164 ==DQM 0 ==
7367 04:41:29.273403 Final DQM duty delay cell = 0
7368 04:41:29.276557 [0] MAX Duty = 5062%(X100), DQS PI = 30
7369 04:41:29.279695 [0] MIN Duty = 4782%(X100), DQS PI = 40
7370 04:41:29.283365 [0] AVG Duty = 4922%(X100)
7371 04:41:29.283445
7372 04:41:29.283509 ==DQM 1 ==
7373 04:41:29.286269 Final DQM duty delay cell = 0
7374 04:41:29.289906 [0] MAX Duty = 5000%(X100), DQS PI = 32
7375 04:41:29.293197 [0] MIN Duty = 4813%(X100), DQS PI = 0
7376 04:41:29.296145 [0] AVG Duty = 4906%(X100)
7377 04:41:29.296226
7378 04:41:29.299712 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7379 04:41:29.299793
7380 04:41:29.302705 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7381 04:41:29.306256 [DutyScan_Calibration_Flow] ====Done====
7382 04:41:29.306337
7383 04:41:29.309442 [DutyScan_Calibration_Flow] k_type=2
7384 04:41:29.326062
7385 04:41:29.326143 ==DQ 0 ==
7386 04:41:29.329281 Final DQ duty delay cell = -4
7387 04:41:29.332709 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7388 04:41:29.336057 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7389 04:41:29.339015 [-4] AVG Duty = 4891%(X100)
7390 04:41:29.339095
7391 04:41:29.339158 ==DQ 1 ==
7392 04:41:29.342198 Final DQ duty delay cell = 0
7393 04:41:29.345925 [0] MAX Duty = 5062%(X100), DQS PI = 32
7394 04:41:29.349274 [0] MIN Duty = 4875%(X100), DQS PI = 54
7395 04:41:29.352604 [0] AVG Duty = 4968%(X100)
7396 04:41:29.352685
7397 04:41:29.355636 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7398 04:41:29.355716
7399 04:41:29.359115 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7400 04:41:29.362037 [DutyScan_Calibration_Flow] ====Done====
7401 04:41:29.365565 nWR fixed to 30
7402 04:41:29.368643 [ModeRegInit_LP4] CH0 RK0
7403 04:41:29.368724 [ModeRegInit_LP4] CH0 RK1
7404 04:41:29.372319 [ModeRegInit_LP4] CH1 RK0
7405 04:41:29.375608 [ModeRegInit_LP4] CH1 RK1
7406 04:41:29.375714 match AC timing 5
7407 04:41:29.381856 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7408 04:41:29.385552 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7409 04:41:29.388683 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7410 04:41:29.395672 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7411 04:41:29.399140 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7412 04:41:29.402112 [MiockJmeterHQA]
7413 04:41:29.402201
7414 04:41:29.404811 [DramcMiockJmeter] u1RxGatingPI = 0
7415 04:41:29.404882 0 : 4366, 4140
7416 04:41:29.404956 4 : 4363, 4137
7417 04:41:29.408346 8 : 4363, 4137
7418 04:41:29.408423 12 : 4252, 4027
7419 04:41:29.411673 16 : 4252, 4027
7420 04:41:29.411744 20 : 4255, 4029
7421 04:41:29.414645 24 : 4252, 4027
7422 04:41:29.414730 28 : 4363, 4137
7423 04:41:29.414792 32 : 4361, 4137
7424 04:41:29.417802 36 : 4250, 4027
7425 04:41:29.417900 40 : 4254, 4029
7426 04:41:29.421403 44 : 4250, 4027
7427 04:41:29.421485 48 : 4363, 4137
7428 04:41:29.424811 52 : 4250, 4027
7429 04:41:29.424892 56 : 4360, 4137
7430 04:41:29.427996 60 : 4252, 4027
7431 04:41:29.428068 64 : 4250, 4027
7432 04:41:29.428128 68 : 4250, 4026
7433 04:41:29.431535 72 : 4250, 4027
7434 04:41:29.431610 76 : 4360, 4137
7435 04:41:29.434571 80 : 4253, 4026
7436 04:41:29.434641 84 : 4361, 4138
7437 04:41:29.437950 88 : 4250, 4026
7438 04:41:29.438055 92 : 4250, 4027
7439 04:41:29.441002 96 : 4250, 3205
7440 04:41:29.441155 100 : 4361, 0
7441 04:41:29.441223 104 : 4250, 0
7442 04:41:29.444273 108 : 4250, 0
7443 04:41:29.444356 112 : 4360, 0
7444 04:41:29.447614 116 : 4360, 0
7445 04:41:29.447697 120 : 4365, 0
7446 04:41:29.447762 124 : 4250, 0
7447 04:41:29.451162 128 : 4250, 0
7448 04:41:29.451245 132 : 4250, 0
7449 04:41:29.451311 136 : 4250, 0
7450 04:41:29.454274 140 : 4250, 0
7451 04:41:29.454379 144 : 4250, 0
7452 04:41:29.457436 148 : 4250, 0
7453 04:41:29.457519 152 : 4250, 0
7454 04:41:29.457584 156 : 4360, 0
7455 04:41:29.461095 160 : 4250, 0
7456 04:41:29.461179 164 : 4250, 0
7457 04:41:29.464339 168 : 4360, 0
7458 04:41:29.464421 172 : 4361, 0
7459 04:41:29.464487 176 : 4250, 0
7460 04:41:29.467771 180 : 4250, 0
7461 04:41:29.467853 184 : 4250, 0
7462 04:41:29.470790 188 : 4250, 0
7463 04:41:29.470873 192 : 4250, 0
7464 04:41:29.470938 196 : 4250, 0
7465 04:41:29.474295 200 : 4250, 0
7466 04:41:29.474378 204 : 4361, 0
7467 04:41:29.477527 208 : 4250, 0
7468 04:41:29.477609 212 : 4250, 0
7469 04:41:29.477675 216 : 4361, 0
7470 04:41:29.480843 220 : 4360, 587
7471 04:41:29.480925 224 : 4250, 3978
7472 04:41:29.484249 228 : 4250, 4027
7473 04:41:29.484331 232 : 4250, 4026
7474 04:41:29.487289 236 : 4250, 4027
7475 04:41:29.487442 240 : 4250, 4027
7476 04:41:29.490704 244 : 4250, 4027
7477 04:41:29.490787 248 : 4250, 4027
7478 04:41:29.493625 252 : 4360, 4137
7479 04:41:29.493708 256 : 4361, 4137
7480 04:41:29.497106 260 : 4247, 4025
7481 04:41:29.497188 264 : 4361, 4138
7482 04:41:29.497254 268 : 4360, 4138
7483 04:41:29.500197 272 : 4250, 4026
7484 04:41:29.500280 276 : 4250, 4026
7485 04:41:29.503761 280 : 4250, 4026
7486 04:41:29.503844 284 : 4250, 4027
7487 04:41:29.506897 288 : 4250, 4026
7488 04:41:29.506979 292 : 4250, 4026
7489 04:41:29.510055 296 : 4250, 4026
7490 04:41:29.510138 300 : 4250, 4027
7491 04:41:29.513768 304 : 4360, 4137
7492 04:41:29.513850 308 : 4361, 4137
7493 04:41:29.517297 312 : 4250, 4027
7494 04:41:29.517379 316 : 4361, 4138
7495 04:41:29.520361 320 : 4360, 4137
7496 04:41:29.520483 324 : 4250, 4026
7497 04:41:29.523652 328 : 4250, 4027
7498 04:41:29.523735 332 : 4250, 4015
7499 04:41:29.523801 336 : 4250, 2061
7500 04:41:29.526600
7501 04:41:29.526681 MIOCK jitter meter ch=0
7502 04:41:29.526745
7503 04:41:29.530656 1T = (336-100) = 236 dly cells
7504 04:41:29.536484 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7505 04:41:29.536566 ==
7506 04:41:29.539660 Dram Type= 6, Freq= 0, CH_0, rank 0
7507 04:41:29.543488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7508 04:41:29.543570 ==
7509 04:41:29.549583 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7510 04:41:29.553253 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7511 04:41:29.556427 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7512 04:41:29.562669 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7513 04:41:29.572408 [CA 0] Center 43 (13~73) winsize 61
7514 04:41:29.576007 [CA 1] Center 42 (12~73) winsize 62
7515 04:41:29.578814 [CA 2] Center 37 (8~67) winsize 60
7516 04:41:29.582428 [CA 3] Center 37 (8~67) winsize 60
7517 04:41:29.585591 [CA 4] Center 36 (6~66) winsize 61
7518 04:41:29.589280 [CA 5] Center 35 (5~66) winsize 62
7519 04:41:29.589362
7520 04:41:29.592373 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7521 04:41:29.592455
7522 04:41:29.595503 [CATrainingPosCal] consider 1 rank data
7523 04:41:29.599073 u2DelayCellTimex100 = 275/100 ps
7524 04:41:29.605266 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7525 04:41:29.609255 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7526 04:41:29.612370 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7527 04:41:29.615467 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7528 04:41:29.619294 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7529 04:41:29.622183 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7530 04:41:29.622298
7531 04:41:29.625206 CA PerBit enable=1, Macro0, CA PI delay=35
7532 04:41:29.625292
7533 04:41:29.628566 [CBTSetCACLKResult] CA Dly = 35
7534 04:41:29.631602 CS Dly: 11 (0~42)
7535 04:41:29.635056 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7536 04:41:29.638353 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7537 04:41:29.638460 ==
7538 04:41:29.641828 Dram Type= 6, Freq= 0, CH_0, rank 1
7539 04:41:29.648612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7540 04:41:29.648688 ==
7541 04:41:29.651623 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7542 04:41:29.658283 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7543 04:41:29.661690 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7544 04:41:29.667855 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7545 04:41:29.676308 [CA 0] Center 44 (14~75) winsize 62
7546 04:41:29.679518 [CA 1] Center 44 (14~74) winsize 61
7547 04:41:29.682391 [CA 2] Center 39 (10~69) winsize 60
7548 04:41:29.686054 [CA 3] Center 39 (10~68) winsize 59
7549 04:41:29.689519 [CA 4] Center 37 (7~67) winsize 61
7550 04:41:29.692464 [CA 5] Center 36 (7~66) winsize 60
7551 04:41:29.692545
7552 04:41:29.696156 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7553 04:41:29.696238
7554 04:41:29.702481 [CATrainingPosCal] consider 2 rank data
7555 04:41:29.702563 u2DelayCellTimex100 = 275/100 ps
7556 04:41:29.708790 CA0 delay=43 (14~73),Diff = 7 PI (24 cell)
7557 04:41:29.712092 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7558 04:41:29.715398 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7559 04:41:29.718882 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7560 04:41:29.722744 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7561 04:41:29.725318 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7562 04:41:29.725413
7563 04:41:29.729109 CA PerBit enable=1, Macro0, CA PI delay=36
7564 04:41:29.729222
7565 04:41:29.732041 [CBTSetCACLKResult] CA Dly = 36
7566 04:41:29.735353 CS Dly: 11 (0~43)
7567 04:41:29.738404 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7568 04:41:29.742187 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7569 04:41:29.742269
7570 04:41:29.745428 ----->DramcWriteLeveling(PI) begin...
7571 04:41:29.748219 ==
7572 04:41:29.751408 Dram Type= 6, Freq= 0, CH_0, rank 0
7573 04:41:29.754863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7574 04:41:29.754945 ==
7575 04:41:29.758229 Write leveling (Byte 0): 36 => 36
7576 04:41:29.761306 Write leveling (Byte 1): 27 => 27
7577 04:41:29.764654 DramcWriteLeveling(PI) end<-----
7578 04:41:29.764735
7579 04:41:29.764799 ==
7580 04:41:29.768647 Dram Type= 6, Freq= 0, CH_0, rank 0
7581 04:41:29.771369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7582 04:41:29.771465 ==
7583 04:41:29.774429 [Gating] SW mode calibration
7584 04:41:29.781103 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7585 04:41:29.787984 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7586 04:41:29.791268 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 04:41:29.794548 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 04:41:29.801122 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 04:41:29.803950 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7590 04:41:29.807514 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7591 04:41:29.813954 1 4 20 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
7592 04:41:29.817547 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 04:41:29.820538 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 04:41:29.827078 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 04:41:29.830505 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 04:41:29.833517 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7597 04:41:29.840622 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
7598 04:41:29.843828 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7599 04:41:29.847162 1 5 20 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
7600 04:41:29.853451 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 04:41:29.856812 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 04:41:29.860243 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 04:41:29.866867 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 04:41:29.869988 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7605 04:41:29.873341 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7606 04:41:29.879721 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7607 04:41:29.883226 1 6 20 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
7608 04:41:29.886596 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 04:41:29.893111 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 04:41:29.896890 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 04:41:29.900071 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 04:41:29.906535 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 04:41:29.909671 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7614 04:41:29.913254 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7615 04:41:29.919197 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7616 04:41:29.922618 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7617 04:41:29.926299 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 04:41:29.932377 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 04:41:29.935833 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 04:41:29.939111 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 04:41:29.945544 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 04:41:29.948934 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 04:41:29.952480 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 04:41:29.958641 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 04:41:29.962315 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 04:41:29.965741 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 04:41:29.971798 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 04:41:29.975221 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7629 04:41:29.978794 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7630 04:41:29.982177 Total UI for P1: 0, mck2ui 16
7631 04:41:29.985379 best dqsien dly found for B0: ( 1, 9, 8)
7632 04:41:29.991914 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7633 04:41:29.995265 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7634 04:41:29.998793 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 04:41:30.001823 Total UI for P1: 0, mck2ui 16
7636 04:41:30.005334 best dqsien dly found for B1: ( 1, 9, 18)
7637 04:41:30.008233 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7638 04:41:30.011610 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7639 04:41:30.011691
7640 04:41:30.018028 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7641 04:41:30.021627 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7642 04:41:30.025122 [Gating] SW calibration Done
7643 04:41:30.025203 ==
7644 04:41:30.028218 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 04:41:30.031530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 04:41:30.031618 ==
7647 04:41:30.031684 RX Vref Scan: 0
7648 04:41:30.034740
7649 04:41:30.034821 RX Vref 0 -> 0, step: 1
7650 04:41:30.034886
7651 04:41:30.038061 RX Delay 0 -> 252, step: 8
7652 04:41:30.041364 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7653 04:41:30.044371 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7654 04:41:30.051414 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7655 04:41:30.054408 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7656 04:41:30.058288 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7657 04:41:30.060930 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7658 04:41:30.064746 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7659 04:41:30.071041 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7660 04:41:30.074552 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7661 04:41:30.077323 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7662 04:41:30.081117 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7663 04:41:30.084219 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7664 04:41:30.090505 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7665 04:41:30.093704 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
7666 04:41:30.097398 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7667 04:41:30.100611 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7668 04:41:30.103713 ==
7669 04:41:30.107106 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 04:41:30.110021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 04:41:30.110103 ==
7672 04:41:30.110168 DQS Delay:
7673 04:41:30.113703 DQS0 = 0, DQS1 = 0
7674 04:41:30.113784 DQM Delay:
7675 04:41:30.116572 DQM0 = 130, DQM1 = 127
7676 04:41:30.116653 DQ Delay:
7677 04:41:30.120376 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =123
7678 04:41:30.123793 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7679 04:41:30.126655 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
7680 04:41:30.129850 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
7681 04:41:30.129932
7682 04:41:30.129997
7683 04:41:30.130056 ==
7684 04:41:30.133200 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 04:41:30.139688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 04:41:30.139770 ==
7687 04:41:30.139835
7688 04:41:30.139894
7689 04:41:30.143295 TX Vref Scan disable
7690 04:41:30.143383 == TX Byte 0 ==
7691 04:41:30.146774 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7692 04:41:30.153150 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7693 04:41:30.153232 == TX Byte 1 ==
7694 04:41:30.156151 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7695 04:41:30.163057 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7696 04:41:30.163139 ==
7697 04:41:30.166561 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 04:41:30.169396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 04:41:30.169478 ==
7700 04:41:30.183309
7701 04:41:30.186972 TX Vref early break, caculate TX vref
7702 04:41:30.189972 TX Vref=16, minBit 7, minWin=22, winSum=371
7703 04:41:30.193466 TX Vref=18, minBit 8, minWin=22, winSum=376
7704 04:41:30.196549 TX Vref=20, minBit 8, minWin=23, winSum=393
7705 04:41:30.200753 TX Vref=22, minBit 0, minWin=24, winSum=402
7706 04:41:30.203503 TX Vref=24, minBit 4, minWin=24, winSum=411
7707 04:41:30.209827 TX Vref=26, minBit 4, minWin=25, winSum=420
7708 04:41:30.213023 TX Vref=28, minBit 1, minWin=25, winSum=421
7709 04:41:30.216705 TX Vref=30, minBit 2, minWin=24, winSum=417
7710 04:41:30.219840 TX Vref=32, minBit 6, minWin=24, winSum=411
7711 04:41:30.223330 TX Vref=34, minBit 1, minWin=24, winSum=398
7712 04:41:30.229825 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28
7713 04:41:30.229933
7714 04:41:30.233332 Final TX Range 0 Vref 28
7715 04:41:30.233414
7716 04:41:30.233478 ==
7717 04:41:30.236118 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 04:41:30.239673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 04:41:30.239755 ==
7720 04:41:30.239819
7721 04:41:30.239879
7722 04:41:30.243085 TX Vref Scan disable
7723 04:41:30.249668 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7724 04:41:30.249750 == TX Byte 0 ==
7725 04:41:30.253019 u2DelayCellOfst[0]=14 cells (4 PI)
7726 04:41:30.256390 u2DelayCellOfst[1]=17 cells (5 PI)
7727 04:41:30.259395 u2DelayCellOfst[2]=14 cells (4 PI)
7728 04:41:30.263025 u2DelayCellOfst[3]=14 cells (4 PI)
7729 04:41:30.266047 u2DelayCellOfst[4]=10 cells (3 PI)
7730 04:41:30.269388 u2DelayCellOfst[5]=0 cells (0 PI)
7731 04:41:30.272346 u2DelayCellOfst[6]=21 cells (6 PI)
7732 04:41:30.275785 u2DelayCellOfst[7]=17 cells (5 PI)
7733 04:41:30.279150 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7734 04:41:30.282596 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7735 04:41:30.285710 == TX Byte 1 ==
7736 04:41:30.289334 u2DelayCellOfst[8]=0 cells (0 PI)
7737 04:41:30.292274 u2DelayCellOfst[9]=0 cells (0 PI)
7738 04:41:30.295625 u2DelayCellOfst[10]=7 cells (2 PI)
7739 04:41:30.295707 u2DelayCellOfst[11]=3 cells (1 PI)
7740 04:41:30.298971 u2DelayCellOfst[12]=10 cells (3 PI)
7741 04:41:30.302363 u2DelayCellOfst[13]=10 cells (3 PI)
7742 04:41:30.305846 u2DelayCellOfst[14]=14 cells (4 PI)
7743 04:41:30.309023 u2DelayCellOfst[15]=10 cells (3 PI)
7744 04:41:30.315608 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7745 04:41:30.318652 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7746 04:41:30.318734 DramC Write-DBI on
7747 04:41:30.322059 ==
7748 04:41:30.322177 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 04:41:30.328998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 04:41:30.329080 ==
7751 04:41:30.329144
7752 04:41:30.329202
7753 04:41:30.332074 TX Vref Scan disable
7754 04:41:30.332155 == TX Byte 0 ==
7755 04:41:30.338517 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7756 04:41:30.338599 == TX Byte 1 ==
7757 04:41:30.342024 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7758 04:41:30.345242 DramC Write-DBI off
7759 04:41:30.345323
7760 04:41:30.345387 [DATLAT]
7761 04:41:30.348665 Freq=1600, CH0 RK0
7762 04:41:30.348763
7763 04:41:30.348857 DATLAT Default: 0xf
7764 04:41:30.352104 0, 0xFFFF, sum = 0
7765 04:41:30.352187 1, 0xFFFF, sum = 0
7766 04:41:30.355280 2, 0xFFFF, sum = 0
7767 04:41:30.355385 3, 0xFFFF, sum = 0
7768 04:41:30.358572 4, 0xFFFF, sum = 0
7769 04:41:30.361909 5, 0xFFFF, sum = 0
7770 04:41:30.361998 6, 0xFFFF, sum = 0
7771 04:41:30.365404 7, 0xFFFF, sum = 0
7772 04:41:30.365486 8, 0xFFFF, sum = 0
7773 04:41:30.368364 9, 0xFFFF, sum = 0
7774 04:41:30.368447 10, 0xFFFF, sum = 0
7775 04:41:30.371962 11, 0xFFFF, sum = 0
7776 04:41:30.372044 12, 0xFFFF, sum = 0
7777 04:41:30.374908 13, 0xFFFF, sum = 0
7778 04:41:30.374989 14, 0x0, sum = 1
7779 04:41:30.378518 15, 0x0, sum = 2
7780 04:41:30.378601 16, 0x0, sum = 3
7781 04:41:30.381719 17, 0x0, sum = 4
7782 04:41:30.381801 best_step = 15
7783 04:41:30.381865
7784 04:41:30.381954 ==
7785 04:41:30.384667 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 04:41:30.388405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 04:41:30.391712 ==
7788 04:41:30.391793 RX Vref Scan: 1
7789 04:41:30.391857
7790 04:41:30.395116 Set Vref Range= 24 -> 127
7791 04:41:30.395196
7792 04:41:30.397886 RX Vref 24 -> 127, step: 1
7793 04:41:30.397994
7794 04:41:30.398090 RX Delay 11 -> 252, step: 4
7795 04:41:30.398180
7796 04:41:30.401508 Set Vref, RX VrefLevel [Byte0]: 24
7797 04:41:30.404863 [Byte1]: 24
7798 04:41:30.408388
7799 04:41:30.408489 Set Vref, RX VrefLevel [Byte0]: 25
7800 04:41:30.411629 [Byte1]: 25
7801 04:41:30.415731
7802 04:41:30.415801 Set Vref, RX VrefLevel [Byte0]: 26
7803 04:41:30.419270 [Byte1]: 26
7804 04:41:30.423758
7805 04:41:30.423831 Set Vref, RX VrefLevel [Byte0]: 27
7806 04:41:30.426841 [Byte1]: 27
7807 04:41:30.431286
7808 04:41:30.431421 Set Vref, RX VrefLevel [Byte0]: 28
7809 04:41:30.434242 [Byte1]: 28
7810 04:41:30.439036
7811 04:41:30.439154 Set Vref, RX VrefLevel [Byte0]: 29
7812 04:41:30.442371 [Byte1]: 29
7813 04:41:30.446552
7814 04:41:30.446651 Set Vref, RX VrefLevel [Byte0]: 30
7815 04:41:30.450125 [Byte1]: 30
7816 04:41:30.454514
7817 04:41:30.454618 Set Vref, RX VrefLevel [Byte0]: 31
7818 04:41:30.457526 [Byte1]: 31
7819 04:41:30.461900
7820 04:41:30.461982 Set Vref, RX VrefLevel [Byte0]: 32
7821 04:41:30.464720 [Byte1]: 32
7822 04:41:30.469756
7823 04:41:30.469837 Set Vref, RX VrefLevel [Byte0]: 33
7824 04:41:30.472356 [Byte1]: 33
7825 04:41:30.477041
7826 04:41:30.477135 Set Vref, RX VrefLevel [Byte0]: 34
7827 04:41:30.480025 [Byte1]: 34
7828 04:41:30.484953
7829 04:41:30.485034 Set Vref, RX VrefLevel [Byte0]: 35
7830 04:41:30.487825 [Byte1]: 35
7831 04:41:30.492171
7832 04:41:30.492252 Set Vref, RX VrefLevel [Byte0]: 36
7833 04:41:30.495261 [Byte1]: 36
7834 04:41:30.499765
7835 04:41:30.499847 Set Vref, RX VrefLevel [Byte0]: 37
7836 04:41:30.503203 [Byte1]: 37
7837 04:41:30.507754
7838 04:41:30.507825 Set Vref, RX VrefLevel [Byte0]: 38
7839 04:41:30.510823 [Byte1]: 38
7840 04:41:30.515007
7841 04:41:30.515116 Set Vref, RX VrefLevel [Byte0]: 39
7842 04:41:30.518334 [Byte1]: 39
7843 04:41:30.522470
7844 04:41:30.522546 Set Vref, RX VrefLevel [Byte0]: 40
7845 04:41:30.525978 [Byte1]: 40
7846 04:41:30.530331
7847 04:41:30.530434 Set Vref, RX VrefLevel [Byte0]: 41
7848 04:41:30.533812 [Byte1]: 41
7849 04:41:30.537687
7850 04:41:30.537763 Set Vref, RX VrefLevel [Byte0]: 42
7851 04:41:30.541135 [Byte1]: 42
7852 04:41:30.545411
7853 04:41:30.545507 Set Vref, RX VrefLevel [Byte0]: 43
7854 04:41:30.548645 [Byte1]: 43
7855 04:41:30.553044
7856 04:41:30.553148 Set Vref, RX VrefLevel [Byte0]: 44
7857 04:41:30.556211 [Byte1]: 44
7858 04:41:30.560564
7859 04:41:30.560665 Set Vref, RX VrefLevel [Byte0]: 45
7860 04:41:30.564006 [Byte1]: 45
7861 04:41:30.568692
7862 04:41:30.568794 Set Vref, RX VrefLevel [Byte0]: 46
7863 04:41:30.571253 [Byte1]: 46
7864 04:41:30.575893
7865 04:41:30.575993 Set Vref, RX VrefLevel [Byte0]: 47
7866 04:41:30.582218 [Byte1]: 47
7867 04:41:30.582320
7868 04:41:30.585650 Set Vref, RX VrefLevel [Byte0]: 48
7869 04:41:30.588871 [Byte1]: 48
7870 04:41:30.588970
7871 04:41:30.592034 Set Vref, RX VrefLevel [Byte0]: 49
7872 04:41:30.595632 [Byte1]: 49
7873 04:41:30.598837
7874 04:41:30.598944 Set Vref, RX VrefLevel [Byte0]: 50
7875 04:41:30.602599 [Byte1]: 50
7876 04:41:30.606111
7877 04:41:30.606186 Set Vref, RX VrefLevel [Byte0]: 51
7878 04:41:30.609848 [Byte1]: 51
7879 04:41:30.614089
7880 04:41:30.614172 Set Vref, RX VrefLevel [Byte0]: 52
7881 04:41:30.617493 [Byte1]: 52
7882 04:41:30.621437
7883 04:41:30.621518 Set Vref, RX VrefLevel [Byte0]: 53
7884 04:41:30.624701 [Byte1]: 53
7885 04:41:30.629434
7886 04:41:30.629515 Set Vref, RX VrefLevel [Byte0]: 54
7887 04:41:30.632459 [Byte1]: 54
7888 04:41:30.636627
7889 04:41:30.636709 Set Vref, RX VrefLevel [Byte0]: 55
7890 04:41:30.640125 [Byte1]: 55
7891 04:41:30.644759
7892 04:41:30.644840 Set Vref, RX VrefLevel [Byte0]: 56
7893 04:41:30.647653 [Byte1]: 56
7894 04:41:30.652273
7895 04:41:30.652354 Set Vref, RX VrefLevel [Byte0]: 57
7896 04:41:30.655254 [Byte1]: 57
7897 04:41:30.659508
7898 04:41:30.659589 Set Vref, RX VrefLevel [Byte0]: 58
7899 04:41:30.662823 [Byte1]: 58
7900 04:41:30.667245
7901 04:41:30.667326 Set Vref, RX VrefLevel [Byte0]: 59
7902 04:41:30.670697 [Byte1]: 59
7903 04:41:30.675222
7904 04:41:30.675336 Set Vref, RX VrefLevel [Byte0]: 60
7905 04:41:30.677844 [Byte1]: 60
7906 04:41:30.682701
7907 04:41:30.682782 Set Vref, RX VrefLevel [Byte0]: 61
7908 04:41:30.685988 [Byte1]: 61
7909 04:41:30.690039
7910 04:41:30.690121 Set Vref, RX VrefLevel [Byte0]: 62
7911 04:41:30.693204 [Byte1]: 62
7912 04:41:30.697485
7913 04:41:30.697589 Set Vref, RX VrefLevel [Byte0]: 63
7914 04:41:30.701053 [Byte1]: 63
7915 04:41:30.705442
7916 04:41:30.705544 Set Vref, RX VrefLevel [Byte0]: 64
7917 04:41:30.708342 [Byte1]: 64
7918 04:41:30.712971
7919 04:41:30.713046 Set Vref, RX VrefLevel [Byte0]: 65
7920 04:41:30.716384 [Byte1]: 65
7921 04:41:30.720512
7922 04:41:30.720608 Set Vref, RX VrefLevel [Byte0]: 66
7923 04:41:30.723971 [Byte1]: 66
7924 04:41:30.728161
7925 04:41:30.728234 Set Vref, RX VrefLevel [Byte0]: 67
7926 04:41:30.731072 [Byte1]: 67
7927 04:41:30.735728
7928 04:41:30.735827 Set Vref, RX VrefLevel [Byte0]: 68
7929 04:41:30.738769 [Byte1]: 68
7930 04:41:30.743355
7931 04:41:30.746230 Set Vref, RX VrefLevel [Byte0]: 69
7932 04:41:30.749739 [Byte1]: 69
7933 04:41:30.749812
7934 04:41:30.753282 Set Vref, RX VrefLevel [Byte0]: 70
7935 04:41:30.756295 [Byte1]: 70
7936 04:41:30.756394
7937 04:41:30.759706 Set Vref, RX VrefLevel [Byte0]: 71
7938 04:41:30.762673 [Byte1]: 71
7939 04:41:30.766109
7940 04:41:30.766181 Set Vref, RX VrefLevel [Byte0]: 72
7941 04:41:30.769402 [Byte1]: 72
7942 04:41:30.773690
7943 04:41:30.773771 Set Vref, RX VrefLevel [Byte0]: 73
7944 04:41:30.777494 [Byte1]: 73
7945 04:41:30.781430
7946 04:41:30.781512 Set Vref, RX VrefLevel [Byte0]: 74
7947 04:41:30.784391 [Byte1]: 74
7948 04:41:30.788716
7949 04:41:30.788798 Set Vref, RX VrefLevel [Byte0]: 75
7950 04:41:30.792227 [Byte1]: 75
7951 04:41:30.796956
7952 04:41:30.797063 Final RX Vref Byte 0 = 51 to rank0
7953 04:41:30.799915 Final RX Vref Byte 1 = 56 to rank0
7954 04:41:30.803290 Final RX Vref Byte 0 = 51 to rank1
7955 04:41:30.806614 Final RX Vref Byte 1 = 56 to rank1==
7956 04:41:30.809615 Dram Type= 6, Freq= 0, CH_0, rank 0
7957 04:41:30.816778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 04:41:30.816886 ==
7959 04:41:30.816978 DQS Delay:
7960 04:41:30.817074 DQS0 = 0, DQS1 = 0
7961 04:41:30.820046 DQM Delay:
7962 04:41:30.820117 DQM0 = 128, DQM1 = 124
7963 04:41:30.822908 DQ Delay:
7964 04:41:30.826404 DQ0 =128, DQ1 =130, DQ2 =124, DQ3 =126
7965 04:41:30.829990 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =132
7966 04:41:30.832798 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7967 04:41:30.836307 DQ12 =132, DQ13 =130, DQ14 =134, DQ15 =132
7968 04:41:30.836405
7969 04:41:30.836495
7970 04:41:30.836589
7971 04:41:30.839857 [DramC_TX_OE_Calibration] TA2
7972 04:41:30.842837 Original DQ_B0 (3 6) =30, OEN = 27
7973 04:41:30.846259 Original DQ_B1 (3 6) =30, OEN = 27
7974 04:41:30.849188 24, 0x0, End_B0=24 End_B1=24
7975 04:41:30.852735 25, 0x0, End_B0=25 End_B1=25
7976 04:41:30.852842 26, 0x0, End_B0=26 End_B1=26
7977 04:41:30.855692 27, 0x0, End_B0=27 End_B1=27
7978 04:41:30.859191 28, 0x0, End_B0=28 End_B1=28
7979 04:41:30.862575 29, 0x0, End_B0=29 End_B1=29
7980 04:41:30.862677 30, 0x0, End_B0=30 End_B1=30
7981 04:41:30.865548 31, 0x4141, End_B0=30 End_B1=30
7982 04:41:30.869098 Byte0 end_step=30 best_step=27
7983 04:41:30.872489 Byte1 end_step=30 best_step=27
7984 04:41:30.875349 Byte0 TX OE(2T, 0.5T) = (3, 3)
7985 04:41:30.879208 Byte1 TX OE(2T, 0.5T) = (3, 3)
7986 04:41:30.879305
7987 04:41:30.879428
7988 04:41:30.885299 [DQSOSCAuto] RK0, (LSB)MR18= 0x1916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
7989 04:41:30.888717 CH0 RK0: MR19=303, MR18=1916
7990 04:41:30.895201 CH0_RK0: MR19=0x303, MR18=0x1916, DQSOSC=397, MR23=63, INC=23, DEC=15
7991 04:41:30.895304
7992 04:41:30.898925 ----->DramcWriteLeveling(PI) begin...
7993 04:41:30.899024 ==
7994 04:41:30.905721 Dram Type= 6, Freq= 0, CH_0, rank 1
7995 04:41:30.905834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7996 04:41:30.905929 ==
7997 04:41:30.908422 Write leveling (Byte 0): 33 => 33
7998 04:41:30.912156 Write leveling (Byte 1): 27 => 27
7999 04:41:30.915113 DramcWriteLeveling(PI) end<-----
8000 04:41:30.915211
8001 04:41:30.915303 ==
8002 04:41:30.918400 Dram Type= 6, Freq= 0, CH_0, rank 1
8003 04:41:30.925097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 04:41:30.925200 ==
8005 04:41:30.925293 [Gating] SW mode calibration
8006 04:41:30.935125 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8007 04:41:30.938064 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8008 04:41:30.941661 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 04:41:30.948124 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 04:41:30.951852 1 4 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
8011 04:41:30.957973 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8012 04:41:30.961004 1 4 16 | B1->B0 | 2828 3434 | 0 1 | (1 1) (1 1)
8013 04:41:30.964341 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 04:41:30.970953 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 04:41:30.974503 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 04:41:30.977471 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 04:41:30.984236 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8018 04:41:30.987548 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8019 04:41:30.991080 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8020 04:41:30.994093 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8021 04:41:31.000764 1 5 20 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
8022 04:41:31.004161 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 04:41:31.010968 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 04:41:31.014269 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 04:41:31.017657 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8026 04:41:31.024249 1 6 8 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8027 04:41:31.026947 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8028 04:41:31.030302 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
8029 04:41:31.036944 1 6 20 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
8030 04:41:31.040305 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 04:41:31.043662 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 04:41:31.050177 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 04:41:31.053397 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 04:41:31.056794 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8035 04:41:31.063089 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8036 04:41:31.066857 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8037 04:41:31.069868 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8038 04:41:31.076620 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8039 04:41:31.079556 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 04:41:31.083062 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 04:41:31.089554 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 04:41:31.093286 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 04:41:31.095911 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 04:41:31.102854 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 04:41:31.106483 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 04:41:31.109333 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 04:41:31.116010 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 04:41:31.119405 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 04:41:31.122527 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 04:41:31.128907 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8051 04:41:31.132355 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8052 04:41:31.135932 Total UI for P1: 0, mck2ui 16
8053 04:41:31.139235 best dqsien dly found for B0: ( 1, 9, 8)
8054 04:41:31.142069 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8055 04:41:31.148855 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8056 04:41:31.152081 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 04:41:31.155677 Total UI for P1: 0, mck2ui 16
8058 04:41:31.158972 best dqsien dly found for B1: ( 1, 9, 16)
8059 04:41:31.162509 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8060 04:41:31.165508 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8061 04:41:31.165581
8062 04:41:31.168903 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8063 04:41:31.172255 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8064 04:41:31.175922 [Gating] SW calibration Done
8065 04:41:31.175991 ==
8066 04:41:31.178647 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 04:41:31.182147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 04:41:31.182240 ==
8069 04:41:31.185183 RX Vref Scan: 0
8070 04:41:31.185249
8071 04:41:31.188562 RX Vref 0 -> 0, step: 1
8072 04:41:31.188626
8073 04:41:31.188685 RX Delay 0 -> 252, step: 8
8074 04:41:31.195137 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
8075 04:41:31.198750 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
8076 04:41:31.201942 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
8077 04:41:31.205406 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
8078 04:41:31.211295 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
8079 04:41:31.214834 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
8080 04:41:31.217719 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
8081 04:41:31.221498 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
8082 04:41:31.224720 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
8083 04:41:31.230966 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
8084 04:41:31.234314 iDelay=192, Bit 10, Center 127 (72 ~ 183) 112
8085 04:41:31.238053 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
8086 04:41:31.241038 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
8087 04:41:31.244239 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
8088 04:41:31.251113 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
8089 04:41:31.254084 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
8090 04:41:31.254167 ==
8091 04:41:31.257509 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 04:41:31.261000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 04:41:31.261085 ==
8094 04:41:31.264301 DQS Delay:
8095 04:41:31.264383 DQS0 = 0, DQS1 = 0
8096 04:41:31.264447 DQM Delay:
8097 04:41:31.267695 DQM0 = 131, DQM1 = 124
8098 04:41:31.267777 DQ Delay:
8099 04:41:31.270781 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8100 04:41:31.277352 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8101 04:41:31.280662 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
8102 04:41:31.283734 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8103 04:41:31.283816
8104 04:41:31.283885
8105 04:41:31.283949 ==
8106 04:41:31.287338 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 04:41:31.290247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 04:41:31.290318 ==
8109 04:41:31.290378
8110 04:41:31.290435
8111 04:41:31.294279 TX Vref Scan disable
8112 04:41:31.297484 == TX Byte 0 ==
8113 04:41:31.300071 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8114 04:41:31.303638 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8115 04:41:31.306970 == TX Byte 1 ==
8116 04:41:31.310584 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8117 04:41:31.313308 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8118 04:41:31.313396 ==
8119 04:41:31.316953 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 04:41:31.323306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 04:41:31.323429 ==
8122 04:41:31.335234
8123 04:41:31.338784 TX Vref early break, caculate TX vref
8124 04:41:31.341923 TX Vref=16, minBit 0, minWin=23, winSum=381
8125 04:41:31.345201 TX Vref=18, minBit 8, minWin=23, winSum=391
8126 04:41:31.348494 TX Vref=20, minBit 8, minWin=24, winSum=402
8127 04:41:31.351606 TX Vref=22, minBit 9, minWin=24, winSum=405
8128 04:41:31.355158 TX Vref=24, minBit 3, minWin=25, winSum=417
8129 04:41:31.361528 TX Vref=26, minBit 4, minWin=25, winSum=425
8130 04:41:31.364561 TX Vref=28, minBit 11, minWin=25, winSum=425
8131 04:41:31.368276 TX Vref=30, minBit 1, minWin=25, winSum=420
8132 04:41:31.371655 TX Vref=32, minBit 1, minWin=25, winSum=408
8133 04:41:31.375008 TX Vref=34, minBit 7, minWin=24, winSum=402
8134 04:41:31.381739 [TxChooseVref] Worse bit 4, Min win 25, Win sum 425, Final Vref 26
8135 04:41:31.381852
8136 04:41:31.384791 Final TX Range 0 Vref 26
8137 04:41:31.384873
8138 04:41:31.384947 ==
8139 04:41:31.388010 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 04:41:31.391124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 04:41:31.391207 ==
8142 04:41:31.391272
8143 04:41:31.391332
8144 04:41:31.394721 TX Vref Scan disable
8145 04:41:31.401183 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8146 04:41:31.401281 == TX Byte 0 ==
8147 04:41:31.405050 u2DelayCellOfst[0]=10 cells (3 PI)
8148 04:41:31.408135 u2DelayCellOfst[1]=14 cells (4 PI)
8149 04:41:31.411471 u2DelayCellOfst[2]=7 cells (2 PI)
8150 04:41:31.414611 u2DelayCellOfst[3]=7 cells (2 PI)
8151 04:41:31.417648 u2DelayCellOfst[4]=7 cells (2 PI)
8152 04:41:31.421119 u2DelayCellOfst[5]=0 cells (0 PI)
8153 04:41:31.424406 u2DelayCellOfst[6]=14 cells (4 PI)
8154 04:41:31.427924 u2DelayCellOfst[7]=14 cells (4 PI)
8155 04:41:31.430840 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8156 04:41:31.433830 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8157 04:41:31.437308 == TX Byte 1 ==
8158 04:41:31.440555 u2DelayCellOfst[8]=0 cells (0 PI)
8159 04:41:31.444288 u2DelayCellOfst[9]=0 cells (0 PI)
8160 04:41:31.447173 u2DelayCellOfst[10]=7 cells (2 PI)
8161 04:41:31.450650 u2DelayCellOfst[11]=0 cells (0 PI)
8162 04:41:31.450731 u2DelayCellOfst[12]=10 cells (3 PI)
8163 04:41:31.453961 u2DelayCellOfst[13]=10 cells (3 PI)
8164 04:41:31.456926 u2DelayCellOfst[14]=14 cells (4 PI)
8165 04:41:31.460323 u2DelayCellOfst[15]=10 cells (3 PI)
8166 04:41:31.466746 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8167 04:41:31.470024 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8168 04:41:31.470098 DramC Write-DBI on
8169 04:41:31.473614 ==
8170 04:41:31.476781 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 04:41:31.480440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 04:41:31.480521 ==
8173 04:41:31.480586
8174 04:41:31.480645
8175 04:41:31.483611 TX Vref Scan disable
8176 04:41:31.483692 == TX Byte 0 ==
8177 04:41:31.490322 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8178 04:41:31.490403 == TX Byte 1 ==
8179 04:41:31.493105 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8180 04:41:31.496469 DramC Write-DBI off
8181 04:41:31.496551
8182 04:41:31.496615 [DATLAT]
8183 04:41:31.500127 Freq=1600, CH0 RK1
8184 04:41:31.500209
8185 04:41:31.500274 DATLAT Default: 0xf
8186 04:41:31.503760 0, 0xFFFF, sum = 0
8187 04:41:31.503843 1, 0xFFFF, sum = 0
8188 04:41:31.507102 2, 0xFFFF, sum = 0
8189 04:41:31.507212 3, 0xFFFF, sum = 0
8190 04:41:31.509724 4, 0xFFFF, sum = 0
8191 04:41:31.509807 5, 0xFFFF, sum = 0
8192 04:41:31.513227 6, 0xFFFF, sum = 0
8193 04:41:31.516598 7, 0xFFFF, sum = 0
8194 04:41:31.516682 8, 0xFFFF, sum = 0
8195 04:41:31.519579 9, 0xFFFF, sum = 0
8196 04:41:31.519663 10, 0xFFFF, sum = 0
8197 04:41:31.523427 11, 0xFFFF, sum = 0
8198 04:41:31.523510 12, 0xFFFF, sum = 0
8199 04:41:31.526412 13, 0xFFFF, sum = 0
8200 04:41:31.526495 14, 0x0, sum = 1
8201 04:41:31.529335 15, 0x0, sum = 2
8202 04:41:31.529417 16, 0x0, sum = 3
8203 04:41:31.532550 17, 0x0, sum = 4
8204 04:41:31.532634 best_step = 15
8205 04:41:31.532698
8206 04:41:31.532757 ==
8207 04:41:31.536193 Dram Type= 6, Freq= 0, CH_0, rank 1
8208 04:41:31.542635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8209 04:41:31.542720 ==
8210 04:41:31.542786 RX Vref Scan: 0
8211 04:41:31.542846
8212 04:41:31.546264 RX Vref 0 -> 0, step: 1
8213 04:41:31.546345
8214 04:41:31.548980 RX Delay 11 -> 252, step: 4
8215 04:41:31.552758 iDelay=191, Bit 0, Center 126 (79 ~ 174) 96
8216 04:41:31.555832 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8217 04:41:31.559294 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8218 04:41:31.565466 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8219 04:41:31.569431 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8220 04:41:31.572456 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8221 04:41:31.575757 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8222 04:41:31.579322 iDelay=191, Bit 7, Center 136 (87 ~ 186) 100
8223 04:41:31.585503 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8224 04:41:31.588816 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8225 04:41:31.592625 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8226 04:41:31.595573 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8227 04:41:31.601898 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8228 04:41:31.605295 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8229 04:41:31.608436 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8230 04:41:31.611755 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8231 04:41:31.611836 ==
8232 04:41:31.615035 Dram Type= 6, Freq= 0, CH_0, rank 1
8233 04:41:31.621630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 04:41:31.621712 ==
8235 04:41:31.621777 DQS Delay:
8236 04:41:31.621836 DQS0 = 0, DQS1 = 0
8237 04:41:31.624802 DQM Delay:
8238 04:41:31.624883 DQM0 = 129, DQM1 = 124
8239 04:41:31.628260 DQ Delay:
8240 04:41:31.631214 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8241 04:41:31.634644 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =136
8242 04:41:31.637872 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8243 04:41:31.641084 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8244 04:41:31.641165
8245 04:41:31.641228
8246 04:41:31.641287
8247 04:41:31.644924 [DramC_TX_OE_Calibration] TA2
8248 04:41:31.647809 Original DQ_B0 (3 6) =30, OEN = 27
8249 04:41:31.651582 Original DQ_B1 (3 6) =30, OEN = 27
8250 04:41:31.654792 24, 0x0, End_B0=24 End_B1=24
8251 04:41:31.654875 25, 0x0, End_B0=25 End_B1=25
8252 04:41:31.658152 26, 0x0, End_B0=26 End_B1=26
8253 04:41:31.661130 27, 0x0, End_B0=27 End_B1=27
8254 04:41:31.664308 28, 0x0, End_B0=28 End_B1=28
8255 04:41:31.667786 29, 0x0, End_B0=29 End_B1=29
8256 04:41:31.667862 30, 0x0, End_B0=30 End_B1=30
8257 04:41:31.670781 31, 0x4141, End_B0=30 End_B1=30
8258 04:41:31.674064 Byte0 end_step=30 best_step=27
8259 04:41:31.677522 Byte1 end_step=30 best_step=27
8260 04:41:31.680959 Byte0 TX OE(2T, 0.5T) = (3, 3)
8261 04:41:31.684301 Byte1 TX OE(2T, 0.5T) = (3, 3)
8262 04:41:31.684382
8263 04:41:31.684446
8264 04:41:31.690932 [DQSOSCAuto] RK1, (LSB)MR18= 0x1310, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8265 04:41:31.694337 CH0 RK1: MR19=303, MR18=1310
8266 04:41:31.700389 CH0_RK1: MR19=0x303, MR18=0x1310, DQSOSC=400, MR23=63, INC=23, DEC=15
8267 04:41:31.703569 [RxdqsGatingPostProcess] freq 1600
8268 04:41:31.710974 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8269 04:41:31.711056 best DQS0 dly(2T, 0.5T) = (1, 1)
8270 04:41:31.713830 best DQS1 dly(2T, 0.5T) = (1, 1)
8271 04:41:31.716884 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8272 04:41:31.720200 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8273 04:41:31.723827 best DQS0 dly(2T, 0.5T) = (1, 1)
8274 04:41:31.726729 best DQS1 dly(2T, 0.5T) = (1, 1)
8275 04:41:31.730162 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8276 04:41:31.733606 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8277 04:41:31.736648 Pre-setting of DQS Precalculation
8278 04:41:31.740124 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8279 04:41:31.743142 ==
8280 04:41:31.743223 Dram Type= 6, Freq= 0, CH_1, rank 0
8281 04:41:31.750125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8282 04:41:31.750207 ==
8283 04:41:31.753104 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8284 04:41:31.759904 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8285 04:41:31.762796 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8286 04:41:31.769510 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8287 04:41:31.777702 [CA 0] Center 42 (12~72) winsize 61
8288 04:41:31.781413 [CA 1] Center 42 (12~72) winsize 61
8289 04:41:31.784140 [CA 2] Center 39 (10~69) winsize 60
8290 04:41:31.787819 [CA 3] Center 37 (8~67) winsize 60
8291 04:41:31.790642 [CA 4] Center 38 (8~69) winsize 62
8292 04:41:31.794144 [CA 5] Center 37 (7~67) winsize 61
8293 04:41:31.794226
8294 04:41:31.797895 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8295 04:41:31.797977
8296 04:41:31.804062 [CATrainingPosCal] consider 1 rank data
8297 04:41:31.804144 u2DelayCellTimex100 = 275/100 ps
8298 04:41:31.811072 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8299 04:41:31.814156 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8300 04:41:31.817112 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
8301 04:41:31.820702 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8302 04:41:31.823772 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8303 04:41:31.827697 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8304 04:41:31.827779
8305 04:41:31.830897 CA PerBit enable=1, Macro0, CA PI delay=37
8306 04:41:31.830978
8307 04:41:31.833676 [CBTSetCACLKResult] CA Dly = 37
8308 04:41:31.837074 CS Dly: 8 (0~39)
8309 04:41:31.840686 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8310 04:41:31.843971 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8311 04:41:31.844056 ==
8312 04:41:31.846756 Dram Type= 6, Freq= 0, CH_1, rank 1
8313 04:41:31.853633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 04:41:31.853714 ==
8315 04:41:31.857108 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8316 04:41:31.863298 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8317 04:41:31.866908 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8318 04:41:31.873392 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8319 04:41:31.881072 [CA 0] Center 41 (11~72) winsize 62
8320 04:41:31.884679 [CA 1] Center 42 (13~72) winsize 60
8321 04:41:31.888059 [CA 2] Center 38 (9~68) winsize 60
8322 04:41:31.890987 [CA 3] Center 37 (7~67) winsize 61
8323 04:41:31.894680 [CA 4] Center 37 (8~67) winsize 60
8324 04:41:31.897968 [CA 5] Center 37 (7~67) winsize 61
8325 04:41:31.898049
8326 04:41:31.900921 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8327 04:41:31.901002
8328 04:41:31.904426 [CATrainingPosCal] consider 2 rank data
8329 04:41:31.907257 u2DelayCellTimex100 = 275/100 ps
8330 04:41:31.911075 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8331 04:41:31.917810 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8332 04:41:31.920725 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
8333 04:41:31.924133 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8334 04:41:31.927786 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8335 04:41:31.930778 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8336 04:41:31.930859
8337 04:41:31.934019 CA PerBit enable=1, Macro0, CA PI delay=37
8338 04:41:31.934100
8339 04:41:31.937336 [CBTSetCACLKResult] CA Dly = 37
8340 04:41:31.940541 CS Dly: 9 (0~42)
8341 04:41:31.943666 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8342 04:41:31.947069 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8343 04:41:31.947151
8344 04:41:31.950797 ----->DramcWriteLeveling(PI) begin...
8345 04:41:31.950881 ==
8346 04:41:31.953846 Dram Type= 6, Freq= 0, CH_1, rank 0
8347 04:41:31.960086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 04:41:31.960169 ==
8349 04:41:31.963403 Write leveling (Byte 0): 23 => 23
8350 04:41:31.966819 Write leveling (Byte 1): 28 => 28
8351 04:41:31.966899 DramcWriteLeveling(PI) end<-----
8352 04:41:31.966963
8353 04:41:31.970750 ==
8354 04:41:31.973777 Dram Type= 6, Freq= 0, CH_1, rank 0
8355 04:41:31.976739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8356 04:41:31.976812 ==
8357 04:41:31.980083 [Gating] SW mode calibration
8358 04:41:31.987079 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8359 04:41:31.990205 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8360 04:41:31.996664 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 04:41:31.999630 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 04:41:32.006094 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 04:41:32.009509 1 4 12 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
8364 04:41:32.012872 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 04:41:32.019294 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 04:41:32.022907 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 04:41:32.026264 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 04:41:32.029239 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 04:41:32.036207 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 04:41:32.039308 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8371 04:41:32.042501 1 5 12 | B1->B0 | 3030 2424 | 1 0 | (1 0) (1 0)
8372 04:41:32.049281 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8373 04:41:32.053105 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 04:41:32.056137 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 04:41:32.062652 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 04:41:32.065861 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 04:41:32.069104 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 04:41:32.075215 1 6 8 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
8379 04:41:32.078851 1 6 12 | B1->B0 | 3030 4444 | 0 1 | (0 0) (0 0)
8380 04:41:32.081861 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 04:41:32.088642 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 04:41:32.091714 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 04:41:32.098595 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 04:41:32.101811 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 04:41:32.104854 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 04:41:32.111590 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 04:41:32.114575 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8388 04:41:32.117855 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8389 04:41:32.124857 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 04:41:32.128394 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 04:41:32.131878 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 04:41:32.138089 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 04:41:32.141072 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 04:41:32.144370 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 04:41:32.151585 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 04:41:32.154656 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 04:41:32.157599 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 04:41:32.164358 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 04:41:32.167585 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 04:41:32.170955 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 04:41:32.177439 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 04:41:32.180780 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8403 04:41:32.184517 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8404 04:41:32.191065 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8405 04:41:32.191146 Total UI for P1: 0, mck2ui 16
8406 04:41:32.194362 best dqsien dly found for B0: ( 1, 9, 10)
8407 04:41:32.200580 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 04:41:32.204408 Total UI for P1: 0, mck2ui 16
8409 04:41:32.206857 best dqsien dly found for B1: ( 1, 9, 14)
8410 04:41:32.210676 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8411 04:41:32.213724 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8412 04:41:32.213797
8413 04:41:32.217082 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8414 04:41:32.220627 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8415 04:41:32.223574 [Gating] SW calibration Done
8416 04:41:32.223649 ==
8417 04:41:32.226586 Dram Type= 6, Freq= 0, CH_1, rank 0
8418 04:41:32.229901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 04:41:32.233617 ==
8420 04:41:32.233690 RX Vref Scan: 0
8421 04:41:32.233768
8422 04:41:32.236456 RX Vref 0 -> 0, step: 1
8423 04:41:32.236533
8424 04:41:32.240308 RX Delay 0 -> 252, step: 8
8425 04:41:32.243316 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8426 04:41:32.246784 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8427 04:41:32.250083 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8428 04:41:32.253348 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8429 04:41:32.259904 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8430 04:41:32.262837 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8431 04:41:32.266263 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8432 04:41:32.269511 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8433 04:41:32.272937 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8434 04:41:32.279767 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8435 04:41:32.283090 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8436 04:41:32.285875 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8437 04:41:32.289454 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8438 04:41:32.295984 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8439 04:41:32.299591 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8440 04:41:32.302258 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8441 04:41:32.302337 ==
8442 04:41:32.305629 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 04:41:32.309079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 04:41:32.309155 ==
8445 04:41:32.312601 DQS Delay:
8446 04:41:32.312674 DQS0 = 0, DQS1 = 0
8447 04:41:32.315958 DQM Delay:
8448 04:41:32.316029 DQM0 = 134, DQM1 = 131
8449 04:41:32.316109 DQ Delay:
8450 04:41:32.322832 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8451 04:41:32.326147 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8452 04:41:32.328655 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8453 04:41:32.332026 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8454 04:41:32.332105
8455 04:41:32.332167
8456 04:41:32.332226 ==
8457 04:41:32.335515 Dram Type= 6, Freq= 0, CH_1, rank 0
8458 04:41:32.338875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8459 04:41:32.338956 ==
8460 04:41:32.339020
8461 04:41:32.339079
8462 04:41:32.342051 TX Vref Scan disable
8463 04:41:32.345163 == TX Byte 0 ==
8464 04:41:32.348527 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8465 04:41:32.352187 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8466 04:41:32.354911 == TX Byte 1 ==
8467 04:41:32.358700 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8468 04:41:32.361769 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8469 04:41:32.361854 ==
8470 04:41:32.364973 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 04:41:32.371513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 04:41:32.371637 ==
8473 04:41:32.384480
8474 04:41:32.388437 TX Vref early break, caculate TX vref
8475 04:41:32.391189 TX Vref=16, minBit 8, minWin=22, winSum=366
8476 04:41:32.394442 TX Vref=18, minBit 8, minWin=22, winSum=379
8477 04:41:32.398221 TX Vref=20, minBit 11, minWin=22, winSum=381
8478 04:41:32.401283 TX Vref=22, minBit 8, minWin=24, winSum=401
8479 04:41:32.404632 TX Vref=24, minBit 1, minWin=25, winSum=405
8480 04:41:32.410956 TX Vref=26, minBit 9, minWin=25, winSum=415
8481 04:41:32.414820 TX Vref=28, minBit 8, minWin=25, winSum=418
8482 04:41:32.417784 TX Vref=30, minBit 9, minWin=24, winSum=412
8483 04:41:32.420809 TX Vref=32, minBit 8, minWin=24, winSum=404
8484 04:41:32.424346 TX Vref=34, minBit 0, minWin=24, winSum=397
8485 04:41:32.431452 TX Vref=36, minBit 9, minWin=22, winSum=383
8486 04:41:32.434612 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 28
8487 04:41:32.434691
8488 04:41:32.437470 Final TX Range 0 Vref 28
8489 04:41:32.437550
8490 04:41:32.437625 ==
8491 04:41:32.441391 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 04:41:32.443821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 04:41:32.447312 ==
8494 04:41:32.447409
8495 04:41:32.447494
8496 04:41:32.447570 TX Vref Scan disable
8497 04:41:32.453998 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8498 04:41:32.454073 == TX Byte 0 ==
8499 04:41:32.457220 u2DelayCellOfst[0]=14 cells (4 PI)
8500 04:41:32.460791 u2DelayCellOfst[1]=10 cells (3 PI)
8501 04:41:32.463660 u2DelayCellOfst[2]=0 cells (0 PI)
8502 04:41:32.467095 u2DelayCellOfst[3]=7 cells (2 PI)
8503 04:41:32.470430 u2DelayCellOfst[4]=10 cells (3 PI)
8504 04:41:32.473947 u2DelayCellOfst[5]=17 cells (5 PI)
8505 04:41:32.477407 u2DelayCellOfst[6]=17 cells (5 PI)
8506 04:41:32.480420 u2DelayCellOfst[7]=7 cells (2 PI)
8507 04:41:32.483303 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8508 04:41:32.486639 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8509 04:41:32.490336 == TX Byte 1 ==
8510 04:41:32.493317 u2DelayCellOfst[8]=0 cells (0 PI)
8511 04:41:32.496681 u2DelayCellOfst[9]=3 cells (1 PI)
8512 04:41:32.500122 u2DelayCellOfst[10]=14 cells (4 PI)
8513 04:41:32.503534 u2DelayCellOfst[11]=7 cells (2 PI)
8514 04:41:32.507432 u2DelayCellOfst[12]=14 cells (4 PI)
8515 04:41:32.510173 u2DelayCellOfst[13]=14 cells (4 PI)
8516 04:41:32.513043 u2DelayCellOfst[14]=17 cells (5 PI)
8517 04:41:32.516438 u2DelayCellOfst[15]=17 cells (5 PI)
8518 04:41:32.519723 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8519 04:41:32.523315 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8520 04:41:32.526303 DramC Write-DBI on
8521 04:41:32.526384 ==
8522 04:41:32.529784 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 04:41:32.533019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 04:41:32.533101 ==
8525 04:41:32.533164
8526 04:41:32.533224
8527 04:41:32.536255 TX Vref Scan disable
8528 04:41:32.536336 == TX Byte 0 ==
8529 04:41:32.543346 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8530 04:41:32.543464 == TX Byte 1 ==
8531 04:41:32.546279 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8532 04:41:32.549730 DramC Write-DBI off
8533 04:41:32.549809
8534 04:41:32.549873 [DATLAT]
8535 04:41:32.552564 Freq=1600, CH1 RK0
8536 04:41:32.552645
8537 04:41:32.555908 DATLAT Default: 0xf
8538 04:41:32.555988 0, 0xFFFF, sum = 0
8539 04:41:32.559224 1, 0xFFFF, sum = 0
8540 04:41:32.559306 2, 0xFFFF, sum = 0
8541 04:41:32.562656 3, 0xFFFF, sum = 0
8542 04:41:32.562737 4, 0xFFFF, sum = 0
8543 04:41:32.566059 5, 0xFFFF, sum = 0
8544 04:41:32.566141 6, 0xFFFF, sum = 0
8545 04:41:32.569062 7, 0xFFFF, sum = 0
8546 04:41:32.569143 8, 0xFFFF, sum = 0
8547 04:41:32.572343 9, 0xFFFF, sum = 0
8548 04:41:32.572425 10, 0xFFFF, sum = 0
8549 04:41:32.575710 11, 0xFFFF, sum = 0
8550 04:41:32.575791 12, 0xFFFF, sum = 0
8551 04:41:32.579232 13, 0xFFFF, sum = 0
8552 04:41:32.579313 14, 0x0, sum = 1
8553 04:41:32.582599 15, 0x0, sum = 2
8554 04:41:32.582706 16, 0x0, sum = 3
8555 04:41:32.585451 17, 0x0, sum = 4
8556 04:41:32.585533 best_step = 15
8557 04:41:32.585597
8558 04:41:32.585656 ==
8559 04:41:32.589161 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 04:41:32.596052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 04:41:32.596133 ==
8562 04:41:32.596197 RX Vref Scan: 1
8563 04:41:32.596257
8564 04:41:32.598851 Set Vref Range= 24 -> 127
8565 04:41:32.598932
8566 04:41:32.602229 RX Vref 24 -> 127, step: 1
8567 04:41:32.602310
8568 04:41:32.605300 RX Delay 19 -> 252, step: 4
8569 04:41:32.605381
8570 04:41:32.608911 Set Vref, RX VrefLevel [Byte0]: 24
8571 04:41:32.608992 [Byte1]: 24
8572 04:41:32.613264
8573 04:41:32.613345 Set Vref, RX VrefLevel [Byte0]: 25
8574 04:41:32.616331 [Byte1]: 25
8575 04:41:32.620903
8576 04:41:32.620984 Set Vref, RX VrefLevel [Byte0]: 26
8577 04:41:32.623975 [Byte1]: 26
8578 04:41:32.628095
8579 04:41:32.628176 Set Vref, RX VrefLevel [Byte0]: 27
8580 04:41:32.631614 [Byte1]: 27
8581 04:41:32.635732
8582 04:41:32.635812 Set Vref, RX VrefLevel [Byte0]: 28
8583 04:41:32.639115 [Byte1]: 28
8584 04:41:32.643447
8585 04:41:32.643527 Set Vref, RX VrefLevel [Byte0]: 29
8586 04:41:32.646888 [Byte1]: 29
8587 04:41:32.651009
8588 04:41:32.651090 Set Vref, RX VrefLevel [Byte0]: 30
8589 04:41:32.654587 [Byte1]: 30
8590 04:41:32.658796
8591 04:41:32.658877 Set Vref, RX VrefLevel [Byte0]: 31
8592 04:41:32.662204 [Byte1]: 31
8593 04:41:32.666179
8594 04:41:32.666259 Set Vref, RX VrefLevel [Byte0]: 32
8595 04:41:32.669932 [Byte1]: 32
8596 04:41:32.673445
8597 04:41:32.673526 Set Vref, RX VrefLevel [Byte0]: 33
8598 04:41:32.676899 [Byte1]: 33
8599 04:41:32.681066
8600 04:41:32.681146 Set Vref, RX VrefLevel [Byte0]: 34
8601 04:41:32.687836 [Byte1]: 34
8602 04:41:32.687916
8603 04:41:32.691236 Set Vref, RX VrefLevel [Byte0]: 35
8604 04:41:32.694459 [Byte1]: 35
8605 04:41:32.694540
8606 04:41:32.697786 Set Vref, RX VrefLevel [Byte0]: 36
8607 04:41:32.701022 [Byte1]: 36
8608 04:41:32.701104
8609 04:41:32.704369 Set Vref, RX VrefLevel [Byte0]: 37
8610 04:41:32.707843 [Byte1]: 37
8611 04:41:32.711782
8612 04:41:32.711863 Set Vref, RX VrefLevel [Byte0]: 38
8613 04:41:32.714671 [Byte1]: 38
8614 04:41:32.719267
8615 04:41:32.719346 Set Vref, RX VrefLevel [Byte0]: 39
8616 04:41:32.722174 [Byte1]: 39
8617 04:41:32.726604
8618 04:41:32.726684 Set Vref, RX VrefLevel [Byte0]: 40
8619 04:41:32.729955 [Byte1]: 40
8620 04:41:32.734499
8621 04:41:32.734596 Set Vref, RX VrefLevel [Byte0]: 41
8622 04:41:32.737750 [Byte1]: 41
8623 04:41:32.741823
8624 04:41:32.741903 Set Vref, RX VrefLevel [Byte0]: 42
8625 04:41:32.745055 [Byte1]: 42
8626 04:41:32.749598
8627 04:41:32.749678 Set Vref, RX VrefLevel [Byte0]: 43
8628 04:41:32.752843 [Byte1]: 43
8629 04:41:32.757111
8630 04:41:32.757191 Set Vref, RX VrefLevel [Byte0]: 44
8631 04:41:32.760034 [Byte1]: 44
8632 04:41:32.764636
8633 04:41:32.764715 Set Vref, RX VrefLevel [Byte0]: 45
8634 04:41:32.767689 [Byte1]: 45
8635 04:41:32.772182
8636 04:41:32.772262 Set Vref, RX VrefLevel [Byte0]: 46
8637 04:41:32.775489 [Byte1]: 46
8638 04:41:32.779543
8639 04:41:32.779623 Set Vref, RX VrefLevel [Byte0]: 47
8640 04:41:32.786209 [Byte1]: 47
8641 04:41:32.786289
8642 04:41:32.789333 Set Vref, RX VrefLevel [Byte0]: 48
8643 04:41:32.792853 [Byte1]: 48
8644 04:41:32.792922
8645 04:41:32.796366 Set Vref, RX VrefLevel [Byte0]: 49
8646 04:41:32.799152 [Byte1]: 49
8647 04:41:32.799228
8648 04:41:32.802471 Set Vref, RX VrefLevel [Byte0]: 50
8649 04:41:32.806024 [Byte1]: 50
8650 04:41:32.809991
8651 04:41:32.810063 Set Vref, RX VrefLevel [Byte0]: 51
8652 04:41:32.813275 [Byte1]: 51
8653 04:41:32.817701
8654 04:41:32.817772 Set Vref, RX VrefLevel [Byte0]: 52
8655 04:41:32.821078 [Byte1]: 52
8656 04:41:32.825337
8657 04:41:32.825409 Set Vref, RX VrefLevel [Byte0]: 53
8658 04:41:32.828336 [Byte1]: 53
8659 04:41:32.832630
8660 04:41:32.832701 Set Vref, RX VrefLevel [Byte0]: 54
8661 04:41:32.835778 [Byte1]: 54
8662 04:41:32.840360
8663 04:41:32.840455 Set Vref, RX VrefLevel [Byte0]: 55
8664 04:41:32.843535 [Byte1]: 55
8665 04:41:32.848110
8666 04:41:32.848184 Set Vref, RX VrefLevel [Byte0]: 56
8667 04:41:32.850922 [Byte1]: 56
8668 04:41:32.855510
8669 04:41:32.855582 Set Vref, RX VrefLevel [Byte0]: 57
8670 04:41:32.858779 [Byte1]: 57
8671 04:41:32.863569
8672 04:41:32.863645 Set Vref, RX VrefLevel [Byte0]: 58
8673 04:41:32.866147 [Byte1]: 58
8674 04:41:32.870689
8675 04:41:32.870786 Set Vref, RX VrefLevel [Byte0]: 59
8676 04:41:32.873836 [Byte1]: 59
8677 04:41:32.877816
8678 04:41:32.877889 Set Vref, RX VrefLevel [Byte0]: 60
8679 04:41:32.881308 [Byte1]: 60
8680 04:41:32.885675
8681 04:41:32.885752 Set Vref, RX VrefLevel [Byte0]: 61
8682 04:41:32.889235 [Byte1]: 61
8683 04:41:32.893414
8684 04:41:32.893496 Set Vref, RX VrefLevel [Byte0]: 62
8685 04:41:32.896555 [Byte1]: 62
8686 04:41:32.900862
8687 04:41:32.900938 Set Vref, RX VrefLevel [Byte0]: 63
8688 04:41:32.904306 [Byte1]: 63
8689 04:41:32.908357
8690 04:41:32.908432 Set Vref, RX VrefLevel [Byte0]: 64
8691 04:41:32.911577 [Byte1]: 64
8692 04:41:32.916272
8693 04:41:32.916351 Set Vref, RX VrefLevel [Byte0]: 65
8694 04:41:32.919394 [Byte1]: 65
8695 04:41:32.923765
8696 04:41:32.923841 Set Vref, RX VrefLevel [Byte0]: 66
8697 04:41:32.927096 [Byte1]: 66
8698 04:41:32.931531
8699 04:41:32.931614 Set Vref, RX VrefLevel [Byte0]: 67
8700 04:41:32.934232 [Byte1]: 67
8701 04:41:32.938741
8702 04:41:32.938817 Set Vref, RX VrefLevel [Byte0]: 68
8703 04:41:32.941723 [Byte1]: 68
8704 04:41:32.946496
8705 04:41:32.946577 Set Vref, RX VrefLevel [Byte0]: 69
8706 04:41:32.950059 [Byte1]: 69
8707 04:41:32.953917
8708 04:41:32.954024 Set Vref, RX VrefLevel [Byte0]: 70
8709 04:41:32.957382 [Byte1]: 70
8710 04:41:32.961532
8711 04:41:32.961613 Set Vref, RX VrefLevel [Byte0]: 71
8712 04:41:32.964939 [Byte1]: 71
8713 04:41:32.968775
8714 04:41:32.968853 Final RX Vref Byte 0 = 55 to rank0
8715 04:41:32.972830 Final RX Vref Byte 1 = 61 to rank0
8716 04:41:32.975822 Final RX Vref Byte 0 = 55 to rank1
8717 04:41:32.978677 Final RX Vref Byte 1 = 61 to rank1==
8718 04:41:32.982136 Dram Type= 6, Freq= 0, CH_1, rank 0
8719 04:41:32.989053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8720 04:41:32.989136 ==
8721 04:41:32.989235 DQS Delay:
8722 04:41:32.992295 DQS0 = 0, DQS1 = 0
8723 04:41:32.992374 DQM Delay:
8724 04:41:32.992453 DQM0 = 132, DQM1 = 130
8725 04:41:32.995605 DQ Delay:
8726 04:41:32.998789 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =132
8727 04:41:33.001759 DQ4 =128, DQ5 =142, DQ6 =146, DQ7 =126
8728 04:41:33.005299 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8729 04:41:33.008946 DQ12 =140, DQ13 =140, DQ14 =136, DQ15 =140
8730 04:41:33.009021
8731 04:41:33.009101
8732 04:41:33.009184
8733 04:41:33.011983 [DramC_TX_OE_Calibration] TA2
8734 04:41:33.014889 Original DQ_B0 (3 6) =30, OEN = 27
8735 04:41:33.018253 Original DQ_B1 (3 6) =30, OEN = 27
8736 04:41:33.021861 24, 0x0, End_B0=24 End_B1=24
8737 04:41:33.025071 25, 0x0, End_B0=25 End_B1=25
8738 04:41:33.025148 26, 0x0, End_B0=26 End_B1=26
8739 04:41:33.027998 27, 0x0, End_B0=27 End_B1=27
8740 04:41:33.031200 28, 0x0, End_B0=28 End_B1=28
8741 04:41:33.034803 29, 0x0, End_B0=29 End_B1=29
8742 04:41:33.034879 30, 0x0, End_B0=30 End_B1=30
8743 04:41:33.037819 31, 0x4141, End_B0=30 End_B1=30
8744 04:41:33.041132 Byte0 end_step=30 best_step=27
8745 04:41:33.044568 Byte1 end_step=30 best_step=27
8746 04:41:33.048058 Byte0 TX OE(2T, 0.5T) = (3, 3)
8747 04:41:33.051500 Byte1 TX OE(2T, 0.5T) = (3, 3)
8748 04:41:33.051567
8749 04:41:33.051626
8750 04:41:33.057690 [DQSOSCAuto] RK0, (LSB)MR18= 0xe17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 402 ps
8751 04:41:33.060806 CH1 RK0: MR19=303, MR18=E17
8752 04:41:33.067582 CH1_RK0: MR19=0x303, MR18=0xE17, DQSOSC=398, MR23=63, INC=23, DEC=15
8753 04:41:33.067666
8754 04:41:33.071288 ----->DramcWriteLeveling(PI) begin...
8755 04:41:33.071394 ==
8756 04:41:33.074704 Dram Type= 6, Freq= 0, CH_1, rank 1
8757 04:41:33.077607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8758 04:41:33.077689 ==
8759 04:41:33.080863 Write leveling (Byte 0): 24 => 24
8760 04:41:33.084327 Write leveling (Byte 1): 26 => 26
8761 04:41:33.087486 DramcWriteLeveling(PI) end<-----
8762 04:41:33.087571
8763 04:41:33.087635 ==
8764 04:41:33.091358 Dram Type= 6, Freq= 0, CH_1, rank 1
8765 04:41:33.093994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8766 04:41:33.097255 ==
8767 04:41:33.097337 [Gating] SW mode calibration
8768 04:41:33.107155 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8769 04:41:33.110423 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8770 04:41:33.114008 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 04:41:33.120545 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 04:41:33.123972 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8773 04:41:33.126838 1 4 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8774 04:41:33.133209 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 04:41:33.136876 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 04:41:33.140429 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 04:41:33.146671 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 04:41:33.150014 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 04:41:33.156567 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8780 04:41:33.159920 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8781 04:41:33.163084 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8782 04:41:33.169625 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 04:41:33.172613 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 04:41:33.176180 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 04:41:33.179697 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 04:41:33.186353 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 04:41:33.189805 1 6 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8788 04:41:33.192778 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8789 04:41:33.199704 1 6 12 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
8790 04:41:33.202585 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 04:41:33.206239 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 04:41:33.213078 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 04:41:33.216004 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 04:41:33.219042 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 04:41:33.225732 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8796 04:41:33.228770 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8797 04:41:33.232448 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8798 04:41:33.238982 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8799 04:41:33.242236 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 04:41:33.248832 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 04:41:33.251658 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 04:41:33.255641 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 04:41:33.261942 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 04:41:33.265536 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 04:41:33.268585 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 04:41:33.274801 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 04:41:33.278377 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 04:41:33.281397 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 04:41:33.288687 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 04:41:33.291415 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 04:41:33.294776 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8812 04:41:33.301816 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8813 04:41:33.304645 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8814 04:41:33.308219 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 04:41:33.311688 Total UI for P1: 0, mck2ui 16
8816 04:41:33.314664 best dqsien dly found for B0: ( 1, 9, 8)
8817 04:41:33.317858 Total UI for P1: 0, mck2ui 16
8818 04:41:33.321041 best dqsien dly found for B1: ( 1, 9, 12)
8819 04:41:33.324392 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8820 04:41:33.327773 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8821 04:41:33.327855
8822 04:41:33.330783 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8823 04:41:33.337671 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8824 04:41:33.337782 [Gating] SW calibration Done
8825 04:41:33.340930 ==
8826 04:41:33.341011 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 04:41:33.347355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 04:41:33.347488 ==
8829 04:41:33.347587 RX Vref Scan: 0
8830 04:41:33.347680
8831 04:41:33.350754 RX Vref 0 -> 0, step: 1
8832 04:41:33.350834
8833 04:41:33.354097 RX Delay 0 -> 252, step: 8
8834 04:41:33.357360 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8835 04:41:33.360566 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8836 04:41:33.363801 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8837 04:41:33.370375 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8838 04:41:33.373748 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8839 04:41:33.377641 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8840 04:41:33.380307 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8841 04:41:33.383682 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8842 04:41:33.390278 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8843 04:41:33.393900 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8844 04:41:33.396863 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8845 04:41:33.400457 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8846 04:41:33.406830 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8847 04:41:33.410076 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8848 04:41:33.413432 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8849 04:41:33.416272 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8850 04:41:33.416355 ==
8851 04:41:33.419832 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 04:41:33.426316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 04:41:33.426424 ==
8854 04:41:33.426516 DQS Delay:
8855 04:41:33.429847 DQS0 = 0, DQS1 = 0
8856 04:41:33.429929 DQM Delay:
8857 04:41:33.430039 DQM0 = 137, DQM1 = 131
8858 04:41:33.432934 DQ Delay:
8859 04:41:33.436537 DQ0 =139, DQ1 =135, DQ2 =127, DQ3 =135
8860 04:41:33.439393 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8861 04:41:33.443299 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8862 04:41:33.446190 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8863 04:41:33.446291
8864 04:41:33.446405
8865 04:41:33.446487 ==
8866 04:41:33.449317 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 04:41:33.453064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 04:41:33.456376 ==
8869 04:41:33.456461
8870 04:41:33.456525
8871 04:41:33.456585 TX Vref Scan disable
8872 04:41:33.459217 == TX Byte 0 ==
8873 04:41:33.462567 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8874 04:41:33.466279 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8875 04:41:33.469358 == TX Byte 1 ==
8876 04:41:33.472606 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8877 04:41:33.479223 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8878 04:41:33.479330 ==
8879 04:41:33.482263 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 04:41:33.485717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 04:41:33.485825 ==
8882 04:41:33.499033
8883 04:41:33.502401 TX Vref early break, caculate TX vref
8884 04:41:33.505560 TX Vref=16, minBit 9, minWin=20, winSum=374
8885 04:41:33.509234 TX Vref=18, minBit 9, minWin=22, winSum=385
8886 04:41:33.512428 TX Vref=20, minBit 9, minWin=22, winSum=391
8887 04:41:33.515343 TX Vref=22, minBit 5, minWin=24, winSum=402
8888 04:41:33.518767 TX Vref=24, minBit 9, minWin=24, winSum=409
8889 04:41:33.525208 TX Vref=26, minBit 9, minWin=23, winSum=412
8890 04:41:33.528658 TX Vref=28, minBit 5, minWin=25, winSum=422
8891 04:41:33.532075 TX Vref=30, minBit 9, minWin=25, winSum=421
8892 04:41:33.535653 TX Vref=32, minBit 9, minWin=24, winSum=409
8893 04:41:33.538646 TX Vref=34, minBit 0, minWin=24, winSum=404
8894 04:41:33.544937 TX Vref=36, minBit 0, minWin=23, winSum=394
8895 04:41:33.548362 [TxChooseVref] Worse bit 5, Min win 25, Win sum 422, Final Vref 28
8896 04:41:33.548487
8897 04:41:33.551975 Final TX Range 0 Vref 28
8898 04:41:33.552061
8899 04:41:33.552142 ==
8900 04:41:33.555074 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 04:41:33.558251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 04:41:33.561588 ==
8903 04:41:33.561707
8904 04:41:33.561800
8905 04:41:33.561888 TX Vref Scan disable
8906 04:41:33.568632 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8907 04:41:33.568743 == TX Byte 0 ==
8908 04:41:33.571928 u2DelayCellOfst[0]=14 cells (4 PI)
8909 04:41:33.575660 u2DelayCellOfst[1]=7 cells (2 PI)
8910 04:41:33.578381 u2DelayCellOfst[2]=0 cells (0 PI)
8911 04:41:33.581656 u2DelayCellOfst[3]=7 cells (2 PI)
8912 04:41:33.584864 u2DelayCellOfst[4]=7 cells (2 PI)
8913 04:41:33.588498 u2DelayCellOfst[5]=14 cells (4 PI)
8914 04:41:33.591949 u2DelayCellOfst[6]=14 cells (4 PI)
8915 04:41:33.595002 u2DelayCellOfst[7]=7 cells (2 PI)
8916 04:41:33.598318 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8917 04:41:33.602014 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8918 04:41:33.605030 == TX Byte 1 ==
8919 04:41:33.608077 u2DelayCellOfst[8]=0 cells (0 PI)
8920 04:41:33.611912 u2DelayCellOfst[9]=3 cells (1 PI)
8921 04:41:33.615005 u2DelayCellOfst[10]=10 cells (3 PI)
8922 04:41:33.615087 u2DelayCellOfst[11]=3 cells (1 PI)
8923 04:41:33.617810 u2DelayCellOfst[12]=10 cells (3 PI)
8924 04:41:33.621337 u2DelayCellOfst[13]=14 cells (4 PI)
8925 04:41:33.624697 u2DelayCellOfst[14]=17 cells (5 PI)
8926 04:41:33.627799 u2DelayCellOfst[15]=14 cells (4 PI)
8927 04:41:33.634474 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8928 04:41:33.637592 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8929 04:41:33.637675 DramC Write-DBI on
8930 04:41:33.641195 ==
8931 04:41:33.641278 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 04:41:33.647640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 04:41:33.647724 ==
8934 04:41:33.647789
8935 04:41:33.647849
8936 04:41:33.650956 TX Vref Scan disable
8937 04:41:33.651038 == TX Byte 0 ==
8938 04:41:33.657779 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8939 04:41:33.657864 == TX Byte 1 ==
8940 04:41:33.661037 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8941 04:41:33.664158 DramC Write-DBI off
8942 04:41:33.664240
8943 04:41:33.664304 [DATLAT]
8944 04:41:33.667618 Freq=1600, CH1 RK1
8945 04:41:33.667700
8946 04:41:33.667765 DATLAT Default: 0xf
8947 04:41:33.671050 0, 0xFFFF, sum = 0
8948 04:41:33.671133 1, 0xFFFF, sum = 0
8949 04:41:33.674463 2, 0xFFFF, sum = 0
8950 04:41:33.674546 3, 0xFFFF, sum = 0
8951 04:41:33.677178 4, 0xFFFF, sum = 0
8952 04:41:33.677262 5, 0xFFFF, sum = 0
8953 04:41:33.680716 6, 0xFFFF, sum = 0
8954 04:41:33.680800 7, 0xFFFF, sum = 0
8955 04:41:33.684024 8, 0xFFFF, sum = 0
8956 04:41:33.687332 9, 0xFFFF, sum = 0
8957 04:41:33.687459 10, 0xFFFF, sum = 0
8958 04:41:33.690536 11, 0xFFFF, sum = 0
8959 04:41:33.690618 12, 0xFFFF, sum = 0
8960 04:41:33.693781 13, 0xFFFF, sum = 0
8961 04:41:33.693864 14, 0x0, sum = 1
8962 04:41:33.696990 15, 0x0, sum = 2
8963 04:41:33.697072 16, 0x0, sum = 3
8964 04:41:33.700467 17, 0x0, sum = 4
8965 04:41:33.700550 best_step = 15
8966 04:41:33.700615
8967 04:41:33.700675 ==
8968 04:41:33.703913 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 04:41:33.707299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 04:41:33.710441 ==
8971 04:41:33.710523 RX Vref Scan: 0
8972 04:41:33.710587
8973 04:41:33.714126 RX Vref 0 -> 0, step: 1
8974 04:41:33.714208
8975 04:41:33.716782 RX Delay 19 -> 252, step: 4
8976 04:41:33.720288 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8977 04:41:33.723268 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8978 04:41:33.726755 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8979 04:41:33.733598 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8980 04:41:33.736614 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8981 04:41:33.739932 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8982 04:41:33.743292 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8983 04:41:33.746688 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8984 04:41:33.752967 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8985 04:41:33.756645 iDelay=195, Bit 9, Center 116 (63 ~ 170) 108
8986 04:41:33.759617 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8987 04:41:33.762916 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8988 04:41:33.769210 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8989 04:41:33.772969 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8990 04:41:33.776305 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8991 04:41:33.779169 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8992 04:41:33.779251 ==
8993 04:41:33.782633 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 04:41:33.789013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 04:41:33.789095 ==
8996 04:41:33.789160 DQS Delay:
8997 04:41:33.789221 DQS0 = 0, DQS1 = 0
8998 04:41:33.792473 DQM Delay:
8999 04:41:33.792555 DQM0 = 132, DQM1 = 127
9000 04:41:33.795695 DQ Delay:
9001 04:41:33.798912 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
9002 04:41:33.802058 DQ4 =132, DQ5 =144, DQ6 =138, DQ7 =128
9003 04:41:33.805720 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
9004 04:41:33.808920 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9005 04:41:33.809002
9006 04:41:33.809066
9007 04:41:33.809126
9008 04:41:33.811930 [DramC_TX_OE_Calibration] TA2
9009 04:41:33.815635 Original DQ_B0 (3 6) =30, OEN = 27
9010 04:41:33.819130 Original DQ_B1 (3 6) =30, OEN = 27
9011 04:41:33.822205 24, 0x0, End_B0=24 End_B1=24
9012 04:41:33.822288 25, 0x0, End_B0=25 End_B1=25
9013 04:41:33.825523 26, 0x0, End_B0=26 End_B1=26
9014 04:41:33.828390 27, 0x0, End_B0=27 End_B1=27
9015 04:41:33.831965 28, 0x0, End_B0=28 End_B1=28
9016 04:41:33.834975 29, 0x0, End_B0=29 End_B1=29
9017 04:41:33.835058 30, 0x0, End_B0=30 End_B1=30
9018 04:41:33.838694 31, 0x4545, End_B0=30 End_B1=30
9019 04:41:33.841729 Byte0 end_step=30 best_step=27
9020 04:41:33.845408 Byte1 end_step=30 best_step=27
9021 04:41:33.848389 Byte0 TX OE(2T, 0.5T) = (3, 3)
9022 04:41:33.851371 Byte1 TX OE(2T, 0.5T) = (3, 3)
9023 04:41:33.851467
9024 04:41:33.851531
9025 04:41:33.858097 [DQSOSCAuto] RK1, (LSB)MR18= 0x1120, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 401 ps
9026 04:41:33.861603 CH1 RK1: MR19=303, MR18=1120
9027 04:41:33.867961 CH1_RK1: MR19=0x303, MR18=0x1120, DQSOSC=393, MR23=63, INC=23, DEC=15
9028 04:41:33.871372 [RxdqsGatingPostProcess] freq 1600
9029 04:41:33.877657 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9030 04:41:33.877763 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 04:41:33.881113 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 04:41:33.884572 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 04:41:33.887684 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 04:41:33.890860 best DQS0 dly(2T, 0.5T) = (1, 1)
9035 04:41:33.894436 best DQS1 dly(2T, 0.5T) = (1, 1)
9036 04:41:33.897859 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9037 04:41:33.900720 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9038 04:41:33.904242 Pre-setting of DQS Precalculation
9039 04:41:33.907708 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9040 04:41:33.917107 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9041 04:41:33.923867 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9042 04:41:33.923969
9043 04:41:33.924068
9044 04:41:33.927341 [Calibration Summary] 3200 Mbps
9045 04:41:33.927481 CH 0, Rank 0
9046 04:41:33.930825 SW Impedance : PASS
9047 04:41:33.930905 DUTY Scan : NO K
9048 04:41:33.933637 ZQ Calibration : PASS
9049 04:41:33.937234 Jitter Meter : NO K
9050 04:41:33.937340 CBT Training : PASS
9051 04:41:33.940636 Write leveling : PASS
9052 04:41:33.943844 RX DQS gating : PASS
9053 04:41:33.943924 RX DQ/DQS(RDDQC) : PASS
9054 04:41:33.947036 TX DQ/DQS : PASS
9055 04:41:33.950424 RX DATLAT : PASS
9056 04:41:33.950522 RX DQ/DQS(Engine): PASS
9057 04:41:33.953671 TX OE : PASS
9058 04:41:33.953776 All Pass.
9059 04:41:33.953864
9060 04:41:33.956904 CH 0, Rank 1
9061 04:41:33.956985 SW Impedance : PASS
9062 04:41:33.960335 DUTY Scan : NO K
9063 04:41:33.963318 ZQ Calibration : PASS
9064 04:41:33.963461 Jitter Meter : NO K
9065 04:41:33.966848 CBT Training : PASS
9066 04:41:33.970203 Write leveling : PASS
9067 04:41:33.970301 RX DQS gating : PASS
9068 04:41:33.973372 RX DQ/DQS(RDDQC) : PASS
9069 04:41:33.976940 TX DQ/DQS : PASS
9070 04:41:33.977017 RX DATLAT : PASS
9071 04:41:33.980023 RX DQ/DQS(Engine): PASS
9072 04:41:33.983596 TX OE : PASS
9073 04:41:33.983678 All Pass.
9074 04:41:33.983741
9075 04:41:33.983799 CH 1, Rank 0
9076 04:41:33.987123 SW Impedance : PASS
9077 04:41:33.989968 DUTY Scan : NO K
9078 04:41:33.990071 ZQ Calibration : PASS
9079 04:41:33.993400 Jitter Meter : NO K
9080 04:41:33.993502 CBT Training : PASS
9081 04:41:33.996272 Write leveling : PASS
9082 04:41:33.999627 RX DQS gating : PASS
9083 04:41:33.999704 RX DQ/DQS(RDDQC) : PASS
9084 04:41:34.003193 TX DQ/DQS : PASS
9085 04:41:34.006164 RX DATLAT : PASS
9086 04:41:34.006266 RX DQ/DQS(Engine): PASS
9087 04:41:34.009651 TX OE : PASS
9088 04:41:34.009748 All Pass.
9089 04:41:34.009835
9090 04:41:34.012995 CH 1, Rank 1
9091 04:41:34.013088 SW Impedance : PASS
9092 04:41:34.016284 DUTY Scan : NO K
9093 04:41:34.019278 ZQ Calibration : PASS
9094 04:41:34.019398 Jitter Meter : NO K
9095 04:41:34.022685 CBT Training : PASS
9096 04:41:34.026335 Write leveling : PASS
9097 04:41:34.026435 RX DQS gating : PASS
9098 04:41:34.029464 RX DQ/DQS(RDDQC) : PASS
9099 04:41:34.032655 TX DQ/DQS : PASS
9100 04:41:34.032726 RX DATLAT : PASS
9101 04:41:34.035940 RX DQ/DQS(Engine): PASS
9102 04:41:34.039351 TX OE : PASS
9103 04:41:34.039455 All Pass.
9104 04:41:34.039520
9105 04:41:34.042498 DramC Write-DBI on
9106 04:41:34.042565 PER_BANK_REFRESH: Hybrid Mode
9107 04:41:34.045830 TX_TRACKING: ON
9108 04:41:34.055658 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9109 04:41:34.062193 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9110 04:41:34.068628 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9111 04:41:34.071927 [FAST_K] Save calibration result to emmc
9112 04:41:34.075064 sync common calibartion params.
9113 04:41:34.078640 sync cbt_mode0:1, 1:1
9114 04:41:34.078722 dram_init: ddr_geometry: 2
9115 04:41:34.082065 dram_init: ddr_geometry: 2
9116 04:41:34.085413 dram_init: ddr_geometry: 2
9117 04:41:34.088772 0:dram_rank_size:100000000
9118 04:41:34.088879 1:dram_rank_size:100000000
9119 04:41:34.095200 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9120 04:41:34.098274 DFS_SHUFFLE_HW_MODE: ON
9121 04:41:34.101712 dramc_set_vcore_voltage set vcore to 725000
9122 04:41:34.104851 Read voltage for 1600, 0
9123 04:41:34.104953 Vio18 = 0
9124 04:41:34.105053 Vcore = 725000
9125 04:41:34.108135 Vdram = 0
9126 04:41:34.108221 Vddq = 0
9127 04:41:34.108283 Vmddr = 0
9128 04:41:34.111416 switch to 3200 Mbps bootup
9129 04:41:34.111512 [DramcRunTimeConfig]
9130 04:41:34.114540 PHYPLL
9131 04:41:34.114622 DPM_CONTROL_AFTERK: ON
9132 04:41:34.118107 PER_BANK_REFRESH: ON
9133 04:41:34.121438 REFRESH_OVERHEAD_REDUCTION: ON
9134 04:41:34.121533 CMD_PICG_NEW_MODE: OFF
9135 04:41:34.124998 XRTWTW_NEW_MODE: ON
9136 04:41:34.125092 XRTRTR_NEW_MODE: ON
9137 04:41:34.127802 TX_TRACKING: ON
9138 04:41:34.127898 RDSEL_TRACKING: OFF
9139 04:41:34.131697 DQS Precalculation for DVFS: ON
9140 04:41:34.134526 RX_TRACKING: OFF
9141 04:41:34.134620 HW_GATING DBG: ON
9142 04:41:34.137586 ZQCS_ENABLE_LP4: ON
9143 04:41:34.137653 RX_PICG_NEW_MODE: ON
9144 04:41:34.140980 TX_PICG_NEW_MODE: ON
9145 04:41:34.144095 ENABLE_RX_DCM_DPHY: ON
9146 04:41:34.147660 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9147 04:41:34.147761 DUMMY_READ_FOR_TRACKING: OFF
9148 04:41:34.151070 !!! SPM_CONTROL_AFTERK: OFF
9149 04:41:34.154530 !!! SPM could not control APHY
9150 04:41:34.157432 IMPEDANCE_TRACKING: ON
9151 04:41:34.157533 TEMP_SENSOR: ON
9152 04:41:34.160823 HW_SAVE_FOR_SR: OFF
9153 04:41:34.160906 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9154 04:41:34.167750 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9155 04:41:34.167832 Read ODT Tracking: ON
9156 04:41:34.171028 Refresh Rate DeBounce: ON
9157 04:41:34.173957 DFS_NO_QUEUE_FLUSH: ON
9158 04:41:34.177237 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9159 04:41:34.177319 ENABLE_DFS_RUNTIME_MRW: OFF
9160 04:41:34.180782 DDR_RESERVE_NEW_MODE: ON
9161 04:41:34.183952 MR_CBT_SWITCH_FREQ: ON
9162 04:41:34.184032 =========================
9163 04:41:34.203617 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9164 04:41:34.206971 dram_init: ddr_geometry: 2
9165 04:41:34.225386 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9166 04:41:34.228700 dram_init: dram init end (result: 0)
9167 04:41:34.234923 DRAM-K: Full calibration passed in 24412 msecs
9168 04:41:34.238589 MRC: failed to locate region type 0.
9169 04:41:34.238670 DRAM rank0 size:0x100000000,
9170 04:41:34.241895 DRAM rank1 size=0x100000000
9171 04:41:34.251480 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9172 04:41:34.257968 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9173 04:41:34.265004 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9174 04:41:34.274682 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9175 04:41:34.274763 DRAM rank0 size:0x100000000,
9176 04:41:34.277569 DRAM rank1 size=0x100000000
9177 04:41:34.277650 CBMEM:
9178 04:41:34.281053 IMD: root @ 0xfffff000 254 entries.
9179 04:41:34.284527 IMD: root @ 0xffffec00 62 entries.
9180 04:41:34.287908 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9181 04:41:34.294297 WARNING: RO_VPD is uninitialized or empty.
9182 04:41:34.297480 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9183 04:41:34.305524 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9184 04:41:34.318216 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9185 04:41:34.329482 BS: romstage times (exec / console): total (unknown) / 23944 ms
9186 04:41:34.329564
9187 04:41:34.329628
9188 04:41:34.339289 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9189 04:41:34.342839 ARM64: Exception handlers installed.
9190 04:41:34.346294 ARM64: Testing exception
9191 04:41:34.349110 ARM64: Done test exception
9192 04:41:34.349191 Enumerating buses...
9193 04:41:34.352630 Show all devs... Before device enumeration.
9194 04:41:34.355445 Root Device: enabled 1
9195 04:41:34.358842 CPU_CLUSTER: 0: enabled 1
9196 04:41:34.358923 CPU: 00: enabled 1
9197 04:41:34.362482 Compare with tree...
9198 04:41:34.362562 Root Device: enabled 1
9199 04:41:34.365343 CPU_CLUSTER: 0: enabled 1
9200 04:41:34.368748 CPU: 00: enabled 1
9201 04:41:34.368828 Root Device scanning...
9202 04:41:34.372446 scan_static_bus for Root Device
9203 04:41:34.375490 CPU_CLUSTER: 0 enabled
9204 04:41:34.378781 scan_static_bus for Root Device done
9205 04:41:34.381942 scan_bus: bus Root Device finished in 8 msecs
9206 04:41:34.382023 done
9207 04:41:34.388835 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9208 04:41:34.392094 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9209 04:41:34.398324 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9210 04:41:34.405264 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9211 04:41:34.405345 Allocating resources...
9212 04:41:34.408308 Reading resources...
9213 04:41:34.411957 Root Device read_resources bus 0 link: 0
9214 04:41:34.415042 DRAM rank0 size:0x100000000,
9215 04:41:34.415123 DRAM rank1 size=0x100000000
9216 04:41:34.421703 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9217 04:41:34.421785 CPU: 00 missing read_resources
9218 04:41:34.428087 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9219 04:41:34.431919 Root Device read_resources bus 0 link: 0 done
9220 04:41:34.434791 Done reading resources.
9221 04:41:34.438214 Show resources in subtree (Root Device)...After reading.
9222 04:41:34.441048 Root Device child on link 0 CPU_CLUSTER: 0
9223 04:41:34.444318 CPU_CLUSTER: 0 child on link 0 CPU: 00
9224 04:41:34.454414 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9225 04:41:34.454511 CPU: 00
9226 04:41:34.460773 Root Device assign_resources, bus 0 link: 0
9227 04:41:34.464314 CPU_CLUSTER: 0 missing set_resources
9228 04:41:34.467577 Root Device assign_resources, bus 0 link: 0 done
9229 04:41:34.470752 Done setting resources.
9230 04:41:34.474453 Show resources in subtree (Root Device)...After assigning values.
9231 04:41:34.477619 Root Device child on link 0 CPU_CLUSTER: 0
9232 04:41:34.483922 CPU_CLUSTER: 0 child on link 0 CPU: 00
9233 04:41:34.490417 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9234 04:41:34.494066 CPU: 00
9235 04:41:34.494146 Done allocating resources.
9236 04:41:34.501179 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9237 04:41:34.501287 Enabling resources...
9238 04:41:34.503696 done.
9239 04:41:34.507459 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9240 04:41:34.510360 Initializing devices...
9241 04:41:34.510441 Root Device init
9242 04:41:34.513488 init hardware done!
9243 04:41:34.513569 0x00000018: ctrlr->caps
9244 04:41:34.516851 52.000 MHz: ctrlr->f_max
9245 04:41:34.520669 0.400 MHz: ctrlr->f_min
9246 04:41:34.523582 0x40ff8080: ctrlr->voltages
9247 04:41:34.523665 sclk: 390625
9248 04:41:34.523730 Bus Width = 1
9249 04:41:34.527052 sclk: 390625
9250 04:41:34.527132 Bus Width = 1
9251 04:41:34.530576 Early init status = 3
9252 04:41:34.533624 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9253 04:41:34.536889 in-header: 03 fc 00 00 01 00 00 00
9254 04:41:34.540289 in-data: 00
9255 04:41:34.543490 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9256 04:41:34.547991 in-header: 03 fd 00 00 00 00 00 00
9257 04:41:34.551338 in-data:
9258 04:41:34.554595 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9259 04:41:34.558147 in-header: 03 fc 00 00 01 00 00 00
9260 04:41:34.561404 in-data: 00
9261 04:41:34.564915 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9262 04:41:34.569241 in-header: 03 fd 00 00 00 00 00 00
9263 04:41:34.572945 in-data:
9264 04:41:34.576009 [SSUSB] Setting up USB HOST controller...
9265 04:41:34.579291 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9266 04:41:34.582885 [SSUSB] phy power-on done.
9267 04:41:34.585737 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9268 04:41:34.592706 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9269 04:41:34.595585 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9270 04:41:34.602328 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9271 04:41:34.609222 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9272 04:41:34.615718 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9273 04:41:34.622429 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9274 04:41:34.628763 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9275 04:41:34.631938 SPM: binary array size = 0x9dc
9276 04:41:34.635721 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9277 04:41:34.641835 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9278 04:41:34.648705 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9279 04:41:34.655578 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9280 04:41:34.658520 configure_display: Starting display init
9281 04:41:34.692703 anx7625_power_on_init: Init interface.
9282 04:41:34.695800 anx7625_disable_pd_protocol: Disabled PD feature.
9283 04:41:34.699013 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9284 04:41:34.726997 anx7625_start_dp_work: Secure OCM version=00
9285 04:41:34.730340 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9286 04:41:34.744935 sp_tx_get_edid_block: EDID Block = 1
9287 04:41:34.847711 Extracted contents:
9288 04:41:34.850978 header: 00 ff ff ff ff ff ff 00
9289 04:41:34.854063 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9290 04:41:34.857562 version: 01 04
9291 04:41:34.860545 basic params: 95 1f 11 78 0a
9292 04:41:34.864144 chroma info: 76 90 94 55 54 90 27 21 50 54
9293 04:41:34.867490 established: 00 00 00
9294 04:41:34.873639 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9295 04:41:34.880600 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9296 04:41:34.883903 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9297 04:41:34.890067 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9298 04:41:34.897133 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9299 04:41:34.900109 extensions: 00
9300 04:41:34.900191 checksum: fb
9301 04:41:34.900256
9302 04:41:34.907002 Manufacturer: IVO Model 57d Serial Number 0
9303 04:41:34.907084 Made week 0 of 2020
9304 04:41:34.910559 EDID version: 1.4
9305 04:41:34.910643 Digital display
9306 04:41:34.913554 6 bits per primary color channel
9307 04:41:34.913653 DisplayPort interface
9308 04:41:34.916973 Maximum image size: 31 cm x 17 cm
9309 04:41:34.919682 Gamma: 220%
9310 04:41:34.919763 Check DPMS levels
9311 04:41:34.926760 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9312 04:41:34.929663 First detailed timing is preferred timing
9313 04:41:34.933105 Established timings supported:
9314 04:41:34.933187 Standard timings supported:
9315 04:41:34.936706 Detailed timings
9316 04:41:34.940002 Hex of detail: 383680a07038204018303c0035ae10000019
9317 04:41:34.946217 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9318 04:41:34.949350 0780 0798 07c8 0820 hborder 0
9319 04:41:34.952873 0438 043b 0447 0458 vborder 0
9320 04:41:34.956428 -hsync -vsync
9321 04:41:34.956509 Did detailed timing
9322 04:41:34.962689 Hex of detail: 000000000000000000000000000000000000
9323 04:41:34.966063 Manufacturer-specified data, tag 0
9324 04:41:34.969067 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9325 04:41:34.973018 ASCII string: InfoVision
9326 04:41:34.975968 Hex of detail: 000000fe00523134304e574635205248200a
9327 04:41:34.979219 ASCII string: R140NWF5 RH
9328 04:41:34.979300 Checksum
9329 04:41:34.982522 Checksum: 0xfb (valid)
9330 04:41:34.985569 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9331 04:41:34.988955 DSI data_rate: 832800000 bps
9332 04:41:34.995830 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9333 04:41:34.998679 anx7625_parse_edid: pixelclock(138800).
9334 04:41:35.001981 hactive(1920), hsync(48), hfp(24), hbp(88)
9335 04:41:35.005472 vactive(1080), vsync(12), vfp(3), vbp(17)
9336 04:41:35.008777 anx7625_dsi_config: config dsi.
9337 04:41:35.015440 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9338 04:41:35.030051 anx7625_dsi_config: success to config DSI
9339 04:41:35.033395 anx7625_dp_start: MIPI phy setup OK.
9340 04:41:35.036246 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9341 04:41:35.039572 mtk_ddp_mode_set invalid vrefresh 60
9342 04:41:35.042932 main_disp_path_setup
9343 04:41:35.043041 ovl_layer_smi_id_en
9344 04:41:35.046359 ovl_layer_smi_id_en
9345 04:41:35.046464 ccorr_config
9346 04:41:35.046553 aal_config
9347 04:41:35.049761 gamma_config
9348 04:41:35.049860 postmask_config
9349 04:41:35.052759 dither_config
9350 04:41:35.055893 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9351 04:41:35.062555 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9352 04:41:35.065964 Root Device init finished in 551 msecs
9353 04:41:35.069583 CPU_CLUSTER: 0 init
9354 04:41:35.075934 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9355 04:41:35.082411 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9356 04:41:35.082489 APU_MBOX 0x190000b0 = 0x10001
9357 04:41:35.086041 APU_MBOX 0x190001b0 = 0x10001
9358 04:41:35.089016 APU_MBOX 0x190005b0 = 0x10001
9359 04:41:35.092257 APU_MBOX 0x190006b0 = 0x10001
9360 04:41:35.098548 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9361 04:41:35.108795 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9362 04:41:35.120943 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9363 04:41:35.127667 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9364 04:41:35.139547 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9365 04:41:35.148685 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9366 04:41:35.152293 CPU_CLUSTER: 0 init finished in 81 msecs
9367 04:41:35.154938 Devices initialized
9368 04:41:35.158714 Show all devs... After init.
9369 04:41:35.158812 Root Device: enabled 1
9370 04:41:35.161684 CPU_CLUSTER: 0: enabled 1
9371 04:41:35.164954 CPU: 00: enabled 1
9372 04:41:35.168064 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9373 04:41:35.171817 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9374 04:41:35.174998 ELOG: NV offset 0x57f000 size 0x1000
9375 04:41:35.181229 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9376 04:41:35.188177 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9377 04:41:35.191771 ELOG: Event(17) added with size 13 at 2024-02-04 04:41:37 UTC
9378 04:41:35.195262 out: cmd=0x121: 03 db 21 01 00 00 00 00
9379 04:41:35.198671 in-header: 03 3e 00 00 2c 00 00 00
9380 04:41:35.211934 in-data: 21 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9381 04:41:35.218384 ELOG: Event(A1) added with size 10 at 2024-02-04 04:41:37 UTC
9382 04:41:35.225006 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9383 04:41:35.231653 ELOG: Event(A0) added with size 9 at 2024-02-04 04:41:37 UTC
9384 04:41:35.235420 elog_add_boot_reason: Logged dev mode boot
9385 04:41:35.238212 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9386 04:41:35.241743 Finalize devices...
9387 04:41:35.241840 Devices finalized
9388 04:41:35.248587 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9389 04:41:35.251347 Writing coreboot table at 0xffe64000
9390 04:41:35.254670 0. 000000000010a000-0000000000113fff: RAMSTAGE
9391 04:41:35.257964 1. 0000000040000000-00000000400fffff: RAM
9392 04:41:35.264804 2. 0000000040100000-000000004032afff: RAMSTAGE
9393 04:41:35.267955 3. 000000004032b000-00000000545fffff: RAM
9394 04:41:35.270762 4. 0000000054600000-000000005465ffff: BL31
9395 04:41:35.274266 5. 0000000054660000-00000000ffe63fff: RAM
9396 04:41:35.280762 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9397 04:41:35.284259 7. 0000000100000000-000000023fffffff: RAM
9398 04:41:35.287237 Passing 5 GPIOs to payload:
9399 04:41:35.290587 NAME | PORT | POLARITY | VALUE
9400 04:41:35.297262 EC in RW | 0x000000aa | low | undefined
9401 04:41:35.300954 EC interrupt | 0x00000005 | low | undefined
9402 04:41:35.303720 TPM interrupt | 0x000000ab | high | undefined
9403 04:41:35.310282 SD card detect | 0x00000011 | high | undefined
9404 04:41:35.313868 speaker enable | 0x00000093 | high | undefined
9405 04:41:35.317626 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9406 04:41:35.320509 in-header: 03 f9 00 00 02 00 00 00
9407 04:41:35.323512 in-data: 02 00
9408 04:41:35.326726 ADC[4]: Raw value=902586 ID=7
9409 04:41:35.326799 ADC[3]: Raw value=213916 ID=1
9410 04:41:35.330222 RAM Code: 0x71
9411 04:41:35.333395 ADC[6]: Raw value=74630 ID=0
9412 04:41:35.333467 ADC[5]: Raw value=213916 ID=1
9413 04:41:35.337187 SKU Code: 0x1
9414 04:41:35.343440 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 521
9415 04:41:35.343522 coreboot table: 964 bytes.
9416 04:41:35.347340 IMD ROOT 0. 0xfffff000 0x00001000
9417 04:41:35.350372 IMD SMALL 1. 0xffffe000 0x00001000
9418 04:41:35.353248 RO MCACHE 2. 0xffffc000 0x00001104
9419 04:41:35.356488 CONSOLE 3. 0xfff7c000 0x00080000
9420 04:41:35.359717 FMAP 4. 0xfff7b000 0x00000452
9421 04:41:35.363694 TIME STAMP 5. 0xfff7a000 0x00000910
9422 04:41:35.366827 VBOOT WORK 6. 0xfff66000 0x00014000
9423 04:41:35.369611 RAMOOPS 7. 0xffe66000 0x00100000
9424 04:41:35.372900 COREBOOT 8. 0xffe64000 0x00002000
9425 04:41:35.376421 IMD small region:
9426 04:41:35.379600 IMD ROOT 0. 0xffffec00 0x00000400
9427 04:41:35.383046 VPD 1. 0xffffeb80 0x0000006c
9428 04:41:35.386342 MMC STATUS 2. 0xffffeb60 0x00000004
9429 04:41:35.389369 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9430 04:41:35.393158 Probing TPM: done!
9431 04:41:35.396687 Connected to device vid:did:rid of 1ae0:0028:00
9432 04:41:35.407180 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9433 04:41:35.410587 Initialized TPM device CR50 revision 0
9434 04:41:35.414412 Checking cr50 for pending updates
9435 04:41:35.418144 Reading cr50 TPM mode
9436 04:41:35.426585 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9437 04:41:35.433293 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9438 04:41:35.473584 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9439 04:41:35.476623 Checking segment from ROM address 0x40100000
9440 04:41:35.480017 Checking segment from ROM address 0x4010001c
9441 04:41:35.486585 Loading segment from ROM address 0x40100000
9442 04:41:35.486666 code (compression=0)
9443 04:41:35.496760 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9444 04:41:35.503443 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9445 04:41:35.503534 it's not compressed!
9446 04:41:35.509603 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9447 04:41:35.516132 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9448 04:41:35.533846 Loading segment from ROM address 0x4010001c
9449 04:41:35.533950 Entry Point 0x80000000
9450 04:41:35.537160 Loaded segments
9451 04:41:35.540093 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9452 04:41:35.546909 Jumping to boot code at 0x80000000(0xffe64000)
9453 04:41:35.553620 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9454 04:41:35.559991 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9455 04:41:35.568419 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9456 04:41:35.572396 Checking segment from ROM address 0x40100000
9457 04:41:35.574825 Checking segment from ROM address 0x4010001c
9458 04:41:35.581781 Loading segment from ROM address 0x40100000
9459 04:41:35.581882 code (compression=1)
9460 04:41:35.588271 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9461 04:41:35.598165 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9462 04:41:35.598266 using LZMA
9463 04:41:35.606560 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9464 04:41:35.612912 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9465 04:41:35.616558 Loading segment from ROM address 0x4010001c
9466 04:41:35.616639 Entry Point 0x54601000
9467 04:41:35.620094 Loaded segments
9468 04:41:35.622902 NOTICE: MT8192 bl31_setup
9469 04:41:35.630086 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9470 04:41:35.633420 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9471 04:41:35.636566 WARNING: region 0:
9472 04:41:35.640070 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 04:41:35.640169 WARNING: region 1:
9474 04:41:35.646542 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9475 04:41:35.650149 WARNING: region 2:
9476 04:41:35.653036 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9477 04:41:35.656560 WARNING: region 3:
9478 04:41:35.660241 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9479 04:41:35.663607 WARNING: region 4:
9480 04:41:35.669962 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9481 04:41:35.670036 WARNING: region 5:
9482 04:41:35.673130 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 04:41:35.676377 WARNING: region 6:
9484 04:41:35.679913 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 04:41:35.683352 WARNING: region 7:
9486 04:41:35.686344 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 04:41:35.693331 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9488 04:41:35.696278 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9489 04:41:35.699654 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9490 04:41:35.706804 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9491 04:41:35.709582 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9492 04:41:35.713496 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9493 04:41:35.719895 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9494 04:41:35.723302 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9495 04:41:35.729854 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9496 04:41:35.733237 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9497 04:41:35.736293 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9498 04:41:35.743111 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9499 04:41:35.746293 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9500 04:41:35.752735 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9501 04:41:35.756282 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9502 04:41:35.759395 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9503 04:41:35.766253 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9504 04:41:35.769787 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9505 04:41:35.773129 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9506 04:41:35.779401 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9507 04:41:35.782857 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9508 04:41:35.789550 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9509 04:41:35.792919 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9510 04:41:35.796084 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9511 04:41:35.802562 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9512 04:41:35.806154 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9513 04:41:35.812731 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9514 04:41:35.816038 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9515 04:41:35.819611 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9516 04:41:35.826081 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9517 04:41:35.828994 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9518 04:41:35.835876 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9519 04:41:35.838862 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9520 04:41:35.842458 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9521 04:41:35.845731 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9522 04:41:35.852217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9523 04:41:35.855996 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9524 04:41:35.859197 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9525 04:41:35.862655 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9526 04:41:35.868665 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9527 04:41:35.872218 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9528 04:41:35.875597 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9529 04:41:35.878870 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9530 04:41:35.885520 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9531 04:41:35.888500 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9532 04:41:35.891972 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9533 04:41:35.895823 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9534 04:41:35.904746 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9535 04:41:35.905648 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9536 04:41:35.912462 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9537 04:41:35.915672 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9538 04:41:35.918935 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9539 04:41:35.925147 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9540 04:41:35.928910 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9541 04:41:35.935411 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9542 04:41:35.938369 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9543 04:41:35.945064 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9544 04:41:35.948493 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9545 04:41:35.952010 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9546 04:41:35.958381 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9547 04:41:35.961824 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9548 04:41:35.968386 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9549 04:41:35.972360 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9550 04:41:35.978494 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9551 04:41:35.981481 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9552 04:41:35.988138 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9553 04:41:35.991490 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9554 04:41:35.994790 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9555 04:41:36.001645 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9556 04:41:36.004796 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9557 04:41:36.011981 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9558 04:41:36.014863 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9559 04:41:36.021413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9560 04:41:36.024936 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9561 04:41:36.028076 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9562 04:41:36.034915 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9563 04:41:36.038580 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9564 04:41:36.044766 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9565 04:41:36.048276 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9566 04:41:36.054810 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9567 04:41:36.058330 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9568 04:41:36.064937 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9569 04:41:36.068008 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9570 04:41:36.071799 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9571 04:41:36.078334 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9572 04:41:36.081464 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9573 04:41:36.088019 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9574 04:41:36.091398 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9575 04:41:36.094763 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9576 04:41:36.101337 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9577 04:41:36.104840 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9578 04:41:36.111326 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9579 04:41:36.114799 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9580 04:41:36.121689 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9581 04:41:36.124961 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9582 04:41:36.131271 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9583 04:41:36.134687 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9584 04:41:36.138191 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9585 04:41:36.141616 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9586 04:41:36.148230 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9587 04:41:36.151517 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9588 04:41:36.154720 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9589 04:41:36.161499 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9590 04:41:36.164420 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9591 04:41:36.171368 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9592 04:41:36.174851 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9593 04:41:36.178476 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9594 04:41:36.184627 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9595 04:41:36.188055 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9596 04:41:36.194394 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9597 04:41:36.197518 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9598 04:41:36.201051 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9599 04:41:36.208147 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9600 04:41:36.211051 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9601 04:41:36.217591 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9602 04:41:36.220965 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9603 04:41:36.224238 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9604 04:41:36.227839 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9605 04:41:36.234439 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9606 04:41:36.237728 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9607 04:41:36.241060 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9608 04:41:36.244575 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9609 04:41:36.250918 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9610 04:41:36.254721 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9611 04:41:36.257802 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9612 04:41:36.264323 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9613 04:41:36.267874 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9614 04:41:36.274544 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9615 04:41:36.277714 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9616 04:41:36.280805 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9617 04:41:36.287772 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9618 04:41:36.290850 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9619 04:41:36.297610 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9620 04:41:36.301016 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9621 04:41:36.303984 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9622 04:41:36.310979 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9623 04:41:36.314365 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9624 04:41:36.318017 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9625 04:41:36.324252 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9626 04:41:36.327346 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9627 04:41:36.334134 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9628 04:41:36.337205 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9629 04:41:36.340892 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9630 04:41:36.347735 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9631 04:41:36.350779 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9632 04:41:36.357125 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9633 04:41:36.361185 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9634 04:41:36.364207 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9635 04:41:36.370467 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9636 04:41:36.373969 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9637 04:41:36.380974 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9638 04:41:36.384091 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9639 04:41:36.387334 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9640 04:41:36.394030 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9641 04:41:36.397076 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9642 04:41:36.400863 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9643 04:41:36.407183 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9644 04:41:36.410440 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9645 04:41:36.417113 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9646 04:41:36.420484 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9647 04:41:36.423651 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9648 04:41:36.430259 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9649 04:41:36.433727 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9650 04:41:36.440014 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9651 04:41:36.443320 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9652 04:41:36.446925 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9653 04:41:36.453623 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9654 04:41:36.456849 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9655 04:41:36.463003 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9656 04:41:36.466617 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9657 04:41:36.470052 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9658 04:41:36.476321 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9659 04:41:36.479866 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9660 04:41:36.486295 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9661 04:41:36.489829 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9662 04:41:36.492689 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9663 04:41:36.499618 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9664 04:41:36.502816 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9665 04:41:36.509447 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9666 04:41:36.512996 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9667 04:41:36.516153 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9668 04:41:36.523055 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9669 04:41:36.525752 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9670 04:41:36.532739 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9671 04:41:36.535672 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9672 04:41:36.539772 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9673 04:41:36.546248 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9674 04:41:36.549426 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9675 04:41:36.555273 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9676 04:41:36.558938 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9677 04:41:36.565641 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9678 04:41:36.569274 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9679 04:41:36.572084 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9680 04:41:36.578827 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9681 04:41:36.581833 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9682 04:41:36.589173 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9683 04:41:36.591939 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9684 04:41:36.598576 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9685 04:41:36.601995 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9686 04:41:36.604893 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9687 04:41:36.612017 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9688 04:41:36.614695 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9689 04:41:36.621850 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9690 04:41:36.624701 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9691 04:41:36.631644 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9692 04:41:36.635266 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9693 04:41:36.638150 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9694 04:41:36.644911 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9695 04:41:36.648047 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9696 04:41:36.654470 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9697 04:41:36.658128 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9698 04:41:36.664301 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9699 04:41:36.667773 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9700 04:41:36.671009 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9701 04:41:36.677393 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9702 04:41:36.680704 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9703 04:41:36.687599 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9704 04:41:36.691298 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9705 04:41:36.693995 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9706 04:41:36.700501 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9707 04:41:36.704042 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9708 04:41:36.710858 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9709 04:41:36.714447 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9710 04:41:36.720738 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9711 04:41:36.723632 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9712 04:41:36.727144 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9713 04:41:36.733623 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9714 04:41:36.736966 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9715 04:41:36.743650 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9716 04:41:36.746768 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9717 04:41:36.750629 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9718 04:41:36.753834 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9719 04:41:36.759996 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9720 04:41:36.763729 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9721 04:41:36.766576 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9722 04:41:36.773791 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9723 04:41:36.777033 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9724 04:41:36.780129 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9725 04:41:36.786640 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9726 04:41:36.789869 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9727 04:41:36.792984 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9728 04:41:36.799839 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9729 04:41:36.802889 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9730 04:41:36.809782 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9731 04:41:36.812723 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9732 04:41:36.816285 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9733 04:41:36.822924 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9734 04:41:36.826214 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9735 04:41:36.829384 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9736 04:41:36.835776 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9737 04:41:36.839279 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9738 04:41:36.846370 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9739 04:41:36.849069 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9740 04:41:36.852532 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9741 04:41:36.859514 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9742 04:41:36.862739 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9743 04:41:36.868978 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9744 04:41:36.872223 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9745 04:41:36.875336 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9746 04:41:36.882068 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9747 04:41:36.885585 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9748 04:41:36.888837 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9749 04:41:36.895128 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9750 04:41:36.898622 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9751 04:41:36.905134 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9752 04:41:36.908311 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9753 04:41:36.911546 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9754 04:41:36.918122 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9755 04:41:36.921554 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9756 04:41:36.924636 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9757 04:41:36.928243 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9758 04:41:36.934929 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9759 04:41:36.938094 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9760 04:41:36.941619 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9761 04:41:36.944648 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9762 04:41:36.951484 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9763 04:41:36.954980 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9764 04:41:36.958327 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9765 04:41:36.961243 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9766 04:41:36.967744 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9767 04:41:36.971352 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9768 04:41:36.974149 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9769 04:41:36.980871 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9770 04:41:36.983953 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9771 04:41:36.990825 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9772 04:41:36.994007 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9773 04:41:37.000456 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9774 04:41:37.003797 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9775 04:41:37.007174 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9776 04:41:37.014124 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9777 04:41:37.017189 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9778 04:41:37.023777 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9779 04:41:37.027245 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9780 04:41:37.030177 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9781 04:41:37.037122 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9782 04:41:37.040131 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9783 04:41:37.047133 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9784 04:41:37.050116 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9785 04:41:37.053600 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9786 04:41:37.059996 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9787 04:41:37.063635 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9788 04:41:37.070177 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9789 04:41:37.073316 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9790 04:41:37.080260 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9791 04:41:37.083550 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9792 04:41:37.086614 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9793 04:41:37.093260 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9794 04:41:37.097038 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9795 04:41:37.103156 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9796 04:41:37.106467 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9797 04:41:37.110252 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9798 04:41:37.116304 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9799 04:41:37.119441 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9800 04:41:37.126362 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9801 04:41:37.129231 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9802 04:41:37.132628 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9803 04:41:37.139333 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9804 04:41:37.142701 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9805 04:41:37.149025 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9806 04:41:37.152562 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9807 04:41:37.159018 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9808 04:41:37.162258 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9809 04:41:37.165768 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9810 04:41:37.172062 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9811 04:41:37.175717 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9812 04:41:37.181870 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9813 04:41:37.185672 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9814 04:41:37.191915 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9815 04:41:37.195073 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9816 04:41:37.198717 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9817 04:41:37.205206 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9818 04:41:37.208300 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9819 04:41:37.215771 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9820 04:41:37.218477 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9821 04:41:37.225205 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9822 04:41:37.227895 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9823 04:41:37.231315 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9824 04:41:37.238008 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9825 04:41:37.241335 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9826 04:41:37.247802 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9827 04:41:37.251266 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9828 04:41:37.255027 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9829 04:41:37.261597 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9830 04:41:37.264964 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9831 04:41:37.271353 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9832 04:41:37.274509 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9833 04:41:37.277864 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9834 04:41:37.284766 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9835 04:41:37.287798 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9836 04:41:37.294473 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9837 04:41:37.298136 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9838 04:41:37.301152 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9839 04:41:37.307733 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9840 04:41:37.311171 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9841 04:41:37.317885 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9842 04:41:37.321068 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9843 04:41:37.327731 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9844 04:41:37.331211 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9845 04:41:37.337184 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9846 04:41:37.340532 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9847 04:41:37.344270 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9848 04:41:37.350567 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9849 04:41:37.353939 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9850 04:41:37.360815 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9851 04:41:37.363589 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9852 04:41:37.370620 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9853 04:41:37.373585 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9854 04:41:37.380284 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9855 04:41:37.383423 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9856 04:41:37.386882 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9857 04:41:37.393357 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9858 04:41:37.396780 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9859 04:41:37.403248 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9860 04:41:37.407567 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9861 04:41:37.413489 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9862 04:41:37.416528 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9863 04:41:37.423248 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9864 04:41:37.426426 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9865 04:41:37.429675 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9866 04:41:37.436215 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9867 04:41:37.439681 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9868 04:41:37.445935 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9869 04:41:37.449682 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9870 04:41:37.456025 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9871 04:41:37.459336 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9872 04:41:37.465702 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9873 04:41:37.469125 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9874 04:41:37.472155 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9875 04:41:37.479045 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9876 04:41:37.482165 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9877 04:41:37.488713 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9878 04:41:37.492402 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9879 04:41:37.498806 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9880 04:41:37.502187 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9881 04:41:37.508638 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9882 04:41:37.512052 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9883 04:41:37.515113 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9884 04:41:37.521971 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9885 04:41:37.525158 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9886 04:41:37.531583 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9887 04:41:37.534936 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9888 04:41:37.541890 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9889 04:41:37.544820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9890 04:41:37.548622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9891 04:41:37.555393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9892 04:41:37.558065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9893 04:41:37.564656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9894 04:41:37.568196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9895 04:41:37.574583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9896 04:41:37.578192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9897 04:41:37.584721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9898 04:41:37.588046 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9899 04:41:37.594345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9900 04:41:37.597724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9901 04:41:37.604170 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9902 04:41:37.607625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9903 04:41:37.614620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9904 04:41:37.617868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9905 04:41:37.624058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9906 04:41:37.627307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9907 04:41:37.634396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9908 04:41:37.637220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9909 04:41:37.644110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9910 04:41:37.647233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9911 04:41:37.654173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9912 04:41:37.656847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9913 04:41:37.663836 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9914 04:41:37.666762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9915 04:41:37.673597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9916 04:41:37.676964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9917 04:41:37.683493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9918 04:41:37.686900 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9919 04:41:37.693317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9920 04:41:37.696662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9921 04:41:37.703065 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9922 04:41:37.703147 INFO: [APUAPC] vio 0
9923 04:41:37.709672 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9924 04:41:37.713412 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9925 04:41:37.716377 INFO: [APUAPC] D0_APC_0: 0x400510
9926 04:41:37.719928 INFO: [APUAPC] D0_APC_1: 0x0
9927 04:41:37.722816 INFO: [APUAPC] D0_APC_2: 0x1540
9928 04:41:37.726218 INFO: [APUAPC] D0_APC_3: 0x0
9929 04:41:37.729752 INFO: [APUAPC] D1_APC_0: 0xffffffff
9930 04:41:37.732947 INFO: [APUAPC] D1_APC_1: 0xffffffff
9931 04:41:37.736304 INFO: [APUAPC] D1_APC_2: 0x3fffff
9932 04:41:37.739810 INFO: [APUAPC] D1_APC_3: 0x0
9933 04:41:37.743215 INFO: [APUAPC] D2_APC_0: 0xffffffff
9934 04:41:37.745994 INFO: [APUAPC] D2_APC_1: 0xffffffff
9935 04:41:37.749434 INFO: [APUAPC] D2_APC_2: 0x3fffff
9936 04:41:37.752541 INFO: [APUAPC] D2_APC_3: 0x0
9937 04:41:37.755768 INFO: [APUAPC] D3_APC_0: 0xffffffff
9938 04:41:37.759669 INFO: [APUAPC] D3_APC_1: 0xffffffff
9939 04:41:37.762826 INFO: [APUAPC] D3_APC_2: 0x3fffff
9940 04:41:37.765638 INFO: [APUAPC] D3_APC_3: 0x0
9941 04:41:37.769777 INFO: [APUAPC] D4_APC_0: 0xffffffff
9942 04:41:37.772240 INFO: [APUAPC] D4_APC_1: 0xffffffff
9943 04:41:37.775783 INFO: [APUAPC] D4_APC_2: 0x3fffff
9944 04:41:37.779060 INFO: [APUAPC] D4_APC_3: 0x0
9945 04:41:37.782572 INFO: [APUAPC] D5_APC_0: 0xffffffff
9946 04:41:37.785723 INFO: [APUAPC] D5_APC_1: 0xffffffff
9947 04:41:37.789179 INFO: [APUAPC] D5_APC_2: 0x3fffff
9948 04:41:37.792273 INFO: [APUAPC] D5_APC_3: 0x0
9949 04:41:37.795855 INFO: [APUAPC] D6_APC_0: 0xffffffff
9950 04:41:37.798689 INFO: [APUAPC] D6_APC_1: 0xffffffff
9951 04:41:37.801989 INFO: [APUAPC] D6_APC_2: 0x3fffff
9952 04:41:37.805748 INFO: [APUAPC] D6_APC_3: 0x0
9953 04:41:37.808721 INFO: [APUAPC] D7_APC_0: 0xffffffff
9954 04:41:37.812382 INFO: [APUAPC] D7_APC_1: 0xffffffff
9955 04:41:37.815257 INFO: [APUAPC] D7_APC_2: 0x3fffff
9956 04:41:37.815339 INFO: [APUAPC] D7_APC_3: 0x0
9957 04:41:37.821752 INFO: [APUAPC] D8_APC_0: 0xffffffff
9958 04:41:37.825091 INFO: [APUAPC] D8_APC_1: 0xffffffff
9959 04:41:37.828214 INFO: [APUAPC] D8_APC_2: 0x3fffff
9960 04:41:37.828323 INFO: [APUAPC] D8_APC_3: 0x0
9961 04:41:37.831711 INFO: [APUAPC] D9_APC_0: 0xffffffff
9962 04:41:37.838158 INFO: [APUAPC] D9_APC_1: 0xffffffff
9963 04:41:37.842049 INFO: [APUAPC] D9_APC_2: 0x3fffff
9964 04:41:37.842131 INFO: [APUAPC] D9_APC_3: 0x0
9965 04:41:37.844932 INFO: [APUAPC] D10_APC_0: 0xffffffff
9966 04:41:37.851270 INFO: [APUAPC] D10_APC_1: 0xffffffff
9967 04:41:37.854910 INFO: [APUAPC] D10_APC_2: 0x3fffff
9968 04:41:37.854992 INFO: [APUAPC] D10_APC_3: 0x0
9969 04:41:37.861466 INFO: [APUAPC] D11_APC_0: 0xffffffff
9970 04:41:37.865058 INFO: [APUAPC] D11_APC_1: 0xffffffff
9971 04:41:37.868311 INFO: [APUAPC] D11_APC_2: 0x3fffff
9972 04:41:37.868392 INFO: [APUAPC] D11_APC_3: 0x0
9973 04:41:37.874834 INFO: [APUAPC] D12_APC_0: 0xffffffff
9974 04:41:37.877827 INFO: [APUAPC] D12_APC_1: 0xffffffff
9975 04:41:37.881153 INFO: [APUAPC] D12_APC_2: 0x3fffff
9976 04:41:37.884301 INFO: [APUAPC] D12_APC_3: 0x0
9977 04:41:37.887581 INFO: [APUAPC] D13_APC_0: 0xffffffff
9978 04:41:37.891293 INFO: [APUAPC] D13_APC_1: 0xffffffff
9979 04:41:37.894600 INFO: [APUAPC] D13_APC_2: 0x3fffff
9980 04:41:37.897524 INFO: [APUAPC] D13_APC_3: 0x0
9981 04:41:37.900874 INFO: [APUAPC] D14_APC_0: 0xffffffff
9982 04:41:37.904478 INFO: [APUAPC] D14_APC_1: 0xffffffff
9983 04:41:37.907347 INFO: [APUAPC] D14_APC_2: 0x3fffff
9984 04:41:37.910885 INFO: [APUAPC] D14_APC_3: 0x0
9985 04:41:37.914776 INFO: [APUAPC] D15_APC_0: 0xffffffff
9986 04:41:37.917518 INFO: [APUAPC] D15_APC_1: 0xffffffff
9987 04:41:37.920763 INFO: [APUAPC] D15_APC_2: 0x3fffff
9988 04:41:37.923796 INFO: [APUAPC] D15_APC_3: 0x0
9989 04:41:37.927377 INFO: [APUAPC] APC_CON: 0x4
9990 04:41:37.927458 INFO: [NOCDAPC] D0_APC_0: 0x0
9991 04:41:37.930975 INFO: [NOCDAPC] D0_APC_1: 0x0
9992 04:41:37.933835 INFO: [NOCDAPC] D1_APC_0: 0x0
9993 04:41:37.937338 INFO: [NOCDAPC] D1_APC_1: 0xfff
9994 04:41:37.940456 INFO: [NOCDAPC] D2_APC_0: 0x0
9995 04:41:37.943895 INFO: [NOCDAPC] D2_APC_1: 0xfff
9996 04:41:37.947624 INFO: [NOCDAPC] D3_APC_0: 0x0
9997 04:41:37.950274 INFO: [NOCDAPC] D3_APC_1: 0xfff
9998 04:41:37.953409 INFO: [NOCDAPC] D4_APC_0: 0x0
9999 04:41:37.956871 INFO: [NOCDAPC] D4_APC_1: 0xfff
10000 04:41:37.960017 INFO: [NOCDAPC] D5_APC_0: 0x0
10001 04:41:37.960099 INFO: [NOCDAPC] D5_APC_1: 0xfff
10002 04:41:37.963563 INFO: [NOCDAPC] D6_APC_0: 0x0
10003 04:41:37.966619 INFO: [NOCDAPC] D6_APC_1: 0xfff
10004 04:41:37.970287 INFO: [NOCDAPC] D7_APC_0: 0x0
10005 04:41:37.973615 INFO: [NOCDAPC] D7_APC_1: 0xfff
10006 04:41:37.976562 INFO: [NOCDAPC] D8_APC_0: 0x0
10007 04:41:37.979793 INFO: [NOCDAPC] D8_APC_1: 0xfff
10008 04:41:37.983521 INFO: [NOCDAPC] D9_APC_0: 0x0
10009 04:41:37.986278 INFO: [NOCDAPC] D9_APC_1: 0xfff
10010 04:41:37.989718 INFO: [NOCDAPC] D10_APC_0: 0x0
10011 04:41:37.993452 INFO: [NOCDAPC] D10_APC_1: 0xfff
10012 04:41:37.996611 INFO: [NOCDAPC] D11_APC_0: 0x0
10013 04:41:37.999870 INFO: [NOCDAPC] D11_APC_1: 0xfff
10014 04:41:38.002703 INFO: [NOCDAPC] D12_APC_0: 0x0
10015 04:41:38.002784 INFO: [NOCDAPC] D12_APC_1: 0xfff
10016 04:41:38.006113 INFO: [NOCDAPC] D13_APC_0: 0x0
10017 04:41:38.010002 INFO: [NOCDAPC] D13_APC_1: 0xfff
10018 04:41:38.012887 INFO: [NOCDAPC] D14_APC_0: 0x0
10019 04:41:38.016443 INFO: [NOCDAPC] D14_APC_1: 0xfff
10020 04:41:38.019299 INFO: [NOCDAPC] D15_APC_0: 0x0
10021 04:41:38.022854 INFO: [NOCDAPC] D15_APC_1: 0xfff
10022 04:41:38.026424 INFO: [NOCDAPC] APC_CON: 0x4
10023 04:41:38.029811 INFO: [APUAPC] set_apusys_apc done
10024 04:41:38.032633 INFO: [DEVAPC] devapc_init done
10025 04:41:38.036146 INFO: GICv3 without legacy support detected.
10026 04:41:38.039148 INFO: ARM GICv3 driver initialized in EL3
10027 04:41:38.046311 INFO: Maximum SPI INTID supported: 639
10028 04:41:38.049221 INFO: BL31: Initializing runtime services
10029 04:41:38.055607 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10030 04:41:38.055689 INFO: SPM: enable CPC mode
10031 04:41:38.062558 INFO: mcdi ready for mcusys-off-idle and system suspend
10032 04:41:38.065870 INFO: BL31: Preparing for EL3 exit to normal world
10033 04:41:38.068870 INFO: Entry point address = 0x80000000
10034 04:41:38.072281 INFO: SPSR = 0x8
10035 04:41:38.078065
10036 04:41:38.078146
10037 04:41:38.078210
10038 04:41:38.081345 Starting depthcharge on Spherion...
10039 04:41:38.081426
10040 04:41:38.081490 Wipe memory regions:
10041 04:41:38.081550
10042 04:41:38.082194 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10043 04:41:38.082295 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10044 04:41:38.082633 Setting prompt string to ['asurada:']
10045 04:41:38.082713 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10046 04:41:38.084962 [0x00000040000000, 0x00000054600000)
10047 04:41:38.206910
10048 04:41:38.207028 [0x00000054660000, 0x00000080000000)
10049 04:41:38.467823
10050 04:41:38.467962 [0x000000821a7280, 0x000000ffe64000)
10051 04:41:39.212593
10052 04:41:39.212763 [0x00000100000000, 0x00000240000000)
10053 04:41:41.102224
10054 04:41:41.106183 Initializing XHCI USB controller at 0x11200000.
10055 04:41:42.143687
10056 04:41:42.147049 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10057 04:41:42.147166
10058 04:41:42.147271
10059 04:41:42.147390
10060 04:41:42.147698 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10062 04:41:42.247988 asurada: tftpboot 192.168.201.1 12699805/tftp-deploy-ft8eg3xo/kernel/image.itb 12699805/tftp-deploy-ft8eg3xo/kernel/cmdline
10063 04:41:42.248121 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10064 04:41:42.248235 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10065 04:41:42.252472 tftpboot 192.168.201.1 12699805/tftp-deploy-ft8eg3xo/kernel/image.itp-deploy-ft8eg3xo/kernel/cmdline
10066 04:41:42.252553
10067 04:41:42.252622 Waiting for link
10068 04:41:42.413201
10069 04:41:42.413358 R8152: Initializing
10070 04:41:42.413458
10071 04:41:42.416447 Version 6 (ocp_data = 5c30)
10072 04:41:42.416550
10073 04:41:42.419718 R8152: Done initializing
10074 04:41:42.419792
10075 04:41:42.419853 Adding net device
10076 04:41:44.322080
10077 04:41:44.322237 done.
10078 04:41:44.322336
10079 04:41:44.322427 MAC: 00:24:32:30:7c:7b
10080 04:41:44.322516
10081 04:41:44.325435 Sending DHCP discover... done.
10082 04:41:44.325537
10083 04:41:48.601817 Waiting for reply... done.
10084 04:41:48.601962
10085 04:41:48.602038 Sending DHCP request... done.
10086 04:41:48.604783
10087 04:41:48.604864 Waiting for reply... done.
10088 04:41:48.604927
10089 04:41:48.607897 My ip is 192.168.201.14
10090 04:41:48.607992
10091 04:41:48.611342 The DHCP server ip is 192.168.201.1
10092 04:41:48.611469
10093 04:41:48.614828 TFTP server IP predefined by user: 192.168.201.1
10094 04:41:48.614909
10095 04:41:48.621110 Bootfile predefined by user: 12699805/tftp-deploy-ft8eg3xo/kernel/image.itb
10096 04:41:48.621190
10097 04:41:48.624454 Sending tftp read request... done.
10098 04:41:48.624533
10099 04:41:48.630726 Waiting for the transfer...
10100 04:41:48.630833
10101 04:41:49.182633 00000000 ################################################################
10102 04:41:49.182768
10103 04:41:49.743789 00080000 ################################################################
10104 04:41:49.743954
10105 04:41:50.295732 00100000 ################################################################
10106 04:41:50.295878
10107 04:41:50.853122 00180000 ################################################################
10108 04:41:50.853284
10109 04:41:51.402366 00200000 ################################################################
10110 04:41:51.402500
10111 04:41:51.961878 00280000 ################################################################
10112 04:41:51.962010
10113 04:41:52.502452 00300000 ################################################################
10114 04:41:52.502591
10115 04:41:53.032424 00380000 ################################################################
10116 04:41:53.032555
10117 04:41:53.574443 00400000 ################################################################
10118 04:41:53.574575
10119 04:41:54.111617 00480000 ################################################################
10120 04:41:54.111787
10121 04:41:54.653582 00500000 ################################################################
10122 04:41:54.653714
10123 04:41:55.304656 00580000 ################################################################
10124 04:41:55.305149
10125 04:41:56.013548 00600000 ################################################################
10126 04:41:56.014172
10127 04:41:56.694422 00680000 ################################################################
10128 04:41:56.694999
10129 04:41:57.398223 00700000 ################################################################
10130 04:41:57.398733
10131 04:41:58.089255 00780000 ################################################################
10132 04:41:58.089453
10133 04:41:58.787526 00800000 ################################################################
10134 04:41:58.788043
10135 04:41:59.502811 00880000 ################################################################
10136 04:41:59.503296
10137 04:42:00.200497 00900000 ################################################################
10138 04:42:00.200636
10139 04:42:00.861331 00980000 ################################################################
10140 04:42:00.861861
10141 04:42:01.564216 00a00000 ################################################################
10142 04:42:01.564766
10143 04:42:02.282291 00a80000 ################################################################
10144 04:42:02.282795
10145 04:42:02.992797 00b00000 ################################################################
10146 04:42:02.993000
10147 04:42:03.628294 00b80000 ################################################################
10148 04:42:03.628449
10149 04:42:04.228674 00c00000 ################################################################
10150 04:42:04.228856
10151 04:42:04.878282 00c80000 ################################################################
10152 04:42:04.878467
10153 04:42:05.574691 00d00000 ################################################################
10154 04:42:05.575196
10155 04:42:06.229444 00d80000 ################################################################
10156 04:42:06.229939
10157 04:42:06.878543 00e00000 ################################################################
10158 04:42:06.878934
10159 04:42:07.470073 00e80000 ################################################################
10160 04:42:07.470232
10161 04:42:08.026730 00f00000 ################################################################
10162 04:42:08.027257
10163 04:42:08.696180 00f80000 ################################################################
10164 04:42:08.696685
10165 04:42:09.291407 01000000 ################################################################
10166 04:42:09.291585
10167 04:42:09.868779 01080000 ################################################################
10168 04:42:09.868915
10169 04:42:10.431807 01100000 ################################################################
10170 04:42:10.431945
10171 04:42:11.062985 01180000 ################################################################
10172 04:42:11.063510
10173 04:42:11.718861 01200000 ################################################################
10174 04:42:11.719549
10175 04:42:12.399961 01280000 ################################################################
10176 04:42:12.400114
10177 04:42:12.982792 01300000 ################################################################
10178 04:42:12.983157
10179 04:42:13.575882 01380000 ################################################################
10180 04:42:13.576017
10181 04:42:14.198770 01400000 ################################################################
10182 04:42:14.199301
10183 04:42:14.821934 01480000 ################################################################
10184 04:42:14.822071
10185 04:42:15.367375 01500000 ################################################################
10186 04:42:15.367544
10187 04:42:15.917125 01580000 ################################################################
10188 04:42:15.917264
10189 04:42:16.472662 01600000 ################################################################
10190 04:42:16.472811
10191 04:42:17.057707 01680000 ################################################################
10192 04:42:17.057860
10193 04:42:17.632778 01700000 ################################################################
10194 04:42:17.632926
10195 04:42:18.197061 01780000 ################################################################
10196 04:42:18.197231
10197 04:42:18.801308 01800000 ################################################################
10198 04:42:18.801801
10199 04:42:19.465327 01880000 ################################################################
10200 04:42:19.465812
10201 04:42:20.119476 01900000 ################################################################
10202 04:42:20.119654
10203 04:42:20.661449 01980000 ################################################################
10204 04:42:20.661625
10205 04:42:21.226441 01a00000 ################################################################
10206 04:42:21.226589
10207 04:42:21.768782 01a80000 ################################################################
10208 04:42:21.768936
10209 04:42:22.328705 01b00000 ################################################################
10210 04:42:22.328872
10211 04:42:22.872429 01b80000 ################################################################
10212 04:42:22.872580
10213 04:42:23.465600 01c00000 ################################################################
10214 04:42:23.465730
10215 04:42:23.477512 01c80000 ## done.
10216 04:42:23.477593
10217 04:42:23.481080 The bootfile was 29895222 bytes long.
10218 04:42:23.481163
10219 04:42:23.481227 Sending tftp read request... done.
10220 04:42:23.484646
10221 04:42:23.484727 Waiting for the transfer...
10222 04:42:23.484791
10223 04:42:23.487711 00000000 # done.
10224 04:42:23.487794
10225 04:42:23.494055 Command line loaded dynamically from TFTP file: 12699805/tftp-deploy-ft8eg3xo/kernel/cmdline
10226 04:42:23.494139
10227 04:42:23.517559 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12699805/extract-nfsrootfs-yh0oczb8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10228 04:42:23.517670
10229 04:42:23.517762 Loading FIT.
10230 04:42:23.517849
10231 04:42:23.520797 Image ramdisk-1 has 17797402 bytes.
10232 04:42:23.520877
10233 04:42:23.523635 Image fdt-1 has 47278 bytes.
10234 04:42:23.523715
10235 04:42:23.527115 Image kernel-1 has 12048508 bytes.
10236 04:42:23.527196
10237 04:42:23.537008 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10238 04:42:23.537117
10239 04:42:23.553388 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10240 04:42:23.553524
10241 04:42:23.559896 Choosing best match conf-1 for compat google,spherion-rev2.
10242 04:42:23.559983
10243 04:42:23.567628 Connected to device vid:did:rid of 1ae0:0028:00
10244 04:42:23.574484
10245 04:42:23.577622 tpm_get_response: command 0x17b, return code 0x0
10246 04:42:23.577706
10247 04:42:23.581012 ec_init: CrosEC protocol v3 supported (256, 248)
10248 04:42:23.585006
10249 04:42:23.588175 tpm_cleanup: add release locality here.
10250 04:42:23.588265
10251 04:42:23.588332 Shutting down all USB controllers.
10252 04:42:23.591524
10253 04:42:23.591624 Removing current net device
10254 04:42:23.591720
10255 04:42:23.598371 Exiting depthcharge with code 4 at timestamp: 74749823
10256 04:42:23.598479
10257 04:42:23.601161 LZMA decompressing kernel-1 to 0x821a6718
10258 04:42:23.601262
10259 04:42:23.604589 LZMA decompressing kernel-1 to 0x40000000
10260 04:42:25.104212
10261 04:42:25.104813 jumping to kernel
10262 04:42:25.106612 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10263 04:42:25.107174 start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10264 04:42:25.107643 Setting prompt string to ['Linux version [0-9]']
10265 04:42:25.108031 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10266 04:42:25.108482 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10267 04:42:25.186135
10268 04:42:25.189237 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10269 04:42:25.193650 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10270 04:42:25.194152 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10271 04:42:25.194580 Setting prompt string to []
10272 04:42:25.195198 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10273 04:42:25.195793 Using line separator: #'\n'#
10274 04:42:25.196186 No login prompt set.
10275 04:42:25.196619 Parsing kernel messages
10276 04:42:25.197009 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10277 04:42:25.197974 [login-action] Waiting for messages, (timeout 00:03:38)
10278 04:42:25.212462 [ 0.000000] Linux version 6.1.75-cip14-rt8 (KernelCI@build-j97480-arm64-gcc-10-defconfig-arm64-chromebook-6n26j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024
10279 04:42:25.215591 [ 0.000000] random: crng init done
10280 04:42:25.222351 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10281 04:42:25.225839 [ 0.000000] efi: UEFI not found.
10282 04:42:25.232942 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10283 04:42:25.242658 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10284 04:42:25.251693 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10285 04:42:25.258110 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10286 04:42:25.265175 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10287 04:42:25.271390 [ 0.000000] printk: bootconsole [mtk8250] enabled
10288 04:42:25.278262 [ 0.000000] NUMA: No NUMA configuration found
10289 04:42:25.284374 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10290 04:42:25.291293 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10291 04:42:25.291744 [ 0.000000] Zone ranges:
10292 04:42:25.298138 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10293 04:42:25.301981 [ 0.000000] DMA32 empty
10294 04:42:25.307467 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10295 04:42:25.310983 [ 0.000000] Movable zone start for each node
10296 04:42:25.314201 [ 0.000000] Early memory node ranges
10297 04:42:25.321496 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10298 04:42:25.327633 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10299 04:42:25.334096 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10300 04:42:25.340914 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10301 04:42:25.347505 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10302 04:42:25.354124 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10303 04:42:25.411018 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10304 04:42:25.417357 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10305 04:42:25.424381 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10306 04:42:25.427186 [ 0.000000] psci: probing for conduit method from DT.
10307 04:42:25.434187 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10308 04:42:25.437224 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10309 04:42:25.443731 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10310 04:42:25.447133 [ 0.000000] psci: SMC Calling Convention v1.2
10311 04:42:25.453799 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10312 04:42:25.457206 [ 0.000000] Detected VIPT I-cache on CPU0
10313 04:42:25.463408 [ 0.000000] CPU features: detected: GIC system register CPU interface
10314 04:42:25.470313 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10315 04:42:25.476640 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10316 04:42:25.483548 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10317 04:42:25.493113 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10318 04:42:25.499309 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10319 04:42:25.502822 [ 0.000000] alternatives: applying boot alternatives
10320 04:42:25.509632 [ 0.000000] Fallback order for Node 0: 0
10321 04:42:25.516133 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10322 04:42:25.519485 [ 0.000000] Policy zone: Normal
10323 04:42:25.543112 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12699805/extract-nfsrootfs-yh0oczb8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10324 04:42:25.552398 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10325 04:42:25.563626 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10326 04:42:25.573316 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10327 04:42:25.579738 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10328 04:42:25.583249 <6>[ 0.000000] software IO TLB: area num 8.
10329 04:42:25.639968 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10330 04:42:25.788851 <6>[ 0.000000] Memory: 7949812K/8385536K available (18048K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 616K bss, 402956K reserved, 32768K cma-reserved)
10331 04:42:25.795649 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10332 04:42:25.802384 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10333 04:42:25.806294 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10334 04:42:25.812464 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10335 04:42:25.819343 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10336 04:42:25.822206 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10337 04:42:25.832244 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10338 04:42:25.838482 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10339 04:42:25.845662 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10340 04:42:25.851927 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10341 04:42:25.855005 <6>[ 0.000000] GICv3: 608 SPIs implemented
10342 04:42:25.858381 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10343 04:42:25.865503 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10344 04:42:25.868378 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10345 04:42:25.874946 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10346 04:42:25.888350 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10347 04:42:25.901180 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10348 04:42:25.907997 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10349 04:42:25.915845 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10350 04:42:25.928880 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10351 04:42:25.935532 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10352 04:42:25.942329 <6>[ 0.009179] Console: colour dummy device 80x25
10353 04:42:25.952030 <6>[ 0.013931] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10354 04:42:25.958507 <6>[ 0.024373] pid_max: default: 32768 minimum: 301
10355 04:42:25.962070 <6>[ 0.029244] LSM: Security Framework initializing
10356 04:42:25.968600 <6>[ 0.034182] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10357 04:42:25.978455 <6>[ 0.041997] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10358 04:42:25.988222 <6>[ 0.051409] cblist_init_generic: Setting adjustable number of callback queues.
10359 04:42:25.992283 <6>[ 0.058851] cblist_init_generic: Setting shift to 3 and lim to 1.
10360 04:42:26.001361 <6>[ 0.065189] cblist_init_generic: Setting adjustable number of callback queues.
10361 04:42:26.007837 <6>[ 0.072663] cblist_init_generic: Setting shift to 3 and lim to 1.
10362 04:42:26.010988 <6>[ 0.079104] rcu: Hierarchical SRCU implementation.
10363 04:42:26.017887 <6>[ 0.079106] rcu: Max phase no-delay instances is 1000.
10364 04:42:26.024964 <6>[ 0.079130] printk: bootconsole [mtk8250] printing thread started
10365 04:42:26.031499 <6>[ 0.097457] EFI services will not be available.
10366 04:42:26.034399 <6>[ 0.097661] smp: Bringing up secondary CPUs ...
10367 04:42:26.040613 <6>[ 0.097975] Detected VIPT I-cache on CPU1
10368 04:42:26.047181 <6>[ 0.098044] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10369 04:42:26.053868 <6>[ 0.098075] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10370 04:42:26.064202 <6>[ 0.125945] Detected VIPT I-cache on CPU2
10371 04:42:26.073686 <6>[ 0.125993] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10372 04:42:26.080110 <6>[ 0.126008] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10373 04:42:26.083357 <6>[ 0.126261] Detected VIPT I-cache on CPU3
10374 04:42:26.090556 <6>[ 0.126307] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10375 04:42:26.096786 <6>[ 0.126321] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10376 04:42:26.103498 <6>[ 0.126628] CPU features: detected: Spectre-v4
10377 04:42:26.106715 <6>[ 0.126635] CPU features: detected: Spectre-BHB
10378 04:42:26.110131 <6>[ 0.126640] Detected PIPT I-cache on CPU4
10379 04:42:26.116582 <6>[ 0.126698] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10380 04:42:26.122911 <6>[ 0.126715] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10381 04:42:26.129803 <6>[ 0.127004] Detected PIPT I-cache on CPU5
10382 04:42:26.136517 <6>[ 0.127063] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10383 04:42:26.142564 <6>[ 0.127079] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10384 04:42:26.146100 <6>[ 0.127352] Detected PIPT I-cache on CPU6
10385 04:42:26.156051 <6>[ 0.127417] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10386 04:42:26.162848 <6>[ 0.127432] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10387 04:42:26.169314 <6>[ 0.127723] Detected PIPT I-cache on CPU7
10388 04:42:26.175663 <6>[ 0.127788] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10389 04:42:26.182224 <6>[ 0.127804] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10390 04:42:26.185505 <6>[ 0.127850] smp: Brought up 1 node, 8 CPUs
10391 04:42:26.192092 <6>[ 0.127855] SMP: Total of 8 processors activated.
10392 04:42:26.195173 <6>[ 0.127858] CPU features: detected: 32-bit EL0 Support
10393 04:42:26.205140 <6>[ 0.127860] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10394 04:42:26.211882 <6>[ 0.127863] CPU features: detected: Common not Private translations
10395 04:42:26.218070 <6>[ 0.127864] CPU features: detected: CRC32 instructions
10396 04:42:26.221700 <6>[ 0.127867] CPU features: detected: RCpc load-acquire (LDAPR)
10397 04:42:26.228029 <6>[ 0.127868] CPU features: detected: LSE atomic instructions
10398 04:42:26.234971 <6>[ 0.127870] CPU features: detected: Privileged Access Never
10399 04:42:26.241305 <6>[ 0.127871] CPU features: detected: RAS Extension Support
10400 04:42:26.247678 <6>[ 0.127874] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10401 04:42:26.251270 <6>[ 0.127941] CPU: All CPU(s) started at EL2
10402 04:42:26.257542 <6>[ 0.127943] alternatives: applying system-wide alternatives
10403 04:42:26.261052 <6>[ 0.141004] devtmpfs: initialized
10404 04:42:26.270771 <6>[ 0.147264] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10405 04:42:26.296044 ��ET: Registered PF_INET protocol family
10406 04:42:26.299188 <6>[ <0.366772] printk: console [ttyS0] printing thread started
10407 04:42:26.306064 6<6>[ 0.366803] printk: console [ttyS0] enabled
10408 04:42:26.312273 >[ 0.242916] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10409 04:42:26.320370 <6>[ 0.366807] printk: bootconsole [mtk8250] disabled
10410 04:42:26.326901 <6>[ 0.384886] printk: bootconsole [mtk8250] printing thread stopped
10411 04:42:26.330286 <6>[ 0.386236] SuperH (H)SCI(F) driver initialized
10412 04:42:26.336915 <6>[ 0.386734] msm_serial: driver initialized
10413 04:42:26.343155 <6>[ 0.391431] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10414 04:42:26.353338 <6>[ 0.391463] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10415 04:42:26.363878 <6>[ 0.391493] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10416 04:42:26.369676 <6>[ 0.391523] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10417 04:42:26.379956 <6>[ 0.391544] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10418 04:42:26.392939 <6>[ 0.391571] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10419 04:42:26.404838 <6>[ 0.391600] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10420 04:42:26.408987 <6>[ 0.391718] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10421 04:42:26.413753 <6>[ 0.391747] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10422 04:42:26.419145 <6>[ 0.402573] loop: module loaded
10423 04:42:26.422574 <6>[ 0.405129] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10424 04:42:26.430592 <4>[ 0.421992] mtk-pmic-keys: Failed to locate of_node [id: -1]
10425 04:42:26.434188 <6>[ 0.422790] megasas: 07.719.03.00-rc1
10426 04:42:26.440429 <6>[ 0.434810] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10427 04:42:26.443972 <6>[ 0.443693] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10428 04:42:26.450673 <6>[ 0.447125] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10429 04:42:26.463542 <6>[ 0.500981] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10430 04:42:26.928247 <6>[ 0.995229] Freeing initrd memory: 17376K
10431 04:42:26.935973 <6>[ 1.001464] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10432 04:42:26.942719 <6>[ 1.006247] tun: Universal TUN/TAP device driver, 1.6
10433 04:42:26.946207 <6>[ 1.007035] thunder_xcv, ver 1.0
10434 04:42:26.949425 <6>[ 1.007052] thunder_bgx, ver 1.0
10435 04:42:26.953012 <6>[ 1.007068] nicpf, ver 1.0
10436 04:42:26.959336 <6>[ 1.008142] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10437 04:42:26.965889 <6>[ 1.008145] hns3: Copyright (c) 2017 Huawei Corporation.
10438 04:42:26.969464 <6>[ 1.008172] hclge is initializing
10439 04:42:26.976137 <6>[ 1.008187] e1000: Intel(R) PRO/1000 Network Driver
10440 04:42:26.979519 <6>[ 1.008188] e1000: Copyright (c) 1999-2006 Intel Corporation.
10441 04:42:26.986978 <6>[ 1.008209] e1000e: Intel(R) PRO/1000 Network Driver
10442 04:42:26.990278 <6>[ 1.008210] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10443 04:42:26.997675 <6>[ 1.008226] igb: Intel(R) Gigabit Ethernet Network Driver
10444 04:42:27.003913 <6>[ 1.008227] igb: Copyright (c) 2007-2014 Intel Corporation.
10445 04:42:27.010904 <6>[ 1.008241] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10446 04:42:27.014413 <6>[ 1.008244] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10447 04:42:27.021025 <6>[ 1.008545] sky2: driver version 1.30
10448 04:42:27.024478 <6>[ 1.009619] VFIO - User Level meta-driver version: 0.3
10449 04:42:27.031569 <6>[ 1.012445] usbcore: registered new interface driver usb-storage
10450 04:42:27.037509 <6>[ 1.012626] usbcore: registered new device driver onboard-usb-hub
10451 04:42:27.044283 <6>[ 1.015456] mt6397-rtc mt6359-rtc: registered as rtc0
10452 04:42:27.051183 <6>[ 1.015610] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-04T04:42:29 UTC (1707021749)
10453 04:42:27.057312 <6>[ 1.016226] i2c_dev: i2c /dev entries driver
10454 04:42:27.063898 <6>[ 1.023394] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10455 04:42:27.070868 <6>[ 1.039388] cpu cpu0: EM: created perf domain
10456 04:42:27.073898 <6>[ 1.039706] cpu cpu4: EM: created perf domain
10457 04:42:27.080935 <6>[ 1.041630] sdhci: Secure Digital Host Controller Interface driver
10458 04:42:27.083675 <6>[ 1.041631] sdhci: Copyright(c) Pierre Ossman
10459 04:42:27.090345 <6>[ 1.041984] Synopsys Designware Multimedia Card Interface Driver
10460 04:42:27.097309 <6>[ 1.042337] sdhci-pltfm: SDHCI platform and OF driver helper
10461 04:42:27.103913 <6>[ 1.046626] ledtrig-cpu: registered to indicate activity on CPUs
10462 04:42:27.107153 <6>[ 1.047259] mmc0: CQHCI version 5.10
10463 04:42:27.113867 <6>[ 1.047419] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10464 04:42:27.120696 <6>[ 1.047700] usbcore: registered new interface driver usbhid
10465 04:42:27.123708 <6>[ 1.047702] usbhid: USB HID core driver
10466 04:42:27.130076 <6>[ 1.047828] spi_master spi0: will run message pump with realtime priority
10467 04:42:27.143601 <6>[ 1.078546] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10468 04:42:27.156685 <6>[ 1.080726] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10469 04:42:27.163048 <6>[ 1.081578] cros-ec-spi spi0.0: Chrome EC device registered
10470 04:42:27.173344 <6>[ 1.098992] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10471 04:42:27.176319 <6>[ 1.101386] NET: Registered PF_PACKET protocol family
10472 04:42:27.183258 <6>[ 1.101489] 9pnet: Installing 9P2000 support
10473 04:42:27.186288 <5>[ 1.101539] Key type dns_resolver registered
10474 04:42:27.189435 <6>[ 1.101928] registered taskstats version 1
10475 04:42:27.195990 <5>[ 1.101953] Loading compiled-in X.509 certificates
10476 04:42:27.206305 <4>[ 1.125953] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10477 04:42:27.216037 <4>[ 1.126090] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10478 04:42:27.222623 <3>[ 1.126099] debugfs: File 'uA_load' in directory '/' already present!
10479 04:42:27.229499 <3>[ 1.126106] debugfs: File 'min_uV' in directory '/' already present!
10480 04:42:27.236078 <3>[ 1.126110] debugfs: File 'max_uV' in directory '/' already present!
10481 04:42:27.242603 <3>[ 1.126113] debugfs: File 'constraint_flags' in directory '/' already present!
10482 04:42:27.252662 <3>[ 1.127976] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10483 04:42:27.259106 <6>[ 1.134801] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10484 04:42:27.265876 <6>[ 1.135509] xhci-mtk 11200000.usb: xHCI Host Controller
10485 04:42:27.272275 <6>[ 1.135543] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10486 04:42:27.282114 <6>[ 1.135741] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10487 04:42:27.285680 <6>[ 1.135789] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10488 04:42:27.292193 <6>[ 1.135888] xhci-mtk 11200000.usb: xHCI Host Controller
10489 04:42:27.298826 <6>[ 1.135897] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10490 04:42:27.308637 <6>[ 1.135905] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10491 04:42:27.312735 <6>[ 1.136438] hub 1-0:1.0: USB hub found
10492 04:42:27.315041 <6>[ 1.136460] hub 1-0:1.0: 1 port detected
10493 04:42:27.325018 <6>[ 1.136793] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10494 04:42:27.328348 <6>[ 1.137296] hub 2-0:1.0: USB hub found
10495 04:42:27.331564 <6>[ 1.137311] hub 2-0:1.0: 1 port detected
10496 04:42:27.338253 <6>[ 1.141183] mtk-msdc 11f70000.mmc: Got CD GPIO
10497 04:42:27.341936 <6>[ 1.141516] mmc0: Command Queue Engine enabled
10498 04:42:27.348788 <6>[ 1.141532] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10499 04:42:27.351840 <6>[ 1.142058] mmcblk0: mmc0:0001 DA4128 116 GiB
10500 04:42:27.358290 <6>[ 1.145559] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10501 04:42:27.365003 <6>[ 1.148060] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10502 04:42:27.368334 <6>[ 1.149128] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10503 04:42:27.374684 <6>[ 1.150085] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10504 04:42:27.384714 <6>[ 1.152986] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10505 04:42:27.391680 <6>[ 1.152992] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10506 04:42:27.401125 <4>[ 1.153063] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10507 04:42:27.407645 <6>[ 1.153557] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10508 04:42:27.418113 <6>[ 1.153558] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10509 04:42:27.424399 <6>[ 1.153687] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10510 04:42:27.430906 <6>[ 1.153697] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10511 04:42:27.441135 <6>[ 1.153699] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10512 04:42:27.450594 <6>[ 1.153702] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10513 04:42:27.457436 <6>[ 1.154726] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10514 04:42:27.467397 <6>[ 1.154742] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10515 04:42:27.474199 <6>[ 1.154746] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10516 04:42:27.483863 <6>[ 1.154750] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10517 04:42:27.490357 <6>[ 1.154753] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10518 04:42:27.500500 <6>[ 1.154757] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10519 04:42:27.507566 <6>[ 1.154761] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10520 04:42:27.516712 <6>[ 1.154764] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10521 04:42:27.523484 <6>[ 1.154768] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10522 04:42:27.533499 <6>[ 1.154772] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10523 04:42:27.540382 <6>[ 1.154775] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10524 04:42:27.550188 <6>[ 1.154779] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10525 04:42:27.556349 <6>[ 1.154782] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10526 04:42:27.566576 <6>[ 1.154786] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10527 04:42:27.572704 <6>[ 1.154790] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10528 04:42:27.579945 <6>[ 1.155062] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10529 04:42:27.586135 <6>[ 1.155761] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10530 04:42:27.593015 <6>[ 1.156001] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10531 04:42:27.599280 <6>[ 1.156235] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10532 04:42:27.605675 <6>[ 1.156484] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10533 04:42:27.615618 <6>[ 1.156632] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10534 04:42:27.626063 <6>[ 1.156641] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10535 04:42:27.635552 <6>[ 1.156643] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10536 04:42:27.645547 <6>[ 1.156647] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10537 04:42:27.652005 <6>[ 1.156650] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10538 04:42:27.661938 <6>[ 1.156654] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10539 04:42:27.671961 <6>[ 1.156656] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10540 04:42:27.681681 <6>[ 1.156659] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10541 04:42:27.691955 <6>[ 1.156662] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10542 04:42:27.702035 <6>[ 1.156665] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10543 04:42:27.711481 <6>[ 1.156668] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10544 04:42:27.717966 <6>[ 1.158032] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10545 04:42:27.724466 <6>[ 1.180101] Trying to probe devices needed for running init ...
10546 04:42:27.731236 <6>[ 1.551537] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10547 04:42:27.734669 <6>[ 1.703627] hub 1-1:1.0: USB hub found
10548 04:42:27.741134 <6>[ 1.704010] hub 1-1:1.0: 4 ports detected
10549 04:42:27.744083 <6>[ 1.706738] hub 1-1:1.0: USB hub found
10550 04:42:27.747612 <6>[ 1.706973] hub 1-1:1.0: 4 ports detected
10551 04:42:27.767190 <6>[ 1.827771] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10552 04:42:27.788622 <6>[ 1.853051] hub 2-1:1.0: USB hub found
10553 04:42:27.791256 <6>[ 1.853506] hub 2-1:1.0: 3 ports detected
10554 04:42:27.794949 <6>[ 1.856466] hub 2-1:1.0: USB hub found
10555 04:42:27.797855 <6>[ 1.856924] hub 2-1:1.0: 3 ports detected
10556 04:42:27.963651 <6>[ 2.023669] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10557 04:42:28.084595 <6>[ 2.151097] hub 1-1.4:1.0: USB hub found
10558 04:42:28.087738 <6>[ 2.151520] hub 1-1.4:1.0: 2 ports detected
10559 04:42:28.090856 <6>[ 2.155054] hub 1-1.4:1.0: USB hub found
10560 04:42:28.097446 <6>[ 2.155432] hub 1-1.4:1.0: 2 ports detected
10561 04:42:28.167130 <6>[ 2.227808] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10562 04:42:28.383316 <6>[ 2.443676] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10563 04:42:28.567266 <6>[ 2.627683] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10564 04:42:39.403765 <6>[ 13.472375] ALSA device list:
10565 04:42:39.410861 <6>[ 13.472391] No soundcards found.
10566 04:42:39.413745 <6>[ 13.476868] Freeing unused kernel memory: 8448K
10567 04:42:39.417320 <6>[ 13.477049] Run /init as init process
10568 04:42:39.420918 Loading, please wait...
10569 04:42:39.444467 Starting version 247.3-7+deb11u2
10570 04:42:39.642503 <6>[ 13.706922] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10571 04:42:39.667118 <6>[ 13.723453] remoteproc remoteproc0: scp is available
10572 04:42:39.673412 <6>[ 13.723656] remoteproc remoteproc0: powering up scp
10573 04:42:39.680331 <6>[ 13.723673] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10574 04:42:39.687127 <6>[ 13.723745] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10575 04:42:39.696931 <3>[ 13.750384] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10576 04:42:39.703123 <3>[ 13.750413] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10577 04:42:39.713564 <3>[ 13.750418] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10578 04:42:39.720042 <3>[ 13.750622] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10579 04:42:39.726366 <3>[ 13.750627] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10580 04:42:39.736492 <3>[ 13.750632] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10581 04:42:39.742762 <3>[ 13.750642] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10582 04:42:39.752840 <3>[ 13.750651] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10583 04:42:39.759695 <3>[ 13.750685] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10584 04:42:39.769405 <3>[ 13.750726] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10585 04:42:39.776073 <3>[ 13.750733] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10586 04:42:39.786787 <3>[ 13.750735] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10587 04:42:39.793133 <3>[ 13.750752] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10588 04:42:39.799431 <3>[ 13.750756] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10589 04:42:39.809461 <3>[ 13.750760] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10590 04:42:39.816467 <3>[ 13.750765] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10591 04:42:39.826862 <3>[ 13.750767] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10592 04:42:39.834090 <3>[ 13.750792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10593 04:42:39.840076 <6>[ 13.808009] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10594 04:42:39.849961 <6>[ 13.808056] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10595 04:42:39.856437 <6>[ 13.808065] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10596 04:42:39.862887 <6>[ 13.826172] mc: Linux media interface: v0.10
10597 04:42:39.869774 <4>[ 13.828819] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10598 04:42:39.876153 <4>[ 13.834873] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10599 04:42:39.885945 <6>[ 13.844940] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10600 04:42:39.889226 <6>[ 13.866398] videodev: Linux video capture interface: v2.00
10601 04:42:39.899650 <4>[ 13.869627] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10602 04:42:39.902409 <4>[ 13.869627] Fallback method does not support PEC.
10603 04:42:39.912062 <6>[ 13.873643] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10604 04:42:39.918748 <6>[ 13.873643] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10605 04:42:39.925738 <6>[ 13.873662] remoteproc remoteproc0: remote processor scp is now up
10606 04:42:39.931864 <6>[ 13.884891] usbcore: registered new device driver r8152-cfgselector
10607 04:42:39.942787 <3>[ 13.886338] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10608 04:42:39.948766 <6>[ 13.908062] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10609 04:42:39.958347 <3>[ 13.909273] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10610 04:42:39.965598 <6>[ 13.910331] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10611 04:42:39.971876 <6>[ 13.928778] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10612 04:42:39.978372 <6>[ 13.928795] pci_bus 0000:00: root bus resource [bus 00-ff]
10613 04:42:39.984573 <6>[ 13.928801] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10614 04:42:39.995097 <6>[ 13.928805] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10615 04:42:40.001201 <6>[ 13.928848] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10616 04:42:40.011355 <6>[ 13.928873] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10617 04:42:40.014506 <6>[ 13.928958] pci 0000:00:00.0: supports D1 D2
10618 04:42:40.021162 <6>[ 13.928961] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10619 04:42:40.027590 <6>[ 13.930526] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10620 04:42:40.034116 <6>[ 13.930628] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10621 04:42:40.043932 <6>[ 13.930659] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10622 04:42:40.051084 <6>[ 13.930678] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10623 04:42:40.057363 <6>[ 13.930696] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10624 04:42:40.063864 <6>[ 13.930808] pci 0000:01:00.0: supports D1 D2
10625 04:42:40.070636 <6>[ 13.930811] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10626 04:42:40.077405 <6>[ 13.943510] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10627 04:42:40.083757 <6>[ 13.943556] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10628 04:42:40.094292 <6>[ 13.943564] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10629 04:42:40.100815 <6>[ 13.943578] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10630 04:42:40.106643 <6>[ 13.943595] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10631 04:42:40.117168 <6>[ 13.943612] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10632 04:42:40.120073 <6>[ 13.943629] pci 0000:00:00.0: PCI bridge to [bus 01]
10633 04:42:40.130008 <6>[ 13.943638] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10634 04:42:40.139617 <6>[ 13.943679] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10635 04:42:40.146526 <6>[ 13.943853] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10636 04:42:40.149830 <6>[ 13.945107] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10637 04:42:40.156292 <6>[ 13.945455] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10638 04:42:40.166437 <6>[ 13.964321] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10639 04:42:40.176068 <6>[ 13.964765] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10640 04:42:40.186106 <6>[ 13.979793] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10641 04:42:40.192649 <5>[ 13.988207] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10642 04:42:40.199385 <5>[ 13.998981] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10643 04:42:40.209300 <5>[ 13.999219] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10644 04:42:40.215582 <4>[ 13.999276] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10645 04:42:40.222093 <6>[ 13.999283] cfg80211: failed to load regulatory.db
10646 04:42:40.228772 <4>[ 14.008162] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10647 04:42:40.238779 <4>[ 14.008175] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10648 04:42:40.242200 <6>[ 14.023768] Bluetooth: Core ver 2.22
10649 04:42:40.248784 <6>[ 14.024263] NET: Registered PF_BLUETOOTH protocol family
10650 04:42:40.255246 <6>[ 14.024266] Bluetooth: HCI device and connection manager initialized
10651 04:42:40.258666 <6>[ 14.024294] Bluetooth: HCI socket layer initialized
10652 04:42:40.265281 <6>[ 14.024306] Bluetooth: L2CAP socket layer initialized
10653 04:42:40.268542 <6>[ 14.024318] Bluetooth: SCO socket layer initialized
10654 04:42:40.278801 <6>[ 14.041416] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10655 04:42:40.288884 <6>[ 14.042450] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10656 04:42:40.295465 <6>[ 14.042556] usbcore: registered new interface driver uvcvideo
10657 04:42:40.298299 <6>[ 14.052747] r8152 2-1.3:1.0 eth0: v1.12.13
10658 04:42:40.304813 <6>[ 14.052896] usbcore: registered new interface driver r8152
10659 04:42:40.311446 <6>[ 14.077474] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10660 04:42:40.318185 <6>[ 14.083758] usbcore: registered new interface driver cdc_ether
10661 04:42:40.324920 <6>[ 14.089025] usbcore: registered new interface driver btusb
10662 04:42:40.334766 <4>[ 14.090137] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10663 04:42:40.341268 <3>[ 14.090162] Bluetooth: hci0: Failed to load firmware file (-2)
10664 04:42:40.347529 <3>[ 14.090167] Bluetooth: hci0: Failed to set up firmware (-2)
10665 04:42:40.357846 <4>[ 14.090171] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10666 04:42:40.364206 <6>[ 14.095114] usbcore: registered new interface driver r8153_ecm
10667 04:42:40.367354 <6>[ 14.111243] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10668 04:42:40.377588 <6>[ 14.111941] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10669 04:42:40.384062 <6>[ 14.112047] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10670 04:42:40.387312 <6>[ 14.131567] mt7921e 0000:01:00.0: ASIC revision: 79610010
10671 04:42:40.397105 <6>[ 14.226927] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10672 04:42:40.397187 <6>[ 14.226927]
10673 04:42:40.400522 Begin: Loading essential drivers ... done.
10674 04:42:40.407447 Begin: Running /scripts/init-premount ... done.
10675 04:42:40.413816 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10676 04:42:40.427096 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for <6>[ 14.488523] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10677 04:42:40.430226 any ethernet to become available
10678 04:42:40.433901 Device /sys/class/net/enx002432307c7b found
10679 04:42:40.436410 done.
10680 04:42:40.486638 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10681 04:42:41.258810 <6>[ 15.324903] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10682 04:42:41.566360 <6>[ 15.635267] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10683 04:42:42.446639 IP-Config: no response after 2 secs - giving up
10684 04:42:42.486180 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10685 04:42:42.498617 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:a1 mtu 1500 DHCP
10686 04:42:43.199733 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10687 04:42:43.206277 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10688 04:42:43.213247 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10689 04:42:43.219187 host : mt8192-asurada-spherion-r0-cbg-2
10690 04:42:43.226035 domain : lava-rack
10691 04:42:43.232699 rootserver: 192.168.201.1 rootpath:
10692 04:42:43.232780 filename :
10693 04:42:43.317056 done.
10694 04:42:43.323864 Begin: Running /scripts/nfs-bottom ... done.
10695 04:42:43.347478 Begin: Running /scripts/init-bottom ... done.
10696 04:42:44.575133 <6>[ 18.640124] NET: Registered PF_INET6 protocol family
10697 04:42:44.578539 <6>[ 18.642433] Segment Routing with IPv6
10698 04:42:44.584941 <6>[ 18.642460] In-situ OAM (IOAM) with IPv6
10699 04:42:44.702323 <30>[ 18.748828] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10700 04:42:44.705468 <30>[ 18.749824] systemd[1]: Detected architecture arm64.
10701 04:42:44.705557
10702 04:42:44.711950 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10703 04:42:44.712032
10704 04:42:44.730618 <30>[ 18.797962] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10705 04:42:45.557432 <30>[ 19.621440] systemd[1]: Queued start job for default target Graphical Interface.
10706 04:42:45.581131 [[0;32m OK [<30>[ 19.645997] systemd[1]: Created slice system-getty.slice.
10707 04:42:45.584117 0m] Created slice [0;1;39msystem-getty.slice[0m.
10708 04:42:45.603349 [[0;32m OK [0m] Created slic<30>[ 19.668998] systemd[1]: Created slice system-modprobe.slice.
10709 04:42:45.606860 e [0;1;39msystem-modprobe.slice[0m.
10710 04:42:45.627167 [[0;32m OK [0m] Created slic<30>[ 19.692904] systemd[1]: Created slice system-serial\x2dgetty.slice.
10711 04:42:45.633579 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10712 04:42:45.652336 [[0;32m OK [0m] Created slic<30>[ 19.717506] systemd[1]: Created slice User and Session Slice.
10713 04:42:45.655398 e [0;1;39mUser and Session Slice[0m.
10714 04:42:45.678413 [[0;32m OK [0m] Started [0;<30>[ 19.740515] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10715 04:42:45.681786 1;39mDispatch Password …ts to Console Directory Watch[0m.
10716 04:42:45.706390 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 19.768441] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10717 04:42:45.709744 sword R…uests to Wall Directory Watch[0m.
10718 04:42:45.737378 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 19.796129] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10719 04:42:45.744481 <30>[ 19.796391] systemd[1]: Reached target Local Encrypted Volumes.
10720 04:42:45.747404 l Encrypted Volumes[0m.
10721 04:42:45.765835 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.831837] systemd[1]: Reached target Paths.
10722 04:42:45.766027 s[0m.
10723 04:42:45.789046 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.851677] systemd[1]: Reached target Remote File Systems.
10724 04:42:45.789230 te File Systems[0m.
10725 04:42:45.810112 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.875655] systemd[1]: Reached target Slices.
10726 04:42:45.810199 es[0m.
10727 04:42:45.830132 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.895686] systemd[1]: Reached target Swap.
10728 04:42:45.830218 [0m.
10729 04:42:45.853950 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.916140] systemd[1]: Listening on initctl Compatibility Named Pipe.
10730 04:42:45.856856 l Compatibility Named Pipe[0m.
10731 04:42:45.866880 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.932279] systemd[1]: Listening on Journal Audit Socket.
10732 04:42:45.870155 l Audit Socket[0m.
10733 04:42:45.890975 [[0;32m OK [0m] Listening on<30>[ 19.957042] systemd[1]: Listening on Journal Socket (/dev/log).
10734 04:42:45.894633 [0;1;39mJournal Socket (/dev/log)[0m.
10735 04:42:45.914729 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.980273] systemd[1]: Listening on Journal Socket.
10736 04:42:45.917386 l Socket[0m.
10737 04:42:45.935843 [[0;32m OK [0m] Listening on<30>[ 20.001181] systemd[1]: Listening on Network Service Netlink Socket.
10738 04:42:45.941883 [0;1;39mNetwork Service Netlink Socket[0m.
10739 04:42:45.961951 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 20.027662] systemd[1]: Listening on udev Control Socket.
10740 04:42:45.965390 ontrol Socket[0m.
10741 04:42:45.983089 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 20.048149] systemd[1]: Listening on udev Kernel Socket.
10742 04:42:45.987507 ernel Socket[0m.
10743 04:42:46.033200 Mounting [0;1;39mHuge Pages File Syste<30>[ 20.095817] systemd[1]: Mounting Huge Pages File System...
10744 04:42:46.033299 m[0m...
10745 04:42:46.056946 Mounting [0;1;39mPOSIX Message Queue F<30>[ 20.119700] systemd[1]: Mounting POSIX Message Queue File System...
10746 04:42:46.057042 ile System[0m...
10747 04:42:46.117638 Mounting [0;1;39mKernel Debug File Sys<30>[ 20.180114] systemd[1]: Mounting Kernel Debug File System...
10748 04:42:46.117757 tem[0m...
10749 04:42:46.138234 <30>[ 20.200105] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10750 04:42:46.155685 Startin<30>[ 20.217839] systemd[1]: Starting Create list of static device nodes for the current kernel...
10751 04:42:46.158646 g [0;1;39mCreate list of st…odes for the current kernel[0m...
10752 04:42:46.185458 Starting [0;1;39mLoad Kernel Module co<30>[ 20.247680] systemd[1]: Starting Load Kernel Module configfs...
10753 04:42:46.185560 nfigfs[0m...
10754 04:42:46.206707 Starting [0;1;39mLoad <30>[ 20.272542] systemd[1]: Starting Load Kernel Module drm...
10755 04:42:46.210236 Kernel Module drm[0m...
10756 04:42:46.231197 Starting [0;1;39mLoad <30>[ 20.296954] systemd[1]: Starting Load Kernel Module fuse...
10757 04:42:46.234419 Kernel Module fuse[0m...
10758 04:42:46.261310 <30>[ 20.326523] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10759 04:42:46.274863 Starting [0;1;39mJourn<30>[ 20.340823] systemd[1]: Starting Journal Service...
10760 04:42:46.274965 al Service[0m...
10761 04:42:46.282030 <6>[ 20.349851] fuse: init (API version 7.37)
10762 04:42:46.303923 Starting [0;1;39mLoad <30>[ 20.369758] systemd[1]: Starting Load Kernel Modules...
10763 04:42:46.307394 Kernel Modules[0m...
10764 04:42:46.331266 Starting [0;1;39mRemou<30>[ 20.396852] systemd[1]: Starting Remount Root and Kernel File Systems...
10765 04:42:46.337961 nt Root and Kernel File Systems[0m...
10766 04:42:46.358566 Starting [0;1;39mColdp<30>[ 20.424131] systemd[1]: Starting Coldplug All udev Devices...
10767 04:42:46.361895 lug All udev Devices[0m...
10768 04:42:46.384087 [[0;32m OK [0m] Mounted [0;<30>[ 20.449573] systemd[1]: Mounted Huge Pages File System.
10769 04:42:46.387213 1;39mHuge Pages File System[0m.
10770 04:42:46.405388 <3>[ 20.471359] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10771 04:42:46.416092 [[0;32m OK [0m] Mounted [0;<30>[ 20.481127] systemd[1]: Mounted POSIX Message Queue File System.
10772 04:42:46.419061 1;39mPOSIX Message Queue File System[0m.
10773 04:42:46.429150 <3>[ 20.492379] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10774 04:42:46.439062 [[0;32m OK [0m] Mounted [0;<30>[ 20.505048] systemd[1]: Mounted Kernel Debug File System.
10775 04:42:46.442372 1;39mKernel Debug File System[0m.
10776 04:42:46.467190 [[0;32m OK [0m] Finished [0<30>[ 20.529577] systemd[1]: Finished Create list of static device nodes for the current kernel.
10777 04:42:46.477904 ;1;39mCreate lis<3>[ 20.532684] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10778 04:42:46.480247 t of st… nodes for the current kernel[0m.
10779 04:42:46.501504 <3>[ 20.566836] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10780 04:42:46.510186 <30>[ 20.578437] systemd[1]: modprobe@configfs.service: Succeeded.
10781 04:42:46.516722 <30>[ 20.580057] systemd[1]: Finished Load Kernel Module configfs.
10782 04:42:46.523565 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10783 04:42:46.533734 <3>[ 20.596290] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10784 04:42:46.544509 [[0;32m OK [0m] Finished [0<30>[ 20.609160] systemd[1]: modprobe@drm.service: Succeeded.
10785 04:42:46.550741 ;1;39mLoad Kerne<30>[ 20.609740] systemd[1]: Finished Load Kernel Module drm.
10786 04:42:46.561170 l Module drm[0m<3>[ 20.616345] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10787 04:42:46.561278 .
10788 04:42:46.573246 <3>[ 20.638242] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10789 04:42:46.584344 [[0;32m OK [0m] Finished [0<30>[ 20.649131] systemd[1]: modprobe@fuse.service: Succeeded.
10790 04:42:46.590980 ;1;39mLoad Kerne<30>[ 20.649716] systemd[1]: Finished Load Kernel Module fuse.
10791 04:42:46.601196 l Module fuse[0<3>[ 20.658247] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10792 04:42:46.601279 m.
10793 04:42:46.617889 <3>[ 20.680089] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10794 04:42:46.628554 [[0;32m OK [0m] Finished [0<30>[ 20.693912] systemd[1]: Finished Load Kernel Modules.
10795 04:42:46.638956 ;1;39mLoad Kerne<3>[ 20.700658] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10796 04:42:46.639110 l Modules[0m.
10797 04:42:46.659800 [[0;32m OK [0m] Finished [0<30>[ 20.725588] systemd[1]: Finished Remount Root and Kernel File Systems.
10798 04:42:46.666885 ;1;39mRemount Root and Kernel File Systems[0m.
10799 04:42:46.687903 [[0;32m OK [0m] Started [0;<30>[ 20.752987] systemd[1]: Started Journal Service.
10800 04:42:46.690747 1;39mJournal Service[0m.
10801 04:42:46.750931 Mounting [0;1;39mFUSE Control File System[0m...
10802 04:42:46.769691 Mounting [0;1;39mKernel Configuration File System[0m...
10803 04:42:46.796101 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10804 04:42:46.816236 Starting [0;1;39mLoad/Save Random Seed[0m...
10805 04:42:46.837398 Starting [0;1;39mApply Kernel Variables[0m...
10806 04:42:46.857166 <46>[ 20.919494] systemd-journald[307]: Received client request to flush runtime journal.
10807 04:42:46.860960 Starting [0;1;39mCreate System Users[0m...
10808 04:42:46.880993 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10809 04:42:46.899628 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10810 04:42:46.923909 <4>[ 20.980360] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10811 04:42:46.933921 <3>[ 20.980376] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10812 04:42:46.937491 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10813 04:42:46.965250 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10814 04:42:46.978865 See 'systemctl status systemd-udev-trigger.service' for details.
10815 04:42:46.996570 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10816 04:42:48.280987 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10817 04:42:48.306885 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10818 04:42:48.354999 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10819 04:42:48.448754 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10820 04:42:48.462832 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10821 04:42:48.478440 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10822 04:42:48.542673 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10823 04:42:48.570474 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10824 04:42:48.772624 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10825 04:42:48.828456 Starting [0;1;39mNetwork Service[0m...
10826 04:42:48.946655 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10827 04:42:49.163512 Starting [0;1;39mNetwork Time Synchronization[0m...
10828 04:42:49.237410 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10829 04:42:49.351867 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10830 04:42:49.488593 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10831 04:42:49.502335 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10832 04:42:49.521676 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10833 04:42:49.574369 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10834 04:42:49.594913 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10835 04:42:49.687764 Starting [0;1;39mNetwork Name Resolution[0m...
10836 04:42:49.712377 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10837 04:42:49.745408 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10838 04:42:49.763790 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10839 04:42:49.783372 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10840 04:42:49.807058 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10841 04:42:49.832205 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10842 04:42:49.857567 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10843 04:42:49.874711 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10844 04:42:49.890365 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10845 04:42:50.607943 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10846 04:42:50.934404 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10847 04:42:50.968923 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10848 04:42:50.991352 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10849 04:42:51.005909 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10850 04:42:51.054514 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10851 04:42:51.065831 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10852 04:42:51.082329 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10853 04:42:51.134775 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10854 04:42:51.246088 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10855 04:42:51.338916 Starting [0;1;39mUser Login Management[0m...
10856 04:42:51.380234 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10857 04:42:51.399219 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10858 04:42:51.417857 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10859 04:42:51.474644 Starting [0;1;39mPermit User Sessions[0m...
10860 04:42:51.626294 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10861 04:42:51.647420 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10862 04:42:51.702851 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10863 04:42:51.722861 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10864 04:42:51.742556 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10865 04:42:51.762322 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10866 04:42:51.780548 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10867 04:42:51.798411 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10868 04:42:51.855707 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10869 04:42:51.937210 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10870 04:42:52.001978
10871 04:42:52.002109
10872 04:42:52.005083 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10873 04:42:52.005167
10874 04:42:52.008195 debian-bullseye-arm64 login: root (automatic login)
10875 04:42:52.008271
10876 04:42:52.008332
10877 04:42:52.345202 Linux debian-bullseye-arm64 6.1.75-cip14-rt8 #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024 aarch64
10878 04:42:52.345334
10879 04:42:52.352226 The programs included with the Debian GNU/Linux system are free software;
10880 04:42:52.358328 the exact distribution terms for each program are described in the
10881 04:42:52.361309 individual files in /usr/share/doc/*/copyright.
10882 04:42:52.361412
10883 04:42:52.368145 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10884 04:42:52.371497 permitted by applicable law.
10885 04:42:52.473012 Matched prompt #10: / #
10887 04:42:52.473287 Setting prompt string to ['/ #']
10888 04:42:52.473382 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10890 04:42:52.473577 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10891 04:42:52.473667 start: 2.2.6 expect-shell-connection (timeout 00:03:11) [common]
10892 04:42:52.473740 Setting prompt string to ['/ #']
10893 04:42:52.473799 Forcing a shell prompt, looking for ['/ #']
10895 04:42:52.524018 / #
10896 04:42:52.524148 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10897 04:42:52.524250 Waiting using forced prompt support (timeout 00:02:30)
10898 04:42:52.529577
10899 04:42:52.529851 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10900 04:42:52.529946 start: 2.2.7 export-device-env (timeout 00:03:11) [common]
10902 04:42:52.630266 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12699805/extract-nfsrootfs-yh0oczb8'
10903 04:42:52.635174 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12699805/extract-nfsrootfs-yh0oczb8'
10905 04:42:52.735821 / # export NFS_SERVER_IP='192.168.201.1'
10906 04:42:52.742120 export NFS_SERVER_IP='192.168.201.1'
10907 04:42:52.742643 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10908 04:42:52.742915 end: 2.2 depthcharge-retry (duration 00:01:49) [common]
10909 04:42:52.743167 end: 2 depthcharge-action (duration 00:01:49) [common]
10910 04:42:52.743451 start: 3 lava-test-retry (timeout 00:01:00) [common]
10911 04:42:52.743707 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10912 04:42:52.743933 Using namespace: common
10914 04:42:52.844657 / # #
10915 04:42:52.845212 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10916 04:42:52.851128 #
10917 04:42:52.851871 Using /lava-12699805
10919 04:42:52.952777 / # export SHELL=/bin/sh
10920 04:42:52.958808 export SHELL=/bin/sh
10922 04:42:53.059330 / # . /lava-12699805/environment
10923 04:42:53.064516 . /lava-12699805/environment
10925 04:42:53.170257 / # /lava-12699805/bin/lava-test-runner /lava-12699805/0
10926 04:42:53.170412 Test shell timeout: 10s (minimum of the action and connection timeout)
10927 04:42:53.175995 /lava-12699805/bin/lava-test-runner /lava-12699805/0
10928 04:42:53.436220 + export TESTRUN_ID=0_dmesg
10929 04:42:53.439564 + cd /lava-12699805/0/tests/0_dmesg
10930 04:42:53.442590 + cat uuid
10931 04:42:53.450408 + UUID=12699805_1.6.2.3.1
10932 04:42:53.450491 + set +x
10933 04:42:53.459994 + KERNELCI_<8>[ 27.523818] <LAVA_SIGNAL_STARTRUN 0_dmesg 12699805_1.6.2.3.1>
10934 04:42:53.460260 Received signal: <STARTRUN> 0_dmesg 12699805_1.6.2.3.1
10935 04:42:53.460334 Starting test lava.0_dmesg (12699805_1.6.2.3.1)
10936 04:42:53.460421 Skipping test definition patterns.
10937 04:42:53.463096 LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10938 04:42:53.564515 <8>[ 27.627665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10939 04:42:53.564817 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10941 04:42:53.636597 <8>[ 27.702138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10942 04:42:53.636902 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10944 04:42:53.711798 + set +x
10945 04:42:53.720999 <8>[ 27.783917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10946 04:42:53.721278 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10948 04:42:53.727898 <LAVA_TEST_RUNNE<8>[ 27.784809] <LAVA_SIGNAL_ENDRUN 0_dmesg 12699805_1.6.2.3.1>
10949 04:42:53.727999 R EXIT>
10950 04:42:53.728256 Received signal: <ENDRUN> 0_dmesg 12699805_1.6.2.3.1
10951 04:42:53.728356 Ending use of test pattern.
10952 04:42:53.728431 Ending test lava.0_dmesg (12699805_1.6.2.3.1), duration 0.27
10954 04:43:09.960574 / # <6>[ 44.031809] vpu: disabling
10955 04:43:09.963372 <6>[ 44.031940] vproc2: disabling
10956 04:43:09.966722 <6>[ 44.032000] vproc1: disabling
10957 04:43:09.969981 <6>[ 44.032055] vaud18: disabling
10958 04:43:09.973530 <6>[ 44.032306] vsram_others: disabling
10959 04:43:09.976861 <6>[ 44.032485] va09: disabling
10960 04:43:09.980187 <6>[ 44.032562] vsram_md: disabling
10961 04:43:09.983268 <6>[ 44.032692] Vgpu: disabling
10963 04:43:52.743987 end: 3.1 lava-test-shell (duration 00:01:00) [common]
10965 04:43:52.744173 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
10967 04:43:52.744319 end: 3 lava-test-retry (duration 00:01:00) [common]
10969 04:43:52.744524 Cleaning after the job
10970 04:43:52.744610 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/ramdisk
10971 04:43:52.747107 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/kernel
10972 04:43:52.759977 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/dtb
10973 04:43:52.760147 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/nfsrootfs
10974 04:43:52.831874 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699805/tftp-deploy-ft8eg3xo/modules
10975 04:43:52.838785 start: 5.1 power-off (timeout 00:00:30) [common]
10976 04:43:52.838998 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
10977 04:43:52.915277 >> Command sent successfully.
10978 04:43:52.917926 Returned 0 in 0 seconds
10979 04:43:53.018334 end: 5.1 power-off (duration 00:00:00) [common]
10981 04:43:53.018663 start: 5.2 read-feedback (timeout 00:10:00) [common]
10982 04:43:53.018929 Listened to connection for namespace 'common' for up to 1s
10983 04:43:54.019468 Finalising connection for namespace 'common'
10984 04:43:54.019635 Disconnecting from shell: Finalise
10985 04:43:54.119969 end: 5.2 read-feedback (duration 00:00:01) [common]
10986 04:43:54.120115 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12699805
10987 04:43:54.490760 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12699805
10988 04:43:54.490940 TestError: A test failed to run, look at the error message.