Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 10
- Kernel Errors: 27
1 04:40:07.360888 lava-dispatcher, installed at version: 2023.10
2 04:40:07.361104 start: 0 validate
3 04:40:07.361234 Start time: 2024-02-04 04:40:07.361226+00:00 (UTC)
4 04:40:07.361345 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:40:07.361474 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 04:40:07.633666 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:40:07.634410 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:40:43.449843 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:40:43.450576 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:40:43.720032 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:40:43.720848 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 04:40:49.988381 validate duration: 42.63
14 04:40:49.988641 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:40:49.988768 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:40:49.988884 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:40:49.989008 Not decompressing ramdisk as can be used compressed.
18 04:40:49.989095 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 04:40:49.989161 saving as /var/lib/lava/dispatcher/tmp/12699794/tftp-deploy-cfipo1j7/ramdisk/rootfs.cpio.gz
20 04:40:49.989224 total size: 34390042 (32 MB)
21 04:40:50.257587 progress 0 % (0 MB)
22 04:40:50.271947 progress 5 % (1 MB)
23 04:40:50.286605 progress 10 % (3 MB)
24 04:40:50.301419 progress 15 % (4 MB)
25 04:40:50.315775 progress 20 % (6 MB)
26 04:40:50.330676 progress 25 % (8 MB)
27 04:40:50.344961 progress 30 % (9 MB)
28 04:40:50.354914 progress 35 % (11 MB)
29 04:40:50.364288 progress 40 % (13 MB)
30 04:40:50.373935 progress 45 % (14 MB)
31 04:40:50.383278 progress 50 % (16 MB)
32 04:40:50.392964 progress 55 % (18 MB)
33 04:40:50.402400 progress 60 % (19 MB)
34 04:40:50.412004 progress 65 % (21 MB)
35 04:40:50.421186 progress 70 % (22 MB)
36 04:40:50.430745 progress 75 % (24 MB)
37 04:40:50.440355 progress 80 % (26 MB)
38 04:40:50.449946 progress 85 % (27 MB)
39 04:40:50.459042 progress 90 % (29 MB)
40 04:40:50.468339 progress 95 % (31 MB)
41 04:40:50.477623 progress 100 % (32 MB)
42 04:40:50.477957 32 MB downloaded in 0.49 s (67.11 MB/s)
43 04:40:50.478172 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:40:50.478433 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:40:50.478519 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:40:50.478603 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:40:50.478745 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 04:40:50.478820 saving as /var/lib/lava/dispatcher/tmp/12699794/tftp-deploy-cfipo1j7/kernel/Image
50 04:40:50.478882 total size: 51597824 (49 MB)
51 04:40:50.478945 No compression specified
52 04:40:50.480168 progress 0 % (0 MB)
53 04:40:50.494699 progress 5 % (2 MB)
54 04:40:50.508932 progress 10 % (4 MB)
55 04:40:50.522943 progress 15 % (7 MB)
56 04:40:50.536812 progress 20 % (9 MB)
57 04:40:50.550703 progress 25 % (12 MB)
58 04:40:50.564545 progress 30 % (14 MB)
59 04:40:50.579832 progress 35 % (17 MB)
60 04:40:50.594741 progress 40 % (19 MB)
61 04:40:50.609743 progress 45 % (22 MB)
62 04:40:50.624462 progress 50 % (24 MB)
63 04:40:50.639914 progress 55 % (27 MB)
64 04:40:50.654198 progress 60 % (29 MB)
65 04:40:50.668735 progress 65 % (32 MB)
66 04:40:50.683149 progress 70 % (34 MB)
67 04:40:50.697749 progress 75 % (36 MB)
68 04:40:50.712957 progress 80 % (39 MB)
69 04:40:50.727883 progress 85 % (41 MB)
70 04:40:50.742476 progress 90 % (44 MB)
71 04:40:50.756795 progress 95 % (46 MB)
72 04:40:50.771136 progress 100 % (49 MB)
73 04:40:50.771410 49 MB downloaded in 0.29 s (168.22 MB/s)
74 04:40:50.771570 end: 1.2.1 http-download (duration 00:00:00) [common]
76 04:40:50.771804 end: 1.2 download-retry (duration 00:00:00) [common]
77 04:40:50.771905 start: 1.3 download-retry (timeout 00:09:59) [common]
78 04:40:50.771995 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 04:40:50.772138 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 04:40:50.772213 saving as /var/lib/lava/dispatcher/tmp/12699794/tftp-deploy-cfipo1j7/dtb/mt8192-asurada-spherion-r0.dtb
81 04:40:50.772284 total size: 47278 (0 MB)
82 04:40:50.772384 No compression specified
83 04:40:50.773604 progress 69 % (0 MB)
84 04:40:50.773894 progress 100 % (0 MB)
85 04:40:50.774053 0 MB downloaded in 0.00 s (25.50 MB/s)
86 04:40:50.774231 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:40:50.774485 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:40:50.774577 start: 1.4 download-retry (timeout 00:09:59) [common]
90 04:40:50.774661 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 04:40:50.774788 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 04:40:50.774862 saving as /var/lib/lava/dispatcher/tmp/12699794/tftp-deploy-cfipo1j7/modules/modules.tar
93 04:40:50.774927 total size: 8633524 (8 MB)
94 04:40:50.774994 Using unxz to decompress xz
95 04:40:50.779660 progress 0 % (0 MB)
96 04:40:50.801460 progress 5 % (0 MB)
97 04:40:50.825791 progress 10 % (0 MB)
98 04:40:50.850440 progress 15 % (1 MB)
99 04:40:50.874809 progress 20 % (1 MB)
100 04:40:50.900780 progress 25 % (2 MB)
101 04:40:50.929452 progress 30 % (2 MB)
102 04:40:50.954247 progress 35 % (2 MB)
103 04:40:50.978086 progress 40 % (3 MB)
104 04:40:51.003964 progress 45 % (3 MB)
105 04:40:51.029895 progress 50 % (4 MB)
106 04:40:51.054646 progress 55 % (4 MB)
107 04:40:51.082067 progress 60 % (4 MB)
108 04:40:51.109665 progress 65 % (5 MB)
109 04:40:51.136662 progress 70 % (5 MB)
110 04:40:51.161834 progress 75 % (6 MB)
111 04:40:51.190890 progress 80 % (6 MB)
112 04:40:51.217073 progress 85 % (7 MB)
113 04:40:51.244113 progress 90 % (7 MB)
114 04:40:51.273882 progress 95 % (7 MB)
115 04:40:51.302521 progress 100 % (8 MB)
116 04:40:51.307985 8 MB downloaded in 0.53 s (15.45 MB/s)
117 04:40:51.308243 end: 1.4.1 http-download (duration 00:00:01) [common]
119 04:40:51.308510 end: 1.4 download-retry (duration 00:00:01) [common]
120 04:40:51.308604 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 04:40:51.308697 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 04:40:51.308826 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:40:51.308912 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 04:40:51.309121 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi
125 04:40:51.309258 makedir: /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin
126 04:40:51.309365 makedir: /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/tests
127 04:40:51.309466 makedir: /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/results
128 04:40:51.309582 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-add-keys
129 04:40:51.309731 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-add-sources
130 04:40:51.309862 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-background-process-start
131 04:40:51.309994 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-background-process-stop
132 04:40:51.310122 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-common-functions
133 04:40:51.310250 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-echo-ipv4
134 04:40:51.310455 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-install-packages
135 04:40:51.310588 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-installed-packages
136 04:40:51.310716 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-os-build
137 04:40:51.310843 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-probe-channel
138 04:40:51.310970 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-probe-ip
139 04:40:51.311096 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-target-ip
140 04:40:51.311221 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-target-mac
141 04:40:51.311346 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-target-storage
142 04:40:51.311475 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-test-case
143 04:40:51.311603 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-test-event
144 04:40:51.311729 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-test-feedback
145 04:40:51.311854 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-test-raise
146 04:40:51.311982 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-test-reference
147 04:40:51.312108 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-test-runner
148 04:40:51.312234 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-test-set
149 04:40:51.312366 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-test-shell
150 04:40:51.312496 Updating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-install-packages (oe)
151 04:40:51.312647 Updating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/bin/lava-installed-packages (oe)
152 04:40:51.312813 Creating /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/environment
153 04:40:51.312915 LAVA metadata
154 04:40:51.312987 - LAVA_JOB_ID=12699794
155 04:40:51.313052 - LAVA_DISPATCHER_IP=192.168.201.1
156 04:40:51.313154 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 04:40:51.313221 skipped lava-vland-overlay
158 04:40:51.313294 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 04:40:51.313371 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 04:40:51.313437 skipped lava-multinode-overlay
161 04:40:51.313524 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 04:40:51.313612 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 04:40:51.313689 Loading test definitions
164 04:40:51.313780 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 04:40:51.313856 Using /lava-12699794 at stage 0
166 04:40:51.314160 uuid=12699794_1.5.2.3.1 testdef=None
167 04:40:51.314247 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 04:40:51.314335 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 04:40:51.314854 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 04:40:51.315083 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 04:40:51.315730 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 04:40:51.315957 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 04:40:51.316568 runner path: /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/0/tests/0_cros-ec test_uuid 12699794_1.5.2.3.1
176 04:40:51.316744 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 04:40:51.316960 Creating lava-test-runner.conf files
179 04:40:51.317021 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12699794/lava-overlay-91pmi9oi/lava-12699794/0 for stage 0
180 04:40:51.317111 - 0_cros-ec
181 04:40:51.317231 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 04:40:51.317331 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 04:40:51.324070 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 04:40:51.324181 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 04:40:51.324266 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 04:40:51.324353 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 04:40:51.324443 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 04:40:52.336658 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 04:40:52.337191 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 04:40:52.337358 extracting modules file /var/lib/lava/dispatcher/tmp/12699794/tftp-deploy-cfipo1j7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699794/extract-overlay-ramdisk-j01d3res/ramdisk
191 04:40:52.583449 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 04:40:52.583624 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 04:40:52.583719 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699794/compress-overlay-eblmdle5/overlay-1.5.2.4.tar.gz to ramdisk
194 04:40:52.583790 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699794/compress-overlay-eblmdle5/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12699794/extract-overlay-ramdisk-j01d3res/ramdisk
195 04:40:52.590883 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 04:40:52.591017 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 04:40:52.591107 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 04:40:52.591196 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 04:40:52.591308 Building ramdisk /var/lib/lava/dispatcher/tmp/12699794/extract-overlay-ramdisk-j01d3res/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12699794/extract-overlay-ramdisk-j01d3res/ramdisk
200 04:40:53.331699 >> 271105 blocks
201 04:40:58.055153 rename /var/lib/lava/dispatcher/tmp/12699794/extract-overlay-ramdisk-j01d3res/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12699794/tftp-deploy-cfipo1j7/ramdisk/ramdisk.cpio.gz
202 04:40:58.055742 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 04:40:58.055915 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 04:40:58.056060 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 04:40:58.056210 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12699794/tftp-deploy-cfipo1j7/kernel/Image'
206 04:41:11.598001 Returned 0 in 13 seconds
207 04:41:11.698747 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12699794/tftp-deploy-cfipo1j7/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12699794/tftp-deploy-cfipo1j7/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12699794/tftp-deploy-cfipo1j7/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12699794/tftp-deploy-cfipo1j7/kernel/image.itb
208 04:41:12.463361 output: FIT description: Kernel Image image with one or more FDT blobs
209 04:41:12.463746 output: Created: Sun Feb 4 04:41:12 2024
210 04:41:12.463820 output: Image 0 (kernel-1)
211 04:41:12.463887 output: Description:
212 04:41:12.463948 output: Created: Sun Feb 4 04:41:12 2024
213 04:41:12.464005 output: Type: Kernel Image
214 04:41:12.464065 output: Compression: lzma compressed
215 04:41:12.464123 output: Data Size: 12048508 Bytes = 11766.12 KiB = 11.49 MiB
216 04:41:12.464181 output: Architecture: AArch64
217 04:41:12.464238 output: OS: Linux
218 04:41:12.464296 output: Load Address: 0x00000000
219 04:41:12.464352 output: Entry Point: 0x00000000
220 04:41:12.464406 output: Hash algo: crc32
221 04:41:12.464460 output: Hash value: 3b31d50c
222 04:41:12.464517 output: Image 1 (fdt-1)
223 04:41:12.464572 output: Description: mt8192-asurada-spherion-r0
224 04:41:12.464623 output: Created: Sun Feb 4 04:41:12 2024
225 04:41:12.464675 output: Type: Flat Device Tree
226 04:41:12.464742 output: Compression: uncompressed
227 04:41:12.464796 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 04:41:12.464847 output: Architecture: AArch64
229 04:41:12.464899 output: Hash algo: crc32
230 04:41:12.464950 output: Hash value: cc4352de
231 04:41:12.465003 output: Image 2 (ramdisk-1)
232 04:41:12.465054 output: Description: unavailable
233 04:41:12.465106 output: Created: Sun Feb 4 04:41:12 2024
234 04:41:12.465158 output: Type: RAMDisk Image
235 04:41:12.465209 output: Compression: Unknown Compression
236 04:41:12.465260 output: Data Size: 47542515 Bytes = 46428.24 KiB = 45.34 MiB
237 04:41:12.465311 output: Architecture: AArch64
238 04:41:12.465362 output: OS: Linux
239 04:41:12.465414 output: Load Address: unavailable
240 04:41:12.465464 output: Entry Point: unavailable
241 04:41:12.465514 output: Hash algo: crc32
242 04:41:12.465566 output: Hash value: 6aad26b0
243 04:41:12.465617 output: Default Configuration: 'conf-1'
244 04:41:12.465668 output: Configuration 0 (conf-1)
245 04:41:12.465719 output: Description: mt8192-asurada-spherion-r0
246 04:41:12.465770 output: Kernel: kernel-1
247 04:41:12.465822 output: Init Ramdisk: ramdisk-1
248 04:41:12.465873 output: FDT: fdt-1
249 04:41:12.465924 output: Loadables: kernel-1
250 04:41:12.465975 output:
251 04:41:12.466170 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 04:41:12.466269 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 04:41:12.466379 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 04:41:12.466473 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 04:41:12.466558 No LXC device requested
256 04:41:12.466638 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 04:41:12.466721 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 04:41:12.466796 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 04:41:12.466863 Checking files for TFTP limit of 4294967296 bytes.
260 04:41:12.467367 end: 1 tftp-deploy (duration 00:00:22) [common]
261 04:41:12.467471 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 04:41:12.467563 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 04:41:12.467682 substitutions:
264 04:41:12.467748 - {DTB}: 12699794/tftp-deploy-cfipo1j7/dtb/mt8192-asurada-spherion-r0.dtb
265 04:41:12.467811 - {INITRD}: 12699794/tftp-deploy-cfipo1j7/ramdisk/ramdisk.cpio.gz
266 04:41:12.467869 - {KERNEL}: 12699794/tftp-deploy-cfipo1j7/kernel/Image
267 04:41:12.467924 - {LAVA_MAC}: None
268 04:41:12.467978 - {PRESEED_CONFIG}: None
269 04:41:12.468032 - {PRESEED_LOCAL}: None
270 04:41:12.468085 - {RAMDISK}: 12699794/tftp-deploy-cfipo1j7/ramdisk/ramdisk.cpio.gz
271 04:41:12.468138 - {ROOT_PART}: None
272 04:41:12.468191 - {ROOT}: None
273 04:41:12.468244 - {SERVER_IP}: 192.168.201.1
274 04:41:12.468296 - {TEE}: None
275 04:41:12.468348 Parsed boot commands:
276 04:41:12.468402 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 04:41:12.468587 Parsed boot commands: tftpboot 192.168.201.1 12699794/tftp-deploy-cfipo1j7/kernel/image.itb 12699794/tftp-deploy-cfipo1j7/kernel/cmdline
278 04:41:12.468672 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 04:41:12.468762 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 04:41:12.468855 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 04:41:12.468940 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 04:41:12.469008 Not connected, no need to disconnect.
283 04:41:12.469079 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 04:41:12.469156 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 04:41:12.469221 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 04:41:12.473404 Setting prompt string to ['lava-test: # ']
287 04:41:12.473785 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 04:41:12.473894 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 04:41:12.474016 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 04:41:12.474140 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 04:41:12.474382 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 04:41:17.603980 >> Command sent successfully.
293 04:41:17.607116 Returned 0 in 5 seconds
294 04:41:17.707503 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 04:41:17.707823 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 04:41:17.707928 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 04:41:17.708019 Setting prompt string to 'Starting depthcharge on Spherion...'
299 04:41:17.708098 Changing prompt to 'Starting depthcharge on Spherion...'
300 04:41:17.708165 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 04:41:17.708443 [Enter `^Ec?' for help]
302 04:41:17.891776
303 04:41:17.891921
304 04:41:17.891990 F0: 102B 0000
305 04:41:17.892054
306 04:41:17.895719 F3: 1001 0000 [0200]
307 04:41:17.895806
308 04:41:17.895871 F3: 1001 0000
309 04:41:17.895932
310 04:41:17.895989 F7: 102D 0000
311 04:41:17.896046
312 04:41:17.898695 F1: 0000 0000
313 04:41:17.898779
314 04:41:17.898844 V0: 0000 0000 [0001]
315 04:41:17.898904
316 04:41:17.898961 00: 0007 8000
317 04:41:17.899024
318 04:41:17.902225 01: 0000 0000
319 04:41:17.902308
320 04:41:17.902376 BP: 0C00 0209 [0000]
321 04:41:17.902458
322 04:41:17.905859 G0: 1182 0000
323 04:41:17.905942
324 04:41:17.906008 EC: 0000 0021 [4000]
325 04:41:17.906068
326 04:41:17.909403 S7: 0000 0000 [0000]
327 04:41:17.909486
328 04:41:17.909551 CC: 0000 0000 [0001]
329 04:41:17.909612
330 04:41:17.913727 T0: 0000 0040 [010F]
331 04:41:17.913819
332 04:41:17.913917 Jump to BL
333 04:41:17.913979
334 04:41:17.938379
335 04:41:17.938502
336 04:41:17.938576
337 04:41:17.945359 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 04:41:17.949438 ARM64: Exception handlers installed.
339 04:41:17.951761 ARM64: Testing exception
340 04:41:17.955684 ARM64: Done test exception
341 04:41:17.962146 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 04:41:17.971798 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 04:41:17.979026 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 04:41:17.989491 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 04:41:17.996278 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 04:41:18.006311 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 04:41:18.016827 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 04:41:18.023110 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 04:41:18.041338 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 04:41:18.044417 WDT: Last reset was cold boot
351 04:41:18.047675 SPI1(PAD0) initialized at 2873684 Hz
352 04:41:18.051269 SPI5(PAD0) initialized at 992727 Hz
353 04:41:18.054360 VBOOT: Loading verstage.
354 04:41:18.061748 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 04:41:18.065044 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 04:41:18.067870 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 04:41:18.071103 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 04:41:18.078669 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 04:41:18.085461 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 04:41:18.096206 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 04:41:18.096301
362 04:41:18.096369
363 04:41:18.106357 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 04:41:18.109692 ARM64: Exception handlers installed.
365 04:41:18.112455 ARM64: Testing exception
366 04:41:18.115927 ARM64: Done test exception
367 04:41:18.119219 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 04:41:18.122438 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 04:41:18.137322 Probing TPM: . done!
370 04:41:18.137423 TPM ready after 0 ms
371 04:41:18.143847 Connected to device vid:did:rid of 1ae0:0028:00
372 04:41:18.153944 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 04:41:18.193349 Initialized TPM device CR50 revision 0
374 04:41:18.204805 tlcl_send_startup: Startup return code is 0
375 04:41:18.204925 TPM: setup succeeded
376 04:41:18.216824 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 04:41:18.225977 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 04:41:18.235366 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 04:41:18.244412 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 04:41:18.247830 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 04:41:18.251058 in-header: 03 07 00 00 08 00 00 00
382 04:41:18.254737 in-data: aa e4 47 04 13 02 00 00
383 04:41:18.257794 Chrome EC: UHEPI supported
384 04:41:18.264800 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 04:41:18.267736 in-header: 03 9d 00 00 08 00 00 00
386 04:41:18.270758 in-data: 10 20 20 08 00 00 00 00
387 04:41:18.270845 Phase 1
388 04:41:18.274265 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 04:41:18.280931 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 04:41:18.287246 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 04:41:18.290850 Recovery requested (1009000e)
392 04:41:18.294733 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 04:41:18.302959 tlcl_extend: response is 0
394 04:41:18.311215 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 04:41:18.316291 tlcl_extend: response is 0
396 04:41:18.323274 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 04:41:18.343799 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 04:41:18.351051 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 04:41:18.351156
400 04:41:18.351243
401 04:41:18.360550 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 04:41:18.363645 ARM64: Exception handlers installed.
403 04:41:18.366797 ARM64: Testing exception
404 04:41:18.366877 ARM64: Done test exception
405 04:41:18.390251 pmic_efuse_setting: Set efuses in 11 msecs
406 04:41:18.394003 pmwrap_interface_init: Select PMIF_VLD_RDY
407 04:41:18.399797 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 04:41:18.403374 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 04:41:18.406783 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 04:41:18.414418 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 04:41:18.417967 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 04:41:18.421318 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 04:41:18.428874 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 04:41:18.431664 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 04:41:18.438954 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 04:41:18.441540 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 04:41:18.445322 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 04:41:18.451777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 04:41:18.454873 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 04:41:18.461635 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 04:41:18.468453 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 04:41:18.472444 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 04:41:18.478757 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 04:41:18.485974 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 04:41:18.489671 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 04:41:18.495930 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 04:41:18.499854 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 04:41:18.506119 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 04:41:18.512863 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 04:41:18.516127 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 04:41:18.523345 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 04:41:18.529483 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 04:41:18.532660 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 04:41:18.539573 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 04:41:18.543310 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 04:41:18.550377 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 04:41:18.552897 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 04:41:18.559422 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 04:41:18.562432 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 04:41:18.569540 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 04:41:18.572904 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 04:41:18.579687 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 04:41:18.582744 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 04:41:18.589881 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 04:41:18.593190 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 04:41:18.596295 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 04:41:18.602937 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 04:41:18.606144 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 04:41:18.609400 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 04:41:18.616340 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 04:41:18.619534 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 04:41:18.622764 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 04:41:18.626263 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 04:41:18.632699 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 04:41:18.635750 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 04:41:18.640329 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 04:41:18.642478 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 04:41:18.652389 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 04:41:18.659554 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 04:41:18.666340 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 04:41:18.672548 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 04:41:18.682662 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 04:41:18.686218 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 04:41:18.692442 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 04:41:18.695943 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 04:41:18.703260 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 04:41:18.709037 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 04:41:18.712323 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 04:41:18.715929 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 04:41:18.726278 [RTC]rtc_get_frequency_meter,154: input=15, output=764
471 04:41:18.736504 [RTC]rtc_get_frequency_meter,154: input=23, output=950
472 04:41:18.745650 [RTC]rtc_get_frequency_meter,154: input=19, output=857
473 04:41:18.755568 [RTC]rtc_get_frequency_meter,154: input=17, output=810
474 04:41:18.764393 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 04:41:18.774244 [RTC]rtc_get_frequency_meter,154: input=16, output=787
476 04:41:18.783658 [RTC]rtc_get_frequency_meter,154: input=17, output=810
477 04:41:18.786996 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 04:41:18.794028 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 04:41:18.797989 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 04:41:18.800748 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 04:41:18.807433 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 04:41:18.810746 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 04:41:18.814615 ADC[4]: Raw value=670432 ID=5
484 04:41:18.814711 ADC[3]: Raw value=212549 ID=1
485 04:41:18.818249 RAM Code: 0x51
486 04:41:18.821224 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 04:41:18.827805 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 04:41:18.834411 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 04:41:18.841616 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 04:41:18.844638 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 04:41:18.848002 in-header: 03 07 00 00 08 00 00 00
492 04:41:18.851077 in-data: aa e4 47 04 13 02 00 00
493 04:41:18.851161 Chrome EC: UHEPI supported
494 04:41:18.857723 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 04:41:18.861767 in-header: 03 d5 00 00 08 00 00 00
496 04:41:18.865578 in-data: 98 20 60 08 00 00 00 00
497 04:41:18.868694 MRC: failed to locate region type 0.
498 04:41:18.875262 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 04:41:18.879579 DRAM-K: Running full calibration
500 04:41:18.885579 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 04:41:18.885672 header.status = 0x0
502 04:41:18.888982 header.version = 0x6 (expected: 0x6)
503 04:41:18.892422 header.size = 0xd00 (expected: 0xd00)
504 04:41:18.895976 header.flags = 0x0
505 04:41:18.901823 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 04:41:18.918674 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 04:41:18.925765 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 04:41:18.928604 dram_init: ddr_geometry: 0
509 04:41:18.932690 [EMI] MDL number = 0
510 04:41:18.932817 [EMI] Get MDL freq = 0
511 04:41:18.935641 dram_init: ddr_type: 0
512 04:41:18.935725 is_discrete_lpddr4: 1
513 04:41:18.938698 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 04:41:18.938782
515 04:41:18.938847
516 04:41:18.942509 [Bian_co] ETT version 0.0.0.1
517 04:41:18.948929 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 04:41:18.949038
519 04:41:18.952035 dramc_set_vcore_voltage set vcore to 650000
520 04:41:18.952121 Read voltage for 800, 4
521 04:41:18.956496 Vio18 = 0
522 04:41:18.956582 Vcore = 650000
523 04:41:18.956649 Vdram = 0
524 04:41:18.959221 Vddq = 0
525 04:41:18.959304 Vmddr = 0
526 04:41:18.962850 dram_init: config_dvfs: 1
527 04:41:18.965540 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 04:41:18.973133 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 04:41:18.975584 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 04:41:18.979085 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 04:41:18.982481 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 04:41:18.986238 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 04:41:18.988983 MEM_TYPE=3, freq_sel=18
534 04:41:18.992471 sv_algorithm_assistance_LP4_1600
535 04:41:18.995696 ============ PULL DRAM RESETB DOWN ============
536 04:41:18.999041 ========== PULL DRAM RESETB DOWN end =========
537 04:41:19.005478 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 04:41:19.009011 ===================================
539 04:41:19.012540 LPDDR4 DRAM CONFIGURATION
540 04:41:19.012627 ===================================
541 04:41:19.015954 EX_ROW_EN[0] = 0x0
542 04:41:19.018814 EX_ROW_EN[1] = 0x0
543 04:41:19.018899 LP4Y_EN = 0x0
544 04:41:19.023035 WORK_FSP = 0x0
545 04:41:19.023122 WL = 0x2
546 04:41:19.025464 RL = 0x2
547 04:41:19.025550 BL = 0x2
548 04:41:19.029001 RPST = 0x0
549 04:41:19.029086 RD_PRE = 0x0
550 04:41:19.032263 WR_PRE = 0x1
551 04:41:19.032354 WR_PST = 0x0
552 04:41:19.035513 DBI_WR = 0x0
553 04:41:19.035603 DBI_RD = 0x0
554 04:41:19.039819 OTF = 0x1
555 04:41:19.042605 ===================================
556 04:41:19.045967 ===================================
557 04:41:19.046066 ANA top config
558 04:41:19.049462 ===================================
559 04:41:19.052090 DLL_ASYNC_EN = 0
560 04:41:19.055477 ALL_SLAVE_EN = 1
561 04:41:19.058731 NEW_RANK_MODE = 1
562 04:41:19.058835 DLL_IDLE_MODE = 1
563 04:41:19.062118 LP45_APHY_COMB_EN = 1
564 04:41:19.065957 TX_ODT_DIS = 1
565 04:41:19.068991 NEW_8X_MODE = 1
566 04:41:19.071991 ===================================
567 04:41:19.075865 ===================================
568 04:41:19.079058 data_rate = 1600
569 04:41:19.079146 CKR = 1
570 04:41:19.082276 DQ_P2S_RATIO = 8
571 04:41:19.086418 ===================================
572 04:41:19.088701 CA_P2S_RATIO = 8
573 04:41:19.092225 DQ_CA_OPEN = 0
574 04:41:19.095818 DQ_SEMI_OPEN = 0
575 04:41:19.095906 CA_SEMI_OPEN = 0
576 04:41:19.098476 CA_FULL_RATE = 0
577 04:41:19.101971 DQ_CKDIV4_EN = 1
578 04:41:19.105803 CA_CKDIV4_EN = 1
579 04:41:19.108994 CA_PREDIV_EN = 0
580 04:41:19.112874 PH8_DLY = 0
581 04:41:19.112962 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 04:41:19.115624 DQ_AAMCK_DIV = 4
583 04:41:19.118740 CA_AAMCK_DIV = 4
584 04:41:19.122006 CA_ADMCK_DIV = 4
585 04:41:19.125510 DQ_TRACK_CA_EN = 0
586 04:41:19.129084 CA_PICK = 800
587 04:41:19.132277 CA_MCKIO = 800
588 04:41:19.132364 MCKIO_SEMI = 0
589 04:41:19.135730 PLL_FREQ = 3068
590 04:41:19.139055 DQ_UI_PI_RATIO = 32
591 04:41:19.142136 CA_UI_PI_RATIO = 0
592 04:41:19.145629 ===================================
593 04:41:19.149207 ===================================
594 04:41:19.153293 memory_type:LPDDR4
595 04:41:19.153383 GP_NUM : 10
596 04:41:19.155332 SRAM_EN : 1
597 04:41:19.155415 MD32_EN : 0
598 04:41:19.158735 ===================================
599 04:41:19.161867 [ANA_INIT] >>>>>>>>>>>>>>
600 04:41:19.165494 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 04:41:19.169192 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 04:41:19.172117 ===================================
603 04:41:19.176040 data_rate = 1600,PCW = 0X7600
604 04:41:19.178540 ===================================
605 04:41:19.182114 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 04:41:19.189315 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 04:41:19.191926 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 04:41:19.198839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 04:41:19.202072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 04:41:19.205654 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 04:41:19.205782 [ANA_INIT] flow start
612 04:41:19.208683 [ANA_INIT] PLL >>>>>>>>
613 04:41:19.211909 [ANA_INIT] PLL <<<<<<<<
614 04:41:19.212023 [ANA_INIT] MIDPI >>>>>>>>
615 04:41:19.215939 [ANA_INIT] MIDPI <<<<<<<<
616 04:41:19.219145 [ANA_INIT] DLL >>>>>>>>
617 04:41:19.219261 [ANA_INIT] flow end
618 04:41:19.225489 ============ LP4 DIFF to SE enter ============
619 04:41:19.228890 ============ LP4 DIFF to SE exit ============
620 04:41:19.229015 [ANA_INIT] <<<<<<<<<<<<<
621 04:41:19.232124 [Flow] Enable top DCM control >>>>>
622 04:41:19.235673 [Flow] Enable top DCM control <<<<<
623 04:41:19.239351 Enable DLL master slave shuffle
624 04:41:19.245692 ==============================================================
625 04:41:19.248863 Gating Mode config
626 04:41:19.252742 ==============================================================
627 04:41:19.255170 Config description:
628 04:41:19.265359 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 04:41:19.272491 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 04:41:19.275324 SELPH_MODE 0: By rank 1: By Phase
631 04:41:19.282107 ==============================================================
632 04:41:19.285956 GAT_TRACK_EN = 1
633 04:41:19.288423 RX_GATING_MODE = 2
634 04:41:19.288512 RX_GATING_TRACK_MODE = 2
635 04:41:19.292078 SELPH_MODE = 1
636 04:41:19.295747 PICG_EARLY_EN = 1
637 04:41:19.298499 VALID_LAT_VALUE = 1
638 04:41:19.305886 ==============================================================
639 04:41:19.308528 Enter into Gating configuration >>>>
640 04:41:19.312458 Exit from Gating configuration <<<<
641 04:41:19.315855 Enter into DVFS_PRE_config >>>>>
642 04:41:19.326075 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 04:41:19.330356 Exit from DVFS_PRE_config <<<<<
644 04:41:19.332285 Enter into PICG configuration >>>>
645 04:41:19.335711 Exit from PICG configuration <<<<
646 04:41:19.338903 [RX_INPUT] configuration >>>>>
647 04:41:19.341999 [RX_INPUT] configuration <<<<<
648 04:41:19.345470 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 04:41:19.352578 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 04:41:19.358902 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 04:41:19.362113 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 04:41:19.368625 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 04:41:19.375354 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 04:41:19.379261 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 04:41:19.385704 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 04:41:19.388553 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 04:41:19.392128 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 04:41:19.395139 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 04:41:19.402290 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 04:41:19.405048 ===================================
661 04:41:19.405145 LPDDR4 DRAM CONFIGURATION
662 04:41:19.408406 ===================================
663 04:41:19.412137 EX_ROW_EN[0] = 0x0
664 04:41:19.416057 EX_ROW_EN[1] = 0x0
665 04:41:19.416180 LP4Y_EN = 0x0
666 04:41:19.418526 WORK_FSP = 0x0
667 04:41:19.418611 WL = 0x2
668 04:41:19.422175 RL = 0x2
669 04:41:19.422282 BL = 0x2
670 04:41:19.425060 RPST = 0x0
671 04:41:19.425148 RD_PRE = 0x0
672 04:41:19.429194 WR_PRE = 0x1
673 04:41:19.429286 WR_PST = 0x0
674 04:41:19.432175 DBI_WR = 0x0
675 04:41:19.432293 DBI_RD = 0x0
676 04:41:19.435364 OTF = 0x1
677 04:41:19.438484 ===================================
678 04:41:19.441830 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 04:41:19.445707 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 04:41:19.452230 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 04:41:19.455078 ===================================
682 04:41:19.455207 LPDDR4 DRAM CONFIGURATION
683 04:41:19.458840 ===================================
684 04:41:19.461965 EX_ROW_EN[0] = 0x10
685 04:41:19.462061 EX_ROW_EN[1] = 0x0
686 04:41:19.464881 LP4Y_EN = 0x0
687 04:41:19.464968 WORK_FSP = 0x0
688 04:41:19.468553 WL = 0x2
689 04:41:19.472393 RL = 0x2
690 04:41:19.472517 BL = 0x2
691 04:41:19.474953 RPST = 0x0
692 04:41:19.475073 RD_PRE = 0x0
693 04:41:19.478484 WR_PRE = 0x1
694 04:41:19.478574 WR_PST = 0x0
695 04:41:19.481539 DBI_WR = 0x0
696 04:41:19.481628 DBI_RD = 0x0
697 04:41:19.484956 OTF = 0x1
698 04:41:19.489325 ===================================
699 04:41:19.491344 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 04:41:19.497022 nWR fixed to 40
701 04:41:19.501776 [ModeRegInit_LP4] CH0 RK0
702 04:41:19.501893 [ModeRegInit_LP4] CH0 RK1
703 04:41:19.503792 [ModeRegInit_LP4] CH1 RK0
704 04:41:19.507153 [ModeRegInit_LP4] CH1 RK1
705 04:41:19.507244 match AC timing 12
706 04:41:19.514080 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 04:41:19.517026 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 04:41:19.520594 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 04:41:19.526761 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 04:41:19.530293 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 04:41:19.530396 [EMI DOE] emi_dcm 0
712 04:41:19.537158 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 04:41:19.537270 ==
714 04:41:19.540422 Dram Type= 6, Freq= 0, CH_0, rank 0
715 04:41:19.544156 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 04:41:19.544269 ==
717 04:41:19.550457 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 04:41:19.557148 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 04:41:19.564530 [CA 0] Center 37 (7~68) winsize 62
720 04:41:19.567652 [CA 1] Center 37 (6~68) winsize 63
721 04:41:19.570772 [CA 2] Center 35 (5~66) winsize 62
722 04:41:19.574594 [CA 3] Center 35 (5~66) winsize 62
723 04:41:19.577642 [CA 4] Center 34 (3~65) winsize 63
724 04:41:19.581131 [CA 5] Center 33 (3~64) winsize 62
725 04:41:19.581230
726 04:41:19.584671 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 04:41:19.584783
728 04:41:19.587862 [CATrainingPosCal] consider 1 rank data
729 04:41:19.591152 u2DelayCellTimex100 = 270/100 ps
730 04:41:19.594529 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 04:41:19.597668 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 04:41:19.604286 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 04:41:19.607540 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
734 04:41:19.611460 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 04:41:19.614561 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 04:41:19.614658
737 04:41:19.617312 CA PerBit enable=1, Macro0, CA PI delay=33
738 04:41:19.617433
739 04:41:19.621124 [CBTSetCACLKResult] CA Dly = 33
740 04:41:19.621217 CS Dly: 5 (0~36)
741 04:41:19.624656 ==
742 04:41:19.627918 Dram Type= 6, Freq= 0, CH_0, rank 1
743 04:41:19.631762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 04:41:19.631872 ==
745 04:41:19.635028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 04:41:19.641912 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 04:41:19.651002 [CA 0] Center 37 (7~68) winsize 62
748 04:41:19.654095 [CA 1] Center 37 (6~68) winsize 63
749 04:41:19.657626 [CA 2] Center 35 (4~66) winsize 63
750 04:41:19.660687 [CA 3] Center 35 (4~66) winsize 63
751 04:41:19.664218 [CA 4] Center 34 (3~65) winsize 63
752 04:41:19.667268 [CA 5] Center 34 (3~65) winsize 63
753 04:41:19.667363
754 04:41:19.671104 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 04:41:19.671198
756 04:41:19.673725 [CATrainingPosCal] consider 2 rank data
757 04:41:19.677396 u2DelayCellTimex100 = 270/100 ps
758 04:41:19.680364 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 04:41:19.683771 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
760 04:41:19.690684 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 04:41:19.693683 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
762 04:41:19.697616 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
763 04:41:19.700535 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 04:41:19.700652
765 04:41:19.704231 CA PerBit enable=1, Macro0, CA PI delay=33
766 04:41:19.704321
767 04:41:19.708492 [CBTSetCACLKResult] CA Dly = 33
768 04:41:19.708610 CS Dly: 5 (0~37)
769 04:41:19.708713
770 04:41:19.710959 ----->DramcWriteLeveling(PI) begin...
771 04:41:19.714362 ==
772 04:41:19.717155 Dram Type= 6, Freq= 0, CH_0, rank 0
773 04:41:19.720917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 04:41:19.721016 ==
775 04:41:19.723812 Write leveling (Byte 0): 29 => 29
776 04:41:19.727503 Write leveling (Byte 1): 29 => 29
777 04:41:19.730720 DramcWriteLeveling(PI) end<-----
778 04:41:19.730817
779 04:41:19.730884 ==
780 04:41:19.734360 Dram Type= 6, Freq= 0, CH_0, rank 0
781 04:41:19.737264 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 04:41:19.737360 ==
783 04:41:19.740570 [Gating] SW mode calibration
784 04:41:19.747786 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 04:41:19.751262 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 04:41:19.757403 0 6 0 | B1->B0 | 3333 3232 | 0 1 | (0 1) (1 0)
787 04:41:19.760945 0 6 4 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
788 04:41:19.764072 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 04:41:19.770448 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 04:41:19.774347 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 04:41:19.778319 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 04:41:19.784478 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 04:41:19.787203 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 04:41:19.791022 0 7 0 | B1->B0 | 2525 2b2b | 1 0 | (1 1) (1 1)
795 04:41:19.797206 0 7 4 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
796 04:41:19.800701 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 04:41:19.804766 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 04:41:19.810877 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 04:41:19.814152 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 04:41:19.817480 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 04:41:19.824006 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 04:41:19.827624 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
803 04:41:19.830781 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
804 04:41:19.833741 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 04:41:19.841099 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 04:41:19.843606 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 04:41:19.846956 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 04:41:19.853718 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 04:41:19.857094 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 04:41:19.860129 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 04:41:19.867160 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 04:41:19.870495 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 04:41:19.874068 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 04:41:19.880562 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 04:41:19.883448 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 04:41:19.887446 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 04:41:19.893857 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 04:41:19.897401 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
819 04:41:19.900638 Total UI for P1: 0, mck2ui 16
820 04:41:19.904184 best dqsien dly found for B1: ( 0, 9, 30)
821 04:41:19.906943 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
822 04:41:19.910848 Total UI for P1: 0, mck2ui 16
823 04:41:19.913675 best dqsien dly found for B0: ( 0, 10, 0)
824 04:41:19.917117 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
825 04:41:19.920992 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
826 04:41:19.921087
827 04:41:19.927159 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
828 04:41:19.930324 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
829 04:41:19.930420 [Gating] SW calibration Done
830 04:41:19.933557 ==
831 04:41:19.937716 Dram Type= 6, Freq= 0, CH_0, rank 0
832 04:41:19.941140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 04:41:19.941239 ==
834 04:41:19.941306 RX Vref Scan: 0
835 04:41:19.941368
836 04:41:19.944459 RX Vref 0 -> 0, step: 1
837 04:41:19.944556
838 04:41:19.947729 RX Delay -130 -> 252, step: 16
839 04:41:19.951313 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
840 04:41:19.954147 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 04:41:19.957769 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
842 04:41:19.964330 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 04:41:19.968075 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
844 04:41:19.971018 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 04:41:19.974455 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 04:41:19.977799 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 04:41:19.980528 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
848 04:41:19.987451 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 04:41:19.991060 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 04:41:19.994088 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 04:41:19.997207 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 04:41:20.004577 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
853 04:41:20.007082 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 04:41:20.010822 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 04:41:20.010916 ==
856 04:41:20.014199 Dram Type= 6, Freq= 0, CH_0, rank 0
857 04:41:20.018239 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 04:41:20.018334 ==
859 04:41:20.020439 DQS Delay:
860 04:41:20.020524 DQS0 = 0, DQS1 = 0
861 04:41:20.024471 DQM Delay:
862 04:41:20.024562 DQM0 = 84, DQM1 = 74
863 04:41:20.024630 DQ Delay:
864 04:41:20.027933 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
865 04:41:20.031089 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
866 04:41:20.033837 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
867 04:41:20.037273 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
868 04:41:20.037364
869 04:41:20.037430
870 04:41:20.040389 ==
871 04:41:20.040476 Dram Type= 6, Freq= 0, CH_0, rank 0
872 04:41:20.048238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 04:41:20.048370 ==
874 04:41:20.048440
875 04:41:20.048501
876 04:41:20.050384 TX Vref Scan disable
877 04:41:20.050469 == TX Byte 0 ==
878 04:41:20.054001 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
879 04:41:20.060472 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
880 04:41:20.060576 == TX Byte 1 ==
881 04:41:20.064992 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
882 04:41:20.071651 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
883 04:41:20.071770 ==
884 04:41:20.074073 Dram Type= 6, Freq= 0, CH_0, rank 0
885 04:41:20.076670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 04:41:20.076777 ==
887 04:41:20.090097 TX Vref=22, minBit 0, minWin=27, winSum=444
888 04:41:20.092934 TX Vref=24, minBit 0, minWin=27, winSum=447
889 04:41:20.096914 TX Vref=26, minBit 4, minWin=27, winSum=455
890 04:41:20.099808 TX Vref=28, minBit 3, minWin=27, winSum=452
891 04:41:20.103383 TX Vref=30, minBit 0, minWin=28, winSum=457
892 04:41:20.109968 TX Vref=32, minBit 1, minWin=27, winSum=455
893 04:41:20.113082 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
894 04:41:20.113184
895 04:41:20.116486 Final TX Range 1 Vref 30
896 04:41:20.116575
897 04:41:20.116642 ==
898 04:41:20.120074 Dram Type= 6, Freq= 0, CH_0, rank 0
899 04:41:20.123786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 04:41:20.123881 ==
901 04:41:20.123948
902 04:41:20.127093
903 04:41:20.127206 TX Vref Scan disable
904 04:41:20.129535 == TX Byte 0 ==
905 04:41:20.133606 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
906 04:41:20.137022 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
907 04:41:20.140015 == TX Byte 1 ==
908 04:41:20.143625 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
909 04:41:20.148431 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
910 04:41:20.149672
911 04:41:20.149760 [DATLAT]
912 04:41:20.149826 Freq=800, CH0 RK0
913 04:41:20.149889
914 04:41:20.153331 DATLAT Default: 0xa
915 04:41:20.153418 0, 0xFFFF, sum = 0
916 04:41:20.156180 1, 0xFFFF, sum = 0
917 04:41:20.156271 2, 0xFFFF, sum = 0
918 04:41:20.160455 3, 0xFFFF, sum = 0
919 04:41:20.160546 4, 0xFFFF, sum = 0
920 04:41:20.163505 5, 0xFFFF, sum = 0
921 04:41:20.166836 6, 0xFFFF, sum = 0
922 04:41:20.166927 7, 0xFFFF, sum = 0
923 04:41:20.166995 8, 0x0, sum = 1
924 04:41:20.169976 9, 0x0, sum = 2
925 04:41:20.170064 10, 0x0, sum = 3
926 04:41:20.173244 11, 0x0, sum = 4
927 04:41:20.173333 best_step = 9
928 04:41:20.173399
929 04:41:20.173461 ==
930 04:41:20.176579 Dram Type= 6, Freq= 0, CH_0, rank 0
931 04:41:20.183179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 04:41:20.183280 ==
933 04:41:20.183349 RX Vref Scan: 1
934 04:41:20.183411
935 04:41:20.186317 Set Vref Range= 32 -> 127
936 04:41:20.186406
937 04:41:20.189866 RX Vref 32 -> 127, step: 1
938 04:41:20.189956
939 04:41:20.193256 RX Delay -111 -> 252, step: 8
940 04:41:20.193344
941 04:41:20.193410 Set Vref, RX VrefLevel [Byte0]: 32
942 04:41:20.196617 [Byte1]: 32
943 04:41:20.201687
944 04:41:20.201788 Set Vref, RX VrefLevel [Byte0]: 33
945 04:41:20.203926 [Byte1]: 33
946 04:41:20.208239
947 04:41:20.208327 Set Vref, RX VrefLevel [Byte0]: 34
948 04:41:20.211741 [Byte1]: 34
949 04:41:20.216062
950 04:41:20.216156 Set Vref, RX VrefLevel [Byte0]: 35
951 04:41:20.219298 [Byte1]: 35
952 04:41:20.224669
953 04:41:20.224787 Set Vref, RX VrefLevel [Byte0]: 36
954 04:41:20.227698 [Byte1]: 36
955 04:41:20.231326
956 04:41:20.231420 Set Vref, RX VrefLevel [Byte0]: 37
957 04:41:20.234529 [Byte1]: 37
958 04:41:20.239139
959 04:41:20.239238 Set Vref, RX VrefLevel [Byte0]: 38
960 04:41:20.242234 [Byte1]: 38
961 04:41:20.246567
962 04:41:20.246673 Set Vref, RX VrefLevel [Byte0]: 39
963 04:41:20.250225 [Byte1]: 39
964 04:41:20.254345
965 04:41:20.254445 Set Vref, RX VrefLevel [Byte0]: 40
966 04:41:20.257472 [Byte1]: 40
967 04:41:20.261920
968 04:41:20.262011 Set Vref, RX VrefLevel [Byte0]: 41
969 04:41:20.266073 [Byte1]: 41
970 04:41:20.269399
971 04:41:20.269493 Set Vref, RX VrefLevel [Byte0]: 42
972 04:41:20.272572 [Byte1]: 42
973 04:41:20.277069
974 04:41:20.277162 Set Vref, RX VrefLevel [Byte0]: 43
975 04:41:20.280489 [Byte1]: 43
976 04:41:20.284972
977 04:41:20.285081 Set Vref, RX VrefLevel [Byte0]: 44
978 04:41:20.287994 [Byte1]: 44
979 04:41:20.292544
980 04:41:20.292662 Set Vref, RX VrefLevel [Byte0]: 45
981 04:41:20.295795 [Byte1]: 45
982 04:41:20.299994
983 04:41:20.300105 Set Vref, RX VrefLevel [Byte0]: 46
984 04:41:20.303239 [Byte1]: 46
985 04:41:20.308022
986 04:41:20.308139 Set Vref, RX VrefLevel [Byte0]: 47
987 04:41:20.311683 [Byte1]: 47
988 04:41:20.315585
989 04:41:20.315676 Set Vref, RX VrefLevel [Byte0]: 48
990 04:41:20.318613 [Byte1]: 48
991 04:41:20.323243
992 04:41:20.323348 Set Vref, RX VrefLevel [Byte0]: 49
993 04:41:20.326417 [Byte1]: 49
994 04:41:20.331609
995 04:41:20.331707 Set Vref, RX VrefLevel [Byte0]: 50
996 04:41:20.334008 [Byte1]: 50
997 04:41:20.338739
998 04:41:20.338843 Set Vref, RX VrefLevel [Byte0]: 51
999 04:41:20.341848 [Byte1]: 51
1000 04:41:20.345786
1001 04:41:20.345901 Set Vref, RX VrefLevel [Byte0]: 52
1002 04:41:20.349210 [Byte1]: 52
1003 04:41:20.353510
1004 04:41:20.353610 Set Vref, RX VrefLevel [Byte0]: 53
1005 04:41:20.357210 [Byte1]: 53
1006 04:41:20.361535
1007 04:41:20.361631 Set Vref, RX VrefLevel [Byte0]: 54
1008 04:41:20.364427 [Byte1]: 54
1009 04:41:20.369245
1010 04:41:20.369342 Set Vref, RX VrefLevel [Byte0]: 55
1011 04:41:20.372957 [Byte1]: 55
1012 04:41:20.376591
1013 04:41:20.376679 Set Vref, RX VrefLevel [Byte0]: 56
1014 04:41:20.380229 [Byte1]: 56
1015 04:41:20.384086
1016 04:41:20.384180 Set Vref, RX VrefLevel [Byte0]: 57
1017 04:41:20.387730 [Byte1]: 57
1018 04:41:20.391992
1019 04:41:20.392086 Set Vref, RX VrefLevel [Byte0]: 58
1020 04:41:20.394987 [Byte1]: 58
1021 04:41:20.399976
1022 04:41:20.400068 Set Vref, RX VrefLevel [Byte0]: 59
1023 04:41:20.402971 [Byte1]: 59
1024 04:41:20.407582
1025 04:41:20.407687 Set Vref, RX VrefLevel [Byte0]: 60
1026 04:41:20.410412 [Byte1]: 60
1027 04:41:20.415670
1028 04:41:20.415765 Set Vref, RX VrefLevel [Byte0]: 61
1029 04:41:20.418319 [Byte1]: 61
1030 04:41:20.423134
1031 04:41:20.423275 Set Vref, RX VrefLevel [Byte0]: 62
1032 04:41:20.425837 [Byte1]: 62
1033 04:41:20.430574
1034 04:41:20.430669 Set Vref, RX VrefLevel [Byte0]: 63
1035 04:41:20.433638 [Byte1]: 63
1036 04:41:20.437757
1037 04:41:20.437846 Set Vref, RX VrefLevel [Byte0]: 64
1038 04:41:20.441173 [Byte1]: 64
1039 04:41:20.445274
1040 04:41:20.445371 Set Vref, RX VrefLevel [Byte0]: 65
1041 04:41:20.448898 [Byte1]: 65
1042 04:41:20.453461
1043 04:41:20.453548 Set Vref, RX VrefLevel [Byte0]: 66
1044 04:41:20.456600 [Byte1]: 66
1045 04:41:20.460533
1046 04:41:20.460645 Set Vref, RX VrefLevel [Byte0]: 67
1047 04:41:20.463691 [Byte1]: 67
1048 04:41:20.468389
1049 04:41:20.468480 Set Vref, RX VrefLevel [Byte0]: 68
1050 04:41:20.475152 [Byte1]: 68
1051 04:41:20.475246
1052 04:41:20.477705 Set Vref, RX VrefLevel [Byte0]: 69
1053 04:41:20.481328 [Byte1]: 69
1054 04:41:20.481421
1055 04:41:20.484486 Set Vref, RX VrefLevel [Byte0]: 70
1056 04:41:20.488539 [Byte1]: 70
1057 04:41:20.491090
1058 04:41:20.491174 Set Vref, RX VrefLevel [Byte0]: 71
1059 04:41:20.494679 [Byte1]: 71
1060 04:41:20.498905
1061 04:41:20.498996 Set Vref, RX VrefLevel [Byte0]: 72
1062 04:41:20.502618 [Byte1]: 72
1063 04:41:20.506646
1064 04:41:20.506736 Set Vref, RX VrefLevel [Byte0]: 73
1065 04:41:20.509588 [Byte1]: 73
1066 04:41:20.514567
1067 04:41:20.514669 Final RX Vref Byte 0 = 50 to rank0
1068 04:41:20.517893 Final RX Vref Byte 1 = 55 to rank0
1069 04:41:20.520672 Final RX Vref Byte 0 = 50 to rank1
1070 04:41:20.524405 Final RX Vref Byte 1 = 55 to rank1==
1071 04:41:20.527497 Dram Type= 6, Freq= 0, CH_0, rank 0
1072 04:41:20.533797 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1073 04:41:20.533920 ==
1074 04:41:20.533986 DQS Delay:
1075 04:41:20.534094 DQS0 = 0, DQS1 = 0
1076 04:41:20.537457 DQM Delay:
1077 04:41:20.537578 DQM0 = 84, DQM1 = 74
1078 04:41:20.541528 DQ Delay:
1079 04:41:20.543865 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1080 04:41:20.547742 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1081 04:41:20.550859 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1082 04:41:20.554779 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1083 04:41:20.554904
1084 04:41:20.554972
1085 04:41:20.560544 [DQSOSCAuto] RK0, (LSB)MR18= 0x3333, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1086 04:41:20.563950 CH0 RK0: MR19=606, MR18=3333
1087 04:41:20.570539 CH0_RK0: MR19=0x606, MR18=0x3333, DQSOSC=396, MR23=63, INC=94, DEC=62
1088 04:41:20.570665
1089 04:41:20.573773 ----->DramcWriteLeveling(PI) begin...
1090 04:41:20.573860 ==
1091 04:41:20.577928 Dram Type= 6, Freq= 0, CH_0, rank 1
1092 04:41:20.580459 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1093 04:41:20.580569 ==
1094 04:41:20.583579 Write leveling (Byte 0): 28 => 28
1095 04:41:20.587474 Write leveling (Byte 1): 31 => 31
1096 04:41:20.590566 DramcWriteLeveling(PI) end<-----
1097 04:41:20.590658
1098 04:41:20.590724 ==
1099 04:41:20.593580 Dram Type= 6, Freq= 0, CH_0, rank 1
1100 04:41:20.596803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1101 04:41:20.596895 ==
1102 04:41:20.600629 [Gating] SW mode calibration
1103 04:41:20.607144 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1104 04:41:20.613655 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1105 04:41:20.616967 0 6 0 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 1)
1106 04:41:20.620636 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1107 04:41:20.627346 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1108 04:41:20.630693 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1109 04:41:20.633581 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1110 04:41:20.640533 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 04:41:20.644033 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 04:41:20.646918 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 04:41:20.653605 0 7 0 | B1->B0 | 2e2e 2d2d | 0 0 | (1 1) (0 0)
1114 04:41:20.656757 0 7 4 | B1->B0 | 4545 4444 | 0 1 | (0 0) (0 0)
1115 04:41:20.660319 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1116 04:41:20.667193 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1117 04:41:20.670378 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1118 04:41:20.674042 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 04:41:20.680336 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 04:41:20.683749 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 04:41:20.687614 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1122 04:41:20.694128 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1123 04:41:20.696918 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1124 04:41:20.700513 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1125 04:41:20.707580 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 04:41:20.710706 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 04:41:20.714429 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 04:41:20.717390 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 04:41:20.723376 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 04:41:20.727019 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 04:41:20.730124 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 04:41:20.736703 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 04:41:20.740335 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 04:41:20.743854 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 04:41:20.749910 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 04:41:20.753730 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 04:41:20.757649 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1138 04:41:20.763264 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1139 04:41:20.766998 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1140 04:41:20.769866 Total UI for P1: 0, mck2ui 16
1141 04:41:20.773818 best dqsien dly found for B0: ( 0, 10, 2)
1142 04:41:20.777618 Total UI for P1: 0, mck2ui 16
1143 04:41:20.780544 best dqsien dly found for B1: ( 0, 10, 4)
1144 04:41:20.783826 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1145 04:41:20.786763 best DQS1 dly(MCK, UI, PI) = (0, 10, 4)
1146 04:41:20.786850
1147 04:41:20.790390 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1148 04:41:20.793985 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 4)
1149 04:41:20.797292 [Gating] SW calibration Done
1150 04:41:20.797381 ==
1151 04:41:20.800411 Dram Type= 6, Freq= 0, CH_0, rank 1
1152 04:41:20.803675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1153 04:41:20.803759 ==
1154 04:41:20.807084 RX Vref Scan: 0
1155 04:41:20.807167
1156 04:41:20.810131 RX Vref 0 -> 0, step: 1
1157 04:41:20.810214
1158 04:41:20.813495 RX Delay -130 -> 252, step: 16
1159 04:41:20.817341 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1160 04:41:20.861461 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1161 04:41:20.861620 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1162 04:41:20.861882 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1163 04:41:20.862631 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1164 04:41:20.863422 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1165 04:41:20.863504 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1166 04:41:20.863753 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1167 04:41:20.864279 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1168 04:41:20.864543 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1169 04:41:20.864611 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1170 04:41:20.864683 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1171 04:41:20.881323 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1172 04:41:20.881474 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1173 04:41:20.882197 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1174 04:41:20.882746 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1175 04:41:20.882826 ==
1176 04:41:20.884981 Dram Type= 6, Freq= 0, CH_0, rank 1
1177 04:41:20.885063 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1178 04:41:20.885127 ==
1179 04:41:20.888090 DQS Delay:
1180 04:41:20.888171 DQS0 = 0, DQS1 = 0
1181 04:41:20.888234 DQM Delay:
1182 04:41:20.888293 DQM0 = 80, DQM1 = 73
1183 04:41:20.892457 DQ Delay:
1184 04:41:20.894904 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
1185 04:41:20.898537 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1186 04:41:20.901351 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1187 04:41:20.905004 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1188 04:41:20.905092
1189 04:41:20.905158
1190 04:41:20.905217 ==
1191 04:41:20.907996 Dram Type= 6, Freq= 0, CH_0, rank 1
1192 04:41:20.911450 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1193 04:41:20.911541 ==
1194 04:41:20.911605
1195 04:41:20.911665
1196 04:41:20.914958 TX Vref Scan disable
1197 04:41:20.915039 == TX Byte 0 ==
1198 04:41:20.921736 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1199 04:41:20.924924 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1200 04:41:20.925016 == TX Byte 1 ==
1201 04:41:20.932157 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1202 04:41:20.934708 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1203 04:41:20.934799 ==
1204 04:41:20.937980 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 04:41:20.941357 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1206 04:41:20.941444 ==
1207 04:41:20.955461 TX Vref=22, minBit 2, minWin=27, winSum=444
1208 04:41:20.959034 TX Vref=24, minBit 0, minWin=27, winSum=447
1209 04:41:20.962245 TX Vref=26, minBit 0, minWin=27, winSum=455
1210 04:41:20.965540 TX Vref=28, minBit 4, minWin=28, winSum=460
1211 04:41:20.969165 TX Vref=30, minBit 4, minWin=28, winSum=460
1212 04:41:20.971964 TX Vref=32, minBit 2, minWin=28, winSum=459
1213 04:41:20.978649 [TxChooseVref] Worse bit 4, Min win 28, Win sum 460, Final Vref 28
1214 04:41:20.978753
1215 04:41:20.982095 Final TX Range 1 Vref 28
1216 04:41:20.982184
1217 04:41:20.982248 ==
1218 04:41:20.986137 Dram Type= 6, Freq= 0, CH_0, rank 1
1219 04:41:20.989647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1220 04:41:20.989736 ==
1221 04:41:20.991894
1222 04:41:20.991975
1223 04:41:20.992038 TX Vref Scan disable
1224 04:41:20.996110 == TX Byte 0 ==
1225 04:41:20.998951 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1226 04:41:21.005908 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1227 04:41:21.006018 == TX Byte 1 ==
1228 04:41:21.009205 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1229 04:41:21.015861 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1230 04:41:21.015966
1231 04:41:21.016033 [DATLAT]
1232 04:41:21.016092 Freq=800, CH0 RK1
1233 04:41:21.016150
1234 04:41:21.019024 DATLAT Default: 0x9
1235 04:41:21.019108 0, 0xFFFF, sum = 0
1236 04:41:21.022471 1, 0xFFFF, sum = 0
1237 04:41:21.022556 2, 0xFFFF, sum = 0
1238 04:41:21.025225 3, 0xFFFF, sum = 0
1239 04:41:21.029081 4, 0xFFFF, sum = 0
1240 04:41:21.029182 5, 0xFFFF, sum = 0
1241 04:41:21.032000 6, 0xFFFF, sum = 0
1242 04:41:21.032085 7, 0xFFFF, sum = 0
1243 04:41:21.035529 8, 0x0, sum = 1
1244 04:41:21.035615 9, 0x0, sum = 2
1245 04:41:21.035681 10, 0x0, sum = 3
1246 04:41:21.038934 11, 0x0, sum = 4
1247 04:41:21.039018 best_step = 9
1248 04:41:21.039082
1249 04:41:21.039141 ==
1250 04:41:21.042396 Dram Type= 6, Freq= 0, CH_0, rank 1
1251 04:41:21.048929 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1252 04:41:21.049045 ==
1253 04:41:21.049114 RX Vref Scan: 0
1254 04:41:21.049174
1255 04:41:21.052703 RX Vref 0 -> 0, step: 1
1256 04:41:21.052826
1257 04:41:21.055239 RX Delay -111 -> 252, step: 8
1258 04:41:21.059179 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1259 04:41:21.061772 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1260 04:41:21.068728 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1261 04:41:21.071862 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1262 04:41:21.075108 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1263 04:41:21.078792 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1264 04:41:21.082519 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1265 04:41:21.089017 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1266 04:41:21.092223 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1267 04:41:21.095791 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1268 04:41:21.098636 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1269 04:41:21.101900 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1270 04:41:21.108917 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1271 04:41:21.112358 iDelay=217, Bit 13, Center 76 (-39 ~ 192) 232
1272 04:41:21.116907 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1273 04:41:21.118500 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1274 04:41:21.118585 ==
1275 04:41:21.122328 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 04:41:21.128986 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1277 04:41:21.129091 ==
1278 04:41:21.129159 DQS Delay:
1279 04:41:21.129219 DQS0 = 0, DQS1 = 0
1280 04:41:21.131992 DQM Delay:
1281 04:41:21.132074 DQM0 = 85, DQM1 = 73
1282 04:41:21.136042 DQ Delay:
1283 04:41:21.139342 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1284 04:41:21.139429 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1285 04:41:21.142315 DQ8 =64, DQ9 =60, DQ10 =72, DQ11 =64
1286 04:41:21.145642 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1287 04:41:21.148918
1288 04:41:21.149009
1289 04:41:21.155148 [DQSOSCAuto] RK1, (LSB)MR18= 0x4040, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1290 04:41:21.158527 CH0 RK1: MR19=606, MR18=4040
1291 04:41:21.165601 CH0_RK1: MR19=0x606, MR18=0x4040, DQSOSC=393, MR23=63, INC=95, DEC=63
1292 04:41:21.168693 [RxdqsGatingPostProcess] freq 800
1293 04:41:21.171840 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1294 04:41:21.175021 Pre-setting of DQS Precalculation
1295 04:41:21.178672 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1296 04:41:21.181995 ==
1297 04:41:21.185530 Dram Type= 6, Freq= 0, CH_1, rank 0
1298 04:41:21.189522 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1299 04:41:21.189606 ==
1300 04:41:21.192640 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1301 04:41:21.199003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1302 04:41:21.208953 [CA 0] Center 36 (6~67) winsize 62
1303 04:41:21.211755 [CA 1] Center 36 (6~67) winsize 62
1304 04:41:21.215031 [CA 2] Center 34 (4~65) winsize 62
1305 04:41:21.218522 [CA 3] Center 34 (4~65) winsize 62
1306 04:41:21.221955 [CA 4] Center 33 (2~64) winsize 63
1307 04:41:21.225191 [CA 5] Center 33 (3~64) winsize 62
1308 04:41:21.225277
1309 04:41:21.228473 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1310 04:41:21.228556
1311 04:41:21.232018 [CATrainingPosCal] consider 1 rank data
1312 04:41:21.235044 u2DelayCellTimex100 = 270/100 ps
1313 04:41:21.238296 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1314 04:41:21.241817 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1315 04:41:21.248214 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1316 04:41:21.251844 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1317 04:41:21.254706 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1318 04:41:21.258550 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1319 04:41:21.258636
1320 04:41:21.262221 CA PerBit enable=1, Macro0, CA PI delay=33
1321 04:41:21.262308
1322 04:41:21.265003 [CBTSetCACLKResult] CA Dly = 33
1323 04:41:21.265085 CS Dly: 4 (0~35)
1324 04:41:21.265148 ==
1325 04:41:21.268119 Dram Type= 6, Freq= 0, CH_1, rank 1
1326 04:41:21.275275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1327 04:41:21.275369 ==
1328 04:41:21.278382 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1329 04:41:21.285418 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1330 04:41:21.294387 [CA 0] Center 36 (6~67) winsize 62
1331 04:41:21.297295 [CA 1] Center 36 (6~67) winsize 62
1332 04:41:21.300916 [CA 2] Center 34 (4~65) winsize 62
1333 04:41:21.304262 [CA 3] Center 34 (4~65) winsize 62
1334 04:41:21.307423 [CA 4] Center 33 (3~64) winsize 62
1335 04:41:21.310715 [CA 5] Center 33 (3~64) winsize 62
1336 04:41:21.310801
1337 04:41:21.315681 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1338 04:41:21.315765
1339 04:41:21.318092 [CATrainingPosCal] consider 2 rank data
1340 04:41:21.320670 u2DelayCellTimex100 = 270/100 ps
1341 04:41:21.324181 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1342 04:41:21.327870 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1343 04:41:21.334207 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1344 04:41:21.337118 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1345 04:41:21.340629 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1346 04:41:21.344066 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1347 04:41:21.344156
1348 04:41:21.348373 CA PerBit enable=1, Macro0, CA PI delay=33
1349 04:41:21.348465
1350 04:41:21.351931 [CBTSetCACLKResult] CA Dly = 33
1351 04:41:21.352016 CS Dly: 4 (0~36)
1352 04:41:21.352080
1353 04:41:21.354645 ----->DramcWriteLeveling(PI) begin...
1354 04:41:21.354727 ==
1355 04:41:21.357378 Dram Type= 6, Freq= 0, CH_1, rank 0
1356 04:41:21.364318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1357 04:41:21.364428 ==
1358 04:41:21.367497 Write leveling (Byte 0): 23 => 23
1359 04:41:21.371022 Write leveling (Byte 1): 23 => 23
1360 04:41:21.371107 DramcWriteLeveling(PI) end<-----
1361 04:41:21.374366
1362 04:41:21.374448 ==
1363 04:41:21.377343 Dram Type= 6, Freq= 0, CH_1, rank 0
1364 04:41:21.380775 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1365 04:41:21.380873 ==
1366 04:41:21.384383 [Gating] SW mode calibration
1367 04:41:21.391234 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1368 04:41:21.394252 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1369 04:41:21.401034 0 6 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
1370 04:41:21.404101 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1371 04:41:21.407640 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1372 04:41:21.414767 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1373 04:41:21.417669 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 04:41:21.420744 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 04:41:21.427748 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 04:41:21.431062 0 6 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1377 04:41:21.434366 0 7 0 | B1->B0 | 3131 4242 | 0 0 | (0 0) (0 0)
1378 04:41:21.441125 0 7 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1379 04:41:21.444148 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1380 04:41:21.447875 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1381 04:41:21.454312 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1382 04:41:21.457333 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 04:41:21.461513 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 04:41:21.464754 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1385 04:41:21.470994 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1386 04:41:21.474778 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1387 04:41:21.477510 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1388 04:41:21.484232 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 04:41:21.487677 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 04:41:21.490879 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 04:41:21.497858 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 04:41:21.501200 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 04:41:21.504628 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 04:41:21.510882 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 04:41:21.514860 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 04:41:21.517927 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 04:41:21.524404 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 04:41:21.527491 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 04:41:21.530675 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 04:41:21.537641 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 04:41:21.540594 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1402 04:41:21.544135 Total UI for P1: 0, mck2ui 16
1403 04:41:21.547790 best dqsien dly found for B0: ( 0, 9, 30)
1404 04:41:21.551303 Total UI for P1: 0, mck2ui 16
1405 04:41:21.554177 best dqsien dly found for B1: ( 0, 9, 30)
1406 04:41:21.557165 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1407 04:41:21.561888 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1408 04:41:21.561980
1409 04:41:21.564245 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1410 04:41:21.568426 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1411 04:41:21.571045 [Gating] SW calibration Done
1412 04:41:21.571131 ==
1413 04:41:21.574356 Dram Type= 6, Freq= 0, CH_1, rank 0
1414 04:41:21.577413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1415 04:41:21.577497 ==
1416 04:41:21.580868 RX Vref Scan: 0
1417 04:41:21.580950
1418 04:41:21.584437 RX Vref 0 -> 0, step: 1
1419 04:41:21.584525
1420 04:41:21.584590 RX Delay -130 -> 252, step: 16
1421 04:41:21.590976 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1422 04:41:21.594353 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1423 04:41:21.598085 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1424 04:41:21.600732 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1425 04:41:21.604028 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1426 04:41:21.610685 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1427 04:41:21.613970 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1428 04:41:21.617643 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1429 04:41:21.620770 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1430 04:41:21.624849 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1431 04:41:21.631662 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1432 04:41:21.634085 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1433 04:41:21.637194 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1434 04:41:21.640916 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1435 04:41:21.643828 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1436 04:41:21.651344 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1437 04:41:21.651474 ==
1438 04:41:21.654217 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 04:41:21.657492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1440 04:41:21.657607 ==
1441 04:41:21.657702 DQS Delay:
1442 04:41:21.660564 DQS0 = 0, DQS1 = 0
1443 04:41:21.660681 DQM Delay:
1444 04:41:21.663919 DQM0 = 81, DQM1 = 72
1445 04:41:21.664003 DQ Delay:
1446 04:41:21.667683 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1447 04:41:21.670556 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1448 04:41:21.674741 DQ8 =53, DQ9 =69, DQ10 =77, DQ11 =69
1449 04:41:21.677573 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1450 04:41:21.677659
1451 04:41:21.677724
1452 04:41:21.677784 ==
1453 04:41:21.680432 Dram Type= 6, Freq= 0, CH_1, rank 0
1454 04:41:21.683788 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1455 04:41:21.687748 ==
1456 04:41:21.687833
1457 04:41:21.687897
1458 04:41:21.687956 TX Vref Scan disable
1459 04:41:21.690327 == TX Byte 0 ==
1460 04:41:21.694203 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1461 04:41:21.697182 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1462 04:41:21.700983 == TX Byte 1 ==
1463 04:41:21.704026 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1464 04:41:21.707356 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1465 04:41:21.707441 ==
1466 04:41:21.710545 Dram Type= 6, Freq= 0, CH_1, rank 0
1467 04:41:21.717749 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1468 04:41:21.717849 ==
1469 04:41:21.728950 TX Vref=22, minBit 0, minWin=28, winSum=453
1470 04:41:21.732390 TX Vref=24, minBit 0, minWin=28, winSum=454
1471 04:41:21.736045 TX Vref=26, minBit 7, minWin=28, winSum=459
1472 04:41:21.739220 TX Vref=28, minBit 9, minWin=28, winSum=462
1473 04:41:21.742164 TX Vref=30, minBit 9, minWin=28, winSum=463
1474 04:41:21.749328 TX Vref=32, minBit 3, minWin=28, winSum=461
1475 04:41:21.752048 [TxChooseVref] Worse bit 9, Min win 28, Win sum 463, Final Vref 30
1476 04:41:21.752138
1477 04:41:21.755511 Final TX Range 1 Vref 30
1478 04:41:21.755595
1479 04:41:21.755659 ==
1480 04:41:21.759129 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 04:41:21.762504 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1482 04:41:21.762591 ==
1483 04:41:21.765547
1484 04:41:21.765628
1485 04:41:21.765692 TX Vref Scan disable
1486 04:41:21.768818 == TX Byte 0 ==
1487 04:41:21.772555 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1488 04:41:21.775713 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1489 04:41:21.778977 == TX Byte 1 ==
1490 04:41:21.782216 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1491 04:41:21.785225 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1492 04:41:21.788726
1493 04:41:21.788812 [DATLAT]
1494 04:41:21.788876 Freq=800, CH1 RK0
1495 04:41:21.788936
1496 04:41:21.793022 DATLAT Default: 0xa
1497 04:41:21.793105 0, 0xFFFF, sum = 0
1498 04:41:21.795739 1, 0xFFFF, sum = 0
1499 04:41:21.795823 2, 0xFFFF, sum = 0
1500 04:41:21.798764 3, 0xFFFF, sum = 0
1501 04:41:21.798847 4, 0xFFFF, sum = 0
1502 04:41:21.801759 5, 0xFFFF, sum = 0
1503 04:41:21.805538 6, 0xFFFF, sum = 0
1504 04:41:21.805625 7, 0xFFFF, sum = 0
1505 04:41:21.805692 8, 0x0, sum = 1
1506 04:41:21.808609 9, 0x0, sum = 2
1507 04:41:21.808692 10, 0x0, sum = 3
1508 04:41:21.812072 11, 0x0, sum = 4
1509 04:41:21.812154 best_step = 9
1510 04:41:21.812216
1511 04:41:21.812301 ==
1512 04:41:21.815633 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 04:41:21.821916 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1514 04:41:21.822019 ==
1515 04:41:21.822085 RX Vref Scan: 1
1516 04:41:21.822143
1517 04:41:21.825649 Set Vref Range= 32 -> 127
1518 04:41:21.825733
1519 04:41:21.828754 RX Vref 32 -> 127, step: 1
1520 04:41:21.828907
1521 04:41:21.832363 RX Delay -111 -> 252, step: 8
1522 04:41:21.832446
1523 04:41:21.836339 Set Vref, RX VrefLevel [Byte0]: 32
1524 04:41:21.838402 [Byte1]: 32
1525 04:41:21.838483
1526 04:41:21.842044 Set Vref, RX VrefLevel [Byte0]: 33
1527 04:41:21.845262 [Byte1]: 33
1528 04:41:21.845344
1529 04:41:21.848532 Set Vref, RX VrefLevel [Byte0]: 34
1530 04:41:21.852433 [Byte1]: 34
1531 04:41:21.852537
1532 04:41:21.855319 Set Vref, RX VrefLevel [Byte0]: 35
1533 04:41:21.858563 [Byte1]: 35
1534 04:41:21.862928
1535 04:41:21.863045 Set Vref, RX VrefLevel [Byte0]: 36
1536 04:41:21.865789 [Byte1]: 36
1537 04:41:21.870526
1538 04:41:21.870613 Set Vref, RX VrefLevel [Byte0]: 37
1539 04:41:21.874198 [Byte1]: 37
1540 04:41:21.877759
1541 04:41:21.877846 Set Vref, RX VrefLevel [Byte0]: 38
1542 04:41:21.881938 [Byte1]: 38
1543 04:41:21.885547
1544 04:41:21.885634 Set Vref, RX VrefLevel [Byte0]: 39
1545 04:41:21.888924 [Byte1]: 39
1546 04:41:21.893919
1547 04:41:21.894009 Set Vref, RX VrefLevel [Byte0]: 40
1548 04:41:21.896400 [Byte1]: 40
1549 04:41:21.900670
1550 04:41:21.900799 Set Vref, RX VrefLevel [Byte0]: 41
1551 04:41:21.904616 [Byte1]: 41
1552 04:41:21.908628
1553 04:41:21.908744 Set Vref, RX VrefLevel [Byte0]: 42
1554 04:41:21.911938 [Byte1]: 42
1555 04:41:21.916041
1556 04:41:21.916126 Set Vref, RX VrefLevel [Byte0]: 43
1557 04:41:21.919390 [Byte1]: 43
1558 04:41:21.924268
1559 04:41:21.924359 Set Vref, RX VrefLevel [Byte0]: 44
1560 04:41:21.927436 [Byte1]: 44
1561 04:41:21.931518
1562 04:41:21.931626 Set Vref, RX VrefLevel [Byte0]: 45
1563 04:41:21.935336 [Byte1]: 45
1564 04:41:21.939178
1565 04:41:21.939267 Set Vref, RX VrefLevel [Byte0]: 46
1566 04:41:21.942218 [Byte1]: 46
1567 04:41:21.947012
1568 04:41:21.947099 Set Vref, RX VrefLevel [Byte0]: 47
1569 04:41:21.950179 [Byte1]: 47
1570 04:41:21.955045
1571 04:41:21.955142 Set Vref, RX VrefLevel [Byte0]: 48
1572 04:41:21.957831 [Byte1]: 48
1573 04:41:21.962043
1574 04:41:21.962129 Set Vref, RX VrefLevel [Byte0]: 49
1575 04:41:21.965556 [Byte1]: 49
1576 04:41:21.969784
1577 04:41:21.969872 Set Vref, RX VrefLevel [Byte0]: 50
1578 04:41:21.972853 [Byte1]: 50
1579 04:41:21.977586
1580 04:41:21.977671 Set Vref, RX VrefLevel [Byte0]: 51
1581 04:41:21.980724 [Byte1]: 51
1582 04:41:21.986455
1583 04:41:21.986543 Set Vref, RX VrefLevel [Byte0]: 52
1584 04:41:21.989246 [Byte1]: 52
1585 04:41:21.992300
1586 04:41:21.992383 Set Vref, RX VrefLevel [Byte0]: 53
1587 04:41:21.995822 [Byte1]: 53
1588 04:41:22.000377
1589 04:41:22.000464 Set Vref, RX VrefLevel [Byte0]: 54
1590 04:41:22.004043 [Byte1]: 54
1591 04:41:22.007643
1592 04:41:22.007728 Set Vref, RX VrefLevel [Byte0]: 55
1593 04:41:22.011561 [Byte1]: 55
1594 04:41:22.015353
1595 04:41:22.015442 Set Vref, RX VrefLevel [Byte0]: 56
1596 04:41:22.019178 [Byte1]: 56
1597 04:41:22.023298
1598 04:41:22.023386 Set Vref, RX VrefLevel [Byte0]: 57
1599 04:41:22.026472 [Byte1]: 57
1600 04:41:22.030717
1601 04:41:22.030804 Set Vref, RX VrefLevel [Byte0]: 58
1602 04:41:22.034240 [Byte1]: 58
1603 04:41:22.038644
1604 04:41:22.038732 Set Vref, RX VrefLevel [Byte0]: 59
1605 04:41:22.041760 [Byte1]: 59
1606 04:41:22.046151
1607 04:41:22.046237 Set Vref, RX VrefLevel [Byte0]: 60
1608 04:41:22.049680 [Byte1]: 60
1609 04:41:22.054171
1610 04:41:22.054266 Set Vref, RX VrefLevel [Byte0]: 61
1611 04:41:22.057375 [Byte1]: 61
1612 04:41:22.061865
1613 04:41:22.061952 Set Vref, RX VrefLevel [Byte0]: 62
1614 04:41:22.064765 [Byte1]: 62
1615 04:41:22.069075
1616 04:41:22.072424 Set Vref, RX VrefLevel [Byte0]: 63
1617 04:41:22.072509 [Byte1]: 63
1618 04:41:22.077454
1619 04:41:22.077544 Set Vref, RX VrefLevel [Byte0]: 64
1620 04:41:22.081693 [Byte1]: 64
1621 04:41:22.084508
1622 04:41:22.084590 Set Vref, RX VrefLevel [Byte0]: 65
1623 04:41:22.087922 [Byte1]: 65
1624 04:41:22.091944
1625 04:41:22.092027 Set Vref, RX VrefLevel [Byte0]: 66
1626 04:41:22.095723 [Byte1]: 66
1627 04:41:22.099468
1628 04:41:22.099556 Set Vref, RX VrefLevel [Byte0]: 67
1629 04:41:22.102900 [Byte1]: 67
1630 04:41:22.107166
1631 04:41:22.107256 Set Vref, RX VrefLevel [Byte0]: 68
1632 04:41:22.111314 [Byte1]: 68
1633 04:41:22.115075
1634 04:41:22.115166 Set Vref, RX VrefLevel [Byte0]: 69
1635 04:41:22.118513 [Byte1]: 69
1636 04:41:22.122638
1637 04:41:22.122724 Set Vref, RX VrefLevel [Byte0]: 70
1638 04:41:22.126005 [Byte1]: 70
1639 04:41:22.130746
1640 04:41:22.130839 Set Vref, RX VrefLevel [Byte0]: 71
1641 04:41:22.133616 [Byte1]: 71
1642 04:41:22.138016
1643 04:41:22.138103 Set Vref, RX VrefLevel [Byte0]: 72
1644 04:41:22.141065 [Byte1]: 72
1645 04:41:22.145903
1646 04:41:22.145996 Set Vref, RX VrefLevel [Byte0]: 73
1647 04:41:22.148666 [Byte1]: 73
1648 04:41:22.153646
1649 04:41:22.153740 Final RX Vref Byte 0 = 56 to rank0
1650 04:41:22.157323 Final RX Vref Byte 1 = 53 to rank0
1651 04:41:22.159739 Final RX Vref Byte 0 = 56 to rank1
1652 04:41:22.163220 Final RX Vref Byte 1 = 53 to rank1==
1653 04:41:22.166558 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 04:41:22.172908 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1655 04:41:22.173008 ==
1656 04:41:22.173075 DQS Delay:
1657 04:41:22.173135 DQS0 = 0, DQS1 = 0
1658 04:41:22.176150 DQM Delay:
1659 04:41:22.176231 DQM0 = 79, DQM1 = 72
1660 04:41:22.179810 DQ Delay:
1661 04:41:22.183264 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
1662 04:41:22.186715 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1663 04:41:22.186801 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1664 04:41:22.193095 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1665 04:41:22.193183
1666 04:41:22.193247
1667 04:41:22.199560 [DQSOSCAuto] RK0, (LSB)MR18= 0x5050, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1668 04:41:22.203513 CH1 RK0: MR19=606, MR18=5050
1669 04:41:22.210095 CH1_RK0: MR19=0x606, MR18=0x5050, DQSOSC=389, MR23=63, INC=97, DEC=65
1670 04:41:22.210198
1671 04:41:22.213361 ----->DramcWriteLeveling(PI) begin...
1672 04:41:22.213450 ==
1673 04:41:22.217303 Dram Type= 6, Freq= 0, CH_1, rank 1
1674 04:41:22.219892 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1675 04:41:22.219976 ==
1676 04:41:22.222898 Write leveling (Byte 0): 26 => 26
1677 04:41:22.226267 Write leveling (Byte 1): 24 => 24
1678 04:41:22.230531 DramcWriteLeveling(PI) end<-----
1679 04:41:22.230625
1680 04:41:22.230691 ==
1681 04:41:22.233508 Dram Type= 6, Freq= 0, CH_1, rank 1
1682 04:41:22.236136 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1683 04:41:22.236222 ==
1684 04:41:22.239659 [Gating] SW mode calibration
1685 04:41:22.246740 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1686 04:41:22.253098 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1687 04:41:22.256137 0 6 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
1688 04:41:22.260092 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1689 04:41:22.266515 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1690 04:41:22.270367 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1691 04:41:22.272652 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1692 04:41:22.279423 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1693 04:41:22.282684 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1694 04:41:22.286206 0 6 28 | B1->B0 | 2424 3232 | 0 0 | (0 0) (1 1)
1695 04:41:22.292969 0 7 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1696 04:41:22.296070 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1697 04:41:22.300296 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1698 04:41:22.306564 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1699 04:41:22.309991 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1700 04:41:22.313360 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1701 04:41:22.319983 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1702 04:41:22.322819 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1703 04:41:22.326104 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1704 04:41:22.329569 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1705 04:41:22.335923 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1706 04:41:22.340645 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1707 04:41:22.342738 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1708 04:41:22.349780 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1709 04:41:22.352685 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1710 04:41:22.356139 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1711 04:41:22.363369 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1712 04:41:22.366041 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1713 04:41:22.369395 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1714 04:41:22.375841 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1715 04:41:22.380315 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 04:41:22.382545 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 04:41:22.389798 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 04:41:22.392692 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1719 04:41:22.396110 Total UI for P1: 0, mck2ui 16
1720 04:41:22.399700 best dqsien dly found for B0: ( 0, 9, 26)
1721 04:41:22.402460 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1722 04:41:22.406356 Total UI for P1: 0, mck2ui 16
1723 04:41:22.409649 best dqsien dly found for B1: ( 0, 9, 28)
1724 04:41:22.413566 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1725 04:41:22.416492 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1726 04:41:22.416580
1727 04:41:22.423344 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1728 04:41:22.427105 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1729 04:41:22.429452 [Gating] SW calibration Done
1730 04:41:22.429541 ==
1731 04:41:22.432666 Dram Type= 6, Freq= 0, CH_1, rank 1
1732 04:41:22.435831 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1733 04:41:22.435918 ==
1734 04:41:22.435984 RX Vref Scan: 0
1735 04:41:22.436045
1736 04:41:22.439259 RX Vref 0 -> 0, step: 1
1737 04:41:22.439344
1738 04:41:22.442391 RX Delay -130 -> 252, step: 16
1739 04:41:22.446175 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1740 04:41:22.449277 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1741 04:41:22.456664 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1742 04:41:22.459200 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1743 04:41:22.462614 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1744 04:41:22.466336 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1745 04:41:22.469453 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1746 04:41:22.472756 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1747 04:41:22.479349 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1748 04:41:22.482400 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1749 04:41:22.485890 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1750 04:41:22.490219 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1751 04:41:22.495665 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1752 04:41:22.499257 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1753 04:41:22.502833 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1754 04:41:22.506186 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1755 04:41:22.506303 ==
1756 04:41:22.509385 Dram Type= 6, Freq= 0, CH_1, rank 1
1757 04:41:22.512639 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1758 04:41:22.517566 ==
1759 04:41:22.517664 DQS Delay:
1760 04:41:22.517730 DQS0 = 0, DQS1 = 0
1761 04:41:22.519034 DQM Delay:
1762 04:41:22.519116 DQM0 = 82, DQM1 = 72
1763 04:41:22.522536 DQ Delay:
1764 04:41:22.522621 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1765 04:41:22.526420 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1766 04:41:22.529215 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1767 04:41:22.532808 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =85
1768 04:41:22.532917
1769 04:41:22.536024
1770 04:41:22.536116 ==
1771 04:41:22.539123 Dram Type= 6, Freq= 0, CH_1, rank 1
1772 04:41:22.556104 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1773 04:41:22.556260 ==
1774 04:41:22.556330
1775 04:41:22.556392
1776 04:41:22.556451 TX Vref Scan disable
1777 04:41:22.556508 == TX Byte 0 ==
1778 04:41:22.556565 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1779 04:41:22.556817 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1780 04:41:22.556880 == TX Byte 1 ==
1781 04:41:22.562392 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1782 04:41:22.565918 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1783 04:41:22.566031 ==
1784 04:41:22.569158 Dram Type= 6, Freq= 0, CH_1, rank 1
1785 04:41:22.572493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1786 04:41:22.572600 ==
1787 04:41:22.585955 TX Vref=22, minBit 0, minWin=28, winSum=453
1788 04:41:22.589317 TX Vref=24, minBit 0, minWin=28, winSum=454
1789 04:41:22.592652 TX Vref=26, minBit 0, minWin=28, winSum=458
1790 04:41:22.596105 TX Vref=28, minBit 1, minWin=28, winSum=458
1791 04:41:22.599239 TX Vref=30, minBit 0, minWin=28, winSum=459
1792 04:41:22.606083 TX Vref=32, minBit 0, minWin=28, winSum=455
1793 04:41:22.609549 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
1794 04:41:22.609647
1795 04:41:22.612419 Final TX Range 1 Vref 30
1796 04:41:22.612503
1797 04:41:22.612568 ==
1798 04:41:22.616335 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 04:41:22.619988 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1800 04:41:22.620080 ==
1801 04:41:22.620147
1802 04:41:22.622445
1803 04:41:22.622528 TX Vref Scan disable
1804 04:41:22.625833 == TX Byte 0 ==
1805 04:41:22.629366 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1806 04:41:22.636508 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1807 04:41:22.636620 == TX Byte 1 ==
1808 04:41:22.639334 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1809 04:41:22.646951 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1810 04:41:22.647056
1811 04:41:22.647123 [DATLAT]
1812 04:41:22.647184 Freq=800, CH1 RK1
1813 04:41:22.647244
1814 04:41:22.649145 DATLAT Default: 0x9
1815 04:41:22.649228 0, 0xFFFF, sum = 0
1816 04:41:22.653392 1, 0xFFFF, sum = 0
1817 04:41:22.653488 2, 0xFFFF, sum = 0
1818 04:41:22.655744 3, 0xFFFF, sum = 0
1819 04:41:22.655828 4, 0xFFFF, sum = 0
1820 04:41:22.659118 5, 0xFFFF, sum = 0
1821 04:41:22.662382 6, 0xFFFF, sum = 0
1822 04:41:22.662474 7, 0xFFFF, sum = 0
1823 04:41:22.662541 8, 0x0, sum = 1
1824 04:41:22.666115 9, 0x0, sum = 2
1825 04:41:22.666205 10, 0x0, sum = 3
1826 04:41:22.668997 11, 0x0, sum = 4
1827 04:41:22.669084 best_step = 9
1828 04:41:22.669149
1829 04:41:22.669208 ==
1830 04:41:22.672379 Dram Type= 6, Freq= 0, CH_1, rank 1
1831 04:41:22.679909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1832 04:41:22.680040 ==
1833 04:41:22.680106 RX Vref Scan: 0
1834 04:41:22.680166
1835 04:41:22.682709 RX Vref 0 -> 0, step: 1
1836 04:41:22.682797
1837 04:41:22.685775 RX Delay -111 -> 252, step: 8
1838 04:41:22.689058 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1839 04:41:22.693196 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1840 04:41:22.698972 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1841 04:41:22.702243 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1842 04:41:22.705653 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1843 04:41:22.709026 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1844 04:41:22.712991 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1845 04:41:22.715669 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1846 04:41:22.722375 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1847 04:41:22.726821 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1848 04:41:22.728851 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1849 04:41:22.732674 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1850 04:41:22.739509 iDelay=217, Bit 12, Center 84 (-39 ~ 208) 248
1851 04:41:22.742271 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1852 04:41:22.745791 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1853 04:41:22.749096 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1854 04:41:22.749186 ==
1855 04:41:22.752165 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 04:41:22.759142 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1857 04:41:22.759260 ==
1858 04:41:22.759329 DQS Delay:
1859 04:41:22.759390 DQS0 = 0, DQS1 = 0
1860 04:41:22.762837 DQM Delay:
1861 04:41:22.762924 DQM0 = 82, DQM1 = 73
1862 04:41:22.765746 DQ Delay:
1863 04:41:22.769350 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1864 04:41:22.769452 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1865 04:41:22.772468 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1866 04:41:22.775435 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =80
1867 04:41:22.779542
1868 04:41:22.779646
1869 04:41:22.785832 [DQSOSCAuto] RK1, (LSB)MR18= 0x3434, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1870 04:41:22.788863 CH1 RK1: MR19=606, MR18=3434
1871 04:41:22.795206 CH1_RK1: MR19=0x606, MR18=0x3434, DQSOSC=396, MR23=63, INC=94, DEC=62
1872 04:41:22.798753 [RxdqsGatingPostProcess] freq 800
1873 04:41:22.802147 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1874 04:41:22.805269 Pre-setting of DQS Precalculation
1875 04:41:22.812907 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1876 04:41:22.818781 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1877 04:41:22.825682 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1878 04:41:22.825799
1879 04:41:22.825867
1880 04:41:22.828870 [Calibration Summary] 1600 Mbps
1881 04:41:22.828956 CH 0, Rank 0
1882 04:41:22.831983 SW Impedance : PASS
1883 04:41:22.835693 DUTY Scan : NO K
1884 04:41:22.835782 ZQ Calibration : PASS
1885 04:41:22.838662 Jitter Meter : NO K
1886 04:41:22.838749 CBT Training : PASS
1887 04:41:22.842881 Write leveling : PASS
1888 04:41:22.845709 RX DQS gating : PASS
1889 04:41:22.845797 RX DQ/DQS(RDDQC) : PASS
1890 04:41:22.849328 TX DQ/DQS : PASS
1891 04:41:22.852173 RX DATLAT : PASS
1892 04:41:22.852264 RX DQ/DQS(Engine): PASS
1893 04:41:22.855623 TX OE : NO K
1894 04:41:22.855709 All Pass.
1895 04:41:22.855774
1896 04:41:22.858726 CH 0, Rank 1
1897 04:41:22.858810 SW Impedance : PASS
1898 04:41:22.862157 DUTY Scan : NO K
1899 04:41:22.865382 ZQ Calibration : PASS
1900 04:41:22.865470 Jitter Meter : NO K
1901 04:41:22.868836 CBT Training : PASS
1902 04:41:22.872012 Write leveling : PASS
1903 04:41:22.872095 RX DQS gating : PASS
1904 04:41:22.876106 RX DQ/DQS(RDDQC) : PASS
1905 04:41:22.878776 TX DQ/DQS : PASS
1906 04:41:22.878861 RX DATLAT : PASS
1907 04:41:22.882177 RX DQ/DQS(Engine): PASS
1908 04:41:22.882262 TX OE : NO K
1909 04:41:22.885448 All Pass.
1910 04:41:22.885534
1911 04:41:22.885599 CH 1, Rank 0
1912 04:41:22.888660 SW Impedance : PASS
1913 04:41:22.888786 DUTY Scan : NO K
1914 04:41:22.891735 ZQ Calibration : PASS
1915 04:41:22.895309 Jitter Meter : NO K
1916 04:41:22.895407 CBT Training : PASS
1917 04:41:22.899053 Write leveling : PASS
1918 04:41:22.902146 RX DQS gating : PASS
1919 04:41:22.902246 RX DQ/DQS(RDDQC) : PASS
1920 04:41:22.905343 TX DQ/DQS : PASS
1921 04:41:22.908665 RX DATLAT : PASS
1922 04:41:22.908798 RX DQ/DQS(Engine): PASS
1923 04:41:22.912149 TX OE : NO K
1924 04:41:22.912240 All Pass.
1925 04:41:22.912307
1926 04:41:22.916463 CH 1, Rank 1
1927 04:41:22.916555 SW Impedance : PASS
1928 04:41:22.918595 DUTY Scan : NO K
1929 04:41:22.922245 ZQ Calibration : PASS
1930 04:41:22.922333 Jitter Meter : NO K
1931 04:41:22.925841 CBT Training : PASS
1932 04:41:22.925926 Write leveling : PASS
1933 04:41:22.929327 RX DQS gating : PASS
1934 04:41:22.932247 RX DQ/DQS(RDDQC) : PASS
1935 04:41:22.932332 TX DQ/DQS : PASS
1936 04:41:22.935510 RX DATLAT : PASS
1937 04:41:22.938867 RX DQ/DQS(Engine): PASS
1938 04:41:22.939000 TX OE : NO K
1939 04:41:22.943920 All Pass.
1940 04:41:22.944056
1941 04:41:22.944211 DramC Write-DBI off
1942 04:41:22.945451 PER_BANK_REFRESH: Hybrid Mode
1943 04:41:22.945531 TX_TRACKING: ON
1944 04:41:22.949339 [GetDramInforAfterCalByMRR] Vendor 6.
1945 04:41:22.955380 [GetDramInforAfterCalByMRR] Revision 606.
1946 04:41:22.959447 [GetDramInforAfterCalByMRR] Revision 2 0.
1947 04:41:22.959591 MR0 0x3939
1948 04:41:22.959706 MR8 0x1111
1949 04:41:22.962517 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1950 04:41:22.962599
1951 04:41:22.965672 MR0 0x3939
1952 04:41:22.965804 MR8 0x1111
1953 04:41:22.968936 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1954 04:41:22.969018
1955 04:41:22.979041 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1956 04:41:22.982045 [FAST_K] Save calibration result to emmc
1957 04:41:22.985406 [FAST_K] Save calibration result to emmc
1958 04:41:22.988972 dram_init: config_dvfs: 1
1959 04:41:22.991920 dramc_set_vcore_voltage set vcore to 662500
1960 04:41:22.995327 Read voltage for 1200, 2
1961 04:41:22.995417 Vio18 = 0
1962 04:41:22.995483 Vcore = 662500
1963 04:41:22.998902 Vdram = 0
1964 04:41:22.998986 Vddq = 0
1965 04:41:22.999051 Vmddr = 0
1966 04:41:23.005656 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1967 04:41:23.008971 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1968 04:41:23.012176 MEM_TYPE=3, freq_sel=15
1969 04:41:23.015681 sv_algorithm_assistance_LP4_1600
1970 04:41:23.019090 ============ PULL DRAM RESETB DOWN ============
1971 04:41:23.022866 ========== PULL DRAM RESETB DOWN end =========
1972 04:41:23.028591 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1973 04:41:23.032116 ===================================
1974 04:41:23.032227 LPDDR4 DRAM CONFIGURATION
1975 04:41:23.035500 ===================================
1976 04:41:23.039433 EX_ROW_EN[0] = 0x0
1977 04:41:23.042811 EX_ROW_EN[1] = 0x0
1978 04:41:23.042903 LP4Y_EN = 0x0
1979 04:41:23.045651 WORK_FSP = 0x0
1980 04:41:23.045737 WL = 0x4
1981 04:41:23.049471 RL = 0x4
1982 04:41:23.049559 BL = 0x2
1983 04:41:23.052033 RPST = 0x0
1984 04:41:23.052122 RD_PRE = 0x0
1985 04:41:23.055850 WR_PRE = 0x1
1986 04:41:23.055934 WR_PST = 0x0
1987 04:41:23.059283 DBI_WR = 0x0
1988 04:41:23.059367 DBI_RD = 0x0
1989 04:41:23.062105 OTF = 0x1
1990 04:41:23.065221 ===================================
1991 04:41:23.068489 ===================================
1992 04:41:23.068628 ANA top config
1993 04:41:23.072396 ===================================
1994 04:41:23.076044 DLL_ASYNC_EN = 0
1995 04:41:23.079648 ALL_SLAVE_EN = 0
1996 04:41:23.079739 NEW_RANK_MODE = 1
1997 04:41:23.082493 DLL_IDLE_MODE = 1
1998 04:41:23.085339 LP45_APHY_COMB_EN = 1
1999 04:41:23.088689 TX_ODT_DIS = 1
2000 04:41:23.092409 NEW_8X_MODE = 1
2001 04:41:23.096154 ===================================
2002 04:41:23.096243 ===================================
2003 04:41:23.099070 data_rate = 2400
2004 04:41:23.102896 CKR = 1
2005 04:41:23.105460 DQ_P2S_RATIO = 8
2006 04:41:23.109105 ===================================
2007 04:41:23.112418 CA_P2S_RATIO = 8
2008 04:41:23.116027 DQ_CA_OPEN = 0
2009 04:41:23.116114 DQ_SEMI_OPEN = 0
2010 04:41:23.118984 CA_SEMI_OPEN = 0
2011 04:41:23.122448 CA_FULL_RATE = 0
2012 04:41:23.125481 DQ_CKDIV4_EN = 0
2013 04:41:23.129272 CA_CKDIV4_EN = 0
2014 04:41:23.132563 CA_PREDIV_EN = 0
2015 04:41:23.135714 PH8_DLY = 17
2016 04:41:23.135815 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2017 04:41:23.138833 DQ_AAMCK_DIV = 4
2018 04:41:23.142082 CA_AAMCK_DIV = 4
2019 04:41:23.145591 CA_ADMCK_DIV = 4
2020 04:41:23.148995 DQ_TRACK_CA_EN = 0
2021 04:41:23.152428 CA_PICK = 1200
2022 04:41:23.152526 CA_MCKIO = 1200
2023 04:41:23.155697 MCKIO_SEMI = 0
2024 04:41:23.159643 PLL_FREQ = 2366
2025 04:41:23.162022 DQ_UI_PI_RATIO = 32
2026 04:41:23.166002 CA_UI_PI_RATIO = 0
2027 04:41:23.168454 ===================================
2028 04:41:23.172600 ===================================
2029 04:41:23.175225 memory_type:LPDDR4
2030 04:41:23.175311 GP_NUM : 10
2031 04:41:23.179132 SRAM_EN : 1
2032 04:41:23.179218 MD32_EN : 0
2033 04:41:23.181937 ===================================
2034 04:41:23.185433 [ANA_INIT] >>>>>>>>>>>>>>
2035 04:41:23.188638 <<<<<< [CONFIGURE PHASE]: ANA_TX
2036 04:41:23.192405 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2037 04:41:23.195282 ===================================
2038 04:41:23.198737 data_rate = 2400,PCW = 0X5b00
2039 04:41:23.202032 ===================================
2040 04:41:23.205362 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2041 04:41:23.211950 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2042 04:41:23.215495 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2043 04:41:23.221774 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2044 04:41:23.225243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2045 04:41:23.229456 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2046 04:41:23.229574 [ANA_INIT] flow start
2047 04:41:23.232315 [ANA_INIT] PLL >>>>>>>>
2048 04:41:23.235427 [ANA_INIT] PLL <<<<<<<<
2049 04:41:23.235534 [ANA_INIT] MIDPI >>>>>>>>
2050 04:41:23.239205 [ANA_INIT] MIDPI <<<<<<<<
2051 04:41:23.242482 [ANA_INIT] DLL >>>>>>>>
2052 04:41:23.242567 [ANA_INIT] DLL <<<<<<<<
2053 04:41:23.245319 [ANA_INIT] flow end
2054 04:41:23.248313 ============ LP4 DIFF to SE enter ============
2055 04:41:23.252217 ============ LP4 DIFF to SE exit ============
2056 04:41:23.255592 [ANA_INIT] <<<<<<<<<<<<<
2057 04:41:23.258452 [Flow] Enable top DCM control >>>>>
2058 04:41:23.262138 [Flow] Enable top DCM control <<<<<
2059 04:41:23.265337 Enable DLL master slave shuffle
2060 04:41:23.271638 ==============================================================
2061 04:41:23.271732 Gating Mode config
2062 04:41:23.279104 ==============================================================
2063 04:41:23.279201 Config description:
2064 04:41:23.288937 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2065 04:41:23.295205 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2066 04:41:23.301936 SELPH_MODE 0: By rank 1: By Phase
2067 04:41:23.305512 ==============================================================
2068 04:41:23.308671 GAT_TRACK_EN = 1
2069 04:41:23.311780 RX_GATING_MODE = 2
2070 04:41:23.315285 RX_GATING_TRACK_MODE = 2
2071 04:41:23.318224 SELPH_MODE = 1
2072 04:41:23.321671 PICG_EARLY_EN = 1
2073 04:41:23.324998 VALID_LAT_VALUE = 1
2074 04:41:23.331519 ==============================================================
2075 04:41:23.334952 Enter into Gating configuration >>>>
2076 04:41:23.338485 Exit from Gating configuration <<<<
2077 04:41:23.338574 Enter into DVFS_PRE_config >>>>>
2078 04:41:23.351712 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2079 04:41:23.355324 Exit from DVFS_PRE_config <<<<<
2080 04:41:23.359350 Enter into PICG configuration >>>>
2081 04:41:23.361921 Exit from PICG configuration <<<<
2082 04:41:23.362010 [RX_INPUT] configuration >>>>>
2083 04:41:23.364985 [RX_INPUT] configuration <<<<<
2084 04:41:23.371722 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2085 04:41:23.375347 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2086 04:41:23.382010 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2087 04:41:23.388487 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2088 04:41:23.394966 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2089 04:41:23.401818 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2090 04:41:23.405088 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2091 04:41:23.408773 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2092 04:41:23.415082 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2093 04:41:23.418833 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2094 04:41:23.421494 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2095 04:41:23.424766 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2096 04:41:23.428344 ===================================
2097 04:41:23.432122 LPDDR4 DRAM CONFIGURATION
2098 04:41:23.435207 ===================================
2099 04:41:23.438225 EX_ROW_EN[0] = 0x0
2100 04:41:23.438315 EX_ROW_EN[1] = 0x0
2101 04:41:23.441799 LP4Y_EN = 0x0
2102 04:41:23.441883 WORK_FSP = 0x0
2103 04:41:23.444916 WL = 0x4
2104 04:41:23.445000 RL = 0x4
2105 04:41:23.448619 BL = 0x2
2106 04:41:23.448716 RPST = 0x0
2107 04:41:23.451620 RD_PRE = 0x0
2108 04:41:23.451711 WR_PRE = 0x1
2109 04:41:23.454897 WR_PST = 0x0
2110 04:41:23.454997 DBI_WR = 0x0
2111 04:41:23.458469 DBI_RD = 0x0
2112 04:41:23.458555 OTF = 0x1
2113 04:41:23.461812 ===================================
2114 04:41:23.468222 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2115 04:41:23.471494 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2116 04:41:23.474858 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2117 04:41:23.477979 ===================================
2118 04:41:23.481442 LPDDR4 DRAM CONFIGURATION
2119 04:41:23.485550 ===================================
2120 04:41:23.488294 EX_ROW_EN[0] = 0x10
2121 04:41:23.488383 EX_ROW_EN[1] = 0x0
2122 04:41:23.491350 LP4Y_EN = 0x0
2123 04:41:23.491434 WORK_FSP = 0x0
2124 04:41:23.495426 WL = 0x4
2125 04:41:23.495510 RL = 0x4
2126 04:41:23.498121 BL = 0x2
2127 04:41:23.498205 RPST = 0x0
2128 04:41:23.501462 RD_PRE = 0x0
2129 04:41:23.501546 WR_PRE = 0x1
2130 04:41:23.505239 WR_PST = 0x0
2131 04:41:23.505324 DBI_WR = 0x0
2132 04:41:23.508390 DBI_RD = 0x0
2133 04:41:23.508474 OTF = 0x1
2134 04:41:23.511312 ===================================
2135 04:41:23.518423 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2136 04:41:23.518531 ==
2137 04:41:23.522630 Dram Type= 6, Freq= 0, CH_0, rank 0
2138 04:41:23.525142 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2139 04:41:23.528365 ==
2140 04:41:23.528454 [Duty_Offset_Calibration]
2141 04:41:23.531606 B0:0 B1:2 CA:1
2142 04:41:23.531691
2143 04:41:23.534780 [DutyScan_Calibration_Flow] k_type=0
2144 04:41:23.543655
2145 04:41:23.543795 ==CLK 0==
2146 04:41:23.546430 Final CLK duty delay cell = 0
2147 04:41:23.550303 [0] MAX Duty = 5093%(X100), DQS PI = 12
2148 04:41:23.553376 [0] MIN Duty = 4938%(X100), DQS PI = 54
2149 04:41:23.553473 [0] AVG Duty = 5015%(X100)
2150 04:41:23.556627
2151 04:41:23.560039 CH0 CLK Duty spec in!! Max-Min= 155%
2152 04:41:23.563464 [DutyScan_Calibration_Flow] ====Done====
2153 04:41:23.563557
2154 04:41:23.566680 [DutyScan_Calibration_Flow] k_type=1
2155 04:41:23.583174
2156 04:41:23.583324 ==DQS 0 ==
2157 04:41:23.586001 Final DQS duty delay cell = 0
2158 04:41:23.589368 [0] MAX Duty = 5125%(X100), DQS PI = 30
2159 04:41:23.592899 [0] MIN Duty = 5031%(X100), DQS PI = 6
2160 04:41:23.592988 [0] AVG Duty = 5078%(X100)
2161 04:41:23.596022
2162 04:41:23.596106 ==DQS 1 ==
2163 04:41:23.599162 Final DQS duty delay cell = 0
2164 04:41:23.603340 [0] MAX Duty = 5031%(X100), DQS PI = 52
2165 04:41:23.605690 [0] MIN Duty = 4906%(X100), DQS PI = 16
2166 04:41:23.605777 [0] AVG Duty = 4968%(X100)
2167 04:41:23.609215
2168 04:41:23.612465 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2169 04:41:23.612547
2170 04:41:23.616167 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2171 04:41:23.619380 [DutyScan_Calibration_Flow] ====Done====
2172 04:41:23.619465
2173 04:41:23.622230 [DutyScan_Calibration_Flow] k_type=3
2174 04:41:23.639556
2175 04:41:23.639708 ==DQM 0 ==
2176 04:41:23.642244 Final DQM duty delay cell = 0
2177 04:41:23.645545 [0] MAX Duty = 5187%(X100), DQS PI = 22
2178 04:41:23.648979 [0] MIN Duty = 5000%(X100), DQS PI = 40
2179 04:41:23.652510 [0] AVG Duty = 5093%(X100)
2180 04:41:23.652609
2181 04:41:23.652675 ==DQM 1 ==
2182 04:41:23.655697 Final DQM duty delay cell = 0
2183 04:41:23.658707 [0] MAX Duty = 4969%(X100), DQS PI = 52
2184 04:41:23.662184 [0] MIN Duty = 4813%(X100), DQS PI = 22
2185 04:41:23.665772 [0] AVG Duty = 4891%(X100)
2186 04:41:23.665861
2187 04:41:23.669122 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2188 04:41:23.669206
2189 04:41:23.672419 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2190 04:41:23.676205 [DutyScan_Calibration_Flow] ====Done====
2191 04:41:23.676290
2192 04:41:23.679075 [DutyScan_Calibration_Flow] k_type=2
2193 04:41:23.694196
2194 04:41:23.694341 ==DQ 0 ==
2195 04:41:23.697503 Final DQ duty delay cell = -4
2196 04:41:23.701204 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2197 04:41:23.703634 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2198 04:41:23.707858 [-4] AVG Duty = 4937%(X100)
2199 04:41:23.707949
2200 04:41:23.708013 ==DQ 1 ==
2201 04:41:23.710766 Final DQ duty delay cell = -4
2202 04:41:23.714126 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2203 04:41:23.717205 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2204 04:41:23.720627 [-4] AVG Duty = 4969%(X100)
2205 04:41:23.720741
2206 04:41:23.724884 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2207 04:41:23.724970
2208 04:41:23.727633 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2209 04:41:23.730587 [DutyScan_Calibration_Flow] ====Done====
2210 04:41:23.730668 ==
2211 04:41:23.734175 Dram Type= 6, Freq= 0, CH_1, rank 0
2212 04:41:23.737334 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2213 04:41:23.737436 ==
2214 04:41:23.740666 [Duty_Offset_Calibration]
2215 04:41:23.740780 B0:0 B1:5 CA:-5
2216 04:41:23.740844
2217 04:41:23.743712 [DutyScan_Calibration_Flow] k_type=0
2218 04:41:23.755031
2219 04:41:23.755170 ==CLK 0==
2220 04:41:23.758263 Final CLK duty delay cell = 0
2221 04:41:23.761470 [0] MAX Duty = 5094%(X100), DQS PI = 24
2222 04:41:23.765133 [0] MIN Duty = 4907%(X100), DQS PI = 2
2223 04:41:23.765223 [0] AVG Duty = 5000%(X100)
2224 04:41:23.768321
2225 04:41:23.768419 CH1 CLK Duty spec in!! Max-Min= 187%
2226 04:41:23.774421 [DutyScan_Calibration_Flow] ====Done====
2227 04:41:23.774516
2228 04:41:23.777506 [DutyScan_Calibration_Flow] k_type=1
2229 04:41:23.793857
2230 04:41:23.794006 ==DQS 0 ==
2231 04:41:23.796428 Final DQS duty delay cell = 0
2232 04:41:23.799993 [0] MAX Duty = 5125%(X100), DQS PI = 16
2233 04:41:23.802968 [0] MIN Duty = 4875%(X100), DQS PI = 40
2234 04:41:23.806112 [0] AVG Duty = 5000%(X100)
2235 04:41:23.806197
2236 04:41:23.806260 ==DQS 1 ==
2237 04:41:23.809945 Final DQS duty delay cell = -4
2238 04:41:23.812672 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2239 04:41:23.816894 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2240 04:41:23.819475 [-4] AVG Duty = 4953%(X100)
2241 04:41:23.819559
2242 04:41:23.823085 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2243 04:41:23.823170
2244 04:41:23.826300 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2245 04:41:23.829566 [DutyScan_Calibration_Flow] ====Done====
2246 04:41:23.829651
2247 04:41:23.832605 [DutyScan_Calibration_Flow] k_type=3
2248 04:41:23.848513
2249 04:41:23.848652 ==DQM 0 ==
2250 04:41:23.851379 Final DQM duty delay cell = -4
2251 04:41:23.855171 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2252 04:41:23.858024 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2253 04:41:23.861610 [-4] AVG Duty = 4953%(X100)
2254 04:41:23.861699
2255 04:41:23.861764 ==DQM 1 ==
2256 04:41:23.865445 Final DQM duty delay cell = -4
2257 04:41:23.868343 [-4] MAX Duty = 5094%(X100), DQS PI = 22
2258 04:41:23.871515 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2259 04:41:23.874685 [-4] AVG Duty = 5000%(X100)
2260 04:41:23.874769
2261 04:41:23.878156 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2262 04:41:23.878240
2263 04:41:23.881523 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2264 04:41:23.885320 [DutyScan_Calibration_Flow] ====Done====
2265 04:41:23.885410
2266 04:41:23.888694 [DutyScan_Calibration_Flow] k_type=2
2267 04:41:23.906154
2268 04:41:23.906306 ==DQ 0 ==
2269 04:41:23.908751 Final DQ duty delay cell = 0
2270 04:41:23.912353 [0] MAX Duty = 5062%(X100), DQS PI = 0
2271 04:41:23.915612 [0] MIN Duty = 4938%(X100), DQS PI = 44
2272 04:41:23.915698 [0] AVG Duty = 5000%(X100)
2273 04:41:23.915764
2274 04:41:23.919243 ==DQ 1 ==
2275 04:41:23.922041 Final DQ duty delay cell = 0
2276 04:41:23.925750 [0] MAX Duty = 5031%(X100), DQS PI = 8
2277 04:41:23.929224 [0] MIN Duty = 4907%(X100), DQS PI = 0
2278 04:41:23.929314 [0] AVG Duty = 4969%(X100)
2279 04:41:23.929380
2280 04:41:23.932463 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2281 04:41:23.932555
2282 04:41:23.935281 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2283 04:41:23.942066 [DutyScan_Calibration_Flow] ====Done====
2284 04:41:23.945076 nWR fixed to 30
2285 04:41:23.945170 [ModeRegInit_LP4] CH0 RK0
2286 04:41:23.948448 [ModeRegInit_LP4] CH0 RK1
2287 04:41:23.952677 [ModeRegInit_LP4] CH1 RK0
2288 04:41:23.952828 [ModeRegInit_LP4] CH1 RK1
2289 04:41:23.955751 match AC timing 6
2290 04:41:23.959123 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2291 04:41:23.962458 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2292 04:41:23.968462 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2293 04:41:23.972024 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2294 04:41:23.978414 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2295 04:41:23.978523 ==
2296 04:41:23.981796 Dram Type= 6, Freq= 0, CH_0, rank 0
2297 04:41:23.985119 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2298 04:41:23.985205 ==
2299 04:41:23.991862 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2300 04:41:23.995359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2301 04:41:24.005269 [CA 0] Center 39 (9~70) winsize 62
2302 04:41:24.008243 [CA 1] Center 39 (8~70) winsize 63
2303 04:41:24.011567 [CA 2] Center 36 (5~67) winsize 63
2304 04:41:24.015401 [CA 3] Center 35 (4~66) winsize 63
2305 04:41:24.018075 [CA 4] Center 34 (3~65) winsize 63
2306 04:41:24.021858 [CA 5] Center 33 (3~64) winsize 62
2307 04:41:24.021948
2308 04:41:24.025589 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2309 04:41:24.025673
2310 04:41:24.028728 [CATrainingPosCal] consider 1 rank data
2311 04:41:24.031510 u2DelayCellTimex100 = 270/100 ps
2312 04:41:24.034770 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2313 04:41:24.038469 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2314 04:41:24.045138 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2315 04:41:24.048875 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2316 04:41:24.051766 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2317 04:41:24.054902 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2318 04:41:24.055002
2319 04:41:24.059306 CA PerBit enable=1, Macro0, CA PI delay=33
2320 04:41:24.059392
2321 04:41:24.062065 [CBTSetCACLKResult] CA Dly = 33
2322 04:41:24.062150 CS Dly: 7 (0~38)
2323 04:41:24.064784 ==
2324 04:41:24.064867 Dram Type= 6, Freq= 0, CH_0, rank 1
2325 04:41:24.071943 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2326 04:41:24.072042 ==
2327 04:41:24.075094 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2328 04:41:24.081516 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2329 04:41:24.090635 [CA 0] Center 39 (8~70) winsize 63
2330 04:41:24.094164 [CA 1] Center 38 (8~69) winsize 62
2331 04:41:24.097541 [CA 2] Center 35 (5~66) winsize 62
2332 04:41:24.100392 [CA 3] Center 35 (4~66) winsize 63
2333 04:41:24.104086 [CA 4] Center 33 (3~64) winsize 62
2334 04:41:24.107020 [CA 5] Center 34 (3~65) winsize 63
2335 04:41:24.107111
2336 04:41:24.110577 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2337 04:41:24.110664
2338 04:41:24.113970 [CATrainingPosCal] consider 2 rank data
2339 04:41:24.117300 u2DelayCellTimex100 = 270/100 ps
2340 04:41:24.120495 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2341 04:41:24.124199 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2342 04:41:24.131121 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2343 04:41:24.133714 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2344 04:41:24.136904 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2345 04:41:24.140064 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2346 04:41:24.140149
2347 04:41:24.143603 CA PerBit enable=1, Macro0, CA PI delay=33
2348 04:41:24.143686
2349 04:41:24.147191 [CBTSetCACLKResult] CA Dly = 33
2350 04:41:24.147274 CS Dly: 7 (0~39)
2351 04:41:24.147338
2352 04:41:24.150101 ----->DramcWriteLeveling(PI) begin...
2353 04:41:24.153666 ==
2354 04:41:24.156839 Dram Type= 6, Freq= 0, CH_0, rank 0
2355 04:41:24.160403 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2356 04:41:24.160492 ==
2357 04:41:24.163930 Write leveling (Byte 0): 26 => 26
2358 04:41:24.167354 Write leveling (Byte 1): 26 => 26
2359 04:41:24.170323 DramcWriteLeveling(PI) end<-----
2360 04:41:24.170407
2361 04:41:24.170471 ==
2362 04:41:24.173741 Dram Type= 6, Freq= 0, CH_0, rank 0
2363 04:41:24.176970 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2364 04:41:24.177058 ==
2365 04:41:24.180688 [Gating] SW mode calibration
2366 04:41:24.187342 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2367 04:41:24.193396 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2368 04:41:24.197387 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2369 04:41:24.199983 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2370 04:41:24.203637 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2371 04:41:24.210217 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2372 04:41:24.213534 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2373 04:41:24.216882 0 11 20 | B1->B0 | 2f2f 2d2d | 1 0 | (1 0) (1 0)
2374 04:41:24.223365 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2375 04:41:24.226859 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2376 04:41:24.230271 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2377 04:41:24.237234 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2378 04:41:24.240092 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2379 04:41:24.243221 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2380 04:41:24.250085 0 12 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2381 04:41:24.254272 0 12 20 | B1->B0 | 3e3e 4444 | 0 0 | (0 0) (0 0)
2382 04:41:24.257054 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2383 04:41:24.263550 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2384 04:41:24.267143 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2385 04:41:24.270113 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2386 04:41:24.276895 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2387 04:41:24.280410 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2388 04:41:24.283438 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2389 04:41:24.289671 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2390 04:41:24.294348 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2391 04:41:24.296354 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2392 04:41:24.303130 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2393 04:41:24.306881 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2394 04:41:24.309833 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2395 04:41:24.316583 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2396 04:41:24.320602 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2397 04:41:24.323665 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2398 04:41:24.326511 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2399 04:41:24.333484 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2400 04:41:24.336675 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2401 04:41:24.340254 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2402 04:41:24.346876 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2403 04:41:24.350769 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 04:41:24.353362 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2405 04:41:24.360390 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2406 04:41:24.364126 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2407 04:41:24.366317 Total UI for P1: 0, mck2ui 16
2408 04:41:24.370274 best dqsien dly found for B0: ( 0, 15, 18)
2409 04:41:24.373184 Total UI for P1: 0, mck2ui 16
2410 04:41:24.376910 best dqsien dly found for B1: ( 0, 15, 20)
2411 04:41:24.379991 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2412 04:41:24.383316 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2413 04:41:24.383406
2414 04:41:24.387006 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2415 04:41:24.390324 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2416 04:41:24.393785 [Gating] SW calibration Done
2417 04:41:24.393872 ==
2418 04:41:24.397002 Dram Type= 6, Freq= 0, CH_0, rank 0
2419 04:41:24.399809 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2420 04:41:24.403874 ==
2421 04:41:24.403967 RX Vref Scan: 0
2422 04:41:24.404035
2423 04:41:24.406878 RX Vref 0 -> 0, step: 1
2424 04:41:24.406961
2425 04:41:24.409759 RX Delay -40 -> 252, step: 8
2426 04:41:24.414298 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2427 04:41:24.417064 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2428 04:41:24.419891 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2429 04:41:24.423259 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2430 04:41:24.430044 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2431 04:41:24.433409 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2432 04:41:24.437244 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2433 04:41:24.439725 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2434 04:41:24.443323 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2435 04:41:24.446896 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2436 04:41:24.453637 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2437 04:41:24.456594 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2438 04:41:24.459605 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2439 04:41:24.463700 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2440 04:41:24.469924 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2441 04:41:24.473584 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2442 04:41:24.473685 ==
2443 04:41:24.476756 Dram Type= 6, Freq= 0, CH_0, rank 0
2444 04:41:24.479970 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2445 04:41:24.480056 ==
2446 04:41:24.480122 DQS Delay:
2447 04:41:24.482935 DQS0 = 0, DQS1 = 0
2448 04:41:24.483017 DQM Delay:
2449 04:41:24.486746 DQM0 = 115, DQM1 = 106
2450 04:41:24.486831 DQ Delay:
2451 04:41:24.489718 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2452 04:41:24.493265 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2453 04:41:24.496521 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2454 04:41:24.499751 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =119
2455 04:41:24.503168
2456 04:41:24.503253
2457 04:41:24.503319 ==
2458 04:41:24.506715 Dram Type= 6, Freq= 0, CH_0, rank 0
2459 04:41:24.509620 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2460 04:41:24.509707 ==
2461 04:41:24.509774
2462 04:41:24.509834
2463 04:41:24.513278 TX Vref Scan disable
2464 04:41:24.513362 == TX Byte 0 ==
2465 04:41:24.519386 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2466 04:41:24.523284 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2467 04:41:24.523376 == TX Byte 1 ==
2468 04:41:24.529541 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2469 04:41:24.533169 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2470 04:41:24.533291 ==
2471 04:41:24.536530 Dram Type= 6, Freq= 0, CH_0, rank 0
2472 04:41:24.539388 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2473 04:41:24.539477 ==
2474 04:41:24.551634 TX Vref=22, minBit 9, minWin=25, winSum=412
2475 04:41:24.555129 TX Vref=24, minBit 10, minWin=25, winSum=418
2476 04:41:24.558565 TX Vref=26, minBit 10, minWin=25, winSum=420
2477 04:41:24.561896 TX Vref=28, minBit 3, minWin=26, winSum=426
2478 04:41:24.565103 TX Vref=30, minBit 3, minWin=26, winSum=425
2479 04:41:24.571562 TX Vref=32, minBit 5, minWin=26, winSum=425
2480 04:41:24.575044 [TxChooseVref] Worse bit 3, Min win 26, Win sum 426, Final Vref 28
2481 04:41:24.575147
2482 04:41:24.578229 Final TX Range 1 Vref 28
2483 04:41:24.578317
2484 04:41:24.578383 ==
2485 04:41:24.581330 Dram Type= 6, Freq= 0, CH_0, rank 0
2486 04:41:24.585237 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2487 04:41:24.587967 ==
2488 04:41:24.588055
2489 04:41:24.588119
2490 04:41:24.588180 TX Vref Scan disable
2491 04:41:24.591780 == TX Byte 0 ==
2492 04:41:24.594973 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2493 04:41:24.598403 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2494 04:41:24.602130 == TX Byte 1 ==
2495 04:41:24.604994 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2496 04:41:24.609793 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2497 04:41:24.612489
2498 04:41:24.612579 [DATLAT]
2499 04:41:24.612645 Freq=1200, CH0 RK0
2500 04:41:24.612732
2501 04:41:24.615688 DATLAT Default: 0xd
2502 04:41:24.615771 0, 0xFFFF, sum = 0
2503 04:41:24.618416 1, 0xFFFF, sum = 0
2504 04:41:24.618501 2, 0xFFFF, sum = 0
2505 04:41:24.621417 3, 0xFFFF, sum = 0
2506 04:41:24.624716 4, 0xFFFF, sum = 0
2507 04:41:24.624832 5, 0xFFFF, sum = 0
2508 04:41:24.627927 6, 0xFFFF, sum = 0
2509 04:41:24.628012 7, 0xFFFF, sum = 0
2510 04:41:24.631273 8, 0xFFFF, sum = 0
2511 04:41:24.631360 9, 0xFFFF, sum = 0
2512 04:41:24.634826 10, 0xFFFF, sum = 0
2513 04:41:24.634930 11, 0x0, sum = 1
2514 04:41:24.638503 12, 0x0, sum = 2
2515 04:41:24.638589 13, 0x0, sum = 3
2516 04:41:24.641351 14, 0x0, sum = 4
2517 04:41:24.641436 best_step = 12
2518 04:41:24.641502
2519 04:41:24.641562 ==
2520 04:41:24.644596 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 04:41:24.648136 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2522 04:41:24.648222 ==
2523 04:41:24.651446 RX Vref Scan: 1
2524 04:41:24.651530
2525 04:41:24.654761 Set Vref Range= 32 -> 127
2526 04:41:24.654851
2527 04:41:24.654919 RX Vref 32 -> 127, step: 1
2528 04:41:24.654980
2529 04:41:24.658058 RX Delay -21 -> 252, step: 4
2530 04:41:24.658143
2531 04:41:24.661269 Set Vref, RX VrefLevel [Byte0]: 32
2532 04:41:24.664890 [Byte1]: 32
2533 04:41:24.668093
2534 04:41:24.668179 Set Vref, RX VrefLevel [Byte0]: 33
2535 04:41:24.672166 [Byte1]: 33
2536 04:41:24.676733
2537 04:41:24.676843 Set Vref, RX VrefLevel [Byte0]: 34
2538 04:41:24.679321 [Byte1]: 34
2539 04:41:24.684053
2540 04:41:24.684145 Set Vref, RX VrefLevel [Byte0]: 35
2541 04:41:24.688060 [Byte1]: 35
2542 04:41:24.691909
2543 04:41:24.691997 Set Vref, RX VrefLevel [Byte0]: 36
2544 04:41:24.695545 [Byte1]: 36
2545 04:41:24.700170
2546 04:41:24.700263 Set Vref, RX VrefLevel [Byte0]: 37
2547 04:41:24.703329 [Byte1]: 37
2548 04:41:24.707662
2549 04:41:24.707754 Set Vref, RX VrefLevel [Byte0]: 38
2550 04:41:24.711786 [Byte1]: 38
2551 04:41:24.715941
2552 04:41:24.716033 Set Vref, RX VrefLevel [Byte0]: 39
2553 04:41:24.719106 [Byte1]: 39
2554 04:41:24.723807
2555 04:41:24.723899 Set Vref, RX VrefLevel [Byte0]: 40
2556 04:41:24.727228 [Byte1]: 40
2557 04:41:24.731406
2558 04:41:24.731498 Set Vref, RX VrefLevel [Byte0]: 41
2559 04:41:24.734872 [Byte1]: 41
2560 04:41:24.740233
2561 04:41:24.740331 Set Vref, RX VrefLevel [Byte0]: 42
2562 04:41:24.743115 [Byte1]: 42
2563 04:41:24.747335
2564 04:41:24.747428 Set Vref, RX VrefLevel [Byte0]: 43
2565 04:41:24.751203 [Byte1]: 43
2566 04:41:24.756043
2567 04:41:24.756144 Set Vref, RX VrefLevel [Byte0]: 44
2568 04:41:24.758613 [Byte1]: 44
2569 04:41:24.764004
2570 04:41:24.764089 Set Vref, RX VrefLevel [Byte0]: 45
2571 04:41:24.766532 [Byte1]: 45
2572 04:41:24.771532
2573 04:41:24.771622 Set Vref, RX VrefLevel [Byte0]: 46
2574 04:41:24.774991 [Byte1]: 46
2575 04:41:24.779422
2576 04:41:24.779514 Set Vref, RX VrefLevel [Byte0]: 47
2577 04:41:24.782532 [Byte1]: 47
2578 04:41:24.787415
2579 04:41:24.787505 Set Vref, RX VrefLevel [Byte0]: 48
2580 04:41:24.791368 [Byte1]: 48
2581 04:41:24.795331
2582 04:41:24.795420 Set Vref, RX VrefLevel [Byte0]: 49
2583 04:41:24.798650 [Byte1]: 49
2584 04:41:24.803197
2585 04:41:24.803291 Set Vref, RX VrefLevel [Byte0]: 50
2586 04:41:24.806990 [Byte1]: 50
2587 04:41:24.810992
2588 04:41:24.811083 Set Vref, RX VrefLevel [Byte0]: 51
2589 04:41:24.814404 [Byte1]: 51
2590 04:41:24.819046
2591 04:41:24.819141 Set Vref, RX VrefLevel [Byte0]: 52
2592 04:41:24.822261 [Byte1]: 52
2593 04:41:24.826798
2594 04:41:24.826899 Set Vref, RX VrefLevel [Byte0]: 53
2595 04:41:24.830215 [Byte1]: 53
2596 04:41:24.834635
2597 04:41:24.834741 Set Vref, RX VrefLevel [Byte0]: 54
2598 04:41:24.837848 [Byte1]: 54
2599 04:41:24.842397
2600 04:41:24.846049 Set Vref, RX VrefLevel [Byte0]: 55
2601 04:41:24.846147 [Byte1]: 55
2602 04:41:24.850343
2603 04:41:24.850435 Set Vref, RX VrefLevel [Byte0]: 56
2604 04:41:24.853456 [Byte1]: 56
2605 04:41:24.859186
2606 04:41:24.859304 Set Vref, RX VrefLevel [Byte0]: 57
2607 04:41:24.861509 [Byte1]: 57
2608 04:41:24.866151
2609 04:41:24.866246 Set Vref, RX VrefLevel [Byte0]: 58
2610 04:41:24.869719 [Byte1]: 58
2611 04:41:24.874030
2612 04:41:24.874130 Set Vref, RX VrefLevel [Byte0]: 59
2613 04:41:24.877421 [Byte1]: 59
2614 04:41:24.881989
2615 04:41:24.882084 Set Vref, RX VrefLevel [Byte0]: 60
2616 04:41:24.885754 [Byte1]: 60
2617 04:41:24.890584
2618 04:41:24.890685 Set Vref, RX VrefLevel [Byte0]: 61
2619 04:41:24.893229 [Byte1]: 61
2620 04:41:24.898138
2621 04:41:24.898236 Set Vref, RX VrefLevel [Byte0]: 62
2622 04:41:24.901797 [Byte1]: 62
2623 04:41:24.905763
2624 04:41:24.905859 Set Vref, RX VrefLevel [Byte0]: 63
2625 04:41:24.909320 [Byte1]: 63
2626 04:41:24.914073
2627 04:41:24.914171 Set Vref, RX VrefLevel [Byte0]: 64
2628 04:41:24.917510 [Byte1]: 64
2629 04:41:24.921653
2630 04:41:24.921745 Set Vref, RX VrefLevel [Byte0]: 65
2631 04:41:24.924998 [Byte1]: 65
2632 04:41:24.929680
2633 04:41:24.929772 Set Vref, RX VrefLevel [Byte0]: 66
2634 04:41:24.933149 [Byte1]: 66
2635 04:41:24.937855
2636 04:41:24.937952 Final RX Vref Byte 0 = 50 to rank0
2637 04:41:24.941587 Final RX Vref Byte 1 = 45 to rank0
2638 04:41:24.944197 Final RX Vref Byte 0 = 50 to rank1
2639 04:41:24.947484 Final RX Vref Byte 1 = 45 to rank1==
2640 04:41:24.951502 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 04:41:24.957367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2642 04:41:24.957478 ==
2643 04:41:24.957545 DQS Delay:
2644 04:41:24.957605 DQS0 = 0, DQS1 = 0
2645 04:41:24.961042 DQM Delay:
2646 04:41:24.961127 DQM0 = 114, DQM1 = 104
2647 04:41:24.964586 DQ Delay:
2648 04:41:24.967396 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2649 04:41:24.970988 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =122
2650 04:41:24.974299 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2651 04:41:24.978243 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2652 04:41:24.978338
2653 04:41:24.978402
2654 04:41:24.984907 [DQSOSCAuto] RK0, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2655 04:41:24.987720 CH0 RK0: MR19=404, MR18=707
2656 04:41:24.993897 CH0_RK0: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
2657 04:41:24.994006
2658 04:41:24.997217 ----->DramcWriteLeveling(PI) begin...
2659 04:41:24.997311 ==
2660 04:41:25.000762 Dram Type= 6, Freq= 0, CH_0, rank 1
2661 04:41:25.004607 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2662 04:41:25.004721 ==
2663 04:41:25.007011 Write leveling (Byte 0): 29 => 29
2664 04:41:25.010365 Write leveling (Byte 1): 25 => 25
2665 04:41:25.013787 DramcWriteLeveling(PI) end<-----
2666 04:41:25.013876
2667 04:41:25.013941 ==
2668 04:41:25.017311 Dram Type= 6, Freq= 0, CH_0, rank 1
2669 04:41:25.023840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2670 04:41:25.023937 ==
2671 04:41:25.024005 [Gating] SW mode calibration
2672 04:41:25.033865 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2673 04:41:25.037264 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2674 04:41:25.040558 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2675 04:41:25.047826 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2676 04:41:25.051622 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2677 04:41:25.053643 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2678 04:41:25.060890 0 11 16 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
2679 04:41:25.064023 0 11 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2680 04:41:25.067957 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2681 04:41:25.074064 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2682 04:41:25.076971 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2683 04:41:25.080475 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2684 04:41:25.087226 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2685 04:41:25.091493 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2686 04:41:25.094122 0 12 16 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
2687 04:41:25.100642 0 12 20 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2688 04:41:25.103499 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2689 04:41:25.106875 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2690 04:41:25.113685 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2691 04:41:25.116982 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2692 04:41:25.120253 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2693 04:41:25.126935 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2694 04:41:25.130340 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2695 04:41:25.134144 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2696 04:41:25.140094 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2697 04:41:25.143436 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2698 04:41:25.147001 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2699 04:41:25.150341 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2700 04:41:25.156842 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2701 04:41:25.160982 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2702 04:41:25.164198 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2703 04:41:25.170090 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2704 04:41:25.173677 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2705 04:41:25.176944 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2706 04:41:25.183948 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2707 04:41:25.187037 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2708 04:41:25.190497 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 04:41:25.197056 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 04:41:25.200576 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2711 04:41:25.203923 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2712 04:41:25.206894 Total UI for P1: 0, mck2ui 16
2713 04:41:25.210413 best dqsien dly found for B0: ( 0, 15, 16)
2714 04:41:25.216840 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2715 04:41:25.216946 Total UI for P1: 0, mck2ui 16
2716 04:41:25.223860 best dqsien dly found for B1: ( 0, 15, 18)
2717 04:41:25.227045 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2718 04:41:25.230037 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2719 04:41:25.230127
2720 04:41:25.233856 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2721 04:41:25.237025 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2722 04:41:25.240282 [Gating] SW calibration Done
2723 04:41:25.240371 ==
2724 04:41:25.243782 Dram Type= 6, Freq= 0, CH_0, rank 1
2725 04:41:25.246995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2726 04:41:25.247083 ==
2727 04:41:25.250554 RX Vref Scan: 0
2728 04:41:25.250638
2729 04:41:25.250703 RX Vref 0 -> 0, step: 1
2730 04:41:25.250763
2731 04:41:25.253591 RX Delay -40 -> 252, step: 8
2732 04:41:25.257027 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2733 04:41:25.263963 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2734 04:41:25.267009 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2735 04:41:25.270131 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2736 04:41:25.274047 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2737 04:41:25.277006 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2738 04:41:25.283716 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2739 04:41:25.287250 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2740 04:41:25.290024 iDelay=200, Bit 8, Center 95 (32 ~ 159) 128
2741 04:41:25.294319 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2742 04:41:25.297353 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2743 04:41:25.300362 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2744 04:41:25.307463 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2745 04:41:25.309977 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2746 04:41:25.313222 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2747 04:41:25.316906 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2748 04:41:25.317000 ==
2749 04:41:25.320163 Dram Type= 6, Freq= 0, CH_0, rank 1
2750 04:41:25.326436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2751 04:41:25.326541 ==
2752 04:41:25.326610 DQS Delay:
2753 04:41:25.330122 DQS0 = 0, DQS1 = 0
2754 04:41:25.330211 DQM Delay:
2755 04:41:25.333298 DQM0 = 116, DQM1 = 106
2756 04:41:25.333388 DQ Delay:
2757 04:41:25.336625 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111
2758 04:41:25.340651 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123
2759 04:41:25.343324 DQ8 =95, DQ9 =91, DQ10 =107, DQ11 =99
2760 04:41:25.347173 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2761 04:41:25.347264
2762 04:41:25.347329
2763 04:41:25.347390 ==
2764 04:41:25.350739 Dram Type= 6, Freq= 0, CH_0, rank 1
2765 04:41:25.354150 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2766 04:41:25.356739 ==
2767 04:41:25.356849
2768 04:41:25.356915
2769 04:41:25.356976 TX Vref Scan disable
2770 04:41:25.359956 == TX Byte 0 ==
2771 04:41:25.363526 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2772 04:41:25.367625 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2773 04:41:25.370035 == TX Byte 1 ==
2774 04:41:25.373286 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2775 04:41:25.376671 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2776 04:41:25.376799 ==
2777 04:41:25.380156 Dram Type= 6, Freq= 0, CH_0, rank 1
2778 04:41:25.386814 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2779 04:41:25.386916 ==
2780 04:41:25.398121 TX Vref=22, minBit 8, minWin=25, winSum=416
2781 04:41:25.400872 TX Vref=24, minBit 13, minWin=25, winSum=423
2782 04:41:25.404379 TX Vref=26, minBit 9, minWin=26, winSum=429
2783 04:41:25.407609 TX Vref=28, minBit 9, minWin=26, winSum=432
2784 04:41:25.410814 TX Vref=30, minBit 8, minWin=26, winSum=434
2785 04:41:25.417676 TX Vref=32, minBit 8, minWin=26, winSum=435
2786 04:41:25.420962 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 32
2787 04:41:25.421058
2788 04:41:25.424515 Final TX Range 1 Vref 32
2789 04:41:25.424601
2790 04:41:25.424666 ==
2791 04:41:25.427974 Dram Type= 6, Freq= 0, CH_0, rank 1
2792 04:41:25.431033 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2793 04:41:25.431120 ==
2794 04:41:25.431186
2795 04:41:25.434448
2796 04:41:25.434532 TX Vref Scan disable
2797 04:41:25.437727 == TX Byte 0 ==
2798 04:41:25.441092 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2799 04:41:25.444316 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2800 04:41:25.447526 == TX Byte 1 ==
2801 04:41:25.451112 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2802 04:41:25.454166 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2803 04:41:25.457739
2804 04:41:25.457838 [DATLAT]
2805 04:41:25.457904 Freq=1200, CH0 RK1
2806 04:41:25.457965
2807 04:41:25.461452 DATLAT Default: 0xc
2808 04:41:25.461536 0, 0xFFFF, sum = 0
2809 04:41:25.464247 1, 0xFFFF, sum = 0
2810 04:41:25.464330 2, 0xFFFF, sum = 0
2811 04:41:25.467691 3, 0xFFFF, sum = 0
2812 04:41:25.467775 4, 0xFFFF, sum = 0
2813 04:41:25.471062 5, 0xFFFF, sum = 0
2814 04:41:25.474266 6, 0xFFFF, sum = 0
2815 04:41:25.474350 7, 0xFFFF, sum = 0
2816 04:41:25.477457 8, 0xFFFF, sum = 0
2817 04:41:25.477540 9, 0xFFFF, sum = 0
2818 04:41:25.480673 10, 0xFFFF, sum = 0
2819 04:41:25.480774 11, 0x0, sum = 1
2820 04:41:25.483983 12, 0x0, sum = 2
2821 04:41:25.484066 13, 0x0, sum = 3
2822 04:41:25.484132 14, 0x0, sum = 4
2823 04:41:25.487509 best_step = 12
2824 04:41:25.487590
2825 04:41:25.487655 ==
2826 04:41:25.490679 Dram Type= 6, Freq= 0, CH_0, rank 1
2827 04:41:25.494260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2828 04:41:25.494345 ==
2829 04:41:25.498245 RX Vref Scan: 0
2830 04:41:25.498327
2831 04:41:25.498392 RX Vref 0 -> 0, step: 1
2832 04:41:25.500787
2833 04:41:25.500869 RX Delay -21 -> 252, step: 4
2834 04:41:25.508273 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2835 04:41:25.511156 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2836 04:41:25.515108 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2837 04:41:25.518084 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2838 04:41:25.521244 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2839 04:41:25.528492 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2840 04:41:25.531296 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2841 04:41:25.534300 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2842 04:41:25.538092 iDelay=199, Bit 8, Center 92 (31 ~ 154) 124
2843 04:41:25.541121 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2844 04:41:25.548996 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2845 04:41:25.551419 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2846 04:41:25.554599 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2847 04:41:25.558305 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2848 04:41:25.561644 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
2849 04:41:25.567905 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2850 04:41:25.568016 ==
2851 04:41:25.571251 Dram Type= 6, Freq= 0, CH_0, rank 1
2852 04:41:25.574646 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2853 04:41:25.574734 ==
2854 04:41:25.574800 DQS Delay:
2855 04:41:25.577665 DQS0 = 0, DQS1 = 0
2856 04:41:25.577748 DQM Delay:
2857 04:41:25.581326 DQM0 = 115, DQM1 = 105
2858 04:41:25.581410 DQ Delay:
2859 04:41:25.584887 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2860 04:41:25.588024 DQ4 =118, DQ5 =108, DQ6 =122, DQ7 =124
2861 04:41:25.592330 DQ8 =92, DQ9 =90, DQ10 =110, DQ11 =96
2862 04:41:25.594313 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2863 04:41:25.594399
2864 04:41:25.594463
2865 04:41:25.604820 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2866 04:41:25.608011 CH0 RK1: MR19=404, MR18=E0E
2867 04:41:25.611411 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2868 04:41:25.614923 [RxdqsGatingPostProcess] freq 1200
2869 04:41:25.621134 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2870 04:41:25.624179 Pre-setting of DQS Precalculation
2871 04:41:25.628118 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2872 04:41:25.628229 ==
2873 04:41:25.631262 Dram Type= 6, Freq= 0, CH_1, rank 0
2874 04:41:25.637818 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2875 04:41:25.637927 ==
2876 04:41:25.641193 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2877 04:41:25.647985 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2878 04:41:25.656768 [CA 0] Center 37 (7~68) winsize 62
2879 04:41:25.659522 [CA 1] Center 37 (7~68) winsize 62
2880 04:41:25.663534 [CA 2] Center 34 (4~65) winsize 62
2881 04:41:25.666560 [CA 3] Center 33 (3~64) winsize 62
2882 04:41:25.669798 [CA 4] Center 32 (2~63) winsize 62
2883 04:41:25.673154 [CA 5] Center 32 (1~63) winsize 63
2884 04:41:25.673247
2885 04:41:25.676129 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2886 04:41:25.676215
2887 04:41:25.679627 [CATrainingPosCal] consider 1 rank data
2888 04:41:25.683146 u2DelayCellTimex100 = 270/100 ps
2889 04:41:25.686515 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2890 04:41:25.689831 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2891 04:41:25.696487 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2892 04:41:25.700123 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2893 04:41:25.703306 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2894 04:41:25.706529 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2895 04:41:25.706615
2896 04:41:25.709653 CA PerBit enable=1, Macro0, CA PI delay=32
2897 04:41:25.709738
2898 04:41:25.713050 [CBTSetCACLKResult] CA Dly = 32
2899 04:41:25.713137 CS Dly: 5 (0~36)
2900 04:41:25.716212 ==
2901 04:41:25.716299 Dram Type= 6, Freq= 0, CH_1, rank 1
2902 04:41:25.723640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2903 04:41:25.723726 ==
2904 04:41:25.726333 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2905 04:41:25.732873 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2906 04:41:25.741828 [CA 0] Center 37 (7~68) winsize 62
2907 04:41:25.744909 [CA 1] Center 37 (7~68) winsize 62
2908 04:41:25.748160 [CA 2] Center 34 (4~65) winsize 62
2909 04:41:25.751502 [CA 3] Center 33 (3~64) winsize 62
2910 04:41:25.755263 [CA 4] Center 32 (2~63) winsize 62
2911 04:41:25.758122 [CA 5] Center 32 (1~63) winsize 63
2912 04:41:25.758206
2913 04:41:25.761673 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2914 04:41:25.761755
2915 04:41:25.764992 [CATrainingPosCal] consider 2 rank data
2916 04:41:25.769032 u2DelayCellTimex100 = 270/100 ps
2917 04:41:25.771728 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2918 04:41:25.775730 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2919 04:41:25.781511 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2920 04:41:25.785296 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2921 04:41:25.788263 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2922 04:41:25.791896 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2923 04:41:25.791978
2924 04:41:25.795074 CA PerBit enable=1, Macro0, CA PI delay=32
2925 04:41:25.795156
2926 04:41:25.798131 [CBTSetCACLKResult] CA Dly = 32
2927 04:41:25.798212 CS Dly: 6 (0~38)
2928 04:41:25.798278
2929 04:41:25.801661 ----->DramcWriteLeveling(PI) begin...
2930 04:41:25.804816 ==
2931 04:41:25.804898 Dram Type= 6, Freq= 0, CH_1, rank 0
2932 04:41:25.812181 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2933 04:41:25.812263 ==
2934 04:41:25.815248 Write leveling (Byte 0): 22 => 22
2935 04:41:25.818796 Write leveling (Byte 1): 21 => 21
2936 04:41:25.821892 DramcWriteLeveling(PI) end<-----
2937 04:41:25.821973
2938 04:41:25.822037 ==
2939 04:41:25.824715 Dram Type= 6, Freq= 0, CH_1, rank 0
2940 04:41:25.828568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2941 04:41:25.828675 ==
2942 04:41:25.832057 [Gating] SW mode calibration
2943 04:41:25.838005 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2944 04:41:25.841407 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2945 04:41:25.848005 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2946 04:41:25.851884 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2947 04:41:25.854875 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2948 04:41:25.861685 0 11 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2949 04:41:25.864749 0 11 16 | B1->B0 | 3232 2b2b | 0 0 | (0 0) (0 1)
2950 04:41:25.868318 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2951 04:41:25.874558 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2952 04:41:25.877828 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2953 04:41:25.881631 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2954 04:41:25.888379 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2955 04:41:25.891741 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2956 04:41:25.895201 0 12 12 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
2957 04:41:25.901257 0 12 16 | B1->B0 | 3131 4545 | 0 0 | (0 0) (0 0)
2958 04:41:25.904583 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2959 04:41:25.908312 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2960 04:41:25.914805 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 04:41:25.917867 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2962 04:41:25.921780 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 04:41:25.928070 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 04:41:25.932464 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2965 04:41:25.935489 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2966 04:41:25.938006 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2967 04:41:25.944979 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 04:41:25.948507 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 04:41:25.952245 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 04:41:25.958888 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 04:41:25.961857 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 04:41:25.964700 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 04:41:25.971516 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 04:41:25.975044 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 04:41:25.978078 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 04:41:25.985137 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 04:41:25.988049 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 04:41:25.991249 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 04:41:25.998154 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 04:41:26.001625 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2981 04:41:26.004178 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2982 04:41:26.010920 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2983 04:41:26.011006 Total UI for P1: 0, mck2ui 16
2984 04:41:26.017608 best dqsien dly found for B0: ( 0, 15, 14)
2985 04:41:26.020930 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2986 04:41:26.024529 Total UI for P1: 0, mck2ui 16
2987 04:41:26.027887 best dqsien dly found for B1: ( 0, 15, 18)
2988 04:41:26.031287 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
2989 04:41:26.034393 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2990 04:41:26.034510
2991 04:41:26.037849 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
2992 04:41:26.041235 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2993 04:41:26.045240 [Gating] SW calibration Done
2994 04:41:26.045321 ==
2995 04:41:26.047578 Dram Type= 6, Freq= 0, CH_1, rank 0
2996 04:41:26.051230 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2997 04:41:26.055454 ==
2998 04:41:26.055535 RX Vref Scan: 0
2999 04:41:26.055600
3000 04:41:26.057573 RX Vref 0 -> 0, step: 1
3001 04:41:26.057659
3002 04:41:26.057726 RX Delay -40 -> 252, step: 8
3003 04:41:26.064963 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3004 04:41:26.069307 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3005 04:41:26.071437 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3006 04:41:26.074412 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3007 04:41:26.078603 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3008 04:41:26.084504 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3009 04:41:26.087778 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3010 04:41:26.092037 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3011 04:41:26.095011 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3012 04:41:26.098796 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3013 04:41:26.105263 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3014 04:41:26.108525 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3015 04:41:26.111713 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3016 04:41:26.114677 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3017 04:41:26.117699 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3018 04:41:26.124563 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3019 04:41:26.124647 ==
3020 04:41:26.128033 Dram Type= 6, Freq= 0, CH_1, rank 0
3021 04:41:26.130888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3022 04:41:26.130973 ==
3023 04:41:26.131037 DQS Delay:
3024 04:41:26.134814 DQS0 = 0, DQS1 = 0
3025 04:41:26.134897 DQM Delay:
3026 04:41:26.138386 DQM0 = 115, DQM1 = 110
3027 04:41:26.138470 DQ Delay:
3028 04:41:26.141572 DQ0 =115, DQ1 =107, DQ2 =107, DQ3 =115
3029 04:41:26.145279 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3030 04:41:26.148128 DQ8 =91, DQ9 =99, DQ10 =111, DQ11 =103
3031 04:41:26.151815 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3032 04:41:26.151898
3033 04:41:26.151963
3034 04:41:26.154524 ==
3035 04:41:26.157839 Dram Type= 6, Freq= 0, CH_1, rank 0
3036 04:41:26.161992 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3037 04:41:26.162077 ==
3038 04:41:26.162143
3039 04:41:26.162207
3040 04:41:26.164938 TX Vref Scan disable
3041 04:41:26.165020 == TX Byte 0 ==
3042 04:41:26.167583 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3043 04:41:26.174523 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3044 04:41:26.174606 == TX Byte 1 ==
3045 04:41:26.178472 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3046 04:41:26.184602 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3047 04:41:26.184684 ==
3048 04:41:26.187967 Dram Type= 6, Freq= 0, CH_1, rank 0
3049 04:41:26.191028 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3050 04:41:26.191110 ==
3051 04:41:26.203266 TX Vref=22, minBit 9, minWin=25, winSum=420
3052 04:41:26.206065 TX Vref=24, minBit 9, minWin=25, winSum=421
3053 04:41:26.209381 TX Vref=26, minBit 1, minWin=26, winSum=431
3054 04:41:26.212874 TX Vref=28, minBit 8, minWin=26, winSum=430
3055 04:41:26.216165 TX Vref=30, minBit 8, minWin=26, winSum=431
3056 04:41:26.219953 TX Vref=32, minBit 9, minWin=26, winSum=433
3057 04:41:26.226182 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 32
3058 04:41:26.226268
3059 04:41:26.229312 Final TX Range 1 Vref 32
3060 04:41:26.229395
3061 04:41:26.229459 ==
3062 04:41:26.233246 Dram Type= 6, Freq= 0, CH_1, rank 0
3063 04:41:26.236003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3064 04:41:26.236086 ==
3065 04:41:26.236151
3066 04:41:26.240120
3067 04:41:26.240202 TX Vref Scan disable
3068 04:41:26.242990 == TX Byte 0 ==
3069 04:41:26.246687 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3070 04:41:26.249506 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3071 04:41:26.252915 == TX Byte 1 ==
3072 04:41:26.256792 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3073 04:41:26.261479 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3074 04:41:26.261564
3075 04:41:26.262946 [DATLAT]
3076 04:41:26.263027 Freq=1200, CH1 RK0
3077 04:41:26.263093
3078 04:41:26.266705 DATLAT Default: 0xd
3079 04:41:26.266792 0, 0xFFFF, sum = 0
3080 04:41:26.269313 1, 0xFFFF, sum = 0
3081 04:41:26.269396 2, 0xFFFF, sum = 0
3082 04:41:26.272652 3, 0xFFFF, sum = 0
3083 04:41:26.272790 4, 0xFFFF, sum = 0
3084 04:41:26.276381 5, 0xFFFF, sum = 0
3085 04:41:26.276490 6, 0xFFFF, sum = 0
3086 04:41:26.280024 7, 0xFFFF, sum = 0
3087 04:41:26.280107 8, 0xFFFF, sum = 0
3088 04:41:26.282672 9, 0xFFFF, sum = 0
3089 04:41:26.286093 10, 0xFFFF, sum = 0
3090 04:41:26.286176 11, 0x0, sum = 1
3091 04:41:26.286243 12, 0x0, sum = 2
3092 04:41:26.289213 13, 0x0, sum = 3
3093 04:41:26.289296 14, 0x0, sum = 4
3094 04:41:26.292832 best_step = 12
3095 04:41:26.292913
3096 04:41:26.292979 ==
3097 04:41:26.296398 Dram Type= 6, Freq= 0, CH_1, rank 0
3098 04:41:26.300367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3099 04:41:26.300450 ==
3100 04:41:26.302658 RX Vref Scan: 1
3101 04:41:26.302740
3102 04:41:26.302805 Set Vref Range= 32 -> 127
3103 04:41:26.306313
3104 04:41:26.306394 RX Vref 32 -> 127, step: 1
3105 04:41:26.306458
3106 04:41:26.309929 RX Delay -29 -> 252, step: 4
3107 04:41:26.310010
3108 04:41:26.312442 Set Vref, RX VrefLevel [Byte0]: 32
3109 04:41:26.316354 [Byte1]: 32
3110 04:41:26.319690
3111 04:41:26.319772 Set Vref, RX VrefLevel [Byte0]: 33
3112 04:41:26.323049 [Byte1]: 33
3113 04:41:26.326999
3114 04:41:26.327081 Set Vref, RX VrefLevel [Byte0]: 34
3115 04:41:26.330243 [Byte1]: 34
3116 04:41:26.335460
3117 04:41:26.335545 Set Vref, RX VrefLevel [Byte0]: 35
3118 04:41:26.338635 [Byte1]: 35
3119 04:41:26.342964
3120 04:41:26.343046 Set Vref, RX VrefLevel [Byte0]: 36
3121 04:41:26.346442 [Byte1]: 36
3122 04:41:26.350781
3123 04:41:26.350863 Set Vref, RX VrefLevel [Byte0]: 37
3124 04:41:26.354200 [Byte1]: 37
3125 04:41:26.359510
3126 04:41:26.359597 Set Vref, RX VrefLevel [Byte0]: 38
3127 04:41:26.362265 [Byte1]: 38
3128 04:41:26.367367
3129 04:41:26.367451 Set Vref, RX VrefLevel [Byte0]: 39
3130 04:41:26.370939 [Byte1]: 39
3131 04:41:26.374965
3132 04:41:26.375047 Set Vref, RX VrefLevel [Byte0]: 40
3133 04:41:26.378320 [Byte1]: 40
3134 04:41:26.382850
3135 04:41:26.382932 Set Vref, RX VrefLevel [Byte0]: 41
3136 04:41:26.386162 [Byte1]: 41
3137 04:41:26.391076
3138 04:41:26.391157 Set Vref, RX VrefLevel [Byte0]: 42
3139 04:41:26.394045 [Byte1]: 42
3140 04:41:26.398597
3141 04:41:26.398680 Set Vref, RX VrefLevel [Byte0]: 43
3142 04:41:26.402088 [Byte1]: 43
3143 04:41:26.406715
3144 04:41:26.406798 Set Vref, RX VrefLevel [Byte0]: 44
3145 04:41:26.410261 [Byte1]: 44
3146 04:41:26.415039
3147 04:41:26.415123 Set Vref, RX VrefLevel [Byte0]: 45
3148 04:41:26.417840 [Byte1]: 45
3149 04:41:26.423320
3150 04:41:26.423405 Set Vref, RX VrefLevel [Byte0]: 46
3151 04:41:26.425969 [Byte1]: 46
3152 04:41:26.430648
3153 04:41:26.430759 Set Vref, RX VrefLevel [Byte0]: 47
3154 04:41:26.434263 [Byte1]: 47
3155 04:41:26.439990
3156 04:41:26.440076 Set Vref, RX VrefLevel [Byte0]: 48
3157 04:41:26.441869 [Byte1]: 48
3158 04:41:26.446567
3159 04:41:26.446651 Set Vref, RX VrefLevel [Byte0]: 49
3160 04:41:26.450110 [Byte1]: 49
3161 04:41:26.454724
3162 04:41:26.454809 Set Vref, RX VrefLevel [Byte0]: 50
3163 04:41:26.458309 [Byte1]: 50
3164 04:41:26.462598
3165 04:41:26.462686 Set Vref, RX VrefLevel [Byte0]: 51
3166 04:41:26.465481 [Byte1]: 51
3167 04:41:26.470663
3168 04:41:26.470748 Set Vref, RX VrefLevel [Byte0]: 52
3169 04:41:26.473695 [Byte1]: 52
3170 04:41:26.478723
3171 04:41:26.478809 Set Vref, RX VrefLevel [Byte0]: 53
3172 04:41:26.482323 [Byte1]: 53
3173 04:41:26.486345
3174 04:41:26.486428 Set Vref, RX VrefLevel [Byte0]: 54
3175 04:41:26.490089 [Byte1]: 54
3176 04:41:26.494343
3177 04:41:26.494425 Set Vref, RX VrefLevel [Byte0]: 55
3178 04:41:26.497805 [Byte1]: 55
3179 04:41:26.502321
3180 04:41:26.502405 Set Vref, RX VrefLevel [Byte0]: 56
3181 04:41:26.505514 [Byte1]: 56
3182 04:41:26.510868
3183 04:41:26.510952 Set Vref, RX VrefLevel [Byte0]: 57
3184 04:41:26.513984 [Byte1]: 57
3185 04:41:26.518455
3186 04:41:26.518540 Set Vref, RX VrefLevel [Byte0]: 58
3187 04:41:26.521756 [Byte1]: 58
3188 04:41:26.525961
3189 04:41:26.529138 Set Vref, RX VrefLevel [Byte0]: 59
3190 04:41:26.529224 [Byte1]: 59
3191 04:41:26.534135
3192 04:41:26.534220 Set Vref, RX VrefLevel [Byte0]: 60
3193 04:41:26.537478 [Byte1]: 60
3194 04:41:26.542231
3195 04:41:26.542317 Set Vref, RX VrefLevel [Byte0]: 61
3196 04:41:26.545441 [Byte1]: 61
3197 04:41:26.551475
3198 04:41:26.551591 Set Vref, RX VrefLevel [Byte0]: 62
3199 04:41:26.553172 [Byte1]: 62
3200 04:41:26.558133
3201 04:41:26.558251 Set Vref, RX VrefLevel [Byte0]: 63
3202 04:41:26.561602 [Byte1]: 63
3203 04:41:26.567095
3204 04:41:26.567195 Set Vref, RX VrefLevel [Byte0]: 64
3205 04:41:26.569455 [Byte1]: 64
3206 04:41:26.574195
3207 04:41:26.574298 Set Vref, RX VrefLevel [Byte0]: 65
3208 04:41:26.577320 [Byte1]: 65
3209 04:41:26.581828
3210 04:41:26.581928 Set Vref, RX VrefLevel [Byte0]: 66
3211 04:41:26.585080 [Byte1]: 66
3212 04:41:26.589671
3213 04:41:26.589775 Set Vref, RX VrefLevel [Byte0]: 67
3214 04:41:26.593120 [Byte1]: 67
3215 04:41:26.598300
3216 04:41:26.598441 Set Vref, RX VrefLevel [Byte0]: 68
3217 04:41:26.600901 [Byte1]: 68
3218 04:41:26.606481
3219 04:41:26.606584 Set Vref, RX VrefLevel [Byte0]: 69
3220 04:41:26.608992 [Byte1]: 69
3221 04:41:26.614098
3222 04:41:26.614200 Set Vref, RX VrefLevel [Byte0]: 70
3223 04:41:26.616850 [Byte1]: 70
3224 04:41:26.621552
3225 04:41:26.621670 Final RX Vref Byte 0 = 62 to rank0
3226 04:41:26.624954 Final RX Vref Byte 1 = 47 to rank0
3227 04:41:26.628396 Final RX Vref Byte 0 = 62 to rank1
3228 04:41:26.631849 Final RX Vref Byte 1 = 47 to rank1==
3229 04:41:26.635193 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 04:41:26.638648 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3231 04:41:26.642194 ==
3232 04:41:26.642277 DQS Delay:
3233 04:41:26.642342 DQS0 = 0, DQS1 = 0
3234 04:41:26.645779 DQM Delay:
3235 04:41:26.645861 DQM0 = 115, DQM1 = 103
3236 04:41:26.649008 DQ Delay:
3237 04:41:26.651579 DQ0 =120, DQ1 =108, DQ2 =106, DQ3 =114
3238 04:41:26.654931 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3239 04:41:26.658640 DQ8 =84, DQ9 =92, DQ10 =108, DQ11 =98
3240 04:41:26.661848 DQ12 =110, DQ13 =114, DQ14 =112, DQ15 =112
3241 04:41:26.661934
3242 04:41:26.662004
3243 04:41:26.667942 [DQSOSCAuto] RK0, (LSB)MR18= 0x1818, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3244 04:41:26.671595 CH1 RK0: MR19=404, MR18=1818
3245 04:41:26.678287 CH1_RK0: MR19=0x404, MR18=0x1818, DQSOSC=400, MR23=63, INC=40, DEC=27
3246 04:41:26.678374
3247 04:41:26.681908 ----->DramcWriteLeveling(PI) begin...
3248 04:41:26.681993 ==
3249 04:41:26.685418 Dram Type= 6, Freq= 0, CH_1, rank 1
3250 04:41:26.688449 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3251 04:41:26.691398 ==
3252 04:41:26.691483 Write leveling (Byte 0): 21 => 21
3253 04:41:26.694507 Write leveling (Byte 1): 21 => 21
3254 04:41:26.697865 DramcWriteLeveling(PI) end<-----
3255 04:41:26.697948
3256 04:41:26.698013 ==
3257 04:41:26.701553 Dram Type= 6, Freq= 0, CH_1, rank 1
3258 04:41:26.707969 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3259 04:41:26.708056 ==
3260 04:41:26.711288 [Gating] SW mode calibration
3261 04:41:26.718213 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3262 04:41:26.721301 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3263 04:41:26.728172 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3264 04:41:26.731066 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3265 04:41:26.734460 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3266 04:41:26.740823 0 11 12 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
3267 04:41:26.744517 0 11 16 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
3268 04:41:26.748057 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3269 04:41:26.755019 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3270 04:41:26.757578 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3271 04:41:26.760736 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3272 04:41:26.764656 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3273 04:41:26.771245 0 12 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3274 04:41:26.774068 0 12 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
3275 04:41:26.777779 0 12 16 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
3276 04:41:26.784614 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3277 04:41:26.788181 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3278 04:41:26.790827 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3279 04:41:26.797458 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3280 04:41:26.801246 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3281 04:41:26.804761 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3282 04:41:26.811535 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3283 04:41:26.814197 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3284 04:41:26.817622 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 04:41:26.824414 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 04:41:26.827730 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 04:41:26.831243 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 04:41:26.837540 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 04:41:26.840655 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 04:41:26.844151 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 04:41:26.851714 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 04:41:26.854258 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 04:41:26.858005 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 04:41:26.861246 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 04:41:26.867534 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 04:41:26.870840 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 04:41:26.874200 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 04:41:26.881199 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3299 04:41:26.884052 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3300 04:41:26.887581 Total UI for P1: 0, mck2ui 16
3301 04:41:26.891423 best dqsien dly found for B0: ( 0, 15, 12)
3302 04:41:26.894787 Total UI for P1: 0, mck2ui 16
3303 04:41:26.897315 best dqsien dly found for B1: ( 0, 15, 14)
3304 04:41:26.900768 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3305 04:41:26.904656 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3306 04:41:26.904780
3307 04:41:26.907589 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3308 04:41:26.910678 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3309 04:41:26.914053 [Gating] SW calibration Done
3310 04:41:26.914135 ==
3311 04:41:26.917656 Dram Type= 6, Freq= 0, CH_1, rank 1
3312 04:41:26.924352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3313 04:41:26.924436 ==
3314 04:41:26.924501 RX Vref Scan: 0
3315 04:41:26.924561
3316 04:41:26.927846 RX Vref 0 -> 0, step: 1
3317 04:41:26.927928
3318 04:41:26.931133 RX Delay -40 -> 252, step: 8
3319 04:41:26.934442 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3320 04:41:26.937825 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3321 04:41:26.941236 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3322 04:41:26.944321 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3323 04:41:26.950794 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3324 04:41:26.953943 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3325 04:41:26.958031 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3326 04:41:26.960851 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3327 04:41:26.964766 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3328 04:41:26.970979 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
3329 04:41:26.974318 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3330 04:41:26.977437 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3331 04:41:26.981049 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3332 04:41:26.984397 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3333 04:41:26.990940 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3334 04:41:26.994858 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3335 04:41:26.994948 ==
3336 04:41:26.997641 Dram Type= 6, Freq= 0, CH_1, rank 1
3337 04:41:27.001345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3338 04:41:27.001452 ==
3339 04:41:27.001542 DQS Delay:
3340 04:41:27.004556 DQS0 = 0, DQS1 = 0
3341 04:41:27.004658 DQM Delay:
3342 04:41:27.007285 DQM0 = 117, DQM1 = 106
3343 04:41:27.007388 DQ Delay:
3344 04:41:27.011204 DQ0 =119, DQ1 =115, DQ2 =103, DQ3 =119
3345 04:41:27.014008 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =119
3346 04:41:27.017751 DQ8 =91, DQ9 =87, DQ10 =107, DQ11 =99
3347 04:41:27.020855 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3348 04:41:27.020961
3349 04:41:27.024846
3350 04:41:27.024950 ==
3351 04:41:27.027756 Dram Type= 6, Freq= 0, CH_1, rank 1
3352 04:41:27.031579 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3353 04:41:27.031667 ==
3354 04:41:27.031754
3355 04:41:27.031835
3356 04:41:27.034146 TX Vref Scan disable
3357 04:41:27.034230 == TX Byte 0 ==
3358 04:41:27.037413 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3359 04:41:27.044379 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3360 04:41:27.044471 == TX Byte 1 ==
3361 04:41:27.050797 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3362 04:41:27.054231 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3363 04:41:27.054318 ==
3364 04:41:27.057883 Dram Type= 6, Freq= 0, CH_1, rank 1
3365 04:41:27.061141 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3366 04:41:27.061230 ==
3367 04:41:27.072866 TX Vref=22, minBit 9, minWin=25, winSum=423
3368 04:41:27.075895 TX Vref=24, minBit 9, minWin=25, winSum=425
3369 04:41:27.079767 TX Vref=26, minBit 11, minWin=25, winSum=428
3370 04:41:27.083002 TX Vref=28, minBit 8, minWin=26, winSum=431
3371 04:41:27.085898 TX Vref=30, minBit 9, minWin=26, winSum=436
3372 04:41:27.092829 TX Vref=32, minBit 3, minWin=26, winSum=432
3373 04:41:27.095760 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
3374 04:41:27.095867
3375 04:41:27.099326 Final TX Range 1 Vref 30
3376 04:41:27.099431
3377 04:41:27.099521 ==
3378 04:41:27.102577 Dram Type= 6, Freq= 0, CH_1, rank 1
3379 04:41:27.105814 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3380 04:41:27.105922 ==
3381 04:41:27.109755
3382 04:41:27.109862
3383 04:41:27.109953 TX Vref Scan disable
3384 04:41:27.112927 == TX Byte 0 ==
3385 04:41:27.115830 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3386 04:41:27.119548 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3387 04:41:27.122812 == TX Byte 1 ==
3388 04:41:27.125912 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3389 04:41:27.129016 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3390 04:41:27.132318
3391 04:41:27.132403 [DATLAT]
3392 04:41:27.132489 Freq=1200, CH1 RK1
3393 04:41:27.132589
3394 04:41:27.135645 DATLAT Default: 0xc
3395 04:41:27.135729 0, 0xFFFF, sum = 0
3396 04:41:27.139732 1, 0xFFFF, sum = 0
3397 04:41:27.139819 2, 0xFFFF, sum = 0
3398 04:41:27.142712 3, 0xFFFF, sum = 0
3399 04:41:27.142798 4, 0xFFFF, sum = 0
3400 04:41:27.145975 5, 0xFFFF, sum = 0
3401 04:41:27.146061 6, 0xFFFF, sum = 0
3402 04:41:27.149362 7, 0xFFFF, sum = 0
3403 04:41:27.149447 8, 0xFFFF, sum = 0
3404 04:41:27.153041 9, 0xFFFF, sum = 0
3405 04:41:27.156264 10, 0xFFFF, sum = 0
3406 04:41:27.156370 11, 0x0, sum = 1
3407 04:41:27.156462 12, 0x0, sum = 2
3408 04:41:27.159182 13, 0x0, sum = 3
3409 04:41:27.159288 14, 0x0, sum = 4
3410 04:41:27.162751 best_step = 12
3411 04:41:27.162853
3412 04:41:27.162941 ==
3413 04:41:27.166168 Dram Type= 6, Freq= 0, CH_1, rank 1
3414 04:41:27.168953 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3415 04:41:27.169059 ==
3416 04:41:27.172837 RX Vref Scan: 0
3417 04:41:27.172943
3418 04:41:27.173037 RX Vref 0 -> 0, step: 1
3419 04:41:27.175825
3420 04:41:27.175928 RX Delay -29 -> 252, step: 4
3421 04:41:27.182829 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3422 04:41:27.186666 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3423 04:41:27.189731 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3424 04:41:27.193421 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3425 04:41:27.196169 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3426 04:41:27.202962 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3427 04:41:27.206361 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3428 04:41:27.210055 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3429 04:41:27.213312 iDelay=195, Bit 8, Center 86 (19 ~ 154) 136
3430 04:41:27.216579 iDelay=195, Bit 9, Center 90 (23 ~ 158) 136
3431 04:41:27.223479 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3432 04:41:27.227477 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3433 04:41:27.229978 iDelay=195, Bit 12, Center 112 (43 ~ 182) 140
3434 04:41:27.233142 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3435 04:41:27.237331 iDelay=195, Bit 14, Center 112 (43 ~ 182) 140
3436 04:41:27.242804 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3437 04:41:27.242910 ==
3438 04:41:27.246956 Dram Type= 6, Freq= 0, CH_1, rank 1
3439 04:41:27.250031 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3440 04:41:27.250136 ==
3441 04:41:27.250229 DQS Delay:
3442 04:41:27.252784 DQS0 = 0, DQS1 = 0
3443 04:41:27.252890 DQM Delay:
3444 04:41:27.256822 DQM0 = 114, DQM1 = 103
3445 04:41:27.256926 DQ Delay:
3446 04:41:27.259158 DQ0 =114, DQ1 =112, DQ2 =108, DQ3 =112
3447 04:41:27.263294 DQ4 =114, DQ5 =122, DQ6 =120, DQ7 =112
3448 04:41:27.266747 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =98
3449 04:41:27.269508 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =112
3450 04:41:27.269611
3451 04:41:27.269701
3452 04:41:27.279710 [DQSOSCAuto] RK1, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
3453 04:41:27.282720 CH1 RK1: MR19=404, MR18=707
3454 04:41:27.285989 CH1_RK1: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
3455 04:41:27.289502 [RxdqsGatingPostProcess] freq 1200
3456 04:41:27.295979 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3457 04:41:27.299518 Pre-setting of DQS Precalculation
3458 04:41:27.302633 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3459 04:41:27.312377 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3460 04:41:27.319122 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3461 04:41:27.319226
3462 04:41:27.319319
3463 04:41:27.322996 [Calibration Summary] 2400 Mbps
3464 04:41:27.323096 CH 0, Rank 0
3465 04:41:27.325565 SW Impedance : PASS
3466 04:41:27.325667 DUTY Scan : NO K
3467 04:41:27.329469 ZQ Calibration : PASS
3468 04:41:27.332340 Jitter Meter : NO K
3469 04:41:27.332441 CBT Training : PASS
3470 04:41:27.335787 Write leveling : PASS
3471 04:41:27.338993 RX DQS gating : PASS
3472 04:41:27.339094 RX DQ/DQS(RDDQC) : PASS
3473 04:41:27.342845 TX DQ/DQS : PASS
3474 04:41:27.345595 RX DATLAT : PASS
3475 04:41:27.345696 RX DQ/DQS(Engine): PASS
3476 04:41:27.348983 TX OE : NO K
3477 04:41:27.349088 All Pass.
3478 04:41:27.349181
3479 04:41:27.352326 CH 0, Rank 1
3480 04:41:27.352428 SW Impedance : PASS
3481 04:41:27.355698 DUTY Scan : NO K
3482 04:41:27.358805 ZQ Calibration : PASS
3483 04:41:27.358946 Jitter Meter : NO K
3484 04:41:27.362596 CBT Training : PASS
3485 04:41:27.362687 Write leveling : PASS
3486 04:41:27.365870 RX DQS gating : PASS
3487 04:41:27.368992 RX DQ/DQS(RDDQC) : PASS
3488 04:41:27.369074 TX DQ/DQS : PASS
3489 04:41:27.373310 RX DATLAT : PASS
3490 04:41:27.376144 RX DQ/DQS(Engine): PASS
3491 04:41:27.376225 TX OE : NO K
3492 04:41:27.378830 All Pass.
3493 04:41:27.378911
3494 04:41:27.378975 CH 1, Rank 0
3495 04:41:27.383029 SW Impedance : PASS
3496 04:41:27.383111 DUTY Scan : NO K
3497 04:41:27.385852 ZQ Calibration : PASS
3498 04:41:27.389186 Jitter Meter : NO K
3499 04:41:27.389269 CBT Training : PASS
3500 04:41:27.393111 Write leveling : PASS
3501 04:41:27.396105 RX DQS gating : PASS
3502 04:41:27.396187 RX DQ/DQS(RDDQC) : PASS
3503 04:41:27.399868 TX DQ/DQS : PASS
3504 04:41:27.402998 RX DATLAT : PASS
3505 04:41:27.403080 RX DQ/DQS(Engine): PASS
3506 04:41:27.406075 TX OE : NO K
3507 04:41:27.406157 All Pass.
3508 04:41:27.406223
3509 04:41:27.406284 CH 1, Rank 1
3510 04:41:27.409034 SW Impedance : PASS
3511 04:41:27.412235 DUTY Scan : NO K
3512 04:41:27.412318 ZQ Calibration : PASS
3513 04:41:27.415560 Jitter Meter : NO K
3514 04:41:27.420112 CBT Training : PASS
3515 04:41:27.420195 Write leveling : PASS
3516 04:41:27.423080 RX DQS gating : PASS
3517 04:41:27.426067 RX DQ/DQS(RDDQC) : PASS
3518 04:41:27.426150 TX DQ/DQS : PASS
3519 04:41:27.428964 RX DATLAT : PASS
3520 04:41:27.432278 RX DQ/DQS(Engine): PASS
3521 04:41:27.432360 TX OE : NO K
3522 04:41:27.435693 All Pass.
3523 04:41:27.435775
3524 04:41:27.435840 DramC Write-DBI off
3525 04:41:27.439136 PER_BANK_REFRESH: Hybrid Mode
3526 04:41:27.439219 TX_TRACKING: ON
3527 04:41:27.449991 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3528 04:41:27.452639 [FAST_K] Save calibration result to emmc
3529 04:41:27.456105 dramc_set_vcore_voltage set vcore to 650000
3530 04:41:27.459469 Read voltage for 600, 5
3531 04:41:27.459556 Vio18 = 0
3532 04:41:27.462556 Vcore = 650000
3533 04:41:27.462640 Vdram = 0
3534 04:41:27.462705 Vddq = 0
3535 04:41:27.462781 Vmddr = 0
3536 04:41:27.469167 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3537 04:41:27.475489 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3538 04:41:27.475584 MEM_TYPE=3, freq_sel=19
3539 04:41:27.479062 sv_algorithm_assistance_LP4_1600
3540 04:41:27.482780 ============ PULL DRAM RESETB DOWN ============
3541 04:41:27.489757 ========== PULL DRAM RESETB DOWN end =========
3542 04:41:27.492263 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3543 04:41:27.495691 ===================================
3544 04:41:27.499357 LPDDR4 DRAM CONFIGURATION
3545 04:41:27.502403 ===================================
3546 04:41:27.502486 EX_ROW_EN[0] = 0x0
3547 04:41:27.505612 EX_ROW_EN[1] = 0x0
3548 04:41:27.505695 LP4Y_EN = 0x0
3549 04:41:27.509066 WORK_FSP = 0x0
3550 04:41:27.509148 WL = 0x2
3551 04:41:27.512365 RL = 0x2
3552 04:41:27.512447 BL = 0x2
3553 04:41:27.515732 RPST = 0x0
3554 04:41:27.515814 RD_PRE = 0x0
3555 04:41:27.519114 WR_PRE = 0x1
3556 04:41:27.519196 WR_PST = 0x0
3557 04:41:27.523469 DBI_WR = 0x0
3558 04:41:27.525835 DBI_RD = 0x0
3559 04:41:27.525917 OTF = 0x1
3560 04:41:27.529062 ===================================
3561 04:41:27.532565 ===================================
3562 04:41:27.532649 ANA top config
3563 04:41:27.535774 ===================================
3564 04:41:27.538838 DLL_ASYNC_EN = 0
3565 04:41:27.542741 ALL_SLAVE_EN = 1
3566 04:41:27.545836 NEW_RANK_MODE = 1
3567 04:41:27.549477 DLL_IDLE_MODE = 1
3568 04:41:27.549562 LP45_APHY_COMB_EN = 1
3569 04:41:27.552975 TX_ODT_DIS = 1
3570 04:41:27.555890 NEW_8X_MODE = 1
3571 04:41:27.559356 ===================================
3572 04:41:27.562302 ===================================
3573 04:41:27.565535 data_rate = 1200
3574 04:41:27.568657 CKR = 1
3575 04:41:27.568780 DQ_P2S_RATIO = 8
3576 04:41:27.572577 ===================================
3577 04:41:27.576010 CA_P2S_RATIO = 8
3578 04:41:27.579544 DQ_CA_OPEN = 0
3579 04:41:27.582417 DQ_SEMI_OPEN = 0
3580 04:41:27.586028 CA_SEMI_OPEN = 0
3581 04:41:27.589108 CA_FULL_RATE = 0
3582 04:41:27.589191 DQ_CKDIV4_EN = 1
3583 04:41:27.592428 CA_CKDIV4_EN = 1
3584 04:41:27.595480 CA_PREDIV_EN = 0
3585 04:41:27.598813 PH8_DLY = 0
3586 04:41:27.602424 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3587 04:41:27.605719 DQ_AAMCK_DIV = 4
3588 04:41:27.605804 CA_AAMCK_DIV = 4
3589 04:41:27.608662 CA_ADMCK_DIV = 4
3590 04:41:27.612626 DQ_TRACK_CA_EN = 0
3591 04:41:27.615797 CA_PICK = 600
3592 04:41:27.619967 CA_MCKIO = 600
3593 04:41:27.622027 MCKIO_SEMI = 0
3594 04:41:27.625142 PLL_FREQ = 2288
3595 04:41:27.625226 DQ_UI_PI_RATIO = 32
3596 04:41:27.628854 CA_UI_PI_RATIO = 0
3597 04:41:27.631905 ===================================
3598 04:41:27.635569 ===================================
3599 04:41:27.638674 memory_type:LPDDR4
3600 04:41:27.642011 GP_NUM : 10
3601 04:41:27.642119 SRAM_EN : 1
3602 04:41:27.644852 MD32_EN : 0
3603 04:41:27.648796 ===================================
3604 04:41:27.651844 [ANA_INIT] >>>>>>>>>>>>>>
3605 04:41:27.651953 <<<<<< [CONFIGURE PHASE]: ANA_TX
3606 04:41:27.655254 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3607 04:41:27.658582 ===================================
3608 04:41:27.661765 data_rate = 1200,PCW = 0X5800
3609 04:41:27.665127 ===================================
3610 04:41:27.668255 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3611 04:41:27.675031 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3612 04:41:27.681396 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3613 04:41:27.685689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3614 04:41:27.688452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3615 04:41:27.692075 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3616 04:41:27.695135 [ANA_INIT] flow start
3617 04:41:27.695244 [ANA_INIT] PLL >>>>>>>>
3618 04:41:27.698511 [ANA_INIT] PLL <<<<<<<<
3619 04:41:27.701858 [ANA_INIT] MIDPI >>>>>>>>
3620 04:41:27.701968 [ANA_INIT] MIDPI <<<<<<<<
3621 04:41:27.705057 [ANA_INIT] DLL >>>>>>>>
3622 04:41:27.708025 [ANA_INIT] flow end
3623 04:41:27.711435 ============ LP4 DIFF to SE enter ============
3624 04:41:27.714698 ============ LP4 DIFF to SE exit ============
3625 04:41:27.717970 [ANA_INIT] <<<<<<<<<<<<<
3626 04:41:27.721712 [Flow] Enable top DCM control >>>>>
3627 04:41:27.726216 [Flow] Enable top DCM control <<<<<
3628 04:41:27.728538 Enable DLL master slave shuffle
3629 04:41:27.734408 ==============================================================
3630 04:41:27.734494 Gating Mode config
3631 04:41:27.741764 ==============================================================
3632 04:41:27.741859 Config description:
3633 04:41:27.751112 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3634 04:41:27.758024 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3635 04:41:27.764670 SELPH_MODE 0: By rank 1: By Phase
3636 04:41:27.767930 ==============================================================
3637 04:41:27.771562 GAT_TRACK_EN = 1
3638 04:41:27.774343 RX_GATING_MODE = 2
3639 04:41:27.777984 RX_GATING_TRACK_MODE = 2
3640 04:41:27.781999 SELPH_MODE = 1
3641 04:41:27.784422 PICG_EARLY_EN = 1
3642 04:41:27.787686 VALID_LAT_VALUE = 1
3643 04:41:27.791716 ==============================================================
3644 04:41:27.794500 Enter into Gating configuration >>>>
3645 04:41:27.798300 Exit from Gating configuration <<<<
3646 04:41:27.801256 Enter into DVFS_PRE_config >>>>>
3647 04:41:27.814543 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3648 04:41:27.817782 Exit from DVFS_PRE_config <<<<<
3649 04:41:27.821730 Enter into PICG configuration >>>>
3650 04:41:27.821816 Exit from PICG configuration <<<<
3651 04:41:27.824519 [RX_INPUT] configuration >>>>>
3652 04:41:27.827476 [RX_INPUT] configuration <<<<<
3653 04:41:27.834701 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3654 04:41:27.837290 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3655 04:41:27.844411 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3656 04:41:27.851562 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3657 04:41:27.857677 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3658 04:41:27.864477 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3659 04:41:27.867518 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3660 04:41:27.870832 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3661 04:41:27.873958 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3662 04:41:27.880771 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3663 04:41:27.884341 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3664 04:41:27.887342 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3665 04:41:27.890620 ===================================
3666 04:41:27.893796 LPDDR4 DRAM CONFIGURATION
3667 04:41:27.896982 ===================================
3668 04:41:27.901355 EX_ROW_EN[0] = 0x0
3669 04:41:27.901440 EX_ROW_EN[1] = 0x0
3670 04:41:27.903841 LP4Y_EN = 0x0
3671 04:41:27.903951 WORK_FSP = 0x0
3672 04:41:27.907438 WL = 0x2
3673 04:41:27.907545 RL = 0x2
3674 04:41:27.910996 BL = 0x2
3675 04:41:27.911104 RPST = 0x0
3676 04:41:27.914570 RD_PRE = 0x0
3677 04:41:27.914678 WR_PRE = 0x1
3678 04:41:27.916789 WR_PST = 0x0
3679 04:41:27.916893 DBI_WR = 0x0
3680 04:41:27.920839 DBI_RD = 0x0
3681 04:41:27.920944 OTF = 0x1
3682 04:41:27.923936 ===================================
3683 04:41:27.930628 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3684 04:41:27.935047 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3685 04:41:27.936713 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3686 04:41:27.940972 ===================================
3687 04:41:27.943868 LPDDR4 DRAM CONFIGURATION
3688 04:41:27.946634 ===================================
3689 04:41:27.950197 EX_ROW_EN[0] = 0x10
3690 04:41:27.950283 EX_ROW_EN[1] = 0x0
3691 04:41:27.953444 LP4Y_EN = 0x0
3692 04:41:27.953528 WORK_FSP = 0x0
3693 04:41:27.956462 WL = 0x2
3694 04:41:27.956543 RL = 0x2
3695 04:41:27.960096 BL = 0x2
3696 04:41:27.960198 RPST = 0x0
3697 04:41:27.963325 RD_PRE = 0x0
3698 04:41:27.963432 WR_PRE = 0x1
3699 04:41:27.966323 WR_PST = 0x0
3700 04:41:27.966426 DBI_WR = 0x0
3701 04:41:27.970842 DBI_RD = 0x0
3702 04:41:27.970947 OTF = 0x1
3703 04:41:27.973717 ===================================
3704 04:41:27.980133 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3705 04:41:27.985006 nWR fixed to 30
3706 04:41:27.987982 [ModeRegInit_LP4] CH0 RK0
3707 04:41:27.988159 [ModeRegInit_LP4] CH0 RK1
3708 04:41:27.991735 [ModeRegInit_LP4] CH1 RK0
3709 04:41:27.994670 [ModeRegInit_LP4] CH1 RK1
3710 04:41:27.994761 match AC timing 16
3711 04:41:28.001227 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3712 04:41:28.004969 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3713 04:41:28.008396 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3714 04:41:28.014905 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3715 04:41:28.017806 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3716 04:41:28.017899 ==
3717 04:41:28.021696 Dram Type= 6, Freq= 0, CH_0, rank 0
3718 04:41:28.024864 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3719 04:41:28.024959 ==
3720 04:41:28.031254 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3721 04:41:28.037483 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3722 04:41:28.040970 [CA 0] Center 35 (5~66) winsize 62
3723 04:41:28.044281 [CA 1] Center 35 (5~66) winsize 62
3724 04:41:28.048421 [CA 2] Center 34 (4~65) winsize 62
3725 04:41:28.052866 [CA 3] Center 34 (4~65) winsize 62
3726 04:41:28.054941 [CA 4] Center 33 (3~64) winsize 62
3727 04:41:28.057524 [CA 5] Center 33 (3~64) winsize 62
3728 04:41:28.057643
3729 04:41:28.061113 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3730 04:41:28.061229
3731 04:41:28.064085 [CATrainingPosCal] consider 1 rank data
3732 04:41:28.067261 u2DelayCellTimex100 = 270/100 ps
3733 04:41:28.070805 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3734 04:41:28.074338 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3735 04:41:28.077757 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3736 04:41:28.080911 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3737 04:41:28.084426 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3738 04:41:28.090650 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3739 04:41:28.090736
3740 04:41:28.094297 CA PerBit enable=1, Macro0, CA PI delay=33
3741 04:41:28.094379
3742 04:41:28.097489 [CBTSetCACLKResult] CA Dly = 33
3743 04:41:28.097571 CS Dly: 4 (0~35)
3744 04:41:28.097636 ==
3745 04:41:28.101483 Dram Type= 6, Freq= 0, CH_0, rank 1
3746 04:41:28.103799 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3747 04:41:28.107656 ==
3748 04:41:28.110283 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3749 04:41:28.117023 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3750 04:41:28.120666 [CA 0] Center 35 (5~66) winsize 62
3751 04:41:28.123928 [CA 1] Center 35 (5~66) winsize 62
3752 04:41:28.127249 [CA 2] Center 34 (4~65) winsize 62
3753 04:41:28.130201 [CA 3] Center 34 (4~65) winsize 62
3754 04:41:28.133929 [CA 4] Center 33 (3~64) winsize 62
3755 04:41:28.137261 [CA 5] Center 33 (3~64) winsize 62
3756 04:41:28.137343
3757 04:41:28.140478 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3758 04:41:28.140561
3759 04:41:28.143650 [CATrainingPosCal] consider 2 rank data
3760 04:41:28.147426 u2DelayCellTimex100 = 270/100 ps
3761 04:41:28.150844 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3762 04:41:28.153589 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3763 04:41:28.157597 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3764 04:41:28.161028 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3765 04:41:28.168055 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3766 04:41:28.170697 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3767 04:41:28.170782
3768 04:41:28.173893 CA PerBit enable=1, Macro0, CA PI delay=33
3769 04:41:28.173978
3770 04:41:28.177299 [CBTSetCACLKResult] CA Dly = 33
3771 04:41:28.177382 CS Dly: 4 (0~36)
3772 04:41:28.177448
3773 04:41:28.180768 ----->DramcWriteLeveling(PI) begin...
3774 04:41:28.180853 ==
3775 04:41:28.184439 Dram Type= 6, Freq= 0, CH_0, rank 0
3776 04:41:28.190312 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3777 04:41:28.190396 ==
3778 04:41:28.193490 Write leveling (Byte 0): 30 => 30
3779 04:41:28.197264 Write leveling (Byte 1): 30 => 30
3780 04:41:28.197356 DramcWriteLeveling(PI) end<-----
3781 04:41:28.197422
3782 04:41:28.200628 ==
3783 04:41:28.200719 Dram Type= 6, Freq= 0, CH_0, rank 0
3784 04:41:28.206926 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3785 04:41:28.207025 ==
3786 04:41:28.210163 [Gating] SW mode calibration
3787 04:41:28.217638 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3788 04:41:28.220951 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3789 04:41:28.226826 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3790 04:41:28.230565 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3791 04:41:28.233915 0 5 8 | B1->B0 | 3232 3232 | 0 1 | (0 0) (1 0)
3792 04:41:28.240044 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
3793 04:41:28.243126 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3794 04:41:28.246532 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3795 04:41:28.253176 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3796 04:41:28.256464 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3797 04:41:28.260020 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3798 04:41:28.266558 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3799 04:41:28.270052 0 6 8 | B1->B0 | 2c2c 3232 | 0 0 | (0 0) (0 0)
3800 04:41:28.273217 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3801 04:41:28.279601 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3802 04:41:28.282885 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3803 04:41:28.286303 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3804 04:41:28.292887 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3805 04:41:28.296281 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3806 04:41:28.299923 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3807 04:41:28.306583 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3808 04:41:28.309746 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3809 04:41:28.312749 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3810 04:41:28.319547 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 04:41:28.322978 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 04:41:28.325870 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 04:41:28.333362 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 04:41:28.335919 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 04:41:28.339487 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 04:41:28.345863 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 04:41:28.348922 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 04:41:28.352563 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 04:41:28.359309 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 04:41:28.362680 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 04:41:28.365377 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 04:41:28.372473 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 04:41:28.375575 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3824 04:41:28.379076 Total UI for P1: 0, mck2ui 16
3825 04:41:28.382524 best dqsien dly found for B0: ( 0, 9, 6)
3826 04:41:28.385736 Total UI for P1: 0, mck2ui 16
3827 04:41:28.388870 best dqsien dly found for B1: ( 0, 9, 6)
3828 04:41:28.391810 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3829 04:41:28.395142 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
3830 04:41:28.395234
3831 04:41:28.398624 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3832 04:41:28.401923 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
3833 04:41:28.405028 [Gating] SW calibration Done
3834 04:41:28.405117 ==
3835 04:41:28.409335 Dram Type= 6, Freq= 0, CH_0, rank 0
3836 04:41:28.412371 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3837 04:41:28.412458 ==
3838 04:41:28.415142 RX Vref Scan: 0
3839 04:41:28.415227
3840 04:41:28.418210 RX Vref 0 -> 0, step: 1
3841 04:41:28.418329
3842 04:41:28.418400 RX Delay -230 -> 252, step: 16
3843 04:41:28.425331 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
3844 04:41:28.428368 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3845 04:41:28.431509 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3846 04:41:28.434932 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3847 04:41:28.441762 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3848 04:41:28.444813 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3849 04:41:28.448216 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3850 04:41:28.452470 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3851 04:41:28.458616 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3852 04:41:28.461232 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3853 04:41:28.465394 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3854 04:41:28.468432 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3855 04:41:28.474732 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3856 04:41:28.478522 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3857 04:41:28.481478 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3858 04:41:28.484663 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3859 04:41:28.484777 ==
3860 04:41:28.487679 Dram Type= 6, Freq= 0, CH_0, rank 0
3861 04:41:28.495210 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3862 04:41:28.495319 ==
3863 04:41:28.495409 DQS Delay:
3864 04:41:28.497494 DQS0 = 0, DQS1 = 0
3865 04:41:28.497579 DQM Delay:
3866 04:41:28.497665 DQM0 = 41, DQM1 = 33
3867 04:41:28.501089 DQ Delay:
3868 04:41:28.504319 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
3869 04:41:28.507636 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3870 04:41:28.511194 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3871 04:41:28.514583 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3872 04:41:28.514684
3873 04:41:28.514772
3874 04:41:28.514854 ==
3875 04:41:28.518034 Dram Type= 6, Freq= 0, CH_0, rank 0
3876 04:41:28.520876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3877 04:41:28.520964 ==
3878 04:41:28.521050
3879 04:41:28.521132
3880 04:41:28.525029 TX Vref Scan disable
3881 04:41:28.525123 == TX Byte 0 ==
3882 04:41:28.531123 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3883 04:41:28.534620 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3884 04:41:28.534719 == TX Byte 1 ==
3885 04:41:28.540692 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3886 04:41:28.543807 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3887 04:41:28.543899 ==
3888 04:41:28.547150 Dram Type= 6, Freq= 0, CH_0, rank 0
3889 04:41:28.550464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3890 04:41:28.554138 ==
3891 04:41:28.554226
3892 04:41:28.554313
3893 04:41:28.554395 TX Vref Scan disable
3894 04:41:28.557869 == TX Byte 0 ==
3895 04:41:28.560782 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3896 04:41:28.567890 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3897 04:41:28.568008 == TX Byte 1 ==
3898 04:41:28.571588 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3899 04:41:28.577516 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3900 04:41:28.577615
3901 04:41:28.577680 [DATLAT]
3902 04:41:28.577741 Freq=600, CH0 RK0
3903 04:41:28.577798
3904 04:41:28.580553 DATLAT Default: 0x9
3905 04:41:28.583808 0, 0xFFFF, sum = 0
3906 04:41:28.583894 1, 0xFFFF, sum = 0
3907 04:41:28.587182 2, 0xFFFF, sum = 0
3908 04:41:28.587264 3, 0xFFFF, sum = 0
3909 04:41:28.590680 4, 0xFFFF, sum = 0
3910 04:41:28.590762 5, 0xFFFF, sum = 0
3911 04:41:28.593854 6, 0xFFFF, sum = 0
3912 04:41:28.593935 7, 0x0, sum = 1
3913 04:41:28.596971 8, 0x0, sum = 2
3914 04:41:28.597052 9, 0x0, sum = 3
3915 04:41:28.597117 10, 0x0, sum = 4
3916 04:41:28.600225 best_step = 8
3917 04:41:28.600306
3918 04:41:28.600370 ==
3919 04:41:28.604177 Dram Type= 6, Freq= 0, CH_0, rank 0
3920 04:41:28.606977 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3921 04:41:28.607063 ==
3922 04:41:28.610481 RX Vref Scan: 1
3923 04:41:28.610563
3924 04:41:28.610657 RX Vref 0 -> 0, step: 1
3925 04:41:28.613791
3926 04:41:28.613871 RX Delay -195 -> 252, step: 8
3927 04:41:28.613935
3928 04:41:28.616831 Set Vref, RX VrefLevel [Byte0]: 50
3929 04:41:28.620542 [Byte1]: 45
3930 04:41:28.624686
3931 04:41:28.624808 Final RX Vref Byte 0 = 50 to rank0
3932 04:41:28.627962 Final RX Vref Byte 1 = 45 to rank0
3933 04:41:28.631044 Final RX Vref Byte 0 = 50 to rank1
3934 04:41:28.634425 Final RX Vref Byte 1 = 45 to rank1==
3935 04:41:28.637778 Dram Type= 6, Freq= 0, CH_0, rank 0
3936 04:41:28.644448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3937 04:41:28.644542 ==
3938 04:41:28.644642 DQS Delay:
3939 04:41:28.647833 DQS0 = 0, DQS1 = 0
3940 04:41:28.647918 DQM Delay:
3941 04:41:28.648004 DQM0 = 41, DQM1 = 31
3942 04:41:28.651355 DQ Delay:
3943 04:41:28.654500 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =40
3944 04:41:28.657677 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =52
3945 04:41:28.660808 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
3946 04:41:28.664168 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
3947 04:41:28.664259
3948 04:41:28.664345
3949 04:41:28.671711 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
3950 04:41:28.673955 CH0 RK0: MR19=808, MR18=5C5C
3951 04:41:28.681050 CH0_RK0: MR19=0x808, MR18=0x5C5C, DQSOSC=392, MR23=63, INC=170, DEC=113
3952 04:41:28.681140
3953 04:41:28.684336 ----->DramcWriteLeveling(PI) begin...
3954 04:41:28.684423 ==
3955 04:41:28.688125 Dram Type= 6, Freq= 0, CH_0, rank 1
3956 04:41:28.691762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3957 04:41:28.691850 ==
3958 04:41:28.693981 Write leveling (Byte 0): 30 => 30
3959 04:41:28.698263 Write leveling (Byte 1): 30 => 30
3960 04:41:28.700639 DramcWriteLeveling(PI) end<-----
3961 04:41:28.700782
3962 04:41:28.700869 ==
3963 04:41:28.704281 Dram Type= 6, Freq= 0, CH_0, rank 1
3964 04:41:28.707516 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3965 04:41:28.710824 ==
3966 04:41:28.710909 [Gating] SW mode calibration
3967 04:41:28.717173 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3968 04:41:28.724225 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3969 04:41:28.727151 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3970 04:41:28.734428 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3971 04:41:28.737249 0 5 8 | B1->B0 | 3333 3333 | 1 1 | (0 1) (1 1)
3972 04:41:28.740393 0 5 12 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
3973 04:41:28.746929 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 04:41:28.750407 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 04:41:28.754177 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 04:41:28.760937 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 04:41:28.764257 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 04:41:28.766912 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 04:41:28.774153 0 6 8 | B1->B0 | 2929 3131 | 0 0 | (0 0) (1 1)
3980 04:41:28.777118 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 04:41:28.780471 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 04:41:28.784350 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 04:41:28.790791 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 04:41:28.793602 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 04:41:28.796969 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 04:41:28.803555 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 04:41:28.807165 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3988 04:41:28.810765 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 04:41:28.816959 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 04:41:28.820043 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 04:41:28.823341 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 04:41:28.830369 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 04:41:28.834200 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 04:41:28.836903 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 04:41:28.843521 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 04:41:28.846279 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 04:41:28.849736 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 04:41:28.856197 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 04:41:28.859631 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 04:41:28.863195 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 04:41:28.869891 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 04:41:28.872703 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 04:41:28.876587 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 04:41:28.879475 Total UI for P1: 0, mck2ui 16
4005 04:41:28.882801 best dqsien dly found for B0: ( 0, 9, 6)
4006 04:41:28.886380 Total UI for P1: 0, mck2ui 16
4007 04:41:28.889895 best dqsien dly found for B1: ( 0, 9, 6)
4008 04:41:28.892779 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4009 04:41:28.896295 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4010 04:41:28.896377
4011 04:41:28.902847 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4012 04:41:28.905918 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4013 04:41:28.906000 [Gating] SW calibration Done
4014 04:41:28.909187 ==
4015 04:41:28.913028 Dram Type= 6, Freq= 0, CH_0, rank 1
4016 04:41:28.916016 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4017 04:41:28.916097 ==
4018 04:41:28.916161 RX Vref Scan: 0
4019 04:41:28.916221
4020 04:41:28.919175 RX Vref 0 -> 0, step: 1
4021 04:41:28.919255
4022 04:41:28.922615 RX Delay -230 -> 252, step: 16
4023 04:41:28.926373 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4024 04:41:28.929039 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4025 04:41:28.935794 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4026 04:41:28.939185 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4027 04:41:28.942686 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4028 04:41:28.946336 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4029 04:41:28.953068 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4030 04:41:28.955685 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4031 04:41:28.958788 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4032 04:41:28.962724 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4033 04:41:28.966004 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4034 04:41:28.972442 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4035 04:41:28.975434 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4036 04:41:28.978830 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4037 04:41:28.982476 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4038 04:41:28.989086 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4039 04:41:28.989171 ==
4040 04:41:28.993256 Dram Type= 6, Freq= 0, CH_0, rank 1
4041 04:41:28.995610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4042 04:41:28.995695 ==
4043 04:41:28.995782 DQS Delay:
4044 04:41:28.999000 DQS0 = 0, DQS1 = 0
4045 04:41:28.999084 DQM Delay:
4046 04:41:29.002053 DQM0 = 41, DQM1 = 32
4047 04:41:29.002137 DQ Delay:
4048 04:41:29.005314 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4049 04:41:29.009340 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4050 04:41:29.011846 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4051 04:41:29.015554 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4052 04:41:29.015638
4053 04:41:29.015724
4054 04:41:29.015805 ==
4055 04:41:29.018746 Dram Type= 6, Freq= 0, CH_0, rank 1
4056 04:41:29.021869 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4057 04:41:29.025841 ==
4058 04:41:29.025925
4059 04:41:29.026010
4060 04:41:29.026091 TX Vref Scan disable
4061 04:41:29.029095 == TX Byte 0 ==
4062 04:41:29.032234 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4063 04:41:29.035345 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4064 04:41:29.038791 == TX Byte 1 ==
4065 04:41:29.041843 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4066 04:41:29.044960 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4067 04:41:29.048641 ==
4068 04:41:29.051853 Dram Type= 6, Freq= 0, CH_0, rank 1
4069 04:41:29.055534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4070 04:41:29.055619 ==
4071 04:41:29.055705
4072 04:41:29.055786
4073 04:41:29.058583 TX Vref Scan disable
4074 04:41:29.058666 == TX Byte 0 ==
4075 04:41:29.065131 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4076 04:41:29.068179 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4077 04:41:29.068264 == TX Byte 1 ==
4078 04:41:29.075059 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4079 04:41:29.078320 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4080 04:41:29.078405
4081 04:41:29.078491 [DATLAT]
4082 04:41:29.081438 Freq=600, CH0 RK1
4083 04:41:29.081522
4084 04:41:29.081608 DATLAT Default: 0x8
4085 04:41:29.084938 0, 0xFFFF, sum = 0
4086 04:41:29.085024 1, 0xFFFF, sum = 0
4087 04:41:29.088124 2, 0xFFFF, sum = 0
4088 04:41:29.088210 3, 0xFFFF, sum = 0
4089 04:41:29.091528 4, 0xFFFF, sum = 0
4090 04:41:29.095007 5, 0xFFFF, sum = 0
4091 04:41:29.095094 6, 0xFFFF, sum = 0
4092 04:41:29.095182 7, 0x0, sum = 1
4093 04:41:29.098253 8, 0x0, sum = 2
4094 04:41:29.098337 9, 0x0, sum = 3
4095 04:41:29.101516 10, 0x0, sum = 4
4096 04:41:29.101602 best_step = 8
4097 04:41:29.101688
4098 04:41:29.101769 ==
4099 04:41:29.105152 Dram Type= 6, Freq= 0, CH_0, rank 1
4100 04:41:29.111789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4101 04:41:29.111875 ==
4102 04:41:29.111961 RX Vref Scan: 0
4103 04:41:29.112043
4104 04:41:29.115009 RX Vref 0 -> 0, step: 1
4105 04:41:29.115094
4106 04:41:29.118294 RX Delay -195 -> 252, step: 8
4107 04:41:29.121537 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4108 04:41:29.128466 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4109 04:41:29.131584 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4110 04:41:29.134257 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4111 04:41:29.138388 iDelay=205, Bit 4, Center 44 (-115 ~ 204) 320
4112 04:41:29.144281 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4113 04:41:29.147714 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4114 04:41:29.151788 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4115 04:41:29.154387 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4116 04:41:29.157712 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4117 04:41:29.164123 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4118 04:41:29.167442 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4119 04:41:29.171038 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4120 04:41:29.174437 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4121 04:41:29.181305 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4122 04:41:29.185451 iDelay=205, Bit 15, Center 40 (-107 ~ 188) 296
4123 04:41:29.185538 ==
4124 04:41:29.187610 Dram Type= 6, Freq= 0, CH_0, rank 1
4125 04:41:29.191065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4126 04:41:29.191148 ==
4127 04:41:29.193938 DQS Delay:
4128 04:41:29.194018 DQS0 = 0, DQS1 = 0
4129 04:41:29.194082 DQM Delay:
4130 04:41:29.197804 DQM0 = 42, DQM1 = 32
4131 04:41:29.197883 DQ Delay:
4132 04:41:29.200828 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4133 04:41:29.204440 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4134 04:41:29.207418 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =24
4135 04:41:29.210644 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4136 04:41:29.210728
4137 04:41:29.210814
4138 04:41:29.220902 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c6c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4139 04:41:29.224041 CH0 RK1: MR19=808, MR18=6C6C
4140 04:41:29.227343 CH0_RK1: MR19=0x808, MR18=0x6C6C, DQSOSC=389, MR23=63, INC=173, DEC=115
4141 04:41:29.230553 [RxdqsGatingPostProcess] freq 600
4142 04:41:29.237433 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4143 04:41:29.240918 Pre-setting of DQS Precalculation
4144 04:41:29.244443 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4145 04:41:29.244528 ==
4146 04:41:29.247141 Dram Type= 6, Freq= 0, CH_1, rank 0
4147 04:41:29.254829 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4148 04:41:29.254915 ==
4149 04:41:29.256891 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4150 04:41:29.263991 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4151 04:41:29.267321 [CA 0] Center 35 (5~66) winsize 62
4152 04:41:29.270933 [CA 1] Center 35 (5~66) winsize 62
4153 04:41:29.274055 [CA 2] Center 33 (3~64) winsize 62
4154 04:41:29.277140 [CA 3] Center 33 (3~64) winsize 62
4155 04:41:29.280492 [CA 4] Center 33 (2~64) winsize 63
4156 04:41:29.283509 [CA 5] Center 33 (2~64) winsize 63
4157 04:41:29.283595
4158 04:41:29.286661 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4159 04:41:29.286746
4160 04:41:29.290796 [CATrainingPosCal] consider 1 rank data
4161 04:41:29.293526 u2DelayCellTimex100 = 270/100 ps
4162 04:41:29.296624 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4163 04:41:29.300447 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4164 04:41:29.306668 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4165 04:41:29.310164 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4166 04:41:29.313697 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4167 04:41:29.318409 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4168 04:41:29.318496
4169 04:41:29.320054 CA PerBit enable=1, Macro0, CA PI delay=33
4170 04:41:29.320139
4171 04:41:29.324309 [CBTSetCACLKResult] CA Dly = 33
4172 04:41:29.324394 CS Dly: 5 (0~36)
4173 04:41:29.326496 ==
4174 04:41:29.330084 Dram Type= 6, Freq= 0, CH_1, rank 1
4175 04:41:29.334157 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4176 04:41:29.334257 ==
4177 04:41:29.336641 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4178 04:41:29.343202 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4179 04:41:29.347025 [CA 0] Center 35 (5~66) winsize 62
4180 04:41:29.350644 [CA 1] Center 34 (4~65) winsize 62
4181 04:41:29.353795 [CA 2] Center 33 (3~64) winsize 62
4182 04:41:29.356703 [CA 3] Center 33 (3~64) winsize 62
4183 04:41:29.361132 [CA 4] Center 32 (2~63) winsize 62
4184 04:41:29.363612 [CA 5] Center 32 (2~63) winsize 62
4185 04:41:29.363696
4186 04:41:29.367362 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4187 04:41:29.367444
4188 04:41:29.370122 [CATrainingPosCal] consider 2 rank data
4189 04:41:29.374025 u2DelayCellTimex100 = 270/100 ps
4190 04:41:29.377212 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4191 04:41:29.383508 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4192 04:41:29.387017 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4193 04:41:29.390389 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4194 04:41:29.393700 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4195 04:41:29.397694 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4196 04:41:29.397775
4197 04:41:29.400574 CA PerBit enable=1, Macro0, CA PI delay=32
4198 04:41:29.400655
4199 04:41:29.403509 [CBTSetCACLKResult] CA Dly = 32
4200 04:41:29.403590 CS Dly: 5 (0~36)
4201 04:41:29.406981
4202 04:41:29.410042 ----->DramcWriteLeveling(PI) begin...
4203 04:41:29.410125 ==
4204 04:41:29.413583 Dram Type= 6, Freq= 0, CH_1, rank 0
4205 04:41:29.416914 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4206 04:41:29.416996 ==
4207 04:41:29.420548 Write leveling (Byte 0): 27 => 27
4208 04:41:29.423575 Write leveling (Byte 1): 28 => 28
4209 04:41:29.426394 DramcWriteLeveling(PI) end<-----
4210 04:41:29.426475
4211 04:41:29.426539 ==
4212 04:41:29.430145 Dram Type= 6, Freq= 0, CH_1, rank 0
4213 04:41:29.432993 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4214 04:41:29.433076 ==
4215 04:41:29.436554 [Gating] SW mode calibration
4216 04:41:29.443156 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4217 04:41:29.449546 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4218 04:41:29.452880 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4219 04:41:29.456714 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
4220 04:41:29.462783 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4221 04:41:29.466716 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 04:41:29.469878 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 04:41:29.476040 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 04:41:29.480238 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 04:41:29.482654 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 04:41:29.489396 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 04:41:29.492910 0 6 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
4228 04:41:29.496539 0 6 8 | B1->B0 | 3939 4141 | 0 0 | (1 1) (0 0)
4229 04:41:29.504200 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 04:41:29.506396 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 04:41:29.509485 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 04:41:29.512635 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 04:41:29.519540 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 04:41:29.522602 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 04:41:29.525993 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 04:41:29.532614 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4237 04:41:29.535905 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 04:41:29.539470 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 04:41:29.546038 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 04:41:29.549019 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 04:41:29.552390 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 04:41:29.559639 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 04:41:29.562883 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 04:41:29.565690 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 04:41:29.572151 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 04:41:29.575924 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 04:41:29.579023 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 04:41:29.586050 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 04:41:29.589272 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 04:41:29.592000 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 04:41:29.598621 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 04:41:29.602229 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4253 04:41:29.605609 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 04:41:29.609194 Total UI for P1: 0, mck2ui 16
4255 04:41:29.612062 best dqsien dly found for B0: ( 0, 9, 8)
4256 04:41:29.615544 Total UI for P1: 0, mck2ui 16
4257 04:41:29.618710 best dqsien dly found for B1: ( 0, 9, 10)
4258 04:41:29.621926 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4259 04:41:29.625487 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4260 04:41:29.625568
4261 04:41:29.633019 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4262 04:41:29.635581 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4263 04:41:29.635662 [Gating] SW calibration Done
4264 04:41:29.638816 ==
4265 04:41:29.643134 Dram Type= 6, Freq= 0, CH_1, rank 0
4266 04:41:29.645752 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4267 04:41:29.645834 ==
4268 04:41:29.645898 RX Vref Scan: 0
4269 04:41:29.645959
4270 04:41:29.648379 RX Vref 0 -> 0, step: 1
4271 04:41:29.648460
4272 04:41:29.651746 RX Delay -230 -> 252, step: 16
4273 04:41:29.655287 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4274 04:41:29.658494 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4275 04:41:29.665026 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4276 04:41:29.668342 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4277 04:41:29.671813 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4278 04:41:29.674689 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4279 04:41:29.681758 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4280 04:41:29.684735 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4281 04:41:29.688661 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4282 04:41:29.692187 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4283 04:41:29.695141 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4284 04:41:29.701274 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4285 04:41:29.705535 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4286 04:41:29.708178 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4287 04:41:29.711321 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4288 04:41:29.718354 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4289 04:41:29.718436 ==
4290 04:41:29.721663 Dram Type= 6, Freq= 0, CH_1, rank 0
4291 04:41:29.724460 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4292 04:41:29.724543 ==
4293 04:41:29.724607 DQS Delay:
4294 04:41:29.727994 DQS0 = 0, DQS1 = 0
4295 04:41:29.728076 DQM Delay:
4296 04:41:29.731514 DQM0 = 39, DQM1 = 34
4297 04:41:29.731596 DQ Delay:
4298 04:41:29.735125 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4299 04:41:29.738086 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4300 04:41:29.741654 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4301 04:41:29.745389 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4302 04:41:29.745471
4303 04:41:29.745534
4304 04:41:29.745593 ==
4305 04:41:29.748203 Dram Type= 6, Freq= 0, CH_1, rank 0
4306 04:41:29.750938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4307 04:41:29.754268 ==
4308 04:41:29.754348
4309 04:41:29.754412
4310 04:41:29.754471 TX Vref Scan disable
4311 04:41:29.757737 == TX Byte 0 ==
4312 04:41:29.761063 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4313 04:41:29.767755 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4314 04:41:29.767869 == TX Byte 1 ==
4315 04:41:29.771410 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4316 04:41:29.777224 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4317 04:41:29.777307 ==
4318 04:41:29.781061 Dram Type= 6, Freq= 0, CH_1, rank 0
4319 04:41:29.784889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4320 04:41:29.784971 ==
4321 04:41:29.785035
4322 04:41:29.785096
4323 04:41:29.787509 TX Vref Scan disable
4324 04:41:29.790861 == TX Byte 0 ==
4325 04:41:29.794339 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4326 04:41:29.797099 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4327 04:41:29.801253 == TX Byte 1 ==
4328 04:41:29.803875 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4329 04:41:29.807531 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4330 04:41:29.807612
4331 04:41:29.807676 [DATLAT]
4332 04:41:29.810791 Freq=600, CH1 RK0
4333 04:41:29.810872
4334 04:41:29.813577 DATLAT Default: 0x9
4335 04:41:29.813657 0, 0xFFFF, sum = 0
4336 04:41:29.817278 1, 0xFFFF, sum = 0
4337 04:41:29.817362 2, 0xFFFF, sum = 0
4338 04:41:29.821270 3, 0xFFFF, sum = 0
4339 04:41:29.821352 4, 0xFFFF, sum = 0
4340 04:41:29.824766 5, 0xFFFF, sum = 0
4341 04:41:29.824848 6, 0xFFFF, sum = 0
4342 04:41:29.827381 7, 0x0, sum = 1
4343 04:41:29.827462 8, 0x0, sum = 2
4344 04:41:29.830283 9, 0x0, sum = 3
4345 04:41:29.830364 10, 0x0, sum = 4
4346 04:41:29.830429 best_step = 8
4347 04:41:29.830488
4348 04:41:29.833979 ==
4349 04:41:29.834059 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 04:41:29.840723 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4351 04:41:29.840821 ==
4352 04:41:29.840886 RX Vref Scan: 1
4353 04:41:29.840946
4354 04:41:29.843702 RX Vref 0 -> 0, step: 1
4355 04:41:29.843783
4356 04:41:29.847088 RX Delay -195 -> 252, step: 8
4357 04:41:29.847169
4358 04:41:29.850468 Set Vref, RX VrefLevel [Byte0]: 62
4359 04:41:29.853605 [Byte1]: 47
4360 04:41:29.853686
4361 04:41:29.856663 Final RX Vref Byte 0 = 62 to rank0
4362 04:41:29.860048 Final RX Vref Byte 1 = 47 to rank0
4363 04:41:29.863710 Final RX Vref Byte 0 = 62 to rank1
4364 04:41:29.867229 Final RX Vref Byte 1 = 47 to rank1==
4365 04:41:29.870113 Dram Type= 6, Freq= 0, CH_1, rank 0
4366 04:41:29.873222 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4367 04:41:29.873302 ==
4368 04:41:29.877349 DQS Delay:
4369 04:41:29.877429 DQS0 = 0, DQS1 = 0
4370 04:41:29.880189 DQM Delay:
4371 04:41:29.880270 DQM0 = 36, DQM1 = 31
4372 04:41:29.883650 DQ Delay:
4373 04:41:29.883730 DQ0 =40, DQ1 =28, DQ2 =28, DQ3 =32
4374 04:41:29.886790 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4375 04:41:29.890182 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4376 04:41:29.893377 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4377 04:41:29.893457
4378 04:41:29.896745
4379 04:41:29.903230 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f6f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4380 04:41:29.906342 CH1 RK0: MR19=808, MR18=6F6F
4381 04:41:29.912931 CH1_RK0: MR19=0x808, MR18=0x6F6F, DQSOSC=389, MR23=63, INC=173, DEC=115
4382 04:41:29.913014
4383 04:41:29.916297 ----->DramcWriteLeveling(PI) begin...
4384 04:41:29.916379 ==
4385 04:41:29.919528 Dram Type= 6, Freq= 0, CH_1, rank 1
4386 04:41:29.923274 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4387 04:41:29.923356 ==
4388 04:41:29.926577 Write leveling (Byte 0): 27 => 27
4389 04:41:29.929725 Write leveling (Byte 1): 28 => 28
4390 04:41:29.932957 DramcWriteLeveling(PI) end<-----
4391 04:41:29.933037
4392 04:41:29.933102 ==
4393 04:41:29.936959 Dram Type= 6, Freq= 0, CH_1, rank 1
4394 04:41:29.939811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4395 04:41:29.939892 ==
4396 04:41:29.942768 [Gating] SW mode calibration
4397 04:41:29.949480 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4398 04:41:29.956098 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4399 04:41:29.959417 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4400 04:41:29.962637 0 5 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4401 04:41:29.969510 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
4402 04:41:29.973165 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 04:41:29.976316 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 04:41:29.982512 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 04:41:29.986022 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 04:41:29.989705 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 04:41:29.995929 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 04:41:29.999173 0 6 4 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
4409 04:41:30.002702 0 6 8 | B1->B0 | 3434 4545 | 0 0 | (0 0) (0 0)
4410 04:41:30.009406 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 04:41:30.012525 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 04:41:30.016038 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 04:41:30.022678 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 04:41:30.025690 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 04:41:30.028928 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 04:41:30.035602 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4417 04:41:30.039080 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 04:41:30.043036 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 04:41:30.049748 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 04:41:30.052654 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 04:41:30.055632 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 04:41:30.062247 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 04:41:30.066023 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 04:41:30.069753 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 04:41:30.075869 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 04:41:30.078801 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 04:41:30.082756 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 04:41:30.089309 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 04:41:30.092248 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 04:41:30.095250 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 04:41:30.102077 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 04:41:30.105513 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4433 04:41:30.108639 Total UI for P1: 0, mck2ui 16
4434 04:41:30.112516 best dqsien dly found for B0: ( 0, 9, 2)
4435 04:41:30.115297 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4436 04:41:30.118409 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 04:41:30.121608 Total UI for P1: 0, mck2ui 16
4438 04:41:30.125226 best dqsien dly found for B1: ( 0, 9, 10)
4439 04:41:30.128464 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4440 04:41:30.131945 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4441 04:41:30.135282
4442 04:41:30.139114 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4443 04:41:30.142615 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4444 04:41:30.145848 [Gating] SW calibration Done
4445 04:41:30.145929 ==
4446 04:41:30.148577 Dram Type= 6, Freq= 0, CH_1, rank 1
4447 04:41:30.151640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4448 04:41:30.151721 ==
4449 04:41:30.151785 RX Vref Scan: 0
4450 04:41:30.155574
4451 04:41:30.155655 RX Vref 0 -> 0, step: 1
4452 04:41:30.155719
4453 04:41:30.158427 RX Delay -230 -> 252, step: 16
4454 04:41:30.161995 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4455 04:41:30.168218 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4456 04:41:30.172232 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4457 04:41:30.174885 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4458 04:41:30.178393 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4459 04:41:30.181934 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4460 04:41:30.188596 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4461 04:41:30.191621 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4462 04:41:30.194787 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4463 04:41:30.198851 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4464 04:41:30.204564 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4465 04:41:30.207877 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4466 04:41:30.211801 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4467 04:41:30.214750 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4468 04:41:30.221583 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4469 04:41:30.224659 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4470 04:41:30.224813 ==
4471 04:41:30.227694 Dram Type= 6, Freq= 0, CH_1, rank 1
4472 04:41:30.231171 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4473 04:41:30.231278 ==
4474 04:41:30.234378 DQS Delay:
4475 04:41:30.234483 DQS0 = 0, DQS1 = 0
4476 04:41:30.238196 DQM Delay:
4477 04:41:30.238303 DQM0 = 43, DQM1 = 35
4478 04:41:30.238397 DQ Delay:
4479 04:41:30.241103 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4480 04:41:30.244100 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4481 04:41:30.247625 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4482 04:41:30.251222 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4483 04:41:30.251328
4484 04:41:30.251419
4485 04:41:30.251507 ==
4486 04:41:30.254384 Dram Type= 6, Freq= 0, CH_1, rank 1
4487 04:41:30.260630 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4488 04:41:30.260775 ==
4489 04:41:30.260869
4490 04:41:30.260959
4491 04:41:30.264241 TX Vref Scan disable
4492 04:41:30.264350 == TX Byte 0 ==
4493 04:41:30.267541 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4494 04:41:30.274205 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4495 04:41:30.274314 == TX Byte 1 ==
4496 04:41:30.280445 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4497 04:41:30.284046 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4498 04:41:30.284153 ==
4499 04:41:30.287134 Dram Type= 6, Freq= 0, CH_1, rank 1
4500 04:41:30.290224 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4501 04:41:30.290330 ==
4502 04:41:30.290424
4503 04:41:30.290514
4504 04:41:30.294038 TX Vref Scan disable
4505 04:41:30.297443 == TX Byte 0 ==
4506 04:41:30.300394 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4507 04:41:30.304036 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4508 04:41:30.306921 == TX Byte 1 ==
4509 04:41:30.309869 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4510 04:41:30.313287 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4511 04:41:30.313392
4512 04:41:30.316469 [DATLAT]
4513 04:41:30.316578 Freq=600, CH1 RK1
4514 04:41:30.316672
4515 04:41:30.320383 DATLAT Default: 0x8
4516 04:41:30.320488 0, 0xFFFF, sum = 0
4517 04:41:30.323422 1, 0xFFFF, sum = 0
4518 04:41:30.323528 2, 0xFFFF, sum = 0
4519 04:41:30.326956 3, 0xFFFF, sum = 0
4520 04:41:30.327063 4, 0xFFFF, sum = 0
4521 04:41:30.330478 5, 0xFFFF, sum = 0
4522 04:41:30.330585 6, 0xFFFF, sum = 0
4523 04:41:30.334228 7, 0x0, sum = 1
4524 04:41:30.334334 8, 0x0, sum = 2
4525 04:41:30.336384 9, 0x0, sum = 3
4526 04:41:30.336490 10, 0x0, sum = 4
4527 04:41:30.340073 best_step = 8
4528 04:41:30.340177
4529 04:41:30.340268 ==
4530 04:41:30.343585 Dram Type= 6, Freq= 0, CH_1, rank 1
4531 04:41:30.346885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4532 04:41:30.346991 ==
4533 04:41:30.349637 RX Vref Scan: 0
4534 04:41:30.349742
4535 04:41:30.349834 RX Vref 0 -> 0, step: 1
4536 04:41:30.349924
4537 04:41:30.353337 RX Delay -195 -> 252, step: 8
4538 04:41:30.360228 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4539 04:41:30.363622 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4540 04:41:30.366741 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4541 04:41:30.369929 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4542 04:41:30.376505 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4543 04:41:30.379789 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4544 04:41:30.383063 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4545 04:41:30.386676 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4546 04:41:30.390094 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4547 04:41:30.396700 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4548 04:41:30.399784 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4549 04:41:30.403544 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4550 04:41:30.407027 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4551 04:41:30.413130 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4552 04:41:30.416324 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4553 04:41:30.419546 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4554 04:41:30.419652 ==
4555 04:41:30.422721 Dram Type= 6, Freq= 0, CH_1, rank 1
4556 04:41:30.429268 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4557 04:41:30.429382 ==
4558 04:41:30.429478 DQS Delay:
4559 04:41:30.429609 DQS0 = 0, DQS1 = 0
4560 04:41:30.432890 DQM Delay:
4561 04:41:30.432990 DQM0 = 36, DQM1 = 29
4562 04:41:30.436237 DQ Delay:
4563 04:41:30.439262 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4564 04:41:30.442798 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4565 04:41:30.446069 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =20
4566 04:41:30.449185 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4567 04:41:30.449267
4568 04:41:30.449337
4569 04:41:30.455686 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4570 04:41:30.459395 CH1 RK1: MR19=808, MR18=5F5F
4571 04:41:30.465701 CH1_RK1: MR19=0x808, MR18=0x5F5F, DQSOSC=391, MR23=63, INC=171, DEC=114
4572 04:41:30.469141 [RxdqsGatingPostProcess] freq 600
4573 04:41:30.473669 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4574 04:41:30.475622 Pre-setting of DQS Precalculation
4575 04:41:30.482667 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4576 04:41:30.488873 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4577 04:41:30.495930 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4578 04:41:30.496015
4579 04:41:30.496079
4580 04:41:30.498530 [Calibration Summary] 1200 Mbps
4581 04:41:30.498633 CH 0, Rank 0
4582 04:41:30.501916 SW Impedance : PASS
4583 04:41:30.505567 DUTY Scan : NO K
4584 04:41:30.505692 ZQ Calibration : PASS
4585 04:41:30.508779 Jitter Meter : NO K
4586 04:41:30.511922 CBT Training : PASS
4587 04:41:30.512004 Write leveling : PASS
4588 04:41:30.515151 RX DQS gating : PASS
4589 04:41:30.518348 RX DQ/DQS(RDDQC) : PASS
4590 04:41:30.518430 TX DQ/DQS : PASS
4591 04:41:30.522043 RX DATLAT : PASS
4592 04:41:30.524840 RX DQ/DQS(Engine): PASS
4593 04:41:30.524935 TX OE : NO K
4594 04:41:30.528384 All Pass.
4595 04:41:30.528494
4596 04:41:30.528559 CH 0, Rank 1
4597 04:41:30.531770 SW Impedance : PASS
4598 04:41:30.531850 DUTY Scan : NO K
4599 04:41:30.534756 ZQ Calibration : PASS
4600 04:41:30.538256 Jitter Meter : NO K
4601 04:41:30.538367 CBT Training : PASS
4602 04:41:30.542034 Write leveling : PASS
4603 04:41:30.545553 RX DQS gating : PASS
4604 04:41:30.545635 RX DQ/DQS(RDDQC) : PASS
4605 04:41:30.548199 TX DQ/DQS : PASS
4606 04:41:30.551864 RX DATLAT : PASS
4607 04:41:30.551944 RX DQ/DQS(Engine): PASS
4608 04:41:30.554889 TX OE : NO K
4609 04:41:30.554971 All Pass.
4610 04:41:30.555063
4611 04:41:30.558149 CH 1, Rank 0
4612 04:41:30.558229 SW Impedance : PASS
4613 04:41:30.561339 DUTY Scan : NO K
4614 04:41:30.561420 ZQ Calibration : PASS
4615 04:41:30.564572 Jitter Meter : NO K
4616 04:41:30.568035 CBT Training : PASS
4617 04:41:30.568148 Write leveling : PASS
4618 04:41:30.571966 RX DQS gating : PASS
4619 04:41:30.574654 RX DQ/DQS(RDDQC) : PASS
4620 04:41:30.574777 TX DQ/DQS : PASS
4621 04:41:30.578018 RX DATLAT : PASS
4622 04:41:30.581296 RX DQ/DQS(Engine): PASS
4623 04:41:30.581398 TX OE : NO K
4624 04:41:30.585043 All Pass.
4625 04:41:30.585160
4626 04:41:30.585224 CH 1, Rank 1
4627 04:41:30.587827 SW Impedance : PASS
4628 04:41:30.587907 DUTY Scan : NO K
4629 04:41:30.591205 ZQ Calibration : PASS
4630 04:41:30.594429 Jitter Meter : NO K
4631 04:41:30.594511 CBT Training : PASS
4632 04:41:30.597894 Write leveling : PASS
4633 04:41:30.600814 RX DQS gating : PASS
4634 04:41:30.600931 RX DQ/DQS(RDDQC) : PASS
4635 04:41:30.604436 TX DQ/DQS : PASS
4636 04:41:30.607826 RX DATLAT : PASS
4637 04:41:30.607944 RX DQ/DQS(Engine): PASS
4638 04:41:30.611108 TX OE : NO K
4639 04:41:30.611189 All Pass.
4640 04:41:30.611254
4641 04:41:30.614888 DramC Write-DBI off
4642 04:41:30.617446 PER_BANK_REFRESH: Hybrid Mode
4643 04:41:30.617556 TX_TRACKING: ON
4644 04:41:30.627548 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4645 04:41:30.630790 [FAST_K] Save calibration result to emmc
4646 04:41:30.634526 dramc_set_vcore_voltage set vcore to 662500
4647 04:41:30.637085 Read voltage for 933, 3
4648 04:41:30.637169 Vio18 = 0
4649 04:41:30.637234 Vcore = 662500
4650 04:41:30.640655 Vdram = 0
4651 04:41:30.640786 Vddq = 0
4652 04:41:30.640894 Vmddr = 0
4653 04:41:30.647033 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4654 04:41:30.650254 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4655 04:41:30.654256 MEM_TYPE=3, freq_sel=17
4656 04:41:30.657578 sv_algorithm_assistance_LP4_1600
4657 04:41:30.660749 ============ PULL DRAM RESETB DOWN ============
4658 04:41:30.664243 ========== PULL DRAM RESETB DOWN end =========
4659 04:41:30.671247 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4660 04:41:30.674026 ===================================
4661 04:41:30.676950 LPDDR4 DRAM CONFIGURATION
4662 04:41:30.680085 ===================================
4663 04:41:30.680168 EX_ROW_EN[0] = 0x0
4664 04:41:30.683484 EX_ROW_EN[1] = 0x0
4665 04:41:30.683593 LP4Y_EN = 0x0
4666 04:41:30.687157 WORK_FSP = 0x0
4667 04:41:30.687239 WL = 0x3
4668 04:41:30.689986 RL = 0x3
4669 04:41:30.690069 BL = 0x2
4670 04:41:30.693433 RPST = 0x0
4671 04:41:30.693515 RD_PRE = 0x0
4672 04:41:30.697058 WR_PRE = 0x1
4673 04:41:30.697141 WR_PST = 0x0
4674 04:41:30.699942 DBI_WR = 0x0
4675 04:41:30.700024 DBI_RD = 0x0
4676 04:41:30.703390 OTF = 0x1
4677 04:41:30.706709 ===================================
4678 04:41:30.710661 ===================================
4679 04:41:30.710751 ANA top config
4680 04:41:30.713491 ===================================
4681 04:41:30.717834 DLL_ASYNC_EN = 0
4682 04:41:30.720183 ALL_SLAVE_EN = 1
4683 04:41:30.723260 NEW_RANK_MODE = 1
4684 04:41:30.723342 DLL_IDLE_MODE = 1
4685 04:41:30.726931 LP45_APHY_COMB_EN = 1
4686 04:41:30.730779 TX_ODT_DIS = 1
4687 04:41:30.733764 NEW_8X_MODE = 1
4688 04:41:30.736639 ===================================
4689 04:41:30.740118 ===================================
4690 04:41:30.742777 data_rate = 1866
4691 04:41:30.746327 CKR = 1
4692 04:41:30.746412 DQ_P2S_RATIO = 8
4693 04:41:30.749948 ===================================
4694 04:41:30.752694 CA_P2S_RATIO = 8
4695 04:41:30.756298 DQ_CA_OPEN = 0
4696 04:41:30.759316 DQ_SEMI_OPEN = 0
4697 04:41:30.763017 CA_SEMI_OPEN = 0
4698 04:41:30.766163 CA_FULL_RATE = 0
4699 04:41:30.766335 DQ_CKDIV4_EN = 1
4700 04:41:30.769348 CA_CKDIV4_EN = 1
4701 04:41:30.772812 CA_PREDIV_EN = 0
4702 04:41:30.777005 PH8_DLY = 0
4703 04:41:30.779583 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4704 04:41:30.782412 DQ_AAMCK_DIV = 4
4705 04:41:30.782518 CA_AAMCK_DIV = 4
4706 04:41:30.785728 CA_ADMCK_DIV = 4
4707 04:41:30.789884 DQ_TRACK_CA_EN = 0
4708 04:41:30.792312 CA_PICK = 933
4709 04:41:30.795841 CA_MCKIO = 933
4710 04:41:30.799346 MCKIO_SEMI = 0
4711 04:41:30.802909 PLL_FREQ = 3732
4712 04:41:30.803016 DQ_UI_PI_RATIO = 32
4713 04:41:30.806455 CA_UI_PI_RATIO = 0
4714 04:41:30.809416 ===================================
4715 04:41:30.813158 ===================================
4716 04:41:30.816051 memory_type:LPDDR4
4717 04:41:30.819094 GP_NUM : 10
4718 04:41:30.819201 SRAM_EN : 1
4719 04:41:30.822368 MD32_EN : 0
4720 04:41:30.825918 ===================================
4721 04:41:30.829171 [ANA_INIT] >>>>>>>>>>>>>>
4722 04:41:30.829279 <<<<<< [CONFIGURE PHASE]: ANA_TX
4723 04:41:30.836003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4724 04:41:30.836116 ===================================
4725 04:41:30.839039 data_rate = 1866,PCW = 0X8f00
4726 04:41:30.842116 ===================================
4727 04:41:30.845573 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4728 04:41:30.851971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4729 04:41:30.858882 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4730 04:41:30.862068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4731 04:41:30.865248 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4732 04:41:30.868246 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4733 04:41:30.871922 [ANA_INIT] flow start
4734 04:41:30.872033 [ANA_INIT] PLL >>>>>>>>
4735 04:41:30.875431 [ANA_INIT] PLL <<<<<<<<
4736 04:41:30.878635 [ANA_INIT] MIDPI >>>>>>>>
4737 04:41:30.881966 [ANA_INIT] MIDPI <<<<<<<<
4738 04:41:30.882075 [ANA_INIT] DLL >>>>>>>>
4739 04:41:30.885159 [ANA_INIT] flow end
4740 04:41:30.889338 ============ LP4 DIFF to SE enter ============
4741 04:41:30.891369 ============ LP4 DIFF to SE exit ============
4742 04:41:30.894832 [ANA_INIT] <<<<<<<<<<<<<
4743 04:41:30.898623 [Flow] Enable top DCM control >>>>>
4744 04:41:30.902041 [Flow] Enable top DCM control <<<<<
4745 04:41:30.905299 Enable DLL master slave shuffle
4746 04:41:30.912130 ==============================================================
4747 04:41:30.912240 Gating Mode config
4748 04:41:30.918874 ==============================================================
4749 04:41:30.918986 Config description:
4750 04:41:30.928509 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4751 04:41:30.935135 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4752 04:41:30.941473 SELPH_MODE 0: By rank 1: By Phase
4753 04:41:30.944951 ==============================================================
4754 04:41:30.948503 GAT_TRACK_EN = 1
4755 04:41:30.951748 RX_GATING_MODE = 2
4756 04:41:30.954770 RX_GATING_TRACK_MODE = 2
4757 04:41:30.957854 SELPH_MODE = 1
4758 04:41:30.961391 PICG_EARLY_EN = 1
4759 04:41:30.965089 VALID_LAT_VALUE = 1
4760 04:41:30.971620 ==============================================================
4761 04:41:30.974254 Enter into Gating configuration >>>>
4762 04:41:30.977961 Exit from Gating configuration <<<<
4763 04:41:30.981071 Enter into DVFS_PRE_config >>>>>
4764 04:41:30.990674 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4765 04:41:30.994045 Exit from DVFS_PRE_config <<<<<
4766 04:41:30.997574 Enter into PICG configuration >>>>
4767 04:41:31.000865 Exit from PICG configuration <<<<
4768 04:41:31.004240 [RX_INPUT] configuration >>>>>
4769 04:41:31.004351 [RX_INPUT] configuration <<<<<
4770 04:41:31.010636 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4771 04:41:31.017169 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4772 04:41:31.020385 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4773 04:41:31.027332 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4774 04:41:31.033603 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4775 04:41:31.040860 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4776 04:41:31.043576 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4777 04:41:31.046889 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4778 04:41:31.053606 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4779 04:41:31.056874 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4780 04:41:31.061584 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4781 04:41:31.066801 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4782 04:41:31.070341 ===================================
4783 04:41:31.070428 LPDDR4 DRAM CONFIGURATION
4784 04:41:31.073368 ===================================
4785 04:41:31.076651 EX_ROW_EN[0] = 0x0
4786 04:41:31.079781 EX_ROW_EN[1] = 0x0
4787 04:41:31.079867 LP4Y_EN = 0x0
4788 04:41:31.083565 WORK_FSP = 0x0
4789 04:41:31.083654 WL = 0x3
4790 04:41:31.086341 RL = 0x3
4791 04:41:31.086420 BL = 0x2
4792 04:41:31.089580 RPST = 0x0
4793 04:41:31.089654 RD_PRE = 0x0
4794 04:41:31.092986 WR_PRE = 0x1
4795 04:41:31.093061 WR_PST = 0x0
4796 04:41:31.096460 DBI_WR = 0x0
4797 04:41:31.096537 DBI_RD = 0x0
4798 04:41:31.099803 OTF = 0x1
4799 04:41:31.102888 ===================================
4800 04:41:31.106420 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4801 04:41:31.110151 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4802 04:41:31.116417 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4803 04:41:31.119817 ===================================
4804 04:41:31.119929 LPDDR4 DRAM CONFIGURATION
4805 04:41:31.122915 ===================================
4806 04:41:31.126499 EX_ROW_EN[0] = 0x10
4807 04:41:31.129222 EX_ROW_EN[1] = 0x0
4808 04:41:31.129330 LP4Y_EN = 0x0
4809 04:41:31.132804 WORK_FSP = 0x0
4810 04:41:31.132911 WL = 0x3
4811 04:41:31.136292 RL = 0x3
4812 04:41:31.136411 BL = 0x2
4813 04:41:31.139391 RPST = 0x0
4814 04:41:31.139499 RD_PRE = 0x0
4815 04:41:31.143296 WR_PRE = 0x1
4816 04:41:31.143406 WR_PST = 0x0
4817 04:41:31.146596 DBI_WR = 0x0
4818 04:41:31.146704 DBI_RD = 0x0
4819 04:41:31.150024 OTF = 0x1
4820 04:41:31.152386 ===================================
4821 04:41:31.159710 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4822 04:41:31.163431 nWR fixed to 30
4823 04:41:31.163547 [ModeRegInit_LP4] CH0 RK0
4824 04:41:31.165554 [ModeRegInit_LP4] CH0 RK1
4825 04:41:31.169132 [ModeRegInit_LP4] CH1 RK0
4826 04:41:31.173053 [ModeRegInit_LP4] CH1 RK1
4827 04:41:31.173166 match AC timing 8
4828 04:41:31.179070 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4829 04:41:31.182478 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4830 04:41:31.185806 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4831 04:41:31.192655 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4832 04:41:31.195942 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4833 04:41:31.196046 ==
4834 04:41:31.198697 Dram Type= 6, Freq= 0, CH_0, rank 0
4835 04:41:31.202535 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4836 04:41:31.202639 ==
4837 04:41:31.208774 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4838 04:41:31.215424 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4839 04:41:31.218539 [CA 0] Center 38 (8~69) winsize 62
4840 04:41:31.221965 [CA 1] Center 38 (8~69) winsize 62
4841 04:41:31.225634 [CA 2] Center 36 (6~67) winsize 62
4842 04:41:31.228854 [CA 3] Center 35 (5~66) winsize 62
4843 04:41:31.232502 [CA 4] Center 34 (4~65) winsize 62
4844 04:41:31.235064 [CA 5] Center 34 (4~65) winsize 62
4845 04:41:31.235165
4846 04:41:31.239109 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4847 04:41:31.239212
4848 04:41:31.242604 [CATrainingPosCal] consider 1 rank data
4849 04:41:31.245519 u2DelayCellTimex100 = 270/100 ps
4850 04:41:31.248869 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4851 04:41:31.252306 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4852 04:41:31.255495 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4853 04:41:31.258765 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4854 04:41:31.261577 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4855 04:41:31.265010 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4856 04:41:31.265116
4857 04:41:31.272648 CA PerBit enable=1, Macro0, CA PI delay=34
4858 04:41:31.272773
4859 04:41:31.275211 [CBTSetCACLKResult] CA Dly = 34
4860 04:41:31.275313 CS Dly: 7 (0~38)
4861 04:41:31.275401 ==
4862 04:41:31.278285 Dram Type= 6, Freq= 0, CH_0, rank 1
4863 04:41:31.281574 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4864 04:41:31.281678 ==
4865 04:41:31.288011 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4866 04:41:31.294593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4867 04:41:31.298273 [CA 0] Center 38 (8~69) winsize 62
4868 04:41:31.301596 [CA 1] Center 38 (8~69) winsize 62
4869 04:41:31.304702 [CA 2] Center 36 (5~67) winsize 63
4870 04:41:31.307864 [CA 3] Center 35 (5~66) winsize 62
4871 04:41:31.311527 [CA 4] Center 34 (4~65) winsize 62
4872 04:41:31.314808 [CA 5] Center 34 (4~64) winsize 61
4873 04:41:31.314913
4874 04:41:31.317492 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4875 04:41:31.317609
4876 04:41:31.321089 [CATrainingPosCal] consider 2 rank data
4877 04:41:31.324984 u2DelayCellTimex100 = 270/100 ps
4878 04:41:31.327536 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4879 04:41:31.330729 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4880 04:41:31.334155 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4881 04:41:31.337675 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4882 04:41:31.344498 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4883 04:41:31.347603 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4884 04:41:31.347682
4885 04:41:31.350737 CA PerBit enable=1, Macro0, CA PI delay=34
4886 04:41:31.350830
4887 04:41:31.353979 [CBTSetCACLKResult] CA Dly = 34
4888 04:41:31.354067 CS Dly: 7 (0~39)
4889 04:41:31.354130
4890 04:41:31.357354 ----->DramcWriteLeveling(PI) begin...
4891 04:41:31.357426 ==
4892 04:41:31.360637 Dram Type= 6, Freq= 0, CH_0, rank 0
4893 04:41:31.367183 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4894 04:41:31.367308 ==
4895 04:41:31.370575 Write leveling (Byte 0): 29 => 29
4896 04:41:31.374386 Write leveling (Byte 1): 27 => 27
4897 04:41:31.374473 DramcWriteLeveling(PI) end<-----
4898 04:41:31.378393
4899 04:41:31.378479 ==
4900 04:41:31.380809 Dram Type= 6, Freq= 0, CH_0, rank 0
4901 04:41:31.384126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4902 04:41:31.384223 ==
4903 04:41:31.386895 [Gating] SW mode calibration
4904 04:41:31.393810 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4905 04:41:31.397507 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4906 04:41:31.403946 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4907 04:41:31.406858 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4908 04:41:31.410145 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4909 04:41:31.417038 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4910 04:41:31.419856 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4911 04:41:31.423626 0 10 20 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (1 0)
4912 04:41:31.430401 0 10 24 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4913 04:41:31.433055 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4914 04:41:31.436720 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4915 04:41:31.443226 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4916 04:41:31.446368 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4917 04:41:31.450914 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4918 04:41:31.456527 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4919 04:41:31.459564 0 11 20 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
4920 04:41:31.462658 0 11 24 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
4921 04:41:31.469537 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4922 04:41:31.472677 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4923 04:41:31.476300 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4924 04:41:31.482586 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4925 04:41:31.486339 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4926 04:41:31.489472 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4927 04:41:31.495874 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4928 04:41:31.499083 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4929 04:41:31.502825 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4930 04:41:31.509147 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4931 04:41:31.512681 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4932 04:41:31.516006 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 04:41:31.522638 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 04:41:31.526327 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 04:41:31.529492 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 04:41:31.536085 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 04:41:31.539528 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 04:41:31.542309 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 04:41:31.549651 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 04:41:31.552581 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 04:41:31.555833 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 04:41:31.561999 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 04:41:31.565864 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4944 04:41:31.568959 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4945 04:41:31.572140 Total UI for P1: 0, mck2ui 16
4946 04:41:31.575554 best dqsien dly found for B0: ( 0, 14, 20)
4947 04:41:31.578479 Total UI for P1: 0, mck2ui 16
4948 04:41:31.582133 best dqsien dly found for B1: ( 0, 14, 20)
4949 04:41:31.585207 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4950 04:41:31.588901 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4951 04:41:31.591669
4952 04:41:31.594957 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4953 04:41:31.598553 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4954 04:41:31.602073 [Gating] SW calibration Done
4955 04:41:31.602161 ==
4956 04:41:31.604972 Dram Type= 6, Freq= 0, CH_0, rank 0
4957 04:41:31.608942 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4958 04:41:31.609033 ==
4959 04:41:31.609122 RX Vref Scan: 0
4960 04:41:31.609206
4961 04:41:31.612814 RX Vref 0 -> 0, step: 1
4962 04:41:31.612901
4963 04:41:31.614894 RX Delay -80 -> 252, step: 8
4964 04:41:31.618779 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4965 04:41:31.622384 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4966 04:41:31.628094 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4967 04:41:31.631751 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4968 04:41:31.635333 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4969 04:41:31.638573 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4970 04:41:31.641750 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4971 04:41:31.645100 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
4972 04:41:31.651528 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4973 04:41:31.654822 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4974 04:41:31.658384 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
4975 04:41:31.661663 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4976 04:41:31.665542 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4977 04:41:31.671770 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4978 04:41:31.674501 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4979 04:41:31.677991 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4980 04:41:31.678078 ==
4981 04:41:31.681618 Dram Type= 6, Freq= 0, CH_0, rank 0
4982 04:41:31.685019 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4983 04:41:31.685107 ==
4984 04:41:31.688300 DQS Delay:
4985 04:41:31.688386 DQS0 = 0, DQS1 = 0
4986 04:41:31.688489 DQM Delay:
4987 04:41:31.690921 DQM0 = 95, DQM1 = 86
4988 04:41:31.691008 DQ Delay:
4989 04:41:31.694369 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
4990 04:41:31.697987 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
4991 04:41:31.700848 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
4992 04:41:31.703991 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
4993 04:41:31.704076
4994 04:41:31.704163
4995 04:41:31.707446 ==
4996 04:41:31.707532 Dram Type= 6, Freq= 0, CH_0, rank 0
4997 04:41:31.714200 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4998 04:41:31.714326 ==
4999 04:41:31.714425
5000 04:41:31.714509
5001 04:41:31.717570 TX Vref Scan disable
5002 04:41:31.717749 == TX Byte 0 ==
5003 04:41:31.723514 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5004 04:41:31.727180 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5005 04:41:31.727295 == TX Byte 1 ==
5006 04:41:31.733823 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5007 04:41:31.736806 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5008 04:41:31.736947 ==
5009 04:41:31.740164 Dram Type= 6, Freq= 0, CH_0, rank 0
5010 04:41:31.743985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5011 04:41:31.744078 ==
5012 04:41:31.744151
5013 04:41:31.744213
5014 04:41:31.747052 TX Vref Scan disable
5015 04:41:31.750542 == TX Byte 0 ==
5016 04:41:31.753689 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5017 04:41:31.756633 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5018 04:41:31.760213 == TX Byte 1 ==
5019 04:41:31.763257 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5020 04:41:31.767175 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5021 04:41:31.767295
5022 04:41:31.770085 [DATLAT]
5023 04:41:31.770175 Freq=933, CH0 RK0
5024 04:41:31.770251
5025 04:41:31.773659 DATLAT Default: 0xd
5026 04:41:31.773757 0, 0xFFFF, sum = 0
5027 04:41:31.776945 1, 0xFFFF, sum = 0
5028 04:41:31.777030 2, 0xFFFF, sum = 0
5029 04:41:31.780254 3, 0xFFFF, sum = 0
5030 04:41:31.780335 4, 0xFFFF, sum = 0
5031 04:41:31.783768 5, 0xFFFF, sum = 0
5032 04:41:31.783843 6, 0xFFFF, sum = 0
5033 04:41:31.786345 7, 0xFFFF, sum = 0
5034 04:41:31.786424 8, 0xFFFF, sum = 0
5035 04:41:31.789853 9, 0xFFFF, sum = 0
5036 04:41:31.789934 10, 0x0, sum = 1
5037 04:41:31.793056 11, 0x0, sum = 2
5038 04:41:31.793139 12, 0x0, sum = 3
5039 04:41:31.796371 13, 0x0, sum = 4
5040 04:41:31.796452 best_step = 11
5041 04:41:31.796516
5042 04:41:31.796614 ==
5043 04:41:31.799977 Dram Type= 6, Freq= 0, CH_0, rank 0
5044 04:41:31.806426 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5045 04:41:31.806513 ==
5046 04:41:31.806579 RX Vref Scan: 1
5047 04:41:31.806640
5048 04:41:31.809685 RX Vref 0 -> 0, step: 1
5049 04:41:31.809762
5050 04:41:31.813400 RX Delay -69 -> 252, step: 4
5051 04:41:31.813475
5052 04:41:31.816202 Set Vref, RX VrefLevel [Byte0]: 50
5053 04:41:31.820026 [Byte1]: 45
5054 04:41:31.820102
5055 04:41:31.822783 Final RX Vref Byte 0 = 50 to rank0
5056 04:41:31.826763 Final RX Vref Byte 1 = 45 to rank0
5057 04:41:31.829596 Final RX Vref Byte 0 = 50 to rank1
5058 04:41:31.833808 Final RX Vref Byte 1 = 45 to rank1==
5059 04:41:31.836041 Dram Type= 6, Freq= 0, CH_0, rank 0
5060 04:41:31.839807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5061 04:41:31.839883 ==
5062 04:41:31.842762 DQS Delay:
5063 04:41:31.842848 DQS0 = 0, DQS1 = 0
5064 04:41:31.847083 DQM Delay:
5065 04:41:31.847168 DQM0 = 96, DQM1 = 87
5066 04:41:31.847234 DQ Delay:
5067 04:41:31.849327 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =94
5068 04:41:31.852686 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =102
5069 04:41:31.855972 DQ8 =78, DQ9 =70, DQ10 =88, DQ11 =78
5070 04:41:31.859163 DQ12 =94, DQ13 =96, DQ14 =98, DQ15 =96
5071 04:41:31.859246
5072 04:41:31.859310
5073 04:41:31.869235 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5074 04:41:31.872474 CH0 RK0: MR19=505, MR18=1F1F
5075 04:41:31.879021 CH0_RK0: MR19=0x505, MR18=0x1F1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5076 04:41:31.879103
5077 04:41:31.882360 ----->DramcWriteLeveling(PI) begin...
5078 04:41:31.882442 ==
5079 04:41:31.886528 Dram Type= 6, Freq= 0, CH_0, rank 1
5080 04:41:31.888918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5081 04:41:31.888997 ==
5082 04:41:31.892848 Write leveling (Byte 0): 28 => 28
5083 04:41:31.895681 Write leveling (Byte 1): 26 => 26
5084 04:41:31.899297 DramcWriteLeveling(PI) end<-----
5085 04:41:31.899382
5086 04:41:31.899447 ==
5087 04:41:31.902647 Dram Type= 6, Freq= 0, CH_0, rank 1
5088 04:41:31.905728 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5089 04:41:31.905800 ==
5090 04:41:31.908683 [Gating] SW mode calibration
5091 04:41:31.915353 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5092 04:41:31.922780 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5093 04:41:31.925377 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 04:41:31.928790 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 04:41:31.935724 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 04:41:31.939242 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 04:41:31.941928 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 04:41:31.948541 0 10 20 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (0 0)
5099 04:41:31.951844 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5100 04:41:31.955386 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 04:41:31.962259 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 04:41:31.965412 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 04:41:31.968755 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 04:41:31.975037 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 04:41:31.978781 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 04:41:31.981952 0 11 20 | B1->B0 | 2828 3333 | 0 0 | (1 1) (0 0)
5107 04:41:31.988977 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5108 04:41:31.991860 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 04:41:31.994917 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 04:41:32.001720 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 04:41:32.004607 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 04:41:32.008421 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 04:41:32.014577 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 04:41:32.018286 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5115 04:41:32.021277 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5116 04:41:32.028717 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 04:41:32.031466 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 04:41:32.034647 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 04:41:32.041150 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 04:41:32.044382 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 04:41:32.048012 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 04:41:32.054589 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 04:41:32.058722 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 04:41:32.060811 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 04:41:32.067586 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 04:41:32.070934 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 04:41:32.073981 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 04:41:32.080941 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 04:41:32.083884 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5130 04:41:32.087741 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5131 04:41:32.093782 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 04:41:32.093909 Total UI for P1: 0, mck2ui 16
5133 04:41:32.101145 best dqsien dly found for B0: ( 0, 14, 18)
5134 04:41:32.101245 Total UI for P1: 0, mck2ui 16
5135 04:41:32.107208 best dqsien dly found for B1: ( 0, 14, 22)
5136 04:41:32.110592 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5137 04:41:32.113587 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5138 04:41:32.113681
5139 04:41:32.117273 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5140 04:41:32.120197 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5141 04:41:32.123553 [Gating] SW calibration Done
5142 04:41:32.123635 ==
5143 04:41:32.126876 Dram Type= 6, Freq= 0, CH_0, rank 1
5144 04:41:32.130268 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5145 04:41:32.130344 ==
5146 04:41:32.133691 RX Vref Scan: 0
5147 04:41:32.133776
5148 04:41:32.133841 RX Vref 0 -> 0, step: 1
5149 04:41:32.136875
5150 04:41:32.136986 RX Delay -80 -> 252, step: 8
5151 04:41:32.143576 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5152 04:41:32.147566 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5153 04:41:32.150909 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5154 04:41:32.154182 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5155 04:41:32.156690 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5156 04:41:32.160205 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5157 04:41:32.167012 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5158 04:41:32.169994 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5159 04:41:32.173235 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5160 04:41:32.176255 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5161 04:41:32.180115 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5162 04:41:32.186842 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5163 04:41:32.189999 iDelay=208, Bit 12, Center 99 (16 ~ 183) 168
5164 04:41:32.193287 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5165 04:41:32.196186 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5166 04:41:32.199833 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5167 04:41:32.199914 ==
5168 04:41:32.203358 Dram Type= 6, Freq= 0, CH_0, rank 1
5169 04:41:32.209381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5170 04:41:32.209462 ==
5171 04:41:32.209527 DQS Delay:
5172 04:41:32.213154 DQS0 = 0, DQS1 = 0
5173 04:41:32.213235 DQM Delay:
5174 04:41:32.215996 DQM0 = 96, DQM1 = 86
5175 04:41:32.216076 DQ Delay:
5176 04:41:32.219378 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5177 04:41:32.222499 DQ4 =99, DQ5 =91, DQ6 =111, DQ7 =107
5178 04:41:32.226360 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =75
5179 04:41:32.229159 DQ12 =99, DQ13 =91, DQ14 =91, DQ15 =95
5180 04:41:32.229255
5181 04:41:32.229353
5182 04:41:32.229419 ==
5183 04:41:32.232658 Dram Type= 6, Freq= 0, CH_0, rank 1
5184 04:41:32.235748 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5185 04:41:32.235816 ==
5186 04:41:32.235875
5187 04:41:32.235938
5188 04:41:32.239296 TX Vref Scan disable
5189 04:41:32.242296 == TX Byte 0 ==
5190 04:41:32.245592 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5191 04:41:32.249072 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5192 04:41:32.252169 == TX Byte 1 ==
5193 04:41:32.255611 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5194 04:41:32.258816 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5195 04:41:32.258911 ==
5196 04:41:32.262135 Dram Type= 6, Freq= 0, CH_0, rank 1
5197 04:41:32.269101 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5198 04:41:32.269259 ==
5199 04:41:32.269354
5200 04:41:32.269433
5201 04:41:32.269512 TX Vref Scan disable
5202 04:41:32.272687 == TX Byte 0 ==
5203 04:41:32.276518 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5204 04:41:32.283261 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5205 04:41:32.283363 == TX Byte 1 ==
5206 04:41:32.286078 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5207 04:41:32.292448 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5208 04:41:32.292548
5209 04:41:32.292645 [DATLAT]
5210 04:41:32.292777 Freq=933, CH0 RK1
5211 04:41:32.292854
5212 04:41:32.295978 DATLAT Default: 0xb
5213 04:41:32.296076 0, 0xFFFF, sum = 0
5214 04:41:32.299147 1, 0xFFFF, sum = 0
5215 04:41:32.299232 2, 0xFFFF, sum = 0
5216 04:41:32.302788 3, 0xFFFF, sum = 0
5217 04:41:32.305858 4, 0xFFFF, sum = 0
5218 04:41:32.305940 5, 0xFFFF, sum = 0
5219 04:41:32.308966 6, 0xFFFF, sum = 0
5220 04:41:32.309048 7, 0xFFFF, sum = 0
5221 04:41:32.312799 8, 0xFFFF, sum = 0
5222 04:41:32.312880 9, 0xFFFF, sum = 0
5223 04:41:32.315477 10, 0x0, sum = 1
5224 04:41:32.315559 11, 0x0, sum = 2
5225 04:41:32.319038 12, 0x0, sum = 3
5226 04:41:32.319120 13, 0x0, sum = 4
5227 04:41:32.319213 best_step = 11
5228 04:41:32.322738
5229 04:41:32.322835 ==
5230 04:41:32.325627 Dram Type= 6, Freq= 0, CH_0, rank 1
5231 04:41:32.329247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5232 04:41:32.329329 ==
5233 04:41:32.329393 RX Vref Scan: 0
5234 04:41:32.329452
5235 04:41:32.332335 RX Vref 0 -> 0, step: 1
5236 04:41:32.332415
5237 04:41:32.335698 RX Delay -61 -> 252, step: 4
5238 04:41:32.342169 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5239 04:41:32.345314 iDelay=203, Bit 1, Center 100 (7 ~ 194) 188
5240 04:41:32.349060 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5241 04:41:32.352063 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5242 04:41:32.355839 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5243 04:41:32.358537 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5244 04:41:32.365143 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5245 04:41:32.368965 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5246 04:41:32.372112 iDelay=203, Bit 8, Center 74 (-13 ~ 162) 176
5247 04:41:32.375758 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5248 04:41:32.379374 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5249 04:41:32.385464 iDelay=203, Bit 11, Center 80 (-5 ~ 166) 172
5250 04:41:32.388595 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5251 04:41:32.391837 iDelay=203, Bit 13, Center 92 (3 ~ 182) 180
5252 04:41:32.395704 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5253 04:41:32.398564 iDelay=203, Bit 15, Center 94 (7 ~ 182) 176
5254 04:41:32.398647 ==
5255 04:41:32.401688 Dram Type= 6, Freq= 0, CH_0, rank 1
5256 04:41:32.408276 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5257 04:41:32.408360 ==
5258 04:41:32.408426 DQS Delay:
5259 04:41:32.408488 DQS0 = 0, DQS1 = 0
5260 04:41:32.411956 DQM Delay:
5261 04:41:32.412038 DQM0 = 98, DQM1 = 86
5262 04:41:32.415419 DQ Delay:
5263 04:41:32.418518 DQ0 =94, DQ1 =100, DQ2 =96, DQ3 =92
5264 04:41:32.421385 DQ4 =102, DQ5 =90, DQ6 =104, DQ7 =108
5265 04:41:32.425132 DQ8 =74, DQ9 =72, DQ10 =88, DQ11 =80
5266 04:41:32.428409 DQ12 =94, DQ13 =92, DQ14 =96, DQ15 =94
5267 04:41:32.428515
5268 04:41:32.428616
5269 04:41:32.434719 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d2d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5270 04:41:32.438263 CH0 RK1: MR19=505, MR18=2D2D
5271 04:41:32.444443 CH0_RK1: MR19=0x505, MR18=0x2D2D, DQSOSC=407, MR23=63, INC=65, DEC=43
5272 04:41:32.448162 [RxdqsGatingPostProcess] freq 933
5273 04:41:32.451363 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5274 04:41:32.454570 Pre-setting of DQS Precalculation
5275 04:41:32.461818 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5276 04:41:32.461902 ==
5277 04:41:32.464522 Dram Type= 6, Freq= 0, CH_1, rank 0
5278 04:41:32.467500 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5279 04:41:32.467584 ==
5280 04:41:32.474377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5281 04:41:32.480911 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5282 04:41:32.484683 [CA 0] Center 37 (7~68) winsize 62
5283 04:41:32.488141 [CA 1] Center 37 (6~68) winsize 63
5284 04:41:32.491232 [CA 2] Center 34 (4~65) winsize 62
5285 04:41:32.494671 [CA 3] Center 34 (4~65) winsize 62
5286 04:41:32.498017 [CA 4] Center 33 (2~64) winsize 63
5287 04:41:32.501169 [CA 5] Center 33 (3~64) winsize 62
5288 04:41:32.501243
5289 04:41:32.504344 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5290 04:41:32.504414
5291 04:41:32.507591 [CATrainingPosCal] consider 1 rank data
5292 04:41:32.511183 u2DelayCellTimex100 = 270/100 ps
5293 04:41:32.514295 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5294 04:41:32.517794 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5295 04:41:32.521078 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5296 04:41:32.524224 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5297 04:41:32.527643 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5298 04:41:32.531083 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5299 04:41:32.531165
5300 04:41:32.537392 CA PerBit enable=1, Macro0, CA PI delay=33
5301 04:41:32.537475
5302 04:41:32.541168 [CBTSetCACLKResult] CA Dly = 33
5303 04:41:32.541250 CS Dly: 5 (0~36)
5304 04:41:32.541316 ==
5305 04:41:32.544032 Dram Type= 6, Freq= 0, CH_1, rank 1
5306 04:41:32.547341 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5307 04:41:32.547424 ==
5308 04:41:32.553747 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5309 04:41:32.560221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5310 04:41:32.563577 [CA 0] Center 37 (6~68) winsize 63
5311 04:41:32.567127 [CA 1] Center 37 (6~68) winsize 63
5312 04:41:32.570396 [CA 2] Center 34 (4~65) winsize 62
5313 04:41:32.573838 [CA 3] Center 33 (3~64) winsize 62
5314 04:41:32.577417 [CA 4] Center 33 (2~64) winsize 63
5315 04:41:32.580342 [CA 5] Center 32 (2~63) winsize 62
5316 04:41:32.580424
5317 04:41:32.583801 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5318 04:41:32.583883
5319 04:41:32.587157 [CATrainingPosCal] consider 2 rank data
5320 04:41:32.590458 u2DelayCellTimex100 = 270/100 ps
5321 04:41:32.593886 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5322 04:41:32.596834 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5323 04:41:32.600460 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5324 04:41:32.603550 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5325 04:41:32.606473 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5326 04:41:32.613667 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5327 04:41:32.613748
5328 04:41:32.617202 CA PerBit enable=1, Macro0, CA PI delay=33
5329 04:41:32.617283
5330 04:41:32.619942 [CBTSetCACLKResult] CA Dly = 33
5331 04:41:32.620022 CS Dly: 5 (0~37)
5332 04:41:32.620087
5333 04:41:32.623418 ----->DramcWriteLeveling(PI) begin...
5334 04:41:32.623500 ==
5335 04:41:32.626946 Dram Type= 6, Freq= 0, CH_1, rank 0
5336 04:41:32.633344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5337 04:41:32.633426 ==
5338 04:41:32.636923 Write leveling (Byte 0): 26 => 26
5339 04:41:32.637004 Write leveling (Byte 1): 26 => 26
5340 04:41:32.639632 DramcWriteLeveling(PI) end<-----
5341 04:41:32.639714
5342 04:41:32.639780 ==
5343 04:41:32.643319 Dram Type= 6, Freq= 0, CH_1, rank 0
5344 04:41:32.649782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5345 04:41:32.649863 ==
5346 04:41:32.653735 [Gating] SW mode calibration
5347 04:41:32.659832 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5348 04:41:32.662863 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5349 04:41:32.669518 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 04:41:32.672976 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 04:41:32.676254 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 04:41:32.683293 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5353 04:41:32.686217 0 10 16 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5354 04:41:32.689277 0 10 20 | B1->B0 | 3333 2424 | 1 0 | (0 1) (1 0)
5355 04:41:32.695971 0 10 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5356 04:41:32.699225 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 04:41:32.702933 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 04:41:32.709686 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 04:41:32.712890 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 04:41:32.715854 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 04:41:32.722216 0 11 16 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5362 04:41:32.725814 0 11 20 | B1->B0 | 2929 4545 | 0 0 | (0 0) (0 0)
5363 04:41:32.729476 0 11 24 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5364 04:41:32.735745 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 04:41:32.739336 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 04:41:32.742213 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 04:41:32.749049 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 04:41:32.752297 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 04:41:32.755938 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5370 04:41:32.762091 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5371 04:41:32.765323 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 04:41:32.768924 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 04:41:32.775870 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 04:41:32.778892 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 04:41:32.782197 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 04:41:32.788694 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 04:41:32.791870 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 04:41:32.795170 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 04:41:32.798599 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 04:41:32.805169 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 04:41:32.808439 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 04:41:32.811987 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 04:41:32.818716 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 04:41:32.822566 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 04:41:32.825164 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5386 04:41:32.832583 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 04:41:32.834883 Total UI for P1: 0, mck2ui 16
5388 04:41:32.838385 best dqsien dly found for B0: ( 0, 14, 16)
5389 04:41:32.841842 Total UI for P1: 0, mck2ui 16
5390 04:41:32.844999 best dqsien dly found for B1: ( 0, 14, 18)
5391 04:41:32.848078 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5392 04:41:32.851494 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5393 04:41:32.851578
5394 04:41:32.855022 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5395 04:41:32.858236 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5396 04:41:32.861947 [Gating] SW calibration Done
5397 04:41:32.862021 ==
5398 04:41:32.864848 Dram Type= 6, Freq= 0, CH_1, rank 0
5399 04:41:32.868058 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5400 04:41:32.868188 ==
5401 04:41:32.871657 RX Vref Scan: 0
5402 04:41:32.871758
5403 04:41:32.874734 RX Vref 0 -> 0, step: 1
5404 04:41:32.874838
5405 04:41:32.874927 RX Delay -80 -> 252, step: 8
5406 04:41:32.881811 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5407 04:41:32.884745 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5408 04:41:32.887768 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5409 04:41:32.891177 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5410 04:41:32.894703 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5411 04:41:32.897618 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5412 04:41:32.904626 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5413 04:41:32.907568 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5414 04:41:32.911267 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5415 04:41:32.914129 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5416 04:41:32.917882 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5417 04:41:32.925106 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5418 04:41:32.927417 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5419 04:41:32.930930 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5420 04:41:32.934641 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5421 04:41:32.937384 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5422 04:41:32.937473 ==
5423 04:41:32.940667 Dram Type= 6, Freq= 0, CH_1, rank 0
5424 04:41:32.947457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5425 04:41:32.947560 ==
5426 04:41:32.947645 DQS Delay:
5427 04:41:32.951020 DQS0 = 0, DQS1 = 0
5428 04:41:32.951117 DQM Delay:
5429 04:41:32.951196 DQM0 = 94, DQM1 = 87
5430 04:41:32.954315 DQ Delay:
5431 04:41:32.957685 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =91
5432 04:41:32.960647 DQ4 =91, DQ5 =107, DQ6 =99, DQ7 =91
5433 04:41:32.964110 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5434 04:41:32.967469 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5435 04:41:32.967550
5436 04:41:32.967648
5437 04:41:32.967744 ==
5438 04:41:32.971080 Dram Type= 6, Freq= 0, CH_1, rank 0
5439 04:41:32.974607 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5440 04:41:32.974707 ==
5441 04:41:32.974808
5442 04:41:32.974904
5443 04:41:32.977923 TX Vref Scan disable
5444 04:41:32.980614 == TX Byte 0 ==
5445 04:41:32.984388 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5446 04:41:32.987284 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5447 04:41:32.990827 == TX Byte 1 ==
5448 04:41:32.994262 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5449 04:41:32.997689 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5450 04:41:32.997787 ==
5451 04:41:33.000676 Dram Type= 6, Freq= 0, CH_1, rank 0
5452 04:41:33.003807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5453 04:41:33.003890 ==
5454 04:41:33.006999
5455 04:41:33.007080
5456 04:41:33.007173 TX Vref Scan disable
5457 04:41:33.010615 == TX Byte 0 ==
5458 04:41:33.013606 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5459 04:41:33.020067 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5460 04:41:33.020151 == TX Byte 1 ==
5461 04:41:33.023857 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5462 04:41:33.030261 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5463 04:41:33.030344
5464 04:41:33.030410 [DATLAT]
5465 04:41:33.030471 Freq=933, CH1 RK0
5466 04:41:33.030531
5467 04:41:33.033552 DATLAT Default: 0xd
5468 04:41:33.033635 0, 0xFFFF, sum = 0
5469 04:41:33.036802 1, 0xFFFF, sum = 0
5470 04:41:33.040715 2, 0xFFFF, sum = 0
5471 04:41:33.040798 3, 0xFFFF, sum = 0
5472 04:41:33.043432 4, 0xFFFF, sum = 0
5473 04:41:33.043516 5, 0xFFFF, sum = 0
5474 04:41:33.046786 6, 0xFFFF, sum = 0
5475 04:41:33.046870 7, 0xFFFF, sum = 0
5476 04:41:33.050435 8, 0xFFFF, sum = 0
5477 04:41:33.050520 9, 0xFFFF, sum = 0
5478 04:41:33.053679 10, 0x0, sum = 1
5479 04:41:33.053763 11, 0x0, sum = 2
5480 04:41:33.056967 12, 0x0, sum = 3
5481 04:41:33.057052 13, 0x0, sum = 4
5482 04:41:33.057119 best_step = 11
5483 04:41:33.057181
5484 04:41:33.060375 ==
5485 04:41:33.063552 Dram Type= 6, Freq= 0, CH_1, rank 0
5486 04:41:33.067221 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5487 04:41:33.067305 ==
5488 04:41:33.067372 RX Vref Scan: 1
5489 04:41:33.067433
5490 04:41:33.070440 RX Vref 0 -> 0, step: 1
5491 04:41:33.070530
5492 04:41:33.073904 RX Delay -69 -> 252, step: 4
5493 04:41:33.073984
5494 04:41:33.076667 Set Vref, RX VrefLevel [Byte0]: 62
5495 04:41:33.080006 [Byte1]: 47
5496 04:41:33.080089
5497 04:41:33.083818 Final RX Vref Byte 0 = 62 to rank0
5498 04:41:33.086778 Final RX Vref Byte 1 = 47 to rank0
5499 04:41:33.090200 Final RX Vref Byte 0 = 62 to rank1
5500 04:41:33.093182 Final RX Vref Byte 1 = 47 to rank1==
5501 04:41:33.096582 Dram Type= 6, Freq= 0, CH_1, rank 0
5502 04:41:33.100177 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5503 04:41:33.103313 ==
5504 04:41:33.103384 DQS Delay:
5505 04:41:33.103446 DQS0 = 0, DQS1 = 0
5506 04:41:33.106918 DQM Delay:
5507 04:41:33.106993 DQM0 = 93, DQM1 = 88
5508 04:41:33.110025 DQ Delay:
5509 04:41:33.113187 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =92
5510 04:41:33.116586 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5511 04:41:33.119855 DQ8 =70, DQ9 =78, DQ10 =88, DQ11 =78
5512 04:41:33.123032 DQ12 =96, DQ13 =100, DQ14 =96, DQ15 =98
5513 04:41:33.123106
5514 04:41:33.123168
5515 04:41:33.129733 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f2f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5516 04:41:33.132882 CH1 RK0: MR19=505, MR18=2F2F
5517 04:41:33.139574 CH1_RK0: MR19=0x505, MR18=0x2F2F, DQSOSC=407, MR23=63, INC=65, DEC=43
5518 04:41:33.139650
5519 04:41:33.143209 ----->DramcWriteLeveling(PI) begin...
5520 04:41:33.143300 ==
5521 04:41:33.146512 Dram Type= 6, Freq= 0, CH_1, rank 1
5522 04:41:33.149263 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5523 04:41:33.149340 ==
5524 04:41:33.152741 Write leveling (Byte 0): 26 => 26
5525 04:41:33.156651 Write leveling (Byte 1): 27 => 27
5526 04:41:33.160076 DramcWriteLeveling(PI) end<-----
5527 04:41:33.160170
5528 04:41:33.160266 ==
5529 04:41:33.162777 Dram Type= 6, Freq= 0, CH_1, rank 1
5530 04:41:33.166207 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5531 04:41:33.166305 ==
5532 04:41:33.169623 [Gating] SW mode calibration
5533 04:41:33.175822 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5534 04:41:33.182620 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5535 04:41:33.185815 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5536 04:41:33.192348 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5537 04:41:33.195699 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5538 04:41:33.198918 0 10 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5539 04:41:33.205803 0 10 16 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
5540 04:41:33.208936 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5541 04:41:33.212609 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5542 04:41:33.219704 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5543 04:41:33.222648 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5544 04:41:33.225598 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5545 04:41:33.232631 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5546 04:41:33.235346 0 11 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5547 04:41:33.239045 0 11 16 | B1->B0 | 2525 4141 | 0 0 | (0 0) (0 0)
5548 04:41:33.246045 0 11 20 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
5549 04:41:33.248871 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5550 04:41:33.252201 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5551 04:41:33.258825 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5552 04:41:33.261960 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5553 04:41:33.265179 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5554 04:41:33.268610 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5555 04:41:33.275113 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5556 04:41:33.278669 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5557 04:41:33.281658 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5558 04:41:33.289094 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5559 04:41:33.292174 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5560 04:41:33.295041 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 04:41:33.301404 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 04:41:33.305312 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 04:41:33.308305 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 04:41:33.315311 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 04:41:33.318218 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 04:41:33.321804 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 04:41:33.328022 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 04:41:33.331880 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 04:41:33.334655 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 04:41:33.341347 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5571 04:41:33.344400 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5572 04:41:33.347848 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5573 04:41:33.354190 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 04:41:33.358458 Total UI for P1: 0, mck2ui 16
5575 04:41:33.361046 best dqsien dly found for B0: ( 0, 14, 16)
5576 04:41:33.364350 Total UI for P1: 0, mck2ui 16
5577 04:41:33.367773 best dqsien dly found for B1: ( 0, 14, 18)
5578 04:41:33.371212 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5579 04:41:33.374029 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5580 04:41:33.374103
5581 04:41:33.377538 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5582 04:41:33.380928 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5583 04:41:33.384156 [Gating] SW calibration Done
5584 04:41:33.384237 ==
5585 04:41:33.387567 Dram Type= 6, Freq= 0, CH_1, rank 1
5586 04:41:33.391363 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5587 04:41:33.391445 ==
5588 04:41:33.394338 RX Vref Scan: 0
5589 04:41:33.394436
5590 04:41:33.397818 RX Vref 0 -> 0, step: 1
5591 04:41:33.397899
5592 04:41:33.397963 RX Delay -80 -> 252, step: 8
5593 04:41:33.404033 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5594 04:41:33.407669 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5595 04:41:33.411269 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5596 04:41:33.413893 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5597 04:41:33.417507 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5598 04:41:33.420610 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5599 04:41:33.427854 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5600 04:41:33.431280 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5601 04:41:33.433897 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5602 04:41:33.437341 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5603 04:41:33.440445 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5604 04:41:33.444052 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5605 04:41:33.450783 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5606 04:41:33.453999 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5607 04:41:33.457261 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5608 04:41:33.460263 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5609 04:41:33.460360 ==
5610 04:41:33.463845 Dram Type= 6, Freq= 0, CH_1, rank 1
5611 04:41:33.470369 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5612 04:41:33.470454 ==
5613 04:41:33.470534 DQS Delay:
5614 04:41:33.470594 DQS0 = 0, DQS1 = 0
5615 04:41:33.473902 DQM Delay:
5616 04:41:33.473985 DQM0 = 98, DQM1 = 88
5617 04:41:33.477571 DQ Delay:
5618 04:41:33.480248 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5619 04:41:33.483676 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5620 04:41:33.487321 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5621 04:41:33.490123 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5622 04:41:33.490205
5623 04:41:33.490270
5624 04:41:33.490329 ==
5625 04:41:33.493739 Dram Type= 6, Freq= 0, CH_1, rank 1
5626 04:41:33.497149 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5627 04:41:33.497231 ==
5628 04:41:33.497296
5629 04:41:33.497356
5630 04:41:33.500046 TX Vref Scan disable
5631 04:41:33.500127 == TX Byte 0 ==
5632 04:41:33.506918 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5633 04:41:33.510495 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5634 04:41:33.510575 == TX Byte 1 ==
5635 04:41:33.516877 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5636 04:41:33.520189 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5637 04:41:33.520264 ==
5638 04:41:33.523378 Dram Type= 6, Freq= 0, CH_1, rank 1
5639 04:41:33.526765 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5640 04:41:33.526846 ==
5641 04:41:33.526945
5642 04:41:33.527038
5643 04:41:33.530748 TX Vref Scan disable
5644 04:41:33.533276 == TX Byte 0 ==
5645 04:41:33.536834 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5646 04:41:33.540145 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5647 04:41:33.543685 == TX Byte 1 ==
5648 04:41:33.546701 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5649 04:41:33.550494 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5650 04:41:33.550568
5651 04:41:33.553293 [DATLAT]
5652 04:41:33.553362 Freq=933, CH1 RK1
5653 04:41:33.553428
5654 04:41:33.556572 DATLAT Default: 0xb
5655 04:41:33.556646 0, 0xFFFF, sum = 0
5656 04:41:33.560123 1, 0xFFFF, sum = 0
5657 04:41:33.560197 2, 0xFFFF, sum = 0
5658 04:41:33.563093 3, 0xFFFF, sum = 0
5659 04:41:33.563167 4, 0xFFFF, sum = 0
5660 04:41:33.566609 5, 0xFFFF, sum = 0
5661 04:41:33.569888 6, 0xFFFF, sum = 0
5662 04:41:33.569964 7, 0xFFFF, sum = 0
5663 04:41:33.573035 8, 0xFFFF, sum = 0
5664 04:41:33.573124 9, 0xFFFF, sum = 0
5665 04:41:33.576943 10, 0x0, sum = 1
5666 04:41:33.577016 11, 0x0, sum = 2
5667 04:41:33.577083 12, 0x0, sum = 3
5668 04:41:33.579591 13, 0x0, sum = 4
5669 04:41:33.579663 best_step = 11
5670 04:41:33.579725
5671 04:41:33.583119 ==
5672 04:41:33.583208 Dram Type= 6, Freq= 0, CH_1, rank 1
5673 04:41:33.589407 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5674 04:41:33.589488 ==
5675 04:41:33.589552 RX Vref Scan: 0
5676 04:41:33.589611
5677 04:41:33.592786 RX Vref 0 -> 0, step: 1
5678 04:41:33.592861
5679 04:41:33.596628 RX Delay -69 -> 252, step: 4
5680 04:41:33.599713 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5681 04:41:33.605768 iDelay=199, Bit 1, Center 90 (-5 ~ 186) 192
5682 04:41:33.609305 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5683 04:41:33.612542 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5684 04:41:33.616527 iDelay=199, Bit 4, Center 94 (-1 ~ 190) 192
5685 04:41:33.618923 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5686 04:41:33.626435 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5687 04:41:33.628879 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5688 04:41:33.632318 iDelay=199, Bit 8, Center 74 (-17 ~ 166) 184
5689 04:41:33.635873 iDelay=199, Bit 9, Center 76 (-13 ~ 166) 180
5690 04:41:33.639527 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5691 04:41:33.645285 iDelay=199, Bit 11, Center 80 (-13 ~ 174) 188
5692 04:41:33.648666 iDelay=199, Bit 12, Center 96 (3 ~ 190) 188
5693 04:41:33.652271 iDelay=199, Bit 13, Center 98 (11 ~ 186) 176
5694 04:41:33.655294 iDelay=199, Bit 14, Center 96 (3 ~ 190) 188
5695 04:41:33.658774 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5696 04:41:33.658929 ==
5697 04:41:33.661891 Dram Type= 6, Freq= 0, CH_1, rank 1
5698 04:41:33.668874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5699 04:41:33.669061 ==
5700 04:41:33.669236 DQS Delay:
5701 04:41:33.671939 DQS0 = 0, DQS1 = 0
5702 04:41:33.672127 DQM Delay:
5703 04:41:33.672256 DQM0 = 94, DQM1 = 87
5704 04:41:33.675308 DQ Delay:
5705 04:41:33.678560 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5706 04:41:33.682461 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5707 04:41:33.685786 DQ8 =74, DQ9 =76, DQ10 =86, DQ11 =80
5708 04:41:33.688808 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5709 04:41:33.688960
5710 04:41:33.689114
5711 04:41:33.695002 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5712 04:41:33.698184 CH1 RK1: MR19=505, MR18=2020
5713 04:41:33.705026 CH1_RK1: MR19=0x505, MR18=0x2020, DQSOSC=411, MR23=63, INC=64, DEC=42
5714 04:41:33.708380 [RxdqsGatingPostProcess] freq 933
5715 04:41:33.711755 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5716 04:41:33.715548 Pre-setting of DQS Precalculation
5717 04:41:33.721270 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5718 04:41:33.728939 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5719 04:41:33.734813 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5720 04:41:33.734923
5721 04:41:33.735020
5722 04:41:33.738681 [Calibration Summary] 1866 Mbps
5723 04:41:33.741370 CH 0, Rank 0
5724 04:41:33.741474 SW Impedance : PASS
5725 04:41:33.744862 DUTY Scan : NO K
5726 04:41:33.748380 ZQ Calibration : PASS
5727 04:41:33.748483 Jitter Meter : NO K
5728 04:41:33.751170 CBT Training : PASS
5729 04:41:33.755113 Write leveling : PASS
5730 04:41:33.755204 RX DQS gating : PASS
5731 04:41:33.758332 RX DQ/DQS(RDDQC) : PASS
5732 04:41:33.758466 TX DQ/DQS : PASS
5733 04:41:33.761078 RX DATLAT : PASS
5734 04:41:33.764380 RX DQ/DQS(Engine): PASS
5735 04:41:33.764493 TX OE : NO K
5736 04:41:33.768353 All Pass.
5737 04:41:33.768471
5738 04:41:33.768567 CH 0, Rank 1
5739 04:41:33.771357 SW Impedance : PASS
5740 04:41:33.771469 DUTY Scan : NO K
5741 04:41:33.774775 ZQ Calibration : PASS
5742 04:41:33.778324 Jitter Meter : NO K
5743 04:41:33.778441 CBT Training : PASS
5744 04:41:33.781242 Write leveling : PASS
5745 04:41:33.784612 RX DQS gating : PASS
5746 04:41:33.784745 RX DQ/DQS(RDDQC) : PASS
5747 04:41:33.787891 TX DQ/DQS : PASS
5748 04:41:33.791896 RX DATLAT : PASS
5749 04:41:33.792037 RX DQ/DQS(Engine): PASS
5750 04:41:33.794398 TX OE : NO K
5751 04:41:33.794509 All Pass.
5752 04:41:33.794605
5753 04:41:33.797978 CH 1, Rank 0
5754 04:41:33.798061 SW Impedance : PASS
5755 04:41:33.800880 DUTY Scan : NO K
5756 04:41:33.804448 ZQ Calibration : PASS
5757 04:41:33.804557 Jitter Meter : NO K
5758 04:41:33.807467 CBT Training : PASS
5759 04:41:33.807577 Write leveling : PASS
5760 04:41:33.811241 RX DQS gating : PASS
5761 04:41:33.814468 RX DQ/DQS(RDDQC) : PASS
5762 04:41:33.814582 TX DQ/DQS : PASS
5763 04:41:33.817502 RX DATLAT : PASS
5764 04:41:33.820703 RX DQ/DQS(Engine): PASS
5765 04:41:33.820787 TX OE : NO K
5766 04:41:33.823917 All Pass.
5767 04:41:33.824001
5768 04:41:33.824067 CH 1, Rank 1
5769 04:41:33.828415 SW Impedance : PASS
5770 04:41:33.828529 DUTY Scan : NO K
5771 04:41:33.831216 ZQ Calibration : PASS
5772 04:41:33.834124 Jitter Meter : NO K
5773 04:41:33.834208 CBT Training : PASS
5774 04:41:33.837815 Write leveling : PASS
5775 04:41:33.840932 RX DQS gating : PASS
5776 04:41:33.841016 RX DQ/DQS(RDDQC) : PASS
5777 04:41:33.844183 TX DQ/DQS : PASS
5778 04:41:33.847214 RX DATLAT : PASS
5779 04:41:33.847297 RX DQ/DQS(Engine): PASS
5780 04:41:33.851282 TX OE : NO K
5781 04:41:33.851366 All Pass.
5782 04:41:33.851433
5783 04:41:33.854038 DramC Write-DBI off
5784 04:41:33.857736 PER_BANK_REFRESH: Hybrid Mode
5785 04:41:33.857820 TX_TRACKING: ON
5786 04:41:33.867002 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5787 04:41:33.870437 [FAST_K] Save calibration result to emmc
5788 04:41:33.874103 dramc_set_vcore_voltage set vcore to 650000
5789 04:41:33.876932 Read voltage for 400, 6
5790 04:41:33.877018 Vio18 = 0
5791 04:41:33.877084 Vcore = 650000
5792 04:41:33.880669 Vdram = 0
5793 04:41:33.880783 Vddq = 0
5794 04:41:33.880892 Vmddr = 0
5795 04:41:33.886891 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5796 04:41:33.890511 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5797 04:41:33.894097 MEM_TYPE=3, freq_sel=20
5798 04:41:33.897141 sv_algorithm_assistance_LP4_800
5799 04:41:33.900584 ============ PULL DRAM RESETB DOWN ============
5800 04:41:33.903811 ========== PULL DRAM RESETB DOWN end =========
5801 04:41:33.910434 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5802 04:41:33.913677 ===================================
5803 04:41:33.916522 LPDDR4 DRAM CONFIGURATION
5804 04:41:33.920183 ===================================
5805 04:41:33.920287 EX_ROW_EN[0] = 0x0
5806 04:41:33.923046 EX_ROW_EN[1] = 0x0
5807 04:41:33.923155 LP4Y_EN = 0x0
5808 04:41:33.926420 WORK_FSP = 0x0
5809 04:41:33.926530 WL = 0x2
5810 04:41:33.929903 RL = 0x2
5811 04:41:33.930003 BL = 0x2
5812 04:41:33.933596 RPST = 0x0
5813 04:41:33.933679 RD_PRE = 0x0
5814 04:41:33.936286 WR_PRE = 0x1
5815 04:41:33.936370 WR_PST = 0x0
5816 04:41:33.939891 DBI_WR = 0x0
5817 04:41:33.939974 DBI_RD = 0x0
5818 04:41:33.943194 OTF = 0x1
5819 04:41:33.946498 ===================================
5820 04:41:33.949651 ===================================
5821 04:41:33.949780 ANA top config
5822 04:41:33.953176 ===================================
5823 04:41:33.956306 DLL_ASYNC_EN = 0
5824 04:41:33.959970 ALL_SLAVE_EN = 1
5825 04:41:33.962824 NEW_RANK_MODE = 1
5826 04:41:33.962961 DLL_IDLE_MODE = 1
5827 04:41:33.966325 LP45_APHY_COMB_EN = 1
5828 04:41:33.969604 TX_ODT_DIS = 1
5829 04:41:33.973278 NEW_8X_MODE = 1
5830 04:41:33.976207 ===================================
5831 04:41:33.979650 ===================================
5832 04:41:33.982672 data_rate = 800
5833 04:41:33.986223 CKR = 1
5834 04:41:33.986327 DQ_P2S_RATIO = 4
5835 04:41:33.989428 ===================================
5836 04:41:33.993233 CA_P2S_RATIO = 4
5837 04:41:33.996084 DQ_CA_OPEN = 0
5838 04:41:33.999938 DQ_SEMI_OPEN = 1
5839 04:41:34.002939 CA_SEMI_OPEN = 1
5840 04:41:34.005842 CA_FULL_RATE = 0
5841 04:41:34.005934 DQ_CKDIV4_EN = 0
5842 04:41:34.009701 CA_CKDIV4_EN = 1
5843 04:41:34.012859 CA_PREDIV_EN = 0
5844 04:41:34.015814 PH8_DLY = 0
5845 04:41:34.019170 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5846 04:41:34.022578 DQ_AAMCK_DIV = 0
5847 04:41:34.022705 CA_AAMCK_DIV = 0
5848 04:41:34.025678 CA_ADMCK_DIV = 4
5849 04:41:34.029075 DQ_TRACK_CA_EN = 0
5850 04:41:34.032015 CA_PICK = 800
5851 04:41:34.036319 CA_MCKIO = 400
5852 04:41:34.039353 MCKIO_SEMI = 400
5853 04:41:34.042303 PLL_FREQ = 3016
5854 04:41:34.045265 DQ_UI_PI_RATIO = 32
5855 04:41:34.045377 CA_UI_PI_RATIO = 32
5856 04:41:34.049030 ===================================
5857 04:41:34.051966 ===================================
5858 04:41:34.055205 memory_type:LPDDR4
5859 04:41:34.058951 GP_NUM : 10
5860 04:41:34.059060 SRAM_EN : 1
5861 04:41:34.062062 MD32_EN : 0
5862 04:41:34.065534 ===================================
5863 04:41:34.069572 [ANA_INIT] >>>>>>>>>>>>>>
5864 04:41:34.072548 <<<<<< [CONFIGURE PHASE]: ANA_TX
5865 04:41:34.075269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5866 04:41:34.079187 ===================================
5867 04:41:34.079298 data_rate = 800,PCW = 0X7400
5868 04:41:34.082543 ===================================
5869 04:41:34.085082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5870 04:41:34.096723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5871 04:41:34.105350 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5872 04:41:34.108051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5873 04:41:34.112055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5874 04:41:34.115475 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5875 04:41:34.118719 [ANA_INIT] flow start
5876 04:41:34.118802 [ANA_INIT] PLL >>>>>>>>
5877 04:41:34.121894 [ANA_INIT] PLL <<<<<<<<
5878 04:41:34.124905 [ANA_INIT] MIDPI >>>>>>>>
5879 04:41:34.124988 [ANA_INIT] MIDPI <<<<<<<<
5880 04:41:34.128078 [ANA_INIT] DLL >>>>>>>>
5881 04:41:34.131273 [ANA_INIT] flow end
5882 04:41:34.135084 ============ LP4 DIFF to SE enter ============
5883 04:41:34.138032 ============ LP4 DIFF to SE exit ============
5884 04:41:34.141338 [ANA_INIT] <<<<<<<<<<<<<
5885 04:41:34.144955 [Flow] Enable top DCM control >>>>>
5886 04:41:34.148399 [Flow] Enable top DCM control <<<<<
5887 04:41:34.151148 Enable DLL master slave shuffle
5888 04:41:34.154375 ==============================================================
5889 04:41:34.158298 Gating Mode config
5890 04:41:34.164763 ==============================================================
5891 04:41:34.164846 Config description:
5892 04:41:34.174589 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5893 04:41:34.181132 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5894 04:41:34.187820 SELPH_MODE 0: By rank 1: By Phase
5895 04:41:34.191169 ==============================================================
5896 04:41:34.194180 GAT_TRACK_EN = 0
5897 04:41:34.197436 RX_GATING_MODE = 2
5898 04:41:34.201106 RX_GATING_TRACK_MODE = 2
5899 04:41:34.204125 SELPH_MODE = 1
5900 04:41:34.208280 PICG_EARLY_EN = 1
5901 04:41:34.211203 VALID_LAT_VALUE = 1
5902 04:41:34.213951 ==============================================================
5903 04:41:34.217342 Enter into Gating configuration >>>>
5904 04:41:34.220911 Exit from Gating configuration <<<<
5905 04:41:34.224681 Enter into DVFS_PRE_config >>>>>
5906 04:41:34.237391 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5907 04:41:34.240558 Exit from DVFS_PRE_config <<<<<
5908 04:41:34.244176 Enter into PICG configuration >>>>
5909 04:41:34.247200 Exit from PICG configuration <<<<
5910 04:41:34.247284 [RX_INPUT] configuration >>>>>
5911 04:41:34.250390 [RX_INPUT] configuration <<<<<
5912 04:41:34.256642 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5913 04:41:34.263361 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5914 04:41:34.266994 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5915 04:41:34.273760 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5916 04:41:34.280352 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5917 04:41:34.286462 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5918 04:41:34.289917 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5919 04:41:34.293669 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5920 04:41:34.300704 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5921 04:41:34.304134 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5922 04:41:34.306695 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5923 04:41:34.313645 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5924 04:41:34.316862 ===================================
5925 04:41:34.316947 LPDDR4 DRAM CONFIGURATION
5926 04:41:34.319923 ===================================
5927 04:41:34.323232 EX_ROW_EN[0] = 0x0
5928 04:41:34.323316 EX_ROW_EN[1] = 0x0
5929 04:41:34.326218 LP4Y_EN = 0x0
5930 04:41:34.326302 WORK_FSP = 0x0
5931 04:41:34.329505 WL = 0x2
5932 04:41:34.333231 RL = 0x2
5933 04:41:34.333315 BL = 0x2
5934 04:41:34.336367 RPST = 0x0
5935 04:41:34.336451 RD_PRE = 0x0
5936 04:41:34.339597 WR_PRE = 0x1
5937 04:41:34.339681 WR_PST = 0x0
5938 04:41:34.343195 DBI_WR = 0x0
5939 04:41:34.343281 DBI_RD = 0x0
5940 04:41:34.345809 OTF = 0x1
5941 04:41:34.349507 ===================================
5942 04:41:34.353403 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5943 04:41:34.355790 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5944 04:41:34.362906 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5945 04:41:34.365904 ===================================
5946 04:41:34.365981 LPDDR4 DRAM CONFIGURATION
5947 04:41:34.369252 ===================================
5948 04:41:34.372506 EX_ROW_EN[0] = 0x10
5949 04:41:34.372623 EX_ROW_EN[1] = 0x0
5950 04:41:34.375533 LP4Y_EN = 0x0
5951 04:41:34.378833 WORK_FSP = 0x0
5952 04:41:34.378926 WL = 0x2
5953 04:41:34.382641 RL = 0x2
5954 04:41:34.382716 BL = 0x2
5955 04:41:34.386084 RPST = 0x0
5956 04:41:34.386162 RD_PRE = 0x0
5957 04:41:34.388991 WR_PRE = 0x1
5958 04:41:34.389071 WR_PST = 0x0
5959 04:41:34.392219 DBI_WR = 0x0
5960 04:41:34.392304 DBI_RD = 0x0
5961 04:41:34.395538 OTF = 0x1
5962 04:41:34.398724 ===================================
5963 04:41:34.405433 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5964 04:41:34.408522 nWR fixed to 30
5965 04:41:34.408610 [ModeRegInit_LP4] CH0 RK0
5966 04:41:34.412092 [ModeRegInit_LP4] CH0 RK1
5967 04:41:34.415418 [ModeRegInit_LP4] CH1 RK0
5968 04:41:34.418799 [ModeRegInit_LP4] CH1 RK1
5969 04:41:34.418883 match AC timing 18
5970 04:41:34.421903 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5971 04:41:34.428376 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5972 04:41:34.432284 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5973 04:41:34.435210 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5974 04:41:34.442051 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5975 04:41:34.442129 ==
5976 04:41:34.445625 Dram Type= 6, Freq= 0, CH_0, rank 0
5977 04:41:34.448249 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5978 04:41:34.448330 ==
5979 04:41:34.454999 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5980 04:41:34.462104 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5981 04:41:34.465318 [CA 0] Center 36 (8~64) winsize 57
5982 04:41:34.465394 [CA 1] Center 36 (8~64) winsize 57
5983 04:41:34.468958 [CA 2] Center 36 (8~64) winsize 57
5984 04:41:34.471693 [CA 3] Center 36 (8~64) winsize 57
5985 04:41:34.474937 [CA 4] Center 36 (8~64) winsize 57
5986 04:41:34.478173 [CA 5] Center 36 (8~64) winsize 57
5987 04:41:34.478274
5988 04:41:34.481294 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5989 04:41:34.481369
5990 04:41:34.488194 [CATrainingPosCal] consider 1 rank data
5991 04:41:34.488272 u2DelayCellTimex100 = 270/100 ps
5992 04:41:34.491570 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5993 04:41:34.498374 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5994 04:41:34.501610 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
5995 04:41:34.505238 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
5996 04:41:34.508651 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
5997 04:41:34.511229 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
5998 04:41:34.511302
5999 04:41:34.514795 CA PerBit enable=1, Macro0, CA PI delay=36
6000 04:41:34.514893
6001 04:41:34.517739 [CBTSetCACLKResult] CA Dly = 36
6002 04:41:34.520955 CS Dly: 1 (0~32)
6003 04:41:34.521028 ==
6004 04:41:34.524776 Dram Type= 6, Freq= 0, CH_0, rank 1
6005 04:41:34.528031 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6006 04:41:34.528113 ==
6007 04:41:34.535125 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6008 04:41:34.538349 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6009 04:41:34.541280 [CA 0] Center 36 (8~64) winsize 57
6010 04:41:34.544330 [CA 1] Center 36 (8~64) winsize 57
6011 04:41:34.547583 [CA 2] Center 36 (8~64) winsize 57
6012 04:41:34.550820 [CA 3] Center 36 (8~64) winsize 57
6013 04:41:34.554688 [CA 4] Center 36 (8~64) winsize 57
6014 04:41:34.557241 [CA 5] Center 36 (8~64) winsize 57
6015 04:41:34.557314
6016 04:41:34.560887 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6017 04:41:34.560966
6018 04:41:34.563883 [CATrainingPosCal] consider 2 rank data
6019 04:41:34.568000 u2DelayCellTimex100 = 270/100 ps
6020 04:41:34.571053 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6021 04:41:34.574248 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6022 04:41:34.577400 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6023 04:41:34.584125 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6024 04:41:34.587247 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6025 04:41:34.590409 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6026 04:41:34.590483
6027 04:41:34.593777 CA PerBit enable=1, Macro0, CA PI delay=36
6028 04:41:34.593852
6029 04:41:34.597458 [CBTSetCACLKResult] CA Dly = 36
6030 04:41:34.597530 CS Dly: 1 (0~32)
6031 04:41:34.597592
6032 04:41:34.600540 ----->DramcWriteLeveling(PI) begin...
6033 04:41:34.603645 ==
6034 04:41:34.603735 Dram Type= 6, Freq= 0, CH_0, rank 0
6035 04:41:34.610508 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6036 04:41:34.610585 ==
6037 04:41:34.613716 Write leveling (Byte 0): 32 => 0
6038 04:41:34.617086 Write leveling (Byte 1): 32 => 0
6039 04:41:34.617172 DramcWriteLeveling(PI) end<-----
6040 04:41:34.620228
6041 04:41:34.620316 ==
6042 04:41:34.623801 Dram Type= 6, Freq= 0, CH_0, rank 0
6043 04:41:34.626711 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6044 04:41:34.626784 ==
6045 04:41:34.630404 [Gating] SW mode calibration
6046 04:41:34.637158 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6047 04:41:34.640875 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6048 04:41:34.646678 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6049 04:41:34.649916 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6050 04:41:34.653297 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6051 04:41:34.660210 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6052 04:41:34.663637 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6053 04:41:34.666478 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6054 04:41:34.673238 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6055 04:41:34.676308 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6056 04:41:34.680301 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6057 04:41:34.683243 Total UI for P1: 0, mck2ui 16
6058 04:41:34.686691 best dqsien dly found for B0: ( 0, 10, 16)
6059 04:41:34.689568 Total UI for P1: 0, mck2ui 16
6060 04:41:34.693237 best dqsien dly found for B1: ( 0, 10, 16)
6061 04:41:34.696155 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6062 04:41:34.703038 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6063 04:41:34.703147
6064 04:41:34.706220 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6065 04:41:34.710063 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6066 04:41:34.713120 [Gating] SW calibration Done
6067 04:41:34.713223 ==
6068 04:41:34.716428 Dram Type= 6, Freq= 0, CH_0, rank 0
6069 04:41:34.719841 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6070 04:41:34.719913 ==
6071 04:41:34.723132 RX Vref Scan: 0
6072 04:41:34.723208
6073 04:41:34.723272 RX Vref 0 -> 0, step: 1
6074 04:41:34.723355
6075 04:41:34.725973 RX Delay -410 -> 252, step: 16
6076 04:41:34.730117 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6077 04:41:34.736580 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6078 04:41:34.739534 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6079 04:41:34.742963 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6080 04:41:34.746223 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6081 04:41:34.752540 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6082 04:41:34.755965 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6083 04:41:34.759712 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6084 04:41:34.763043 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6085 04:41:34.770014 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6086 04:41:34.772350 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6087 04:41:34.775799 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6088 04:41:34.782718 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6089 04:41:34.786072 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6090 04:41:34.789003 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6091 04:41:34.791948 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6092 04:41:34.795281 ==
6093 04:41:34.795377 Dram Type= 6, Freq= 0, CH_0, rank 0
6094 04:41:34.802299 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6095 04:41:34.802385 ==
6096 04:41:34.802464 DQS Delay:
6097 04:41:34.805510 DQS0 = 43, DQS1 = 59
6098 04:41:34.805610 DQM Delay:
6099 04:41:34.808914 DQM0 = 5, DQM1 = 14
6100 04:41:34.809020 DQ Delay:
6101 04:41:34.812423 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6102 04:41:34.815901 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6103 04:41:34.818466 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6104 04:41:34.821762 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6105 04:41:34.821843
6106 04:41:34.821907
6107 04:41:34.821965 ==
6108 04:41:34.825150 Dram Type= 6, Freq= 0, CH_0, rank 0
6109 04:41:34.828356 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6110 04:41:34.828433 ==
6111 04:41:34.828496
6112 04:41:34.828555
6113 04:41:34.831928 TX Vref Scan disable
6114 04:41:34.832047 == TX Byte 0 ==
6115 04:41:34.838978 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6116 04:41:34.841638 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6117 04:41:34.841740 == TX Byte 1 ==
6118 04:41:34.848361 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6119 04:41:34.852102 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6120 04:41:34.852177 ==
6121 04:41:34.855088 Dram Type= 6, Freq= 0, CH_0, rank 0
6122 04:41:34.858480 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6123 04:41:34.858554 ==
6124 04:41:34.858620
6125 04:41:34.858682
6126 04:41:34.861727 TX Vref Scan disable
6127 04:41:34.861801 == TX Byte 0 ==
6128 04:41:34.868494 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6129 04:41:34.871550 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6130 04:41:34.871622 == TX Byte 1 ==
6131 04:41:34.877957 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6132 04:41:34.881254 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6133 04:41:34.881345
6134 04:41:34.881407 [DATLAT]
6135 04:41:34.885034 Freq=400, CH0 RK0
6136 04:41:34.885121
6137 04:41:34.885182 DATLAT Default: 0xf
6138 04:41:34.888145 0, 0xFFFF, sum = 0
6139 04:41:34.891446 1, 0xFFFF, sum = 0
6140 04:41:34.891519 2, 0xFFFF, sum = 0
6141 04:41:34.894508 3, 0xFFFF, sum = 0
6142 04:41:34.894593 4, 0xFFFF, sum = 0
6143 04:41:34.897715 5, 0xFFFF, sum = 0
6144 04:41:34.897800 6, 0xFFFF, sum = 0
6145 04:41:34.901084 7, 0xFFFF, sum = 0
6146 04:41:34.901158 8, 0xFFFF, sum = 0
6147 04:41:34.904183 9, 0xFFFF, sum = 0
6148 04:41:34.904272 10, 0xFFFF, sum = 0
6149 04:41:34.907711 11, 0xFFFF, sum = 0
6150 04:41:34.907797 12, 0x0, sum = 1
6151 04:41:34.911285 13, 0x0, sum = 2
6152 04:41:34.911368 14, 0x0, sum = 3
6153 04:41:34.914318 15, 0x0, sum = 4
6154 04:41:34.914389 best_step = 13
6155 04:41:34.914449
6156 04:41:34.914511 ==
6157 04:41:34.917516 Dram Type= 6, Freq= 0, CH_0, rank 0
6158 04:41:34.921139 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6159 04:41:34.924373 ==
6160 04:41:34.924457 RX Vref Scan: 1
6161 04:41:34.924522
6162 04:41:34.927531 RX Vref 0 -> 0, step: 1
6163 04:41:34.927616
6164 04:41:34.931169 RX Delay -359 -> 252, step: 8
6165 04:41:34.931246
6166 04:41:34.933984 Set Vref, RX VrefLevel [Byte0]: 50
6167 04:41:34.937678 [Byte1]: 45
6168 04:41:34.937751
6169 04:41:34.940655 Final RX Vref Byte 0 = 50 to rank0
6170 04:41:34.944069 Final RX Vref Byte 1 = 45 to rank0
6171 04:41:34.947690 Final RX Vref Byte 0 = 50 to rank1
6172 04:41:34.950851 Final RX Vref Byte 1 = 45 to rank1==
6173 04:41:34.954853 Dram Type= 6, Freq= 0, CH_0, rank 0
6174 04:41:34.957382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6175 04:41:34.957461 ==
6176 04:41:34.960396 DQS Delay:
6177 04:41:34.960469 DQS0 = 52, DQS1 = 68
6178 04:41:34.964430 DQM Delay:
6179 04:41:34.964501 DQM0 = 9, DQM1 = 17
6180 04:41:34.967247 DQ Delay:
6181 04:41:34.967320 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6182 04:41:34.970689 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6183 04:41:34.974178 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6184 04:41:34.977249 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =28
6185 04:41:34.977337
6186 04:41:34.977402
6187 04:41:34.987320 [DQSOSCAuto] RK0, (LSB)MR18= 0xa4a4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6188 04:41:34.990349 CH0 RK0: MR19=C0C, MR18=A4A4
6189 04:41:34.993536 CH0_RK0: MR19=0xC0C, MR18=0xA4A4, DQSOSC=389, MR23=63, INC=390, DEC=260
6190 04:41:34.997007 ==
6191 04:41:35.000073 Dram Type= 6, Freq= 0, CH_0, rank 1
6192 04:41:35.003863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6193 04:41:35.003937 ==
6194 04:41:35.007029 [Gating] SW mode calibration
6195 04:41:35.013547 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6196 04:41:35.016834 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6197 04:41:35.023746 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6198 04:41:35.027009 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6199 04:41:35.030158 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6200 04:41:35.037035 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6201 04:41:35.040289 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6202 04:41:35.043099 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6203 04:41:35.050428 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6204 04:41:35.053038 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6205 04:41:35.057417 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6206 04:41:35.059842 Total UI for P1: 0, mck2ui 16
6207 04:41:35.063177 best dqsien dly found for B0: ( 0, 10, 16)
6208 04:41:35.066373 Total UI for P1: 0, mck2ui 16
6209 04:41:35.069803 best dqsien dly found for B1: ( 0, 10, 16)
6210 04:41:35.073259 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6211 04:41:35.076962 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6212 04:41:35.077039
6213 04:41:35.082881 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6214 04:41:35.086580 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6215 04:41:35.089996 [Gating] SW calibration Done
6216 04:41:35.090065 ==
6217 04:41:35.093268 Dram Type= 6, Freq= 0, CH_0, rank 1
6218 04:41:35.096536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6219 04:41:35.096607 ==
6220 04:41:35.096666 RX Vref Scan: 0
6221 04:41:35.099235
6222 04:41:35.099300 RX Vref 0 -> 0, step: 1
6223 04:41:35.099359
6224 04:41:35.103077 RX Delay -410 -> 252, step: 16
6225 04:41:35.106476 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6226 04:41:35.112600 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6227 04:41:35.115946 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6228 04:41:35.119068 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6229 04:41:35.123027 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6230 04:41:35.129211 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6231 04:41:35.132977 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6232 04:41:35.136241 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6233 04:41:35.139273 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6234 04:41:35.146018 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6235 04:41:35.149011 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6236 04:41:35.152259 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6237 04:41:35.155968 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6238 04:41:35.162299 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6239 04:41:35.165568 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6240 04:41:35.168989 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6241 04:41:35.169061 ==
6242 04:41:35.172525 Dram Type= 6, Freq= 0, CH_0, rank 1
6243 04:41:35.179618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6244 04:41:35.179696 ==
6245 04:41:35.179760 DQS Delay:
6246 04:41:35.182079 DQS0 = 43, DQS1 = 59
6247 04:41:35.182164 DQM Delay:
6248 04:41:35.185675 DQM0 = 7, DQM1 = 15
6249 04:41:35.185763 DQ Delay:
6250 04:41:35.188826 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6251 04:41:35.192101 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6252 04:41:35.192178 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6253 04:41:35.195767 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6254 04:41:35.199025
6255 04:41:35.199100
6256 04:41:35.199163 ==
6257 04:41:35.201874 Dram Type= 6, Freq= 0, CH_0, rank 1
6258 04:41:35.205061 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6259 04:41:35.205177 ==
6260 04:41:35.205270
6261 04:41:35.205360
6262 04:41:35.208771 TX Vref Scan disable
6263 04:41:35.208856 == TX Byte 0 ==
6264 04:41:35.211574 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6265 04:41:35.218420 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6266 04:41:35.218494 == TX Byte 1 ==
6267 04:41:35.221956 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6268 04:41:35.228569 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6269 04:41:35.228649 ==
6270 04:41:35.231304 Dram Type= 6, Freq= 0, CH_0, rank 1
6271 04:41:35.234989 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6272 04:41:35.235061 ==
6273 04:41:35.235126
6274 04:41:35.235185
6275 04:41:35.238201 TX Vref Scan disable
6276 04:41:35.238272 == TX Byte 0 ==
6277 04:41:35.244564 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6278 04:41:35.248139 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6279 04:41:35.248228 == TX Byte 1 ==
6280 04:41:35.254567 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6281 04:41:35.258017 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6282 04:41:35.258093
6283 04:41:35.258156 [DATLAT]
6284 04:41:35.261507 Freq=400, CH0 RK1
6285 04:41:35.261582
6286 04:41:35.261643 DATLAT Default: 0xd
6287 04:41:35.264366 0, 0xFFFF, sum = 0
6288 04:41:35.264442 1, 0xFFFF, sum = 0
6289 04:41:35.268068 2, 0xFFFF, sum = 0
6290 04:41:35.268148 3, 0xFFFF, sum = 0
6291 04:41:35.271240 4, 0xFFFF, sum = 0
6292 04:41:35.271341 5, 0xFFFF, sum = 0
6293 04:41:35.274210 6, 0xFFFF, sum = 0
6294 04:41:35.274332 7, 0xFFFF, sum = 0
6295 04:41:35.277908 8, 0xFFFF, sum = 0
6296 04:41:35.278003 9, 0xFFFF, sum = 0
6297 04:41:35.281024 10, 0xFFFF, sum = 0
6298 04:41:35.284143 11, 0xFFFF, sum = 0
6299 04:41:35.284220 12, 0x0, sum = 1
6300 04:41:35.284285 13, 0x0, sum = 2
6301 04:41:35.287814 14, 0x0, sum = 3
6302 04:41:35.287887 15, 0x0, sum = 4
6303 04:41:35.291937 best_step = 13
6304 04:41:35.292007
6305 04:41:35.292072 ==
6306 04:41:35.294299 Dram Type= 6, Freq= 0, CH_0, rank 1
6307 04:41:35.297600 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6308 04:41:35.297675 ==
6309 04:41:35.301080 RX Vref Scan: 0
6310 04:41:35.301151
6311 04:41:35.301212 RX Vref 0 -> 0, step: 1
6312 04:41:35.301271
6313 04:41:35.303996 RX Delay -359 -> 252, step: 8
6314 04:41:35.312330 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6315 04:41:35.316311 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6316 04:41:35.319012 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6317 04:41:35.322428 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6318 04:41:35.329254 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6319 04:41:35.332730 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6320 04:41:35.336106 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6321 04:41:35.339326 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6322 04:41:35.345651 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6323 04:41:35.349369 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6324 04:41:35.352606 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6325 04:41:35.355846 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6326 04:41:35.362697 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6327 04:41:35.365721 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6328 04:41:35.369025 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6329 04:41:35.375472 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6330 04:41:35.375551 ==
6331 04:41:35.379609 Dram Type= 6, Freq= 0, CH_0, rank 1
6332 04:41:35.382429 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6333 04:41:35.382509 ==
6334 04:41:35.382573 DQS Delay:
6335 04:41:35.385337 DQS0 = 52, DQS1 = 64
6336 04:41:35.385414 DQM Delay:
6337 04:41:35.388864 DQM0 = 10, DQM1 = 13
6338 04:41:35.388933 DQ Delay:
6339 04:41:35.392177 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6340 04:41:35.396190 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =20
6341 04:41:35.398650 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6342 04:41:35.402155 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6343 04:41:35.402270
6344 04:41:35.402334
6345 04:41:35.409075 [DQSOSCAuto] RK1, (LSB)MR18= 0xc4c4, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6346 04:41:35.411922 CH0 RK1: MR19=C0C, MR18=C4C4
6347 04:41:35.418327 CH0_RK1: MR19=0xC0C, MR18=0xC4C4, DQSOSC=385, MR23=63, INC=398, DEC=265
6348 04:41:35.421726 [RxdqsGatingPostProcess] freq 400
6349 04:41:35.428427 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6350 04:41:35.431553 Pre-setting of DQS Precalculation
6351 04:41:35.435242 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6352 04:41:35.435351 ==
6353 04:41:35.438247 Dram Type= 6, Freq= 0, CH_1, rank 0
6354 04:41:35.442110 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6355 04:41:35.442185 ==
6356 04:41:35.448288 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6357 04:41:35.454902 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6358 04:41:35.458319 [CA 0] Center 36 (8~64) winsize 57
6359 04:41:35.461769 [CA 1] Center 36 (8~64) winsize 57
6360 04:41:35.464875 [CA 2] Center 36 (8~64) winsize 57
6361 04:41:35.468423 [CA 3] Center 36 (8~64) winsize 57
6362 04:41:35.468493 [CA 4] Center 36 (8~64) winsize 57
6363 04:41:35.471492 [CA 5] Center 36 (8~64) winsize 57
6364 04:41:35.471564
6365 04:41:35.478519 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6366 04:41:35.478600
6367 04:41:35.481543 [CATrainingPosCal] consider 1 rank data
6368 04:41:35.484906 u2DelayCellTimex100 = 270/100 ps
6369 04:41:35.488057 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6370 04:41:35.491254 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6371 04:41:35.495247 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6372 04:41:35.498013 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6373 04:41:35.501454 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6374 04:41:35.504565 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6375 04:41:35.504634
6376 04:41:35.508702 CA PerBit enable=1, Macro0, CA PI delay=36
6377 04:41:35.508808
6378 04:41:35.512081 [CBTSetCACLKResult] CA Dly = 36
6379 04:41:35.515289 CS Dly: 1 (0~32)
6380 04:41:35.515363 ==
6381 04:41:35.518302 Dram Type= 6, Freq= 0, CH_1, rank 1
6382 04:41:35.521294 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6383 04:41:35.521367 ==
6384 04:41:35.528039 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6385 04:41:35.534889 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6386 04:41:35.534965 [CA 0] Center 36 (8~64) winsize 57
6387 04:41:35.538056 [CA 1] Center 36 (8~64) winsize 57
6388 04:41:35.541170 [CA 2] Center 36 (8~64) winsize 57
6389 04:41:35.544557 [CA 3] Center 36 (8~64) winsize 57
6390 04:41:35.547839 [CA 4] Center 36 (8~64) winsize 57
6391 04:41:35.551529 [CA 5] Center 36 (8~64) winsize 57
6392 04:41:35.551627
6393 04:41:35.554302 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6394 04:41:35.554388
6395 04:41:35.557925 [CATrainingPosCal] consider 2 rank data
6396 04:41:35.561342 u2DelayCellTimex100 = 270/100 ps
6397 04:41:35.564931 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6398 04:41:35.568599 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6399 04:41:35.574630 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6400 04:41:35.577779 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6401 04:41:35.580871 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6402 04:41:35.584641 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6403 04:41:35.584737
6404 04:41:35.587686 CA PerBit enable=1, Macro0, CA PI delay=36
6405 04:41:35.587758
6406 04:41:35.591296 [CBTSetCACLKResult] CA Dly = 36
6407 04:41:35.591367 CS Dly: 1 (0~32)
6408 04:41:35.594022
6409 04:41:35.597715 ----->DramcWriteLeveling(PI) begin...
6410 04:41:35.597794 ==
6411 04:41:35.600933 Dram Type= 6, Freq= 0, CH_1, rank 0
6412 04:41:35.604406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6413 04:41:35.604482 ==
6414 04:41:35.607678 Write leveling (Byte 0): 32 => 0
6415 04:41:35.610838 Write leveling (Byte 1): 32 => 0
6416 04:41:35.614332 DramcWriteLeveling(PI) end<-----
6417 04:41:35.614433
6418 04:41:35.614552 ==
6419 04:41:35.617775 Dram Type= 6, Freq= 0, CH_1, rank 0
6420 04:41:35.621485 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6421 04:41:35.621563 ==
6422 04:41:35.624051 [Gating] SW mode calibration
6423 04:41:35.630820 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6424 04:41:35.638538 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6425 04:41:35.640833 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 04:41:35.644095 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6427 04:41:35.648089 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 04:41:35.654310 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6429 04:41:35.657943 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 04:41:35.660964 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 04:41:35.667982 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 04:41:35.670918 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6433 04:41:35.674138 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 04:41:35.677417 Total UI for P1: 0, mck2ui 16
6435 04:41:35.680779 best dqsien dly found for B0: ( 0, 10, 16)
6436 04:41:35.684175 Total UI for P1: 0, mck2ui 16
6437 04:41:35.687656 best dqsien dly found for B1: ( 0, 10, 16)
6438 04:41:35.690536 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6439 04:41:35.697115 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6440 04:41:35.697189
6441 04:41:35.700066 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6442 04:41:35.704216 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6443 04:41:35.707292 [Gating] SW calibration Done
6444 04:41:35.707362 ==
6445 04:41:35.710729 Dram Type= 6, Freq= 0, CH_1, rank 0
6446 04:41:35.714174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6447 04:41:35.714247 ==
6448 04:41:35.717208 RX Vref Scan: 0
6449 04:41:35.717286
6450 04:41:35.717350 RX Vref 0 -> 0, step: 1
6451 04:41:35.717409
6452 04:41:35.719953 RX Delay -410 -> 252, step: 16
6453 04:41:35.727008 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6454 04:41:35.729886 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6455 04:41:35.733052 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6456 04:41:35.736556 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6457 04:41:35.743199 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6458 04:41:35.747001 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6459 04:41:35.749922 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6460 04:41:35.753212 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6461 04:41:35.759576 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6462 04:41:35.763153 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6463 04:41:35.766156 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6464 04:41:35.769813 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6465 04:41:35.776533 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6466 04:41:35.780107 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6467 04:41:35.782748 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6468 04:41:35.789236 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6469 04:41:35.789308 ==
6470 04:41:35.792987 Dram Type= 6, Freq= 0, CH_1, rank 0
6471 04:41:35.796360 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6472 04:41:35.796429 ==
6473 04:41:35.796493 DQS Delay:
6474 04:41:35.799388 DQS0 = 43, DQS1 = 59
6475 04:41:35.799460 DQM Delay:
6476 04:41:35.802614 DQM0 = 6, DQM1 = 15
6477 04:41:35.802686 DQ Delay:
6478 04:41:35.806057 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6479 04:41:35.809116 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6480 04:41:35.812451 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6481 04:41:35.815976 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6482 04:41:35.816049
6483 04:41:35.816110
6484 04:41:35.816168 ==
6485 04:41:35.819113 Dram Type= 6, Freq= 0, CH_1, rank 0
6486 04:41:35.822434 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6487 04:41:35.822511 ==
6488 04:41:35.822573
6489 04:41:35.822632
6490 04:41:35.825790 TX Vref Scan disable
6491 04:41:35.825861 == TX Byte 0 ==
6492 04:41:35.832638 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6493 04:41:35.835422 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6494 04:41:35.835497 == TX Byte 1 ==
6495 04:41:35.842131 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6496 04:41:35.845753 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6497 04:41:35.845826 ==
6498 04:41:35.848588 Dram Type= 6, Freq= 0, CH_1, rank 0
6499 04:41:35.852470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6500 04:41:35.852547 ==
6501 04:41:35.852610
6502 04:41:35.856369
6503 04:41:35.856441 TX Vref Scan disable
6504 04:41:35.858771 == TX Byte 0 ==
6505 04:41:35.862363 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6506 04:41:35.865420 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6507 04:41:35.868710 == TX Byte 1 ==
6508 04:41:35.872033 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6509 04:41:35.876025 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6510 04:41:35.876105
6511 04:41:35.879365 [DATLAT]
6512 04:41:35.879440 Freq=400, CH1 RK0
6513 04:41:35.879507
6514 04:41:35.881980 DATLAT Default: 0xf
6515 04:41:35.882052 0, 0xFFFF, sum = 0
6516 04:41:35.885620 1, 0xFFFF, sum = 0
6517 04:41:35.885696 2, 0xFFFF, sum = 0
6518 04:41:35.888379 3, 0xFFFF, sum = 0
6519 04:41:35.888456 4, 0xFFFF, sum = 0
6520 04:41:35.892254 5, 0xFFFF, sum = 0
6521 04:41:35.892328 6, 0xFFFF, sum = 0
6522 04:41:35.895625 7, 0xFFFF, sum = 0
6523 04:41:35.895739 8, 0xFFFF, sum = 0
6524 04:41:35.898911 9, 0xFFFF, sum = 0
6525 04:41:35.898994 10, 0xFFFF, sum = 0
6526 04:41:35.901947 11, 0xFFFF, sum = 0
6527 04:41:35.902016 12, 0x0, sum = 1
6528 04:41:35.904998 13, 0x0, sum = 2
6529 04:41:35.905070 14, 0x0, sum = 3
6530 04:41:35.908156 15, 0x0, sum = 4
6531 04:41:35.908258 best_step = 13
6532 04:41:35.908317
6533 04:41:35.908374 ==
6534 04:41:35.911457 Dram Type= 6, Freq= 0, CH_1, rank 0
6535 04:41:35.918048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6536 04:41:35.918123 ==
6537 04:41:35.918187 RX Vref Scan: 1
6538 04:41:35.918250
6539 04:41:35.921242 RX Vref 0 -> 0, step: 1
6540 04:41:35.921310
6541 04:41:35.924778 RX Delay -359 -> 252, step: 8
6542 04:41:35.924853
6543 04:41:35.927844 Set Vref, RX VrefLevel [Byte0]: 62
6544 04:41:35.931138 [Byte1]: 47
6545 04:41:35.934992
6546 04:41:35.935067 Final RX Vref Byte 0 = 62 to rank0
6547 04:41:35.938667 Final RX Vref Byte 1 = 47 to rank0
6548 04:41:35.940949 Final RX Vref Byte 0 = 62 to rank1
6549 04:41:35.944799 Final RX Vref Byte 1 = 47 to rank1==
6550 04:41:35.947566 Dram Type= 6, Freq= 0, CH_1, rank 0
6551 04:41:35.954201 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6552 04:41:35.954286 ==
6553 04:41:35.954352 DQS Delay:
6554 04:41:35.957762 DQS0 = 52, DQS1 = 68
6555 04:41:35.957835 DQM Delay:
6556 04:41:35.957897 DQM0 = 10, DQM1 = 20
6557 04:41:35.960925 DQ Delay:
6558 04:41:35.964458 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6559 04:41:35.964566 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6560 04:41:35.967508 DQ8 =0, DQ9 =12, DQ10 =20, DQ11 =12
6561 04:41:35.970752 DQ12 =28, DQ13 =28, DQ14 =28, DQ15 =32
6562 04:41:35.974403
6563 04:41:35.974474
6564 04:41:35.981045 [DQSOSCAuto] RK0, (LSB)MR18= 0xd2d2, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6565 04:41:35.984258 CH1 RK0: MR19=C0C, MR18=D2D2
6566 04:41:35.990868 CH1_RK0: MR19=0xC0C, MR18=0xD2D2, DQSOSC=383, MR23=63, INC=402, DEC=268
6567 04:41:35.990946 ==
6568 04:41:35.994586 Dram Type= 6, Freq= 0, CH_1, rank 1
6569 04:41:35.997800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6570 04:41:35.997871 ==
6571 04:41:36.001052 [Gating] SW mode calibration
6572 04:41:36.007496 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6573 04:41:36.014018 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6574 04:41:36.017025 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6575 04:41:36.020366 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6576 04:41:36.027119 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6577 04:41:36.030233 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6578 04:41:36.033424 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6579 04:41:36.040618 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6580 04:41:36.043486 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6581 04:41:36.047429 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6582 04:41:36.053439 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6583 04:41:36.053515 Total UI for P1: 0, mck2ui 16
6584 04:41:36.059962 best dqsien dly found for B0: ( 0, 10, 16)
6585 04:41:36.060038 Total UI for P1: 0, mck2ui 16
6586 04:41:36.063280 best dqsien dly found for B1: ( 0, 10, 16)
6587 04:41:36.069692 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6588 04:41:36.073047 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6589 04:41:36.073125
6590 04:41:36.076406 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6591 04:41:36.079536 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6592 04:41:36.083286 [Gating] SW calibration Done
6593 04:41:36.083361 ==
6594 04:41:36.086204 Dram Type= 6, Freq= 0, CH_1, rank 1
6595 04:41:36.089866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6596 04:41:36.089939 ==
6597 04:41:36.093506 RX Vref Scan: 0
6598 04:41:36.093604
6599 04:41:36.096317 RX Vref 0 -> 0, step: 1
6600 04:41:36.096386
6601 04:41:36.096446 RX Delay -410 -> 252, step: 16
6602 04:41:36.102986 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6603 04:41:36.106296 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6604 04:41:36.109529 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6605 04:41:36.112609 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6606 04:41:36.119432 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6607 04:41:36.122652 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6608 04:41:36.126099 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6609 04:41:36.129871 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6610 04:41:36.136335 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6611 04:41:36.139289 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6612 04:41:36.142458 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6613 04:41:36.146494 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6614 04:41:36.152487 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6615 04:41:36.156059 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6616 04:41:36.159372 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6617 04:41:36.165936 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6618 04:41:36.166013 ==
6619 04:41:36.169088 Dram Type= 6, Freq= 0, CH_1, rank 1
6620 04:41:36.172571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6621 04:41:36.172673 ==
6622 04:41:36.172819 DQS Delay:
6623 04:41:36.175733 DQS0 = 43, DQS1 = 59
6624 04:41:36.175810 DQM Delay:
6625 04:41:36.179441 DQM0 = 11, DQM1 = 17
6626 04:41:36.179514 DQ Delay:
6627 04:41:36.182226 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6628 04:41:36.186450 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6629 04:41:36.189246 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6630 04:41:36.192409 DQ12 =32, DQ13 =24, DQ14 =32, DQ15 =24
6631 04:41:36.192484
6632 04:41:36.192547
6633 04:41:36.192606 ==
6634 04:41:36.195875 Dram Type= 6, Freq= 0, CH_1, rank 1
6635 04:41:36.198927 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6636 04:41:36.199000 ==
6637 04:41:36.199063
6638 04:41:36.199121
6639 04:41:36.202566 TX Vref Scan disable
6640 04:41:36.205337 == TX Byte 0 ==
6641 04:41:36.208932 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6642 04:41:36.212191 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6643 04:41:36.212271 == TX Byte 1 ==
6644 04:41:36.218749 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6645 04:41:36.222375 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6646 04:41:36.222456 ==
6647 04:41:36.225607 Dram Type= 6, Freq= 0, CH_1, rank 1
6648 04:41:36.228527 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6649 04:41:36.228608 ==
6650 04:41:36.228673
6651 04:41:36.231744
6652 04:41:36.231824 TX Vref Scan disable
6653 04:41:36.235397 == TX Byte 0 ==
6654 04:41:36.238313 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6655 04:41:36.241516 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6656 04:41:36.245776 == TX Byte 1 ==
6657 04:41:36.248545 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6658 04:41:36.251562 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6659 04:41:36.251636
6660 04:41:36.251702 [DATLAT]
6661 04:41:36.255807 Freq=400, CH1 RK1
6662 04:41:36.255876
6663 04:41:36.255971 DATLAT Default: 0xd
6664 04:41:36.258704 0, 0xFFFF, sum = 0
6665 04:41:36.258772 1, 0xFFFF, sum = 0
6666 04:41:36.261599 2, 0xFFFF, sum = 0
6667 04:41:36.265334 3, 0xFFFF, sum = 0
6668 04:41:36.265409 4, 0xFFFF, sum = 0
6669 04:41:36.268657 5, 0xFFFF, sum = 0
6670 04:41:36.268771 6, 0xFFFF, sum = 0
6671 04:41:36.271748 7, 0xFFFF, sum = 0
6672 04:41:36.271816 8, 0xFFFF, sum = 0
6673 04:41:36.274906 9, 0xFFFF, sum = 0
6674 04:41:36.274979 10, 0xFFFF, sum = 0
6675 04:41:36.278594 11, 0xFFFF, sum = 0
6676 04:41:36.278688 12, 0x0, sum = 1
6677 04:41:36.281373 13, 0x0, sum = 2
6678 04:41:36.281448 14, 0x0, sum = 3
6679 04:41:36.285500 15, 0x0, sum = 4
6680 04:41:36.285570 best_step = 13
6681 04:41:36.285631
6682 04:41:36.285688 ==
6683 04:41:36.287853 Dram Type= 6, Freq= 0, CH_1, rank 1
6684 04:41:36.291742 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6685 04:41:36.294411 ==
6686 04:41:36.294483 RX Vref Scan: 0
6687 04:41:36.294544
6688 04:41:36.298530 RX Vref 0 -> 0, step: 1
6689 04:41:36.298600
6690 04:41:36.301512 RX Delay -359 -> 252, step: 8
6691 04:41:36.308202 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6692 04:41:36.311042 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6693 04:41:36.314329 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6694 04:41:36.317819 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6695 04:41:36.324548 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6696 04:41:36.328815 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6697 04:41:36.330782 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6698 04:41:36.334019 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6699 04:41:36.340879 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6700 04:41:36.344340 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6701 04:41:36.347353 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6702 04:41:36.350815 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6703 04:41:36.357597 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6704 04:41:36.360668 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6705 04:41:36.363903 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6706 04:41:36.370355 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6707 04:41:36.370433 ==
6708 04:41:36.374153 Dram Type= 6, Freq= 0, CH_1, rank 1
6709 04:41:36.377041 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6710 04:41:36.377120 ==
6711 04:41:36.377185 DQS Delay:
6712 04:41:36.380799 DQS0 = 48, DQS1 = 64
6713 04:41:36.380879 DQM Delay:
6714 04:41:36.383472 DQM0 = 9, DQM1 = 15
6715 04:41:36.383550 DQ Delay:
6716 04:41:36.387108 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6717 04:41:36.390234 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6718 04:41:36.393520 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6719 04:41:36.396567 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6720 04:41:36.396666
6721 04:41:36.396760
6722 04:41:36.403754 [DQSOSCAuto] RK1, (LSB)MR18= 0xb5b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6723 04:41:36.406554 CH1 RK1: MR19=C0C, MR18=B5B5
6724 04:41:36.413572 CH1_RK1: MR19=0xC0C, MR18=0xB5B5, DQSOSC=387, MR23=63, INC=394, DEC=262
6725 04:41:36.416754 [RxdqsGatingPostProcess] freq 400
6726 04:41:36.423083 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6727 04:41:36.423157 Pre-setting of DQS Precalculation
6728 04:41:36.430032 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6729 04:41:36.436432 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6730 04:41:36.442879 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6731 04:41:36.442956
6732 04:41:36.443020
6733 04:41:36.446206 [Calibration Summary] 800 Mbps
6734 04:41:36.449670 CH 0, Rank 0
6735 04:41:36.449777 SW Impedance : PASS
6736 04:41:36.453134 DUTY Scan : NO K
6737 04:41:36.456547 ZQ Calibration : PASS
6738 04:41:36.456617 Jitter Meter : NO K
6739 04:41:36.459696 CBT Training : PASS
6740 04:41:36.459764 Write leveling : PASS
6741 04:41:36.463341 RX DQS gating : PASS
6742 04:41:36.466001 RX DQ/DQS(RDDQC) : PASS
6743 04:41:36.466074 TX DQ/DQS : PASS
6744 04:41:36.469220 RX DATLAT : PASS
6745 04:41:36.472727 RX DQ/DQS(Engine): PASS
6746 04:41:36.472811 TX OE : NO K
6747 04:41:36.476196 All Pass.
6748 04:41:36.476277
6749 04:41:36.476340 CH 0, Rank 1
6750 04:41:36.480055 SW Impedance : PASS
6751 04:41:36.480126 DUTY Scan : NO K
6752 04:41:36.482622 ZQ Calibration : PASS
6753 04:41:36.486330 Jitter Meter : NO K
6754 04:41:36.486417 CBT Training : PASS
6755 04:41:36.490439 Write leveling : NO K
6756 04:41:36.492739 RX DQS gating : PASS
6757 04:41:36.492824 RX DQ/DQS(RDDQC) : PASS
6758 04:41:36.496001 TX DQ/DQS : PASS
6759 04:41:36.499839 RX DATLAT : PASS
6760 04:41:36.499909 RX DQ/DQS(Engine): PASS
6761 04:41:36.502707 TX OE : NO K
6762 04:41:36.502776 All Pass.
6763 04:41:36.502837
6764 04:41:36.505812 CH 1, Rank 0
6765 04:41:36.505882 SW Impedance : PASS
6766 04:41:36.508940 DUTY Scan : NO K
6767 04:41:36.512159 ZQ Calibration : PASS
6768 04:41:36.512227 Jitter Meter : NO K
6769 04:41:36.516209 CBT Training : PASS
6770 04:41:36.519344 Write leveling : PASS
6771 04:41:36.519411 RX DQS gating : PASS
6772 04:41:36.522539 RX DQ/DQS(RDDQC) : PASS
6773 04:41:36.522609 TX DQ/DQS : PASS
6774 04:41:36.525714 RX DATLAT : PASS
6775 04:41:36.529187 RX DQ/DQS(Engine): PASS
6776 04:41:36.529260 TX OE : NO K
6777 04:41:36.532273 All Pass.
6778 04:41:36.532340
6779 04:41:36.532401 CH 1, Rank 1
6780 04:41:36.535721 SW Impedance : PASS
6781 04:41:36.535790 DUTY Scan : NO K
6782 04:41:36.539372 ZQ Calibration : PASS
6783 04:41:36.542326 Jitter Meter : NO K
6784 04:41:36.542431 CBT Training : PASS
6785 04:41:36.545823 Write leveling : NO K
6786 04:41:36.549520 RX DQS gating : PASS
6787 04:41:36.549595 RX DQ/DQS(RDDQC) : PASS
6788 04:41:36.552219 TX DQ/DQS : PASS
6789 04:41:36.555609 RX DATLAT : PASS
6790 04:41:36.555679 RX DQ/DQS(Engine): PASS
6791 04:41:36.558735 TX OE : NO K
6792 04:41:36.558803 All Pass.
6793 04:41:36.558869
6794 04:41:36.561738 DramC Write-DBI off
6795 04:41:36.565111 PER_BANK_REFRESH: Hybrid Mode
6796 04:41:36.565185 TX_TRACKING: ON
6797 04:41:36.575435 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6798 04:41:36.578728 [FAST_K] Save calibration result to emmc
6799 04:41:36.581862 dramc_set_vcore_voltage set vcore to 725000
6800 04:41:36.585002 Read voltage for 1600, 0
6801 04:41:36.585077 Vio18 = 0
6802 04:41:36.585140 Vcore = 725000
6803 04:41:36.588693 Vdram = 0
6804 04:41:36.588809 Vddq = 0
6805 04:41:36.588876 Vmddr = 0
6806 04:41:36.595194 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6807 04:41:36.598571 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6808 04:41:36.601966 MEM_TYPE=3, freq_sel=13
6809 04:41:36.604940 sv_algorithm_assistance_LP4_3733
6810 04:41:36.608503 ============ PULL DRAM RESETB DOWN ============
6811 04:41:36.615066 ========== PULL DRAM RESETB DOWN end =========
6812 04:41:36.618113 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6813 04:41:36.621694 ===================================
6814 04:41:36.625353 LPDDR4 DRAM CONFIGURATION
6815 04:41:36.628681 ===================================
6816 04:41:36.628775 EX_ROW_EN[0] = 0x0
6817 04:41:36.631632 EX_ROW_EN[1] = 0x0
6818 04:41:36.631719 LP4Y_EN = 0x0
6819 04:41:36.635040 WORK_FSP = 0x1
6820 04:41:36.635122 WL = 0x5
6821 04:41:36.638242 RL = 0x5
6822 04:41:36.638310 BL = 0x2
6823 04:41:36.641599 RPST = 0x0
6824 04:41:36.641690 RD_PRE = 0x0
6825 04:41:36.644926 WR_PRE = 0x1
6826 04:41:36.645019 WR_PST = 0x1
6827 04:41:36.647800 DBI_WR = 0x0
6828 04:41:36.651677 DBI_RD = 0x0
6829 04:41:36.651753 OTF = 0x1
6830 04:41:36.654615 ===================================
6831 04:41:36.657865 ===================================
6832 04:41:36.657942 ANA top config
6833 04:41:36.661382 ===================================
6834 04:41:36.664671 DLL_ASYNC_EN = 0
6835 04:41:36.667765 ALL_SLAVE_EN = 0
6836 04:41:36.671117 NEW_RANK_MODE = 1
6837 04:41:36.674459 DLL_IDLE_MODE = 1
6838 04:41:36.674537 LP45_APHY_COMB_EN = 1
6839 04:41:36.677850 TX_ODT_DIS = 0
6840 04:41:36.681609 NEW_8X_MODE = 1
6841 04:41:36.684464 ===================================
6842 04:41:36.687568 ===================================
6843 04:41:36.691031 data_rate = 3200
6844 04:41:36.694219 CKR = 1
6845 04:41:36.697514 DQ_P2S_RATIO = 8
6846 04:41:36.700584 ===================================
6847 04:41:36.700682 CA_P2S_RATIO = 8
6848 04:41:36.704191 DQ_CA_OPEN = 0
6849 04:41:36.707355 DQ_SEMI_OPEN = 0
6850 04:41:36.711017 CA_SEMI_OPEN = 0
6851 04:41:36.714216 CA_FULL_RATE = 0
6852 04:41:36.717236 DQ_CKDIV4_EN = 0
6853 04:41:36.717317 CA_CKDIV4_EN = 0
6854 04:41:36.720908 CA_PREDIV_EN = 0
6855 04:41:36.724236 PH8_DLY = 12
6856 04:41:36.727547 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6857 04:41:36.730446 DQ_AAMCK_DIV = 4
6858 04:41:36.734303 CA_AAMCK_DIV = 4
6859 04:41:36.734401 CA_ADMCK_DIV = 4
6860 04:41:36.737537 DQ_TRACK_CA_EN = 0
6861 04:41:36.740182 CA_PICK = 1600
6862 04:41:36.744596 CA_MCKIO = 1600
6863 04:41:36.746791 MCKIO_SEMI = 0
6864 04:41:36.750308 PLL_FREQ = 3068
6865 04:41:36.753361 DQ_UI_PI_RATIO = 32
6866 04:41:36.757241 CA_UI_PI_RATIO = 0
6867 04:41:36.760372 ===================================
6868 04:41:36.760453 ===================================
6869 04:41:36.763661 memory_type:LPDDR4
6870 04:41:36.766995 GP_NUM : 10
6871 04:41:36.767076 SRAM_EN : 1
6872 04:41:36.769976 MD32_EN : 0
6873 04:41:36.773757 ===================================
6874 04:41:36.777265 [ANA_INIT] >>>>>>>>>>>>>>
6875 04:41:36.780858 <<<<<< [CONFIGURE PHASE]: ANA_TX
6876 04:41:36.783549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6877 04:41:36.786937 ===================================
6878 04:41:36.790966 data_rate = 3200,PCW = 0X7600
6879 04:41:36.791064 ===================================
6880 04:41:36.796872 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6881 04:41:36.799890 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6882 04:41:36.806926 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6883 04:41:36.810349 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6884 04:41:36.813154 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6885 04:41:36.816868 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6886 04:41:36.819837 [ANA_INIT] flow start
6887 04:41:36.823259 [ANA_INIT] PLL >>>>>>>>
6888 04:41:36.823382 [ANA_INIT] PLL <<<<<<<<
6889 04:41:36.826294 [ANA_INIT] MIDPI >>>>>>>>
6890 04:41:36.830455 [ANA_INIT] MIDPI <<<<<<<<
6891 04:41:36.830553 [ANA_INIT] DLL >>>>>>>>
6892 04:41:36.833604 [ANA_INIT] DLL <<<<<<<<
6893 04:41:36.836575 [ANA_INIT] flow end
6894 04:41:36.839956 ============ LP4 DIFF to SE enter ============
6895 04:41:36.843570 ============ LP4 DIFF to SE exit ============
6896 04:41:36.846450 [ANA_INIT] <<<<<<<<<<<<<
6897 04:41:36.850007 [Flow] Enable top DCM control >>>>>
6898 04:41:36.853043 [Flow] Enable top DCM control <<<<<
6899 04:41:36.856066 Enable DLL master slave shuffle
6900 04:41:36.859521 ==============================================================
6901 04:41:36.863130 Gating Mode config
6902 04:41:36.870233 ==============================================================
6903 04:41:36.870318 Config description:
6904 04:41:36.879582 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6905 04:41:36.886120 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6906 04:41:36.892795 SELPH_MODE 0: By rank 1: By Phase
6907 04:41:36.896330 ==============================================================
6908 04:41:36.899503 GAT_TRACK_EN = 1
6909 04:41:36.902757 RX_GATING_MODE = 2
6910 04:41:36.906165 RX_GATING_TRACK_MODE = 2
6911 04:41:36.909387 SELPH_MODE = 1
6912 04:41:36.912806 PICG_EARLY_EN = 1
6913 04:41:36.915852 VALID_LAT_VALUE = 1
6914 04:41:36.920227 ==============================================================
6915 04:41:36.922609 Enter into Gating configuration >>>>
6916 04:41:36.925594 Exit from Gating configuration <<<<
6917 04:41:36.929218 Enter into DVFS_PRE_config >>>>>
6918 04:41:36.942774 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6919 04:41:36.945430 Exit from DVFS_PRE_config <<<<<
6920 04:41:36.948918 Enter into PICG configuration >>>>
6921 04:41:36.952093 Exit from PICG configuration <<<<
6922 04:41:36.952176 [RX_INPUT] configuration >>>>>
6923 04:41:36.955344 [RX_INPUT] configuration <<<<<
6924 04:41:36.961910 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6925 04:41:36.965277 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6926 04:41:36.972099 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6927 04:41:36.978627 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6928 04:41:36.985570 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6929 04:41:36.991810 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6930 04:41:36.995372 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6931 04:41:36.998626 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6932 04:41:37.005471 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6933 04:41:37.008419 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6934 04:41:37.011639 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6935 04:41:37.015300 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6936 04:41:37.018707 ===================================
6937 04:41:37.021610 LPDDR4 DRAM CONFIGURATION
6938 04:41:37.025273 ===================================
6939 04:41:37.029474 EX_ROW_EN[0] = 0x0
6940 04:41:37.029559 EX_ROW_EN[1] = 0x0
6941 04:41:37.031597 LP4Y_EN = 0x0
6942 04:41:37.031681 WORK_FSP = 0x1
6943 04:41:37.035108 WL = 0x5
6944 04:41:37.035191 RL = 0x5
6945 04:41:37.038411 BL = 0x2
6946 04:41:37.038494 RPST = 0x0
6947 04:41:37.041657 RD_PRE = 0x0
6948 04:41:37.041740 WR_PRE = 0x1
6949 04:41:37.045314 WR_PST = 0x1
6950 04:41:37.047978 DBI_WR = 0x0
6951 04:41:37.048061 DBI_RD = 0x0
6952 04:41:37.051190 OTF = 0x1
6953 04:41:37.054641 ===================================
6954 04:41:37.057983 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6955 04:41:37.061105 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6956 04:41:37.064485 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6957 04:41:37.067967 ===================================
6958 04:41:37.072118 LPDDR4 DRAM CONFIGURATION
6959 04:41:37.074656 ===================================
6960 04:41:37.078670 EX_ROW_EN[0] = 0x10
6961 04:41:37.078753 EX_ROW_EN[1] = 0x0
6962 04:41:37.081662 LP4Y_EN = 0x0
6963 04:41:37.081745 WORK_FSP = 0x1
6964 04:41:37.084844 WL = 0x5
6965 04:41:37.084926 RL = 0x5
6966 04:41:37.087782 BL = 0x2
6967 04:41:37.087864 RPST = 0x0
6968 04:41:37.091401 RD_PRE = 0x0
6969 04:41:37.091484 WR_PRE = 0x1
6970 04:41:37.094619 WR_PST = 0x1
6971 04:41:37.094702 DBI_WR = 0x0
6972 04:41:37.097654 DBI_RD = 0x0
6973 04:41:37.101405 OTF = 0x1
6974 04:41:37.104244 ===================================
6975 04:41:37.107629 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6976 04:41:37.107713 ==
6977 04:41:37.111418 Dram Type= 6, Freq= 0, CH_0, rank 0
6978 04:41:37.117597 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6979 04:41:37.117679 ==
6980 04:41:37.117745 [Duty_Offset_Calibration]
6981 04:41:37.121362 B0:0 B1:2 CA:1
6982 04:41:37.121460
6983 04:41:37.124007 [DutyScan_Calibration_Flow] k_type=0
6984 04:41:37.134108
6985 04:41:37.134189 ==CLK 0==
6986 04:41:37.137147 Final CLK duty delay cell = 0
6987 04:41:37.140667 [0] MAX Duty = 5156%(X100), DQS PI = 20
6988 04:41:37.143754 [0] MIN Duty = 4938%(X100), DQS PI = 54
6989 04:41:37.143835 [0] AVG Duty = 5047%(X100)
6990 04:41:37.147530
6991 04:41:37.150661 CH0 CLK Duty spec in!! Max-Min= 218%
6992 04:41:37.154757 [DutyScan_Calibration_Flow] ====Done====
6993 04:41:37.154839
6994 04:41:37.156951 [DutyScan_Calibration_Flow] k_type=1
6995 04:41:37.174310
6996 04:41:37.174402 ==DQS 0 ==
6997 04:41:37.177533 Final DQS duty delay cell = 0
6998 04:41:37.180603 [0] MAX Duty = 5156%(X100), DQS PI = 34
6999 04:41:37.183563 [0] MIN Duty = 5031%(X100), DQS PI = 8
7000 04:41:37.186917 [0] AVG Duty = 5093%(X100)
7001 04:41:37.186998
7002 04:41:37.187063 ==DQS 1 ==
7003 04:41:37.190922 Final DQS duty delay cell = 0
7004 04:41:37.194447 [0] MAX Duty = 5062%(X100), DQS PI = 6
7005 04:41:37.197502 [0] MIN Duty = 4876%(X100), DQS PI = 16
7006 04:41:37.200928 [0] AVG Duty = 4969%(X100)
7007 04:41:37.201026
7008 04:41:37.203637 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7009 04:41:37.203718
7010 04:41:37.206925 CH0 DQS 1 Duty spec in!! Max-Min= 186%
7011 04:41:37.210650 [DutyScan_Calibration_Flow] ====Done====
7012 04:41:37.210731
7013 04:41:37.213854 [DutyScan_Calibration_Flow] k_type=3
7014 04:41:37.231355
7015 04:41:37.231469 ==DQM 0 ==
7016 04:41:37.234172 Final DQM duty delay cell = 0
7017 04:41:37.237419 [0] MAX Duty = 5187%(X100), DQS PI = 22
7018 04:41:37.241521 [0] MIN Duty = 4907%(X100), DQS PI = 56
7019 04:41:37.244183 [0] AVG Duty = 5047%(X100)
7020 04:41:37.244266
7021 04:41:37.244332 ==DQM 1 ==
7022 04:41:37.247293 Final DQM duty delay cell = 0
7023 04:41:37.250806 [0] MAX Duty = 5031%(X100), DQS PI = 4
7024 04:41:37.254241 [0] MIN Duty = 4813%(X100), DQS PI = 14
7025 04:41:37.257424 [0] AVG Duty = 4922%(X100)
7026 04:41:37.257503
7027 04:41:37.261045 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7028 04:41:37.261142
7029 04:41:37.264507 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7030 04:41:37.267757 [DutyScan_Calibration_Flow] ====Done====
7031 04:41:37.267840
7032 04:41:37.270895 [DutyScan_Calibration_Flow] k_type=2
7033 04:41:37.287012
7034 04:41:37.287098 ==DQ 0 ==
7035 04:41:37.290686 Final DQ duty delay cell = 0
7036 04:41:37.293843 [0] MAX Duty = 5218%(X100), DQS PI = 18
7037 04:41:37.297152 [0] MIN Duty = 4969%(X100), DQS PI = 8
7038 04:41:37.297237 [0] AVG Duty = 5093%(X100)
7039 04:41:37.300380
7040 04:41:37.300489 ==DQ 1 ==
7041 04:41:37.304127 Final DQ duty delay cell = -4
7042 04:41:37.307001 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7043 04:41:37.310337 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7044 04:41:37.313591 [-4] AVG Duty = 4953%(X100)
7045 04:41:37.313673
7046 04:41:37.317454 CH0 DQ 0 Duty spec in!! Max-Min= 249%
7047 04:41:37.317537
7048 04:41:37.320095 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7049 04:41:37.323734 [DutyScan_Calibration_Flow] ====Done====
7050 04:41:37.323822 ==
7051 04:41:37.327032 Dram Type= 6, Freq= 0, CH_1, rank 0
7052 04:41:37.330024 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7053 04:41:37.330107 ==
7054 04:41:37.333274 [Duty_Offset_Calibration]
7055 04:41:37.333357 B0:0 B1:5 CA:-5
7056 04:41:37.333422
7057 04:41:37.337079 [DutyScan_Calibration_Flow] k_type=0
7058 04:41:37.348054
7059 04:41:37.348134 ==CLK 0==
7060 04:41:37.350882 Final CLK duty delay cell = 0
7061 04:41:37.354416 [0] MAX Duty = 5156%(X100), DQS PI = 22
7062 04:41:37.358085 [0] MIN Duty = 4875%(X100), DQS PI = 52
7063 04:41:37.361272 [0] AVG Duty = 5015%(X100)
7064 04:41:37.361353
7065 04:41:37.364504 CH1 CLK Duty spec in!! Max-Min= 281%
7066 04:41:37.368487 [DutyScan_Calibration_Flow] ====Done====
7067 04:41:37.368569
7068 04:41:37.371199 [DutyScan_Calibration_Flow] k_type=1
7069 04:41:37.386809
7070 04:41:37.386892 ==DQS 0 ==
7071 04:41:37.390360 Final DQS duty delay cell = 0
7072 04:41:37.393269 [0] MAX Duty = 5187%(X100), DQS PI = 20
7073 04:41:37.397174 [0] MIN Duty = 4876%(X100), DQS PI = 42
7074 04:41:37.400474 [0] AVG Duty = 5031%(X100)
7075 04:41:37.400556
7076 04:41:37.400620 ==DQS 1 ==
7077 04:41:37.403584 Final DQS duty delay cell = -4
7078 04:41:37.406696 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7079 04:41:37.410022 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7080 04:41:37.413648 [-4] AVG Duty = 4922%(X100)
7081 04:41:37.413732
7082 04:41:37.416868 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7083 04:41:37.416951
7084 04:41:37.420045 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7085 04:41:37.423426 [DutyScan_Calibration_Flow] ====Done====
7086 04:41:37.423510
7087 04:41:37.427372 [DutyScan_Calibration_Flow] k_type=3
7088 04:41:37.442634
7089 04:41:37.442718 ==DQM 0 ==
7090 04:41:37.445840 Final DQM duty delay cell = -4
7091 04:41:37.449144 [-4] MAX Duty = 5062%(X100), DQS PI = 32
7092 04:41:37.452552 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7093 04:41:37.456056 [-4] AVG Duty = 4922%(X100)
7094 04:41:37.456140
7095 04:41:37.456225 ==DQM 1 ==
7096 04:41:37.460068 Final DQM duty delay cell = -4
7097 04:41:37.462544 [-4] MAX Duty = 5062%(X100), DQS PI = 16
7098 04:41:37.466381 [-4] MIN Duty = 4876%(X100), DQS PI = 40
7099 04:41:37.469163 [-4] AVG Duty = 4969%(X100)
7100 04:41:37.469247
7101 04:41:37.472801 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7102 04:41:37.472886
7103 04:41:37.476140 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7104 04:41:37.479585 [DutyScan_Calibration_Flow] ====Done====
7105 04:41:37.479694
7106 04:41:37.482506 [DutyScan_Calibration_Flow] k_type=2
7107 04:41:37.499890
7108 04:41:37.499989 ==DQ 0 ==
7109 04:41:37.503635 Final DQ duty delay cell = 0
7110 04:41:37.506381 [0] MAX Duty = 5062%(X100), DQS PI = 2
7111 04:41:37.510103 [0] MIN Duty = 4938%(X100), DQS PI = 46
7112 04:41:37.510203 [0] AVG Duty = 5000%(X100)
7113 04:41:37.513765
7114 04:41:37.513862 ==DQ 1 ==
7115 04:41:37.516814 Final DQ duty delay cell = 0
7116 04:41:37.520020 [0] MAX Duty = 5031%(X100), DQS PI = 4
7117 04:41:37.523479 [0] MIN Duty = 4907%(X100), DQS PI = 22
7118 04:41:37.523580 [0] AVG Duty = 4969%(X100)
7119 04:41:37.523722
7120 04:41:37.526623 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7121 04:41:37.529779
7122 04:41:37.533083 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7123 04:41:37.536699 [DutyScan_Calibration_Flow] ====Done====
7124 04:41:37.539519 nWR fixed to 30
7125 04:41:37.539651 [ModeRegInit_LP4] CH0 RK0
7126 04:41:37.543405 [ModeRegInit_LP4] CH0 RK1
7127 04:41:37.546634 [ModeRegInit_LP4] CH1 RK0
7128 04:41:37.549577 [ModeRegInit_LP4] CH1 RK1
7129 04:41:37.549692 match AC timing 4
7130 04:41:37.553264 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7131 04:41:37.560590 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7132 04:41:37.563108 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7133 04:41:37.569448 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7134 04:41:37.573184 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7135 04:41:37.573259 [MiockJmeterHQA]
7136 04:41:37.573353
7137 04:41:37.576773 [DramcMiockJmeter] u1RxGatingPI = 0
7138 04:41:37.579262 0 : 4257, 4029
7139 04:41:37.579367 4 : 4362, 4137
7140 04:41:37.582567 8 : 4254, 4029
7141 04:41:37.582682 12 : 4363, 4138
7142 04:41:37.582782 16 : 4252, 4027
7143 04:41:37.585942 20 : 4252, 4027
7144 04:41:37.586086 24 : 4253, 4026
7145 04:41:37.589035 28 : 4363, 4138
7146 04:41:37.589166 32 : 4362, 4137
7147 04:41:37.592637 36 : 4252, 4027
7148 04:41:37.592759 40 : 4253, 4027
7149 04:41:37.596139 44 : 4252, 4027
7150 04:41:37.596246 48 : 4252, 4027
7151 04:41:37.596346 52 : 4255, 4029
7152 04:41:37.599110 56 : 4363, 4138
7153 04:41:37.599230 60 : 4249, 4027
7154 04:41:37.602653 64 : 4250, 4027
7155 04:41:37.602754 68 : 4250, 4027
7156 04:41:37.605581 72 : 4252, 4029
7157 04:41:37.605661 76 : 4250, 4027
7158 04:41:37.609016 80 : 4360, 4138
7159 04:41:37.609116 84 : 4360, 4137
7160 04:41:37.609218 88 : 4250, 4027
7161 04:41:37.612878 92 : 4250, 4027
7162 04:41:37.612959 96 : 4250, 4026
7163 04:41:37.615496 100 : 4250, 2089
7164 04:41:37.615587 104 : 4250, 0
7165 04:41:37.618912 108 : 4255, 0
7166 04:41:37.619000 112 : 4361, 0
7167 04:41:37.619067 116 : 4250, 0
7168 04:41:37.622234 120 : 4250, 0
7169 04:41:37.622319 124 : 4250, 0
7170 04:41:37.622386 128 : 4252, 0
7171 04:41:37.625851 132 : 4249, 0
7172 04:41:37.625937 136 : 4250, 0
7173 04:41:37.629508 140 : 4363, 0
7174 04:41:37.629592 144 : 4361, 0
7175 04:41:37.629659 148 : 4360, 0
7176 04:41:37.633156 152 : 4363, 0
7177 04:41:37.633241 156 : 4250, 0
7178 04:41:37.635860 160 : 4250, 0
7179 04:41:37.635945 164 : 4250, 0
7180 04:41:37.636012 168 : 4252, 0
7181 04:41:37.639044 172 : 4249, 0
7182 04:41:37.639129 176 : 4250, 0
7183 04:41:37.642213 180 : 4252, 0
7184 04:41:37.642298 184 : 4360, 0
7185 04:41:37.642364 188 : 4250, 0
7186 04:41:37.645746 192 : 4360, 0
7187 04:41:37.645831 196 : 4249, 0
7188 04:41:37.649069 200 : 4250, 0
7189 04:41:37.649153 204 : 4363, 0
7190 04:41:37.649221 208 : 4249, 0
7191 04:41:37.651832 212 : 4250, 0
7192 04:41:37.651917 216 : 4250, 0
7193 04:41:37.655931 220 : 4252, 842
7194 04:41:37.656015 224 : 4250, 4009
7195 04:41:37.656083 228 : 4250, 4027
7196 04:41:37.658657 232 : 4250, 4027
7197 04:41:37.658742 236 : 4249, 4027
7198 04:41:37.661891 240 : 4250, 4026
7199 04:41:37.661975 244 : 4250, 4027
7200 04:41:37.665120 248 : 4360, 4138
7201 04:41:37.665205 252 : 4250, 4027
7202 04:41:37.668944 256 : 4250, 4026
7203 04:41:37.669028 260 : 4361, 4137
7204 04:41:37.672318 264 : 4252, 4027
7205 04:41:37.672402 268 : 4249, 4027
7206 04:41:37.675077 272 : 4363, 4140
7207 04:41:37.675162 276 : 4250, 4026
7208 04:41:37.678588 280 : 4250, 4027
7209 04:41:37.678698 284 : 4250, 4027
7210 04:41:37.678789 288 : 4252, 4029
7211 04:41:37.682255 292 : 4250, 4026
7212 04:41:37.682343 296 : 4253, 4029
7213 04:41:37.685097 300 : 4363, 4138
7214 04:41:37.685183 304 : 4249, 4027
7215 04:41:37.688673 308 : 4250, 4026
7216 04:41:37.688777 312 : 4361, 4137
7217 04:41:37.692088 316 : 4252, 4027
7218 04:41:37.692175 320 : 4249, 4027
7219 04:41:37.695234 324 : 4363, 4140
7220 04:41:37.695321 328 : 4250, 4026
7221 04:41:37.698870 332 : 4250, 4027
7222 04:41:37.698957 336 : 4250, 3808
7223 04:41:37.701726 340 : 4252, 1989
7224 04:41:37.701813
7225 04:41:37.701900 MIOCK jitter meter ch=0
7226 04:41:37.701983
7227 04:41:37.705248 1T = (340-100) = 240 dly cells
7228 04:41:37.711600 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7229 04:41:37.711687 ==
7230 04:41:37.715267 Dram Type= 6, Freq= 0, CH_0, rank 0
7231 04:41:37.718310 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7232 04:41:37.718424 ==
7233 04:41:37.725110 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7234 04:41:37.728107 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7235 04:41:37.731352 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7236 04:41:37.738387 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7237 04:41:37.747213 [CA 0] Center 42 (12~73) winsize 62
7238 04:41:37.750411 [CA 1] Center 42 (12~73) winsize 62
7239 04:41:37.753615 [CA 2] Center 39 (9~69) winsize 61
7240 04:41:37.757064 [CA 3] Center 38 (9~68) winsize 60
7241 04:41:37.760557 [CA 4] Center 37 (7~67) winsize 61
7242 04:41:37.763623 [CA 5] Center 36 (6~66) winsize 61
7243 04:41:37.763720
7244 04:41:37.767396 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7245 04:41:37.767492
7246 04:41:37.770273 [CATrainingPosCal] consider 1 rank data
7247 04:41:37.773506 u2DelayCellTimex100 = 271/100 ps
7248 04:41:37.777312 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7249 04:41:37.783590 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7250 04:41:37.787216 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7251 04:41:37.790085 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7252 04:41:37.794034 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7253 04:41:37.797085 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7254 04:41:37.797167
7255 04:41:37.799999 CA PerBit enable=1, Macro0, CA PI delay=36
7256 04:41:37.800081
7257 04:41:37.803646 [CBTSetCACLKResult] CA Dly = 36
7258 04:41:37.806863 CS Dly: 10 (0~41)
7259 04:41:37.810956 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7260 04:41:37.813340 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7261 04:41:37.813416 ==
7262 04:41:37.816594 Dram Type= 6, Freq= 0, CH_0, rank 1
7263 04:41:37.820093 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7264 04:41:37.823506 ==
7265 04:41:37.827000 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7266 04:41:37.830013 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7267 04:41:37.836830 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7268 04:41:37.843166 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7269 04:41:37.850229 [CA 0] Center 42 (12~73) winsize 62
7270 04:41:37.853046 [CA 1] Center 41 (11~72) winsize 62
7271 04:41:37.856867 [CA 2] Center 38 (8~68) winsize 61
7272 04:41:37.859824 [CA 3] Center 37 (7~67) winsize 61
7273 04:41:37.863163 [CA 4] Center 35 (5~65) winsize 61
7274 04:41:37.866131 [CA 5] Center 35 (5~66) winsize 62
7275 04:41:37.866228
7276 04:41:37.869589 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7277 04:41:37.869691
7278 04:41:37.876129 [CATrainingPosCal] consider 2 rank data
7279 04:41:37.876231 u2DelayCellTimex100 = 271/100 ps
7280 04:41:37.882643 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7281 04:41:37.886101 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
7282 04:41:37.889484 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7283 04:41:37.892581 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7284 04:41:37.895947 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7285 04:41:37.899058 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7286 04:41:37.899140
7287 04:41:37.902753 CA PerBit enable=1, Macro0, CA PI delay=36
7288 04:41:37.902834
7289 04:41:37.905757 [CBTSetCACLKResult] CA Dly = 36
7290 04:41:37.909259 CS Dly: 11 (0~43)
7291 04:41:37.912862 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7292 04:41:37.916234 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7293 04:41:37.916316
7294 04:41:37.919722 ----->DramcWriteLeveling(PI) begin...
7295 04:41:37.919804 ==
7296 04:41:37.922304 Dram Type= 6, Freq= 0, CH_0, rank 0
7297 04:41:37.929471 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7298 04:41:37.929553 ==
7299 04:41:37.932138 Write leveling (Byte 0): 28 => 28
7300 04:41:37.935461 Write leveling (Byte 1): 24 => 24
7301 04:41:37.935542 DramcWriteLeveling(PI) end<-----
7302 04:41:37.935606
7303 04:41:37.939182 ==
7304 04:41:37.942305 Dram Type= 6, Freq= 0, CH_0, rank 0
7305 04:41:37.945691 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7306 04:41:37.945772 ==
7307 04:41:37.948801 [Gating] SW mode calibration
7308 04:41:37.955700 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7309 04:41:37.958791 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7310 04:41:37.965821 0 12 0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
7311 04:41:37.968683 0 12 4 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
7312 04:41:37.972465 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7313 04:41:37.978875 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7314 04:41:37.982313 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7315 04:41:37.986454 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7316 04:41:37.992112 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7317 04:41:37.995667 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7318 04:41:37.998685 0 13 0 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
7319 04:41:38.005203 0 13 4 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
7320 04:41:38.008622 0 13 8 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
7321 04:41:38.011955 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7322 04:41:38.018832 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7323 04:41:38.022682 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7324 04:41:38.025294 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7325 04:41:38.032396 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7326 04:41:38.035165 0 14 0 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7327 04:41:38.038398 0 14 4 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
7328 04:41:38.045737 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7329 04:41:38.048714 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7330 04:41:38.051772 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7331 04:41:38.058318 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7332 04:41:38.061487 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7333 04:41:38.065094 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7334 04:41:38.071467 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7335 04:41:38.074830 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7336 04:41:38.078246 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7337 04:41:38.084990 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7338 04:41:38.088135 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7339 04:41:38.091539 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7340 04:41:38.094619 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7341 04:41:38.101619 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7342 04:41:38.104557 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7343 04:41:38.108797 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7344 04:41:38.114743 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7345 04:41:38.117671 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7346 04:41:38.121575 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7347 04:41:38.127950 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7348 04:41:38.131599 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7349 04:41:38.134971 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 04:41:38.141638 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7351 04:41:38.144303 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7352 04:41:38.147813 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7353 04:41:38.151152 Total UI for P1: 0, mck2ui 16
7354 04:41:38.154577 best dqsien dly found for B0: ( 1, 1, 2)
7355 04:41:38.157804 Total UI for P1: 0, mck2ui 16
7356 04:41:38.161756 best dqsien dly found for B1: ( 1, 1, 4)
7357 04:41:38.165045 best DQS0 dly(MCK, UI, PI) = (1, 1, 2)
7358 04:41:38.167624 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7359 04:41:38.167707
7360 04:41:38.174229 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 2)
7361 04:41:38.177378 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7362 04:41:38.177487 [Gating] SW calibration Done
7363 04:41:38.181148 ==
7364 04:41:38.184163 Dram Type= 6, Freq= 0, CH_0, rank 0
7365 04:41:38.187802 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7366 04:41:38.187889 ==
7367 04:41:38.187977 RX Vref Scan: 0
7368 04:41:38.188060
7369 04:41:38.191471 RX Vref 0 -> 0, step: 1
7370 04:41:38.191558
7371 04:41:38.194414 RX Delay 0 -> 252, step: 8
7372 04:41:38.197666 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7373 04:41:38.200867 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7374 04:41:38.204369 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7375 04:41:38.210429 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7376 04:41:38.214285 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7377 04:41:38.217055 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7378 04:41:38.220496 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7379 04:41:38.224241 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7380 04:41:38.230808 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7381 04:41:38.234179 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7382 04:41:38.237022 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7383 04:41:38.240316 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7384 04:41:38.247217 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7385 04:41:38.250122 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7386 04:41:38.254008 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7387 04:41:38.256817 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7388 04:41:38.256905 ==
7389 04:41:38.261057 Dram Type= 6, Freq= 0, CH_0, rank 0
7390 04:41:38.267130 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7391 04:41:38.267217 ==
7392 04:41:38.267305 DQS Delay:
7393 04:41:38.267389 DQS0 = 0, DQS1 = 0
7394 04:41:38.270377 DQM Delay:
7395 04:41:38.270463 DQM0 = 130, DQM1 = 124
7396 04:41:38.273528 DQ Delay:
7397 04:41:38.277351 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7398 04:41:38.280556 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7399 04:41:38.283175 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7400 04:41:38.286771 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7401 04:41:38.286859
7402 04:41:38.286947
7403 04:41:38.287029 ==
7404 04:41:38.290088 Dram Type= 6, Freq= 0, CH_0, rank 0
7405 04:41:38.293825 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7406 04:41:38.297076 ==
7407 04:41:38.297163
7408 04:41:38.297251
7409 04:41:38.297334 TX Vref Scan disable
7410 04:41:38.299535 == TX Byte 0 ==
7411 04:41:38.302865 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7412 04:41:38.306612 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7413 04:41:38.309755 == TX Byte 1 ==
7414 04:41:38.312990 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7415 04:41:38.316558 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7416 04:41:38.319558 ==
7417 04:41:38.323149 Dram Type= 6, Freq= 0, CH_0, rank 0
7418 04:41:38.326355 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7419 04:41:38.326440 ==
7420 04:41:38.338998
7421 04:41:38.341612 TX Vref early break, caculate TX vref
7422 04:41:38.345408 TX Vref=16, minBit 8, minWin=22, winSum=370
7423 04:41:38.348263 TX Vref=18, minBit 4, minWin=23, winSum=381
7424 04:41:38.352171 TX Vref=20, minBit 8, minWin=23, winSum=393
7425 04:41:38.354996 TX Vref=22, minBit 8, minWin=24, winSum=398
7426 04:41:38.358710 TX Vref=24, minBit 10, minWin=24, winSum=411
7427 04:41:38.365642 TX Vref=26, minBit 8, minWin=25, winSum=415
7428 04:41:38.368702 TX Vref=28, minBit 8, minWin=25, winSum=416
7429 04:41:38.371968 TX Vref=30, minBit 0, minWin=25, winSum=410
7430 04:41:38.374846 TX Vref=32, minBit 8, minWin=24, winSum=404
7431 04:41:38.378045 TX Vref=34, minBit 0, minWin=24, winSum=393
7432 04:41:38.385222 [TxChooseVref] Worse bit 8, Min win 25, Win sum 416, Final Vref 28
7433 04:41:38.385309
7434 04:41:38.388448 Final TX Range 0 Vref 28
7435 04:41:38.388532
7436 04:41:38.388633 ==
7437 04:41:38.391566 Dram Type= 6, Freq= 0, CH_0, rank 0
7438 04:41:38.394885 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7439 04:41:38.394970 ==
7440 04:41:38.395056
7441 04:41:38.395137
7442 04:41:38.397967 TX Vref Scan disable
7443 04:41:38.404891 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7444 04:41:38.404977 == TX Byte 0 ==
7445 04:41:38.408351 u2DelayCellOfst[0]=14 cells (4 PI)
7446 04:41:38.412023 u2DelayCellOfst[1]=18 cells (5 PI)
7447 04:41:38.414645 u2DelayCellOfst[2]=14 cells (4 PI)
7448 04:41:38.418413 u2DelayCellOfst[3]=10 cells (3 PI)
7449 04:41:38.421415 u2DelayCellOfst[4]=7 cells (2 PI)
7450 04:41:38.424895 u2DelayCellOfst[5]=0 cells (0 PI)
7451 04:41:38.428226 u2DelayCellOfst[6]=18 cells (5 PI)
7452 04:41:38.431798 u2DelayCellOfst[7]=14 cells (4 PI)
7453 04:41:38.435126 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7454 04:41:38.438229 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7455 04:41:38.441458 == TX Byte 1 ==
7456 04:41:38.441542 u2DelayCellOfst[8]=3 cells (1 PI)
7457 04:41:38.444320 u2DelayCellOfst[9]=0 cells (0 PI)
7458 04:41:38.447856 u2DelayCellOfst[10]=10 cells (3 PI)
7459 04:41:38.451418 u2DelayCellOfst[11]=3 cells (1 PI)
7460 04:41:38.454726 u2DelayCellOfst[12]=14 cells (4 PI)
7461 04:41:38.457508 u2DelayCellOfst[13]=14 cells (4 PI)
7462 04:41:38.461079 u2DelayCellOfst[14]=18 cells (5 PI)
7463 04:41:38.464308 u2DelayCellOfst[15]=14 cells (4 PI)
7464 04:41:38.467649 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
7465 04:41:38.474438 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
7466 04:41:38.474541 DramC Write-DBI on
7467 04:41:38.474630 ==
7468 04:41:38.478180 Dram Type= 6, Freq= 0, CH_0, rank 0
7469 04:41:38.484449 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7470 04:41:38.484537 ==
7471 04:41:38.484638
7472 04:41:38.484773
7473 04:41:38.484860 TX Vref Scan disable
7474 04:41:38.488030 == TX Byte 0 ==
7475 04:41:38.491148 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7476 04:41:38.495034 == TX Byte 1 ==
7477 04:41:38.497904 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
7478 04:41:38.501919 DramC Write-DBI off
7479 04:41:38.502020
7480 04:41:38.502108 [DATLAT]
7481 04:41:38.502190 Freq=1600, CH0 RK0
7482 04:41:38.502272
7483 04:41:38.504387 DATLAT Default: 0xf
7484 04:41:38.507868 0, 0xFFFF, sum = 0
7485 04:41:38.507954 1, 0xFFFF, sum = 0
7486 04:41:38.510791 2, 0xFFFF, sum = 0
7487 04:41:38.510891 3, 0xFFFF, sum = 0
7488 04:41:38.514188 4, 0xFFFF, sum = 0
7489 04:41:38.514336 5, 0xFFFF, sum = 0
7490 04:41:38.517905 6, 0xFFFF, sum = 0
7491 04:41:38.518008 7, 0xFFFF, sum = 0
7492 04:41:38.520913 8, 0xFFFF, sum = 0
7493 04:41:38.521001 9, 0xFFFF, sum = 0
7494 04:41:38.524450 10, 0xFFFF, sum = 0
7495 04:41:38.524536 11, 0xFFFF, sum = 0
7496 04:41:38.527677 12, 0xFFF, sum = 0
7497 04:41:38.527762 13, 0x0, sum = 1
7498 04:41:38.531508 14, 0x0, sum = 2
7499 04:41:38.531593 15, 0x0, sum = 3
7500 04:41:38.534152 16, 0x0, sum = 4
7501 04:41:38.534270 best_step = 14
7502 04:41:38.534356
7503 04:41:38.534436 ==
7504 04:41:38.538170 Dram Type= 6, Freq= 0, CH_0, rank 0
7505 04:41:38.544107 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7506 04:41:38.544191 ==
7507 04:41:38.544292 RX Vref Scan: 1
7508 04:41:38.544391
7509 04:41:38.547275 Set Vref Range= 24 -> 127
7510 04:41:38.547359
7511 04:41:38.550926 RX Vref 24 -> 127, step: 1
7512 04:41:38.551043
7513 04:41:38.551154 RX Delay 11 -> 252, step: 4
7514 04:41:38.551236
7515 04:41:38.554149 Set Vref, RX VrefLevel [Byte0]: 24
7516 04:41:38.557245 [Byte1]: 24
7517 04:41:38.561675
7518 04:41:38.561759 Set Vref, RX VrefLevel [Byte0]: 25
7519 04:41:38.564826 [Byte1]: 25
7520 04:41:38.568851
7521 04:41:38.568935 Set Vref, RX VrefLevel [Byte0]: 26
7522 04:41:38.572369 [Byte1]: 26
7523 04:41:38.576479
7524 04:41:38.576563 Set Vref, RX VrefLevel [Byte0]: 27
7525 04:41:38.580248 [Byte1]: 27
7526 04:41:38.584306
7527 04:41:38.584393 Set Vref, RX VrefLevel [Byte0]: 28
7528 04:41:38.587420 [Byte1]: 28
7529 04:41:38.591842
7530 04:41:38.591926 Set Vref, RX VrefLevel [Byte0]: 29
7531 04:41:38.595319 [Byte1]: 29
7532 04:41:38.599234
7533 04:41:38.599318 Set Vref, RX VrefLevel [Byte0]: 30
7534 04:41:38.602727 [Byte1]: 30
7535 04:41:38.607234
7536 04:41:38.607349 Set Vref, RX VrefLevel [Byte0]: 31
7537 04:41:38.610259 [Byte1]: 31
7538 04:41:38.615110
7539 04:41:38.615218 Set Vref, RX VrefLevel [Byte0]: 32
7540 04:41:38.618355 [Byte1]: 32
7541 04:41:38.622114
7542 04:41:38.622215 Set Vref, RX VrefLevel [Byte0]: 33
7543 04:41:38.625549 [Byte1]: 33
7544 04:41:38.630188
7545 04:41:38.630282 Set Vref, RX VrefLevel [Byte0]: 34
7546 04:41:38.633151 [Byte1]: 34
7547 04:41:38.637748
7548 04:41:38.637832 Set Vref, RX VrefLevel [Byte0]: 35
7549 04:41:38.640866 [Byte1]: 35
7550 04:41:38.645325
7551 04:41:38.645409 Set Vref, RX VrefLevel [Byte0]: 36
7552 04:41:38.648314 [Byte1]: 36
7553 04:41:38.652949
7554 04:41:38.653033 Set Vref, RX VrefLevel [Byte0]: 37
7555 04:41:38.656988 [Byte1]: 37
7556 04:41:38.660512
7557 04:41:38.660596 Set Vref, RX VrefLevel [Byte0]: 38
7558 04:41:38.663712 [Byte1]: 38
7559 04:41:38.667868
7560 04:41:38.667953 Set Vref, RX VrefLevel [Byte0]: 39
7561 04:41:38.671320 [Byte1]: 39
7562 04:41:38.675646
7563 04:41:38.675730 Set Vref, RX VrefLevel [Byte0]: 40
7564 04:41:38.678631 [Byte1]: 40
7565 04:41:38.684153
7566 04:41:38.684278 Set Vref, RX VrefLevel [Byte0]: 41
7567 04:41:38.686802 [Byte1]: 41
7568 04:41:38.690840
7569 04:41:38.690963 Set Vref, RX VrefLevel [Byte0]: 42
7570 04:41:38.693969 [Byte1]: 42
7571 04:41:38.698696
7572 04:41:38.698801 Set Vref, RX VrefLevel [Byte0]: 43
7573 04:41:38.701527 [Byte1]: 43
7574 04:41:38.706057
7575 04:41:38.706138 Set Vref, RX VrefLevel [Byte0]: 44
7576 04:41:38.709560 [Byte1]: 44
7577 04:41:38.713784
7578 04:41:38.713871 Set Vref, RX VrefLevel [Byte0]: 45
7579 04:41:38.717008 [Byte1]: 45
7580 04:41:38.721152
7581 04:41:38.721250 Set Vref, RX VrefLevel [Byte0]: 46
7582 04:41:38.724487 [Byte1]: 46
7583 04:41:38.728616
7584 04:41:38.728745 Set Vref, RX VrefLevel [Byte0]: 47
7585 04:41:38.732420 [Byte1]: 47
7586 04:41:38.736520
7587 04:41:38.736622 Set Vref, RX VrefLevel [Byte0]: 48
7588 04:41:38.739926 [Byte1]: 48
7589 04:41:38.744419
7590 04:41:38.744521 Set Vref, RX VrefLevel [Byte0]: 49
7591 04:41:38.747417 [Byte1]: 49
7592 04:41:38.751825
7593 04:41:38.751921 Set Vref, RX VrefLevel [Byte0]: 50
7594 04:41:38.755396 [Byte1]: 50
7595 04:41:38.759534
7596 04:41:38.759632 Set Vref, RX VrefLevel [Byte0]: 51
7597 04:41:38.762861 [Byte1]: 51
7598 04:41:38.766618
7599 04:41:38.766689 Set Vref, RX VrefLevel [Byte0]: 52
7600 04:41:38.769908 [Byte1]: 52
7601 04:41:38.775125
7602 04:41:38.775201 Set Vref, RX VrefLevel [Byte0]: 53
7603 04:41:38.777905 [Byte1]: 53
7604 04:41:38.782475
7605 04:41:38.782596 Set Vref, RX VrefLevel [Byte0]: 54
7606 04:41:38.785315 [Byte1]: 54
7607 04:41:38.789639
7608 04:41:38.789739 Set Vref, RX VrefLevel [Byte0]: 55
7609 04:41:38.792998 [Byte1]: 55
7610 04:41:38.797571
7611 04:41:38.797645 Set Vref, RX VrefLevel [Byte0]: 56
7612 04:41:38.800562 [Byte1]: 56
7613 04:41:38.805122
7614 04:41:38.805194 Set Vref, RX VrefLevel [Byte0]: 57
7615 04:41:38.808354 [Byte1]: 57
7616 04:41:38.812486
7617 04:41:38.812584 Set Vref, RX VrefLevel [Byte0]: 58
7618 04:41:38.816133 [Byte1]: 58
7619 04:41:38.820337
7620 04:41:38.820435 Set Vref, RX VrefLevel [Byte0]: 59
7621 04:41:38.823785 [Byte1]: 59
7622 04:41:38.827881
7623 04:41:38.827977 Set Vref, RX VrefLevel [Byte0]: 60
7624 04:41:38.830944 [Byte1]: 60
7625 04:41:38.835800
7626 04:41:38.835903 Set Vref, RX VrefLevel [Byte0]: 61
7627 04:41:38.838788 [Byte1]: 61
7628 04:41:38.843410
7629 04:41:38.843514 Set Vref, RX VrefLevel [Byte0]: 62
7630 04:41:38.846359 [Byte1]: 62
7631 04:41:38.850481
7632 04:41:38.850646 Set Vref, RX VrefLevel [Byte0]: 63
7633 04:41:38.853983 [Byte1]: 63
7634 04:41:38.858619
7635 04:41:38.858725 Set Vref, RX VrefLevel [Byte0]: 64
7636 04:41:38.861589 [Byte1]: 64
7637 04:41:38.866126
7638 04:41:38.866214 Set Vref, RX VrefLevel [Byte0]: 65
7639 04:41:38.869238 [Byte1]: 65
7640 04:41:38.873977
7641 04:41:38.874140 Set Vref, RX VrefLevel [Byte0]: 66
7642 04:41:38.876795 [Byte1]: 66
7643 04:41:38.881092
7644 04:41:38.881169 Set Vref, RX VrefLevel [Byte0]: 67
7645 04:41:38.884586 [Byte1]: 67
7646 04:41:38.888653
7647 04:41:38.888767 Set Vref, RX VrefLevel [Byte0]: 68
7648 04:41:38.891799 [Byte1]: 68
7649 04:41:38.896254
7650 04:41:38.896351 Set Vref, RX VrefLevel [Byte0]: 69
7651 04:41:38.899695 [Byte1]: 69
7652 04:41:38.903954
7653 04:41:38.904065 Set Vref, RX VrefLevel [Byte0]: 70
7654 04:41:38.906953 [Byte1]: 70
7655 04:41:38.911821
7656 04:41:38.911938 Set Vref, RX VrefLevel [Byte0]: 71
7657 04:41:38.914463 [Byte1]: 71
7658 04:41:38.919096
7659 04:41:38.919168 Set Vref, RX VrefLevel [Byte0]: 72
7660 04:41:38.922561 [Byte1]: 72
7661 04:41:38.926889
7662 04:41:38.926962 Final RX Vref Byte 0 = 51 to rank0
7663 04:41:38.930018 Final RX Vref Byte 1 = 56 to rank0
7664 04:41:38.933641 Final RX Vref Byte 0 = 51 to rank1
7665 04:41:38.936351 Final RX Vref Byte 1 = 56 to rank1==
7666 04:41:38.940215 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 04:41:38.946606 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7668 04:41:38.946714 ==
7669 04:41:38.946807 DQS Delay:
7670 04:41:38.949892 DQS0 = 0, DQS1 = 0
7671 04:41:38.949999 DQM Delay:
7672 04:41:38.950065 DQM0 = 127, DQM1 = 121
7673 04:41:38.952940 DQ Delay:
7674 04:41:38.956426 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =124
7675 04:41:38.959762 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7676 04:41:38.963150 DQ8 =110, DQ9 =104, DQ10 =122, DQ11 =112
7677 04:41:38.966570 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7678 04:41:38.966642
7679 04:41:38.966704
7680 04:41:38.966762
7681 04:41:38.969590 [DramC_TX_OE_Calibration] TA2
7682 04:41:38.973062 Original DQ_B0 (3 6) =30, OEN = 27
7683 04:41:38.976377 Original DQ_B1 (3 6) =30, OEN = 27
7684 04:41:38.979618 24, 0x0, End_B0=24 End_B1=24
7685 04:41:38.979743 25, 0x0, End_B0=25 End_B1=25
7686 04:41:38.983338 26, 0x0, End_B0=26 End_B1=26
7687 04:41:38.986624 27, 0x0, End_B0=27 End_B1=27
7688 04:41:38.989679 28, 0x0, End_B0=28 End_B1=28
7689 04:41:38.993108 29, 0x0, End_B0=29 End_B1=29
7690 04:41:38.993185 30, 0x0, End_B0=30 End_B1=30
7691 04:41:38.996152 31, 0x4141, End_B0=30 End_B1=30
7692 04:41:38.999681 Byte0 end_step=30 best_step=27
7693 04:41:39.002795 Byte1 end_step=30 best_step=27
7694 04:41:39.005999 Byte0 TX OE(2T, 0.5T) = (3, 3)
7695 04:41:39.009237 Byte1 TX OE(2T, 0.5T) = (3, 3)
7696 04:41:39.009336
7697 04:41:39.009400
7698 04:41:39.016130 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7699 04:41:39.019184 CH0 RK0: MR19=303, MR18=1B1B
7700 04:41:39.026051 CH0_RK0: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
7701 04:41:39.026151
7702 04:41:39.029197 ----->DramcWriteLeveling(PI) begin...
7703 04:41:39.029292 ==
7704 04:41:39.032420 Dram Type= 6, Freq= 0, CH_0, rank 1
7705 04:41:39.035906 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7706 04:41:39.036000 ==
7707 04:41:39.039260 Write leveling (Byte 0): 29 => 29
7708 04:41:39.042299 Write leveling (Byte 1): 26 => 26
7709 04:41:39.046006 DramcWriteLeveling(PI) end<-----
7710 04:41:39.046078
7711 04:41:39.046176 ==
7712 04:41:39.048840 Dram Type= 6, Freq= 0, CH_0, rank 1
7713 04:41:39.053551 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7714 04:41:39.053631 ==
7715 04:41:39.055554 [Gating] SW mode calibration
7716 04:41:39.062125 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7717 04:41:39.069614 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7718 04:41:39.072177 0 12 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7719 04:41:39.078920 0 12 4 | B1->B0 | 2524 3434 | 1 1 | (0 0) (1 1)
7720 04:41:39.082183 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7721 04:41:39.085243 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7722 04:41:39.092472 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7723 04:41:39.095343 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7724 04:41:39.098882 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7725 04:41:39.105698 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
7726 04:41:39.109319 0 13 0 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)
7727 04:41:39.111790 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
7728 04:41:39.118305 0 13 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7729 04:41:39.122424 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7730 04:41:39.125391 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7731 04:41:39.132186 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7732 04:41:39.135700 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7733 04:41:39.138547 0 13 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7734 04:41:39.145385 0 14 0 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
7735 04:41:39.148469 0 14 4 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
7736 04:41:39.151660 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7737 04:41:39.158326 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7738 04:41:39.161740 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7739 04:41:39.165404 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7740 04:41:39.171646 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7741 04:41:39.174755 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7742 04:41:39.178763 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7743 04:41:39.181638 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7744 04:41:39.188379 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7745 04:41:39.191536 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7746 04:41:39.194641 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7747 04:41:39.201916 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7748 04:41:39.205114 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7749 04:41:39.208333 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 04:41:39.215088 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 04:41:39.217805 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 04:41:39.221287 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 04:41:39.228606 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 04:41:39.231309 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 04:41:39.234430 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 04:41:39.241014 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7757 04:41:39.244493 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7758 04:41:39.247728 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7759 04:41:39.254458 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7760 04:41:39.257681 Total UI for P1: 0, mck2ui 16
7761 04:41:39.260723 best dqsien dly found for B0: ( 1, 0, 30)
7762 04:41:39.264283 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7763 04:41:39.267270 Total UI for P1: 0, mck2ui 16
7764 04:41:39.270549 best dqsien dly found for B1: ( 1, 1, 2)
7765 04:41:39.274192 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7766 04:41:39.277996 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7767 04:41:39.278084
7768 04:41:39.281147 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7769 04:41:39.284756 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7770 04:41:39.286914 [Gating] SW calibration Done
7771 04:41:39.287022 ==
7772 04:41:39.290801 Dram Type= 6, Freq= 0, CH_0, rank 1
7773 04:41:39.297197 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7774 04:41:39.297313 ==
7775 04:41:39.297378 RX Vref Scan: 0
7776 04:41:39.297440
7777 04:41:39.300760 RX Vref 0 -> 0, step: 1
7778 04:41:39.300841
7779 04:41:39.303602 RX Delay 0 -> 252, step: 8
7780 04:41:39.307175 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7781 04:41:39.310201 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7782 04:41:39.314106 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7783 04:41:39.317509 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7784 04:41:39.324223 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7785 04:41:39.326997 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7786 04:41:39.331207 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7787 04:41:39.333449 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7788 04:41:39.337284 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7789 04:41:39.343200 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7790 04:41:39.346685 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7791 04:41:39.350793 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7792 04:41:39.353651 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7793 04:41:39.356438 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7794 04:41:39.363940 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7795 04:41:39.367144 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7796 04:41:39.367229 ==
7797 04:41:39.369752 Dram Type= 6, Freq= 0, CH_0, rank 1
7798 04:41:39.373144 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7799 04:41:39.373229 ==
7800 04:41:39.376780 DQS Delay:
7801 04:41:39.376865 DQS0 = 0, DQS1 = 0
7802 04:41:39.379960 DQM Delay:
7803 04:41:39.380070 DQM0 = 130, DQM1 = 124
7804 04:41:39.380178 DQ Delay:
7805 04:41:39.383021 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7806 04:41:39.390292 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7807 04:41:39.393143 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7808 04:41:39.396255 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7809 04:41:39.396338
7810 04:41:39.396405
7811 04:41:39.396466 ==
7812 04:41:39.399506 Dram Type= 6, Freq= 0, CH_0, rank 1
7813 04:41:39.402626 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7814 04:41:39.402711 ==
7815 04:41:39.402777
7816 04:41:39.402839
7817 04:41:39.406502 TX Vref Scan disable
7818 04:41:39.409436 == TX Byte 0 ==
7819 04:41:39.412824 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7820 04:41:39.415961 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7821 04:41:39.419732 == TX Byte 1 ==
7822 04:41:39.422579 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7823 04:41:39.425878 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7824 04:41:39.425962 ==
7825 04:41:39.429643 Dram Type= 6, Freq= 0, CH_0, rank 1
7826 04:41:39.432447 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7827 04:41:39.436031 ==
7828 04:41:39.447307
7829 04:41:39.450638 TX Vref early break, caculate TX vref
7830 04:41:39.454197 TX Vref=16, minBit 8, minWin=22, winSum=374
7831 04:41:39.457020 TX Vref=18, minBit 9, minWin=22, winSum=379
7832 04:41:39.460199 TX Vref=20, minBit 9, minWin=23, winSum=396
7833 04:41:39.463923 TX Vref=22, minBit 1, minWin=24, winSum=398
7834 04:41:39.467539 TX Vref=24, minBit 1, minWin=24, winSum=404
7835 04:41:39.473531 TX Vref=26, minBit 8, minWin=24, winSum=415
7836 04:41:39.476977 TX Vref=28, minBit 8, minWin=24, winSum=415
7837 04:41:39.480205 TX Vref=30, minBit 8, minWin=24, winSum=412
7838 04:41:39.484141 TX Vref=32, minBit 1, minWin=24, winSum=400
7839 04:41:39.486785 TX Vref=34, minBit 1, minWin=24, winSum=393
7840 04:41:39.493595 [TxChooseVref] Worse bit 8, Min win 24, Win sum 415, Final Vref 26
7841 04:41:39.493678
7842 04:41:39.496769 Final TX Range 0 Vref 26
7843 04:41:39.496900
7844 04:41:39.496966 ==
7845 04:41:39.500067 Dram Type= 6, Freq= 0, CH_0, rank 1
7846 04:41:39.503536 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7847 04:41:39.503661 ==
7848 04:41:39.503743
7849 04:41:39.503805
7850 04:41:39.506892 TX Vref Scan disable
7851 04:41:39.513297 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7852 04:41:39.513380 == TX Byte 0 ==
7853 04:41:39.517076 u2DelayCellOfst[0]=14 cells (4 PI)
7854 04:41:39.520537 u2DelayCellOfst[1]=18 cells (5 PI)
7855 04:41:39.523451 u2DelayCellOfst[2]=10 cells (3 PI)
7856 04:41:39.526975 u2DelayCellOfst[3]=14 cells (4 PI)
7857 04:41:39.529827 u2DelayCellOfst[4]=10 cells (3 PI)
7858 04:41:39.533164 u2DelayCellOfst[5]=0 cells (0 PI)
7859 04:41:39.536727 u2DelayCellOfst[6]=18 cells (5 PI)
7860 04:41:39.539974 u2DelayCellOfst[7]=21 cells (6 PI)
7861 04:41:39.543877 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7862 04:41:39.546341 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7863 04:41:39.549948 == TX Byte 1 ==
7864 04:41:39.553123 u2DelayCellOfst[8]=0 cells (0 PI)
7865 04:41:39.553231 u2DelayCellOfst[9]=0 cells (0 PI)
7866 04:41:39.556623 u2DelayCellOfst[10]=10 cells (3 PI)
7867 04:41:39.559712 u2DelayCellOfst[11]=7 cells (2 PI)
7868 04:41:39.563051 u2DelayCellOfst[12]=10 cells (3 PI)
7869 04:41:39.566408 u2DelayCellOfst[13]=14 cells (4 PI)
7870 04:41:39.569499 u2DelayCellOfst[14]=18 cells (5 PI)
7871 04:41:39.573640 u2DelayCellOfst[15]=14 cells (4 PI)
7872 04:41:39.576848 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7873 04:41:39.583432 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7874 04:41:39.583515 DramC Write-DBI on
7875 04:41:39.583612 ==
7876 04:41:39.586304 Dram Type= 6, Freq= 0, CH_0, rank 1
7877 04:41:39.592703 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7878 04:41:39.592825 ==
7879 04:41:39.592890
7880 04:41:39.592951
7881 04:41:39.593009 TX Vref Scan disable
7882 04:41:39.597004 == TX Byte 0 ==
7883 04:41:39.600660 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7884 04:41:39.603461 == TX Byte 1 ==
7885 04:41:39.606967 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7886 04:41:39.610163 DramC Write-DBI off
7887 04:41:39.610245
7888 04:41:39.610310 [DATLAT]
7889 04:41:39.610396 Freq=1600, CH0 RK1
7890 04:41:39.610485
7891 04:41:39.613302 DATLAT Default: 0xe
7892 04:41:39.613374 0, 0xFFFF, sum = 0
7893 04:41:39.616520 1, 0xFFFF, sum = 0
7894 04:41:39.620270 2, 0xFFFF, sum = 0
7895 04:41:39.620344 3, 0xFFFF, sum = 0
7896 04:41:39.623402 4, 0xFFFF, sum = 0
7897 04:41:39.623508 5, 0xFFFF, sum = 0
7898 04:41:39.626472 6, 0xFFFF, sum = 0
7899 04:41:39.626570 7, 0xFFFF, sum = 0
7900 04:41:39.630272 8, 0xFFFF, sum = 0
7901 04:41:39.630370 9, 0xFFFF, sum = 0
7902 04:41:39.633506 10, 0xFFFF, sum = 0
7903 04:41:39.633604 11, 0xFFFF, sum = 0
7904 04:41:39.636456 12, 0x8FFF, sum = 0
7905 04:41:39.636560 13, 0x0, sum = 1
7906 04:41:39.639827 14, 0x0, sum = 2
7907 04:41:39.639924 15, 0x0, sum = 3
7908 04:41:39.643136 16, 0x0, sum = 4
7909 04:41:39.643232 best_step = 14
7910 04:41:39.643328
7911 04:41:39.643413 ==
7912 04:41:39.646485 Dram Type= 6, Freq= 0, CH_0, rank 1
7913 04:41:39.649944 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7914 04:41:39.653170 ==
7915 04:41:39.653256 RX Vref Scan: 0
7916 04:41:39.653322
7917 04:41:39.656279 RX Vref 0 -> 0, step: 1
7918 04:41:39.656348
7919 04:41:39.656409 RX Delay 11 -> 252, step: 4
7920 04:41:39.664122 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7921 04:41:39.666907 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7922 04:41:39.670326 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7923 04:41:39.674305 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7924 04:41:39.677694 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7925 04:41:39.684598 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7926 04:41:39.687264 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
7927 04:41:39.690465 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7928 04:41:39.693593 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
7929 04:41:39.697191 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7930 04:41:39.703955 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7931 04:41:39.706768 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7932 04:41:39.709981 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7933 04:41:39.713601 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7934 04:41:39.719982 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7935 04:41:39.723756 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7936 04:41:39.723827 ==
7937 04:41:39.726988 Dram Type= 6, Freq= 0, CH_0, rank 1
7938 04:41:39.730156 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7939 04:41:39.730226 ==
7940 04:41:39.733446 DQS Delay:
7941 04:41:39.733514 DQS0 = 0, DQS1 = 0
7942 04:41:39.733578 DQM Delay:
7943 04:41:39.737068 DQM0 = 128, DQM1 = 120
7944 04:41:39.737138 DQ Delay:
7945 04:41:39.739890 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
7946 04:41:39.743078 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =138
7947 04:41:39.746793 DQ8 =110, DQ9 =106, DQ10 =122, DQ11 =112
7948 04:41:39.753074 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
7949 04:41:39.753187
7950 04:41:39.753290
7951 04:41:39.753381
7952 04:41:39.756608 [DramC_TX_OE_Calibration] TA2
7953 04:41:39.760149 Original DQ_B0 (3 6) =30, OEN = 27
7954 04:41:39.760238 Original DQ_B1 (3 6) =30, OEN = 27
7955 04:41:39.762874 24, 0x0, End_B0=24 End_B1=24
7956 04:41:39.766173 25, 0x0, End_B0=25 End_B1=25
7957 04:41:39.769640 26, 0x0, End_B0=26 End_B1=26
7958 04:41:39.772934 27, 0x0, End_B0=27 End_B1=27
7959 04:41:39.773008 28, 0x0, End_B0=28 End_B1=28
7960 04:41:39.776265 29, 0x0, End_B0=29 End_B1=29
7961 04:41:39.779535 30, 0x0, End_B0=30 End_B1=30
7962 04:41:39.783232 31, 0x4141, End_B0=30 End_B1=30
7963 04:41:39.786042 Byte0 end_step=30 best_step=27
7964 04:41:39.789504 Byte1 end_step=30 best_step=27
7965 04:41:39.789583 Byte0 TX OE(2T, 0.5T) = (3, 3)
7966 04:41:39.793615 Byte1 TX OE(2T, 0.5T) = (3, 3)
7967 04:41:39.793693
7968 04:41:39.793755
7969 04:41:39.802743 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
7970 04:41:39.806301 CH0 RK1: MR19=303, MR18=2121
7971 04:41:39.809133 CH0_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
7972 04:41:39.813125 [RxdqsGatingPostProcess] freq 1600
7973 04:41:39.819401 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7974 04:41:39.822629 Pre-setting of DQS Precalculation
7975 04:41:39.825853 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7976 04:41:39.825931 ==
7977 04:41:39.829516 Dram Type= 6, Freq= 0, CH_1, rank 0
7978 04:41:39.835626 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7979 04:41:39.835704 ==
7980 04:41:39.839128 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7981 04:41:39.845773 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7982 04:41:39.849271 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7983 04:41:39.855349 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7984 04:41:39.862787 [CA 0] Center 40 (10~71) winsize 62
7985 04:41:39.866008 [CA 1] Center 40 (10~70) winsize 61
7986 04:41:39.869816 [CA 2] Center 36 (7~66) winsize 60
7987 04:41:39.873205 [CA 3] Center 35 (6~65) winsize 60
7988 04:41:39.876113 [CA 4] Center 33 (4~63) winsize 60
7989 04:41:39.879479 [CA 5] Center 33 (4~63) winsize 60
7990 04:41:39.879552
7991 04:41:39.882619 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7992 04:41:39.882724
7993 04:41:39.886495 [CATrainingPosCal] consider 1 rank data
7994 04:41:39.889545 u2DelayCellTimex100 = 271/100 ps
7995 04:41:39.893056 CA0 delay=40 (10~71),Diff = 7 PI (25 cell)
7996 04:41:39.899391 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
7997 04:41:39.902873 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
7998 04:41:39.905951 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
7999 04:41:39.909336 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8000 04:41:39.912860 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8001 04:41:39.912939
8002 04:41:39.915669 CA PerBit enable=1, Macro0, CA PI delay=33
8003 04:41:39.915744
8004 04:41:39.918956 [CBTSetCACLKResult] CA Dly = 33
8005 04:41:39.922221 CS Dly: 9 (0~40)
8006 04:41:39.925580 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8007 04:41:39.928955 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8008 04:41:39.929031 ==
8009 04:41:39.932714 Dram Type= 6, Freq= 0, CH_1, rank 1
8010 04:41:39.935950 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8011 04:41:39.938833 ==
8012 04:41:39.942448 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8013 04:41:39.946083 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8014 04:41:39.952070 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8015 04:41:39.958524 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8016 04:41:39.965016 [CA 0] Center 41 (11~71) winsize 61
8017 04:41:39.968800 [CA 1] Center 40 (10~71) winsize 62
8018 04:41:39.971669 [CA 2] Center 36 (7~66) winsize 60
8019 04:41:39.975440 [CA 3] Center 36 (7~65) winsize 59
8020 04:41:39.978996 [CA 4] Center 34 (5~64) winsize 60
8021 04:41:39.981960 [CA 5] Center 34 (5~64) winsize 60
8022 04:41:39.982045
8023 04:41:39.985810 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8024 04:41:39.985884
8025 04:41:39.988248 [CATrainingPosCal] consider 2 rank data
8026 04:41:39.992109 u2DelayCellTimex100 = 271/100 ps
8027 04:41:39.994778 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8028 04:41:40.001846 CA1 delay=40 (10~70),Diff = 6 PI (21 cell)
8029 04:41:40.004794 CA2 delay=36 (7~66),Diff = 2 PI (7 cell)
8030 04:41:40.008400 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8031 04:41:40.011761 CA4 delay=34 (5~63),Diff = 0 PI (0 cell)
8032 04:41:40.015294 CA5 delay=34 (5~63),Diff = 0 PI (0 cell)
8033 04:41:40.015366
8034 04:41:40.018841 CA PerBit enable=1, Macro0, CA PI delay=34
8035 04:41:40.018916
8036 04:41:40.021323 [CBTSetCACLKResult] CA Dly = 34
8037 04:41:40.024835 CS Dly: 9 (0~41)
8038 04:41:40.028025 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8039 04:41:40.031630 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8040 04:41:40.031714
8041 04:41:40.035068 ----->DramcWriteLeveling(PI) begin...
8042 04:41:40.035145 ==
8043 04:41:40.037891 Dram Type= 6, Freq= 0, CH_1, rank 0
8044 04:41:40.044627 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8045 04:41:40.044713 ==
8046 04:41:40.047798 Write leveling (Byte 0): 21 => 21
8047 04:41:40.047871 Write leveling (Byte 1): 21 => 21
8048 04:41:40.051176 DramcWriteLeveling(PI) end<-----
8049 04:41:40.051250
8050 04:41:40.051311 ==
8051 04:41:40.054401 Dram Type= 6, Freq= 0, CH_1, rank 0
8052 04:41:40.061571 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8053 04:41:40.061647 ==
8054 04:41:40.064468 [Gating] SW mode calibration
8055 04:41:40.070957 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8056 04:41:40.074638 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8057 04:41:40.081450 0 12 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8058 04:41:40.084360 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 04:41:40.087569 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 04:41:40.094521 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 04:41:40.098345 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 04:41:40.101135 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 04:41:40.107711 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8064 04:41:40.111350 0 12 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
8065 04:41:40.114342 0 13 0 | B1->B0 | 3333 2424 | 1 0 | (1 0) (0 0)
8066 04:41:40.121097 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8067 04:41:40.124254 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 04:41:40.127450 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 04:41:40.134333 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 04:41:40.137978 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 04:41:40.140895 0 13 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8072 04:41:40.147349 0 13 28 | B1->B0 | 2323 3837 | 0 1 | (0 0) (0 0)
8073 04:41:40.151514 0 14 0 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
8074 04:41:40.153861 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 04:41:40.157363 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 04:41:40.164026 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 04:41:40.167369 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 04:41:40.170615 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 04:41:40.177336 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8080 04:41:40.180592 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8081 04:41:40.183817 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8082 04:41:40.190883 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8083 04:41:40.193649 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 04:41:40.196981 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 04:41:40.204117 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 04:41:40.206798 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 04:41:40.210102 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 04:41:40.216904 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 04:41:40.220375 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 04:41:40.223831 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 04:41:40.230281 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 04:41:40.233470 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 04:41:40.236811 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 04:41:40.243521 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 04:41:40.246821 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8096 04:41:40.250818 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8097 04:41:40.256699 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8098 04:41:40.256792 Total UI for P1: 0, mck2ui 16
8099 04:41:40.263142 best dqsien dly found for B0: ( 1, 0, 26)
8100 04:41:40.266833 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8101 04:41:40.270369 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 04:41:40.273109 Total UI for P1: 0, mck2ui 16
8103 04:41:40.276646 best dqsien dly found for B1: ( 1, 1, 0)
8104 04:41:40.279593 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8105 04:41:40.283075 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8106 04:41:40.283156
8107 04:41:40.289617 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8108 04:41:40.292991 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8109 04:41:40.293069 [Gating] SW calibration Done
8110 04:41:40.296831 ==
8111 04:41:40.299745 Dram Type= 6, Freq= 0, CH_1, rank 0
8112 04:41:40.303210 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8113 04:41:40.303285 ==
8114 04:41:40.303346 RX Vref Scan: 0
8115 04:41:40.303405
8116 04:41:40.306769 RX Vref 0 -> 0, step: 1
8117 04:41:40.306849
8118 04:41:40.309583 RX Delay 0 -> 252, step: 8
8119 04:41:40.313276 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8120 04:41:40.316686 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8121 04:41:40.319987 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8122 04:41:40.325870 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8123 04:41:40.329537 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8124 04:41:40.332599 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8125 04:41:40.336811 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8126 04:41:40.339390 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8127 04:41:40.346462 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8128 04:41:40.349224 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8129 04:41:40.352734 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8130 04:41:40.355753 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8131 04:41:40.359082 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8132 04:41:40.366315 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8133 04:41:40.369241 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8134 04:41:40.373206 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8135 04:41:40.373282 ==
8136 04:41:40.376129 Dram Type= 6, Freq= 0, CH_1, rank 0
8137 04:41:40.379323 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8138 04:41:40.382501 ==
8139 04:41:40.382587 DQS Delay:
8140 04:41:40.382651 DQS0 = 0, DQS1 = 0
8141 04:41:40.385429 DQM Delay:
8142 04:41:40.385506 DQM0 = 129, DQM1 = 125
8143 04:41:40.389636 DQ Delay:
8144 04:41:40.392281 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8145 04:41:40.395665 DQ4 =127, DQ5 =143, DQ6 =135, DQ7 =127
8146 04:41:40.399268 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8147 04:41:40.403217 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8148 04:41:40.403296
8149 04:41:40.403358
8150 04:41:40.403417 ==
8151 04:41:40.405423 Dram Type= 6, Freq= 0, CH_1, rank 0
8152 04:41:40.408676 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8153 04:41:40.408780 ==
8154 04:41:40.412624
8155 04:41:40.412700
8156 04:41:40.412799 TX Vref Scan disable
8157 04:41:40.415503 == TX Byte 0 ==
8158 04:41:40.418934 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8159 04:41:40.422222 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8160 04:41:40.425921 == TX Byte 1 ==
8161 04:41:40.428909 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8162 04:41:40.432423 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8163 04:41:40.432497 ==
8164 04:41:40.436371 Dram Type= 6, Freq= 0, CH_1, rank 0
8165 04:41:40.442055 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8166 04:41:40.442131 ==
8167 04:41:40.453401
8168 04:41:40.456541 TX Vref early break, caculate TX vref
8169 04:41:40.459706 TX Vref=16, minBit 3, minWin=21, winSum=368
8170 04:41:40.463073 TX Vref=18, minBit 1, minWin=22, winSum=376
8171 04:41:40.466656 TX Vref=20, minBit 0, minWin=23, winSum=386
8172 04:41:40.469540 TX Vref=22, minBit 3, minWin=22, winSum=389
8173 04:41:40.473084 TX Vref=24, minBit 1, minWin=24, winSum=406
8174 04:41:40.479681 TX Vref=26, minBit 3, minWin=24, winSum=412
8175 04:41:40.483195 TX Vref=28, minBit 0, minWin=24, winSum=415
8176 04:41:40.486387 TX Vref=30, minBit 1, minWin=24, winSum=403
8177 04:41:40.490436 TX Vref=32, minBit 3, minWin=23, winSum=399
8178 04:41:40.493005 TX Vref=34, minBit 1, minWin=22, winSum=393
8179 04:41:40.499533 [TxChooseVref] Worse bit 0, Min win 24, Win sum 415, Final Vref 28
8180 04:41:40.499634
8181 04:41:40.502705 Final TX Range 0 Vref 28
8182 04:41:40.502788
8183 04:41:40.502918 ==
8184 04:41:40.506391 Dram Type= 6, Freq= 0, CH_1, rank 0
8185 04:41:40.509416 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8186 04:41:40.509577 ==
8187 04:41:40.509667
8188 04:41:40.509760
8189 04:41:40.512656 TX Vref Scan disable
8190 04:41:40.519364 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8191 04:41:40.519440 == TX Byte 0 ==
8192 04:41:40.523255 u2DelayCellOfst[0]=18 cells (5 PI)
8193 04:41:40.525962 u2DelayCellOfst[1]=14 cells (4 PI)
8194 04:41:40.529155 u2DelayCellOfst[2]=0 cells (0 PI)
8195 04:41:40.532688 u2DelayCellOfst[3]=7 cells (2 PI)
8196 04:41:40.535751 u2DelayCellOfst[4]=10 cells (3 PI)
8197 04:41:40.539997 u2DelayCellOfst[5]=18 cells (5 PI)
8198 04:41:40.542814 u2DelayCellOfst[6]=18 cells (5 PI)
8199 04:41:40.545908 u2DelayCellOfst[7]=7 cells (2 PI)
8200 04:41:40.549381 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8201 04:41:40.552989 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8202 04:41:40.556049 == TX Byte 1 ==
8203 04:41:40.556146 u2DelayCellOfst[8]=0 cells (0 PI)
8204 04:41:40.559636 u2DelayCellOfst[9]=3 cells (1 PI)
8205 04:41:40.562657 u2DelayCellOfst[10]=7 cells (2 PI)
8206 04:41:40.565891 u2DelayCellOfst[11]=0 cells (0 PI)
8207 04:41:40.569114 u2DelayCellOfst[12]=14 cells (4 PI)
8208 04:41:40.572212 u2DelayCellOfst[13]=18 cells (5 PI)
8209 04:41:40.575558 u2DelayCellOfst[14]=18 cells (5 PI)
8210 04:41:40.578931 u2DelayCellOfst[15]=18 cells (5 PI)
8211 04:41:40.582234 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8212 04:41:40.589472 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8213 04:41:40.589569 DramC Write-DBI on
8214 04:41:40.589675 ==
8215 04:41:40.592141 Dram Type= 6, Freq= 0, CH_1, rank 0
8216 04:41:40.598939 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8217 04:41:40.599035 ==
8218 04:41:40.599124
8219 04:41:40.599200
8220 04:41:40.599303 TX Vref Scan disable
8221 04:41:40.603152 == TX Byte 0 ==
8222 04:41:40.606130 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8223 04:41:40.608782 == TX Byte 1 ==
8224 04:41:40.612375 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8225 04:41:40.615875 DramC Write-DBI off
8226 04:41:40.615956
8227 04:41:40.616037 [DATLAT]
8228 04:41:40.616174 Freq=1600, CH1 RK0
8229 04:41:40.616300
8230 04:41:40.619045 DATLAT Default: 0xf
8231 04:41:40.622760 0, 0xFFFF, sum = 0
8232 04:41:40.622878 1, 0xFFFF, sum = 0
8233 04:41:40.625420 2, 0xFFFF, sum = 0
8234 04:41:40.625495 3, 0xFFFF, sum = 0
8235 04:41:40.629079 4, 0xFFFF, sum = 0
8236 04:41:40.629177 5, 0xFFFF, sum = 0
8237 04:41:40.631952 6, 0xFFFF, sum = 0
8238 04:41:40.632038 7, 0xFFFF, sum = 0
8239 04:41:40.635650 8, 0xFFFF, sum = 0
8240 04:41:40.635721 9, 0xFFFF, sum = 0
8241 04:41:40.638718 10, 0xFFFF, sum = 0
8242 04:41:40.638797 11, 0xFFFF, sum = 0
8243 04:41:40.642228 12, 0xF7F, sum = 0
8244 04:41:40.642317 13, 0x0, sum = 1
8245 04:41:40.645397 14, 0x0, sum = 2
8246 04:41:40.645467 15, 0x0, sum = 3
8247 04:41:40.648595 16, 0x0, sum = 4
8248 04:41:40.648721 best_step = 14
8249 04:41:40.648798
8250 04:41:40.648855 ==
8251 04:41:40.651671 Dram Type= 6, Freq= 0, CH_1, rank 0
8252 04:41:40.655012 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8253 04:41:40.658263 ==
8254 04:41:40.658338 RX Vref Scan: 1
8255 04:41:40.658399
8256 04:41:40.661948 Set Vref Range= 24 -> 127
8257 04:41:40.662013
8258 04:41:40.665092 RX Vref 24 -> 127, step: 1
8259 04:41:40.665158
8260 04:41:40.665216 RX Delay 3 -> 252, step: 4
8261 04:41:40.665271
8262 04:41:40.668466 Set Vref, RX VrefLevel [Byte0]: 24
8263 04:41:40.672047 [Byte1]: 24
8264 04:41:40.675547
8265 04:41:40.675613 Set Vref, RX VrefLevel [Byte0]: 25
8266 04:41:40.678954 [Byte1]: 25
8267 04:41:40.683014
8268 04:41:40.683121 Set Vref, RX VrefLevel [Byte0]: 26
8269 04:41:40.686438 [Byte1]: 26
8270 04:41:40.691115
8271 04:41:40.694636 Set Vref, RX VrefLevel [Byte0]: 27
8272 04:41:40.697412 [Byte1]: 27
8273 04:41:40.697504
8274 04:41:40.700644 Set Vref, RX VrefLevel [Byte0]: 28
8275 04:41:40.704709 [Byte1]: 28
8276 04:41:40.704796
8277 04:41:40.707540 Set Vref, RX VrefLevel [Byte0]: 29
8278 04:41:40.710932 [Byte1]: 29
8279 04:41:40.714055
8280 04:41:40.714133 Set Vref, RX VrefLevel [Byte0]: 30
8281 04:41:40.717275 [Byte1]: 30
8282 04:41:40.721667
8283 04:41:40.721739 Set Vref, RX VrefLevel [Byte0]: 31
8284 04:41:40.724862 [Byte1]: 31
8285 04:41:40.729357
8286 04:41:40.729427 Set Vref, RX VrefLevel [Byte0]: 32
8287 04:41:40.732547 [Byte1]: 32
8288 04:41:40.737341
8289 04:41:40.737410 Set Vref, RX VrefLevel [Byte0]: 33
8290 04:41:40.740632 [Byte1]: 33
8291 04:41:40.744727
8292 04:41:40.744831 Set Vref, RX VrefLevel [Byte0]: 34
8293 04:41:40.747721 [Byte1]: 34
8294 04:41:40.752380
8295 04:41:40.752483 Set Vref, RX VrefLevel [Byte0]: 35
8296 04:41:40.755881 [Byte1]: 35
8297 04:41:40.759550
8298 04:41:40.759649 Set Vref, RX VrefLevel [Byte0]: 36
8299 04:41:40.763299 [Byte1]: 36
8300 04:41:40.767324
8301 04:41:40.767398 Set Vref, RX VrefLevel [Byte0]: 37
8302 04:41:40.770680 [Byte1]: 37
8303 04:41:40.775172
8304 04:41:40.775241 Set Vref, RX VrefLevel [Byte0]: 38
8305 04:41:40.778439 [Byte1]: 38
8306 04:41:40.783024
8307 04:41:40.783105 Set Vref, RX VrefLevel [Byte0]: 39
8308 04:41:40.785989 [Byte1]: 39
8309 04:41:40.790432
8310 04:41:40.790512 Set Vref, RX VrefLevel [Byte0]: 40
8311 04:41:40.793556 [Byte1]: 40
8312 04:41:40.797844
8313 04:41:40.797911 Set Vref, RX VrefLevel [Byte0]: 41
8314 04:41:40.801045 [Byte1]: 41
8315 04:41:40.806245
8316 04:41:40.806318 Set Vref, RX VrefLevel [Byte0]: 42
8317 04:41:40.808805 [Byte1]: 42
8318 04:41:40.813340
8319 04:41:40.813407 Set Vref, RX VrefLevel [Byte0]: 43
8320 04:41:40.816658 [Byte1]: 43
8321 04:41:40.821243
8322 04:41:40.821311 Set Vref, RX VrefLevel [Byte0]: 44
8323 04:41:40.824324 [Byte1]: 44
8324 04:41:40.828606
8325 04:41:40.828714 Set Vref, RX VrefLevel [Byte0]: 45
8326 04:41:40.831987 [Byte1]: 45
8327 04:41:40.836344
8328 04:41:40.836425 Set Vref, RX VrefLevel [Byte0]: 46
8329 04:41:40.839558 [Byte1]: 46
8330 04:41:40.844231
8331 04:41:40.844309 Set Vref, RX VrefLevel [Byte0]: 47
8332 04:41:40.847221 [Byte1]: 47
8333 04:41:40.851605
8334 04:41:40.851678 Set Vref, RX VrefLevel [Byte0]: 48
8335 04:41:40.855067 [Byte1]: 48
8336 04:41:40.859378
8337 04:41:40.859452 Set Vref, RX VrefLevel [Byte0]: 49
8338 04:41:40.862803 [Byte1]: 49
8339 04:41:40.866741
8340 04:41:40.866814 Set Vref, RX VrefLevel [Byte0]: 50
8341 04:41:40.870851 [Byte1]: 50
8342 04:41:40.874566
8343 04:41:40.874651 Set Vref, RX VrefLevel [Byte0]: 51
8344 04:41:40.878004 [Byte1]: 51
8345 04:41:40.882299
8346 04:41:40.882404 Set Vref, RX VrefLevel [Byte0]: 52
8347 04:41:40.885330 [Byte1]: 52
8348 04:41:40.889893
8349 04:41:40.889973 Set Vref, RX VrefLevel [Byte0]: 53
8350 04:41:40.893206 [Byte1]: 53
8351 04:41:40.897630
8352 04:41:40.897698 Set Vref, RX VrefLevel [Byte0]: 54
8353 04:41:40.900798 [Byte1]: 54
8354 04:41:40.905250
8355 04:41:40.905332 Set Vref, RX VrefLevel [Byte0]: 55
8356 04:41:40.908879 [Byte1]: 55
8357 04:41:40.913091
8358 04:41:40.913163 Set Vref, RX VrefLevel [Byte0]: 56
8359 04:41:40.916741 [Byte1]: 56
8360 04:41:40.920300
8361 04:41:40.920371 Set Vref, RX VrefLevel [Byte0]: 57
8362 04:41:40.923813 [Byte1]: 57
8363 04:41:40.928381
8364 04:41:40.928455 Set Vref, RX VrefLevel [Byte0]: 58
8365 04:41:40.931681 [Byte1]: 58
8366 04:41:40.935791
8367 04:41:40.935865 Set Vref, RX VrefLevel [Byte0]: 59
8368 04:41:40.939194 [Byte1]: 59
8369 04:41:40.943741
8370 04:41:40.943812 Set Vref, RX VrefLevel [Byte0]: 60
8371 04:41:40.946961 [Byte1]: 60
8372 04:41:40.951164
8373 04:41:40.951242 Set Vref, RX VrefLevel [Byte0]: 61
8374 04:41:40.954505 [Byte1]: 61
8375 04:41:40.958802
8376 04:41:40.958924 Set Vref, RX VrefLevel [Byte0]: 62
8377 04:41:40.961901 [Byte1]: 62
8378 04:41:40.966400
8379 04:41:40.966505 Set Vref, RX VrefLevel [Byte0]: 63
8380 04:41:40.969537 [Byte1]: 63
8381 04:41:40.974685
8382 04:41:40.974782 Set Vref, RX VrefLevel [Byte0]: 64
8383 04:41:40.977491 [Byte1]: 64
8384 04:41:40.982093
8385 04:41:40.982189 Set Vref, RX VrefLevel [Byte0]: 65
8386 04:41:40.985311 [Byte1]: 65
8387 04:41:40.990033
8388 04:41:40.990114 Set Vref, RX VrefLevel [Byte0]: 66
8389 04:41:40.992648 [Byte1]: 66
8390 04:41:40.996913
8391 04:41:40.996993 Set Vref, RX VrefLevel [Byte0]: 67
8392 04:41:41.000304 [Byte1]: 67
8393 04:41:41.004683
8394 04:41:41.004803 Set Vref, RX VrefLevel [Byte0]: 68
8395 04:41:41.008287 [Byte1]: 68
8396 04:41:41.012500
8397 04:41:41.012597 Set Vref, RX VrefLevel [Byte0]: 69
8398 04:41:41.015512 [Byte1]: 69
8399 04:41:41.020289
8400 04:41:41.020368 Set Vref, RX VrefLevel [Byte0]: 70
8401 04:41:41.023808 [Byte1]: 70
8402 04:41:41.027601
8403 04:41:41.027698 Set Vref, RX VrefLevel [Byte0]: 71
8404 04:41:41.030936 [Byte1]: 71
8405 04:41:41.035349
8406 04:41:41.035445 Set Vref, RX VrefLevel [Byte0]: 72
8407 04:41:41.039008 [Byte1]: 72
8408 04:41:41.043042
8409 04:41:41.043123 Set Vref, RX VrefLevel [Byte0]: 73
8410 04:41:41.046262 [Byte1]: 73
8411 04:41:41.050731
8412 04:41:41.050852 Set Vref, RX VrefLevel [Byte0]: 74
8413 04:41:41.054482 [Byte1]: 74
8414 04:41:41.058287
8415 04:41:41.058370 Set Vref, RX VrefLevel [Byte0]: 75
8416 04:41:41.062069 [Byte1]: 75
8417 04:41:41.066392
8418 04:41:41.066472 Final RX Vref Byte 0 = 57 to rank0
8419 04:41:41.069333 Final RX Vref Byte 1 = 54 to rank0
8420 04:41:41.073000 Final RX Vref Byte 0 = 57 to rank1
8421 04:41:41.076043 Final RX Vref Byte 1 = 54 to rank1==
8422 04:41:41.079287 Dram Type= 6, Freq= 0, CH_1, rank 0
8423 04:41:41.086251 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8424 04:41:41.086361 ==
8425 04:41:41.086464 DQS Delay:
8426 04:41:41.089230 DQS0 = 0, DQS1 = 0
8427 04:41:41.089308 DQM Delay:
8428 04:41:41.089373 DQM0 = 128, DQM1 = 124
8429 04:41:41.092196 DQ Delay:
8430 04:41:41.095997 DQ0 =130, DQ1 =122, DQ2 =116, DQ3 =126
8431 04:41:41.099008 DQ4 =128, DQ5 =140, DQ6 =136, DQ7 =126
8432 04:41:41.102518 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8433 04:41:41.105550 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134
8434 04:41:41.105635
8435 04:41:41.105720
8436 04:41:41.105800
8437 04:41:41.108968 [DramC_TX_OE_Calibration] TA2
8438 04:41:41.112601 Original DQ_B0 (3 6) =30, OEN = 27
8439 04:41:41.116017 Original DQ_B1 (3 6) =30, OEN = 27
8440 04:41:41.119115 24, 0x0, End_B0=24 End_B1=24
8441 04:41:41.119202 25, 0x0, End_B0=25 End_B1=25
8442 04:41:41.122135 26, 0x0, End_B0=26 End_B1=26
8443 04:41:41.125408 27, 0x0, End_B0=27 End_B1=27
8444 04:41:41.128863 28, 0x0, End_B0=28 End_B1=28
8445 04:41:41.132120 29, 0x0, End_B0=29 End_B1=29
8446 04:41:41.132190 30, 0x0, End_B0=30 End_B1=30
8447 04:41:41.135976 31, 0x4545, End_B0=30 End_B1=30
8448 04:41:41.139225 Byte0 end_step=30 best_step=27
8449 04:41:41.142622 Byte1 end_step=30 best_step=27
8450 04:41:41.145564 Byte0 TX OE(2T, 0.5T) = (3, 3)
8451 04:41:41.149335 Byte1 TX OE(2T, 0.5T) = (3, 3)
8452 04:41:41.149418
8453 04:41:41.149481
8454 04:41:41.155172 [DQSOSCAuto] RK0, (LSB)MR18= 0x2727, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8455 04:41:41.158486 CH1 RK0: MR19=303, MR18=2727
8456 04:41:41.165499 CH1_RK0: MR19=0x303, MR18=0x2727, DQSOSC=390, MR23=63, INC=24, DEC=16
8457 04:41:41.165574
8458 04:41:41.168509 ----->DramcWriteLeveling(PI) begin...
8459 04:41:41.168581 ==
8460 04:41:41.172220 Dram Type= 6, Freq= 0, CH_1, rank 1
8461 04:41:41.175355 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8462 04:41:41.175425 ==
8463 04:41:41.179041 Write leveling (Byte 0): 22 => 22
8464 04:41:41.181751 Write leveling (Byte 1): 22 => 22
8465 04:41:41.185469 DramcWriteLeveling(PI) end<-----
8466 04:41:41.185553
8467 04:41:41.185616 ==
8468 04:41:41.188526 Dram Type= 6, Freq= 0, CH_1, rank 1
8469 04:41:41.192060 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8470 04:41:41.192129 ==
8471 04:41:41.195291 [Gating] SW mode calibration
8472 04:41:41.202315 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8473 04:41:41.208678 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8474 04:41:41.211732 0 12 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8475 04:41:41.215592 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8476 04:41:41.222176 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8477 04:41:41.225736 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8478 04:41:41.228084 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8479 04:41:41.235009 0 12 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8480 04:41:41.238802 0 12 24 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8481 04:41:41.241762 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8482 04:41:41.248316 0 13 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
8483 04:41:41.251316 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8484 04:41:41.255060 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8485 04:41:41.261471 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8486 04:41:41.265117 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8487 04:41:41.267798 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8488 04:41:41.274647 0 13 24 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8489 04:41:41.278169 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8490 04:41:41.281330 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8491 04:41:41.287862 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8492 04:41:41.291348 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8493 04:41:41.294521 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8494 04:41:41.301142 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8495 04:41:41.304835 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8496 04:41:41.307471 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8497 04:41:41.314914 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8498 04:41:41.318021 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 04:41:41.320959 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 04:41:41.327344 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 04:41:41.330473 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 04:41:41.334238 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 04:41:41.340922 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 04:41:41.343764 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 04:41:41.347498 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 04:41:41.354050 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 04:41:41.357099 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 04:41:41.361011 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 04:41:41.367138 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 04:41:41.371018 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 04:41:41.373625 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 04:41:41.380595 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8513 04:41:41.383952 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8514 04:41:41.386708 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8515 04:41:41.390258 Total UI for P1: 0, mck2ui 16
8516 04:41:41.393830 best dqsien dly found for B0: ( 1, 0, 26)
8517 04:41:41.397000 Total UI for P1: 0, mck2ui 16
8518 04:41:41.400097 best dqsien dly found for B1: ( 1, 0, 28)
8519 04:41:41.403598 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8520 04:41:41.407020 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8521 04:41:41.407119
8522 04:41:41.414007 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8523 04:41:41.417270 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8524 04:41:41.420563 [Gating] SW calibration Done
8525 04:41:41.420666 ==
8526 04:41:41.423679 Dram Type= 6, Freq= 0, CH_1, rank 1
8527 04:41:41.426683 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8528 04:41:41.426761 ==
8529 04:41:41.426844 RX Vref Scan: 0
8530 04:41:41.426925
8531 04:41:41.430207 RX Vref 0 -> 0, step: 1
8532 04:41:41.430285
8533 04:41:41.433508 RX Delay 0 -> 252, step: 8
8534 04:41:41.436685 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8535 04:41:41.439845 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8536 04:41:41.446327 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8537 04:41:41.449557 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8538 04:41:41.452970 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8539 04:41:41.456336 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8540 04:41:41.459720 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8541 04:41:41.466111 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8542 04:41:41.469671 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8543 04:41:41.473619 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8544 04:41:41.475939 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8545 04:41:41.479432 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8546 04:41:41.486314 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8547 04:41:41.489327 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8548 04:41:41.492790 iDelay=200, Bit 14, Center 135 (72 ~ 199) 128
8549 04:41:41.495690 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8550 04:41:41.495765 ==
8551 04:41:41.499563 Dram Type= 6, Freq= 0, CH_1, rank 1
8552 04:41:41.506145 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8553 04:41:41.506226 ==
8554 04:41:41.506310 DQS Delay:
8555 04:41:41.509965 DQS0 = 0, DQS1 = 0
8556 04:41:41.510050 DQM Delay:
8557 04:41:41.510133 DQM0 = 132, DQM1 = 126
8558 04:41:41.512615 DQ Delay:
8559 04:41:41.515681 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8560 04:41:41.518749 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8561 04:41:41.522525 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8562 04:41:41.525397 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8563 04:41:41.525481
8564 04:41:41.525547
8565 04:41:41.525608 ==
8566 04:41:41.529108 Dram Type= 6, Freq= 0, CH_1, rank 1
8567 04:41:41.535512 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8568 04:41:41.535596 ==
8569 04:41:41.535663
8570 04:41:41.535724
8571 04:41:41.535782 TX Vref Scan disable
8572 04:41:41.539198 == TX Byte 0 ==
8573 04:41:41.542357 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8574 04:41:41.548668 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8575 04:41:41.548776 == TX Byte 1 ==
8576 04:41:41.552161 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8577 04:41:41.558563 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8578 04:41:41.558648 ==
8579 04:41:41.562080 Dram Type= 6, Freq= 0, CH_1, rank 1
8580 04:41:41.565254 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8581 04:41:41.565332 ==
8582 04:41:41.578596
8583 04:41:41.581583 TX Vref early break, caculate TX vref
8584 04:41:41.585329 TX Vref=16, minBit 3, minWin=22, winSum=375
8585 04:41:41.588397 TX Vref=18, minBit 5, minWin=22, winSum=380
8586 04:41:41.591677 TX Vref=20, minBit 3, minWin=23, winSum=395
8587 04:41:41.594963 TX Vref=22, minBit 1, minWin=24, winSum=402
8588 04:41:41.598737 TX Vref=24, minBit 1, minWin=24, winSum=409
8589 04:41:41.605307 TX Vref=26, minBit 0, minWin=24, winSum=414
8590 04:41:41.608649 TX Vref=28, minBit 0, minWin=25, winSum=416
8591 04:41:41.611577 TX Vref=30, minBit 0, minWin=24, winSum=416
8592 04:41:41.615494 TX Vref=32, minBit 0, minWin=23, winSum=405
8593 04:41:41.618609 TX Vref=34, minBit 0, minWin=23, winSum=396
8594 04:41:41.621697 TX Vref=36, minBit 0, minWin=21, winSum=389
8595 04:41:41.628068 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 28
8596 04:41:41.628150
8597 04:41:41.631984 Final TX Range 0 Vref 28
8598 04:41:41.632056
8599 04:41:41.632118 ==
8600 04:41:41.634638 Dram Type= 6, Freq= 0, CH_1, rank 1
8601 04:41:41.638050 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8602 04:41:41.638153 ==
8603 04:41:41.638246
8604 04:41:41.638337
8605 04:41:41.641430 TX Vref Scan disable
8606 04:41:41.648243 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8607 04:41:41.648325 == TX Byte 0 ==
8608 04:41:41.651758 u2DelayCellOfst[0]=14 cells (4 PI)
8609 04:41:41.654425 u2DelayCellOfst[1]=7 cells (2 PI)
8610 04:41:41.657726 u2DelayCellOfst[2]=0 cells (0 PI)
8611 04:41:41.661696 u2DelayCellOfst[3]=7 cells (2 PI)
8612 04:41:41.664994 u2DelayCellOfst[4]=7 cells (2 PI)
8613 04:41:41.667546 u2DelayCellOfst[5]=10 cells (3 PI)
8614 04:41:41.671094 u2DelayCellOfst[6]=14 cells (4 PI)
8615 04:41:41.674320 u2DelayCellOfst[7]=3 cells (1 PI)
8616 04:41:41.677610 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8617 04:41:41.681381 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8618 04:41:41.684246 == TX Byte 1 ==
8619 04:41:41.687290 u2DelayCellOfst[8]=0 cells (0 PI)
8620 04:41:41.691048 u2DelayCellOfst[9]=7 cells (2 PI)
8621 04:41:41.694287 u2DelayCellOfst[10]=14 cells (4 PI)
8622 04:41:41.694368 u2DelayCellOfst[11]=3 cells (1 PI)
8623 04:41:41.697510 u2DelayCellOfst[12]=18 cells (5 PI)
8624 04:41:41.700753 u2DelayCellOfst[13]=21 cells (6 PI)
8625 04:41:41.704129 u2DelayCellOfst[14]=21 cells (6 PI)
8626 04:41:41.707045 u2DelayCellOfst[15]=21 cells (6 PI)
8627 04:41:41.713747 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8628 04:41:41.717252 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8629 04:41:41.717330 DramC Write-DBI on
8630 04:41:41.717394 ==
8631 04:41:41.720191 Dram Type= 6, Freq= 0, CH_1, rank 1
8632 04:41:41.727469 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8633 04:41:41.727547 ==
8634 04:41:41.727610
8635 04:41:41.727669
8636 04:41:41.730645 TX Vref Scan disable
8637 04:41:41.730722 == TX Byte 0 ==
8638 04:41:41.737124 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8639 04:41:41.737202 == TX Byte 1 ==
8640 04:41:41.740520 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8641 04:41:41.743492 DramC Write-DBI off
8642 04:41:41.743568
8643 04:41:41.743635 [DATLAT]
8644 04:41:41.746630 Freq=1600, CH1 RK1
8645 04:41:41.746704
8646 04:41:41.746765 DATLAT Default: 0xe
8647 04:41:41.750030 0, 0xFFFF, sum = 0
8648 04:41:41.750108 1, 0xFFFF, sum = 0
8649 04:41:41.753535 2, 0xFFFF, sum = 0
8650 04:41:41.753610 3, 0xFFFF, sum = 0
8651 04:41:41.756644 4, 0xFFFF, sum = 0
8652 04:41:41.756754 5, 0xFFFF, sum = 0
8653 04:41:41.759961 6, 0xFFFF, sum = 0
8654 04:41:41.760034 7, 0xFFFF, sum = 0
8655 04:41:41.763538 8, 0xFFFF, sum = 0
8656 04:41:41.763613 9, 0xFFFF, sum = 0
8657 04:41:41.766678 10, 0xFFFF, sum = 0
8658 04:41:41.770440 11, 0xFFFF, sum = 0
8659 04:41:41.770519 12, 0x8F7F, sum = 0
8660 04:41:41.773462 13, 0x0, sum = 1
8661 04:41:41.773537 14, 0x0, sum = 2
8662 04:41:41.776448 15, 0x0, sum = 3
8663 04:41:41.776522 16, 0x0, sum = 4
8664 04:41:41.776585 best_step = 14
8665 04:41:41.776648
8666 04:41:41.779830 ==
8667 04:41:41.783515 Dram Type= 6, Freq= 0, CH_1, rank 1
8668 04:41:41.787040 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8669 04:41:41.787141 ==
8670 04:41:41.787238 RX Vref Scan: 0
8671 04:41:41.787314
8672 04:41:41.790427 RX Vref 0 -> 0, step: 1
8673 04:41:41.790525
8674 04:41:41.793180 RX Delay 3 -> 252, step: 4
8675 04:41:41.796497 iDelay=195, Bit 0, Center 130 (79 ~ 182) 104
8676 04:41:41.799641 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8677 04:41:41.806754 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8678 04:41:41.809886 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8679 04:41:41.813010 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8680 04:41:41.816422 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8681 04:41:41.819981 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8682 04:41:41.827361 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8683 04:41:41.830018 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8684 04:41:41.833384 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8685 04:41:41.835931 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8686 04:41:41.839694 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8687 04:41:41.846013 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8688 04:41:41.850034 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8689 04:41:41.852891 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8690 04:41:41.856034 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8691 04:41:41.856116 ==
8692 04:41:41.859401 Dram Type= 6, Freq= 0, CH_1, rank 1
8693 04:41:41.866141 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8694 04:41:41.866223 ==
8695 04:41:41.866288 DQS Delay:
8696 04:41:41.869539 DQS0 = 0, DQS1 = 0
8697 04:41:41.869621 DQM Delay:
8698 04:41:41.872993 DQM0 = 127, DQM1 = 123
8699 04:41:41.873074 DQ Delay:
8700 04:41:41.875963 DQ0 =130, DQ1 =124, DQ2 =116, DQ3 =122
8701 04:41:41.879325 DQ4 =124, DQ5 =138, DQ6 =136, DQ7 =126
8702 04:41:41.883317 DQ8 =106, DQ9 =112, DQ10 =124, DQ11 =114
8703 04:41:41.885947 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8704 04:41:41.886049
8705 04:41:41.886145
8706 04:41:41.886221
8707 04:41:41.889461 [DramC_TX_OE_Calibration] TA2
8708 04:41:41.892351 Original DQ_B0 (3 6) =30, OEN = 27
8709 04:41:41.895854 Original DQ_B1 (3 6) =30, OEN = 27
8710 04:41:41.899326 24, 0x0, End_B0=24 End_B1=24
8711 04:41:41.902511 25, 0x0, End_B0=25 End_B1=25
8712 04:41:41.902605 26, 0x0, End_B0=26 End_B1=26
8713 04:41:41.905449 27, 0x0, End_B0=27 End_B1=27
8714 04:41:41.908745 28, 0x0, End_B0=28 End_B1=28
8715 04:41:41.912380 29, 0x0, End_B0=29 End_B1=29
8716 04:41:41.915431 30, 0x0, End_B0=30 End_B1=30
8717 04:41:41.915512 31, 0x4141, End_B0=30 End_B1=30
8718 04:41:41.918857 Byte0 end_step=30 best_step=27
8719 04:41:41.922339 Byte1 end_step=30 best_step=27
8720 04:41:41.925240 Byte0 TX OE(2T, 0.5T) = (3, 3)
8721 04:41:41.928701 Byte1 TX OE(2T, 0.5T) = (3, 3)
8722 04:41:41.928789
8723 04:41:41.928877
8724 04:41:41.935383 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8725 04:41:41.938770 CH1 RK1: MR19=303, MR18=1F1F
8726 04:41:41.945265 CH1_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
8727 04:41:41.948532 [RxdqsGatingPostProcess] freq 1600
8728 04:41:41.955843 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8729 04:41:41.955938 Pre-setting of DQS Precalculation
8730 04:41:41.961491 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8731 04:41:41.968689 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8732 04:41:41.974775 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8733 04:41:41.974862
8734 04:41:41.974927
8735 04:41:41.978255 [Calibration Summary] 3200 Mbps
8736 04:41:41.981527 CH 0, Rank 0
8737 04:41:41.981611 SW Impedance : PASS
8738 04:41:41.985090 DUTY Scan : NO K
8739 04:41:41.988495 ZQ Calibration : PASS
8740 04:41:41.988579 Jitter Meter : NO K
8741 04:41:41.991438 CBT Training : PASS
8742 04:41:41.994954 Write leveling : PASS
8743 04:41:41.995038 RX DQS gating : PASS
8744 04:41:41.998725 RX DQ/DQS(RDDQC) : PASS
8745 04:41:42.001694 TX DQ/DQS : PASS
8746 04:41:42.001777 RX DATLAT : PASS
8747 04:41:42.004560 RX DQ/DQS(Engine): PASS
8748 04:41:42.008288 TX OE : PASS
8749 04:41:42.008410 All Pass.
8750 04:41:42.008505
8751 04:41:42.008609 CH 0, Rank 1
8752 04:41:42.011190 SW Impedance : PASS
8753 04:41:42.014355 DUTY Scan : NO K
8754 04:41:42.014456 ZQ Calibration : PASS
8755 04:41:42.018272 Jitter Meter : NO K
8756 04:41:42.020892 CBT Training : PASS
8757 04:41:42.020962 Write leveling : PASS
8758 04:41:42.025040 RX DQS gating : PASS
8759 04:41:42.025113 RX DQ/DQS(RDDQC) : PASS
8760 04:41:42.027837 TX DQ/DQS : PASS
8761 04:41:42.030757 RX DATLAT : PASS
8762 04:41:42.030838 RX DQ/DQS(Engine): PASS
8763 04:41:42.034694 TX OE : PASS
8764 04:41:42.034787 All Pass.
8765 04:41:42.034878
8766 04:41:42.037512 CH 1, Rank 0
8767 04:41:42.037590 SW Impedance : PASS
8768 04:41:42.041034 DUTY Scan : NO K
8769 04:41:42.044141 ZQ Calibration : PASS
8770 04:41:42.044267 Jitter Meter : NO K
8771 04:41:42.047783 CBT Training : PASS
8772 04:41:42.051078 Write leveling : PASS
8773 04:41:42.051199 RX DQS gating : PASS
8774 04:41:42.054317 RX DQ/DQS(RDDQC) : PASS
8775 04:41:42.057170 TX DQ/DQS : PASS
8776 04:41:42.057262 RX DATLAT : PASS
8777 04:41:42.060928 RX DQ/DQS(Engine): PASS
8778 04:41:42.064148 TX OE : PASS
8779 04:41:42.064237 All Pass.
8780 04:41:42.064320
8781 04:41:42.064398 CH 1, Rank 1
8782 04:41:42.067614 SW Impedance : PASS
8783 04:41:42.071289 DUTY Scan : NO K
8784 04:41:42.071440 ZQ Calibration : PASS
8785 04:41:42.073803 Jitter Meter : NO K
8786 04:41:42.077487 CBT Training : PASS
8787 04:41:42.077567 Write leveling : PASS
8788 04:41:42.080483 RX DQS gating : PASS
8789 04:41:42.083650 RX DQ/DQS(RDDQC) : PASS
8790 04:41:42.083736 TX DQ/DQS : PASS
8791 04:41:42.087649 RX DATLAT : PASS
8792 04:41:42.087732 RX DQ/DQS(Engine): PASS
8793 04:41:42.091302 TX OE : PASS
8794 04:41:42.091400 All Pass.
8795 04:41:42.091480
8796 04:41:42.093880 DramC Write-DBI on
8797 04:41:42.097222 PER_BANK_REFRESH: Hybrid Mode
8798 04:41:42.097329 TX_TRACKING: ON
8799 04:41:42.107073 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8800 04:41:42.114061 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8801 04:41:42.123932 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8802 04:41:42.126871 [FAST_K] Save calibration result to emmc
8803 04:41:42.129996 sync common calibartion params.
8804 04:41:42.130090 sync cbt_mode0:0, 1:0
8805 04:41:42.133110 dram_init: ddr_geometry: 0
8806 04:41:42.136840 dram_init: ddr_geometry: 0
8807 04:41:42.136916 dram_init: ddr_geometry: 0
8808 04:41:42.140184 0:dram_rank_size:80000000
8809 04:41:42.143095 1:dram_rank_size:80000000
8810 04:41:42.146273 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8811 04:41:42.149597 DFS_SHUFFLE_HW_MODE: ON
8812 04:41:42.152924 dramc_set_vcore_voltage set vcore to 725000
8813 04:41:42.156216 Read voltage for 1600, 0
8814 04:41:42.156326 Vio18 = 0
8815 04:41:42.159918 Vcore = 725000
8816 04:41:42.159997 Vdram = 0
8817 04:41:42.160062 Vddq = 0
8818 04:41:42.160121 Vmddr = 0
8819 04:41:42.163577 switch to 3200 Mbps bootup
8820 04:41:42.166185 [DramcRunTimeConfig]
8821 04:41:42.166264 PHYPLL
8822 04:41:42.170168 DPM_CONTROL_AFTERK: ON
8823 04:41:42.170283 PER_BANK_REFRESH: ON
8824 04:41:42.172808 REFRESH_OVERHEAD_REDUCTION: ON
8825 04:41:42.176646 CMD_PICG_NEW_MODE: OFF
8826 04:41:42.176750 XRTWTW_NEW_MODE: ON
8827 04:41:42.179719 XRTRTR_NEW_MODE: ON
8828 04:41:42.179799 TX_TRACKING: ON
8829 04:41:42.182599 RDSEL_TRACKING: OFF
8830 04:41:42.186152 DQS Precalculation for DVFS: ON
8831 04:41:42.186234 RX_TRACKING: OFF
8832 04:41:42.189488 HW_GATING DBG: ON
8833 04:41:42.189596 ZQCS_ENABLE_LP4: ON
8834 04:41:42.192608 RX_PICG_NEW_MODE: ON
8835 04:41:42.192682 TX_PICG_NEW_MODE: ON
8836 04:41:42.196100 ENABLE_RX_DCM_DPHY: ON
8837 04:41:42.199400 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8838 04:41:42.203282 DUMMY_READ_FOR_TRACKING: OFF
8839 04:41:42.203357 !!! SPM_CONTROL_AFTERK: OFF
8840 04:41:42.205867 !!! SPM could not control APHY
8841 04:41:42.209315 IMPEDANCE_TRACKING: ON
8842 04:41:42.209390 TEMP_SENSOR: ON
8843 04:41:42.212633 HW_SAVE_FOR_SR: OFF
8844 04:41:42.215678 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8845 04:41:42.219492 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8846 04:41:42.219567 Read ODT Tracking: ON
8847 04:41:42.223130 Refresh Rate DeBounce: ON
8848 04:41:42.226073 DFS_NO_QUEUE_FLUSH: ON
8849 04:41:42.229656 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8850 04:41:42.229746 ENABLE_DFS_RUNTIME_MRW: OFF
8851 04:41:42.232350 DDR_RESERVE_NEW_MODE: ON
8852 04:41:42.235532 MR_CBT_SWITCH_FREQ: ON
8853 04:41:42.235605 =========================
8854 04:41:42.255613 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8855 04:41:42.259176 dram_init: ddr_geometry: 0
8856 04:41:42.276990 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8857 04:41:42.281294 dram_init: dram init end (result: 0)
8858 04:41:42.286974 DRAM-K: Full calibration passed in 23396 msecs
8859 04:41:42.290878 MRC: failed to locate region type 0.
8860 04:41:42.291005 DRAM rank0 size:0x80000000,
8861 04:41:42.293950 DRAM rank1 size=0x80000000
8862 04:41:42.304180 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8863 04:41:42.310274 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8864 04:41:42.316960 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8865 04:41:42.323702 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8866 04:41:42.327226 DRAM rank0 size:0x80000000,
8867 04:41:42.330325 DRAM rank1 size=0x80000000
8868 04:41:42.330400 CBMEM:
8869 04:41:42.333439 IMD: root @ 0xfffff000 254 entries.
8870 04:41:42.336887 IMD: root @ 0xffffec00 62 entries.
8871 04:41:42.340251 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8872 04:41:42.343431 WARNING: RO_VPD is uninitialized or empty.
8873 04:41:42.350807 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8874 04:41:42.356788 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8875 04:41:42.369698 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8876 04:41:42.381186 BS: romstage times (exec / console): total (unknown) / 22934 ms
8877 04:41:42.381269
8878 04:41:42.381352
8879 04:41:42.391146 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8880 04:41:42.394631 ARM64: Exception handlers installed.
8881 04:41:42.397773 ARM64: Testing exception
8882 04:41:42.400740 ARM64: Done test exception
8883 04:41:42.400845 Enumerating buses...
8884 04:41:42.404254 Show all devs... Before device enumeration.
8885 04:41:42.407341 Root Device: enabled 1
8886 04:41:42.410413 CPU_CLUSTER: 0: enabled 1
8887 04:41:42.410550 CPU: 00: enabled 1
8888 04:41:42.413659 Compare with tree...
8889 04:41:42.413752 Root Device: enabled 1
8890 04:41:42.418376 CPU_CLUSTER: 0: enabled 1
8891 04:41:42.420421 CPU: 00: enabled 1
8892 04:41:42.420514 Root Device scanning...
8893 04:41:42.423724 scan_static_bus for Root Device
8894 04:41:42.426919 CPU_CLUSTER: 0 enabled
8895 04:41:42.430602 scan_static_bus for Root Device done
8896 04:41:42.433897 scan_bus: bus Root Device finished in 8 msecs
8897 04:41:42.433992 done
8898 04:41:42.440327 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8899 04:41:42.443533 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8900 04:41:42.450328 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8901 04:41:42.454118 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8902 04:41:42.457204 Allocating resources...
8903 04:41:42.460305 Reading resources...
8904 04:41:42.464040 Root Device read_resources bus 0 link: 0
8905 04:41:42.466596 DRAM rank0 size:0x80000000,
8906 04:41:42.466692 DRAM rank1 size=0x80000000
8907 04:41:42.470384 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8908 04:41:42.473632 CPU: 00 missing read_resources
8909 04:41:42.480086 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8910 04:41:42.483159 Root Device read_resources bus 0 link: 0 done
8911 04:41:42.483240 Done reading resources.
8912 04:41:42.489807 Show resources in subtree (Root Device)...After reading.
8913 04:41:42.493040 Root Device child on link 0 CPU_CLUSTER: 0
8914 04:41:42.496640 CPU_CLUSTER: 0 child on link 0 CPU: 00
8915 04:41:42.506286 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8916 04:41:42.506419 CPU: 00
8917 04:41:42.509915 Root Device assign_resources, bus 0 link: 0
8918 04:41:42.512740 CPU_CLUSTER: 0 missing set_resources
8919 04:41:42.519523 Root Device assign_resources, bus 0 link: 0 done
8920 04:41:42.519603 Done setting resources.
8921 04:41:42.526521 Show resources in subtree (Root Device)...After assigning values.
8922 04:41:42.530332 Root Device child on link 0 CPU_CLUSTER: 0
8923 04:41:42.532752 CPU_CLUSTER: 0 child on link 0 CPU: 00
8924 04:41:42.542829 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8925 04:41:42.542913 CPU: 00
8926 04:41:42.545921 Done allocating resources.
8927 04:41:42.552508 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8928 04:41:42.552591 Enabling resources...
8929 04:41:42.552656 done.
8930 04:41:42.559657 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8931 04:41:42.563359 Initializing devices...
8932 04:41:42.563461 Root Device init
8933 04:41:42.566076 init hardware done!
8934 04:41:42.566157 0x00000018: ctrlr->caps
8935 04:41:42.569049 52.000 MHz: ctrlr->f_max
8936 04:41:42.572352 0.400 MHz: ctrlr->f_min
8937 04:41:42.572443 0x40ff8080: ctrlr->voltages
8938 04:41:42.575623 sclk: 390625
8939 04:41:42.575704 Bus Width = 1
8940 04:41:42.575768 sclk: 390625
8941 04:41:42.579525 Bus Width = 1
8942 04:41:42.582138 Early init status = 3
8943 04:41:42.585780 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8944 04:41:42.589210 in-header: 03 fb 00 00 01 00 00 00
8945 04:41:42.592375 in-data: 01
8946 04:41:42.595743 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8947 04:41:42.600056 in-header: 03 fb 00 00 01 00 00 00
8948 04:41:42.603266 in-data: 01
8949 04:41:42.607071 [SSUSB] Setting up USB HOST controller...
8950 04:41:42.609584 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8951 04:41:42.613492 [SSUSB] phy power-on done.
8952 04:41:42.616579 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8953 04:41:42.623484 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8954 04:41:42.626351 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8955 04:41:42.633093 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8956 04:41:42.639795 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8957 04:41:42.646016 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8958 04:41:42.653129 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8959 04:41:42.659548 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8960 04:41:42.662807 SPM: binary array size = 0x9dc
8961 04:41:42.666438 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8962 04:41:42.673271 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8963 04:41:42.679382 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8964 04:41:42.685721 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8965 04:41:42.690068 configure_display: Starting display init
8966 04:41:42.723450 anx7625_power_on_init: Init interface.
8967 04:41:42.726405 anx7625_disable_pd_protocol: Disabled PD feature.
8968 04:41:42.729604 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8969 04:41:42.757774 anx7625_start_dp_work: Secure OCM version=00
8970 04:41:42.760915 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8971 04:41:42.775962 sp_tx_get_edid_block: EDID Block = 1
8972 04:41:42.878409 Extracted contents:
8973 04:41:42.881556 header: 00 ff ff ff ff ff ff 00
8974 04:41:42.884831 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8975 04:41:42.888064 version: 01 04
8976 04:41:42.891512 basic params: 95 1f 11 78 0a
8977 04:41:42.894832 chroma info: 76 90 94 55 54 90 27 21 50 54
8978 04:41:42.898051 established: 00 00 00
8979 04:41:42.905550 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8980 04:41:42.911077 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8981 04:41:42.914937 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8982 04:41:42.921426 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8983 04:41:42.927955 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8984 04:41:42.931250 extensions: 00
8985 04:41:42.931327 checksum: fb
8986 04:41:42.931389
8987 04:41:42.934314 Manufacturer: IVO Model 57d Serial Number 0
8988 04:41:42.937907 Made week 0 of 2020
8989 04:41:42.941409 EDID version: 1.4
8990 04:41:42.941484 Digital display
8991 04:41:42.944586 6 bits per primary color channel
8992 04:41:42.944659 DisplayPort interface
8993 04:41:42.947592 Maximum image size: 31 cm x 17 cm
8994 04:41:42.951396 Gamma: 220%
8995 04:41:42.951472 Check DPMS levels
8996 04:41:42.954491 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
8997 04:41:42.960899 First detailed timing is preferred timing
8998 04:41:42.960982 Established timings supported:
8999 04:41:42.963931 Standard timings supported:
9000 04:41:42.967631 Detailed timings
9001 04:41:42.970990 Hex of detail: 383680a07038204018303c0035ae10000019
9002 04:41:42.977827 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9003 04:41:42.980536 0780 0798 07c8 0820 hborder 0
9004 04:41:42.984303 0438 043b 0447 0458 vborder 0
9005 04:41:42.987380 -hsync -vsync
9006 04:41:42.987457 Did detailed timing
9007 04:41:42.993985 Hex of detail: 000000000000000000000000000000000000
9008 04:41:42.997281 Manufacturer-specified data, tag 0
9009 04:41:43.000385 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9010 04:41:43.003745 ASCII string: InfoVision
9011 04:41:43.007055 Hex of detail: 000000fe00523134304e574635205248200a
9012 04:41:43.011141 ASCII string: R140NWF5 RH
9013 04:41:43.011215 Checksum
9014 04:41:43.013879 Checksum: 0xfb (valid)
9015 04:41:43.017102 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9016 04:41:43.020098 DSI data_rate: 832800000 bps
9017 04:41:43.027317 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9018 04:41:43.030481 anx7625_parse_edid: pixelclock(138800).
9019 04:41:43.033795 hactive(1920), hsync(48), hfp(24), hbp(88)
9020 04:41:43.037026 vactive(1080), vsync(12), vfp(3), vbp(17)
9021 04:41:43.040184 anx7625_dsi_config: config dsi.
9022 04:41:43.047044 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9023 04:41:43.060442 anx7625_dsi_config: success to config DSI
9024 04:41:43.064668 anx7625_dp_start: MIPI phy setup OK.
9025 04:41:43.067339 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9026 04:41:43.070277 mtk_ddp_mode_set invalid vrefresh 60
9027 04:41:43.073673 main_disp_path_setup
9028 04:41:43.073753 ovl_layer_smi_id_en
9029 04:41:43.077021 ovl_layer_smi_id_en
9030 04:41:43.077101 ccorr_config
9031 04:41:43.077167 aal_config
9032 04:41:43.080381 gamma_config
9033 04:41:43.080459 postmask_config
9034 04:41:43.083513 dither_config
9035 04:41:43.086883 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9036 04:41:43.093963 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9037 04:41:43.096784 Root Device init finished in 530 msecs
9038 04:41:43.099947 CPU_CLUSTER: 0 init
9039 04:41:43.106418 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9040 04:41:43.113027 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9041 04:41:43.113153 APU_MBOX 0x190000b0 = 0x10001
9042 04:41:43.116500 APU_MBOX 0x190001b0 = 0x10001
9043 04:41:43.120079 APU_MBOX 0x190005b0 = 0x10001
9044 04:41:43.123453 APU_MBOX 0x190006b0 = 0x10001
9045 04:41:43.129817 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9046 04:41:43.139521 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9047 04:41:43.151839 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9048 04:41:43.158333 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9049 04:41:43.170456 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9050 04:41:43.179571 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9051 04:41:43.182964 CPU_CLUSTER: 0 init finished in 81 msecs
9052 04:41:43.186028 Devices initialized
9053 04:41:43.189246 Show all devs... After init.
9054 04:41:43.189319 Root Device: enabled 1
9055 04:41:43.192391 CPU_CLUSTER: 0: enabled 1
9056 04:41:43.195572 CPU: 00: enabled 1
9057 04:41:43.199382 BS: BS_DEV_INIT run times (exec / console): 208 / 428 ms
9058 04:41:43.202385 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9059 04:41:43.206001 ELOG: NV offset 0x57f000 size 0x1000
9060 04:41:43.211976 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9061 04:41:43.218684 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9062 04:41:43.222339 ELOG: Event(17) added with size 13 at 2024-02-04 04:41:45 UTC
9063 04:41:43.229136 out: cmd=0x121: 03 db 21 01 00 00 00 00
9064 04:41:43.232141 in-header: 03 2d 00 00 2c 00 00 00
9065 04:41:43.241970 in-data: 36 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9066 04:41:43.249116 ELOG: Event(A1) added with size 10 at 2024-02-04 04:41:45 UTC
9067 04:41:43.255617 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9068 04:41:43.261994 ELOG: Event(A0) added with size 9 at 2024-02-04 04:41:45 UTC
9069 04:41:43.264995 elog_add_boot_reason: Logged dev mode boot
9070 04:41:43.271959 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9071 04:41:43.272057 Finalize devices...
9072 04:41:43.275004 Devices finalized
9073 04:41:43.278248 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9074 04:41:43.282250 Writing coreboot table at 0xffe64000
9075 04:41:43.285369 0. 000000000010a000-0000000000113fff: RAMSTAGE
9076 04:41:43.291520 1. 0000000040000000-00000000400fffff: RAM
9077 04:41:43.294940 2. 0000000040100000-000000004032afff: RAMSTAGE
9078 04:41:43.298171 3. 000000004032b000-00000000545fffff: RAM
9079 04:41:43.301225 4. 0000000054600000-000000005465ffff: BL31
9080 04:41:43.304702 5. 0000000054660000-00000000ffe63fff: RAM
9081 04:41:43.311101 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9082 04:41:43.314566 7. 0000000100000000-000000013fffffff: RAM
9083 04:41:43.318077 Passing 5 GPIOs to payload:
9084 04:41:43.321362 NAME | PORT | POLARITY | VALUE
9085 04:41:43.327930 EC in RW | 0x000000aa | low | undefined
9086 04:41:43.331142 EC interrupt | 0x00000005 | low | undefined
9087 04:41:43.334671 TPM interrupt | 0x000000ab | high | undefined
9088 04:41:43.341182 SD card detect | 0x00000011 | high | undefined
9089 04:41:43.344912 speaker enable | 0x00000093 | high | undefined
9090 04:41:43.347551 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9091 04:41:43.351529 in-header: 03 ef 00 00 02 00 00 00
9092 04:41:43.354181 in-data: 0c 00
9093 04:41:43.357734 ADC[4]: Raw value=669327 ID=5
9094 04:41:43.357810 ADC[3]: Raw value=212549 ID=1
9095 04:41:43.361235 RAM Code: 0x51
9096 04:41:43.364445 ADC[6]: Raw value=74410 ID=0
9097 04:41:43.367620 ADC[5]: Raw value=211444 ID=1
9098 04:41:43.367702 SKU Code: 0x1
9099 04:41:43.374611 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d4c
9100 04:41:43.374713 coreboot table: 964 bytes.
9101 04:41:43.377385 IMD ROOT 0. 0xfffff000 0x00001000
9102 04:41:43.380727 IMD SMALL 1. 0xffffe000 0x00001000
9103 04:41:43.384307 RO MCACHE 2. 0xffffc000 0x00001104
9104 04:41:43.387319 CONSOLE 3. 0xfff7c000 0x00080000
9105 04:41:43.390588 FMAP 4. 0xfff7b000 0x00000452
9106 04:41:43.393814 TIME STAMP 5. 0xfff7a000 0x00000910
9107 04:41:43.397243 VBOOT WORK 6. 0xfff66000 0x00014000
9108 04:41:43.400457 RAMOOPS 7. 0xffe66000 0x00100000
9109 04:41:43.404366 COREBOOT 8. 0xffe64000 0x00002000
9110 04:41:43.407716 IMD small region:
9111 04:41:43.410820 IMD ROOT 0. 0xffffec00 0x00000400
9112 04:41:43.413841 VPD 1. 0xffffeb80 0x0000006c
9113 04:41:43.416876 MMC STATUS 2. 0xffffeb60 0x00000004
9114 04:41:43.420945 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9115 04:41:43.423847 Probing TPM: done!
9116 04:41:43.427541 Connected to device vid:did:rid of 1ae0:0028:00
9117 04:41:43.438542 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9118 04:41:43.442831 Initialized TPM device CR50 revision 0
9119 04:41:43.445961 Checking cr50 for pending updates
9120 04:41:43.449533 Reading cr50 TPM mode
9121 04:41:43.458007 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9122 04:41:43.464368 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9123 04:41:43.505076 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9124 04:41:43.507586 Checking segment from ROM address 0x40100000
9125 04:41:43.511737 Checking segment from ROM address 0x4010001c
9126 04:41:43.517910 Loading segment from ROM address 0x40100000
9127 04:41:43.518010 code (compression=0)
9128 04:41:43.524465 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9129 04:41:43.534546 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9130 04:41:43.534692 it's not compressed!
9131 04:41:43.541552 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9132 04:41:43.544589 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9133 04:41:43.564903 Loading segment from ROM address 0x4010001c
9134 04:41:43.564989 Entry Point 0x80000000
9135 04:41:43.568052 Loaded segments
9136 04:41:43.571212 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9137 04:41:43.578014 Jumping to boot code at 0x80000000(0xffe64000)
9138 04:41:43.584654 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9139 04:41:43.591828 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9140 04:41:43.599525 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9141 04:41:43.602824 Checking segment from ROM address 0x40100000
9142 04:41:43.606286 Checking segment from ROM address 0x4010001c
9143 04:41:43.612320 Loading segment from ROM address 0x40100000
9144 04:41:43.612399 code (compression=1)
9145 04:41:43.619171 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9146 04:41:43.629309 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9147 04:41:43.629397 using LZMA
9148 04:41:43.637458 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9149 04:41:43.644403 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9150 04:41:43.647779 Loading segment from ROM address 0x4010001c
9151 04:41:43.647896 Entry Point 0x54601000
9152 04:41:43.651523 Loaded segments
9153 04:41:43.654515 NOTICE: MT8192 bl31_setup
9154 04:41:43.661022 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9155 04:41:43.664427 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9156 04:41:43.667684 WARNING: region 0:
9157 04:41:43.671269 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9158 04:41:43.671351 WARNING: region 1:
9159 04:41:43.677556 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9160 04:41:43.681193 WARNING: region 2:
9161 04:41:43.685573 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9162 04:41:43.688345 WARNING: region 3:
9163 04:41:43.691069 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9164 04:41:43.694482 WARNING: region 4:
9165 04:41:43.700610 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9166 04:41:43.700726 WARNING: region 5:
9167 04:41:43.704168 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9168 04:41:43.708269 WARNING: region 6:
9169 04:41:43.710951 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9170 04:41:43.713990 WARNING: region 7:
9171 04:41:43.717285 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9172 04:41:43.724830 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9173 04:41:43.727101 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9174 04:41:43.730491 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9175 04:41:43.737883 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9176 04:41:43.740505 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9177 04:41:43.747502 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9178 04:41:43.750255 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9179 04:41:43.753975 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9180 04:41:43.760884 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9181 04:41:43.764162 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9182 04:41:43.767141 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9183 04:41:43.774493 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9184 04:41:43.777273 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9185 04:41:43.783701 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9186 04:41:43.787412 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9187 04:41:43.790438 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9188 04:41:43.797145 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9189 04:41:43.800300 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9190 04:41:43.803912 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9191 04:41:43.810246 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9192 04:41:43.813723 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9193 04:41:43.820463 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9194 04:41:43.823932 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9195 04:41:43.827030 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9196 04:41:43.833940 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9197 04:41:43.837155 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9198 04:41:43.843585 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9199 04:41:43.846993 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9200 04:41:43.850290 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9201 04:41:43.857138 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9202 04:41:43.860328 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9203 04:41:43.867321 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9204 04:41:43.870950 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9205 04:41:43.873668 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9206 04:41:43.877193 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9207 04:41:43.883593 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9208 04:41:43.887750 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9209 04:41:43.890558 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9210 04:41:43.893327 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9211 04:41:43.899886 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9212 04:41:43.903354 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9213 04:41:43.906555 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9214 04:41:43.909886 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9215 04:41:43.916998 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9216 04:41:43.920374 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9217 04:41:43.923693 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9218 04:41:43.926772 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9219 04:41:43.933529 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9220 04:41:43.936836 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9221 04:41:43.939998 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9222 04:41:43.946981 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9223 04:41:43.950307 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9224 04:41:43.956828 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9225 04:41:43.960004 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9226 04:41:43.967273 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9227 04:41:43.970122 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9228 04:41:43.973794 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9229 04:41:43.979945 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9230 04:41:43.983077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9231 04:41:43.990369 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9232 04:41:43.993738 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9233 04:41:43.999933 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9234 04:41:44.003746 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9235 04:41:44.009913 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9236 04:41:44.013086 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9237 04:41:44.016781 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9238 04:41:44.023577 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9239 04:41:44.026591 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9240 04:41:44.033223 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9241 04:41:44.036830 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9242 04:41:44.043133 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9243 04:41:44.046796 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9244 04:41:44.050177 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9245 04:41:44.056919 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9246 04:41:44.059967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9247 04:41:44.066467 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9248 04:41:44.070069 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9249 04:41:44.077070 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9250 04:41:44.079998 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9251 04:41:44.083401 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9252 04:41:44.090164 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9253 04:41:44.093683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9254 04:41:44.100828 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9255 04:41:44.103588 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9256 04:41:44.110324 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9257 04:41:44.113700 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9258 04:41:44.116906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9259 04:41:44.123295 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9260 04:41:44.126563 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9261 04:41:44.133242 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9262 04:41:44.136959 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9263 04:41:44.143446 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9264 04:41:44.146557 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9265 04:41:44.149793 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9266 04:41:44.156867 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9267 04:41:44.160232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9268 04:41:44.167021 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9269 04:41:44.170600 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9270 04:41:44.174001 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9271 04:41:44.176659 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9272 04:41:44.183611 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9273 04:41:44.186802 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9274 04:41:44.190172 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9275 04:41:44.196914 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9276 04:41:44.200092 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9277 04:41:44.206418 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9278 04:41:44.210544 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9279 04:41:44.213593 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9280 04:41:44.220474 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9281 04:41:44.223047 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9282 04:41:44.230262 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9283 04:41:44.233264 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9284 04:41:44.236319 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9285 04:41:44.243271 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9286 04:41:44.246530 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9287 04:41:44.252977 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9288 04:41:44.256407 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9289 04:41:44.260143 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9290 04:41:44.263456 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9291 04:41:44.270102 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9292 04:41:44.273481 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9293 04:41:44.276937 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9294 04:41:44.279981 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9295 04:41:44.286317 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9296 04:41:44.289774 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9297 04:41:44.293385 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9298 04:41:44.300236 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9299 04:41:44.303218 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9300 04:41:44.309715 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9301 04:41:44.313551 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9302 04:41:44.316523 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9303 04:41:44.323269 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9304 04:41:44.326461 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9305 04:41:44.333309 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9306 04:41:44.336426 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9307 04:41:44.339842 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9308 04:41:44.346281 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9309 04:41:44.349924 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9310 04:41:44.353371 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9311 04:41:44.359429 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9312 04:41:44.363685 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9313 04:41:44.369665 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9314 04:41:44.372683 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9315 04:41:44.376219 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9316 04:41:44.382981 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9317 04:41:44.386246 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9318 04:41:44.393327 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9319 04:41:44.396692 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9320 04:41:44.399441 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9321 04:41:44.406322 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9322 04:41:44.409430 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9323 04:41:44.416045 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9324 04:41:44.419537 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9325 04:41:44.423050 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9326 04:41:44.429743 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9327 04:41:44.433169 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9328 04:41:44.439770 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9329 04:41:44.442864 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9330 04:41:44.446475 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9331 04:41:44.452445 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9332 04:41:44.455808 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9333 04:41:44.459422 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9334 04:41:44.466111 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9335 04:41:44.469160 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9336 04:41:44.475822 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9337 04:41:44.479294 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9338 04:41:44.482419 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9339 04:41:44.489372 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9340 04:41:44.492824 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9341 04:41:44.498865 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9342 04:41:44.502678 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9343 04:41:44.506299 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9344 04:41:44.513136 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9345 04:41:44.515504 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9346 04:41:44.522615 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9347 04:41:44.525810 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9348 04:41:44.529175 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9349 04:41:44.535692 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9350 04:41:44.539124 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9351 04:41:44.542440 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9352 04:41:44.549150 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9353 04:41:44.552305 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9354 04:41:44.558718 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9355 04:41:44.562265 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9356 04:41:44.566068 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9357 04:41:44.572120 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9358 04:41:44.575324 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9359 04:41:44.582238 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9360 04:41:44.585179 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9361 04:41:44.592108 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9362 04:41:44.595055 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9363 04:41:44.598555 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9364 04:41:44.604996 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9365 04:41:44.608689 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9366 04:41:44.614871 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9367 04:41:44.619003 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9368 04:41:44.621861 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9369 04:41:44.628375 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9370 04:41:44.632111 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9371 04:41:44.638395 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9372 04:41:44.641745 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9373 04:41:44.648058 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9374 04:41:44.651538 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9375 04:41:44.654659 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9376 04:41:44.661081 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9377 04:41:44.664645 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9378 04:41:44.671417 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9379 04:41:44.674896 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9380 04:41:44.681995 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9381 04:41:44.684243 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9382 04:41:44.687872 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9383 04:41:44.694327 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9384 04:41:44.697461 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9385 04:41:44.704474 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9386 04:41:44.707873 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9387 04:41:44.710747 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9388 04:41:44.717657 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9389 04:41:44.720976 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9390 04:41:44.727653 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9391 04:41:44.731067 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9392 04:41:44.737121 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9393 04:41:44.740820 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9394 04:41:44.743920 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9395 04:41:44.750296 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9396 04:41:44.754028 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9397 04:41:44.761106 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9398 04:41:44.763748 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9399 04:41:44.770354 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9400 04:41:44.773896 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9401 04:41:44.776751 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9402 04:41:44.780106 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9403 04:41:44.787113 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9404 04:41:44.791214 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9405 04:41:44.793696 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9406 04:41:44.796973 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9407 04:41:44.803557 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9408 04:41:44.807054 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9409 04:41:44.813320 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9410 04:41:44.816763 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9411 04:41:44.820071 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9412 04:41:44.826472 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9413 04:41:44.830010 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9414 04:41:44.836467 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9415 04:41:44.840168 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9416 04:41:44.842930 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9417 04:41:44.849901 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9418 04:41:44.853334 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9419 04:41:44.856536 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9420 04:41:44.862699 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9421 04:41:44.866634 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9422 04:41:44.869274 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9423 04:41:44.876683 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9424 04:41:44.879738 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9425 04:41:44.886133 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9426 04:41:44.889587 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9427 04:41:44.892527 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9428 04:41:44.899483 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9429 04:41:44.902646 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9430 04:41:44.906148 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9431 04:41:44.912581 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9432 04:41:44.915634 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9433 04:41:44.922380 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9434 04:41:44.925883 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9435 04:41:44.929342 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9436 04:41:44.935677 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9437 04:41:44.939456 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9438 04:41:44.942220 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9439 04:41:44.949418 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9440 04:41:44.953073 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9441 04:41:44.956000 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9442 04:41:44.958972 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9443 04:41:44.965896 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9444 04:41:44.968849 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9445 04:41:44.972256 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9446 04:41:44.975705 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9447 04:41:44.982711 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9448 04:41:44.985661 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9449 04:41:44.988552 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9450 04:41:44.992200 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9451 04:41:44.998912 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9452 04:41:45.002146 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9453 04:41:45.005109 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9454 04:41:45.012060 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9455 04:41:45.015335 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9456 04:41:45.021764 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9457 04:41:45.025578 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9458 04:41:45.028052 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9459 04:41:45.035660 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9460 04:41:45.038827 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9461 04:41:45.044667 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9462 04:41:45.048271 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9463 04:41:45.051852 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9464 04:41:45.057962 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9465 04:41:45.061515 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9466 04:41:45.068314 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9467 04:41:45.071539 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9468 04:41:45.078010 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9469 04:41:45.081568 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9470 04:41:45.084683 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9471 04:41:45.091391 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9472 04:41:45.094943 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9473 04:41:45.101283 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9474 04:41:45.104680 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9475 04:41:45.107869 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9476 04:41:45.115232 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9477 04:41:45.117915 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9478 04:41:45.124300 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9479 04:41:45.128106 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9480 04:41:45.130963 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9481 04:41:45.137792 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9482 04:41:45.141798 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9483 04:41:45.147789 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9484 04:41:45.151184 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9485 04:41:45.154108 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9486 04:41:45.160887 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9487 04:41:45.164541 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9488 04:41:45.170969 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9489 04:41:45.174632 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9490 04:41:45.181033 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9491 04:41:45.184523 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9492 04:41:45.188054 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9493 04:41:45.194218 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9494 04:41:45.197857 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9495 04:41:45.204535 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9496 04:41:45.207654 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9497 04:41:45.210953 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9498 04:41:45.217526 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9499 04:41:45.220603 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9500 04:41:45.226870 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9501 04:41:45.230427 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9502 04:41:45.236965 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9503 04:41:45.240418 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9504 04:41:45.243262 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9505 04:41:45.250202 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9506 04:41:45.253476 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9507 04:41:45.260253 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9508 04:41:45.264107 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9509 04:41:45.266633 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9510 04:41:45.273695 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9511 04:41:45.277057 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9512 04:41:45.283819 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9513 04:41:45.286347 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9514 04:41:45.293349 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9515 04:41:45.297020 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9516 04:41:45.299823 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9517 04:41:45.306063 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9518 04:41:45.309922 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9519 04:41:45.316211 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9520 04:41:45.319808 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9521 04:41:45.323277 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9522 04:41:45.329650 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9523 04:41:45.333066 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9524 04:41:45.339624 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9525 04:41:45.343280 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9526 04:41:45.349176 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9527 04:41:45.352984 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9528 04:41:45.355971 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9529 04:41:45.362298 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9530 04:41:45.365783 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9531 04:41:45.372770 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9532 04:41:45.375884 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9533 04:41:45.382668 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9534 04:41:45.385781 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9535 04:41:45.389329 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9536 04:41:45.395473 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9537 04:41:45.399020 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9538 04:41:45.405691 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9539 04:41:45.409470 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9540 04:41:45.415236 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9541 04:41:45.418785 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9542 04:41:45.425194 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9543 04:41:45.428297 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9544 04:41:45.431921 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9545 04:41:45.438439 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9546 04:41:45.441897 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9547 04:41:45.448494 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9548 04:41:45.452197 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9549 04:41:45.458482 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9550 04:41:45.462437 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9551 04:41:45.468426 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9552 04:41:45.472076 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9553 04:41:45.474852 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9554 04:41:45.481487 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9555 04:41:45.485033 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9556 04:41:45.491675 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9557 04:41:45.494936 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9558 04:41:45.501420 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9559 04:41:45.504487 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9560 04:41:45.511380 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9561 04:41:45.514314 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9562 04:41:45.518021 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9563 04:41:45.524811 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9564 04:41:45.527606 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9565 04:41:45.534186 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9566 04:41:45.537786 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9567 04:41:45.544975 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9568 04:41:45.547392 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9569 04:41:45.553908 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9570 04:41:45.557169 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9571 04:41:45.560876 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9572 04:41:45.567165 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9573 04:41:45.570746 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9574 04:41:45.577797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9575 04:41:45.581903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9576 04:41:45.584075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9577 04:41:45.590562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9578 04:41:45.593631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9579 04:41:45.600635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9580 04:41:45.604136 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9581 04:41:45.610345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9582 04:41:45.613917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9583 04:41:45.620283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9584 04:41:45.623780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9585 04:41:45.630626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9586 04:41:45.633306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9587 04:41:45.640273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9588 04:41:45.643656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9589 04:41:45.649651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9590 04:41:45.653432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9591 04:41:45.659735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9592 04:41:45.663060 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9593 04:41:45.669424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9594 04:41:45.673260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9595 04:41:45.680040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9596 04:41:45.683012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9597 04:41:45.689823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9598 04:41:45.692844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9599 04:41:45.699525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9600 04:41:45.702497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9601 04:41:45.709069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9602 04:41:45.713042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9603 04:41:45.719496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9604 04:41:45.722985 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9605 04:41:45.729573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9606 04:41:45.732675 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9607 04:41:45.735976 INFO: [APUAPC] vio 0
9608 04:41:45.739227 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9609 04:41:45.746046 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9610 04:41:45.749198 INFO: [APUAPC] D0_APC_0: 0x400510
9611 04:41:45.752230 INFO: [APUAPC] D0_APC_1: 0x0
9612 04:41:45.752325 INFO: [APUAPC] D0_APC_2: 0x1540
9613 04:41:45.755454 INFO: [APUAPC] D0_APC_3: 0x0
9614 04:41:45.758890 INFO: [APUAPC] D1_APC_0: 0xffffffff
9615 04:41:45.762723 INFO: [APUAPC] D1_APC_1: 0xffffffff
9616 04:41:45.765511 INFO: [APUAPC] D1_APC_2: 0x3fffff
9617 04:41:45.768922 INFO: [APUAPC] D1_APC_3: 0x0
9618 04:41:45.773155 INFO: [APUAPC] D2_APC_0: 0xffffffff
9619 04:41:45.775710 INFO: [APUAPC] D2_APC_1: 0xffffffff
9620 04:41:45.778799 INFO: [APUAPC] D2_APC_2: 0x3fffff
9621 04:41:45.781926 INFO: [APUAPC] D2_APC_3: 0x0
9622 04:41:45.785531 INFO: [APUAPC] D3_APC_0: 0xffffffff
9623 04:41:45.789524 INFO: [APUAPC] D3_APC_1: 0xffffffff
9624 04:41:45.791868 INFO: [APUAPC] D3_APC_2: 0x3fffff
9625 04:41:45.795238 INFO: [APUAPC] D3_APC_3: 0x0
9626 04:41:45.798616 INFO: [APUAPC] D4_APC_0: 0xffffffff
9627 04:41:45.802476 INFO: [APUAPC] D4_APC_1: 0xffffffff
9628 04:41:45.805063 INFO: [APUAPC] D4_APC_2: 0x3fffff
9629 04:41:45.809518 INFO: [APUAPC] D4_APC_3: 0x0
9630 04:41:45.811725 INFO: [APUAPC] D5_APC_0: 0xffffffff
9631 04:41:45.815436 INFO: [APUAPC] D5_APC_1: 0xffffffff
9632 04:41:45.818551 INFO: [APUAPC] D5_APC_2: 0x3fffff
9633 04:41:45.821622 INFO: [APUAPC] D5_APC_3: 0x0
9634 04:41:45.824878 INFO: [APUAPC] D6_APC_0: 0xffffffff
9635 04:41:45.828491 INFO: [APUAPC] D6_APC_1: 0xffffffff
9636 04:41:45.832248 INFO: [APUAPC] D6_APC_2: 0x3fffff
9637 04:41:45.835089 INFO: [APUAPC] D6_APC_3: 0x0
9638 04:41:45.838713 INFO: [APUAPC] D7_APC_0: 0xffffffff
9639 04:41:45.841354 INFO: [APUAPC] D7_APC_1: 0xffffffff
9640 04:41:45.844793 INFO: [APUAPC] D7_APC_2: 0x3fffff
9641 04:41:45.848305 INFO: [APUAPC] D7_APC_3: 0x0
9642 04:41:45.851190 INFO: [APUAPC] D8_APC_0: 0xffffffff
9643 04:41:45.854477 INFO: [APUAPC] D8_APC_1: 0xffffffff
9644 04:41:45.858192 INFO: [APUAPC] D8_APC_2: 0x3fffff
9645 04:41:45.861554 INFO: [APUAPC] D8_APC_3: 0x0
9646 04:41:45.864975 INFO: [APUAPC] D9_APC_0: 0xffffffff
9647 04:41:45.868415 INFO: [APUAPC] D9_APC_1: 0xffffffff
9648 04:41:45.871557 INFO: [APUAPC] D9_APC_2: 0x3fffff
9649 04:41:45.874747 INFO: [APUAPC] D9_APC_3: 0x0
9650 04:41:45.877913 INFO: [APUAPC] D10_APC_0: 0xffffffff
9651 04:41:45.881598 INFO: [APUAPC] D10_APC_1: 0xffffffff
9652 04:41:45.884829 INFO: [APUAPC] D10_APC_2: 0x3fffff
9653 04:41:45.888222 INFO: [APUAPC] D10_APC_3: 0x0
9654 04:41:45.891306 INFO: [APUAPC] D11_APC_0: 0xffffffff
9655 04:41:45.894237 INFO: [APUAPC] D11_APC_1: 0xffffffff
9656 04:41:45.898024 INFO: [APUAPC] D11_APC_2: 0x3fffff
9657 04:41:45.901277 INFO: [APUAPC] D11_APC_3: 0x0
9658 04:41:45.904217 INFO: [APUAPC] D12_APC_0: 0xffffffff
9659 04:41:45.907560 INFO: [APUAPC] D12_APC_1: 0xffffffff
9660 04:41:45.910585 INFO: [APUAPC] D12_APC_2: 0x3fffff
9661 04:41:45.915027 INFO: [APUAPC] D12_APC_3: 0x0
9662 04:41:45.917681 INFO: [APUAPC] D13_APC_0: 0xffffffff
9663 04:41:45.920909 INFO: [APUAPC] D13_APC_1: 0xffffffff
9664 04:41:45.924950 INFO: [APUAPC] D13_APC_2: 0x3fffff
9665 04:41:45.927309 INFO: [APUAPC] D13_APC_3: 0x0
9666 04:41:45.930599 INFO: [APUAPC] D14_APC_0: 0xffffffff
9667 04:41:45.934277 INFO: [APUAPC] D14_APC_1: 0xffffffff
9668 04:41:45.937464 INFO: [APUAPC] D14_APC_2: 0x3fffff
9669 04:41:45.940638 INFO: [APUAPC] D14_APC_3: 0x0
9670 04:41:45.943764 INFO: [APUAPC] D15_APC_0: 0xffffffff
9671 04:41:45.947287 INFO: [APUAPC] D15_APC_1: 0xffffffff
9672 04:41:45.950495 INFO: [APUAPC] D15_APC_2: 0x3fffff
9673 04:41:45.954026 INFO: [APUAPC] D15_APC_3: 0x0
9674 04:41:45.957034 INFO: [APUAPC] APC_CON: 0x4
9675 04:41:45.960300 INFO: [NOCDAPC] D0_APC_0: 0x0
9676 04:41:45.964124 INFO: [NOCDAPC] D0_APC_1: 0x0
9677 04:41:45.966971 INFO: [NOCDAPC] D1_APC_0: 0x0
9678 04:41:45.967072 INFO: [NOCDAPC] D1_APC_1: 0xfff
9679 04:41:45.970223 INFO: [NOCDAPC] D2_APC_0: 0x0
9680 04:41:45.973879 INFO: [NOCDAPC] D2_APC_1: 0xfff
9681 04:41:45.976997 INFO: [NOCDAPC] D3_APC_0: 0x0
9682 04:41:45.979914 INFO: [NOCDAPC] D3_APC_1: 0xfff
9683 04:41:45.983446 INFO: [NOCDAPC] D4_APC_0: 0x0
9684 04:41:45.986730 INFO: [NOCDAPC] D4_APC_1: 0xfff
9685 04:41:45.989896 INFO: [NOCDAPC] D5_APC_0: 0x0
9686 04:41:45.993061 INFO: [NOCDAPC] D5_APC_1: 0xfff
9687 04:41:45.997033 INFO: [NOCDAPC] D6_APC_0: 0x0
9688 04:41:46.000372 INFO: [NOCDAPC] D6_APC_1: 0xfff
9689 04:41:46.004849 INFO: [NOCDAPC] D7_APC_0: 0x0
9690 04:41:46.004926 INFO: [NOCDAPC] D7_APC_1: 0xfff
9691 04:41:46.006579 INFO: [NOCDAPC] D8_APC_0: 0x0
9692 04:41:46.009971 INFO: [NOCDAPC] D8_APC_1: 0xfff
9693 04:41:46.014272 INFO: [NOCDAPC] D9_APC_0: 0x0
9694 04:41:46.016473 INFO: [NOCDAPC] D9_APC_1: 0xfff
9695 04:41:46.020643 INFO: [NOCDAPC] D10_APC_0: 0x0
9696 04:41:46.023515 INFO: [NOCDAPC] D10_APC_1: 0xfff
9697 04:41:46.027088 INFO: [NOCDAPC] D11_APC_0: 0x0
9698 04:41:46.029813 INFO: [NOCDAPC] D11_APC_1: 0xfff
9699 04:41:46.032986 INFO: [NOCDAPC] D12_APC_0: 0x0
9700 04:41:46.036940 INFO: [NOCDAPC] D12_APC_1: 0xfff
9701 04:41:46.039840 INFO: [NOCDAPC] D13_APC_0: 0x0
9702 04:41:46.043039 INFO: [NOCDAPC] D13_APC_1: 0xfff
9703 04:41:46.046421 INFO: [NOCDAPC] D14_APC_0: 0x0
9704 04:41:46.049565 INFO: [NOCDAPC] D14_APC_1: 0xfff
9705 04:41:46.049639 INFO: [NOCDAPC] D15_APC_0: 0x0
9706 04:41:46.052831 INFO: [NOCDAPC] D15_APC_1: 0xfff
9707 04:41:46.056599 INFO: [NOCDAPC] APC_CON: 0x4
9708 04:41:46.059828 INFO: [APUAPC] set_apusys_apc done
9709 04:41:46.062660 INFO: [DEVAPC] devapc_init done
9710 04:41:46.066566 INFO: GICv3 without legacy support detected.
9711 04:41:46.072685 INFO: ARM GICv3 driver initialized in EL3
9712 04:41:46.075775 INFO: Maximum SPI INTID supported: 639
9713 04:41:46.079356 INFO: BL31: Initializing runtime services
9714 04:41:46.086399 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9715 04:41:46.089088 INFO: SPM: enable CPC mode
9716 04:41:46.092665 INFO: mcdi ready for mcusys-off-idle and system suspend
9717 04:41:46.099187 INFO: BL31: Preparing for EL3 exit to normal world
9718 04:41:46.102559 INFO: Entry point address = 0x80000000
9719 04:41:46.102660 INFO: SPSR = 0x8
9720 04:41:46.109116
9721 04:41:46.109196
9722 04:41:46.109260
9723 04:41:46.112249 Starting depthcharge on Spherion...
9724 04:41:46.112350
9725 04:41:46.112445 Wipe memory regions:
9726 04:41:46.112532
9727 04:41:46.113223 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9728 04:41:46.113325 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9729 04:41:46.113404 Setting prompt string to ['asurada:']
9730 04:41:46.113481 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9731 04:41:46.115458 [0x00000040000000, 0x00000054600000)
9732 04:41:46.238061
9733 04:41:46.238197 [0x00000054660000, 0x00000080000000)
9734 04:41:46.498424
9735 04:41:46.498558 [0x000000821a7280, 0x000000ffe64000)
9736 04:41:47.243310
9737 04:41:47.243440 [0x00000100000000, 0x00000140000000)
9738 04:41:47.624145
9739 04:41:47.627354 Initializing XHCI USB controller at 0x11200000.
9740 04:41:48.665347
9741 04:41:48.668405 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9742 04:41:48.668867
9743 04:41:48.669196
9744 04:41:48.669516
9745 04:41:48.670259 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9747 04:41:48.771322 asurada: tftpboot 192.168.201.1 12699794/tftp-deploy-cfipo1j7/kernel/image.itb 12699794/tftp-deploy-cfipo1j7/kernel/cmdline
9748 04:41:48.771831 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9749 04:41:48.772244 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9750 04:41:48.776593 tftpboot 192.168.201.1 12699794/tftp-deploy-cfipo1j7/kernel/image.itp-deploy-cfipo1j7/kernel/cmdline
9751 04:41:48.777045
9752 04:41:48.777375 Waiting for link
9753 04:41:48.936991
9754 04:41:48.937121 R8152: Initializing
9755 04:41:48.937189
9756 04:41:48.940470 Version 9 (ocp_data = 6010)
9757 04:41:48.940581
9758 04:41:48.944466 R8152: Done initializing
9759 04:41:48.944565
9760 04:41:48.944658 Adding net device
9761 04:41:50.974358
9762 04:41:50.975142 done.
9763 04:41:50.975564
9764 04:41:50.975910 MAC: 00:e0:4c:68:03:bd
9765 04:41:50.976268
9766 04:41:50.977384 Sending DHCP discover... done.
9767 04:41:50.977829
9768 04:41:50.980331 Waiting for reply... done.
9769 04:41:50.980847
9770 04:41:50.983756 Sending DHCP request... done.
9771 04:41:50.984163
9772 04:41:50.986845 Waiting for reply... done.
9773 04:41:50.987254
9774 04:41:50.987577 My ip is 192.168.201.16
9775 04:41:50.987877
9776 04:41:50.990541 The DHCP server ip is 192.168.201.1
9777 04:41:50.991090
9778 04:41:50.996849 TFTP server IP predefined by user: 192.168.201.1
9779 04:41:50.997331
9780 04:41:51.003918 Bootfile predefined by user: 12699794/tftp-deploy-cfipo1j7/kernel/image.itb
9781 04:41:51.004569
9782 04:41:51.007335 Sending tftp read request... done.
9783 04:41:51.008113
9784 04:41:51.014211 Waiting for the transfer...
9785 04:41:51.014782
9786 04:41:51.276911 00000000 ################################################################
9787 04:41:51.277088
9788 04:41:51.528506 00080000 ################################################################
9789 04:41:51.528684
9790 04:41:51.780438 00100000 ################################################################
9791 04:41:51.780599
9792 04:41:52.029488 00180000 ################################################################
9793 04:41:52.029620
9794 04:41:52.282587 00200000 ################################################################
9795 04:41:52.282741
9796 04:41:52.535621 00280000 ################################################################
9797 04:41:52.535771
9798 04:41:52.788040 00300000 ################################################################
9799 04:41:52.788200
9800 04:41:53.041618 00380000 ################################################################
9801 04:41:53.041747
9802 04:41:53.292463 00400000 ################################################################
9803 04:41:53.292624
9804 04:41:53.540479 00480000 ################################################################
9805 04:41:53.540635
9806 04:41:53.790929 00500000 ################################################################
9807 04:41:53.791088
9808 04:41:54.044060 00580000 ################################################################
9809 04:41:54.044217
9810 04:41:54.296742 00600000 ################################################################
9811 04:41:54.296875
9812 04:41:54.548858 00680000 ################################################################
9813 04:41:54.549013
9814 04:41:54.798505 00700000 ################################################################
9815 04:41:54.798672
9816 04:41:55.049820 00780000 ################################################################
9817 04:41:55.049960
9818 04:41:55.306809 00800000 ################################################################
9819 04:41:55.306983
9820 04:41:55.560918 00880000 ################################################################
9821 04:41:55.561092
9822 04:41:55.811961 00900000 ################################################################
9823 04:41:55.812179
9824 04:41:56.065931 00980000 ################################################################
9825 04:41:56.066069
9826 04:41:56.321550 00a00000 ################################################################
9827 04:41:56.321717
9828 04:41:56.574298 00a80000 ################################################################
9829 04:41:56.574464
9830 04:41:56.826886 00b00000 ################################################################
9831 04:41:56.827053
9832 04:41:57.078189 00b80000 ################################################################
9833 04:41:57.078352
9834 04:41:57.334180 00c00000 ################################################################
9835 04:41:57.334362
9836 04:41:57.583946 00c80000 ################################################################
9837 04:41:57.584090
9838 04:41:57.837191 00d00000 ################################################################
9839 04:41:57.837328
9840 04:41:58.090653 00d80000 ################################################################
9841 04:41:58.090789
9842 04:41:58.343033 00e00000 ################################################################
9843 04:41:58.343216
9844 04:41:58.595332 00e80000 ################################################################
9845 04:41:58.595467
9846 04:41:58.845196 00f00000 ################################################################
9847 04:41:58.845330
9848 04:41:59.095865 00f80000 ################################################################
9849 04:41:59.095998
9850 04:41:59.347156 01000000 ################################################################
9851 04:41:59.347302
9852 04:41:59.598432 01080000 ################################################################
9853 04:41:59.598570
9854 04:41:59.851722 01100000 ################################################################
9855 04:41:59.851866
9856 04:42:00.105489 01180000 ################################################################
9857 04:42:00.105627
9858 04:42:00.355530 01200000 ################################################################
9859 04:42:00.355669
9860 04:42:00.604796 01280000 ################################################################
9861 04:42:00.604965
9862 04:42:00.855499 01300000 ################################################################
9863 04:42:00.855636
9864 04:42:01.107724 01380000 ################################################################
9865 04:42:01.107869
9866 04:42:01.371147 01400000 ################################################################
9867 04:42:01.371284
9868 04:42:01.624382 01480000 ################################################################
9869 04:42:01.624523
9870 04:42:01.883788 01500000 ################################################################
9871 04:42:01.883921
9872 04:42:02.133025 01580000 ################################################################
9873 04:42:02.133162
9874 04:42:02.384427 01600000 ################################################################
9875 04:42:02.384560
9876 04:42:02.634145 01680000 ################################################################
9877 04:42:02.634285
9878 04:42:02.886243 01700000 ################################################################
9879 04:42:02.886376
9880 04:42:03.138214 01780000 ################################################################
9881 04:42:03.138384
9882 04:42:03.389238 01800000 ################################################################
9883 04:42:03.389387
9884 04:42:03.640391 01880000 ################################################################
9885 04:42:03.640528
9886 04:42:03.892126 01900000 ################################################################
9887 04:42:03.892259
9888 04:42:04.146427 01980000 ################################################################
9889 04:42:04.146587
9890 04:42:04.396884 01a00000 ################################################################
9891 04:42:04.397019
9892 04:42:04.648897 01a80000 ################################################################
9893 04:42:04.649041
9894 04:42:04.900453 01b00000 ################################################################
9895 04:42:04.900595
9896 04:42:05.150568 01b80000 ################################################################
9897 04:42:05.150700
9898 04:42:05.400377 01c00000 ################################################################
9899 04:42:05.400511
9900 04:42:05.655032 01c80000 ################################################################
9901 04:42:05.655160
9902 04:42:05.909353 01d00000 ################################################################
9903 04:42:05.909498
9904 04:42:06.167459 01d80000 ################################################################
9905 04:42:06.167601
9906 04:42:06.420927 01e00000 ################################################################
9907 04:42:06.421071
9908 04:42:06.674140 01e80000 ################################################################
9909 04:42:06.674282
9910 04:42:06.927654 01f00000 ################################################################
9911 04:42:06.927793
9912 04:42:07.181520 01f80000 ################################################################
9913 04:42:07.181668
9914 04:42:07.430647 02000000 ################################################################
9915 04:42:07.430790
9916 04:42:07.684153 02080000 ################################################################
9917 04:42:07.684285
9918 04:42:07.940450 02100000 ################################################################
9919 04:42:07.940581
9920 04:42:08.194335 02180000 ################################################################
9921 04:42:08.194465
9922 04:42:08.447572 02200000 ################################################################
9923 04:42:08.447738
9924 04:42:08.703482 02280000 ################################################################
9925 04:42:08.703610
9926 04:42:08.957664 02300000 ################################################################
9927 04:42:08.957796
9928 04:42:09.210419 02380000 ################################################################
9929 04:42:09.210553
9930 04:42:09.464234 02400000 ################################################################
9931 04:42:09.464364
9932 04:42:09.717746 02480000 ################################################################
9933 04:42:09.717876
9934 04:42:09.972208 02500000 ################################################################
9935 04:42:09.972346
9936 04:42:10.224438 02580000 ################################################################
9937 04:42:10.224579
9938 04:42:10.474907 02600000 ################################################################
9939 04:42:10.475040
9940 04:42:10.729282 02680000 ################################################################
9941 04:42:10.729419
9942 04:42:10.985213 02700000 ################################################################
9943 04:42:10.985354
9944 04:42:11.247829 02780000 ################################################################
9945 04:42:11.247968
9946 04:42:11.501908 02800000 ################################################################
9947 04:42:11.502043
9948 04:42:11.755008 02880000 ################################################################
9949 04:42:11.755142
9950 04:42:12.008330 02900000 ################################################################
9951 04:42:12.008462
9952 04:42:12.263334 02980000 ################################################################
9953 04:42:12.263476
9954 04:42:12.515794 02a00000 ################################################################
9955 04:42:12.515928
9956 04:42:12.769880 02a80000 ################################################################
9957 04:42:12.770012
9958 04:42:13.023440 02b00000 ################################################################
9959 04:42:13.023570
9960 04:42:13.276478 02b80000 ################################################################
9961 04:42:13.276610
9962 04:42:13.529192 02c00000 ################################################################
9963 04:42:13.529329
9964 04:42:13.784164 02c80000 ################################################################
9965 04:42:13.784296
9966 04:42:14.042374 02d00000 ################################################################
9967 04:42:14.042540
9968 04:42:14.294652 02d80000 ################################################################
9969 04:42:14.294785
9970 04:42:14.548495 02e00000 ################################################################
9971 04:42:14.548657
9972 04:42:14.805787 02e80000 ################################################################
9973 04:42:14.805919
9974 04:42:15.062014 02f00000 ################################################################
9975 04:42:15.062147
9976 04:42:15.316661 02f80000 ################################################################
9977 04:42:15.316821
9978 04:42:15.571079 03000000 ################################################################
9979 04:42:15.571220
9980 04:42:15.822707 03080000 ################################################################
9981 04:42:15.822838
9982 04:42:16.077937 03100000 ################################################################
9983 04:42:16.078071
9984 04:42:16.331542 03180000 ################################################################
9985 04:42:16.331674
9986 04:42:16.585153 03200000 ################################################################
9987 04:42:16.585288
9988 04:42:16.837068 03280000 ################################################################
9989 04:42:16.837200
9990 04:42:17.095739 03300000 ################################################################
9991 04:42:17.095867
9992 04:42:17.348191 03380000 ################################################################
9993 04:42:17.348324
9994 04:42:17.603371 03400000 ################################################################
9995 04:42:17.603498
9996 04:42:17.854360 03480000 ################################################################
9997 04:42:17.854491
9998 04:42:18.108883 03500000 ################################################################
9999 04:42:18.109008
10000 04:42:18.367719 03580000 ################################################################
10001 04:42:18.367846
10002 04:42:18.627421 03600000 ################################################################
10003 04:42:18.627549
10004 04:42:18.885704 03680000 ################################################################
10005 04:42:18.885830
10006 04:42:19.140525 03700000 ################################################################
10007 04:42:19.140651
10008 04:42:19.396835 03780000 ################################################################
10009 04:42:19.396965
10010 04:42:19.653927 03800000 ################################################################
10011 04:42:19.654053
10012 04:42:19.842787 03880000 ################################################# done.
10013 04:42:19.842912
10014 04:42:19.845896 The bootfile was 59640334 bytes long.
10015 04:42:19.845979
10016 04:42:19.849741 Sending tftp read request... done.
10017 04:42:19.849823
10018 04:42:19.852696 Waiting for the transfer...
10019 04:42:19.852820
10020 04:42:19.852884 00000000 # done.
10021 04:42:19.852945
10022 04:42:19.863120 Command line loaded dynamically from TFTP file: 12699794/tftp-deploy-cfipo1j7/kernel/cmdline
10023 04:42:19.863200
10024 04:42:19.876270 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10025 04:42:19.876355
10026 04:42:19.876418 Loading FIT.
10027 04:42:19.876477
10028 04:42:19.879189 Image ramdisk-1 has 47542515 bytes.
10029 04:42:19.879268
10030 04:42:19.882788 Image fdt-1 has 47278 bytes.
10031 04:42:19.882867
10032 04:42:19.885963 Image kernel-1 has 12048508 bytes.
10033 04:42:19.886042
10034 04:42:19.895788 Compat preference: google,spherion-rev12-sku1 google,spherion-rev12 google,spherion-sku1 google,spherion
10035 04:42:19.895869
10036 04:42:19.912397 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
10037 04:42:19.912482
10038 04:42:19.915486 Choosing best match conf-1 for compat google,spherion.
10039 04:42:19.920653
10040 04:42:19.925301 Connected to device vid:did:rid of 1ae0:0028:00
10041 04:42:19.933108
10042 04:42:19.935906 tpm_get_response: command 0x17b, return code 0x0
10043 04:42:19.935987
10044 04:42:19.939162 ec_init: CrosEC protocol v3 supported (256, 248)
10045 04:42:19.943489
10046 04:42:19.946887 tpm_cleanup: add release locality here.
10047 04:42:19.946967
10048 04:42:19.947029 Shutting down all USB controllers.
10049 04:42:19.949948
10050 04:42:19.950027 Removing current net device
10051 04:42:19.950089
10052 04:42:19.956888 Exiting depthcharge with code 4 at timestamp: 62014835
10053 04:42:19.956968
10054 04:42:19.960274 LZMA decompressing kernel-1 to 0x821a6718
10055 04:42:19.960353
10056 04:42:19.963048 LZMA decompressing kernel-1 to 0x40000000
10057 04:42:21.461105
10058 04:42:21.461246 jumping to kernel
10059 04:42:21.461760 end: 2.2.4 bootloader-commands (duration 00:00:35) [common]
10060 04:42:21.461857 start: 2.2.5 auto-login-action (timeout 00:03:51) [common]
10061 04:42:21.461944 Setting prompt string to ['Linux version [0-9]']
10062 04:42:21.462042 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 04:42:21.462146 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10064 04:42:21.512376
10065 04:42:21.515741 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10066 04:42:21.519708 start: 2.2.5.1 login-action (timeout 00:03:51) [common]
10067 04:42:21.519800 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10068 04:42:21.519869 Setting prompt string to []
10069 04:42:21.519946 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10070 04:42:21.520016 Using line separator: #'\n'#
10071 04:42:21.520074 No login prompt set.
10072 04:42:21.520132 Parsing kernel messages
10073 04:42:21.520185 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10074 04:42:21.520286 [login-action] Waiting for messages, (timeout 00:03:51)
10075 04:42:21.538647 [ 0.000000] Linux version 6.1.75-cip14-rt8 (KernelCI@build-j97480-arm64-gcc-10-defconfig-arm64-chromebook-6n26j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024
10076 04:42:21.542039 [ 0.000000] random: crng init done
10077 04:42:21.548844 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10078 04:42:21.552962 [ 0.000000] efi: UEFI not found.
10079 04:42:21.558740 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10080 04:42:21.568816 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10081 04:42:21.575441 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10082 04:42:21.585467 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10083 04:42:21.591966 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10084 04:42:21.599163 [ 0.000000] printk: bootconsole [mtk8250] enabled
10085 04:42:21.604764 [ 0.000000] NUMA: No NUMA configuration found
10086 04:42:21.611436 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10087 04:42:21.614764 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10088 04:42:21.617884 [ 0.000000] Zone ranges:
10089 04:42:21.624616 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10090 04:42:21.628607 [ 0.000000] DMA32 empty
10091 04:42:21.634547 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10092 04:42:21.638055 [ 0.000000] Movable zone start for each node
10093 04:42:21.641355 [ 0.000000] Early memory node ranges
10094 04:42:21.647849 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10095 04:42:21.654533 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10096 04:42:21.661084 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10097 04:42:21.667636 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10098 04:42:21.674227 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10099 04:42:21.680587 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10100 04:42:21.711395 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10101 04:42:21.717789 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10102 04:42:21.724552 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10103 04:42:21.728664 [ 0.000000] psci: probing for conduit method from DT.
10104 04:42:21.734376 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10105 04:42:21.737621 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10106 04:42:21.744025 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10107 04:42:21.747783 [ 0.000000] psci: SMC Calling Convention v1.2
10108 04:42:21.754315 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10109 04:42:21.758024 [ 0.000000] Detected VIPT I-cache on CPU0
10110 04:42:21.764157 [ 0.000000] CPU features: detected: GIC system register CPU interface
10111 04:42:21.770984 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10112 04:42:21.777411 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10113 04:42:21.784602 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10114 04:42:21.793607 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10115 04:42:21.800619 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10116 04:42:21.804254 [ 0.000000] alternatives: applying boot alternatives
10117 04:42:21.810216 [ 0.000000] Fallback order for Node 0: 0
10118 04:42:21.816948 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10119 04:42:21.820099 [ 0.000000] Policy zone: Normal
10120 04:42:21.833639 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10121 04:42:21.843138 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10122 04:42:21.853995 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10123 04:42:21.863969 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10124 04:42:21.870857 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10125 04:42:21.873977 <6>[ 0.000000] software IO TLB: area num 8.
10126 04:42:21.929978 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10127 04:42:22.009979 <6>[ 0.000000] Memory: 3806352K/4191232K available (18048K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 616K bss, 352112K reserved, 32768K cma-reserved)
10128 04:42:22.017122 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10129 04:42:22.023689 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10130 04:42:22.026473 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10131 04:42:22.033156 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10132 04:42:22.040223 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10133 04:42:22.043378 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10134 04:42:22.052766 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10135 04:42:22.059606 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10136 04:42:22.066400 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10137 04:42:22.073484 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10138 04:42:22.075839 <6>[ 0.000000] GICv3: 608 SPIs implemented
10139 04:42:22.079596 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10140 04:42:22.086082 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10141 04:42:22.089443 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10142 04:42:22.096636 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10143 04:42:22.109166 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10144 04:42:22.122239 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10145 04:42:22.128559 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10146 04:42:22.136596 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10147 04:42:22.149946 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10148 04:42:22.156340 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10149 04:42:22.163360 <6>[ 0.009179] Console: colour dummy device 80x25
10150 04:42:22.172889 <6>[ 0.013899] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10151 04:42:22.179595 <6>[ 0.024341] pid_max: default: 32768 minimum: 301
10152 04:42:22.182662 <6>[ 0.029211] LSM: Security Framework initializing
10153 04:42:22.189661 <6>[ 0.034124] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10154 04:42:22.199474 <6>[ 0.041776] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10155 04:42:22.206460 <6>[ 0.050944] cblist_init_generic: Setting adjustable number of callback queues.
10156 04:42:22.213124 <6>[ 0.058384] cblist_init_generic: Setting shift to 3 and lim to 1.
10157 04:42:22.222381 <6>[ 0.064761] cblist_init_generic: Setting adjustable number of callback queues.
10158 04:42:22.226037 <6>[ 0.072235] cblist_init_generic: Setting shift to 3 and lim to 1.
10159 04:42:22.233111 <6>[ 0.078709] rcu: Hierarchical SRCU implementation.
10160 04:42:22.239814 <6>[ 0.078711] rcu: Max phase no-delay instances is 1000.
10161 04:42:22.245742 <6>[ 0.078735] printk: bootconsole [mtk8250] printing thread started
10162 04:42:22.252459 <6>[ 0.097054] EFI services will not be available.
10163 04:42:22.255964 <6>[ 0.097254] smp: Bringing up secondary CPUs ...
10164 04:42:22.258888 <6>[ 0.097563] Detected VIPT I-cache on CPU1
10165 04:42:22.268728 <6>[ 0.097627] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10166 04:42:22.275487 <6>[ 0.097658] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10167 04:42:22.285276 <6>[ 0.125545] Detected VIPT I-cache on CPU2
10168 04:42:22.290653 <6>[ 0.125591] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10169 04:42:22.297413 <6>[ 0.125606] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10170 04:42:22.303905 <6>[ 0.125859] Detected VIPT I-cache on CPU3
10171 04:42:22.310280 <6>[ 0.125904] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10172 04:42:22.317435 <6>[ 0.125918] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10173 04:42:22.320500 <6>[ 0.126226] CPU features: detected: Spectre-v4
10174 04:42:22.326761 <6>[ 0.126233] CPU features: detected: Spectre-BHB
10175 04:42:22.330001 <6>[ 0.126238] Detected PIPT I-cache on CPU4
10176 04:42:22.336430 <6>[ 0.126296] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10177 04:42:22.343700 <6>[ 0.126313] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10178 04:42:22.350137 <6>[ 0.126601] Detected PIPT I-cache on CPU5
10179 04:42:22.356308 <6>[ 0.126661] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10180 04:42:22.362841 <6>[ 0.126678] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10181 04:42:22.366480 <6>[ 0.126952] Detected PIPT I-cache on CPU6
10182 04:42:22.376109 <6>[ 0.127012] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10183 04:42:22.382965 <6>[ 0.127028] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10184 04:42:22.386568 <6>[ 0.127321] Detected PIPT I-cache on CPU7
10185 04:42:22.393195 <6>[ 0.127385] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10186 04:42:22.399326 <6>[ 0.127401] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10187 04:42:22.405728 <6>[ 0.127447] smp: Brought up 1 node, 8 CPUs
10188 04:42:22.409193 <6>[ 0.127452] SMP: Total of 8 processors activated.
10189 04:42:22.415467 <6>[ 0.127455] CPU features: detected: 32-bit EL0 Support
10190 04:42:22.422553 <6>[ 0.127457] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10191 04:42:22.429347 <6>[ 0.127460] CPU features: detected: Common not Private translations
10192 04:42:22.435296 <6>[ 0.127461] CPU features: detected: CRC32 instructions
10193 04:42:22.441964 <6>[ 0.127464] CPU features: detected: RCpc load-acquire (LDAPR)
10194 04:42:22.448885 <6>[ 0.127465] CPU features: detected: LSE atomic instructions
10195 04:42:22.452108 <6>[ 0.127467] CPU features: detected: Privileged Access Never
10196 04:42:22.458686 <6>[ 0.127468] CPU features: detected: RAS Extension Support
10197 04:42:22.464583 <6>[ 0.127471] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10198 04:42:22.471714 <6>[ 0.127537] CPU: All CPU(s) started at EL2
10199 04:42:22.474845 <6>[ 0.127539] alternatives: applying system-wide alternatives
10200 04:42:22.478220 <6>[ 0.139866] devtmpfs: initialized
10201 04:42:22.487897 <6>[ 0.145291] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10202 04:42:22.511436 �@Registered PF_INET protocol family
10203 04:42:22.521441 <6>[ 0.227212] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10204 04:42:22.527612 <6>[ 0.229634] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10205 04:42:22.537881 <6>[ 0.229676] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10206 04:42:22.544469 <6>[ 0.229688] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10207 04:42:22.554102 <6>[ 0.229962] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10208 04:42:22.561224 <6>[ 0.231012] TCP: Hash tables configured (established 32768 bind 32768)
10209 04:42:22.568119 <6>[ 0.231120] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10210 04:42:22.574497 <6>[ 0.231219] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10211 04:42:22.581261 <6>[ 0.231388] NET: Registered PF_UNIX/PF_LOCAL protocol family
10212 04:42:22.587615 <6>[ 0.231569] RPC: Registered named UNIX socket transport module.
10213 04:42:22.590991 <6>[ 0.231572] RPC: Registered udp transport module.
10214 04:42:22.597528 <6>[ 0.231573] RPC: Registered tcp transport module.
10215 04:42:22.604375 <6>[ 0.231575] RPC: Registered tcp NFSv4.1 backchannel transport module.
10216 04:42:22.610438 <6>[ 0.454492] pr<intk: console [ttyS0] printing thread started
10217 04:42:22.613784 6<6>[ 0.454519] printk: console [ttyS0] enabled
10218 04:42:22.616976 >[ 0.231580] PCI: CLS 0 bytes, default 64
10219 04:42:22.626188 <6>[ 0.454522] printk: bootconsole [mtk8250] disabled
10220 04:42:22.632438 <6>[ 0.468951] printk: bootconsole [mtk8250] printing thread stopped
10221 04:42:22.635742 <6>[ 0.470335] SuperH (H)SCI(F) driver initialized
10222 04:42:22.642843 <6>[ 0.470824] msm_serial: driver initialized
10223 04:42:22.649462 <6>[ 0.475468] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10224 04:42:22.658711 <6>[ 0.475499] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10225 04:42:22.665681 <6>[ 0.475529] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10226 04:42:22.675308 <6>[ 0.475558] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10227 04:42:22.687126 <6>[ 0.475579] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10228 04:42:22.696659 <6>[ 0.475606] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10229 04:42:22.701783 <6>[ 0.475634] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10230 04:42:22.714134 <6>[ 0.475767] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10231 04:42:22.727037 <6>[ 0.475796] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10232 04:42:22.727626 <6>[ 0.492017] loop: module loaded
10233 04:42:22.730639 <6>[ 0.494590] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10234 04:42:22.735989 <4>[ 0.518620] mtk-pmic-keys: Failed to locate of_node [id: -1]
10235 04:42:22.740235 <6>[ 0.519402] megasas: 07.719.03.00-rc1
10236 04:42:22.744068 <6>[ 0.528309] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10237 04:42:22.751917 <6>[ 0.535502] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10238 04:42:22.755131 <6>[ 0.547579] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10239 04:42:22.768075 <6>[ 0.601148] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10240 04:42:24.401646 <6>[ 2.244537] Freeing initrd memory: 46424K
10241 04:42:24.408384 <6>[ 2.250718] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10242 04:42:24.411569 <6>[ 2.255301] tun: Universal TUN/TAP device driver, 1.6
10243 04:42:24.415418 <6>[ 2.256058] thunder_xcv, ver 1.0
10244 04:42:24.418232 <6>[ 2.256075] thunder_bgx, ver 1.0
10245 04:42:24.421546 <6>[ 2.256089] nicpf, ver 1.0
10246 04:42:24.428138 <6>[ 2.257140] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10247 04:42:24.435337 <6>[ 2.257143] hns3: Copyright (c) 2017 Huawei Corporation.
10248 04:42:24.438281 <6>[ 2.257166] hclge is initializing
10249 04:42:24.445023 <6>[ 2.257179] e1000: Intel(R) PRO/1000 Network Driver
10250 04:42:24.452556 <6>[ 2.257181] e1000: Copyright (c) 1999-2006 Intel Corporation.
10251 04:42:24.455717 <6>[ 2.257197] e1000e: Intel(R) PRO/1000 Network Driver
10252 04:42:24.462429 <6>[ 2.257199] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10253 04:42:24.466313 <6>[ 2.257217] igb: Intel(R) Gigabit Ethernet Network Driver
10254 04:42:24.472345 <6>[ 2.257219] igb: Copyright (c) 2007-2014 Intel Corporation.
10255 04:42:24.479894 <6>[ 2.257233] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10256 04:42:24.485741 <6>[ 2.257235] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10257 04:42:24.489094 <6>[ 2.257522] sky2: driver version 1.30
10258 04:42:24.496108 <6>[ 2.258602] VFIO - User Level meta-driver version: 0.3
10259 04:42:24.502584 <6>[ 2.261450] usbcore: registered new interface driver usb-storage
10260 04:42:24.509763 <6>[ 2.261628] usbcore: registered new device driver onboard-usb-hub
10261 04:42:24.512117 <6>[ 2.264383] mt6397-rtc mt6359-rtc: registered as rtc0
10262 04:42:24.522353 <6>[ 2.264536] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-04T04:42:27 UTC (1707021747)
10263 04:42:24.525967 <6>[ 2.265146] i2c_dev: i2c /dev entries driver
10264 04:42:24.535896 <6>[ 2.272242] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10265 04:42:24.538580 <6>[ 2.288209] cpu cpu0: EM: created perf domain
10266 04:42:24.541820 <6>[ 2.288497] cpu cpu4: EM: created perf domain
10267 04:42:24.549363 <6>[ 2.290666] sdhci: Secure Digital Host Controller Interface driver
10268 04:42:24.555460 <6>[ 2.290667] sdhci: Copyright(c) Pierre Ossman
10269 04:42:24.562173 <6>[ 2.290982] Synopsys Designware Multimedia Card Interface Driver
10270 04:42:24.566486 <6>[ 2.291324] sdhci-pltfm: SDHCI platform and OF driver helper
10271 04:42:24.571844 <6>[ 2.295635] ledtrig-cpu: registered to indicate activity on CPUs
10272 04:42:24.579016 <6>[ 2.296200] mmc0: CQHCI version 5.10
10273 04:42:24.585196 <6>[ 2.296276] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10274 04:42:24.588209 <6>[ 2.296526] usbcore: registered new interface driver usbhid
10275 04:42:24.594956 <6>[ 2.296527] usbhid: USB HID core driver
10276 04:42:24.601600 <6>[ 2.296655] spi_master spi0: will run message pump with realtime priority
10277 04:42:24.614905 <6>[ 2.323482] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10278 04:42:24.627586 <6>[ 2.326208] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10279 04:42:24.631003 <6>[ 2.327210] cros-ec-spi spi0.0: Chrome EC device registered
10280 04:42:24.640984 <6>[ 2.338919] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10281 04:42:24.647472 <6>[ 2.339792] NET: Registered PF_PACKET protocol family
10282 04:42:24.650779 <6>[ 2.339860] 9pnet: Installing 9P2000 support
10283 04:42:24.657627 <5>[ 2.339891] Key type dns_resolver registered
10284 04:42:24.661015 <6>[ 2.340392] registered taskstats version 1
10285 04:42:24.664282 <5>[ 2.340407] Loading compiled-in X.509 certificates
10286 04:42:24.677558 <4>[ 2.356293] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10287 04:42:24.687348 <4>[ 2.356433] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10288 04:42:24.694093 <3>[ 2.356442] debugfs: File 'uA_load' in directory '/' already present!
10289 04:42:24.700245 <3>[ 2.356449] debugfs: File 'min_uV' in directory '/' already present!
10290 04:42:24.707036 <3>[ 2.356452] debugfs: File 'max_uV' in directory '/' already present!
10291 04:42:24.714279 <3>[ 2.356455] debugfs: File 'constraint_flags' in directory '/' already present!
10292 04:42:24.723566 <3>[ 2.358282] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10293 04:42:24.726668 <6>[ 2.365190] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10294 04:42:24.733857 <6>[ 2.365766] xhci-mtk 11200000.usb: xHCI Host Controller
10295 04:42:24.740539 <6>[ 2.365785] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10296 04:42:24.749942 <6>[ 2.366003] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10297 04:42:24.757140 <6>[ 2.366056] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10298 04:42:24.763645 <6>[ 2.366161] xhci-mtk 11200000.usb: xHCI Host Controller
10299 04:42:24.769906 <6>[ 2.366168] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10300 04:42:24.776498 <6>[ 2.366176] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10301 04:42:24.782947 <6>[ 2.366764] hub 1-0:1.0: USB hub found
10302 04:42:24.786523 <6>[ 2.366790] hub 1-0:1.0: 1 port detected
10303 04:42:24.793460 <6>[ 2.367028] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10304 04:42:24.799976 <6>[ 2.367322] hub 2-0:1.0: USB hub found
10305 04:42:24.802547 <6>[ 2.367343] hub 2-0:1.0: 1 port detected
10306 04:42:24.806492 <6>[ 2.370557] mtk-msdc 11f70000.mmc: Got CD GPIO
10307 04:42:24.816564 <6>[ 2.385437] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10308 04:42:24.822409 <6>[ 2.385448] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10309 04:42:24.826002 <6>[ 2.385861] mmc0: Command Queue Engine enabled
10310 04:42:24.832558 <6>[ 2.385870] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10311 04:42:24.842714 <4>[ 2.386045] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10312 04:42:24.848987 <6>[ 2.386420] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10313 04:42:24.855434 <6>[ 2.386602] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10314 04:42:24.861937 <6>[ 2.386607] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10315 04:42:24.872083 <6>[ 2.386793] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10316 04:42:24.878488 <6>[ 2.386801] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10317 04:42:24.888996 <6>[ 2.386802] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10318 04:42:24.895257 <6>[ 2.386806] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10319 04:42:24.904879 <6>[ 2.388536] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10320 04:42:24.911725 <6>[ 2.388553] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10321 04:42:24.921970 <6>[ 2.388556] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10322 04:42:24.927921 <6>[ 2.388560] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10323 04:42:24.938185 <6>[ 2.388563] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10324 04:42:24.944615 <6>[ 2.388566] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10325 04:42:24.954820 <6>[ 2.388570] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10326 04:42:24.964304 <6>[ 2.388573] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10327 04:42:24.971279 <6>[ 2.388576] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10328 04:42:24.980941 <6>[ 2.388579] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10329 04:42:24.987640 <6>[ 2.388583] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10330 04:42:24.998010 <6>[ 2.388586] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10331 04:42:25.004281 <6>[ 2.388591] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10332 04:42:25.014016 <6>[ 2.388594] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10333 04:42:25.020634 <6>[ 2.388600] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10334 04:42:25.027357 <6>[ 2.389068] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10335 04:42:25.034530 <6>[ 2.389725] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10336 04:42:25.040196 <6>[ 2.389958] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10337 04:42:25.046848 <6>[ 2.390178] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10338 04:42:25.053578 <6>[ 2.390401] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10339 04:42:25.063532 <6>[ 2.390546] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10340 04:42:25.073777 <6>[ 2.390555] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10341 04:42:25.080104 <6>[ 2.390557] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10342 04:42:25.089953 <6>[ 2.390560] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10343 04:42:25.100213 <6>[ 2.390563] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10344 04:42:25.109880 <6>[ 2.390567] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10345 04:42:25.119567 <6>[ 2.390569] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10346 04:42:25.129911 <6>[ 2.390572] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10347 04:42:25.136896 <6>[ 2.390574] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10348 04:42:25.149700 <6>[ 2.390577] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10349 04:42:25.159573 <6>[ 2.390581] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10350 04:42:25.162966 <6>[ 2.390657] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10351 04:42:25.172463 <6>[ 2.391488] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10352 04:42:25.175837 <6>[ 2.392485] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10353 04:42:25.182611 <6>[ 2.393322] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10354 04:42:25.189377 <6>[ 2.393830] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10355 04:42:25.195539 <6>[ 2.792293] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10356 04:42:25.199334 <6>[ 2.945178] hub 1-1:1.0: USB hub found
10357 04:42:25.205437 <6>[ 2.945576] hub 1-1:1.0: 4 ports detected
10358 04:42:25.208932 <6>[ 2.948744] hub 1-1:1.0: USB hub found
10359 04:42:25.213151 <6>[ 2.949058] hub 1-1:1.0: 4 ports detected
10360 04:42:25.229031 <6>[ 3.068530] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10361 04:42:25.249555 <6>[ 3.094942] hub 2-1:1.0: USB hub found
10362 04:42:25.253626 <6>[ 3.095438] hub 2-1:1.0: 3 ports detected
10363 04:42:25.256346 <6>[ 3.098695] hub 2-1:1.0: USB hub found
10364 04:42:25.259723 <6>[ 3.099103] hub 2-1:1.0: 3 ports detected
10365 04:42:25.425079 <6>[ 3.264440] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10366 04:42:25.545710 <6>[ 3.391623] hub 1-1.4:1.0: USB hub found
10367 04:42:25.549243 <6>[ 3.391960] hub 1-1.4:1.0: 2 ports detected
10368 04:42:25.552783 <6>[ 3.394476] hub 1-1.4:1.0: USB hub found
10369 04:42:25.559228 <6>[ 3.394802] hub 1-1.4:1.0: 2 ports detected
10370 04:42:25.629080 <6>[ 3.468499] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10371 04:42:25.841460 <6>[ 3.680410] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10372 04:42:26.024990 <6>[ 3.864407] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10373 04:42:36.841855 <6>[ 14.689408] ALSA device list:
10374 04:42:36.848136 <6>[ 14.689429] No soundcards found.
10375 04:42:36.851307 <6>[ 14.693685] Freeing unused kernel memory: 8448K
10376 04:42:36.854681 <6>[ 14.693836] Run /init as init process
10377 04:42:36.888820 <6>[ 14.735342] NET: Registered PF_INET6 protocol family
10378 04:42:36.891782 <6>[ 14.736540] Segment Routing with IPv6
10379 04:42:36.898237 <6>[ 14.736554] In-situ OAM (IOAM) with IPv6
10380 04:42:36.908897
10381 04:42:36.931770 Welcome to [1mD<30>[ 14.759162] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10382 04:42:36.938480 <30>[ 14.759685] systemd[1]: Detected architecture arm64.
10383 04:42:36.941656 ebian GNU/Linux 11 (bullseye)[0m!
10384 04:42:36.941735
10385 04:42:36.960206 <30>[ 14.804612] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10386 04:42:37.072310 <30>[ 14.915143] systemd[1]: Queued start job for default target Graphical Interface.
10387 04:42:37.085394 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.929198] systemd[1]: Created slice system-getty.slice.
10388 04:42:37.088473 m-getty.slice[0m.
10389 04:42:37.112460 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.952959] systemd[1]: Created slice system-modprobe.slice.
10390 04:42:37.112950 m-modprobe.slice[0m.
10391 04:42:37.136189 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.976922] systemd[1]: Created slice system-serial\x2dgetty.slice.
10392 04:42:37.139199 m-serial\x2dgetty.slice[0m.
10393 04:42:37.158456 [[0;32m OK [0m] Created slic<30>[ 15.002136] systemd[1]: Created slice User and Session Slice.
10394 04:42:37.162099 e [0;1;39mUser and Session Slice[0m.
10395 04:42:37.184540 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 15.025172] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10396 04:42:37.187754 ssword …ts to Console Directory Watch[0m.
10397 04:42:37.212510 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 15.053127] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10398 04:42:37.215906 sword R…uests to Wall Directory Watch[0m.
10399 04:42:37.243673 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 15.080495] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10400 04:42:37.250050 <30>[ 15.080686] systemd[1]: Reached target Local Encrypted Volumes.
10401 04:42:37.253593 l Encrypted Volumes[0m.
10402 04:42:37.272463 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 15.116946] systemd[1]: Reached target Paths.
10403 04:42:37.272545 s[0m.
10404 04:42:37.295713 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 15.136450] systemd[1]: Reached target Remote File Systems.
10405 04:42:37.295809 te File Systems[0m.
10406 04:42:37.317169 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 15.160806] systemd[1]: Reached target Slices.
10407 04:42:37.317384 es[0m.
10408 04:42:37.336597 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 15.180514] systemd[1]: Reached target Swap.
10409 04:42:37.336962 [0m.
10410 04:42:37.360240 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 15.200934] systemd[1]: Listening on initctl Compatibility Named Pipe.
10411 04:42:37.363315 l Compatibility Named Pipe[0m.
10412 04:42:37.370242 <30>[ 15.216085] systemd[1]: Listening on Journal Audit Socket.
10413 04:42:37.376624 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10414 04:42:37.393768 [[0;32m OK [0m] Listening on<30>[ 15.237551] systemd[1]: Listening on Journal Socket (/dev/log).
10415 04:42:37.396969 [0;1;39mJournal Socket (/dev/log)[0m.
10416 04:42:37.417774 [[0;32m OK [0m] Listening on<30>[ 15.261646] systemd[1]: Listening on Journal Socket.
10417 04:42:37.421251 [0;1;39mJournal Socket[0m.
10418 04:42:37.440353 [[0;32m OK [0m] Listening on [0;1;39mNetwor<30>[ 15.281108] systemd[1]: Listening on Network Service Netlink Socket.
10419 04:42:37.444029 k Service Netlink Socket[0m.
10420 04:42:37.460859 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 15.304946] systemd[1]: Listening on udev Control Socket.
10421 04:42:37.464107 ontrol Socket[0m.
10422 04:42:37.485635 [[0;32m OK [0m] Listening on<30>[ 15.329492] systemd[1]: Listening on udev Kernel Socket.
10423 04:42:37.488890 [0;1;39mudev Kernel Socket[0m.
10424 04:42:37.536266 Mounting [0;1;39mHuge Pages File Syste<30>[ 15.376589] systemd[1]: Mounting Huge Pages File System...
10425 04:42:37.536879 m[0m...
10426 04:42:37.555000 Mounting [0;1;39mPOSIX<30>[ 15.398503] systemd[1]: Mounting POSIX Message Queue File System...
10427 04:42:37.557904 Message Queue File System[0m...
10428 04:42:37.578806 Mounting [0;1;39mKerne<30>[ 15.422596] systemd[1]: Mounting Kernel Debug File System...
10429 04:42:37.581691 l Debug File System[0m...
10430 04:42:37.604030 <30>[ 15.444702] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10431 04:42:37.613722 <30>[ 15.447976] systemd[1]: Starting Create list of static device nodes for the current kernel...
10432 04:42:37.620871 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10433 04:42:37.647726 Starting [0;1;39mLoad Kernel Module co<30>[ 15.488564] systemd[1]: Starting Load Kernel Module configfs...
10434 04:42:37.648159 nfigfs[0m...
10435 04:42:37.672351 Starting [0;1;39mLoad Kernel Module dr<30>[ 15.512544] systemd[1]: Starting Load Kernel Module drm...
10436 04:42:37.672812 m[0m...
10437 04:42:37.692380 <30>[ 15.532907] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10438 04:42:37.705293 Starting [0;1;39mJourn<30>[ 15.549489] systemd[1]: Starting Journal Service...
10439 04:42:37.705741 al Service[0m...
10440 04:42:37.730838 Starting [0;1;39mLoad <30>[ 15.574373] systemd[1]: Starting Load Kernel Modules...
10441 04:42:37.733975 Kernel Modules[0m...
10442 04:42:37.759888 Starting [0;1;39mRemount Root and Kern<30>[ 15.600621] systemd[1]: Starting Remount Root and Kernel File Systems...
10443 04:42:37.763055 el File Systems[0m...
10444 04:42:37.782080 Starting [0;1;39mColdp<30>[ 15.626235] systemd[1]: Starting Coldplug All udev Devices...
10445 04:42:37.785270 lug All udev Devices[0m...
10446 04:42:37.807943 [[0;32m OK [<30>[ 15.655201] systemd[1]: Started Journal Service.
10447 04:42:37.814761 0m] Started [0;1;39mJournal Service[0m.
10448 04:42:37.830931 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10449 04:42:37.846040 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10450 04:42:37.862150 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10451 04:42:37.881515 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10452 04:42:37.899085 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10453 04:42:37.918603 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10454 04:42:37.933756 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10455 04:42:37.955655 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10456 04:42:37.969271 See 'systemctl status systemd-remount-fs.service' for details.
10457 04:42:38.032931 Mounting [0;1;39mKernel Configuration File System[0m...
10458 04:42:38.053778 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10459 04:42:38.067808 <46>[ 15.911008] systemd-journald[195]: Received client request to flush runtime journal.
10460 04:42:38.078382 Starting [0;1;39mLoad/Save Random Seed[0m...
10461 04:42:38.098839 Starting [0;1;39mApply Kernel Variables[0m...
10462 04:42:38.118135 Starting [0;1;39mCreate System Users[0m...
10463 04:42:38.138013 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10464 04:42:38.154091 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10465 04:42:38.173600 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10466 04:42:38.186947 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10467 04:42:38.202700 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10468 04:42:38.218102 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10469 04:42:38.281983 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10470 04:42:38.302457 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10471 04:42:38.317435 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10472 04:42:38.332630 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10473 04:42:38.381788 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10474 04:42:38.407706 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10475 04:42:38.426324 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10476 04:42:38.448201 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10477 04:42:38.508617 Starting [0;1;39mNetwork Service[0m...
10478 04:42:38.525348 Starting [0;1;39mNetwork Time Synchronization[0m...
10479 04:42:38.549880 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10480 04:42:38.580824 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10481 04:42:38.599611 <4>[ 16.440309] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10482 04:42:38.612083 <4>[ 16.454274] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10483 04:42:38.652603 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m..<6>[ 16.492462] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10484 04:42:38.652724 .
10485 04:42:38.662432 <6>[ 16.492545] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10486 04:42:38.669610 <6>[ 16.492556] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10487 04:42:38.675801 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10488 04:42:38.682672 <6>[ 16.526979] usbcore: registered new device driver r8152-cfgselector
10489 04:42:38.697854 [[0;32m OK [0m] Started [0;<3>[ 16.536331] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10490 04:42:38.707207 1;39mNetwork Tim<3>[ 16.536365] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10491 04:42:38.714088 <3>[ 16.536374] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10492 04:42:38.724002 e Synchronizatio<3>[ 16.545860] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10493 04:42:38.724082 n[0m.
10494 04:42:38.734106 <3>[ 16.545887] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10495 04:42:38.740220 <3>[ 16.545898] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10496 04:42:38.750215 <3>[ 16.545913] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10497 04:42:38.756720 <3>[ 16.545926] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10498 04:42:38.766679 <3>[ 16.561616] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10499 04:42:38.773092 <3>[ 16.563849] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10500 04:42:38.783230 [[0;32m OK [0m] Finished [0<3>[ 16.563869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10501 04:42:38.793159 ;1;39mLoad/Save <3>[ 16.563876] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10502 04:42:38.802789 Screen …s of l<3>[ 16.567611] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10503 04:42:38.812652 <3>[ 16.567638] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10504 04:42:38.819457 eds:white:kbd_ba<3>[ 16.567647] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10505 04:42:38.830159 <3>[ 16.567658] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10506 04:42:38.837039 <3>[ 16.567665] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10507 04:42:38.837119 cklight[0m.
10508 04:42:38.846672 <3>[ 16.570049] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10509 04:42:38.857076 <6>[ 16.583067] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10510 04:42:38.866313 <6>[ 16.600887] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10511 04:42:38.873768 <6>[ 16.609856] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10512 04:42:38.880662 <6>[ 16.630983] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10513 04:42:38.887610 <6>[ 16.631007] pci_bus 0000:00: root bus resource [bus 00-ff]
10514 04:42:38.894498 <6>[ 16.631015] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10515 04:42:38.904447 <6>[ 16.631021] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10516 04:42:38.911049 <6>[ 16.631061] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10517 04:42:38.918648 [[0;32m OK [<6>[ 16.631082] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10518 04:42:38.924895 0m] Found device<6>[ 16.631167] pci 0000:00:00.0: supports D1 D2
10519 04:42:38.931790 <6>[ 16.631170] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10520 04:42:38.938596 <6>[ 16.631320] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10521 04:42:38.948458 <6>[ 16.634838] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10522 04:42:38.951935 <6>[ 16.645857] remoteproc remoteproc0: scp is available
10523 04:42:38.958900 [0;1;39m/dev/t<6>[ 16.645923] remoteproc remoteproc0: powering up scp
10524 04:42:38.959088 tyS0[0m.
10525 04:42:38.967808 <6>[ 16.645927] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10526 04:42:38.974505 <6>[ 16.645938] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10527 04:42:38.981137 <4>[ 16.653994] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10528 04:42:38.988264 <4>[ 16.653994] Fallback method does not support PEC.
10529 04:42:38.994468 <3>[ 16.680551] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10530 04:42:39.004525 <6>[ 16.727668] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10531 04:42:39.014578 <6>[ 16.729629] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10532 04:42:39.021273 <3>[ 16.730538] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10533 04:42:39.028275 <6>[ 16.730720] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10534 04:42:39.034996 <6>[ 16.730763] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10535 04:42:39.044439 <6>[ 16.730784] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10536 04:42:39.051025 <6>[ 16.730804] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10537 04:42:39.054544 <6>[ 16.730998] pci 0000:01:00.0: supports D1 D2
10538 04:42:39.060656 <6>[ 16.731009] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10539 04:42:39.067849 <6>[ 16.731956] mc: Linux media interface: v0.10
10540 04:42:39.074335 <3>[ 16.746840] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10541 04:42:39.082279 [[0;32m OK [<6>[ 16.749777] videodev: Linux video capture interface: v2.00
10542 04:42:39.088697 <6>[ 16.770076] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10543 04:42:39.098148 <6>[ 16.770150] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10544 04:42:39.104666 <6>[ 16.770157] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10545 04:42:39.114570 <6>[ 16.770172] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10546 04:42:39.121092 <6>[ 16.770188] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10547 04:42:39.127478 <6>[ 16.770204] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10548 04:42:39.134985 0m] Finished [0<6>[ 16.770222] pci 0000:00:00.0: PCI bridge to [bus 01]
10549 04:42:39.142108 <6>[ 16.770232] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10550 04:42:39.149720 <6>[ 16.772348] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10551 04:42:39.159270 ;1;39mUpdate UTM<6>[ 16.772631] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10552 04:42:39.169349 P about System B<6>[ 16.772639] remoteproc remoteproc0: remote processor scp is now up
10553 04:42:39.175907 oot/Shutdown[0m<6>[ 16.776471] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10554 04:42:39.175992 .
10555 04:42:39.183521 <6>[ 16.777184] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10556 04:42:39.190591 <3>[ 16.777270] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10557 04:42:39.196941 <6>[ 16.832949] Bluetooth: Core ver 2.22
10558 04:42:39.200257 <6>[ 16.833924] NET: Registered PF_BLUETOOTH protocol family
10559 04:42:39.206764 <6>[ 16.833937] Bluetooth: HCI device and connection manager initialized
10560 04:42:39.213503 <6>[ 16.833961] Bluetooth: HCI socket layer initialized
10561 04:42:39.216645 <6>[ 16.833970] Bluetooth: L2CAP socket layer initialized
10562 04:42:39.223634 <6>[ 16.834006] Bluetooth: SCO socket layer initialized
10563 04:42:39.227470 <6>[ 16.881092] r8152 2-1.3:1.0 eth0: v1.12.13
10564 04:42:39.234126 <6>[ 16.881417] usbcore: registered new interface driver r8152
10565 04:42:39.240160 <6>[ 16.891175] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10566 04:42:39.247659 <6>[ 16.893160] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10567 04:42:39.251175 <6>[ 16.895935] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10568 04:42:39.264949 <6>[ 16.899279] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10569 04:42:39.271716 <6>[ 16.899411] usbcore: registered new interface driver uvcvideo
10570 04:42:39.277751 <6>[ 16.923987] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10571 04:42:39.284917 [[0;32m OK [<6>[ 16.931470] usbcore: registered new interface driver btusb
10572 04:42:39.295337 0m] Reached targ<4>[ 16.932177] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10573 04:42:39.302501 et [0;1;39mBlue<3>[ 16.932192] Bluetooth: hci0: Failed to load firmware file (-2)
10574 04:42:39.309312 <3>[ 16.932198] Bluetooth: hci0: Failed to set up firmware (-2)
10575 04:42:39.309397 tooth[0m.
10576 04:42:39.322630 <4>[ 16.932204] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10577 04:42:39.329710 <3>[ 16.932433] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10578 04:42:39.336568 <6>[ 16.934182] usbcore: registered new interface driver cdc_ether
10579 04:42:39.343432 <6>[ 16.956955] usbcore: registered new interface driver r8153_ecm
10580 04:42:39.349475 <6>[ 16.975151] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10581 04:42:39.359416 <6>[ 16.977059] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10582 04:42:39.366060 <5>[ 16.991787] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10583 04:42:39.372984 <6>[ 16.991916] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10584 04:42:39.379349 <3>[ 16.995050] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10585 04:42:39.386326 <5>[ 17.001219] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10586 04:42:39.396618 <5>[ 17.001684] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10587 04:42:39.405729 <3>[ 17.007091] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10588 04:42:39.412554 <3>[ 17.041057] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10589 04:42:39.422114 <3>[ 17.042389] power_supply sbs-5-000b: driver failed to report `energy_full' property: -6
10590 04:42:39.429264 <3>[ 17.079146] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10591 04:42:39.438587 <4>[ 17.278366] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10592 04:42:39.445055 <6>[ 17.278436] cfg80211: failed to load regulatory.db
10593 04:42:39.451742 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10594 04:42:39.468379 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10595 04:42:39.487579 <6>[ 17.329046] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10596 04:42:39.494279 <6>[ 17.329157] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10597 04:42:39.497588 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10598 04:42:39.504430 <6>[ 17.348400] mt7921e 0000:01:00.0: ASIC revision: 79610010
10599 04:42:39.517155 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10600 04:42:39.535729 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10601 04:42:39.549151 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10602 04:42:39.568140 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10603 04:42:39.581000 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10604 04:42:39.603039 [[0;32m OK [0m] Reached target [0;1;39mBasi<6>[ 17.444344] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10605 04:42:39.606310 <6>[ 17.444344]
10606 04:42:39.606392 c System[0m.
10607 04:42:39.624263 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10608 04:42:39.652858 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10609 04:42:39.688993 Starting [0;1;39mUser Login Management[0m...
10610 04:42:39.712305 Starting [0;1;39mNetwork Name Resolution[0m...
10611 04:42:39.741332 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10612 04:42:39.763581 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10613 04:42:39.782997 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10614 04:42:39.804325 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10615 04:42:39.822633 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10616 04:42:39.840592 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10617 04:42:39.863809 <6>[ 17.704987] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10618 04:42:39.883207 Starting [0;1;39mPermit User Sessions[0m...
10619 04:42:39.900533 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10620 04:42:39.924234 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10621 04:42:39.942929 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10622 04:42:39.962742 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10623 04:42:39.977730 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10624 04:42:39.993429 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10625 04:42:40.042578 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10626 04:42:40.081777 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10627 04:42:40.121169
10628 04:42:40.121622
10629 04:42:40.124231 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10630 04:42:40.124647
10631 04:42:40.127737 debian-bullseye-arm64 login: root (automatic login)
10632 04:42:40.128154
10633 04:42:40.128483
10634 04:42:40.142843 Linux debian-bullseye-arm64 6.1.75-cip14-rt8 #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024 aarch64
10635 04:42:40.143269
10636 04:42:40.148674 The programs included with the Debian GNU/Linux system are free software;
10637 04:42:40.155809 the exact distribution terms for each program are described in the
10638 04:42:40.158375 individual files in /usr/share/doc/*/copyright.
10639 04:42:40.158456
10640 04:42:40.165206 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10641 04:42:40.168543 permitted by applicable law.
10642 04:42:40.168934 Matched prompt #10: / #
10644 04:42:40.169139 Setting prompt string to ['/ #']
10645 04:42:40.169229 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10647 04:42:40.169417 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10648 04:42:40.169502 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
10649 04:42:40.169569 Setting prompt string to ['/ #']
10650 04:42:40.169629 Forcing a shell prompt, looking for ['/ #']
10652 04:42:40.219820 / #
10653 04:42:40.220000 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10654 04:42:40.220166 Waiting using forced prompt support (timeout 00:02:30)
10655 04:42:40.225455
10656 04:42:40.225892 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10657 04:42:40.226123 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
10658 04:42:40.226360 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10659 04:42:40.226568 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
10660 04:42:40.226775 end: 2 depthcharge-action (duration 00:01:28) [common]
10661 04:42:40.226982 start: 3 lava-test-retry (timeout 00:05:00) [common]
10662 04:42:40.227185 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
10663 04:42:40.227360 Using namespace: common
10665 04:42:40.328049 / # #
10666 04:42:40.328570 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
10667 04:42:40.334178 #
10668 04:42:40.334890 Using /lava-12699794
10670 04:42:40.435996 / # export SHELL=/bin/sh
10671 04:42:40.442697 export SHELL=/bin/sh
10673 04:42:40.544142 / # . /lava-12699794/environment
10674 04:42:40.550105 . /lava-12699794/environment
10676 04:42:40.650863 / # /lava-12699794/bin/lava-test-runner /lava-12699794/0
10677 04:42:40.651102 Test shell timeout: 10s (minimum of the action and connection timeout)
10678 04:42:40.651640 <6>[ 18.436333] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c6803bd: link becomes ready
10679 04:42:40.651794 <6>[ 18.436852] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10680 04:42:40.692836 /lava-12699794/bin/lava-test-runner /lava-12699794/0
10681 04:42:40.692988 + export TESTRUN_ID=0_cros-ec
10682 04:42:40.693057 +<8>[ 18.527574] <LAVA_SIGNAL_STARTRUN 0_cros-ec 12699794_1.5.2.3.1>
10683 04:42:40.693121 cd /lava-12699794/0/tests/0_cros-ec
10684 04:42:40.693185 + cat uuid
10685 04:42:40.693246 + UUID=12699794_1.5.2.3.1
10686 04:42:40.693305 + set +x
10687 04:42:40.693552 Received signal: <STARTRUN> 0_cros-ec 12699794_1.5.2.3.1
10688 04:42:40.693621 Starting test lava.0_cros-ec (12699794_1.5.2.3.1)
10689 04:42:40.693700 Skipping test definition patterns.
10690 04:42:40.693999 + python3 -m cros.runners.lava_runner -v
10691 04:42:40.697051 <6>[ 18.543363] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10692 04:42:40.697125
10693 04:42:41.055252 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
10694 04:42:41.061621 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
10695 04:42:41.064611
10696 04:42:41.067993 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
10698 04:42:41.071224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
10699 04:42:41.077864 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
10700 04:42:41.084933 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
10701 04:42:41.085067
10702 04:42:41.091477 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8
10703 04:42:41.091600 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'test_cros_ec_accel_iio_data_is_<8', 'result': 'unknown'}
10704 04:42:41.097843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8>[ 18.941998] <LAVA_SIGNAL_ENDRUN 0_cros-ec 12699794_1.5.2.3.1>
10705 04:42:41.098126 Received signal: <ENDRUN> 0_cros-ec 12699794_1.5.2.3.1
10706 04:42:41.098237 Ending use of test pattern.
10707 04:42:41.098320 Ending test lava.0_cros-ec (12699794_1.5.2.3.1), duration 0.40
10709 04:42:41.101076 valid RESULT=skip>
10710 04:42:41.104734 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
10711 04:42:41.111479 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
10712 04:42:41.111623
10713 04:42:41.117911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
10714 04:42:41.118271 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
10716 04:42:41.124539 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10717 04:42:41.131078 Checks the standard ABI for the main Embedded Controller. ... ok
10718 04:42:41.131369
10719 04:42:41.134498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
10720 04:42:41.134989 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
10722 04:42:41.141371 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
10723 04:42:41.148082 Checks the main Embedded controller character device. ... ok
10724 04:42:41.148469
10725 04:42:41.151200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
10726 04:42:41.151828 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
10728 04:42:41.157471 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10729 04:42:41.164753 Checks basic comunication with the main Embedded controller. ... ok
10730 04:42:41.165185
10731 04:42:41.170898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
10732 04:42:41.171595 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
10734 04:42:41.174580 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10735 04:42:41.184094 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
10736 04:42:41.184497
10737 04:42:41.188107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
10738 04:42:41.188749 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
10740 04:42:41.193854 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10741 04:42:41.200379 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
10742 04:42:41.200846
10743 04:42:41.207410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
10744 04:42:41.208084 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
10746 04:42:41.213933 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
10747 04:42:41.220375 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
10748 04:42:41.220834
10749 04:42:41.227056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
10750 04:42:41.227727 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
10752 04:42:41.230616 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10753 04:42:41.240091 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
10754 04:42:41.240509
10755 04:42:41.243514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
10756 04:42:41.244182 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
10758 04:42:41.250770 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10759 04:42:41.259840 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
10760 04:42:41.260258
10761 04:42:41.263393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
10762 04:42:41.264079 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
10764 04:42:41.269813 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10765 04:42:41.276277 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
10766 04:42:41.276696
10767 04:42:41.283232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
10768 04:42:41.283905 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
10770 04:42:41.289551 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10771 04:42:41.296579 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
10772 04:42:41.297174
10773 04:42:41.302987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
10774 04:42:41.303770 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
10776 04:42:41.309303 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
10777 04:42:41.316112 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
10778 04:42:41.316566
10779 04:42:41.322832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
10780 04:42:41.323531 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
10782 04:42:41.329349 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
10783 04:42:41.335817 Check the cros battery ABI. ... skipped 'No BAT found'
10784 04:42:41.336278
10785 04:42:41.342334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
10786 04:42:41.343077 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
10788 04:42:41.349188 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
10789 04:42:41.355931 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
10790 04:42:41.356355
10791 04:42:41.362445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
10792 04:42:41.363171 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
10794 04:42:41.365976 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
10795 04:42:41.372135 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
10796 04:42:41.372592
10797 04:42:41.378602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
10798 04:42:41.379276 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
10800 04:42:41.385365 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
10801 04:42:41.392401 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
10802 04:42:41.392851
10803 04:42:41.398690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
10804 04:42:41.399154
10805 04:42:41.399773 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
10807 04:42:41.404998 ----------------------------------------------------------------------
10808 04:42:41.408248 Ran 18 tests in 0.006s
10809 04:42:41.408703
10810 04:42:41.409123 OK (skipped=15)
10811 04:42:41.411688 + set +x
10812 04:42:41.412147 <LAVA_TEST_RUNNER EXIT>
10813 04:42:41.412807 ok: lava_test_shell seems to have completed
10814 04:42:41.413687 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
10815 04:42:41.414174 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10816 04:42:41.414672 end: 3 lava-test-retry (duration 00:00:01) [common]
10817 04:42:41.415157 start: 4 finalize (timeout 00:08:09) [common]
10818 04:42:41.415629 start: 4.1 power-off (timeout 00:00:30) [common]
10819 04:42:41.416426 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10820 04:42:41.497392 >> Command sent successfully.
10821 04:42:41.499722 Returned 0 in 0 seconds
10822 04:42:41.600181 end: 4.1 power-off (duration 00:00:00) [common]
10824 04:42:41.600513 start: 4.2 read-feedback (timeout 00:08:08) [common]
10825 04:42:41.600835 Listened to connection for namespace 'common' for up to 1s
10826 04:42:42.601945 Finalising connection for namespace 'common'
10827 04:42:42.602634 Disconnecting from shell: Finalise
10828 04:42:42.603046 / #
10829 04:42:42.704062 end: 4.2 read-feedback (duration 00:00:01) [common]
10830 04:42:42.704793 end: 4 finalize (duration 00:00:01) [common]
10831 04:42:42.705420 Cleaning after the job
10832 04:42:42.705957 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699794/tftp-deploy-cfipo1j7/ramdisk
10833 04:42:42.733782 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699794/tftp-deploy-cfipo1j7/kernel
10834 04:42:42.750133 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699794/tftp-deploy-cfipo1j7/dtb
10835 04:42:42.750380 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699794/tftp-deploy-cfipo1j7/modules
10836 04:42:42.759842 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12699794
10837 04:42:42.881836 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12699794
10838 04:42:42.882015 Job finished correctly